2006.211.07:24:50.04:Log Opened: Mark IV Field System Version 9.7.7 2006.211.07:24:50.05:location,TSUKUB32,-140.09,36.10,61.0 2006.211.07:24:50.05:horizon1,0.,5.,360. 2006.211.07:24:50.05:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.211.07:24:50.06:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.211.07:24:50.06:drivev11,330,270,no 2006.211.07:24:50.06:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.211.07:24:50.07:drivev13,15.000,268,10.000,10.000,10.000 2006.211.07:24:50.07:drivev21,330,270,no 2006.211.07:24:50.07:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.211.07:24:50.08:drivev23,15.000,268,10.000,10.000,10.000 2006.211.07:24:50.08:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.211.07:24:50.08:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.211.07:24:50.09:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.211.07:24:50.09:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.211.07:24:50.09:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.211.07:24:50.10:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.211.07:24:50.10:time,-0.364,101.533,rate 2006.211.07:24:50.10:flagr,200 2006.211.07:24:50.11:proc=k06211ts 2006.211.07:24:50.11:" k06211 2006 tsukub32 t ts 2006.211.07:24:50.12:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.211.07:24:50.12:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.211.07:24:50.12:" 108 tsukub32 14 17400 2006.211.07:24:50.13:" drudg version 050216 compiled under fs 9.7.07 2006.211.07:24:50.13:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.211.07:24:50.13:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.211.07:24:50.16:source=azel,0d,88d 2006.211.07:24:50.16#antcn#PM 1 00019 2005 228 00 22 31 00 2006.211.07:24:50.16#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.211.07:24:50.16#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.211.07:24:50.16#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.211.07:24:50.16#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.211.07:24:50.16#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.211.07:24:51.14#flagr#flagr/antenna,new-source 2006.211.07:24:51.14:!+2m 2006.211.07:26:03.14#trakl#Source acquired 2006.211.07:26:05.15#flagr#flagr/antenna,acquired 2006.211.07:26:51.15:scan_name=211-0730,k06211,60 2006.211.07:26:51.15:source=3c418,203837.03,511912.7,2000.0,ccw 2006.211.07:26:52.15#flagr#flagr/antenna,new-source 2006.211.07:26:52.15:ready_k5 2006.211.07:26:52.15&ready_k5/obsinfo=st 2006.211.07:26:52.16&ready_k5/autoobs=1 2006.211.07:26:52.16&ready_k5/autoobs=2 2006.211.07:26:52.16&ready_k5/autoobs=3 2006.211.07:26:52.17&ready_k5/autoobs=4 2006.211.07:26:52.17&ready_k5/obsinfo 2006.211.07:26:52.17/obsinfo=st/error_log.tmp was not found (or not removed). 2006.211.07:26:55.31/autoobs//k5ts1/ autoobs started! 2006.211.07:26:58.38/autoobs//k5ts2/ autoobs started! 2006.211.07:27:01.48/autoobs//k5ts3/ autoobs started! 2006.211.07:27:04.58/autoobs//k5ts4/ autoobs started! 2006.211.07:27:04.61/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:27:04.61:4f8m12a=1 2006.211.07:27:04.61&4f8m12a/xlog=on 2006.211.07:27:04.61&4f8m12a/echo=on 2006.211.07:27:04.61&4f8m12a/pcalon 2006.211.07:27:04.61&4f8m12a/"tpicd=stop 2006.211.07:27:04.61&4f8m12a/vc4f8 2006.211.07:27:04.61&4f8m12a/ifd4f 2006.211.07:27:04.61&4f8m12a/"form=m,16.000,1:2 2006.211.07:27:04.61&4f8m12a/"tpicd 2006.211.07:27:04.61&4f8m12a/echo=off 2006.211.07:27:04.61&4f8m12a/xlog=off 2006.211.07:27:04.61$4f8m12a/echo=on 2006.211.07:27:04.61$4f8m12a/pcalon 2006.211.07:27:04.61&pcalon/"no phase cal control is implemented here 2006.211.07:27:04.61$pcalon/"no phase cal control is implemented here 2006.211.07:27:04.61$4f8m12a/"tpicd=stop 2006.211.07:27:04.61$4f8m12a/vc4f8 2006.211.07:27:04.61&vc4f8/valo=1,532.99 2006.211.07:27:04.61&vc4f8/va=1,8 2006.211.07:27:04.61&vc4f8/valo=2,572.99 2006.211.07:27:04.61&vc4f8/va=2,7 2006.211.07:27:04.61&vc4f8/valo=3,672.99 2006.211.07:27:04.61&vc4f8/va=3,6 2006.211.07:27:04.61&vc4f8/valo=4,832.99 2006.211.07:27:04.61&vc4f8/va=4,7 2006.211.07:27:04.61&vc4f8/valo=5,652.99 2006.211.07:27:04.61&vc4f8/va=5,7 2006.211.07:27:04.61&vc4f8/valo=6,772.99 2006.211.07:27:04.61&vc4f8/va=6,6 2006.211.07:27:04.61&vc4f8/valo=7,832.99 2006.211.07:27:04.61&vc4f8/va=7,6 2006.211.07:27:04.61&vc4f8/valo=8,852.99 2006.211.07:27:04.61&vc4f8/va=8,7 2006.211.07:27:04.61&vc4f8/vblo=1,632.99 2006.211.07:27:04.61&vc4f8/vb=1,4 2006.211.07:27:04.61&vc4f8/vblo=2,640.99 2006.211.07:27:04.61&vc4f8/vb=2,4 2006.211.07:27:04.61&vc4f8/vblo=3,656.99 2006.211.07:27:04.61&vc4f8/vb=3,3 2006.211.07:27:04.61&vc4f8/vblo=4,712.99 2006.211.07:27:04.61&vc4f8/vb=4,3 2006.211.07:27:04.61&vc4f8/vblo=5,744.99 2006.211.07:27:04.61&vc4f8/vb=5,3 2006.211.07:27:04.61&vc4f8/vblo=6,752.99 2006.211.07:27:04.61&vc4f8/vb=6,3 2006.211.07:27:04.61&vc4f8/vabw=wide 2006.211.07:27:04.61&vc4f8/vbbw=wide 2006.211.07:27:04.61$vc4f8/valo=1,532.99 2006.211.07:27:04.61#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:27:04.61#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:27:04.61#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:04.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:04.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:04.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:04.61#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:27:04.61#ibcon#first serial, iclass 18, count 0 2006.211.07:27:04.61#ibcon#enter sib2, iclass 18, count 0 2006.211.07:27:04.61#ibcon#flushed, iclass 18, count 0 2006.211.07:27:04.61#ibcon#about to write, iclass 18, count 0 2006.211.07:27:04.61#ibcon#wrote, iclass 18, count 0 2006.211.07:27:04.61#ibcon#about to read 3, iclass 18, count 0 2006.211.07:27:04.64#ibcon#read 3, iclass 18, count 0 2006.211.07:27:04.64#ibcon#about to read 4, iclass 18, count 0 2006.211.07:27:04.64#ibcon#read 4, iclass 18, count 0 2006.211.07:27:04.64#ibcon#about to read 5, iclass 18, count 0 2006.211.07:27:04.64#ibcon#read 5, iclass 18, count 0 2006.211.07:27:04.64#ibcon#about to read 6, iclass 18, count 0 2006.211.07:27:04.64#ibcon#read 6, iclass 18, count 0 2006.211.07:27:04.64#ibcon#end of sib2, iclass 18, count 0 2006.211.07:27:04.64#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:27:04.64#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:27:04.64#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:27:04.64#ibcon#*before write, iclass 18, count 0 2006.211.07:27:04.64#ibcon#enter sib2, iclass 18, count 0 2006.211.07:27:04.64#ibcon#flushed, iclass 18, count 0 2006.211.07:27:04.64#ibcon#about to write, iclass 18, count 0 2006.211.07:27:04.64#ibcon#wrote, iclass 18, count 0 2006.211.07:27:04.64#ibcon#about to read 3, iclass 18, count 0 2006.211.07:27:04.68#ibcon#read 3, iclass 18, count 0 2006.211.07:27:04.68#ibcon#about to read 4, iclass 18, count 0 2006.211.07:27:04.68#ibcon#read 4, iclass 18, count 0 2006.211.07:27:04.68#ibcon#about to read 5, iclass 18, count 0 2006.211.07:27:04.68#ibcon#read 5, iclass 18, count 0 2006.211.07:27:04.68#ibcon#about to read 6, iclass 18, count 0 2006.211.07:27:04.68#ibcon#read 6, iclass 18, count 0 2006.211.07:27:04.68#ibcon#end of sib2, iclass 18, count 0 2006.211.07:27:04.68#ibcon#*after write, iclass 18, count 0 2006.211.07:27:04.68#ibcon#*before return 0, iclass 18, count 0 2006.211.07:27:04.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:04.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:04.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:27:04.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:27:04.69$vc4f8/va=1,8 2006.211.07:27:04.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:27:04.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:27:04.69#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:04.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:04.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:04.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:04.69#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:27:04.69#ibcon#first serial, iclass 20, count 2 2006.211.07:27:04.69#ibcon#enter sib2, iclass 20, count 2 2006.211.07:27:04.69#ibcon#flushed, iclass 20, count 2 2006.211.07:27:04.69#ibcon#about to write, iclass 20, count 2 2006.211.07:27:04.69#ibcon#wrote, iclass 20, count 2 2006.211.07:27:04.69#ibcon#about to read 3, iclass 20, count 2 2006.211.07:27:04.70#ibcon#read 3, iclass 20, count 2 2006.211.07:27:04.70#ibcon#about to read 4, iclass 20, count 2 2006.211.07:27:04.70#ibcon#read 4, iclass 20, count 2 2006.211.07:27:04.70#ibcon#about to read 5, iclass 20, count 2 2006.211.07:27:04.70#ibcon#read 5, iclass 20, count 2 2006.211.07:27:04.70#ibcon#about to read 6, iclass 20, count 2 2006.211.07:27:04.70#ibcon#read 6, iclass 20, count 2 2006.211.07:27:04.70#ibcon#end of sib2, iclass 20, count 2 2006.211.07:27:04.70#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:27:04.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:27:04.70#ibcon#[25=AT01-08\r\n] 2006.211.07:27:04.70#ibcon#*before write, iclass 20, count 2 2006.211.07:27:04.70#ibcon#enter sib2, iclass 20, count 2 2006.211.07:27:04.70#ibcon#flushed, iclass 20, count 2 2006.211.07:27:04.70#ibcon#about to write, iclass 20, count 2 2006.211.07:27:04.70#ibcon#wrote, iclass 20, count 2 2006.211.07:27:04.70#ibcon#about to read 3, iclass 20, count 2 2006.211.07:27:04.73#ibcon#read 3, iclass 20, count 2 2006.211.07:27:04.73#ibcon#about to read 4, iclass 20, count 2 2006.211.07:27:04.73#ibcon#read 4, iclass 20, count 2 2006.211.07:27:04.73#ibcon#about to read 5, iclass 20, count 2 2006.211.07:27:04.73#ibcon#read 5, iclass 20, count 2 2006.211.07:27:04.73#ibcon#about to read 6, iclass 20, count 2 2006.211.07:27:04.73#ibcon#read 6, iclass 20, count 2 2006.211.07:27:04.73#ibcon#end of sib2, iclass 20, count 2 2006.211.07:27:04.73#ibcon#*after write, iclass 20, count 2 2006.211.07:27:04.73#ibcon#*before return 0, iclass 20, count 2 2006.211.07:27:04.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:04.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:04.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:27:04.73#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:04.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:04.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:04.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:04.85#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:27:04.85#ibcon#first serial, iclass 20, count 0 2006.211.07:27:04.85#ibcon#enter sib2, iclass 20, count 0 2006.211.07:27:04.85#ibcon#flushed, iclass 20, count 0 2006.211.07:27:04.85#ibcon#about to write, iclass 20, count 0 2006.211.07:27:04.85#ibcon#wrote, iclass 20, count 0 2006.211.07:27:04.85#ibcon#about to read 3, iclass 20, count 0 2006.211.07:27:04.87#ibcon#read 3, iclass 20, count 0 2006.211.07:27:04.87#ibcon#about to read 4, iclass 20, count 0 2006.211.07:27:04.87#ibcon#read 4, iclass 20, count 0 2006.211.07:27:04.87#ibcon#about to read 5, iclass 20, count 0 2006.211.07:27:04.87#ibcon#read 5, iclass 20, count 0 2006.211.07:27:04.87#ibcon#about to read 6, iclass 20, count 0 2006.211.07:27:04.87#ibcon#read 6, iclass 20, count 0 2006.211.07:27:04.87#ibcon#end of sib2, iclass 20, count 0 2006.211.07:27:04.87#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:27:04.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:27:04.87#ibcon#[25=USB\r\n] 2006.211.07:27:04.87#ibcon#*before write, iclass 20, count 0 2006.211.07:27:04.87#ibcon#enter sib2, iclass 20, count 0 2006.211.07:27:04.87#ibcon#flushed, iclass 20, count 0 2006.211.07:27:04.87#ibcon#about to write, iclass 20, count 0 2006.211.07:27:04.87#ibcon#wrote, iclass 20, count 0 2006.211.07:27:04.87#ibcon#about to read 3, iclass 20, count 0 2006.211.07:27:04.90#ibcon#read 3, iclass 20, count 0 2006.211.07:27:04.90#ibcon#about to read 4, iclass 20, count 0 2006.211.07:27:04.90#ibcon#read 4, iclass 20, count 0 2006.211.07:27:04.90#ibcon#about to read 5, iclass 20, count 0 2006.211.07:27:04.90#ibcon#read 5, iclass 20, count 0 2006.211.07:27:04.90#ibcon#about to read 6, iclass 20, count 0 2006.211.07:27:04.90#ibcon#read 6, iclass 20, count 0 2006.211.07:27:04.90#ibcon#end of sib2, iclass 20, count 0 2006.211.07:27:04.90#ibcon#*after write, iclass 20, count 0 2006.211.07:27:04.90#ibcon#*before return 0, iclass 20, count 0 2006.211.07:27:04.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:04.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:04.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:27:04.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:27:04.91$vc4f8/valo=2,572.99 2006.211.07:27:04.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:27:04.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:27:04.91#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:04.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:04.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:04.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:04.91#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:27:04.91#ibcon#first serial, iclass 22, count 0 2006.211.07:27:04.91#ibcon#enter sib2, iclass 22, count 0 2006.211.07:27:04.91#ibcon#flushed, iclass 22, count 0 2006.211.07:27:04.91#ibcon#about to write, iclass 22, count 0 2006.211.07:27:04.91#ibcon#wrote, iclass 22, count 0 2006.211.07:27:04.91#ibcon#about to read 3, iclass 22, count 0 2006.211.07:27:04.92#ibcon#read 3, iclass 22, count 0 2006.211.07:27:04.92#ibcon#about to read 4, iclass 22, count 0 2006.211.07:27:04.92#ibcon#read 4, iclass 22, count 0 2006.211.07:27:04.92#ibcon#about to read 5, iclass 22, count 0 2006.211.07:27:04.92#ibcon#read 5, iclass 22, count 0 2006.211.07:27:04.92#ibcon#about to read 6, iclass 22, count 0 2006.211.07:27:04.92#ibcon#read 6, iclass 22, count 0 2006.211.07:27:04.92#ibcon#end of sib2, iclass 22, count 0 2006.211.07:27:04.92#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:27:04.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:27:04.92#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:27:04.92#ibcon#*before write, iclass 22, count 0 2006.211.07:27:04.92#ibcon#enter sib2, iclass 22, count 0 2006.211.07:27:04.92#ibcon#flushed, iclass 22, count 0 2006.211.07:27:04.92#ibcon#about to write, iclass 22, count 0 2006.211.07:27:04.92#ibcon#wrote, iclass 22, count 0 2006.211.07:27:04.92#ibcon#about to read 3, iclass 22, count 0 2006.211.07:27:04.96#ibcon#read 3, iclass 22, count 0 2006.211.07:27:04.96#ibcon#about to read 4, iclass 22, count 0 2006.211.07:27:04.96#ibcon#read 4, iclass 22, count 0 2006.211.07:27:04.96#ibcon#about to read 5, iclass 22, count 0 2006.211.07:27:04.96#ibcon#read 5, iclass 22, count 0 2006.211.07:27:04.96#ibcon#about to read 6, iclass 22, count 0 2006.211.07:27:04.96#ibcon#read 6, iclass 22, count 0 2006.211.07:27:04.96#ibcon#end of sib2, iclass 22, count 0 2006.211.07:27:04.96#ibcon#*after write, iclass 22, count 0 2006.211.07:27:04.96#ibcon#*before return 0, iclass 22, count 0 2006.211.07:27:04.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:04.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:04.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:27:04.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:27:04.97$vc4f8/va=2,7 2006.211.07:27:04.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:27:04.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:27:04.97#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:04.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:05.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:05.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:05.02#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:27:05.02#ibcon#first serial, iclass 24, count 2 2006.211.07:27:05.02#ibcon#enter sib2, iclass 24, count 2 2006.211.07:27:05.02#ibcon#flushed, iclass 24, count 2 2006.211.07:27:05.02#ibcon#about to write, iclass 24, count 2 2006.211.07:27:05.02#ibcon#wrote, iclass 24, count 2 2006.211.07:27:05.02#ibcon#about to read 3, iclass 24, count 2 2006.211.07:27:05.03#ibcon#read 3, iclass 24, count 2 2006.211.07:27:05.03#ibcon#about to read 4, iclass 24, count 2 2006.211.07:27:05.03#ibcon#read 4, iclass 24, count 2 2006.211.07:27:05.03#ibcon#about to read 5, iclass 24, count 2 2006.211.07:27:05.03#ibcon#read 5, iclass 24, count 2 2006.211.07:27:05.03#ibcon#about to read 6, iclass 24, count 2 2006.211.07:27:05.03#ibcon#read 6, iclass 24, count 2 2006.211.07:27:05.03#ibcon#end of sib2, iclass 24, count 2 2006.211.07:27:05.03#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:27:05.03#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:27:05.03#ibcon#[25=AT02-07\r\n] 2006.211.07:27:05.03#ibcon#*before write, iclass 24, count 2 2006.211.07:27:05.03#ibcon#enter sib2, iclass 24, count 2 2006.211.07:27:05.03#ibcon#flushed, iclass 24, count 2 2006.211.07:27:05.03#ibcon#about to write, iclass 24, count 2 2006.211.07:27:05.03#ibcon#wrote, iclass 24, count 2 2006.211.07:27:05.03#ibcon#about to read 3, iclass 24, count 2 2006.211.07:27:05.06#ibcon#read 3, iclass 24, count 2 2006.211.07:27:05.06#ibcon#about to read 4, iclass 24, count 2 2006.211.07:27:05.06#ibcon#read 4, iclass 24, count 2 2006.211.07:27:05.06#ibcon#about to read 5, iclass 24, count 2 2006.211.07:27:05.06#ibcon#read 5, iclass 24, count 2 2006.211.07:27:05.06#ibcon#about to read 6, iclass 24, count 2 2006.211.07:27:05.06#ibcon#read 6, iclass 24, count 2 2006.211.07:27:05.06#ibcon#end of sib2, iclass 24, count 2 2006.211.07:27:05.06#ibcon#*after write, iclass 24, count 2 2006.211.07:27:05.06#ibcon#*before return 0, iclass 24, count 2 2006.211.07:27:05.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:05.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:05.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:27:05.06#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:05.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:05.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:05.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:05.18#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:27:05.18#ibcon#first serial, iclass 24, count 0 2006.211.07:27:05.18#ibcon#enter sib2, iclass 24, count 0 2006.211.07:27:05.18#ibcon#flushed, iclass 24, count 0 2006.211.07:27:05.18#ibcon#about to write, iclass 24, count 0 2006.211.07:27:05.18#ibcon#wrote, iclass 24, count 0 2006.211.07:27:05.18#ibcon#about to read 3, iclass 24, count 0 2006.211.07:27:05.20#ibcon#read 3, iclass 24, count 0 2006.211.07:27:05.20#ibcon#about to read 4, iclass 24, count 0 2006.211.07:27:05.20#ibcon#read 4, iclass 24, count 0 2006.211.07:27:05.20#ibcon#about to read 5, iclass 24, count 0 2006.211.07:27:05.20#ibcon#read 5, iclass 24, count 0 2006.211.07:27:05.20#ibcon#about to read 6, iclass 24, count 0 2006.211.07:27:05.20#ibcon#read 6, iclass 24, count 0 2006.211.07:27:05.20#ibcon#end of sib2, iclass 24, count 0 2006.211.07:27:05.20#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:27:05.20#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:27:05.20#ibcon#[25=USB\r\n] 2006.211.07:27:05.20#ibcon#*before write, iclass 24, count 0 2006.211.07:27:05.20#ibcon#enter sib2, iclass 24, count 0 2006.211.07:27:05.20#ibcon#flushed, iclass 24, count 0 2006.211.07:27:05.20#ibcon#about to write, iclass 24, count 0 2006.211.07:27:05.20#ibcon#wrote, iclass 24, count 0 2006.211.07:27:05.20#ibcon#about to read 3, iclass 24, count 0 2006.211.07:27:05.23#ibcon#read 3, iclass 24, count 0 2006.211.07:27:05.23#ibcon#about to read 4, iclass 24, count 0 2006.211.07:27:05.23#ibcon#read 4, iclass 24, count 0 2006.211.07:27:05.23#ibcon#about to read 5, iclass 24, count 0 2006.211.07:27:05.23#ibcon#read 5, iclass 24, count 0 2006.211.07:27:05.23#ibcon#about to read 6, iclass 24, count 0 2006.211.07:27:05.23#ibcon#read 6, iclass 24, count 0 2006.211.07:27:05.23#ibcon#end of sib2, iclass 24, count 0 2006.211.07:27:05.23#ibcon#*after write, iclass 24, count 0 2006.211.07:27:05.23#ibcon#*before return 0, iclass 24, count 0 2006.211.07:27:05.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:05.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:05.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:27:05.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:27:05.24$vc4f8/valo=3,672.99 2006.211.07:27:05.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:27:05.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:27:05.24#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:05.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:05.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:05.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:05.24#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:27:05.24#ibcon#first serial, iclass 26, count 0 2006.211.07:27:05.24#ibcon#enter sib2, iclass 26, count 0 2006.211.07:27:05.24#ibcon#flushed, iclass 26, count 0 2006.211.07:27:05.24#ibcon#about to write, iclass 26, count 0 2006.211.07:27:05.24#ibcon#wrote, iclass 26, count 0 2006.211.07:27:05.24#ibcon#about to read 3, iclass 26, count 0 2006.211.07:27:05.25#ibcon#read 3, iclass 26, count 0 2006.211.07:27:05.25#ibcon#about to read 4, iclass 26, count 0 2006.211.07:27:05.25#ibcon#read 4, iclass 26, count 0 2006.211.07:27:05.25#ibcon#about to read 5, iclass 26, count 0 2006.211.07:27:05.25#ibcon#read 5, iclass 26, count 0 2006.211.07:27:05.25#ibcon#about to read 6, iclass 26, count 0 2006.211.07:27:05.25#ibcon#read 6, iclass 26, count 0 2006.211.07:27:05.25#ibcon#end of sib2, iclass 26, count 0 2006.211.07:27:05.25#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:27:05.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:27:05.25#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:27:05.25#ibcon#*before write, iclass 26, count 0 2006.211.07:27:05.25#ibcon#enter sib2, iclass 26, count 0 2006.211.07:27:05.25#ibcon#flushed, iclass 26, count 0 2006.211.07:27:05.25#ibcon#about to write, iclass 26, count 0 2006.211.07:27:05.25#ibcon#wrote, iclass 26, count 0 2006.211.07:27:05.25#ibcon#about to read 3, iclass 26, count 0 2006.211.07:27:05.29#ibcon#read 3, iclass 26, count 0 2006.211.07:27:05.29#ibcon#about to read 4, iclass 26, count 0 2006.211.07:27:05.29#ibcon#read 4, iclass 26, count 0 2006.211.07:27:05.29#ibcon#about to read 5, iclass 26, count 0 2006.211.07:27:05.29#ibcon#read 5, iclass 26, count 0 2006.211.07:27:05.29#ibcon#about to read 6, iclass 26, count 0 2006.211.07:27:05.29#ibcon#read 6, iclass 26, count 0 2006.211.07:27:05.29#ibcon#end of sib2, iclass 26, count 0 2006.211.07:27:05.29#ibcon#*after write, iclass 26, count 0 2006.211.07:27:05.29#ibcon#*before return 0, iclass 26, count 0 2006.211.07:27:05.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:05.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:05.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:27:05.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:27:05.30$vc4f8/va=3,6 2006.211.07:27:05.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.07:27:05.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.07:27:05.30#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:05.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:05.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:05.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:05.34#ibcon#enter wrdev, iclass 28, count 2 2006.211.07:27:05.34#ibcon#first serial, iclass 28, count 2 2006.211.07:27:05.34#ibcon#enter sib2, iclass 28, count 2 2006.211.07:27:05.34#ibcon#flushed, iclass 28, count 2 2006.211.07:27:05.34#ibcon#about to write, iclass 28, count 2 2006.211.07:27:05.34#ibcon#wrote, iclass 28, count 2 2006.211.07:27:05.34#ibcon#about to read 3, iclass 28, count 2 2006.211.07:27:05.36#ibcon#read 3, iclass 28, count 2 2006.211.07:27:05.36#ibcon#about to read 4, iclass 28, count 2 2006.211.07:27:05.36#ibcon#read 4, iclass 28, count 2 2006.211.07:27:05.36#ibcon#about to read 5, iclass 28, count 2 2006.211.07:27:05.36#ibcon#read 5, iclass 28, count 2 2006.211.07:27:05.36#ibcon#about to read 6, iclass 28, count 2 2006.211.07:27:05.36#ibcon#read 6, iclass 28, count 2 2006.211.07:27:05.36#ibcon#end of sib2, iclass 28, count 2 2006.211.07:27:05.36#ibcon#*mode == 0, iclass 28, count 2 2006.211.07:27:05.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.07:27:05.36#ibcon#[25=AT03-06\r\n] 2006.211.07:27:05.36#ibcon#*before write, iclass 28, count 2 2006.211.07:27:05.36#ibcon#enter sib2, iclass 28, count 2 2006.211.07:27:05.36#ibcon#flushed, iclass 28, count 2 2006.211.07:27:05.36#ibcon#about to write, iclass 28, count 2 2006.211.07:27:05.36#ibcon#wrote, iclass 28, count 2 2006.211.07:27:05.36#ibcon#about to read 3, iclass 28, count 2 2006.211.07:27:05.39#ibcon#read 3, iclass 28, count 2 2006.211.07:27:05.39#ibcon#about to read 4, iclass 28, count 2 2006.211.07:27:05.39#ibcon#read 4, iclass 28, count 2 2006.211.07:27:05.39#ibcon#about to read 5, iclass 28, count 2 2006.211.07:27:05.39#ibcon#read 5, iclass 28, count 2 2006.211.07:27:05.39#ibcon#about to read 6, iclass 28, count 2 2006.211.07:27:05.39#ibcon#read 6, iclass 28, count 2 2006.211.07:27:05.39#ibcon#end of sib2, iclass 28, count 2 2006.211.07:27:05.39#ibcon#*after write, iclass 28, count 2 2006.211.07:27:05.39#ibcon#*before return 0, iclass 28, count 2 2006.211.07:27:05.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:05.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:05.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.07:27:05.39#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:05.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:05.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:05.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:05.51#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:27:05.51#ibcon#first serial, iclass 28, count 0 2006.211.07:27:05.51#ibcon#enter sib2, iclass 28, count 0 2006.211.07:27:05.51#ibcon#flushed, iclass 28, count 0 2006.211.07:27:05.51#ibcon#about to write, iclass 28, count 0 2006.211.07:27:05.51#ibcon#wrote, iclass 28, count 0 2006.211.07:27:05.51#ibcon#about to read 3, iclass 28, count 0 2006.211.07:27:05.53#ibcon#read 3, iclass 28, count 0 2006.211.07:27:05.53#ibcon#about to read 4, iclass 28, count 0 2006.211.07:27:05.53#ibcon#read 4, iclass 28, count 0 2006.211.07:27:05.53#ibcon#about to read 5, iclass 28, count 0 2006.211.07:27:05.53#ibcon#read 5, iclass 28, count 0 2006.211.07:27:05.53#ibcon#about to read 6, iclass 28, count 0 2006.211.07:27:05.53#ibcon#read 6, iclass 28, count 0 2006.211.07:27:05.53#ibcon#end of sib2, iclass 28, count 0 2006.211.07:27:05.53#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:27:05.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:27:05.53#ibcon#[25=USB\r\n] 2006.211.07:27:05.53#ibcon#*before write, iclass 28, count 0 2006.211.07:27:05.53#ibcon#enter sib2, iclass 28, count 0 2006.211.07:27:05.53#ibcon#flushed, iclass 28, count 0 2006.211.07:27:05.53#ibcon#about to write, iclass 28, count 0 2006.211.07:27:05.53#ibcon#wrote, iclass 28, count 0 2006.211.07:27:05.53#ibcon#about to read 3, iclass 28, count 0 2006.211.07:27:05.56#ibcon#read 3, iclass 28, count 0 2006.211.07:27:05.56#ibcon#about to read 4, iclass 28, count 0 2006.211.07:27:05.56#ibcon#read 4, iclass 28, count 0 2006.211.07:27:05.56#ibcon#about to read 5, iclass 28, count 0 2006.211.07:27:05.56#ibcon#read 5, iclass 28, count 0 2006.211.07:27:05.56#ibcon#about to read 6, iclass 28, count 0 2006.211.07:27:05.56#ibcon#read 6, iclass 28, count 0 2006.211.07:27:05.56#ibcon#end of sib2, iclass 28, count 0 2006.211.07:27:05.56#ibcon#*after write, iclass 28, count 0 2006.211.07:27:05.56#ibcon#*before return 0, iclass 28, count 0 2006.211.07:27:05.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:05.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:05.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:27:05.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:27:05.57$vc4f8/valo=4,832.99 2006.211.07:27:05.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.07:27:05.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.07:27:05.57#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:05.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:05.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:05.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:05.57#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:27:05.57#ibcon#first serial, iclass 30, count 0 2006.211.07:27:05.57#ibcon#enter sib2, iclass 30, count 0 2006.211.07:27:05.57#ibcon#flushed, iclass 30, count 0 2006.211.07:27:05.57#ibcon#about to write, iclass 30, count 0 2006.211.07:27:05.57#ibcon#wrote, iclass 30, count 0 2006.211.07:27:05.57#ibcon#about to read 3, iclass 30, count 0 2006.211.07:27:05.58#ibcon#read 3, iclass 30, count 0 2006.211.07:27:05.58#ibcon#about to read 4, iclass 30, count 0 2006.211.07:27:05.58#ibcon#read 4, iclass 30, count 0 2006.211.07:27:05.58#ibcon#about to read 5, iclass 30, count 0 2006.211.07:27:05.58#ibcon#read 5, iclass 30, count 0 2006.211.07:27:05.58#ibcon#about to read 6, iclass 30, count 0 2006.211.07:27:05.58#ibcon#read 6, iclass 30, count 0 2006.211.07:27:05.58#ibcon#end of sib2, iclass 30, count 0 2006.211.07:27:05.58#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:27:05.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:27:05.58#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:27:05.58#ibcon#*before write, iclass 30, count 0 2006.211.07:27:05.58#ibcon#enter sib2, iclass 30, count 0 2006.211.07:27:05.58#ibcon#flushed, iclass 30, count 0 2006.211.07:27:05.58#ibcon#about to write, iclass 30, count 0 2006.211.07:27:05.58#ibcon#wrote, iclass 30, count 0 2006.211.07:27:05.58#ibcon#about to read 3, iclass 30, count 0 2006.211.07:27:05.62#ibcon#read 3, iclass 30, count 0 2006.211.07:27:05.62#ibcon#about to read 4, iclass 30, count 0 2006.211.07:27:05.62#ibcon#read 4, iclass 30, count 0 2006.211.07:27:05.62#ibcon#about to read 5, iclass 30, count 0 2006.211.07:27:05.62#ibcon#read 5, iclass 30, count 0 2006.211.07:27:05.62#ibcon#about to read 6, iclass 30, count 0 2006.211.07:27:05.62#ibcon#read 6, iclass 30, count 0 2006.211.07:27:05.62#ibcon#end of sib2, iclass 30, count 0 2006.211.07:27:05.62#ibcon#*after write, iclass 30, count 0 2006.211.07:27:05.62#ibcon#*before return 0, iclass 30, count 0 2006.211.07:27:05.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:05.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:05.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:27:05.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:27:05.63$vc4f8/va=4,7 2006.211.07:27:05.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.07:27:05.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.07:27:05.63#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:05.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:05.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:05.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:05.67#ibcon#enter wrdev, iclass 32, count 2 2006.211.07:27:05.67#ibcon#first serial, iclass 32, count 2 2006.211.07:27:05.67#ibcon#enter sib2, iclass 32, count 2 2006.211.07:27:05.67#ibcon#flushed, iclass 32, count 2 2006.211.07:27:05.67#ibcon#about to write, iclass 32, count 2 2006.211.07:27:05.67#ibcon#wrote, iclass 32, count 2 2006.211.07:27:05.67#ibcon#about to read 3, iclass 32, count 2 2006.211.07:27:05.69#ibcon#read 3, iclass 32, count 2 2006.211.07:27:05.69#ibcon#about to read 4, iclass 32, count 2 2006.211.07:27:05.69#ibcon#read 4, iclass 32, count 2 2006.211.07:27:05.69#ibcon#about to read 5, iclass 32, count 2 2006.211.07:27:05.69#ibcon#read 5, iclass 32, count 2 2006.211.07:27:05.69#ibcon#about to read 6, iclass 32, count 2 2006.211.07:27:05.69#ibcon#read 6, iclass 32, count 2 2006.211.07:27:05.69#ibcon#end of sib2, iclass 32, count 2 2006.211.07:27:05.69#ibcon#*mode == 0, iclass 32, count 2 2006.211.07:27:05.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.07:27:05.69#ibcon#[25=AT04-07\r\n] 2006.211.07:27:05.69#ibcon#*before write, iclass 32, count 2 2006.211.07:27:05.69#ibcon#enter sib2, iclass 32, count 2 2006.211.07:27:05.69#ibcon#flushed, iclass 32, count 2 2006.211.07:27:05.69#ibcon#about to write, iclass 32, count 2 2006.211.07:27:05.69#ibcon#wrote, iclass 32, count 2 2006.211.07:27:05.69#ibcon#about to read 3, iclass 32, count 2 2006.211.07:27:05.72#ibcon#read 3, iclass 32, count 2 2006.211.07:27:05.72#ibcon#about to read 4, iclass 32, count 2 2006.211.07:27:05.72#ibcon#read 4, iclass 32, count 2 2006.211.07:27:05.72#ibcon#about to read 5, iclass 32, count 2 2006.211.07:27:05.72#ibcon#read 5, iclass 32, count 2 2006.211.07:27:05.72#ibcon#about to read 6, iclass 32, count 2 2006.211.07:27:05.72#ibcon#read 6, iclass 32, count 2 2006.211.07:27:05.72#ibcon#end of sib2, iclass 32, count 2 2006.211.07:27:05.72#ibcon#*after write, iclass 32, count 2 2006.211.07:27:05.72#ibcon#*before return 0, iclass 32, count 2 2006.211.07:27:05.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:05.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:05.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.07:27:05.72#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:05.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:05.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:05.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:05.84#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:27:05.84#ibcon#first serial, iclass 32, count 0 2006.211.07:27:05.84#ibcon#enter sib2, iclass 32, count 0 2006.211.07:27:05.84#ibcon#flushed, iclass 32, count 0 2006.211.07:27:05.84#ibcon#about to write, iclass 32, count 0 2006.211.07:27:05.84#ibcon#wrote, iclass 32, count 0 2006.211.07:27:05.84#ibcon#about to read 3, iclass 32, count 0 2006.211.07:27:05.86#ibcon#read 3, iclass 32, count 0 2006.211.07:27:05.86#ibcon#about to read 4, iclass 32, count 0 2006.211.07:27:05.86#ibcon#read 4, iclass 32, count 0 2006.211.07:27:05.86#ibcon#about to read 5, iclass 32, count 0 2006.211.07:27:05.86#ibcon#read 5, iclass 32, count 0 2006.211.07:27:05.86#ibcon#about to read 6, iclass 32, count 0 2006.211.07:27:05.86#ibcon#read 6, iclass 32, count 0 2006.211.07:27:05.86#ibcon#end of sib2, iclass 32, count 0 2006.211.07:27:05.86#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:27:05.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:27:05.86#ibcon#[25=USB\r\n] 2006.211.07:27:05.86#ibcon#*before write, iclass 32, count 0 2006.211.07:27:05.86#ibcon#enter sib2, iclass 32, count 0 2006.211.07:27:05.86#ibcon#flushed, iclass 32, count 0 2006.211.07:27:05.86#ibcon#about to write, iclass 32, count 0 2006.211.07:27:05.86#ibcon#wrote, iclass 32, count 0 2006.211.07:27:05.86#ibcon#about to read 3, iclass 32, count 0 2006.211.07:27:05.89#ibcon#read 3, iclass 32, count 0 2006.211.07:27:05.89#ibcon#about to read 4, iclass 32, count 0 2006.211.07:27:05.89#ibcon#read 4, iclass 32, count 0 2006.211.07:27:05.89#ibcon#about to read 5, iclass 32, count 0 2006.211.07:27:05.89#ibcon#read 5, iclass 32, count 0 2006.211.07:27:05.89#ibcon#about to read 6, iclass 32, count 0 2006.211.07:27:05.89#ibcon#read 6, iclass 32, count 0 2006.211.07:27:05.89#ibcon#end of sib2, iclass 32, count 0 2006.211.07:27:05.89#ibcon#*after write, iclass 32, count 0 2006.211.07:27:05.89#ibcon#*before return 0, iclass 32, count 0 2006.211.07:27:05.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:05.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:05.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:27:05.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:27:05.90$vc4f8/valo=5,652.99 2006.211.07:27:05.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.07:27:05.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.07:27:05.90#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:05.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:05.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:05.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:05.90#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:27:05.90#ibcon#first serial, iclass 34, count 0 2006.211.07:27:05.90#ibcon#enter sib2, iclass 34, count 0 2006.211.07:27:05.90#ibcon#flushed, iclass 34, count 0 2006.211.07:27:05.90#ibcon#about to write, iclass 34, count 0 2006.211.07:27:05.90#ibcon#wrote, iclass 34, count 0 2006.211.07:27:05.90#ibcon#about to read 3, iclass 34, count 0 2006.211.07:27:05.91#ibcon#read 3, iclass 34, count 0 2006.211.07:27:05.91#ibcon#about to read 4, iclass 34, count 0 2006.211.07:27:05.91#ibcon#read 4, iclass 34, count 0 2006.211.07:27:05.91#ibcon#about to read 5, iclass 34, count 0 2006.211.07:27:05.91#ibcon#read 5, iclass 34, count 0 2006.211.07:27:05.91#ibcon#about to read 6, iclass 34, count 0 2006.211.07:27:05.91#ibcon#read 6, iclass 34, count 0 2006.211.07:27:05.91#ibcon#end of sib2, iclass 34, count 0 2006.211.07:27:05.91#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:27:05.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:27:05.91#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:27:05.91#ibcon#*before write, iclass 34, count 0 2006.211.07:27:05.91#ibcon#enter sib2, iclass 34, count 0 2006.211.07:27:05.91#ibcon#flushed, iclass 34, count 0 2006.211.07:27:05.91#ibcon#about to write, iclass 34, count 0 2006.211.07:27:05.91#ibcon#wrote, iclass 34, count 0 2006.211.07:27:05.91#ibcon#about to read 3, iclass 34, count 0 2006.211.07:27:05.95#ibcon#read 3, iclass 34, count 0 2006.211.07:27:05.95#ibcon#about to read 4, iclass 34, count 0 2006.211.07:27:05.95#ibcon#read 4, iclass 34, count 0 2006.211.07:27:05.95#ibcon#about to read 5, iclass 34, count 0 2006.211.07:27:05.95#ibcon#read 5, iclass 34, count 0 2006.211.07:27:05.95#ibcon#about to read 6, iclass 34, count 0 2006.211.07:27:05.95#ibcon#read 6, iclass 34, count 0 2006.211.07:27:05.95#ibcon#end of sib2, iclass 34, count 0 2006.211.07:27:05.95#ibcon#*after write, iclass 34, count 0 2006.211.07:27:05.95#ibcon#*before return 0, iclass 34, count 0 2006.211.07:27:05.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:05.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:05.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:27:05.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:27:05.96$vc4f8/va=5,7 2006.211.07:27:05.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.07:27:05.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.07:27:05.96#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:05.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:06.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:06.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:06.00#ibcon#enter wrdev, iclass 36, count 2 2006.211.07:27:06.00#ibcon#first serial, iclass 36, count 2 2006.211.07:27:06.00#ibcon#enter sib2, iclass 36, count 2 2006.211.07:27:06.00#ibcon#flushed, iclass 36, count 2 2006.211.07:27:06.00#ibcon#about to write, iclass 36, count 2 2006.211.07:27:06.00#ibcon#wrote, iclass 36, count 2 2006.211.07:27:06.00#ibcon#about to read 3, iclass 36, count 2 2006.211.07:27:06.02#ibcon#read 3, iclass 36, count 2 2006.211.07:27:06.02#ibcon#about to read 4, iclass 36, count 2 2006.211.07:27:06.02#ibcon#read 4, iclass 36, count 2 2006.211.07:27:06.02#ibcon#about to read 5, iclass 36, count 2 2006.211.07:27:06.02#ibcon#read 5, iclass 36, count 2 2006.211.07:27:06.02#ibcon#about to read 6, iclass 36, count 2 2006.211.07:27:06.02#ibcon#read 6, iclass 36, count 2 2006.211.07:27:06.02#ibcon#end of sib2, iclass 36, count 2 2006.211.07:27:06.02#ibcon#*mode == 0, iclass 36, count 2 2006.211.07:27:06.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.07:27:06.02#ibcon#[25=AT05-07\r\n] 2006.211.07:27:06.02#ibcon#*before write, iclass 36, count 2 2006.211.07:27:06.02#ibcon#enter sib2, iclass 36, count 2 2006.211.07:27:06.02#ibcon#flushed, iclass 36, count 2 2006.211.07:27:06.02#ibcon#about to write, iclass 36, count 2 2006.211.07:27:06.02#ibcon#wrote, iclass 36, count 2 2006.211.07:27:06.02#ibcon#about to read 3, iclass 36, count 2 2006.211.07:27:06.05#ibcon#read 3, iclass 36, count 2 2006.211.07:27:06.05#ibcon#about to read 4, iclass 36, count 2 2006.211.07:27:06.05#ibcon#read 4, iclass 36, count 2 2006.211.07:27:06.05#ibcon#about to read 5, iclass 36, count 2 2006.211.07:27:06.05#ibcon#read 5, iclass 36, count 2 2006.211.07:27:06.05#ibcon#about to read 6, iclass 36, count 2 2006.211.07:27:06.05#ibcon#read 6, iclass 36, count 2 2006.211.07:27:06.05#ibcon#end of sib2, iclass 36, count 2 2006.211.07:27:06.05#ibcon#*after write, iclass 36, count 2 2006.211.07:27:06.05#ibcon#*before return 0, iclass 36, count 2 2006.211.07:27:06.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:06.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:06.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.07:27:06.05#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:06.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:06.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:06.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:06.17#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:27:06.17#ibcon#first serial, iclass 36, count 0 2006.211.07:27:06.17#ibcon#enter sib2, iclass 36, count 0 2006.211.07:27:06.17#ibcon#flushed, iclass 36, count 0 2006.211.07:27:06.17#ibcon#about to write, iclass 36, count 0 2006.211.07:27:06.17#ibcon#wrote, iclass 36, count 0 2006.211.07:27:06.17#ibcon#about to read 3, iclass 36, count 0 2006.211.07:27:06.19#ibcon#read 3, iclass 36, count 0 2006.211.07:27:06.19#ibcon#about to read 4, iclass 36, count 0 2006.211.07:27:06.19#ibcon#read 4, iclass 36, count 0 2006.211.07:27:06.19#ibcon#about to read 5, iclass 36, count 0 2006.211.07:27:06.19#ibcon#read 5, iclass 36, count 0 2006.211.07:27:06.19#ibcon#about to read 6, iclass 36, count 0 2006.211.07:27:06.19#ibcon#read 6, iclass 36, count 0 2006.211.07:27:06.19#ibcon#end of sib2, iclass 36, count 0 2006.211.07:27:06.19#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:27:06.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:27:06.19#ibcon#[25=USB\r\n] 2006.211.07:27:06.19#ibcon#*before write, iclass 36, count 0 2006.211.07:27:06.19#ibcon#enter sib2, iclass 36, count 0 2006.211.07:27:06.19#ibcon#flushed, iclass 36, count 0 2006.211.07:27:06.19#ibcon#about to write, iclass 36, count 0 2006.211.07:27:06.19#ibcon#wrote, iclass 36, count 0 2006.211.07:27:06.19#ibcon#about to read 3, iclass 36, count 0 2006.211.07:27:06.22#ibcon#read 3, iclass 36, count 0 2006.211.07:27:06.22#ibcon#about to read 4, iclass 36, count 0 2006.211.07:27:06.22#ibcon#read 4, iclass 36, count 0 2006.211.07:27:06.22#ibcon#about to read 5, iclass 36, count 0 2006.211.07:27:06.22#ibcon#read 5, iclass 36, count 0 2006.211.07:27:06.22#ibcon#about to read 6, iclass 36, count 0 2006.211.07:27:06.22#ibcon#read 6, iclass 36, count 0 2006.211.07:27:06.22#ibcon#end of sib2, iclass 36, count 0 2006.211.07:27:06.22#ibcon#*after write, iclass 36, count 0 2006.211.07:27:06.22#ibcon#*before return 0, iclass 36, count 0 2006.211.07:27:06.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:06.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:06.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:27:06.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:27:06.23$vc4f8/valo=6,772.99 2006.211.07:27:06.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.07:27:06.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.07:27:06.23#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:06.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:06.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:06.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:06.23#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:27:06.23#ibcon#first serial, iclass 38, count 0 2006.211.07:27:06.23#ibcon#enter sib2, iclass 38, count 0 2006.211.07:27:06.23#ibcon#flushed, iclass 38, count 0 2006.211.07:27:06.23#ibcon#about to write, iclass 38, count 0 2006.211.07:27:06.23#ibcon#wrote, iclass 38, count 0 2006.211.07:27:06.23#ibcon#about to read 3, iclass 38, count 0 2006.211.07:27:06.24#ibcon#read 3, iclass 38, count 0 2006.211.07:27:06.24#ibcon#about to read 4, iclass 38, count 0 2006.211.07:27:06.24#ibcon#read 4, iclass 38, count 0 2006.211.07:27:06.24#ibcon#about to read 5, iclass 38, count 0 2006.211.07:27:06.24#ibcon#read 5, iclass 38, count 0 2006.211.07:27:06.24#ibcon#about to read 6, iclass 38, count 0 2006.211.07:27:06.24#ibcon#read 6, iclass 38, count 0 2006.211.07:27:06.24#ibcon#end of sib2, iclass 38, count 0 2006.211.07:27:06.24#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:27:06.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:27:06.24#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:27:06.24#ibcon#*before write, iclass 38, count 0 2006.211.07:27:06.24#ibcon#enter sib2, iclass 38, count 0 2006.211.07:27:06.24#ibcon#flushed, iclass 38, count 0 2006.211.07:27:06.24#ibcon#about to write, iclass 38, count 0 2006.211.07:27:06.24#ibcon#wrote, iclass 38, count 0 2006.211.07:27:06.24#ibcon#about to read 3, iclass 38, count 0 2006.211.07:27:06.28#ibcon#read 3, iclass 38, count 0 2006.211.07:27:06.28#ibcon#about to read 4, iclass 38, count 0 2006.211.07:27:06.28#ibcon#read 4, iclass 38, count 0 2006.211.07:27:06.28#ibcon#about to read 5, iclass 38, count 0 2006.211.07:27:06.28#ibcon#read 5, iclass 38, count 0 2006.211.07:27:06.28#ibcon#about to read 6, iclass 38, count 0 2006.211.07:27:06.28#ibcon#read 6, iclass 38, count 0 2006.211.07:27:06.28#ibcon#end of sib2, iclass 38, count 0 2006.211.07:27:06.28#ibcon#*after write, iclass 38, count 0 2006.211.07:27:06.28#ibcon#*before return 0, iclass 38, count 0 2006.211.07:27:06.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:06.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:06.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:27:06.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:27:06.29$vc4f8/va=6,6 2006.211.07:27:06.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.07:27:06.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.07:27:06.29#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:06.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:27:06.33#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:27:06.33#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:27:06.33#ibcon#enter wrdev, iclass 40, count 2 2006.211.07:27:06.33#ibcon#first serial, iclass 40, count 2 2006.211.07:27:06.33#ibcon#enter sib2, iclass 40, count 2 2006.211.07:27:06.33#ibcon#flushed, iclass 40, count 2 2006.211.07:27:06.33#ibcon#about to write, iclass 40, count 2 2006.211.07:27:06.33#ibcon#wrote, iclass 40, count 2 2006.211.07:27:06.33#ibcon#about to read 3, iclass 40, count 2 2006.211.07:27:06.35#ibcon#read 3, iclass 40, count 2 2006.211.07:27:06.35#ibcon#about to read 4, iclass 40, count 2 2006.211.07:27:06.35#ibcon#read 4, iclass 40, count 2 2006.211.07:27:06.35#ibcon#about to read 5, iclass 40, count 2 2006.211.07:27:06.35#ibcon#read 5, iclass 40, count 2 2006.211.07:27:06.35#ibcon#about to read 6, iclass 40, count 2 2006.211.07:27:06.35#ibcon#read 6, iclass 40, count 2 2006.211.07:27:06.35#ibcon#end of sib2, iclass 40, count 2 2006.211.07:27:06.35#ibcon#*mode == 0, iclass 40, count 2 2006.211.07:27:06.35#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.07:27:06.35#ibcon#[25=AT06-06\r\n] 2006.211.07:27:06.35#ibcon#*before write, iclass 40, count 2 2006.211.07:27:06.35#ibcon#enter sib2, iclass 40, count 2 2006.211.07:27:06.35#ibcon#flushed, iclass 40, count 2 2006.211.07:27:06.35#ibcon#about to write, iclass 40, count 2 2006.211.07:27:06.35#ibcon#wrote, iclass 40, count 2 2006.211.07:27:06.35#ibcon#about to read 3, iclass 40, count 2 2006.211.07:27:06.38#ibcon#read 3, iclass 40, count 2 2006.211.07:27:06.38#ibcon#about to read 4, iclass 40, count 2 2006.211.07:27:06.38#ibcon#read 4, iclass 40, count 2 2006.211.07:27:06.38#ibcon#about to read 5, iclass 40, count 2 2006.211.07:27:06.38#ibcon#read 5, iclass 40, count 2 2006.211.07:27:06.38#ibcon#about to read 6, iclass 40, count 2 2006.211.07:27:06.38#ibcon#read 6, iclass 40, count 2 2006.211.07:27:06.38#ibcon#end of sib2, iclass 40, count 2 2006.211.07:27:06.38#ibcon#*after write, iclass 40, count 2 2006.211.07:27:06.38#ibcon#*before return 0, iclass 40, count 2 2006.211.07:27:06.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:27:06.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:27:06.38#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.07:27:06.38#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:06.38#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:27:06.50#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:27:06.50#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:27:06.50#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:27:06.50#ibcon#first serial, iclass 40, count 0 2006.211.07:27:06.50#ibcon#enter sib2, iclass 40, count 0 2006.211.07:27:06.50#ibcon#flushed, iclass 40, count 0 2006.211.07:27:06.50#ibcon#about to write, iclass 40, count 0 2006.211.07:27:06.50#ibcon#wrote, iclass 40, count 0 2006.211.07:27:06.50#ibcon#about to read 3, iclass 40, count 0 2006.211.07:27:06.52#ibcon#read 3, iclass 40, count 0 2006.211.07:27:06.52#ibcon#about to read 4, iclass 40, count 0 2006.211.07:27:06.52#ibcon#read 4, iclass 40, count 0 2006.211.07:27:06.52#ibcon#about to read 5, iclass 40, count 0 2006.211.07:27:06.52#ibcon#read 5, iclass 40, count 0 2006.211.07:27:06.52#ibcon#about to read 6, iclass 40, count 0 2006.211.07:27:06.52#ibcon#read 6, iclass 40, count 0 2006.211.07:27:06.52#ibcon#end of sib2, iclass 40, count 0 2006.211.07:27:06.52#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:27:06.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:27:06.52#ibcon#[25=USB\r\n] 2006.211.07:27:06.52#ibcon#*before write, iclass 40, count 0 2006.211.07:27:06.52#ibcon#enter sib2, iclass 40, count 0 2006.211.07:27:06.52#ibcon#flushed, iclass 40, count 0 2006.211.07:27:06.52#ibcon#about to write, iclass 40, count 0 2006.211.07:27:06.52#ibcon#wrote, iclass 40, count 0 2006.211.07:27:06.52#ibcon#about to read 3, iclass 40, count 0 2006.211.07:27:06.55#ibcon#read 3, iclass 40, count 0 2006.211.07:27:06.55#ibcon#about to read 4, iclass 40, count 0 2006.211.07:27:06.55#ibcon#read 4, iclass 40, count 0 2006.211.07:27:06.55#ibcon#about to read 5, iclass 40, count 0 2006.211.07:27:06.55#ibcon#read 5, iclass 40, count 0 2006.211.07:27:06.55#ibcon#about to read 6, iclass 40, count 0 2006.211.07:27:06.55#ibcon#read 6, iclass 40, count 0 2006.211.07:27:06.55#ibcon#end of sib2, iclass 40, count 0 2006.211.07:27:06.55#ibcon#*after write, iclass 40, count 0 2006.211.07:27:06.55#ibcon#*before return 0, iclass 40, count 0 2006.211.07:27:06.55#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:27:06.55#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:27:06.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:27:06.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:27:06.56$vc4f8/valo=7,832.99 2006.211.07:27:06.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.07:27:06.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.07:27:06.56#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:06.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:27:06.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:27:06.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:27:06.56#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:27:06.56#ibcon#first serial, iclass 4, count 0 2006.211.07:27:06.56#ibcon#enter sib2, iclass 4, count 0 2006.211.07:27:06.56#ibcon#flushed, iclass 4, count 0 2006.211.07:27:06.56#ibcon#about to write, iclass 4, count 0 2006.211.07:27:06.56#ibcon#wrote, iclass 4, count 0 2006.211.07:27:06.56#ibcon#about to read 3, iclass 4, count 0 2006.211.07:27:06.57#ibcon#read 3, iclass 4, count 0 2006.211.07:27:06.57#ibcon#about to read 4, iclass 4, count 0 2006.211.07:27:06.57#ibcon#read 4, iclass 4, count 0 2006.211.07:27:06.57#ibcon#about to read 5, iclass 4, count 0 2006.211.07:27:06.57#ibcon#read 5, iclass 4, count 0 2006.211.07:27:06.57#ibcon#about to read 6, iclass 4, count 0 2006.211.07:27:06.57#ibcon#read 6, iclass 4, count 0 2006.211.07:27:06.57#ibcon#end of sib2, iclass 4, count 0 2006.211.07:27:06.57#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:27:06.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:27:06.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:27:06.57#ibcon#*before write, iclass 4, count 0 2006.211.07:27:06.57#ibcon#enter sib2, iclass 4, count 0 2006.211.07:27:06.57#ibcon#flushed, iclass 4, count 0 2006.211.07:27:06.57#ibcon#about to write, iclass 4, count 0 2006.211.07:27:06.57#ibcon#wrote, iclass 4, count 0 2006.211.07:27:06.57#ibcon#about to read 3, iclass 4, count 0 2006.211.07:27:06.61#ibcon#read 3, iclass 4, count 0 2006.211.07:27:06.61#ibcon#about to read 4, iclass 4, count 0 2006.211.07:27:06.61#ibcon#read 4, iclass 4, count 0 2006.211.07:27:06.61#ibcon#about to read 5, iclass 4, count 0 2006.211.07:27:06.61#ibcon#read 5, iclass 4, count 0 2006.211.07:27:06.61#ibcon#about to read 6, iclass 4, count 0 2006.211.07:27:06.61#ibcon#read 6, iclass 4, count 0 2006.211.07:27:06.61#ibcon#end of sib2, iclass 4, count 0 2006.211.07:27:06.61#ibcon#*after write, iclass 4, count 0 2006.211.07:27:06.61#ibcon#*before return 0, iclass 4, count 0 2006.211.07:27:06.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:27:06.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:27:06.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:27:06.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:27:06.62$vc4f8/va=7,6 2006.211.07:27:06.62#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.07:27:06.62#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.07:27:06.62#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:06.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:27:06.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:27:06.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:27:06.66#ibcon#enter wrdev, iclass 6, count 2 2006.211.07:27:06.66#ibcon#first serial, iclass 6, count 2 2006.211.07:27:06.66#ibcon#enter sib2, iclass 6, count 2 2006.211.07:27:06.66#ibcon#flushed, iclass 6, count 2 2006.211.07:27:06.66#ibcon#about to write, iclass 6, count 2 2006.211.07:27:06.66#ibcon#wrote, iclass 6, count 2 2006.211.07:27:06.66#ibcon#about to read 3, iclass 6, count 2 2006.211.07:27:06.68#ibcon#read 3, iclass 6, count 2 2006.211.07:27:06.68#ibcon#about to read 4, iclass 6, count 2 2006.211.07:27:06.68#ibcon#read 4, iclass 6, count 2 2006.211.07:27:06.68#ibcon#about to read 5, iclass 6, count 2 2006.211.07:27:06.68#ibcon#read 5, iclass 6, count 2 2006.211.07:27:06.68#ibcon#about to read 6, iclass 6, count 2 2006.211.07:27:06.68#ibcon#read 6, iclass 6, count 2 2006.211.07:27:06.68#ibcon#end of sib2, iclass 6, count 2 2006.211.07:27:06.68#ibcon#*mode == 0, iclass 6, count 2 2006.211.07:27:06.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.07:27:06.68#ibcon#[25=AT07-06\r\n] 2006.211.07:27:06.68#ibcon#*before write, iclass 6, count 2 2006.211.07:27:06.68#ibcon#enter sib2, iclass 6, count 2 2006.211.07:27:06.68#ibcon#flushed, iclass 6, count 2 2006.211.07:27:06.68#ibcon#about to write, iclass 6, count 2 2006.211.07:27:06.68#ibcon#wrote, iclass 6, count 2 2006.211.07:27:06.68#ibcon#about to read 3, iclass 6, count 2 2006.211.07:27:06.71#ibcon#read 3, iclass 6, count 2 2006.211.07:27:06.71#ibcon#about to read 4, iclass 6, count 2 2006.211.07:27:06.71#ibcon#read 4, iclass 6, count 2 2006.211.07:27:06.71#ibcon#about to read 5, iclass 6, count 2 2006.211.07:27:06.71#ibcon#read 5, iclass 6, count 2 2006.211.07:27:06.71#ibcon#about to read 6, iclass 6, count 2 2006.211.07:27:06.71#ibcon#read 6, iclass 6, count 2 2006.211.07:27:06.71#ibcon#end of sib2, iclass 6, count 2 2006.211.07:27:06.71#ibcon#*after write, iclass 6, count 2 2006.211.07:27:06.71#ibcon#*before return 0, iclass 6, count 2 2006.211.07:27:06.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:27:06.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:27:06.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.07:27:06.71#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:06.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:27:06.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:27:06.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:27:06.83#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:27:06.83#ibcon#first serial, iclass 6, count 0 2006.211.07:27:06.83#ibcon#enter sib2, iclass 6, count 0 2006.211.07:27:06.83#ibcon#flushed, iclass 6, count 0 2006.211.07:27:06.83#ibcon#about to write, iclass 6, count 0 2006.211.07:27:06.83#ibcon#wrote, iclass 6, count 0 2006.211.07:27:06.83#ibcon#about to read 3, iclass 6, count 0 2006.211.07:27:06.85#ibcon#read 3, iclass 6, count 0 2006.211.07:27:06.85#ibcon#about to read 4, iclass 6, count 0 2006.211.07:27:06.85#ibcon#read 4, iclass 6, count 0 2006.211.07:27:06.85#ibcon#about to read 5, iclass 6, count 0 2006.211.07:27:06.85#ibcon#read 5, iclass 6, count 0 2006.211.07:27:06.85#ibcon#about to read 6, iclass 6, count 0 2006.211.07:27:06.85#ibcon#read 6, iclass 6, count 0 2006.211.07:27:06.85#ibcon#end of sib2, iclass 6, count 0 2006.211.07:27:06.85#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:27:06.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:27:06.85#ibcon#[25=USB\r\n] 2006.211.07:27:06.85#ibcon#*before write, iclass 6, count 0 2006.211.07:27:06.85#ibcon#enter sib2, iclass 6, count 0 2006.211.07:27:06.85#ibcon#flushed, iclass 6, count 0 2006.211.07:27:06.85#ibcon#about to write, iclass 6, count 0 2006.211.07:27:06.85#ibcon#wrote, iclass 6, count 0 2006.211.07:27:06.85#ibcon#about to read 3, iclass 6, count 0 2006.211.07:27:06.88#ibcon#read 3, iclass 6, count 0 2006.211.07:27:06.88#ibcon#about to read 4, iclass 6, count 0 2006.211.07:27:06.88#ibcon#read 4, iclass 6, count 0 2006.211.07:27:06.88#ibcon#about to read 5, iclass 6, count 0 2006.211.07:27:06.88#ibcon#read 5, iclass 6, count 0 2006.211.07:27:06.88#ibcon#about to read 6, iclass 6, count 0 2006.211.07:27:06.88#ibcon#read 6, iclass 6, count 0 2006.211.07:27:06.88#ibcon#end of sib2, iclass 6, count 0 2006.211.07:27:06.88#ibcon#*after write, iclass 6, count 0 2006.211.07:27:06.88#ibcon#*before return 0, iclass 6, count 0 2006.211.07:27:06.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:27:06.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:27:06.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:27:06.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:27:06.89$vc4f8/valo=8,852.99 2006.211.07:27:06.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.07:27:06.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.07:27:06.89#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:06.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:27:06.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:27:06.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:27:06.89#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:27:06.89#ibcon#first serial, iclass 10, count 0 2006.211.07:27:06.89#ibcon#enter sib2, iclass 10, count 0 2006.211.07:27:06.89#ibcon#flushed, iclass 10, count 0 2006.211.07:27:06.89#ibcon#about to write, iclass 10, count 0 2006.211.07:27:06.89#ibcon#wrote, iclass 10, count 0 2006.211.07:27:06.89#ibcon#about to read 3, iclass 10, count 0 2006.211.07:27:06.90#ibcon#read 3, iclass 10, count 0 2006.211.07:27:06.90#ibcon#about to read 4, iclass 10, count 0 2006.211.07:27:06.90#ibcon#read 4, iclass 10, count 0 2006.211.07:27:06.90#ibcon#about to read 5, iclass 10, count 0 2006.211.07:27:06.90#ibcon#read 5, iclass 10, count 0 2006.211.07:27:06.90#ibcon#about to read 6, iclass 10, count 0 2006.211.07:27:06.90#ibcon#read 6, iclass 10, count 0 2006.211.07:27:06.90#ibcon#end of sib2, iclass 10, count 0 2006.211.07:27:06.90#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:27:06.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:27:06.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:27:06.90#ibcon#*before write, iclass 10, count 0 2006.211.07:27:06.90#ibcon#enter sib2, iclass 10, count 0 2006.211.07:27:06.90#ibcon#flushed, iclass 10, count 0 2006.211.07:27:06.90#ibcon#about to write, iclass 10, count 0 2006.211.07:27:06.90#ibcon#wrote, iclass 10, count 0 2006.211.07:27:06.90#ibcon#about to read 3, iclass 10, count 0 2006.211.07:27:06.94#ibcon#read 3, iclass 10, count 0 2006.211.07:27:06.94#ibcon#about to read 4, iclass 10, count 0 2006.211.07:27:06.94#ibcon#read 4, iclass 10, count 0 2006.211.07:27:06.94#ibcon#about to read 5, iclass 10, count 0 2006.211.07:27:06.94#ibcon#read 5, iclass 10, count 0 2006.211.07:27:06.94#ibcon#about to read 6, iclass 10, count 0 2006.211.07:27:06.94#ibcon#read 6, iclass 10, count 0 2006.211.07:27:06.94#ibcon#end of sib2, iclass 10, count 0 2006.211.07:27:06.94#ibcon#*after write, iclass 10, count 0 2006.211.07:27:06.94#ibcon#*before return 0, iclass 10, count 0 2006.211.07:27:06.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:27:06.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:27:06.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:27:06.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:27:06.95$vc4f8/va=8,7 2006.211.07:27:06.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.07:27:06.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.07:27:06.95#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:06.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:27:06.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:27:06.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:27:06.99#ibcon#enter wrdev, iclass 12, count 2 2006.211.07:27:06.99#ibcon#first serial, iclass 12, count 2 2006.211.07:27:06.99#ibcon#enter sib2, iclass 12, count 2 2006.211.07:27:06.99#ibcon#flushed, iclass 12, count 2 2006.211.07:27:06.99#ibcon#about to write, iclass 12, count 2 2006.211.07:27:06.99#ibcon#wrote, iclass 12, count 2 2006.211.07:27:06.99#ibcon#about to read 3, iclass 12, count 2 2006.211.07:27:07.01#ibcon#read 3, iclass 12, count 2 2006.211.07:27:07.01#ibcon#about to read 4, iclass 12, count 2 2006.211.07:27:07.01#ibcon#read 4, iclass 12, count 2 2006.211.07:27:07.01#ibcon#about to read 5, iclass 12, count 2 2006.211.07:27:07.01#ibcon#read 5, iclass 12, count 2 2006.211.07:27:07.01#ibcon#about to read 6, iclass 12, count 2 2006.211.07:27:07.01#ibcon#read 6, iclass 12, count 2 2006.211.07:27:07.01#ibcon#end of sib2, iclass 12, count 2 2006.211.07:27:07.01#ibcon#*mode == 0, iclass 12, count 2 2006.211.07:27:07.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.07:27:07.01#ibcon#[25=AT08-07\r\n] 2006.211.07:27:07.01#ibcon#*before write, iclass 12, count 2 2006.211.07:27:07.01#ibcon#enter sib2, iclass 12, count 2 2006.211.07:27:07.01#ibcon#flushed, iclass 12, count 2 2006.211.07:27:07.01#ibcon#about to write, iclass 12, count 2 2006.211.07:27:07.01#ibcon#wrote, iclass 12, count 2 2006.211.07:27:07.01#ibcon#about to read 3, iclass 12, count 2 2006.211.07:27:07.04#ibcon#read 3, iclass 12, count 2 2006.211.07:27:07.04#ibcon#about to read 4, iclass 12, count 2 2006.211.07:27:07.04#ibcon#read 4, iclass 12, count 2 2006.211.07:27:07.04#ibcon#about to read 5, iclass 12, count 2 2006.211.07:27:07.04#ibcon#read 5, iclass 12, count 2 2006.211.07:27:07.04#ibcon#about to read 6, iclass 12, count 2 2006.211.07:27:07.04#ibcon#read 6, iclass 12, count 2 2006.211.07:27:07.04#ibcon#end of sib2, iclass 12, count 2 2006.211.07:27:07.04#ibcon#*after write, iclass 12, count 2 2006.211.07:27:07.04#ibcon#*before return 0, iclass 12, count 2 2006.211.07:27:07.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:27:07.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:27:07.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.07:27:07.04#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:07.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:27:07.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:27:07.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:27:07.16#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:27:07.16#ibcon#first serial, iclass 12, count 0 2006.211.07:27:07.16#ibcon#enter sib2, iclass 12, count 0 2006.211.07:27:07.16#ibcon#flushed, iclass 12, count 0 2006.211.07:27:07.16#ibcon#about to write, iclass 12, count 0 2006.211.07:27:07.16#ibcon#wrote, iclass 12, count 0 2006.211.07:27:07.16#ibcon#about to read 3, iclass 12, count 0 2006.211.07:27:07.18#ibcon#read 3, iclass 12, count 0 2006.211.07:27:07.18#ibcon#about to read 4, iclass 12, count 0 2006.211.07:27:07.18#ibcon#read 4, iclass 12, count 0 2006.211.07:27:07.18#ibcon#about to read 5, iclass 12, count 0 2006.211.07:27:07.18#ibcon#read 5, iclass 12, count 0 2006.211.07:27:07.18#ibcon#about to read 6, iclass 12, count 0 2006.211.07:27:07.18#ibcon#read 6, iclass 12, count 0 2006.211.07:27:07.18#ibcon#end of sib2, iclass 12, count 0 2006.211.07:27:07.18#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:27:07.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:27:07.18#ibcon#[25=USB\r\n] 2006.211.07:27:07.18#ibcon#*before write, iclass 12, count 0 2006.211.07:27:07.18#ibcon#enter sib2, iclass 12, count 0 2006.211.07:27:07.18#ibcon#flushed, iclass 12, count 0 2006.211.07:27:07.18#ibcon#about to write, iclass 12, count 0 2006.211.07:27:07.18#ibcon#wrote, iclass 12, count 0 2006.211.07:27:07.18#ibcon#about to read 3, iclass 12, count 0 2006.211.07:27:07.21#ibcon#read 3, iclass 12, count 0 2006.211.07:27:07.21#ibcon#about to read 4, iclass 12, count 0 2006.211.07:27:07.21#ibcon#read 4, iclass 12, count 0 2006.211.07:27:07.21#ibcon#about to read 5, iclass 12, count 0 2006.211.07:27:07.21#ibcon#read 5, iclass 12, count 0 2006.211.07:27:07.21#ibcon#about to read 6, iclass 12, count 0 2006.211.07:27:07.21#ibcon#read 6, iclass 12, count 0 2006.211.07:27:07.21#ibcon#end of sib2, iclass 12, count 0 2006.211.07:27:07.21#ibcon#*after write, iclass 12, count 0 2006.211.07:27:07.21#ibcon#*before return 0, iclass 12, count 0 2006.211.07:27:07.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:27:07.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:27:07.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:27:07.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:27:07.22$vc4f8/vblo=1,632.99 2006.211.07:27:07.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.07:27:07.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.07:27:07.22#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:07.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:27:07.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:27:07.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:27:07.22#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:27:07.22#ibcon#first serial, iclass 14, count 0 2006.211.07:27:07.22#ibcon#enter sib2, iclass 14, count 0 2006.211.07:27:07.22#ibcon#flushed, iclass 14, count 0 2006.211.07:27:07.22#ibcon#about to write, iclass 14, count 0 2006.211.07:27:07.22#ibcon#wrote, iclass 14, count 0 2006.211.07:27:07.22#ibcon#about to read 3, iclass 14, count 0 2006.211.07:27:07.23#ibcon#read 3, iclass 14, count 0 2006.211.07:27:07.23#ibcon#about to read 4, iclass 14, count 0 2006.211.07:27:07.23#ibcon#read 4, iclass 14, count 0 2006.211.07:27:07.23#ibcon#about to read 5, iclass 14, count 0 2006.211.07:27:07.23#ibcon#read 5, iclass 14, count 0 2006.211.07:27:07.23#ibcon#about to read 6, iclass 14, count 0 2006.211.07:27:07.23#ibcon#read 6, iclass 14, count 0 2006.211.07:27:07.23#ibcon#end of sib2, iclass 14, count 0 2006.211.07:27:07.23#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:27:07.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:27:07.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:27:07.23#ibcon#*before write, iclass 14, count 0 2006.211.07:27:07.23#ibcon#enter sib2, iclass 14, count 0 2006.211.07:27:07.23#ibcon#flushed, iclass 14, count 0 2006.211.07:27:07.23#ibcon#about to write, iclass 14, count 0 2006.211.07:27:07.23#ibcon#wrote, iclass 14, count 0 2006.211.07:27:07.23#ibcon#about to read 3, iclass 14, count 0 2006.211.07:27:07.27#ibcon#read 3, iclass 14, count 0 2006.211.07:27:07.27#ibcon#about to read 4, iclass 14, count 0 2006.211.07:27:07.27#ibcon#read 4, iclass 14, count 0 2006.211.07:27:07.27#ibcon#about to read 5, iclass 14, count 0 2006.211.07:27:07.27#ibcon#read 5, iclass 14, count 0 2006.211.07:27:07.27#ibcon#about to read 6, iclass 14, count 0 2006.211.07:27:07.27#ibcon#read 6, iclass 14, count 0 2006.211.07:27:07.27#ibcon#end of sib2, iclass 14, count 0 2006.211.07:27:07.27#ibcon#*after write, iclass 14, count 0 2006.211.07:27:07.27#ibcon#*before return 0, iclass 14, count 0 2006.211.07:27:07.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:27:07.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:27:07.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:27:07.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:27:07.27$vc4f8/vb=1,4 2006.211.07:27:07.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.07:27:07.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.07:27:07.28#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:07.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:27:07.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:27:07.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:27:07.28#ibcon#enter wrdev, iclass 16, count 2 2006.211.07:27:07.28#ibcon#first serial, iclass 16, count 2 2006.211.07:27:07.28#ibcon#enter sib2, iclass 16, count 2 2006.211.07:27:07.28#ibcon#flushed, iclass 16, count 2 2006.211.07:27:07.28#ibcon#about to write, iclass 16, count 2 2006.211.07:27:07.28#ibcon#wrote, iclass 16, count 2 2006.211.07:27:07.28#ibcon#about to read 3, iclass 16, count 2 2006.211.07:27:07.29#ibcon#read 3, iclass 16, count 2 2006.211.07:27:07.29#ibcon#about to read 4, iclass 16, count 2 2006.211.07:27:07.29#ibcon#read 4, iclass 16, count 2 2006.211.07:27:07.29#ibcon#about to read 5, iclass 16, count 2 2006.211.07:27:07.29#ibcon#read 5, iclass 16, count 2 2006.211.07:27:07.29#ibcon#about to read 6, iclass 16, count 2 2006.211.07:27:07.29#ibcon#read 6, iclass 16, count 2 2006.211.07:27:07.29#ibcon#end of sib2, iclass 16, count 2 2006.211.07:27:07.29#ibcon#*mode == 0, iclass 16, count 2 2006.211.07:27:07.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.07:27:07.29#ibcon#[27=AT01-04\r\n] 2006.211.07:27:07.29#ibcon#*before write, iclass 16, count 2 2006.211.07:27:07.29#ibcon#enter sib2, iclass 16, count 2 2006.211.07:27:07.29#ibcon#flushed, iclass 16, count 2 2006.211.07:27:07.29#ibcon#about to write, iclass 16, count 2 2006.211.07:27:07.29#ibcon#wrote, iclass 16, count 2 2006.211.07:27:07.29#ibcon#about to read 3, iclass 16, count 2 2006.211.07:27:07.32#ibcon#read 3, iclass 16, count 2 2006.211.07:27:07.32#ibcon#about to read 4, iclass 16, count 2 2006.211.07:27:07.32#ibcon#read 4, iclass 16, count 2 2006.211.07:27:07.32#ibcon#about to read 5, iclass 16, count 2 2006.211.07:27:07.32#ibcon#read 5, iclass 16, count 2 2006.211.07:27:07.32#ibcon#about to read 6, iclass 16, count 2 2006.211.07:27:07.32#ibcon#read 6, iclass 16, count 2 2006.211.07:27:07.32#ibcon#end of sib2, iclass 16, count 2 2006.211.07:27:07.32#ibcon#*after write, iclass 16, count 2 2006.211.07:27:07.32#ibcon#*before return 0, iclass 16, count 2 2006.211.07:27:07.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:27:07.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:27:07.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.07:27:07.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:07.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:27:07.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:27:07.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:27:07.44#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:27:07.44#ibcon#first serial, iclass 16, count 0 2006.211.07:27:07.44#ibcon#enter sib2, iclass 16, count 0 2006.211.07:27:07.44#ibcon#flushed, iclass 16, count 0 2006.211.07:27:07.44#ibcon#about to write, iclass 16, count 0 2006.211.07:27:07.44#ibcon#wrote, iclass 16, count 0 2006.211.07:27:07.44#ibcon#about to read 3, iclass 16, count 0 2006.211.07:27:07.46#ibcon#read 3, iclass 16, count 0 2006.211.07:27:07.46#ibcon#about to read 4, iclass 16, count 0 2006.211.07:27:07.46#ibcon#read 4, iclass 16, count 0 2006.211.07:27:07.46#ibcon#about to read 5, iclass 16, count 0 2006.211.07:27:07.46#ibcon#read 5, iclass 16, count 0 2006.211.07:27:07.46#ibcon#about to read 6, iclass 16, count 0 2006.211.07:27:07.46#ibcon#read 6, iclass 16, count 0 2006.211.07:27:07.46#ibcon#end of sib2, iclass 16, count 0 2006.211.07:27:07.46#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:27:07.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:27:07.46#ibcon#[27=USB\r\n] 2006.211.07:27:07.46#ibcon#*before write, iclass 16, count 0 2006.211.07:27:07.46#ibcon#enter sib2, iclass 16, count 0 2006.211.07:27:07.46#ibcon#flushed, iclass 16, count 0 2006.211.07:27:07.46#ibcon#about to write, iclass 16, count 0 2006.211.07:27:07.46#ibcon#wrote, iclass 16, count 0 2006.211.07:27:07.46#ibcon#about to read 3, iclass 16, count 0 2006.211.07:27:07.49#ibcon#read 3, iclass 16, count 0 2006.211.07:27:07.49#ibcon#about to read 4, iclass 16, count 0 2006.211.07:27:07.49#ibcon#read 4, iclass 16, count 0 2006.211.07:27:07.49#ibcon#about to read 5, iclass 16, count 0 2006.211.07:27:07.49#ibcon#read 5, iclass 16, count 0 2006.211.07:27:07.49#ibcon#about to read 6, iclass 16, count 0 2006.211.07:27:07.49#ibcon#read 6, iclass 16, count 0 2006.211.07:27:07.49#ibcon#end of sib2, iclass 16, count 0 2006.211.07:27:07.49#ibcon#*after write, iclass 16, count 0 2006.211.07:27:07.49#ibcon#*before return 0, iclass 16, count 0 2006.211.07:27:07.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:27:07.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:27:07.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:27:07.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:27:07.50$vc4f8/vblo=2,640.99 2006.211.07:27:07.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:27:07.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:27:07.50#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:07.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:07.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:07.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:07.50#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:27:07.50#ibcon#first serial, iclass 18, count 0 2006.211.07:27:07.50#ibcon#enter sib2, iclass 18, count 0 2006.211.07:27:07.50#ibcon#flushed, iclass 18, count 0 2006.211.07:27:07.50#ibcon#about to write, iclass 18, count 0 2006.211.07:27:07.50#ibcon#wrote, iclass 18, count 0 2006.211.07:27:07.50#ibcon#about to read 3, iclass 18, count 0 2006.211.07:27:07.51#ibcon#read 3, iclass 18, count 0 2006.211.07:27:07.51#ibcon#about to read 4, iclass 18, count 0 2006.211.07:27:07.51#ibcon#read 4, iclass 18, count 0 2006.211.07:27:07.51#ibcon#about to read 5, iclass 18, count 0 2006.211.07:27:07.51#ibcon#read 5, iclass 18, count 0 2006.211.07:27:07.51#ibcon#about to read 6, iclass 18, count 0 2006.211.07:27:07.51#ibcon#read 6, iclass 18, count 0 2006.211.07:27:07.51#ibcon#end of sib2, iclass 18, count 0 2006.211.07:27:07.51#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:27:07.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:27:07.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:27:07.51#ibcon#*before write, iclass 18, count 0 2006.211.07:27:07.51#ibcon#enter sib2, iclass 18, count 0 2006.211.07:27:07.51#ibcon#flushed, iclass 18, count 0 2006.211.07:27:07.51#ibcon#about to write, iclass 18, count 0 2006.211.07:27:07.51#ibcon#wrote, iclass 18, count 0 2006.211.07:27:07.51#ibcon#about to read 3, iclass 18, count 0 2006.211.07:27:07.55#ibcon#read 3, iclass 18, count 0 2006.211.07:27:07.55#ibcon#about to read 4, iclass 18, count 0 2006.211.07:27:07.55#ibcon#read 4, iclass 18, count 0 2006.211.07:27:07.55#ibcon#about to read 5, iclass 18, count 0 2006.211.07:27:07.55#ibcon#read 5, iclass 18, count 0 2006.211.07:27:07.55#ibcon#about to read 6, iclass 18, count 0 2006.211.07:27:07.55#ibcon#read 6, iclass 18, count 0 2006.211.07:27:07.55#ibcon#end of sib2, iclass 18, count 0 2006.211.07:27:07.55#ibcon#*after write, iclass 18, count 0 2006.211.07:27:07.55#ibcon#*before return 0, iclass 18, count 0 2006.211.07:27:07.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:07.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:27:07.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:27:07.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:27:07.56$vc4f8/vb=2,4 2006.211.07:27:07.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:27:07.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:27:07.56#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:07.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:07.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:07.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:07.60#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:27:07.60#ibcon#first serial, iclass 20, count 2 2006.211.07:27:07.60#ibcon#enter sib2, iclass 20, count 2 2006.211.07:27:07.60#ibcon#flushed, iclass 20, count 2 2006.211.07:27:07.60#ibcon#about to write, iclass 20, count 2 2006.211.07:27:07.60#ibcon#wrote, iclass 20, count 2 2006.211.07:27:07.60#ibcon#about to read 3, iclass 20, count 2 2006.211.07:27:07.62#ibcon#read 3, iclass 20, count 2 2006.211.07:27:07.62#ibcon#about to read 4, iclass 20, count 2 2006.211.07:27:07.62#ibcon#read 4, iclass 20, count 2 2006.211.07:27:07.62#ibcon#about to read 5, iclass 20, count 2 2006.211.07:27:07.62#ibcon#read 5, iclass 20, count 2 2006.211.07:27:07.62#ibcon#about to read 6, iclass 20, count 2 2006.211.07:27:07.62#ibcon#read 6, iclass 20, count 2 2006.211.07:27:07.62#ibcon#end of sib2, iclass 20, count 2 2006.211.07:27:07.62#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:27:07.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:27:07.62#ibcon#[27=AT02-04\r\n] 2006.211.07:27:07.62#ibcon#*before write, iclass 20, count 2 2006.211.07:27:07.62#ibcon#enter sib2, iclass 20, count 2 2006.211.07:27:07.62#ibcon#flushed, iclass 20, count 2 2006.211.07:27:07.62#ibcon#about to write, iclass 20, count 2 2006.211.07:27:07.62#ibcon#wrote, iclass 20, count 2 2006.211.07:27:07.62#ibcon#about to read 3, iclass 20, count 2 2006.211.07:27:07.65#ibcon#read 3, iclass 20, count 2 2006.211.07:27:07.65#ibcon#about to read 4, iclass 20, count 2 2006.211.07:27:07.65#ibcon#read 4, iclass 20, count 2 2006.211.07:27:07.65#ibcon#about to read 5, iclass 20, count 2 2006.211.07:27:07.65#ibcon#read 5, iclass 20, count 2 2006.211.07:27:07.65#ibcon#about to read 6, iclass 20, count 2 2006.211.07:27:07.65#ibcon#read 6, iclass 20, count 2 2006.211.07:27:07.65#ibcon#end of sib2, iclass 20, count 2 2006.211.07:27:07.65#ibcon#*after write, iclass 20, count 2 2006.211.07:27:07.65#ibcon#*before return 0, iclass 20, count 2 2006.211.07:27:07.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:07.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:27:07.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:27:07.65#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:07.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:07.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:07.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:07.77#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:27:07.77#ibcon#first serial, iclass 20, count 0 2006.211.07:27:07.77#ibcon#enter sib2, iclass 20, count 0 2006.211.07:27:07.77#ibcon#flushed, iclass 20, count 0 2006.211.07:27:07.77#ibcon#about to write, iclass 20, count 0 2006.211.07:27:07.77#ibcon#wrote, iclass 20, count 0 2006.211.07:27:07.77#ibcon#about to read 3, iclass 20, count 0 2006.211.07:27:07.79#ibcon#read 3, iclass 20, count 0 2006.211.07:27:07.79#ibcon#about to read 4, iclass 20, count 0 2006.211.07:27:07.79#ibcon#read 4, iclass 20, count 0 2006.211.07:27:07.79#ibcon#about to read 5, iclass 20, count 0 2006.211.07:27:07.79#ibcon#read 5, iclass 20, count 0 2006.211.07:27:07.79#ibcon#about to read 6, iclass 20, count 0 2006.211.07:27:07.79#ibcon#read 6, iclass 20, count 0 2006.211.07:27:07.79#ibcon#end of sib2, iclass 20, count 0 2006.211.07:27:07.79#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:27:07.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:27:07.79#ibcon#[27=USB\r\n] 2006.211.07:27:07.79#ibcon#*before write, iclass 20, count 0 2006.211.07:27:07.79#ibcon#enter sib2, iclass 20, count 0 2006.211.07:27:07.79#ibcon#flushed, iclass 20, count 0 2006.211.07:27:07.79#ibcon#about to write, iclass 20, count 0 2006.211.07:27:07.79#ibcon#wrote, iclass 20, count 0 2006.211.07:27:07.79#ibcon#about to read 3, iclass 20, count 0 2006.211.07:27:07.82#ibcon#read 3, iclass 20, count 0 2006.211.07:27:07.82#ibcon#about to read 4, iclass 20, count 0 2006.211.07:27:07.82#ibcon#read 4, iclass 20, count 0 2006.211.07:27:07.82#ibcon#about to read 5, iclass 20, count 0 2006.211.07:27:07.82#ibcon#read 5, iclass 20, count 0 2006.211.07:27:07.82#ibcon#about to read 6, iclass 20, count 0 2006.211.07:27:07.82#ibcon#read 6, iclass 20, count 0 2006.211.07:27:07.82#ibcon#end of sib2, iclass 20, count 0 2006.211.07:27:07.82#ibcon#*after write, iclass 20, count 0 2006.211.07:27:07.82#ibcon#*before return 0, iclass 20, count 0 2006.211.07:27:07.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:07.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:27:07.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:27:07.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:27:07.83$vc4f8/vblo=3,656.99 2006.211.07:27:07.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:27:07.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:27:07.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:07.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:07.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:07.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:07.83#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:27:07.83#ibcon#first serial, iclass 22, count 0 2006.211.07:27:07.83#ibcon#enter sib2, iclass 22, count 0 2006.211.07:27:07.83#ibcon#flushed, iclass 22, count 0 2006.211.07:27:07.83#ibcon#about to write, iclass 22, count 0 2006.211.07:27:07.83#ibcon#wrote, iclass 22, count 0 2006.211.07:27:07.83#ibcon#about to read 3, iclass 22, count 0 2006.211.07:27:07.84#ibcon#read 3, iclass 22, count 0 2006.211.07:27:07.84#ibcon#about to read 4, iclass 22, count 0 2006.211.07:27:07.84#ibcon#read 4, iclass 22, count 0 2006.211.07:27:07.84#ibcon#about to read 5, iclass 22, count 0 2006.211.07:27:07.84#ibcon#read 5, iclass 22, count 0 2006.211.07:27:07.84#ibcon#about to read 6, iclass 22, count 0 2006.211.07:27:07.84#ibcon#read 6, iclass 22, count 0 2006.211.07:27:07.84#ibcon#end of sib2, iclass 22, count 0 2006.211.07:27:07.84#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:27:07.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:27:07.84#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:27:07.84#ibcon#*before write, iclass 22, count 0 2006.211.07:27:07.84#ibcon#enter sib2, iclass 22, count 0 2006.211.07:27:07.84#ibcon#flushed, iclass 22, count 0 2006.211.07:27:07.84#ibcon#about to write, iclass 22, count 0 2006.211.07:27:07.84#ibcon#wrote, iclass 22, count 0 2006.211.07:27:07.84#ibcon#about to read 3, iclass 22, count 0 2006.211.07:27:07.88#ibcon#read 3, iclass 22, count 0 2006.211.07:27:07.88#ibcon#about to read 4, iclass 22, count 0 2006.211.07:27:07.88#ibcon#read 4, iclass 22, count 0 2006.211.07:27:07.88#ibcon#about to read 5, iclass 22, count 0 2006.211.07:27:07.88#ibcon#read 5, iclass 22, count 0 2006.211.07:27:07.88#ibcon#about to read 6, iclass 22, count 0 2006.211.07:27:07.88#ibcon#read 6, iclass 22, count 0 2006.211.07:27:07.88#ibcon#end of sib2, iclass 22, count 0 2006.211.07:27:07.88#ibcon#*after write, iclass 22, count 0 2006.211.07:27:07.88#ibcon#*before return 0, iclass 22, count 0 2006.211.07:27:07.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:07.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:27:07.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:27:07.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:27:07.89$vc4f8/vb=3,3 2006.211.07:27:07.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:27:07.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:27:07.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:07.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:07.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:07.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:07.93#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:27:07.93#ibcon#first serial, iclass 24, count 2 2006.211.07:27:07.93#ibcon#enter sib2, iclass 24, count 2 2006.211.07:27:07.93#ibcon#flushed, iclass 24, count 2 2006.211.07:27:07.93#ibcon#about to write, iclass 24, count 2 2006.211.07:27:07.93#ibcon#wrote, iclass 24, count 2 2006.211.07:27:07.93#ibcon#about to read 3, iclass 24, count 2 2006.211.07:27:07.95#ibcon#read 3, iclass 24, count 2 2006.211.07:27:07.95#ibcon#about to read 4, iclass 24, count 2 2006.211.07:27:07.95#ibcon#read 4, iclass 24, count 2 2006.211.07:27:07.95#ibcon#about to read 5, iclass 24, count 2 2006.211.07:27:07.95#ibcon#read 5, iclass 24, count 2 2006.211.07:27:07.95#ibcon#about to read 6, iclass 24, count 2 2006.211.07:27:07.95#ibcon#read 6, iclass 24, count 2 2006.211.07:27:07.95#ibcon#end of sib2, iclass 24, count 2 2006.211.07:27:07.95#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:27:07.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:27:07.95#ibcon#[27=AT03-03\r\n] 2006.211.07:27:07.95#ibcon#*before write, iclass 24, count 2 2006.211.07:27:07.95#ibcon#enter sib2, iclass 24, count 2 2006.211.07:27:07.95#ibcon#flushed, iclass 24, count 2 2006.211.07:27:07.95#ibcon#about to write, iclass 24, count 2 2006.211.07:27:07.95#ibcon#wrote, iclass 24, count 2 2006.211.07:27:07.95#ibcon#about to read 3, iclass 24, count 2 2006.211.07:27:07.98#ibcon#read 3, iclass 24, count 2 2006.211.07:27:07.98#ibcon#about to read 4, iclass 24, count 2 2006.211.07:27:07.98#ibcon#read 4, iclass 24, count 2 2006.211.07:27:07.98#ibcon#about to read 5, iclass 24, count 2 2006.211.07:27:07.98#ibcon#read 5, iclass 24, count 2 2006.211.07:27:07.98#ibcon#about to read 6, iclass 24, count 2 2006.211.07:27:07.98#ibcon#read 6, iclass 24, count 2 2006.211.07:27:07.98#ibcon#end of sib2, iclass 24, count 2 2006.211.07:27:07.98#ibcon#*after write, iclass 24, count 2 2006.211.07:27:07.98#ibcon#*before return 0, iclass 24, count 2 2006.211.07:27:07.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:07.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:27:07.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:27:07.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:07.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:08.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:08.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:08.10#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:27:08.10#ibcon#first serial, iclass 24, count 0 2006.211.07:27:08.10#ibcon#enter sib2, iclass 24, count 0 2006.211.07:27:08.10#ibcon#flushed, iclass 24, count 0 2006.211.07:27:08.10#ibcon#about to write, iclass 24, count 0 2006.211.07:27:08.10#ibcon#wrote, iclass 24, count 0 2006.211.07:27:08.10#ibcon#about to read 3, iclass 24, count 0 2006.211.07:27:08.12#ibcon#read 3, iclass 24, count 0 2006.211.07:27:08.12#ibcon#about to read 4, iclass 24, count 0 2006.211.07:27:08.12#ibcon#read 4, iclass 24, count 0 2006.211.07:27:08.12#ibcon#about to read 5, iclass 24, count 0 2006.211.07:27:08.12#ibcon#read 5, iclass 24, count 0 2006.211.07:27:08.12#ibcon#about to read 6, iclass 24, count 0 2006.211.07:27:08.12#ibcon#read 6, iclass 24, count 0 2006.211.07:27:08.12#ibcon#end of sib2, iclass 24, count 0 2006.211.07:27:08.12#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:27:08.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:27:08.12#ibcon#[27=USB\r\n] 2006.211.07:27:08.12#ibcon#*before write, iclass 24, count 0 2006.211.07:27:08.12#ibcon#enter sib2, iclass 24, count 0 2006.211.07:27:08.12#ibcon#flushed, iclass 24, count 0 2006.211.07:27:08.12#ibcon#about to write, iclass 24, count 0 2006.211.07:27:08.12#ibcon#wrote, iclass 24, count 0 2006.211.07:27:08.12#ibcon#about to read 3, iclass 24, count 0 2006.211.07:27:08.15#ibcon#read 3, iclass 24, count 0 2006.211.07:27:08.15#ibcon#about to read 4, iclass 24, count 0 2006.211.07:27:08.15#ibcon#read 4, iclass 24, count 0 2006.211.07:27:08.15#ibcon#about to read 5, iclass 24, count 0 2006.211.07:27:08.15#ibcon#read 5, iclass 24, count 0 2006.211.07:27:08.15#ibcon#about to read 6, iclass 24, count 0 2006.211.07:27:08.15#ibcon#read 6, iclass 24, count 0 2006.211.07:27:08.15#ibcon#end of sib2, iclass 24, count 0 2006.211.07:27:08.15#ibcon#*after write, iclass 24, count 0 2006.211.07:27:08.15#ibcon#*before return 0, iclass 24, count 0 2006.211.07:27:08.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:08.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:27:08.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:27:08.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:27:08.15$vc4f8/vblo=4,712.99 2006.211.07:27:08.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:27:08.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:27:08.16#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:08.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:08.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:08.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:08.16#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:27:08.16#ibcon#first serial, iclass 26, count 0 2006.211.07:27:08.16#ibcon#enter sib2, iclass 26, count 0 2006.211.07:27:08.16#ibcon#flushed, iclass 26, count 0 2006.211.07:27:08.16#ibcon#about to write, iclass 26, count 0 2006.211.07:27:08.16#ibcon#wrote, iclass 26, count 0 2006.211.07:27:08.16#ibcon#about to read 3, iclass 26, count 0 2006.211.07:27:08.17#ibcon#read 3, iclass 26, count 0 2006.211.07:27:08.17#ibcon#about to read 4, iclass 26, count 0 2006.211.07:27:08.17#ibcon#read 4, iclass 26, count 0 2006.211.07:27:08.17#ibcon#about to read 5, iclass 26, count 0 2006.211.07:27:08.17#ibcon#read 5, iclass 26, count 0 2006.211.07:27:08.17#ibcon#about to read 6, iclass 26, count 0 2006.211.07:27:08.17#ibcon#read 6, iclass 26, count 0 2006.211.07:27:08.17#ibcon#end of sib2, iclass 26, count 0 2006.211.07:27:08.17#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:27:08.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:27:08.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:27:08.17#ibcon#*before write, iclass 26, count 0 2006.211.07:27:08.17#ibcon#enter sib2, iclass 26, count 0 2006.211.07:27:08.17#ibcon#flushed, iclass 26, count 0 2006.211.07:27:08.17#ibcon#about to write, iclass 26, count 0 2006.211.07:27:08.17#ibcon#wrote, iclass 26, count 0 2006.211.07:27:08.17#ibcon#about to read 3, iclass 26, count 0 2006.211.07:27:08.21#ibcon#read 3, iclass 26, count 0 2006.211.07:27:08.21#ibcon#about to read 4, iclass 26, count 0 2006.211.07:27:08.21#ibcon#read 4, iclass 26, count 0 2006.211.07:27:08.21#ibcon#about to read 5, iclass 26, count 0 2006.211.07:27:08.21#ibcon#read 5, iclass 26, count 0 2006.211.07:27:08.21#ibcon#about to read 6, iclass 26, count 0 2006.211.07:27:08.21#ibcon#read 6, iclass 26, count 0 2006.211.07:27:08.21#ibcon#end of sib2, iclass 26, count 0 2006.211.07:27:08.21#ibcon#*after write, iclass 26, count 0 2006.211.07:27:08.21#ibcon#*before return 0, iclass 26, count 0 2006.211.07:27:08.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:08.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:27:08.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:27:08.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:27:08.22$vc4f8/vb=4,3 2006.211.07:27:08.22#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.07:27:08.22#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.07:27:08.22#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:08.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:08.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:08.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:08.26#ibcon#enter wrdev, iclass 28, count 2 2006.211.07:27:08.26#ibcon#first serial, iclass 28, count 2 2006.211.07:27:08.26#ibcon#enter sib2, iclass 28, count 2 2006.211.07:27:08.26#ibcon#flushed, iclass 28, count 2 2006.211.07:27:08.26#ibcon#about to write, iclass 28, count 2 2006.211.07:27:08.26#ibcon#wrote, iclass 28, count 2 2006.211.07:27:08.26#ibcon#about to read 3, iclass 28, count 2 2006.211.07:27:08.28#ibcon#read 3, iclass 28, count 2 2006.211.07:27:08.28#ibcon#about to read 4, iclass 28, count 2 2006.211.07:27:08.28#ibcon#read 4, iclass 28, count 2 2006.211.07:27:08.28#ibcon#about to read 5, iclass 28, count 2 2006.211.07:27:08.28#ibcon#read 5, iclass 28, count 2 2006.211.07:27:08.28#ibcon#about to read 6, iclass 28, count 2 2006.211.07:27:08.28#ibcon#read 6, iclass 28, count 2 2006.211.07:27:08.28#ibcon#end of sib2, iclass 28, count 2 2006.211.07:27:08.28#ibcon#*mode == 0, iclass 28, count 2 2006.211.07:27:08.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.07:27:08.28#ibcon#[27=AT04-03\r\n] 2006.211.07:27:08.28#ibcon#*before write, iclass 28, count 2 2006.211.07:27:08.28#ibcon#enter sib2, iclass 28, count 2 2006.211.07:27:08.28#ibcon#flushed, iclass 28, count 2 2006.211.07:27:08.28#ibcon#about to write, iclass 28, count 2 2006.211.07:27:08.28#ibcon#wrote, iclass 28, count 2 2006.211.07:27:08.28#ibcon#about to read 3, iclass 28, count 2 2006.211.07:27:08.31#ibcon#read 3, iclass 28, count 2 2006.211.07:27:08.31#ibcon#about to read 4, iclass 28, count 2 2006.211.07:27:08.31#ibcon#read 4, iclass 28, count 2 2006.211.07:27:08.31#ibcon#about to read 5, iclass 28, count 2 2006.211.07:27:08.31#ibcon#read 5, iclass 28, count 2 2006.211.07:27:08.31#ibcon#about to read 6, iclass 28, count 2 2006.211.07:27:08.31#ibcon#read 6, iclass 28, count 2 2006.211.07:27:08.31#ibcon#end of sib2, iclass 28, count 2 2006.211.07:27:08.31#ibcon#*after write, iclass 28, count 2 2006.211.07:27:08.31#ibcon#*before return 0, iclass 28, count 2 2006.211.07:27:08.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:08.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:27:08.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.07:27:08.31#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:08.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:08.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:08.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:08.43#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:27:08.43#ibcon#first serial, iclass 28, count 0 2006.211.07:27:08.43#ibcon#enter sib2, iclass 28, count 0 2006.211.07:27:08.43#ibcon#flushed, iclass 28, count 0 2006.211.07:27:08.43#ibcon#about to write, iclass 28, count 0 2006.211.07:27:08.43#ibcon#wrote, iclass 28, count 0 2006.211.07:27:08.43#ibcon#about to read 3, iclass 28, count 0 2006.211.07:27:08.45#ibcon#read 3, iclass 28, count 0 2006.211.07:27:08.45#ibcon#about to read 4, iclass 28, count 0 2006.211.07:27:08.45#ibcon#read 4, iclass 28, count 0 2006.211.07:27:08.45#ibcon#about to read 5, iclass 28, count 0 2006.211.07:27:08.45#ibcon#read 5, iclass 28, count 0 2006.211.07:27:08.45#ibcon#about to read 6, iclass 28, count 0 2006.211.07:27:08.45#ibcon#read 6, iclass 28, count 0 2006.211.07:27:08.45#ibcon#end of sib2, iclass 28, count 0 2006.211.07:27:08.45#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:27:08.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:27:08.45#ibcon#[27=USB\r\n] 2006.211.07:27:08.45#ibcon#*before write, iclass 28, count 0 2006.211.07:27:08.45#ibcon#enter sib2, iclass 28, count 0 2006.211.07:27:08.45#ibcon#flushed, iclass 28, count 0 2006.211.07:27:08.45#ibcon#about to write, iclass 28, count 0 2006.211.07:27:08.45#ibcon#wrote, iclass 28, count 0 2006.211.07:27:08.45#ibcon#about to read 3, iclass 28, count 0 2006.211.07:27:08.48#ibcon#read 3, iclass 28, count 0 2006.211.07:27:08.48#ibcon#about to read 4, iclass 28, count 0 2006.211.07:27:08.48#ibcon#read 4, iclass 28, count 0 2006.211.07:27:08.48#ibcon#about to read 5, iclass 28, count 0 2006.211.07:27:08.48#ibcon#read 5, iclass 28, count 0 2006.211.07:27:08.48#ibcon#about to read 6, iclass 28, count 0 2006.211.07:27:08.48#ibcon#read 6, iclass 28, count 0 2006.211.07:27:08.48#ibcon#end of sib2, iclass 28, count 0 2006.211.07:27:08.48#ibcon#*after write, iclass 28, count 0 2006.211.07:27:08.48#ibcon#*before return 0, iclass 28, count 0 2006.211.07:27:08.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:08.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:27:08.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:27:08.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:27:08.49$vc4f8/vblo=5,744.99 2006.211.07:27:08.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.07:27:08.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.07:27:08.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:08.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:08.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:08.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:08.49#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:27:08.49#ibcon#first serial, iclass 30, count 0 2006.211.07:27:08.49#ibcon#enter sib2, iclass 30, count 0 2006.211.07:27:08.49#ibcon#flushed, iclass 30, count 0 2006.211.07:27:08.49#ibcon#about to write, iclass 30, count 0 2006.211.07:27:08.49#ibcon#wrote, iclass 30, count 0 2006.211.07:27:08.49#ibcon#about to read 3, iclass 30, count 0 2006.211.07:27:08.50#ibcon#read 3, iclass 30, count 0 2006.211.07:27:08.50#ibcon#about to read 4, iclass 30, count 0 2006.211.07:27:08.50#ibcon#read 4, iclass 30, count 0 2006.211.07:27:08.50#ibcon#about to read 5, iclass 30, count 0 2006.211.07:27:08.50#ibcon#read 5, iclass 30, count 0 2006.211.07:27:08.50#ibcon#about to read 6, iclass 30, count 0 2006.211.07:27:08.50#ibcon#read 6, iclass 30, count 0 2006.211.07:27:08.50#ibcon#end of sib2, iclass 30, count 0 2006.211.07:27:08.50#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:27:08.50#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:27:08.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:27:08.50#ibcon#*before write, iclass 30, count 0 2006.211.07:27:08.50#ibcon#enter sib2, iclass 30, count 0 2006.211.07:27:08.50#ibcon#flushed, iclass 30, count 0 2006.211.07:27:08.50#ibcon#about to write, iclass 30, count 0 2006.211.07:27:08.50#ibcon#wrote, iclass 30, count 0 2006.211.07:27:08.50#ibcon#about to read 3, iclass 30, count 0 2006.211.07:27:08.54#ibcon#read 3, iclass 30, count 0 2006.211.07:27:08.54#ibcon#about to read 4, iclass 30, count 0 2006.211.07:27:08.54#ibcon#read 4, iclass 30, count 0 2006.211.07:27:08.54#ibcon#about to read 5, iclass 30, count 0 2006.211.07:27:08.54#ibcon#read 5, iclass 30, count 0 2006.211.07:27:08.54#ibcon#about to read 6, iclass 30, count 0 2006.211.07:27:08.54#ibcon#read 6, iclass 30, count 0 2006.211.07:27:08.54#ibcon#end of sib2, iclass 30, count 0 2006.211.07:27:08.54#ibcon#*after write, iclass 30, count 0 2006.211.07:27:08.54#ibcon#*before return 0, iclass 30, count 0 2006.211.07:27:08.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:08.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:27:08.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:27:08.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:27:08.54$vc4f8/vb=5,3 2006.211.07:27:08.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.07:27:08.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.07:27:08.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:08.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:08.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:08.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:08.59#ibcon#enter wrdev, iclass 32, count 2 2006.211.07:27:08.59#ibcon#first serial, iclass 32, count 2 2006.211.07:27:08.59#ibcon#enter sib2, iclass 32, count 2 2006.211.07:27:08.59#ibcon#flushed, iclass 32, count 2 2006.211.07:27:08.59#ibcon#about to write, iclass 32, count 2 2006.211.07:27:08.59#ibcon#wrote, iclass 32, count 2 2006.211.07:27:08.59#ibcon#about to read 3, iclass 32, count 2 2006.211.07:27:08.61#ibcon#read 3, iclass 32, count 2 2006.211.07:27:08.61#ibcon#about to read 4, iclass 32, count 2 2006.211.07:27:08.61#ibcon#read 4, iclass 32, count 2 2006.211.07:27:08.61#ibcon#about to read 5, iclass 32, count 2 2006.211.07:27:08.61#ibcon#read 5, iclass 32, count 2 2006.211.07:27:08.61#ibcon#about to read 6, iclass 32, count 2 2006.211.07:27:08.61#ibcon#read 6, iclass 32, count 2 2006.211.07:27:08.61#ibcon#end of sib2, iclass 32, count 2 2006.211.07:27:08.61#ibcon#*mode == 0, iclass 32, count 2 2006.211.07:27:08.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.07:27:08.61#ibcon#[27=AT05-03\r\n] 2006.211.07:27:08.61#ibcon#*before write, iclass 32, count 2 2006.211.07:27:08.61#ibcon#enter sib2, iclass 32, count 2 2006.211.07:27:08.61#ibcon#flushed, iclass 32, count 2 2006.211.07:27:08.61#ibcon#about to write, iclass 32, count 2 2006.211.07:27:08.61#ibcon#wrote, iclass 32, count 2 2006.211.07:27:08.61#ibcon#about to read 3, iclass 32, count 2 2006.211.07:27:08.64#ibcon#read 3, iclass 32, count 2 2006.211.07:27:08.64#ibcon#about to read 4, iclass 32, count 2 2006.211.07:27:08.64#ibcon#read 4, iclass 32, count 2 2006.211.07:27:08.64#ibcon#about to read 5, iclass 32, count 2 2006.211.07:27:08.64#ibcon#read 5, iclass 32, count 2 2006.211.07:27:08.64#ibcon#about to read 6, iclass 32, count 2 2006.211.07:27:08.64#ibcon#read 6, iclass 32, count 2 2006.211.07:27:08.64#ibcon#end of sib2, iclass 32, count 2 2006.211.07:27:08.64#ibcon#*after write, iclass 32, count 2 2006.211.07:27:08.64#ibcon#*before return 0, iclass 32, count 2 2006.211.07:27:08.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:08.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:27:08.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.07:27:08.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:08.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:08.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:08.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:08.76#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:27:08.76#ibcon#first serial, iclass 32, count 0 2006.211.07:27:08.76#ibcon#enter sib2, iclass 32, count 0 2006.211.07:27:08.76#ibcon#flushed, iclass 32, count 0 2006.211.07:27:08.76#ibcon#about to write, iclass 32, count 0 2006.211.07:27:08.76#ibcon#wrote, iclass 32, count 0 2006.211.07:27:08.76#ibcon#about to read 3, iclass 32, count 0 2006.211.07:27:08.78#ibcon#read 3, iclass 32, count 0 2006.211.07:27:08.78#ibcon#about to read 4, iclass 32, count 0 2006.211.07:27:08.78#ibcon#read 4, iclass 32, count 0 2006.211.07:27:08.78#ibcon#about to read 5, iclass 32, count 0 2006.211.07:27:08.78#ibcon#read 5, iclass 32, count 0 2006.211.07:27:08.78#ibcon#about to read 6, iclass 32, count 0 2006.211.07:27:08.78#ibcon#read 6, iclass 32, count 0 2006.211.07:27:08.78#ibcon#end of sib2, iclass 32, count 0 2006.211.07:27:08.78#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:27:08.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:27:08.78#ibcon#[27=USB\r\n] 2006.211.07:27:08.78#ibcon#*before write, iclass 32, count 0 2006.211.07:27:08.78#ibcon#enter sib2, iclass 32, count 0 2006.211.07:27:08.78#ibcon#flushed, iclass 32, count 0 2006.211.07:27:08.78#ibcon#about to write, iclass 32, count 0 2006.211.07:27:08.78#ibcon#wrote, iclass 32, count 0 2006.211.07:27:08.78#ibcon#about to read 3, iclass 32, count 0 2006.211.07:27:08.81#ibcon#read 3, iclass 32, count 0 2006.211.07:27:08.81#ibcon#about to read 4, iclass 32, count 0 2006.211.07:27:08.81#ibcon#read 4, iclass 32, count 0 2006.211.07:27:08.81#ibcon#about to read 5, iclass 32, count 0 2006.211.07:27:08.81#ibcon#read 5, iclass 32, count 0 2006.211.07:27:08.81#ibcon#about to read 6, iclass 32, count 0 2006.211.07:27:08.81#ibcon#read 6, iclass 32, count 0 2006.211.07:27:08.81#ibcon#end of sib2, iclass 32, count 0 2006.211.07:27:08.81#ibcon#*after write, iclass 32, count 0 2006.211.07:27:08.81#ibcon#*before return 0, iclass 32, count 0 2006.211.07:27:08.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:08.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:27:08.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:27:08.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:27:08.81$vc4f8/vblo=6,752.99 2006.211.07:27:08.82#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.07:27:08.82#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.07:27:08.82#ibcon#ireg 17 cls_cnt 0 2006.211.07:27:08.82#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:08.82#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:08.82#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:08.82#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:27:08.82#ibcon#first serial, iclass 34, count 0 2006.211.07:27:08.82#ibcon#enter sib2, iclass 34, count 0 2006.211.07:27:08.82#ibcon#flushed, iclass 34, count 0 2006.211.07:27:08.82#ibcon#about to write, iclass 34, count 0 2006.211.07:27:08.82#ibcon#wrote, iclass 34, count 0 2006.211.07:27:08.82#ibcon#about to read 3, iclass 34, count 0 2006.211.07:27:08.83#ibcon#read 3, iclass 34, count 0 2006.211.07:27:08.83#ibcon#about to read 4, iclass 34, count 0 2006.211.07:27:08.83#ibcon#read 4, iclass 34, count 0 2006.211.07:27:08.83#ibcon#about to read 5, iclass 34, count 0 2006.211.07:27:08.83#ibcon#read 5, iclass 34, count 0 2006.211.07:27:08.83#ibcon#about to read 6, iclass 34, count 0 2006.211.07:27:08.83#ibcon#read 6, iclass 34, count 0 2006.211.07:27:08.83#ibcon#end of sib2, iclass 34, count 0 2006.211.07:27:08.83#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:27:08.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:27:08.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:27:08.83#ibcon#*before write, iclass 34, count 0 2006.211.07:27:08.83#ibcon#enter sib2, iclass 34, count 0 2006.211.07:27:08.83#ibcon#flushed, iclass 34, count 0 2006.211.07:27:08.83#ibcon#about to write, iclass 34, count 0 2006.211.07:27:08.83#ibcon#wrote, iclass 34, count 0 2006.211.07:27:08.83#ibcon#about to read 3, iclass 34, count 0 2006.211.07:27:08.87#ibcon#read 3, iclass 34, count 0 2006.211.07:27:08.87#ibcon#about to read 4, iclass 34, count 0 2006.211.07:27:08.87#ibcon#read 4, iclass 34, count 0 2006.211.07:27:08.87#ibcon#about to read 5, iclass 34, count 0 2006.211.07:27:08.87#ibcon#read 5, iclass 34, count 0 2006.211.07:27:08.87#ibcon#about to read 6, iclass 34, count 0 2006.211.07:27:08.87#ibcon#read 6, iclass 34, count 0 2006.211.07:27:08.87#ibcon#end of sib2, iclass 34, count 0 2006.211.07:27:08.87#ibcon#*after write, iclass 34, count 0 2006.211.07:27:08.87#ibcon#*before return 0, iclass 34, count 0 2006.211.07:27:08.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:08.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:27:08.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:27:08.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:27:08.88$vc4f8/vb=6,3 2006.211.07:27:08.88#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.07:27:08.88#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.07:27:08.88#ibcon#ireg 11 cls_cnt 2 2006.211.07:27:08.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:08.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:08.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:08.92#ibcon#enter wrdev, iclass 36, count 2 2006.211.07:27:08.92#ibcon#first serial, iclass 36, count 2 2006.211.07:27:08.92#ibcon#enter sib2, iclass 36, count 2 2006.211.07:27:08.92#ibcon#flushed, iclass 36, count 2 2006.211.07:27:08.92#ibcon#about to write, iclass 36, count 2 2006.211.07:27:08.92#ibcon#wrote, iclass 36, count 2 2006.211.07:27:08.92#ibcon#about to read 3, iclass 36, count 2 2006.211.07:27:08.94#ibcon#read 3, iclass 36, count 2 2006.211.07:27:08.94#ibcon#about to read 4, iclass 36, count 2 2006.211.07:27:08.94#ibcon#read 4, iclass 36, count 2 2006.211.07:27:08.94#ibcon#about to read 5, iclass 36, count 2 2006.211.07:27:08.94#ibcon#read 5, iclass 36, count 2 2006.211.07:27:08.94#ibcon#about to read 6, iclass 36, count 2 2006.211.07:27:08.94#ibcon#read 6, iclass 36, count 2 2006.211.07:27:08.94#ibcon#end of sib2, iclass 36, count 2 2006.211.07:27:08.94#ibcon#*mode == 0, iclass 36, count 2 2006.211.07:27:08.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.07:27:08.94#ibcon#[27=AT06-03\r\n] 2006.211.07:27:08.94#ibcon#*before write, iclass 36, count 2 2006.211.07:27:08.94#ibcon#enter sib2, iclass 36, count 2 2006.211.07:27:08.94#ibcon#flushed, iclass 36, count 2 2006.211.07:27:08.94#ibcon#about to write, iclass 36, count 2 2006.211.07:27:08.94#ibcon#wrote, iclass 36, count 2 2006.211.07:27:08.94#ibcon#about to read 3, iclass 36, count 2 2006.211.07:27:08.97#ibcon#read 3, iclass 36, count 2 2006.211.07:27:08.97#ibcon#about to read 4, iclass 36, count 2 2006.211.07:27:08.97#ibcon#read 4, iclass 36, count 2 2006.211.07:27:08.97#ibcon#about to read 5, iclass 36, count 2 2006.211.07:27:08.97#ibcon#read 5, iclass 36, count 2 2006.211.07:27:08.97#ibcon#about to read 6, iclass 36, count 2 2006.211.07:27:08.97#ibcon#read 6, iclass 36, count 2 2006.211.07:27:08.97#ibcon#end of sib2, iclass 36, count 2 2006.211.07:27:08.97#ibcon#*after write, iclass 36, count 2 2006.211.07:27:08.97#ibcon#*before return 0, iclass 36, count 2 2006.211.07:27:08.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:08.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:27:08.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.07:27:08.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:27:08.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:09.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:09.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:09.09#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:27:09.09#ibcon#first serial, iclass 36, count 0 2006.211.07:27:09.09#ibcon#enter sib2, iclass 36, count 0 2006.211.07:27:09.09#ibcon#flushed, iclass 36, count 0 2006.211.07:27:09.09#ibcon#about to write, iclass 36, count 0 2006.211.07:27:09.09#ibcon#wrote, iclass 36, count 0 2006.211.07:27:09.09#ibcon#about to read 3, iclass 36, count 0 2006.211.07:27:09.11#ibcon#read 3, iclass 36, count 0 2006.211.07:27:09.11#ibcon#about to read 4, iclass 36, count 0 2006.211.07:27:09.11#ibcon#read 4, iclass 36, count 0 2006.211.07:27:09.11#ibcon#about to read 5, iclass 36, count 0 2006.211.07:27:09.11#ibcon#read 5, iclass 36, count 0 2006.211.07:27:09.11#ibcon#about to read 6, iclass 36, count 0 2006.211.07:27:09.11#ibcon#read 6, iclass 36, count 0 2006.211.07:27:09.11#ibcon#end of sib2, iclass 36, count 0 2006.211.07:27:09.11#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:27:09.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:27:09.11#ibcon#[27=USB\r\n] 2006.211.07:27:09.11#ibcon#*before write, iclass 36, count 0 2006.211.07:27:09.11#ibcon#enter sib2, iclass 36, count 0 2006.211.07:27:09.11#ibcon#flushed, iclass 36, count 0 2006.211.07:27:09.11#ibcon#about to write, iclass 36, count 0 2006.211.07:27:09.11#ibcon#wrote, iclass 36, count 0 2006.211.07:27:09.11#ibcon#about to read 3, iclass 36, count 0 2006.211.07:27:09.15#ibcon#read 3, iclass 36, count 0 2006.211.07:27:09.15#ibcon#about to read 4, iclass 36, count 0 2006.211.07:27:09.15#ibcon#read 4, iclass 36, count 0 2006.211.07:27:09.15#ibcon#about to read 5, iclass 36, count 0 2006.211.07:27:09.15#ibcon#read 5, iclass 36, count 0 2006.211.07:27:09.15#ibcon#about to read 6, iclass 36, count 0 2006.211.07:27:09.15#ibcon#read 6, iclass 36, count 0 2006.211.07:27:09.15#ibcon#end of sib2, iclass 36, count 0 2006.211.07:27:09.15#ibcon#*after write, iclass 36, count 0 2006.211.07:27:09.15#ibcon#*before return 0, iclass 36, count 0 2006.211.07:27:09.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:09.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:27:09.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:27:09.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:27:09.15$vc4f8/vabw=wide 2006.211.07:27:09.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.07:27:09.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.07:27:09.15#ibcon#ireg 8 cls_cnt 0 2006.211.07:27:09.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:09.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:09.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:09.15#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:27:09.15#ibcon#first serial, iclass 38, count 0 2006.211.07:27:09.15#ibcon#enter sib2, iclass 38, count 0 2006.211.07:27:09.15#ibcon#flushed, iclass 38, count 0 2006.211.07:27:09.15#ibcon#about to write, iclass 38, count 0 2006.211.07:27:09.15#ibcon#wrote, iclass 38, count 0 2006.211.07:27:09.15#ibcon#about to read 3, iclass 38, count 0 2006.211.07:27:09.16#ibcon#read 3, iclass 38, count 0 2006.211.07:27:09.16#ibcon#about to read 4, iclass 38, count 0 2006.211.07:27:09.16#ibcon#read 4, iclass 38, count 0 2006.211.07:27:09.16#ibcon#about to read 5, iclass 38, count 0 2006.211.07:27:09.16#ibcon#read 5, iclass 38, count 0 2006.211.07:27:09.16#ibcon#about to read 6, iclass 38, count 0 2006.211.07:27:09.16#ibcon#read 6, iclass 38, count 0 2006.211.07:27:09.16#ibcon#end of sib2, iclass 38, count 0 2006.211.07:27:09.16#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:27:09.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:27:09.16#ibcon#[25=BW32\r\n] 2006.211.07:27:09.16#ibcon#*before write, iclass 38, count 0 2006.211.07:27:09.16#ibcon#enter sib2, iclass 38, count 0 2006.211.07:27:09.16#ibcon#flushed, iclass 38, count 0 2006.211.07:27:09.16#ibcon#about to write, iclass 38, count 0 2006.211.07:27:09.16#ibcon#wrote, iclass 38, count 0 2006.211.07:27:09.16#ibcon#about to read 3, iclass 38, count 0 2006.211.07:27:09.19#ibcon#read 3, iclass 38, count 0 2006.211.07:27:09.19#ibcon#about to read 4, iclass 38, count 0 2006.211.07:27:09.19#ibcon#read 4, iclass 38, count 0 2006.211.07:27:09.19#ibcon#about to read 5, iclass 38, count 0 2006.211.07:27:09.19#ibcon#read 5, iclass 38, count 0 2006.211.07:27:09.19#ibcon#about to read 6, iclass 38, count 0 2006.211.07:27:09.19#ibcon#read 6, iclass 38, count 0 2006.211.07:27:09.19#ibcon#end of sib2, iclass 38, count 0 2006.211.07:27:09.19#ibcon#*after write, iclass 38, count 0 2006.211.07:27:09.19#ibcon#*before return 0, iclass 38, count 0 2006.211.07:27:09.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:09.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:27:09.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:27:09.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:27:09.20$vc4f8/vbbw=wide 2006.211.07:27:09.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:27:09.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:27:09.20#ibcon#ireg 8 cls_cnt 0 2006.211.07:27:09.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:27:09.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:27:09.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:27:09.26#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:27:09.26#ibcon#first serial, iclass 40, count 0 2006.211.07:27:09.26#ibcon#enter sib2, iclass 40, count 0 2006.211.07:27:09.26#ibcon#flushed, iclass 40, count 0 2006.211.07:27:09.26#ibcon#about to write, iclass 40, count 0 2006.211.07:27:09.26#ibcon#wrote, iclass 40, count 0 2006.211.07:27:09.26#ibcon#about to read 3, iclass 40, count 0 2006.211.07:27:09.28#ibcon#read 3, iclass 40, count 0 2006.211.07:27:09.28#ibcon#about to read 4, iclass 40, count 0 2006.211.07:27:09.28#ibcon#read 4, iclass 40, count 0 2006.211.07:27:09.28#ibcon#about to read 5, iclass 40, count 0 2006.211.07:27:09.28#ibcon#read 5, iclass 40, count 0 2006.211.07:27:09.28#ibcon#about to read 6, iclass 40, count 0 2006.211.07:27:09.28#ibcon#read 6, iclass 40, count 0 2006.211.07:27:09.28#ibcon#end of sib2, iclass 40, count 0 2006.211.07:27:09.28#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:27:09.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:27:09.28#ibcon#[27=BW32\r\n] 2006.211.07:27:09.28#ibcon#*before write, iclass 40, count 0 2006.211.07:27:09.28#ibcon#enter sib2, iclass 40, count 0 2006.211.07:27:09.28#ibcon#flushed, iclass 40, count 0 2006.211.07:27:09.28#ibcon#about to write, iclass 40, count 0 2006.211.07:27:09.28#ibcon#wrote, iclass 40, count 0 2006.211.07:27:09.28#ibcon#about to read 3, iclass 40, count 0 2006.211.07:27:09.31#ibcon#read 3, iclass 40, count 0 2006.211.07:27:09.31#ibcon#about to read 4, iclass 40, count 0 2006.211.07:27:09.31#ibcon#read 4, iclass 40, count 0 2006.211.07:27:09.31#ibcon#about to read 5, iclass 40, count 0 2006.211.07:27:09.31#ibcon#read 5, iclass 40, count 0 2006.211.07:27:09.31#ibcon#about to read 6, iclass 40, count 0 2006.211.07:27:09.31#ibcon#read 6, iclass 40, count 0 2006.211.07:27:09.31#ibcon#end of sib2, iclass 40, count 0 2006.211.07:27:09.31#ibcon#*after write, iclass 40, count 0 2006.211.07:27:09.31#ibcon#*before return 0, iclass 40, count 0 2006.211.07:27:09.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:27:09.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:27:09.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:27:09.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:27:09.32$4f8m12a/ifd4f 2006.211.07:27:09.32&ifd4f/lo= 2006.211.07:27:09.32&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:27:09.32&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:27:09.32&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:27:09.32&ifd4f/patch= 2006.211.07:27:09.32&ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:27:09.32&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:27:09.32&ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:27:09.32$ifd4f/lo= 2006.211.07:27:09.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:27:09.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:27:09.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:27:09.32$ifd4f/patch= 2006.211.07:27:09.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:27:09.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:27:09.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:27:09.32$4f8m12a/"form=m,16.000,1:2 2006.211.07:27:09.32$4f8m12a/"tpicd 2006.211.07:27:09.32$4f8m12a/echo=off 2006.211.07:27:09.32$4f8m12a/xlog=off 2006.211.07:27:09.32:!2006.211.07:29:50 2006.211.07:27:26.14#trakl#Source acquired 2006.211.07:27:27.14#flagr#flagr/antenna,acquired 2006.211.07:27:51.14#trakl#Off source 2006.211.07:27:51.14?ERROR st -7 Antenna off-source! 2006.211.07:27:51.14#trakl#az 37.844 el 16.781 azerr*cos(el) 0.0177 elerr -0.0041 2006.211.07:27:51.15#flagr#flagr/antenna,off-source 2006.211.07:27:57.14#trakl#Source re-acquired 2006.211.07:27:57.14#flagr#flagr/antenna,re-acquired 2006.211.07:28:27.14#trakl#Off source 2006.211.07:28:27.14?ERROR st -7 Antenna off-source! 2006.211.07:28:27.14#trakl#az 37.903 el 16.855 azerr*cos(el) 0.0180 elerr -0.0084 2006.211.07:28:27.14#flagr#flagr/antenna,off-source 2006.211.07:28:33.14#trakl#Source re-acquired 2006.211.07:28:33.14#flagr#flagr/antenna,re-acquired 2006.211.07:29:46.13#trakl#Off source 2006.211.07:29:46.13?ERROR st -7 Antenna off-source! 2006.211.07:29:46.13#trakl#az 38.034 el 17.019 azerr*cos(el) 0.0224 elerr 0.0141 2006.211.07:29:48.13#flagr#flagr/antenna,off-source 2006.211.07:29:50.01:preob 2006.211.07:29:50.01&preob/onsource 2006.211.07:29:51.13?ERROR an -103 Pointing computer tracking errors are too large. 2006.211.07:29:51.13?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.211.07:29:51.13/onsource/SLEWING 2006.211.07:29:51.13:!2006.211.07:30:00 2006.211.07:29:55.13#trakl#Source re-acquired 2006.211.07:29:56.13#flagr#flagr/antenna,re-acquired 2006.211.07:30:00.00:data_valid=on 2006.211.07:30:00.00:midob 2006.211.07:30:00.00&midob/onsource 2006.211.07:30:00.00&midob/wx 2006.211.07:30:00.00&midob/cable 2006.211.07:30:00.00&midob/va 2006.211.07:30:00.00&midob/valo 2006.211.07:30:00.00&midob/vb 2006.211.07:30:00.00&midob/vblo 2006.211.07:30:00.00&midob/vabw 2006.211.07:30:00.00&midob/vbbw 2006.211.07:30:00.00&midob/"form 2006.211.07:30:00.00&midob/xfe 2006.211.07:30:00.00&midob/ifatt 2006.211.07:30:00.00&midob/clockoff 2006.211.07:30:00.00&midob/sy=logmail 2006.211.07:30:00.00&midob/"sy=run setcl adapt & 2006.211.07:30:00.13/onsource/TRACKING 2006.211.07:30:00.13/wx/24.98,1010.2,76 2006.211.07:30:00.29/cable/+6.4355E-03 2006.211.07:30:01.38/va/01,08,usb,yes,31,33 2006.211.07:30:01.38/va/02,07,usb,yes,31,32 2006.211.07:30:01.38/va/03,06,usb,yes,33,33 2006.211.07:30:01.38/va/04,07,usb,yes,32,34 2006.211.07:30:01.38/va/05,07,usb,yes,35,37 2006.211.07:30:01.38/va/06,06,usb,yes,34,34 2006.211.07:30:01.38/va/07,06,usb,yes,35,34 2006.211.07:30:01.38/va/08,07,usb,yes,33,32 2006.211.07:30:01.61/valo/01,532.99,yes,locked 2006.211.07:30:01.61/valo/02,572.99,yes,locked 2006.211.07:30:01.61/valo/03,672.99,yes,locked 2006.211.07:30:01.61/valo/04,832.99,yes,locked 2006.211.07:30:01.61/valo/05,652.99,yes,locked 2006.211.07:30:01.61/valo/06,772.99,yes,locked 2006.211.07:30:01.61/valo/07,832.99,yes,locked 2006.211.07:30:01.61/valo/08,852.99,yes,locked 2006.211.07:30:02.70/vb/01,04,usb,yes,30,29 2006.211.07:30:02.70/vb/02,04,usb,yes,32,33 2006.211.07:30:02.70/vb/03,03,usb,yes,35,40 2006.211.07:30:02.70/vb/04,03,usb,yes,37,36 2006.211.07:30:02.70/vb/05,03,usb,yes,35,39 2006.211.07:30:02.70/vb/06,03,usb,yes,35,39 2006.211.07:30:02.70/vb/07,04,usb,yes,31,31 2006.211.07:30:02.70/vb/08,03,usb,yes,35,39 2006.211.07:30:02.94/vblo/01,632.99,yes,locked 2006.211.07:30:02.94/vblo/02,640.99,yes,locked 2006.211.07:30:02.94/vblo/03,656.99,yes,locked 2006.211.07:30:02.94/vblo/04,712.99,yes,locked 2006.211.07:30:02.94/vblo/05,744.99,yes,locked 2006.211.07:30:02.94/vblo/06,752.99,yes,locked 2006.211.07:30:02.94/vblo/07,734.99,yes,locked 2006.211.07:30:02.94/vblo/08,744.99,yes,locked 2006.211.07:30:03.09/vabw/8 2006.211.07:30:03.24/vbbw/8 2006.211.07:30:03.39/xfe/off,on,13.0 2006.211.07:30:03.79/ifatt/23,28,28,28 2006.211.07:30:03.79&clockoff/"gps-fmout=1p 2006.211.07:30:03.79&clockoff/fmout-gps=1p 2006.211.07:30:04.07/fmout-gps/S +4.47E-07 2006.211.07:30:04.12:!2006.211.07:31:00 2006.211.07:31:00.01:data_valid=off 2006.211.07:31:00.01:postob 2006.211.07:31:00.01&postob/cable 2006.211.07:31:00.01&postob/wx 2006.211.07:31:00.01&postob/clockoff 2006.211.07:31:00.10/cable/+6.4369E-03 2006.211.07:31:00.10/wx/24.98,1010.2,76 2006.211.07:31:01.07/fmout-gps/S +4.47E-07 2006.211.07:31:01.07:scan_name=211-0733,k06211,60 2006.211.07:31:01.07:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.211.07:31:02.13#flagr#flagr/antenna,new-source 2006.211.07:31:02.13:checkk5 2006.211.07:31:02.13&checkk5/chk_autoobs=1 2006.211.07:31:02.13&checkk5/chk_autoobs=2 2006.211.07:31:02.13&checkk5/chk_autoobs=3 2006.211.07:31:02.13&checkk5/chk_autoobs=4 2006.211.07:31:02.13&checkk5/chk_obsdata=1 2006.211.07:31:02.13&checkk5/chk_obsdata=2 2006.211.07:31:02.13&checkk5/chk_obsdata=3 2006.211.07:31:02.13&checkk5/chk_obsdata=4 2006.211.07:31:02.13&checkk5/k5log=1 2006.211.07:31:02.13&checkk5/k5log=2 2006.211.07:31:02.13&checkk5/k5log=3 2006.211.07:31:02.14&checkk5/k5log=4 2006.211.07:31:02.14&checkk5/obsinfo 2006.211.07:31:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:31:02.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:31:03.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:31:03.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:31:03.84/chk_obsdata//k5ts1/T2110730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:31:04.18/chk_obsdata//k5ts2/T2110730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:31:04.51/chk_obsdata//k5ts3/T2110730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:31:04.84/chk_obsdata//k5ts4/T2110730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:31:05.52/k5log//k5ts1_log_newline 2006.211.07:31:06.24/k5log//k5ts2_log_newline 2006.211.07:31:06.89/k5log//k5ts3_log_newline 2006.211.07:31:07.55/k5log//k5ts4_log_newline 2006.211.07:31:07.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:31:07.58:4f8m12a=1 2006.211.07:31:07.58$4f8m12a/echo=on 2006.211.07:31:07.58$4f8m12a/pcalon 2006.211.07:31:07.58$pcalon/"no phase cal control is implemented here 2006.211.07:31:07.58$4f8m12a/"tpicd=stop 2006.211.07:31:07.58$4f8m12a/vc4f8 2006.211.07:31:07.58$vc4f8/valo=1,532.99 2006.211.07:31:07.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:31:07.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:31:07.59#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:07.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:07.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:07.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:07.59#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:31:07.59#ibcon#first serial, iclass 3, count 0 2006.211.07:31:07.59#ibcon#enter sib2, iclass 3, count 0 2006.211.07:31:07.59#ibcon#flushed, iclass 3, count 0 2006.211.07:31:07.59#ibcon#about to write, iclass 3, count 0 2006.211.07:31:07.59#ibcon#wrote, iclass 3, count 0 2006.211.07:31:07.59#ibcon#about to read 3, iclass 3, count 0 2006.211.07:31:07.60#ibcon#read 3, iclass 3, count 0 2006.211.07:31:07.60#ibcon#about to read 4, iclass 3, count 0 2006.211.07:31:07.60#ibcon#read 4, iclass 3, count 0 2006.211.07:31:07.60#ibcon#about to read 5, iclass 3, count 0 2006.211.07:31:07.60#ibcon#read 5, iclass 3, count 0 2006.211.07:31:07.60#ibcon#about to read 6, iclass 3, count 0 2006.211.07:31:07.60#ibcon#read 6, iclass 3, count 0 2006.211.07:31:07.60#ibcon#end of sib2, iclass 3, count 0 2006.211.07:31:07.60#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:31:07.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:31:07.60#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:31:07.60#ibcon#*before write, iclass 3, count 0 2006.211.07:31:07.60#ibcon#enter sib2, iclass 3, count 0 2006.211.07:31:07.60#ibcon#flushed, iclass 3, count 0 2006.211.07:31:07.60#ibcon#about to write, iclass 3, count 0 2006.211.07:31:07.60#ibcon#wrote, iclass 3, count 0 2006.211.07:31:07.60#ibcon#about to read 3, iclass 3, count 0 2006.211.07:31:07.65#ibcon#read 3, iclass 3, count 0 2006.211.07:31:07.65#ibcon#about to read 4, iclass 3, count 0 2006.211.07:31:07.65#ibcon#read 4, iclass 3, count 0 2006.211.07:31:07.65#ibcon#about to read 5, iclass 3, count 0 2006.211.07:31:07.65#ibcon#read 5, iclass 3, count 0 2006.211.07:31:07.65#ibcon#about to read 6, iclass 3, count 0 2006.211.07:31:07.65#ibcon#read 6, iclass 3, count 0 2006.211.07:31:07.65#ibcon#end of sib2, iclass 3, count 0 2006.211.07:31:07.65#ibcon#*after write, iclass 3, count 0 2006.211.07:31:07.65#ibcon#*before return 0, iclass 3, count 0 2006.211.07:31:07.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:07.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:07.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:31:07.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:31:07.65$vc4f8/va=1,8 2006.211.07:31:07.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:31:07.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:31:07.65#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:07.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:07.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:07.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:07.65#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:31:07.65#ibcon#first serial, iclass 5, count 2 2006.211.07:31:07.65#ibcon#enter sib2, iclass 5, count 2 2006.211.07:31:07.65#ibcon#flushed, iclass 5, count 2 2006.211.07:31:07.65#ibcon#about to write, iclass 5, count 2 2006.211.07:31:07.65#ibcon#wrote, iclass 5, count 2 2006.211.07:31:07.65#ibcon#about to read 3, iclass 5, count 2 2006.211.07:31:07.67#ibcon#read 3, iclass 5, count 2 2006.211.07:31:07.67#ibcon#about to read 4, iclass 5, count 2 2006.211.07:31:07.67#ibcon#read 4, iclass 5, count 2 2006.211.07:31:07.67#ibcon#about to read 5, iclass 5, count 2 2006.211.07:31:07.67#ibcon#read 5, iclass 5, count 2 2006.211.07:31:07.67#ibcon#about to read 6, iclass 5, count 2 2006.211.07:31:07.67#ibcon#read 6, iclass 5, count 2 2006.211.07:31:07.67#ibcon#end of sib2, iclass 5, count 2 2006.211.07:31:07.67#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:31:07.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:31:07.67#ibcon#[25=AT01-08\r\n] 2006.211.07:31:07.67#ibcon#*before write, iclass 5, count 2 2006.211.07:31:07.67#ibcon#enter sib2, iclass 5, count 2 2006.211.07:31:07.67#ibcon#flushed, iclass 5, count 2 2006.211.07:31:07.67#ibcon#about to write, iclass 5, count 2 2006.211.07:31:07.67#ibcon#wrote, iclass 5, count 2 2006.211.07:31:07.67#ibcon#about to read 3, iclass 5, count 2 2006.211.07:31:07.70#ibcon#read 3, iclass 5, count 2 2006.211.07:31:07.70#ibcon#about to read 4, iclass 5, count 2 2006.211.07:31:07.70#ibcon#read 4, iclass 5, count 2 2006.211.07:31:07.70#ibcon#about to read 5, iclass 5, count 2 2006.211.07:31:07.70#ibcon#read 5, iclass 5, count 2 2006.211.07:31:07.70#ibcon#about to read 6, iclass 5, count 2 2006.211.07:31:07.70#ibcon#read 6, iclass 5, count 2 2006.211.07:31:07.70#ibcon#end of sib2, iclass 5, count 2 2006.211.07:31:07.70#ibcon#*after write, iclass 5, count 2 2006.211.07:31:07.70#ibcon#*before return 0, iclass 5, count 2 2006.211.07:31:07.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:07.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:07.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:31:07.70#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:07.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:07.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:07.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:07.82#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:31:07.82#ibcon#first serial, iclass 5, count 0 2006.211.07:31:07.82#ibcon#enter sib2, iclass 5, count 0 2006.211.07:31:07.82#ibcon#flushed, iclass 5, count 0 2006.211.07:31:07.82#ibcon#about to write, iclass 5, count 0 2006.211.07:31:07.82#ibcon#wrote, iclass 5, count 0 2006.211.07:31:07.82#ibcon#about to read 3, iclass 5, count 0 2006.211.07:31:07.84#ibcon#read 3, iclass 5, count 0 2006.211.07:31:07.84#ibcon#about to read 4, iclass 5, count 0 2006.211.07:31:07.84#ibcon#read 4, iclass 5, count 0 2006.211.07:31:07.84#ibcon#about to read 5, iclass 5, count 0 2006.211.07:31:07.84#ibcon#read 5, iclass 5, count 0 2006.211.07:31:07.84#ibcon#about to read 6, iclass 5, count 0 2006.211.07:31:07.84#ibcon#read 6, iclass 5, count 0 2006.211.07:31:07.84#ibcon#end of sib2, iclass 5, count 0 2006.211.07:31:07.84#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:31:07.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:31:07.84#ibcon#[25=USB\r\n] 2006.211.07:31:07.84#ibcon#*before write, iclass 5, count 0 2006.211.07:31:07.84#ibcon#enter sib2, iclass 5, count 0 2006.211.07:31:07.84#ibcon#flushed, iclass 5, count 0 2006.211.07:31:07.84#ibcon#about to write, iclass 5, count 0 2006.211.07:31:07.84#ibcon#wrote, iclass 5, count 0 2006.211.07:31:07.84#ibcon#about to read 3, iclass 5, count 0 2006.211.07:31:07.87#ibcon#read 3, iclass 5, count 0 2006.211.07:31:07.87#ibcon#about to read 4, iclass 5, count 0 2006.211.07:31:07.87#ibcon#read 4, iclass 5, count 0 2006.211.07:31:07.87#ibcon#about to read 5, iclass 5, count 0 2006.211.07:31:07.87#ibcon#read 5, iclass 5, count 0 2006.211.07:31:07.87#ibcon#about to read 6, iclass 5, count 0 2006.211.07:31:07.87#ibcon#read 6, iclass 5, count 0 2006.211.07:31:07.87#ibcon#end of sib2, iclass 5, count 0 2006.211.07:31:07.87#ibcon#*after write, iclass 5, count 0 2006.211.07:31:07.87#ibcon#*before return 0, iclass 5, count 0 2006.211.07:31:07.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:07.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:07.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:31:07.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:31:07.87$vc4f8/valo=2,572.99 2006.211.07:31:07.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:31:07.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:31:07.87#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:07.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:07.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:07.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:07.87#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:31:07.87#ibcon#first serial, iclass 7, count 0 2006.211.07:31:07.87#ibcon#enter sib2, iclass 7, count 0 2006.211.07:31:07.87#ibcon#flushed, iclass 7, count 0 2006.211.07:31:07.87#ibcon#about to write, iclass 7, count 0 2006.211.07:31:07.87#ibcon#wrote, iclass 7, count 0 2006.211.07:31:07.87#ibcon#about to read 3, iclass 7, count 0 2006.211.07:31:07.89#ibcon#read 3, iclass 7, count 0 2006.211.07:31:07.89#ibcon#about to read 4, iclass 7, count 0 2006.211.07:31:07.89#ibcon#read 4, iclass 7, count 0 2006.211.07:31:07.89#ibcon#about to read 5, iclass 7, count 0 2006.211.07:31:07.89#ibcon#read 5, iclass 7, count 0 2006.211.07:31:07.89#ibcon#about to read 6, iclass 7, count 0 2006.211.07:31:07.89#ibcon#read 6, iclass 7, count 0 2006.211.07:31:07.89#ibcon#end of sib2, iclass 7, count 0 2006.211.07:31:07.89#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:31:07.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:31:07.89#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:31:07.89#ibcon#*before write, iclass 7, count 0 2006.211.07:31:07.89#ibcon#enter sib2, iclass 7, count 0 2006.211.07:31:07.89#ibcon#flushed, iclass 7, count 0 2006.211.07:31:07.89#ibcon#about to write, iclass 7, count 0 2006.211.07:31:07.89#ibcon#wrote, iclass 7, count 0 2006.211.07:31:07.89#ibcon#about to read 3, iclass 7, count 0 2006.211.07:31:07.93#ibcon#read 3, iclass 7, count 0 2006.211.07:31:07.93#ibcon#about to read 4, iclass 7, count 0 2006.211.07:31:07.93#ibcon#read 4, iclass 7, count 0 2006.211.07:31:07.93#ibcon#about to read 5, iclass 7, count 0 2006.211.07:31:07.93#ibcon#read 5, iclass 7, count 0 2006.211.07:31:07.93#ibcon#about to read 6, iclass 7, count 0 2006.211.07:31:07.93#ibcon#read 6, iclass 7, count 0 2006.211.07:31:07.93#ibcon#end of sib2, iclass 7, count 0 2006.211.07:31:07.93#ibcon#*after write, iclass 7, count 0 2006.211.07:31:07.93#ibcon#*before return 0, iclass 7, count 0 2006.211.07:31:07.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:07.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:07.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:31:07.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:31:07.93$vc4f8/va=2,7 2006.211.07:31:07.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:31:07.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:31:07.93#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:07.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:07.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:07.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:07.99#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:31:07.99#ibcon#first serial, iclass 11, count 2 2006.211.07:31:07.99#ibcon#enter sib2, iclass 11, count 2 2006.211.07:31:07.99#ibcon#flushed, iclass 11, count 2 2006.211.07:31:07.99#ibcon#about to write, iclass 11, count 2 2006.211.07:31:07.99#ibcon#wrote, iclass 11, count 2 2006.211.07:31:07.99#ibcon#about to read 3, iclass 11, count 2 2006.211.07:31:08.01#ibcon#read 3, iclass 11, count 2 2006.211.07:31:08.01#ibcon#about to read 4, iclass 11, count 2 2006.211.07:31:08.01#ibcon#read 4, iclass 11, count 2 2006.211.07:31:08.01#ibcon#about to read 5, iclass 11, count 2 2006.211.07:31:08.01#ibcon#read 5, iclass 11, count 2 2006.211.07:31:08.01#ibcon#about to read 6, iclass 11, count 2 2006.211.07:31:08.01#ibcon#read 6, iclass 11, count 2 2006.211.07:31:08.01#ibcon#end of sib2, iclass 11, count 2 2006.211.07:31:08.01#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:31:08.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:31:08.01#ibcon#[25=AT02-07\r\n] 2006.211.07:31:08.01#ibcon#*before write, iclass 11, count 2 2006.211.07:31:08.01#ibcon#enter sib2, iclass 11, count 2 2006.211.07:31:08.01#ibcon#flushed, iclass 11, count 2 2006.211.07:31:08.01#ibcon#about to write, iclass 11, count 2 2006.211.07:31:08.01#ibcon#wrote, iclass 11, count 2 2006.211.07:31:08.01#ibcon#about to read 3, iclass 11, count 2 2006.211.07:31:08.04#ibcon#read 3, iclass 11, count 2 2006.211.07:31:08.04#ibcon#about to read 4, iclass 11, count 2 2006.211.07:31:08.04#ibcon#read 4, iclass 11, count 2 2006.211.07:31:08.04#ibcon#about to read 5, iclass 11, count 2 2006.211.07:31:08.04#ibcon#read 5, iclass 11, count 2 2006.211.07:31:08.04#ibcon#about to read 6, iclass 11, count 2 2006.211.07:31:08.04#ibcon#read 6, iclass 11, count 2 2006.211.07:31:08.04#ibcon#end of sib2, iclass 11, count 2 2006.211.07:31:08.04#ibcon#*after write, iclass 11, count 2 2006.211.07:31:08.04#ibcon#*before return 0, iclass 11, count 2 2006.211.07:31:08.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:08.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:08.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:31:08.04#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:08.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:08.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:08.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:08.16#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:31:08.16#ibcon#first serial, iclass 11, count 0 2006.211.07:31:08.16#ibcon#enter sib2, iclass 11, count 0 2006.211.07:31:08.16#ibcon#flushed, iclass 11, count 0 2006.211.07:31:08.16#ibcon#about to write, iclass 11, count 0 2006.211.07:31:08.16#ibcon#wrote, iclass 11, count 0 2006.211.07:31:08.16#ibcon#about to read 3, iclass 11, count 0 2006.211.07:31:08.18#ibcon#read 3, iclass 11, count 0 2006.211.07:31:08.18#ibcon#about to read 4, iclass 11, count 0 2006.211.07:31:08.18#ibcon#read 4, iclass 11, count 0 2006.211.07:31:08.18#ibcon#about to read 5, iclass 11, count 0 2006.211.07:31:08.18#ibcon#read 5, iclass 11, count 0 2006.211.07:31:08.18#ibcon#about to read 6, iclass 11, count 0 2006.211.07:31:08.18#ibcon#read 6, iclass 11, count 0 2006.211.07:31:08.18#ibcon#end of sib2, iclass 11, count 0 2006.211.07:31:08.18#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:31:08.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:31:08.18#ibcon#[25=USB\r\n] 2006.211.07:31:08.18#ibcon#*before write, iclass 11, count 0 2006.211.07:31:08.18#ibcon#enter sib2, iclass 11, count 0 2006.211.07:31:08.18#ibcon#flushed, iclass 11, count 0 2006.211.07:31:08.18#ibcon#about to write, iclass 11, count 0 2006.211.07:31:08.18#ibcon#wrote, iclass 11, count 0 2006.211.07:31:08.18#ibcon#about to read 3, iclass 11, count 0 2006.211.07:31:08.21#ibcon#read 3, iclass 11, count 0 2006.211.07:31:08.21#ibcon#about to read 4, iclass 11, count 0 2006.211.07:31:08.21#ibcon#read 4, iclass 11, count 0 2006.211.07:31:08.21#ibcon#about to read 5, iclass 11, count 0 2006.211.07:31:08.21#ibcon#read 5, iclass 11, count 0 2006.211.07:31:08.21#ibcon#about to read 6, iclass 11, count 0 2006.211.07:31:08.21#ibcon#read 6, iclass 11, count 0 2006.211.07:31:08.21#ibcon#end of sib2, iclass 11, count 0 2006.211.07:31:08.21#ibcon#*after write, iclass 11, count 0 2006.211.07:31:08.21#ibcon#*before return 0, iclass 11, count 0 2006.211.07:31:08.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:08.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:08.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:31:08.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:31:08.21$vc4f8/valo=3,672.99 2006.211.07:31:08.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:31:08.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:31:08.21#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:08.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:08.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:08.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:08.21#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:31:08.21#ibcon#first serial, iclass 13, count 0 2006.211.07:31:08.21#ibcon#enter sib2, iclass 13, count 0 2006.211.07:31:08.21#ibcon#flushed, iclass 13, count 0 2006.211.07:31:08.21#ibcon#about to write, iclass 13, count 0 2006.211.07:31:08.21#ibcon#wrote, iclass 13, count 0 2006.211.07:31:08.21#ibcon#about to read 3, iclass 13, count 0 2006.211.07:31:08.23#ibcon#read 3, iclass 13, count 0 2006.211.07:31:08.23#ibcon#about to read 4, iclass 13, count 0 2006.211.07:31:08.23#ibcon#read 4, iclass 13, count 0 2006.211.07:31:08.23#ibcon#about to read 5, iclass 13, count 0 2006.211.07:31:08.23#ibcon#read 5, iclass 13, count 0 2006.211.07:31:08.23#ibcon#about to read 6, iclass 13, count 0 2006.211.07:31:08.23#ibcon#read 6, iclass 13, count 0 2006.211.07:31:08.23#ibcon#end of sib2, iclass 13, count 0 2006.211.07:31:08.23#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:31:08.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:31:08.23#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:31:08.23#ibcon#*before write, iclass 13, count 0 2006.211.07:31:08.23#ibcon#enter sib2, iclass 13, count 0 2006.211.07:31:08.23#ibcon#flushed, iclass 13, count 0 2006.211.07:31:08.23#ibcon#about to write, iclass 13, count 0 2006.211.07:31:08.23#ibcon#wrote, iclass 13, count 0 2006.211.07:31:08.23#ibcon#about to read 3, iclass 13, count 0 2006.211.07:31:08.27#ibcon#read 3, iclass 13, count 0 2006.211.07:31:08.27#ibcon#about to read 4, iclass 13, count 0 2006.211.07:31:08.27#ibcon#read 4, iclass 13, count 0 2006.211.07:31:08.27#ibcon#about to read 5, iclass 13, count 0 2006.211.07:31:08.27#ibcon#read 5, iclass 13, count 0 2006.211.07:31:08.27#ibcon#about to read 6, iclass 13, count 0 2006.211.07:31:08.27#ibcon#read 6, iclass 13, count 0 2006.211.07:31:08.27#ibcon#end of sib2, iclass 13, count 0 2006.211.07:31:08.27#ibcon#*after write, iclass 13, count 0 2006.211.07:31:08.27#ibcon#*before return 0, iclass 13, count 0 2006.211.07:31:08.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:08.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:08.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:31:08.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:31:08.27$vc4f8/va=3,6 2006.211.07:31:08.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.07:31:08.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.07:31:08.27#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:08.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:08.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:08.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:08.33#ibcon#enter wrdev, iclass 15, count 2 2006.211.07:31:08.33#ibcon#first serial, iclass 15, count 2 2006.211.07:31:08.33#ibcon#enter sib2, iclass 15, count 2 2006.211.07:31:08.33#ibcon#flushed, iclass 15, count 2 2006.211.07:31:08.33#ibcon#about to write, iclass 15, count 2 2006.211.07:31:08.33#ibcon#wrote, iclass 15, count 2 2006.211.07:31:08.33#ibcon#about to read 3, iclass 15, count 2 2006.211.07:31:08.35#ibcon#read 3, iclass 15, count 2 2006.211.07:31:08.35#ibcon#about to read 4, iclass 15, count 2 2006.211.07:31:08.35#ibcon#read 4, iclass 15, count 2 2006.211.07:31:08.35#ibcon#about to read 5, iclass 15, count 2 2006.211.07:31:08.35#ibcon#read 5, iclass 15, count 2 2006.211.07:31:08.35#ibcon#about to read 6, iclass 15, count 2 2006.211.07:31:08.35#ibcon#read 6, iclass 15, count 2 2006.211.07:31:08.35#ibcon#end of sib2, iclass 15, count 2 2006.211.07:31:08.35#ibcon#*mode == 0, iclass 15, count 2 2006.211.07:31:08.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.07:31:08.35#ibcon#[25=AT03-06\r\n] 2006.211.07:31:08.35#ibcon#*before write, iclass 15, count 2 2006.211.07:31:08.35#ibcon#enter sib2, iclass 15, count 2 2006.211.07:31:08.35#ibcon#flushed, iclass 15, count 2 2006.211.07:31:08.35#ibcon#about to write, iclass 15, count 2 2006.211.07:31:08.35#ibcon#wrote, iclass 15, count 2 2006.211.07:31:08.35#ibcon#about to read 3, iclass 15, count 2 2006.211.07:31:08.38#ibcon#read 3, iclass 15, count 2 2006.211.07:31:08.38#ibcon#about to read 4, iclass 15, count 2 2006.211.07:31:08.38#ibcon#read 4, iclass 15, count 2 2006.211.07:31:08.38#ibcon#about to read 5, iclass 15, count 2 2006.211.07:31:08.38#ibcon#read 5, iclass 15, count 2 2006.211.07:31:08.38#ibcon#about to read 6, iclass 15, count 2 2006.211.07:31:08.38#ibcon#read 6, iclass 15, count 2 2006.211.07:31:08.38#ibcon#end of sib2, iclass 15, count 2 2006.211.07:31:08.38#ibcon#*after write, iclass 15, count 2 2006.211.07:31:08.38#ibcon#*before return 0, iclass 15, count 2 2006.211.07:31:08.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:08.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:08.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.07:31:08.38#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:08.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:08.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:08.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:08.50#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:31:08.50#ibcon#first serial, iclass 15, count 0 2006.211.07:31:08.50#ibcon#enter sib2, iclass 15, count 0 2006.211.07:31:08.50#ibcon#flushed, iclass 15, count 0 2006.211.07:31:08.50#ibcon#about to write, iclass 15, count 0 2006.211.07:31:08.50#ibcon#wrote, iclass 15, count 0 2006.211.07:31:08.50#ibcon#about to read 3, iclass 15, count 0 2006.211.07:31:08.52#ibcon#read 3, iclass 15, count 0 2006.211.07:31:08.52#ibcon#about to read 4, iclass 15, count 0 2006.211.07:31:08.52#ibcon#read 4, iclass 15, count 0 2006.211.07:31:08.52#ibcon#about to read 5, iclass 15, count 0 2006.211.07:31:08.52#ibcon#read 5, iclass 15, count 0 2006.211.07:31:08.52#ibcon#about to read 6, iclass 15, count 0 2006.211.07:31:08.52#ibcon#read 6, iclass 15, count 0 2006.211.07:31:08.52#ibcon#end of sib2, iclass 15, count 0 2006.211.07:31:08.52#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:31:08.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:31:08.52#ibcon#[25=USB\r\n] 2006.211.07:31:08.52#ibcon#*before write, iclass 15, count 0 2006.211.07:31:08.52#ibcon#enter sib2, iclass 15, count 0 2006.211.07:31:08.52#ibcon#flushed, iclass 15, count 0 2006.211.07:31:08.52#ibcon#about to write, iclass 15, count 0 2006.211.07:31:08.52#ibcon#wrote, iclass 15, count 0 2006.211.07:31:08.52#ibcon#about to read 3, iclass 15, count 0 2006.211.07:31:08.55#ibcon#read 3, iclass 15, count 0 2006.211.07:31:08.55#ibcon#about to read 4, iclass 15, count 0 2006.211.07:31:08.55#ibcon#read 4, iclass 15, count 0 2006.211.07:31:08.55#ibcon#about to read 5, iclass 15, count 0 2006.211.07:31:08.55#ibcon#read 5, iclass 15, count 0 2006.211.07:31:08.55#ibcon#about to read 6, iclass 15, count 0 2006.211.07:31:08.55#ibcon#read 6, iclass 15, count 0 2006.211.07:31:08.55#ibcon#end of sib2, iclass 15, count 0 2006.211.07:31:08.55#ibcon#*after write, iclass 15, count 0 2006.211.07:31:08.55#ibcon#*before return 0, iclass 15, count 0 2006.211.07:31:08.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:08.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:08.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:31:08.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:31:08.55$vc4f8/valo=4,832.99 2006.211.07:31:08.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.07:31:08.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.07:31:08.55#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:08.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:08.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:08.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:08.55#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:31:08.55#ibcon#first serial, iclass 17, count 0 2006.211.07:31:08.55#ibcon#enter sib2, iclass 17, count 0 2006.211.07:31:08.55#ibcon#flushed, iclass 17, count 0 2006.211.07:31:08.55#ibcon#about to write, iclass 17, count 0 2006.211.07:31:08.55#ibcon#wrote, iclass 17, count 0 2006.211.07:31:08.55#ibcon#about to read 3, iclass 17, count 0 2006.211.07:31:08.57#ibcon#read 3, iclass 17, count 0 2006.211.07:31:08.57#ibcon#about to read 4, iclass 17, count 0 2006.211.07:31:08.57#ibcon#read 4, iclass 17, count 0 2006.211.07:31:08.57#ibcon#about to read 5, iclass 17, count 0 2006.211.07:31:08.57#ibcon#read 5, iclass 17, count 0 2006.211.07:31:08.57#ibcon#about to read 6, iclass 17, count 0 2006.211.07:31:08.57#ibcon#read 6, iclass 17, count 0 2006.211.07:31:08.57#ibcon#end of sib2, iclass 17, count 0 2006.211.07:31:08.57#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:31:08.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:31:08.57#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:31:08.57#ibcon#*before write, iclass 17, count 0 2006.211.07:31:08.57#ibcon#enter sib2, iclass 17, count 0 2006.211.07:31:08.57#ibcon#flushed, iclass 17, count 0 2006.211.07:31:08.57#ibcon#about to write, iclass 17, count 0 2006.211.07:31:08.57#ibcon#wrote, iclass 17, count 0 2006.211.07:31:08.57#ibcon#about to read 3, iclass 17, count 0 2006.211.07:31:08.61#ibcon#read 3, iclass 17, count 0 2006.211.07:31:08.61#ibcon#about to read 4, iclass 17, count 0 2006.211.07:31:08.61#ibcon#read 4, iclass 17, count 0 2006.211.07:31:08.61#ibcon#about to read 5, iclass 17, count 0 2006.211.07:31:08.61#ibcon#read 5, iclass 17, count 0 2006.211.07:31:08.61#ibcon#about to read 6, iclass 17, count 0 2006.211.07:31:08.61#ibcon#read 6, iclass 17, count 0 2006.211.07:31:08.61#ibcon#end of sib2, iclass 17, count 0 2006.211.07:31:08.61#ibcon#*after write, iclass 17, count 0 2006.211.07:31:08.61#ibcon#*before return 0, iclass 17, count 0 2006.211.07:31:08.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:08.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:08.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:31:08.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:31:08.61$vc4f8/va=4,7 2006.211.07:31:08.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.07:31:08.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.07:31:08.61#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:08.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:08.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:08.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:08.67#ibcon#enter wrdev, iclass 19, count 2 2006.211.07:31:08.67#ibcon#first serial, iclass 19, count 2 2006.211.07:31:08.67#ibcon#enter sib2, iclass 19, count 2 2006.211.07:31:08.67#ibcon#flushed, iclass 19, count 2 2006.211.07:31:08.67#ibcon#about to write, iclass 19, count 2 2006.211.07:31:08.67#ibcon#wrote, iclass 19, count 2 2006.211.07:31:08.67#ibcon#about to read 3, iclass 19, count 2 2006.211.07:31:08.69#ibcon#read 3, iclass 19, count 2 2006.211.07:31:08.69#ibcon#about to read 4, iclass 19, count 2 2006.211.07:31:08.69#ibcon#read 4, iclass 19, count 2 2006.211.07:31:08.69#ibcon#about to read 5, iclass 19, count 2 2006.211.07:31:08.69#ibcon#read 5, iclass 19, count 2 2006.211.07:31:08.69#ibcon#about to read 6, iclass 19, count 2 2006.211.07:31:08.69#ibcon#read 6, iclass 19, count 2 2006.211.07:31:08.69#ibcon#end of sib2, iclass 19, count 2 2006.211.07:31:08.69#ibcon#*mode == 0, iclass 19, count 2 2006.211.07:31:08.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.07:31:08.69#ibcon#[25=AT04-07\r\n] 2006.211.07:31:08.69#ibcon#*before write, iclass 19, count 2 2006.211.07:31:08.69#ibcon#enter sib2, iclass 19, count 2 2006.211.07:31:08.69#ibcon#flushed, iclass 19, count 2 2006.211.07:31:08.69#ibcon#about to write, iclass 19, count 2 2006.211.07:31:08.69#ibcon#wrote, iclass 19, count 2 2006.211.07:31:08.69#ibcon#about to read 3, iclass 19, count 2 2006.211.07:31:08.72#ibcon#read 3, iclass 19, count 2 2006.211.07:31:08.72#ibcon#about to read 4, iclass 19, count 2 2006.211.07:31:08.72#ibcon#read 4, iclass 19, count 2 2006.211.07:31:08.72#ibcon#about to read 5, iclass 19, count 2 2006.211.07:31:08.72#ibcon#read 5, iclass 19, count 2 2006.211.07:31:08.72#ibcon#about to read 6, iclass 19, count 2 2006.211.07:31:08.72#ibcon#read 6, iclass 19, count 2 2006.211.07:31:08.72#ibcon#end of sib2, iclass 19, count 2 2006.211.07:31:08.72#ibcon#*after write, iclass 19, count 2 2006.211.07:31:08.72#ibcon#*before return 0, iclass 19, count 2 2006.211.07:31:08.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:08.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:08.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.07:31:08.72#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:08.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:08.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:08.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:08.84#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:31:08.84#ibcon#first serial, iclass 19, count 0 2006.211.07:31:08.84#ibcon#enter sib2, iclass 19, count 0 2006.211.07:31:08.84#ibcon#flushed, iclass 19, count 0 2006.211.07:31:08.84#ibcon#about to write, iclass 19, count 0 2006.211.07:31:08.84#ibcon#wrote, iclass 19, count 0 2006.211.07:31:08.84#ibcon#about to read 3, iclass 19, count 0 2006.211.07:31:08.86#ibcon#read 3, iclass 19, count 0 2006.211.07:31:08.86#ibcon#about to read 4, iclass 19, count 0 2006.211.07:31:08.86#ibcon#read 4, iclass 19, count 0 2006.211.07:31:08.86#ibcon#about to read 5, iclass 19, count 0 2006.211.07:31:08.86#ibcon#read 5, iclass 19, count 0 2006.211.07:31:08.86#ibcon#about to read 6, iclass 19, count 0 2006.211.07:31:08.86#ibcon#read 6, iclass 19, count 0 2006.211.07:31:08.86#ibcon#end of sib2, iclass 19, count 0 2006.211.07:31:08.86#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:31:08.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:31:08.86#ibcon#[25=USB\r\n] 2006.211.07:31:08.86#ibcon#*before write, iclass 19, count 0 2006.211.07:31:08.86#ibcon#enter sib2, iclass 19, count 0 2006.211.07:31:08.86#ibcon#flushed, iclass 19, count 0 2006.211.07:31:08.86#ibcon#about to write, iclass 19, count 0 2006.211.07:31:08.86#ibcon#wrote, iclass 19, count 0 2006.211.07:31:08.86#ibcon#about to read 3, iclass 19, count 0 2006.211.07:31:08.89#ibcon#read 3, iclass 19, count 0 2006.211.07:31:08.89#ibcon#about to read 4, iclass 19, count 0 2006.211.07:31:08.89#ibcon#read 4, iclass 19, count 0 2006.211.07:31:08.89#ibcon#about to read 5, iclass 19, count 0 2006.211.07:31:08.89#ibcon#read 5, iclass 19, count 0 2006.211.07:31:08.89#ibcon#about to read 6, iclass 19, count 0 2006.211.07:31:08.89#ibcon#read 6, iclass 19, count 0 2006.211.07:31:08.89#ibcon#end of sib2, iclass 19, count 0 2006.211.07:31:08.89#ibcon#*after write, iclass 19, count 0 2006.211.07:31:08.89#ibcon#*before return 0, iclass 19, count 0 2006.211.07:31:08.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:08.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:08.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:31:08.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:31:08.89$vc4f8/valo=5,652.99 2006.211.07:31:08.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.07:31:08.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.07:31:08.89#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:08.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:08.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:08.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:08.89#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:31:08.89#ibcon#first serial, iclass 21, count 0 2006.211.07:31:08.89#ibcon#enter sib2, iclass 21, count 0 2006.211.07:31:08.89#ibcon#flushed, iclass 21, count 0 2006.211.07:31:08.89#ibcon#about to write, iclass 21, count 0 2006.211.07:31:08.89#ibcon#wrote, iclass 21, count 0 2006.211.07:31:08.89#ibcon#about to read 3, iclass 21, count 0 2006.211.07:31:08.91#ibcon#read 3, iclass 21, count 0 2006.211.07:31:08.91#ibcon#about to read 4, iclass 21, count 0 2006.211.07:31:08.91#ibcon#read 4, iclass 21, count 0 2006.211.07:31:08.91#ibcon#about to read 5, iclass 21, count 0 2006.211.07:31:08.91#ibcon#read 5, iclass 21, count 0 2006.211.07:31:08.91#ibcon#about to read 6, iclass 21, count 0 2006.211.07:31:08.91#ibcon#read 6, iclass 21, count 0 2006.211.07:31:08.91#ibcon#end of sib2, iclass 21, count 0 2006.211.07:31:08.91#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:31:08.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:31:08.91#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:31:08.91#ibcon#*before write, iclass 21, count 0 2006.211.07:31:08.91#ibcon#enter sib2, iclass 21, count 0 2006.211.07:31:08.91#ibcon#flushed, iclass 21, count 0 2006.211.07:31:08.91#ibcon#about to write, iclass 21, count 0 2006.211.07:31:08.91#ibcon#wrote, iclass 21, count 0 2006.211.07:31:08.91#ibcon#about to read 3, iclass 21, count 0 2006.211.07:31:08.95#ibcon#read 3, iclass 21, count 0 2006.211.07:31:08.95#ibcon#about to read 4, iclass 21, count 0 2006.211.07:31:08.95#ibcon#read 4, iclass 21, count 0 2006.211.07:31:08.95#ibcon#about to read 5, iclass 21, count 0 2006.211.07:31:08.95#ibcon#read 5, iclass 21, count 0 2006.211.07:31:08.95#ibcon#about to read 6, iclass 21, count 0 2006.211.07:31:08.95#ibcon#read 6, iclass 21, count 0 2006.211.07:31:08.95#ibcon#end of sib2, iclass 21, count 0 2006.211.07:31:08.95#ibcon#*after write, iclass 21, count 0 2006.211.07:31:08.95#ibcon#*before return 0, iclass 21, count 0 2006.211.07:31:08.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:08.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:08.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:31:08.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:31:08.95$vc4f8/va=5,7 2006.211.07:31:08.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.07:31:08.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.07:31:08.95#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:08.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:09.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:09.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:09.01#ibcon#enter wrdev, iclass 23, count 2 2006.211.07:31:09.01#ibcon#first serial, iclass 23, count 2 2006.211.07:31:09.01#ibcon#enter sib2, iclass 23, count 2 2006.211.07:31:09.01#ibcon#flushed, iclass 23, count 2 2006.211.07:31:09.01#ibcon#about to write, iclass 23, count 2 2006.211.07:31:09.01#ibcon#wrote, iclass 23, count 2 2006.211.07:31:09.01#ibcon#about to read 3, iclass 23, count 2 2006.211.07:31:09.03#ibcon#read 3, iclass 23, count 2 2006.211.07:31:09.03#ibcon#about to read 4, iclass 23, count 2 2006.211.07:31:09.03#ibcon#read 4, iclass 23, count 2 2006.211.07:31:09.03#ibcon#about to read 5, iclass 23, count 2 2006.211.07:31:09.03#ibcon#read 5, iclass 23, count 2 2006.211.07:31:09.03#ibcon#about to read 6, iclass 23, count 2 2006.211.07:31:09.03#ibcon#read 6, iclass 23, count 2 2006.211.07:31:09.03#ibcon#end of sib2, iclass 23, count 2 2006.211.07:31:09.03#ibcon#*mode == 0, iclass 23, count 2 2006.211.07:31:09.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.07:31:09.03#ibcon#[25=AT05-07\r\n] 2006.211.07:31:09.03#ibcon#*before write, iclass 23, count 2 2006.211.07:31:09.03#ibcon#enter sib2, iclass 23, count 2 2006.211.07:31:09.03#ibcon#flushed, iclass 23, count 2 2006.211.07:31:09.03#ibcon#about to write, iclass 23, count 2 2006.211.07:31:09.03#ibcon#wrote, iclass 23, count 2 2006.211.07:31:09.03#ibcon#about to read 3, iclass 23, count 2 2006.211.07:31:09.06#ibcon#read 3, iclass 23, count 2 2006.211.07:31:09.06#ibcon#about to read 4, iclass 23, count 2 2006.211.07:31:09.06#ibcon#read 4, iclass 23, count 2 2006.211.07:31:09.06#ibcon#about to read 5, iclass 23, count 2 2006.211.07:31:09.06#ibcon#read 5, iclass 23, count 2 2006.211.07:31:09.06#ibcon#about to read 6, iclass 23, count 2 2006.211.07:31:09.06#ibcon#read 6, iclass 23, count 2 2006.211.07:31:09.06#ibcon#end of sib2, iclass 23, count 2 2006.211.07:31:09.06#ibcon#*after write, iclass 23, count 2 2006.211.07:31:09.06#ibcon#*before return 0, iclass 23, count 2 2006.211.07:31:09.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:09.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:09.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.07:31:09.06#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:09.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:09.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:09.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:09.18#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:31:09.18#ibcon#first serial, iclass 23, count 0 2006.211.07:31:09.18#ibcon#enter sib2, iclass 23, count 0 2006.211.07:31:09.18#ibcon#flushed, iclass 23, count 0 2006.211.07:31:09.18#ibcon#about to write, iclass 23, count 0 2006.211.07:31:09.18#ibcon#wrote, iclass 23, count 0 2006.211.07:31:09.18#ibcon#about to read 3, iclass 23, count 0 2006.211.07:31:09.20#ibcon#read 3, iclass 23, count 0 2006.211.07:31:09.20#ibcon#about to read 4, iclass 23, count 0 2006.211.07:31:09.20#ibcon#read 4, iclass 23, count 0 2006.211.07:31:09.20#ibcon#about to read 5, iclass 23, count 0 2006.211.07:31:09.20#ibcon#read 5, iclass 23, count 0 2006.211.07:31:09.20#ibcon#about to read 6, iclass 23, count 0 2006.211.07:31:09.20#ibcon#read 6, iclass 23, count 0 2006.211.07:31:09.20#ibcon#end of sib2, iclass 23, count 0 2006.211.07:31:09.20#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:31:09.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:31:09.20#ibcon#[25=USB\r\n] 2006.211.07:31:09.20#ibcon#*before write, iclass 23, count 0 2006.211.07:31:09.20#ibcon#enter sib2, iclass 23, count 0 2006.211.07:31:09.20#ibcon#flushed, iclass 23, count 0 2006.211.07:31:09.20#ibcon#about to write, iclass 23, count 0 2006.211.07:31:09.20#ibcon#wrote, iclass 23, count 0 2006.211.07:31:09.20#ibcon#about to read 3, iclass 23, count 0 2006.211.07:31:09.23#ibcon#read 3, iclass 23, count 0 2006.211.07:31:09.23#ibcon#about to read 4, iclass 23, count 0 2006.211.07:31:09.23#ibcon#read 4, iclass 23, count 0 2006.211.07:31:09.23#ibcon#about to read 5, iclass 23, count 0 2006.211.07:31:09.23#ibcon#read 5, iclass 23, count 0 2006.211.07:31:09.23#ibcon#about to read 6, iclass 23, count 0 2006.211.07:31:09.23#ibcon#read 6, iclass 23, count 0 2006.211.07:31:09.23#ibcon#end of sib2, iclass 23, count 0 2006.211.07:31:09.23#ibcon#*after write, iclass 23, count 0 2006.211.07:31:09.23#ibcon#*before return 0, iclass 23, count 0 2006.211.07:31:09.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:09.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:09.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:31:09.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:31:09.23$vc4f8/valo=6,772.99 2006.211.07:31:09.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:31:09.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:31:09.23#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:09.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:09.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:09.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:09.23#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:31:09.23#ibcon#first serial, iclass 25, count 0 2006.211.07:31:09.23#ibcon#enter sib2, iclass 25, count 0 2006.211.07:31:09.23#ibcon#flushed, iclass 25, count 0 2006.211.07:31:09.23#ibcon#about to write, iclass 25, count 0 2006.211.07:31:09.23#ibcon#wrote, iclass 25, count 0 2006.211.07:31:09.23#ibcon#about to read 3, iclass 25, count 0 2006.211.07:31:09.25#ibcon#read 3, iclass 25, count 0 2006.211.07:31:09.25#ibcon#about to read 4, iclass 25, count 0 2006.211.07:31:09.25#ibcon#read 4, iclass 25, count 0 2006.211.07:31:09.25#ibcon#about to read 5, iclass 25, count 0 2006.211.07:31:09.25#ibcon#read 5, iclass 25, count 0 2006.211.07:31:09.25#ibcon#about to read 6, iclass 25, count 0 2006.211.07:31:09.25#ibcon#read 6, iclass 25, count 0 2006.211.07:31:09.25#ibcon#end of sib2, iclass 25, count 0 2006.211.07:31:09.25#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:31:09.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:31:09.25#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:31:09.25#ibcon#*before write, iclass 25, count 0 2006.211.07:31:09.25#ibcon#enter sib2, iclass 25, count 0 2006.211.07:31:09.25#ibcon#flushed, iclass 25, count 0 2006.211.07:31:09.25#ibcon#about to write, iclass 25, count 0 2006.211.07:31:09.25#ibcon#wrote, iclass 25, count 0 2006.211.07:31:09.25#ibcon#about to read 3, iclass 25, count 0 2006.211.07:31:09.29#ibcon#read 3, iclass 25, count 0 2006.211.07:31:09.29#ibcon#about to read 4, iclass 25, count 0 2006.211.07:31:09.29#ibcon#read 4, iclass 25, count 0 2006.211.07:31:09.29#ibcon#about to read 5, iclass 25, count 0 2006.211.07:31:09.29#ibcon#read 5, iclass 25, count 0 2006.211.07:31:09.29#ibcon#about to read 6, iclass 25, count 0 2006.211.07:31:09.29#ibcon#read 6, iclass 25, count 0 2006.211.07:31:09.29#ibcon#end of sib2, iclass 25, count 0 2006.211.07:31:09.29#ibcon#*after write, iclass 25, count 0 2006.211.07:31:09.29#ibcon#*before return 0, iclass 25, count 0 2006.211.07:31:09.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:09.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:09.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:31:09.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:31:09.29$vc4f8/va=6,6 2006.211.07:31:09.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.07:31:09.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.07:31:09.29#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:09.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:31:09.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:31:09.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:31:09.35#ibcon#enter wrdev, iclass 27, count 2 2006.211.07:31:09.35#ibcon#first serial, iclass 27, count 2 2006.211.07:31:09.35#ibcon#enter sib2, iclass 27, count 2 2006.211.07:31:09.35#ibcon#flushed, iclass 27, count 2 2006.211.07:31:09.35#ibcon#about to write, iclass 27, count 2 2006.211.07:31:09.35#ibcon#wrote, iclass 27, count 2 2006.211.07:31:09.35#ibcon#about to read 3, iclass 27, count 2 2006.211.07:31:09.37#ibcon#read 3, iclass 27, count 2 2006.211.07:31:09.37#ibcon#about to read 4, iclass 27, count 2 2006.211.07:31:09.37#ibcon#read 4, iclass 27, count 2 2006.211.07:31:09.37#ibcon#about to read 5, iclass 27, count 2 2006.211.07:31:09.37#ibcon#read 5, iclass 27, count 2 2006.211.07:31:09.37#ibcon#about to read 6, iclass 27, count 2 2006.211.07:31:09.37#ibcon#read 6, iclass 27, count 2 2006.211.07:31:09.37#ibcon#end of sib2, iclass 27, count 2 2006.211.07:31:09.37#ibcon#*mode == 0, iclass 27, count 2 2006.211.07:31:09.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.07:31:09.37#ibcon#[25=AT06-06\r\n] 2006.211.07:31:09.37#ibcon#*before write, iclass 27, count 2 2006.211.07:31:09.37#ibcon#enter sib2, iclass 27, count 2 2006.211.07:31:09.37#ibcon#flushed, iclass 27, count 2 2006.211.07:31:09.37#ibcon#about to write, iclass 27, count 2 2006.211.07:31:09.37#ibcon#wrote, iclass 27, count 2 2006.211.07:31:09.37#ibcon#about to read 3, iclass 27, count 2 2006.211.07:31:09.40#ibcon#read 3, iclass 27, count 2 2006.211.07:31:09.40#ibcon#about to read 4, iclass 27, count 2 2006.211.07:31:09.40#ibcon#read 4, iclass 27, count 2 2006.211.07:31:09.40#ibcon#about to read 5, iclass 27, count 2 2006.211.07:31:09.40#ibcon#read 5, iclass 27, count 2 2006.211.07:31:09.40#ibcon#about to read 6, iclass 27, count 2 2006.211.07:31:09.40#ibcon#read 6, iclass 27, count 2 2006.211.07:31:09.40#ibcon#end of sib2, iclass 27, count 2 2006.211.07:31:09.40#ibcon#*after write, iclass 27, count 2 2006.211.07:31:09.40#ibcon#*before return 0, iclass 27, count 2 2006.211.07:31:09.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:31:09.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:31:09.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.07:31:09.40#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:09.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:31:09.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:31:09.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:31:09.52#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:31:09.52#ibcon#first serial, iclass 27, count 0 2006.211.07:31:09.52#ibcon#enter sib2, iclass 27, count 0 2006.211.07:31:09.52#ibcon#flushed, iclass 27, count 0 2006.211.07:31:09.52#ibcon#about to write, iclass 27, count 0 2006.211.07:31:09.52#ibcon#wrote, iclass 27, count 0 2006.211.07:31:09.52#ibcon#about to read 3, iclass 27, count 0 2006.211.07:31:09.54#ibcon#read 3, iclass 27, count 0 2006.211.07:31:09.54#ibcon#about to read 4, iclass 27, count 0 2006.211.07:31:09.54#ibcon#read 4, iclass 27, count 0 2006.211.07:31:09.54#ibcon#about to read 5, iclass 27, count 0 2006.211.07:31:09.54#ibcon#read 5, iclass 27, count 0 2006.211.07:31:09.54#ibcon#about to read 6, iclass 27, count 0 2006.211.07:31:09.54#ibcon#read 6, iclass 27, count 0 2006.211.07:31:09.54#ibcon#end of sib2, iclass 27, count 0 2006.211.07:31:09.54#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:31:09.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:31:09.54#ibcon#[25=USB\r\n] 2006.211.07:31:09.54#ibcon#*before write, iclass 27, count 0 2006.211.07:31:09.54#ibcon#enter sib2, iclass 27, count 0 2006.211.07:31:09.54#ibcon#flushed, iclass 27, count 0 2006.211.07:31:09.54#ibcon#about to write, iclass 27, count 0 2006.211.07:31:09.54#ibcon#wrote, iclass 27, count 0 2006.211.07:31:09.54#ibcon#about to read 3, iclass 27, count 0 2006.211.07:31:09.57#ibcon#read 3, iclass 27, count 0 2006.211.07:31:09.57#ibcon#about to read 4, iclass 27, count 0 2006.211.07:31:09.57#ibcon#read 4, iclass 27, count 0 2006.211.07:31:09.57#ibcon#about to read 5, iclass 27, count 0 2006.211.07:31:09.57#ibcon#read 5, iclass 27, count 0 2006.211.07:31:09.57#ibcon#about to read 6, iclass 27, count 0 2006.211.07:31:09.57#ibcon#read 6, iclass 27, count 0 2006.211.07:31:09.57#ibcon#end of sib2, iclass 27, count 0 2006.211.07:31:09.57#ibcon#*after write, iclass 27, count 0 2006.211.07:31:09.57#ibcon#*before return 0, iclass 27, count 0 2006.211.07:31:09.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:31:09.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:31:09.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:31:09.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:31:09.57$vc4f8/valo=7,832.99 2006.211.07:31:09.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:31:09.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:31:09.57#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:09.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:31:09.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:31:09.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:31:09.57#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:31:09.57#ibcon#first serial, iclass 29, count 0 2006.211.07:31:09.57#ibcon#enter sib2, iclass 29, count 0 2006.211.07:31:09.57#ibcon#flushed, iclass 29, count 0 2006.211.07:31:09.57#ibcon#about to write, iclass 29, count 0 2006.211.07:31:09.57#ibcon#wrote, iclass 29, count 0 2006.211.07:31:09.57#ibcon#about to read 3, iclass 29, count 0 2006.211.07:31:09.59#ibcon#read 3, iclass 29, count 0 2006.211.07:31:09.59#ibcon#about to read 4, iclass 29, count 0 2006.211.07:31:09.59#ibcon#read 4, iclass 29, count 0 2006.211.07:31:09.59#ibcon#about to read 5, iclass 29, count 0 2006.211.07:31:09.59#ibcon#read 5, iclass 29, count 0 2006.211.07:31:09.59#ibcon#about to read 6, iclass 29, count 0 2006.211.07:31:09.59#ibcon#read 6, iclass 29, count 0 2006.211.07:31:09.59#ibcon#end of sib2, iclass 29, count 0 2006.211.07:31:09.59#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:31:09.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:31:09.59#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:31:09.59#ibcon#*before write, iclass 29, count 0 2006.211.07:31:09.59#ibcon#enter sib2, iclass 29, count 0 2006.211.07:31:09.59#ibcon#flushed, iclass 29, count 0 2006.211.07:31:09.59#ibcon#about to write, iclass 29, count 0 2006.211.07:31:09.59#ibcon#wrote, iclass 29, count 0 2006.211.07:31:09.59#ibcon#about to read 3, iclass 29, count 0 2006.211.07:31:09.63#ibcon#read 3, iclass 29, count 0 2006.211.07:31:09.63#ibcon#about to read 4, iclass 29, count 0 2006.211.07:31:09.63#ibcon#read 4, iclass 29, count 0 2006.211.07:31:09.63#ibcon#about to read 5, iclass 29, count 0 2006.211.07:31:09.63#ibcon#read 5, iclass 29, count 0 2006.211.07:31:09.63#ibcon#about to read 6, iclass 29, count 0 2006.211.07:31:09.63#ibcon#read 6, iclass 29, count 0 2006.211.07:31:09.63#ibcon#end of sib2, iclass 29, count 0 2006.211.07:31:09.63#ibcon#*after write, iclass 29, count 0 2006.211.07:31:09.63#ibcon#*before return 0, iclass 29, count 0 2006.211.07:31:09.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:31:09.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:31:09.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:31:09.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:31:09.63$vc4f8/va=7,6 2006.211.07:31:09.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:31:09.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:31:09.63#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:09.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:31:09.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:31:09.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:31:09.69#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:31:09.69#ibcon#first serial, iclass 31, count 2 2006.211.07:31:09.69#ibcon#enter sib2, iclass 31, count 2 2006.211.07:31:09.69#ibcon#flushed, iclass 31, count 2 2006.211.07:31:09.69#ibcon#about to write, iclass 31, count 2 2006.211.07:31:09.69#ibcon#wrote, iclass 31, count 2 2006.211.07:31:09.69#ibcon#about to read 3, iclass 31, count 2 2006.211.07:31:09.71#ibcon#read 3, iclass 31, count 2 2006.211.07:31:09.71#ibcon#about to read 4, iclass 31, count 2 2006.211.07:31:09.71#ibcon#read 4, iclass 31, count 2 2006.211.07:31:09.71#ibcon#about to read 5, iclass 31, count 2 2006.211.07:31:09.71#ibcon#read 5, iclass 31, count 2 2006.211.07:31:09.71#ibcon#about to read 6, iclass 31, count 2 2006.211.07:31:09.71#ibcon#read 6, iclass 31, count 2 2006.211.07:31:09.71#ibcon#end of sib2, iclass 31, count 2 2006.211.07:31:09.71#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:31:09.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:31:09.71#ibcon#[25=AT07-06\r\n] 2006.211.07:31:09.71#ibcon#*before write, iclass 31, count 2 2006.211.07:31:09.71#ibcon#enter sib2, iclass 31, count 2 2006.211.07:31:09.71#ibcon#flushed, iclass 31, count 2 2006.211.07:31:09.71#ibcon#about to write, iclass 31, count 2 2006.211.07:31:09.71#ibcon#wrote, iclass 31, count 2 2006.211.07:31:09.71#ibcon#about to read 3, iclass 31, count 2 2006.211.07:31:09.74#ibcon#read 3, iclass 31, count 2 2006.211.07:31:09.74#ibcon#about to read 4, iclass 31, count 2 2006.211.07:31:09.74#ibcon#read 4, iclass 31, count 2 2006.211.07:31:09.74#ibcon#about to read 5, iclass 31, count 2 2006.211.07:31:09.74#ibcon#read 5, iclass 31, count 2 2006.211.07:31:09.74#ibcon#about to read 6, iclass 31, count 2 2006.211.07:31:09.74#ibcon#read 6, iclass 31, count 2 2006.211.07:31:09.74#ibcon#end of sib2, iclass 31, count 2 2006.211.07:31:09.74#ibcon#*after write, iclass 31, count 2 2006.211.07:31:09.74#ibcon#*before return 0, iclass 31, count 2 2006.211.07:31:09.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:31:09.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:31:09.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:31:09.74#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:09.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:31:09.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:31:09.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:31:09.86#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:31:09.86#ibcon#first serial, iclass 31, count 0 2006.211.07:31:09.86#ibcon#enter sib2, iclass 31, count 0 2006.211.07:31:09.86#ibcon#flushed, iclass 31, count 0 2006.211.07:31:09.86#ibcon#about to write, iclass 31, count 0 2006.211.07:31:09.86#ibcon#wrote, iclass 31, count 0 2006.211.07:31:09.86#ibcon#about to read 3, iclass 31, count 0 2006.211.07:31:09.88#ibcon#read 3, iclass 31, count 0 2006.211.07:31:09.88#ibcon#about to read 4, iclass 31, count 0 2006.211.07:31:09.88#ibcon#read 4, iclass 31, count 0 2006.211.07:31:09.88#ibcon#about to read 5, iclass 31, count 0 2006.211.07:31:09.88#ibcon#read 5, iclass 31, count 0 2006.211.07:31:09.88#ibcon#about to read 6, iclass 31, count 0 2006.211.07:31:09.88#ibcon#read 6, iclass 31, count 0 2006.211.07:31:09.88#ibcon#end of sib2, iclass 31, count 0 2006.211.07:31:09.88#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:31:09.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:31:09.88#ibcon#[25=USB\r\n] 2006.211.07:31:09.88#ibcon#*before write, iclass 31, count 0 2006.211.07:31:09.88#ibcon#enter sib2, iclass 31, count 0 2006.211.07:31:09.88#ibcon#flushed, iclass 31, count 0 2006.211.07:31:09.88#ibcon#about to write, iclass 31, count 0 2006.211.07:31:09.88#ibcon#wrote, iclass 31, count 0 2006.211.07:31:09.88#ibcon#about to read 3, iclass 31, count 0 2006.211.07:31:09.91#ibcon#read 3, iclass 31, count 0 2006.211.07:31:09.91#ibcon#about to read 4, iclass 31, count 0 2006.211.07:31:09.91#ibcon#read 4, iclass 31, count 0 2006.211.07:31:09.91#ibcon#about to read 5, iclass 31, count 0 2006.211.07:31:09.91#ibcon#read 5, iclass 31, count 0 2006.211.07:31:09.91#ibcon#about to read 6, iclass 31, count 0 2006.211.07:31:09.91#ibcon#read 6, iclass 31, count 0 2006.211.07:31:09.91#ibcon#end of sib2, iclass 31, count 0 2006.211.07:31:09.91#ibcon#*after write, iclass 31, count 0 2006.211.07:31:09.91#ibcon#*before return 0, iclass 31, count 0 2006.211.07:31:09.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:31:09.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:31:09.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:31:09.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:31:09.91$vc4f8/valo=8,852.99 2006.211.07:31:09.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:31:09.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:31:09.91#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:09.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:31:09.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:31:09.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:31:09.91#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:31:09.91#ibcon#first serial, iclass 33, count 0 2006.211.07:31:09.91#ibcon#enter sib2, iclass 33, count 0 2006.211.07:31:09.91#ibcon#flushed, iclass 33, count 0 2006.211.07:31:09.91#ibcon#about to write, iclass 33, count 0 2006.211.07:31:09.91#ibcon#wrote, iclass 33, count 0 2006.211.07:31:09.91#ibcon#about to read 3, iclass 33, count 0 2006.211.07:31:09.93#ibcon#read 3, iclass 33, count 0 2006.211.07:31:09.93#ibcon#about to read 4, iclass 33, count 0 2006.211.07:31:09.93#ibcon#read 4, iclass 33, count 0 2006.211.07:31:09.93#ibcon#about to read 5, iclass 33, count 0 2006.211.07:31:09.93#ibcon#read 5, iclass 33, count 0 2006.211.07:31:09.93#ibcon#about to read 6, iclass 33, count 0 2006.211.07:31:09.93#ibcon#read 6, iclass 33, count 0 2006.211.07:31:09.93#ibcon#end of sib2, iclass 33, count 0 2006.211.07:31:09.93#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:31:09.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:31:09.93#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:31:09.93#ibcon#*before write, iclass 33, count 0 2006.211.07:31:09.93#ibcon#enter sib2, iclass 33, count 0 2006.211.07:31:09.93#ibcon#flushed, iclass 33, count 0 2006.211.07:31:09.93#ibcon#about to write, iclass 33, count 0 2006.211.07:31:09.93#ibcon#wrote, iclass 33, count 0 2006.211.07:31:09.93#ibcon#about to read 3, iclass 33, count 0 2006.211.07:31:09.97#ibcon#read 3, iclass 33, count 0 2006.211.07:31:09.97#ibcon#about to read 4, iclass 33, count 0 2006.211.07:31:09.97#ibcon#read 4, iclass 33, count 0 2006.211.07:31:09.97#ibcon#about to read 5, iclass 33, count 0 2006.211.07:31:09.97#ibcon#read 5, iclass 33, count 0 2006.211.07:31:09.97#ibcon#about to read 6, iclass 33, count 0 2006.211.07:31:09.97#ibcon#read 6, iclass 33, count 0 2006.211.07:31:09.97#ibcon#end of sib2, iclass 33, count 0 2006.211.07:31:09.97#ibcon#*after write, iclass 33, count 0 2006.211.07:31:09.97#ibcon#*before return 0, iclass 33, count 0 2006.211.07:31:09.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:31:09.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:31:09.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:31:09.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:31:09.97$vc4f8/va=8,7 2006.211.07:31:09.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:31:09.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:31:09.97#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:09.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:31:10.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:31:10.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:31:10.03#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:31:10.03#ibcon#first serial, iclass 35, count 2 2006.211.07:31:10.03#ibcon#enter sib2, iclass 35, count 2 2006.211.07:31:10.03#ibcon#flushed, iclass 35, count 2 2006.211.07:31:10.03#ibcon#about to write, iclass 35, count 2 2006.211.07:31:10.03#ibcon#wrote, iclass 35, count 2 2006.211.07:31:10.03#ibcon#about to read 3, iclass 35, count 2 2006.211.07:31:10.05#ibcon#read 3, iclass 35, count 2 2006.211.07:31:10.05#ibcon#about to read 4, iclass 35, count 2 2006.211.07:31:10.05#ibcon#read 4, iclass 35, count 2 2006.211.07:31:10.05#ibcon#about to read 5, iclass 35, count 2 2006.211.07:31:10.05#ibcon#read 5, iclass 35, count 2 2006.211.07:31:10.05#ibcon#about to read 6, iclass 35, count 2 2006.211.07:31:10.05#ibcon#read 6, iclass 35, count 2 2006.211.07:31:10.05#ibcon#end of sib2, iclass 35, count 2 2006.211.07:31:10.05#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:31:10.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:31:10.05#ibcon#[25=AT08-07\r\n] 2006.211.07:31:10.05#ibcon#*before write, iclass 35, count 2 2006.211.07:31:10.05#ibcon#enter sib2, iclass 35, count 2 2006.211.07:31:10.05#ibcon#flushed, iclass 35, count 2 2006.211.07:31:10.05#ibcon#about to write, iclass 35, count 2 2006.211.07:31:10.05#ibcon#wrote, iclass 35, count 2 2006.211.07:31:10.05#ibcon#about to read 3, iclass 35, count 2 2006.211.07:31:10.08#ibcon#read 3, iclass 35, count 2 2006.211.07:31:10.08#ibcon#about to read 4, iclass 35, count 2 2006.211.07:31:10.08#ibcon#read 4, iclass 35, count 2 2006.211.07:31:10.08#ibcon#about to read 5, iclass 35, count 2 2006.211.07:31:10.08#ibcon#read 5, iclass 35, count 2 2006.211.07:31:10.08#ibcon#about to read 6, iclass 35, count 2 2006.211.07:31:10.08#ibcon#read 6, iclass 35, count 2 2006.211.07:31:10.08#ibcon#end of sib2, iclass 35, count 2 2006.211.07:31:10.08#ibcon#*after write, iclass 35, count 2 2006.211.07:31:10.08#ibcon#*before return 0, iclass 35, count 2 2006.211.07:31:10.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:31:10.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:31:10.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:31:10.08#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:10.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:31:10.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:31:10.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:31:10.20#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:31:10.20#ibcon#first serial, iclass 35, count 0 2006.211.07:31:10.20#ibcon#enter sib2, iclass 35, count 0 2006.211.07:31:10.20#ibcon#flushed, iclass 35, count 0 2006.211.07:31:10.20#ibcon#about to write, iclass 35, count 0 2006.211.07:31:10.20#ibcon#wrote, iclass 35, count 0 2006.211.07:31:10.20#ibcon#about to read 3, iclass 35, count 0 2006.211.07:31:10.22#ibcon#read 3, iclass 35, count 0 2006.211.07:31:10.22#ibcon#about to read 4, iclass 35, count 0 2006.211.07:31:10.22#ibcon#read 4, iclass 35, count 0 2006.211.07:31:10.22#ibcon#about to read 5, iclass 35, count 0 2006.211.07:31:10.22#ibcon#read 5, iclass 35, count 0 2006.211.07:31:10.22#ibcon#about to read 6, iclass 35, count 0 2006.211.07:31:10.22#ibcon#read 6, iclass 35, count 0 2006.211.07:31:10.22#ibcon#end of sib2, iclass 35, count 0 2006.211.07:31:10.22#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:31:10.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:31:10.22#ibcon#[25=USB\r\n] 2006.211.07:31:10.22#ibcon#*before write, iclass 35, count 0 2006.211.07:31:10.22#ibcon#enter sib2, iclass 35, count 0 2006.211.07:31:10.22#ibcon#flushed, iclass 35, count 0 2006.211.07:31:10.22#ibcon#about to write, iclass 35, count 0 2006.211.07:31:10.22#ibcon#wrote, iclass 35, count 0 2006.211.07:31:10.22#ibcon#about to read 3, iclass 35, count 0 2006.211.07:31:10.25#ibcon#read 3, iclass 35, count 0 2006.211.07:31:10.25#ibcon#about to read 4, iclass 35, count 0 2006.211.07:31:10.25#ibcon#read 4, iclass 35, count 0 2006.211.07:31:10.25#ibcon#about to read 5, iclass 35, count 0 2006.211.07:31:10.25#ibcon#read 5, iclass 35, count 0 2006.211.07:31:10.25#ibcon#about to read 6, iclass 35, count 0 2006.211.07:31:10.25#ibcon#read 6, iclass 35, count 0 2006.211.07:31:10.25#ibcon#end of sib2, iclass 35, count 0 2006.211.07:31:10.25#ibcon#*after write, iclass 35, count 0 2006.211.07:31:10.25#ibcon#*before return 0, iclass 35, count 0 2006.211.07:31:10.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:31:10.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:31:10.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:31:10.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:31:10.25$vc4f8/vblo=1,632.99 2006.211.07:31:10.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:31:10.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:31:10.25#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:10.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:31:10.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:31:10.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:31:10.25#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:31:10.25#ibcon#first serial, iclass 37, count 0 2006.211.07:31:10.25#ibcon#enter sib2, iclass 37, count 0 2006.211.07:31:10.25#ibcon#flushed, iclass 37, count 0 2006.211.07:31:10.25#ibcon#about to write, iclass 37, count 0 2006.211.07:31:10.25#ibcon#wrote, iclass 37, count 0 2006.211.07:31:10.25#ibcon#about to read 3, iclass 37, count 0 2006.211.07:31:10.27#ibcon#read 3, iclass 37, count 0 2006.211.07:31:10.27#ibcon#about to read 4, iclass 37, count 0 2006.211.07:31:10.27#ibcon#read 4, iclass 37, count 0 2006.211.07:31:10.27#ibcon#about to read 5, iclass 37, count 0 2006.211.07:31:10.27#ibcon#read 5, iclass 37, count 0 2006.211.07:31:10.27#ibcon#about to read 6, iclass 37, count 0 2006.211.07:31:10.27#ibcon#read 6, iclass 37, count 0 2006.211.07:31:10.27#ibcon#end of sib2, iclass 37, count 0 2006.211.07:31:10.27#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:31:10.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:31:10.27#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:31:10.27#ibcon#*before write, iclass 37, count 0 2006.211.07:31:10.27#ibcon#enter sib2, iclass 37, count 0 2006.211.07:31:10.27#ibcon#flushed, iclass 37, count 0 2006.211.07:31:10.27#ibcon#about to write, iclass 37, count 0 2006.211.07:31:10.27#ibcon#wrote, iclass 37, count 0 2006.211.07:31:10.27#ibcon#about to read 3, iclass 37, count 0 2006.211.07:31:10.31#ibcon#read 3, iclass 37, count 0 2006.211.07:31:10.31#ibcon#about to read 4, iclass 37, count 0 2006.211.07:31:10.31#ibcon#read 4, iclass 37, count 0 2006.211.07:31:10.31#ibcon#about to read 5, iclass 37, count 0 2006.211.07:31:10.31#ibcon#read 5, iclass 37, count 0 2006.211.07:31:10.31#ibcon#about to read 6, iclass 37, count 0 2006.211.07:31:10.31#ibcon#read 6, iclass 37, count 0 2006.211.07:31:10.31#ibcon#end of sib2, iclass 37, count 0 2006.211.07:31:10.31#ibcon#*after write, iclass 37, count 0 2006.211.07:31:10.31#ibcon#*before return 0, iclass 37, count 0 2006.211.07:31:10.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:31:10.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:31:10.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:31:10.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:31:10.31$vc4f8/vb=1,4 2006.211.07:31:10.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:31:10.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:31:10.31#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:10.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:31:10.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:31:10.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:31:10.31#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:31:10.31#ibcon#first serial, iclass 39, count 2 2006.211.07:31:10.31#ibcon#enter sib2, iclass 39, count 2 2006.211.07:31:10.31#ibcon#flushed, iclass 39, count 2 2006.211.07:31:10.31#ibcon#about to write, iclass 39, count 2 2006.211.07:31:10.31#ibcon#wrote, iclass 39, count 2 2006.211.07:31:10.31#ibcon#about to read 3, iclass 39, count 2 2006.211.07:31:10.33#ibcon#read 3, iclass 39, count 2 2006.211.07:31:10.33#ibcon#about to read 4, iclass 39, count 2 2006.211.07:31:10.33#ibcon#read 4, iclass 39, count 2 2006.211.07:31:10.33#ibcon#about to read 5, iclass 39, count 2 2006.211.07:31:10.33#ibcon#read 5, iclass 39, count 2 2006.211.07:31:10.33#ibcon#about to read 6, iclass 39, count 2 2006.211.07:31:10.33#ibcon#read 6, iclass 39, count 2 2006.211.07:31:10.33#ibcon#end of sib2, iclass 39, count 2 2006.211.07:31:10.33#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:31:10.33#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:31:10.33#ibcon#[27=AT01-04\r\n] 2006.211.07:31:10.33#ibcon#*before write, iclass 39, count 2 2006.211.07:31:10.33#ibcon#enter sib2, iclass 39, count 2 2006.211.07:31:10.33#ibcon#flushed, iclass 39, count 2 2006.211.07:31:10.33#ibcon#about to write, iclass 39, count 2 2006.211.07:31:10.33#ibcon#wrote, iclass 39, count 2 2006.211.07:31:10.33#ibcon#about to read 3, iclass 39, count 2 2006.211.07:31:10.36#ibcon#read 3, iclass 39, count 2 2006.211.07:31:10.36#ibcon#about to read 4, iclass 39, count 2 2006.211.07:31:10.36#ibcon#read 4, iclass 39, count 2 2006.211.07:31:10.36#ibcon#about to read 5, iclass 39, count 2 2006.211.07:31:10.36#ibcon#read 5, iclass 39, count 2 2006.211.07:31:10.36#ibcon#about to read 6, iclass 39, count 2 2006.211.07:31:10.36#ibcon#read 6, iclass 39, count 2 2006.211.07:31:10.36#ibcon#end of sib2, iclass 39, count 2 2006.211.07:31:10.36#ibcon#*after write, iclass 39, count 2 2006.211.07:31:10.36#ibcon#*before return 0, iclass 39, count 2 2006.211.07:31:10.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:31:10.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:31:10.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:31:10.36#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:10.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:31:10.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:31:10.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:31:10.48#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:31:10.48#ibcon#first serial, iclass 39, count 0 2006.211.07:31:10.48#ibcon#enter sib2, iclass 39, count 0 2006.211.07:31:10.48#ibcon#flushed, iclass 39, count 0 2006.211.07:31:10.48#ibcon#about to write, iclass 39, count 0 2006.211.07:31:10.48#ibcon#wrote, iclass 39, count 0 2006.211.07:31:10.48#ibcon#about to read 3, iclass 39, count 0 2006.211.07:31:10.50#ibcon#read 3, iclass 39, count 0 2006.211.07:31:10.50#ibcon#about to read 4, iclass 39, count 0 2006.211.07:31:10.50#ibcon#read 4, iclass 39, count 0 2006.211.07:31:10.50#ibcon#about to read 5, iclass 39, count 0 2006.211.07:31:10.50#ibcon#read 5, iclass 39, count 0 2006.211.07:31:10.50#ibcon#about to read 6, iclass 39, count 0 2006.211.07:31:10.50#ibcon#read 6, iclass 39, count 0 2006.211.07:31:10.50#ibcon#end of sib2, iclass 39, count 0 2006.211.07:31:10.50#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:31:10.50#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:31:10.50#ibcon#[27=USB\r\n] 2006.211.07:31:10.50#ibcon#*before write, iclass 39, count 0 2006.211.07:31:10.50#ibcon#enter sib2, iclass 39, count 0 2006.211.07:31:10.50#ibcon#flushed, iclass 39, count 0 2006.211.07:31:10.50#ibcon#about to write, iclass 39, count 0 2006.211.07:31:10.50#ibcon#wrote, iclass 39, count 0 2006.211.07:31:10.50#ibcon#about to read 3, iclass 39, count 0 2006.211.07:31:10.53#ibcon#read 3, iclass 39, count 0 2006.211.07:31:10.53#ibcon#about to read 4, iclass 39, count 0 2006.211.07:31:10.53#ibcon#read 4, iclass 39, count 0 2006.211.07:31:10.53#ibcon#about to read 5, iclass 39, count 0 2006.211.07:31:10.53#ibcon#read 5, iclass 39, count 0 2006.211.07:31:10.53#ibcon#about to read 6, iclass 39, count 0 2006.211.07:31:10.53#ibcon#read 6, iclass 39, count 0 2006.211.07:31:10.53#ibcon#end of sib2, iclass 39, count 0 2006.211.07:31:10.53#ibcon#*after write, iclass 39, count 0 2006.211.07:31:10.53#ibcon#*before return 0, iclass 39, count 0 2006.211.07:31:10.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:31:10.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:31:10.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:31:10.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:31:10.53$vc4f8/vblo=2,640.99 2006.211.07:31:10.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:31:10.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:31:10.53#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:10.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:10.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:10.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:10.53#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:31:10.53#ibcon#first serial, iclass 3, count 0 2006.211.07:31:10.53#ibcon#enter sib2, iclass 3, count 0 2006.211.07:31:10.53#ibcon#flushed, iclass 3, count 0 2006.211.07:31:10.53#ibcon#about to write, iclass 3, count 0 2006.211.07:31:10.53#ibcon#wrote, iclass 3, count 0 2006.211.07:31:10.53#ibcon#about to read 3, iclass 3, count 0 2006.211.07:31:10.55#ibcon#read 3, iclass 3, count 0 2006.211.07:31:10.55#ibcon#about to read 4, iclass 3, count 0 2006.211.07:31:10.55#ibcon#read 4, iclass 3, count 0 2006.211.07:31:10.55#ibcon#about to read 5, iclass 3, count 0 2006.211.07:31:10.55#ibcon#read 5, iclass 3, count 0 2006.211.07:31:10.55#ibcon#about to read 6, iclass 3, count 0 2006.211.07:31:10.55#ibcon#read 6, iclass 3, count 0 2006.211.07:31:10.55#ibcon#end of sib2, iclass 3, count 0 2006.211.07:31:10.55#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:31:10.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:31:10.55#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:31:10.55#ibcon#*before write, iclass 3, count 0 2006.211.07:31:10.55#ibcon#enter sib2, iclass 3, count 0 2006.211.07:31:10.55#ibcon#flushed, iclass 3, count 0 2006.211.07:31:10.55#ibcon#about to write, iclass 3, count 0 2006.211.07:31:10.55#ibcon#wrote, iclass 3, count 0 2006.211.07:31:10.55#ibcon#about to read 3, iclass 3, count 0 2006.211.07:31:10.59#ibcon#read 3, iclass 3, count 0 2006.211.07:31:10.59#ibcon#about to read 4, iclass 3, count 0 2006.211.07:31:10.59#ibcon#read 4, iclass 3, count 0 2006.211.07:31:10.59#ibcon#about to read 5, iclass 3, count 0 2006.211.07:31:10.59#ibcon#read 5, iclass 3, count 0 2006.211.07:31:10.59#ibcon#about to read 6, iclass 3, count 0 2006.211.07:31:10.59#ibcon#read 6, iclass 3, count 0 2006.211.07:31:10.59#ibcon#end of sib2, iclass 3, count 0 2006.211.07:31:10.59#ibcon#*after write, iclass 3, count 0 2006.211.07:31:10.59#ibcon#*before return 0, iclass 3, count 0 2006.211.07:31:10.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:10.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:31:10.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:31:10.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:31:10.59$vc4f8/vb=2,4 2006.211.07:31:10.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:31:10.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:31:10.59#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:10.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:10.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:10.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:10.65#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:31:10.65#ibcon#first serial, iclass 5, count 2 2006.211.07:31:10.65#ibcon#enter sib2, iclass 5, count 2 2006.211.07:31:10.65#ibcon#flushed, iclass 5, count 2 2006.211.07:31:10.65#ibcon#about to write, iclass 5, count 2 2006.211.07:31:10.65#ibcon#wrote, iclass 5, count 2 2006.211.07:31:10.65#ibcon#about to read 3, iclass 5, count 2 2006.211.07:31:10.67#ibcon#read 3, iclass 5, count 2 2006.211.07:31:10.67#ibcon#about to read 4, iclass 5, count 2 2006.211.07:31:10.67#ibcon#read 4, iclass 5, count 2 2006.211.07:31:10.67#ibcon#about to read 5, iclass 5, count 2 2006.211.07:31:10.67#ibcon#read 5, iclass 5, count 2 2006.211.07:31:10.67#ibcon#about to read 6, iclass 5, count 2 2006.211.07:31:10.67#ibcon#read 6, iclass 5, count 2 2006.211.07:31:10.67#ibcon#end of sib2, iclass 5, count 2 2006.211.07:31:10.67#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:31:10.67#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:31:10.67#ibcon#[27=AT02-04\r\n] 2006.211.07:31:10.67#ibcon#*before write, iclass 5, count 2 2006.211.07:31:10.67#ibcon#enter sib2, iclass 5, count 2 2006.211.07:31:10.67#ibcon#flushed, iclass 5, count 2 2006.211.07:31:10.67#ibcon#about to write, iclass 5, count 2 2006.211.07:31:10.67#ibcon#wrote, iclass 5, count 2 2006.211.07:31:10.67#ibcon#about to read 3, iclass 5, count 2 2006.211.07:31:10.70#ibcon#read 3, iclass 5, count 2 2006.211.07:31:10.70#ibcon#about to read 4, iclass 5, count 2 2006.211.07:31:10.70#ibcon#read 4, iclass 5, count 2 2006.211.07:31:10.70#ibcon#about to read 5, iclass 5, count 2 2006.211.07:31:10.70#ibcon#read 5, iclass 5, count 2 2006.211.07:31:10.70#ibcon#about to read 6, iclass 5, count 2 2006.211.07:31:10.70#ibcon#read 6, iclass 5, count 2 2006.211.07:31:10.70#ibcon#end of sib2, iclass 5, count 2 2006.211.07:31:10.70#ibcon#*after write, iclass 5, count 2 2006.211.07:31:10.70#ibcon#*before return 0, iclass 5, count 2 2006.211.07:31:10.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:10.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:31:10.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:31:10.70#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:10.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:10.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:10.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:10.82#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:31:10.82#ibcon#first serial, iclass 5, count 0 2006.211.07:31:10.82#ibcon#enter sib2, iclass 5, count 0 2006.211.07:31:10.82#ibcon#flushed, iclass 5, count 0 2006.211.07:31:10.82#ibcon#about to write, iclass 5, count 0 2006.211.07:31:10.82#ibcon#wrote, iclass 5, count 0 2006.211.07:31:10.82#ibcon#about to read 3, iclass 5, count 0 2006.211.07:31:10.84#ibcon#read 3, iclass 5, count 0 2006.211.07:31:10.84#ibcon#about to read 4, iclass 5, count 0 2006.211.07:31:10.84#ibcon#read 4, iclass 5, count 0 2006.211.07:31:10.84#ibcon#about to read 5, iclass 5, count 0 2006.211.07:31:10.84#ibcon#read 5, iclass 5, count 0 2006.211.07:31:10.84#ibcon#about to read 6, iclass 5, count 0 2006.211.07:31:10.84#ibcon#read 6, iclass 5, count 0 2006.211.07:31:10.84#ibcon#end of sib2, iclass 5, count 0 2006.211.07:31:10.84#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:31:10.84#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:31:10.84#ibcon#[27=USB\r\n] 2006.211.07:31:10.84#ibcon#*before write, iclass 5, count 0 2006.211.07:31:10.84#ibcon#enter sib2, iclass 5, count 0 2006.211.07:31:10.84#ibcon#flushed, iclass 5, count 0 2006.211.07:31:10.84#ibcon#about to write, iclass 5, count 0 2006.211.07:31:10.84#ibcon#wrote, iclass 5, count 0 2006.211.07:31:10.84#ibcon#about to read 3, iclass 5, count 0 2006.211.07:31:10.87#ibcon#read 3, iclass 5, count 0 2006.211.07:31:10.87#ibcon#about to read 4, iclass 5, count 0 2006.211.07:31:10.87#ibcon#read 4, iclass 5, count 0 2006.211.07:31:10.87#ibcon#about to read 5, iclass 5, count 0 2006.211.07:31:10.87#ibcon#read 5, iclass 5, count 0 2006.211.07:31:10.87#ibcon#about to read 6, iclass 5, count 0 2006.211.07:31:10.87#ibcon#read 6, iclass 5, count 0 2006.211.07:31:10.87#ibcon#end of sib2, iclass 5, count 0 2006.211.07:31:10.87#ibcon#*after write, iclass 5, count 0 2006.211.07:31:10.87#ibcon#*before return 0, iclass 5, count 0 2006.211.07:31:10.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:10.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:31:10.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:31:10.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:31:10.87$vc4f8/vblo=3,656.99 2006.211.07:31:10.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:31:10.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:31:10.87#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:10.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:10.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:10.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:10.87#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:31:10.87#ibcon#first serial, iclass 7, count 0 2006.211.07:31:10.87#ibcon#enter sib2, iclass 7, count 0 2006.211.07:31:10.87#ibcon#flushed, iclass 7, count 0 2006.211.07:31:10.87#ibcon#about to write, iclass 7, count 0 2006.211.07:31:10.87#ibcon#wrote, iclass 7, count 0 2006.211.07:31:10.87#ibcon#about to read 3, iclass 7, count 0 2006.211.07:31:10.89#ibcon#read 3, iclass 7, count 0 2006.211.07:31:10.89#ibcon#about to read 4, iclass 7, count 0 2006.211.07:31:10.89#ibcon#read 4, iclass 7, count 0 2006.211.07:31:10.89#ibcon#about to read 5, iclass 7, count 0 2006.211.07:31:10.89#ibcon#read 5, iclass 7, count 0 2006.211.07:31:10.89#ibcon#about to read 6, iclass 7, count 0 2006.211.07:31:10.89#ibcon#read 6, iclass 7, count 0 2006.211.07:31:10.89#ibcon#end of sib2, iclass 7, count 0 2006.211.07:31:10.89#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:31:10.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:31:10.89#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:31:10.89#ibcon#*before write, iclass 7, count 0 2006.211.07:31:10.89#ibcon#enter sib2, iclass 7, count 0 2006.211.07:31:10.89#ibcon#flushed, iclass 7, count 0 2006.211.07:31:10.89#ibcon#about to write, iclass 7, count 0 2006.211.07:31:10.89#ibcon#wrote, iclass 7, count 0 2006.211.07:31:10.89#ibcon#about to read 3, iclass 7, count 0 2006.211.07:31:10.93#ibcon#read 3, iclass 7, count 0 2006.211.07:31:10.93#ibcon#about to read 4, iclass 7, count 0 2006.211.07:31:10.93#ibcon#read 4, iclass 7, count 0 2006.211.07:31:10.93#ibcon#about to read 5, iclass 7, count 0 2006.211.07:31:10.93#ibcon#read 5, iclass 7, count 0 2006.211.07:31:10.93#ibcon#about to read 6, iclass 7, count 0 2006.211.07:31:10.93#ibcon#read 6, iclass 7, count 0 2006.211.07:31:10.93#ibcon#end of sib2, iclass 7, count 0 2006.211.07:31:10.93#ibcon#*after write, iclass 7, count 0 2006.211.07:31:10.93#ibcon#*before return 0, iclass 7, count 0 2006.211.07:31:10.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:10.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:31:10.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:31:10.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:31:10.93$vc4f8/vb=3,3 2006.211.07:31:10.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:31:10.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:31:10.93#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:10.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:10.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:10.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:10.99#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:31:10.99#ibcon#first serial, iclass 11, count 2 2006.211.07:31:10.99#ibcon#enter sib2, iclass 11, count 2 2006.211.07:31:10.99#ibcon#flushed, iclass 11, count 2 2006.211.07:31:10.99#ibcon#about to write, iclass 11, count 2 2006.211.07:31:10.99#ibcon#wrote, iclass 11, count 2 2006.211.07:31:10.99#ibcon#about to read 3, iclass 11, count 2 2006.211.07:31:11.01#ibcon#read 3, iclass 11, count 2 2006.211.07:31:11.01#ibcon#about to read 4, iclass 11, count 2 2006.211.07:31:11.01#ibcon#read 4, iclass 11, count 2 2006.211.07:31:11.01#ibcon#about to read 5, iclass 11, count 2 2006.211.07:31:11.01#ibcon#read 5, iclass 11, count 2 2006.211.07:31:11.01#ibcon#about to read 6, iclass 11, count 2 2006.211.07:31:11.01#ibcon#read 6, iclass 11, count 2 2006.211.07:31:11.01#ibcon#end of sib2, iclass 11, count 2 2006.211.07:31:11.01#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:31:11.01#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:31:11.01#ibcon#[27=AT03-03\r\n] 2006.211.07:31:11.01#ibcon#*before write, iclass 11, count 2 2006.211.07:31:11.01#ibcon#enter sib2, iclass 11, count 2 2006.211.07:31:11.01#ibcon#flushed, iclass 11, count 2 2006.211.07:31:11.01#ibcon#about to write, iclass 11, count 2 2006.211.07:31:11.01#ibcon#wrote, iclass 11, count 2 2006.211.07:31:11.01#ibcon#about to read 3, iclass 11, count 2 2006.211.07:31:11.04#ibcon#read 3, iclass 11, count 2 2006.211.07:31:11.04#ibcon#about to read 4, iclass 11, count 2 2006.211.07:31:11.04#ibcon#read 4, iclass 11, count 2 2006.211.07:31:11.04#ibcon#about to read 5, iclass 11, count 2 2006.211.07:31:11.04#ibcon#read 5, iclass 11, count 2 2006.211.07:31:11.04#ibcon#about to read 6, iclass 11, count 2 2006.211.07:31:11.04#ibcon#read 6, iclass 11, count 2 2006.211.07:31:11.04#ibcon#end of sib2, iclass 11, count 2 2006.211.07:31:11.04#ibcon#*after write, iclass 11, count 2 2006.211.07:31:11.04#ibcon#*before return 0, iclass 11, count 2 2006.211.07:31:11.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:11.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:31:11.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:31:11.04#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:11.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:11.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:11.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:11.16#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:31:11.16#ibcon#first serial, iclass 11, count 0 2006.211.07:31:11.16#ibcon#enter sib2, iclass 11, count 0 2006.211.07:31:11.16#ibcon#flushed, iclass 11, count 0 2006.211.07:31:11.16#ibcon#about to write, iclass 11, count 0 2006.211.07:31:11.16#ibcon#wrote, iclass 11, count 0 2006.211.07:31:11.16#ibcon#about to read 3, iclass 11, count 0 2006.211.07:31:11.18#ibcon#read 3, iclass 11, count 0 2006.211.07:31:11.18#ibcon#about to read 4, iclass 11, count 0 2006.211.07:31:11.18#ibcon#read 4, iclass 11, count 0 2006.211.07:31:11.18#ibcon#about to read 5, iclass 11, count 0 2006.211.07:31:11.18#ibcon#read 5, iclass 11, count 0 2006.211.07:31:11.18#ibcon#about to read 6, iclass 11, count 0 2006.211.07:31:11.18#ibcon#read 6, iclass 11, count 0 2006.211.07:31:11.18#ibcon#end of sib2, iclass 11, count 0 2006.211.07:31:11.18#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:31:11.18#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:31:11.18#ibcon#[27=USB\r\n] 2006.211.07:31:11.18#ibcon#*before write, iclass 11, count 0 2006.211.07:31:11.18#ibcon#enter sib2, iclass 11, count 0 2006.211.07:31:11.18#ibcon#flushed, iclass 11, count 0 2006.211.07:31:11.18#ibcon#about to write, iclass 11, count 0 2006.211.07:31:11.18#ibcon#wrote, iclass 11, count 0 2006.211.07:31:11.18#ibcon#about to read 3, iclass 11, count 0 2006.211.07:31:11.21#ibcon#read 3, iclass 11, count 0 2006.211.07:31:11.21#ibcon#about to read 4, iclass 11, count 0 2006.211.07:31:11.21#ibcon#read 4, iclass 11, count 0 2006.211.07:31:11.21#ibcon#about to read 5, iclass 11, count 0 2006.211.07:31:11.21#ibcon#read 5, iclass 11, count 0 2006.211.07:31:11.21#ibcon#about to read 6, iclass 11, count 0 2006.211.07:31:11.21#ibcon#read 6, iclass 11, count 0 2006.211.07:31:11.21#ibcon#end of sib2, iclass 11, count 0 2006.211.07:31:11.21#ibcon#*after write, iclass 11, count 0 2006.211.07:31:11.21#ibcon#*before return 0, iclass 11, count 0 2006.211.07:31:11.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:11.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:31:11.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:31:11.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:31:11.21$vc4f8/vblo=4,712.99 2006.211.07:31:11.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:31:11.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:31:11.21#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:11.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:11.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:11.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:11.21#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:31:11.21#ibcon#first serial, iclass 13, count 0 2006.211.07:31:11.21#ibcon#enter sib2, iclass 13, count 0 2006.211.07:31:11.21#ibcon#flushed, iclass 13, count 0 2006.211.07:31:11.21#ibcon#about to write, iclass 13, count 0 2006.211.07:31:11.21#ibcon#wrote, iclass 13, count 0 2006.211.07:31:11.21#ibcon#about to read 3, iclass 13, count 0 2006.211.07:31:11.23#ibcon#read 3, iclass 13, count 0 2006.211.07:31:11.23#ibcon#about to read 4, iclass 13, count 0 2006.211.07:31:11.23#ibcon#read 4, iclass 13, count 0 2006.211.07:31:11.23#ibcon#about to read 5, iclass 13, count 0 2006.211.07:31:11.23#ibcon#read 5, iclass 13, count 0 2006.211.07:31:11.23#ibcon#about to read 6, iclass 13, count 0 2006.211.07:31:11.23#ibcon#read 6, iclass 13, count 0 2006.211.07:31:11.23#ibcon#end of sib2, iclass 13, count 0 2006.211.07:31:11.23#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:31:11.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:31:11.23#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:31:11.23#ibcon#*before write, iclass 13, count 0 2006.211.07:31:11.23#ibcon#enter sib2, iclass 13, count 0 2006.211.07:31:11.23#ibcon#flushed, iclass 13, count 0 2006.211.07:31:11.23#ibcon#about to write, iclass 13, count 0 2006.211.07:31:11.23#ibcon#wrote, iclass 13, count 0 2006.211.07:31:11.23#ibcon#about to read 3, iclass 13, count 0 2006.211.07:31:11.27#ibcon#read 3, iclass 13, count 0 2006.211.07:31:11.27#ibcon#about to read 4, iclass 13, count 0 2006.211.07:31:11.27#ibcon#read 4, iclass 13, count 0 2006.211.07:31:11.27#ibcon#about to read 5, iclass 13, count 0 2006.211.07:31:11.27#ibcon#read 5, iclass 13, count 0 2006.211.07:31:11.27#ibcon#about to read 6, iclass 13, count 0 2006.211.07:31:11.27#ibcon#read 6, iclass 13, count 0 2006.211.07:31:11.27#ibcon#end of sib2, iclass 13, count 0 2006.211.07:31:11.27#ibcon#*after write, iclass 13, count 0 2006.211.07:31:11.27#ibcon#*before return 0, iclass 13, count 0 2006.211.07:31:11.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:11.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:31:11.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:31:11.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:31:11.27$vc4f8/vb=4,3 2006.211.07:31:11.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.07:31:11.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.07:31:11.27#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:11.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:11.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:11.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:11.33#ibcon#enter wrdev, iclass 15, count 2 2006.211.07:31:11.33#ibcon#first serial, iclass 15, count 2 2006.211.07:31:11.33#ibcon#enter sib2, iclass 15, count 2 2006.211.07:31:11.33#ibcon#flushed, iclass 15, count 2 2006.211.07:31:11.33#ibcon#about to write, iclass 15, count 2 2006.211.07:31:11.33#ibcon#wrote, iclass 15, count 2 2006.211.07:31:11.33#ibcon#about to read 3, iclass 15, count 2 2006.211.07:31:11.35#ibcon#read 3, iclass 15, count 2 2006.211.07:31:11.35#ibcon#about to read 4, iclass 15, count 2 2006.211.07:31:11.35#ibcon#read 4, iclass 15, count 2 2006.211.07:31:11.35#ibcon#about to read 5, iclass 15, count 2 2006.211.07:31:11.35#ibcon#read 5, iclass 15, count 2 2006.211.07:31:11.35#ibcon#about to read 6, iclass 15, count 2 2006.211.07:31:11.35#ibcon#read 6, iclass 15, count 2 2006.211.07:31:11.35#ibcon#end of sib2, iclass 15, count 2 2006.211.07:31:11.35#ibcon#*mode == 0, iclass 15, count 2 2006.211.07:31:11.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.07:31:11.35#ibcon#[27=AT04-03\r\n] 2006.211.07:31:11.35#ibcon#*before write, iclass 15, count 2 2006.211.07:31:11.35#ibcon#enter sib2, iclass 15, count 2 2006.211.07:31:11.35#ibcon#flushed, iclass 15, count 2 2006.211.07:31:11.35#ibcon#about to write, iclass 15, count 2 2006.211.07:31:11.35#ibcon#wrote, iclass 15, count 2 2006.211.07:31:11.35#ibcon#about to read 3, iclass 15, count 2 2006.211.07:31:11.38#ibcon#read 3, iclass 15, count 2 2006.211.07:31:11.38#ibcon#about to read 4, iclass 15, count 2 2006.211.07:31:11.38#ibcon#read 4, iclass 15, count 2 2006.211.07:31:11.38#ibcon#about to read 5, iclass 15, count 2 2006.211.07:31:11.38#ibcon#read 5, iclass 15, count 2 2006.211.07:31:11.38#ibcon#about to read 6, iclass 15, count 2 2006.211.07:31:11.38#ibcon#read 6, iclass 15, count 2 2006.211.07:31:11.38#ibcon#end of sib2, iclass 15, count 2 2006.211.07:31:11.38#ibcon#*after write, iclass 15, count 2 2006.211.07:31:11.38#ibcon#*before return 0, iclass 15, count 2 2006.211.07:31:11.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:11.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:31:11.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.07:31:11.38#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:11.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:11.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:11.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:11.50#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:31:11.50#ibcon#first serial, iclass 15, count 0 2006.211.07:31:11.50#ibcon#enter sib2, iclass 15, count 0 2006.211.07:31:11.50#ibcon#flushed, iclass 15, count 0 2006.211.07:31:11.50#ibcon#about to write, iclass 15, count 0 2006.211.07:31:11.50#ibcon#wrote, iclass 15, count 0 2006.211.07:31:11.50#ibcon#about to read 3, iclass 15, count 0 2006.211.07:31:11.52#ibcon#read 3, iclass 15, count 0 2006.211.07:31:11.52#ibcon#about to read 4, iclass 15, count 0 2006.211.07:31:11.52#ibcon#read 4, iclass 15, count 0 2006.211.07:31:11.52#ibcon#about to read 5, iclass 15, count 0 2006.211.07:31:11.52#ibcon#read 5, iclass 15, count 0 2006.211.07:31:11.52#ibcon#about to read 6, iclass 15, count 0 2006.211.07:31:11.52#ibcon#read 6, iclass 15, count 0 2006.211.07:31:11.52#ibcon#end of sib2, iclass 15, count 0 2006.211.07:31:11.52#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:31:11.52#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:31:11.52#ibcon#[27=USB\r\n] 2006.211.07:31:11.52#ibcon#*before write, iclass 15, count 0 2006.211.07:31:11.52#ibcon#enter sib2, iclass 15, count 0 2006.211.07:31:11.52#ibcon#flushed, iclass 15, count 0 2006.211.07:31:11.52#ibcon#about to write, iclass 15, count 0 2006.211.07:31:11.52#ibcon#wrote, iclass 15, count 0 2006.211.07:31:11.52#ibcon#about to read 3, iclass 15, count 0 2006.211.07:31:11.55#ibcon#read 3, iclass 15, count 0 2006.211.07:31:11.55#ibcon#about to read 4, iclass 15, count 0 2006.211.07:31:11.55#ibcon#read 4, iclass 15, count 0 2006.211.07:31:11.55#ibcon#about to read 5, iclass 15, count 0 2006.211.07:31:11.55#ibcon#read 5, iclass 15, count 0 2006.211.07:31:11.55#ibcon#about to read 6, iclass 15, count 0 2006.211.07:31:11.55#ibcon#read 6, iclass 15, count 0 2006.211.07:31:11.55#ibcon#end of sib2, iclass 15, count 0 2006.211.07:31:11.55#ibcon#*after write, iclass 15, count 0 2006.211.07:31:11.55#ibcon#*before return 0, iclass 15, count 0 2006.211.07:31:11.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:11.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:31:11.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:31:11.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:31:11.55$vc4f8/vblo=5,744.99 2006.211.07:31:11.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.07:31:11.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.07:31:11.55#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:11.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:11.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:11.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:11.55#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:31:11.55#ibcon#first serial, iclass 17, count 0 2006.211.07:31:11.55#ibcon#enter sib2, iclass 17, count 0 2006.211.07:31:11.55#ibcon#flushed, iclass 17, count 0 2006.211.07:31:11.55#ibcon#about to write, iclass 17, count 0 2006.211.07:31:11.55#ibcon#wrote, iclass 17, count 0 2006.211.07:31:11.55#ibcon#about to read 3, iclass 17, count 0 2006.211.07:31:11.57#ibcon#read 3, iclass 17, count 0 2006.211.07:31:11.57#ibcon#about to read 4, iclass 17, count 0 2006.211.07:31:11.57#ibcon#read 4, iclass 17, count 0 2006.211.07:31:11.57#ibcon#about to read 5, iclass 17, count 0 2006.211.07:31:11.57#ibcon#read 5, iclass 17, count 0 2006.211.07:31:11.57#ibcon#about to read 6, iclass 17, count 0 2006.211.07:31:11.57#ibcon#read 6, iclass 17, count 0 2006.211.07:31:11.57#ibcon#end of sib2, iclass 17, count 0 2006.211.07:31:11.57#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:31:11.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:31:11.57#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:31:11.57#ibcon#*before write, iclass 17, count 0 2006.211.07:31:11.57#ibcon#enter sib2, iclass 17, count 0 2006.211.07:31:11.57#ibcon#flushed, iclass 17, count 0 2006.211.07:31:11.57#ibcon#about to write, iclass 17, count 0 2006.211.07:31:11.57#ibcon#wrote, iclass 17, count 0 2006.211.07:31:11.57#ibcon#about to read 3, iclass 17, count 0 2006.211.07:31:11.61#ibcon#read 3, iclass 17, count 0 2006.211.07:31:11.61#ibcon#about to read 4, iclass 17, count 0 2006.211.07:31:11.61#ibcon#read 4, iclass 17, count 0 2006.211.07:31:11.61#ibcon#about to read 5, iclass 17, count 0 2006.211.07:31:11.61#ibcon#read 5, iclass 17, count 0 2006.211.07:31:11.61#ibcon#about to read 6, iclass 17, count 0 2006.211.07:31:11.61#ibcon#read 6, iclass 17, count 0 2006.211.07:31:11.61#ibcon#end of sib2, iclass 17, count 0 2006.211.07:31:11.61#ibcon#*after write, iclass 17, count 0 2006.211.07:31:11.61#ibcon#*before return 0, iclass 17, count 0 2006.211.07:31:11.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:11.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:31:11.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:31:11.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:31:11.61$vc4f8/vb=5,3 2006.211.07:31:11.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.07:31:11.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.07:31:11.61#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:11.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:11.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:11.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:11.67#ibcon#enter wrdev, iclass 19, count 2 2006.211.07:31:11.67#ibcon#first serial, iclass 19, count 2 2006.211.07:31:11.67#ibcon#enter sib2, iclass 19, count 2 2006.211.07:31:11.67#ibcon#flushed, iclass 19, count 2 2006.211.07:31:11.67#ibcon#about to write, iclass 19, count 2 2006.211.07:31:11.67#ibcon#wrote, iclass 19, count 2 2006.211.07:31:11.67#ibcon#about to read 3, iclass 19, count 2 2006.211.07:31:11.69#ibcon#read 3, iclass 19, count 2 2006.211.07:31:11.69#ibcon#about to read 4, iclass 19, count 2 2006.211.07:31:11.69#ibcon#read 4, iclass 19, count 2 2006.211.07:31:11.69#ibcon#about to read 5, iclass 19, count 2 2006.211.07:31:11.69#ibcon#read 5, iclass 19, count 2 2006.211.07:31:11.69#ibcon#about to read 6, iclass 19, count 2 2006.211.07:31:11.69#ibcon#read 6, iclass 19, count 2 2006.211.07:31:11.69#ibcon#end of sib2, iclass 19, count 2 2006.211.07:31:11.69#ibcon#*mode == 0, iclass 19, count 2 2006.211.07:31:11.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.07:31:11.69#ibcon#[27=AT05-03\r\n] 2006.211.07:31:11.69#ibcon#*before write, iclass 19, count 2 2006.211.07:31:11.69#ibcon#enter sib2, iclass 19, count 2 2006.211.07:31:11.69#ibcon#flushed, iclass 19, count 2 2006.211.07:31:11.69#ibcon#about to write, iclass 19, count 2 2006.211.07:31:11.69#ibcon#wrote, iclass 19, count 2 2006.211.07:31:11.69#ibcon#about to read 3, iclass 19, count 2 2006.211.07:31:11.72#ibcon#read 3, iclass 19, count 2 2006.211.07:31:11.72#ibcon#about to read 4, iclass 19, count 2 2006.211.07:31:11.72#ibcon#read 4, iclass 19, count 2 2006.211.07:31:11.72#ibcon#about to read 5, iclass 19, count 2 2006.211.07:31:11.72#ibcon#read 5, iclass 19, count 2 2006.211.07:31:11.72#ibcon#about to read 6, iclass 19, count 2 2006.211.07:31:11.72#ibcon#read 6, iclass 19, count 2 2006.211.07:31:11.72#ibcon#end of sib2, iclass 19, count 2 2006.211.07:31:11.72#ibcon#*after write, iclass 19, count 2 2006.211.07:31:11.72#ibcon#*before return 0, iclass 19, count 2 2006.211.07:31:11.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:11.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:31:11.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.07:31:11.72#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:11.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:11.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:11.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:11.84#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:31:11.84#ibcon#first serial, iclass 19, count 0 2006.211.07:31:11.84#ibcon#enter sib2, iclass 19, count 0 2006.211.07:31:11.84#ibcon#flushed, iclass 19, count 0 2006.211.07:31:11.84#ibcon#about to write, iclass 19, count 0 2006.211.07:31:11.84#ibcon#wrote, iclass 19, count 0 2006.211.07:31:11.84#ibcon#about to read 3, iclass 19, count 0 2006.211.07:31:11.86#ibcon#read 3, iclass 19, count 0 2006.211.07:31:11.86#ibcon#about to read 4, iclass 19, count 0 2006.211.07:31:11.86#ibcon#read 4, iclass 19, count 0 2006.211.07:31:11.86#ibcon#about to read 5, iclass 19, count 0 2006.211.07:31:11.86#ibcon#read 5, iclass 19, count 0 2006.211.07:31:11.86#ibcon#about to read 6, iclass 19, count 0 2006.211.07:31:11.86#ibcon#read 6, iclass 19, count 0 2006.211.07:31:11.86#ibcon#end of sib2, iclass 19, count 0 2006.211.07:31:11.86#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:31:11.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:31:11.86#ibcon#[27=USB\r\n] 2006.211.07:31:11.86#ibcon#*before write, iclass 19, count 0 2006.211.07:31:11.86#ibcon#enter sib2, iclass 19, count 0 2006.211.07:31:11.86#ibcon#flushed, iclass 19, count 0 2006.211.07:31:11.86#ibcon#about to write, iclass 19, count 0 2006.211.07:31:11.86#ibcon#wrote, iclass 19, count 0 2006.211.07:31:11.86#ibcon#about to read 3, iclass 19, count 0 2006.211.07:31:11.89#ibcon#read 3, iclass 19, count 0 2006.211.07:31:11.89#ibcon#about to read 4, iclass 19, count 0 2006.211.07:31:11.89#ibcon#read 4, iclass 19, count 0 2006.211.07:31:11.89#ibcon#about to read 5, iclass 19, count 0 2006.211.07:31:11.89#ibcon#read 5, iclass 19, count 0 2006.211.07:31:11.89#ibcon#about to read 6, iclass 19, count 0 2006.211.07:31:11.89#ibcon#read 6, iclass 19, count 0 2006.211.07:31:11.89#ibcon#end of sib2, iclass 19, count 0 2006.211.07:31:11.89#ibcon#*after write, iclass 19, count 0 2006.211.07:31:11.89#ibcon#*before return 0, iclass 19, count 0 2006.211.07:31:11.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:11.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:31:11.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:31:11.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:31:11.89$vc4f8/vblo=6,752.99 2006.211.07:31:11.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.07:31:11.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.07:31:11.89#ibcon#ireg 17 cls_cnt 0 2006.211.07:31:11.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:11.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:11.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:11.89#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:31:11.89#ibcon#first serial, iclass 21, count 0 2006.211.07:31:11.89#ibcon#enter sib2, iclass 21, count 0 2006.211.07:31:11.89#ibcon#flushed, iclass 21, count 0 2006.211.07:31:11.89#ibcon#about to write, iclass 21, count 0 2006.211.07:31:11.89#ibcon#wrote, iclass 21, count 0 2006.211.07:31:11.89#ibcon#about to read 3, iclass 21, count 0 2006.211.07:31:11.91#ibcon#read 3, iclass 21, count 0 2006.211.07:31:11.91#ibcon#about to read 4, iclass 21, count 0 2006.211.07:31:11.91#ibcon#read 4, iclass 21, count 0 2006.211.07:31:11.91#ibcon#about to read 5, iclass 21, count 0 2006.211.07:31:11.91#ibcon#read 5, iclass 21, count 0 2006.211.07:31:11.91#ibcon#about to read 6, iclass 21, count 0 2006.211.07:31:11.91#ibcon#read 6, iclass 21, count 0 2006.211.07:31:11.91#ibcon#end of sib2, iclass 21, count 0 2006.211.07:31:11.91#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:31:11.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:31:11.91#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:31:11.91#ibcon#*before write, iclass 21, count 0 2006.211.07:31:11.91#ibcon#enter sib2, iclass 21, count 0 2006.211.07:31:11.91#ibcon#flushed, iclass 21, count 0 2006.211.07:31:11.91#ibcon#about to write, iclass 21, count 0 2006.211.07:31:11.91#ibcon#wrote, iclass 21, count 0 2006.211.07:31:11.91#ibcon#about to read 3, iclass 21, count 0 2006.211.07:31:11.95#ibcon#read 3, iclass 21, count 0 2006.211.07:31:11.95#ibcon#about to read 4, iclass 21, count 0 2006.211.07:31:11.95#ibcon#read 4, iclass 21, count 0 2006.211.07:31:11.95#ibcon#about to read 5, iclass 21, count 0 2006.211.07:31:11.95#ibcon#read 5, iclass 21, count 0 2006.211.07:31:11.95#ibcon#about to read 6, iclass 21, count 0 2006.211.07:31:11.95#ibcon#read 6, iclass 21, count 0 2006.211.07:31:11.95#ibcon#end of sib2, iclass 21, count 0 2006.211.07:31:11.95#ibcon#*after write, iclass 21, count 0 2006.211.07:31:11.95#ibcon#*before return 0, iclass 21, count 0 2006.211.07:31:11.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:11.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:31:11.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:31:11.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:31:11.95$vc4f8/vb=6,3 2006.211.07:31:11.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.07:31:11.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.07:31:11.95#ibcon#ireg 11 cls_cnt 2 2006.211.07:31:11.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:12.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:12.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:12.01#ibcon#enter wrdev, iclass 23, count 2 2006.211.07:31:12.01#ibcon#first serial, iclass 23, count 2 2006.211.07:31:12.01#ibcon#enter sib2, iclass 23, count 2 2006.211.07:31:12.01#ibcon#flushed, iclass 23, count 2 2006.211.07:31:12.01#ibcon#about to write, iclass 23, count 2 2006.211.07:31:12.01#ibcon#wrote, iclass 23, count 2 2006.211.07:31:12.01#ibcon#about to read 3, iclass 23, count 2 2006.211.07:31:12.03#ibcon#read 3, iclass 23, count 2 2006.211.07:31:12.03#ibcon#about to read 4, iclass 23, count 2 2006.211.07:31:12.03#ibcon#read 4, iclass 23, count 2 2006.211.07:31:12.03#ibcon#about to read 5, iclass 23, count 2 2006.211.07:31:12.03#ibcon#read 5, iclass 23, count 2 2006.211.07:31:12.03#ibcon#about to read 6, iclass 23, count 2 2006.211.07:31:12.03#ibcon#read 6, iclass 23, count 2 2006.211.07:31:12.03#ibcon#end of sib2, iclass 23, count 2 2006.211.07:31:12.03#ibcon#*mode == 0, iclass 23, count 2 2006.211.07:31:12.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.07:31:12.03#ibcon#[27=AT06-03\r\n] 2006.211.07:31:12.03#ibcon#*before write, iclass 23, count 2 2006.211.07:31:12.03#ibcon#enter sib2, iclass 23, count 2 2006.211.07:31:12.03#ibcon#flushed, iclass 23, count 2 2006.211.07:31:12.03#ibcon#about to write, iclass 23, count 2 2006.211.07:31:12.03#ibcon#wrote, iclass 23, count 2 2006.211.07:31:12.03#ibcon#about to read 3, iclass 23, count 2 2006.211.07:31:12.06#ibcon#read 3, iclass 23, count 2 2006.211.07:31:12.06#ibcon#about to read 4, iclass 23, count 2 2006.211.07:31:12.06#ibcon#read 4, iclass 23, count 2 2006.211.07:31:12.06#ibcon#about to read 5, iclass 23, count 2 2006.211.07:31:12.06#ibcon#read 5, iclass 23, count 2 2006.211.07:31:12.06#ibcon#about to read 6, iclass 23, count 2 2006.211.07:31:12.06#ibcon#read 6, iclass 23, count 2 2006.211.07:31:12.06#ibcon#end of sib2, iclass 23, count 2 2006.211.07:31:12.06#ibcon#*after write, iclass 23, count 2 2006.211.07:31:12.06#ibcon#*before return 0, iclass 23, count 2 2006.211.07:31:12.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:12.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:31:12.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.07:31:12.06#ibcon#ireg 7 cls_cnt 0 2006.211.07:31:12.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:12.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:12.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:12.18#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:31:12.18#ibcon#first serial, iclass 23, count 0 2006.211.07:31:12.18#ibcon#enter sib2, iclass 23, count 0 2006.211.07:31:12.18#ibcon#flushed, iclass 23, count 0 2006.211.07:31:12.18#ibcon#about to write, iclass 23, count 0 2006.211.07:31:12.18#ibcon#wrote, iclass 23, count 0 2006.211.07:31:12.18#ibcon#about to read 3, iclass 23, count 0 2006.211.07:31:12.20#ibcon#read 3, iclass 23, count 0 2006.211.07:31:12.20#ibcon#about to read 4, iclass 23, count 0 2006.211.07:31:12.20#ibcon#read 4, iclass 23, count 0 2006.211.07:31:12.20#ibcon#about to read 5, iclass 23, count 0 2006.211.07:31:12.20#ibcon#read 5, iclass 23, count 0 2006.211.07:31:12.20#ibcon#about to read 6, iclass 23, count 0 2006.211.07:31:12.20#ibcon#read 6, iclass 23, count 0 2006.211.07:31:12.20#ibcon#end of sib2, iclass 23, count 0 2006.211.07:31:12.20#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:31:12.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:31:12.20#ibcon#[27=USB\r\n] 2006.211.07:31:12.20#ibcon#*before write, iclass 23, count 0 2006.211.07:31:12.20#ibcon#enter sib2, iclass 23, count 0 2006.211.07:31:12.20#ibcon#flushed, iclass 23, count 0 2006.211.07:31:12.20#ibcon#about to write, iclass 23, count 0 2006.211.07:31:12.20#ibcon#wrote, iclass 23, count 0 2006.211.07:31:12.20#ibcon#about to read 3, iclass 23, count 0 2006.211.07:31:12.23#ibcon#read 3, iclass 23, count 0 2006.211.07:31:12.23#ibcon#about to read 4, iclass 23, count 0 2006.211.07:31:12.23#ibcon#read 4, iclass 23, count 0 2006.211.07:31:12.23#ibcon#about to read 5, iclass 23, count 0 2006.211.07:31:12.23#ibcon#read 5, iclass 23, count 0 2006.211.07:31:12.23#ibcon#about to read 6, iclass 23, count 0 2006.211.07:31:12.23#ibcon#read 6, iclass 23, count 0 2006.211.07:31:12.23#ibcon#end of sib2, iclass 23, count 0 2006.211.07:31:12.23#ibcon#*after write, iclass 23, count 0 2006.211.07:31:12.23#ibcon#*before return 0, iclass 23, count 0 2006.211.07:31:12.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:12.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:31:12.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:31:12.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:31:12.23$vc4f8/vabw=wide 2006.211.07:31:12.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:31:12.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:31:12.23#ibcon#ireg 8 cls_cnt 0 2006.211.07:31:12.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:12.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:12.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:12.23#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:31:12.23#ibcon#first serial, iclass 25, count 0 2006.211.07:31:12.23#ibcon#enter sib2, iclass 25, count 0 2006.211.07:31:12.23#ibcon#flushed, iclass 25, count 0 2006.211.07:31:12.23#ibcon#about to write, iclass 25, count 0 2006.211.07:31:12.23#ibcon#wrote, iclass 25, count 0 2006.211.07:31:12.23#ibcon#about to read 3, iclass 25, count 0 2006.211.07:31:12.25#ibcon#read 3, iclass 25, count 0 2006.211.07:31:12.25#ibcon#about to read 4, iclass 25, count 0 2006.211.07:31:12.25#ibcon#read 4, iclass 25, count 0 2006.211.07:31:12.25#ibcon#about to read 5, iclass 25, count 0 2006.211.07:31:12.25#ibcon#read 5, iclass 25, count 0 2006.211.07:31:12.25#ibcon#about to read 6, iclass 25, count 0 2006.211.07:31:12.25#ibcon#read 6, iclass 25, count 0 2006.211.07:31:12.25#ibcon#end of sib2, iclass 25, count 0 2006.211.07:31:12.25#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:31:12.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:31:12.25#ibcon#[25=BW32\r\n] 2006.211.07:31:12.25#ibcon#*before write, iclass 25, count 0 2006.211.07:31:12.25#ibcon#enter sib2, iclass 25, count 0 2006.211.07:31:12.25#ibcon#flushed, iclass 25, count 0 2006.211.07:31:12.25#ibcon#about to write, iclass 25, count 0 2006.211.07:31:12.25#ibcon#wrote, iclass 25, count 0 2006.211.07:31:12.25#ibcon#about to read 3, iclass 25, count 0 2006.211.07:31:12.28#ibcon#read 3, iclass 25, count 0 2006.211.07:31:12.28#ibcon#about to read 4, iclass 25, count 0 2006.211.07:31:12.28#ibcon#read 4, iclass 25, count 0 2006.211.07:31:12.28#ibcon#about to read 5, iclass 25, count 0 2006.211.07:31:12.28#ibcon#read 5, iclass 25, count 0 2006.211.07:31:12.28#ibcon#about to read 6, iclass 25, count 0 2006.211.07:31:12.28#ibcon#read 6, iclass 25, count 0 2006.211.07:31:12.28#ibcon#end of sib2, iclass 25, count 0 2006.211.07:31:12.28#ibcon#*after write, iclass 25, count 0 2006.211.07:31:12.28#ibcon#*before return 0, iclass 25, count 0 2006.211.07:31:12.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:12.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:31:12.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:31:12.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:31:12.28$vc4f8/vbbw=wide 2006.211.07:31:12.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.07:31:12.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.07:31:12.28#ibcon#ireg 8 cls_cnt 0 2006.211.07:31:12.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:31:12.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:31:12.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:31:12.35#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:31:12.35#ibcon#first serial, iclass 27, count 0 2006.211.07:31:12.35#ibcon#enter sib2, iclass 27, count 0 2006.211.07:31:12.35#ibcon#flushed, iclass 27, count 0 2006.211.07:31:12.35#ibcon#about to write, iclass 27, count 0 2006.211.07:31:12.35#ibcon#wrote, iclass 27, count 0 2006.211.07:31:12.35#ibcon#about to read 3, iclass 27, count 0 2006.211.07:31:12.37#ibcon#read 3, iclass 27, count 0 2006.211.07:31:12.37#ibcon#about to read 4, iclass 27, count 0 2006.211.07:31:12.37#ibcon#read 4, iclass 27, count 0 2006.211.07:31:12.37#ibcon#about to read 5, iclass 27, count 0 2006.211.07:31:12.37#ibcon#read 5, iclass 27, count 0 2006.211.07:31:12.37#ibcon#about to read 6, iclass 27, count 0 2006.211.07:31:12.37#ibcon#read 6, iclass 27, count 0 2006.211.07:31:12.37#ibcon#end of sib2, iclass 27, count 0 2006.211.07:31:12.37#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:31:12.37#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:31:12.37#ibcon#[27=BW32\r\n] 2006.211.07:31:12.37#ibcon#*before write, iclass 27, count 0 2006.211.07:31:12.37#ibcon#enter sib2, iclass 27, count 0 2006.211.07:31:12.37#ibcon#flushed, iclass 27, count 0 2006.211.07:31:12.37#ibcon#about to write, iclass 27, count 0 2006.211.07:31:12.37#ibcon#wrote, iclass 27, count 0 2006.211.07:31:12.37#ibcon#about to read 3, iclass 27, count 0 2006.211.07:31:12.40#ibcon#read 3, iclass 27, count 0 2006.211.07:31:12.40#ibcon#about to read 4, iclass 27, count 0 2006.211.07:31:12.40#ibcon#read 4, iclass 27, count 0 2006.211.07:31:12.40#ibcon#about to read 5, iclass 27, count 0 2006.211.07:31:12.40#ibcon#read 5, iclass 27, count 0 2006.211.07:31:12.40#ibcon#about to read 6, iclass 27, count 0 2006.211.07:31:12.40#ibcon#read 6, iclass 27, count 0 2006.211.07:31:12.40#ibcon#end of sib2, iclass 27, count 0 2006.211.07:31:12.40#ibcon#*after write, iclass 27, count 0 2006.211.07:31:12.40#ibcon#*before return 0, iclass 27, count 0 2006.211.07:31:12.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:31:12.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:31:12.40#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:31:12.40#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:31:12.40$4f8m12a/ifd4f 2006.211.07:31:12.40$ifd4f/lo= 2006.211.07:31:12.40$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:31:12.40$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:31:12.40$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:31:12.40$ifd4f/patch= 2006.211.07:31:12.40$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:31:12.41$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:31:12.41$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:31:12.41$4f8m12a/"form=m,16.000,1:2 2006.211.07:31:12.41$4f8m12a/"tpicd 2006.211.07:31:12.41$4f8m12a/echo=off 2006.211.07:31:12.41$4f8m12a/xlog=off 2006.211.07:31:12.41:!2006.211.07:33:20 2006.211.07:31:53.14#trakl#Source acquired 2006.211.07:31:54.14#flagr#flagr/antenna,acquired 2006.211.07:33:20.01:preob 2006.211.07:33:21.14/onsource/TRACKING 2006.211.07:33:21.14:!2006.211.07:33:30 2006.211.07:33:30.00:data_valid=on 2006.211.07:33:30.00:midob 2006.211.07:33:30.14/onsource/TRACKING 2006.211.07:33:30.14/wx/24.99,1010.2,75 2006.211.07:33:30.26/cable/+6.4390E-03 2006.211.07:33:31.35/va/01,08,usb,yes,33,35 2006.211.07:33:31.35/va/02,07,usb,yes,34,35 2006.211.07:33:31.35/va/03,06,usb,yes,35,36 2006.211.07:33:31.35/va/04,07,usb,yes,34,37 2006.211.07:33:31.35/va/05,07,usb,yes,37,39 2006.211.07:33:31.35/va/06,06,usb,yes,36,36 2006.211.07:33:31.35/va/07,06,usb,yes,37,37 2006.211.07:33:31.35/va/08,07,usb,yes,35,35 2006.211.07:33:31.58/valo/01,532.99,yes,locked 2006.211.07:33:31.58/valo/02,572.99,yes,locked 2006.211.07:33:31.58/valo/03,672.99,yes,locked 2006.211.07:33:31.58/valo/04,832.99,yes,locked 2006.211.07:33:31.58/valo/05,652.99,yes,locked 2006.211.07:33:31.58/valo/06,772.99,yes,locked 2006.211.07:33:31.58/valo/07,832.99,yes,locked 2006.211.07:33:31.58/valo/08,852.99,yes,locked 2006.211.07:33:32.67/vb/01,04,usb,yes,29,30 2006.211.07:33:32.67/vb/02,04,usb,yes,31,36 2006.211.07:33:32.67/vb/03,03,usb,yes,34,39 2006.211.07:33:32.67/vb/04,03,usb,yes,36,36 2006.211.07:33:32.67/vb/05,03,usb,yes,34,39 2006.211.07:33:32.67/vb/06,03,usb,yes,35,38 2006.211.07:33:32.67/vb/07,04,usb,yes,30,30 2006.211.07:33:32.67/vb/08,03,usb,yes,35,38 2006.211.07:33:32.91/vblo/01,632.99,yes,locked 2006.211.07:33:32.91/vblo/02,640.99,yes,locked 2006.211.07:33:32.91/vblo/03,656.99,yes,locked 2006.211.07:33:32.91/vblo/04,712.99,yes,locked 2006.211.07:33:32.91/vblo/05,744.99,yes,locked 2006.211.07:33:32.91/vblo/06,752.99,yes,locked 2006.211.07:33:32.91/vblo/07,734.99,yes,locked 2006.211.07:33:32.91/vblo/08,744.99,yes,locked 2006.211.07:33:33.06/vabw/8 2006.211.07:33:33.21/vbbw/8 2006.211.07:33:33.30/xfe/off,on,12.0 2006.211.07:33:33.69/ifatt/23,28,28,28 2006.211.07:33:34.07/fmout-gps/S +4.46E-07 2006.211.07:33:34.12:!2006.211.07:34:30 2006.211.07:34:30.01:data_valid=off 2006.211.07:34:30.01:postob 2006.211.07:34:30.13/cable/+6.4387E-03 2006.211.07:34:30.13/wx/25.00,1010.2,74 2006.211.07:34:31.07/fmout-gps/S +4.46E-07 2006.211.07:34:31.07:scan_name=211-0735,k06211,60 2006.211.07:34:31.07:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.211.07:34:32.14#flagr#flagr/antenna,new-source 2006.211.07:34:32.14:checkk5 2006.211.07:34:32.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:34:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:34:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:34:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:34:33.84/chk_obsdata//k5ts1/T2110733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:34:34.18/chk_obsdata//k5ts2/T2110733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:34:34.51/chk_obsdata//k5ts3/T2110733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:34:34.84/chk_obsdata//k5ts4/T2110733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:34:35.50/k5log//k5ts1_log_newline 2006.211.07:34:36.18/k5log//k5ts2_log_newline 2006.211.07:34:36.83/k5log//k5ts3_log_newline 2006.211.07:34:37.49/k5log//k5ts4_log_newline 2006.211.07:34:37.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:34:37.51:4f8m12a=1 2006.211.07:34:37.51$4f8m12a/echo=on 2006.211.07:34:37.51$4f8m12a/pcalon 2006.211.07:34:37.51$pcalon/"no phase cal control is implemented here 2006.211.07:34:37.51$4f8m12a/"tpicd=stop 2006.211.07:34:37.51$4f8m12a/vc4f8 2006.211.07:34:37.51$vc4f8/valo=1,532.99 2006.211.07:34:37.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.07:34:37.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.07:34:37.52#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:37.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:37.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:37.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:37.52#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:34:37.52#ibcon#first serial, iclass 38, count 0 2006.211.07:34:37.52#ibcon#enter sib2, iclass 38, count 0 2006.211.07:34:37.52#ibcon#flushed, iclass 38, count 0 2006.211.07:34:37.52#ibcon#about to write, iclass 38, count 0 2006.211.07:34:37.52#ibcon#wrote, iclass 38, count 0 2006.211.07:34:37.52#ibcon#about to read 3, iclass 38, count 0 2006.211.07:34:37.53#ibcon#read 3, iclass 38, count 0 2006.211.07:34:37.53#ibcon#about to read 4, iclass 38, count 0 2006.211.07:34:37.53#ibcon#read 4, iclass 38, count 0 2006.211.07:34:37.53#ibcon#about to read 5, iclass 38, count 0 2006.211.07:34:37.53#ibcon#read 5, iclass 38, count 0 2006.211.07:34:37.53#ibcon#about to read 6, iclass 38, count 0 2006.211.07:34:37.53#ibcon#read 6, iclass 38, count 0 2006.211.07:34:37.53#ibcon#end of sib2, iclass 38, count 0 2006.211.07:34:37.53#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:34:37.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:34:37.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:34:37.53#ibcon#*before write, iclass 38, count 0 2006.211.07:34:37.53#ibcon#enter sib2, iclass 38, count 0 2006.211.07:34:37.53#ibcon#flushed, iclass 38, count 0 2006.211.07:34:37.53#ibcon#about to write, iclass 38, count 0 2006.211.07:34:37.53#ibcon#wrote, iclass 38, count 0 2006.211.07:34:37.53#ibcon#about to read 3, iclass 38, count 0 2006.211.07:34:37.58#ibcon#read 3, iclass 38, count 0 2006.211.07:34:37.58#ibcon#about to read 4, iclass 38, count 0 2006.211.07:34:37.58#ibcon#read 4, iclass 38, count 0 2006.211.07:34:37.58#ibcon#about to read 5, iclass 38, count 0 2006.211.07:34:37.58#ibcon#read 5, iclass 38, count 0 2006.211.07:34:37.58#ibcon#about to read 6, iclass 38, count 0 2006.211.07:34:37.58#ibcon#read 6, iclass 38, count 0 2006.211.07:34:37.58#ibcon#end of sib2, iclass 38, count 0 2006.211.07:34:37.58#ibcon#*after write, iclass 38, count 0 2006.211.07:34:37.58#ibcon#*before return 0, iclass 38, count 0 2006.211.07:34:37.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:37.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:37.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:34:37.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:34:37.58$vc4f8/va=1,8 2006.211.07:34:37.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.07:34:37.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.07:34:37.58#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:37.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:37.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:37.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:37.58#ibcon#enter wrdev, iclass 40, count 2 2006.211.07:34:37.58#ibcon#first serial, iclass 40, count 2 2006.211.07:34:37.58#ibcon#enter sib2, iclass 40, count 2 2006.211.07:34:37.58#ibcon#flushed, iclass 40, count 2 2006.211.07:34:37.58#ibcon#about to write, iclass 40, count 2 2006.211.07:34:37.58#ibcon#wrote, iclass 40, count 2 2006.211.07:34:37.58#ibcon#about to read 3, iclass 40, count 2 2006.211.07:34:37.60#ibcon#read 3, iclass 40, count 2 2006.211.07:34:37.60#ibcon#about to read 4, iclass 40, count 2 2006.211.07:34:37.60#ibcon#read 4, iclass 40, count 2 2006.211.07:34:37.60#ibcon#about to read 5, iclass 40, count 2 2006.211.07:34:37.60#ibcon#read 5, iclass 40, count 2 2006.211.07:34:37.60#ibcon#about to read 6, iclass 40, count 2 2006.211.07:34:37.60#ibcon#read 6, iclass 40, count 2 2006.211.07:34:37.60#ibcon#end of sib2, iclass 40, count 2 2006.211.07:34:37.60#ibcon#*mode == 0, iclass 40, count 2 2006.211.07:34:37.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.07:34:37.60#ibcon#[25=AT01-08\r\n] 2006.211.07:34:37.60#ibcon#*before write, iclass 40, count 2 2006.211.07:34:37.60#ibcon#enter sib2, iclass 40, count 2 2006.211.07:34:37.60#ibcon#flushed, iclass 40, count 2 2006.211.07:34:37.60#ibcon#about to write, iclass 40, count 2 2006.211.07:34:37.60#ibcon#wrote, iclass 40, count 2 2006.211.07:34:37.60#ibcon#about to read 3, iclass 40, count 2 2006.211.07:34:37.63#ibcon#read 3, iclass 40, count 2 2006.211.07:34:37.63#ibcon#about to read 4, iclass 40, count 2 2006.211.07:34:37.63#ibcon#read 4, iclass 40, count 2 2006.211.07:34:37.63#ibcon#about to read 5, iclass 40, count 2 2006.211.07:34:37.63#ibcon#read 5, iclass 40, count 2 2006.211.07:34:37.63#ibcon#about to read 6, iclass 40, count 2 2006.211.07:34:37.63#ibcon#read 6, iclass 40, count 2 2006.211.07:34:37.63#ibcon#end of sib2, iclass 40, count 2 2006.211.07:34:37.63#ibcon#*after write, iclass 40, count 2 2006.211.07:34:37.63#ibcon#*before return 0, iclass 40, count 2 2006.211.07:34:37.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:37.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:37.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.07:34:37.63#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:37.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:37.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:37.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:37.75#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:34:37.75#ibcon#first serial, iclass 40, count 0 2006.211.07:34:37.75#ibcon#enter sib2, iclass 40, count 0 2006.211.07:34:37.75#ibcon#flushed, iclass 40, count 0 2006.211.07:34:37.75#ibcon#about to write, iclass 40, count 0 2006.211.07:34:37.75#ibcon#wrote, iclass 40, count 0 2006.211.07:34:37.75#ibcon#about to read 3, iclass 40, count 0 2006.211.07:34:37.77#ibcon#read 3, iclass 40, count 0 2006.211.07:34:37.77#ibcon#about to read 4, iclass 40, count 0 2006.211.07:34:37.77#ibcon#read 4, iclass 40, count 0 2006.211.07:34:37.77#ibcon#about to read 5, iclass 40, count 0 2006.211.07:34:37.77#ibcon#read 5, iclass 40, count 0 2006.211.07:34:37.77#ibcon#about to read 6, iclass 40, count 0 2006.211.07:34:37.77#ibcon#read 6, iclass 40, count 0 2006.211.07:34:37.77#ibcon#end of sib2, iclass 40, count 0 2006.211.07:34:37.77#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:34:37.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:34:37.77#ibcon#[25=USB\r\n] 2006.211.07:34:37.77#ibcon#*before write, iclass 40, count 0 2006.211.07:34:37.77#ibcon#enter sib2, iclass 40, count 0 2006.211.07:34:37.77#ibcon#flushed, iclass 40, count 0 2006.211.07:34:37.77#ibcon#about to write, iclass 40, count 0 2006.211.07:34:37.77#ibcon#wrote, iclass 40, count 0 2006.211.07:34:37.77#ibcon#about to read 3, iclass 40, count 0 2006.211.07:34:37.80#ibcon#read 3, iclass 40, count 0 2006.211.07:34:37.80#ibcon#about to read 4, iclass 40, count 0 2006.211.07:34:37.80#ibcon#read 4, iclass 40, count 0 2006.211.07:34:37.80#ibcon#about to read 5, iclass 40, count 0 2006.211.07:34:37.80#ibcon#read 5, iclass 40, count 0 2006.211.07:34:37.80#ibcon#about to read 6, iclass 40, count 0 2006.211.07:34:37.80#ibcon#read 6, iclass 40, count 0 2006.211.07:34:37.80#ibcon#end of sib2, iclass 40, count 0 2006.211.07:34:37.80#ibcon#*after write, iclass 40, count 0 2006.211.07:34:37.80#ibcon#*before return 0, iclass 40, count 0 2006.211.07:34:37.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:37.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:37.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:34:37.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:34:37.80$vc4f8/valo=2,572.99 2006.211.07:34:37.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.07:34:37.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.07:34:37.80#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:37.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:37.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:37.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:37.80#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:34:37.80#ibcon#first serial, iclass 4, count 0 2006.211.07:34:37.80#ibcon#enter sib2, iclass 4, count 0 2006.211.07:34:37.80#ibcon#flushed, iclass 4, count 0 2006.211.07:34:37.80#ibcon#about to write, iclass 4, count 0 2006.211.07:34:37.80#ibcon#wrote, iclass 4, count 0 2006.211.07:34:37.80#ibcon#about to read 3, iclass 4, count 0 2006.211.07:34:37.82#ibcon#read 3, iclass 4, count 0 2006.211.07:34:37.82#ibcon#about to read 4, iclass 4, count 0 2006.211.07:34:37.82#ibcon#read 4, iclass 4, count 0 2006.211.07:34:37.82#ibcon#about to read 5, iclass 4, count 0 2006.211.07:34:37.82#ibcon#read 5, iclass 4, count 0 2006.211.07:34:37.82#ibcon#about to read 6, iclass 4, count 0 2006.211.07:34:37.82#ibcon#read 6, iclass 4, count 0 2006.211.07:34:37.82#ibcon#end of sib2, iclass 4, count 0 2006.211.07:34:37.82#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:34:37.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:34:37.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:34:37.82#ibcon#*before write, iclass 4, count 0 2006.211.07:34:37.82#ibcon#enter sib2, iclass 4, count 0 2006.211.07:34:37.82#ibcon#flushed, iclass 4, count 0 2006.211.07:34:37.82#ibcon#about to write, iclass 4, count 0 2006.211.07:34:37.82#ibcon#wrote, iclass 4, count 0 2006.211.07:34:37.82#ibcon#about to read 3, iclass 4, count 0 2006.211.07:34:37.86#ibcon#read 3, iclass 4, count 0 2006.211.07:34:37.86#ibcon#about to read 4, iclass 4, count 0 2006.211.07:34:37.86#ibcon#read 4, iclass 4, count 0 2006.211.07:34:37.86#ibcon#about to read 5, iclass 4, count 0 2006.211.07:34:37.86#ibcon#read 5, iclass 4, count 0 2006.211.07:34:37.86#ibcon#about to read 6, iclass 4, count 0 2006.211.07:34:37.86#ibcon#read 6, iclass 4, count 0 2006.211.07:34:37.86#ibcon#end of sib2, iclass 4, count 0 2006.211.07:34:37.86#ibcon#*after write, iclass 4, count 0 2006.211.07:34:37.86#ibcon#*before return 0, iclass 4, count 0 2006.211.07:34:37.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:37.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:37.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:34:37.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:34:37.86$vc4f8/va=2,7 2006.211.07:34:37.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.07:34:37.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.07:34:37.86#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:37.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:37.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:37.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:37.92#ibcon#enter wrdev, iclass 6, count 2 2006.211.07:34:37.92#ibcon#first serial, iclass 6, count 2 2006.211.07:34:37.92#ibcon#enter sib2, iclass 6, count 2 2006.211.07:34:37.92#ibcon#flushed, iclass 6, count 2 2006.211.07:34:37.92#ibcon#about to write, iclass 6, count 2 2006.211.07:34:37.92#ibcon#wrote, iclass 6, count 2 2006.211.07:34:37.92#ibcon#about to read 3, iclass 6, count 2 2006.211.07:34:37.94#ibcon#read 3, iclass 6, count 2 2006.211.07:34:37.94#ibcon#about to read 4, iclass 6, count 2 2006.211.07:34:37.94#ibcon#read 4, iclass 6, count 2 2006.211.07:34:37.94#ibcon#about to read 5, iclass 6, count 2 2006.211.07:34:37.94#ibcon#read 5, iclass 6, count 2 2006.211.07:34:37.94#ibcon#about to read 6, iclass 6, count 2 2006.211.07:34:37.94#ibcon#read 6, iclass 6, count 2 2006.211.07:34:37.94#ibcon#end of sib2, iclass 6, count 2 2006.211.07:34:37.94#ibcon#*mode == 0, iclass 6, count 2 2006.211.07:34:37.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.07:34:37.94#ibcon#[25=AT02-07\r\n] 2006.211.07:34:37.94#ibcon#*before write, iclass 6, count 2 2006.211.07:34:37.94#ibcon#enter sib2, iclass 6, count 2 2006.211.07:34:37.94#ibcon#flushed, iclass 6, count 2 2006.211.07:34:37.94#ibcon#about to write, iclass 6, count 2 2006.211.07:34:37.94#ibcon#wrote, iclass 6, count 2 2006.211.07:34:37.94#ibcon#about to read 3, iclass 6, count 2 2006.211.07:34:37.97#ibcon#read 3, iclass 6, count 2 2006.211.07:34:37.97#ibcon#about to read 4, iclass 6, count 2 2006.211.07:34:37.97#ibcon#read 4, iclass 6, count 2 2006.211.07:34:37.97#ibcon#about to read 5, iclass 6, count 2 2006.211.07:34:37.97#ibcon#read 5, iclass 6, count 2 2006.211.07:34:37.97#ibcon#about to read 6, iclass 6, count 2 2006.211.07:34:37.97#ibcon#read 6, iclass 6, count 2 2006.211.07:34:37.97#ibcon#end of sib2, iclass 6, count 2 2006.211.07:34:37.97#ibcon#*after write, iclass 6, count 2 2006.211.07:34:37.97#ibcon#*before return 0, iclass 6, count 2 2006.211.07:34:37.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:37.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:37.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.07:34:37.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:37.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:38.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:38.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:38.09#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:34:38.09#ibcon#first serial, iclass 6, count 0 2006.211.07:34:38.09#ibcon#enter sib2, iclass 6, count 0 2006.211.07:34:38.09#ibcon#flushed, iclass 6, count 0 2006.211.07:34:38.09#ibcon#about to write, iclass 6, count 0 2006.211.07:34:38.09#ibcon#wrote, iclass 6, count 0 2006.211.07:34:38.09#ibcon#about to read 3, iclass 6, count 0 2006.211.07:34:38.11#ibcon#read 3, iclass 6, count 0 2006.211.07:34:38.11#ibcon#about to read 4, iclass 6, count 0 2006.211.07:34:38.11#ibcon#read 4, iclass 6, count 0 2006.211.07:34:38.11#ibcon#about to read 5, iclass 6, count 0 2006.211.07:34:38.11#ibcon#read 5, iclass 6, count 0 2006.211.07:34:38.11#ibcon#about to read 6, iclass 6, count 0 2006.211.07:34:38.11#ibcon#read 6, iclass 6, count 0 2006.211.07:34:38.11#ibcon#end of sib2, iclass 6, count 0 2006.211.07:34:38.11#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:34:38.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:34:38.11#ibcon#[25=USB\r\n] 2006.211.07:34:38.11#ibcon#*before write, iclass 6, count 0 2006.211.07:34:38.11#ibcon#enter sib2, iclass 6, count 0 2006.211.07:34:38.11#ibcon#flushed, iclass 6, count 0 2006.211.07:34:38.11#ibcon#about to write, iclass 6, count 0 2006.211.07:34:38.11#ibcon#wrote, iclass 6, count 0 2006.211.07:34:38.11#ibcon#about to read 3, iclass 6, count 0 2006.211.07:34:38.14#ibcon#read 3, iclass 6, count 0 2006.211.07:34:38.14#ibcon#about to read 4, iclass 6, count 0 2006.211.07:34:38.14#ibcon#read 4, iclass 6, count 0 2006.211.07:34:38.14#ibcon#about to read 5, iclass 6, count 0 2006.211.07:34:38.14#ibcon#read 5, iclass 6, count 0 2006.211.07:34:38.14#ibcon#about to read 6, iclass 6, count 0 2006.211.07:34:38.14#ibcon#read 6, iclass 6, count 0 2006.211.07:34:38.14#ibcon#end of sib2, iclass 6, count 0 2006.211.07:34:38.14#ibcon#*after write, iclass 6, count 0 2006.211.07:34:38.14#ibcon#*before return 0, iclass 6, count 0 2006.211.07:34:38.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:38.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:38.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:34:38.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:34:38.14$vc4f8/valo=3,672.99 2006.211.07:34:38.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.07:34:38.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.07:34:38.14#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:38.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:38.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:38.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:38.14#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:34:38.14#ibcon#first serial, iclass 10, count 0 2006.211.07:34:38.14#ibcon#enter sib2, iclass 10, count 0 2006.211.07:34:38.14#ibcon#flushed, iclass 10, count 0 2006.211.07:34:38.14#ibcon#about to write, iclass 10, count 0 2006.211.07:34:38.14#ibcon#wrote, iclass 10, count 0 2006.211.07:34:38.14#ibcon#about to read 3, iclass 10, count 0 2006.211.07:34:38.16#ibcon#read 3, iclass 10, count 0 2006.211.07:34:38.16#ibcon#about to read 4, iclass 10, count 0 2006.211.07:34:38.16#ibcon#read 4, iclass 10, count 0 2006.211.07:34:38.16#ibcon#about to read 5, iclass 10, count 0 2006.211.07:34:38.16#ibcon#read 5, iclass 10, count 0 2006.211.07:34:38.16#ibcon#about to read 6, iclass 10, count 0 2006.211.07:34:38.16#ibcon#read 6, iclass 10, count 0 2006.211.07:34:38.16#ibcon#end of sib2, iclass 10, count 0 2006.211.07:34:38.16#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:34:38.16#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:34:38.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:34:38.16#ibcon#*before write, iclass 10, count 0 2006.211.07:34:38.16#ibcon#enter sib2, iclass 10, count 0 2006.211.07:34:38.16#ibcon#flushed, iclass 10, count 0 2006.211.07:34:38.16#ibcon#about to write, iclass 10, count 0 2006.211.07:34:38.16#ibcon#wrote, iclass 10, count 0 2006.211.07:34:38.16#ibcon#about to read 3, iclass 10, count 0 2006.211.07:34:38.20#ibcon#read 3, iclass 10, count 0 2006.211.07:34:38.20#ibcon#about to read 4, iclass 10, count 0 2006.211.07:34:38.20#ibcon#read 4, iclass 10, count 0 2006.211.07:34:38.20#ibcon#about to read 5, iclass 10, count 0 2006.211.07:34:38.20#ibcon#read 5, iclass 10, count 0 2006.211.07:34:38.20#ibcon#about to read 6, iclass 10, count 0 2006.211.07:34:38.20#ibcon#read 6, iclass 10, count 0 2006.211.07:34:38.20#ibcon#end of sib2, iclass 10, count 0 2006.211.07:34:38.20#ibcon#*after write, iclass 10, count 0 2006.211.07:34:38.20#ibcon#*before return 0, iclass 10, count 0 2006.211.07:34:38.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:38.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:38.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:34:38.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:34:38.20$vc4f8/va=3,6 2006.211.07:34:38.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.07:34:38.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.07:34:38.20#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:38.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:38.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:38.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:38.26#ibcon#enter wrdev, iclass 12, count 2 2006.211.07:34:38.26#ibcon#first serial, iclass 12, count 2 2006.211.07:34:38.26#ibcon#enter sib2, iclass 12, count 2 2006.211.07:34:38.26#ibcon#flushed, iclass 12, count 2 2006.211.07:34:38.26#ibcon#about to write, iclass 12, count 2 2006.211.07:34:38.26#ibcon#wrote, iclass 12, count 2 2006.211.07:34:38.26#ibcon#about to read 3, iclass 12, count 2 2006.211.07:34:38.28#ibcon#read 3, iclass 12, count 2 2006.211.07:34:38.28#ibcon#about to read 4, iclass 12, count 2 2006.211.07:34:38.28#ibcon#read 4, iclass 12, count 2 2006.211.07:34:38.28#ibcon#about to read 5, iclass 12, count 2 2006.211.07:34:38.28#ibcon#read 5, iclass 12, count 2 2006.211.07:34:38.28#ibcon#about to read 6, iclass 12, count 2 2006.211.07:34:38.28#ibcon#read 6, iclass 12, count 2 2006.211.07:34:38.28#ibcon#end of sib2, iclass 12, count 2 2006.211.07:34:38.28#ibcon#*mode == 0, iclass 12, count 2 2006.211.07:34:38.28#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.07:34:38.28#ibcon#[25=AT03-06\r\n] 2006.211.07:34:38.28#ibcon#*before write, iclass 12, count 2 2006.211.07:34:38.28#ibcon#enter sib2, iclass 12, count 2 2006.211.07:34:38.28#ibcon#flushed, iclass 12, count 2 2006.211.07:34:38.28#ibcon#about to write, iclass 12, count 2 2006.211.07:34:38.28#ibcon#wrote, iclass 12, count 2 2006.211.07:34:38.28#ibcon#about to read 3, iclass 12, count 2 2006.211.07:34:38.31#ibcon#read 3, iclass 12, count 2 2006.211.07:34:38.31#ibcon#about to read 4, iclass 12, count 2 2006.211.07:34:38.31#ibcon#read 4, iclass 12, count 2 2006.211.07:34:38.31#ibcon#about to read 5, iclass 12, count 2 2006.211.07:34:38.31#ibcon#read 5, iclass 12, count 2 2006.211.07:34:38.31#ibcon#about to read 6, iclass 12, count 2 2006.211.07:34:38.31#ibcon#read 6, iclass 12, count 2 2006.211.07:34:38.31#ibcon#end of sib2, iclass 12, count 2 2006.211.07:34:38.31#ibcon#*after write, iclass 12, count 2 2006.211.07:34:38.31#ibcon#*before return 0, iclass 12, count 2 2006.211.07:34:38.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:38.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:38.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.07:34:38.31#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:38.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:38.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:38.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:38.43#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:34:38.43#ibcon#first serial, iclass 12, count 0 2006.211.07:34:38.43#ibcon#enter sib2, iclass 12, count 0 2006.211.07:34:38.43#ibcon#flushed, iclass 12, count 0 2006.211.07:34:38.43#ibcon#about to write, iclass 12, count 0 2006.211.07:34:38.43#ibcon#wrote, iclass 12, count 0 2006.211.07:34:38.43#ibcon#about to read 3, iclass 12, count 0 2006.211.07:34:38.45#ibcon#read 3, iclass 12, count 0 2006.211.07:34:38.45#ibcon#about to read 4, iclass 12, count 0 2006.211.07:34:38.45#ibcon#read 4, iclass 12, count 0 2006.211.07:34:38.45#ibcon#about to read 5, iclass 12, count 0 2006.211.07:34:38.45#ibcon#read 5, iclass 12, count 0 2006.211.07:34:38.45#ibcon#about to read 6, iclass 12, count 0 2006.211.07:34:38.45#ibcon#read 6, iclass 12, count 0 2006.211.07:34:38.45#ibcon#end of sib2, iclass 12, count 0 2006.211.07:34:38.45#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:34:38.45#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:34:38.45#ibcon#[25=USB\r\n] 2006.211.07:34:38.45#ibcon#*before write, iclass 12, count 0 2006.211.07:34:38.45#ibcon#enter sib2, iclass 12, count 0 2006.211.07:34:38.45#ibcon#flushed, iclass 12, count 0 2006.211.07:34:38.45#ibcon#about to write, iclass 12, count 0 2006.211.07:34:38.45#ibcon#wrote, iclass 12, count 0 2006.211.07:34:38.45#ibcon#about to read 3, iclass 12, count 0 2006.211.07:34:38.48#ibcon#read 3, iclass 12, count 0 2006.211.07:34:38.48#ibcon#about to read 4, iclass 12, count 0 2006.211.07:34:38.48#ibcon#read 4, iclass 12, count 0 2006.211.07:34:38.48#ibcon#about to read 5, iclass 12, count 0 2006.211.07:34:38.48#ibcon#read 5, iclass 12, count 0 2006.211.07:34:38.48#ibcon#about to read 6, iclass 12, count 0 2006.211.07:34:38.48#ibcon#read 6, iclass 12, count 0 2006.211.07:34:38.48#ibcon#end of sib2, iclass 12, count 0 2006.211.07:34:38.48#ibcon#*after write, iclass 12, count 0 2006.211.07:34:38.48#ibcon#*before return 0, iclass 12, count 0 2006.211.07:34:38.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:38.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:38.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:34:38.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:34:38.48$vc4f8/valo=4,832.99 2006.211.07:34:38.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.07:34:38.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.07:34:38.48#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:38.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:38.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:38.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:38.48#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:34:38.48#ibcon#first serial, iclass 14, count 0 2006.211.07:34:38.48#ibcon#enter sib2, iclass 14, count 0 2006.211.07:34:38.48#ibcon#flushed, iclass 14, count 0 2006.211.07:34:38.48#ibcon#about to write, iclass 14, count 0 2006.211.07:34:38.48#ibcon#wrote, iclass 14, count 0 2006.211.07:34:38.48#ibcon#about to read 3, iclass 14, count 0 2006.211.07:34:38.50#ibcon#read 3, iclass 14, count 0 2006.211.07:34:38.50#ibcon#about to read 4, iclass 14, count 0 2006.211.07:34:38.50#ibcon#read 4, iclass 14, count 0 2006.211.07:34:38.50#ibcon#about to read 5, iclass 14, count 0 2006.211.07:34:38.50#ibcon#read 5, iclass 14, count 0 2006.211.07:34:38.50#ibcon#about to read 6, iclass 14, count 0 2006.211.07:34:38.50#ibcon#read 6, iclass 14, count 0 2006.211.07:34:38.50#ibcon#end of sib2, iclass 14, count 0 2006.211.07:34:38.50#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:34:38.50#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:34:38.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:34:38.50#ibcon#*before write, iclass 14, count 0 2006.211.07:34:38.50#ibcon#enter sib2, iclass 14, count 0 2006.211.07:34:38.50#ibcon#flushed, iclass 14, count 0 2006.211.07:34:38.50#ibcon#about to write, iclass 14, count 0 2006.211.07:34:38.50#ibcon#wrote, iclass 14, count 0 2006.211.07:34:38.50#ibcon#about to read 3, iclass 14, count 0 2006.211.07:34:38.54#ibcon#read 3, iclass 14, count 0 2006.211.07:34:38.54#ibcon#about to read 4, iclass 14, count 0 2006.211.07:34:38.54#ibcon#read 4, iclass 14, count 0 2006.211.07:34:38.54#ibcon#about to read 5, iclass 14, count 0 2006.211.07:34:38.54#ibcon#read 5, iclass 14, count 0 2006.211.07:34:38.54#ibcon#about to read 6, iclass 14, count 0 2006.211.07:34:38.54#ibcon#read 6, iclass 14, count 0 2006.211.07:34:38.54#ibcon#end of sib2, iclass 14, count 0 2006.211.07:34:38.54#ibcon#*after write, iclass 14, count 0 2006.211.07:34:38.54#ibcon#*before return 0, iclass 14, count 0 2006.211.07:34:38.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:38.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:38.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:34:38.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:34:38.54$vc4f8/va=4,7 2006.211.07:34:38.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.07:34:38.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.07:34:38.54#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:38.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:38.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:38.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:38.60#ibcon#enter wrdev, iclass 16, count 2 2006.211.07:34:38.60#ibcon#first serial, iclass 16, count 2 2006.211.07:34:38.60#ibcon#enter sib2, iclass 16, count 2 2006.211.07:34:38.60#ibcon#flushed, iclass 16, count 2 2006.211.07:34:38.60#ibcon#about to write, iclass 16, count 2 2006.211.07:34:38.60#ibcon#wrote, iclass 16, count 2 2006.211.07:34:38.60#ibcon#about to read 3, iclass 16, count 2 2006.211.07:34:38.62#ibcon#read 3, iclass 16, count 2 2006.211.07:34:38.62#ibcon#about to read 4, iclass 16, count 2 2006.211.07:34:38.62#ibcon#read 4, iclass 16, count 2 2006.211.07:34:38.62#ibcon#about to read 5, iclass 16, count 2 2006.211.07:34:38.62#ibcon#read 5, iclass 16, count 2 2006.211.07:34:38.62#ibcon#about to read 6, iclass 16, count 2 2006.211.07:34:38.62#ibcon#read 6, iclass 16, count 2 2006.211.07:34:38.62#ibcon#end of sib2, iclass 16, count 2 2006.211.07:34:38.62#ibcon#*mode == 0, iclass 16, count 2 2006.211.07:34:38.62#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.07:34:38.62#ibcon#[25=AT04-07\r\n] 2006.211.07:34:38.62#ibcon#*before write, iclass 16, count 2 2006.211.07:34:38.62#ibcon#enter sib2, iclass 16, count 2 2006.211.07:34:38.62#ibcon#flushed, iclass 16, count 2 2006.211.07:34:38.62#ibcon#about to write, iclass 16, count 2 2006.211.07:34:38.62#ibcon#wrote, iclass 16, count 2 2006.211.07:34:38.62#ibcon#about to read 3, iclass 16, count 2 2006.211.07:34:38.65#ibcon#read 3, iclass 16, count 2 2006.211.07:34:38.65#ibcon#about to read 4, iclass 16, count 2 2006.211.07:34:38.65#ibcon#read 4, iclass 16, count 2 2006.211.07:34:38.65#ibcon#about to read 5, iclass 16, count 2 2006.211.07:34:38.65#ibcon#read 5, iclass 16, count 2 2006.211.07:34:38.65#ibcon#about to read 6, iclass 16, count 2 2006.211.07:34:38.65#ibcon#read 6, iclass 16, count 2 2006.211.07:34:38.65#ibcon#end of sib2, iclass 16, count 2 2006.211.07:34:38.65#ibcon#*after write, iclass 16, count 2 2006.211.07:34:38.65#ibcon#*before return 0, iclass 16, count 2 2006.211.07:34:38.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:38.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:38.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.07:34:38.65#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:38.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:38.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:38.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:38.77#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:34:38.77#ibcon#first serial, iclass 16, count 0 2006.211.07:34:38.77#ibcon#enter sib2, iclass 16, count 0 2006.211.07:34:38.77#ibcon#flushed, iclass 16, count 0 2006.211.07:34:38.77#ibcon#about to write, iclass 16, count 0 2006.211.07:34:38.77#ibcon#wrote, iclass 16, count 0 2006.211.07:34:38.77#ibcon#about to read 3, iclass 16, count 0 2006.211.07:34:38.79#ibcon#read 3, iclass 16, count 0 2006.211.07:34:38.79#ibcon#about to read 4, iclass 16, count 0 2006.211.07:34:38.79#ibcon#read 4, iclass 16, count 0 2006.211.07:34:38.79#ibcon#about to read 5, iclass 16, count 0 2006.211.07:34:38.79#ibcon#read 5, iclass 16, count 0 2006.211.07:34:38.79#ibcon#about to read 6, iclass 16, count 0 2006.211.07:34:38.79#ibcon#read 6, iclass 16, count 0 2006.211.07:34:38.79#ibcon#end of sib2, iclass 16, count 0 2006.211.07:34:38.79#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:34:38.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:34:38.79#ibcon#[25=USB\r\n] 2006.211.07:34:38.79#ibcon#*before write, iclass 16, count 0 2006.211.07:34:38.79#ibcon#enter sib2, iclass 16, count 0 2006.211.07:34:38.79#ibcon#flushed, iclass 16, count 0 2006.211.07:34:38.79#ibcon#about to write, iclass 16, count 0 2006.211.07:34:38.79#ibcon#wrote, iclass 16, count 0 2006.211.07:34:38.79#ibcon#about to read 3, iclass 16, count 0 2006.211.07:34:38.82#ibcon#read 3, iclass 16, count 0 2006.211.07:34:38.82#ibcon#about to read 4, iclass 16, count 0 2006.211.07:34:38.82#ibcon#read 4, iclass 16, count 0 2006.211.07:34:38.82#ibcon#about to read 5, iclass 16, count 0 2006.211.07:34:38.82#ibcon#read 5, iclass 16, count 0 2006.211.07:34:38.82#ibcon#about to read 6, iclass 16, count 0 2006.211.07:34:38.82#ibcon#read 6, iclass 16, count 0 2006.211.07:34:38.82#ibcon#end of sib2, iclass 16, count 0 2006.211.07:34:38.82#ibcon#*after write, iclass 16, count 0 2006.211.07:34:38.82#ibcon#*before return 0, iclass 16, count 0 2006.211.07:34:38.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:38.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:38.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:34:38.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:34:38.82$vc4f8/valo=5,652.99 2006.211.07:34:38.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:34:38.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:34:38.82#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:38.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:38.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:38.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:38.82#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:34:38.82#ibcon#first serial, iclass 18, count 0 2006.211.07:34:38.82#ibcon#enter sib2, iclass 18, count 0 2006.211.07:34:38.82#ibcon#flushed, iclass 18, count 0 2006.211.07:34:38.82#ibcon#about to write, iclass 18, count 0 2006.211.07:34:38.82#ibcon#wrote, iclass 18, count 0 2006.211.07:34:38.82#ibcon#about to read 3, iclass 18, count 0 2006.211.07:34:38.84#ibcon#read 3, iclass 18, count 0 2006.211.07:34:38.84#ibcon#about to read 4, iclass 18, count 0 2006.211.07:34:38.84#ibcon#read 4, iclass 18, count 0 2006.211.07:34:38.84#ibcon#about to read 5, iclass 18, count 0 2006.211.07:34:38.84#ibcon#read 5, iclass 18, count 0 2006.211.07:34:38.84#ibcon#about to read 6, iclass 18, count 0 2006.211.07:34:38.84#ibcon#read 6, iclass 18, count 0 2006.211.07:34:38.84#ibcon#end of sib2, iclass 18, count 0 2006.211.07:34:38.84#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:34:38.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:34:38.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:34:38.84#ibcon#*before write, iclass 18, count 0 2006.211.07:34:38.84#ibcon#enter sib2, iclass 18, count 0 2006.211.07:34:38.84#ibcon#flushed, iclass 18, count 0 2006.211.07:34:38.84#ibcon#about to write, iclass 18, count 0 2006.211.07:34:38.84#ibcon#wrote, iclass 18, count 0 2006.211.07:34:38.84#ibcon#about to read 3, iclass 18, count 0 2006.211.07:34:38.88#ibcon#read 3, iclass 18, count 0 2006.211.07:34:38.88#ibcon#about to read 4, iclass 18, count 0 2006.211.07:34:38.88#ibcon#read 4, iclass 18, count 0 2006.211.07:34:38.88#ibcon#about to read 5, iclass 18, count 0 2006.211.07:34:38.88#ibcon#read 5, iclass 18, count 0 2006.211.07:34:38.88#ibcon#about to read 6, iclass 18, count 0 2006.211.07:34:38.88#ibcon#read 6, iclass 18, count 0 2006.211.07:34:38.88#ibcon#end of sib2, iclass 18, count 0 2006.211.07:34:38.88#ibcon#*after write, iclass 18, count 0 2006.211.07:34:38.88#ibcon#*before return 0, iclass 18, count 0 2006.211.07:34:38.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:38.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:38.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:34:38.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:34:38.88$vc4f8/va=5,7 2006.211.07:34:38.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:34:38.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:34:38.88#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:38.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:38.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:38.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:38.94#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:34:38.94#ibcon#first serial, iclass 20, count 2 2006.211.07:34:38.94#ibcon#enter sib2, iclass 20, count 2 2006.211.07:34:38.94#ibcon#flushed, iclass 20, count 2 2006.211.07:34:38.94#ibcon#about to write, iclass 20, count 2 2006.211.07:34:38.94#ibcon#wrote, iclass 20, count 2 2006.211.07:34:38.94#ibcon#about to read 3, iclass 20, count 2 2006.211.07:34:38.96#ibcon#read 3, iclass 20, count 2 2006.211.07:34:38.96#ibcon#about to read 4, iclass 20, count 2 2006.211.07:34:38.96#ibcon#read 4, iclass 20, count 2 2006.211.07:34:38.96#ibcon#about to read 5, iclass 20, count 2 2006.211.07:34:38.96#ibcon#read 5, iclass 20, count 2 2006.211.07:34:38.96#ibcon#about to read 6, iclass 20, count 2 2006.211.07:34:38.96#ibcon#read 6, iclass 20, count 2 2006.211.07:34:38.96#ibcon#end of sib2, iclass 20, count 2 2006.211.07:34:38.96#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:34:38.96#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:34:38.96#ibcon#[25=AT05-07\r\n] 2006.211.07:34:38.96#ibcon#*before write, iclass 20, count 2 2006.211.07:34:38.96#ibcon#enter sib2, iclass 20, count 2 2006.211.07:34:38.96#ibcon#flushed, iclass 20, count 2 2006.211.07:34:38.96#ibcon#about to write, iclass 20, count 2 2006.211.07:34:38.96#ibcon#wrote, iclass 20, count 2 2006.211.07:34:38.96#ibcon#about to read 3, iclass 20, count 2 2006.211.07:34:38.99#ibcon#read 3, iclass 20, count 2 2006.211.07:34:38.99#ibcon#about to read 4, iclass 20, count 2 2006.211.07:34:38.99#ibcon#read 4, iclass 20, count 2 2006.211.07:34:38.99#ibcon#about to read 5, iclass 20, count 2 2006.211.07:34:38.99#ibcon#read 5, iclass 20, count 2 2006.211.07:34:38.99#ibcon#about to read 6, iclass 20, count 2 2006.211.07:34:38.99#ibcon#read 6, iclass 20, count 2 2006.211.07:34:38.99#ibcon#end of sib2, iclass 20, count 2 2006.211.07:34:38.99#ibcon#*after write, iclass 20, count 2 2006.211.07:34:38.99#ibcon#*before return 0, iclass 20, count 2 2006.211.07:34:38.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:38.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:38.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:34:38.99#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:38.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:39.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:39.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:39.11#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:34:39.11#ibcon#first serial, iclass 20, count 0 2006.211.07:34:39.11#ibcon#enter sib2, iclass 20, count 0 2006.211.07:34:39.11#ibcon#flushed, iclass 20, count 0 2006.211.07:34:39.11#ibcon#about to write, iclass 20, count 0 2006.211.07:34:39.11#ibcon#wrote, iclass 20, count 0 2006.211.07:34:39.11#ibcon#about to read 3, iclass 20, count 0 2006.211.07:34:39.13#ibcon#read 3, iclass 20, count 0 2006.211.07:34:39.13#ibcon#about to read 4, iclass 20, count 0 2006.211.07:34:39.13#ibcon#read 4, iclass 20, count 0 2006.211.07:34:39.13#ibcon#about to read 5, iclass 20, count 0 2006.211.07:34:39.13#ibcon#read 5, iclass 20, count 0 2006.211.07:34:39.13#ibcon#about to read 6, iclass 20, count 0 2006.211.07:34:39.13#ibcon#read 6, iclass 20, count 0 2006.211.07:34:39.13#ibcon#end of sib2, iclass 20, count 0 2006.211.07:34:39.13#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:34:39.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:34:39.13#ibcon#[25=USB\r\n] 2006.211.07:34:39.13#ibcon#*before write, iclass 20, count 0 2006.211.07:34:39.13#ibcon#enter sib2, iclass 20, count 0 2006.211.07:34:39.13#ibcon#flushed, iclass 20, count 0 2006.211.07:34:39.13#ibcon#about to write, iclass 20, count 0 2006.211.07:34:39.13#ibcon#wrote, iclass 20, count 0 2006.211.07:34:39.13#ibcon#about to read 3, iclass 20, count 0 2006.211.07:34:39.16#ibcon#read 3, iclass 20, count 0 2006.211.07:34:39.16#ibcon#about to read 4, iclass 20, count 0 2006.211.07:34:39.16#ibcon#read 4, iclass 20, count 0 2006.211.07:34:39.16#ibcon#about to read 5, iclass 20, count 0 2006.211.07:34:39.16#ibcon#read 5, iclass 20, count 0 2006.211.07:34:39.16#ibcon#about to read 6, iclass 20, count 0 2006.211.07:34:39.16#ibcon#read 6, iclass 20, count 0 2006.211.07:34:39.16#ibcon#end of sib2, iclass 20, count 0 2006.211.07:34:39.16#ibcon#*after write, iclass 20, count 0 2006.211.07:34:39.16#ibcon#*before return 0, iclass 20, count 0 2006.211.07:34:39.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:39.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:39.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:34:39.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:34:39.16$vc4f8/valo=6,772.99 2006.211.07:34:39.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:34:39.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:34:39.16#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:39.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:39.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:39.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:39.16#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:34:39.16#ibcon#first serial, iclass 22, count 0 2006.211.07:34:39.16#ibcon#enter sib2, iclass 22, count 0 2006.211.07:34:39.16#ibcon#flushed, iclass 22, count 0 2006.211.07:34:39.16#ibcon#about to write, iclass 22, count 0 2006.211.07:34:39.16#ibcon#wrote, iclass 22, count 0 2006.211.07:34:39.16#ibcon#about to read 3, iclass 22, count 0 2006.211.07:34:39.18#ibcon#read 3, iclass 22, count 0 2006.211.07:34:39.18#ibcon#about to read 4, iclass 22, count 0 2006.211.07:34:39.18#ibcon#read 4, iclass 22, count 0 2006.211.07:34:39.18#ibcon#about to read 5, iclass 22, count 0 2006.211.07:34:39.18#ibcon#read 5, iclass 22, count 0 2006.211.07:34:39.18#ibcon#about to read 6, iclass 22, count 0 2006.211.07:34:39.18#ibcon#read 6, iclass 22, count 0 2006.211.07:34:39.18#ibcon#end of sib2, iclass 22, count 0 2006.211.07:34:39.18#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:34:39.18#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:34:39.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:34:39.18#ibcon#*before write, iclass 22, count 0 2006.211.07:34:39.18#ibcon#enter sib2, iclass 22, count 0 2006.211.07:34:39.18#ibcon#flushed, iclass 22, count 0 2006.211.07:34:39.18#ibcon#about to write, iclass 22, count 0 2006.211.07:34:39.18#ibcon#wrote, iclass 22, count 0 2006.211.07:34:39.18#ibcon#about to read 3, iclass 22, count 0 2006.211.07:34:39.22#ibcon#read 3, iclass 22, count 0 2006.211.07:34:39.22#ibcon#about to read 4, iclass 22, count 0 2006.211.07:34:39.22#ibcon#read 4, iclass 22, count 0 2006.211.07:34:39.22#ibcon#about to read 5, iclass 22, count 0 2006.211.07:34:39.22#ibcon#read 5, iclass 22, count 0 2006.211.07:34:39.22#ibcon#about to read 6, iclass 22, count 0 2006.211.07:34:39.22#ibcon#read 6, iclass 22, count 0 2006.211.07:34:39.22#ibcon#end of sib2, iclass 22, count 0 2006.211.07:34:39.22#ibcon#*after write, iclass 22, count 0 2006.211.07:34:39.22#ibcon#*before return 0, iclass 22, count 0 2006.211.07:34:39.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:39.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:39.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:34:39.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:34:39.22$vc4f8/va=6,6 2006.211.07:34:39.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:34:39.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:34:39.22#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:39.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:39.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:39.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:39.28#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:34:39.28#ibcon#first serial, iclass 24, count 2 2006.211.07:34:39.28#ibcon#enter sib2, iclass 24, count 2 2006.211.07:34:39.28#ibcon#flushed, iclass 24, count 2 2006.211.07:34:39.28#ibcon#about to write, iclass 24, count 2 2006.211.07:34:39.28#ibcon#wrote, iclass 24, count 2 2006.211.07:34:39.28#ibcon#about to read 3, iclass 24, count 2 2006.211.07:34:39.30#ibcon#read 3, iclass 24, count 2 2006.211.07:34:39.30#ibcon#about to read 4, iclass 24, count 2 2006.211.07:34:39.30#ibcon#read 4, iclass 24, count 2 2006.211.07:34:39.30#ibcon#about to read 5, iclass 24, count 2 2006.211.07:34:39.30#ibcon#read 5, iclass 24, count 2 2006.211.07:34:39.30#ibcon#about to read 6, iclass 24, count 2 2006.211.07:34:39.30#ibcon#read 6, iclass 24, count 2 2006.211.07:34:39.30#ibcon#end of sib2, iclass 24, count 2 2006.211.07:34:39.30#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:34:39.30#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:34:39.30#ibcon#[25=AT06-06\r\n] 2006.211.07:34:39.30#ibcon#*before write, iclass 24, count 2 2006.211.07:34:39.30#ibcon#enter sib2, iclass 24, count 2 2006.211.07:34:39.30#ibcon#flushed, iclass 24, count 2 2006.211.07:34:39.30#ibcon#about to write, iclass 24, count 2 2006.211.07:34:39.30#ibcon#wrote, iclass 24, count 2 2006.211.07:34:39.30#ibcon#about to read 3, iclass 24, count 2 2006.211.07:34:39.33#ibcon#read 3, iclass 24, count 2 2006.211.07:34:39.33#ibcon#about to read 4, iclass 24, count 2 2006.211.07:34:39.33#ibcon#read 4, iclass 24, count 2 2006.211.07:34:39.33#ibcon#about to read 5, iclass 24, count 2 2006.211.07:34:39.33#ibcon#read 5, iclass 24, count 2 2006.211.07:34:39.33#ibcon#about to read 6, iclass 24, count 2 2006.211.07:34:39.33#ibcon#read 6, iclass 24, count 2 2006.211.07:34:39.33#ibcon#end of sib2, iclass 24, count 2 2006.211.07:34:39.33#ibcon#*after write, iclass 24, count 2 2006.211.07:34:39.33#ibcon#*before return 0, iclass 24, count 2 2006.211.07:34:39.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:39.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:39.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:34:39.33#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:39.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:39.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:39.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:39.45#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:34:39.45#ibcon#first serial, iclass 24, count 0 2006.211.07:34:39.45#ibcon#enter sib2, iclass 24, count 0 2006.211.07:34:39.45#ibcon#flushed, iclass 24, count 0 2006.211.07:34:39.45#ibcon#about to write, iclass 24, count 0 2006.211.07:34:39.45#ibcon#wrote, iclass 24, count 0 2006.211.07:34:39.45#ibcon#about to read 3, iclass 24, count 0 2006.211.07:34:39.47#ibcon#read 3, iclass 24, count 0 2006.211.07:34:39.47#ibcon#about to read 4, iclass 24, count 0 2006.211.07:34:39.47#ibcon#read 4, iclass 24, count 0 2006.211.07:34:39.47#ibcon#about to read 5, iclass 24, count 0 2006.211.07:34:39.47#ibcon#read 5, iclass 24, count 0 2006.211.07:34:39.47#ibcon#about to read 6, iclass 24, count 0 2006.211.07:34:39.47#ibcon#read 6, iclass 24, count 0 2006.211.07:34:39.47#ibcon#end of sib2, iclass 24, count 0 2006.211.07:34:39.47#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:34:39.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:34:39.47#ibcon#[25=USB\r\n] 2006.211.07:34:39.47#ibcon#*before write, iclass 24, count 0 2006.211.07:34:39.47#ibcon#enter sib2, iclass 24, count 0 2006.211.07:34:39.47#ibcon#flushed, iclass 24, count 0 2006.211.07:34:39.47#ibcon#about to write, iclass 24, count 0 2006.211.07:34:39.47#ibcon#wrote, iclass 24, count 0 2006.211.07:34:39.47#ibcon#about to read 3, iclass 24, count 0 2006.211.07:34:39.50#ibcon#read 3, iclass 24, count 0 2006.211.07:34:39.50#ibcon#about to read 4, iclass 24, count 0 2006.211.07:34:39.50#ibcon#read 4, iclass 24, count 0 2006.211.07:34:39.50#ibcon#about to read 5, iclass 24, count 0 2006.211.07:34:39.50#ibcon#read 5, iclass 24, count 0 2006.211.07:34:39.50#ibcon#about to read 6, iclass 24, count 0 2006.211.07:34:39.50#ibcon#read 6, iclass 24, count 0 2006.211.07:34:39.50#ibcon#end of sib2, iclass 24, count 0 2006.211.07:34:39.50#ibcon#*after write, iclass 24, count 0 2006.211.07:34:39.50#ibcon#*before return 0, iclass 24, count 0 2006.211.07:34:39.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:39.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:39.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:34:39.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:34:39.50$vc4f8/valo=7,832.99 2006.211.07:34:39.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:34:39.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:34:39.50#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:39.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:39.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:39.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:39.50#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:34:39.50#ibcon#first serial, iclass 26, count 0 2006.211.07:34:39.50#ibcon#enter sib2, iclass 26, count 0 2006.211.07:34:39.50#ibcon#flushed, iclass 26, count 0 2006.211.07:34:39.50#ibcon#about to write, iclass 26, count 0 2006.211.07:34:39.50#ibcon#wrote, iclass 26, count 0 2006.211.07:34:39.50#ibcon#about to read 3, iclass 26, count 0 2006.211.07:34:39.52#ibcon#read 3, iclass 26, count 0 2006.211.07:34:39.52#ibcon#about to read 4, iclass 26, count 0 2006.211.07:34:39.52#ibcon#read 4, iclass 26, count 0 2006.211.07:34:39.52#ibcon#about to read 5, iclass 26, count 0 2006.211.07:34:39.52#ibcon#read 5, iclass 26, count 0 2006.211.07:34:39.52#ibcon#about to read 6, iclass 26, count 0 2006.211.07:34:39.52#ibcon#read 6, iclass 26, count 0 2006.211.07:34:39.52#ibcon#end of sib2, iclass 26, count 0 2006.211.07:34:39.52#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:34:39.52#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:34:39.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:34:39.52#ibcon#*before write, iclass 26, count 0 2006.211.07:34:39.52#ibcon#enter sib2, iclass 26, count 0 2006.211.07:34:39.52#ibcon#flushed, iclass 26, count 0 2006.211.07:34:39.52#ibcon#about to write, iclass 26, count 0 2006.211.07:34:39.52#ibcon#wrote, iclass 26, count 0 2006.211.07:34:39.52#ibcon#about to read 3, iclass 26, count 0 2006.211.07:34:39.56#ibcon#read 3, iclass 26, count 0 2006.211.07:34:39.56#ibcon#about to read 4, iclass 26, count 0 2006.211.07:34:39.56#ibcon#read 4, iclass 26, count 0 2006.211.07:34:39.56#ibcon#about to read 5, iclass 26, count 0 2006.211.07:34:39.56#ibcon#read 5, iclass 26, count 0 2006.211.07:34:39.56#ibcon#about to read 6, iclass 26, count 0 2006.211.07:34:39.56#ibcon#read 6, iclass 26, count 0 2006.211.07:34:39.56#ibcon#end of sib2, iclass 26, count 0 2006.211.07:34:39.56#ibcon#*after write, iclass 26, count 0 2006.211.07:34:39.56#ibcon#*before return 0, iclass 26, count 0 2006.211.07:34:39.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:39.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:39.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:34:39.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:34:39.56$vc4f8/va=7,6 2006.211.07:34:39.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.07:34:39.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.07:34:39.56#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:39.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:34:39.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:34:39.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:34:39.62#ibcon#enter wrdev, iclass 28, count 2 2006.211.07:34:39.62#ibcon#first serial, iclass 28, count 2 2006.211.07:34:39.62#ibcon#enter sib2, iclass 28, count 2 2006.211.07:34:39.62#ibcon#flushed, iclass 28, count 2 2006.211.07:34:39.62#ibcon#about to write, iclass 28, count 2 2006.211.07:34:39.62#ibcon#wrote, iclass 28, count 2 2006.211.07:34:39.62#ibcon#about to read 3, iclass 28, count 2 2006.211.07:34:39.64#ibcon#read 3, iclass 28, count 2 2006.211.07:34:39.64#ibcon#about to read 4, iclass 28, count 2 2006.211.07:34:39.64#ibcon#read 4, iclass 28, count 2 2006.211.07:34:39.64#ibcon#about to read 5, iclass 28, count 2 2006.211.07:34:39.64#ibcon#read 5, iclass 28, count 2 2006.211.07:34:39.64#ibcon#about to read 6, iclass 28, count 2 2006.211.07:34:39.64#ibcon#read 6, iclass 28, count 2 2006.211.07:34:39.64#ibcon#end of sib2, iclass 28, count 2 2006.211.07:34:39.64#ibcon#*mode == 0, iclass 28, count 2 2006.211.07:34:39.64#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.07:34:39.64#ibcon#[25=AT07-06\r\n] 2006.211.07:34:39.64#ibcon#*before write, iclass 28, count 2 2006.211.07:34:39.64#ibcon#enter sib2, iclass 28, count 2 2006.211.07:34:39.64#ibcon#flushed, iclass 28, count 2 2006.211.07:34:39.64#ibcon#about to write, iclass 28, count 2 2006.211.07:34:39.64#ibcon#wrote, iclass 28, count 2 2006.211.07:34:39.64#ibcon#about to read 3, iclass 28, count 2 2006.211.07:34:39.67#ibcon#read 3, iclass 28, count 2 2006.211.07:34:39.67#ibcon#about to read 4, iclass 28, count 2 2006.211.07:34:39.67#ibcon#read 4, iclass 28, count 2 2006.211.07:34:39.67#ibcon#about to read 5, iclass 28, count 2 2006.211.07:34:39.67#ibcon#read 5, iclass 28, count 2 2006.211.07:34:39.67#ibcon#about to read 6, iclass 28, count 2 2006.211.07:34:39.67#ibcon#read 6, iclass 28, count 2 2006.211.07:34:39.67#ibcon#end of sib2, iclass 28, count 2 2006.211.07:34:39.67#ibcon#*after write, iclass 28, count 2 2006.211.07:34:39.67#ibcon#*before return 0, iclass 28, count 2 2006.211.07:34:39.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:34:39.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:34:39.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.07:34:39.67#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:39.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:34:39.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:34:39.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:34:39.79#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:34:39.79#ibcon#first serial, iclass 28, count 0 2006.211.07:34:39.79#ibcon#enter sib2, iclass 28, count 0 2006.211.07:34:39.79#ibcon#flushed, iclass 28, count 0 2006.211.07:34:39.79#ibcon#about to write, iclass 28, count 0 2006.211.07:34:39.79#ibcon#wrote, iclass 28, count 0 2006.211.07:34:39.79#ibcon#about to read 3, iclass 28, count 0 2006.211.07:34:39.81#ibcon#read 3, iclass 28, count 0 2006.211.07:34:39.81#ibcon#about to read 4, iclass 28, count 0 2006.211.07:34:39.81#ibcon#read 4, iclass 28, count 0 2006.211.07:34:39.81#ibcon#about to read 5, iclass 28, count 0 2006.211.07:34:39.81#ibcon#read 5, iclass 28, count 0 2006.211.07:34:39.81#ibcon#about to read 6, iclass 28, count 0 2006.211.07:34:39.81#ibcon#read 6, iclass 28, count 0 2006.211.07:34:39.81#ibcon#end of sib2, iclass 28, count 0 2006.211.07:34:39.81#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:34:39.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:34:39.81#ibcon#[25=USB\r\n] 2006.211.07:34:39.81#ibcon#*before write, iclass 28, count 0 2006.211.07:34:39.81#ibcon#enter sib2, iclass 28, count 0 2006.211.07:34:39.81#ibcon#flushed, iclass 28, count 0 2006.211.07:34:39.81#ibcon#about to write, iclass 28, count 0 2006.211.07:34:39.81#ibcon#wrote, iclass 28, count 0 2006.211.07:34:39.81#ibcon#about to read 3, iclass 28, count 0 2006.211.07:34:39.83#abcon#<5=/04 4.1 8.1 25.00 731010.2\r\n> 2006.211.07:34:39.84#ibcon#read 3, iclass 28, count 0 2006.211.07:34:39.84#ibcon#about to read 4, iclass 28, count 0 2006.211.07:34:39.84#ibcon#read 4, iclass 28, count 0 2006.211.07:34:39.84#ibcon#about to read 5, iclass 28, count 0 2006.211.07:34:39.84#ibcon#read 5, iclass 28, count 0 2006.211.07:34:39.84#ibcon#about to read 6, iclass 28, count 0 2006.211.07:34:39.84#ibcon#read 6, iclass 28, count 0 2006.211.07:34:39.84#ibcon#end of sib2, iclass 28, count 0 2006.211.07:34:39.84#ibcon#*after write, iclass 28, count 0 2006.211.07:34:39.84#ibcon#*before return 0, iclass 28, count 0 2006.211.07:34:39.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:34:39.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:34:39.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:34:39.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:34:39.84$vc4f8/valo=8,852.99 2006.211.07:34:39.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:34:39.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:34:39.84#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:39.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:34:39.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:34:39.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:34:39.84#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:34:39.84#ibcon#first serial, iclass 33, count 0 2006.211.07:34:39.84#ibcon#enter sib2, iclass 33, count 0 2006.211.07:34:39.84#ibcon#flushed, iclass 33, count 0 2006.211.07:34:39.84#ibcon#about to write, iclass 33, count 0 2006.211.07:34:39.84#ibcon#wrote, iclass 33, count 0 2006.211.07:34:39.84#ibcon#about to read 3, iclass 33, count 0 2006.211.07:34:39.85#abcon#{5=INTERFACE CLEAR} 2006.211.07:34:39.86#ibcon#read 3, iclass 33, count 0 2006.211.07:34:39.86#ibcon#about to read 4, iclass 33, count 0 2006.211.07:34:39.86#ibcon#read 4, iclass 33, count 0 2006.211.07:34:39.86#ibcon#about to read 5, iclass 33, count 0 2006.211.07:34:39.86#ibcon#read 5, iclass 33, count 0 2006.211.07:34:39.86#ibcon#about to read 6, iclass 33, count 0 2006.211.07:34:39.86#ibcon#read 6, iclass 33, count 0 2006.211.07:34:39.86#ibcon#end of sib2, iclass 33, count 0 2006.211.07:34:39.86#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:34:39.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:34:39.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:34:39.86#ibcon#*before write, iclass 33, count 0 2006.211.07:34:39.86#ibcon#enter sib2, iclass 33, count 0 2006.211.07:34:39.86#ibcon#flushed, iclass 33, count 0 2006.211.07:34:39.86#ibcon#about to write, iclass 33, count 0 2006.211.07:34:39.86#ibcon#wrote, iclass 33, count 0 2006.211.07:34:39.86#ibcon#about to read 3, iclass 33, count 0 2006.211.07:34:39.90#ibcon#read 3, iclass 33, count 0 2006.211.07:34:39.90#ibcon#about to read 4, iclass 33, count 0 2006.211.07:34:39.90#ibcon#read 4, iclass 33, count 0 2006.211.07:34:39.90#ibcon#about to read 5, iclass 33, count 0 2006.211.07:34:39.90#ibcon#read 5, iclass 33, count 0 2006.211.07:34:39.90#ibcon#about to read 6, iclass 33, count 0 2006.211.07:34:39.90#ibcon#read 6, iclass 33, count 0 2006.211.07:34:39.90#ibcon#end of sib2, iclass 33, count 0 2006.211.07:34:39.90#ibcon#*after write, iclass 33, count 0 2006.211.07:34:39.90#ibcon#*before return 0, iclass 33, count 0 2006.211.07:34:39.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:34:39.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:34:39.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:34:39.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:34:39.90$vc4f8/va=8,7 2006.211.07:34:39.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.07:34:39.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.07:34:39.90#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:39.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:34:39.91#abcon#[5=S1D000X0/0*\r\n] 2006.211.07:34:39.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:34:39.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:34:39.96#ibcon#enter wrdev, iclass 36, count 2 2006.211.07:34:39.96#ibcon#first serial, iclass 36, count 2 2006.211.07:34:39.96#ibcon#enter sib2, iclass 36, count 2 2006.211.07:34:39.96#ibcon#flushed, iclass 36, count 2 2006.211.07:34:39.96#ibcon#about to write, iclass 36, count 2 2006.211.07:34:39.96#ibcon#wrote, iclass 36, count 2 2006.211.07:34:39.96#ibcon#about to read 3, iclass 36, count 2 2006.211.07:34:39.98#ibcon#read 3, iclass 36, count 2 2006.211.07:34:39.98#ibcon#about to read 4, iclass 36, count 2 2006.211.07:34:39.98#ibcon#read 4, iclass 36, count 2 2006.211.07:34:39.98#ibcon#about to read 5, iclass 36, count 2 2006.211.07:34:39.98#ibcon#read 5, iclass 36, count 2 2006.211.07:34:39.98#ibcon#about to read 6, iclass 36, count 2 2006.211.07:34:39.98#ibcon#read 6, iclass 36, count 2 2006.211.07:34:39.98#ibcon#end of sib2, iclass 36, count 2 2006.211.07:34:39.98#ibcon#*mode == 0, iclass 36, count 2 2006.211.07:34:39.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.07:34:39.98#ibcon#[25=AT08-07\r\n] 2006.211.07:34:39.98#ibcon#*before write, iclass 36, count 2 2006.211.07:34:39.98#ibcon#enter sib2, iclass 36, count 2 2006.211.07:34:39.98#ibcon#flushed, iclass 36, count 2 2006.211.07:34:39.98#ibcon#about to write, iclass 36, count 2 2006.211.07:34:39.98#ibcon#wrote, iclass 36, count 2 2006.211.07:34:39.98#ibcon#about to read 3, iclass 36, count 2 2006.211.07:34:40.01#ibcon#read 3, iclass 36, count 2 2006.211.07:34:40.01#ibcon#about to read 4, iclass 36, count 2 2006.211.07:34:40.01#ibcon#read 4, iclass 36, count 2 2006.211.07:34:40.01#ibcon#about to read 5, iclass 36, count 2 2006.211.07:34:40.01#ibcon#read 5, iclass 36, count 2 2006.211.07:34:40.01#ibcon#about to read 6, iclass 36, count 2 2006.211.07:34:40.01#ibcon#read 6, iclass 36, count 2 2006.211.07:34:40.01#ibcon#end of sib2, iclass 36, count 2 2006.211.07:34:40.01#ibcon#*after write, iclass 36, count 2 2006.211.07:34:40.01#ibcon#*before return 0, iclass 36, count 2 2006.211.07:34:40.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:34:40.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:34:40.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.07:34:40.01#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:40.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:34:40.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:34:40.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:34:40.13#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:34:40.13#ibcon#first serial, iclass 36, count 0 2006.211.07:34:40.13#ibcon#enter sib2, iclass 36, count 0 2006.211.07:34:40.13#ibcon#flushed, iclass 36, count 0 2006.211.07:34:40.13#ibcon#about to write, iclass 36, count 0 2006.211.07:34:40.13#ibcon#wrote, iclass 36, count 0 2006.211.07:34:40.13#ibcon#about to read 3, iclass 36, count 0 2006.211.07:34:40.15#ibcon#read 3, iclass 36, count 0 2006.211.07:34:40.15#ibcon#about to read 4, iclass 36, count 0 2006.211.07:34:40.15#ibcon#read 4, iclass 36, count 0 2006.211.07:34:40.15#ibcon#about to read 5, iclass 36, count 0 2006.211.07:34:40.15#ibcon#read 5, iclass 36, count 0 2006.211.07:34:40.15#ibcon#about to read 6, iclass 36, count 0 2006.211.07:34:40.15#ibcon#read 6, iclass 36, count 0 2006.211.07:34:40.15#ibcon#end of sib2, iclass 36, count 0 2006.211.07:34:40.15#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:34:40.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:34:40.15#ibcon#[25=USB\r\n] 2006.211.07:34:40.15#ibcon#*before write, iclass 36, count 0 2006.211.07:34:40.15#ibcon#enter sib2, iclass 36, count 0 2006.211.07:34:40.15#ibcon#flushed, iclass 36, count 0 2006.211.07:34:40.15#ibcon#about to write, iclass 36, count 0 2006.211.07:34:40.15#ibcon#wrote, iclass 36, count 0 2006.211.07:34:40.15#ibcon#about to read 3, iclass 36, count 0 2006.211.07:34:40.18#ibcon#read 3, iclass 36, count 0 2006.211.07:34:40.18#ibcon#about to read 4, iclass 36, count 0 2006.211.07:34:40.18#ibcon#read 4, iclass 36, count 0 2006.211.07:34:40.18#ibcon#about to read 5, iclass 36, count 0 2006.211.07:34:40.18#ibcon#read 5, iclass 36, count 0 2006.211.07:34:40.18#ibcon#about to read 6, iclass 36, count 0 2006.211.07:34:40.18#ibcon#read 6, iclass 36, count 0 2006.211.07:34:40.18#ibcon#end of sib2, iclass 36, count 0 2006.211.07:34:40.18#ibcon#*after write, iclass 36, count 0 2006.211.07:34:40.18#ibcon#*before return 0, iclass 36, count 0 2006.211.07:34:40.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:34:40.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:34:40.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:34:40.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:34:40.18$vc4f8/vblo=1,632.99 2006.211.07:34:40.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.07:34:40.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.07:34:40.18#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:40.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:40.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:40.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:40.18#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:34:40.18#ibcon#first serial, iclass 38, count 0 2006.211.07:34:40.18#ibcon#enter sib2, iclass 38, count 0 2006.211.07:34:40.18#ibcon#flushed, iclass 38, count 0 2006.211.07:34:40.18#ibcon#about to write, iclass 38, count 0 2006.211.07:34:40.18#ibcon#wrote, iclass 38, count 0 2006.211.07:34:40.18#ibcon#about to read 3, iclass 38, count 0 2006.211.07:34:40.20#ibcon#read 3, iclass 38, count 0 2006.211.07:34:40.20#ibcon#about to read 4, iclass 38, count 0 2006.211.07:34:40.20#ibcon#read 4, iclass 38, count 0 2006.211.07:34:40.20#ibcon#about to read 5, iclass 38, count 0 2006.211.07:34:40.20#ibcon#read 5, iclass 38, count 0 2006.211.07:34:40.20#ibcon#about to read 6, iclass 38, count 0 2006.211.07:34:40.20#ibcon#read 6, iclass 38, count 0 2006.211.07:34:40.20#ibcon#end of sib2, iclass 38, count 0 2006.211.07:34:40.20#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:34:40.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:34:40.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:34:40.20#ibcon#*before write, iclass 38, count 0 2006.211.07:34:40.20#ibcon#enter sib2, iclass 38, count 0 2006.211.07:34:40.20#ibcon#flushed, iclass 38, count 0 2006.211.07:34:40.20#ibcon#about to write, iclass 38, count 0 2006.211.07:34:40.20#ibcon#wrote, iclass 38, count 0 2006.211.07:34:40.20#ibcon#about to read 3, iclass 38, count 0 2006.211.07:34:40.24#ibcon#read 3, iclass 38, count 0 2006.211.07:34:40.24#ibcon#about to read 4, iclass 38, count 0 2006.211.07:34:40.24#ibcon#read 4, iclass 38, count 0 2006.211.07:34:40.24#ibcon#about to read 5, iclass 38, count 0 2006.211.07:34:40.24#ibcon#read 5, iclass 38, count 0 2006.211.07:34:40.24#ibcon#about to read 6, iclass 38, count 0 2006.211.07:34:40.24#ibcon#read 6, iclass 38, count 0 2006.211.07:34:40.24#ibcon#end of sib2, iclass 38, count 0 2006.211.07:34:40.24#ibcon#*after write, iclass 38, count 0 2006.211.07:34:40.24#ibcon#*before return 0, iclass 38, count 0 2006.211.07:34:40.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:40.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:34:40.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:34:40.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:34:40.24$vc4f8/vb=1,4 2006.211.07:34:40.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.07:34:40.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.07:34:40.24#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:40.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:40.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:40.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:40.24#ibcon#enter wrdev, iclass 40, count 2 2006.211.07:34:40.24#ibcon#first serial, iclass 40, count 2 2006.211.07:34:40.24#ibcon#enter sib2, iclass 40, count 2 2006.211.07:34:40.24#ibcon#flushed, iclass 40, count 2 2006.211.07:34:40.24#ibcon#about to write, iclass 40, count 2 2006.211.07:34:40.24#ibcon#wrote, iclass 40, count 2 2006.211.07:34:40.24#ibcon#about to read 3, iclass 40, count 2 2006.211.07:34:40.26#ibcon#read 3, iclass 40, count 2 2006.211.07:34:40.26#ibcon#about to read 4, iclass 40, count 2 2006.211.07:34:40.26#ibcon#read 4, iclass 40, count 2 2006.211.07:34:40.26#ibcon#about to read 5, iclass 40, count 2 2006.211.07:34:40.26#ibcon#read 5, iclass 40, count 2 2006.211.07:34:40.26#ibcon#about to read 6, iclass 40, count 2 2006.211.07:34:40.26#ibcon#read 6, iclass 40, count 2 2006.211.07:34:40.26#ibcon#end of sib2, iclass 40, count 2 2006.211.07:34:40.26#ibcon#*mode == 0, iclass 40, count 2 2006.211.07:34:40.26#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.07:34:40.26#ibcon#[27=AT01-04\r\n] 2006.211.07:34:40.26#ibcon#*before write, iclass 40, count 2 2006.211.07:34:40.26#ibcon#enter sib2, iclass 40, count 2 2006.211.07:34:40.26#ibcon#flushed, iclass 40, count 2 2006.211.07:34:40.26#ibcon#about to write, iclass 40, count 2 2006.211.07:34:40.26#ibcon#wrote, iclass 40, count 2 2006.211.07:34:40.26#ibcon#about to read 3, iclass 40, count 2 2006.211.07:34:40.29#ibcon#read 3, iclass 40, count 2 2006.211.07:34:40.29#ibcon#about to read 4, iclass 40, count 2 2006.211.07:34:40.29#ibcon#read 4, iclass 40, count 2 2006.211.07:34:40.29#ibcon#about to read 5, iclass 40, count 2 2006.211.07:34:40.29#ibcon#read 5, iclass 40, count 2 2006.211.07:34:40.29#ibcon#about to read 6, iclass 40, count 2 2006.211.07:34:40.29#ibcon#read 6, iclass 40, count 2 2006.211.07:34:40.29#ibcon#end of sib2, iclass 40, count 2 2006.211.07:34:40.29#ibcon#*after write, iclass 40, count 2 2006.211.07:34:40.29#ibcon#*before return 0, iclass 40, count 2 2006.211.07:34:40.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:40.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:34:40.29#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.07:34:40.29#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:40.29#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:40.41#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:40.41#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:40.41#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:34:40.41#ibcon#first serial, iclass 40, count 0 2006.211.07:34:40.41#ibcon#enter sib2, iclass 40, count 0 2006.211.07:34:40.41#ibcon#flushed, iclass 40, count 0 2006.211.07:34:40.41#ibcon#about to write, iclass 40, count 0 2006.211.07:34:40.41#ibcon#wrote, iclass 40, count 0 2006.211.07:34:40.41#ibcon#about to read 3, iclass 40, count 0 2006.211.07:34:40.43#ibcon#read 3, iclass 40, count 0 2006.211.07:34:40.43#ibcon#about to read 4, iclass 40, count 0 2006.211.07:34:40.43#ibcon#read 4, iclass 40, count 0 2006.211.07:34:40.43#ibcon#about to read 5, iclass 40, count 0 2006.211.07:34:40.43#ibcon#read 5, iclass 40, count 0 2006.211.07:34:40.43#ibcon#about to read 6, iclass 40, count 0 2006.211.07:34:40.43#ibcon#read 6, iclass 40, count 0 2006.211.07:34:40.43#ibcon#end of sib2, iclass 40, count 0 2006.211.07:34:40.43#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:34:40.43#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:34:40.43#ibcon#[27=USB\r\n] 2006.211.07:34:40.43#ibcon#*before write, iclass 40, count 0 2006.211.07:34:40.43#ibcon#enter sib2, iclass 40, count 0 2006.211.07:34:40.43#ibcon#flushed, iclass 40, count 0 2006.211.07:34:40.43#ibcon#about to write, iclass 40, count 0 2006.211.07:34:40.43#ibcon#wrote, iclass 40, count 0 2006.211.07:34:40.43#ibcon#about to read 3, iclass 40, count 0 2006.211.07:34:40.46#ibcon#read 3, iclass 40, count 0 2006.211.07:34:40.46#ibcon#about to read 4, iclass 40, count 0 2006.211.07:34:40.46#ibcon#read 4, iclass 40, count 0 2006.211.07:34:40.46#ibcon#about to read 5, iclass 40, count 0 2006.211.07:34:40.46#ibcon#read 5, iclass 40, count 0 2006.211.07:34:40.46#ibcon#about to read 6, iclass 40, count 0 2006.211.07:34:40.46#ibcon#read 6, iclass 40, count 0 2006.211.07:34:40.46#ibcon#end of sib2, iclass 40, count 0 2006.211.07:34:40.46#ibcon#*after write, iclass 40, count 0 2006.211.07:34:40.46#ibcon#*before return 0, iclass 40, count 0 2006.211.07:34:40.46#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:40.46#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:34:40.46#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:34:40.46#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:34:40.46$vc4f8/vblo=2,640.99 2006.211.07:34:40.46#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.07:34:40.46#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.07:34:40.46#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:40.46#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:40.46#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:40.46#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:40.46#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:34:40.46#ibcon#first serial, iclass 4, count 0 2006.211.07:34:40.46#ibcon#enter sib2, iclass 4, count 0 2006.211.07:34:40.46#ibcon#flushed, iclass 4, count 0 2006.211.07:34:40.46#ibcon#about to write, iclass 4, count 0 2006.211.07:34:40.46#ibcon#wrote, iclass 4, count 0 2006.211.07:34:40.46#ibcon#about to read 3, iclass 4, count 0 2006.211.07:34:40.48#ibcon#read 3, iclass 4, count 0 2006.211.07:34:40.48#ibcon#about to read 4, iclass 4, count 0 2006.211.07:34:40.48#ibcon#read 4, iclass 4, count 0 2006.211.07:34:40.48#ibcon#about to read 5, iclass 4, count 0 2006.211.07:34:40.48#ibcon#read 5, iclass 4, count 0 2006.211.07:34:40.48#ibcon#about to read 6, iclass 4, count 0 2006.211.07:34:40.48#ibcon#read 6, iclass 4, count 0 2006.211.07:34:40.48#ibcon#end of sib2, iclass 4, count 0 2006.211.07:34:40.48#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:34:40.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:34:40.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:34:40.48#ibcon#*before write, iclass 4, count 0 2006.211.07:34:40.48#ibcon#enter sib2, iclass 4, count 0 2006.211.07:34:40.48#ibcon#flushed, iclass 4, count 0 2006.211.07:34:40.48#ibcon#about to write, iclass 4, count 0 2006.211.07:34:40.48#ibcon#wrote, iclass 4, count 0 2006.211.07:34:40.48#ibcon#about to read 3, iclass 4, count 0 2006.211.07:34:40.52#ibcon#read 3, iclass 4, count 0 2006.211.07:34:40.52#ibcon#about to read 4, iclass 4, count 0 2006.211.07:34:40.52#ibcon#read 4, iclass 4, count 0 2006.211.07:34:40.52#ibcon#about to read 5, iclass 4, count 0 2006.211.07:34:40.52#ibcon#read 5, iclass 4, count 0 2006.211.07:34:40.52#ibcon#about to read 6, iclass 4, count 0 2006.211.07:34:40.52#ibcon#read 6, iclass 4, count 0 2006.211.07:34:40.52#ibcon#end of sib2, iclass 4, count 0 2006.211.07:34:40.52#ibcon#*after write, iclass 4, count 0 2006.211.07:34:40.52#ibcon#*before return 0, iclass 4, count 0 2006.211.07:34:40.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:40.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:34:40.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:34:40.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:34:40.52$vc4f8/vb=2,4 2006.211.07:34:40.52#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.07:34:40.52#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.07:34:40.52#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:40.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:40.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:40.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:40.58#ibcon#enter wrdev, iclass 6, count 2 2006.211.07:34:40.58#ibcon#first serial, iclass 6, count 2 2006.211.07:34:40.58#ibcon#enter sib2, iclass 6, count 2 2006.211.07:34:40.58#ibcon#flushed, iclass 6, count 2 2006.211.07:34:40.58#ibcon#about to write, iclass 6, count 2 2006.211.07:34:40.58#ibcon#wrote, iclass 6, count 2 2006.211.07:34:40.58#ibcon#about to read 3, iclass 6, count 2 2006.211.07:34:40.60#ibcon#read 3, iclass 6, count 2 2006.211.07:34:40.60#ibcon#about to read 4, iclass 6, count 2 2006.211.07:34:40.60#ibcon#read 4, iclass 6, count 2 2006.211.07:34:40.60#ibcon#about to read 5, iclass 6, count 2 2006.211.07:34:40.60#ibcon#read 5, iclass 6, count 2 2006.211.07:34:40.60#ibcon#about to read 6, iclass 6, count 2 2006.211.07:34:40.60#ibcon#read 6, iclass 6, count 2 2006.211.07:34:40.60#ibcon#end of sib2, iclass 6, count 2 2006.211.07:34:40.60#ibcon#*mode == 0, iclass 6, count 2 2006.211.07:34:40.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.07:34:40.60#ibcon#[27=AT02-04\r\n] 2006.211.07:34:40.60#ibcon#*before write, iclass 6, count 2 2006.211.07:34:40.60#ibcon#enter sib2, iclass 6, count 2 2006.211.07:34:40.60#ibcon#flushed, iclass 6, count 2 2006.211.07:34:40.60#ibcon#about to write, iclass 6, count 2 2006.211.07:34:40.60#ibcon#wrote, iclass 6, count 2 2006.211.07:34:40.60#ibcon#about to read 3, iclass 6, count 2 2006.211.07:34:40.63#ibcon#read 3, iclass 6, count 2 2006.211.07:34:40.63#ibcon#about to read 4, iclass 6, count 2 2006.211.07:34:40.63#ibcon#read 4, iclass 6, count 2 2006.211.07:34:40.63#ibcon#about to read 5, iclass 6, count 2 2006.211.07:34:40.63#ibcon#read 5, iclass 6, count 2 2006.211.07:34:40.63#ibcon#about to read 6, iclass 6, count 2 2006.211.07:34:40.63#ibcon#read 6, iclass 6, count 2 2006.211.07:34:40.63#ibcon#end of sib2, iclass 6, count 2 2006.211.07:34:40.63#ibcon#*after write, iclass 6, count 2 2006.211.07:34:40.63#ibcon#*before return 0, iclass 6, count 2 2006.211.07:34:40.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:40.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:34:40.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.07:34:40.63#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:40.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:40.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:40.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:40.75#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:34:40.75#ibcon#first serial, iclass 6, count 0 2006.211.07:34:40.75#ibcon#enter sib2, iclass 6, count 0 2006.211.07:34:40.75#ibcon#flushed, iclass 6, count 0 2006.211.07:34:40.75#ibcon#about to write, iclass 6, count 0 2006.211.07:34:40.75#ibcon#wrote, iclass 6, count 0 2006.211.07:34:40.75#ibcon#about to read 3, iclass 6, count 0 2006.211.07:34:40.77#ibcon#read 3, iclass 6, count 0 2006.211.07:34:40.77#ibcon#about to read 4, iclass 6, count 0 2006.211.07:34:40.77#ibcon#read 4, iclass 6, count 0 2006.211.07:34:40.77#ibcon#about to read 5, iclass 6, count 0 2006.211.07:34:40.77#ibcon#read 5, iclass 6, count 0 2006.211.07:34:40.77#ibcon#about to read 6, iclass 6, count 0 2006.211.07:34:40.77#ibcon#read 6, iclass 6, count 0 2006.211.07:34:40.77#ibcon#end of sib2, iclass 6, count 0 2006.211.07:34:40.77#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:34:40.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:34:40.77#ibcon#[27=USB\r\n] 2006.211.07:34:40.77#ibcon#*before write, iclass 6, count 0 2006.211.07:34:40.77#ibcon#enter sib2, iclass 6, count 0 2006.211.07:34:40.77#ibcon#flushed, iclass 6, count 0 2006.211.07:34:40.77#ibcon#about to write, iclass 6, count 0 2006.211.07:34:40.77#ibcon#wrote, iclass 6, count 0 2006.211.07:34:40.77#ibcon#about to read 3, iclass 6, count 0 2006.211.07:34:40.80#ibcon#read 3, iclass 6, count 0 2006.211.07:34:40.80#ibcon#about to read 4, iclass 6, count 0 2006.211.07:34:40.80#ibcon#read 4, iclass 6, count 0 2006.211.07:34:40.80#ibcon#about to read 5, iclass 6, count 0 2006.211.07:34:40.80#ibcon#read 5, iclass 6, count 0 2006.211.07:34:40.80#ibcon#about to read 6, iclass 6, count 0 2006.211.07:34:40.80#ibcon#read 6, iclass 6, count 0 2006.211.07:34:40.80#ibcon#end of sib2, iclass 6, count 0 2006.211.07:34:40.80#ibcon#*after write, iclass 6, count 0 2006.211.07:34:40.80#ibcon#*before return 0, iclass 6, count 0 2006.211.07:34:40.80#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:40.80#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:34:40.80#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:34:40.80#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:34:40.80$vc4f8/vblo=3,656.99 2006.211.07:34:40.80#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.07:34:40.80#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.07:34:40.80#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:40.80#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:40.80#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:40.80#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:40.80#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:34:40.80#ibcon#first serial, iclass 10, count 0 2006.211.07:34:40.80#ibcon#enter sib2, iclass 10, count 0 2006.211.07:34:40.80#ibcon#flushed, iclass 10, count 0 2006.211.07:34:40.80#ibcon#about to write, iclass 10, count 0 2006.211.07:34:40.80#ibcon#wrote, iclass 10, count 0 2006.211.07:34:40.80#ibcon#about to read 3, iclass 10, count 0 2006.211.07:34:40.82#ibcon#read 3, iclass 10, count 0 2006.211.07:34:40.82#ibcon#about to read 4, iclass 10, count 0 2006.211.07:34:40.82#ibcon#read 4, iclass 10, count 0 2006.211.07:34:40.82#ibcon#about to read 5, iclass 10, count 0 2006.211.07:34:40.82#ibcon#read 5, iclass 10, count 0 2006.211.07:34:40.82#ibcon#about to read 6, iclass 10, count 0 2006.211.07:34:40.82#ibcon#read 6, iclass 10, count 0 2006.211.07:34:40.82#ibcon#end of sib2, iclass 10, count 0 2006.211.07:34:40.82#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:34:40.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:34:40.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:34:40.82#ibcon#*before write, iclass 10, count 0 2006.211.07:34:40.82#ibcon#enter sib2, iclass 10, count 0 2006.211.07:34:40.82#ibcon#flushed, iclass 10, count 0 2006.211.07:34:40.82#ibcon#about to write, iclass 10, count 0 2006.211.07:34:40.82#ibcon#wrote, iclass 10, count 0 2006.211.07:34:40.82#ibcon#about to read 3, iclass 10, count 0 2006.211.07:34:40.86#ibcon#read 3, iclass 10, count 0 2006.211.07:34:40.86#ibcon#about to read 4, iclass 10, count 0 2006.211.07:34:40.86#ibcon#read 4, iclass 10, count 0 2006.211.07:34:40.86#ibcon#about to read 5, iclass 10, count 0 2006.211.07:34:40.86#ibcon#read 5, iclass 10, count 0 2006.211.07:34:40.86#ibcon#about to read 6, iclass 10, count 0 2006.211.07:34:40.86#ibcon#read 6, iclass 10, count 0 2006.211.07:34:40.86#ibcon#end of sib2, iclass 10, count 0 2006.211.07:34:40.86#ibcon#*after write, iclass 10, count 0 2006.211.07:34:40.86#ibcon#*before return 0, iclass 10, count 0 2006.211.07:34:40.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:40.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:34:40.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:34:40.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:34:40.86$vc4f8/vb=3,3 2006.211.07:34:40.86#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.07:34:40.86#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.07:34:40.86#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:40.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:40.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:40.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:40.92#ibcon#enter wrdev, iclass 12, count 2 2006.211.07:34:40.92#ibcon#first serial, iclass 12, count 2 2006.211.07:34:40.92#ibcon#enter sib2, iclass 12, count 2 2006.211.07:34:40.92#ibcon#flushed, iclass 12, count 2 2006.211.07:34:40.92#ibcon#about to write, iclass 12, count 2 2006.211.07:34:40.92#ibcon#wrote, iclass 12, count 2 2006.211.07:34:40.92#ibcon#about to read 3, iclass 12, count 2 2006.211.07:34:40.94#ibcon#read 3, iclass 12, count 2 2006.211.07:34:40.94#ibcon#about to read 4, iclass 12, count 2 2006.211.07:34:40.94#ibcon#read 4, iclass 12, count 2 2006.211.07:34:40.94#ibcon#about to read 5, iclass 12, count 2 2006.211.07:34:40.94#ibcon#read 5, iclass 12, count 2 2006.211.07:34:40.94#ibcon#about to read 6, iclass 12, count 2 2006.211.07:34:40.94#ibcon#read 6, iclass 12, count 2 2006.211.07:34:40.94#ibcon#end of sib2, iclass 12, count 2 2006.211.07:34:40.94#ibcon#*mode == 0, iclass 12, count 2 2006.211.07:34:40.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.07:34:40.94#ibcon#[27=AT03-03\r\n] 2006.211.07:34:40.94#ibcon#*before write, iclass 12, count 2 2006.211.07:34:40.94#ibcon#enter sib2, iclass 12, count 2 2006.211.07:34:40.94#ibcon#flushed, iclass 12, count 2 2006.211.07:34:40.94#ibcon#about to write, iclass 12, count 2 2006.211.07:34:40.94#ibcon#wrote, iclass 12, count 2 2006.211.07:34:40.94#ibcon#about to read 3, iclass 12, count 2 2006.211.07:34:40.97#ibcon#read 3, iclass 12, count 2 2006.211.07:34:40.97#ibcon#about to read 4, iclass 12, count 2 2006.211.07:34:40.97#ibcon#read 4, iclass 12, count 2 2006.211.07:34:40.97#ibcon#about to read 5, iclass 12, count 2 2006.211.07:34:40.97#ibcon#read 5, iclass 12, count 2 2006.211.07:34:40.97#ibcon#about to read 6, iclass 12, count 2 2006.211.07:34:40.97#ibcon#read 6, iclass 12, count 2 2006.211.07:34:40.97#ibcon#end of sib2, iclass 12, count 2 2006.211.07:34:40.97#ibcon#*after write, iclass 12, count 2 2006.211.07:34:40.97#ibcon#*before return 0, iclass 12, count 2 2006.211.07:34:40.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:40.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:34:40.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.07:34:40.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:40.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:41.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:41.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:41.09#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:34:41.09#ibcon#first serial, iclass 12, count 0 2006.211.07:34:41.09#ibcon#enter sib2, iclass 12, count 0 2006.211.07:34:41.09#ibcon#flushed, iclass 12, count 0 2006.211.07:34:41.09#ibcon#about to write, iclass 12, count 0 2006.211.07:34:41.09#ibcon#wrote, iclass 12, count 0 2006.211.07:34:41.09#ibcon#about to read 3, iclass 12, count 0 2006.211.07:34:41.11#ibcon#read 3, iclass 12, count 0 2006.211.07:34:41.11#ibcon#about to read 4, iclass 12, count 0 2006.211.07:34:41.11#ibcon#read 4, iclass 12, count 0 2006.211.07:34:41.11#ibcon#about to read 5, iclass 12, count 0 2006.211.07:34:41.11#ibcon#read 5, iclass 12, count 0 2006.211.07:34:41.11#ibcon#about to read 6, iclass 12, count 0 2006.211.07:34:41.11#ibcon#read 6, iclass 12, count 0 2006.211.07:34:41.11#ibcon#end of sib2, iclass 12, count 0 2006.211.07:34:41.11#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:34:41.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:34:41.11#ibcon#[27=USB\r\n] 2006.211.07:34:41.11#ibcon#*before write, iclass 12, count 0 2006.211.07:34:41.11#ibcon#enter sib2, iclass 12, count 0 2006.211.07:34:41.11#ibcon#flushed, iclass 12, count 0 2006.211.07:34:41.11#ibcon#about to write, iclass 12, count 0 2006.211.07:34:41.11#ibcon#wrote, iclass 12, count 0 2006.211.07:34:41.11#ibcon#about to read 3, iclass 12, count 0 2006.211.07:34:41.14#ibcon#read 3, iclass 12, count 0 2006.211.07:34:41.14#ibcon#about to read 4, iclass 12, count 0 2006.211.07:34:41.14#ibcon#read 4, iclass 12, count 0 2006.211.07:34:41.14#ibcon#about to read 5, iclass 12, count 0 2006.211.07:34:41.14#ibcon#read 5, iclass 12, count 0 2006.211.07:34:41.14#ibcon#about to read 6, iclass 12, count 0 2006.211.07:34:41.14#ibcon#read 6, iclass 12, count 0 2006.211.07:34:41.14#ibcon#end of sib2, iclass 12, count 0 2006.211.07:34:41.14#ibcon#*after write, iclass 12, count 0 2006.211.07:34:41.14#ibcon#*before return 0, iclass 12, count 0 2006.211.07:34:41.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:41.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:34:41.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:34:41.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:34:41.14$vc4f8/vblo=4,712.99 2006.211.07:34:41.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.07:34:41.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.07:34:41.14#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:41.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:41.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:41.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:41.14#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:34:41.14#ibcon#first serial, iclass 14, count 0 2006.211.07:34:41.14#ibcon#enter sib2, iclass 14, count 0 2006.211.07:34:41.14#ibcon#flushed, iclass 14, count 0 2006.211.07:34:41.14#ibcon#about to write, iclass 14, count 0 2006.211.07:34:41.14#ibcon#wrote, iclass 14, count 0 2006.211.07:34:41.14#ibcon#about to read 3, iclass 14, count 0 2006.211.07:34:41.16#ibcon#read 3, iclass 14, count 0 2006.211.07:34:41.16#ibcon#about to read 4, iclass 14, count 0 2006.211.07:34:41.16#ibcon#read 4, iclass 14, count 0 2006.211.07:34:41.16#ibcon#about to read 5, iclass 14, count 0 2006.211.07:34:41.16#ibcon#read 5, iclass 14, count 0 2006.211.07:34:41.16#ibcon#about to read 6, iclass 14, count 0 2006.211.07:34:41.16#ibcon#read 6, iclass 14, count 0 2006.211.07:34:41.16#ibcon#end of sib2, iclass 14, count 0 2006.211.07:34:41.16#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:34:41.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:34:41.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:34:41.16#ibcon#*before write, iclass 14, count 0 2006.211.07:34:41.16#ibcon#enter sib2, iclass 14, count 0 2006.211.07:34:41.16#ibcon#flushed, iclass 14, count 0 2006.211.07:34:41.16#ibcon#about to write, iclass 14, count 0 2006.211.07:34:41.16#ibcon#wrote, iclass 14, count 0 2006.211.07:34:41.16#ibcon#about to read 3, iclass 14, count 0 2006.211.07:34:41.20#ibcon#read 3, iclass 14, count 0 2006.211.07:34:41.20#ibcon#about to read 4, iclass 14, count 0 2006.211.07:34:41.20#ibcon#read 4, iclass 14, count 0 2006.211.07:34:41.20#ibcon#about to read 5, iclass 14, count 0 2006.211.07:34:41.20#ibcon#read 5, iclass 14, count 0 2006.211.07:34:41.20#ibcon#about to read 6, iclass 14, count 0 2006.211.07:34:41.20#ibcon#read 6, iclass 14, count 0 2006.211.07:34:41.20#ibcon#end of sib2, iclass 14, count 0 2006.211.07:34:41.20#ibcon#*after write, iclass 14, count 0 2006.211.07:34:41.20#ibcon#*before return 0, iclass 14, count 0 2006.211.07:34:41.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:41.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:34:41.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:34:41.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:34:41.20$vc4f8/vb=4,3 2006.211.07:34:41.20#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.07:34:41.20#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.07:34:41.20#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:41.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:41.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:41.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:41.26#ibcon#enter wrdev, iclass 16, count 2 2006.211.07:34:41.26#ibcon#first serial, iclass 16, count 2 2006.211.07:34:41.26#ibcon#enter sib2, iclass 16, count 2 2006.211.07:34:41.26#ibcon#flushed, iclass 16, count 2 2006.211.07:34:41.26#ibcon#about to write, iclass 16, count 2 2006.211.07:34:41.26#ibcon#wrote, iclass 16, count 2 2006.211.07:34:41.26#ibcon#about to read 3, iclass 16, count 2 2006.211.07:34:41.28#ibcon#read 3, iclass 16, count 2 2006.211.07:34:41.28#ibcon#about to read 4, iclass 16, count 2 2006.211.07:34:41.28#ibcon#read 4, iclass 16, count 2 2006.211.07:34:41.28#ibcon#about to read 5, iclass 16, count 2 2006.211.07:34:41.28#ibcon#read 5, iclass 16, count 2 2006.211.07:34:41.28#ibcon#about to read 6, iclass 16, count 2 2006.211.07:34:41.28#ibcon#read 6, iclass 16, count 2 2006.211.07:34:41.28#ibcon#end of sib2, iclass 16, count 2 2006.211.07:34:41.28#ibcon#*mode == 0, iclass 16, count 2 2006.211.07:34:41.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.07:34:41.28#ibcon#[27=AT04-03\r\n] 2006.211.07:34:41.28#ibcon#*before write, iclass 16, count 2 2006.211.07:34:41.28#ibcon#enter sib2, iclass 16, count 2 2006.211.07:34:41.28#ibcon#flushed, iclass 16, count 2 2006.211.07:34:41.28#ibcon#about to write, iclass 16, count 2 2006.211.07:34:41.28#ibcon#wrote, iclass 16, count 2 2006.211.07:34:41.28#ibcon#about to read 3, iclass 16, count 2 2006.211.07:34:41.31#ibcon#read 3, iclass 16, count 2 2006.211.07:34:41.31#ibcon#about to read 4, iclass 16, count 2 2006.211.07:34:41.31#ibcon#read 4, iclass 16, count 2 2006.211.07:34:41.31#ibcon#about to read 5, iclass 16, count 2 2006.211.07:34:41.31#ibcon#read 5, iclass 16, count 2 2006.211.07:34:41.31#ibcon#about to read 6, iclass 16, count 2 2006.211.07:34:41.31#ibcon#read 6, iclass 16, count 2 2006.211.07:34:41.31#ibcon#end of sib2, iclass 16, count 2 2006.211.07:34:41.31#ibcon#*after write, iclass 16, count 2 2006.211.07:34:41.31#ibcon#*before return 0, iclass 16, count 2 2006.211.07:34:41.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:41.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:34:41.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.07:34:41.31#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:41.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:41.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:41.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:41.43#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:34:41.43#ibcon#first serial, iclass 16, count 0 2006.211.07:34:41.43#ibcon#enter sib2, iclass 16, count 0 2006.211.07:34:41.43#ibcon#flushed, iclass 16, count 0 2006.211.07:34:41.43#ibcon#about to write, iclass 16, count 0 2006.211.07:34:41.43#ibcon#wrote, iclass 16, count 0 2006.211.07:34:41.43#ibcon#about to read 3, iclass 16, count 0 2006.211.07:34:41.45#ibcon#read 3, iclass 16, count 0 2006.211.07:34:41.45#ibcon#about to read 4, iclass 16, count 0 2006.211.07:34:41.45#ibcon#read 4, iclass 16, count 0 2006.211.07:34:41.45#ibcon#about to read 5, iclass 16, count 0 2006.211.07:34:41.45#ibcon#read 5, iclass 16, count 0 2006.211.07:34:41.45#ibcon#about to read 6, iclass 16, count 0 2006.211.07:34:41.45#ibcon#read 6, iclass 16, count 0 2006.211.07:34:41.45#ibcon#end of sib2, iclass 16, count 0 2006.211.07:34:41.45#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:34:41.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:34:41.45#ibcon#[27=USB\r\n] 2006.211.07:34:41.45#ibcon#*before write, iclass 16, count 0 2006.211.07:34:41.45#ibcon#enter sib2, iclass 16, count 0 2006.211.07:34:41.45#ibcon#flushed, iclass 16, count 0 2006.211.07:34:41.45#ibcon#about to write, iclass 16, count 0 2006.211.07:34:41.45#ibcon#wrote, iclass 16, count 0 2006.211.07:34:41.45#ibcon#about to read 3, iclass 16, count 0 2006.211.07:34:41.48#ibcon#read 3, iclass 16, count 0 2006.211.07:34:41.48#ibcon#about to read 4, iclass 16, count 0 2006.211.07:34:41.48#ibcon#read 4, iclass 16, count 0 2006.211.07:34:41.48#ibcon#about to read 5, iclass 16, count 0 2006.211.07:34:41.48#ibcon#read 5, iclass 16, count 0 2006.211.07:34:41.48#ibcon#about to read 6, iclass 16, count 0 2006.211.07:34:41.48#ibcon#read 6, iclass 16, count 0 2006.211.07:34:41.48#ibcon#end of sib2, iclass 16, count 0 2006.211.07:34:41.48#ibcon#*after write, iclass 16, count 0 2006.211.07:34:41.48#ibcon#*before return 0, iclass 16, count 0 2006.211.07:34:41.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:41.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:34:41.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:34:41.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:34:41.48$vc4f8/vblo=5,744.99 2006.211.07:34:41.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:34:41.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:34:41.48#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:41.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:41.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:41.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:41.48#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:34:41.48#ibcon#first serial, iclass 18, count 0 2006.211.07:34:41.48#ibcon#enter sib2, iclass 18, count 0 2006.211.07:34:41.48#ibcon#flushed, iclass 18, count 0 2006.211.07:34:41.48#ibcon#about to write, iclass 18, count 0 2006.211.07:34:41.48#ibcon#wrote, iclass 18, count 0 2006.211.07:34:41.48#ibcon#about to read 3, iclass 18, count 0 2006.211.07:34:41.50#ibcon#read 3, iclass 18, count 0 2006.211.07:34:41.50#ibcon#about to read 4, iclass 18, count 0 2006.211.07:34:41.50#ibcon#read 4, iclass 18, count 0 2006.211.07:34:41.50#ibcon#about to read 5, iclass 18, count 0 2006.211.07:34:41.50#ibcon#read 5, iclass 18, count 0 2006.211.07:34:41.50#ibcon#about to read 6, iclass 18, count 0 2006.211.07:34:41.50#ibcon#read 6, iclass 18, count 0 2006.211.07:34:41.50#ibcon#end of sib2, iclass 18, count 0 2006.211.07:34:41.50#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:34:41.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:34:41.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:34:41.50#ibcon#*before write, iclass 18, count 0 2006.211.07:34:41.50#ibcon#enter sib2, iclass 18, count 0 2006.211.07:34:41.50#ibcon#flushed, iclass 18, count 0 2006.211.07:34:41.50#ibcon#about to write, iclass 18, count 0 2006.211.07:34:41.50#ibcon#wrote, iclass 18, count 0 2006.211.07:34:41.50#ibcon#about to read 3, iclass 18, count 0 2006.211.07:34:41.54#ibcon#read 3, iclass 18, count 0 2006.211.07:34:41.54#ibcon#about to read 4, iclass 18, count 0 2006.211.07:34:41.54#ibcon#read 4, iclass 18, count 0 2006.211.07:34:41.54#ibcon#about to read 5, iclass 18, count 0 2006.211.07:34:41.54#ibcon#read 5, iclass 18, count 0 2006.211.07:34:41.54#ibcon#about to read 6, iclass 18, count 0 2006.211.07:34:41.54#ibcon#read 6, iclass 18, count 0 2006.211.07:34:41.54#ibcon#end of sib2, iclass 18, count 0 2006.211.07:34:41.54#ibcon#*after write, iclass 18, count 0 2006.211.07:34:41.54#ibcon#*before return 0, iclass 18, count 0 2006.211.07:34:41.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:41.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:34:41.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:34:41.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:34:41.54$vc4f8/vb=5,3 2006.211.07:34:41.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:34:41.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:34:41.54#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:41.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:41.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:41.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:41.60#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:34:41.60#ibcon#first serial, iclass 20, count 2 2006.211.07:34:41.60#ibcon#enter sib2, iclass 20, count 2 2006.211.07:34:41.60#ibcon#flushed, iclass 20, count 2 2006.211.07:34:41.60#ibcon#about to write, iclass 20, count 2 2006.211.07:34:41.60#ibcon#wrote, iclass 20, count 2 2006.211.07:34:41.60#ibcon#about to read 3, iclass 20, count 2 2006.211.07:34:41.62#ibcon#read 3, iclass 20, count 2 2006.211.07:34:41.62#ibcon#about to read 4, iclass 20, count 2 2006.211.07:34:41.62#ibcon#read 4, iclass 20, count 2 2006.211.07:34:41.62#ibcon#about to read 5, iclass 20, count 2 2006.211.07:34:41.62#ibcon#read 5, iclass 20, count 2 2006.211.07:34:41.62#ibcon#about to read 6, iclass 20, count 2 2006.211.07:34:41.62#ibcon#read 6, iclass 20, count 2 2006.211.07:34:41.62#ibcon#end of sib2, iclass 20, count 2 2006.211.07:34:41.62#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:34:41.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:34:41.62#ibcon#[27=AT05-03\r\n] 2006.211.07:34:41.62#ibcon#*before write, iclass 20, count 2 2006.211.07:34:41.62#ibcon#enter sib2, iclass 20, count 2 2006.211.07:34:41.62#ibcon#flushed, iclass 20, count 2 2006.211.07:34:41.62#ibcon#about to write, iclass 20, count 2 2006.211.07:34:41.62#ibcon#wrote, iclass 20, count 2 2006.211.07:34:41.62#ibcon#about to read 3, iclass 20, count 2 2006.211.07:34:41.65#ibcon#read 3, iclass 20, count 2 2006.211.07:34:41.65#ibcon#about to read 4, iclass 20, count 2 2006.211.07:34:41.65#ibcon#read 4, iclass 20, count 2 2006.211.07:34:41.65#ibcon#about to read 5, iclass 20, count 2 2006.211.07:34:41.65#ibcon#read 5, iclass 20, count 2 2006.211.07:34:41.65#ibcon#about to read 6, iclass 20, count 2 2006.211.07:34:41.65#ibcon#read 6, iclass 20, count 2 2006.211.07:34:41.65#ibcon#end of sib2, iclass 20, count 2 2006.211.07:34:41.65#ibcon#*after write, iclass 20, count 2 2006.211.07:34:41.65#ibcon#*before return 0, iclass 20, count 2 2006.211.07:34:41.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:41.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:34:41.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:34:41.65#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:41.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:41.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:41.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:41.77#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:34:41.77#ibcon#first serial, iclass 20, count 0 2006.211.07:34:41.77#ibcon#enter sib2, iclass 20, count 0 2006.211.07:34:41.77#ibcon#flushed, iclass 20, count 0 2006.211.07:34:41.77#ibcon#about to write, iclass 20, count 0 2006.211.07:34:41.77#ibcon#wrote, iclass 20, count 0 2006.211.07:34:41.77#ibcon#about to read 3, iclass 20, count 0 2006.211.07:34:41.79#ibcon#read 3, iclass 20, count 0 2006.211.07:34:41.79#ibcon#about to read 4, iclass 20, count 0 2006.211.07:34:41.79#ibcon#read 4, iclass 20, count 0 2006.211.07:34:41.79#ibcon#about to read 5, iclass 20, count 0 2006.211.07:34:41.79#ibcon#read 5, iclass 20, count 0 2006.211.07:34:41.79#ibcon#about to read 6, iclass 20, count 0 2006.211.07:34:41.79#ibcon#read 6, iclass 20, count 0 2006.211.07:34:41.79#ibcon#end of sib2, iclass 20, count 0 2006.211.07:34:41.79#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:34:41.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:34:41.79#ibcon#[27=USB\r\n] 2006.211.07:34:41.79#ibcon#*before write, iclass 20, count 0 2006.211.07:34:41.79#ibcon#enter sib2, iclass 20, count 0 2006.211.07:34:41.79#ibcon#flushed, iclass 20, count 0 2006.211.07:34:41.79#ibcon#about to write, iclass 20, count 0 2006.211.07:34:41.79#ibcon#wrote, iclass 20, count 0 2006.211.07:34:41.79#ibcon#about to read 3, iclass 20, count 0 2006.211.07:34:41.82#ibcon#read 3, iclass 20, count 0 2006.211.07:34:41.82#ibcon#about to read 4, iclass 20, count 0 2006.211.07:34:41.82#ibcon#read 4, iclass 20, count 0 2006.211.07:34:41.82#ibcon#about to read 5, iclass 20, count 0 2006.211.07:34:41.82#ibcon#read 5, iclass 20, count 0 2006.211.07:34:41.82#ibcon#about to read 6, iclass 20, count 0 2006.211.07:34:41.82#ibcon#read 6, iclass 20, count 0 2006.211.07:34:41.82#ibcon#end of sib2, iclass 20, count 0 2006.211.07:34:41.82#ibcon#*after write, iclass 20, count 0 2006.211.07:34:41.82#ibcon#*before return 0, iclass 20, count 0 2006.211.07:34:41.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:41.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:34:41.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:34:41.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:34:41.82$vc4f8/vblo=6,752.99 2006.211.07:34:41.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:34:41.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:34:41.82#ibcon#ireg 17 cls_cnt 0 2006.211.07:34:41.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:41.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:41.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:41.82#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:34:41.82#ibcon#first serial, iclass 22, count 0 2006.211.07:34:41.82#ibcon#enter sib2, iclass 22, count 0 2006.211.07:34:41.82#ibcon#flushed, iclass 22, count 0 2006.211.07:34:41.82#ibcon#about to write, iclass 22, count 0 2006.211.07:34:41.82#ibcon#wrote, iclass 22, count 0 2006.211.07:34:41.82#ibcon#about to read 3, iclass 22, count 0 2006.211.07:34:41.84#ibcon#read 3, iclass 22, count 0 2006.211.07:34:41.84#ibcon#about to read 4, iclass 22, count 0 2006.211.07:34:41.84#ibcon#read 4, iclass 22, count 0 2006.211.07:34:41.84#ibcon#about to read 5, iclass 22, count 0 2006.211.07:34:41.84#ibcon#read 5, iclass 22, count 0 2006.211.07:34:41.84#ibcon#about to read 6, iclass 22, count 0 2006.211.07:34:41.84#ibcon#read 6, iclass 22, count 0 2006.211.07:34:41.84#ibcon#end of sib2, iclass 22, count 0 2006.211.07:34:41.84#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:34:41.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:34:41.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:34:41.84#ibcon#*before write, iclass 22, count 0 2006.211.07:34:41.84#ibcon#enter sib2, iclass 22, count 0 2006.211.07:34:41.84#ibcon#flushed, iclass 22, count 0 2006.211.07:34:41.84#ibcon#about to write, iclass 22, count 0 2006.211.07:34:41.84#ibcon#wrote, iclass 22, count 0 2006.211.07:34:41.84#ibcon#about to read 3, iclass 22, count 0 2006.211.07:34:41.88#ibcon#read 3, iclass 22, count 0 2006.211.07:34:41.88#ibcon#about to read 4, iclass 22, count 0 2006.211.07:34:41.88#ibcon#read 4, iclass 22, count 0 2006.211.07:34:41.88#ibcon#about to read 5, iclass 22, count 0 2006.211.07:34:41.88#ibcon#read 5, iclass 22, count 0 2006.211.07:34:41.88#ibcon#about to read 6, iclass 22, count 0 2006.211.07:34:41.88#ibcon#read 6, iclass 22, count 0 2006.211.07:34:41.88#ibcon#end of sib2, iclass 22, count 0 2006.211.07:34:41.88#ibcon#*after write, iclass 22, count 0 2006.211.07:34:41.88#ibcon#*before return 0, iclass 22, count 0 2006.211.07:34:41.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:41.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:34:41.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:34:41.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:34:41.88$vc4f8/vb=6,3 2006.211.07:34:41.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:34:41.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:34:41.88#ibcon#ireg 11 cls_cnt 2 2006.211.07:34:41.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:41.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:41.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:41.94#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:34:41.94#ibcon#first serial, iclass 24, count 2 2006.211.07:34:41.94#ibcon#enter sib2, iclass 24, count 2 2006.211.07:34:41.94#ibcon#flushed, iclass 24, count 2 2006.211.07:34:41.94#ibcon#about to write, iclass 24, count 2 2006.211.07:34:41.94#ibcon#wrote, iclass 24, count 2 2006.211.07:34:41.94#ibcon#about to read 3, iclass 24, count 2 2006.211.07:34:41.96#ibcon#read 3, iclass 24, count 2 2006.211.07:34:41.96#ibcon#about to read 4, iclass 24, count 2 2006.211.07:34:41.96#ibcon#read 4, iclass 24, count 2 2006.211.07:34:41.96#ibcon#about to read 5, iclass 24, count 2 2006.211.07:34:41.96#ibcon#read 5, iclass 24, count 2 2006.211.07:34:41.96#ibcon#about to read 6, iclass 24, count 2 2006.211.07:34:41.96#ibcon#read 6, iclass 24, count 2 2006.211.07:34:41.96#ibcon#end of sib2, iclass 24, count 2 2006.211.07:34:41.96#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:34:41.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:34:41.96#ibcon#[27=AT06-03\r\n] 2006.211.07:34:41.96#ibcon#*before write, iclass 24, count 2 2006.211.07:34:41.96#ibcon#enter sib2, iclass 24, count 2 2006.211.07:34:41.96#ibcon#flushed, iclass 24, count 2 2006.211.07:34:41.96#ibcon#about to write, iclass 24, count 2 2006.211.07:34:41.96#ibcon#wrote, iclass 24, count 2 2006.211.07:34:41.96#ibcon#about to read 3, iclass 24, count 2 2006.211.07:34:41.99#ibcon#read 3, iclass 24, count 2 2006.211.07:34:41.99#ibcon#about to read 4, iclass 24, count 2 2006.211.07:34:41.99#ibcon#read 4, iclass 24, count 2 2006.211.07:34:41.99#ibcon#about to read 5, iclass 24, count 2 2006.211.07:34:41.99#ibcon#read 5, iclass 24, count 2 2006.211.07:34:41.99#ibcon#about to read 6, iclass 24, count 2 2006.211.07:34:41.99#ibcon#read 6, iclass 24, count 2 2006.211.07:34:41.99#ibcon#end of sib2, iclass 24, count 2 2006.211.07:34:41.99#ibcon#*after write, iclass 24, count 2 2006.211.07:34:41.99#ibcon#*before return 0, iclass 24, count 2 2006.211.07:34:41.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:41.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:34:41.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:34:41.99#ibcon#ireg 7 cls_cnt 0 2006.211.07:34:41.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:42.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:42.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:42.11#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:34:42.11#ibcon#first serial, iclass 24, count 0 2006.211.07:34:42.11#ibcon#enter sib2, iclass 24, count 0 2006.211.07:34:42.11#ibcon#flushed, iclass 24, count 0 2006.211.07:34:42.11#ibcon#about to write, iclass 24, count 0 2006.211.07:34:42.11#ibcon#wrote, iclass 24, count 0 2006.211.07:34:42.11#ibcon#about to read 3, iclass 24, count 0 2006.211.07:34:42.13#ibcon#read 3, iclass 24, count 0 2006.211.07:34:42.13#ibcon#about to read 4, iclass 24, count 0 2006.211.07:34:42.13#ibcon#read 4, iclass 24, count 0 2006.211.07:34:42.13#ibcon#about to read 5, iclass 24, count 0 2006.211.07:34:42.13#ibcon#read 5, iclass 24, count 0 2006.211.07:34:42.13#ibcon#about to read 6, iclass 24, count 0 2006.211.07:34:42.13#ibcon#read 6, iclass 24, count 0 2006.211.07:34:42.13#ibcon#end of sib2, iclass 24, count 0 2006.211.07:34:42.13#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:34:42.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:34:42.13#ibcon#[27=USB\r\n] 2006.211.07:34:42.13#ibcon#*before write, iclass 24, count 0 2006.211.07:34:42.13#ibcon#enter sib2, iclass 24, count 0 2006.211.07:34:42.13#ibcon#flushed, iclass 24, count 0 2006.211.07:34:42.13#ibcon#about to write, iclass 24, count 0 2006.211.07:34:42.13#ibcon#wrote, iclass 24, count 0 2006.211.07:34:42.13#ibcon#about to read 3, iclass 24, count 0 2006.211.07:34:42.16#ibcon#read 3, iclass 24, count 0 2006.211.07:34:42.16#ibcon#about to read 4, iclass 24, count 0 2006.211.07:34:42.16#ibcon#read 4, iclass 24, count 0 2006.211.07:34:42.16#ibcon#about to read 5, iclass 24, count 0 2006.211.07:34:42.16#ibcon#read 5, iclass 24, count 0 2006.211.07:34:42.16#ibcon#about to read 6, iclass 24, count 0 2006.211.07:34:42.16#ibcon#read 6, iclass 24, count 0 2006.211.07:34:42.16#ibcon#end of sib2, iclass 24, count 0 2006.211.07:34:42.16#ibcon#*after write, iclass 24, count 0 2006.211.07:34:42.16#ibcon#*before return 0, iclass 24, count 0 2006.211.07:34:42.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:42.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:34:42.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:34:42.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:34:42.16$vc4f8/vabw=wide 2006.211.07:34:42.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:34:42.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:34:42.16#ibcon#ireg 8 cls_cnt 0 2006.211.07:34:42.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:42.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:42.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:42.16#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:34:42.16#ibcon#first serial, iclass 26, count 0 2006.211.07:34:42.16#ibcon#enter sib2, iclass 26, count 0 2006.211.07:34:42.16#ibcon#flushed, iclass 26, count 0 2006.211.07:34:42.16#ibcon#about to write, iclass 26, count 0 2006.211.07:34:42.16#ibcon#wrote, iclass 26, count 0 2006.211.07:34:42.16#ibcon#about to read 3, iclass 26, count 0 2006.211.07:34:42.18#ibcon#read 3, iclass 26, count 0 2006.211.07:34:42.18#ibcon#about to read 4, iclass 26, count 0 2006.211.07:34:42.18#ibcon#read 4, iclass 26, count 0 2006.211.07:34:42.18#ibcon#about to read 5, iclass 26, count 0 2006.211.07:34:42.18#ibcon#read 5, iclass 26, count 0 2006.211.07:34:42.18#ibcon#about to read 6, iclass 26, count 0 2006.211.07:34:42.18#ibcon#read 6, iclass 26, count 0 2006.211.07:34:42.18#ibcon#end of sib2, iclass 26, count 0 2006.211.07:34:42.18#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:34:42.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:34:42.18#ibcon#[25=BW32\r\n] 2006.211.07:34:42.18#ibcon#*before write, iclass 26, count 0 2006.211.07:34:42.18#ibcon#enter sib2, iclass 26, count 0 2006.211.07:34:42.18#ibcon#flushed, iclass 26, count 0 2006.211.07:34:42.18#ibcon#about to write, iclass 26, count 0 2006.211.07:34:42.18#ibcon#wrote, iclass 26, count 0 2006.211.07:34:42.18#ibcon#about to read 3, iclass 26, count 0 2006.211.07:34:42.21#ibcon#read 3, iclass 26, count 0 2006.211.07:34:42.21#ibcon#about to read 4, iclass 26, count 0 2006.211.07:34:42.21#ibcon#read 4, iclass 26, count 0 2006.211.07:34:42.21#ibcon#about to read 5, iclass 26, count 0 2006.211.07:34:42.21#ibcon#read 5, iclass 26, count 0 2006.211.07:34:42.21#ibcon#about to read 6, iclass 26, count 0 2006.211.07:34:42.21#ibcon#read 6, iclass 26, count 0 2006.211.07:34:42.21#ibcon#end of sib2, iclass 26, count 0 2006.211.07:34:42.21#ibcon#*after write, iclass 26, count 0 2006.211.07:34:42.21#ibcon#*before return 0, iclass 26, count 0 2006.211.07:34:42.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:42.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:34:42.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:34:42.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:34:42.21$vc4f8/vbbw=wide 2006.211.07:34:42.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.07:34:42.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.07:34:42.21#ibcon#ireg 8 cls_cnt 0 2006.211.07:34:42.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:34:42.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:34:42.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:34:42.28#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:34:42.28#ibcon#first serial, iclass 28, count 0 2006.211.07:34:42.28#ibcon#enter sib2, iclass 28, count 0 2006.211.07:34:42.28#ibcon#flushed, iclass 28, count 0 2006.211.07:34:42.28#ibcon#about to write, iclass 28, count 0 2006.211.07:34:42.28#ibcon#wrote, iclass 28, count 0 2006.211.07:34:42.28#ibcon#about to read 3, iclass 28, count 0 2006.211.07:34:42.30#ibcon#read 3, iclass 28, count 0 2006.211.07:34:42.30#ibcon#about to read 4, iclass 28, count 0 2006.211.07:34:42.30#ibcon#read 4, iclass 28, count 0 2006.211.07:34:42.30#ibcon#about to read 5, iclass 28, count 0 2006.211.07:34:42.30#ibcon#read 5, iclass 28, count 0 2006.211.07:34:42.30#ibcon#about to read 6, iclass 28, count 0 2006.211.07:34:42.30#ibcon#read 6, iclass 28, count 0 2006.211.07:34:42.30#ibcon#end of sib2, iclass 28, count 0 2006.211.07:34:42.30#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:34:42.30#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:34:42.30#ibcon#[27=BW32\r\n] 2006.211.07:34:42.30#ibcon#*before write, iclass 28, count 0 2006.211.07:34:42.30#ibcon#enter sib2, iclass 28, count 0 2006.211.07:34:42.30#ibcon#flushed, iclass 28, count 0 2006.211.07:34:42.30#ibcon#about to write, iclass 28, count 0 2006.211.07:34:42.30#ibcon#wrote, iclass 28, count 0 2006.211.07:34:42.30#ibcon#about to read 3, iclass 28, count 0 2006.211.07:34:42.33#ibcon#read 3, iclass 28, count 0 2006.211.07:34:42.33#ibcon#about to read 4, iclass 28, count 0 2006.211.07:34:42.33#ibcon#read 4, iclass 28, count 0 2006.211.07:34:42.33#ibcon#about to read 5, iclass 28, count 0 2006.211.07:34:42.33#ibcon#read 5, iclass 28, count 0 2006.211.07:34:42.33#ibcon#about to read 6, iclass 28, count 0 2006.211.07:34:42.33#ibcon#read 6, iclass 28, count 0 2006.211.07:34:42.33#ibcon#end of sib2, iclass 28, count 0 2006.211.07:34:42.33#ibcon#*after write, iclass 28, count 0 2006.211.07:34:42.33#ibcon#*before return 0, iclass 28, count 0 2006.211.07:34:42.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:34:42.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:34:42.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:34:42.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:34:42.33$4f8m12a/ifd4f 2006.211.07:34:42.33$ifd4f/lo= 2006.211.07:34:42.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:34:42.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:34:42.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:34:42.33$ifd4f/patch= 2006.211.07:34:42.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:34:42.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:34:42.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:34:42.33$4f8m12a/"form=m,16.000,1:2 2006.211.07:34:42.33$4f8m12a/"tpicd 2006.211.07:34:42.33$4f8m12a/echo=off 2006.211.07:34:42.33$4f8m12a/xlog=off 2006.211.07:34:42.33:!2006.211.07:35:10 2006.211.07:34:57.14#trakl#Source acquired 2006.211.07:34:57.14#flagr#flagr/antenna,acquired 2006.211.07:35:10.01:preob 2006.211.07:35:11.14/onsource/TRACKING 2006.211.07:35:11.14:!2006.211.07:35:20 2006.211.07:35:20.00:data_valid=on 2006.211.07:35:20.00:midob 2006.211.07:35:20.14/onsource/TRACKING 2006.211.07:35:20.14/wx/25.00,1010.1,74 2006.211.07:35:20.25/cable/+6.4377E-03 2006.211.07:35:21.34/va/01,08,usb,yes,28,30 2006.211.07:35:21.34/va/02,07,usb,yes,28,30 2006.211.07:35:21.34/va/03,06,usb,yes,30,30 2006.211.07:35:21.34/va/04,07,usb,yes,29,31 2006.211.07:35:21.34/va/05,07,usb,yes,32,33 2006.211.07:35:21.34/va/06,06,usb,yes,31,31 2006.211.07:35:21.34/va/07,06,usb,yes,31,31 2006.211.07:35:21.34/va/08,07,usb,yes,30,29 2006.211.07:35:21.57/valo/01,532.99,yes,locked 2006.211.07:35:21.57/valo/02,572.99,yes,locked 2006.211.07:35:21.57/valo/03,672.99,yes,locked 2006.211.07:35:21.57/valo/04,832.99,yes,locked 2006.211.07:35:21.57/valo/05,652.99,yes,locked 2006.211.07:35:21.57/valo/06,772.99,yes,locked 2006.211.07:35:21.57/valo/07,832.99,yes,locked 2006.211.07:35:21.57/valo/08,852.99,yes,locked 2006.211.07:35:22.66/vb/01,04,usb,yes,28,27 2006.211.07:35:22.66/vb/02,04,usb,yes,30,31 2006.211.07:35:22.66/vb/03,03,usb,yes,33,37 2006.211.07:35:22.66/vb/04,03,usb,yes,34,34 2006.211.07:35:22.66/vb/05,03,usb,yes,32,36 2006.211.07:35:22.66/vb/06,03,usb,yes,33,36 2006.211.07:35:22.66/vb/07,04,usb,yes,29,28 2006.211.07:35:22.66/vb/08,03,usb,yes,33,36 2006.211.07:35:22.89/vblo/01,632.99,yes,locked 2006.211.07:35:22.89/vblo/02,640.99,yes,locked 2006.211.07:35:22.89/vblo/03,656.99,yes,locked 2006.211.07:35:22.89/vblo/04,712.99,yes,locked 2006.211.07:35:22.89/vblo/05,744.99,yes,locked 2006.211.07:35:22.89/vblo/06,752.99,yes,locked 2006.211.07:35:22.89/vblo/07,734.99,yes,locked 2006.211.07:35:22.89/vblo/08,744.99,yes,locked 2006.211.07:35:23.04/vabw/8 2006.211.07:35:23.19/vbbw/8 2006.211.07:35:23.30/xfe/off,on,12.0 2006.211.07:35:23.68/ifatt/23,28,28,28 2006.211.07:35:24.08/fmout-gps/S +4.46E-07 2006.211.07:35:24.12:!2006.211.07:36:20 2006.211.07:36:20.00:data_valid=off 2006.211.07:36:20.00:postob 2006.211.07:36:20.21/cable/+6.4387E-03 2006.211.07:36:20.21/wx/24.99,1010.1,75 2006.211.07:36:21.08/fmout-gps/S +4.48E-07 2006.211.07:36:21.08:scan_name=211-0737,k06211,60 2006.211.07:36:21.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.211.07:36:22.14#flagr#flagr/antenna,new-source 2006.211.07:36:22.14:checkk5 2006.211.07:36:22.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:36:22.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:36:23.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:36:23.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:36:23.85/chk_obsdata//k5ts1/T2110735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:36:24.18/chk_obsdata//k5ts2/T2110735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:36:24.51/chk_obsdata//k5ts3/T2110735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:36:24.84/chk_obsdata//k5ts4/T2110735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:36:25.50/k5log//k5ts1_log_newline 2006.211.07:36:26.15/k5log//k5ts2_log_newline 2006.211.07:36:26.80/k5log//k5ts3_log_newline 2006.211.07:36:27.46/k5log//k5ts4_log_newline 2006.211.07:36:27.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:36:27.48:4f8m12a=1 2006.211.07:36:27.48$4f8m12a/echo=on 2006.211.07:36:27.48$4f8m12a/pcalon 2006.211.07:36:27.48$pcalon/"no phase cal control is implemented here 2006.211.07:36:27.48$4f8m12a/"tpicd=stop 2006.211.07:36:27.48$4f8m12a/vc4f8 2006.211.07:36:27.48$vc4f8/valo=1,532.99 2006.211.07:36:27.48#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.07:36:27.48#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.07:36:27.48#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:27.48#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:27.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:27.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:27.49#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:36:27.49#ibcon#first serial, iclass 35, count 0 2006.211.07:36:27.49#ibcon#enter sib2, iclass 35, count 0 2006.211.07:36:27.49#ibcon#flushed, iclass 35, count 0 2006.211.07:36:27.49#ibcon#about to write, iclass 35, count 0 2006.211.07:36:27.49#ibcon#wrote, iclass 35, count 0 2006.211.07:36:27.49#ibcon#about to read 3, iclass 35, count 0 2006.211.07:36:27.50#ibcon#read 3, iclass 35, count 0 2006.211.07:36:27.50#ibcon#about to read 4, iclass 35, count 0 2006.211.07:36:27.50#ibcon#read 4, iclass 35, count 0 2006.211.07:36:27.50#ibcon#about to read 5, iclass 35, count 0 2006.211.07:36:27.50#ibcon#read 5, iclass 35, count 0 2006.211.07:36:27.50#ibcon#about to read 6, iclass 35, count 0 2006.211.07:36:27.50#ibcon#read 6, iclass 35, count 0 2006.211.07:36:27.50#ibcon#end of sib2, iclass 35, count 0 2006.211.07:36:27.50#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:36:27.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:36:27.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:36:27.50#ibcon#*before write, iclass 35, count 0 2006.211.07:36:27.50#ibcon#enter sib2, iclass 35, count 0 2006.211.07:36:27.50#ibcon#flushed, iclass 35, count 0 2006.211.07:36:27.50#ibcon#about to write, iclass 35, count 0 2006.211.07:36:27.50#ibcon#wrote, iclass 35, count 0 2006.211.07:36:27.50#ibcon#about to read 3, iclass 35, count 0 2006.211.07:36:27.55#ibcon#read 3, iclass 35, count 0 2006.211.07:36:27.55#ibcon#about to read 4, iclass 35, count 0 2006.211.07:36:27.55#ibcon#read 4, iclass 35, count 0 2006.211.07:36:27.55#ibcon#about to read 5, iclass 35, count 0 2006.211.07:36:27.55#ibcon#read 5, iclass 35, count 0 2006.211.07:36:27.55#ibcon#about to read 6, iclass 35, count 0 2006.211.07:36:27.55#ibcon#read 6, iclass 35, count 0 2006.211.07:36:27.55#ibcon#end of sib2, iclass 35, count 0 2006.211.07:36:27.55#ibcon#*after write, iclass 35, count 0 2006.211.07:36:27.55#ibcon#*before return 0, iclass 35, count 0 2006.211.07:36:27.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:27.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:27.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:36:27.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:36:27.55$vc4f8/va=1,8 2006.211.07:36:27.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.07:36:27.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.07:36:27.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:27.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:27.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:27.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:27.55#ibcon#enter wrdev, iclass 37, count 2 2006.211.07:36:27.55#ibcon#first serial, iclass 37, count 2 2006.211.07:36:27.55#ibcon#enter sib2, iclass 37, count 2 2006.211.07:36:27.55#ibcon#flushed, iclass 37, count 2 2006.211.07:36:27.55#ibcon#about to write, iclass 37, count 2 2006.211.07:36:27.55#ibcon#wrote, iclass 37, count 2 2006.211.07:36:27.55#ibcon#about to read 3, iclass 37, count 2 2006.211.07:36:27.57#ibcon#read 3, iclass 37, count 2 2006.211.07:36:27.57#ibcon#about to read 4, iclass 37, count 2 2006.211.07:36:27.57#ibcon#read 4, iclass 37, count 2 2006.211.07:36:27.57#ibcon#about to read 5, iclass 37, count 2 2006.211.07:36:27.57#ibcon#read 5, iclass 37, count 2 2006.211.07:36:27.57#ibcon#about to read 6, iclass 37, count 2 2006.211.07:36:27.57#ibcon#read 6, iclass 37, count 2 2006.211.07:36:27.57#ibcon#end of sib2, iclass 37, count 2 2006.211.07:36:27.57#ibcon#*mode == 0, iclass 37, count 2 2006.211.07:36:27.57#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.07:36:27.57#ibcon#[25=AT01-08\r\n] 2006.211.07:36:27.57#ibcon#*before write, iclass 37, count 2 2006.211.07:36:27.57#ibcon#enter sib2, iclass 37, count 2 2006.211.07:36:27.57#ibcon#flushed, iclass 37, count 2 2006.211.07:36:27.57#ibcon#about to write, iclass 37, count 2 2006.211.07:36:27.57#ibcon#wrote, iclass 37, count 2 2006.211.07:36:27.57#ibcon#about to read 3, iclass 37, count 2 2006.211.07:36:27.60#ibcon#read 3, iclass 37, count 2 2006.211.07:36:27.60#ibcon#about to read 4, iclass 37, count 2 2006.211.07:36:27.60#ibcon#read 4, iclass 37, count 2 2006.211.07:36:27.60#ibcon#about to read 5, iclass 37, count 2 2006.211.07:36:27.60#ibcon#read 5, iclass 37, count 2 2006.211.07:36:27.60#ibcon#about to read 6, iclass 37, count 2 2006.211.07:36:27.60#ibcon#read 6, iclass 37, count 2 2006.211.07:36:27.60#ibcon#end of sib2, iclass 37, count 2 2006.211.07:36:27.60#ibcon#*after write, iclass 37, count 2 2006.211.07:36:27.60#ibcon#*before return 0, iclass 37, count 2 2006.211.07:36:27.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:27.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:27.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.07:36:27.60#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:27.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:27.72#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:27.72#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:27.72#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:36:27.72#ibcon#first serial, iclass 37, count 0 2006.211.07:36:27.72#ibcon#enter sib2, iclass 37, count 0 2006.211.07:36:27.72#ibcon#flushed, iclass 37, count 0 2006.211.07:36:27.72#ibcon#about to write, iclass 37, count 0 2006.211.07:36:27.72#ibcon#wrote, iclass 37, count 0 2006.211.07:36:27.72#ibcon#about to read 3, iclass 37, count 0 2006.211.07:36:27.74#ibcon#read 3, iclass 37, count 0 2006.211.07:36:27.74#ibcon#about to read 4, iclass 37, count 0 2006.211.07:36:27.74#ibcon#read 4, iclass 37, count 0 2006.211.07:36:27.74#ibcon#about to read 5, iclass 37, count 0 2006.211.07:36:27.74#ibcon#read 5, iclass 37, count 0 2006.211.07:36:27.74#ibcon#about to read 6, iclass 37, count 0 2006.211.07:36:27.74#ibcon#read 6, iclass 37, count 0 2006.211.07:36:27.74#ibcon#end of sib2, iclass 37, count 0 2006.211.07:36:27.74#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:36:27.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:36:27.74#ibcon#[25=USB\r\n] 2006.211.07:36:27.74#ibcon#*before write, iclass 37, count 0 2006.211.07:36:27.74#ibcon#enter sib2, iclass 37, count 0 2006.211.07:36:27.74#ibcon#flushed, iclass 37, count 0 2006.211.07:36:27.74#ibcon#about to write, iclass 37, count 0 2006.211.07:36:27.74#ibcon#wrote, iclass 37, count 0 2006.211.07:36:27.74#ibcon#about to read 3, iclass 37, count 0 2006.211.07:36:27.77#ibcon#read 3, iclass 37, count 0 2006.211.07:36:27.77#ibcon#about to read 4, iclass 37, count 0 2006.211.07:36:27.77#ibcon#read 4, iclass 37, count 0 2006.211.07:36:27.77#ibcon#about to read 5, iclass 37, count 0 2006.211.07:36:27.77#ibcon#read 5, iclass 37, count 0 2006.211.07:36:27.77#ibcon#about to read 6, iclass 37, count 0 2006.211.07:36:27.77#ibcon#read 6, iclass 37, count 0 2006.211.07:36:27.77#ibcon#end of sib2, iclass 37, count 0 2006.211.07:36:27.77#ibcon#*after write, iclass 37, count 0 2006.211.07:36:27.77#ibcon#*before return 0, iclass 37, count 0 2006.211.07:36:27.77#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:27.77#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:27.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:36:27.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:36:27.77$vc4f8/valo=2,572.99 2006.211.07:36:27.77#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.07:36:27.77#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.07:36:27.77#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:27.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:27.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:27.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:27.77#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:36:27.77#ibcon#first serial, iclass 39, count 0 2006.211.07:36:27.77#ibcon#enter sib2, iclass 39, count 0 2006.211.07:36:27.77#ibcon#flushed, iclass 39, count 0 2006.211.07:36:27.77#ibcon#about to write, iclass 39, count 0 2006.211.07:36:27.77#ibcon#wrote, iclass 39, count 0 2006.211.07:36:27.77#ibcon#about to read 3, iclass 39, count 0 2006.211.07:36:27.79#ibcon#read 3, iclass 39, count 0 2006.211.07:36:27.79#ibcon#about to read 4, iclass 39, count 0 2006.211.07:36:27.79#ibcon#read 4, iclass 39, count 0 2006.211.07:36:27.79#ibcon#about to read 5, iclass 39, count 0 2006.211.07:36:27.79#ibcon#read 5, iclass 39, count 0 2006.211.07:36:27.79#ibcon#about to read 6, iclass 39, count 0 2006.211.07:36:27.79#ibcon#read 6, iclass 39, count 0 2006.211.07:36:27.79#ibcon#end of sib2, iclass 39, count 0 2006.211.07:36:27.79#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:36:27.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:36:27.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:36:27.79#ibcon#*before write, iclass 39, count 0 2006.211.07:36:27.79#ibcon#enter sib2, iclass 39, count 0 2006.211.07:36:27.79#ibcon#flushed, iclass 39, count 0 2006.211.07:36:27.79#ibcon#about to write, iclass 39, count 0 2006.211.07:36:27.79#ibcon#wrote, iclass 39, count 0 2006.211.07:36:27.79#ibcon#about to read 3, iclass 39, count 0 2006.211.07:36:27.83#ibcon#read 3, iclass 39, count 0 2006.211.07:36:27.83#ibcon#about to read 4, iclass 39, count 0 2006.211.07:36:27.83#ibcon#read 4, iclass 39, count 0 2006.211.07:36:27.83#ibcon#about to read 5, iclass 39, count 0 2006.211.07:36:27.83#ibcon#read 5, iclass 39, count 0 2006.211.07:36:27.83#ibcon#about to read 6, iclass 39, count 0 2006.211.07:36:27.83#ibcon#read 6, iclass 39, count 0 2006.211.07:36:27.83#ibcon#end of sib2, iclass 39, count 0 2006.211.07:36:27.83#ibcon#*after write, iclass 39, count 0 2006.211.07:36:27.83#ibcon#*before return 0, iclass 39, count 0 2006.211.07:36:27.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:27.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:27.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:36:27.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:36:27.83$vc4f8/va=2,7 2006.211.07:36:27.83#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.07:36:27.83#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.07:36:27.83#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:27.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:27.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:27.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:27.89#ibcon#enter wrdev, iclass 3, count 2 2006.211.07:36:27.89#ibcon#first serial, iclass 3, count 2 2006.211.07:36:27.89#ibcon#enter sib2, iclass 3, count 2 2006.211.07:36:27.89#ibcon#flushed, iclass 3, count 2 2006.211.07:36:27.89#ibcon#about to write, iclass 3, count 2 2006.211.07:36:27.89#ibcon#wrote, iclass 3, count 2 2006.211.07:36:27.89#ibcon#about to read 3, iclass 3, count 2 2006.211.07:36:27.91#ibcon#read 3, iclass 3, count 2 2006.211.07:36:27.91#ibcon#about to read 4, iclass 3, count 2 2006.211.07:36:27.91#ibcon#read 4, iclass 3, count 2 2006.211.07:36:27.91#ibcon#about to read 5, iclass 3, count 2 2006.211.07:36:27.91#ibcon#read 5, iclass 3, count 2 2006.211.07:36:27.91#ibcon#about to read 6, iclass 3, count 2 2006.211.07:36:27.91#ibcon#read 6, iclass 3, count 2 2006.211.07:36:27.91#ibcon#end of sib2, iclass 3, count 2 2006.211.07:36:27.91#ibcon#*mode == 0, iclass 3, count 2 2006.211.07:36:27.91#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.07:36:27.91#ibcon#[25=AT02-07\r\n] 2006.211.07:36:27.91#ibcon#*before write, iclass 3, count 2 2006.211.07:36:27.91#ibcon#enter sib2, iclass 3, count 2 2006.211.07:36:27.91#ibcon#flushed, iclass 3, count 2 2006.211.07:36:27.91#ibcon#about to write, iclass 3, count 2 2006.211.07:36:27.91#ibcon#wrote, iclass 3, count 2 2006.211.07:36:27.91#ibcon#about to read 3, iclass 3, count 2 2006.211.07:36:27.94#ibcon#read 3, iclass 3, count 2 2006.211.07:36:27.94#ibcon#about to read 4, iclass 3, count 2 2006.211.07:36:27.94#ibcon#read 4, iclass 3, count 2 2006.211.07:36:27.94#ibcon#about to read 5, iclass 3, count 2 2006.211.07:36:27.94#ibcon#read 5, iclass 3, count 2 2006.211.07:36:27.94#ibcon#about to read 6, iclass 3, count 2 2006.211.07:36:27.94#ibcon#read 6, iclass 3, count 2 2006.211.07:36:27.94#ibcon#end of sib2, iclass 3, count 2 2006.211.07:36:27.94#ibcon#*after write, iclass 3, count 2 2006.211.07:36:27.94#ibcon#*before return 0, iclass 3, count 2 2006.211.07:36:27.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:27.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:27.94#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.07:36:27.94#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:27.94#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:28.06#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:28.06#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:28.06#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:36:28.06#ibcon#first serial, iclass 3, count 0 2006.211.07:36:28.06#ibcon#enter sib2, iclass 3, count 0 2006.211.07:36:28.06#ibcon#flushed, iclass 3, count 0 2006.211.07:36:28.06#ibcon#about to write, iclass 3, count 0 2006.211.07:36:28.06#ibcon#wrote, iclass 3, count 0 2006.211.07:36:28.06#ibcon#about to read 3, iclass 3, count 0 2006.211.07:36:28.08#ibcon#read 3, iclass 3, count 0 2006.211.07:36:28.08#ibcon#about to read 4, iclass 3, count 0 2006.211.07:36:28.08#ibcon#read 4, iclass 3, count 0 2006.211.07:36:28.08#ibcon#about to read 5, iclass 3, count 0 2006.211.07:36:28.08#ibcon#read 5, iclass 3, count 0 2006.211.07:36:28.08#ibcon#about to read 6, iclass 3, count 0 2006.211.07:36:28.08#ibcon#read 6, iclass 3, count 0 2006.211.07:36:28.08#ibcon#end of sib2, iclass 3, count 0 2006.211.07:36:28.08#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:36:28.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:36:28.08#ibcon#[25=USB\r\n] 2006.211.07:36:28.08#ibcon#*before write, iclass 3, count 0 2006.211.07:36:28.08#ibcon#enter sib2, iclass 3, count 0 2006.211.07:36:28.08#ibcon#flushed, iclass 3, count 0 2006.211.07:36:28.08#ibcon#about to write, iclass 3, count 0 2006.211.07:36:28.08#ibcon#wrote, iclass 3, count 0 2006.211.07:36:28.08#ibcon#about to read 3, iclass 3, count 0 2006.211.07:36:28.11#ibcon#read 3, iclass 3, count 0 2006.211.07:36:28.11#ibcon#about to read 4, iclass 3, count 0 2006.211.07:36:28.11#ibcon#read 4, iclass 3, count 0 2006.211.07:36:28.11#ibcon#about to read 5, iclass 3, count 0 2006.211.07:36:28.11#ibcon#read 5, iclass 3, count 0 2006.211.07:36:28.11#ibcon#about to read 6, iclass 3, count 0 2006.211.07:36:28.11#ibcon#read 6, iclass 3, count 0 2006.211.07:36:28.11#ibcon#end of sib2, iclass 3, count 0 2006.211.07:36:28.11#ibcon#*after write, iclass 3, count 0 2006.211.07:36:28.11#ibcon#*before return 0, iclass 3, count 0 2006.211.07:36:28.11#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:28.11#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:28.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:36:28.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:36:28.11$vc4f8/valo=3,672.99 2006.211.07:36:28.11#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.07:36:28.11#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.07:36:28.11#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:28.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:28.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:28.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:28.11#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:36:28.11#ibcon#first serial, iclass 5, count 0 2006.211.07:36:28.11#ibcon#enter sib2, iclass 5, count 0 2006.211.07:36:28.11#ibcon#flushed, iclass 5, count 0 2006.211.07:36:28.11#ibcon#about to write, iclass 5, count 0 2006.211.07:36:28.11#ibcon#wrote, iclass 5, count 0 2006.211.07:36:28.11#ibcon#about to read 3, iclass 5, count 0 2006.211.07:36:28.13#ibcon#read 3, iclass 5, count 0 2006.211.07:36:28.13#ibcon#about to read 4, iclass 5, count 0 2006.211.07:36:28.13#ibcon#read 4, iclass 5, count 0 2006.211.07:36:28.13#ibcon#about to read 5, iclass 5, count 0 2006.211.07:36:28.13#ibcon#read 5, iclass 5, count 0 2006.211.07:36:28.13#ibcon#about to read 6, iclass 5, count 0 2006.211.07:36:28.13#ibcon#read 6, iclass 5, count 0 2006.211.07:36:28.13#ibcon#end of sib2, iclass 5, count 0 2006.211.07:36:28.13#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:36:28.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:36:28.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:36:28.13#ibcon#*before write, iclass 5, count 0 2006.211.07:36:28.13#ibcon#enter sib2, iclass 5, count 0 2006.211.07:36:28.13#ibcon#flushed, iclass 5, count 0 2006.211.07:36:28.13#ibcon#about to write, iclass 5, count 0 2006.211.07:36:28.13#ibcon#wrote, iclass 5, count 0 2006.211.07:36:28.13#ibcon#about to read 3, iclass 5, count 0 2006.211.07:36:28.17#ibcon#read 3, iclass 5, count 0 2006.211.07:36:28.17#ibcon#about to read 4, iclass 5, count 0 2006.211.07:36:28.17#ibcon#read 4, iclass 5, count 0 2006.211.07:36:28.17#ibcon#about to read 5, iclass 5, count 0 2006.211.07:36:28.17#ibcon#read 5, iclass 5, count 0 2006.211.07:36:28.17#ibcon#about to read 6, iclass 5, count 0 2006.211.07:36:28.17#ibcon#read 6, iclass 5, count 0 2006.211.07:36:28.17#ibcon#end of sib2, iclass 5, count 0 2006.211.07:36:28.17#ibcon#*after write, iclass 5, count 0 2006.211.07:36:28.17#ibcon#*before return 0, iclass 5, count 0 2006.211.07:36:28.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:28.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:28.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:36:28.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:36:28.17$vc4f8/va=3,6 2006.211.07:36:28.17#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.07:36:28.17#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.07:36:28.17#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:28.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:28.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:28.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:28.23#ibcon#enter wrdev, iclass 7, count 2 2006.211.07:36:28.23#ibcon#first serial, iclass 7, count 2 2006.211.07:36:28.23#ibcon#enter sib2, iclass 7, count 2 2006.211.07:36:28.23#ibcon#flushed, iclass 7, count 2 2006.211.07:36:28.23#ibcon#about to write, iclass 7, count 2 2006.211.07:36:28.23#ibcon#wrote, iclass 7, count 2 2006.211.07:36:28.23#ibcon#about to read 3, iclass 7, count 2 2006.211.07:36:28.25#ibcon#read 3, iclass 7, count 2 2006.211.07:36:28.25#ibcon#about to read 4, iclass 7, count 2 2006.211.07:36:28.25#ibcon#read 4, iclass 7, count 2 2006.211.07:36:28.25#ibcon#about to read 5, iclass 7, count 2 2006.211.07:36:28.25#ibcon#read 5, iclass 7, count 2 2006.211.07:36:28.25#ibcon#about to read 6, iclass 7, count 2 2006.211.07:36:28.25#ibcon#read 6, iclass 7, count 2 2006.211.07:36:28.25#ibcon#end of sib2, iclass 7, count 2 2006.211.07:36:28.25#ibcon#*mode == 0, iclass 7, count 2 2006.211.07:36:28.25#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.07:36:28.25#ibcon#[25=AT03-06\r\n] 2006.211.07:36:28.25#ibcon#*before write, iclass 7, count 2 2006.211.07:36:28.25#ibcon#enter sib2, iclass 7, count 2 2006.211.07:36:28.25#ibcon#flushed, iclass 7, count 2 2006.211.07:36:28.25#ibcon#about to write, iclass 7, count 2 2006.211.07:36:28.25#ibcon#wrote, iclass 7, count 2 2006.211.07:36:28.25#ibcon#about to read 3, iclass 7, count 2 2006.211.07:36:28.28#ibcon#read 3, iclass 7, count 2 2006.211.07:36:28.28#ibcon#about to read 4, iclass 7, count 2 2006.211.07:36:28.28#ibcon#read 4, iclass 7, count 2 2006.211.07:36:28.28#ibcon#about to read 5, iclass 7, count 2 2006.211.07:36:28.28#ibcon#read 5, iclass 7, count 2 2006.211.07:36:28.28#ibcon#about to read 6, iclass 7, count 2 2006.211.07:36:28.28#ibcon#read 6, iclass 7, count 2 2006.211.07:36:28.28#ibcon#end of sib2, iclass 7, count 2 2006.211.07:36:28.28#ibcon#*after write, iclass 7, count 2 2006.211.07:36:28.28#ibcon#*before return 0, iclass 7, count 2 2006.211.07:36:28.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:28.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:28.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.07:36:28.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:28.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:28.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:28.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:28.40#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:36:28.40#ibcon#first serial, iclass 7, count 0 2006.211.07:36:28.40#ibcon#enter sib2, iclass 7, count 0 2006.211.07:36:28.40#ibcon#flushed, iclass 7, count 0 2006.211.07:36:28.40#ibcon#about to write, iclass 7, count 0 2006.211.07:36:28.40#ibcon#wrote, iclass 7, count 0 2006.211.07:36:28.40#ibcon#about to read 3, iclass 7, count 0 2006.211.07:36:28.42#ibcon#read 3, iclass 7, count 0 2006.211.07:36:28.42#ibcon#about to read 4, iclass 7, count 0 2006.211.07:36:28.42#ibcon#read 4, iclass 7, count 0 2006.211.07:36:28.42#ibcon#about to read 5, iclass 7, count 0 2006.211.07:36:28.42#ibcon#read 5, iclass 7, count 0 2006.211.07:36:28.42#ibcon#about to read 6, iclass 7, count 0 2006.211.07:36:28.42#ibcon#read 6, iclass 7, count 0 2006.211.07:36:28.42#ibcon#end of sib2, iclass 7, count 0 2006.211.07:36:28.42#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:36:28.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:36:28.42#ibcon#[25=USB\r\n] 2006.211.07:36:28.42#ibcon#*before write, iclass 7, count 0 2006.211.07:36:28.42#ibcon#enter sib2, iclass 7, count 0 2006.211.07:36:28.42#ibcon#flushed, iclass 7, count 0 2006.211.07:36:28.42#ibcon#about to write, iclass 7, count 0 2006.211.07:36:28.42#ibcon#wrote, iclass 7, count 0 2006.211.07:36:28.42#ibcon#about to read 3, iclass 7, count 0 2006.211.07:36:28.45#ibcon#read 3, iclass 7, count 0 2006.211.07:36:28.45#ibcon#about to read 4, iclass 7, count 0 2006.211.07:36:28.45#ibcon#read 4, iclass 7, count 0 2006.211.07:36:28.45#ibcon#about to read 5, iclass 7, count 0 2006.211.07:36:28.45#ibcon#read 5, iclass 7, count 0 2006.211.07:36:28.45#ibcon#about to read 6, iclass 7, count 0 2006.211.07:36:28.45#ibcon#read 6, iclass 7, count 0 2006.211.07:36:28.45#ibcon#end of sib2, iclass 7, count 0 2006.211.07:36:28.45#ibcon#*after write, iclass 7, count 0 2006.211.07:36:28.45#ibcon#*before return 0, iclass 7, count 0 2006.211.07:36:28.45#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:28.45#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:28.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:36:28.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:36:28.45$vc4f8/valo=4,832.99 2006.211.07:36:28.45#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:36:28.45#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:36:28.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:28.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:28.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:28.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:28.45#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:36:28.45#ibcon#first serial, iclass 11, count 0 2006.211.07:36:28.45#ibcon#enter sib2, iclass 11, count 0 2006.211.07:36:28.45#ibcon#flushed, iclass 11, count 0 2006.211.07:36:28.45#ibcon#about to write, iclass 11, count 0 2006.211.07:36:28.45#ibcon#wrote, iclass 11, count 0 2006.211.07:36:28.45#ibcon#about to read 3, iclass 11, count 0 2006.211.07:36:28.47#ibcon#read 3, iclass 11, count 0 2006.211.07:36:28.47#ibcon#about to read 4, iclass 11, count 0 2006.211.07:36:28.47#ibcon#read 4, iclass 11, count 0 2006.211.07:36:28.47#ibcon#about to read 5, iclass 11, count 0 2006.211.07:36:28.47#ibcon#read 5, iclass 11, count 0 2006.211.07:36:28.47#ibcon#about to read 6, iclass 11, count 0 2006.211.07:36:28.47#ibcon#read 6, iclass 11, count 0 2006.211.07:36:28.47#ibcon#end of sib2, iclass 11, count 0 2006.211.07:36:28.47#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:36:28.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:36:28.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:36:28.47#ibcon#*before write, iclass 11, count 0 2006.211.07:36:28.47#ibcon#enter sib2, iclass 11, count 0 2006.211.07:36:28.47#ibcon#flushed, iclass 11, count 0 2006.211.07:36:28.47#ibcon#about to write, iclass 11, count 0 2006.211.07:36:28.47#ibcon#wrote, iclass 11, count 0 2006.211.07:36:28.47#ibcon#about to read 3, iclass 11, count 0 2006.211.07:36:28.51#ibcon#read 3, iclass 11, count 0 2006.211.07:36:28.51#ibcon#about to read 4, iclass 11, count 0 2006.211.07:36:28.51#ibcon#read 4, iclass 11, count 0 2006.211.07:36:28.51#ibcon#about to read 5, iclass 11, count 0 2006.211.07:36:28.51#ibcon#read 5, iclass 11, count 0 2006.211.07:36:28.51#ibcon#about to read 6, iclass 11, count 0 2006.211.07:36:28.51#ibcon#read 6, iclass 11, count 0 2006.211.07:36:28.51#ibcon#end of sib2, iclass 11, count 0 2006.211.07:36:28.51#ibcon#*after write, iclass 11, count 0 2006.211.07:36:28.51#ibcon#*before return 0, iclass 11, count 0 2006.211.07:36:28.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:28.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:28.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:36:28.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:36:28.51$vc4f8/va=4,7 2006.211.07:36:28.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.07:36:28.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.07:36:28.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:28.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:28.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:28.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:28.57#ibcon#enter wrdev, iclass 13, count 2 2006.211.07:36:28.57#ibcon#first serial, iclass 13, count 2 2006.211.07:36:28.57#ibcon#enter sib2, iclass 13, count 2 2006.211.07:36:28.57#ibcon#flushed, iclass 13, count 2 2006.211.07:36:28.57#ibcon#about to write, iclass 13, count 2 2006.211.07:36:28.57#ibcon#wrote, iclass 13, count 2 2006.211.07:36:28.57#ibcon#about to read 3, iclass 13, count 2 2006.211.07:36:28.59#ibcon#read 3, iclass 13, count 2 2006.211.07:36:28.59#ibcon#about to read 4, iclass 13, count 2 2006.211.07:36:28.59#ibcon#read 4, iclass 13, count 2 2006.211.07:36:28.59#ibcon#about to read 5, iclass 13, count 2 2006.211.07:36:28.59#ibcon#read 5, iclass 13, count 2 2006.211.07:36:28.59#ibcon#about to read 6, iclass 13, count 2 2006.211.07:36:28.59#ibcon#read 6, iclass 13, count 2 2006.211.07:36:28.59#ibcon#end of sib2, iclass 13, count 2 2006.211.07:36:28.59#ibcon#*mode == 0, iclass 13, count 2 2006.211.07:36:28.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.07:36:28.59#ibcon#[25=AT04-07\r\n] 2006.211.07:36:28.59#ibcon#*before write, iclass 13, count 2 2006.211.07:36:28.59#ibcon#enter sib2, iclass 13, count 2 2006.211.07:36:28.59#ibcon#flushed, iclass 13, count 2 2006.211.07:36:28.59#ibcon#about to write, iclass 13, count 2 2006.211.07:36:28.59#ibcon#wrote, iclass 13, count 2 2006.211.07:36:28.59#ibcon#about to read 3, iclass 13, count 2 2006.211.07:36:28.62#ibcon#read 3, iclass 13, count 2 2006.211.07:36:28.62#ibcon#about to read 4, iclass 13, count 2 2006.211.07:36:28.62#ibcon#read 4, iclass 13, count 2 2006.211.07:36:28.62#ibcon#about to read 5, iclass 13, count 2 2006.211.07:36:28.62#ibcon#read 5, iclass 13, count 2 2006.211.07:36:28.62#ibcon#about to read 6, iclass 13, count 2 2006.211.07:36:28.62#ibcon#read 6, iclass 13, count 2 2006.211.07:36:28.62#ibcon#end of sib2, iclass 13, count 2 2006.211.07:36:28.62#ibcon#*after write, iclass 13, count 2 2006.211.07:36:28.62#ibcon#*before return 0, iclass 13, count 2 2006.211.07:36:28.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:28.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:28.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.07:36:28.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:28.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:28.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:28.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:28.74#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:36:28.74#ibcon#first serial, iclass 13, count 0 2006.211.07:36:28.74#ibcon#enter sib2, iclass 13, count 0 2006.211.07:36:28.74#ibcon#flushed, iclass 13, count 0 2006.211.07:36:28.74#ibcon#about to write, iclass 13, count 0 2006.211.07:36:28.74#ibcon#wrote, iclass 13, count 0 2006.211.07:36:28.74#ibcon#about to read 3, iclass 13, count 0 2006.211.07:36:28.76#ibcon#read 3, iclass 13, count 0 2006.211.07:36:28.76#ibcon#about to read 4, iclass 13, count 0 2006.211.07:36:28.76#ibcon#read 4, iclass 13, count 0 2006.211.07:36:28.76#ibcon#about to read 5, iclass 13, count 0 2006.211.07:36:28.76#ibcon#read 5, iclass 13, count 0 2006.211.07:36:28.76#ibcon#about to read 6, iclass 13, count 0 2006.211.07:36:28.76#ibcon#read 6, iclass 13, count 0 2006.211.07:36:28.76#ibcon#end of sib2, iclass 13, count 0 2006.211.07:36:28.76#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:36:28.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:36:28.76#ibcon#[25=USB\r\n] 2006.211.07:36:28.76#ibcon#*before write, iclass 13, count 0 2006.211.07:36:28.76#ibcon#enter sib2, iclass 13, count 0 2006.211.07:36:28.76#ibcon#flushed, iclass 13, count 0 2006.211.07:36:28.76#ibcon#about to write, iclass 13, count 0 2006.211.07:36:28.76#ibcon#wrote, iclass 13, count 0 2006.211.07:36:28.76#ibcon#about to read 3, iclass 13, count 0 2006.211.07:36:28.79#ibcon#read 3, iclass 13, count 0 2006.211.07:36:28.79#ibcon#about to read 4, iclass 13, count 0 2006.211.07:36:28.79#ibcon#read 4, iclass 13, count 0 2006.211.07:36:28.79#ibcon#about to read 5, iclass 13, count 0 2006.211.07:36:28.79#ibcon#read 5, iclass 13, count 0 2006.211.07:36:28.79#ibcon#about to read 6, iclass 13, count 0 2006.211.07:36:28.79#ibcon#read 6, iclass 13, count 0 2006.211.07:36:28.79#ibcon#end of sib2, iclass 13, count 0 2006.211.07:36:28.79#ibcon#*after write, iclass 13, count 0 2006.211.07:36:28.79#ibcon#*before return 0, iclass 13, count 0 2006.211.07:36:28.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:28.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:28.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:36:28.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:36:28.79$vc4f8/valo=5,652.99 2006.211.07:36:28.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:36:28.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:36:28.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:28.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:36:28.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:36:28.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:36:28.79#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:36:28.79#ibcon#first serial, iclass 15, count 0 2006.211.07:36:28.79#ibcon#enter sib2, iclass 15, count 0 2006.211.07:36:28.79#ibcon#flushed, iclass 15, count 0 2006.211.07:36:28.79#ibcon#about to write, iclass 15, count 0 2006.211.07:36:28.79#ibcon#wrote, iclass 15, count 0 2006.211.07:36:28.79#ibcon#about to read 3, iclass 15, count 0 2006.211.07:36:28.81#ibcon#read 3, iclass 15, count 0 2006.211.07:36:28.81#ibcon#about to read 4, iclass 15, count 0 2006.211.07:36:28.81#ibcon#read 4, iclass 15, count 0 2006.211.07:36:28.81#ibcon#about to read 5, iclass 15, count 0 2006.211.07:36:28.81#ibcon#read 5, iclass 15, count 0 2006.211.07:36:28.81#ibcon#about to read 6, iclass 15, count 0 2006.211.07:36:28.81#ibcon#read 6, iclass 15, count 0 2006.211.07:36:28.81#ibcon#end of sib2, iclass 15, count 0 2006.211.07:36:28.81#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:36:28.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:36:28.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:36:28.81#ibcon#*before write, iclass 15, count 0 2006.211.07:36:28.81#ibcon#enter sib2, iclass 15, count 0 2006.211.07:36:28.81#ibcon#flushed, iclass 15, count 0 2006.211.07:36:28.81#ibcon#about to write, iclass 15, count 0 2006.211.07:36:28.81#ibcon#wrote, iclass 15, count 0 2006.211.07:36:28.81#ibcon#about to read 3, iclass 15, count 0 2006.211.07:36:28.85#ibcon#read 3, iclass 15, count 0 2006.211.07:36:28.85#ibcon#about to read 4, iclass 15, count 0 2006.211.07:36:28.85#ibcon#read 4, iclass 15, count 0 2006.211.07:36:28.85#ibcon#about to read 5, iclass 15, count 0 2006.211.07:36:28.85#ibcon#read 5, iclass 15, count 0 2006.211.07:36:28.85#ibcon#about to read 6, iclass 15, count 0 2006.211.07:36:28.85#ibcon#read 6, iclass 15, count 0 2006.211.07:36:28.85#ibcon#end of sib2, iclass 15, count 0 2006.211.07:36:28.85#ibcon#*after write, iclass 15, count 0 2006.211.07:36:28.85#ibcon#*before return 0, iclass 15, count 0 2006.211.07:36:28.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:36:28.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:36:28.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:36:28.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:36:28.85$vc4f8/va=5,7 2006.211.07:36:28.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.07:36:28.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.07:36:28.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:28.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:36:28.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:36:28.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:36:28.91#ibcon#enter wrdev, iclass 17, count 2 2006.211.07:36:28.91#ibcon#first serial, iclass 17, count 2 2006.211.07:36:28.91#ibcon#enter sib2, iclass 17, count 2 2006.211.07:36:28.91#ibcon#flushed, iclass 17, count 2 2006.211.07:36:28.91#ibcon#about to write, iclass 17, count 2 2006.211.07:36:28.91#ibcon#wrote, iclass 17, count 2 2006.211.07:36:28.91#ibcon#about to read 3, iclass 17, count 2 2006.211.07:36:28.93#ibcon#read 3, iclass 17, count 2 2006.211.07:36:28.93#ibcon#about to read 4, iclass 17, count 2 2006.211.07:36:28.93#ibcon#read 4, iclass 17, count 2 2006.211.07:36:28.93#ibcon#about to read 5, iclass 17, count 2 2006.211.07:36:28.93#ibcon#read 5, iclass 17, count 2 2006.211.07:36:28.93#ibcon#about to read 6, iclass 17, count 2 2006.211.07:36:28.93#ibcon#read 6, iclass 17, count 2 2006.211.07:36:28.93#ibcon#end of sib2, iclass 17, count 2 2006.211.07:36:28.93#ibcon#*mode == 0, iclass 17, count 2 2006.211.07:36:28.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.07:36:28.93#ibcon#[25=AT05-07\r\n] 2006.211.07:36:28.93#ibcon#*before write, iclass 17, count 2 2006.211.07:36:28.93#ibcon#enter sib2, iclass 17, count 2 2006.211.07:36:28.93#ibcon#flushed, iclass 17, count 2 2006.211.07:36:28.93#ibcon#about to write, iclass 17, count 2 2006.211.07:36:28.93#ibcon#wrote, iclass 17, count 2 2006.211.07:36:28.93#ibcon#about to read 3, iclass 17, count 2 2006.211.07:36:28.96#ibcon#read 3, iclass 17, count 2 2006.211.07:36:28.96#ibcon#about to read 4, iclass 17, count 2 2006.211.07:36:28.96#ibcon#read 4, iclass 17, count 2 2006.211.07:36:28.96#ibcon#about to read 5, iclass 17, count 2 2006.211.07:36:28.96#ibcon#read 5, iclass 17, count 2 2006.211.07:36:28.96#ibcon#about to read 6, iclass 17, count 2 2006.211.07:36:28.96#ibcon#read 6, iclass 17, count 2 2006.211.07:36:28.96#ibcon#end of sib2, iclass 17, count 2 2006.211.07:36:28.96#ibcon#*after write, iclass 17, count 2 2006.211.07:36:28.96#ibcon#*before return 0, iclass 17, count 2 2006.211.07:36:28.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:36:28.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:36:28.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.07:36:28.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:28.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:36:29.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:36:29.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:36:29.08#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:36:29.08#ibcon#first serial, iclass 17, count 0 2006.211.07:36:29.08#ibcon#enter sib2, iclass 17, count 0 2006.211.07:36:29.08#ibcon#flushed, iclass 17, count 0 2006.211.07:36:29.08#ibcon#about to write, iclass 17, count 0 2006.211.07:36:29.08#ibcon#wrote, iclass 17, count 0 2006.211.07:36:29.08#ibcon#about to read 3, iclass 17, count 0 2006.211.07:36:29.10#ibcon#read 3, iclass 17, count 0 2006.211.07:36:29.10#ibcon#about to read 4, iclass 17, count 0 2006.211.07:36:29.10#ibcon#read 4, iclass 17, count 0 2006.211.07:36:29.10#ibcon#about to read 5, iclass 17, count 0 2006.211.07:36:29.10#ibcon#read 5, iclass 17, count 0 2006.211.07:36:29.10#ibcon#about to read 6, iclass 17, count 0 2006.211.07:36:29.10#ibcon#read 6, iclass 17, count 0 2006.211.07:36:29.10#ibcon#end of sib2, iclass 17, count 0 2006.211.07:36:29.10#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:36:29.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:36:29.10#ibcon#[25=USB\r\n] 2006.211.07:36:29.10#ibcon#*before write, iclass 17, count 0 2006.211.07:36:29.10#ibcon#enter sib2, iclass 17, count 0 2006.211.07:36:29.10#ibcon#flushed, iclass 17, count 0 2006.211.07:36:29.10#ibcon#about to write, iclass 17, count 0 2006.211.07:36:29.10#ibcon#wrote, iclass 17, count 0 2006.211.07:36:29.10#ibcon#about to read 3, iclass 17, count 0 2006.211.07:36:29.13#ibcon#read 3, iclass 17, count 0 2006.211.07:36:29.13#ibcon#about to read 4, iclass 17, count 0 2006.211.07:36:29.13#ibcon#read 4, iclass 17, count 0 2006.211.07:36:29.13#ibcon#about to read 5, iclass 17, count 0 2006.211.07:36:29.13#ibcon#read 5, iclass 17, count 0 2006.211.07:36:29.13#ibcon#about to read 6, iclass 17, count 0 2006.211.07:36:29.13#ibcon#read 6, iclass 17, count 0 2006.211.07:36:29.13#ibcon#end of sib2, iclass 17, count 0 2006.211.07:36:29.13#ibcon#*after write, iclass 17, count 0 2006.211.07:36:29.13#ibcon#*before return 0, iclass 17, count 0 2006.211.07:36:29.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:36:29.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:36:29.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:36:29.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:36:29.13$vc4f8/valo=6,772.99 2006.211.07:36:29.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.07:36:29.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.07:36:29.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:29.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:29.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:29.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:29.13#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:36:29.13#ibcon#first serial, iclass 19, count 0 2006.211.07:36:29.13#ibcon#enter sib2, iclass 19, count 0 2006.211.07:36:29.13#ibcon#flushed, iclass 19, count 0 2006.211.07:36:29.13#ibcon#about to write, iclass 19, count 0 2006.211.07:36:29.13#ibcon#wrote, iclass 19, count 0 2006.211.07:36:29.13#ibcon#about to read 3, iclass 19, count 0 2006.211.07:36:29.15#ibcon#read 3, iclass 19, count 0 2006.211.07:36:29.15#ibcon#about to read 4, iclass 19, count 0 2006.211.07:36:29.15#ibcon#read 4, iclass 19, count 0 2006.211.07:36:29.15#ibcon#about to read 5, iclass 19, count 0 2006.211.07:36:29.15#ibcon#read 5, iclass 19, count 0 2006.211.07:36:29.15#ibcon#about to read 6, iclass 19, count 0 2006.211.07:36:29.15#ibcon#read 6, iclass 19, count 0 2006.211.07:36:29.15#ibcon#end of sib2, iclass 19, count 0 2006.211.07:36:29.15#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:36:29.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:36:29.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:36:29.15#ibcon#*before write, iclass 19, count 0 2006.211.07:36:29.15#ibcon#enter sib2, iclass 19, count 0 2006.211.07:36:29.15#ibcon#flushed, iclass 19, count 0 2006.211.07:36:29.15#ibcon#about to write, iclass 19, count 0 2006.211.07:36:29.15#ibcon#wrote, iclass 19, count 0 2006.211.07:36:29.15#ibcon#about to read 3, iclass 19, count 0 2006.211.07:36:29.19#ibcon#read 3, iclass 19, count 0 2006.211.07:36:29.19#ibcon#about to read 4, iclass 19, count 0 2006.211.07:36:29.19#ibcon#read 4, iclass 19, count 0 2006.211.07:36:29.19#ibcon#about to read 5, iclass 19, count 0 2006.211.07:36:29.19#ibcon#read 5, iclass 19, count 0 2006.211.07:36:29.19#ibcon#about to read 6, iclass 19, count 0 2006.211.07:36:29.19#ibcon#read 6, iclass 19, count 0 2006.211.07:36:29.19#ibcon#end of sib2, iclass 19, count 0 2006.211.07:36:29.19#ibcon#*after write, iclass 19, count 0 2006.211.07:36:29.19#ibcon#*before return 0, iclass 19, count 0 2006.211.07:36:29.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:29.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:29.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:36:29.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:36:29.19$vc4f8/va=6,6 2006.211.07:36:29.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.07:36:29.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.07:36:29.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:29.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:29.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:29.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:29.25#ibcon#enter wrdev, iclass 21, count 2 2006.211.07:36:29.25#ibcon#first serial, iclass 21, count 2 2006.211.07:36:29.25#ibcon#enter sib2, iclass 21, count 2 2006.211.07:36:29.25#ibcon#flushed, iclass 21, count 2 2006.211.07:36:29.25#ibcon#about to write, iclass 21, count 2 2006.211.07:36:29.25#ibcon#wrote, iclass 21, count 2 2006.211.07:36:29.25#ibcon#about to read 3, iclass 21, count 2 2006.211.07:36:29.27#ibcon#read 3, iclass 21, count 2 2006.211.07:36:29.27#ibcon#about to read 4, iclass 21, count 2 2006.211.07:36:29.27#ibcon#read 4, iclass 21, count 2 2006.211.07:36:29.27#ibcon#about to read 5, iclass 21, count 2 2006.211.07:36:29.27#ibcon#read 5, iclass 21, count 2 2006.211.07:36:29.27#ibcon#about to read 6, iclass 21, count 2 2006.211.07:36:29.27#ibcon#read 6, iclass 21, count 2 2006.211.07:36:29.27#ibcon#end of sib2, iclass 21, count 2 2006.211.07:36:29.27#ibcon#*mode == 0, iclass 21, count 2 2006.211.07:36:29.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.07:36:29.27#ibcon#[25=AT06-06\r\n] 2006.211.07:36:29.27#ibcon#*before write, iclass 21, count 2 2006.211.07:36:29.27#ibcon#enter sib2, iclass 21, count 2 2006.211.07:36:29.27#ibcon#flushed, iclass 21, count 2 2006.211.07:36:29.27#ibcon#about to write, iclass 21, count 2 2006.211.07:36:29.27#ibcon#wrote, iclass 21, count 2 2006.211.07:36:29.27#ibcon#about to read 3, iclass 21, count 2 2006.211.07:36:29.30#ibcon#read 3, iclass 21, count 2 2006.211.07:36:29.30#ibcon#about to read 4, iclass 21, count 2 2006.211.07:36:29.30#ibcon#read 4, iclass 21, count 2 2006.211.07:36:29.30#ibcon#about to read 5, iclass 21, count 2 2006.211.07:36:29.30#ibcon#read 5, iclass 21, count 2 2006.211.07:36:29.30#ibcon#about to read 6, iclass 21, count 2 2006.211.07:36:29.30#ibcon#read 6, iclass 21, count 2 2006.211.07:36:29.30#ibcon#end of sib2, iclass 21, count 2 2006.211.07:36:29.30#ibcon#*after write, iclass 21, count 2 2006.211.07:36:29.30#ibcon#*before return 0, iclass 21, count 2 2006.211.07:36:29.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:29.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:29.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.07:36:29.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:29.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:29.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:29.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:29.42#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:36:29.42#ibcon#first serial, iclass 21, count 0 2006.211.07:36:29.42#ibcon#enter sib2, iclass 21, count 0 2006.211.07:36:29.42#ibcon#flushed, iclass 21, count 0 2006.211.07:36:29.42#ibcon#about to write, iclass 21, count 0 2006.211.07:36:29.42#ibcon#wrote, iclass 21, count 0 2006.211.07:36:29.42#ibcon#about to read 3, iclass 21, count 0 2006.211.07:36:29.44#ibcon#read 3, iclass 21, count 0 2006.211.07:36:29.44#ibcon#about to read 4, iclass 21, count 0 2006.211.07:36:29.44#ibcon#read 4, iclass 21, count 0 2006.211.07:36:29.44#ibcon#about to read 5, iclass 21, count 0 2006.211.07:36:29.44#ibcon#read 5, iclass 21, count 0 2006.211.07:36:29.44#ibcon#about to read 6, iclass 21, count 0 2006.211.07:36:29.44#ibcon#read 6, iclass 21, count 0 2006.211.07:36:29.44#ibcon#end of sib2, iclass 21, count 0 2006.211.07:36:29.44#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:36:29.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:36:29.44#ibcon#[25=USB\r\n] 2006.211.07:36:29.44#ibcon#*before write, iclass 21, count 0 2006.211.07:36:29.44#ibcon#enter sib2, iclass 21, count 0 2006.211.07:36:29.44#ibcon#flushed, iclass 21, count 0 2006.211.07:36:29.44#ibcon#about to write, iclass 21, count 0 2006.211.07:36:29.44#ibcon#wrote, iclass 21, count 0 2006.211.07:36:29.44#ibcon#about to read 3, iclass 21, count 0 2006.211.07:36:29.47#ibcon#read 3, iclass 21, count 0 2006.211.07:36:29.47#ibcon#about to read 4, iclass 21, count 0 2006.211.07:36:29.47#ibcon#read 4, iclass 21, count 0 2006.211.07:36:29.47#ibcon#about to read 5, iclass 21, count 0 2006.211.07:36:29.47#ibcon#read 5, iclass 21, count 0 2006.211.07:36:29.47#ibcon#about to read 6, iclass 21, count 0 2006.211.07:36:29.47#ibcon#read 6, iclass 21, count 0 2006.211.07:36:29.47#ibcon#end of sib2, iclass 21, count 0 2006.211.07:36:29.47#ibcon#*after write, iclass 21, count 0 2006.211.07:36:29.47#ibcon#*before return 0, iclass 21, count 0 2006.211.07:36:29.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:29.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:29.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:36:29.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:36:29.47$vc4f8/valo=7,832.99 2006.211.07:36:29.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:36:29.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:36:29.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:29.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:29.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:29.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:29.47#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:36:29.47#ibcon#first serial, iclass 23, count 0 2006.211.07:36:29.47#ibcon#enter sib2, iclass 23, count 0 2006.211.07:36:29.47#ibcon#flushed, iclass 23, count 0 2006.211.07:36:29.47#ibcon#about to write, iclass 23, count 0 2006.211.07:36:29.47#ibcon#wrote, iclass 23, count 0 2006.211.07:36:29.47#ibcon#about to read 3, iclass 23, count 0 2006.211.07:36:29.49#ibcon#read 3, iclass 23, count 0 2006.211.07:36:29.49#ibcon#about to read 4, iclass 23, count 0 2006.211.07:36:29.49#ibcon#read 4, iclass 23, count 0 2006.211.07:36:29.49#ibcon#about to read 5, iclass 23, count 0 2006.211.07:36:29.49#ibcon#read 5, iclass 23, count 0 2006.211.07:36:29.49#ibcon#about to read 6, iclass 23, count 0 2006.211.07:36:29.49#ibcon#read 6, iclass 23, count 0 2006.211.07:36:29.49#ibcon#end of sib2, iclass 23, count 0 2006.211.07:36:29.49#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:36:29.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:36:29.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:36:29.49#ibcon#*before write, iclass 23, count 0 2006.211.07:36:29.49#ibcon#enter sib2, iclass 23, count 0 2006.211.07:36:29.49#ibcon#flushed, iclass 23, count 0 2006.211.07:36:29.49#ibcon#about to write, iclass 23, count 0 2006.211.07:36:29.49#ibcon#wrote, iclass 23, count 0 2006.211.07:36:29.49#ibcon#about to read 3, iclass 23, count 0 2006.211.07:36:29.53#ibcon#read 3, iclass 23, count 0 2006.211.07:36:29.53#ibcon#about to read 4, iclass 23, count 0 2006.211.07:36:29.53#ibcon#read 4, iclass 23, count 0 2006.211.07:36:29.53#ibcon#about to read 5, iclass 23, count 0 2006.211.07:36:29.53#ibcon#read 5, iclass 23, count 0 2006.211.07:36:29.53#ibcon#about to read 6, iclass 23, count 0 2006.211.07:36:29.53#ibcon#read 6, iclass 23, count 0 2006.211.07:36:29.53#ibcon#end of sib2, iclass 23, count 0 2006.211.07:36:29.53#ibcon#*after write, iclass 23, count 0 2006.211.07:36:29.53#ibcon#*before return 0, iclass 23, count 0 2006.211.07:36:29.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:29.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:29.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:36:29.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:36:29.53$vc4f8/va=7,6 2006.211.07:36:29.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.07:36:29.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.07:36:29.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:29.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:36:29.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:36:29.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:36:29.59#ibcon#enter wrdev, iclass 25, count 2 2006.211.07:36:29.59#ibcon#first serial, iclass 25, count 2 2006.211.07:36:29.59#ibcon#enter sib2, iclass 25, count 2 2006.211.07:36:29.59#ibcon#flushed, iclass 25, count 2 2006.211.07:36:29.59#ibcon#about to write, iclass 25, count 2 2006.211.07:36:29.59#ibcon#wrote, iclass 25, count 2 2006.211.07:36:29.59#ibcon#about to read 3, iclass 25, count 2 2006.211.07:36:29.61#ibcon#read 3, iclass 25, count 2 2006.211.07:36:29.61#ibcon#about to read 4, iclass 25, count 2 2006.211.07:36:29.61#ibcon#read 4, iclass 25, count 2 2006.211.07:36:29.61#ibcon#about to read 5, iclass 25, count 2 2006.211.07:36:29.61#ibcon#read 5, iclass 25, count 2 2006.211.07:36:29.61#ibcon#about to read 6, iclass 25, count 2 2006.211.07:36:29.61#ibcon#read 6, iclass 25, count 2 2006.211.07:36:29.61#ibcon#end of sib2, iclass 25, count 2 2006.211.07:36:29.61#ibcon#*mode == 0, iclass 25, count 2 2006.211.07:36:29.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.07:36:29.61#ibcon#[25=AT07-06\r\n] 2006.211.07:36:29.61#ibcon#*before write, iclass 25, count 2 2006.211.07:36:29.61#ibcon#enter sib2, iclass 25, count 2 2006.211.07:36:29.61#ibcon#flushed, iclass 25, count 2 2006.211.07:36:29.61#ibcon#about to write, iclass 25, count 2 2006.211.07:36:29.61#ibcon#wrote, iclass 25, count 2 2006.211.07:36:29.61#ibcon#about to read 3, iclass 25, count 2 2006.211.07:36:29.64#ibcon#read 3, iclass 25, count 2 2006.211.07:36:29.64#ibcon#about to read 4, iclass 25, count 2 2006.211.07:36:29.64#ibcon#read 4, iclass 25, count 2 2006.211.07:36:29.64#ibcon#about to read 5, iclass 25, count 2 2006.211.07:36:29.64#ibcon#read 5, iclass 25, count 2 2006.211.07:36:29.64#ibcon#about to read 6, iclass 25, count 2 2006.211.07:36:29.64#ibcon#read 6, iclass 25, count 2 2006.211.07:36:29.64#ibcon#end of sib2, iclass 25, count 2 2006.211.07:36:29.64#ibcon#*after write, iclass 25, count 2 2006.211.07:36:29.64#ibcon#*before return 0, iclass 25, count 2 2006.211.07:36:29.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:36:29.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:36:29.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.07:36:29.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:29.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:36:29.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:36:29.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:36:29.76#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:36:29.76#ibcon#first serial, iclass 25, count 0 2006.211.07:36:29.76#ibcon#enter sib2, iclass 25, count 0 2006.211.07:36:29.76#ibcon#flushed, iclass 25, count 0 2006.211.07:36:29.76#ibcon#about to write, iclass 25, count 0 2006.211.07:36:29.76#ibcon#wrote, iclass 25, count 0 2006.211.07:36:29.76#ibcon#about to read 3, iclass 25, count 0 2006.211.07:36:29.78#ibcon#read 3, iclass 25, count 0 2006.211.07:36:29.78#ibcon#about to read 4, iclass 25, count 0 2006.211.07:36:29.78#ibcon#read 4, iclass 25, count 0 2006.211.07:36:29.78#ibcon#about to read 5, iclass 25, count 0 2006.211.07:36:29.78#ibcon#read 5, iclass 25, count 0 2006.211.07:36:29.78#ibcon#about to read 6, iclass 25, count 0 2006.211.07:36:29.78#ibcon#read 6, iclass 25, count 0 2006.211.07:36:29.78#ibcon#end of sib2, iclass 25, count 0 2006.211.07:36:29.78#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:36:29.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:36:29.78#ibcon#[25=USB\r\n] 2006.211.07:36:29.78#ibcon#*before write, iclass 25, count 0 2006.211.07:36:29.78#ibcon#enter sib2, iclass 25, count 0 2006.211.07:36:29.78#ibcon#flushed, iclass 25, count 0 2006.211.07:36:29.78#ibcon#about to write, iclass 25, count 0 2006.211.07:36:29.78#ibcon#wrote, iclass 25, count 0 2006.211.07:36:29.78#ibcon#about to read 3, iclass 25, count 0 2006.211.07:36:29.81#ibcon#read 3, iclass 25, count 0 2006.211.07:36:29.81#ibcon#about to read 4, iclass 25, count 0 2006.211.07:36:29.81#ibcon#read 4, iclass 25, count 0 2006.211.07:36:29.81#ibcon#about to read 5, iclass 25, count 0 2006.211.07:36:29.81#ibcon#read 5, iclass 25, count 0 2006.211.07:36:29.81#ibcon#about to read 6, iclass 25, count 0 2006.211.07:36:29.81#ibcon#read 6, iclass 25, count 0 2006.211.07:36:29.81#ibcon#end of sib2, iclass 25, count 0 2006.211.07:36:29.81#ibcon#*after write, iclass 25, count 0 2006.211.07:36:29.81#ibcon#*before return 0, iclass 25, count 0 2006.211.07:36:29.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:36:29.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:36:29.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:36:29.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:36:29.81$vc4f8/valo=8,852.99 2006.211.07:36:29.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.07:36:29.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.07:36:29.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:29.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:36:29.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:36:29.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:36:29.81#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:36:29.81#ibcon#first serial, iclass 27, count 0 2006.211.07:36:29.81#ibcon#enter sib2, iclass 27, count 0 2006.211.07:36:29.81#ibcon#flushed, iclass 27, count 0 2006.211.07:36:29.81#ibcon#about to write, iclass 27, count 0 2006.211.07:36:29.81#ibcon#wrote, iclass 27, count 0 2006.211.07:36:29.81#ibcon#about to read 3, iclass 27, count 0 2006.211.07:36:29.83#ibcon#read 3, iclass 27, count 0 2006.211.07:36:29.83#ibcon#about to read 4, iclass 27, count 0 2006.211.07:36:29.83#ibcon#read 4, iclass 27, count 0 2006.211.07:36:29.83#ibcon#about to read 5, iclass 27, count 0 2006.211.07:36:29.83#ibcon#read 5, iclass 27, count 0 2006.211.07:36:29.83#ibcon#about to read 6, iclass 27, count 0 2006.211.07:36:29.83#ibcon#read 6, iclass 27, count 0 2006.211.07:36:29.83#ibcon#end of sib2, iclass 27, count 0 2006.211.07:36:29.83#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:36:29.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:36:29.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:36:29.83#ibcon#*before write, iclass 27, count 0 2006.211.07:36:29.83#ibcon#enter sib2, iclass 27, count 0 2006.211.07:36:29.83#ibcon#flushed, iclass 27, count 0 2006.211.07:36:29.83#ibcon#about to write, iclass 27, count 0 2006.211.07:36:29.83#ibcon#wrote, iclass 27, count 0 2006.211.07:36:29.83#ibcon#about to read 3, iclass 27, count 0 2006.211.07:36:29.87#ibcon#read 3, iclass 27, count 0 2006.211.07:36:29.87#ibcon#about to read 4, iclass 27, count 0 2006.211.07:36:29.87#ibcon#read 4, iclass 27, count 0 2006.211.07:36:29.87#ibcon#about to read 5, iclass 27, count 0 2006.211.07:36:29.87#ibcon#read 5, iclass 27, count 0 2006.211.07:36:29.87#ibcon#about to read 6, iclass 27, count 0 2006.211.07:36:29.87#ibcon#read 6, iclass 27, count 0 2006.211.07:36:29.87#ibcon#end of sib2, iclass 27, count 0 2006.211.07:36:29.87#ibcon#*after write, iclass 27, count 0 2006.211.07:36:29.87#ibcon#*before return 0, iclass 27, count 0 2006.211.07:36:29.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:36:29.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:36:29.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:36:29.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:36:29.87$vc4f8/va=8,7 2006.211.07:36:29.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.07:36:29.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.07:36:29.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:29.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:36:29.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:36:29.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:36:29.93#ibcon#enter wrdev, iclass 29, count 2 2006.211.07:36:29.93#ibcon#first serial, iclass 29, count 2 2006.211.07:36:29.93#ibcon#enter sib2, iclass 29, count 2 2006.211.07:36:29.93#ibcon#flushed, iclass 29, count 2 2006.211.07:36:29.93#ibcon#about to write, iclass 29, count 2 2006.211.07:36:29.93#ibcon#wrote, iclass 29, count 2 2006.211.07:36:29.93#ibcon#about to read 3, iclass 29, count 2 2006.211.07:36:29.95#ibcon#read 3, iclass 29, count 2 2006.211.07:36:29.95#ibcon#about to read 4, iclass 29, count 2 2006.211.07:36:29.95#ibcon#read 4, iclass 29, count 2 2006.211.07:36:29.95#ibcon#about to read 5, iclass 29, count 2 2006.211.07:36:29.95#ibcon#read 5, iclass 29, count 2 2006.211.07:36:29.95#ibcon#about to read 6, iclass 29, count 2 2006.211.07:36:29.95#ibcon#read 6, iclass 29, count 2 2006.211.07:36:29.95#ibcon#end of sib2, iclass 29, count 2 2006.211.07:36:29.95#ibcon#*mode == 0, iclass 29, count 2 2006.211.07:36:29.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.07:36:29.95#ibcon#[25=AT08-07\r\n] 2006.211.07:36:29.95#ibcon#*before write, iclass 29, count 2 2006.211.07:36:29.95#ibcon#enter sib2, iclass 29, count 2 2006.211.07:36:29.95#ibcon#flushed, iclass 29, count 2 2006.211.07:36:29.95#ibcon#about to write, iclass 29, count 2 2006.211.07:36:29.95#ibcon#wrote, iclass 29, count 2 2006.211.07:36:29.95#ibcon#about to read 3, iclass 29, count 2 2006.211.07:36:29.98#ibcon#read 3, iclass 29, count 2 2006.211.07:36:29.98#ibcon#about to read 4, iclass 29, count 2 2006.211.07:36:29.98#ibcon#read 4, iclass 29, count 2 2006.211.07:36:29.98#ibcon#about to read 5, iclass 29, count 2 2006.211.07:36:29.98#ibcon#read 5, iclass 29, count 2 2006.211.07:36:29.98#ibcon#about to read 6, iclass 29, count 2 2006.211.07:36:29.98#ibcon#read 6, iclass 29, count 2 2006.211.07:36:29.98#ibcon#end of sib2, iclass 29, count 2 2006.211.07:36:29.98#ibcon#*after write, iclass 29, count 2 2006.211.07:36:29.98#ibcon#*before return 0, iclass 29, count 2 2006.211.07:36:29.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:36:29.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:36:29.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.07:36:29.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:29.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:36:30.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:36:30.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:36:30.10#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:36:30.10#ibcon#first serial, iclass 29, count 0 2006.211.07:36:30.10#ibcon#enter sib2, iclass 29, count 0 2006.211.07:36:30.10#ibcon#flushed, iclass 29, count 0 2006.211.07:36:30.10#ibcon#about to write, iclass 29, count 0 2006.211.07:36:30.10#ibcon#wrote, iclass 29, count 0 2006.211.07:36:30.10#ibcon#about to read 3, iclass 29, count 0 2006.211.07:36:30.12#ibcon#read 3, iclass 29, count 0 2006.211.07:36:30.12#ibcon#about to read 4, iclass 29, count 0 2006.211.07:36:30.12#ibcon#read 4, iclass 29, count 0 2006.211.07:36:30.12#ibcon#about to read 5, iclass 29, count 0 2006.211.07:36:30.12#ibcon#read 5, iclass 29, count 0 2006.211.07:36:30.12#ibcon#about to read 6, iclass 29, count 0 2006.211.07:36:30.12#ibcon#read 6, iclass 29, count 0 2006.211.07:36:30.12#ibcon#end of sib2, iclass 29, count 0 2006.211.07:36:30.12#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:36:30.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:36:30.12#ibcon#[25=USB\r\n] 2006.211.07:36:30.12#ibcon#*before write, iclass 29, count 0 2006.211.07:36:30.12#ibcon#enter sib2, iclass 29, count 0 2006.211.07:36:30.12#ibcon#flushed, iclass 29, count 0 2006.211.07:36:30.12#ibcon#about to write, iclass 29, count 0 2006.211.07:36:30.12#ibcon#wrote, iclass 29, count 0 2006.211.07:36:30.12#ibcon#about to read 3, iclass 29, count 0 2006.211.07:36:30.15#ibcon#read 3, iclass 29, count 0 2006.211.07:36:30.15#ibcon#about to read 4, iclass 29, count 0 2006.211.07:36:30.15#ibcon#read 4, iclass 29, count 0 2006.211.07:36:30.15#ibcon#about to read 5, iclass 29, count 0 2006.211.07:36:30.15#ibcon#read 5, iclass 29, count 0 2006.211.07:36:30.15#ibcon#about to read 6, iclass 29, count 0 2006.211.07:36:30.15#ibcon#read 6, iclass 29, count 0 2006.211.07:36:30.15#ibcon#end of sib2, iclass 29, count 0 2006.211.07:36:30.15#ibcon#*after write, iclass 29, count 0 2006.211.07:36:30.15#ibcon#*before return 0, iclass 29, count 0 2006.211.07:36:30.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:36:30.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:36:30.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:36:30.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:36:30.15$vc4f8/vblo=1,632.99 2006.211.07:36:30.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.07:36:30.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.07:36:30.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:30.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:36:30.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:36:30.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:36:30.15#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:36:30.15#ibcon#first serial, iclass 31, count 0 2006.211.07:36:30.15#ibcon#enter sib2, iclass 31, count 0 2006.211.07:36:30.15#ibcon#flushed, iclass 31, count 0 2006.211.07:36:30.15#ibcon#about to write, iclass 31, count 0 2006.211.07:36:30.15#ibcon#wrote, iclass 31, count 0 2006.211.07:36:30.15#ibcon#about to read 3, iclass 31, count 0 2006.211.07:36:30.17#ibcon#read 3, iclass 31, count 0 2006.211.07:36:30.17#ibcon#about to read 4, iclass 31, count 0 2006.211.07:36:30.17#ibcon#read 4, iclass 31, count 0 2006.211.07:36:30.17#ibcon#about to read 5, iclass 31, count 0 2006.211.07:36:30.17#ibcon#read 5, iclass 31, count 0 2006.211.07:36:30.17#ibcon#about to read 6, iclass 31, count 0 2006.211.07:36:30.17#ibcon#read 6, iclass 31, count 0 2006.211.07:36:30.17#ibcon#end of sib2, iclass 31, count 0 2006.211.07:36:30.17#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:36:30.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:36:30.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:36:30.17#ibcon#*before write, iclass 31, count 0 2006.211.07:36:30.17#ibcon#enter sib2, iclass 31, count 0 2006.211.07:36:30.17#ibcon#flushed, iclass 31, count 0 2006.211.07:36:30.17#ibcon#about to write, iclass 31, count 0 2006.211.07:36:30.17#ibcon#wrote, iclass 31, count 0 2006.211.07:36:30.17#ibcon#about to read 3, iclass 31, count 0 2006.211.07:36:30.21#ibcon#read 3, iclass 31, count 0 2006.211.07:36:30.21#ibcon#about to read 4, iclass 31, count 0 2006.211.07:36:30.21#ibcon#read 4, iclass 31, count 0 2006.211.07:36:30.21#ibcon#about to read 5, iclass 31, count 0 2006.211.07:36:30.21#ibcon#read 5, iclass 31, count 0 2006.211.07:36:30.21#ibcon#about to read 6, iclass 31, count 0 2006.211.07:36:30.21#ibcon#read 6, iclass 31, count 0 2006.211.07:36:30.21#ibcon#end of sib2, iclass 31, count 0 2006.211.07:36:30.21#ibcon#*after write, iclass 31, count 0 2006.211.07:36:30.21#ibcon#*before return 0, iclass 31, count 0 2006.211.07:36:30.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:36:30.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:36:30.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:36:30.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:36:30.21$vc4f8/vb=1,4 2006.211.07:36:30.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.07:36:30.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.07:36:30.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:30.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:36:30.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:36:30.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:36:30.21#ibcon#enter wrdev, iclass 33, count 2 2006.211.07:36:30.21#ibcon#first serial, iclass 33, count 2 2006.211.07:36:30.21#ibcon#enter sib2, iclass 33, count 2 2006.211.07:36:30.21#ibcon#flushed, iclass 33, count 2 2006.211.07:36:30.21#ibcon#about to write, iclass 33, count 2 2006.211.07:36:30.21#ibcon#wrote, iclass 33, count 2 2006.211.07:36:30.21#ibcon#about to read 3, iclass 33, count 2 2006.211.07:36:30.23#ibcon#read 3, iclass 33, count 2 2006.211.07:36:30.23#ibcon#about to read 4, iclass 33, count 2 2006.211.07:36:30.23#ibcon#read 4, iclass 33, count 2 2006.211.07:36:30.23#ibcon#about to read 5, iclass 33, count 2 2006.211.07:36:30.23#ibcon#read 5, iclass 33, count 2 2006.211.07:36:30.23#ibcon#about to read 6, iclass 33, count 2 2006.211.07:36:30.23#ibcon#read 6, iclass 33, count 2 2006.211.07:36:30.23#ibcon#end of sib2, iclass 33, count 2 2006.211.07:36:30.23#ibcon#*mode == 0, iclass 33, count 2 2006.211.07:36:30.23#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.07:36:30.23#ibcon#[27=AT01-04\r\n] 2006.211.07:36:30.23#ibcon#*before write, iclass 33, count 2 2006.211.07:36:30.23#ibcon#enter sib2, iclass 33, count 2 2006.211.07:36:30.23#ibcon#flushed, iclass 33, count 2 2006.211.07:36:30.23#ibcon#about to write, iclass 33, count 2 2006.211.07:36:30.23#ibcon#wrote, iclass 33, count 2 2006.211.07:36:30.23#ibcon#about to read 3, iclass 33, count 2 2006.211.07:36:30.26#ibcon#read 3, iclass 33, count 2 2006.211.07:36:30.26#ibcon#about to read 4, iclass 33, count 2 2006.211.07:36:30.26#ibcon#read 4, iclass 33, count 2 2006.211.07:36:30.26#ibcon#about to read 5, iclass 33, count 2 2006.211.07:36:30.26#ibcon#read 5, iclass 33, count 2 2006.211.07:36:30.26#ibcon#about to read 6, iclass 33, count 2 2006.211.07:36:30.26#ibcon#read 6, iclass 33, count 2 2006.211.07:36:30.26#ibcon#end of sib2, iclass 33, count 2 2006.211.07:36:30.26#ibcon#*after write, iclass 33, count 2 2006.211.07:36:30.26#ibcon#*before return 0, iclass 33, count 2 2006.211.07:36:30.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:36:30.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:36:30.26#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.07:36:30.26#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:30.26#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:36:30.38#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:36:30.38#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:36:30.38#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:36:30.38#ibcon#first serial, iclass 33, count 0 2006.211.07:36:30.38#ibcon#enter sib2, iclass 33, count 0 2006.211.07:36:30.38#ibcon#flushed, iclass 33, count 0 2006.211.07:36:30.38#ibcon#about to write, iclass 33, count 0 2006.211.07:36:30.38#ibcon#wrote, iclass 33, count 0 2006.211.07:36:30.38#ibcon#about to read 3, iclass 33, count 0 2006.211.07:36:30.40#ibcon#read 3, iclass 33, count 0 2006.211.07:36:30.40#ibcon#about to read 4, iclass 33, count 0 2006.211.07:36:30.40#ibcon#read 4, iclass 33, count 0 2006.211.07:36:30.40#ibcon#about to read 5, iclass 33, count 0 2006.211.07:36:30.40#ibcon#read 5, iclass 33, count 0 2006.211.07:36:30.40#ibcon#about to read 6, iclass 33, count 0 2006.211.07:36:30.40#ibcon#read 6, iclass 33, count 0 2006.211.07:36:30.40#ibcon#end of sib2, iclass 33, count 0 2006.211.07:36:30.40#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:36:30.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:36:30.40#ibcon#[27=USB\r\n] 2006.211.07:36:30.40#ibcon#*before write, iclass 33, count 0 2006.211.07:36:30.40#ibcon#enter sib2, iclass 33, count 0 2006.211.07:36:30.40#ibcon#flushed, iclass 33, count 0 2006.211.07:36:30.40#ibcon#about to write, iclass 33, count 0 2006.211.07:36:30.40#ibcon#wrote, iclass 33, count 0 2006.211.07:36:30.40#ibcon#about to read 3, iclass 33, count 0 2006.211.07:36:30.43#ibcon#read 3, iclass 33, count 0 2006.211.07:36:30.43#ibcon#about to read 4, iclass 33, count 0 2006.211.07:36:30.43#ibcon#read 4, iclass 33, count 0 2006.211.07:36:30.43#ibcon#about to read 5, iclass 33, count 0 2006.211.07:36:30.43#ibcon#read 5, iclass 33, count 0 2006.211.07:36:30.43#ibcon#about to read 6, iclass 33, count 0 2006.211.07:36:30.43#ibcon#read 6, iclass 33, count 0 2006.211.07:36:30.43#ibcon#end of sib2, iclass 33, count 0 2006.211.07:36:30.43#ibcon#*after write, iclass 33, count 0 2006.211.07:36:30.43#ibcon#*before return 0, iclass 33, count 0 2006.211.07:36:30.43#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:36:30.43#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:36:30.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:36:30.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:36:30.43$vc4f8/vblo=2,640.99 2006.211.07:36:30.43#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.07:36:30.43#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.07:36:30.43#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:30.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:30.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:30.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:30.43#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:36:30.43#ibcon#first serial, iclass 35, count 0 2006.211.07:36:30.43#ibcon#enter sib2, iclass 35, count 0 2006.211.07:36:30.43#ibcon#flushed, iclass 35, count 0 2006.211.07:36:30.43#ibcon#about to write, iclass 35, count 0 2006.211.07:36:30.43#ibcon#wrote, iclass 35, count 0 2006.211.07:36:30.43#ibcon#about to read 3, iclass 35, count 0 2006.211.07:36:30.45#ibcon#read 3, iclass 35, count 0 2006.211.07:36:30.45#ibcon#about to read 4, iclass 35, count 0 2006.211.07:36:30.45#ibcon#read 4, iclass 35, count 0 2006.211.07:36:30.45#ibcon#about to read 5, iclass 35, count 0 2006.211.07:36:30.45#ibcon#read 5, iclass 35, count 0 2006.211.07:36:30.45#ibcon#about to read 6, iclass 35, count 0 2006.211.07:36:30.45#ibcon#read 6, iclass 35, count 0 2006.211.07:36:30.45#ibcon#end of sib2, iclass 35, count 0 2006.211.07:36:30.45#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:36:30.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:36:30.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:36:30.45#ibcon#*before write, iclass 35, count 0 2006.211.07:36:30.45#ibcon#enter sib2, iclass 35, count 0 2006.211.07:36:30.45#ibcon#flushed, iclass 35, count 0 2006.211.07:36:30.45#ibcon#about to write, iclass 35, count 0 2006.211.07:36:30.45#ibcon#wrote, iclass 35, count 0 2006.211.07:36:30.45#ibcon#about to read 3, iclass 35, count 0 2006.211.07:36:30.49#ibcon#read 3, iclass 35, count 0 2006.211.07:36:30.49#ibcon#about to read 4, iclass 35, count 0 2006.211.07:36:30.49#ibcon#read 4, iclass 35, count 0 2006.211.07:36:30.49#ibcon#about to read 5, iclass 35, count 0 2006.211.07:36:30.49#ibcon#read 5, iclass 35, count 0 2006.211.07:36:30.49#ibcon#about to read 6, iclass 35, count 0 2006.211.07:36:30.49#ibcon#read 6, iclass 35, count 0 2006.211.07:36:30.49#ibcon#end of sib2, iclass 35, count 0 2006.211.07:36:30.49#ibcon#*after write, iclass 35, count 0 2006.211.07:36:30.49#ibcon#*before return 0, iclass 35, count 0 2006.211.07:36:30.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:30.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:36:30.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:36:30.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:36:30.49$vc4f8/vb=2,4 2006.211.07:36:30.49#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.07:36:30.49#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.07:36:30.49#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:30.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:30.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:30.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:30.55#ibcon#enter wrdev, iclass 37, count 2 2006.211.07:36:30.55#ibcon#first serial, iclass 37, count 2 2006.211.07:36:30.55#ibcon#enter sib2, iclass 37, count 2 2006.211.07:36:30.55#ibcon#flushed, iclass 37, count 2 2006.211.07:36:30.55#ibcon#about to write, iclass 37, count 2 2006.211.07:36:30.55#ibcon#wrote, iclass 37, count 2 2006.211.07:36:30.55#ibcon#about to read 3, iclass 37, count 2 2006.211.07:36:30.57#ibcon#read 3, iclass 37, count 2 2006.211.07:36:30.57#ibcon#about to read 4, iclass 37, count 2 2006.211.07:36:30.57#ibcon#read 4, iclass 37, count 2 2006.211.07:36:30.57#ibcon#about to read 5, iclass 37, count 2 2006.211.07:36:30.57#ibcon#read 5, iclass 37, count 2 2006.211.07:36:30.57#ibcon#about to read 6, iclass 37, count 2 2006.211.07:36:30.57#ibcon#read 6, iclass 37, count 2 2006.211.07:36:30.57#ibcon#end of sib2, iclass 37, count 2 2006.211.07:36:30.57#ibcon#*mode == 0, iclass 37, count 2 2006.211.07:36:30.57#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.07:36:30.57#ibcon#[27=AT02-04\r\n] 2006.211.07:36:30.57#ibcon#*before write, iclass 37, count 2 2006.211.07:36:30.57#ibcon#enter sib2, iclass 37, count 2 2006.211.07:36:30.57#ibcon#flushed, iclass 37, count 2 2006.211.07:36:30.57#ibcon#about to write, iclass 37, count 2 2006.211.07:36:30.57#ibcon#wrote, iclass 37, count 2 2006.211.07:36:30.57#ibcon#about to read 3, iclass 37, count 2 2006.211.07:36:30.60#ibcon#read 3, iclass 37, count 2 2006.211.07:36:30.60#ibcon#about to read 4, iclass 37, count 2 2006.211.07:36:30.60#ibcon#read 4, iclass 37, count 2 2006.211.07:36:30.60#ibcon#about to read 5, iclass 37, count 2 2006.211.07:36:30.60#ibcon#read 5, iclass 37, count 2 2006.211.07:36:30.60#ibcon#about to read 6, iclass 37, count 2 2006.211.07:36:30.60#ibcon#read 6, iclass 37, count 2 2006.211.07:36:30.60#ibcon#end of sib2, iclass 37, count 2 2006.211.07:36:30.60#ibcon#*after write, iclass 37, count 2 2006.211.07:36:30.60#ibcon#*before return 0, iclass 37, count 2 2006.211.07:36:30.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:30.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:36:30.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.07:36:30.60#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:30.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:30.72#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:30.72#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:30.72#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:36:30.72#ibcon#first serial, iclass 37, count 0 2006.211.07:36:30.72#ibcon#enter sib2, iclass 37, count 0 2006.211.07:36:30.72#ibcon#flushed, iclass 37, count 0 2006.211.07:36:30.72#ibcon#about to write, iclass 37, count 0 2006.211.07:36:30.72#ibcon#wrote, iclass 37, count 0 2006.211.07:36:30.72#ibcon#about to read 3, iclass 37, count 0 2006.211.07:36:30.74#ibcon#read 3, iclass 37, count 0 2006.211.07:36:30.74#ibcon#about to read 4, iclass 37, count 0 2006.211.07:36:30.74#ibcon#read 4, iclass 37, count 0 2006.211.07:36:30.74#ibcon#about to read 5, iclass 37, count 0 2006.211.07:36:30.74#ibcon#read 5, iclass 37, count 0 2006.211.07:36:30.74#ibcon#about to read 6, iclass 37, count 0 2006.211.07:36:30.74#ibcon#read 6, iclass 37, count 0 2006.211.07:36:30.74#ibcon#end of sib2, iclass 37, count 0 2006.211.07:36:30.74#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:36:30.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:36:30.74#ibcon#[27=USB\r\n] 2006.211.07:36:30.74#ibcon#*before write, iclass 37, count 0 2006.211.07:36:30.74#ibcon#enter sib2, iclass 37, count 0 2006.211.07:36:30.74#ibcon#flushed, iclass 37, count 0 2006.211.07:36:30.74#ibcon#about to write, iclass 37, count 0 2006.211.07:36:30.74#ibcon#wrote, iclass 37, count 0 2006.211.07:36:30.74#ibcon#about to read 3, iclass 37, count 0 2006.211.07:36:30.77#ibcon#read 3, iclass 37, count 0 2006.211.07:36:30.77#ibcon#about to read 4, iclass 37, count 0 2006.211.07:36:30.77#ibcon#read 4, iclass 37, count 0 2006.211.07:36:30.77#ibcon#about to read 5, iclass 37, count 0 2006.211.07:36:30.77#ibcon#read 5, iclass 37, count 0 2006.211.07:36:30.77#ibcon#about to read 6, iclass 37, count 0 2006.211.07:36:30.77#ibcon#read 6, iclass 37, count 0 2006.211.07:36:30.77#ibcon#end of sib2, iclass 37, count 0 2006.211.07:36:30.77#ibcon#*after write, iclass 37, count 0 2006.211.07:36:30.77#ibcon#*before return 0, iclass 37, count 0 2006.211.07:36:30.77#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:30.77#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:36:30.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:36:30.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:36:30.77$vc4f8/vblo=3,656.99 2006.211.07:36:30.77#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.07:36:30.77#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.07:36:30.77#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:30.77#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:30.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:30.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:30.77#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:36:30.77#ibcon#first serial, iclass 39, count 0 2006.211.07:36:30.77#ibcon#enter sib2, iclass 39, count 0 2006.211.07:36:30.77#ibcon#flushed, iclass 39, count 0 2006.211.07:36:30.77#ibcon#about to write, iclass 39, count 0 2006.211.07:36:30.77#ibcon#wrote, iclass 39, count 0 2006.211.07:36:30.77#ibcon#about to read 3, iclass 39, count 0 2006.211.07:36:30.79#ibcon#read 3, iclass 39, count 0 2006.211.07:36:30.79#ibcon#about to read 4, iclass 39, count 0 2006.211.07:36:30.79#ibcon#read 4, iclass 39, count 0 2006.211.07:36:30.79#ibcon#about to read 5, iclass 39, count 0 2006.211.07:36:30.79#ibcon#read 5, iclass 39, count 0 2006.211.07:36:30.79#ibcon#about to read 6, iclass 39, count 0 2006.211.07:36:30.79#ibcon#read 6, iclass 39, count 0 2006.211.07:36:30.79#ibcon#end of sib2, iclass 39, count 0 2006.211.07:36:30.79#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:36:30.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:36:30.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:36:30.79#ibcon#*before write, iclass 39, count 0 2006.211.07:36:30.79#ibcon#enter sib2, iclass 39, count 0 2006.211.07:36:30.79#ibcon#flushed, iclass 39, count 0 2006.211.07:36:30.79#ibcon#about to write, iclass 39, count 0 2006.211.07:36:30.79#ibcon#wrote, iclass 39, count 0 2006.211.07:36:30.79#ibcon#about to read 3, iclass 39, count 0 2006.211.07:36:30.83#ibcon#read 3, iclass 39, count 0 2006.211.07:36:30.83#ibcon#about to read 4, iclass 39, count 0 2006.211.07:36:30.83#ibcon#read 4, iclass 39, count 0 2006.211.07:36:30.83#ibcon#about to read 5, iclass 39, count 0 2006.211.07:36:30.83#ibcon#read 5, iclass 39, count 0 2006.211.07:36:30.83#ibcon#about to read 6, iclass 39, count 0 2006.211.07:36:30.83#ibcon#read 6, iclass 39, count 0 2006.211.07:36:30.83#ibcon#end of sib2, iclass 39, count 0 2006.211.07:36:30.83#ibcon#*after write, iclass 39, count 0 2006.211.07:36:30.83#ibcon#*before return 0, iclass 39, count 0 2006.211.07:36:30.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:30.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:36:30.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:36:30.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:36:30.83$vc4f8/vb=3,3 2006.211.07:36:30.83#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.07:36:30.83#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.07:36:30.83#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:30.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:30.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:30.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:30.89#ibcon#enter wrdev, iclass 3, count 2 2006.211.07:36:30.89#ibcon#first serial, iclass 3, count 2 2006.211.07:36:30.89#ibcon#enter sib2, iclass 3, count 2 2006.211.07:36:30.89#ibcon#flushed, iclass 3, count 2 2006.211.07:36:30.89#ibcon#about to write, iclass 3, count 2 2006.211.07:36:30.89#ibcon#wrote, iclass 3, count 2 2006.211.07:36:30.89#ibcon#about to read 3, iclass 3, count 2 2006.211.07:36:30.91#ibcon#read 3, iclass 3, count 2 2006.211.07:36:30.91#ibcon#about to read 4, iclass 3, count 2 2006.211.07:36:30.91#ibcon#read 4, iclass 3, count 2 2006.211.07:36:30.91#ibcon#about to read 5, iclass 3, count 2 2006.211.07:36:30.91#ibcon#read 5, iclass 3, count 2 2006.211.07:36:30.91#ibcon#about to read 6, iclass 3, count 2 2006.211.07:36:30.91#ibcon#read 6, iclass 3, count 2 2006.211.07:36:30.91#ibcon#end of sib2, iclass 3, count 2 2006.211.07:36:30.91#ibcon#*mode == 0, iclass 3, count 2 2006.211.07:36:30.91#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.07:36:30.91#ibcon#[27=AT03-03\r\n] 2006.211.07:36:30.91#ibcon#*before write, iclass 3, count 2 2006.211.07:36:30.91#ibcon#enter sib2, iclass 3, count 2 2006.211.07:36:30.91#ibcon#flushed, iclass 3, count 2 2006.211.07:36:30.91#ibcon#about to write, iclass 3, count 2 2006.211.07:36:30.91#ibcon#wrote, iclass 3, count 2 2006.211.07:36:30.91#ibcon#about to read 3, iclass 3, count 2 2006.211.07:36:30.94#ibcon#read 3, iclass 3, count 2 2006.211.07:36:30.94#ibcon#about to read 4, iclass 3, count 2 2006.211.07:36:30.94#ibcon#read 4, iclass 3, count 2 2006.211.07:36:30.94#ibcon#about to read 5, iclass 3, count 2 2006.211.07:36:30.94#ibcon#read 5, iclass 3, count 2 2006.211.07:36:30.94#ibcon#about to read 6, iclass 3, count 2 2006.211.07:36:30.94#ibcon#read 6, iclass 3, count 2 2006.211.07:36:30.94#ibcon#end of sib2, iclass 3, count 2 2006.211.07:36:30.94#ibcon#*after write, iclass 3, count 2 2006.211.07:36:30.94#ibcon#*before return 0, iclass 3, count 2 2006.211.07:36:30.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:30.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:36:30.94#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.07:36:30.94#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:30.94#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:31.06#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:31.06#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:31.06#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:36:31.06#ibcon#first serial, iclass 3, count 0 2006.211.07:36:31.06#ibcon#enter sib2, iclass 3, count 0 2006.211.07:36:31.06#ibcon#flushed, iclass 3, count 0 2006.211.07:36:31.06#ibcon#about to write, iclass 3, count 0 2006.211.07:36:31.06#ibcon#wrote, iclass 3, count 0 2006.211.07:36:31.06#ibcon#about to read 3, iclass 3, count 0 2006.211.07:36:31.08#ibcon#read 3, iclass 3, count 0 2006.211.07:36:31.08#ibcon#about to read 4, iclass 3, count 0 2006.211.07:36:31.08#ibcon#read 4, iclass 3, count 0 2006.211.07:36:31.08#ibcon#about to read 5, iclass 3, count 0 2006.211.07:36:31.08#ibcon#read 5, iclass 3, count 0 2006.211.07:36:31.08#ibcon#about to read 6, iclass 3, count 0 2006.211.07:36:31.08#ibcon#read 6, iclass 3, count 0 2006.211.07:36:31.08#ibcon#end of sib2, iclass 3, count 0 2006.211.07:36:31.08#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:36:31.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:36:31.08#ibcon#[27=USB\r\n] 2006.211.07:36:31.08#ibcon#*before write, iclass 3, count 0 2006.211.07:36:31.08#ibcon#enter sib2, iclass 3, count 0 2006.211.07:36:31.08#ibcon#flushed, iclass 3, count 0 2006.211.07:36:31.08#ibcon#about to write, iclass 3, count 0 2006.211.07:36:31.08#ibcon#wrote, iclass 3, count 0 2006.211.07:36:31.08#ibcon#about to read 3, iclass 3, count 0 2006.211.07:36:31.11#ibcon#read 3, iclass 3, count 0 2006.211.07:36:31.11#ibcon#about to read 4, iclass 3, count 0 2006.211.07:36:31.11#ibcon#read 4, iclass 3, count 0 2006.211.07:36:31.11#ibcon#about to read 5, iclass 3, count 0 2006.211.07:36:31.11#ibcon#read 5, iclass 3, count 0 2006.211.07:36:31.11#ibcon#about to read 6, iclass 3, count 0 2006.211.07:36:31.11#ibcon#read 6, iclass 3, count 0 2006.211.07:36:31.11#ibcon#end of sib2, iclass 3, count 0 2006.211.07:36:31.11#ibcon#*after write, iclass 3, count 0 2006.211.07:36:31.11#ibcon#*before return 0, iclass 3, count 0 2006.211.07:36:31.11#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:31.11#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:36:31.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:36:31.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:36:31.11$vc4f8/vblo=4,712.99 2006.211.07:36:31.11#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.07:36:31.11#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.07:36:31.11#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:31.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:31.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:31.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:31.11#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:36:31.11#ibcon#first serial, iclass 5, count 0 2006.211.07:36:31.11#ibcon#enter sib2, iclass 5, count 0 2006.211.07:36:31.11#ibcon#flushed, iclass 5, count 0 2006.211.07:36:31.11#ibcon#about to write, iclass 5, count 0 2006.211.07:36:31.11#ibcon#wrote, iclass 5, count 0 2006.211.07:36:31.11#ibcon#about to read 3, iclass 5, count 0 2006.211.07:36:31.13#ibcon#read 3, iclass 5, count 0 2006.211.07:36:31.13#ibcon#about to read 4, iclass 5, count 0 2006.211.07:36:31.13#ibcon#read 4, iclass 5, count 0 2006.211.07:36:31.13#ibcon#about to read 5, iclass 5, count 0 2006.211.07:36:31.13#ibcon#read 5, iclass 5, count 0 2006.211.07:36:31.13#ibcon#about to read 6, iclass 5, count 0 2006.211.07:36:31.13#ibcon#read 6, iclass 5, count 0 2006.211.07:36:31.13#ibcon#end of sib2, iclass 5, count 0 2006.211.07:36:31.13#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:36:31.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:36:31.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:36:31.13#ibcon#*before write, iclass 5, count 0 2006.211.07:36:31.13#ibcon#enter sib2, iclass 5, count 0 2006.211.07:36:31.13#ibcon#flushed, iclass 5, count 0 2006.211.07:36:31.13#ibcon#about to write, iclass 5, count 0 2006.211.07:36:31.13#ibcon#wrote, iclass 5, count 0 2006.211.07:36:31.13#ibcon#about to read 3, iclass 5, count 0 2006.211.07:36:31.17#ibcon#read 3, iclass 5, count 0 2006.211.07:36:31.17#ibcon#about to read 4, iclass 5, count 0 2006.211.07:36:31.17#ibcon#read 4, iclass 5, count 0 2006.211.07:36:31.17#ibcon#about to read 5, iclass 5, count 0 2006.211.07:36:31.17#ibcon#read 5, iclass 5, count 0 2006.211.07:36:31.17#ibcon#about to read 6, iclass 5, count 0 2006.211.07:36:31.17#ibcon#read 6, iclass 5, count 0 2006.211.07:36:31.17#ibcon#end of sib2, iclass 5, count 0 2006.211.07:36:31.17#ibcon#*after write, iclass 5, count 0 2006.211.07:36:31.17#ibcon#*before return 0, iclass 5, count 0 2006.211.07:36:31.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:31.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:36:31.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:36:31.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:36:31.17$vc4f8/vb=4,3 2006.211.07:36:31.17#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.07:36:31.17#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.07:36:31.17#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:31.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:31.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:31.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:31.23#ibcon#enter wrdev, iclass 7, count 2 2006.211.07:36:31.23#ibcon#first serial, iclass 7, count 2 2006.211.07:36:31.23#ibcon#enter sib2, iclass 7, count 2 2006.211.07:36:31.23#ibcon#flushed, iclass 7, count 2 2006.211.07:36:31.23#ibcon#about to write, iclass 7, count 2 2006.211.07:36:31.23#ibcon#wrote, iclass 7, count 2 2006.211.07:36:31.23#ibcon#about to read 3, iclass 7, count 2 2006.211.07:36:31.25#ibcon#read 3, iclass 7, count 2 2006.211.07:36:31.25#ibcon#about to read 4, iclass 7, count 2 2006.211.07:36:31.25#ibcon#read 4, iclass 7, count 2 2006.211.07:36:31.25#ibcon#about to read 5, iclass 7, count 2 2006.211.07:36:31.25#ibcon#read 5, iclass 7, count 2 2006.211.07:36:31.25#ibcon#about to read 6, iclass 7, count 2 2006.211.07:36:31.25#ibcon#read 6, iclass 7, count 2 2006.211.07:36:31.25#ibcon#end of sib2, iclass 7, count 2 2006.211.07:36:31.25#ibcon#*mode == 0, iclass 7, count 2 2006.211.07:36:31.25#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.07:36:31.25#ibcon#[27=AT04-03\r\n] 2006.211.07:36:31.25#ibcon#*before write, iclass 7, count 2 2006.211.07:36:31.25#ibcon#enter sib2, iclass 7, count 2 2006.211.07:36:31.25#ibcon#flushed, iclass 7, count 2 2006.211.07:36:31.25#ibcon#about to write, iclass 7, count 2 2006.211.07:36:31.25#ibcon#wrote, iclass 7, count 2 2006.211.07:36:31.25#ibcon#about to read 3, iclass 7, count 2 2006.211.07:36:31.28#ibcon#read 3, iclass 7, count 2 2006.211.07:36:31.28#ibcon#about to read 4, iclass 7, count 2 2006.211.07:36:31.28#ibcon#read 4, iclass 7, count 2 2006.211.07:36:31.28#ibcon#about to read 5, iclass 7, count 2 2006.211.07:36:31.28#ibcon#read 5, iclass 7, count 2 2006.211.07:36:31.28#ibcon#about to read 6, iclass 7, count 2 2006.211.07:36:31.28#ibcon#read 6, iclass 7, count 2 2006.211.07:36:31.28#ibcon#end of sib2, iclass 7, count 2 2006.211.07:36:31.28#ibcon#*after write, iclass 7, count 2 2006.211.07:36:31.28#ibcon#*before return 0, iclass 7, count 2 2006.211.07:36:31.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:31.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:36:31.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.07:36:31.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:31.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:31.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:31.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:31.40#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:36:31.40#ibcon#first serial, iclass 7, count 0 2006.211.07:36:31.40#ibcon#enter sib2, iclass 7, count 0 2006.211.07:36:31.40#ibcon#flushed, iclass 7, count 0 2006.211.07:36:31.40#ibcon#about to write, iclass 7, count 0 2006.211.07:36:31.40#ibcon#wrote, iclass 7, count 0 2006.211.07:36:31.40#ibcon#about to read 3, iclass 7, count 0 2006.211.07:36:31.42#ibcon#read 3, iclass 7, count 0 2006.211.07:36:31.42#ibcon#about to read 4, iclass 7, count 0 2006.211.07:36:31.42#ibcon#read 4, iclass 7, count 0 2006.211.07:36:31.42#ibcon#about to read 5, iclass 7, count 0 2006.211.07:36:31.42#ibcon#read 5, iclass 7, count 0 2006.211.07:36:31.42#ibcon#about to read 6, iclass 7, count 0 2006.211.07:36:31.42#ibcon#read 6, iclass 7, count 0 2006.211.07:36:31.42#ibcon#end of sib2, iclass 7, count 0 2006.211.07:36:31.42#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:36:31.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:36:31.42#ibcon#[27=USB\r\n] 2006.211.07:36:31.42#ibcon#*before write, iclass 7, count 0 2006.211.07:36:31.42#ibcon#enter sib2, iclass 7, count 0 2006.211.07:36:31.42#ibcon#flushed, iclass 7, count 0 2006.211.07:36:31.42#ibcon#about to write, iclass 7, count 0 2006.211.07:36:31.42#ibcon#wrote, iclass 7, count 0 2006.211.07:36:31.42#ibcon#about to read 3, iclass 7, count 0 2006.211.07:36:31.45#ibcon#read 3, iclass 7, count 0 2006.211.07:36:31.45#ibcon#about to read 4, iclass 7, count 0 2006.211.07:36:31.45#ibcon#read 4, iclass 7, count 0 2006.211.07:36:31.45#ibcon#about to read 5, iclass 7, count 0 2006.211.07:36:31.45#ibcon#read 5, iclass 7, count 0 2006.211.07:36:31.45#ibcon#about to read 6, iclass 7, count 0 2006.211.07:36:31.45#ibcon#read 6, iclass 7, count 0 2006.211.07:36:31.45#ibcon#end of sib2, iclass 7, count 0 2006.211.07:36:31.45#ibcon#*after write, iclass 7, count 0 2006.211.07:36:31.45#ibcon#*before return 0, iclass 7, count 0 2006.211.07:36:31.45#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:31.45#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:36:31.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:36:31.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:36:31.45$vc4f8/vblo=5,744.99 2006.211.07:36:31.45#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:36:31.45#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:36:31.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:31.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:31.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:31.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:31.45#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:36:31.45#ibcon#first serial, iclass 11, count 0 2006.211.07:36:31.45#ibcon#enter sib2, iclass 11, count 0 2006.211.07:36:31.45#ibcon#flushed, iclass 11, count 0 2006.211.07:36:31.45#ibcon#about to write, iclass 11, count 0 2006.211.07:36:31.45#ibcon#wrote, iclass 11, count 0 2006.211.07:36:31.45#ibcon#about to read 3, iclass 11, count 0 2006.211.07:36:31.47#ibcon#read 3, iclass 11, count 0 2006.211.07:36:31.47#ibcon#about to read 4, iclass 11, count 0 2006.211.07:36:31.47#ibcon#read 4, iclass 11, count 0 2006.211.07:36:31.47#ibcon#about to read 5, iclass 11, count 0 2006.211.07:36:31.47#ibcon#read 5, iclass 11, count 0 2006.211.07:36:31.47#ibcon#about to read 6, iclass 11, count 0 2006.211.07:36:31.47#ibcon#read 6, iclass 11, count 0 2006.211.07:36:31.47#ibcon#end of sib2, iclass 11, count 0 2006.211.07:36:31.47#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:36:31.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:36:31.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:36:31.47#ibcon#*before write, iclass 11, count 0 2006.211.07:36:31.47#ibcon#enter sib2, iclass 11, count 0 2006.211.07:36:31.47#ibcon#flushed, iclass 11, count 0 2006.211.07:36:31.47#ibcon#about to write, iclass 11, count 0 2006.211.07:36:31.47#ibcon#wrote, iclass 11, count 0 2006.211.07:36:31.47#ibcon#about to read 3, iclass 11, count 0 2006.211.07:36:31.51#ibcon#read 3, iclass 11, count 0 2006.211.07:36:31.51#ibcon#about to read 4, iclass 11, count 0 2006.211.07:36:31.51#ibcon#read 4, iclass 11, count 0 2006.211.07:36:31.51#ibcon#about to read 5, iclass 11, count 0 2006.211.07:36:31.51#ibcon#read 5, iclass 11, count 0 2006.211.07:36:31.51#ibcon#about to read 6, iclass 11, count 0 2006.211.07:36:31.51#ibcon#read 6, iclass 11, count 0 2006.211.07:36:31.51#ibcon#end of sib2, iclass 11, count 0 2006.211.07:36:31.51#ibcon#*after write, iclass 11, count 0 2006.211.07:36:31.51#ibcon#*before return 0, iclass 11, count 0 2006.211.07:36:31.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:31.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:36:31.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:36:31.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:36:31.51$vc4f8/vb=5,3 2006.211.07:36:31.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.07:36:31.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.07:36:31.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:31.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:31.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:31.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:31.57#ibcon#enter wrdev, iclass 13, count 2 2006.211.07:36:31.57#ibcon#first serial, iclass 13, count 2 2006.211.07:36:31.57#ibcon#enter sib2, iclass 13, count 2 2006.211.07:36:31.57#ibcon#flushed, iclass 13, count 2 2006.211.07:36:31.57#ibcon#about to write, iclass 13, count 2 2006.211.07:36:31.57#ibcon#wrote, iclass 13, count 2 2006.211.07:36:31.57#ibcon#about to read 3, iclass 13, count 2 2006.211.07:36:31.59#ibcon#read 3, iclass 13, count 2 2006.211.07:36:31.59#ibcon#about to read 4, iclass 13, count 2 2006.211.07:36:31.59#ibcon#read 4, iclass 13, count 2 2006.211.07:36:31.59#ibcon#about to read 5, iclass 13, count 2 2006.211.07:36:31.59#ibcon#read 5, iclass 13, count 2 2006.211.07:36:31.59#ibcon#about to read 6, iclass 13, count 2 2006.211.07:36:31.59#ibcon#read 6, iclass 13, count 2 2006.211.07:36:31.59#ibcon#end of sib2, iclass 13, count 2 2006.211.07:36:31.59#ibcon#*mode == 0, iclass 13, count 2 2006.211.07:36:31.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.07:36:31.59#ibcon#[27=AT05-03\r\n] 2006.211.07:36:31.59#ibcon#*before write, iclass 13, count 2 2006.211.07:36:31.59#ibcon#enter sib2, iclass 13, count 2 2006.211.07:36:31.59#ibcon#flushed, iclass 13, count 2 2006.211.07:36:31.59#ibcon#about to write, iclass 13, count 2 2006.211.07:36:31.59#ibcon#wrote, iclass 13, count 2 2006.211.07:36:31.59#ibcon#about to read 3, iclass 13, count 2 2006.211.07:36:31.62#ibcon#read 3, iclass 13, count 2 2006.211.07:36:31.62#ibcon#about to read 4, iclass 13, count 2 2006.211.07:36:31.62#ibcon#read 4, iclass 13, count 2 2006.211.07:36:31.62#ibcon#about to read 5, iclass 13, count 2 2006.211.07:36:31.62#ibcon#read 5, iclass 13, count 2 2006.211.07:36:31.62#ibcon#about to read 6, iclass 13, count 2 2006.211.07:36:31.62#ibcon#read 6, iclass 13, count 2 2006.211.07:36:31.62#ibcon#end of sib2, iclass 13, count 2 2006.211.07:36:31.62#ibcon#*after write, iclass 13, count 2 2006.211.07:36:31.62#ibcon#*before return 0, iclass 13, count 2 2006.211.07:36:31.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:31.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:36:31.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.07:36:31.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:31.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:31.70#abcon#<5=/04 4.4 9.2 24.99 751010.1\r\n> 2006.211.07:36:31.72#abcon#{5=INTERFACE CLEAR} 2006.211.07:36:31.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:31.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:31.74#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:36:31.74#ibcon#first serial, iclass 13, count 0 2006.211.07:36:31.74#ibcon#enter sib2, iclass 13, count 0 2006.211.07:36:31.74#ibcon#flushed, iclass 13, count 0 2006.211.07:36:31.74#ibcon#about to write, iclass 13, count 0 2006.211.07:36:31.74#ibcon#wrote, iclass 13, count 0 2006.211.07:36:31.74#ibcon#about to read 3, iclass 13, count 0 2006.211.07:36:31.76#ibcon#read 3, iclass 13, count 0 2006.211.07:36:31.76#ibcon#about to read 4, iclass 13, count 0 2006.211.07:36:31.76#ibcon#read 4, iclass 13, count 0 2006.211.07:36:31.76#ibcon#about to read 5, iclass 13, count 0 2006.211.07:36:31.76#ibcon#read 5, iclass 13, count 0 2006.211.07:36:31.76#ibcon#about to read 6, iclass 13, count 0 2006.211.07:36:31.76#ibcon#read 6, iclass 13, count 0 2006.211.07:36:31.76#ibcon#end of sib2, iclass 13, count 0 2006.211.07:36:31.76#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:36:31.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:36:31.76#ibcon#[27=USB\r\n] 2006.211.07:36:31.76#ibcon#*before write, iclass 13, count 0 2006.211.07:36:31.76#ibcon#enter sib2, iclass 13, count 0 2006.211.07:36:31.76#ibcon#flushed, iclass 13, count 0 2006.211.07:36:31.76#ibcon#about to write, iclass 13, count 0 2006.211.07:36:31.76#ibcon#wrote, iclass 13, count 0 2006.211.07:36:31.76#ibcon#about to read 3, iclass 13, count 0 2006.211.07:36:31.78#abcon#[5=S1D000X0/0*\r\n] 2006.211.07:36:31.79#ibcon#read 3, iclass 13, count 0 2006.211.07:36:31.79#ibcon#about to read 4, iclass 13, count 0 2006.211.07:36:31.79#ibcon#read 4, iclass 13, count 0 2006.211.07:36:31.79#ibcon#about to read 5, iclass 13, count 0 2006.211.07:36:31.79#ibcon#read 5, iclass 13, count 0 2006.211.07:36:31.79#ibcon#about to read 6, iclass 13, count 0 2006.211.07:36:31.79#ibcon#read 6, iclass 13, count 0 2006.211.07:36:31.79#ibcon#end of sib2, iclass 13, count 0 2006.211.07:36:31.79#ibcon#*after write, iclass 13, count 0 2006.211.07:36:31.79#ibcon#*before return 0, iclass 13, count 0 2006.211.07:36:31.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:31.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:36:31.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:36:31.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:36:31.79$vc4f8/vblo=6,752.99 2006.211.07:36:31.79#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.07:36:31.79#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.07:36:31.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:36:31.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:31.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:31.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:31.79#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:36:31.79#ibcon#first serial, iclass 19, count 0 2006.211.07:36:31.79#ibcon#enter sib2, iclass 19, count 0 2006.211.07:36:31.79#ibcon#flushed, iclass 19, count 0 2006.211.07:36:31.79#ibcon#about to write, iclass 19, count 0 2006.211.07:36:31.79#ibcon#wrote, iclass 19, count 0 2006.211.07:36:31.79#ibcon#about to read 3, iclass 19, count 0 2006.211.07:36:31.81#ibcon#read 3, iclass 19, count 0 2006.211.07:36:31.81#ibcon#about to read 4, iclass 19, count 0 2006.211.07:36:31.81#ibcon#read 4, iclass 19, count 0 2006.211.07:36:31.81#ibcon#about to read 5, iclass 19, count 0 2006.211.07:36:31.81#ibcon#read 5, iclass 19, count 0 2006.211.07:36:31.81#ibcon#about to read 6, iclass 19, count 0 2006.211.07:36:31.81#ibcon#read 6, iclass 19, count 0 2006.211.07:36:31.81#ibcon#end of sib2, iclass 19, count 0 2006.211.07:36:31.81#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:36:31.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:36:31.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:36:31.81#ibcon#*before write, iclass 19, count 0 2006.211.07:36:31.81#ibcon#enter sib2, iclass 19, count 0 2006.211.07:36:31.81#ibcon#flushed, iclass 19, count 0 2006.211.07:36:31.81#ibcon#about to write, iclass 19, count 0 2006.211.07:36:31.81#ibcon#wrote, iclass 19, count 0 2006.211.07:36:31.81#ibcon#about to read 3, iclass 19, count 0 2006.211.07:36:31.85#ibcon#read 3, iclass 19, count 0 2006.211.07:36:31.85#ibcon#about to read 4, iclass 19, count 0 2006.211.07:36:31.85#ibcon#read 4, iclass 19, count 0 2006.211.07:36:31.85#ibcon#about to read 5, iclass 19, count 0 2006.211.07:36:31.85#ibcon#read 5, iclass 19, count 0 2006.211.07:36:31.85#ibcon#about to read 6, iclass 19, count 0 2006.211.07:36:31.85#ibcon#read 6, iclass 19, count 0 2006.211.07:36:31.85#ibcon#end of sib2, iclass 19, count 0 2006.211.07:36:31.85#ibcon#*after write, iclass 19, count 0 2006.211.07:36:31.85#ibcon#*before return 0, iclass 19, count 0 2006.211.07:36:31.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:31.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:36:31.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:36:31.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:36:31.85$vc4f8/vb=6,3 2006.211.07:36:31.85#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.07:36:31.85#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.07:36:31.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:36:31.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:31.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:31.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:31.91#ibcon#enter wrdev, iclass 21, count 2 2006.211.07:36:31.91#ibcon#first serial, iclass 21, count 2 2006.211.07:36:31.91#ibcon#enter sib2, iclass 21, count 2 2006.211.07:36:31.91#ibcon#flushed, iclass 21, count 2 2006.211.07:36:31.91#ibcon#about to write, iclass 21, count 2 2006.211.07:36:31.91#ibcon#wrote, iclass 21, count 2 2006.211.07:36:31.91#ibcon#about to read 3, iclass 21, count 2 2006.211.07:36:31.93#ibcon#read 3, iclass 21, count 2 2006.211.07:36:31.93#ibcon#about to read 4, iclass 21, count 2 2006.211.07:36:31.93#ibcon#read 4, iclass 21, count 2 2006.211.07:36:31.93#ibcon#about to read 5, iclass 21, count 2 2006.211.07:36:31.93#ibcon#read 5, iclass 21, count 2 2006.211.07:36:31.93#ibcon#about to read 6, iclass 21, count 2 2006.211.07:36:31.93#ibcon#read 6, iclass 21, count 2 2006.211.07:36:31.93#ibcon#end of sib2, iclass 21, count 2 2006.211.07:36:31.93#ibcon#*mode == 0, iclass 21, count 2 2006.211.07:36:31.93#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.07:36:31.93#ibcon#[27=AT06-03\r\n] 2006.211.07:36:31.93#ibcon#*before write, iclass 21, count 2 2006.211.07:36:31.93#ibcon#enter sib2, iclass 21, count 2 2006.211.07:36:31.93#ibcon#flushed, iclass 21, count 2 2006.211.07:36:31.93#ibcon#about to write, iclass 21, count 2 2006.211.07:36:31.93#ibcon#wrote, iclass 21, count 2 2006.211.07:36:31.93#ibcon#about to read 3, iclass 21, count 2 2006.211.07:36:31.96#ibcon#read 3, iclass 21, count 2 2006.211.07:36:31.96#ibcon#about to read 4, iclass 21, count 2 2006.211.07:36:31.96#ibcon#read 4, iclass 21, count 2 2006.211.07:36:31.96#ibcon#about to read 5, iclass 21, count 2 2006.211.07:36:31.96#ibcon#read 5, iclass 21, count 2 2006.211.07:36:31.96#ibcon#about to read 6, iclass 21, count 2 2006.211.07:36:31.96#ibcon#read 6, iclass 21, count 2 2006.211.07:36:31.96#ibcon#end of sib2, iclass 21, count 2 2006.211.07:36:31.96#ibcon#*after write, iclass 21, count 2 2006.211.07:36:31.96#ibcon#*before return 0, iclass 21, count 2 2006.211.07:36:31.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:31.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:36:31.96#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.07:36:31.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:36:31.96#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:32.08#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:32.08#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:32.08#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:36:32.08#ibcon#first serial, iclass 21, count 0 2006.211.07:36:32.08#ibcon#enter sib2, iclass 21, count 0 2006.211.07:36:32.08#ibcon#flushed, iclass 21, count 0 2006.211.07:36:32.08#ibcon#about to write, iclass 21, count 0 2006.211.07:36:32.08#ibcon#wrote, iclass 21, count 0 2006.211.07:36:32.08#ibcon#about to read 3, iclass 21, count 0 2006.211.07:36:32.10#ibcon#read 3, iclass 21, count 0 2006.211.07:36:32.10#ibcon#about to read 4, iclass 21, count 0 2006.211.07:36:32.10#ibcon#read 4, iclass 21, count 0 2006.211.07:36:32.10#ibcon#about to read 5, iclass 21, count 0 2006.211.07:36:32.10#ibcon#read 5, iclass 21, count 0 2006.211.07:36:32.10#ibcon#about to read 6, iclass 21, count 0 2006.211.07:36:32.10#ibcon#read 6, iclass 21, count 0 2006.211.07:36:32.10#ibcon#end of sib2, iclass 21, count 0 2006.211.07:36:32.10#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:36:32.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:36:32.10#ibcon#[27=USB\r\n] 2006.211.07:36:32.10#ibcon#*before write, iclass 21, count 0 2006.211.07:36:32.10#ibcon#enter sib2, iclass 21, count 0 2006.211.07:36:32.10#ibcon#flushed, iclass 21, count 0 2006.211.07:36:32.10#ibcon#about to write, iclass 21, count 0 2006.211.07:36:32.10#ibcon#wrote, iclass 21, count 0 2006.211.07:36:32.10#ibcon#about to read 3, iclass 21, count 0 2006.211.07:36:32.13#ibcon#read 3, iclass 21, count 0 2006.211.07:36:32.13#ibcon#about to read 4, iclass 21, count 0 2006.211.07:36:32.13#ibcon#read 4, iclass 21, count 0 2006.211.07:36:32.13#ibcon#about to read 5, iclass 21, count 0 2006.211.07:36:32.13#ibcon#read 5, iclass 21, count 0 2006.211.07:36:32.13#ibcon#about to read 6, iclass 21, count 0 2006.211.07:36:32.13#ibcon#read 6, iclass 21, count 0 2006.211.07:36:32.13#ibcon#end of sib2, iclass 21, count 0 2006.211.07:36:32.13#ibcon#*after write, iclass 21, count 0 2006.211.07:36:32.13#ibcon#*before return 0, iclass 21, count 0 2006.211.07:36:32.13#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:32.13#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:36:32.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:36:32.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:36:32.13$vc4f8/vabw=wide 2006.211.07:36:32.13#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:36:32.13#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:36:32.13#ibcon#ireg 8 cls_cnt 0 2006.211.07:36:32.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:32.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:32.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:32.13#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:36:32.13#ibcon#first serial, iclass 23, count 0 2006.211.07:36:32.13#ibcon#enter sib2, iclass 23, count 0 2006.211.07:36:32.13#ibcon#flushed, iclass 23, count 0 2006.211.07:36:32.13#ibcon#about to write, iclass 23, count 0 2006.211.07:36:32.13#ibcon#wrote, iclass 23, count 0 2006.211.07:36:32.13#ibcon#about to read 3, iclass 23, count 0 2006.211.07:36:32.15#ibcon#read 3, iclass 23, count 0 2006.211.07:36:32.15#ibcon#about to read 4, iclass 23, count 0 2006.211.07:36:32.15#ibcon#read 4, iclass 23, count 0 2006.211.07:36:32.15#ibcon#about to read 5, iclass 23, count 0 2006.211.07:36:32.15#ibcon#read 5, iclass 23, count 0 2006.211.07:36:32.15#ibcon#about to read 6, iclass 23, count 0 2006.211.07:36:32.15#ibcon#read 6, iclass 23, count 0 2006.211.07:36:32.15#ibcon#end of sib2, iclass 23, count 0 2006.211.07:36:32.15#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:36:32.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:36:32.15#ibcon#[25=BW32\r\n] 2006.211.07:36:32.15#ibcon#*before write, iclass 23, count 0 2006.211.07:36:32.15#ibcon#enter sib2, iclass 23, count 0 2006.211.07:36:32.15#ibcon#flushed, iclass 23, count 0 2006.211.07:36:32.15#ibcon#about to write, iclass 23, count 0 2006.211.07:36:32.15#ibcon#wrote, iclass 23, count 0 2006.211.07:36:32.15#ibcon#about to read 3, iclass 23, count 0 2006.211.07:36:32.18#ibcon#read 3, iclass 23, count 0 2006.211.07:36:32.18#ibcon#about to read 4, iclass 23, count 0 2006.211.07:36:32.18#ibcon#read 4, iclass 23, count 0 2006.211.07:36:32.18#ibcon#about to read 5, iclass 23, count 0 2006.211.07:36:32.18#ibcon#read 5, iclass 23, count 0 2006.211.07:36:32.18#ibcon#about to read 6, iclass 23, count 0 2006.211.07:36:32.18#ibcon#read 6, iclass 23, count 0 2006.211.07:36:32.18#ibcon#end of sib2, iclass 23, count 0 2006.211.07:36:32.18#ibcon#*after write, iclass 23, count 0 2006.211.07:36:32.18#ibcon#*before return 0, iclass 23, count 0 2006.211.07:36:32.18#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:32.18#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:36:32.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:36:32.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:36:32.18$vc4f8/vbbw=wide 2006.211.07:36:32.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:36:32.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:36:32.18#ibcon#ireg 8 cls_cnt 0 2006.211.07:36:32.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:36:32.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:36:32.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:36:32.25#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:36:32.25#ibcon#first serial, iclass 25, count 0 2006.211.07:36:32.25#ibcon#enter sib2, iclass 25, count 0 2006.211.07:36:32.25#ibcon#flushed, iclass 25, count 0 2006.211.07:36:32.25#ibcon#about to write, iclass 25, count 0 2006.211.07:36:32.25#ibcon#wrote, iclass 25, count 0 2006.211.07:36:32.25#ibcon#about to read 3, iclass 25, count 0 2006.211.07:36:32.27#ibcon#read 3, iclass 25, count 0 2006.211.07:36:32.27#ibcon#about to read 4, iclass 25, count 0 2006.211.07:36:32.27#ibcon#read 4, iclass 25, count 0 2006.211.07:36:32.27#ibcon#about to read 5, iclass 25, count 0 2006.211.07:36:32.27#ibcon#read 5, iclass 25, count 0 2006.211.07:36:32.27#ibcon#about to read 6, iclass 25, count 0 2006.211.07:36:32.27#ibcon#read 6, iclass 25, count 0 2006.211.07:36:32.27#ibcon#end of sib2, iclass 25, count 0 2006.211.07:36:32.27#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:36:32.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:36:32.27#ibcon#[27=BW32\r\n] 2006.211.07:36:32.27#ibcon#*before write, iclass 25, count 0 2006.211.07:36:32.27#ibcon#enter sib2, iclass 25, count 0 2006.211.07:36:32.27#ibcon#flushed, iclass 25, count 0 2006.211.07:36:32.27#ibcon#about to write, iclass 25, count 0 2006.211.07:36:32.27#ibcon#wrote, iclass 25, count 0 2006.211.07:36:32.27#ibcon#about to read 3, iclass 25, count 0 2006.211.07:36:32.30#ibcon#read 3, iclass 25, count 0 2006.211.07:36:32.30#ibcon#about to read 4, iclass 25, count 0 2006.211.07:36:32.30#ibcon#read 4, iclass 25, count 0 2006.211.07:36:32.30#ibcon#about to read 5, iclass 25, count 0 2006.211.07:36:32.30#ibcon#read 5, iclass 25, count 0 2006.211.07:36:32.30#ibcon#about to read 6, iclass 25, count 0 2006.211.07:36:32.30#ibcon#read 6, iclass 25, count 0 2006.211.07:36:32.30#ibcon#end of sib2, iclass 25, count 0 2006.211.07:36:32.30#ibcon#*after write, iclass 25, count 0 2006.211.07:36:32.30#ibcon#*before return 0, iclass 25, count 0 2006.211.07:36:32.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:36:32.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:36:32.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:36:32.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:36:32.30$4f8m12a/ifd4f 2006.211.07:36:32.30$ifd4f/lo= 2006.211.07:36:32.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:36:32.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:36:32.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:36:32.30$ifd4f/patch= 2006.211.07:36:32.30$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:36:32.30$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:36:32.30$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:36:32.30$4f8m12a/"form=m,16.000,1:2 2006.211.07:36:32.30$4f8m12a/"tpicd 2006.211.07:36:32.30$4f8m12a/echo=off 2006.211.07:36:32.30$4f8m12a/xlog=off 2006.211.07:36:32.30:!2006.211.07:37:00 2006.211.07:36:42.14#trakl#Source acquired 2006.211.07:36:44.14#flagr#flagr/antenna,acquired 2006.211.07:37:00.00:preob 2006.211.07:37:00.14/onsource/TRACKING 2006.211.07:37:00.14:!2006.211.07:37:10 2006.211.07:37:10.00:data_valid=on 2006.211.07:37:10.00:midob 2006.211.07:37:11.14/onsource/TRACKING 2006.211.07:37:11.14/wx/24.98,1010.1,75 2006.211.07:37:11.31/cable/+6.4376E-03 2006.211.07:37:12.40/va/01,08,usb,yes,29,31 2006.211.07:37:12.40/va/02,07,usb,yes,30,31 2006.211.07:37:12.40/va/03,06,usb,yes,31,31 2006.211.07:37:12.40/va/04,07,usb,yes,30,33 2006.211.07:37:12.40/va/05,07,usb,yes,33,35 2006.211.07:37:12.40/va/06,06,usb,yes,32,32 2006.211.07:37:12.40/va/07,06,usb,yes,33,32 2006.211.07:37:12.40/va/08,07,usb,yes,31,30 2006.211.07:37:12.63/valo/01,532.99,yes,locked 2006.211.07:37:12.63/valo/02,572.99,yes,locked 2006.211.07:37:12.63/valo/03,672.99,yes,locked 2006.211.07:37:12.63/valo/04,832.99,yes,locked 2006.211.07:37:12.63/valo/05,652.99,yes,locked 2006.211.07:37:12.63/valo/06,772.99,yes,locked 2006.211.07:37:12.63/valo/07,832.99,yes,locked 2006.211.07:37:12.63/valo/08,852.99,yes,locked 2006.211.07:37:13.72/vb/01,04,usb,yes,29,28 2006.211.07:37:13.72/vb/02,04,usb,yes,31,32 2006.211.07:37:13.72/vb/03,03,usb,yes,34,38 2006.211.07:37:13.72/vb/04,03,usb,yes,35,35 2006.211.07:37:13.72/vb/05,03,usb,yes,33,38 2006.211.07:37:13.72/vb/06,03,usb,yes,34,37 2006.211.07:37:13.72/vb/07,04,usb,yes,30,29 2006.211.07:37:13.72/vb/08,03,usb,yes,34,38 2006.211.07:37:13.96/vblo/01,632.99,yes,locked 2006.211.07:37:13.96/vblo/02,640.99,yes,locked 2006.211.07:37:13.96/vblo/03,656.99,yes,locked 2006.211.07:37:13.96/vblo/04,712.99,yes,locked 2006.211.07:37:13.96/vblo/05,744.99,yes,locked 2006.211.07:37:13.96/vblo/06,752.99,yes,locked 2006.211.07:37:13.96/vblo/07,734.99,yes,locked 2006.211.07:37:13.96/vblo/08,744.99,yes,locked 2006.211.07:37:14.11/vabw/8 2006.211.07:37:14.26/vbbw/8 2006.211.07:37:14.39/xfe/off,on,12.0 2006.211.07:37:14.77/ifatt/23,28,28,28 2006.211.07:37:15.07/fmout-gps/S +4.49E-07 2006.211.07:37:15.11:!2006.211.07:38:10 2006.211.07:38:10.00:data_valid=off 2006.211.07:38:10.00:postob 2006.211.07:38:10.10/cable/+6.4386E-03 2006.211.07:38:10.10/wx/24.97,1010.1,75 2006.211.07:38:11.07/fmout-gps/S +4.50E-07 2006.211.07:38:11.07:scan_name=211-0739,k06211,60 2006.211.07:38:11.07:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.211.07:38:11.13#flagr#flagr/antenna,new-source 2006.211.07:38:12.13:checkk5 2006.211.07:38:12.44/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:38:12.79/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:38:13.12/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:38:13.46/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:38:13.80/chk_obsdata//k5ts1/T2110737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:38:14.13/chk_obsdata//k5ts2/T2110737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:38:14.47/chk_obsdata//k5ts3/T2110737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:38:14.80/chk_obsdata//k5ts4/T2110737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:38:15.45/k5log//k5ts1_log_newline 2006.211.07:38:16.10/k5log//k5ts2_log_newline 2006.211.07:38:16.75/k5log//k5ts3_log_newline 2006.211.07:38:17.41/k5log//k5ts4_log_newline 2006.211.07:38:17.43/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:38:17.43:4f8m12a=1 2006.211.07:38:17.43$4f8m12a/echo=on 2006.211.07:38:17.43$4f8m12a/pcalon 2006.211.07:38:17.43$pcalon/"no phase cal control is implemented here 2006.211.07:38:17.43$4f8m12a/"tpicd=stop 2006.211.07:38:17.43$4f8m12a/vc4f8 2006.211.07:38:17.43$vc4f8/valo=1,532.99 2006.211.07:38:17.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:38:17.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:38:17.44#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:17.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:17.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:17.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:17.44#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:38:17.44#ibcon#first serial, iclass 32, count 0 2006.211.07:38:17.44#ibcon#enter sib2, iclass 32, count 0 2006.211.07:38:17.44#ibcon#flushed, iclass 32, count 0 2006.211.07:38:17.44#ibcon#about to write, iclass 32, count 0 2006.211.07:38:17.44#ibcon#wrote, iclass 32, count 0 2006.211.07:38:17.44#ibcon#about to read 3, iclass 32, count 0 2006.211.07:38:17.45#ibcon#read 3, iclass 32, count 0 2006.211.07:38:17.45#ibcon#about to read 4, iclass 32, count 0 2006.211.07:38:17.45#ibcon#read 4, iclass 32, count 0 2006.211.07:38:17.45#ibcon#about to read 5, iclass 32, count 0 2006.211.07:38:17.45#ibcon#read 5, iclass 32, count 0 2006.211.07:38:17.45#ibcon#about to read 6, iclass 32, count 0 2006.211.07:38:17.45#ibcon#read 6, iclass 32, count 0 2006.211.07:38:17.45#ibcon#end of sib2, iclass 32, count 0 2006.211.07:38:17.45#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:38:17.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:38:17.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:38:17.45#ibcon#*before write, iclass 32, count 0 2006.211.07:38:17.45#ibcon#enter sib2, iclass 32, count 0 2006.211.07:38:17.45#ibcon#flushed, iclass 32, count 0 2006.211.07:38:17.45#ibcon#about to write, iclass 32, count 0 2006.211.07:38:17.45#ibcon#wrote, iclass 32, count 0 2006.211.07:38:17.45#ibcon#about to read 3, iclass 32, count 0 2006.211.07:38:17.50#ibcon#read 3, iclass 32, count 0 2006.211.07:38:17.50#ibcon#about to read 4, iclass 32, count 0 2006.211.07:38:17.50#ibcon#read 4, iclass 32, count 0 2006.211.07:38:17.50#ibcon#about to read 5, iclass 32, count 0 2006.211.07:38:17.50#ibcon#read 5, iclass 32, count 0 2006.211.07:38:17.50#ibcon#about to read 6, iclass 32, count 0 2006.211.07:38:17.50#ibcon#read 6, iclass 32, count 0 2006.211.07:38:17.50#ibcon#end of sib2, iclass 32, count 0 2006.211.07:38:17.50#ibcon#*after write, iclass 32, count 0 2006.211.07:38:17.50#ibcon#*before return 0, iclass 32, count 0 2006.211.07:38:17.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:17.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:17.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:38:17.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:38:17.50$vc4f8/va=1,8 2006.211.07:38:17.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:38:17.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:38:17.50#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:17.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:17.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:17.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:17.50#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:38:17.50#ibcon#first serial, iclass 34, count 2 2006.211.07:38:17.50#ibcon#enter sib2, iclass 34, count 2 2006.211.07:38:17.50#ibcon#flushed, iclass 34, count 2 2006.211.07:38:17.50#ibcon#about to write, iclass 34, count 2 2006.211.07:38:17.50#ibcon#wrote, iclass 34, count 2 2006.211.07:38:17.50#ibcon#about to read 3, iclass 34, count 2 2006.211.07:38:17.52#ibcon#read 3, iclass 34, count 2 2006.211.07:38:17.52#ibcon#about to read 4, iclass 34, count 2 2006.211.07:38:17.52#ibcon#read 4, iclass 34, count 2 2006.211.07:38:17.52#ibcon#about to read 5, iclass 34, count 2 2006.211.07:38:17.52#ibcon#read 5, iclass 34, count 2 2006.211.07:38:17.52#ibcon#about to read 6, iclass 34, count 2 2006.211.07:38:17.52#ibcon#read 6, iclass 34, count 2 2006.211.07:38:17.52#ibcon#end of sib2, iclass 34, count 2 2006.211.07:38:17.52#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:38:17.52#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:38:17.52#ibcon#[25=AT01-08\r\n] 2006.211.07:38:17.52#ibcon#*before write, iclass 34, count 2 2006.211.07:38:17.52#ibcon#enter sib2, iclass 34, count 2 2006.211.07:38:17.52#ibcon#flushed, iclass 34, count 2 2006.211.07:38:17.52#ibcon#about to write, iclass 34, count 2 2006.211.07:38:17.52#ibcon#wrote, iclass 34, count 2 2006.211.07:38:17.52#ibcon#about to read 3, iclass 34, count 2 2006.211.07:38:17.55#ibcon#read 3, iclass 34, count 2 2006.211.07:38:17.55#ibcon#about to read 4, iclass 34, count 2 2006.211.07:38:17.55#ibcon#read 4, iclass 34, count 2 2006.211.07:38:17.55#ibcon#about to read 5, iclass 34, count 2 2006.211.07:38:17.55#ibcon#read 5, iclass 34, count 2 2006.211.07:38:17.55#ibcon#about to read 6, iclass 34, count 2 2006.211.07:38:17.55#ibcon#read 6, iclass 34, count 2 2006.211.07:38:17.55#ibcon#end of sib2, iclass 34, count 2 2006.211.07:38:17.55#ibcon#*after write, iclass 34, count 2 2006.211.07:38:17.55#ibcon#*before return 0, iclass 34, count 2 2006.211.07:38:17.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:17.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:17.55#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:38:17.55#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:17.55#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:17.67#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:17.67#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:17.67#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:38:17.67#ibcon#first serial, iclass 34, count 0 2006.211.07:38:17.67#ibcon#enter sib2, iclass 34, count 0 2006.211.07:38:17.67#ibcon#flushed, iclass 34, count 0 2006.211.07:38:17.67#ibcon#about to write, iclass 34, count 0 2006.211.07:38:17.67#ibcon#wrote, iclass 34, count 0 2006.211.07:38:17.67#ibcon#about to read 3, iclass 34, count 0 2006.211.07:38:17.69#ibcon#read 3, iclass 34, count 0 2006.211.07:38:17.69#ibcon#about to read 4, iclass 34, count 0 2006.211.07:38:17.69#ibcon#read 4, iclass 34, count 0 2006.211.07:38:17.69#ibcon#about to read 5, iclass 34, count 0 2006.211.07:38:17.69#ibcon#read 5, iclass 34, count 0 2006.211.07:38:17.69#ibcon#about to read 6, iclass 34, count 0 2006.211.07:38:17.69#ibcon#read 6, iclass 34, count 0 2006.211.07:38:17.69#ibcon#end of sib2, iclass 34, count 0 2006.211.07:38:17.69#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:38:17.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:38:17.69#ibcon#[25=USB\r\n] 2006.211.07:38:17.69#ibcon#*before write, iclass 34, count 0 2006.211.07:38:17.69#ibcon#enter sib2, iclass 34, count 0 2006.211.07:38:17.69#ibcon#flushed, iclass 34, count 0 2006.211.07:38:17.69#ibcon#about to write, iclass 34, count 0 2006.211.07:38:17.69#ibcon#wrote, iclass 34, count 0 2006.211.07:38:17.69#ibcon#about to read 3, iclass 34, count 0 2006.211.07:38:17.72#ibcon#read 3, iclass 34, count 0 2006.211.07:38:17.72#ibcon#about to read 4, iclass 34, count 0 2006.211.07:38:17.72#ibcon#read 4, iclass 34, count 0 2006.211.07:38:17.72#ibcon#about to read 5, iclass 34, count 0 2006.211.07:38:17.72#ibcon#read 5, iclass 34, count 0 2006.211.07:38:17.72#ibcon#about to read 6, iclass 34, count 0 2006.211.07:38:17.72#ibcon#read 6, iclass 34, count 0 2006.211.07:38:17.72#ibcon#end of sib2, iclass 34, count 0 2006.211.07:38:17.72#ibcon#*after write, iclass 34, count 0 2006.211.07:38:17.72#ibcon#*before return 0, iclass 34, count 0 2006.211.07:38:17.72#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:17.72#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:17.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:38:17.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:38:17.72$vc4f8/valo=2,572.99 2006.211.07:38:17.72#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.07:38:17.72#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.07:38:17.72#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:17.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:17.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:17.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:17.72#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:38:17.72#ibcon#first serial, iclass 36, count 0 2006.211.07:38:17.72#ibcon#enter sib2, iclass 36, count 0 2006.211.07:38:17.72#ibcon#flushed, iclass 36, count 0 2006.211.07:38:17.72#ibcon#about to write, iclass 36, count 0 2006.211.07:38:17.72#ibcon#wrote, iclass 36, count 0 2006.211.07:38:17.72#ibcon#about to read 3, iclass 36, count 0 2006.211.07:38:17.74#ibcon#read 3, iclass 36, count 0 2006.211.07:38:17.74#ibcon#about to read 4, iclass 36, count 0 2006.211.07:38:17.74#ibcon#read 4, iclass 36, count 0 2006.211.07:38:17.74#ibcon#about to read 5, iclass 36, count 0 2006.211.07:38:17.74#ibcon#read 5, iclass 36, count 0 2006.211.07:38:17.74#ibcon#about to read 6, iclass 36, count 0 2006.211.07:38:17.74#ibcon#read 6, iclass 36, count 0 2006.211.07:38:17.74#ibcon#end of sib2, iclass 36, count 0 2006.211.07:38:17.74#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:38:17.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:38:17.74#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:38:17.74#ibcon#*before write, iclass 36, count 0 2006.211.07:38:17.74#ibcon#enter sib2, iclass 36, count 0 2006.211.07:38:17.74#ibcon#flushed, iclass 36, count 0 2006.211.07:38:17.74#ibcon#about to write, iclass 36, count 0 2006.211.07:38:17.74#ibcon#wrote, iclass 36, count 0 2006.211.07:38:17.74#ibcon#about to read 3, iclass 36, count 0 2006.211.07:38:17.78#ibcon#read 3, iclass 36, count 0 2006.211.07:38:17.78#ibcon#about to read 4, iclass 36, count 0 2006.211.07:38:17.78#ibcon#read 4, iclass 36, count 0 2006.211.07:38:17.78#ibcon#about to read 5, iclass 36, count 0 2006.211.07:38:17.78#ibcon#read 5, iclass 36, count 0 2006.211.07:38:17.78#ibcon#about to read 6, iclass 36, count 0 2006.211.07:38:17.78#ibcon#read 6, iclass 36, count 0 2006.211.07:38:17.78#ibcon#end of sib2, iclass 36, count 0 2006.211.07:38:17.78#ibcon#*after write, iclass 36, count 0 2006.211.07:38:17.78#ibcon#*before return 0, iclass 36, count 0 2006.211.07:38:17.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:17.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:17.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:38:17.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:38:17.78$vc4f8/va=2,7 2006.211.07:38:17.78#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.07:38:17.78#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.07:38:17.78#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:17.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:17.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:17.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:17.84#ibcon#enter wrdev, iclass 38, count 2 2006.211.07:38:17.84#ibcon#first serial, iclass 38, count 2 2006.211.07:38:17.84#ibcon#enter sib2, iclass 38, count 2 2006.211.07:38:17.84#ibcon#flushed, iclass 38, count 2 2006.211.07:38:17.84#ibcon#about to write, iclass 38, count 2 2006.211.07:38:17.84#ibcon#wrote, iclass 38, count 2 2006.211.07:38:17.84#ibcon#about to read 3, iclass 38, count 2 2006.211.07:38:17.86#ibcon#read 3, iclass 38, count 2 2006.211.07:38:17.86#ibcon#about to read 4, iclass 38, count 2 2006.211.07:38:17.86#ibcon#read 4, iclass 38, count 2 2006.211.07:38:17.86#ibcon#about to read 5, iclass 38, count 2 2006.211.07:38:17.86#ibcon#read 5, iclass 38, count 2 2006.211.07:38:17.86#ibcon#about to read 6, iclass 38, count 2 2006.211.07:38:17.86#ibcon#read 6, iclass 38, count 2 2006.211.07:38:17.86#ibcon#end of sib2, iclass 38, count 2 2006.211.07:38:17.86#ibcon#*mode == 0, iclass 38, count 2 2006.211.07:38:17.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.07:38:17.86#ibcon#[25=AT02-07\r\n] 2006.211.07:38:17.86#ibcon#*before write, iclass 38, count 2 2006.211.07:38:17.86#ibcon#enter sib2, iclass 38, count 2 2006.211.07:38:17.86#ibcon#flushed, iclass 38, count 2 2006.211.07:38:17.86#ibcon#about to write, iclass 38, count 2 2006.211.07:38:17.86#ibcon#wrote, iclass 38, count 2 2006.211.07:38:17.86#ibcon#about to read 3, iclass 38, count 2 2006.211.07:38:17.89#ibcon#read 3, iclass 38, count 2 2006.211.07:38:17.89#ibcon#about to read 4, iclass 38, count 2 2006.211.07:38:17.89#ibcon#read 4, iclass 38, count 2 2006.211.07:38:17.89#ibcon#about to read 5, iclass 38, count 2 2006.211.07:38:17.89#ibcon#read 5, iclass 38, count 2 2006.211.07:38:17.89#ibcon#about to read 6, iclass 38, count 2 2006.211.07:38:17.89#ibcon#read 6, iclass 38, count 2 2006.211.07:38:17.89#ibcon#end of sib2, iclass 38, count 2 2006.211.07:38:17.89#ibcon#*after write, iclass 38, count 2 2006.211.07:38:17.89#ibcon#*before return 0, iclass 38, count 2 2006.211.07:38:17.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:17.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:17.89#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.07:38:17.89#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:17.89#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:18.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:18.01#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:18.01#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:38:18.01#ibcon#first serial, iclass 38, count 0 2006.211.07:38:18.01#ibcon#enter sib2, iclass 38, count 0 2006.211.07:38:18.01#ibcon#flushed, iclass 38, count 0 2006.211.07:38:18.01#ibcon#about to write, iclass 38, count 0 2006.211.07:38:18.01#ibcon#wrote, iclass 38, count 0 2006.211.07:38:18.01#ibcon#about to read 3, iclass 38, count 0 2006.211.07:38:18.03#ibcon#read 3, iclass 38, count 0 2006.211.07:38:18.03#ibcon#about to read 4, iclass 38, count 0 2006.211.07:38:18.03#ibcon#read 4, iclass 38, count 0 2006.211.07:38:18.03#ibcon#about to read 5, iclass 38, count 0 2006.211.07:38:18.03#ibcon#read 5, iclass 38, count 0 2006.211.07:38:18.03#ibcon#about to read 6, iclass 38, count 0 2006.211.07:38:18.03#ibcon#read 6, iclass 38, count 0 2006.211.07:38:18.03#ibcon#end of sib2, iclass 38, count 0 2006.211.07:38:18.03#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:38:18.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:38:18.03#ibcon#[25=USB\r\n] 2006.211.07:38:18.03#ibcon#*before write, iclass 38, count 0 2006.211.07:38:18.03#ibcon#enter sib2, iclass 38, count 0 2006.211.07:38:18.03#ibcon#flushed, iclass 38, count 0 2006.211.07:38:18.03#ibcon#about to write, iclass 38, count 0 2006.211.07:38:18.03#ibcon#wrote, iclass 38, count 0 2006.211.07:38:18.03#ibcon#about to read 3, iclass 38, count 0 2006.211.07:38:18.06#ibcon#read 3, iclass 38, count 0 2006.211.07:38:18.06#ibcon#about to read 4, iclass 38, count 0 2006.211.07:38:18.06#ibcon#read 4, iclass 38, count 0 2006.211.07:38:18.06#ibcon#about to read 5, iclass 38, count 0 2006.211.07:38:18.06#ibcon#read 5, iclass 38, count 0 2006.211.07:38:18.06#ibcon#about to read 6, iclass 38, count 0 2006.211.07:38:18.06#ibcon#read 6, iclass 38, count 0 2006.211.07:38:18.06#ibcon#end of sib2, iclass 38, count 0 2006.211.07:38:18.06#ibcon#*after write, iclass 38, count 0 2006.211.07:38:18.06#ibcon#*before return 0, iclass 38, count 0 2006.211.07:38:18.06#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:18.06#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:18.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:38:18.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:38:18.06$vc4f8/valo=3,672.99 2006.211.07:38:18.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:38:18.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:38:18.06#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:18.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:18.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:18.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:18.06#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:38:18.06#ibcon#first serial, iclass 40, count 0 2006.211.07:38:18.06#ibcon#enter sib2, iclass 40, count 0 2006.211.07:38:18.06#ibcon#flushed, iclass 40, count 0 2006.211.07:38:18.06#ibcon#about to write, iclass 40, count 0 2006.211.07:38:18.06#ibcon#wrote, iclass 40, count 0 2006.211.07:38:18.06#ibcon#about to read 3, iclass 40, count 0 2006.211.07:38:18.08#ibcon#read 3, iclass 40, count 0 2006.211.07:38:18.08#ibcon#about to read 4, iclass 40, count 0 2006.211.07:38:18.08#ibcon#read 4, iclass 40, count 0 2006.211.07:38:18.08#ibcon#about to read 5, iclass 40, count 0 2006.211.07:38:18.08#ibcon#read 5, iclass 40, count 0 2006.211.07:38:18.08#ibcon#about to read 6, iclass 40, count 0 2006.211.07:38:18.08#ibcon#read 6, iclass 40, count 0 2006.211.07:38:18.08#ibcon#end of sib2, iclass 40, count 0 2006.211.07:38:18.08#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:38:18.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:38:18.08#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:38:18.08#ibcon#*before write, iclass 40, count 0 2006.211.07:38:18.08#ibcon#enter sib2, iclass 40, count 0 2006.211.07:38:18.08#ibcon#flushed, iclass 40, count 0 2006.211.07:38:18.08#ibcon#about to write, iclass 40, count 0 2006.211.07:38:18.08#ibcon#wrote, iclass 40, count 0 2006.211.07:38:18.08#ibcon#about to read 3, iclass 40, count 0 2006.211.07:38:18.12#ibcon#read 3, iclass 40, count 0 2006.211.07:38:18.12#ibcon#about to read 4, iclass 40, count 0 2006.211.07:38:18.12#ibcon#read 4, iclass 40, count 0 2006.211.07:38:18.12#ibcon#about to read 5, iclass 40, count 0 2006.211.07:38:18.12#ibcon#read 5, iclass 40, count 0 2006.211.07:38:18.12#ibcon#about to read 6, iclass 40, count 0 2006.211.07:38:18.12#ibcon#read 6, iclass 40, count 0 2006.211.07:38:18.12#ibcon#end of sib2, iclass 40, count 0 2006.211.07:38:18.12#ibcon#*after write, iclass 40, count 0 2006.211.07:38:18.12#ibcon#*before return 0, iclass 40, count 0 2006.211.07:38:18.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:18.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:18.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:38:18.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:38:18.12$vc4f8/va=3,6 2006.211.07:38:18.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:38:18.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:38:18.12#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:18.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:18.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:18.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:18.18#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:38:18.18#ibcon#first serial, iclass 4, count 2 2006.211.07:38:18.18#ibcon#enter sib2, iclass 4, count 2 2006.211.07:38:18.18#ibcon#flushed, iclass 4, count 2 2006.211.07:38:18.18#ibcon#about to write, iclass 4, count 2 2006.211.07:38:18.18#ibcon#wrote, iclass 4, count 2 2006.211.07:38:18.18#ibcon#about to read 3, iclass 4, count 2 2006.211.07:38:18.20#ibcon#read 3, iclass 4, count 2 2006.211.07:38:18.20#ibcon#about to read 4, iclass 4, count 2 2006.211.07:38:18.20#ibcon#read 4, iclass 4, count 2 2006.211.07:38:18.20#ibcon#about to read 5, iclass 4, count 2 2006.211.07:38:18.20#ibcon#read 5, iclass 4, count 2 2006.211.07:38:18.20#ibcon#about to read 6, iclass 4, count 2 2006.211.07:38:18.20#ibcon#read 6, iclass 4, count 2 2006.211.07:38:18.20#ibcon#end of sib2, iclass 4, count 2 2006.211.07:38:18.20#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:38:18.20#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:38:18.20#ibcon#[25=AT03-06\r\n] 2006.211.07:38:18.20#ibcon#*before write, iclass 4, count 2 2006.211.07:38:18.20#ibcon#enter sib2, iclass 4, count 2 2006.211.07:38:18.20#ibcon#flushed, iclass 4, count 2 2006.211.07:38:18.20#ibcon#about to write, iclass 4, count 2 2006.211.07:38:18.20#ibcon#wrote, iclass 4, count 2 2006.211.07:38:18.20#ibcon#about to read 3, iclass 4, count 2 2006.211.07:38:18.23#ibcon#read 3, iclass 4, count 2 2006.211.07:38:18.23#ibcon#about to read 4, iclass 4, count 2 2006.211.07:38:18.23#ibcon#read 4, iclass 4, count 2 2006.211.07:38:18.23#ibcon#about to read 5, iclass 4, count 2 2006.211.07:38:18.23#ibcon#read 5, iclass 4, count 2 2006.211.07:38:18.23#ibcon#about to read 6, iclass 4, count 2 2006.211.07:38:18.23#ibcon#read 6, iclass 4, count 2 2006.211.07:38:18.23#ibcon#end of sib2, iclass 4, count 2 2006.211.07:38:18.23#ibcon#*after write, iclass 4, count 2 2006.211.07:38:18.23#ibcon#*before return 0, iclass 4, count 2 2006.211.07:38:18.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:18.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:18.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:38:18.23#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:18.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:18.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:18.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:18.35#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:38:18.35#ibcon#first serial, iclass 4, count 0 2006.211.07:38:18.35#ibcon#enter sib2, iclass 4, count 0 2006.211.07:38:18.35#ibcon#flushed, iclass 4, count 0 2006.211.07:38:18.35#ibcon#about to write, iclass 4, count 0 2006.211.07:38:18.35#ibcon#wrote, iclass 4, count 0 2006.211.07:38:18.35#ibcon#about to read 3, iclass 4, count 0 2006.211.07:38:18.37#ibcon#read 3, iclass 4, count 0 2006.211.07:38:18.37#ibcon#about to read 4, iclass 4, count 0 2006.211.07:38:18.37#ibcon#read 4, iclass 4, count 0 2006.211.07:38:18.37#ibcon#about to read 5, iclass 4, count 0 2006.211.07:38:18.37#ibcon#read 5, iclass 4, count 0 2006.211.07:38:18.37#ibcon#about to read 6, iclass 4, count 0 2006.211.07:38:18.37#ibcon#read 6, iclass 4, count 0 2006.211.07:38:18.37#ibcon#end of sib2, iclass 4, count 0 2006.211.07:38:18.37#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:38:18.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:38:18.37#ibcon#[25=USB\r\n] 2006.211.07:38:18.37#ibcon#*before write, iclass 4, count 0 2006.211.07:38:18.37#ibcon#enter sib2, iclass 4, count 0 2006.211.07:38:18.37#ibcon#flushed, iclass 4, count 0 2006.211.07:38:18.37#ibcon#about to write, iclass 4, count 0 2006.211.07:38:18.37#ibcon#wrote, iclass 4, count 0 2006.211.07:38:18.37#ibcon#about to read 3, iclass 4, count 0 2006.211.07:38:18.40#ibcon#read 3, iclass 4, count 0 2006.211.07:38:18.40#ibcon#about to read 4, iclass 4, count 0 2006.211.07:38:18.40#ibcon#read 4, iclass 4, count 0 2006.211.07:38:18.40#ibcon#about to read 5, iclass 4, count 0 2006.211.07:38:18.40#ibcon#read 5, iclass 4, count 0 2006.211.07:38:18.40#ibcon#about to read 6, iclass 4, count 0 2006.211.07:38:18.40#ibcon#read 6, iclass 4, count 0 2006.211.07:38:18.40#ibcon#end of sib2, iclass 4, count 0 2006.211.07:38:18.40#ibcon#*after write, iclass 4, count 0 2006.211.07:38:18.40#ibcon#*before return 0, iclass 4, count 0 2006.211.07:38:18.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:18.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:18.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:38:18.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:38:18.40$vc4f8/valo=4,832.99 2006.211.07:38:18.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:38:18.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:38:18.40#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:18.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:18.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:18.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:18.40#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:38:18.40#ibcon#first serial, iclass 6, count 0 2006.211.07:38:18.40#ibcon#enter sib2, iclass 6, count 0 2006.211.07:38:18.40#ibcon#flushed, iclass 6, count 0 2006.211.07:38:18.40#ibcon#about to write, iclass 6, count 0 2006.211.07:38:18.40#ibcon#wrote, iclass 6, count 0 2006.211.07:38:18.40#ibcon#about to read 3, iclass 6, count 0 2006.211.07:38:18.42#ibcon#read 3, iclass 6, count 0 2006.211.07:38:18.42#ibcon#about to read 4, iclass 6, count 0 2006.211.07:38:18.42#ibcon#read 4, iclass 6, count 0 2006.211.07:38:18.42#ibcon#about to read 5, iclass 6, count 0 2006.211.07:38:18.42#ibcon#read 5, iclass 6, count 0 2006.211.07:38:18.42#ibcon#about to read 6, iclass 6, count 0 2006.211.07:38:18.42#ibcon#read 6, iclass 6, count 0 2006.211.07:38:18.42#ibcon#end of sib2, iclass 6, count 0 2006.211.07:38:18.42#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:38:18.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:38:18.42#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:38:18.42#ibcon#*before write, iclass 6, count 0 2006.211.07:38:18.42#ibcon#enter sib2, iclass 6, count 0 2006.211.07:38:18.42#ibcon#flushed, iclass 6, count 0 2006.211.07:38:18.42#ibcon#about to write, iclass 6, count 0 2006.211.07:38:18.42#ibcon#wrote, iclass 6, count 0 2006.211.07:38:18.42#ibcon#about to read 3, iclass 6, count 0 2006.211.07:38:18.46#ibcon#read 3, iclass 6, count 0 2006.211.07:38:18.46#ibcon#about to read 4, iclass 6, count 0 2006.211.07:38:18.46#ibcon#read 4, iclass 6, count 0 2006.211.07:38:18.46#ibcon#about to read 5, iclass 6, count 0 2006.211.07:38:18.46#ibcon#read 5, iclass 6, count 0 2006.211.07:38:18.46#ibcon#about to read 6, iclass 6, count 0 2006.211.07:38:18.46#ibcon#read 6, iclass 6, count 0 2006.211.07:38:18.46#ibcon#end of sib2, iclass 6, count 0 2006.211.07:38:18.46#ibcon#*after write, iclass 6, count 0 2006.211.07:38:18.46#ibcon#*before return 0, iclass 6, count 0 2006.211.07:38:18.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:18.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:18.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:38:18.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:38:18.46$vc4f8/va=4,7 2006.211.07:38:18.46#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:38:18.46#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:38:18.46#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:18.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:18.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:18.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:18.52#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:38:18.52#ibcon#first serial, iclass 10, count 2 2006.211.07:38:18.52#ibcon#enter sib2, iclass 10, count 2 2006.211.07:38:18.52#ibcon#flushed, iclass 10, count 2 2006.211.07:38:18.52#ibcon#about to write, iclass 10, count 2 2006.211.07:38:18.52#ibcon#wrote, iclass 10, count 2 2006.211.07:38:18.52#ibcon#about to read 3, iclass 10, count 2 2006.211.07:38:18.54#ibcon#read 3, iclass 10, count 2 2006.211.07:38:18.54#ibcon#about to read 4, iclass 10, count 2 2006.211.07:38:18.54#ibcon#read 4, iclass 10, count 2 2006.211.07:38:18.54#ibcon#about to read 5, iclass 10, count 2 2006.211.07:38:18.54#ibcon#read 5, iclass 10, count 2 2006.211.07:38:18.54#ibcon#about to read 6, iclass 10, count 2 2006.211.07:38:18.54#ibcon#read 6, iclass 10, count 2 2006.211.07:38:18.54#ibcon#end of sib2, iclass 10, count 2 2006.211.07:38:18.54#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:38:18.54#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:38:18.54#ibcon#[25=AT04-07\r\n] 2006.211.07:38:18.54#ibcon#*before write, iclass 10, count 2 2006.211.07:38:18.54#ibcon#enter sib2, iclass 10, count 2 2006.211.07:38:18.54#ibcon#flushed, iclass 10, count 2 2006.211.07:38:18.54#ibcon#about to write, iclass 10, count 2 2006.211.07:38:18.54#ibcon#wrote, iclass 10, count 2 2006.211.07:38:18.54#ibcon#about to read 3, iclass 10, count 2 2006.211.07:38:18.57#ibcon#read 3, iclass 10, count 2 2006.211.07:38:18.57#ibcon#about to read 4, iclass 10, count 2 2006.211.07:38:18.57#ibcon#read 4, iclass 10, count 2 2006.211.07:38:18.57#ibcon#about to read 5, iclass 10, count 2 2006.211.07:38:18.57#ibcon#read 5, iclass 10, count 2 2006.211.07:38:18.57#ibcon#about to read 6, iclass 10, count 2 2006.211.07:38:18.57#ibcon#read 6, iclass 10, count 2 2006.211.07:38:18.57#ibcon#end of sib2, iclass 10, count 2 2006.211.07:38:18.57#ibcon#*after write, iclass 10, count 2 2006.211.07:38:18.57#ibcon#*before return 0, iclass 10, count 2 2006.211.07:38:18.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:18.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:18.57#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:38:18.57#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:18.57#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:18.69#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:18.69#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:18.69#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:38:18.69#ibcon#first serial, iclass 10, count 0 2006.211.07:38:18.69#ibcon#enter sib2, iclass 10, count 0 2006.211.07:38:18.69#ibcon#flushed, iclass 10, count 0 2006.211.07:38:18.69#ibcon#about to write, iclass 10, count 0 2006.211.07:38:18.69#ibcon#wrote, iclass 10, count 0 2006.211.07:38:18.69#ibcon#about to read 3, iclass 10, count 0 2006.211.07:38:18.71#ibcon#read 3, iclass 10, count 0 2006.211.07:38:18.71#ibcon#about to read 4, iclass 10, count 0 2006.211.07:38:18.71#ibcon#read 4, iclass 10, count 0 2006.211.07:38:18.71#ibcon#about to read 5, iclass 10, count 0 2006.211.07:38:18.71#ibcon#read 5, iclass 10, count 0 2006.211.07:38:18.71#ibcon#about to read 6, iclass 10, count 0 2006.211.07:38:18.71#ibcon#read 6, iclass 10, count 0 2006.211.07:38:18.71#ibcon#end of sib2, iclass 10, count 0 2006.211.07:38:18.71#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:38:18.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:38:18.71#ibcon#[25=USB\r\n] 2006.211.07:38:18.71#ibcon#*before write, iclass 10, count 0 2006.211.07:38:18.71#ibcon#enter sib2, iclass 10, count 0 2006.211.07:38:18.71#ibcon#flushed, iclass 10, count 0 2006.211.07:38:18.71#ibcon#about to write, iclass 10, count 0 2006.211.07:38:18.71#ibcon#wrote, iclass 10, count 0 2006.211.07:38:18.71#ibcon#about to read 3, iclass 10, count 0 2006.211.07:38:18.74#ibcon#read 3, iclass 10, count 0 2006.211.07:38:18.74#ibcon#about to read 4, iclass 10, count 0 2006.211.07:38:18.74#ibcon#read 4, iclass 10, count 0 2006.211.07:38:18.74#ibcon#about to read 5, iclass 10, count 0 2006.211.07:38:18.74#ibcon#read 5, iclass 10, count 0 2006.211.07:38:18.74#ibcon#about to read 6, iclass 10, count 0 2006.211.07:38:18.74#ibcon#read 6, iclass 10, count 0 2006.211.07:38:18.74#ibcon#end of sib2, iclass 10, count 0 2006.211.07:38:18.74#ibcon#*after write, iclass 10, count 0 2006.211.07:38:18.74#ibcon#*before return 0, iclass 10, count 0 2006.211.07:38:18.74#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:18.74#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:18.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:38:18.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:38:18.74$vc4f8/valo=5,652.99 2006.211.07:38:18.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:38:18.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:38:18.74#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:18.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:18.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:18.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:18.74#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:38:18.74#ibcon#first serial, iclass 12, count 0 2006.211.07:38:18.74#ibcon#enter sib2, iclass 12, count 0 2006.211.07:38:18.74#ibcon#flushed, iclass 12, count 0 2006.211.07:38:18.74#ibcon#about to write, iclass 12, count 0 2006.211.07:38:18.74#ibcon#wrote, iclass 12, count 0 2006.211.07:38:18.74#ibcon#about to read 3, iclass 12, count 0 2006.211.07:38:18.76#ibcon#read 3, iclass 12, count 0 2006.211.07:38:18.76#ibcon#about to read 4, iclass 12, count 0 2006.211.07:38:18.76#ibcon#read 4, iclass 12, count 0 2006.211.07:38:18.76#ibcon#about to read 5, iclass 12, count 0 2006.211.07:38:18.76#ibcon#read 5, iclass 12, count 0 2006.211.07:38:18.76#ibcon#about to read 6, iclass 12, count 0 2006.211.07:38:18.76#ibcon#read 6, iclass 12, count 0 2006.211.07:38:18.76#ibcon#end of sib2, iclass 12, count 0 2006.211.07:38:18.76#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:38:18.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:38:18.76#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:38:18.76#ibcon#*before write, iclass 12, count 0 2006.211.07:38:18.76#ibcon#enter sib2, iclass 12, count 0 2006.211.07:38:18.76#ibcon#flushed, iclass 12, count 0 2006.211.07:38:18.76#ibcon#about to write, iclass 12, count 0 2006.211.07:38:18.76#ibcon#wrote, iclass 12, count 0 2006.211.07:38:18.76#ibcon#about to read 3, iclass 12, count 0 2006.211.07:38:18.80#ibcon#read 3, iclass 12, count 0 2006.211.07:38:18.80#ibcon#about to read 4, iclass 12, count 0 2006.211.07:38:18.80#ibcon#read 4, iclass 12, count 0 2006.211.07:38:18.80#ibcon#about to read 5, iclass 12, count 0 2006.211.07:38:18.80#ibcon#read 5, iclass 12, count 0 2006.211.07:38:18.80#ibcon#about to read 6, iclass 12, count 0 2006.211.07:38:18.80#ibcon#read 6, iclass 12, count 0 2006.211.07:38:18.80#ibcon#end of sib2, iclass 12, count 0 2006.211.07:38:18.80#ibcon#*after write, iclass 12, count 0 2006.211.07:38:18.80#ibcon#*before return 0, iclass 12, count 0 2006.211.07:38:18.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:18.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:18.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:38:18.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:38:18.80$vc4f8/va=5,7 2006.211.07:38:18.80#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:38:18.80#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:38:18.80#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:18.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:18.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:18.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:18.86#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:38:18.86#ibcon#first serial, iclass 14, count 2 2006.211.07:38:18.86#ibcon#enter sib2, iclass 14, count 2 2006.211.07:38:18.86#ibcon#flushed, iclass 14, count 2 2006.211.07:38:18.86#ibcon#about to write, iclass 14, count 2 2006.211.07:38:18.86#ibcon#wrote, iclass 14, count 2 2006.211.07:38:18.86#ibcon#about to read 3, iclass 14, count 2 2006.211.07:38:18.88#ibcon#read 3, iclass 14, count 2 2006.211.07:38:18.88#ibcon#about to read 4, iclass 14, count 2 2006.211.07:38:18.88#ibcon#read 4, iclass 14, count 2 2006.211.07:38:18.88#ibcon#about to read 5, iclass 14, count 2 2006.211.07:38:18.88#ibcon#read 5, iclass 14, count 2 2006.211.07:38:18.88#ibcon#about to read 6, iclass 14, count 2 2006.211.07:38:18.88#ibcon#read 6, iclass 14, count 2 2006.211.07:38:18.88#ibcon#end of sib2, iclass 14, count 2 2006.211.07:38:18.88#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:38:18.88#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:38:18.88#ibcon#[25=AT05-07\r\n] 2006.211.07:38:18.88#ibcon#*before write, iclass 14, count 2 2006.211.07:38:18.88#ibcon#enter sib2, iclass 14, count 2 2006.211.07:38:18.88#ibcon#flushed, iclass 14, count 2 2006.211.07:38:18.88#ibcon#about to write, iclass 14, count 2 2006.211.07:38:18.88#ibcon#wrote, iclass 14, count 2 2006.211.07:38:18.88#ibcon#about to read 3, iclass 14, count 2 2006.211.07:38:18.91#ibcon#read 3, iclass 14, count 2 2006.211.07:38:18.91#ibcon#about to read 4, iclass 14, count 2 2006.211.07:38:18.91#ibcon#read 4, iclass 14, count 2 2006.211.07:38:18.91#ibcon#about to read 5, iclass 14, count 2 2006.211.07:38:18.91#ibcon#read 5, iclass 14, count 2 2006.211.07:38:18.91#ibcon#about to read 6, iclass 14, count 2 2006.211.07:38:18.91#ibcon#read 6, iclass 14, count 2 2006.211.07:38:18.91#ibcon#end of sib2, iclass 14, count 2 2006.211.07:38:18.91#ibcon#*after write, iclass 14, count 2 2006.211.07:38:18.91#ibcon#*before return 0, iclass 14, count 2 2006.211.07:38:18.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:18.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:18.91#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:38:18.91#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:18.91#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:19.03#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:19.03#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:19.03#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:38:19.03#ibcon#first serial, iclass 14, count 0 2006.211.07:38:19.03#ibcon#enter sib2, iclass 14, count 0 2006.211.07:38:19.03#ibcon#flushed, iclass 14, count 0 2006.211.07:38:19.03#ibcon#about to write, iclass 14, count 0 2006.211.07:38:19.03#ibcon#wrote, iclass 14, count 0 2006.211.07:38:19.03#ibcon#about to read 3, iclass 14, count 0 2006.211.07:38:19.05#ibcon#read 3, iclass 14, count 0 2006.211.07:38:19.05#ibcon#about to read 4, iclass 14, count 0 2006.211.07:38:19.05#ibcon#read 4, iclass 14, count 0 2006.211.07:38:19.05#ibcon#about to read 5, iclass 14, count 0 2006.211.07:38:19.05#ibcon#read 5, iclass 14, count 0 2006.211.07:38:19.05#ibcon#about to read 6, iclass 14, count 0 2006.211.07:38:19.05#ibcon#read 6, iclass 14, count 0 2006.211.07:38:19.05#ibcon#end of sib2, iclass 14, count 0 2006.211.07:38:19.05#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:38:19.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:38:19.05#ibcon#[25=USB\r\n] 2006.211.07:38:19.05#ibcon#*before write, iclass 14, count 0 2006.211.07:38:19.05#ibcon#enter sib2, iclass 14, count 0 2006.211.07:38:19.05#ibcon#flushed, iclass 14, count 0 2006.211.07:38:19.05#ibcon#about to write, iclass 14, count 0 2006.211.07:38:19.05#ibcon#wrote, iclass 14, count 0 2006.211.07:38:19.05#ibcon#about to read 3, iclass 14, count 0 2006.211.07:38:19.08#ibcon#read 3, iclass 14, count 0 2006.211.07:38:19.08#ibcon#about to read 4, iclass 14, count 0 2006.211.07:38:19.08#ibcon#read 4, iclass 14, count 0 2006.211.07:38:19.08#ibcon#about to read 5, iclass 14, count 0 2006.211.07:38:19.08#ibcon#read 5, iclass 14, count 0 2006.211.07:38:19.08#ibcon#about to read 6, iclass 14, count 0 2006.211.07:38:19.08#ibcon#read 6, iclass 14, count 0 2006.211.07:38:19.08#ibcon#end of sib2, iclass 14, count 0 2006.211.07:38:19.08#ibcon#*after write, iclass 14, count 0 2006.211.07:38:19.08#ibcon#*before return 0, iclass 14, count 0 2006.211.07:38:19.08#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:19.08#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:19.08#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:38:19.08#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:38:19.08$vc4f8/valo=6,772.99 2006.211.07:38:19.08#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:38:19.08#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:38:19.08#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:19.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:19.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:19.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:19.08#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:38:19.08#ibcon#first serial, iclass 16, count 0 2006.211.07:38:19.08#ibcon#enter sib2, iclass 16, count 0 2006.211.07:38:19.08#ibcon#flushed, iclass 16, count 0 2006.211.07:38:19.08#ibcon#about to write, iclass 16, count 0 2006.211.07:38:19.08#ibcon#wrote, iclass 16, count 0 2006.211.07:38:19.08#ibcon#about to read 3, iclass 16, count 0 2006.211.07:38:19.10#ibcon#read 3, iclass 16, count 0 2006.211.07:38:19.10#ibcon#about to read 4, iclass 16, count 0 2006.211.07:38:19.10#ibcon#read 4, iclass 16, count 0 2006.211.07:38:19.10#ibcon#about to read 5, iclass 16, count 0 2006.211.07:38:19.10#ibcon#read 5, iclass 16, count 0 2006.211.07:38:19.10#ibcon#about to read 6, iclass 16, count 0 2006.211.07:38:19.10#ibcon#read 6, iclass 16, count 0 2006.211.07:38:19.10#ibcon#end of sib2, iclass 16, count 0 2006.211.07:38:19.10#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:38:19.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:38:19.10#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:38:19.10#ibcon#*before write, iclass 16, count 0 2006.211.07:38:19.10#ibcon#enter sib2, iclass 16, count 0 2006.211.07:38:19.10#ibcon#flushed, iclass 16, count 0 2006.211.07:38:19.10#ibcon#about to write, iclass 16, count 0 2006.211.07:38:19.10#ibcon#wrote, iclass 16, count 0 2006.211.07:38:19.10#ibcon#about to read 3, iclass 16, count 0 2006.211.07:38:19.14#ibcon#read 3, iclass 16, count 0 2006.211.07:38:19.14#ibcon#about to read 4, iclass 16, count 0 2006.211.07:38:19.14#ibcon#read 4, iclass 16, count 0 2006.211.07:38:19.14#ibcon#about to read 5, iclass 16, count 0 2006.211.07:38:19.14#ibcon#read 5, iclass 16, count 0 2006.211.07:38:19.14#ibcon#about to read 6, iclass 16, count 0 2006.211.07:38:19.14#ibcon#read 6, iclass 16, count 0 2006.211.07:38:19.14#ibcon#end of sib2, iclass 16, count 0 2006.211.07:38:19.14#ibcon#*after write, iclass 16, count 0 2006.211.07:38:19.14#ibcon#*before return 0, iclass 16, count 0 2006.211.07:38:19.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:19.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:19.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:38:19.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:38:19.14$vc4f8/va=6,6 2006.211.07:38:19.14#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.07:38:19.14#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.07:38:19.14#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:19.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:38:19.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:38:19.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:38:19.20#ibcon#enter wrdev, iclass 18, count 2 2006.211.07:38:19.20#ibcon#first serial, iclass 18, count 2 2006.211.07:38:19.20#ibcon#enter sib2, iclass 18, count 2 2006.211.07:38:19.20#ibcon#flushed, iclass 18, count 2 2006.211.07:38:19.20#ibcon#about to write, iclass 18, count 2 2006.211.07:38:19.20#ibcon#wrote, iclass 18, count 2 2006.211.07:38:19.20#ibcon#about to read 3, iclass 18, count 2 2006.211.07:38:19.22#ibcon#read 3, iclass 18, count 2 2006.211.07:38:19.22#ibcon#about to read 4, iclass 18, count 2 2006.211.07:38:19.22#ibcon#read 4, iclass 18, count 2 2006.211.07:38:19.22#ibcon#about to read 5, iclass 18, count 2 2006.211.07:38:19.22#ibcon#read 5, iclass 18, count 2 2006.211.07:38:19.22#ibcon#about to read 6, iclass 18, count 2 2006.211.07:38:19.22#ibcon#read 6, iclass 18, count 2 2006.211.07:38:19.22#ibcon#end of sib2, iclass 18, count 2 2006.211.07:38:19.22#ibcon#*mode == 0, iclass 18, count 2 2006.211.07:38:19.22#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.07:38:19.22#ibcon#[25=AT06-06\r\n] 2006.211.07:38:19.22#ibcon#*before write, iclass 18, count 2 2006.211.07:38:19.22#ibcon#enter sib2, iclass 18, count 2 2006.211.07:38:19.22#ibcon#flushed, iclass 18, count 2 2006.211.07:38:19.22#ibcon#about to write, iclass 18, count 2 2006.211.07:38:19.22#ibcon#wrote, iclass 18, count 2 2006.211.07:38:19.22#ibcon#about to read 3, iclass 18, count 2 2006.211.07:38:19.25#ibcon#read 3, iclass 18, count 2 2006.211.07:38:19.25#ibcon#about to read 4, iclass 18, count 2 2006.211.07:38:19.25#ibcon#read 4, iclass 18, count 2 2006.211.07:38:19.25#ibcon#about to read 5, iclass 18, count 2 2006.211.07:38:19.25#ibcon#read 5, iclass 18, count 2 2006.211.07:38:19.25#ibcon#about to read 6, iclass 18, count 2 2006.211.07:38:19.25#ibcon#read 6, iclass 18, count 2 2006.211.07:38:19.25#ibcon#end of sib2, iclass 18, count 2 2006.211.07:38:19.25#ibcon#*after write, iclass 18, count 2 2006.211.07:38:19.25#ibcon#*before return 0, iclass 18, count 2 2006.211.07:38:19.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:38:19.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:38:19.25#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.07:38:19.25#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:19.25#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:38:19.37#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:38:19.37#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:38:19.37#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:38:19.37#ibcon#first serial, iclass 18, count 0 2006.211.07:38:19.37#ibcon#enter sib2, iclass 18, count 0 2006.211.07:38:19.37#ibcon#flushed, iclass 18, count 0 2006.211.07:38:19.37#ibcon#about to write, iclass 18, count 0 2006.211.07:38:19.37#ibcon#wrote, iclass 18, count 0 2006.211.07:38:19.37#ibcon#about to read 3, iclass 18, count 0 2006.211.07:38:19.39#ibcon#read 3, iclass 18, count 0 2006.211.07:38:19.39#ibcon#about to read 4, iclass 18, count 0 2006.211.07:38:19.39#ibcon#read 4, iclass 18, count 0 2006.211.07:38:19.39#ibcon#about to read 5, iclass 18, count 0 2006.211.07:38:19.39#ibcon#read 5, iclass 18, count 0 2006.211.07:38:19.39#ibcon#about to read 6, iclass 18, count 0 2006.211.07:38:19.39#ibcon#read 6, iclass 18, count 0 2006.211.07:38:19.39#ibcon#end of sib2, iclass 18, count 0 2006.211.07:38:19.39#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:38:19.39#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:38:19.39#ibcon#[25=USB\r\n] 2006.211.07:38:19.39#ibcon#*before write, iclass 18, count 0 2006.211.07:38:19.39#ibcon#enter sib2, iclass 18, count 0 2006.211.07:38:19.39#ibcon#flushed, iclass 18, count 0 2006.211.07:38:19.39#ibcon#about to write, iclass 18, count 0 2006.211.07:38:19.39#ibcon#wrote, iclass 18, count 0 2006.211.07:38:19.39#ibcon#about to read 3, iclass 18, count 0 2006.211.07:38:19.42#ibcon#read 3, iclass 18, count 0 2006.211.07:38:19.42#ibcon#about to read 4, iclass 18, count 0 2006.211.07:38:19.42#ibcon#read 4, iclass 18, count 0 2006.211.07:38:19.42#ibcon#about to read 5, iclass 18, count 0 2006.211.07:38:19.42#ibcon#read 5, iclass 18, count 0 2006.211.07:38:19.42#ibcon#about to read 6, iclass 18, count 0 2006.211.07:38:19.42#ibcon#read 6, iclass 18, count 0 2006.211.07:38:19.42#ibcon#end of sib2, iclass 18, count 0 2006.211.07:38:19.42#ibcon#*after write, iclass 18, count 0 2006.211.07:38:19.42#ibcon#*before return 0, iclass 18, count 0 2006.211.07:38:19.42#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:38:19.42#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:38:19.42#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:38:19.42#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:38:19.42$vc4f8/valo=7,832.99 2006.211.07:38:19.42#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.07:38:19.42#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.07:38:19.42#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:19.42#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:38:19.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:38:19.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:38:19.42#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:38:19.42#ibcon#first serial, iclass 20, count 0 2006.211.07:38:19.42#ibcon#enter sib2, iclass 20, count 0 2006.211.07:38:19.42#ibcon#flushed, iclass 20, count 0 2006.211.07:38:19.42#ibcon#about to write, iclass 20, count 0 2006.211.07:38:19.42#ibcon#wrote, iclass 20, count 0 2006.211.07:38:19.42#ibcon#about to read 3, iclass 20, count 0 2006.211.07:38:19.44#ibcon#read 3, iclass 20, count 0 2006.211.07:38:19.44#ibcon#about to read 4, iclass 20, count 0 2006.211.07:38:19.44#ibcon#read 4, iclass 20, count 0 2006.211.07:38:19.44#ibcon#about to read 5, iclass 20, count 0 2006.211.07:38:19.44#ibcon#read 5, iclass 20, count 0 2006.211.07:38:19.44#ibcon#about to read 6, iclass 20, count 0 2006.211.07:38:19.44#ibcon#read 6, iclass 20, count 0 2006.211.07:38:19.44#ibcon#end of sib2, iclass 20, count 0 2006.211.07:38:19.44#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:38:19.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:38:19.44#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:38:19.44#ibcon#*before write, iclass 20, count 0 2006.211.07:38:19.44#ibcon#enter sib2, iclass 20, count 0 2006.211.07:38:19.44#ibcon#flushed, iclass 20, count 0 2006.211.07:38:19.44#ibcon#about to write, iclass 20, count 0 2006.211.07:38:19.44#ibcon#wrote, iclass 20, count 0 2006.211.07:38:19.44#ibcon#about to read 3, iclass 20, count 0 2006.211.07:38:19.48#ibcon#read 3, iclass 20, count 0 2006.211.07:38:19.48#ibcon#about to read 4, iclass 20, count 0 2006.211.07:38:19.48#ibcon#read 4, iclass 20, count 0 2006.211.07:38:19.48#ibcon#about to read 5, iclass 20, count 0 2006.211.07:38:19.48#ibcon#read 5, iclass 20, count 0 2006.211.07:38:19.48#ibcon#about to read 6, iclass 20, count 0 2006.211.07:38:19.48#ibcon#read 6, iclass 20, count 0 2006.211.07:38:19.48#ibcon#end of sib2, iclass 20, count 0 2006.211.07:38:19.48#ibcon#*after write, iclass 20, count 0 2006.211.07:38:19.48#ibcon#*before return 0, iclass 20, count 0 2006.211.07:38:19.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:38:19.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:38:19.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:38:19.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:38:19.48$vc4f8/va=7,6 2006.211.07:38:19.48#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.07:38:19.48#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.07:38:19.48#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:19.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:38:19.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:38:19.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:38:19.54#ibcon#enter wrdev, iclass 22, count 2 2006.211.07:38:19.54#ibcon#first serial, iclass 22, count 2 2006.211.07:38:19.54#ibcon#enter sib2, iclass 22, count 2 2006.211.07:38:19.54#ibcon#flushed, iclass 22, count 2 2006.211.07:38:19.54#ibcon#about to write, iclass 22, count 2 2006.211.07:38:19.54#ibcon#wrote, iclass 22, count 2 2006.211.07:38:19.54#ibcon#about to read 3, iclass 22, count 2 2006.211.07:38:19.56#ibcon#read 3, iclass 22, count 2 2006.211.07:38:19.56#ibcon#about to read 4, iclass 22, count 2 2006.211.07:38:19.56#ibcon#read 4, iclass 22, count 2 2006.211.07:38:19.56#ibcon#about to read 5, iclass 22, count 2 2006.211.07:38:19.56#ibcon#read 5, iclass 22, count 2 2006.211.07:38:19.56#ibcon#about to read 6, iclass 22, count 2 2006.211.07:38:19.56#ibcon#read 6, iclass 22, count 2 2006.211.07:38:19.56#ibcon#end of sib2, iclass 22, count 2 2006.211.07:38:19.56#ibcon#*mode == 0, iclass 22, count 2 2006.211.07:38:19.56#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.07:38:19.56#ibcon#[25=AT07-06\r\n] 2006.211.07:38:19.56#ibcon#*before write, iclass 22, count 2 2006.211.07:38:19.56#ibcon#enter sib2, iclass 22, count 2 2006.211.07:38:19.56#ibcon#flushed, iclass 22, count 2 2006.211.07:38:19.56#ibcon#about to write, iclass 22, count 2 2006.211.07:38:19.56#ibcon#wrote, iclass 22, count 2 2006.211.07:38:19.56#ibcon#about to read 3, iclass 22, count 2 2006.211.07:38:19.59#ibcon#read 3, iclass 22, count 2 2006.211.07:38:19.59#ibcon#about to read 4, iclass 22, count 2 2006.211.07:38:19.59#ibcon#read 4, iclass 22, count 2 2006.211.07:38:19.59#ibcon#about to read 5, iclass 22, count 2 2006.211.07:38:19.59#ibcon#read 5, iclass 22, count 2 2006.211.07:38:19.59#ibcon#about to read 6, iclass 22, count 2 2006.211.07:38:19.59#ibcon#read 6, iclass 22, count 2 2006.211.07:38:19.59#ibcon#end of sib2, iclass 22, count 2 2006.211.07:38:19.59#ibcon#*after write, iclass 22, count 2 2006.211.07:38:19.59#ibcon#*before return 0, iclass 22, count 2 2006.211.07:38:19.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:38:19.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:38:19.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.07:38:19.59#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:19.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:38:19.71#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:38:19.71#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:38:19.71#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:38:19.71#ibcon#first serial, iclass 22, count 0 2006.211.07:38:19.71#ibcon#enter sib2, iclass 22, count 0 2006.211.07:38:19.71#ibcon#flushed, iclass 22, count 0 2006.211.07:38:19.71#ibcon#about to write, iclass 22, count 0 2006.211.07:38:19.71#ibcon#wrote, iclass 22, count 0 2006.211.07:38:19.71#ibcon#about to read 3, iclass 22, count 0 2006.211.07:38:19.73#ibcon#read 3, iclass 22, count 0 2006.211.07:38:19.73#ibcon#about to read 4, iclass 22, count 0 2006.211.07:38:19.73#ibcon#read 4, iclass 22, count 0 2006.211.07:38:19.73#ibcon#about to read 5, iclass 22, count 0 2006.211.07:38:19.73#ibcon#read 5, iclass 22, count 0 2006.211.07:38:19.73#ibcon#about to read 6, iclass 22, count 0 2006.211.07:38:19.73#ibcon#read 6, iclass 22, count 0 2006.211.07:38:19.73#ibcon#end of sib2, iclass 22, count 0 2006.211.07:38:19.73#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:38:19.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:38:19.73#ibcon#[25=USB\r\n] 2006.211.07:38:19.73#ibcon#*before write, iclass 22, count 0 2006.211.07:38:19.73#ibcon#enter sib2, iclass 22, count 0 2006.211.07:38:19.73#ibcon#flushed, iclass 22, count 0 2006.211.07:38:19.73#ibcon#about to write, iclass 22, count 0 2006.211.07:38:19.73#ibcon#wrote, iclass 22, count 0 2006.211.07:38:19.73#ibcon#about to read 3, iclass 22, count 0 2006.211.07:38:19.76#ibcon#read 3, iclass 22, count 0 2006.211.07:38:19.76#ibcon#about to read 4, iclass 22, count 0 2006.211.07:38:19.76#ibcon#read 4, iclass 22, count 0 2006.211.07:38:19.76#ibcon#about to read 5, iclass 22, count 0 2006.211.07:38:19.76#ibcon#read 5, iclass 22, count 0 2006.211.07:38:19.76#ibcon#about to read 6, iclass 22, count 0 2006.211.07:38:19.76#ibcon#read 6, iclass 22, count 0 2006.211.07:38:19.76#ibcon#end of sib2, iclass 22, count 0 2006.211.07:38:19.76#ibcon#*after write, iclass 22, count 0 2006.211.07:38:19.76#ibcon#*before return 0, iclass 22, count 0 2006.211.07:38:19.76#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:38:19.76#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:38:19.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:38:19.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:38:19.76$vc4f8/valo=8,852.99 2006.211.07:38:19.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.07:38:19.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.07:38:19.76#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:19.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:38:19.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:38:19.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:38:19.76#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:38:19.76#ibcon#first serial, iclass 24, count 0 2006.211.07:38:19.76#ibcon#enter sib2, iclass 24, count 0 2006.211.07:38:19.76#ibcon#flushed, iclass 24, count 0 2006.211.07:38:19.76#ibcon#about to write, iclass 24, count 0 2006.211.07:38:19.76#ibcon#wrote, iclass 24, count 0 2006.211.07:38:19.76#ibcon#about to read 3, iclass 24, count 0 2006.211.07:38:19.78#ibcon#read 3, iclass 24, count 0 2006.211.07:38:19.78#ibcon#about to read 4, iclass 24, count 0 2006.211.07:38:19.78#ibcon#read 4, iclass 24, count 0 2006.211.07:38:19.78#ibcon#about to read 5, iclass 24, count 0 2006.211.07:38:19.78#ibcon#read 5, iclass 24, count 0 2006.211.07:38:19.78#ibcon#about to read 6, iclass 24, count 0 2006.211.07:38:19.78#ibcon#read 6, iclass 24, count 0 2006.211.07:38:19.78#ibcon#end of sib2, iclass 24, count 0 2006.211.07:38:19.78#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:38:19.78#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:38:19.78#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:38:19.78#ibcon#*before write, iclass 24, count 0 2006.211.07:38:19.78#ibcon#enter sib2, iclass 24, count 0 2006.211.07:38:19.78#ibcon#flushed, iclass 24, count 0 2006.211.07:38:19.78#ibcon#about to write, iclass 24, count 0 2006.211.07:38:19.78#ibcon#wrote, iclass 24, count 0 2006.211.07:38:19.78#ibcon#about to read 3, iclass 24, count 0 2006.211.07:38:19.82#ibcon#read 3, iclass 24, count 0 2006.211.07:38:19.82#ibcon#about to read 4, iclass 24, count 0 2006.211.07:38:19.82#ibcon#read 4, iclass 24, count 0 2006.211.07:38:19.82#ibcon#about to read 5, iclass 24, count 0 2006.211.07:38:19.82#ibcon#read 5, iclass 24, count 0 2006.211.07:38:19.82#ibcon#about to read 6, iclass 24, count 0 2006.211.07:38:19.82#ibcon#read 6, iclass 24, count 0 2006.211.07:38:19.82#ibcon#end of sib2, iclass 24, count 0 2006.211.07:38:19.82#ibcon#*after write, iclass 24, count 0 2006.211.07:38:19.82#ibcon#*before return 0, iclass 24, count 0 2006.211.07:38:19.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:38:19.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:38:19.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:38:19.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:38:19.82$vc4f8/va=8,7 2006.211.07:38:19.82#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.07:38:19.82#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.07:38:19.82#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:19.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:38:19.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:38:19.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:38:19.88#ibcon#enter wrdev, iclass 26, count 2 2006.211.07:38:19.88#ibcon#first serial, iclass 26, count 2 2006.211.07:38:19.88#ibcon#enter sib2, iclass 26, count 2 2006.211.07:38:19.88#ibcon#flushed, iclass 26, count 2 2006.211.07:38:19.88#ibcon#about to write, iclass 26, count 2 2006.211.07:38:19.88#ibcon#wrote, iclass 26, count 2 2006.211.07:38:19.88#ibcon#about to read 3, iclass 26, count 2 2006.211.07:38:19.90#ibcon#read 3, iclass 26, count 2 2006.211.07:38:19.90#ibcon#about to read 4, iclass 26, count 2 2006.211.07:38:19.90#ibcon#read 4, iclass 26, count 2 2006.211.07:38:19.90#ibcon#about to read 5, iclass 26, count 2 2006.211.07:38:19.90#ibcon#read 5, iclass 26, count 2 2006.211.07:38:19.90#ibcon#about to read 6, iclass 26, count 2 2006.211.07:38:19.90#ibcon#read 6, iclass 26, count 2 2006.211.07:38:19.90#ibcon#end of sib2, iclass 26, count 2 2006.211.07:38:19.90#ibcon#*mode == 0, iclass 26, count 2 2006.211.07:38:19.90#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.07:38:19.90#ibcon#[25=AT08-07\r\n] 2006.211.07:38:19.90#ibcon#*before write, iclass 26, count 2 2006.211.07:38:19.90#ibcon#enter sib2, iclass 26, count 2 2006.211.07:38:19.90#ibcon#flushed, iclass 26, count 2 2006.211.07:38:19.90#ibcon#about to write, iclass 26, count 2 2006.211.07:38:19.90#ibcon#wrote, iclass 26, count 2 2006.211.07:38:19.90#ibcon#about to read 3, iclass 26, count 2 2006.211.07:38:19.93#ibcon#read 3, iclass 26, count 2 2006.211.07:38:19.93#ibcon#about to read 4, iclass 26, count 2 2006.211.07:38:19.93#ibcon#read 4, iclass 26, count 2 2006.211.07:38:19.93#ibcon#about to read 5, iclass 26, count 2 2006.211.07:38:19.93#ibcon#read 5, iclass 26, count 2 2006.211.07:38:19.93#ibcon#about to read 6, iclass 26, count 2 2006.211.07:38:19.93#ibcon#read 6, iclass 26, count 2 2006.211.07:38:19.93#ibcon#end of sib2, iclass 26, count 2 2006.211.07:38:19.93#ibcon#*after write, iclass 26, count 2 2006.211.07:38:19.93#ibcon#*before return 0, iclass 26, count 2 2006.211.07:38:19.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:38:19.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:38:19.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.07:38:19.93#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:19.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:38:20.05#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:38:20.05#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:38:20.05#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:38:20.05#ibcon#first serial, iclass 26, count 0 2006.211.07:38:20.05#ibcon#enter sib2, iclass 26, count 0 2006.211.07:38:20.05#ibcon#flushed, iclass 26, count 0 2006.211.07:38:20.05#ibcon#about to write, iclass 26, count 0 2006.211.07:38:20.05#ibcon#wrote, iclass 26, count 0 2006.211.07:38:20.05#ibcon#about to read 3, iclass 26, count 0 2006.211.07:38:20.07#ibcon#read 3, iclass 26, count 0 2006.211.07:38:20.07#ibcon#about to read 4, iclass 26, count 0 2006.211.07:38:20.07#ibcon#read 4, iclass 26, count 0 2006.211.07:38:20.07#ibcon#about to read 5, iclass 26, count 0 2006.211.07:38:20.07#ibcon#read 5, iclass 26, count 0 2006.211.07:38:20.07#ibcon#about to read 6, iclass 26, count 0 2006.211.07:38:20.07#ibcon#read 6, iclass 26, count 0 2006.211.07:38:20.07#ibcon#end of sib2, iclass 26, count 0 2006.211.07:38:20.07#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:38:20.07#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:38:20.07#ibcon#[25=USB\r\n] 2006.211.07:38:20.07#ibcon#*before write, iclass 26, count 0 2006.211.07:38:20.07#ibcon#enter sib2, iclass 26, count 0 2006.211.07:38:20.07#ibcon#flushed, iclass 26, count 0 2006.211.07:38:20.07#ibcon#about to write, iclass 26, count 0 2006.211.07:38:20.07#ibcon#wrote, iclass 26, count 0 2006.211.07:38:20.07#ibcon#about to read 3, iclass 26, count 0 2006.211.07:38:20.10#ibcon#read 3, iclass 26, count 0 2006.211.07:38:20.10#ibcon#about to read 4, iclass 26, count 0 2006.211.07:38:20.10#ibcon#read 4, iclass 26, count 0 2006.211.07:38:20.10#ibcon#about to read 5, iclass 26, count 0 2006.211.07:38:20.10#ibcon#read 5, iclass 26, count 0 2006.211.07:38:20.10#ibcon#about to read 6, iclass 26, count 0 2006.211.07:38:20.10#ibcon#read 6, iclass 26, count 0 2006.211.07:38:20.10#ibcon#end of sib2, iclass 26, count 0 2006.211.07:38:20.10#ibcon#*after write, iclass 26, count 0 2006.211.07:38:20.10#ibcon#*before return 0, iclass 26, count 0 2006.211.07:38:20.10#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:38:20.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:38:20.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:38:20.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:38:20.10$vc4f8/vblo=1,632.99 2006.211.07:38:20.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.07:38:20.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.07:38:20.10#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:20.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:38:20.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:38:20.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:38:20.10#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:38:20.10#ibcon#first serial, iclass 28, count 0 2006.211.07:38:20.10#ibcon#enter sib2, iclass 28, count 0 2006.211.07:38:20.10#ibcon#flushed, iclass 28, count 0 2006.211.07:38:20.10#ibcon#about to write, iclass 28, count 0 2006.211.07:38:20.10#ibcon#wrote, iclass 28, count 0 2006.211.07:38:20.10#ibcon#about to read 3, iclass 28, count 0 2006.211.07:38:20.12#ibcon#read 3, iclass 28, count 0 2006.211.07:38:20.12#ibcon#about to read 4, iclass 28, count 0 2006.211.07:38:20.12#ibcon#read 4, iclass 28, count 0 2006.211.07:38:20.12#ibcon#about to read 5, iclass 28, count 0 2006.211.07:38:20.12#ibcon#read 5, iclass 28, count 0 2006.211.07:38:20.12#ibcon#about to read 6, iclass 28, count 0 2006.211.07:38:20.12#ibcon#read 6, iclass 28, count 0 2006.211.07:38:20.12#ibcon#end of sib2, iclass 28, count 0 2006.211.07:38:20.12#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:38:20.12#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:38:20.12#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:38:20.12#ibcon#*before write, iclass 28, count 0 2006.211.07:38:20.12#ibcon#enter sib2, iclass 28, count 0 2006.211.07:38:20.12#ibcon#flushed, iclass 28, count 0 2006.211.07:38:20.12#ibcon#about to write, iclass 28, count 0 2006.211.07:38:20.12#ibcon#wrote, iclass 28, count 0 2006.211.07:38:20.12#ibcon#about to read 3, iclass 28, count 0 2006.211.07:38:20.16#ibcon#read 3, iclass 28, count 0 2006.211.07:38:20.16#ibcon#about to read 4, iclass 28, count 0 2006.211.07:38:20.16#ibcon#read 4, iclass 28, count 0 2006.211.07:38:20.16#ibcon#about to read 5, iclass 28, count 0 2006.211.07:38:20.16#ibcon#read 5, iclass 28, count 0 2006.211.07:38:20.16#ibcon#about to read 6, iclass 28, count 0 2006.211.07:38:20.16#ibcon#read 6, iclass 28, count 0 2006.211.07:38:20.16#ibcon#end of sib2, iclass 28, count 0 2006.211.07:38:20.16#ibcon#*after write, iclass 28, count 0 2006.211.07:38:20.16#ibcon#*before return 0, iclass 28, count 0 2006.211.07:38:20.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:38:20.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:38:20.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:38:20.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:38:20.16$vc4f8/vb=1,4 2006.211.07:38:20.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.07:38:20.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.07:38:20.16#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:20.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:38:20.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:38:20.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:38:20.16#ibcon#enter wrdev, iclass 30, count 2 2006.211.07:38:20.16#ibcon#first serial, iclass 30, count 2 2006.211.07:38:20.16#ibcon#enter sib2, iclass 30, count 2 2006.211.07:38:20.16#ibcon#flushed, iclass 30, count 2 2006.211.07:38:20.16#ibcon#about to write, iclass 30, count 2 2006.211.07:38:20.16#ibcon#wrote, iclass 30, count 2 2006.211.07:38:20.16#ibcon#about to read 3, iclass 30, count 2 2006.211.07:38:20.18#ibcon#read 3, iclass 30, count 2 2006.211.07:38:20.18#ibcon#about to read 4, iclass 30, count 2 2006.211.07:38:20.18#ibcon#read 4, iclass 30, count 2 2006.211.07:38:20.18#ibcon#about to read 5, iclass 30, count 2 2006.211.07:38:20.18#ibcon#read 5, iclass 30, count 2 2006.211.07:38:20.18#ibcon#about to read 6, iclass 30, count 2 2006.211.07:38:20.18#ibcon#read 6, iclass 30, count 2 2006.211.07:38:20.18#ibcon#end of sib2, iclass 30, count 2 2006.211.07:38:20.18#ibcon#*mode == 0, iclass 30, count 2 2006.211.07:38:20.18#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.07:38:20.18#ibcon#[27=AT01-04\r\n] 2006.211.07:38:20.18#ibcon#*before write, iclass 30, count 2 2006.211.07:38:20.18#ibcon#enter sib2, iclass 30, count 2 2006.211.07:38:20.18#ibcon#flushed, iclass 30, count 2 2006.211.07:38:20.18#ibcon#about to write, iclass 30, count 2 2006.211.07:38:20.18#ibcon#wrote, iclass 30, count 2 2006.211.07:38:20.18#ibcon#about to read 3, iclass 30, count 2 2006.211.07:38:20.21#ibcon#read 3, iclass 30, count 2 2006.211.07:38:20.21#ibcon#about to read 4, iclass 30, count 2 2006.211.07:38:20.21#ibcon#read 4, iclass 30, count 2 2006.211.07:38:20.21#ibcon#about to read 5, iclass 30, count 2 2006.211.07:38:20.21#ibcon#read 5, iclass 30, count 2 2006.211.07:38:20.21#ibcon#about to read 6, iclass 30, count 2 2006.211.07:38:20.21#ibcon#read 6, iclass 30, count 2 2006.211.07:38:20.21#ibcon#end of sib2, iclass 30, count 2 2006.211.07:38:20.21#ibcon#*after write, iclass 30, count 2 2006.211.07:38:20.21#ibcon#*before return 0, iclass 30, count 2 2006.211.07:38:20.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:38:20.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:38:20.21#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.07:38:20.21#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:20.21#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:38:20.33#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:38:20.33#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:38:20.33#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:38:20.33#ibcon#first serial, iclass 30, count 0 2006.211.07:38:20.33#ibcon#enter sib2, iclass 30, count 0 2006.211.07:38:20.33#ibcon#flushed, iclass 30, count 0 2006.211.07:38:20.33#ibcon#about to write, iclass 30, count 0 2006.211.07:38:20.33#ibcon#wrote, iclass 30, count 0 2006.211.07:38:20.33#ibcon#about to read 3, iclass 30, count 0 2006.211.07:38:20.35#ibcon#read 3, iclass 30, count 0 2006.211.07:38:20.35#ibcon#about to read 4, iclass 30, count 0 2006.211.07:38:20.35#ibcon#read 4, iclass 30, count 0 2006.211.07:38:20.35#ibcon#about to read 5, iclass 30, count 0 2006.211.07:38:20.35#ibcon#read 5, iclass 30, count 0 2006.211.07:38:20.35#ibcon#about to read 6, iclass 30, count 0 2006.211.07:38:20.35#ibcon#read 6, iclass 30, count 0 2006.211.07:38:20.35#ibcon#end of sib2, iclass 30, count 0 2006.211.07:38:20.35#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:38:20.35#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:38:20.35#ibcon#[27=USB\r\n] 2006.211.07:38:20.35#ibcon#*before write, iclass 30, count 0 2006.211.07:38:20.35#ibcon#enter sib2, iclass 30, count 0 2006.211.07:38:20.35#ibcon#flushed, iclass 30, count 0 2006.211.07:38:20.35#ibcon#about to write, iclass 30, count 0 2006.211.07:38:20.35#ibcon#wrote, iclass 30, count 0 2006.211.07:38:20.35#ibcon#about to read 3, iclass 30, count 0 2006.211.07:38:20.38#ibcon#read 3, iclass 30, count 0 2006.211.07:38:20.38#ibcon#about to read 4, iclass 30, count 0 2006.211.07:38:20.38#ibcon#read 4, iclass 30, count 0 2006.211.07:38:20.38#ibcon#about to read 5, iclass 30, count 0 2006.211.07:38:20.38#ibcon#read 5, iclass 30, count 0 2006.211.07:38:20.38#ibcon#about to read 6, iclass 30, count 0 2006.211.07:38:20.38#ibcon#read 6, iclass 30, count 0 2006.211.07:38:20.38#ibcon#end of sib2, iclass 30, count 0 2006.211.07:38:20.38#ibcon#*after write, iclass 30, count 0 2006.211.07:38:20.38#ibcon#*before return 0, iclass 30, count 0 2006.211.07:38:20.38#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:38:20.38#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:38:20.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:38:20.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:38:20.38$vc4f8/vblo=2,640.99 2006.211.07:38:20.38#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:38:20.38#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:38:20.38#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:20.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:20.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:20.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:20.38#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:38:20.38#ibcon#first serial, iclass 32, count 0 2006.211.07:38:20.38#ibcon#enter sib2, iclass 32, count 0 2006.211.07:38:20.38#ibcon#flushed, iclass 32, count 0 2006.211.07:38:20.38#ibcon#about to write, iclass 32, count 0 2006.211.07:38:20.38#ibcon#wrote, iclass 32, count 0 2006.211.07:38:20.38#ibcon#about to read 3, iclass 32, count 0 2006.211.07:38:20.40#ibcon#read 3, iclass 32, count 0 2006.211.07:38:20.40#ibcon#about to read 4, iclass 32, count 0 2006.211.07:38:20.40#ibcon#read 4, iclass 32, count 0 2006.211.07:38:20.40#ibcon#about to read 5, iclass 32, count 0 2006.211.07:38:20.40#ibcon#read 5, iclass 32, count 0 2006.211.07:38:20.40#ibcon#about to read 6, iclass 32, count 0 2006.211.07:38:20.40#ibcon#read 6, iclass 32, count 0 2006.211.07:38:20.40#ibcon#end of sib2, iclass 32, count 0 2006.211.07:38:20.40#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:38:20.40#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:38:20.40#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:38:20.40#ibcon#*before write, iclass 32, count 0 2006.211.07:38:20.40#ibcon#enter sib2, iclass 32, count 0 2006.211.07:38:20.40#ibcon#flushed, iclass 32, count 0 2006.211.07:38:20.40#ibcon#about to write, iclass 32, count 0 2006.211.07:38:20.40#ibcon#wrote, iclass 32, count 0 2006.211.07:38:20.40#ibcon#about to read 3, iclass 32, count 0 2006.211.07:38:20.44#ibcon#read 3, iclass 32, count 0 2006.211.07:38:20.44#ibcon#about to read 4, iclass 32, count 0 2006.211.07:38:20.44#ibcon#read 4, iclass 32, count 0 2006.211.07:38:20.44#ibcon#about to read 5, iclass 32, count 0 2006.211.07:38:20.44#ibcon#read 5, iclass 32, count 0 2006.211.07:38:20.44#ibcon#about to read 6, iclass 32, count 0 2006.211.07:38:20.44#ibcon#read 6, iclass 32, count 0 2006.211.07:38:20.44#ibcon#end of sib2, iclass 32, count 0 2006.211.07:38:20.44#ibcon#*after write, iclass 32, count 0 2006.211.07:38:20.44#ibcon#*before return 0, iclass 32, count 0 2006.211.07:38:20.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:20.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:38:20.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:38:20.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:38:20.44$vc4f8/vb=2,4 2006.211.07:38:20.44#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:38:20.44#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:38:20.44#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:20.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:20.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:20.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:20.50#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:38:20.50#ibcon#first serial, iclass 34, count 2 2006.211.07:38:20.50#ibcon#enter sib2, iclass 34, count 2 2006.211.07:38:20.50#ibcon#flushed, iclass 34, count 2 2006.211.07:38:20.50#ibcon#about to write, iclass 34, count 2 2006.211.07:38:20.50#ibcon#wrote, iclass 34, count 2 2006.211.07:38:20.50#ibcon#about to read 3, iclass 34, count 2 2006.211.07:38:20.52#ibcon#read 3, iclass 34, count 2 2006.211.07:38:20.52#ibcon#about to read 4, iclass 34, count 2 2006.211.07:38:20.52#ibcon#read 4, iclass 34, count 2 2006.211.07:38:20.52#ibcon#about to read 5, iclass 34, count 2 2006.211.07:38:20.52#ibcon#read 5, iclass 34, count 2 2006.211.07:38:20.52#ibcon#about to read 6, iclass 34, count 2 2006.211.07:38:20.52#ibcon#read 6, iclass 34, count 2 2006.211.07:38:20.52#ibcon#end of sib2, iclass 34, count 2 2006.211.07:38:20.52#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:38:20.52#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:38:20.52#ibcon#[27=AT02-04\r\n] 2006.211.07:38:20.52#ibcon#*before write, iclass 34, count 2 2006.211.07:38:20.52#ibcon#enter sib2, iclass 34, count 2 2006.211.07:38:20.52#ibcon#flushed, iclass 34, count 2 2006.211.07:38:20.52#ibcon#about to write, iclass 34, count 2 2006.211.07:38:20.52#ibcon#wrote, iclass 34, count 2 2006.211.07:38:20.52#ibcon#about to read 3, iclass 34, count 2 2006.211.07:38:20.55#ibcon#read 3, iclass 34, count 2 2006.211.07:38:20.55#ibcon#about to read 4, iclass 34, count 2 2006.211.07:38:20.55#ibcon#read 4, iclass 34, count 2 2006.211.07:38:20.55#ibcon#about to read 5, iclass 34, count 2 2006.211.07:38:20.55#ibcon#read 5, iclass 34, count 2 2006.211.07:38:20.55#ibcon#about to read 6, iclass 34, count 2 2006.211.07:38:20.55#ibcon#read 6, iclass 34, count 2 2006.211.07:38:20.55#ibcon#end of sib2, iclass 34, count 2 2006.211.07:38:20.55#ibcon#*after write, iclass 34, count 2 2006.211.07:38:20.55#ibcon#*before return 0, iclass 34, count 2 2006.211.07:38:20.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:20.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:38:20.55#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:38:20.55#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:20.55#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:20.67#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:20.67#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:20.67#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:38:20.67#ibcon#first serial, iclass 34, count 0 2006.211.07:38:20.67#ibcon#enter sib2, iclass 34, count 0 2006.211.07:38:20.67#ibcon#flushed, iclass 34, count 0 2006.211.07:38:20.67#ibcon#about to write, iclass 34, count 0 2006.211.07:38:20.67#ibcon#wrote, iclass 34, count 0 2006.211.07:38:20.67#ibcon#about to read 3, iclass 34, count 0 2006.211.07:38:20.69#ibcon#read 3, iclass 34, count 0 2006.211.07:38:20.69#ibcon#about to read 4, iclass 34, count 0 2006.211.07:38:20.69#ibcon#read 4, iclass 34, count 0 2006.211.07:38:20.69#ibcon#about to read 5, iclass 34, count 0 2006.211.07:38:20.69#ibcon#read 5, iclass 34, count 0 2006.211.07:38:20.69#ibcon#about to read 6, iclass 34, count 0 2006.211.07:38:20.69#ibcon#read 6, iclass 34, count 0 2006.211.07:38:20.69#ibcon#end of sib2, iclass 34, count 0 2006.211.07:38:20.69#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:38:20.69#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:38:20.69#ibcon#[27=USB\r\n] 2006.211.07:38:20.69#ibcon#*before write, iclass 34, count 0 2006.211.07:38:20.69#ibcon#enter sib2, iclass 34, count 0 2006.211.07:38:20.69#ibcon#flushed, iclass 34, count 0 2006.211.07:38:20.69#ibcon#about to write, iclass 34, count 0 2006.211.07:38:20.69#ibcon#wrote, iclass 34, count 0 2006.211.07:38:20.69#ibcon#about to read 3, iclass 34, count 0 2006.211.07:38:20.72#ibcon#read 3, iclass 34, count 0 2006.211.07:38:20.72#ibcon#about to read 4, iclass 34, count 0 2006.211.07:38:20.72#ibcon#read 4, iclass 34, count 0 2006.211.07:38:20.72#ibcon#about to read 5, iclass 34, count 0 2006.211.07:38:20.72#ibcon#read 5, iclass 34, count 0 2006.211.07:38:20.72#ibcon#about to read 6, iclass 34, count 0 2006.211.07:38:20.72#ibcon#read 6, iclass 34, count 0 2006.211.07:38:20.72#ibcon#end of sib2, iclass 34, count 0 2006.211.07:38:20.72#ibcon#*after write, iclass 34, count 0 2006.211.07:38:20.72#ibcon#*before return 0, iclass 34, count 0 2006.211.07:38:20.72#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:20.72#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:38:20.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:38:20.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:38:20.72$vc4f8/vblo=3,656.99 2006.211.07:38:20.72#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.07:38:20.72#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.07:38:20.72#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:20.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:20.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:20.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:20.72#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:38:20.72#ibcon#first serial, iclass 36, count 0 2006.211.07:38:20.72#ibcon#enter sib2, iclass 36, count 0 2006.211.07:38:20.72#ibcon#flushed, iclass 36, count 0 2006.211.07:38:20.72#ibcon#about to write, iclass 36, count 0 2006.211.07:38:20.72#ibcon#wrote, iclass 36, count 0 2006.211.07:38:20.72#ibcon#about to read 3, iclass 36, count 0 2006.211.07:38:20.74#ibcon#read 3, iclass 36, count 0 2006.211.07:38:20.74#ibcon#about to read 4, iclass 36, count 0 2006.211.07:38:20.74#ibcon#read 4, iclass 36, count 0 2006.211.07:38:20.74#ibcon#about to read 5, iclass 36, count 0 2006.211.07:38:20.74#ibcon#read 5, iclass 36, count 0 2006.211.07:38:20.74#ibcon#about to read 6, iclass 36, count 0 2006.211.07:38:20.74#ibcon#read 6, iclass 36, count 0 2006.211.07:38:20.74#ibcon#end of sib2, iclass 36, count 0 2006.211.07:38:20.74#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:38:20.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:38:20.74#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:38:20.74#ibcon#*before write, iclass 36, count 0 2006.211.07:38:20.74#ibcon#enter sib2, iclass 36, count 0 2006.211.07:38:20.74#ibcon#flushed, iclass 36, count 0 2006.211.07:38:20.74#ibcon#about to write, iclass 36, count 0 2006.211.07:38:20.74#ibcon#wrote, iclass 36, count 0 2006.211.07:38:20.74#ibcon#about to read 3, iclass 36, count 0 2006.211.07:38:20.78#ibcon#read 3, iclass 36, count 0 2006.211.07:38:20.78#ibcon#about to read 4, iclass 36, count 0 2006.211.07:38:20.78#ibcon#read 4, iclass 36, count 0 2006.211.07:38:20.78#ibcon#about to read 5, iclass 36, count 0 2006.211.07:38:20.78#ibcon#read 5, iclass 36, count 0 2006.211.07:38:20.78#ibcon#about to read 6, iclass 36, count 0 2006.211.07:38:20.78#ibcon#read 6, iclass 36, count 0 2006.211.07:38:20.78#ibcon#end of sib2, iclass 36, count 0 2006.211.07:38:20.78#ibcon#*after write, iclass 36, count 0 2006.211.07:38:20.78#ibcon#*before return 0, iclass 36, count 0 2006.211.07:38:20.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:20.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:38:20.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:38:20.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:38:20.78$vc4f8/vb=3,3 2006.211.07:38:20.78#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.07:38:20.78#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.07:38:20.78#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:20.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:20.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:20.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:20.84#ibcon#enter wrdev, iclass 38, count 2 2006.211.07:38:20.84#ibcon#first serial, iclass 38, count 2 2006.211.07:38:20.84#ibcon#enter sib2, iclass 38, count 2 2006.211.07:38:20.84#ibcon#flushed, iclass 38, count 2 2006.211.07:38:20.84#ibcon#about to write, iclass 38, count 2 2006.211.07:38:20.84#ibcon#wrote, iclass 38, count 2 2006.211.07:38:20.84#ibcon#about to read 3, iclass 38, count 2 2006.211.07:38:20.86#ibcon#read 3, iclass 38, count 2 2006.211.07:38:20.86#ibcon#about to read 4, iclass 38, count 2 2006.211.07:38:20.86#ibcon#read 4, iclass 38, count 2 2006.211.07:38:20.86#ibcon#about to read 5, iclass 38, count 2 2006.211.07:38:20.86#ibcon#read 5, iclass 38, count 2 2006.211.07:38:20.86#ibcon#about to read 6, iclass 38, count 2 2006.211.07:38:20.86#ibcon#read 6, iclass 38, count 2 2006.211.07:38:20.86#ibcon#end of sib2, iclass 38, count 2 2006.211.07:38:20.86#ibcon#*mode == 0, iclass 38, count 2 2006.211.07:38:20.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.07:38:20.86#ibcon#[27=AT03-03\r\n] 2006.211.07:38:20.86#ibcon#*before write, iclass 38, count 2 2006.211.07:38:20.86#ibcon#enter sib2, iclass 38, count 2 2006.211.07:38:20.86#ibcon#flushed, iclass 38, count 2 2006.211.07:38:20.86#ibcon#about to write, iclass 38, count 2 2006.211.07:38:20.86#ibcon#wrote, iclass 38, count 2 2006.211.07:38:20.86#ibcon#about to read 3, iclass 38, count 2 2006.211.07:38:20.89#ibcon#read 3, iclass 38, count 2 2006.211.07:38:20.89#ibcon#about to read 4, iclass 38, count 2 2006.211.07:38:20.89#ibcon#read 4, iclass 38, count 2 2006.211.07:38:20.89#ibcon#about to read 5, iclass 38, count 2 2006.211.07:38:20.89#ibcon#read 5, iclass 38, count 2 2006.211.07:38:20.89#ibcon#about to read 6, iclass 38, count 2 2006.211.07:38:20.89#ibcon#read 6, iclass 38, count 2 2006.211.07:38:20.89#ibcon#end of sib2, iclass 38, count 2 2006.211.07:38:20.89#ibcon#*after write, iclass 38, count 2 2006.211.07:38:20.89#ibcon#*before return 0, iclass 38, count 2 2006.211.07:38:20.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:20.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:38:20.89#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.07:38:20.89#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:20.89#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:21.01#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:21.01#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:21.01#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:38:21.01#ibcon#first serial, iclass 38, count 0 2006.211.07:38:21.01#ibcon#enter sib2, iclass 38, count 0 2006.211.07:38:21.01#ibcon#flushed, iclass 38, count 0 2006.211.07:38:21.01#ibcon#about to write, iclass 38, count 0 2006.211.07:38:21.01#ibcon#wrote, iclass 38, count 0 2006.211.07:38:21.01#ibcon#about to read 3, iclass 38, count 0 2006.211.07:38:21.03#ibcon#read 3, iclass 38, count 0 2006.211.07:38:21.03#ibcon#about to read 4, iclass 38, count 0 2006.211.07:38:21.03#ibcon#read 4, iclass 38, count 0 2006.211.07:38:21.03#ibcon#about to read 5, iclass 38, count 0 2006.211.07:38:21.03#ibcon#read 5, iclass 38, count 0 2006.211.07:38:21.03#ibcon#about to read 6, iclass 38, count 0 2006.211.07:38:21.03#ibcon#read 6, iclass 38, count 0 2006.211.07:38:21.03#ibcon#end of sib2, iclass 38, count 0 2006.211.07:38:21.03#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:38:21.03#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:38:21.03#ibcon#[27=USB\r\n] 2006.211.07:38:21.03#ibcon#*before write, iclass 38, count 0 2006.211.07:38:21.03#ibcon#enter sib2, iclass 38, count 0 2006.211.07:38:21.03#ibcon#flushed, iclass 38, count 0 2006.211.07:38:21.03#ibcon#about to write, iclass 38, count 0 2006.211.07:38:21.03#ibcon#wrote, iclass 38, count 0 2006.211.07:38:21.03#ibcon#about to read 3, iclass 38, count 0 2006.211.07:38:21.06#ibcon#read 3, iclass 38, count 0 2006.211.07:38:21.06#ibcon#about to read 4, iclass 38, count 0 2006.211.07:38:21.06#ibcon#read 4, iclass 38, count 0 2006.211.07:38:21.06#ibcon#about to read 5, iclass 38, count 0 2006.211.07:38:21.06#ibcon#read 5, iclass 38, count 0 2006.211.07:38:21.06#ibcon#about to read 6, iclass 38, count 0 2006.211.07:38:21.06#ibcon#read 6, iclass 38, count 0 2006.211.07:38:21.06#ibcon#end of sib2, iclass 38, count 0 2006.211.07:38:21.06#ibcon#*after write, iclass 38, count 0 2006.211.07:38:21.06#ibcon#*before return 0, iclass 38, count 0 2006.211.07:38:21.06#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:21.06#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:38:21.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:38:21.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:38:21.06$vc4f8/vblo=4,712.99 2006.211.07:38:21.06#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:38:21.06#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:38:21.06#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:21.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:21.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:21.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:21.06#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:38:21.06#ibcon#first serial, iclass 40, count 0 2006.211.07:38:21.06#ibcon#enter sib2, iclass 40, count 0 2006.211.07:38:21.06#ibcon#flushed, iclass 40, count 0 2006.211.07:38:21.06#ibcon#about to write, iclass 40, count 0 2006.211.07:38:21.06#ibcon#wrote, iclass 40, count 0 2006.211.07:38:21.06#ibcon#about to read 3, iclass 40, count 0 2006.211.07:38:21.08#ibcon#read 3, iclass 40, count 0 2006.211.07:38:21.08#ibcon#about to read 4, iclass 40, count 0 2006.211.07:38:21.08#ibcon#read 4, iclass 40, count 0 2006.211.07:38:21.08#ibcon#about to read 5, iclass 40, count 0 2006.211.07:38:21.08#ibcon#read 5, iclass 40, count 0 2006.211.07:38:21.08#ibcon#about to read 6, iclass 40, count 0 2006.211.07:38:21.08#ibcon#read 6, iclass 40, count 0 2006.211.07:38:21.08#ibcon#end of sib2, iclass 40, count 0 2006.211.07:38:21.08#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:38:21.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:38:21.08#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:38:21.08#ibcon#*before write, iclass 40, count 0 2006.211.07:38:21.08#ibcon#enter sib2, iclass 40, count 0 2006.211.07:38:21.08#ibcon#flushed, iclass 40, count 0 2006.211.07:38:21.08#ibcon#about to write, iclass 40, count 0 2006.211.07:38:21.08#ibcon#wrote, iclass 40, count 0 2006.211.07:38:21.08#ibcon#about to read 3, iclass 40, count 0 2006.211.07:38:21.12#ibcon#read 3, iclass 40, count 0 2006.211.07:38:21.12#ibcon#about to read 4, iclass 40, count 0 2006.211.07:38:21.12#ibcon#read 4, iclass 40, count 0 2006.211.07:38:21.12#ibcon#about to read 5, iclass 40, count 0 2006.211.07:38:21.12#ibcon#read 5, iclass 40, count 0 2006.211.07:38:21.12#ibcon#about to read 6, iclass 40, count 0 2006.211.07:38:21.12#ibcon#read 6, iclass 40, count 0 2006.211.07:38:21.12#ibcon#end of sib2, iclass 40, count 0 2006.211.07:38:21.12#ibcon#*after write, iclass 40, count 0 2006.211.07:38:21.12#ibcon#*before return 0, iclass 40, count 0 2006.211.07:38:21.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:21.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:38:21.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:38:21.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:38:21.12$vc4f8/vb=4,3 2006.211.07:38:21.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:38:21.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:38:21.12#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:21.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:21.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:21.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:21.18#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:38:21.18#ibcon#first serial, iclass 4, count 2 2006.211.07:38:21.18#ibcon#enter sib2, iclass 4, count 2 2006.211.07:38:21.18#ibcon#flushed, iclass 4, count 2 2006.211.07:38:21.18#ibcon#about to write, iclass 4, count 2 2006.211.07:38:21.18#ibcon#wrote, iclass 4, count 2 2006.211.07:38:21.18#ibcon#about to read 3, iclass 4, count 2 2006.211.07:38:21.20#ibcon#read 3, iclass 4, count 2 2006.211.07:38:21.20#ibcon#about to read 4, iclass 4, count 2 2006.211.07:38:21.20#ibcon#read 4, iclass 4, count 2 2006.211.07:38:21.20#ibcon#about to read 5, iclass 4, count 2 2006.211.07:38:21.20#ibcon#read 5, iclass 4, count 2 2006.211.07:38:21.20#ibcon#about to read 6, iclass 4, count 2 2006.211.07:38:21.20#ibcon#read 6, iclass 4, count 2 2006.211.07:38:21.20#ibcon#end of sib2, iclass 4, count 2 2006.211.07:38:21.20#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:38:21.20#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:38:21.20#ibcon#[27=AT04-03\r\n] 2006.211.07:38:21.20#ibcon#*before write, iclass 4, count 2 2006.211.07:38:21.20#ibcon#enter sib2, iclass 4, count 2 2006.211.07:38:21.20#ibcon#flushed, iclass 4, count 2 2006.211.07:38:21.20#ibcon#about to write, iclass 4, count 2 2006.211.07:38:21.20#ibcon#wrote, iclass 4, count 2 2006.211.07:38:21.20#ibcon#about to read 3, iclass 4, count 2 2006.211.07:38:21.23#ibcon#read 3, iclass 4, count 2 2006.211.07:38:21.23#ibcon#about to read 4, iclass 4, count 2 2006.211.07:38:21.23#ibcon#read 4, iclass 4, count 2 2006.211.07:38:21.23#ibcon#about to read 5, iclass 4, count 2 2006.211.07:38:21.23#ibcon#read 5, iclass 4, count 2 2006.211.07:38:21.23#ibcon#about to read 6, iclass 4, count 2 2006.211.07:38:21.23#ibcon#read 6, iclass 4, count 2 2006.211.07:38:21.23#ibcon#end of sib2, iclass 4, count 2 2006.211.07:38:21.23#ibcon#*after write, iclass 4, count 2 2006.211.07:38:21.23#ibcon#*before return 0, iclass 4, count 2 2006.211.07:38:21.23#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:21.23#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:38:21.23#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:38:21.23#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:21.23#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:21.35#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:21.35#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:21.35#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:38:21.35#ibcon#first serial, iclass 4, count 0 2006.211.07:38:21.35#ibcon#enter sib2, iclass 4, count 0 2006.211.07:38:21.35#ibcon#flushed, iclass 4, count 0 2006.211.07:38:21.35#ibcon#about to write, iclass 4, count 0 2006.211.07:38:21.35#ibcon#wrote, iclass 4, count 0 2006.211.07:38:21.35#ibcon#about to read 3, iclass 4, count 0 2006.211.07:38:21.37#ibcon#read 3, iclass 4, count 0 2006.211.07:38:21.37#ibcon#about to read 4, iclass 4, count 0 2006.211.07:38:21.37#ibcon#read 4, iclass 4, count 0 2006.211.07:38:21.37#ibcon#about to read 5, iclass 4, count 0 2006.211.07:38:21.37#ibcon#read 5, iclass 4, count 0 2006.211.07:38:21.37#ibcon#about to read 6, iclass 4, count 0 2006.211.07:38:21.37#ibcon#read 6, iclass 4, count 0 2006.211.07:38:21.37#ibcon#end of sib2, iclass 4, count 0 2006.211.07:38:21.37#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:38:21.37#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:38:21.37#ibcon#[27=USB\r\n] 2006.211.07:38:21.37#ibcon#*before write, iclass 4, count 0 2006.211.07:38:21.37#ibcon#enter sib2, iclass 4, count 0 2006.211.07:38:21.37#ibcon#flushed, iclass 4, count 0 2006.211.07:38:21.37#ibcon#about to write, iclass 4, count 0 2006.211.07:38:21.37#ibcon#wrote, iclass 4, count 0 2006.211.07:38:21.37#ibcon#about to read 3, iclass 4, count 0 2006.211.07:38:21.40#ibcon#read 3, iclass 4, count 0 2006.211.07:38:21.40#ibcon#about to read 4, iclass 4, count 0 2006.211.07:38:21.40#ibcon#read 4, iclass 4, count 0 2006.211.07:38:21.40#ibcon#about to read 5, iclass 4, count 0 2006.211.07:38:21.40#ibcon#read 5, iclass 4, count 0 2006.211.07:38:21.40#ibcon#about to read 6, iclass 4, count 0 2006.211.07:38:21.40#ibcon#read 6, iclass 4, count 0 2006.211.07:38:21.40#ibcon#end of sib2, iclass 4, count 0 2006.211.07:38:21.40#ibcon#*after write, iclass 4, count 0 2006.211.07:38:21.40#ibcon#*before return 0, iclass 4, count 0 2006.211.07:38:21.40#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:21.40#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:38:21.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:38:21.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:38:21.40$vc4f8/vblo=5,744.99 2006.211.07:38:21.40#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:38:21.40#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:38:21.40#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:21.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:21.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:21.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:21.40#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:38:21.40#ibcon#first serial, iclass 6, count 0 2006.211.07:38:21.40#ibcon#enter sib2, iclass 6, count 0 2006.211.07:38:21.40#ibcon#flushed, iclass 6, count 0 2006.211.07:38:21.40#ibcon#about to write, iclass 6, count 0 2006.211.07:38:21.40#ibcon#wrote, iclass 6, count 0 2006.211.07:38:21.40#ibcon#about to read 3, iclass 6, count 0 2006.211.07:38:21.42#ibcon#read 3, iclass 6, count 0 2006.211.07:38:21.42#ibcon#about to read 4, iclass 6, count 0 2006.211.07:38:21.42#ibcon#read 4, iclass 6, count 0 2006.211.07:38:21.42#ibcon#about to read 5, iclass 6, count 0 2006.211.07:38:21.42#ibcon#read 5, iclass 6, count 0 2006.211.07:38:21.42#ibcon#about to read 6, iclass 6, count 0 2006.211.07:38:21.42#ibcon#read 6, iclass 6, count 0 2006.211.07:38:21.42#ibcon#end of sib2, iclass 6, count 0 2006.211.07:38:21.42#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:38:21.42#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:38:21.42#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:38:21.42#ibcon#*before write, iclass 6, count 0 2006.211.07:38:21.42#ibcon#enter sib2, iclass 6, count 0 2006.211.07:38:21.42#ibcon#flushed, iclass 6, count 0 2006.211.07:38:21.42#ibcon#about to write, iclass 6, count 0 2006.211.07:38:21.42#ibcon#wrote, iclass 6, count 0 2006.211.07:38:21.42#ibcon#about to read 3, iclass 6, count 0 2006.211.07:38:21.46#ibcon#read 3, iclass 6, count 0 2006.211.07:38:21.46#ibcon#about to read 4, iclass 6, count 0 2006.211.07:38:21.46#ibcon#read 4, iclass 6, count 0 2006.211.07:38:21.46#ibcon#about to read 5, iclass 6, count 0 2006.211.07:38:21.46#ibcon#read 5, iclass 6, count 0 2006.211.07:38:21.46#ibcon#about to read 6, iclass 6, count 0 2006.211.07:38:21.46#ibcon#read 6, iclass 6, count 0 2006.211.07:38:21.46#ibcon#end of sib2, iclass 6, count 0 2006.211.07:38:21.46#ibcon#*after write, iclass 6, count 0 2006.211.07:38:21.46#ibcon#*before return 0, iclass 6, count 0 2006.211.07:38:21.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:21.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:38:21.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:38:21.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:38:21.46$vc4f8/vb=5,3 2006.211.07:38:21.46#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:38:21.46#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:38:21.46#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:21.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:21.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:21.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:21.52#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:38:21.52#ibcon#first serial, iclass 10, count 2 2006.211.07:38:21.52#ibcon#enter sib2, iclass 10, count 2 2006.211.07:38:21.52#ibcon#flushed, iclass 10, count 2 2006.211.07:38:21.52#ibcon#about to write, iclass 10, count 2 2006.211.07:38:21.52#ibcon#wrote, iclass 10, count 2 2006.211.07:38:21.52#ibcon#about to read 3, iclass 10, count 2 2006.211.07:38:21.54#ibcon#read 3, iclass 10, count 2 2006.211.07:38:21.54#ibcon#about to read 4, iclass 10, count 2 2006.211.07:38:21.54#ibcon#read 4, iclass 10, count 2 2006.211.07:38:21.54#ibcon#about to read 5, iclass 10, count 2 2006.211.07:38:21.54#ibcon#read 5, iclass 10, count 2 2006.211.07:38:21.54#ibcon#about to read 6, iclass 10, count 2 2006.211.07:38:21.54#ibcon#read 6, iclass 10, count 2 2006.211.07:38:21.54#ibcon#end of sib2, iclass 10, count 2 2006.211.07:38:21.54#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:38:21.54#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:38:21.54#ibcon#[27=AT05-03\r\n] 2006.211.07:38:21.54#ibcon#*before write, iclass 10, count 2 2006.211.07:38:21.54#ibcon#enter sib2, iclass 10, count 2 2006.211.07:38:21.54#ibcon#flushed, iclass 10, count 2 2006.211.07:38:21.54#ibcon#about to write, iclass 10, count 2 2006.211.07:38:21.54#ibcon#wrote, iclass 10, count 2 2006.211.07:38:21.54#ibcon#about to read 3, iclass 10, count 2 2006.211.07:38:21.57#ibcon#read 3, iclass 10, count 2 2006.211.07:38:21.57#ibcon#about to read 4, iclass 10, count 2 2006.211.07:38:21.57#ibcon#read 4, iclass 10, count 2 2006.211.07:38:21.57#ibcon#about to read 5, iclass 10, count 2 2006.211.07:38:21.57#ibcon#read 5, iclass 10, count 2 2006.211.07:38:21.57#ibcon#about to read 6, iclass 10, count 2 2006.211.07:38:21.57#ibcon#read 6, iclass 10, count 2 2006.211.07:38:21.57#ibcon#end of sib2, iclass 10, count 2 2006.211.07:38:21.57#ibcon#*after write, iclass 10, count 2 2006.211.07:38:21.57#ibcon#*before return 0, iclass 10, count 2 2006.211.07:38:21.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:21.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:38:21.57#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:38:21.57#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:21.57#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:21.69#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:21.69#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:21.69#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:38:21.69#ibcon#first serial, iclass 10, count 0 2006.211.07:38:21.69#ibcon#enter sib2, iclass 10, count 0 2006.211.07:38:21.69#ibcon#flushed, iclass 10, count 0 2006.211.07:38:21.69#ibcon#about to write, iclass 10, count 0 2006.211.07:38:21.69#ibcon#wrote, iclass 10, count 0 2006.211.07:38:21.69#ibcon#about to read 3, iclass 10, count 0 2006.211.07:38:21.71#ibcon#read 3, iclass 10, count 0 2006.211.07:38:21.71#ibcon#about to read 4, iclass 10, count 0 2006.211.07:38:21.71#ibcon#read 4, iclass 10, count 0 2006.211.07:38:21.71#ibcon#about to read 5, iclass 10, count 0 2006.211.07:38:21.71#ibcon#read 5, iclass 10, count 0 2006.211.07:38:21.71#ibcon#about to read 6, iclass 10, count 0 2006.211.07:38:21.71#ibcon#read 6, iclass 10, count 0 2006.211.07:38:21.71#ibcon#end of sib2, iclass 10, count 0 2006.211.07:38:21.71#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:38:21.71#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:38:21.71#ibcon#[27=USB\r\n] 2006.211.07:38:21.71#ibcon#*before write, iclass 10, count 0 2006.211.07:38:21.71#ibcon#enter sib2, iclass 10, count 0 2006.211.07:38:21.71#ibcon#flushed, iclass 10, count 0 2006.211.07:38:21.71#ibcon#about to write, iclass 10, count 0 2006.211.07:38:21.71#ibcon#wrote, iclass 10, count 0 2006.211.07:38:21.71#ibcon#about to read 3, iclass 10, count 0 2006.211.07:38:21.74#ibcon#read 3, iclass 10, count 0 2006.211.07:38:21.74#ibcon#about to read 4, iclass 10, count 0 2006.211.07:38:21.74#ibcon#read 4, iclass 10, count 0 2006.211.07:38:21.74#ibcon#about to read 5, iclass 10, count 0 2006.211.07:38:21.74#ibcon#read 5, iclass 10, count 0 2006.211.07:38:21.74#ibcon#about to read 6, iclass 10, count 0 2006.211.07:38:21.74#ibcon#read 6, iclass 10, count 0 2006.211.07:38:21.74#ibcon#end of sib2, iclass 10, count 0 2006.211.07:38:21.74#ibcon#*after write, iclass 10, count 0 2006.211.07:38:21.74#ibcon#*before return 0, iclass 10, count 0 2006.211.07:38:21.74#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:21.74#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:38:21.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:38:21.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:38:21.74$vc4f8/vblo=6,752.99 2006.211.07:38:21.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:38:21.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:38:21.74#ibcon#ireg 17 cls_cnt 0 2006.211.07:38:21.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:21.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:21.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:21.74#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:38:21.74#ibcon#first serial, iclass 12, count 0 2006.211.07:38:21.74#ibcon#enter sib2, iclass 12, count 0 2006.211.07:38:21.74#ibcon#flushed, iclass 12, count 0 2006.211.07:38:21.74#ibcon#about to write, iclass 12, count 0 2006.211.07:38:21.74#ibcon#wrote, iclass 12, count 0 2006.211.07:38:21.74#ibcon#about to read 3, iclass 12, count 0 2006.211.07:38:21.76#ibcon#read 3, iclass 12, count 0 2006.211.07:38:21.76#ibcon#about to read 4, iclass 12, count 0 2006.211.07:38:21.76#ibcon#read 4, iclass 12, count 0 2006.211.07:38:21.76#ibcon#about to read 5, iclass 12, count 0 2006.211.07:38:21.76#ibcon#read 5, iclass 12, count 0 2006.211.07:38:21.76#ibcon#about to read 6, iclass 12, count 0 2006.211.07:38:21.76#ibcon#read 6, iclass 12, count 0 2006.211.07:38:21.76#ibcon#end of sib2, iclass 12, count 0 2006.211.07:38:21.76#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:38:21.76#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:38:21.76#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:38:21.76#ibcon#*before write, iclass 12, count 0 2006.211.07:38:21.76#ibcon#enter sib2, iclass 12, count 0 2006.211.07:38:21.76#ibcon#flushed, iclass 12, count 0 2006.211.07:38:21.76#ibcon#about to write, iclass 12, count 0 2006.211.07:38:21.76#ibcon#wrote, iclass 12, count 0 2006.211.07:38:21.76#ibcon#about to read 3, iclass 12, count 0 2006.211.07:38:21.80#ibcon#read 3, iclass 12, count 0 2006.211.07:38:21.80#ibcon#about to read 4, iclass 12, count 0 2006.211.07:38:21.80#ibcon#read 4, iclass 12, count 0 2006.211.07:38:21.80#ibcon#about to read 5, iclass 12, count 0 2006.211.07:38:21.80#ibcon#read 5, iclass 12, count 0 2006.211.07:38:21.80#ibcon#about to read 6, iclass 12, count 0 2006.211.07:38:21.80#ibcon#read 6, iclass 12, count 0 2006.211.07:38:21.80#ibcon#end of sib2, iclass 12, count 0 2006.211.07:38:21.80#ibcon#*after write, iclass 12, count 0 2006.211.07:38:21.80#ibcon#*before return 0, iclass 12, count 0 2006.211.07:38:21.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:21.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:38:21.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:38:21.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:38:21.80$vc4f8/vb=6,3 2006.211.07:38:21.80#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:38:21.80#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:38:21.80#ibcon#ireg 11 cls_cnt 2 2006.211.07:38:21.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:21.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:21.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:21.86#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:38:21.86#ibcon#first serial, iclass 14, count 2 2006.211.07:38:21.86#ibcon#enter sib2, iclass 14, count 2 2006.211.07:38:21.86#ibcon#flushed, iclass 14, count 2 2006.211.07:38:21.86#ibcon#about to write, iclass 14, count 2 2006.211.07:38:21.86#ibcon#wrote, iclass 14, count 2 2006.211.07:38:21.86#ibcon#about to read 3, iclass 14, count 2 2006.211.07:38:21.88#ibcon#read 3, iclass 14, count 2 2006.211.07:38:21.88#ibcon#about to read 4, iclass 14, count 2 2006.211.07:38:21.88#ibcon#read 4, iclass 14, count 2 2006.211.07:38:21.88#ibcon#about to read 5, iclass 14, count 2 2006.211.07:38:21.88#ibcon#read 5, iclass 14, count 2 2006.211.07:38:21.88#ibcon#about to read 6, iclass 14, count 2 2006.211.07:38:21.88#ibcon#read 6, iclass 14, count 2 2006.211.07:38:21.88#ibcon#end of sib2, iclass 14, count 2 2006.211.07:38:21.88#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:38:21.88#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:38:21.88#ibcon#[27=AT06-03\r\n] 2006.211.07:38:21.88#ibcon#*before write, iclass 14, count 2 2006.211.07:38:21.88#ibcon#enter sib2, iclass 14, count 2 2006.211.07:38:21.88#ibcon#flushed, iclass 14, count 2 2006.211.07:38:21.88#ibcon#about to write, iclass 14, count 2 2006.211.07:38:21.88#ibcon#wrote, iclass 14, count 2 2006.211.07:38:21.88#ibcon#about to read 3, iclass 14, count 2 2006.211.07:38:21.91#ibcon#read 3, iclass 14, count 2 2006.211.07:38:21.91#ibcon#about to read 4, iclass 14, count 2 2006.211.07:38:21.91#ibcon#read 4, iclass 14, count 2 2006.211.07:38:21.91#ibcon#about to read 5, iclass 14, count 2 2006.211.07:38:21.91#ibcon#read 5, iclass 14, count 2 2006.211.07:38:21.91#ibcon#about to read 6, iclass 14, count 2 2006.211.07:38:21.91#ibcon#read 6, iclass 14, count 2 2006.211.07:38:21.91#ibcon#end of sib2, iclass 14, count 2 2006.211.07:38:21.91#ibcon#*after write, iclass 14, count 2 2006.211.07:38:21.91#ibcon#*before return 0, iclass 14, count 2 2006.211.07:38:21.91#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:21.91#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:38:21.91#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:38:21.91#ibcon#ireg 7 cls_cnt 0 2006.211.07:38:21.91#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:22.03#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:22.03#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:22.03#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:38:22.03#ibcon#first serial, iclass 14, count 0 2006.211.07:38:22.03#ibcon#enter sib2, iclass 14, count 0 2006.211.07:38:22.03#ibcon#flushed, iclass 14, count 0 2006.211.07:38:22.03#ibcon#about to write, iclass 14, count 0 2006.211.07:38:22.03#ibcon#wrote, iclass 14, count 0 2006.211.07:38:22.03#ibcon#about to read 3, iclass 14, count 0 2006.211.07:38:22.05#ibcon#read 3, iclass 14, count 0 2006.211.07:38:22.05#ibcon#about to read 4, iclass 14, count 0 2006.211.07:38:22.05#ibcon#read 4, iclass 14, count 0 2006.211.07:38:22.05#ibcon#about to read 5, iclass 14, count 0 2006.211.07:38:22.05#ibcon#read 5, iclass 14, count 0 2006.211.07:38:22.05#ibcon#about to read 6, iclass 14, count 0 2006.211.07:38:22.05#ibcon#read 6, iclass 14, count 0 2006.211.07:38:22.05#ibcon#end of sib2, iclass 14, count 0 2006.211.07:38:22.05#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:38:22.05#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:38:22.05#ibcon#[27=USB\r\n] 2006.211.07:38:22.05#ibcon#*before write, iclass 14, count 0 2006.211.07:38:22.05#ibcon#enter sib2, iclass 14, count 0 2006.211.07:38:22.05#ibcon#flushed, iclass 14, count 0 2006.211.07:38:22.05#ibcon#about to write, iclass 14, count 0 2006.211.07:38:22.05#ibcon#wrote, iclass 14, count 0 2006.211.07:38:22.05#ibcon#about to read 3, iclass 14, count 0 2006.211.07:38:22.08#ibcon#read 3, iclass 14, count 0 2006.211.07:38:22.08#ibcon#about to read 4, iclass 14, count 0 2006.211.07:38:22.08#ibcon#read 4, iclass 14, count 0 2006.211.07:38:22.08#ibcon#about to read 5, iclass 14, count 0 2006.211.07:38:22.08#ibcon#read 5, iclass 14, count 0 2006.211.07:38:22.08#ibcon#about to read 6, iclass 14, count 0 2006.211.07:38:22.08#ibcon#read 6, iclass 14, count 0 2006.211.07:38:22.08#ibcon#end of sib2, iclass 14, count 0 2006.211.07:38:22.08#ibcon#*after write, iclass 14, count 0 2006.211.07:38:22.08#ibcon#*before return 0, iclass 14, count 0 2006.211.07:38:22.08#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:22.08#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:38:22.08#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:38:22.08#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:38:22.08$vc4f8/vabw=wide 2006.211.07:38:22.08#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:38:22.08#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:38:22.08#ibcon#ireg 8 cls_cnt 0 2006.211.07:38:22.08#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:22.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:22.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:22.08#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:38:22.08#ibcon#first serial, iclass 16, count 0 2006.211.07:38:22.08#ibcon#enter sib2, iclass 16, count 0 2006.211.07:38:22.08#ibcon#flushed, iclass 16, count 0 2006.211.07:38:22.08#ibcon#about to write, iclass 16, count 0 2006.211.07:38:22.08#ibcon#wrote, iclass 16, count 0 2006.211.07:38:22.08#ibcon#about to read 3, iclass 16, count 0 2006.211.07:38:22.10#ibcon#read 3, iclass 16, count 0 2006.211.07:38:22.10#ibcon#about to read 4, iclass 16, count 0 2006.211.07:38:22.10#ibcon#read 4, iclass 16, count 0 2006.211.07:38:22.10#ibcon#about to read 5, iclass 16, count 0 2006.211.07:38:22.10#ibcon#read 5, iclass 16, count 0 2006.211.07:38:22.10#ibcon#about to read 6, iclass 16, count 0 2006.211.07:38:22.10#ibcon#read 6, iclass 16, count 0 2006.211.07:38:22.10#ibcon#end of sib2, iclass 16, count 0 2006.211.07:38:22.10#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:38:22.10#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:38:22.10#ibcon#[25=BW32\r\n] 2006.211.07:38:22.10#ibcon#*before write, iclass 16, count 0 2006.211.07:38:22.10#ibcon#enter sib2, iclass 16, count 0 2006.211.07:38:22.10#ibcon#flushed, iclass 16, count 0 2006.211.07:38:22.10#ibcon#about to write, iclass 16, count 0 2006.211.07:38:22.10#ibcon#wrote, iclass 16, count 0 2006.211.07:38:22.10#ibcon#about to read 3, iclass 16, count 0 2006.211.07:38:22.13#ibcon#read 3, iclass 16, count 0 2006.211.07:38:22.13#ibcon#about to read 4, iclass 16, count 0 2006.211.07:38:22.13#ibcon#read 4, iclass 16, count 0 2006.211.07:38:22.13#ibcon#about to read 5, iclass 16, count 0 2006.211.07:38:22.13#ibcon#read 5, iclass 16, count 0 2006.211.07:38:22.13#ibcon#about to read 6, iclass 16, count 0 2006.211.07:38:22.13#ibcon#read 6, iclass 16, count 0 2006.211.07:38:22.13#ibcon#end of sib2, iclass 16, count 0 2006.211.07:38:22.13#ibcon#*after write, iclass 16, count 0 2006.211.07:38:22.13#ibcon#*before return 0, iclass 16, count 0 2006.211.07:38:22.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:22.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:38:22.13#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:38:22.13#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:38:22.13$vc4f8/vbbw=wide 2006.211.07:38:22.13#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:38:22.13#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:38:22.13#ibcon#ireg 8 cls_cnt 0 2006.211.07:38:22.13#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:38:22.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:38:22.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:38:22.20#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:38:22.20#ibcon#first serial, iclass 18, count 0 2006.211.07:38:22.20#ibcon#enter sib2, iclass 18, count 0 2006.211.07:38:22.20#ibcon#flushed, iclass 18, count 0 2006.211.07:38:22.20#ibcon#about to write, iclass 18, count 0 2006.211.07:38:22.20#ibcon#wrote, iclass 18, count 0 2006.211.07:38:22.20#ibcon#about to read 3, iclass 18, count 0 2006.211.07:38:22.22#ibcon#read 3, iclass 18, count 0 2006.211.07:38:22.22#ibcon#about to read 4, iclass 18, count 0 2006.211.07:38:22.22#ibcon#read 4, iclass 18, count 0 2006.211.07:38:22.22#ibcon#about to read 5, iclass 18, count 0 2006.211.07:38:22.22#ibcon#read 5, iclass 18, count 0 2006.211.07:38:22.22#ibcon#about to read 6, iclass 18, count 0 2006.211.07:38:22.22#ibcon#read 6, iclass 18, count 0 2006.211.07:38:22.22#ibcon#end of sib2, iclass 18, count 0 2006.211.07:38:22.22#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:38:22.22#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:38:22.22#ibcon#[27=BW32\r\n] 2006.211.07:38:22.22#ibcon#*before write, iclass 18, count 0 2006.211.07:38:22.22#ibcon#enter sib2, iclass 18, count 0 2006.211.07:38:22.22#ibcon#flushed, iclass 18, count 0 2006.211.07:38:22.22#ibcon#about to write, iclass 18, count 0 2006.211.07:38:22.22#ibcon#wrote, iclass 18, count 0 2006.211.07:38:22.22#ibcon#about to read 3, iclass 18, count 0 2006.211.07:38:22.25#ibcon#read 3, iclass 18, count 0 2006.211.07:38:22.25#ibcon#about to read 4, iclass 18, count 0 2006.211.07:38:22.25#ibcon#read 4, iclass 18, count 0 2006.211.07:38:22.25#ibcon#about to read 5, iclass 18, count 0 2006.211.07:38:22.25#ibcon#read 5, iclass 18, count 0 2006.211.07:38:22.25#ibcon#about to read 6, iclass 18, count 0 2006.211.07:38:22.25#ibcon#read 6, iclass 18, count 0 2006.211.07:38:22.25#ibcon#end of sib2, iclass 18, count 0 2006.211.07:38:22.25#ibcon#*after write, iclass 18, count 0 2006.211.07:38:22.25#ibcon#*before return 0, iclass 18, count 0 2006.211.07:38:22.25#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:38:22.25#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:38:22.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:38:22.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:38:22.25$4f8m12a/ifd4f 2006.211.07:38:22.25$ifd4f/lo= 2006.211.07:38:22.25$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:38:22.25$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:38:22.25$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:38:22.25$ifd4f/patch= 2006.211.07:38:22.25$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:38:22.25$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:38:22.25$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:38:22.25$4f8m12a/"form=m,16.000,1:2 2006.211.07:38:22.25$4f8m12a/"tpicd 2006.211.07:38:22.25$4f8m12a/echo=off 2006.211.07:38:22.25$4f8m12a/xlog=off 2006.211.07:38:22.25:!2006.211.07:38:50 2006.211.07:38:30.13#trakl#Source acquired 2006.211.07:38:32.13#flagr#flagr/antenna,acquired 2006.211.07:38:50.00:preob 2006.211.07:38:51.13/onsource/TRACKING 2006.211.07:38:51.13:!2006.211.07:39:00 2006.211.07:39:00.00:data_valid=on 2006.211.07:39:00.00:midob 2006.211.07:39:00.13/onsource/TRACKING 2006.211.07:39:00.13/wx/24.97,1010.1,75 2006.211.07:39:00.21/cable/+6.4381E-03 2006.211.07:39:01.30/va/01,08,usb,yes,28,30 2006.211.07:39:01.30/va/02,07,usb,yes,28,30 2006.211.07:39:01.30/va/03,06,usb,yes,30,30 2006.211.07:39:01.30/va/04,07,usb,yes,29,31 2006.211.07:39:01.30/va/05,07,usb,yes,31,33 2006.211.07:39:01.30/va/06,06,usb,yes,30,30 2006.211.07:39:01.30/va/07,06,usb,yes,31,31 2006.211.07:39:01.30/va/08,07,usb,yes,29,29 2006.211.07:39:01.53/valo/01,532.99,yes,locked 2006.211.07:39:01.53/valo/02,572.99,yes,locked 2006.211.07:39:01.53/valo/03,672.99,yes,locked 2006.211.07:39:01.53/valo/04,832.99,yes,locked 2006.211.07:39:01.53/valo/05,652.99,yes,locked 2006.211.07:39:01.53/valo/06,772.99,yes,locked 2006.211.07:39:01.53/valo/07,832.99,yes,locked 2006.211.07:39:01.53/valo/08,852.99,yes,locked 2006.211.07:39:02.62/vb/01,04,usb,yes,28,27 2006.211.07:39:02.62/vb/02,04,usb,yes,30,31 2006.211.07:39:02.62/vb/03,03,usb,yes,33,37 2006.211.07:39:02.62/vb/04,03,usb,yes,34,34 2006.211.07:39:02.62/vb/05,03,usb,yes,32,36 2006.211.07:39:02.62/vb/06,03,usb,yes,33,36 2006.211.07:39:02.62/vb/07,04,usb,yes,29,28 2006.211.07:39:02.62/vb/08,03,usb,yes,33,36 2006.211.07:39:02.86/vblo/01,632.99,yes,locked 2006.211.07:39:02.86/vblo/02,640.99,yes,locked 2006.211.07:39:02.86/vblo/03,656.99,yes,locked 2006.211.07:39:02.86/vblo/04,712.99,yes,locked 2006.211.07:39:02.86/vblo/05,744.99,yes,locked 2006.211.07:39:02.86/vblo/06,752.99,yes,locked 2006.211.07:39:02.86/vblo/07,734.99,yes,locked 2006.211.07:39:02.86/vblo/08,744.99,yes,locked 2006.211.07:39:03.01/vabw/8 2006.211.07:39:03.16/vbbw/8 2006.211.07:39:03.25/xfe/off,on,12.2 2006.211.07:39:03.63/ifatt/23,28,28,28 2006.211.07:39:04.07/fmout-gps/S +4.50E-07 2006.211.07:39:04.11:!2006.211.07:40:00 2006.211.07:40:00.00:data_valid=off 2006.211.07:40:00.00:postob 2006.211.07:40:00.22/cable/+6.4379E-03 2006.211.07:40:00.22/wx/24.96,1010.2,76 2006.211.07:40:01.08/fmout-gps/S +4.49E-07 2006.211.07:40:01.08:scan_name=211-0740,k06211,60 2006.211.07:40:01.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.211.07:40:01.14#flagr#flagr/antenna,new-source 2006.211.07:40:02.14:checkk5 2006.211.07:40:02.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:40:02.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:40:03.18/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:40:03.52/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:40:03.86/chk_obsdata//k5ts1/T2110739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:40:04.19/chk_obsdata//k5ts2/T2110739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:40:04.52/chk_obsdata//k5ts3/T2110739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:40:04.86/chk_obsdata//k5ts4/T2110739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:40:05.51/k5log//k5ts1_log_newline 2006.211.07:40:06.17/k5log//k5ts2_log_newline 2006.211.07:40:06.82/k5log//k5ts3_log_newline 2006.211.07:40:07.48/k5log//k5ts4_log_newline 2006.211.07:40:07.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:40:07.50:4f8m12a=1 2006.211.07:40:07.50$4f8m12a/echo=on 2006.211.07:40:07.50$4f8m12a/pcalon 2006.211.07:40:07.50$pcalon/"no phase cal control is implemented here 2006.211.07:40:07.50$4f8m12a/"tpicd=stop 2006.211.07:40:07.50$4f8m12a/vc4f8 2006.211.07:40:07.50$vc4f8/valo=1,532.99 2006.211.07:40:07.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:40:07.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:40:07.51#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:07.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:07.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:07.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:07.51#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:40:07.51#ibcon#first serial, iclass 29, count 0 2006.211.07:40:07.51#ibcon#enter sib2, iclass 29, count 0 2006.211.07:40:07.51#ibcon#flushed, iclass 29, count 0 2006.211.07:40:07.51#ibcon#about to write, iclass 29, count 0 2006.211.07:40:07.51#ibcon#wrote, iclass 29, count 0 2006.211.07:40:07.51#ibcon#about to read 3, iclass 29, count 0 2006.211.07:40:07.52#ibcon#read 3, iclass 29, count 0 2006.211.07:40:07.52#ibcon#about to read 4, iclass 29, count 0 2006.211.07:40:07.52#ibcon#read 4, iclass 29, count 0 2006.211.07:40:07.52#ibcon#about to read 5, iclass 29, count 0 2006.211.07:40:07.52#ibcon#read 5, iclass 29, count 0 2006.211.07:40:07.52#ibcon#about to read 6, iclass 29, count 0 2006.211.07:40:07.52#ibcon#read 6, iclass 29, count 0 2006.211.07:40:07.52#ibcon#end of sib2, iclass 29, count 0 2006.211.07:40:07.52#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:40:07.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:40:07.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:40:07.52#ibcon#*before write, iclass 29, count 0 2006.211.07:40:07.52#ibcon#enter sib2, iclass 29, count 0 2006.211.07:40:07.52#ibcon#flushed, iclass 29, count 0 2006.211.07:40:07.52#ibcon#about to write, iclass 29, count 0 2006.211.07:40:07.52#ibcon#wrote, iclass 29, count 0 2006.211.07:40:07.52#ibcon#about to read 3, iclass 29, count 0 2006.211.07:40:07.57#ibcon#read 3, iclass 29, count 0 2006.211.07:40:07.57#ibcon#about to read 4, iclass 29, count 0 2006.211.07:40:07.57#ibcon#read 4, iclass 29, count 0 2006.211.07:40:07.57#ibcon#about to read 5, iclass 29, count 0 2006.211.07:40:07.57#ibcon#read 5, iclass 29, count 0 2006.211.07:40:07.57#ibcon#about to read 6, iclass 29, count 0 2006.211.07:40:07.57#ibcon#read 6, iclass 29, count 0 2006.211.07:40:07.57#ibcon#end of sib2, iclass 29, count 0 2006.211.07:40:07.57#ibcon#*after write, iclass 29, count 0 2006.211.07:40:07.57#ibcon#*before return 0, iclass 29, count 0 2006.211.07:40:07.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:07.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:07.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:40:07.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:40:07.57$vc4f8/va=1,8 2006.211.07:40:07.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:40:07.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:40:07.57#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:07.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:07.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:07.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:07.57#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:40:07.57#ibcon#first serial, iclass 31, count 2 2006.211.07:40:07.57#ibcon#enter sib2, iclass 31, count 2 2006.211.07:40:07.57#ibcon#flushed, iclass 31, count 2 2006.211.07:40:07.57#ibcon#about to write, iclass 31, count 2 2006.211.07:40:07.57#ibcon#wrote, iclass 31, count 2 2006.211.07:40:07.57#ibcon#about to read 3, iclass 31, count 2 2006.211.07:40:07.59#ibcon#read 3, iclass 31, count 2 2006.211.07:40:07.59#ibcon#about to read 4, iclass 31, count 2 2006.211.07:40:07.59#ibcon#read 4, iclass 31, count 2 2006.211.07:40:07.59#ibcon#about to read 5, iclass 31, count 2 2006.211.07:40:07.59#ibcon#read 5, iclass 31, count 2 2006.211.07:40:07.59#ibcon#about to read 6, iclass 31, count 2 2006.211.07:40:07.59#ibcon#read 6, iclass 31, count 2 2006.211.07:40:07.59#ibcon#end of sib2, iclass 31, count 2 2006.211.07:40:07.59#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:40:07.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:40:07.59#ibcon#[25=AT01-08\r\n] 2006.211.07:40:07.59#ibcon#*before write, iclass 31, count 2 2006.211.07:40:07.59#ibcon#enter sib2, iclass 31, count 2 2006.211.07:40:07.59#ibcon#flushed, iclass 31, count 2 2006.211.07:40:07.59#ibcon#about to write, iclass 31, count 2 2006.211.07:40:07.59#ibcon#wrote, iclass 31, count 2 2006.211.07:40:07.59#ibcon#about to read 3, iclass 31, count 2 2006.211.07:40:07.62#ibcon#read 3, iclass 31, count 2 2006.211.07:40:07.62#ibcon#about to read 4, iclass 31, count 2 2006.211.07:40:07.62#ibcon#read 4, iclass 31, count 2 2006.211.07:40:07.62#ibcon#about to read 5, iclass 31, count 2 2006.211.07:40:07.62#ibcon#read 5, iclass 31, count 2 2006.211.07:40:07.62#ibcon#about to read 6, iclass 31, count 2 2006.211.07:40:07.62#ibcon#read 6, iclass 31, count 2 2006.211.07:40:07.62#ibcon#end of sib2, iclass 31, count 2 2006.211.07:40:07.62#ibcon#*after write, iclass 31, count 2 2006.211.07:40:07.62#ibcon#*before return 0, iclass 31, count 2 2006.211.07:40:07.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:07.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:07.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:40:07.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:07.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:07.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:07.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:07.74#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:40:07.74#ibcon#first serial, iclass 31, count 0 2006.211.07:40:07.74#ibcon#enter sib2, iclass 31, count 0 2006.211.07:40:07.74#ibcon#flushed, iclass 31, count 0 2006.211.07:40:07.74#ibcon#about to write, iclass 31, count 0 2006.211.07:40:07.74#ibcon#wrote, iclass 31, count 0 2006.211.07:40:07.74#ibcon#about to read 3, iclass 31, count 0 2006.211.07:40:07.76#ibcon#read 3, iclass 31, count 0 2006.211.07:40:07.76#ibcon#about to read 4, iclass 31, count 0 2006.211.07:40:07.76#ibcon#read 4, iclass 31, count 0 2006.211.07:40:07.76#ibcon#about to read 5, iclass 31, count 0 2006.211.07:40:07.76#ibcon#read 5, iclass 31, count 0 2006.211.07:40:07.76#ibcon#about to read 6, iclass 31, count 0 2006.211.07:40:07.76#ibcon#read 6, iclass 31, count 0 2006.211.07:40:07.76#ibcon#end of sib2, iclass 31, count 0 2006.211.07:40:07.76#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:40:07.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:40:07.76#ibcon#[25=USB\r\n] 2006.211.07:40:07.76#ibcon#*before write, iclass 31, count 0 2006.211.07:40:07.76#ibcon#enter sib2, iclass 31, count 0 2006.211.07:40:07.76#ibcon#flushed, iclass 31, count 0 2006.211.07:40:07.76#ibcon#about to write, iclass 31, count 0 2006.211.07:40:07.76#ibcon#wrote, iclass 31, count 0 2006.211.07:40:07.76#ibcon#about to read 3, iclass 31, count 0 2006.211.07:40:07.79#ibcon#read 3, iclass 31, count 0 2006.211.07:40:07.79#ibcon#about to read 4, iclass 31, count 0 2006.211.07:40:07.79#ibcon#read 4, iclass 31, count 0 2006.211.07:40:07.79#ibcon#about to read 5, iclass 31, count 0 2006.211.07:40:07.79#ibcon#read 5, iclass 31, count 0 2006.211.07:40:07.79#ibcon#about to read 6, iclass 31, count 0 2006.211.07:40:07.79#ibcon#read 6, iclass 31, count 0 2006.211.07:40:07.79#ibcon#end of sib2, iclass 31, count 0 2006.211.07:40:07.79#ibcon#*after write, iclass 31, count 0 2006.211.07:40:07.79#ibcon#*before return 0, iclass 31, count 0 2006.211.07:40:07.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:07.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:07.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:40:07.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:40:07.79$vc4f8/valo=2,572.99 2006.211.07:40:07.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:40:07.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:40:07.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:07.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:07.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:07.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:07.79#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:40:07.79#ibcon#first serial, iclass 33, count 0 2006.211.07:40:07.79#ibcon#enter sib2, iclass 33, count 0 2006.211.07:40:07.79#ibcon#flushed, iclass 33, count 0 2006.211.07:40:07.79#ibcon#about to write, iclass 33, count 0 2006.211.07:40:07.79#ibcon#wrote, iclass 33, count 0 2006.211.07:40:07.79#ibcon#about to read 3, iclass 33, count 0 2006.211.07:40:07.81#ibcon#read 3, iclass 33, count 0 2006.211.07:40:07.81#ibcon#about to read 4, iclass 33, count 0 2006.211.07:40:07.81#ibcon#read 4, iclass 33, count 0 2006.211.07:40:07.81#ibcon#about to read 5, iclass 33, count 0 2006.211.07:40:07.81#ibcon#read 5, iclass 33, count 0 2006.211.07:40:07.81#ibcon#about to read 6, iclass 33, count 0 2006.211.07:40:07.81#ibcon#read 6, iclass 33, count 0 2006.211.07:40:07.81#ibcon#end of sib2, iclass 33, count 0 2006.211.07:40:07.81#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:40:07.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:40:07.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:40:07.81#ibcon#*before write, iclass 33, count 0 2006.211.07:40:07.81#ibcon#enter sib2, iclass 33, count 0 2006.211.07:40:07.81#ibcon#flushed, iclass 33, count 0 2006.211.07:40:07.81#ibcon#about to write, iclass 33, count 0 2006.211.07:40:07.81#ibcon#wrote, iclass 33, count 0 2006.211.07:40:07.81#ibcon#about to read 3, iclass 33, count 0 2006.211.07:40:07.85#ibcon#read 3, iclass 33, count 0 2006.211.07:40:07.85#ibcon#about to read 4, iclass 33, count 0 2006.211.07:40:07.85#ibcon#read 4, iclass 33, count 0 2006.211.07:40:07.85#ibcon#about to read 5, iclass 33, count 0 2006.211.07:40:07.85#ibcon#read 5, iclass 33, count 0 2006.211.07:40:07.85#ibcon#about to read 6, iclass 33, count 0 2006.211.07:40:07.85#ibcon#read 6, iclass 33, count 0 2006.211.07:40:07.85#ibcon#end of sib2, iclass 33, count 0 2006.211.07:40:07.85#ibcon#*after write, iclass 33, count 0 2006.211.07:40:07.85#ibcon#*before return 0, iclass 33, count 0 2006.211.07:40:07.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:07.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:07.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:40:07.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:40:07.85$vc4f8/va=2,7 2006.211.07:40:07.85#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:40:07.85#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:40:07.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:07.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:07.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:07.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:07.91#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:40:07.91#ibcon#first serial, iclass 35, count 2 2006.211.07:40:07.91#ibcon#enter sib2, iclass 35, count 2 2006.211.07:40:07.91#ibcon#flushed, iclass 35, count 2 2006.211.07:40:07.91#ibcon#about to write, iclass 35, count 2 2006.211.07:40:07.91#ibcon#wrote, iclass 35, count 2 2006.211.07:40:07.91#ibcon#about to read 3, iclass 35, count 2 2006.211.07:40:07.93#ibcon#read 3, iclass 35, count 2 2006.211.07:40:07.93#ibcon#about to read 4, iclass 35, count 2 2006.211.07:40:07.93#ibcon#read 4, iclass 35, count 2 2006.211.07:40:07.93#ibcon#about to read 5, iclass 35, count 2 2006.211.07:40:07.93#ibcon#read 5, iclass 35, count 2 2006.211.07:40:07.93#ibcon#about to read 6, iclass 35, count 2 2006.211.07:40:07.93#ibcon#read 6, iclass 35, count 2 2006.211.07:40:07.93#ibcon#end of sib2, iclass 35, count 2 2006.211.07:40:07.93#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:40:07.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:40:07.93#ibcon#[25=AT02-07\r\n] 2006.211.07:40:07.93#ibcon#*before write, iclass 35, count 2 2006.211.07:40:07.93#ibcon#enter sib2, iclass 35, count 2 2006.211.07:40:07.93#ibcon#flushed, iclass 35, count 2 2006.211.07:40:07.93#ibcon#about to write, iclass 35, count 2 2006.211.07:40:07.93#ibcon#wrote, iclass 35, count 2 2006.211.07:40:07.93#ibcon#about to read 3, iclass 35, count 2 2006.211.07:40:07.96#ibcon#read 3, iclass 35, count 2 2006.211.07:40:07.96#ibcon#about to read 4, iclass 35, count 2 2006.211.07:40:07.96#ibcon#read 4, iclass 35, count 2 2006.211.07:40:07.96#ibcon#about to read 5, iclass 35, count 2 2006.211.07:40:07.96#ibcon#read 5, iclass 35, count 2 2006.211.07:40:07.96#ibcon#about to read 6, iclass 35, count 2 2006.211.07:40:07.96#ibcon#read 6, iclass 35, count 2 2006.211.07:40:07.96#ibcon#end of sib2, iclass 35, count 2 2006.211.07:40:07.96#ibcon#*after write, iclass 35, count 2 2006.211.07:40:07.96#ibcon#*before return 0, iclass 35, count 2 2006.211.07:40:07.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:07.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:07.96#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:40:07.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:07.96#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:08.08#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:08.08#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:08.08#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:40:08.08#ibcon#first serial, iclass 35, count 0 2006.211.07:40:08.08#ibcon#enter sib2, iclass 35, count 0 2006.211.07:40:08.08#ibcon#flushed, iclass 35, count 0 2006.211.07:40:08.08#ibcon#about to write, iclass 35, count 0 2006.211.07:40:08.08#ibcon#wrote, iclass 35, count 0 2006.211.07:40:08.08#ibcon#about to read 3, iclass 35, count 0 2006.211.07:40:08.10#ibcon#read 3, iclass 35, count 0 2006.211.07:40:08.10#ibcon#about to read 4, iclass 35, count 0 2006.211.07:40:08.10#ibcon#read 4, iclass 35, count 0 2006.211.07:40:08.10#ibcon#about to read 5, iclass 35, count 0 2006.211.07:40:08.10#ibcon#read 5, iclass 35, count 0 2006.211.07:40:08.10#ibcon#about to read 6, iclass 35, count 0 2006.211.07:40:08.10#ibcon#read 6, iclass 35, count 0 2006.211.07:40:08.10#ibcon#end of sib2, iclass 35, count 0 2006.211.07:40:08.10#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:40:08.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:40:08.10#ibcon#[25=USB\r\n] 2006.211.07:40:08.10#ibcon#*before write, iclass 35, count 0 2006.211.07:40:08.10#ibcon#enter sib2, iclass 35, count 0 2006.211.07:40:08.10#ibcon#flushed, iclass 35, count 0 2006.211.07:40:08.10#ibcon#about to write, iclass 35, count 0 2006.211.07:40:08.10#ibcon#wrote, iclass 35, count 0 2006.211.07:40:08.10#ibcon#about to read 3, iclass 35, count 0 2006.211.07:40:08.13#ibcon#read 3, iclass 35, count 0 2006.211.07:40:08.13#ibcon#about to read 4, iclass 35, count 0 2006.211.07:40:08.13#ibcon#read 4, iclass 35, count 0 2006.211.07:40:08.13#ibcon#about to read 5, iclass 35, count 0 2006.211.07:40:08.13#ibcon#read 5, iclass 35, count 0 2006.211.07:40:08.13#ibcon#about to read 6, iclass 35, count 0 2006.211.07:40:08.13#ibcon#read 6, iclass 35, count 0 2006.211.07:40:08.13#ibcon#end of sib2, iclass 35, count 0 2006.211.07:40:08.13#ibcon#*after write, iclass 35, count 0 2006.211.07:40:08.13#ibcon#*before return 0, iclass 35, count 0 2006.211.07:40:08.13#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:08.13#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:08.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:40:08.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:40:08.13$vc4f8/valo=3,672.99 2006.211.07:40:08.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:40:08.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:40:08.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:08.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:08.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:08.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:08.13#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:40:08.13#ibcon#first serial, iclass 37, count 0 2006.211.07:40:08.13#ibcon#enter sib2, iclass 37, count 0 2006.211.07:40:08.13#ibcon#flushed, iclass 37, count 0 2006.211.07:40:08.13#ibcon#about to write, iclass 37, count 0 2006.211.07:40:08.13#ibcon#wrote, iclass 37, count 0 2006.211.07:40:08.13#ibcon#about to read 3, iclass 37, count 0 2006.211.07:40:08.15#ibcon#read 3, iclass 37, count 0 2006.211.07:40:08.15#ibcon#about to read 4, iclass 37, count 0 2006.211.07:40:08.15#ibcon#read 4, iclass 37, count 0 2006.211.07:40:08.15#ibcon#about to read 5, iclass 37, count 0 2006.211.07:40:08.15#ibcon#read 5, iclass 37, count 0 2006.211.07:40:08.15#ibcon#about to read 6, iclass 37, count 0 2006.211.07:40:08.15#ibcon#read 6, iclass 37, count 0 2006.211.07:40:08.15#ibcon#end of sib2, iclass 37, count 0 2006.211.07:40:08.15#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:40:08.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:40:08.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:40:08.15#ibcon#*before write, iclass 37, count 0 2006.211.07:40:08.15#ibcon#enter sib2, iclass 37, count 0 2006.211.07:40:08.15#ibcon#flushed, iclass 37, count 0 2006.211.07:40:08.15#ibcon#about to write, iclass 37, count 0 2006.211.07:40:08.15#ibcon#wrote, iclass 37, count 0 2006.211.07:40:08.15#ibcon#about to read 3, iclass 37, count 0 2006.211.07:40:08.19#ibcon#read 3, iclass 37, count 0 2006.211.07:40:08.19#ibcon#about to read 4, iclass 37, count 0 2006.211.07:40:08.19#ibcon#read 4, iclass 37, count 0 2006.211.07:40:08.19#ibcon#about to read 5, iclass 37, count 0 2006.211.07:40:08.19#ibcon#read 5, iclass 37, count 0 2006.211.07:40:08.19#ibcon#about to read 6, iclass 37, count 0 2006.211.07:40:08.19#ibcon#read 6, iclass 37, count 0 2006.211.07:40:08.19#ibcon#end of sib2, iclass 37, count 0 2006.211.07:40:08.19#ibcon#*after write, iclass 37, count 0 2006.211.07:40:08.19#ibcon#*before return 0, iclass 37, count 0 2006.211.07:40:08.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:08.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:08.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:40:08.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:40:08.19$vc4f8/va=3,6 2006.211.07:40:08.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:40:08.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:40:08.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:08.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:08.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:08.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:08.25#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:40:08.25#ibcon#first serial, iclass 39, count 2 2006.211.07:40:08.25#ibcon#enter sib2, iclass 39, count 2 2006.211.07:40:08.25#ibcon#flushed, iclass 39, count 2 2006.211.07:40:08.25#ibcon#about to write, iclass 39, count 2 2006.211.07:40:08.25#ibcon#wrote, iclass 39, count 2 2006.211.07:40:08.25#ibcon#about to read 3, iclass 39, count 2 2006.211.07:40:08.27#ibcon#read 3, iclass 39, count 2 2006.211.07:40:08.27#ibcon#about to read 4, iclass 39, count 2 2006.211.07:40:08.27#ibcon#read 4, iclass 39, count 2 2006.211.07:40:08.27#ibcon#about to read 5, iclass 39, count 2 2006.211.07:40:08.27#ibcon#read 5, iclass 39, count 2 2006.211.07:40:08.27#ibcon#about to read 6, iclass 39, count 2 2006.211.07:40:08.27#ibcon#read 6, iclass 39, count 2 2006.211.07:40:08.27#ibcon#end of sib2, iclass 39, count 2 2006.211.07:40:08.27#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:40:08.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:40:08.27#ibcon#[25=AT03-06\r\n] 2006.211.07:40:08.27#ibcon#*before write, iclass 39, count 2 2006.211.07:40:08.27#ibcon#enter sib2, iclass 39, count 2 2006.211.07:40:08.27#ibcon#flushed, iclass 39, count 2 2006.211.07:40:08.27#ibcon#about to write, iclass 39, count 2 2006.211.07:40:08.27#ibcon#wrote, iclass 39, count 2 2006.211.07:40:08.27#ibcon#about to read 3, iclass 39, count 2 2006.211.07:40:08.30#ibcon#read 3, iclass 39, count 2 2006.211.07:40:08.30#ibcon#about to read 4, iclass 39, count 2 2006.211.07:40:08.30#ibcon#read 4, iclass 39, count 2 2006.211.07:40:08.30#ibcon#about to read 5, iclass 39, count 2 2006.211.07:40:08.30#ibcon#read 5, iclass 39, count 2 2006.211.07:40:08.30#ibcon#about to read 6, iclass 39, count 2 2006.211.07:40:08.30#ibcon#read 6, iclass 39, count 2 2006.211.07:40:08.30#ibcon#end of sib2, iclass 39, count 2 2006.211.07:40:08.30#ibcon#*after write, iclass 39, count 2 2006.211.07:40:08.30#ibcon#*before return 0, iclass 39, count 2 2006.211.07:40:08.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:08.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:08.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:40:08.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:08.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:08.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:08.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:08.42#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:40:08.42#ibcon#first serial, iclass 39, count 0 2006.211.07:40:08.42#ibcon#enter sib2, iclass 39, count 0 2006.211.07:40:08.42#ibcon#flushed, iclass 39, count 0 2006.211.07:40:08.42#ibcon#about to write, iclass 39, count 0 2006.211.07:40:08.42#ibcon#wrote, iclass 39, count 0 2006.211.07:40:08.42#ibcon#about to read 3, iclass 39, count 0 2006.211.07:40:08.44#ibcon#read 3, iclass 39, count 0 2006.211.07:40:08.44#ibcon#about to read 4, iclass 39, count 0 2006.211.07:40:08.44#ibcon#read 4, iclass 39, count 0 2006.211.07:40:08.44#ibcon#about to read 5, iclass 39, count 0 2006.211.07:40:08.44#ibcon#read 5, iclass 39, count 0 2006.211.07:40:08.44#ibcon#about to read 6, iclass 39, count 0 2006.211.07:40:08.44#ibcon#read 6, iclass 39, count 0 2006.211.07:40:08.44#ibcon#end of sib2, iclass 39, count 0 2006.211.07:40:08.44#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:40:08.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:40:08.44#ibcon#[25=USB\r\n] 2006.211.07:40:08.44#ibcon#*before write, iclass 39, count 0 2006.211.07:40:08.44#ibcon#enter sib2, iclass 39, count 0 2006.211.07:40:08.44#ibcon#flushed, iclass 39, count 0 2006.211.07:40:08.44#ibcon#about to write, iclass 39, count 0 2006.211.07:40:08.44#ibcon#wrote, iclass 39, count 0 2006.211.07:40:08.44#ibcon#about to read 3, iclass 39, count 0 2006.211.07:40:08.47#ibcon#read 3, iclass 39, count 0 2006.211.07:40:08.47#ibcon#about to read 4, iclass 39, count 0 2006.211.07:40:08.47#ibcon#read 4, iclass 39, count 0 2006.211.07:40:08.47#ibcon#about to read 5, iclass 39, count 0 2006.211.07:40:08.47#ibcon#read 5, iclass 39, count 0 2006.211.07:40:08.47#ibcon#about to read 6, iclass 39, count 0 2006.211.07:40:08.47#ibcon#read 6, iclass 39, count 0 2006.211.07:40:08.47#ibcon#end of sib2, iclass 39, count 0 2006.211.07:40:08.47#ibcon#*after write, iclass 39, count 0 2006.211.07:40:08.47#ibcon#*before return 0, iclass 39, count 0 2006.211.07:40:08.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:08.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:08.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:40:08.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:40:08.47$vc4f8/valo=4,832.99 2006.211.07:40:08.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:40:08.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:40:08.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:08.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:08.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:08.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:08.47#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:40:08.47#ibcon#first serial, iclass 3, count 0 2006.211.07:40:08.47#ibcon#enter sib2, iclass 3, count 0 2006.211.07:40:08.47#ibcon#flushed, iclass 3, count 0 2006.211.07:40:08.47#ibcon#about to write, iclass 3, count 0 2006.211.07:40:08.47#ibcon#wrote, iclass 3, count 0 2006.211.07:40:08.47#ibcon#about to read 3, iclass 3, count 0 2006.211.07:40:08.49#ibcon#read 3, iclass 3, count 0 2006.211.07:40:08.49#ibcon#about to read 4, iclass 3, count 0 2006.211.07:40:08.49#ibcon#read 4, iclass 3, count 0 2006.211.07:40:08.49#ibcon#about to read 5, iclass 3, count 0 2006.211.07:40:08.49#ibcon#read 5, iclass 3, count 0 2006.211.07:40:08.49#ibcon#about to read 6, iclass 3, count 0 2006.211.07:40:08.49#ibcon#read 6, iclass 3, count 0 2006.211.07:40:08.49#ibcon#end of sib2, iclass 3, count 0 2006.211.07:40:08.49#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:40:08.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:40:08.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:40:08.49#ibcon#*before write, iclass 3, count 0 2006.211.07:40:08.49#ibcon#enter sib2, iclass 3, count 0 2006.211.07:40:08.49#ibcon#flushed, iclass 3, count 0 2006.211.07:40:08.49#ibcon#about to write, iclass 3, count 0 2006.211.07:40:08.49#ibcon#wrote, iclass 3, count 0 2006.211.07:40:08.49#ibcon#about to read 3, iclass 3, count 0 2006.211.07:40:08.53#ibcon#read 3, iclass 3, count 0 2006.211.07:40:08.53#ibcon#about to read 4, iclass 3, count 0 2006.211.07:40:08.53#ibcon#read 4, iclass 3, count 0 2006.211.07:40:08.53#ibcon#about to read 5, iclass 3, count 0 2006.211.07:40:08.53#ibcon#read 5, iclass 3, count 0 2006.211.07:40:08.53#ibcon#about to read 6, iclass 3, count 0 2006.211.07:40:08.53#ibcon#read 6, iclass 3, count 0 2006.211.07:40:08.53#ibcon#end of sib2, iclass 3, count 0 2006.211.07:40:08.53#ibcon#*after write, iclass 3, count 0 2006.211.07:40:08.53#ibcon#*before return 0, iclass 3, count 0 2006.211.07:40:08.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:08.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:08.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:40:08.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:40:08.53$vc4f8/va=4,7 2006.211.07:40:08.53#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:40:08.53#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:40:08.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:08.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:08.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:08.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:08.59#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:40:08.59#ibcon#first serial, iclass 5, count 2 2006.211.07:40:08.59#ibcon#enter sib2, iclass 5, count 2 2006.211.07:40:08.59#ibcon#flushed, iclass 5, count 2 2006.211.07:40:08.59#ibcon#about to write, iclass 5, count 2 2006.211.07:40:08.59#ibcon#wrote, iclass 5, count 2 2006.211.07:40:08.59#ibcon#about to read 3, iclass 5, count 2 2006.211.07:40:08.61#ibcon#read 3, iclass 5, count 2 2006.211.07:40:08.61#ibcon#about to read 4, iclass 5, count 2 2006.211.07:40:08.61#ibcon#read 4, iclass 5, count 2 2006.211.07:40:08.61#ibcon#about to read 5, iclass 5, count 2 2006.211.07:40:08.61#ibcon#read 5, iclass 5, count 2 2006.211.07:40:08.61#ibcon#about to read 6, iclass 5, count 2 2006.211.07:40:08.61#ibcon#read 6, iclass 5, count 2 2006.211.07:40:08.61#ibcon#end of sib2, iclass 5, count 2 2006.211.07:40:08.61#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:40:08.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:40:08.61#ibcon#[25=AT04-07\r\n] 2006.211.07:40:08.61#ibcon#*before write, iclass 5, count 2 2006.211.07:40:08.61#ibcon#enter sib2, iclass 5, count 2 2006.211.07:40:08.61#ibcon#flushed, iclass 5, count 2 2006.211.07:40:08.61#ibcon#about to write, iclass 5, count 2 2006.211.07:40:08.61#ibcon#wrote, iclass 5, count 2 2006.211.07:40:08.61#ibcon#about to read 3, iclass 5, count 2 2006.211.07:40:08.64#ibcon#read 3, iclass 5, count 2 2006.211.07:40:08.64#ibcon#about to read 4, iclass 5, count 2 2006.211.07:40:08.64#ibcon#read 4, iclass 5, count 2 2006.211.07:40:08.64#ibcon#about to read 5, iclass 5, count 2 2006.211.07:40:08.64#ibcon#read 5, iclass 5, count 2 2006.211.07:40:08.64#ibcon#about to read 6, iclass 5, count 2 2006.211.07:40:08.64#ibcon#read 6, iclass 5, count 2 2006.211.07:40:08.64#ibcon#end of sib2, iclass 5, count 2 2006.211.07:40:08.64#ibcon#*after write, iclass 5, count 2 2006.211.07:40:08.64#ibcon#*before return 0, iclass 5, count 2 2006.211.07:40:08.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:08.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:08.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:40:08.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:08.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:08.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:08.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:08.76#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:40:08.76#ibcon#first serial, iclass 5, count 0 2006.211.07:40:08.76#ibcon#enter sib2, iclass 5, count 0 2006.211.07:40:08.76#ibcon#flushed, iclass 5, count 0 2006.211.07:40:08.76#ibcon#about to write, iclass 5, count 0 2006.211.07:40:08.76#ibcon#wrote, iclass 5, count 0 2006.211.07:40:08.76#ibcon#about to read 3, iclass 5, count 0 2006.211.07:40:08.78#ibcon#read 3, iclass 5, count 0 2006.211.07:40:08.78#ibcon#about to read 4, iclass 5, count 0 2006.211.07:40:08.78#ibcon#read 4, iclass 5, count 0 2006.211.07:40:08.78#ibcon#about to read 5, iclass 5, count 0 2006.211.07:40:08.78#ibcon#read 5, iclass 5, count 0 2006.211.07:40:08.78#ibcon#about to read 6, iclass 5, count 0 2006.211.07:40:08.78#ibcon#read 6, iclass 5, count 0 2006.211.07:40:08.78#ibcon#end of sib2, iclass 5, count 0 2006.211.07:40:08.78#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:40:08.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:40:08.78#ibcon#[25=USB\r\n] 2006.211.07:40:08.78#ibcon#*before write, iclass 5, count 0 2006.211.07:40:08.78#ibcon#enter sib2, iclass 5, count 0 2006.211.07:40:08.78#ibcon#flushed, iclass 5, count 0 2006.211.07:40:08.78#ibcon#about to write, iclass 5, count 0 2006.211.07:40:08.78#ibcon#wrote, iclass 5, count 0 2006.211.07:40:08.78#ibcon#about to read 3, iclass 5, count 0 2006.211.07:40:08.81#ibcon#read 3, iclass 5, count 0 2006.211.07:40:08.81#ibcon#about to read 4, iclass 5, count 0 2006.211.07:40:08.81#ibcon#read 4, iclass 5, count 0 2006.211.07:40:08.81#ibcon#about to read 5, iclass 5, count 0 2006.211.07:40:08.81#ibcon#read 5, iclass 5, count 0 2006.211.07:40:08.81#ibcon#about to read 6, iclass 5, count 0 2006.211.07:40:08.81#ibcon#read 6, iclass 5, count 0 2006.211.07:40:08.81#ibcon#end of sib2, iclass 5, count 0 2006.211.07:40:08.81#ibcon#*after write, iclass 5, count 0 2006.211.07:40:08.81#ibcon#*before return 0, iclass 5, count 0 2006.211.07:40:08.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:08.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:08.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:40:08.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:40:08.81$vc4f8/valo=5,652.99 2006.211.07:40:08.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:40:08.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:40:08.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:08.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:08.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:08.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:08.81#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:40:08.81#ibcon#first serial, iclass 7, count 0 2006.211.07:40:08.81#ibcon#enter sib2, iclass 7, count 0 2006.211.07:40:08.81#ibcon#flushed, iclass 7, count 0 2006.211.07:40:08.81#ibcon#about to write, iclass 7, count 0 2006.211.07:40:08.81#ibcon#wrote, iclass 7, count 0 2006.211.07:40:08.81#ibcon#about to read 3, iclass 7, count 0 2006.211.07:40:08.83#ibcon#read 3, iclass 7, count 0 2006.211.07:40:08.83#ibcon#about to read 4, iclass 7, count 0 2006.211.07:40:08.83#ibcon#read 4, iclass 7, count 0 2006.211.07:40:08.83#ibcon#about to read 5, iclass 7, count 0 2006.211.07:40:08.83#ibcon#read 5, iclass 7, count 0 2006.211.07:40:08.83#ibcon#about to read 6, iclass 7, count 0 2006.211.07:40:08.83#ibcon#read 6, iclass 7, count 0 2006.211.07:40:08.83#ibcon#end of sib2, iclass 7, count 0 2006.211.07:40:08.83#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:40:08.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:40:08.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:40:08.83#ibcon#*before write, iclass 7, count 0 2006.211.07:40:08.83#ibcon#enter sib2, iclass 7, count 0 2006.211.07:40:08.83#ibcon#flushed, iclass 7, count 0 2006.211.07:40:08.83#ibcon#about to write, iclass 7, count 0 2006.211.07:40:08.83#ibcon#wrote, iclass 7, count 0 2006.211.07:40:08.83#ibcon#about to read 3, iclass 7, count 0 2006.211.07:40:08.87#ibcon#read 3, iclass 7, count 0 2006.211.07:40:08.87#ibcon#about to read 4, iclass 7, count 0 2006.211.07:40:08.87#ibcon#read 4, iclass 7, count 0 2006.211.07:40:08.87#ibcon#about to read 5, iclass 7, count 0 2006.211.07:40:08.87#ibcon#read 5, iclass 7, count 0 2006.211.07:40:08.87#ibcon#about to read 6, iclass 7, count 0 2006.211.07:40:08.87#ibcon#read 6, iclass 7, count 0 2006.211.07:40:08.87#ibcon#end of sib2, iclass 7, count 0 2006.211.07:40:08.87#ibcon#*after write, iclass 7, count 0 2006.211.07:40:08.87#ibcon#*before return 0, iclass 7, count 0 2006.211.07:40:08.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:08.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:08.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:40:08.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:40:08.87$vc4f8/va=5,7 2006.211.07:40:08.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:40:08.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:40:08.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:08.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:08.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:08.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:08.93#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:40:08.93#ibcon#first serial, iclass 11, count 2 2006.211.07:40:08.93#ibcon#enter sib2, iclass 11, count 2 2006.211.07:40:08.93#ibcon#flushed, iclass 11, count 2 2006.211.07:40:08.93#ibcon#about to write, iclass 11, count 2 2006.211.07:40:08.93#ibcon#wrote, iclass 11, count 2 2006.211.07:40:08.93#ibcon#about to read 3, iclass 11, count 2 2006.211.07:40:08.95#ibcon#read 3, iclass 11, count 2 2006.211.07:40:08.95#ibcon#about to read 4, iclass 11, count 2 2006.211.07:40:08.95#ibcon#read 4, iclass 11, count 2 2006.211.07:40:08.95#ibcon#about to read 5, iclass 11, count 2 2006.211.07:40:08.95#ibcon#read 5, iclass 11, count 2 2006.211.07:40:08.95#ibcon#about to read 6, iclass 11, count 2 2006.211.07:40:08.95#ibcon#read 6, iclass 11, count 2 2006.211.07:40:08.95#ibcon#end of sib2, iclass 11, count 2 2006.211.07:40:08.95#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:40:08.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:40:08.95#ibcon#[25=AT05-07\r\n] 2006.211.07:40:08.95#ibcon#*before write, iclass 11, count 2 2006.211.07:40:08.95#ibcon#enter sib2, iclass 11, count 2 2006.211.07:40:08.95#ibcon#flushed, iclass 11, count 2 2006.211.07:40:08.95#ibcon#about to write, iclass 11, count 2 2006.211.07:40:08.95#ibcon#wrote, iclass 11, count 2 2006.211.07:40:08.95#ibcon#about to read 3, iclass 11, count 2 2006.211.07:40:08.98#ibcon#read 3, iclass 11, count 2 2006.211.07:40:08.98#ibcon#about to read 4, iclass 11, count 2 2006.211.07:40:08.98#ibcon#read 4, iclass 11, count 2 2006.211.07:40:08.98#ibcon#about to read 5, iclass 11, count 2 2006.211.07:40:08.98#ibcon#read 5, iclass 11, count 2 2006.211.07:40:08.98#ibcon#about to read 6, iclass 11, count 2 2006.211.07:40:08.98#ibcon#read 6, iclass 11, count 2 2006.211.07:40:08.98#ibcon#end of sib2, iclass 11, count 2 2006.211.07:40:08.98#ibcon#*after write, iclass 11, count 2 2006.211.07:40:08.98#ibcon#*before return 0, iclass 11, count 2 2006.211.07:40:08.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:08.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:08.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:40:08.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:08.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:09.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:09.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:09.10#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:40:09.10#ibcon#first serial, iclass 11, count 0 2006.211.07:40:09.10#ibcon#enter sib2, iclass 11, count 0 2006.211.07:40:09.10#ibcon#flushed, iclass 11, count 0 2006.211.07:40:09.10#ibcon#about to write, iclass 11, count 0 2006.211.07:40:09.10#ibcon#wrote, iclass 11, count 0 2006.211.07:40:09.10#ibcon#about to read 3, iclass 11, count 0 2006.211.07:40:09.12#ibcon#read 3, iclass 11, count 0 2006.211.07:40:09.12#ibcon#about to read 4, iclass 11, count 0 2006.211.07:40:09.12#ibcon#read 4, iclass 11, count 0 2006.211.07:40:09.12#ibcon#about to read 5, iclass 11, count 0 2006.211.07:40:09.12#ibcon#read 5, iclass 11, count 0 2006.211.07:40:09.12#ibcon#about to read 6, iclass 11, count 0 2006.211.07:40:09.12#ibcon#read 6, iclass 11, count 0 2006.211.07:40:09.12#ibcon#end of sib2, iclass 11, count 0 2006.211.07:40:09.12#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:40:09.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:40:09.12#ibcon#[25=USB\r\n] 2006.211.07:40:09.12#ibcon#*before write, iclass 11, count 0 2006.211.07:40:09.12#ibcon#enter sib2, iclass 11, count 0 2006.211.07:40:09.12#ibcon#flushed, iclass 11, count 0 2006.211.07:40:09.12#ibcon#about to write, iclass 11, count 0 2006.211.07:40:09.12#ibcon#wrote, iclass 11, count 0 2006.211.07:40:09.12#ibcon#about to read 3, iclass 11, count 0 2006.211.07:40:09.15#ibcon#read 3, iclass 11, count 0 2006.211.07:40:09.15#ibcon#about to read 4, iclass 11, count 0 2006.211.07:40:09.15#ibcon#read 4, iclass 11, count 0 2006.211.07:40:09.15#ibcon#about to read 5, iclass 11, count 0 2006.211.07:40:09.15#ibcon#read 5, iclass 11, count 0 2006.211.07:40:09.15#ibcon#about to read 6, iclass 11, count 0 2006.211.07:40:09.15#ibcon#read 6, iclass 11, count 0 2006.211.07:40:09.15#ibcon#end of sib2, iclass 11, count 0 2006.211.07:40:09.15#ibcon#*after write, iclass 11, count 0 2006.211.07:40:09.15#ibcon#*before return 0, iclass 11, count 0 2006.211.07:40:09.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:09.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:09.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:40:09.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:40:09.15$vc4f8/valo=6,772.99 2006.211.07:40:09.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:40:09.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:40:09.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:09.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:09.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:09.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:09.15#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:40:09.15#ibcon#first serial, iclass 13, count 0 2006.211.07:40:09.15#ibcon#enter sib2, iclass 13, count 0 2006.211.07:40:09.15#ibcon#flushed, iclass 13, count 0 2006.211.07:40:09.15#ibcon#about to write, iclass 13, count 0 2006.211.07:40:09.15#ibcon#wrote, iclass 13, count 0 2006.211.07:40:09.15#ibcon#about to read 3, iclass 13, count 0 2006.211.07:40:09.17#ibcon#read 3, iclass 13, count 0 2006.211.07:40:09.17#ibcon#about to read 4, iclass 13, count 0 2006.211.07:40:09.17#ibcon#read 4, iclass 13, count 0 2006.211.07:40:09.17#ibcon#about to read 5, iclass 13, count 0 2006.211.07:40:09.17#ibcon#read 5, iclass 13, count 0 2006.211.07:40:09.17#ibcon#about to read 6, iclass 13, count 0 2006.211.07:40:09.17#ibcon#read 6, iclass 13, count 0 2006.211.07:40:09.17#ibcon#end of sib2, iclass 13, count 0 2006.211.07:40:09.17#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:40:09.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:40:09.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:40:09.17#ibcon#*before write, iclass 13, count 0 2006.211.07:40:09.17#ibcon#enter sib2, iclass 13, count 0 2006.211.07:40:09.17#ibcon#flushed, iclass 13, count 0 2006.211.07:40:09.17#ibcon#about to write, iclass 13, count 0 2006.211.07:40:09.17#ibcon#wrote, iclass 13, count 0 2006.211.07:40:09.17#ibcon#about to read 3, iclass 13, count 0 2006.211.07:40:09.21#ibcon#read 3, iclass 13, count 0 2006.211.07:40:09.21#ibcon#about to read 4, iclass 13, count 0 2006.211.07:40:09.21#ibcon#read 4, iclass 13, count 0 2006.211.07:40:09.21#ibcon#about to read 5, iclass 13, count 0 2006.211.07:40:09.21#ibcon#read 5, iclass 13, count 0 2006.211.07:40:09.21#ibcon#about to read 6, iclass 13, count 0 2006.211.07:40:09.21#ibcon#read 6, iclass 13, count 0 2006.211.07:40:09.21#ibcon#end of sib2, iclass 13, count 0 2006.211.07:40:09.21#ibcon#*after write, iclass 13, count 0 2006.211.07:40:09.21#ibcon#*before return 0, iclass 13, count 0 2006.211.07:40:09.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:09.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:09.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:40:09.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:40:09.21$vc4f8/va=6,6 2006.211.07:40:09.21#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.07:40:09.21#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.07:40:09.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:09.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:40:09.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:40:09.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:40:09.27#ibcon#enter wrdev, iclass 15, count 2 2006.211.07:40:09.27#ibcon#first serial, iclass 15, count 2 2006.211.07:40:09.27#ibcon#enter sib2, iclass 15, count 2 2006.211.07:40:09.27#ibcon#flushed, iclass 15, count 2 2006.211.07:40:09.27#ibcon#about to write, iclass 15, count 2 2006.211.07:40:09.27#ibcon#wrote, iclass 15, count 2 2006.211.07:40:09.27#ibcon#about to read 3, iclass 15, count 2 2006.211.07:40:09.29#ibcon#read 3, iclass 15, count 2 2006.211.07:40:09.29#ibcon#about to read 4, iclass 15, count 2 2006.211.07:40:09.29#ibcon#read 4, iclass 15, count 2 2006.211.07:40:09.29#ibcon#about to read 5, iclass 15, count 2 2006.211.07:40:09.29#ibcon#read 5, iclass 15, count 2 2006.211.07:40:09.29#ibcon#about to read 6, iclass 15, count 2 2006.211.07:40:09.29#ibcon#read 6, iclass 15, count 2 2006.211.07:40:09.29#ibcon#end of sib2, iclass 15, count 2 2006.211.07:40:09.29#ibcon#*mode == 0, iclass 15, count 2 2006.211.07:40:09.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.07:40:09.29#ibcon#[25=AT06-06\r\n] 2006.211.07:40:09.29#ibcon#*before write, iclass 15, count 2 2006.211.07:40:09.29#ibcon#enter sib2, iclass 15, count 2 2006.211.07:40:09.29#ibcon#flushed, iclass 15, count 2 2006.211.07:40:09.29#ibcon#about to write, iclass 15, count 2 2006.211.07:40:09.29#ibcon#wrote, iclass 15, count 2 2006.211.07:40:09.29#ibcon#about to read 3, iclass 15, count 2 2006.211.07:40:09.32#ibcon#read 3, iclass 15, count 2 2006.211.07:40:09.32#ibcon#about to read 4, iclass 15, count 2 2006.211.07:40:09.32#ibcon#read 4, iclass 15, count 2 2006.211.07:40:09.32#ibcon#about to read 5, iclass 15, count 2 2006.211.07:40:09.32#ibcon#read 5, iclass 15, count 2 2006.211.07:40:09.32#ibcon#about to read 6, iclass 15, count 2 2006.211.07:40:09.32#ibcon#read 6, iclass 15, count 2 2006.211.07:40:09.32#ibcon#end of sib2, iclass 15, count 2 2006.211.07:40:09.32#ibcon#*after write, iclass 15, count 2 2006.211.07:40:09.32#ibcon#*before return 0, iclass 15, count 2 2006.211.07:40:09.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:40:09.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:40:09.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.07:40:09.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:09.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:40:09.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:40:09.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:40:09.44#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:40:09.44#ibcon#first serial, iclass 15, count 0 2006.211.07:40:09.44#ibcon#enter sib2, iclass 15, count 0 2006.211.07:40:09.44#ibcon#flushed, iclass 15, count 0 2006.211.07:40:09.44#ibcon#about to write, iclass 15, count 0 2006.211.07:40:09.44#ibcon#wrote, iclass 15, count 0 2006.211.07:40:09.44#ibcon#about to read 3, iclass 15, count 0 2006.211.07:40:09.46#ibcon#read 3, iclass 15, count 0 2006.211.07:40:09.46#ibcon#about to read 4, iclass 15, count 0 2006.211.07:40:09.46#ibcon#read 4, iclass 15, count 0 2006.211.07:40:09.46#ibcon#about to read 5, iclass 15, count 0 2006.211.07:40:09.46#ibcon#read 5, iclass 15, count 0 2006.211.07:40:09.46#ibcon#about to read 6, iclass 15, count 0 2006.211.07:40:09.46#ibcon#read 6, iclass 15, count 0 2006.211.07:40:09.46#ibcon#end of sib2, iclass 15, count 0 2006.211.07:40:09.46#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:40:09.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:40:09.46#ibcon#[25=USB\r\n] 2006.211.07:40:09.46#ibcon#*before write, iclass 15, count 0 2006.211.07:40:09.46#ibcon#enter sib2, iclass 15, count 0 2006.211.07:40:09.46#ibcon#flushed, iclass 15, count 0 2006.211.07:40:09.46#ibcon#about to write, iclass 15, count 0 2006.211.07:40:09.46#ibcon#wrote, iclass 15, count 0 2006.211.07:40:09.46#ibcon#about to read 3, iclass 15, count 0 2006.211.07:40:09.49#ibcon#read 3, iclass 15, count 0 2006.211.07:40:09.49#ibcon#about to read 4, iclass 15, count 0 2006.211.07:40:09.49#ibcon#read 4, iclass 15, count 0 2006.211.07:40:09.49#ibcon#about to read 5, iclass 15, count 0 2006.211.07:40:09.49#ibcon#read 5, iclass 15, count 0 2006.211.07:40:09.49#ibcon#about to read 6, iclass 15, count 0 2006.211.07:40:09.49#ibcon#read 6, iclass 15, count 0 2006.211.07:40:09.49#ibcon#end of sib2, iclass 15, count 0 2006.211.07:40:09.49#ibcon#*after write, iclass 15, count 0 2006.211.07:40:09.49#ibcon#*before return 0, iclass 15, count 0 2006.211.07:40:09.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:40:09.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:40:09.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:40:09.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:40:09.49$vc4f8/valo=7,832.99 2006.211.07:40:09.49#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.07:40:09.49#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.07:40:09.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:09.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:40:09.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:40:09.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:40:09.49#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:40:09.49#ibcon#first serial, iclass 17, count 0 2006.211.07:40:09.49#ibcon#enter sib2, iclass 17, count 0 2006.211.07:40:09.49#ibcon#flushed, iclass 17, count 0 2006.211.07:40:09.49#ibcon#about to write, iclass 17, count 0 2006.211.07:40:09.49#ibcon#wrote, iclass 17, count 0 2006.211.07:40:09.49#ibcon#about to read 3, iclass 17, count 0 2006.211.07:40:09.51#ibcon#read 3, iclass 17, count 0 2006.211.07:40:09.51#ibcon#about to read 4, iclass 17, count 0 2006.211.07:40:09.51#ibcon#read 4, iclass 17, count 0 2006.211.07:40:09.51#ibcon#about to read 5, iclass 17, count 0 2006.211.07:40:09.51#ibcon#read 5, iclass 17, count 0 2006.211.07:40:09.51#ibcon#about to read 6, iclass 17, count 0 2006.211.07:40:09.51#ibcon#read 6, iclass 17, count 0 2006.211.07:40:09.51#ibcon#end of sib2, iclass 17, count 0 2006.211.07:40:09.51#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:40:09.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:40:09.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:40:09.51#ibcon#*before write, iclass 17, count 0 2006.211.07:40:09.51#ibcon#enter sib2, iclass 17, count 0 2006.211.07:40:09.51#ibcon#flushed, iclass 17, count 0 2006.211.07:40:09.51#ibcon#about to write, iclass 17, count 0 2006.211.07:40:09.51#ibcon#wrote, iclass 17, count 0 2006.211.07:40:09.51#ibcon#about to read 3, iclass 17, count 0 2006.211.07:40:09.55#ibcon#read 3, iclass 17, count 0 2006.211.07:40:09.55#ibcon#about to read 4, iclass 17, count 0 2006.211.07:40:09.55#ibcon#read 4, iclass 17, count 0 2006.211.07:40:09.55#ibcon#about to read 5, iclass 17, count 0 2006.211.07:40:09.55#ibcon#read 5, iclass 17, count 0 2006.211.07:40:09.55#ibcon#about to read 6, iclass 17, count 0 2006.211.07:40:09.55#ibcon#read 6, iclass 17, count 0 2006.211.07:40:09.55#ibcon#end of sib2, iclass 17, count 0 2006.211.07:40:09.55#ibcon#*after write, iclass 17, count 0 2006.211.07:40:09.55#ibcon#*before return 0, iclass 17, count 0 2006.211.07:40:09.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:40:09.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:40:09.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:40:09.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:40:09.55$vc4f8/va=7,6 2006.211.07:40:09.55#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.07:40:09.55#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.07:40:09.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:09.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:40:09.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:40:09.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:40:09.61#ibcon#enter wrdev, iclass 19, count 2 2006.211.07:40:09.61#ibcon#first serial, iclass 19, count 2 2006.211.07:40:09.61#ibcon#enter sib2, iclass 19, count 2 2006.211.07:40:09.61#ibcon#flushed, iclass 19, count 2 2006.211.07:40:09.61#ibcon#about to write, iclass 19, count 2 2006.211.07:40:09.61#ibcon#wrote, iclass 19, count 2 2006.211.07:40:09.61#ibcon#about to read 3, iclass 19, count 2 2006.211.07:40:09.63#ibcon#read 3, iclass 19, count 2 2006.211.07:40:09.63#ibcon#about to read 4, iclass 19, count 2 2006.211.07:40:09.63#ibcon#read 4, iclass 19, count 2 2006.211.07:40:09.63#ibcon#about to read 5, iclass 19, count 2 2006.211.07:40:09.63#ibcon#read 5, iclass 19, count 2 2006.211.07:40:09.63#ibcon#about to read 6, iclass 19, count 2 2006.211.07:40:09.63#ibcon#read 6, iclass 19, count 2 2006.211.07:40:09.63#ibcon#end of sib2, iclass 19, count 2 2006.211.07:40:09.63#ibcon#*mode == 0, iclass 19, count 2 2006.211.07:40:09.63#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.07:40:09.63#ibcon#[25=AT07-06\r\n] 2006.211.07:40:09.63#ibcon#*before write, iclass 19, count 2 2006.211.07:40:09.63#ibcon#enter sib2, iclass 19, count 2 2006.211.07:40:09.63#ibcon#flushed, iclass 19, count 2 2006.211.07:40:09.63#ibcon#about to write, iclass 19, count 2 2006.211.07:40:09.63#ibcon#wrote, iclass 19, count 2 2006.211.07:40:09.63#ibcon#about to read 3, iclass 19, count 2 2006.211.07:40:09.66#ibcon#read 3, iclass 19, count 2 2006.211.07:40:09.66#ibcon#about to read 4, iclass 19, count 2 2006.211.07:40:09.66#ibcon#read 4, iclass 19, count 2 2006.211.07:40:09.66#ibcon#about to read 5, iclass 19, count 2 2006.211.07:40:09.66#ibcon#read 5, iclass 19, count 2 2006.211.07:40:09.66#ibcon#about to read 6, iclass 19, count 2 2006.211.07:40:09.66#ibcon#read 6, iclass 19, count 2 2006.211.07:40:09.66#ibcon#end of sib2, iclass 19, count 2 2006.211.07:40:09.66#ibcon#*after write, iclass 19, count 2 2006.211.07:40:09.66#ibcon#*before return 0, iclass 19, count 2 2006.211.07:40:09.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:40:09.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:40:09.66#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.07:40:09.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:09.66#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:40:09.78#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:40:09.78#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:40:09.78#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:40:09.78#ibcon#first serial, iclass 19, count 0 2006.211.07:40:09.78#ibcon#enter sib2, iclass 19, count 0 2006.211.07:40:09.78#ibcon#flushed, iclass 19, count 0 2006.211.07:40:09.78#ibcon#about to write, iclass 19, count 0 2006.211.07:40:09.78#ibcon#wrote, iclass 19, count 0 2006.211.07:40:09.78#ibcon#about to read 3, iclass 19, count 0 2006.211.07:40:09.80#ibcon#read 3, iclass 19, count 0 2006.211.07:40:09.80#ibcon#about to read 4, iclass 19, count 0 2006.211.07:40:09.80#ibcon#read 4, iclass 19, count 0 2006.211.07:40:09.80#ibcon#about to read 5, iclass 19, count 0 2006.211.07:40:09.80#ibcon#read 5, iclass 19, count 0 2006.211.07:40:09.80#ibcon#about to read 6, iclass 19, count 0 2006.211.07:40:09.80#ibcon#read 6, iclass 19, count 0 2006.211.07:40:09.80#ibcon#end of sib2, iclass 19, count 0 2006.211.07:40:09.80#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:40:09.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:40:09.80#ibcon#[25=USB\r\n] 2006.211.07:40:09.80#ibcon#*before write, iclass 19, count 0 2006.211.07:40:09.80#ibcon#enter sib2, iclass 19, count 0 2006.211.07:40:09.80#ibcon#flushed, iclass 19, count 0 2006.211.07:40:09.80#ibcon#about to write, iclass 19, count 0 2006.211.07:40:09.80#ibcon#wrote, iclass 19, count 0 2006.211.07:40:09.80#ibcon#about to read 3, iclass 19, count 0 2006.211.07:40:09.83#ibcon#read 3, iclass 19, count 0 2006.211.07:40:09.83#ibcon#about to read 4, iclass 19, count 0 2006.211.07:40:09.83#ibcon#read 4, iclass 19, count 0 2006.211.07:40:09.83#ibcon#about to read 5, iclass 19, count 0 2006.211.07:40:09.83#ibcon#read 5, iclass 19, count 0 2006.211.07:40:09.83#ibcon#about to read 6, iclass 19, count 0 2006.211.07:40:09.83#ibcon#read 6, iclass 19, count 0 2006.211.07:40:09.83#ibcon#end of sib2, iclass 19, count 0 2006.211.07:40:09.83#ibcon#*after write, iclass 19, count 0 2006.211.07:40:09.83#ibcon#*before return 0, iclass 19, count 0 2006.211.07:40:09.83#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:40:09.83#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:40:09.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:40:09.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:40:09.83$vc4f8/valo=8,852.99 2006.211.07:40:09.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.07:40:09.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.07:40:09.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:09.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:40:09.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:40:09.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:40:09.83#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:40:09.83#ibcon#first serial, iclass 21, count 0 2006.211.07:40:09.83#ibcon#enter sib2, iclass 21, count 0 2006.211.07:40:09.83#ibcon#flushed, iclass 21, count 0 2006.211.07:40:09.83#ibcon#about to write, iclass 21, count 0 2006.211.07:40:09.83#ibcon#wrote, iclass 21, count 0 2006.211.07:40:09.83#ibcon#about to read 3, iclass 21, count 0 2006.211.07:40:09.85#ibcon#read 3, iclass 21, count 0 2006.211.07:40:09.85#ibcon#about to read 4, iclass 21, count 0 2006.211.07:40:09.85#ibcon#read 4, iclass 21, count 0 2006.211.07:40:09.85#ibcon#about to read 5, iclass 21, count 0 2006.211.07:40:09.85#ibcon#read 5, iclass 21, count 0 2006.211.07:40:09.85#ibcon#about to read 6, iclass 21, count 0 2006.211.07:40:09.85#ibcon#read 6, iclass 21, count 0 2006.211.07:40:09.85#ibcon#end of sib2, iclass 21, count 0 2006.211.07:40:09.85#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:40:09.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:40:09.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:40:09.85#ibcon#*before write, iclass 21, count 0 2006.211.07:40:09.85#ibcon#enter sib2, iclass 21, count 0 2006.211.07:40:09.85#ibcon#flushed, iclass 21, count 0 2006.211.07:40:09.85#ibcon#about to write, iclass 21, count 0 2006.211.07:40:09.85#ibcon#wrote, iclass 21, count 0 2006.211.07:40:09.85#ibcon#about to read 3, iclass 21, count 0 2006.211.07:40:09.89#ibcon#read 3, iclass 21, count 0 2006.211.07:40:09.89#ibcon#about to read 4, iclass 21, count 0 2006.211.07:40:09.89#ibcon#read 4, iclass 21, count 0 2006.211.07:40:09.89#ibcon#about to read 5, iclass 21, count 0 2006.211.07:40:09.89#ibcon#read 5, iclass 21, count 0 2006.211.07:40:09.89#ibcon#about to read 6, iclass 21, count 0 2006.211.07:40:09.89#ibcon#read 6, iclass 21, count 0 2006.211.07:40:09.89#ibcon#end of sib2, iclass 21, count 0 2006.211.07:40:09.89#ibcon#*after write, iclass 21, count 0 2006.211.07:40:09.89#ibcon#*before return 0, iclass 21, count 0 2006.211.07:40:09.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:40:09.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:40:09.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:40:09.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:40:09.89$vc4f8/va=8,7 2006.211.07:40:09.89#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.07:40:09.89#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.07:40:09.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:09.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:40:09.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:40:09.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:40:09.95#ibcon#enter wrdev, iclass 23, count 2 2006.211.07:40:09.95#ibcon#first serial, iclass 23, count 2 2006.211.07:40:09.95#ibcon#enter sib2, iclass 23, count 2 2006.211.07:40:09.95#ibcon#flushed, iclass 23, count 2 2006.211.07:40:09.95#ibcon#about to write, iclass 23, count 2 2006.211.07:40:09.95#ibcon#wrote, iclass 23, count 2 2006.211.07:40:09.95#ibcon#about to read 3, iclass 23, count 2 2006.211.07:40:09.97#ibcon#read 3, iclass 23, count 2 2006.211.07:40:09.97#ibcon#about to read 4, iclass 23, count 2 2006.211.07:40:09.97#ibcon#read 4, iclass 23, count 2 2006.211.07:40:09.97#ibcon#about to read 5, iclass 23, count 2 2006.211.07:40:09.97#ibcon#read 5, iclass 23, count 2 2006.211.07:40:09.97#ibcon#about to read 6, iclass 23, count 2 2006.211.07:40:09.97#ibcon#read 6, iclass 23, count 2 2006.211.07:40:09.97#ibcon#end of sib2, iclass 23, count 2 2006.211.07:40:09.97#ibcon#*mode == 0, iclass 23, count 2 2006.211.07:40:09.97#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.07:40:09.97#ibcon#[25=AT08-07\r\n] 2006.211.07:40:09.97#ibcon#*before write, iclass 23, count 2 2006.211.07:40:09.97#ibcon#enter sib2, iclass 23, count 2 2006.211.07:40:09.97#ibcon#flushed, iclass 23, count 2 2006.211.07:40:09.97#ibcon#about to write, iclass 23, count 2 2006.211.07:40:09.97#ibcon#wrote, iclass 23, count 2 2006.211.07:40:09.97#ibcon#about to read 3, iclass 23, count 2 2006.211.07:40:10.00#ibcon#read 3, iclass 23, count 2 2006.211.07:40:10.00#ibcon#about to read 4, iclass 23, count 2 2006.211.07:40:10.00#ibcon#read 4, iclass 23, count 2 2006.211.07:40:10.00#ibcon#about to read 5, iclass 23, count 2 2006.211.07:40:10.00#ibcon#read 5, iclass 23, count 2 2006.211.07:40:10.00#ibcon#about to read 6, iclass 23, count 2 2006.211.07:40:10.00#ibcon#read 6, iclass 23, count 2 2006.211.07:40:10.00#ibcon#end of sib2, iclass 23, count 2 2006.211.07:40:10.00#ibcon#*after write, iclass 23, count 2 2006.211.07:40:10.00#ibcon#*before return 0, iclass 23, count 2 2006.211.07:40:10.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:40:10.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:40:10.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.07:40:10.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:10.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:40:10.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:40:10.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:40:10.12#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:40:10.12#ibcon#first serial, iclass 23, count 0 2006.211.07:40:10.12#ibcon#enter sib2, iclass 23, count 0 2006.211.07:40:10.12#ibcon#flushed, iclass 23, count 0 2006.211.07:40:10.12#ibcon#about to write, iclass 23, count 0 2006.211.07:40:10.12#ibcon#wrote, iclass 23, count 0 2006.211.07:40:10.12#ibcon#about to read 3, iclass 23, count 0 2006.211.07:40:10.14#ibcon#read 3, iclass 23, count 0 2006.211.07:40:10.14#ibcon#about to read 4, iclass 23, count 0 2006.211.07:40:10.14#ibcon#read 4, iclass 23, count 0 2006.211.07:40:10.14#ibcon#about to read 5, iclass 23, count 0 2006.211.07:40:10.14#ibcon#read 5, iclass 23, count 0 2006.211.07:40:10.14#ibcon#about to read 6, iclass 23, count 0 2006.211.07:40:10.14#ibcon#read 6, iclass 23, count 0 2006.211.07:40:10.14#ibcon#end of sib2, iclass 23, count 0 2006.211.07:40:10.14#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:40:10.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:40:10.14#ibcon#[25=USB\r\n] 2006.211.07:40:10.14#ibcon#*before write, iclass 23, count 0 2006.211.07:40:10.14#ibcon#enter sib2, iclass 23, count 0 2006.211.07:40:10.14#ibcon#flushed, iclass 23, count 0 2006.211.07:40:10.14#ibcon#about to write, iclass 23, count 0 2006.211.07:40:10.14#ibcon#wrote, iclass 23, count 0 2006.211.07:40:10.14#ibcon#about to read 3, iclass 23, count 0 2006.211.07:40:10.17#ibcon#read 3, iclass 23, count 0 2006.211.07:40:10.17#ibcon#about to read 4, iclass 23, count 0 2006.211.07:40:10.17#ibcon#read 4, iclass 23, count 0 2006.211.07:40:10.17#ibcon#about to read 5, iclass 23, count 0 2006.211.07:40:10.17#ibcon#read 5, iclass 23, count 0 2006.211.07:40:10.17#ibcon#about to read 6, iclass 23, count 0 2006.211.07:40:10.17#ibcon#read 6, iclass 23, count 0 2006.211.07:40:10.17#ibcon#end of sib2, iclass 23, count 0 2006.211.07:40:10.17#ibcon#*after write, iclass 23, count 0 2006.211.07:40:10.17#ibcon#*before return 0, iclass 23, count 0 2006.211.07:40:10.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:40:10.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:40:10.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:40:10.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:40:10.17$vc4f8/vblo=1,632.99 2006.211.07:40:10.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:40:10.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:40:10.17#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:10.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:40:10.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:40:10.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:40:10.17#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:40:10.17#ibcon#first serial, iclass 25, count 0 2006.211.07:40:10.17#ibcon#enter sib2, iclass 25, count 0 2006.211.07:40:10.17#ibcon#flushed, iclass 25, count 0 2006.211.07:40:10.17#ibcon#about to write, iclass 25, count 0 2006.211.07:40:10.17#ibcon#wrote, iclass 25, count 0 2006.211.07:40:10.17#ibcon#about to read 3, iclass 25, count 0 2006.211.07:40:10.19#ibcon#read 3, iclass 25, count 0 2006.211.07:40:10.19#ibcon#about to read 4, iclass 25, count 0 2006.211.07:40:10.19#ibcon#read 4, iclass 25, count 0 2006.211.07:40:10.19#ibcon#about to read 5, iclass 25, count 0 2006.211.07:40:10.19#ibcon#read 5, iclass 25, count 0 2006.211.07:40:10.19#ibcon#about to read 6, iclass 25, count 0 2006.211.07:40:10.19#ibcon#read 6, iclass 25, count 0 2006.211.07:40:10.19#ibcon#end of sib2, iclass 25, count 0 2006.211.07:40:10.19#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:40:10.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:40:10.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:40:10.19#ibcon#*before write, iclass 25, count 0 2006.211.07:40:10.19#ibcon#enter sib2, iclass 25, count 0 2006.211.07:40:10.19#ibcon#flushed, iclass 25, count 0 2006.211.07:40:10.19#ibcon#about to write, iclass 25, count 0 2006.211.07:40:10.19#ibcon#wrote, iclass 25, count 0 2006.211.07:40:10.19#ibcon#about to read 3, iclass 25, count 0 2006.211.07:40:10.23#ibcon#read 3, iclass 25, count 0 2006.211.07:40:10.23#ibcon#about to read 4, iclass 25, count 0 2006.211.07:40:10.23#ibcon#read 4, iclass 25, count 0 2006.211.07:40:10.23#ibcon#about to read 5, iclass 25, count 0 2006.211.07:40:10.23#ibcon#read 5, iclass 25, count 0 2006.211.07:40:10.23#ibcon#about to read 6, iclass 25, count 0 2006.211.07:40:10.23#ibcon#read 6, iclass 25, count 0 2006.211.07:40:10.23#ibcon#end of sib2, iclass 25, count 0 2006.211.07:40:10.23#ibcon#*after write, iclass 25, count 0 2006.211.07:40:10.23#ibcon#*before return 0, iclass 25, count 0 2006.211.07:40:10.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:40:10.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:40:10.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:40:10.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:40:10.23$vc4f8/vb=1,4 2006.211.07:40:10.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.07:40:10.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.07:40:10.23#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:10.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:40:10.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:40:10.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:40:10.23#ibcon#enter wrdev, iclass 27, count 2 2006.211.07:40:10.23#ibcon#first serial, iclass 27, count 2 2006.211.07:40:10.23#ibcon#enter sib2, iclass 27, count 2 2006.211.07:40:10.23#ibcon#flushed, iclass 27, count 2 2006.211.07:40:10.23#ibcon#about to write, iclass 27, count 2 2006.211.07:40:10.23#ibcon#wrote, iclass 27, count 2 2006.211.07:40:10.23#ibcon#about to read 3, iclass 27, count 2 2006.211.07:40:10.25#ibcon#read 3, iclass 27, count 2 2006.211.07:40:10.25#ibcon#about to read 4, iclass 27, count 2 2006.211.07:40:10.25#ibcon#read 4, iclass 27, count 2 2006.211.07:40:10.25#ibcon#about to read 5, iclass 27, count 2 2006.211.07:40:10.25#ibcon#read 5, iclass 27, count 2 2006.211.07:40:10.25#ibcon#about to read 6, iclass 27, count 2 2006.211.07:40:10.25#ibcon#read 6, iclass 27, count 2 2006.211.07:40:10.25#ibcon#end of sib2, iclass 27, count 2 2006.211.07:40:10.25#ibcon#*mode == 0, iclass 27, count 2 2006.211.07:40:10.25#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.07:40:10.25#ibcon#[27=AT01-04\r\n] 2006.211.07:40:10.25#ibcon#*before write, iclass 27, count 2 2006.211.07:40:10.25#ibcon#enter sib2, iclass 27, count 2 2006.211.07:40:10.25#ibcon#flushed, iclass 27, count 2 2006.211.07:40:10.25#ibcon#about to write, iclass 27, count 2 2006.211.07:40:10.25#ibcon#wrote, iclass 27, count 2 2006.211.07:40:10.25#ibcon#about to read 3, iclass 27, count 2 2006.211.07:40:10.28#ibcon#read 3, iclass 27, count 2 2006.211.07:40:10.28#ibcon#about to read 4, iclass 27, count 2 2006.211.07:40:10.28#ibcon#read 4, iclass 27, count 2 2006.211.07:40:10.28#ibcon#about to read 5, iclass 27, count 2 2006.211.07:40:10.28#ibcon#read 5, iclass 27, count 2 2006.211.07:40:10.28#ibcon#about to read 6, iclass 27, count 2 2006.211.07:40:10.28#ibcon#read 6, iclass 27, count 2 2006.211.07:40:10.28#ibcon#end of sib2, iclass 27, count 2 2006.211.07:40:10.28#ibcon#*after write, iclass 27, count 2 2006.211.07:40:10.28#ibcon#*before return 0, iclass 27, count 2 2006.211.07:40:10.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:40:10.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:40:10.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.07:40:10.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:10.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:40:10.40#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:40:10.40#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:40:10.40#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:40:10.40#ibcon#first serial, iclass 27, count 0 2006.211.07:40:10.40#ibcon#enter sib2, iclass 27, count 0 2006.211.07:40:10.40#ibcon#flushed, iclass 27, count 0 2006.211.07:40:10.40#ibcon#about to write, iclass 27, count 0 2006.211.07:40:10.40#ibcon#wrote, iclass 27, count 0 2006.211.07:40:10.40#ibcon#about to read 3, iclass 27, count 0 2006.211.07:40:10.42#ibcon#read 3, iclass 27, count 0 2006.211.07:40:10.42#ibcon#about to read 4, iclass 27, count 0 2006.211.07:40:10.42#ibcon#read 4, iclass 27, count 0 2006.211.07:40:10.42#ibcon#about to read 5, iclass 27, count 0 2006.211.07:40:10.42#ibcon#read 5, iclass 27, count 0 2006.211.07:40:10.42#ibcon#about to read 6, iclass 27, count 0 2006.211.07:40:10.42#ibcon#read 6, iclass 27, count 0 2006.211.07:40:10.42#ibcon#end of sib2, iclass 27, count 0 2006.211.07:40:10.42#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:40:10.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:40:10.42#ibcon#[27=USB\r\n] 2006.211.07:40:10.42#ibcon#*before write, iclass 27, count 0 2006.211.07:40:10.42#ibcon#enter sib2, iclass 27, count 0 2006.211.07:40:10.42#ibcon#flushed, iclass 27, count 0 2006.211.07:40:10.42#ibcon#about to write, iclass 27, count 0 2006.211.07:40:10.42#ibcon#wrote, iclass 27, count 0 2006.211.07:40:10.42#ibcon#about to read 3, iclass 27, count 0 2006.211.07:40:10.45#ibcon#read 3, iclass 27, count 0 2006.211.07:40:10.45#ibcon#about to read 4, iclass 27, count 0 2006.211.07:40:10.45#ibcon#read 4, iclass 27, count 0 2006.211.07:40:10.45#ibcon#about to read 5, iclass 27, count 0 2006.211.07:40:10.45#ibcon#read 5, iclass 27, count 0 2006.211.07:40:10.45#ibcon#about to read 6, iclass 27, count 0 2006.211.07:40:10.45#ibcon#read 6, iclass 27, count 0 2006.211.07:40:10.45#ibcon#end of sib2, iclass 27, count 0 2006.211.07:40:10.45#ibcon#*after write, iclass 27, count 0 2006.211.07:40:10.45#ibcon#*before return 0, iclass 27, count 0 2006.211.07:40:10.45#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:40:10.45#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:40:10.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:40:10.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:40:10.45$vc4f8/vblo=2,640.99 2006.211.07:40:10.45#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:40:10.45#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:40:10.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:10.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:10.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:10.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:10.45#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:40:10.45#ibcon#first serial, iclass 29, count 0 2006.211.07:40:10.45#ibcon#enter sib2, iclass 29, count 0 2006.211.07:40:10.45#ibcon#flushed, iclass 29, count 0 2006.211.07:40:10.45#ibcon#about to write, iclass 29, count 0 2006.211.07:40:10.45#ibcon#wrote, iclass 29, count 0 2006.211.07:40:10.45#ibcon#about to read 3, iclass 29, count 0 2006.211.07:40:10.47#ibcon#read 3, iclass 29, count 0 2006.211.07:40:10.47#ibcon#about to read 4, iclass 29, count 0 2006.211.07:40:10.47#ibcon#read 4, iclass 29, count 0 2006.211.07:40:10.47#ibcon#about to read 5, iclass 29, count 0 2006.211.07:40:10.47#ibcon#read 5, iclass 29, count 0 2006.211.07:40:10.47#ibcon#about to read 6, iclass 29, count 0 2006.211.07:40:10.47#ibcon#read 6, iclass 29, count 0 2006.211.07:40:10.47#ibcon#end of sib2, iclass 29, count 0 2006.211.07:40:10.47#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:40:10.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:40:10.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:40:10.47#ibcon#*before write, iclass 29, count 0 2006.211.07:40:10.47#ibcon#enter sib2, iclass 29, count 0 2006.211.07:40:10.47#ibcon#flushed, iclass 29, count 0 2006.211.07:40:10.47#ibcon#about to write, iclass 29, count 0 2006.211.07:40:10.47#ibcon#wrote, iclass 29, count 0 2006.211.07:40:10.47#ibcon#about to read 3, iclass 29, count 0 2006.211.07:40:10.51#ibcon#read 3, iclass 29, count 0 2006.211.07:40:10.51#ibcon#about to read 4, iclass 29, count 0 2006.211.07:40:10.51#ibcon#read 4, iclass 29, count 0 2006.211.07:40:10.51#ibcon#about to read 5, iclass 29, count 0 2006.211.07:40:10.51#ibcon#read 5, iclass 29, count 0 2006.211.07:40:10.51#ibcon#about to read 6, iclass 29, count 0 2006.211.07:40:10.51#ibcon#read 6, iclass 29, count 0 2006.211.07:40:10.51#ibcon#end of sib2, iclass 29, count 0 2006.211.07:40:10.51#ibcon#*after write, iclass 29, count 0 2006.211.07:40:10.51#ibcon#*before return 0, iclass 29, count 0 2006.211.07:40:10.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:10.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:40:10.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:40:10.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:40:10.51$vc4f8/vb=2,4 2006.211.07:40:10.51#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:40:10.51#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:40:10.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:10.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:10.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:10.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:10.57#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:40:10.57#ibcon#first serial, iclass 31, count 2 2006.211.07:40:10.57#ibcon#enter sib2, iclass 31, count 2 2006.211.07:40:10.57#ibcon#flushed, iclass 31, count 2 2006.211.07:40:10.57#ibcon#about to write, iclass 31, count 2 2006.211.07:40:10.57#ibcon#wrote, iclass 31, count 2 2006.211.07:40:10.57#ibcon#about to read 3, iclass 31, count 2 2006.211.07:40:10.59#ibcon#read 3, iclass 31, count 2 2006.211.07:40:10.59#ibcon#about to read 4, iclass 31, count 2 2006.211.07:40:10.59#ibcon#read 4, iclass 31, count 2 2006.211.07:40:10.59#ibcon#about to read 5, iclass 31, count 2 2006.211.07:40:10.59#ibcon#read 5, iclass 31, count 2 2006.211.07:40:10.59#ibcon#about to read 6, iclass 31, count 2 2006.211.07:40:10.59#ibcon#read 6, iclass 31, count 2 2006.211.07:40:10.59#ibcon#end of sib2, iclass 31, count 2 2006.211.07:40:10.59#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:40:10.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:40:10.59#ibcon#[27=AT02-04\r\n] 2006.211.07:40:10.59#ibcon#*before write, iclass 31, count 2 2006.211.07:40:10.59#ibcon#enter sib2, iclass 31, count 2 2006.211.07:40:10.59#ibcon#flushed, iclass 31, count 2 2006.211.07:40:10.59#ibcon#about to write, iclass 31, count 2 2006.211.07:40:10.59#ibcon#wrote, iclass 31, count 2 2006.211.07:40:10.59#ibcon#about to read 3, iclass 31, count 2 2006.211.07:40:10.62#ibcon#read 3, iclass 31, count 2 2006.211.07:40:10.62#ibcon#about to read 4, iclass 31, count 2 2006.211.07:40:10.62#ibcon#read 4, iclass 31, count 2 2006.211.07:40:10.62#ibcon#about to read 5, iclass 31, count 2 2006.211.07:40:10.62#ibcon#read 5, iclass 31, count 2 2006.211.07:40:10.62#ibcon#about to read 6, iclass 31, count 2 2006.211.07:40:10.62#ibcon#read 6, iclass 31, count 2 2006.211.07:40:10.62#ibcon#end of sib2, iclass 31, count 2 2006.211.07:40:10.62#ibcon#*after write, iclass 31, count 2 2006.211.07:40:10.62#ibcon#*before return 0, iclass 31, count 2 2006.211.07:40:10.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:10.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:40:10.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:40:10.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:10.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:10.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:10.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:10.74#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:40:10.74#ibcon#first serial, iclass 31, count 0 2006.211.07:40:10.74#ibcon#enter sib2, iclass 31, count 0 2006.211.07:40:10.74#ibcon#flushed, iclass 31, count 0 2006.211.07:40:10.74#ibcon#about to write, iclass 31, count 0 2006.211.07:40:10.74#ibcon#wrote, iclass 31, count 0 2006.211.07:40:10.74#ibcon#about to read 3, iclass 31, count 0 2006.211.07:40:10.76#ibcon#read 3, iclass 31, count 0 2006.211.07:40:10.76#ibcon#about to read 4, iclass 31, count 0 2006.211.07:40:10.76#ibcon#read 4, iclass 31, count 0 2006.211.07:40:10.76#ibcon#about to read 5, iclass 31, count 0 2006.211.07:40:10.76#ibcon#read 5, iclass 31, count 0 2006.211.07:40:10.76#ibcon#about to read 6, iclass 31, count 0 2006.211.07:40:10.76#ibcon#read 6, iclass 31, count 0 2006.211.07:40:10.76#ibcon#end of sib2, iclass 31, count 0 2006.211.07:40:10.76#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:40:10.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:40:10.76#ibcon#[27=USB\r\n] 2006.211.07:40:10.76#ibcon#*before write, iclass 31, count 0 2006.211.07:40:10.76#ibcon#enter sib2, iclass 31, count 0 2006.211.07:40:10.76#ibcon#flushed, iclass 31, count 0 2006.211.07:40:10.76#ibcon#about to write, iclass 31, count 0 2006.211.07:40:10.76#ibcon#wrote, iclass 31, count 0 2006.211.07:40:10.76#ibcon#about to read 3, iclass 31, count 0 2006.211.07:40:10.79#ibcon#read 3, iclass 31, count 0 2006.211.07:40:10.79#ibcon#about to read 4, iclass 31, count 0 2006.211.07:40:10.79#ibcon#read 4, iclass 31, count 0 2006.211.07:40:10.79#ibcon#about to read 5, iclass 31, count 0 2006.211.07:40:10.79#ibcon#read 5, iclass 31, count 0 2006.211.07:40:10.79#ibcon#about to read 6, iclass 31, count 0 2006.211.07:40:10.79#ibcon#read 6, iclass 31, count 0 2006.211.07:40:10.79#ibcon#end of sib2, iclass 31, count 0 2006.211.07:40:10.79#ibcon#*after write, iclass 31, count 0 2006.211.07:40:10.79#ibcon#*before return 0, iclass 31, count 0 2006.211.07:40:10.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:10.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:40:10.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:40:10.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:40:10.79$vc4f8/vblo=3,656.99 2006.211.07:40:10.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:40:10.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:40:10.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:10.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:10.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:10.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:10.79#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:40:10.79#ibcon#first serial, iclass 33, count 0 2006.211.07:40:10.79#ibcon#enter sib2, iclass 33, count 0 2006.211.07:40:10.79#ibcon#flushed, iclass 33, count 0 2006.211.07:40:10.79#ibcon#about to write, iclass 33, count 0 2006.211.07:40:10.79#ibcon#wrote, iclass 33, count 0 2006.211.07:40:10.79#ibcon#about to read 3, iclass 33, count 0 2006.211.07:40:10.81#ibcon#read 3, iclass 33, count 0 2006.211.07:40:10.81#ibcon#about to read 4, iclass 33, count 0 2006.211.07:40:10.81#ibcon#read 4, iclass 33, count 0 2006.211.07:40:10.81#ibcon#about to read 5, iclass 33, count 0 2006.211.07:40:10.81#ibcon#read 5, iclass 33, count 0 2006.211.07:40:10.81#ibcon#about to read 6, iclass 33, count 0 2006.211.07:40:10.81#ibcon#read 6, iclass 33, count 0 2006.211.07:40:10.81#ibcon#end of sib2, iclass 33, count 0 2006.211.07:40:10.81#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:40:10.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:40:10.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:40:10.81#ibcon#*before write, iclass 33, count 0 2006.211.07:40:10.81#ibcon#enter sib2, iclass 33, count 0 2006.211.07:40:10.81#ibcon#flushed, iclass 33, count 0 2006.211.07:40:10.81#ibcon#about to write, iclass 33, count 0 2006.211.07:40:10.81#ibcon#wrote, iclass 33, count 0 2006.211.07:40:10.81#ibcon#about to read 3, iclass 33, count 0 2006.211.07:40:10.85#ibcon#read 3, iclass 33, count 0 2006.211.07:40:10.85#ibcon#about to read 4, iclass 33, count 0 2006.211.07:40:10.85#ibcon#read 4, iclass 33, count 0 2006.211.07:40:10.85#ibcon#about to read 5, iclass 33, count 0 2006.211.07:40:10.85#ibcon#read 5, iclass 33, count 0 2006.211.07:40:10.85#ibcon#about to read 6, iclass 33, count 0 2006.211.07:40:10.85#ibcon#read 6, iclass 33, count 0 2006.211.07:40:10.85#ibcon#end of sib2, iclass 33, count 0 2006.211.07:40:10.85#ibcon#*after write, iclass 33, count 0 2006.211.07:40:10.85#ibcon#*before return 0, iclass 33, count 0 2006.211.07:40:10.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:10.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:40:10.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:40:10.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:40:10.85$vc4f8/vb=3,3 2006.211.07:40:10.85#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:40:10.85#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:40:10.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:10.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:10.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:10.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:10.91#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:40:10.91#ibcon#first serial, iclass 35, count 2 2006.211.07:40:10.91#ibcon#enter sib2, iclass 35, count 2 2006.211.07:40:10.91#ibcon#flushed, iclass 35, count 2 2006.211.07:40:10.91#ibcon#about to write, iclass 35, count 2 2006.211.07:40:10.91#ibcon#wrote, iclass 35, count 2 2006.211.07:40:10.91#ibcon#about to read 3, iclass 35, count 2 2006.211.07:40:10.93#ibcon#read 3, iclass 35, count 2 2006.211.07:40:10.93#ibcon#about to read 4, iclass 35, count 2 2006.211.07:40:10.93#ibcon#read 4, iclass 35, count 2 2006.211.07:40:10.93#ibcon#about to read 5, iclass 35, count 2 2006.211.07:40:10.93#ibcon#read 5, iclass 35, count 2 2006.211.07:40:10.93#ibcon#about to read 6, iclass 35, count 2 2006.211.07:40:10.93#ibcon#read 6, iclass 35, count 2 2006.211.07:40:10.93#ibcon#end of sib2, iclass 35, count 2 2006.211.07:40:10.93#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:40:10.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:40:10.93#ibcon#[27=AT03-03\r\n] 2006.211.07:40:10.93#ibcon#*before write, iclass 35, count 2 2006.211.07:40:10.93#ibcon#enter sib2, iclass 35, count 2 2006.211.07:40:10.93#ibcon#flushed, iclass 35, count 2 2006.211.07:40:10.93#ibcon#about to write, iclass 35, count 2 2006.211.07:40:10.93#ibcon#wrote, iclass 35, count 2 2006.211.07:40:10.93#ibcon#about to read 3, iclass 35, count 2 2006.211.07:40:10.96#ibcon#read 3, iclass 35, count 2 2006.211.07:40:10.96#ibcon#about to read 4, iclass 35, count 2 2006.211.07:40:10.96#ibcon#read 4, iclass 35, count 2 2006.211.07:40:10.96#ibcon#about to read 5, iclass 35, count 2 2006.211.07:40:10.96#ibcon#read 5, iclass 35, count 2 2006.211.07:40:10.96#ibcon#about to read 6, iclass 35, count 2 2006.211.07:40:10.96#ibcon#read 6, iclass 35, count 2 2006.211.07:40:10.96#ibcon#end of sib2, iclass 35, count 2 2006.211.07:40:10.96#ibcon#*after write, iclass 35, count 2 2006.211.07:40:10.96#ibcon#*before return 0, iclass 35, count 2 2006.211.07:40:10.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:10.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:40:10.96#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:40:10.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:10.96#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:11.08#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:11.08#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:11.08#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:40:11.08#ibcon#first serial, iclass 35, count 0 2006.211.07:40:11.08#ibcon#enter sib2, iclass 35, count 0 2006.211.07:40:11.08#ibcon#flushed, iclass 35, count 0 2006.211.07:40:11.08#ibcon#about to write, iclass 35, count 0 2006.211.07:40:11.08#ibcon#wrote, iclass 35, count 0 2006.211.07:40:11.08#ibcon#about to read 3, iclass 35, count 0 2006.211.07:40:11.10#ibcon#read 3, iclass 35, count 0 2006.211.07:40:11.10#ibcon#about to read 4, iclass 35, count 0 2006.211.07:40:11.10#ibcon#read 4, iclass 35, count 0 2006.211.07:40:11.10#ibcon#about to read 5, iclass 35, count 0 2006.211.07:40:11.10#ibcon#read 5, iclass 35, count 0 2006.211.07:40:11.10#ibcon#about to read 6, iclass 35, count 0 2006.211.07:40:11.10#ibcon#read 6, iclass 35, count 0 2006.211.07:40:11.10#ibcon#end of sib2, iclass 35, count 0 2006.211.07:40:11.10#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:40:11.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:40:11.10#ibcon#[27=USB\r\n] 2006.211.07:40:11.10#ibcon#*before write, iclass 35, count 0 2006.211.07:40:11.10#ibcon#enter sib2, iclass 35, count 0 2006.211.07:40:11.10#ibcon#flushed, iclass 35, count 0 2006.211.07:40:11.10#ibcon#about to write, iclass 35, count 0 2006.211.07:40:11.10#ibcon#wrote, iclass 35, count 0 2006.211.07:40:11.10#ibcon#about to read 3, iclass 35, count 0 2006.211.07:40:11.13#ibcon#read 3, iclass 35, count 0 2006.211.07:40:11.13#ibcon#about to read 4, iclass 35, count 0 2006.211.07:40:11.13#ibcon#read 4, iclass 35, count 0 2006.211.07:40:11.13#ibcon#about to read 5, iclass 35, count 0 2006.211.07:40:11.13#ibcon#read 5, iclass 35, count 0 2006.211.07:40:11.13#ibcon#about to read 6, iclass 35, count 0 2006.211.07:40:11.13#ibcon#read 6, iclass 35, count 0 2006.211.07:40:11.13#ibcon#end of sib2, iclass 35, count 0 2006.211.07:40:11.13#ibcon#*after write, iclass 35, count 0 2006.211.07:40:11.13#ibcon#*before return 0, iclass 35, count 0 2006.211.07:40:11.13#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:11.13#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:40:11.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:40:11.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:40:11.13$vc4f8/vblo=4,712.99 2006.211.07:40:11.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:40:11.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:40:11.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:11.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:11.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:11.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:11.13#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:40:11.13#ibcon#first serial, iclass 37, count 0 2006.211.07:40:11.13#ibcon#enter sib2, iclass 37, count 0 2006.211.07:40:11.13#ibcon#flushed, iclass 37, count 0 2006.211.07:40:11.13#ibcon#about to write, iclass 37, count 0 2006.211.07:40:11.13#ibcon#wrote, iclass 37, count 0 2006.211.07:40:11.13#ibcon#about to read 3, iclass 37, count 0 2006.211.07:40:11.15#ibcon#read 3, iclass 37, count 0 2006.211.07:40:11.15#ibcon#about to read 4, iclass 37, count 0 2006.211.07:40:11.15#ibcon#read 4, iclass 37, count 0 2006.211.07:40:11.15#ibcon#about to read 5, iclass 37, count 0 2006.211.07:40:11.15#ibcon#read 5, iclass 37, count 0 2006.211.07:40:11.15#ibcon#about to read 6, iclass 37, count 0 2006.211.07:40:11.15#ibcon#read 6, iclass 37, count 0 2006.211.07:40:11.15#ibcon#end of sib2, iclass 37, count 0 2006.211.07:40:11.15#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:40:11.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:40:11.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:40:11.15#ibcon#*before write, iclass 37, count 0 2006.211.07:40:11.15#ibcon#enter sib2, iclass 37, count 0 2006.211.07:40:11.15#ibcon#flushed, iclass 37, count 0 2006.211.07:40:11.15#ibcon#about to write, iclass 37, count 0 2006.211.07:40:11.15#ibcon#wrote, iclass 37, count 0 2006.211.07:40:11.15#ibcon#about to read 3, iclass 37, count 0 2006.211.07:40:11.19#ibcon#read 3, iclass 37, count 0 2006.211.07:40:11.19#ibcon#about to read 4, iclass 37, count 0 2006.211.07:40:11.19#ibcon#read 4, iclass 37, count 0 2006.211.07:40:11.19#ibcon#about to read 5, iclass 37, count 0 2006.211.07:40:11.19#ibcon#read 5, iclass 37, count 0 2006.211.07:40:11.19#ibcon#about to read 6, iclass 37, count 0 2006.211.07:40:11.19#ibcon#read 6, iclass 37, count 0 2006.211.07:40:11.19#ibcon#end of sib2, iclass 37, count 0 2006.211.07:40:11.19#ibcon#*after write, iclass 37, count 0 2006.211.07:40:11.19#ibcon#*before return 0, iclass 37, count 0 2006.211.07:40:11.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:11.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:40:11.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:40:11.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:40:11.19$vc4f8/vb=4,3 2006.211.07:40:11.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:40:11.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:40:11.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:11.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:11.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:11.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:11.25#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:40:11.25#ibcon#first serial, iclass 39, count 2 2006.211.07:40:11.25#ibcon#enter sib2, iclass 39, count 2 2006.211.07:40:11.25#ibcon#flushed, iclass 39, count 2 2006.211.07:40:11.25#ibcon#about to write, iclass 39, count 2 2006.211.07:40:11.25#ibcon#wrote, iclass 39, count 2 2006.211.07:40:11.25#ibcon#about to read 3, iclass 39, count 2 2006.211.07:40:11.27#ibcon#read 3, iclass 39, count 2 2006.211.07:40:11.27#ibcon#about to read 4, iclass 39, count 2 2006.211.07:40:11.27#ibcon#read 4, iclass 39, count 2 2006.211.07:40:11.27#ibcon#about to read 5, iclass 39, count 2 2006.211.07:40:11.27#ibcon#read 5, iclass 39, count 2 2006.211.07:40:11.27#ibcon#about to read 6, iclass 39, count 2 2006.211.07:40:11.27#ibcon#read 6, iclass 39, count 2 2006.211.07:40:11.27#ibcon#end of sib2, iclass 39, count 2 2006.211.07:40:11.27#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:40:11.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:40:11.27#ibcon#[27=AT04-03\r\n] 2006.211.07:40:11.27#ibcon#*before write, iclass 39, count 2 2006.211.07:40:11.27#ibcon#enter sib2, iclass 39, count 2 2006.211.07:40:11.27#ibcon#flushed, iclass 39, count 2 2006.211.07:40:11.27#ibcon#about to write, iclass 39, count 2 2006.211.07:40:11.27#ibcon#wrote, iclass 39, count 2 2006.211.07:40:11.27#ibcon#about to read 3, iclass 39, count 2 2006.211.07:40:11.30#ibcon#read 3, iclass 39, count 2 2006.211.07:40:11.30#ibcon#about to read 4, iclass 39, count 2 2006.211.07:40:11.30#ibcon#read 4, iclass 39, count 2 2006.211.07:40:11.30#ibcon#about to read 5, iclass 39, count 2 2006.211.07:40:11.30#ibcon#read 5, iclass 39, count 2 2006.211.07:40:11.30#ibcon#about to read 6, iclass 39, count 2 2006.211.07:40:11.30#ibcon#read 6, iclass 39, count 2 2006.211.07:40:11.30#ibcon#end of sib2, iclass 39, count 2 2006.211.07:40:11.30#ibcon#*after write, iclass 39, count 2 2006.211.07:40:11.30#ibcon#*before return 0, iclass 39, count 2 2006.211.07:40:11.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:11.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:40:11.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:40:11.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:11.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:11.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:11.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:11.42#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:40:11.42#ibcon#first serial, iclass 39, count 0 2006.211.07:40:11.42#ibcon#enter sib2, iclass 39, count 0 2006.211.07:40:11.42#ibcon#flushed, iclass 39, count 0 2006.211.07:40:11.42#ibcon#about to write, iclass 39, count 0 2006.211.07:40:11.42#ibcon#wrote, iclass 39, count 0 2006.211.07:40:11.42#ibcon#about to read 3, iclass 39, count 0 2006.211.07:40:11.44#ibcon#read 3, iclass 39, count 0 2006.211.07:40:11.44#ibcon#about to read 4, iclass 39, count 0 2006.211.07:40:11.44#ibcon#read 4, iclass 39, count 0 2006.211.07:40:11.44#ibcon#about to read 5, iclass 39, count 0 2006.211.07:40:11.44#ibcon#read 5, iclass 39, count 0 2006.211.07:40:11.44#ibcon#about to read 6, iclass 39, count 0 2006.211.07:40:11.44#ibcon#read 6, iclass 39, count 0 2006.211.07:40:11.44#ibcon#end of sib2, iclass 39, count 0 2006.211.07:40:11.44#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:40:11.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:40:11.44#ibcon#[27=USB\r\n] 2006.211.07:40:11.44#ibcon#*before write, iclass 39, count 0 2006.211.07:40:11.44#ibcon#enter sib2, iclass 39, count 0 2006.211.07:40:11.44#ibcon#flushed, iclass 39, count 0 2006.211.07:40:11.44#ibcon#about to write, iclass 39, count 0 2006.211.07:40:11.44#ibcon#wrote, iclass 39, count 0 2006.211.07:40:11.44#ibcon#about to read 3, iclass 39, count 0 2006.211.07:40:11.47#ibcon#read 3, iclass 39, count 0 2006.211.07:40:11.47#ibcon#about to read 4, iclass 39, count 0 2006.211.07:40:11.47#ibcon#read 4, iclass 39, count 0 2006.211.07:40:11.47#ibcon#about to read 5, iclass 39, count 0 2006.211.07:40:11.47#ibcon#read 5, iclass 39, count 0 2006.211.07:40:11.47#ibcon#about to read 6, iclass 39, count 0 2006.211.07:40:11.47#ibcon#read 6, iclass 39, count 0 2006.211.07:40:11.47#ibcon#end of sib2, iclass 39, count 0 2006.211.07:40:11.47#ibcon#*after write, iclass 39, count 0 2006.211.07:40:11.47#ibcon#*before return 0, iclass 39, count 0 2006.211.07:40:11.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:11.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:40:11.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:40:11.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:40:11.47$vc4f8/vblo=5,744.99 2006.211.07:40:11.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:40:11.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:40:11.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:11.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:11.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:11.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:11.47#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:40:11.47#ibcon#first serial, iclass 3, count 0 2006.211.07:40:11.47#ibcon#enter sib2, iclass 3, count 0 2006.211.07:40:11.47#ibcon#flushed, iclass 3, count 0 2006.211.07:40:11.47#ibcon#about to write, iclass 3, count 0 2006.211.07:40:11.47#ibcon#wrote, iclass 3, count 0 2006.211.07:40:11.47#ibcon#about to read 3, iclass 3, count 0 2006.211.07:40:11.49#ibcon#read 3, iclass 3, count 0 2006.211.07:40:11.49#ibcon#about to read 4, iclass 3, count 0 2006.211.07:40:11.49#ibcon#read 4, iclass 3, count 0 2006.211.07:40:11.49#ibcon#about to read 5, iclass 3, count 0 2006.211.07:40:11.49#ibcon#read 5, iclass 3, count 0 2006.211.07:40:11.49#ibcon#about to read 6, iclass 3, count 0 2006.211.07:40:11.49#ibcon#read 6, iclass 3, count 0 2006.211.07:40:11.49#ibcon#end of sib2, iclass 3, count 0 2006.211.07:40:11.49#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:40:11.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:40:11.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:40:11.49#ibcon#*before write, iclass 3, count 0 2006.211.07:40:11.49#ibcon#enter sib2, iclass 3, count 0 2006.211.07:40:11.49#ibcon#flushed, iclass 3, count 0 2006.211.07:40:11.49#ibcon#about to write, iclass 3, count 0 2006.211.07:40:11.49#ibcon#wrote, iclass 3, count 0 2006.211.07:40:11.49#ibcon#about to read 3, iclass 3, count 0 2006.211.07:40:11.53#ibcon#read 3, iclass 3, count 0 2006.211.07:40:11.53#ibcon#about to read 4, iclass 3, count 0 2006.211.07:40:11.53#ibcon#read 4, iclass 3, count 0 2006.211.07:40:11.53#ibcon#about to read 5, iclass 3, count 0 2006.211.07:40:11.53#ibcon#read 5, iclass 3, count 0 2006.211.07:40:11.53#ibcon#about to read 6, iclass 3, count 0 2006.211.07:40:11.53#ibcon#read 6, iclass 3, count 0 2006.211.07:40:11.53#ibcon#end of sib2, iclass 3, count 0 2006.211.07:40:11.53#ibcon#*after write, iclass 3, count 0 2006.211.07:40:11.53#ibcon#*before return 0, iclass 3, count 0 2006.211.07:40:11.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:11.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:40:11.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:40:11.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:40:11.53$vc4f8/vb=5,3 2006.211.07:40:11.53#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:40:11.53#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:40:11.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:11.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:11.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:11.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:11.59#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:40:11.59#ibcon#first serial, iclass 5, count 2 2006.211.07:40:11.59#ibcon#enter sib2, iclass 5, count 2 2006.211.07:40:11.59#ibcon#flushed, iclass 5, count 2 2006.211.07:40:11.59#ibcon#about to write, iclass 5, count 2 2006.211.07:40:11.59#ibcon#wrote, iclass 5, count 2 2006.211.07:40:11.59#ibcon#about to read 3, iclass 5, count 2 2006.211.07:40:11.61#ibcon#read 3, iclass 5, count 2 2006.211.07:40:11.61#ibcon#about to read 4, iclass 5, count 2 2006.211.07:40:11.61#ibcon#read 4, iclass 5, count 2 2006.211.07:40:11.61#ibcon#about to read 5, iclass 5, count 2 2006.211.07:40:11.61#ibcon#read 5, iclass 5, count 2 2006.211.07:40:11.61#ibcon#about to read 6, iclass 5, count 2 2006.211.07:40:11.61#ibcon#read 6, iclass 5, count 2 2006.211.07:40:11.61#ibcon#end of sib2, iclass 5, count 2 2006.211.07:40:11.61#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:40:11.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:40:11.61#ibcon#[27=AT05-03\r\n] 2006.211.07:40:11.61#ibcon#*before write, iclass 5, count 2 2006.211.07:40:11.61#ibcon#enter sib2, iclass 5, count 2 2006.211.07:40:11.61#ibcon#flushed, iclass 5, count 2 2006.211.07:40:11.61#ibcon#about to write, iclass 5, count 2 2006.211.07:40:11.61#ibcon#wrote, iclass 5, count 2 2006.211.07:40:11.61#ibcon#about to read 3, iclass 5, count 2 2006.211.07:40:11.64#ibcon#read 3, iclass 5, count 2 2006.211.07:40:11.64#ibcon#about to read 4, iclass 5, count 2 2006.211.07:40:11.64#ibcon#read 4, iclass 5, count 2 2006.211.07:40:11.64#ibcon#about to read 5, iclass 5, count 2 2006.211.07:40:11.64#ibcon#read 5, iclass 5, count 2 2006.211.07:40:11.64#ibcon#about to read 6, iclass 5, count 2 2006.211.07:40:11.64#ibcon#read 6, iclass 5, count 2 2006.211.07:40:11.64#ibcon#end of sib2, iclass 5, count 2 2006.211.07:40:11.64#ibcon#*after write, iclass 5, count 2 2006.211.07:40:11.64#ibcon#*before return 0, iclass 5, count 2 2006.211.07:40:11.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:11.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:40:11.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:40:11.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:11.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:11.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:11.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:11.76#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:40:11.76#ibcon#first serial, iclass 5, count 0 2006.211.07:40:11.76#ibcon#enter sib2, iclass 5, count 0 2006.211.07:40:11.76#ibcon#flushed, iclass 5, count 0 2006.211.07:40:11.76#ibcon#about to write, iclass 5, count 0 2006.211.07:40:11.76#ibcon#wrote, iclass 5, count 0 2006.211.07:40:11.76#ibcon#about to read 3, iclass 5, count 0 2006.211.07:40:11.78#ibcon#read 3, iclass 5, count 0 2006.211.07:40:11.78#ibcon#about to read 4, iclass 5, count 0 2006.211.07:40:11.78#ibcon#read 4, iclass 5, count 0 2006.211.07:40:11.78#ibcon#about to read 5, iclass 5, count 0 2006.211.07:40:11.78#ibcon#read 5, iclass 5, count 0 2006.211.07:40:11.78#ibcon#about to read 6, iclass 5, count 0 2006.211.07:40:11.78#ibcon#read 6, iclass 5, count 0 2006.211.07:40:11.78#ibcon#end of sib2, iclass 5, count 0 2006.211.07:40:11.78#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:40:11.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:40:11.78#ibcon#[27=USB\r\n] 2006.211.07:40:11.78#ibcon#*before write, iclass 5, count 0 2006.211.07:40:11.78#ibcon#enter sib2, iclass 5, count 0 2006.211.07:40:11.78#ibcon#flushed, iclass 5, count 0 2006.211.07:40:11.78#ibcon#about to write, iclass 5, count 0 2006.211.07:40:11.78#ibcon#wrote, iclass 5, count 0 2006.211.07:40:11.78#ibcon#about to read 3, iclass 5, count 0 2006.211.07:40:11.81#ibcon#read 3, iclass 5, count 0 2006.211.07:40:11.81#ibcon#about to read 4, iclass 5, count 0 2006.211.07:40:11.81#ibcon#read 4, iclass 5, count 0 2006.211.07:40:11.81#ibcon#about to read 5, iclass 5, count 0 2006.211.07:40:11.81#ibcon#read 5, iclass 5, count 0 2006.211.07:40:11.81#ibcon#about to read 6, iclass 5, count 0 2006.211.07:40:11.81#ibcon#read 6, iclass 5, count 0 2006.211.07:40:11.81#ibcon#end of sib2, iclass 5, count 0 2006.211.07:40:11.81#ibcon#*after write, iclass 5, count 0 2006.211.07:40:11.81#ibcon#*before return 0, iclass 5, count 0 2006.211.07:40:11.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:11.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:40:11.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:40:11.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:40:11.81$vc4f8/vblo=6,752.99 2006.211.07:40:11.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:40:11.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:40:11.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:40:11.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:11.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:11.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:11.81#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:40:11.81#ibcon#first serial, iclass 7, count 0 2006.211.07:40:11.81#ibcon#enter sib2, iclass 7, count 0 2006.211.07:40:11.81#ibcon#flushed, iclass 7, count 0 2006.211.07:40:11.81#ibcon#about to write, iclass 7, count 0 2006.211.07:40:11.81#ibcon#wrote, iclass 7, count 0 2006.211.07:40:11.81#ibcon#about to read 3, iclass 7, count 0 2006.211.07:40:11.83#ibcon#read 3, iclass 7, count 0 2006.211.07:40:11.83#ibcon#about to read 4, iclass 7, count 0 2006.211.07:40:11.83#ibcon#read 4, iclass 7, count 0 2006.211.07:40:11.83#ibcon#about to read 5, iclass 7, count 0 2006.211.07:40:11.83#ibcon#read 5, iclass 7, count 0 2006.211.07:40:11.83#ibcon#about to read 6, iclass 7, count 0 2006.211.07:40:11.83#ibcon#read 6, iclass 7, count 0 2006.211.07:40:11.83#ibcon#end of sib2, iclass 7, count 0 2006.211.07:40:11.83#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:40:11.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:40:11.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:40:11.83#ibcon#*before write, iclass 7, count 0 2006.211.07:40:11.83#ibcon#enter sib2, iclass 7, count 0 2006.211.07:40:11.83#ibcon#flushed, iclass 7, count 0 2006.211.07:40:11.83#ibcon#about to write, iclass 7, count 0 2006.211.07:40:11.83#ibcon#wrote, iclass 7, count 0 2006.211.07:40:11.83#ibcon#about to read 3, iclass 7, count 0 2006.211.07:40:11.87#ibcon#read 3, iclass 7, count 0 2006.211.07:40:11.87#ibcon#about to read 4, iclass 7, count 0 2006.211.07:40:11.87#ibcon#read 4, iclass 7, count 0 2006.211.07:40:11.87#ibcon#about to read 5, iclass 7, count 0 2006.211.07:40:11.87#ibcon#read 5, iclass 7, count 0 2006.211.07:40:11.87#ibcon#about to read 6, iclass 7, count 0 2006.211.07:40:11.87#ibcon#read 6, iclass 7, count 0 2006.211.07:40:11.87#ibcon#end of sib2, iclass 7, count 0 2006.211.07:40:11.87#ibcon#*after write, iclass 7, count 0 2006.211.07:40:11.87#ibcon#*before return 0, iclass 7, count 0 2006.211.07:40:11.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:11.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:40:11.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:40:11.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:40:11.87$vc4f8/vb=6,3 2006.211.07:40:11.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:40:11.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:40:11.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:40:11.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:11.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:11.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:11.93#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:40:11.93#ibcon#first serial, iclass 11, count 2 2006.211.07:40:11.93#ibcon#enter sib2, iclass 11, count 2 2006.211.07:40:11.93#ibcon#flushed, iclass 11, count 2 2006.211.07:40:11.93#ibcon#about to write, iclass 11, count 2 2006.211.07:40:11.93#ibcon#wrote, iclass 11, count 2 2006.211.07:40:11.93#ibcon#about to read 3, iclass 11, count 2 2006.211.07:40:11.95#ibcon#read 3, iclass 11, count 2 2006.211.07:40:11.95#ibcon#about to read 4, iclass 11, count 2 2006.211.07:40:11.95#ibcon#read 4, iclass 11, count 2 2006.211.07:40:11.95#ibcon#about to read 5, iclass 11, count 2 2006.211.07:40:11.95#ibcon#read 5, iclass 11, count 2 2006.211.07:40:11.95#ibcon#about to read 6, iclass 11, count 2 2006.211.07:40:11.95#ibcon#read 6, iclass 11, count 2 2006.211.07:40:11.95#ibcon#end of sib2, iclass 11, count 2 2006.211.07:40:11.95#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:40:11.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:40:11.95#ibcon#[27=AT06-03\r\n] 2006.211.07:40:11.95#ibcon#*before write, iclass 11, count 2 2006.211.07:40:11.95#ibcon#enter sib2, iclass 11, count 2 2006.211.07:40:11.95#ibcon#flushed, iclass 11, count 2 2006.211.07:40:11.95#ibcon#about to write, iclass 11, count 2 2006.211.07:40:11.95#ibcon#wrote, iclass 11, count 2 2006.211.07:40:11.95#ibcon#about to read 3, iclass 11, count 2 2006.211.07:40:11.98#ibcon#read 3, iclass 11, count 2 2006.211.07:40:11.98#ibcon#about to read 4, iclass 11, count 2 2006.211.07:40:11.98#ibcon#read 4, iclass 11, count 2 2006.211.07:40:11.98#ibcon#about to read 5, iclass 11, count 2 2006.211.07:40:11.98#ibcon#read 5, iclass 11, count 2 2006.211.07:40:11.98#ibcon#about to read 6, iclass 11, count 2 2006.211.07:40:11.98#ibcon#read 6, iclass 11, count 2 2006.211.07:40:11.98#ibcon#end of sib2, iclass 11, count 2 2006.211.07:40:11.98#ibcon#*after write, iclass 11, count 2 2006.211.07:40:11.98#ibcon#*before return 0, iclass 11, count 2 2006.211.07:40:11.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:11.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:40:11.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:40:11.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:40:11.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:12.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:12.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:12.10#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:40:12.10#ibcon#first serial, iclass 11, count 0 2006.211.07:40:12.10#ibcon#enter sib2, iclass 11, count 0 2006.211.07:40:12.10#ibcon#flushed, iclass 11, count 0 2006.211.07:40:12.10#ibcon#about to write, iclass 11, count 0 2006.211.07:40:12.10#ibcon#wrote, iclass 11, count 0 2006.211.07:40:12.10#ibcon#about to read 3, iclass 11, count 0 2006.211.07:40:12.12#ibcon#read 3, iclass 11, count 0 2006.211.07:40:12.12#ibcon#about to read 4, iclass 11, count 0 2006.211.07:40:12.12#ibcon#read 4, iclass 11, count 0 2006.211.07:40:12.12#ibcon#about to read 5, iclass 11, count 0 2006.211.07:40:12.12#ibcon#read 5, iclass 11, count 0 2006.211.07:40:12.12#ibcon#about to read 6, iclass 11, count 0 2006.211.07:40:12.12#ibcon#read 6, iclass 11, count 0 2006.211.07:40:12.12#ibcon#end of sib2, iclass 11, count 0 2006.211.07:40:12.12#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:40:12.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:40:12.12#ibcon#[27=USB\r\n] 2006.211.07:40:12.12#ibcon#*before write, iclass 11, count 0 2006.211.07:40:12.12#ibcon#enter sib2, iclass 11, count 0 2006.211.07:40:12.12#ibcon#flushed, iclass 11, count 0 2006.211.07:40:12.12#ibcon#about to write, iclass 11, count 0 2006.211.07:40:12.12#ibcon#wrote, iclass 11, count 0 2006.211.07:40:12.12#ibcon#about to read 3, iclass 11, count 0 2006.211.07:40:12.15#ibcon#read 3, iclass 11, count 0 2006.211.07:40:12.15#ibcon#about to read 4, iclass 11, count 0 2006.211.07:40:12.15#ibcon#read 4, iclass 11, count 0 2006.211.07:40:12.15#ibcon#about to read 5, iclass 11, count 0 2006.211.07:40:12.15#ibcon#read 5, iclass 11, count 0 2006.211.07:40:12.15#ibcon#about to read 6, iclass 11, count 0 2006.211.07:40:12.15#ibcon#read 6, iclass 11, count 0 2006.211.07:40:12.15#ibcon#end of sib2, iclass 11, count 0 2006.211.07:40:12.15#ibcon#*after write, iclass 11, count 0 2006.211.07:40:12.15#ibcon#*before return 0, iclass 11, count 0 2006.211.07:40:12.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:12.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:40:12.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:40:12.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:40:12.15$vc4f8/vabw=wide 2006.211.07:40:12.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:40:12.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:40:12.15#ibcon#ireg 8 cls_cnt 0 2006.211.07:40:12.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:12.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:12.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:12.15#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:40:12.15#ibcon#first serial, iclass 13, count 0 2006.211.07:40:12.15#ibcon#enter sib2, iclass 13, count 0 2006.211.07:40:12.15#ibcon#flushed, iclass 13, count 0 2006.211.07:40:12.15#ibcon#about to write, iclass 13, count 0 2006.211.07:40:12.15#ibcon#wrote, iclass 13, count 0 2006.211.07:40:12.15#ibcon#about to read 3, iclass 13, count 0 2006.211.07:40:12.17#ibcon#read 3, iclass 13, count 0 2006.211.07:40:12.17#ibcon#about to read 4, iclass 13, count 0 2006.211.07:40:12.17#ibcon#read 4, iclass 13, count 0 2006.211.07:40:12.17#ibcon#about to read 5, iclass 13, count 0 2006.211.07:40:12.17#ibcon#read 5, iclass 13, count 0 2006.211.07:40:12.17#ibcon#about to read 6, iclass 13, count 0 2006.211.07:40:12.17#ibcon#read 6, iclass 13, count 0 2006.211.07:40:12.17#ibcon#end of sib2, iclass 13, count 0 2006.211.07:40:12.17#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:40:12.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:40:12.17#ibcon#[25=BW32\r\n] 2006.211.07:40:12.17#ibcon#*before write, iclass 13, count 0 2006.211.07:40:12.17#ibcon#enter sib2, iclass 13, count 0 2006.211.07:40:12.17#ibcon#flushed, iclass 13, count 0 2006.211.07:40:12.17#ibcon#about to write, iclass 13, count 0 2006.211.07:40:12.17#ibcon#wrote, iclass 13, count 0 2006.211.07:40:12.17#ibcon#about to read 3, iclass 13, count 0 2006.211.07:40:12.20#ibcon#read 3, iclass 13, count 0 2006.211.07:40:12.20#ibcon#about to read 4, iclass 13, count 0 2006.211.07:40:12.20#ibcon#read 4, iclass 13, count 0 2006.211.07:40:12.20#ibcon#about to read 5, iclass 13, count 0 2006.211.07:40:12.20#ibcon#read 5, iclass 13, count 0 2006.211.07:40:12.20#ibcon#about to read 6, iclass 13, count 0 2006.211.07:40:12.20#ibcon#read 6, iclass 13, count 0 2006.211.07:40:12.20#ibcon#end of sib2, iclass 13, count 0 2006.211.07:40:12.20#ibcon#*after write, iclass 13, count 0 2006.211.07:40:12.20#ibcon#*before return 0, iclass 13, count 0 2006.211.07:40:12.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:12.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:40:12.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:40:12.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:40:12.20$vc4f8/vbbw=wide 2006.211.07:40:12.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:40:12.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:40:12.20#ibcon#ireg 8 cls_cnt 0 2006.211.07:40:12.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:40:12.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:40:12.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:40:12.27#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:40:12.27#ibcon#first serial, iclass 15, count 0 2006.211.07:40:12.27#ibcon#enter sib2, iclass 15, count 0 2006.211.07:40:12.27#ibcon#flushed, iclass 15, count 0 2006.211.07:40:12.27#ibcon#about to write, iclass 15, count 0 2006.211.07:40:12.27#ibcon#wrote, iclass 15, count 0 2006.211.07:40:12.27#ibcon#about to read 3, iclass 15, count 0 2006.211.07:40:12.29#ibcon#read 3, iclass 15, count 0 2006.211.07:40:12.29#ibcon#about to read 4, iclass 15, count 0 2006.211.07:40:12.29#ibcon#read 4, iclass 15, count 0 2006.211.07:40:12.29#ibcon#about to read 5, iclass 15, count 0 2006.211.07:40:12.29#ibcon#read 5, iclass 15, count 0 2006.211.07:40:12.29#ibcon#about to read 6, iclass 15, count 0 2006.211.07:40:12.29#ibcon#read 6, iclass 15, count 0 2006.211.07:40:12.29#ibcon#end of sib2, iclass 15, count 0 2006.211.07:40:12.29#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:40:12.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:40:12.29#ibcon#[27=BW32\r\n] 2006.211.07:40:12.29#ibcon#*before write, iclass 15, count 0 2006.211.07:40:12.29#ibcon#enter sib2, iclass 15, count 0 2006.211.07:40:12.29#ibcon#flushed, iclass 15, count 0 2006.211.07:40:12.29#ibcon#about to write, iclass 15, count 0 2006.211.07:40:12.29#ibcon#wrote, iclass 15, count 0 2006.211.07:40:12.29#ibcon#about to read 3, iclass 15, count 0 2006.211.07:40:12.32#ibcon#read 3, iclass 15, count 0 2006.211.07:40:12.32#ibcon#about to read 4, iclass 15, count 0 2006.211.07:40:12.32#ibcon#read 4, iclass 15, count 0 2006.211.07:40:12.32#ibcon#about to read 5, iclass 15, count 0 2006.211.07:40:12.32#ibcon#read 5, iclass 15, count 0 2006.211.07:40:12.32#ibcon#about to read 6, iclass 15, count 0 2006.211.07:40:12.32#ibcon#read 6, iclass 15, count 0 2006.211.07:40:12.32#ibcon#end of sib2, iclass 15, count 0 2006.211.07:40:12.32#ibcon#*after write, iclass 15, count 0 2006.211.07:40:12.32#ibcon#*before return 0, iclass 15, count 0 2006.211.07:40:12.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:40:12.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:40:12.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:40:12.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:40:12.32$4f8m12a/ifd4f 2006.211.07:40:12.32$ifd4f/lo= 2006.211.07:40:12.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:40:12.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:40:12.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:40:12.32$ifd4f/patch= 2006.211.07:40:12.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:40:12.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:40:12.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:40:12.32$4f8m12a/"form=m,16.000,1:2 2006.211.07:40:12.32$4f8m12a/"tpicd 2006.211.07:40:12.32$4f8m12a/echo=off 2006.211.07:40:12.32$4f8m12a/xlog=off 2006.211.07:40:12.32:!2006.211.07:40:40 2006.211.07:40:19.14#trakl#Source acquired 2006.211.07:40:19.14#flagr#flagr/antenna,acquired 2006.211.07:40:40.00:preob 2006.211.07:40:41.14/onsource/TRACKING 2006.211.07:40:41.14:!2006.211.07:40:50 2006.211.07:40:50.00:data_valid=on 2006.211.07:40:50.00:midob 2006.211.07:40:50.14/onsource/TRACKING 2006.211.07:40:50.14/wx/24.95,1010.1,75 2006.211.07:40:50.38/cable/+6.4388E-03 2006.211.07:40:51.47/va/01,08,usb,yes,28,29 2006.211.07:40:51.47/va/02,07,usb,yes,28,29 2006.211.07:40:51.47/va/03,06,usb,yes,29,30 2006.211.07:40:51.47/va/04,07,usb,yes,29,31 2006.211.07:40:51.47/va/05,07,usb,yes,31,33 2006.211.07:40:51.47/va/06,06,usb,yes,30,30 2006.211.07:40:51.47/va/07,06,usb,yes,31,31 2006.211.07:40:51.47/va/08,07,usb,yes,29,29 2006.211.07:40:51.70/valo/01,532.99,yes,locked 2006.211.07:40:51.70/valo/02,572.99,yes,locked 2006.211.07:40:51.70/valo/03,672.99,yes,locked 2006.211.07:40:51.70/valo/04,832.99,yes,locked 2006.211.07:40:51.70/valo/05,652.99,yes,locked 2006.211.07:40:51.70/valo/06,772.99,yes,locked 2006.211.07:40:51.70/valo/07,832.99,yes,locked 2006.211.07:40:51.70/valo/08,852.99,yes,locked 2006.211.07:40:52.79/vb/01,04,usb,yes,28,27 2006.211.07:40:52.79/vb/02,04,usb,yes,30,31 2006.211.07:40:52.79/vb/03,03,usb,yes,32,37 2006.211.07:40:52.79/vb/04,03,usb,yes,33,34 2006.211.07:40:52.79/vb/05,03,usb,yes,32,36 2006.211.07:40:52.79/vb/06,03,usb,yes,33,36 2006.211.07:40:52.79/vb/07,04,usb,yes,28,28 2006.211.07:40:52.79/vb/08,03,usb,yes,33,36 2006.211.07:40:53.02/vblo/01,632.99,yes,locked 2006.211.07:40:53.02/vblo/02,640.99,yes,locked 2006.211.07:40:53.02/vblo/03,656.99,yes,locked 2006.211.07:40:53.02/vblo/04,712.99,yes,locked 2006.211.07:40:53.02/vblo/05,744.99,yes,locked 2006.211.07:40:53.02/vblo/06,752.99,yes,locked 2006.211.07:40:53.02/vblo/07,734.99,yes,locked 2006.211.07:40:53.02/vblo/08,744.99,yes,locked 2006.211.07:40:53.17/vabw/8 2006.211.07:40:53.32/vbbw/8 2006.211.07:40:53.41/xfe/off,on,12.5 2006.211.07:40:53.79/ifatt/23,28,28,28 2006.211.07:40:54.08/fmout-gps/S +4.48E-07 2006.211.07:40:54.12:!2006.211.07:41:50 2006.211.07:41:35.14#trakl#Off source 2006.211.07:41:35.14?ERROR st -7 Antenna off-source! 2006.211.07:41:35.14#trakl#az 20.234 el 70.015 azerr*cos(el) 0.0000 elerr 0.0215 2006.211.07:41:37.14#flagr#flagr/antenna,off-source 2006.211.07:41:41.14#trakl#Source re-acquired 2006.211.07:41:43.14#flagr#flagr/antenna,re-acquired 2006.211.07:41:50.00:data_valid=off 2006.211.07:41:50.00:postob 2006.211.07:41:50.23/cable/+6.4377E-03 2006.211.07:41:50.23/wx/24.95,1010.1,75 2006.211.07:41:51.08/fmout-gps/S +4.48E-07 2006.211.07:41:51.08:scan_name=211-0742,k06211,60 2006.211.07:41:51.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.211.07:41:51.14#flagr#flagr/antenna,new-source 2006.211.07:41:52.14:checkk5 2006.211.07:41:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:41:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:41:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:41:53.52/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:41:53.84/chk_obsdata//k5ts1/T2110740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:41:54.18/chk_obsdata//k5ts2/T2110740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:41:54.52/chk_obsdata//k5ts3/T2110740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:41:54.85/chk_obsdata//k5ts4/T2110740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:41:55.50/k5log//k5ts1_log_newline 2006.211.07:41:56.16/k5log//k5ts2_log_newline 2006.211.07:41:56.82/k5log//k5ts3_log_newline 2006.211.07:41:57.47/k5log//k5ts4_log_newline 2006.211.07:41:57.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:41:57.49:4f8m12a=1 2006.211.07:41:57.49$4f8m12a/echo=on 2006.211.07:41:57.49$4f8m12a/pcalon 2006.211.07:41:57.49$pcalon/"no phase cal control is implemented here 2006.211.07:41:57.49$4f8m12a/"tpicd=stop 2006.211.07:41:57.49$4f8m12a/vc4f8 2006.211.07:41:57.49$vc4f8/valo=1,532.99 2006.211.07:41:57.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.07:41:57.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.07:41:57.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:57.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:41:57.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:41:57.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:41:57.49#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:41:57.49#ibcon#first serial, iclass 28, count 0 2006.211.07:41:57.49#ibcon#enter sib2, iclass 28, count 0 2006.211.07:41:57.49#ibcon#flushed, iclass 28, count 0 2006.211.07:41:57.49#ibcon#about to write, iclass 28, count 0 2006.211.07:41:57.49#ibcon#wrote, iclass 28, count 0 2006.211.07:41:57.49#ibcon#about to read 3, iclass 28, count 0 2006.211.07:41:57.51#ibcon#read 3, iclass 28, count 0 2006.211.07:41:57.51#ibcon#about to read 4, iclass 28, count 0 2006.211.07:41:57.51#ibcon#read 4, iclass 28, count 0 2006.211.07:41:57.51#ibcon#about to read 5, iclass 28, count 0 2006.211.07:41:57.51#ibcon#read 5, iclass 28, count 0 2006.211.07:41:57.51#ibcon#about to read 6, iclass 28, count 0 2006.211.07:41:57.51#ibcon#read 6, iclass 28, count 0 2006.211.07:41:57.51#ibcon#end of sib2, iclass 28, count 0 2006.211.07:41:57.51#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:41:57.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:41:57.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:41:57.51#ibcon#*before write, iclass 28, count 0 2006.211.07:41:57.51#ibcon#enter sib2, iclass 28, count 0 2006.211.07:41:57.51#ibcon#flushed, iclass 28, count 0 2006.211.07:41:57.51#ibcon#about to write, iclass 28, count 0 2006.211.07:41:57.51#ibcon#wrote, iclass 28, count 0 2006.211.07:41:57.51#ibcon#about to read 3, iclass 28, count 0 2006.211.07:41:57.56#ibcon#read 3, iclass 28, count 0 2006.211.07:41:57.56#ibcon#about to read 4, iclass 28, count 0 2006.211.07:41:57.56#ibcon#read 4, iclass 28, count 0 2006.211.07:41:57.56#ibcon#about to read 5, iclass 28, count 0 2006.211.07:41:57.56#ibcon#read 5, iclass 28, count 0 2006.211.07:41:57.56#ibcon#about to read 6, iclass 28, count 0 2006.211.07:41:57.56#ibcon#read 6, iclass 28, count 0 2006.211.07:41:57.56#ibcon#end of sib2, iclass 28, count 0 2006.211.07:41:57.56#ibcon#*after write, iclass 28, count 0 2006.211.07:41:57.56#ibcon#*before return 0, iclass 28, count 0 2006.211.07:41:57.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:41:57.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:41:57.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:41:57.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:41:57.56$vc4f8/va=1,8 2006.211.07:41:57.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.07:41:57.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.07:41:57.56#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:57.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:41:57.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:41:57.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:41:57.56#ibcon#enter wrdev, iclass 30, count 2 2006.211.07:41:57.56#ibcon#first serial, iclass 30, count 2 2006.211.07:41:57.56#ibcon#enter sib2, iclass 30, count 2 2006.211.07:41:57.56#ibcon#flushed, iclass 30, count 2 2006.211.07:41:57.56#ibcon#about to write, iclass 30, count 2 2006.211.07:41:57.56#ibcon#wrote, iclass 30, count 2 2006.211.07:41:57.56#ibcon#about to read 3, iclass 30, count 2 2006.211.07:41:57.58#ibcon#read 3, iclass 30, count 2 2006.211.07:41:57.58#ibcon#about to read 4, iclass 30, count 2 2006.211.07:41:57.58#ibcon#read 4, iclass 30, count 2 2006.211.07:41:57.58#ibcon#about to read 5, iclass 30, count 2 2006.211.07:41:57.58#ibcon#read 5, iclass 30, count 2 2006.211.07:41:57.58#ibcon#about to read 6, iclass 30, count 2 2006.211.07:41:57.58#ibcon#read 6, iclass 30, count 2 2006.211.07:41:57.58#ibcon#end of sib2, iclass 30, count 2 2006.211.07:41:57.58#ibcon#*mode == 0, iclass 30, count 2 2006.211.07:41:57.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.07:41:57.58#ibcon#[25=AT01-08\r\n] 2006.211.07:41:57.58#ibcon#*before write, iclass 30, count 2 2006.211.07:41:57.58#ibcon#enter sib2, iclass 30, count 2 2006.211.07:41:57.58#ibcon#flushed, iclass 30, count 2 2006.211.07:41:57.58#ibcon#about to write, iclass 30, count 2 2006.211.07:41:57.58#ibcon#wrote, iclass 30, count 2 2006.211.07:41:57.58#ibcon#about to read 3, iclass 30, count 2 2006.211.07:41:57.61#ibcon#read 3, iclass 30, count 2 2006.211.07:41:57.61#ibcon#about to read 4, iclass 30, count 2 2006.211.07:41:57.61#ibcon#read 4, iclass 30, count 2 2006.211.07:41:57.61#ibcon#about to read 5, iclass 30, count 2 2006.211.07:41:57.61#ibcon#read 5, iclass 30, count 2 2006.211.07:41:57.61#ibcon#about to read 6, iclass 30, count 2 2006.211.07:41:57.61#ibcon#read 6, iclass 30, count 2 2006.211.07:41:57.61#ibcon#end of sib2, iclass 30, count 2 2006.211.07:41:57.61#ibcon#*after write, iclass 30, count 2 2006.211.07:41:57.61#ibcon#*before return 0, iclass 30, count 2 2006.211.07:41:57.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:41:57.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:41:57.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.07:41:57.61#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:57.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:41:57.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:41:57.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:41:57.73#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:41:57.73#ibcon#first serial, iclass 30, count 0 2006.211.07:41:57.73#ibcon#enter sib2, iclass 30, count 0 2006.211.07:41:57.73#ibcon#flushed, iclass 30, count 0 2006.211.07:41:57.73#ibcon#about to write, iclass 30, count 0 2006.211.07:41:57.73#ibcon#wrote, iclass 30, count 0 2006.211.07:41:57.73#ibcon#about to read 3, iclass 30, count 0 2006.211.07:41:57.75#ibcon#read 3, iclass 30, count 0 2006.211.07:41:57.75#ibcon#about to read 4, iclass 30, count 0 2006.211.07:41:57.75#ibcon#read 4, iclass 30, count 0 2006.211.07:41:57.75#ibcon#about to read 5, iclass 30, count 0 2006.211.07:41:57.75#ibcon#read 5, iclass 30, count 0 2006.211.07:41:57.75#ibcon#about to read 6, iclass 30, count 0 2006.211.07:41:57.75#ibcon#read 6, iclass 30, count 0 2006.211.07:41:57.75#ibcon#end of sib2, iclass 30, count 0 2006.211.07:41:57.75#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:41:57.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:41:57.75#ibcon#[25=USB\r\n] 2006.211.07:41:57.75#ibcon#*before write, iclass 30, count 0 2006.211.07:41:57.75#ibcon#enter sib2, iclass 30, count 0 2006.211.07:41:57.75#ibcon#flushed, iclass 30, count 0 2006.211.07:41:57.75#ibcon#about to write, iclass 30, count 0 2006.211.07:41:57.75#ibcon#wrote, iclass 30, count 0 2006.211.07:41:57.75#ibcon#about to read 3, iclass 30, count 0 2006.211.07:41:57.78#ibcon#read 3, iclass 30, count 0 2006.211.07:41:57.78#ibcon#about to read 4, iclass 30, count 0 2006.211.07:41:57.78#ibcon#read 4, iclass 30, count 0 2006.211.07:41:57.78#ibcon#about to read 5, iclass 30, count 0 2006.211.07:41:57.78#ibcon#read 5, iclass 30, count 0 2006.211.07:41:57.78#ibcon#about to read 6, iclass 30, count 0 2006.211.07:41:57.78#ibcon#read 6, iclass 30, count 0 2006.211.07:41:57.78#ibcon#end of sib2, iclass 30, count 0 2006.211.07:41:57.78#ibcon#*after write, iclass 30, count 0 2006.211.07:41:57.78#ibcon#*before return 0, iclass 30, count 0 2006.211.07:41:57.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:41:57.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:41:57.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:41:57.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:41:57.78$vc4f8/valo=2,572.99 2006.211.07:41:57.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:41:57.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:41:57.78#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:57.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:41:57.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:41:57.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:41:57.78#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:41:57.78#ibcon#first serial, iclass 32, count 0 2006.211.07:41:57.78#ibcon#enter sib2, iclass 32, count 0 2006.211.07:41:57.78#ibcon#flushed, iclass 32, count 0 2006.211.07:41:57.78#ibcon#about to write, iclass 32, count 0 2006.211.07:41:57.78#ibcon#wrote, iclass 32, count 0 2006.211.07:41:57.78#ibcon#about to read 3, iclass 32, count 0 2006.211.07:41:57.80#ibcon#read 3, iclass 32, count 0 2006.211.07:41:57.80#ibcon#about to read 4, iclass 32, count 0 2006.211.07:41:57.80#ibcon#read 4, iclass 32, count 0 2006.211.07:41:57.80#ibcon#about to read 5, iclass 32, count 0 2006.211.07:41:57.80#ibcon#read 5, iclass 32, count 0 2006.211.07:41:57.80#ibcon#about to read 6, iclass 32, count 0 2006.211.07:41:57.80#ibcon#read 6, iclass 32, count 0 2006.211.07:41:57.80#ibcon#end of sib2, iclass 32, count 0 2006.211.07:41:57.80#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:41:57.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:41:57.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:41:57.80#ibcon#*before write, iclass 32, count 0 2006.211.07:41:57.80#ibcon#enter sib2, iclass 32, count 0 2006.211.07:41:57.80#ibcon#flushed, iclass 32, count 0 2006.211.07:41:57.80#ibcon#about to write, iclass 32, count 0 2006.211.07:41:57.80#ibcon#wrote, iclass 32, count 0 2006.211.07:41:57.80#ibcon#about to read 3, iclass 32, count 0 2006.211.07:41:57.84#ibcon#read 3, iclass 32, count 0 2006.211.07:41:57.84#ibcon#about to read 4, iclass 32, count 0 2006.211.07:41:57.84#ibcon#read 4, iclass 32, count 0 2006.211.07:41:57.84#ibcon#about to read 5, iclass 32, count 0 2006.211.07:41:57.84#ibcon#read 5, iclass 32, count 0 2006.211.07:41:57.84#ibcon#about to read 6, iclass 32, count 0 2006.211.07:41:57.84#ibcon#read 6, iclass 32, count 0 2006.211.07:41:57.84#ibcon#end of sib2, iclass 32, count 0 2006.211.07:41:57.84#ibcon#*after write, iclass 32, count 0 2006.211.07:41:57.84#ibcon#*before return 0, iclass 32, count 0 2006.211.07:41:57.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:41:57.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:41:57.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:41:57.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:41:57.84$vc4f8/va=2,7 2006.211.07:41:57.84#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:41:57.84#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:41:57.84#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:57.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:41:57.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:41:57.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:41:57.90#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:41:57.90#ibcon#first serial, iclass 34, count 2 2006.211.07:41:57.90#ibcon#enter sib2, iclass 34, count 2 2006.211.07:41:57.90#ibcon#flushed, iclass 34, count 2 2006.211.07:41:57.90#ibcon#about to write, iclass 34, count 2 2006.211.07:41:57.90#ibcon#wrote, iclass 34, count 2 2006.211.07:41:57.90#ibcon#about to read 3, iclass 34, count 2 2006.211.07:41:57.92#ibcon#read 3, iclass 34, count 2 2006.211.07:41:57.92#ibcon#about to read 4, iclass 34, count 2 2006.211.07:41:57.92#ibcon#read 4, iclass 34, count 2 2006.211.07:41:57.92#ibcon#about to read 5, iclass 34, count 2 2006.211.07:41:57.92#ibcon#read 5, iclass 34, count 2 2006.211.07:41:57.92#ibcon#about to read 6, iclass 34, count 2 2006.211.07:41:57.92#ibcon#read 6, iclass 34, count 2 2006.211.07:41:57.92#ibcon#end of sib2, iclass 34, count 2 2006.211.07:41:57.92#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:41:57.92#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:41:57.92#ibcon#[25=AT02-07\r\n] 2006.211.07:41:57.92#ibcon#*before write, iclass 34, count 2 2006.211.07:41:57.92#ibcon#enter sib2, iclass 34, count 2 2006.211.07:41:57.92#ibcon#flushed, iclass 34, count 2 2006.211.07:41:57.92#ibcon#about to write, iclass 34, count 2 2006.211.07:41:57.92#ibcon#wrote, iclass 34, count 2 2006.211.07:41:57.92#ibcon#about to read 3, iclass 34, count 2 2006.211.07:41:57.95#ibcon#read 3, iclass 34, count 2 2006.211.07:41:57.95#ibcon#about to read 4, iclass 34, count 2 2006.211.07:41:57.95#ibcon#read 4, iclass 34, count 2 2006.211.07:41:57.95#ibcon#about to read 5, iclass 34, count 2 2006.211.07:41:57.95#ibcon#read 5, iclass 34, count 2 2006.211.07:41:57.95#ibcon#about to read 6, iclass 34, count 2 2006.211.07:41:57.95#ibcon#read 6, iclass 34, count 2 2006.211.07:41:57.95#ibcon#end of sib2, iclass 34, count 2 2006.211.07:41:57.95#ibcon#*after write, iclass 34, count 2 2006.211.07:41:57.95#ibcon#*before return 0, iclass 34, count 2 2006.211.07:41:57.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:41:57.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:41:57.95#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:41:57.95#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:57.95#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:41:58.07#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:41:58.07#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:41:58.07#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:41:58.07#ibcon#first serial, iclass 34, count 0 2006.211.07:41:58.07#ibcon#enter sib2, iclass 34, count 0 2006.211.07:41:58.07#ibcon#flushed, iclass 34, count 0 2006.211.07:41:58.07#ibcon#about to write, iclass 34, count 0 2006.211.07:41:58.07#ibcon#wrote, iclass 34, count 0 2006.211.07:41:58.07#ibcon#about to read 3, iclass 34, count 0 2006.211.07:41:58.09#ibcon#read 3, iclass 34, count 0 2006.211.07:41:58.09#ibcon#about to read 4, iclass 34, count 0 2006.211.07:41:58.09#ibcon#read 4, iclass 34, count 0 2006.211.07:41:58.09#ibcon#about to read 5, iclass 34, count 0 2006.211.07:41:58.09#ibcon#read 5, iclass 34, count 0 2006.211.07:41:58.09#ibcon#about to read 6, iclass 34, count 0 2006.211.07:41:58.09#ibcon#read 6, iclass 34, count 0 2006.211.07:41:58.09#ibcon#end of sib2, iclass 34, count 0 2006.211.07:41:58.09#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:41:58.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:41:58.09#ibcon#[25=USB\r\n] 2006.211.07:41:58.09#ibcon#*before write, iclass 34, count 0 2006.211.07:41:58.09#ibcon#enter sib2, iclass 34, count 0 2006.211.07:41:58.09#ibcon#flushed, iclass 34, count 0 2006.211.07:41:58.09#ibcon#about to write, iclass 34, count 0 2006.211.07:41:58.09#ibcon#wrote, iclass 34, count 0 2006.211.07:41:58.09#ibcon#about to read 3, iclass 34, count 0 2006.211.07:41:58.12#ibcon#read 3, iclass 34, count 0 2006.211.07:41:58.12#ibcon#about to read 4, iclass 34, count 0 2006.211.07:41:58.12#ibcon#read 4, iclass 34, count 0 2006.211.07:41:58.12#ibcon#about to read 5, iclass 34, count 0 2006.211.07:41:58.12#ibcon#read 5, iclass 34, count 0 2006.211.07:41:58.12#ibcon#about to read 6, iclass 34, count 0 2006.211.07:41:58.12#ibcon#read 6, iclass 34, count 0 2006.211.07:41:58.12#ibcon#end of sib2, iclass 34, count 0 2006.211.07:41:58.12#ibcon#*after write, iclass 34, count 0 2006.211.07:41:58.12#ibcon#*before return 0, iclass 34, count 0 2006.211.07:41:58.12#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:41:58.12#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:41:58.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:41:58.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:41:58.12$vc4f8/valo=3,672.99 2006.211.07:41:58.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.07:41:58.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.07:41:58.12#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:58.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:41:58.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:41:58.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:41:58.12#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:41:58.12#ibcon#first serial, iclass 36, count 0 2006.211.07:41:58.12#ibcon#enter sib2, iclass 36, count 0 2006.211.07:41:58.12#ibcon#flushed, iclass 36, count 0 2006.211.07:41:58.12#ibcon#about to write, iclass 36, count 0 2006.211.07:41:58.12#ibcon#wrote, iclass 36, count 0 2006.211.07:41:58.12#ibcon#about to read 3, iclass 36, count 0 2006.211.07:41:58.14#ibcon#read 3, iclass 36, count 0 2006.211.07:41:58.14#ibcon#about to read 4, iclass 36, count 0 2006.211.07:41:58.14#ibcon#read 4, iclass 36, count 0 2006.211.07:41:58.14#ibcon#about to read 5, iclass 36, count 0 2006.211.07:41:58.14#ibcon#read 5, iclass 36, count 0 2006.211.07:41:58.14#ibcon#about to read 6, iclass 36, count 0 2006.211.07:41:58.14#ibcon#read 6, iclass 36, count 0 2006.211.07:41:58.14#ibcon#end of sib2, iclass 36, count 0 2006.211.07:41:58.14#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:41:58.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:41:58.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:41:58.14#ibcon#*before write, iclass 36, count 0 2006.211.07:41:58.14#ibcon#enter sib2, iclass 36, count 0 2006.211.07:41:58.14#ibcon#flushed, iclass 36, count 0 2006.211.07:41:58.14#ibcon#about to write, iclass 36, count 0 2006.211.07:41:58.14#ibcon#wrote, iclass 36, count 0 2006.211.07:41:58.14#ibcon#about to read 3, iclass 36, count 0 2006.211.07:41:58.18#ibcon#read 3, iclass 36, count 0 2006.211.07:41:58.18#ibcon#about to read 4, iclass 36, count 0 2006.211.07:41:58.18#ibcon#read 4, iclass 36, count 0 2006.211.07:41:58.18#ibcon#about to read 5, iclass 36, count 0 2006.211.07:41:58.18#ibcon#read 5, iclass 36, count 0 2006.211.07:41:58.18#ibcon#about to read 6, iclass 36, count 0 2006.211.07:41:58.18#ibcon#read 6, iclass 36, count 0 2006.211.07:41:58.18#ibcon#end of sib2, iclass 36, count 0 2006.211.07:41:58.18#ibcon#*after write, iclass 36, count 0 2006.211.07:41:58.18#ibcon#*before return 0, iclass 36, count 0 2006.211.07:41:58.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:41:58.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:41:58.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:41:58.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:41:58.18$vc4f8/va=3,6 2006.211.07:41:58.18#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.07:41:58.18#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.07:41:58.18#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:58.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:41:58.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:41:58.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:41:58.24#ibcon#enter wrdev, iclass 38, count 2 2006.211.07:41:58.24#ibcon#first serial, iclass 38, count 2 2006.211.07:41:58.24#ibcon#enter sib2, iclass 38, count 2 2006.211.07:41:58.24#ibcon#flushed, iclass 38, count 2 2006.211.07:41:58.24#ibcon#about to write, iclass 38, count 2 2006.211.07:41:58.24#ibcon#wrote, iclass 38, count 2 2006.211.07:41:58.24#ibcon#about to read 3, iclass 38, count 2 2006.211.07:41:58.26#ibcon#read 3, iclass 38, count 2 2006.211.07:41:58.26#ibcon#about to read 4, iclass 38, count 2 2006.211.07:41:58.26#ibcon#read 4, iclass 38, count 2 2006.211.07:41:58.26#ibcon#about to read 5, iclass 38, count 2 2006.211.07:41:58.26#ibcon#read 5, iclass 38, count 2 2006.211.07:41:58.26#ibcon#about to read 6, iclass 38, count 2 2006.211.07:41:58.26#ibcon#read 6, iclass 38, count 2 2006.211.07:41:58.26#ibcon#end of sib2, iclass 38, count 2 2006.211.07:41:58.26#ibcon#*mode == 0, iclass 38, count 2 2006.211.07:41:58.26#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.07:41:58.26#ibcon#[25=AT03-06\r\n] 2006.211.07:41:58.26#ibcon#*before write, iclass 38, count 2 2006.211.07:41:58.26#ibcon#enter sib2, iclass 38, count 2 2006.211.07:41:58.26#ibcon#flushed, iclass 38, count 2 2006.211.07:41:58.26#ibcon#about to write, iclass 38, count 2 2006.211.07:41:58.26#ibcon#wrote, iclass 38, count 2 2006.211.07:41:58.26#ibcon#about to read 3, iclass 38, count 2 2006.211.07:41:58.29#ibcon#read 3, iclass 38, count 2 2006.211.07:41:58.29#ibcon#about to read 4, iclass 38, count 2 2006.211.07:41:58.29#ibcon#read 4, iclass 38, count 2 2006.211.07:41:58.29#ibcon#about to read 5, iclass 38, count 2 2006.211.07:41:58.29#ibcon#read 5, iclass 38, count 2 2006.211.07:41:58.29#ibcon#about to read 6, iclass 38, count 2 2006.211.07:41:58.29#ibcon#read 6, iclass 38, count 2 2006.211.07:41:58.29#ibcon#end of sib2, iclass 38, count 2 2006.211.07:41:58.29#ibcon#*after write, iclass 38, count 2 2006.211.07:41:58.29#ibcon#*before return 0, iclass 38, count 2 2006.211.07:41:58.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:41:58.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:41:58.29#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.07:41:58.29#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:58.29#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:41:58.41#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:41:58.41#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:41:58.41#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:41:58.41#ibcon#first serial, iclass 38, count 0 2006.211.07:41:58.41#ibcon#enter sib2, iclass 38, count 0 2006.211.07:41:58.41#ibcon#flushed, iclass 38, count 0 2006.211.07:41:58.41#ibcon#about to write, iclass 38, count 0 2006.211.07:41:58.41#ibcon#wrote, iclass 38, count 0 2006.211.07:41:58.41#ibcon#about to read 3, iclass 38, count 0 2006.211.07:41:58.43#ibcon#read 3, iclass 38, count 0 2006.211.07:41:58.43#ibcon#about to read 4, iclass 38, count 0 2006.211.07:41:58.43#ibcon#read 4, iclass 38, count 0 2006.211.07:41:58.43#ibcon#about to read 5, iclass 38, count 0 2006.211.07:41:58.43#ibcon#read 5, iclass 38, count 0 2006.211.07:41:58.43#ibcon#about to read 6, iclass 38, count 0 2006.211.07:41:58.43#ibcon#read 6, iclass 38, count 0 2006.211.07:41:58.43#ibcon#end of sib2, iclass 38, count 0 2006.211.07:41:58.43#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:41:58.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:41:58.43#ibcon#[25=USB\r\n] 2006.211.07:41:58.43#ibcon#*before write, iclass 38, count 0 2006.211.07:41:58.43#ibcon#enter sib2, iclass 38, count 0 2006.211.07:41:58.43#ibcon#flushed, iclass 38, count 0 2006.211.07:41:58.43#ibcon#about to write, iclass 38, count 0 2006.211.07:41:58.43#ibcon#wrote, iclass 38, count 0 2006.211.07:41:58.43#ibcon#about to read 3, iclass 38, count 0 2006.211.07:41:58.46#ibcon#read 3, iclass 38, count 0 2006.211.07:41:58.46#ibcon#about to read 4, iclass 38, count 0 2006.211.07:41:58.46#ibcon#read 4, iclass 38, count 0 2006.211.07:41:58.46#ibcon#about to read 5, iclass 38, count 0 2006.211.07:41:58.46#ibcon#read 5, iclass 38, count 0 2006.211.07:41:58.46#ibcon#about to read 6, iclass 38, count 0 2006.211.07:41:58.46#ibcon#read 6, iclass 38, count 0 2006.211.07:41:58.46#ibcon#end of sib2, iclass 38, count 0 2006.211.07:41:58.46#ibcon#*after write, iclass 38, count 0 2006.211.07:41:58.46#ibcon#*before return 0, iclass 38, count 0 2006.211.07:41:58.46#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:41:58.46#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:41:58.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:41:58.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:41:58.46$vc4f8/valo=4,832.99 2006.211.07:41:58.46#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:41:58.46#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:41:58.46#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:58.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:41:58.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:41:58.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:41:58.46#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:41:58.46#ibcon#first serial, iclass 40, count 0 2006.211.07:41:58.46#ibcon#enter sib2, iclass 40, count 0 2006.211.07:41:58.46#ibcon#flushed, iclass 40, count 0 2006.211.07:41:58.46#ibcon#about to write, iclass 40, count 0 2006.211.07:41:58.46#ibcon#wrote, iclass 40, count 0 2006.211.07:41:58.46#ibcon#about to read 3, iclass 40, count 0 2006.211.07:41:58.48#ibcon#read 3, iclass 40, count 0 2006.211.07:41:58.48#ibcon#about to read 4, iclass 40, count 0 2006.211.07:41:58.48#ibcon#read 4, iclass 40, count 0 2006.211.07:41:58.48#ibcon#about to read 5, iclass 40, count 0 2006.211.07:41:58.48#ibcon#read 5, iclass 40, count 0 2006.211.07:41:58.48#ibcon#about to read 6, iclass 40, count 0 2006.211.07:41:58.48#ibcon#read 6, iclass 40, count 0 2006.211.07:41:58.48#ibcon#end of sib2, iclass 40, count 0 2006.211.07:41:58.48#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:41:58.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:41:58.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:41:58.48#ibcon#*before write, iclass 40, count 0 2006.211.07:41:58.48#ibcon#enter sib2, iclass 40, count 0 2006.211.07:41:58.48#ibcon#flushed, iclass 40, count 0 2006.211.07:41:58.48#ibcon#about to write, iclass 40, count 0 2006.211.07:41:58.48#ibcon#wrote, iclass 40, count 0 2006.211.07:41:58.48#ibcon#about to read 3, iclass 40, count 0 2006.211.07:41:58.52#ibcon#read 3, iclass 40, count 0 2006.211.07:41:58.52#ibcon#about to read 4, iclass 40, count 0 2006.211.07:41:58.52#ibcon#read 4, iclass 40, count 0 2006.211.07:41:58.52#ibcon#about to read 5, iclass 40, count 0 2006.211.07:41:58.52#ibcon#read 5, iclass 40, count 0 2006.211.07:41:58.52#ibcon#about to read 6, iclass 40, count 0 2006.211.07:41:58.52#ibcon#read 6, iclass 40, count 0 2006.211.07:41:58.52#ibcon#end of sib2, iclass 40, count 0 2006.211.07:41:58.52#ibcon#*after write, iclass 40, count 0 2006.211.07:41:58.52#ibcon#*before return 0, iclass 40, count 0 2006.211.07:41:58.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:41:58.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:41:58.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:41:58.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:41:58.52$vc4f8/va=4,7 2006.211.07:41:58.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:41:58.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:41:58.52#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:58.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:41:58.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:41:58.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:41:58.58#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:41:58.58#ibcon#first serial, iclass 4, count 2 2006.211.07:41:58.58#ibcon#enter sib2, iclass 4, count 2 2006.211.07:41:58.58#ibcon#flushed, iclass 4, count 2 2006.211.07:41:58.58#ibcon#about to write, iclass 4, count 2 2006.211.07:41:58.58#ibcon#wrote, iclass 4, count 2 2006.211.07:41:58.58#ibcon#about to read 3, iclass 4, count 2 2006.211.07:41:58.60#ibcon#read 3, iclass 4, count 2 2006.211.07:41:58.60#ibcon#about to read 4, iclass 4, count 2 2006.211.07:41:58.60#ibcon#read 4, iclass 4, count 2 2006.211.07:41:58.60#ibcon#about to read 5, iclass 4, count 2 2006.211.07:41:58.60#ibcon#read 5, iclass 4, count 2 2006.211.07:41:58.60#ibcon#about to read 6, iclass 4, count 2 2006.211.07:41:58.60#ibcon#read 6, iclass 4, count 2 2006.211.07:41:58.60#ibcon#end of sib2, iclass 4, count 2 2006.211.07:41:58.60#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:41:58.60#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:41:58.60#ibcon#[25=AT04-07\r\n] 2006.211.07:41:58.60#ibcon#*before write, iclass 4, count 2 2006.211.07:41:58.60#ibcon#enter sib2, iclass 4, count 2 2006.211.07:41:58.60#ibcon#flushed, iclass 4, count 2 2006.211.07:41:58.60#ibcon#about to write, iclass 4, count 2 2006.211.07:41:58.60#ibcon#wrote, iclass 4, count 2 2006.211.07:41:58.60#ibcon#about to read 3, iclass 4, count 2 2006.211.07:41:58.63#ibcon#read 3, iclass 4, count 2 2006.211.07:41:58.63#ibcon#about to read 4, iclass 4, count 2 2006.211.07:41:58.63#ibcon#read 4, iclass 4, count 2 2006.211.07:41:58.63#ibcon#about to read 5, iclass 4, count 2 2006.211.07:41:58.63#ibcon#read 5, iclass 4, count 2 2006.211.07:41:58.63#ibcon#about to read 6, iclass 4, count 2 2006.211.07:41:58.63#ibcon#read 6, iclass 4, count 2 2006.211.07:41:58.63#ibcon#end of sib2, iclass 4, count 2 2006.211.07:41:58.63#ibcon#*after write, iclass 4, count 2 2006.211.07:41:58.63#ibcon#*before return 0, iclass 4, count 2 2006.211.07:41:58.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:41:58.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:41:58.63#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:41:58.63#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:58.63#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:41:58.75#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:41:58.75#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:41:58.75#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:41:58.75#ibcon#first serial, iclass 4, count 0 2006.211.07:41:58.75#ibcon#enter sib2, iclass 4, count 0 2006.211.07:41:58.75#ibcon#flushed, iclass 4, count 0 2006.211.07:41:58.75#ibcon#about to write, iclass 4, count 0 2006.211.07:41:58.75#ibcon#wrote, iclass 4, count 0 2006.211.07:41:58.75#ibcon#about to read 3, iclass 4, count 0 2006.211.07:41:58.77#ibcon#read 3, iclass 4, count 0 2006.211.07:41:58.77#ibcon#about to read 4, iclass 4, count 0 2006.211.07:41:58.77#ibcon#read 4, iclass 4, count 0 2006.211.07:41:58.77#ibcon#about to read 5, iclass 4, count 0 2006.211.07:41:58.77#ibcon#read 5, iclass 4, count 0 2006.211.07:41:58.77#ibcon#about to read 6, iclass 4, count 0 2006.211.07:41:58.77#ibcon#read 6, iclass 4, count 0 2006.211.07:41:58.77#ibcon#end of sib2, iclass 4, count 0 2006.211.07:41:58.77#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:41:58.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:41:58.77#ibcon#[25=USB\r\n] 2006.211.07:41:58.77#ibcon#*before write, iclass 4, count 0 2006.211.07:41:58.77#ibcon#enter sib2, iclass 4, count 0 2006.211.07:41:58.77#ibcon#flushed, iclass 4, count 0 2006.211.07:41:58.77#ibcon#about to write, iclass 4, count 0 2006.211.07:41:58.77#ibcon#wrote, iclass 4, count 0 2006.211.07:41:58.77#ibcon#about to read 3, iclass 4, count 0 2006.211.07:41:58.80#ibcon#read 3, iclass 4, count 0 2006.211.07:41:58.80#ibcon#about to read 4, iclass 4, count 0 2006.211.07:41:58.80#ibcon#read 4, iclass 4, count 0 2006.211.07:41:58.80#ibcon#about to read 5, iclass 4, count 0 2006.211.07:41:58.80#ibcon#read 5, iclass 4, count 0 2006.211.07:41:58.80#ibcon#about to read 6, iclass 4, count 0 2006.211.07:41:58.80#ibcon#read 6, iclass 4, count 0 2006.211.07:41:58.80#ibcon#end of sib2, iclass 4, count 0 2006.211.07:41:58.80#ibcon#*after write, iclass 4, count 0 2006.211.07:41:58.80#ibcon#*before return 0, iclass 4, count 0 2006.211.07:41:58.80#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:41:58.80#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:41:58.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:41:58.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:41:58.80$vc4f8/valo=5,652.99 2006.211.07:41:58.80#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:41:58.80#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:41:58.80#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:58.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:41:58.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:41:58.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:41:58.80#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:41:58.80#ibcon#first serial, iclass 6, count 0 2006.211.07:41:58.80#ibcon#enter sib2, iclass 6, count 0 2006.211.07:41:58.80#ibcon#flushed, iclass 6, count 0 2006.211.07:41:58.80#ibcon#about to write, iclass 6, count 0 2006.211.07:41:58.80#ibcon#wrote, iclass 6, count 0 2006.211.07:41:58.80#ibcon#about to read 3, iclass 6, count 0 2006.211.07:41:58.82#ibcon#read 3, iclass 6, count 0 2006.211.07:41:58.82#ibcon#about to read 4, iclass 6, count 0 2006.211.07:41:58.82#ibcon#read 4, iclass 6, count 0 2006.211.07:41:58.82#ibcon#about to read 5, iclass 6, count 0 2006.211.07:41:58.82#ibcon#read 5, iclass 6, count 0 2006.211.07:41:58.82#ibcon#about to read 6, iclass 6, count 0 2006.211.07:41:58.82#ibcon#read 6, iclass 6, count 0 2006.211.07:41:58.82#ibcon#end of sib2, iclass 6, count 0 2006.211.07:41:58.82#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:41:58.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:41:58.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:41:58.82#ibcon#*before write, iclass 6, count 0 2006.211.07:41:58.82#ibcon#enter sib2, iclass 6, count 0 2006.211.07:41:58.82#ibcon#flushed, iclass 6, count 0 2006.211.07:41:58.82#ibcon#about to write, iclass 6, count 0 2006.211.07:41:58.82#ibcon#wrote, iclass 6, count 0 2006.211.07:41:58.82#ibcon#about to read 3, iclass 6, count 0 2006.211.07:41:58.86#ibcon#read 3, iclass 6, count 0 2006.211.07:41:58.86#ibcon#about to read 4, iclass 6, count 0 2006.211.07:41:58.86#ibcon#read 4, iclass 6, count 0 2006.211.07:41:58.86#ibcon#about to read 5, iclass 6, count 0 2006.211.07:41:58.86#ibcon#read 5, iclass 6, count 0 2006.211.07:41:58.86#ibcon#about to read 6, iclass 6, count 0 2006.211.07:41:58.86#ibcon#read 6, iclass 6, count 0 2006.211.07:41:58.86#ibcon#end of sib2, iclass 6, count 0 2006.211.07:41:58.86#ibcon#*after write, iclass 6, count 0 2006.211.07:41:58.86#ibcon#*before return 0, iclass 6, count 0 2006.211.07:41:58.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:41:58.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:41:58.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:41:58.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:41:58.86$vc4f8/va=5,7 2006.211.07:41:58.86#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:41:58.86#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:41:58.86#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:58.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:41:58.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:41:58.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:41:58.92#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:41:58.92#ibcon#first serial, iclass 10, count 2 2006.211.07:41:58.92#ibcon#enter sib2, iclass 10, count 2 2006.211.07:41:58.92#ibcon#flushed, iclass 10, count 2 2006.211.07:41:58.92#ibcon#about to write, iclass 10, count 2 2006.211.07:41:58.92#ibcon#wrote, iclass 10, count 2 2006.211.07:41:58.92#ibcon#about to read 3, iclass 10, count 2 2006.211.07:41:58.94#ibcon#read 3, iclass 10, count 2 2006.211.07:41:58.94#ibcon#about to read 4, iclass 10, count 2 2006.211.07:41:58.94#ibcon#read 4, iclass 10, count 2 2006.211.07:41:58.94#ibcon#about to read 5, iclass 10, count 2 2006.211.07:41:58.94#ibcon#read 5, iclass 10, count 2 2006.211.07:41:58.94#ibcon#about to read 6, iclass 10, count 2 2006.211.07:41:58.94#ibcon#read 6, iclass 10, count 2 2006.211.07:41:58.94#ibcon#end of sib2, iclass 10, count 2 2006.211.07:41:58.94#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:41:58.94#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:41:58.94#ibcon#[25=AT05-07\r\n] 2006.211.07:41:58.94#ibcon#*before write, iclass 10, count 2 2006.211.07:41:58.94#ibcon#enter sib2, iclass 10, count 2 2006.211.07:41:58.94#ibcon#flushed, iclass 10, count 2 2006.211.07:41:58.94#ibcon#about to write, iclass 10, count 2 2006.211.07:41:58.94#ibcon#wrote, iclass 10, count 2 2006.211.07:41:58.94#ibcon#about to read 3, iclass 10, count 2 2006.211.07:41:58.97#ibcon#read 3, iclass 10, count 2 2006.211.07:41:58.97#ibcon#about to read 4, iclass 10, count 2 2006.211.07:41:58.97#ibcon#read 4, iclass 10, count 2 2006.211.07:41:58.97#ibcon#about to read 5, iclass 10, count 2 2006.211.07:41:58.97#ibcon#read 5, iclass 10, count 2 2006.211.07:41:58.97#ibcon#about to read 6, iclass 10, count 2 2006.211.07:41:58.97#ibcon#read 6, iclass 10, count 2 2006.211.07:41:58.97#ibcon#end of sib2, iclass 10, count 2 2006.211.07:41:58.97#ibcon#*after write, iclass 10, count 2 2006.211.07:41:58.97#ibcon#*before return 0, iclass 10, count 2 2006.211.07:41:58.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:41:58.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:41:58.97#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:41:58.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:58.97#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:41:59.09#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:41:59.09#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:41:59.09#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:41:59.09#ibcon#first serial, iclass 10, count 0 2006.211.07:41:59.09#ibcon#enter sib2, iclass 10, count 0 2006.211.07:41:59.09#ibcon#flushed, iclass 10, count 0 2006.211.07:41:59.09#ibcon#about to write, iclass 10, count 0 2006.211.07:41:59.09#ibcon#wrote, iclass 10, count 0 2006.211.07:41:59.09#ibcon#about to read 3, iclass 10, count 0 2006.211.07:41:59.11#ibcon#read 3, iclass 10, count 0 2006.211.07:41:59.11#ibcon#about to read 4, iclass 10, count 0 2006.211.07:41:59.11#ibcon#read 4, iclass 10, count 0 2006.211.07:41:59.11#ibcon#about to read 5, iclass 10, count 0 2006.211.07:41:59.11#ibcon#read 5, iclass 10, count 0 2006.211.07:41:59.11#ibcon#about to read 6, iclass 10, count 0 2006.211.07:41:59.11#ibcon#read 6, iclass 10, count 0 2006.211.07:41:59.11#ibcon#end of sib2, iclass 10, count 0 2006.211.07:41:59.11#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:41:59.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:41:59.11#ibcon#[25=USB\r\n] 2006.211.07:41:59.11#ibcon#*before write, iclass 10, count 0 2006.211.07:41:59.11#ibcon#enter sib2, iclass 10, count 0 2006.211.07:41:59.11#ibcon#flushed, iclass 10, count 0 2006.211.07:41:59.11#ibcon#about to write, iclass 10, count 0 2006.211.07:41:59.11#ibcon#wrote, iclass 10, count 0 2006.211.07:41:59.11#ibcon#about to read 3, iclass 10, count 0 2006.211.07:41:59.14#ibcon#read 3, iclass 10, count 0 2006.211.07:41:59.14#ibcon#about to read 4, iclass 10, count 0 2006.211.07:41:59.14#ibcon#read 4, iclass 10, count 0 2006.211.07:41:59.14#ibcon#about to read 5, iclass 10, count 0 2006.211.07:41:59.14#ibcon#read 5, iclass 10, count 0 2006.211.07:41:59.14#ibcon#about to read 6, iclass 10, count 0 2006.211.07:41:59.14#ibcon#read 6, iclass 10, count 0 2006.211.07:41:59.14#ibcon#end of sib2, iclass 10, count 0 2006.211.07:41:59.14#ibcon#*after write, iclass 10, count 0 2006.211.07:41:59.14#ibcon#*before return 0, iclass 10, count 0 2006.211.07:41:59.14#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:41:59.14#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:41:59.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:41:59.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:41:59.14$vc4f8/valo=6,772.99 2006.211.07:41:59.14#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:41:59.14#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:41:59.14#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:59.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:41:59.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:41:59.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:41:59.14#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:41:59.14#ibcon#first serial, iclass 12, count 0 2006.211.07:41:59.14#ibcon#enter sib2, iclass 12, count 0 2006.211.07:41:59.14#ibcon#flushed, iclass 12, count 0 2006.211.07:41:59.14#ibcon#about to write, iclass 12, count 0 2006.211.07:41:59.14#ibcon#wrote, iclass 12, count 0 2006.211.07:41:59.14#ibcon#about to read 3, iclass 12, count 0 2006.211.07:41:59.16#ibcon#read 3, iclass 12, count 0 2006.211.07:41:59.16#ibcon#about to read 4, iclass 12, count 0 2006.211.07:41:59.16#ibcon#read 4, iclass 12, count 0 2006.211.07:41:59.16#ibcon#about to read 5, iclass 12, count 0 2006.211.07:41:59.16#ibcon#read 5, iclass 12, count 0 2006.211.07:41:59.16#ibcon#about to read 6, iclass 12, count 0 2006.211.07:41:59.16#ibcon#read 6, iclass 12, count 0 2006.211.07:41:59.16#ibcon#end of sib2, iclass 12, count 0 2006.211.07:41:59.16#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:41:59.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:41:59.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:41:59.16#ibcon#*before write, iclass 12, count 0 2006.211.07:41:59.16#ibcon#enter sib2, iclass 12, count 0 2006.211.07:41:59.16#ibcon#flushed, iclass 12, count 0 2006.211.07:41:59.16#ibcon#about to write, iclass 12, count 0 2006.211.07:41:59.16#ibcon#wrote, iclass 12, count 0 2006.211.07:41:59.16#ibcon#about to read 3, iclass 12, count 0 2006.211.07:41:59.20#ibcon#read 3, iclass 12, count 0 2006.211.07:41:59.20#ibcon#about to read 4, iclass 12, count 0 2006.211.07:41:59.20#ibcon#read 4, iclass 12, count 0 2006.211.07:41:59.20#ibcon#about to read 5, iclass 12, count 0 2006.211.07:41:59.20#ibcon#read 5, iclass 12, count 0 2006.211.07:41:59.20#ibcon#about to read 6, iclass 12, count 0 2006.211.07:41:59.20#ibcon#read 6, iclass 12, count 0 2006.211.07:41:59.20#ibcon#end of sib2, iclass 12, count 0 2006.211.07:41:59.20#ibcon#*after write, iclass 12, count 0 2006.211.07:41:59.20#ibcon#*before return 0, iclass 12, count 0 2006.211.07:41:59.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:41:59.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:41:59.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:41:59.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:41:59.20$vc4f8/va=6,6 2006.211.07:41:59.20#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:41:59.20#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:41:59.20#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:59.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:41:59.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:41:59.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:41:59.26#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:41:59.26#ibcon#first serial, iclass 14, count 2 2006.211.07:41:59.26#ibcon#enter sib2, iclass 14, count 2 2006.211.07:41:59.26#ibcon#flushed, iclass 14, count 2 2006.211.07:41:59.26#ibcon#about to write, iclass 14, count 2 2006.211.07:41:59.26#ibcon#wrote, iclass 14, count 2 2006.211.07:41:59.26#ibcon#about to read 3, iclass 14, count 2 2006.211.07:41:59.28#ibcon#read 3, iclass 14, count 2 2006.211.07:41:59.28#ibcon#about to read 4, iclass 14, count 2 2006.211.07:41:59.28#ibcon#read 4, iclass 14, count 2 2006.211.07:41:59.28#ibcon#about to read 5, iclass 14, count 2 2006.211.07:41:59.28#ibcon#read 5, iclass 14, count 2 2006.211.07:41:59.28#ibcon#about to read 6, iclass 14, count 2 2006.211.07:41:59.28#ibcon#read 6, iclass 14, count 2 2006.211.07:41:59.28#ibcon#end of sib2, iclass 14, count 2 2006.211.07:41:59.28#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:41:59.28#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:41:59.28#ibcon#[25=AT06-06\r\n] 2006.211.07:41:59.28#ibcon#*before write, iclass 14, count 2 2006.211.07:41:59.28#ibcon#enter sib2, iclass 14, count 2 2006.211.07:41:59.28#ibcon#flushed, iclass 14, count 2 2006.211.07:41:59.28#ibcon#about to write, iclass 14, count 2 2006.211.07:41:59.28#ibcon#wrote, iclass 14, count 2 2006.211.07:41:59.28#ibcon#about to read 3, iclass 14, count 2 2006.211.07:41:59.31#ibcon#read 3, iclass 14, count 2 2006.211.07:41:59.31#ibcon#about to read 4, iclass 14, count 2 2006.211.07:41:59.31#ibcon#read 4, iclass 14, count 2 2006.211.07:41:59.31#ibcon#about to read 5, iclass 14, count 2 2006.211.07:41:59.31#ibcon#read 5, iclass 14, count 2 2006.211.07:41:59.31#ibcon#about to read 6, iclass 14, count 2 2006.211.07:41:59.31#ibcon#read 6, iclass 14, count 2 2006.211.07:41:59.31#ibcon#end of sib2, iclass 14, count 2 2006.211.07:41:59.31#ibcon#*after write, iclass 14, count 2 2006.211.07:41:59.31#ibcon#*before return 0, iclass 14, count 2 2006.211.07:41:59.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:41:59.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:41:59.31#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:41:59.31#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:59.31#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:41:59.43#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:41:59.43#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:41:59.43#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:41:59.43#ibcon#first serial, iclass 14, count 0 2006.211.07:41:59.43#ibcon#enter sib2, iclass 14, count 0 2006.211.07:41:59.43#ibcon#flushed, iclass 14, count 0 2006.211.07:41:59.43#ibcon#about to write, iclass 14, count 0 2006.211.07:41:59.43#ibcon#wrote, iclass 14, count 0 2006.211.07:41:59.43#ibcon#about to read 3, iclass 14, count 0 2006.211.07:41:59.45#ibcon#read 3, iclass 14, count 0 2006.211.07:41:59.45#ibcon#about to read 4, iclass 14, count 0 2006.211.07:41:59.45#ibcon#read 4, iclass 14, count 0 2006.211.07:41:59.45#ibcon#about to read 5, iclass 14, count 0 2006.211.07:41:59.45#ibcon#read 5, iclass 14, count 0 2006.211.07:41:59.45#ibcon#about to read 6, iclass 14, count 0 2006.211.07:41:59.45#ibcon#read 6, iclass 14, count 0 2006.211.07:41:59.45#ibcon#end of sib2, iclass 14, count 0 2006.211.07:41:59.45#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:41:59.45#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:41:59.45#ibcon#[25=USB\r\n] 2006.211.07:41:59.45#ibcon#*before write, iclass 14, count 0 2006.211.07:41:59.45#ibcon#enter sib2, iclass 14, count 0 2006.211.07:41:59.45#ibcon#flushed, iclass 14, count 0 2006.211.07:41:59.45#ibcon#about to write, iclass 14, count 0 2006.211.07:41:59.45#ibcon#wrote, iclass 14, count 0 2006.211.07:41:59.45#ibcon#about to read 3, iclass 14, count 0 2006.211.07:41:59.48#ibcon#read 3, iclass 14, count 0 2006.211.07:41:59.48#ibcon#about to read 4, iclass 14, count 0 2006.211.07:41:59.48#ibcon#read 4, iclass 14, count 0 2006.211.07:41:59.48#ibcon#about to read 5, iclass 14, count 0 2006.211.07:41:59.48#ibcon#read 5, iclass 14, count 0 2006.211.07:41:59.48#ibcon#about to read 6, iclass 14, count 0 2006.211.07:41:59.48#ibcon#read 6, iclass 14, count 0 2006.211.07:41:59.48#ibcon#end of sib2, iclass 14, count 0 2006.211.07:41:59.48#ibcon#*after write, iclass 14, count 0 2006.211.07:41:59.48#ibcon#*before return 0, iclass 14, count 0 2006.211.07:41:59.48#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:41:59.48#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:41:59.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:41:59.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:41:59.48$vc4f8/valo=7,832.99 2006.211.07:41:59.48#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:41:59.48#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:41:59.48#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:59.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:41:59.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:41:59.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:41:59.48#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:41:59.48#ibcon#first serial, iclass 16, count 0 2006.211.07:41:59.48#ibcon#enter sib2, iclass 16, count 0 2006.211.07:41:59.48#ibcon#flushed, iclass 16, count 0 2006.211.07:41:59.48#ibcon#about to write, iclass 16, count 0 2006.211.07:41:59.48#ibcon#wrote, iclass 16, count 0 2006.211.07:41:59.48#ibcon#about to read 3, iclass 16, count 0 2006.211.07:41:59.50#ibcon#read 3, iclass 16, count 0 2006.211.07:41:59.50#ibcon#about to read 4, iclass 16, count 0 2006.211.07:41:59.50#ibcon#read 4, iclass 16, count 0 2006.211.07:41:59.50#ibcon#about to read 5, iclass 16, count 0 2006.211.07:41:59.50#ibcon#read 5, iclass 16, count 0 2006.211.07:41:59.50#ibcon#about to read 6, iclass 16, count 0 2006.211.07:41:59.50#ibcon#read 6, iclass 16, count 0 2006.211.07:41:59.50#ibcon#end of sib2, iclass 16, count 0 2006.211.07:41:59.50#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:41:59.50#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:41:59.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:41:59.50#ibcon#*before write, iclass 16, count 0 2006.211.07:41:59.50#ibcon#enter sib2, iclass 16, count 0 2006.211.07:41:59.50#ibcon#flushed, iclass 16, count 0 2006.211.07:41:59.50#ibcon#about to write, iclass 16, count 0 2006.211.07:41:59.50#ibcon#wrote, iclass 16, count 0 2006.211.07:41:59.50#ibcon#about to read 3, iclass 16, count 0 2006.211.07:41:59.54#ibcon#read 3, iclass 16, count 0 2006.211.07:41:59.54#ibcon#about to read 4, iclass 16, count 0 2006.211.07:41:59.54#ibcon#read 4, iclass 16, count 0 2006.211.07:41:59.54#ibcon#about to read 5, iclass 16, count 0 2006.211.07:41:59.54#ibcon#read 5, iclass 16, count 0 2006.211.07:41:59.54#ibcon#about to read 6, iclass 16, count 0 2006.211.07:41:59.54#ibcon#read 6, iclass 16, count 0 2006.211.07:41:59.54#ibcon#end of sib2, iclass 16, count 0 2006.211.07:41:59.54#ibcon#*after write, iclass 16, count 0 2006.211.07:41:59.54#ibcon#*before return 0, iclass 16, count 0 2006.211.07:41:59.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:41:59.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:41:59.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:41:59.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:41:59.54$vc4f8/va=7,6 2006.211.07:41:59.54#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.07:41:59.54#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.07:41:59.54#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:59.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:41:59.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:41:59.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:41:59.60#ibcon#enter wrdev, iclass 18, count 2 2006.211.07:41:59.60#ibcon#first serial, iclass 18, count 2 2006.211.07:41:59.60#ibcon#enter sib2, iclass 18, count 2 2006.211.07:41:59.60#ibcon#flushed, iclass 18, count 2 2006.211.07:41:59.60#ibcon#about to write, iclass 18, count 2 2006.211.07:41:59.60#ibcon#wrote, iclass 18, count 2 2006.211.07:41:59.60#ibcon#about to read 3, iclass 18, count 2 2006.211.07:41:59.62#ibcon#read 3, iclass 18, count 2 2006.211.07:41:59.62#ibcon#about to read 4, iclass 18, count 2 2006.211.07:41:59.62#ibcon#read 4, iclass 18, count 2 2006.211.07:41:59.62#ibcon#about to read 5, iclass 18, count 2 2006.211.07:41:59.62#ibcon#read 5, iclass 18, count 2 2006.211.07:41:59.62#ibcon#about to read 6, iclass 18, count 2 2006.211.07:41:59.62#ibcon#read 6, iclass 18, count 2 2006.211.07:41:59.62#ibcon#end of sib2, iclass 18, count 2 2006.211.07:41:59.62#ibcon#*mode == 0, iclass 18, count 2 2006.211.07:41:59.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.07:41:59.62#ibcon#[25=AT07-06\r\n] 2006.211.07:41:59.62#ibcon#*before write, iclass 18, count 2 2006.211.07:41:59.62#ibcon#enter sib2, iclass 18, count 2 2006.211.07:41:59.62#ibcon#flushed, iclass 18, count 2 2006.211.07:41:59.62#ibcon#about to write, iclass 18, count 2 2006.211.07:41:59.62#ibcon#wrote, iclass 18, count 2 2006.211.07:41:59.62#ibcon#about to read 3, iclass 18, count 2 2006.211.07:41:59.65#ibcon#read 3, iclass 18, count 2 2006.211.07:41:59.65#ibcon#about to read 4, iclass 18, count 2 2006.211.07:41:59.65#ibcon#read 4, iclass 18, count 2 2006.211.07:41:59.65#ibcon#about to read 5, iclass 18, count 2 2006.211.07:41:59.65#ibcon#read 5, iclass 18, count 2 2006.211.07:41:59.65#ibcon#about to read 6, iclass 18, count 2 2006.211.07:41:59.65#ibcon#read 6, iclass 18, count 2 2006.211.07:41:59.65#ibcon#end of sib2, iclass 18, count 2 2006.211.07:41:59.65#ibcon#*after write, iclass 18, count 2 2006.211.07:41:59.65#ibcon#*before return 0, iclass 18, count 2 2006.211.07:41:59.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:41:59.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:41:59.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.07:41:59.65#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:59.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:41:59.77#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:41:59.77#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:41:59.77#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:41:59.77#ibcon#first serial, iclass 18, count 0 2006.211.07:41:59.77#ibcon#enter sib2, iclass 18, count 0 2006.211.07:41:59.77#ibcon#flushed, iclass 18, count 0 2006.211.07:41:59.77#ibcon#about to write, iclass 18, count 0 2006.211.07:41:59.77#ibcon#wrote, iclass 18, count 0 2006.211.07:41:59.77#ibcon#about to read 3, iclass 18, count 0 2006.211.07:41:59.79#ibcon#read 3, iclass 18, count 0 2006.211.07:41:59.79#ibcon#about to read 4, iclass 18, count 0 2006.211.07:41:59.79#ibcon#read 4, iclass 18, count 0 2006.211.07:41:59.79#ibcon#about to read 5, iclass 18, count 0 2006.211.07:41:59.79#ibcon#read 5, iclass 18, count 0 2006.211.07:41:59.79#ibcon#about to read 6, iclass 18, count 0 2006.211.07:41:59.79#ibcon#read 6, iclass 18, count 0 2006.211.07:41:59.79#ibcon#end of sib2, iclass 18, count 0 2006.211.07:41:59.79#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:41:59.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:41:59.79#ibcon#[25=USB\r\n] 2006.211.07:41:59.79#ibcon#*before write, iclass 18, count 0 2006.211.07:41:59.79#ibcon#enter sib2, iclass 18, count 0 2006.211.07:41:59.79#ibcon#flushed, iclass 18, count 0 2006.211.07:41:59.79#ibcon#about to write, iclass 18, count 0 2006.211.07:41:59.79#ibcon#wrote, iclass 18, count 0 2006.211.07:41:59.79#ibcon#about to read 3, iclass 18, count 0 2006.211.07:41:59.82#ibcon#read 3, iclass 18, count 0 2006.211.07:41:59.82#ibcon#about to read 4, iclass 18, count 0 2006.211.07:41:59.82#ibcon#read 4, iclass 18, count 0 2006.211.07:41:59.82#ibcon#about to read 5, iclass 18, count 0 2006.211.07:41:59.82#ibcon#read 5, iclass 18, count 0 2006.211.07:41:59.82#ibcon#about to read 6, iclass 18, count 0 2006.211.07:41:59.82#ibcon#read 6, iclass 18, count 0 2006.211.07:41:59.82#ibcon#end of sib2, iclass 18, count 0 2006.211.07:41:59.82#ibcon#*after write, iclass 18, count 0 2006.211.07:41:59.82#ibcon#*before return 0, iclass 18, count 0 2006.211.07:41:59.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:41:59.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:41:59.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:41:59.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:41:59.82$vc4f8/valo=8,852.99 2006.211.07:41:59.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.07:41:59.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.07:41:59.82#ibcon#ireg 17 cls_cnt 0 2006.211.07:41:59.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:41:59.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:41:59.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:41:59.82#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:41:59.82#ibcon#first serial, iclass 20, count 0 2006.211.07:41:59.82#ibcon#enter sib2, iclass 20, count 0 2006.211.07:41:59.82#ibcon#flushed, iclass 20, count 0 2006.211.07:41:59.82#ibcon#about to write, iclass 20, count 0 2006.211.07:41:59.82#ibcon#wrote, iclass 20, count 0 2006.211.07:41:59.82#ibcon#about to read 3, iclass 20, count 0 2006.211.07:41:59.84#ibcon#read 3, iclass 20, count 0 2006.211.07:41:59.84#ibcon#about to read 4, iclass 20, count 0 2006.211.07:41:59.84#ibcon#read 4, iclass 20, count 0 2006.211.07:41:59.84#ibcon#about to read 5, iclass 20, count 0 2006.211.07:41:59.84#ibcon#read 5, iclass 20, count 0 2006.211.07:41:59.84#ibcon#about to read 6, iclass 20, count 0 2006.211.07:41:59.84#ibcon#read 6, iclass 20, count 0 2006.211.07:41:59.84#ibcon#end of sib2, iclass 20, count 0 2006.211.07:41:59.84#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:41:59.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:41:59.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:41:59.84#ibcon#*before write, iclass 20, count 0 2006.211.07:41:59.84#ibcon#enter sib2, iclass 20, count 0 2006.211.07:41:59.84#ibcon#flushed, iclass 20, count 0 2006.211.07:41:59.84#ibcon#about to write, iclass 20, count 0 2006.211.07:41:59.84#ibcon#wrote, iclass 20, count 0 2006.211.07:41:59.84#ibcon#about to read 3, iclass 20, count 0 2006.211.07:41:59.88#ibcon#read 3, iclass 20, count 0 2006.211.07:41:59.88#ibcon#about to read 4, iclass 20, count 0 2006.211.07:41:59.88#ibcon#read 4, iclass 20, count 0 2006.211.07:41:59.88#ibcon#about to read 5, iclass 20, count 0 2006.211.07:41:59.88#ibcon#read 5, iclass 20, count 0 2006.211.07:41:59.88#ibcon#about to read 6, iclass 20, count 0 2006.211.07:41:59.88#ibcon#read 6, iclass 20, count 0 2006.211.07:41:59.88#ibcon#end of sib2, iclass 20, count 0 2006.211.07:41:59.88#ibcon#*after write, iclass 20, count 0 2006.211.07:41:59.88#ibcon#*before return 0, iclass 20, count 0 2006.211.07:41:59.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:41:59.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:41:59.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:41:59.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:41:59.88$vc4f8/va=8,7 2006.211.07:41:59.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.07:41:59.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.07:41:59.88#ibcon#ireg 11 cls_cnt 2 2006.211.07:41:59.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:41:59.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:41:59.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:41:59.94#ibcon#enter wrdev, iclass 22, count 2 2006.211.07:41:59.94#ibcon#first serial, iclass 22, count 2 2006.211.07:41:59.94#ibcon#enter sib2, iclass 22, count 2 2006.211.07:41:59.94#ibcon#flushed, iclass 22, count 2 2006.211.07:41:59.94#ibcon#about to write, iclass 22, count 2 2006.211.07:41:59.94#ibcon#wrote, iclass 22, count 2 2006.211.07:41:59.94#ibcon#about to read 3, iclass 22, count 2 2006.211.07:41:59.96#ibcon#read 3, iclass 22, count 2 2006.211.07:41:59.96#ibcon#about to read 4, iclass 22, count 2 2006.211.07:41:59.96#ibcon#read 4, iclass 22, count 2 2006.211.07:41:59.96#ibcon#about to read 5, iclass 22, count 2 2006.211.07:41:59.96#ibcon#read 5, iclass 22, count 2 2006.211.07:41:59.96#ibcon#about to read 6, iclass 22, count 2 2006.211.07:41:59.96#ibcon#read 6, iclass 22, count 2 2006.211.07:41:59.96#ibcon#end of sib2, iclass 22, count 2 2006.211.07:41:59.96#ibcon#*mode == 0, iclass 22, count 2 2006.211.07:41:59.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.07:41:59.96#ibcon#[25=AT08-07\r\n] 2006.211.07:41:59.96#ibcon#*before write, iclass 22, count 2 2006.211.07:41:59.96#ibcon#enter sib2, iclass 22, count 2 2006.211.07:41:59.96#ibcon#flushed, iclass 22, count 2 2006.211.07:41:59.96#ibcon#about to write, iclass 22, count 2 2006.211.07:41:59.96#ibcon#wrote, iclass 22, count 2 2006.211.07:41:59.96#ibcon#about to read 3, iclass 22, count 2 2006.211.07:41:59.99#ibcon#read 3, iclass 22, count 2 2006.211.07:41:59.99#ibcon#about to read 4, iclass 22, count 2 2006.211.07:41:59.99#ibcon#read 4, iclass 22, count 2 2006.211.07:41:59.99#ibcon#about to read 5, iclass 22, count 2 2006.211.07:41:59.99#ibcon#read 5, iclass 22, count 2 2006.211.07:41:59.99#ibcon#about to read 6, iclass 22, count 2 2006.211.07:41:59.99#ibcon#read 6, iclass 22, count 2 2006.211.07:41:59.99#ibcon#end of sib2, iclass 22, count 2 2006.211.07:41:59.99#ibcon#*after write, iclass 22, count 2 2006.211.07:41:59.99#ibcon#*before return 0, iclass 22, count 2 2006.211.07:41:59.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:41:59.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:41:59.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.07:41:59.99#ibcon#ireg 7 cls_cnt 0 2006.211.07:41:59.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:42:00.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:42:00.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:42:00.11#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:42:00.11#ibcon#first serial, iclass 22, count 0 2006.211.07:42:00.11#ibcon#enter sib2, iclass 22, count 0 2006.211.07:42:00.11#ibcon#flushed, iclass 22, count 0 2006.211.07:42:00.11#ibcon#about to write, iclass 22, count 0 2006.211.07:42:00.11#ibcon#wrote, iclass 22, count 0 2006.211.07:42:00.11#ibcon#about to read 3, iclass 22, count 0 2006.211.07:42:00.13#ibcon#read 3, iclass 22, count 0 2006.211.07:42:00.13#ibcon#about to read 4, iclass 22, count 0 2006.211.07:42:00.13#ibcon#read 4, iclass 22, count 0 2006.211.07:42:00.13#ibcon#about to read 5, iclass 22, count 0 2006.211.07:42:00.13#ibcon#read 5, iclass 22, count 0 2006.211.07:42:00.13#ibcon#about to read 6, iclass 22, count 0 2006.211.07:42:00.13#ibcon#read 6, iclass 22, count 0 2006.211.07:42:00.13#ibcon#end of sib2, iclass 22, count 0 2006.211.07:42:00.13#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:42:00.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:42:00.13#ibcon#[25=USB\r\n] 2006.211.07:42:00.13#ibcon#*before write, iclass 22, count 0 2006.211.07:42:00.13#ibcon#enter sib2, iclass 22, count 0 2006.211.07:42:00.13#ibcon#flushed, iclass 22, count 0 2006.211.07:42:00.13#ibcon#about to write, iclass 22, count 0 2006.211.07:42:00.13#ibcon#wrote, iclass 22, count 0 2006.211.07:42:00.13#ibcon#about to read 3, iclass 22, count 0 2006.211.07:42:00.16#ibcon#read 3, iclass 22, count 0 2006.211.07:42:00.16#ibcon#about to read 4, iclass 22, count 0 2006.211.07:42:00.16#ibcon#read 4, iclass 22, count 0 2006.211.07:42:00.16#ibcon#about to read 5, iclass 22, count 0 2006.211.07:42:00.16#ibcon#read 5, iclass 22, count 0 2006.211.07:42:00.16#ibcon#about to read 6, iclass 22, count 0 2006.211.07:42:00.16#ibcon#read 6, iclass 22, count 0 2006.211.07:42:00.16#ibcon#end of sib2, iclass 22, count 0 2006.211.07:42:00.16#ibcon#*after write, iclass 22, count 0 2006.211.07:42:00.16#ibcon#*before return 0, iclass 22, count 0 2006.211.07:42:00.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:42:00.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:42:00.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:42:00.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:42:00.16$vc4f8/vblo=1,632.99 2006.211.07:42:00.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.07:42:00.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.07:42:00.16#ibcon#ireg 17 cls_cnt 0 2006.211.07:42:00.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:42:00.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:42:00.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:42:00.16#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:42:00.16#ibcon#first serial, iclass 24, count 0 2006.211.07:42:00.16#ibcon#enter sib2, iclass 24, count 0 2006.211.07:42:00.16#ibcon#flushed, iclass 24, count 0 2006.211.07:42:00.16#ibcon#about to write, iclass 24, count 0 2006.211.07:42:00.16#ibcon#wrote, iclass 24, count 0 2006.211.07:42:00.16#ibcon#about to read 3, iclass 24, count 0 2006.211.07:42:00.18#ibcon#read 3, iclass 24, count 0 2006.211.07:42:00.18#ibcon#about to read 4, iclass 24, count 0 2006.211.07:42:00.18#ibcon#read 4, iclass 24, count 0 2006.211.07:42:00.18#ibcon#about to read 5, iclass 24, count 0 2006.211.07:42:00.18#ibcon#read 5, iclass 24, count 0 2006.211.07:42:00.18#ibcon#about to read 6, iclass 24, count 0 2006.211.07:42:00.18#ibcon#read 6, iclass 24, count 0 2006.211.07:42:00.18#ibcon#end of sib2, iclass 24, count 0 2006.211.07:42:00.18#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:42:00.18#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:42:00.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:42:00.18#ibcon#*before write, iclass 24, count 0 2006.211.07:42:00.18#ibcon#enter sib2, iclass 24, count 0 2006.211.07:42:00.18#ibcon#flushed, iclass 24, count 0 2006.211.07:42:00.18#ibcon#about to write, iclass 24, count 0 2006.211.07:42:00.18#ibcon#wrote, iclass 24, count 0 2006.211.07:42:00.18#ibcon#about to read 3, iclass 24, count 0 2006.211.07:42:00.22#ibcon#read 3, iclass 24, count 0 2006.211.07:42:00.22#ibcon#about to read 4, iclass 24, count 0 2006.211.07:42:00.22#ibcon#read 4, iclass 24, count 0 2006.211.07:42:00.22#ibcon#about to read 5, iclass 24, count 0 2006.211.07:42:00.22#ibcon#read 5, iclass 24, count 0 2006.211.07:42:00.22#ibcon#about to read 6, iclass 24, count 0 2006.211.07:42:00.22#ibcon#read 6, iclass 24, count 0 2006.211.07:42:00.22#ibcon#end of sib2, iclass 24, count 0 2006.211.07:42:00.22#ibcon#*after write, iclass 24, count 0 2006.211.07:42:00.22#ibcon#*before return 0, iclass 24, count 0 2006.211.07:42:00.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:42:00.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:42:00.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:42:00.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:42:00.22$vc4f8/vb=1,4 2006.211.07:42:00.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.07:42:00.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.07:42:00.22#ibcon#ireg 11 cls_cnt 2 2006.211.07:42:00.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:42:00.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:42:00.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:42:00.22#ibcon#enter wrdev, iclass 26, count 2 2006.211.07:42:00.22#ibcon#first serial, iclass 26, count 2 2006.211.07:42:00.22#ibcon#enter sib2, iclass 26, count 2 2006.211.07:42:00.22#ibcon#flushed, iclass 26, count 2 2006.211.07:42:00.22#ibcon#about to write, iclass 26, count 2 2006.211.07:42:00.22#ibcon#wrote, iclass 26, count 2 2006.211.07:42:00.22#ibcon#about to read 3, iclass 26, count 2 2006.211.07:42:00.24#ibcon#read 3, iclass 26, count 2 2006.211.07:42:00.24#ibcon#about to read 4, iclass 26, count 2 2006.211.07:42:00.24#ibcon#read 4, iclass 26, count 2 2006.211.07:42:00.24#ibcon#about to read 5, iclass 26, count 2 2006.211.07:42:00.24#ibcon#read 5, iclass 26, count 2 2006.211.07:42:00.24#ibcon#about to read 6, iclass 26, count 2 2006.211.07:42:00.24#ibcon#read 6, iclass 26, count 2 2006.211.07:42:00.24#ibcon#end of sib2, iclass 26, count 2 2006.211.07:42:00.24#ibcon#*mode == 0, iclass 26, count 2 2006.211.07:42:00.24#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.07:42:00.24#ibcon#[27=AT01-04\r\n] 2006.211.07:42:00.24#ibcon#*before write, iclass 26, count 2 2006.211.07:42:00.24#ibcon#enter sib2, iclass 26, count 2 2006.211.07:42:00.24#ibcon#flushed, iclass 26, count 2 2006.211.07:42:00.24#ibcon#about to write, iclass 26, count 2 2006.211.07:42:00.24#ibcon#wrote, iclass 26, count 2 2006.211.07:42:00.24#ibcon#about to read 3, iclass 26, count 2 2006.211.07:42:00.27#ibcon#read 3, iclass 26, count 2 2006.211.07:42:00.27#ibcon#about to read 4, iclass 26, count 2 2006.211.07:42:00.27#ibcon#read 4, iclass 26, count 2 2006.211.07:42:00.27#ibcon#about to read 5, iclass 26, count 2 2006.211.07:42:00.27#ibcon#read 5, iclass 26, count 2 2006.211.07:42:00.27#ibcon#about to read 6, iclass 26, count 2 2006.211.07:42:00.27#ibcon#read 6, iclass 26, count 2 2006.211.07:42:00.27#ibcon#end of sib2, iclass 26, count 2 2006.211.07:42:00.27#ibcon#*after write, iclass 26, count 2 2006.211.07:42:00.27#ibcon#*before return 0, iclass 26, count 2 2006.211.07:42:00.27#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:42:00.27#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:42:00.27#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.07:42:00.27#ibcon#ireg 7 cls_cnt 0 2006.211.07:42:00.27#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:42:00.39#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:42:00.39#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:42:00.39#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:42:00.39#ibcon#first serial, iclass 26, count 0 2006.211.07:42:00.39#ibcon#enter sib2, iclass 26, count 0 2006.211.07:42:00.39#ibcon#flushed, iclass 26, count 0 2006.211.07:42:00.39#ibcon#about to write, iclass 26, count 0 2006.211.07:42:00.39#ibcon#wrote, iclass 26, count 0 2006.211.07:42:00.39#ibcon#about to read 3, iclass 26, count 0 2006.211.07:42:00.41#ibcon#read 3, iclass 26, count 0 2006.211.07:42:00.41#ibcon#about to read 4, iclass 26, count 0 2006.211.07:42:00.41#ibcon#read 4, iclass 26, count 0 2006.211.07:42:00.41#ibcon#about to read 5, iclass 26, count 0 2006.211.07:42:00.41#ibcon#read 5, iclass 26, count 0 2006.211.07:42:00.41#ibcon#about to read 6, iclass 26, count 0 2006.211.07:42:00.41#ibcon#read 6, iclass 26, count 0 2006.211.07:42:00.41#ibcon#end of sib2, iclass 26, count 0 2006.211.07:42:00.41#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:42:00.41#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:42:00.41#ibcon#[27=USB\r\n] 2006.211.07:42:00.41#ibcon#*before write, iclass 26, count 0 2006.211.07:42:00.41#ibcon#enter sib2, iclass 26, count 0 2006.211.07:42:00.41#ibcon#flushed, iclass 26, count 0 2006.211.07:42:00.41#ibcon#about to write, iclass 26, count 0 2006.211.07:42:00.41#ibcon#wrote, iclass 26, count 0 2006.211.07:42:00.41#ibcon#about to read 3, iclass 26, count 0 2006.211.07:42:00.44#ibcon#read 3, iclass 26, count 0 2006.211.07:42:00.44#ibcon#about to read 4, iclass 26, count 0 2006.211.07:42:00.44#ibcon#read 4, iclass 26, count 0 2006.211.07:42:00.44#ibcon#about to read 5, iclass 26, count 0 2006.211.07:42:00.44#ibcon#read 5, iclass 26, count 0 2006.211.07:42:00.44#ibcon#about to read 6, iclass 26, count 0 2006.211.07:42:00.44#ibcon#read 6, iclass 26, count 0 2006.211.07:42:00.44#ibcon#end of sib2, iclass 26, count 0 2006.211.07:42:00.44#ibcon#*after write, iclass 26, count 0 2006.211.07:42:00.44#ibcon#*before return 0, iclass 26, count 0 2006.211.07:42:00.44#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:42:00.44#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:42:00.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:42:00.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:42:00.44$vc4f8/vblo=2,640.99 2006.211.07:42:00.44#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.07:42:00.44#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.07:42:00.44#ibcon#ireg 17 cls_cnt 0 2006.211.07:42:00.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:42:00.44#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:42:00.44#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:42:00.44#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:42:00.44#ibcon#first serial, iclass 28, count 0 2006.211.07:42:00.44#ibcon#enter sib2, iclass 28, count 0 2006.211.07:42:00.44#ibcon#flushed, iclass 28, count 0 2006.211.07:42:00.44#ibcon#about to write, iclass 28, count 0 2006.211.07:42:00.44#ibcon#wrote, iclass 28, count 0 2006.211.07:42:00.44#ibcon#about to read 3, iclass 28, count 0 2006.211.07:42:00.46#ibcon#read 3, iclass 28, count 0 2006.211.07:42:00.46#ibcon#about to read 4, iclass 28, count 0 2006.211.07:42:00.46#ibcon#read 4, iclass 28, count 0 2006.211.07:42:00.46#ibcon#about to read 5, iclass 28, count 0 2006.211.07:42:00.46#ibcon#read 5, iclass 28, count 0 2006.211.07:42:00.46#ibcon#about to read 6, iclass 28, count 0 2006.211.07:42:00.46#ibcon#read 6, iclass 28, count 0 2006.211.07:42:00.46#ibcon#end of sib2, iclass 28, count 0 2006.211.07:42:00.46#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:42:00.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:42:00.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:42:00.46#ibcon#*before write, iclass 28, count 0 2006.211.07:42:00.46#ibcon#enter sib2, iclass 28, count 0 2006.211.07:42:00.46#ibcon#flushed, iclass 28, count 0 2006.211.07:42:00.46#ibcon#about to write, iclass 28, count 0 2006.211.07:42:00.46#ibcon#wrote, iclass 28, count 0 2006.211.07:42:00.46#ibcon#about to read 3, iclass 28, count 0 2006.211.07:42:00.50#ibcon#read 3, iclass 28, count 0 2006.211.07:42:00.50#ibcon#about to read 4, iclass 28, count 0 2006.211.07:42:00.50#ibcon#read 4, iclass 28, count 0 2006.211.07:42:00.50#ibcon#about to read 5, iclass 28, count 0 2006.211.07:42:00.50#ibcon#read 5, iclass 28, count 0 2006.211.07:42:00.50#ibcon#about to read 6, iclass 28, count 0 2006.211.07:42:00.50#ibcon#read 6, iclass 28, count 0 2006.211.07:42:00.50#ibcon#end of sib2, iclass 28, count 0 2006.211.07:42:00.50#ibcon#*after write, iclass 28, count 0 2006.211.07:42:00.50#ibcon#*before return 0, iclass 28, count 0 2006.211.07:42:00.50#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:42:00.50#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:42:00.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:42:00.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:42:00.50$vc4f8/vb=2,4 2006.211.07:42:00.50#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.07:42:00.50#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.07:42:00.50#ibcon#ireg 11 cls_cnt 2 2006.211.07:42:00.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:42:00.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:42:00.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:42:00.56#ibcon#enter wrdev, iclass 30, count 2 2006.211.07:42:00.56#ibcon#first serial, iclass 30, count 2 2006.211.07:42:00.56#ibcon#enter sib2, iclass 30, count 2 2006.211.07:42:00.56#ibcon#flushed, iclass 30, count 2 2006.211.07:42:00.56#ibcon#about to write, iclass 30, count 2 2006.211.07:42:00.56#ibcon#wrote, iclass 30, count 2 2006.211.07:42:00.56#ibcon#about to read 3, iclass 30, count 2 2006.211.07:42:00.58#ibcon#read 3, iclass 30, count 2 2006.211.07:42:00.58#ibcon#about to read 4, iclass 30, count 2 2006.211.07:42:00.58#ibcon#read 4, iclass 30, count 2 2006.211.07:42:00.58#ibcon#about to read 5, iclass 30, count 2 2006.211.07:42:00.58#ibcon#read 5, iclass 30, count 2 2006.211.07:42:00.58#ibcon#about to read 6, iclass 30, count 2 2006.211.07:42:00.58#ibcon#read 6, iclass 30, count 2 2006.211.07:42:00.58#ibcon#end of sib2, iclass 30, count 2 2006.211.07:42:00.58#ibcon#*mode == 0, iclass 30, count 2 2006.211.07:42:00.58#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.07:42:00.58#ibcon#[27=AT02-04\r\n] 2006.211.07:42:00.58#ibcon#*before write, iclass 30, count 2 2006.211.07:42:00.58#ibcon#enter sib2, iclass 30, count 2 2006.211.07:42:00.58#ibcon#flushed, iclass 30, count 2 2006.211.07:42:00.58#ibcon#about to write, iclass 30, count 2 2006.211.07:42:00.58#ibcon#wrote, iclass 30, count 2 2006.211.07:42:00.58#ibcon#about to read 3, iclass 30, count 2 2006.211.07:42:00.61#ibcon#read 3, iclass 30, count 2 2006.211.07:42:00.61#ibcon#about to read 4, iclass 30, count 2 2006.211.07:42:00.61#ibcon#read 4, iclass 30, count 2 2006.211.07:42:00.61#ibcon#about to read 5, iclass 30, count 2 2006.211.07:42:00.61#ibcon#read 5, iclass 30, count 2 2006.211.07:42:00.61#ibcon#about to read 6, iclass 30, count 2 2006.211.07:42:00.61#ibcon#read 6, iclass 30, count 2 2006.211.07:42:00.61#ibcon#end of sib2, iclass 30, count 2 2006.211.07:42:00.61#ibcon#*after write, iclass 30, count 2 2006.211.07:42:00.61#ibcon#*before return 0, iclass 30, count 2 2006.211.07:42:00.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:42:00.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:42:00.61#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.07:42:00.61#ibcon#ireg 7 cls_cnt 0 2006.211.07:42:00.61#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:42:00.73#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:42:00.73#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:42:00.73#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:42:00.73#ibcon#first serial, iclass 30, count 0 2006.211.07:42:00.73#ibcon#enter sib2, iclass 30, count 0 2006.211.07:42:00.73#ibcon#flushed, iclass 30, count 0 2006.211.07:42:00.73#ibcon#about to write, iclass 30, count 0 2006.211.07:42:00.73#ibcon#wrote, iclass 30, count 0 2006.211.07:42:00.73#ibcon#about to read 3, iclass 30, count 0 2006.211.07:42:00.75#ibcon#read 3, iclass 30, count 0 2006.211.07:42:00.75#ibcon#about to read 4, iclass 30, count 0 2006.211.07:42:00.75#ibcon#read 4, iclass 30, count 0 2006.211.07:42:00.75#ibcon#about to read 5, iclass 30, count 0 2006.211.07:42:00.75#ibcon#read 5, iclass 30, count 0 2006.211.07:42:00.75#ibcon#about to read 6, iclass 30, count 0 2006.211.07:42:00.75#ibcon#read 6, iclass 30, count 0 2006.211.07:42:00.75#ibcon#end of sib2, iclass 30, count 0 2006.211.07:42:00.75#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:42:00.75#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:42:00.75#ibcon#[27=USB\r\n] 2006.211.07:42:00.75#ibcon#*before write, iclass 30, count 0 2006.211.07:42:00.75#ibcon#enter sib2, iclass 30, count 0 2006.211.07:42:00.75#ibcon#flushed, iclass 30, count 0 2006.211.07:42:00.75#ibcon#about to write, iclass 30, count 0 2006.211.07:42:00.75#ibcon#wrote, iclass 30, count 0 2006.211.07:42:00.75#ibcon#about to read 3, iclass 30, count 0 2006.211.07:42:00.78#ibcon#read 3, iclass 30, count 0 2006.211.07:42:00.78#ibcon#about to read 4, iclass 30, count 0 2006.211.07:42:00.78#ibcon#read 4, iclass 30, count 0 2006.211.07:42:00.78#ibcon#about to read 5, iclass 30, count 0 2006.211.07:42:00.78#ibcon#read 5, iclass 30, count 0 2006.211.07:42:00.78#ibcon#about to read 6, iclass 30, count 0 2006.211.07:42:00.78#ibcon#read 6, iclass 30, count 0 2006.211.07:42:00.78#ibcon#end of sib2, iclass 30, count 0 2006.211.07:42:00.78#ibcon#*after write, iclass 30, count 0 2006.211.07:42:00.78#ibcon#*before return 0, iclass 30, count 0 2006.211.07:42:00.78#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:42:00.78#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:42:00.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:42:00.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:42:00.78$vc4f8/vblo=3,656.99 2006.211.07:42:00.78#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:42:00.78#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:42:00.78#ibcon#ireg 17 cls_cnt 0 2006.211.07:42:00.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:42:00.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:42:00.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:42:00.78#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:42:00.78#ibcon#first serial, iclass 32, count 0 2006.211.07:42:00.78#ibcon#enter sib2, iclass 32, count 0 2006.211.07:42:00.78#ibcon#flushed, iclass 32, count 0 2006.211.07:42:00.78#ibcon#about to write, iclass 32, count 0 2006.211.07:42:00.78#ibcon#wrote, iclass 32, count 0 2006.211.07:42:00.78#ibcon#about to read 3, iclass 32, count 0 2006.211.07:42:00.80#ibcon#read 3, iclass 32, count 0 2006.211.07:42:00.80#ibcon#about to read 4, iclass 32, count 0 2006.211.07:42:00.80#ibcon#read 4, iclass 32, count 0 2006.211.07:42:00.80#ibcon#about to read 5, iclass 32, count 0 2006.211.07:42:00.80#ibcon#read 5, iclass 32, count 0 2006.211.07:42:00.80#ibcon#about to read 6, iclass 32, count 0 2006.211.07:42:00.80#ibcon#read 6, iclass 32, count 0 2006.211.07:42:00.80#ibcon#end of sib2, iclass 32, count 0 2006.211.07:42:00.80#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:42:00.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:42:00.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:42:00.80#ibcon#*before write, iclass 32, count 0 2006.211.07:42:00.80#ibcon#enter sib2, iclass 32, count 0 2006.211.07:42:00.80#ibcon#flushed, iclass 32, count 0 2006.211.07:42:00.80#ibcon#about to write, iclass 32, count 0 2006.211.07:42:00.80#ibcon#wrote, iclass 32, count 0 2006.211.07:42:00.80#ibcon#about to read 3, iclass 32, count 0 2006.211.07:42:00.84#ibcon#read 3, iclass 32, count 0 2006.211.07:42:00.84#ibcon#about to read 4, iclass 32, count 0 2006.211.07:42:00.84#ibcon#read 4, iclass 32, count 0 2006.211.07:42:00.84#ibcon#about to read 5, iclass 32, count 0 2006.211.07:42:00.84#ibcon#read 5, iclass 32, count 0 2006.211.07:42:00.84#ibcon#about to read 6, iclass 32, count 0 2006.211.07:42:00.84#ibcon#read 6, iclass 32, count 0 2006.211.07:42:00.84#ibcon#end of sib2, iclass 32, count 0 2006.211.07:42:00.84#ibcon#*after write, iclass 32, count 0 2006.211.07:42:00.84#ibcon#*before return 0, iclass 32, count 0 2006.211.07:42:00.84#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:42:00.84#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:42:00.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:42:00.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:42:00.84$vc4f8/vb=3,3 2006.211.07:42:00.84#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:42:00.84#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:42:00.84#ibcon#ireg 11 cls_cnt 2 2006.211.07:42:00.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:42:00.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:42:00.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:42:00.90#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:42:00.90#ibcon#first serial, iclass 34, count 2 2006.211.07:42:00.90#ibcon#enter sib2, iclass 34, count 2 2006.211.07:42:00.90#ibcon#flushed, iclass 34, count 2 2006.211.07:42:00.90#ibcon#about to write, iclass 34, count 2 2006.211.07:42:00.90#ibcon#wrote, iclass 34, count 2 2006.211.07:42:00.90#ibcon#about to read 3, iclass 34, count 2 2006.211.07:42:00.92#ibcon#read 3, iclass 34, count 2 2006.211.07:42:00.92#ibcon#about to read 4, iclass 34, count 2 2006.211.07:42:00.92#ibcon#read 4, iclass 34, count 2 2006.211.07:42:00.92#ibcon#about to read 5, iclass 34, count 2 2006.211.07:42:00.92#ibcon#read 5, iclass 34, count 2 2006.211.07:42:00.92#ibcon#about to read 6, iclass 34, count 2 2006.211.07:42:00.92#ibcon#read 6, iclass 34, count 2 2006.211.07:42:00.92#ibcon#end of sib2, iclass 34, count 2 2006.211.07:42:00.92#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:42:00.92#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:42:00.92#ibcon#[27=AT03-03\r\n] 2006.211.07:42:00.92#ibcon#*before write, iclass 34, count 2 2006.211.07:42:00.92#ibcon#enter sib2, iclass 34, count 2 2006.211.07:42:00.92#ibcon#flushed, iclass 34, count 2 2006.211.07:42:00.92#ibcon#about to write, iclass 34, count 2 2006.211.07:42:00.92#ibcon#wrote, iclass 34, count 2 2006.211.07:42:00.92#ibcon#about to read 3, iclass 34, count 2 2006.211.07:42:00.95#ibcon#read 3, iclass 34, count 2 2006.211.07:42:00.95#ibcon#about to read 4, iclass 34, count 2 2006.211.07:42:00.95#ibcon#read 4, iclass 34, count 2 2006.211.07:42:00.95#ibcon#about to read 5, iclass 34, count 2 2006.211.07:42:00.95#ibcon#read 5, iclass 34, count 2 2006.211.07:42:00.95#ibcon#about to read 6, iclass 34, count 2 2006.211.07:42:00.95#ibcon#read 6, iclass 34, count 2 2006.211.07:42:00.95#ibcon#end of sib2, iclass 34, count 2 2006.211.07:42:00.95#ibcon#*after write, iclass 34, count 2 2006.211.07:42:00.95#ibcon#*before return 0, iclass 34, count 2 2006.211.07:42:00.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:42:00.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:42:00.95#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:42:00.95#ibcon#ireg 7 cls_cnt 0 2006.211.07:42:00.95#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:42:01.07#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:42:01.07#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:42:01.07#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:42:01.07#ibcon#first serial, iclass 34, count 0 2006.211.07:42:01.07#ibcon#enter sib2, iclass 34, count 0 2006.211.07:42:01.07#ibcon#flushed, iclass 34, count 0 2006.211.07:42:01.07#ibcon#about to write, iclass 34, count 0 2006.211.07:42:01.07#ibcon#wrote, iclass 34, count 0 2006.211.07:42:01.07#ibcon#about to read 3, iclass 34, count 0 2006.211.07:42:01.09#ibcon#read 3, iclass 34, count 0 2006.211.07:42:01.09#ibcon#about to read 4, iclass 34, count 0 2006.211.07:42:01.09#ibcon#read 4, iclass 34, count 0 2006.211.07:42:01.09#ibcon#about to read 5, iclass 34, count 0 2006.211.07:42:01.09#ibcon#read 5, iclass 34, count 0 2006.211.07:42:01.09#ibcon#about to read 6, iclass 34, count 0 2006.211.07:42:01.09#ibcon#read 6, iclass 34, count 0 2006.211.07:42:01.09#ibcon#end of sib2, iclass 34, count 0 2006.211.07:42:01.09#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:42:01.09#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:42:01.09#ibcon#[27=USB\r\n] 2006.211.07:42:01.09#ibcon#*before write, iclass 34, count 0 2006.211.07:42:01.09#ibcon#enter sib2, iclass 34, count 0 2006.211.07:42:01.09#ibcon#flushed, iclass 34, count 0 2006.211.07:42:01.09#ibcon#about to write, iclass 34, count 0 2006.211.07:42:01.09#ibcon#wrote, iclass 34, count 0 2006.211.07:42:01.09#ibcon#about to read 3, iclass 34, count 0 2006.211.07:42:01.12#ibcon#read 3, iclass 34, count 0 2006.211.07:42:01.12#ibcon#about to read 4, iclass 34, count 0 2006.211.07:42:01.12#ibcon#read 4, iclass 34, count 0 2006.211.07:42:01.12#ibcon#about to read 5, iclass 34, count 0 2006.211.07:42:01.12#ibcon#read 5, iclass 34, count 0 2006.211.07:42:01.12#ibcon#about to read 6, iclass 34, count 0 2006.211.07:42:01.12#ibcon#read 6, iclass 34, count 0 2006.211.07:42:01.12#ibcon#end of sib2, iclass 34, count 0 2006.211.07:42:01.12#ibcon#*after write, iclass 34, count 0 2006.211.07:42:01.12#ibcon#*before return 0, iclass 34, count 0 2006.211.07:42:01.12#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:42:01.12#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:42:01.12#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:42:01.12#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:42:01.12$vc4f8/vblo=4,712.99 2006.211.07:42:01.12#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.07:42:01.12#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.07:42:01.12#ibcon#ireg 17 cls_cnt 0 2006.211.07:42:01.12#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:42:01.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:42:01.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:42:01.12#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:42:01.12#ibcon#first serial, iclass 36, count 0 2006.211.07:42:01.12#ibcon#enter sib2, iclass 36, count 0 2006.211.07:42:01.12#ibcon#flushed, iclass 36, count 0 2006.211.07:42:01.12#ibcon#about to write, iclass 36, count 0 2006.211.07:42:01.12#ibcon#wrote, iclass 36, count 0 2006.211.07:42:01.12#ibcon#about to read 3, iclass 36, count 0 2006.211.07:42:01.14#ibcon#read 3, iclass 36, count 0 2006.211.07:42:01.14#ibcon#about to read 4, iclass 36, count 0 2006.211.07:42:01.14#ibcon#read 4, iclass 36, count 0 2006.211.07:42:01.14#ibcon#about to read 5, iclass 36, count 0 2006.211.07:42:01.14#ibcon#read 5, iclass 36, count 0 2006.211.07:42:01.14#ibcon#about to read 6, iclass 36, count 0 2006.211.07:42:01.14#ibcon#read 6, iclass 36, count 0 2006.211.07:42:01.14#ibcon#end of sib2, iclass 36, count 0 2006.211.07:42:01.14#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:42:01.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:42:01.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:42:01.14#ibcon#*before write, iclass 36, count 0 2006.211.07:42:01.14#ibcon#enter sib2, iclass 36, count 0 2006.211.07:42:01.14#ibcon#flushed, iclass 36, count 0 2006.211.07:42:01.14#ibcon#about to write, iclass 36, count 0 2006.211.07:42:01.14#ibcon#wrote, iclass 36, count 0 2006.211.07:42:01.14#ibcon#about to read 3, iclass 36, count 0 2006.211.07:42:01.18#ibcon#read 3, iclass 36, count 0 2006.211.07:42:01.18#ibcon#about to read 4, iclass 36, count 0 2006.211.07:42:01.18#ibcon#read 4, iclass 36, count 0 2006.211.07:42:01.18#ibcon#about to read 5, iclass 36, count 0 2006.211.07:42:01.18#ibcon#read 5, iclass 36, count 0 2006.211.07:42:01.18#ibcon#about to read 6, iclass 36, count 0 2006.211.07:42:01.18#ibcon#read 6, iclass 36, count 0 2006.211.07:42:01.18#ibcon#end of sib2, iclass 36, count 0 2006.211.07:42:01.18#ibcon#*after write, iclass 36, count 0 2006.211.07:42:01.18#ibcon#*before return 0, iclass 36, count 0 2006.211.07:42:01.18#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:42:01.18#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:42:01.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:42:01.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:42:01.18$vc4f8/vb=4,3 2006.211.07:42:01.18#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.07:42:01.18#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.07:42:01.18#ibcon#ireg 11 cls_cnt 2 2006.211.07:42:01.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:42:01.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:42:01.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:42:01.24#ibcon#enter wrdev, iclass 38, count 2 2006.211.07:42:01.24#ibcon#first serial, iclass 38, count 2 2006.211.07:42:01.24#ibcon#enter sib2, iclass 38, count 2 2006.211.07:42:01.24#ibcon#flushed, iclass 38, count 2 2006.211.07:42:01.24#ibcon#about to write, iclass 38, count 2 2006.211.07:42:01.24#ibcon#wrote, iclass 38, count 2 2006.211.07:42:01.24#ibcon#about to read 3, iclass 38, count 2 2006.211.07:42:01.26#ibcon#read 3, iclass 38, count 2 2006.211.07:42:01.26#ibcon#about to read 4, iclass 38, count 2 2006.211.07:42:01.26#ibcon#read 4, iclass 38, count 2 2006.211.07:42:01.26#ibcon#about to read 5, iclass 38, count 2 2006.211.07:42:01.26#ibcon#read 5, iclass 38, count 2 2006.211.07:42:01.26#ibcon#about to read 6, iclass 38, count 2 2006.211.07:42:01.26#ibcon#read 6, iclass 38, count 2 2006.211.07:42:01.26#ibcon#end of sib2, iclass 38, count 2 2006.211.07:42:01.26#ibcon#*mode == 0, iclass 38, count 2 2006.211.07:42:01.26#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.07:42:01.26#ibcon#[27=AT04-03\r\n] 2006.211.07:42:01.26#ibcon#*before write, iclass 38, count 2 2006.211.07:42:01.26#ibcon#enter sib2, iclass 38, count 2 2006.211.07:42:01.26#ibcon#flushed, iclass 38, count 2 2006.211.07:42:01.26#ibcon#about to write, iclass 38, count 2 2006.211.07:42:01.26#ibcon#wrote, iclass 38, count 2 2006.211.07:42:01.26#ibcon#about to read 3, iclass 38, count 2 2006.211.07:42:01.29#ibcon#read 3, iclass 38, count 2 2006.211.07:42:01.29#ibcon#about to read 4, iclass 38, count 2 2006.211.07:42:01.29#ibcon#read 4, iclass 38, count 2 2006.211.07:42:01.29#ibcon#about to read 5, iclass 38, count 2 2006.211.07:42:01.29#ibcon#read 5, iclass 38, count 2 2006.211.07:42:01.29#ibcon#about to read 6, iclass 38, count 2 2006.211.07:42:01.29#ibcon#read 6, iclass 38, count 2 2006.211.07:42:01.29#ibcon#end of sib2, iclass 38, count 2 2006.211.07:42:01.29#ibcon#*after write, iclass 38, count 2 2006.211.07:42:01.29#ibcon#*before return 0, iclass 38, count 2 2006.211.07:42:01.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:42:01.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:42:01.29#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.07:42:01.29#ibcon#ireg 7 cls_cnt 0 2006.211.07:42:01.29#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:42:01.41#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:42:01.41#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:42:01.41#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:42:01.41#ibcon#first serial, iclass 38, count 0 2006.211.07:42:01.41#ibcon#enter sib2, iclass 38, count 0 2006.211.07:42:01.41#ibcon#flushed, iclass 38, count 0 2006.211.07:42:01.41#ibcon#about to write, iclass 38, count 0 2006.211.07:42:01.41#ibcon#wrote, iclass 38, count 0 2006.211.07:42:01.41#ibcon#about to read 3, iclass 38, count 0 2006.211.07:42:01.43#ibcon#read 3, iclass 38, count 0 2006.211.07:42:01.43#ibcon#about to read 4, iclass 38, count 0 2006.211.07:42:01.43#ibcon#read 4, iclass 38, count 0 2006.211.07:42:01.43#ibcon#about to read 5, iclass 38, count 0 2006.211.07:42:01.43#ibcon#read 5, iclass 38, count 0 2006.211.07:42:01.43#ibcon#about to read 6, iclass 38, count 0 2006.211.07:42:01.43#ibcon#read 6, iclass 38, count 0 2006.211.07:42:01.43#ibcon#end of sib2, iclass 38, count 0 2006.211.07:42:01.43#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:42:01.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:42:01.43#ibcon#[27=USB\r\n] 2006.211.07:42:01.43#ibcon#*before write, iclass 38, count 0 2006.211.07:42:01.43#ibcon#enter sib2, iclass 38, count 0 2006.211.07:42:01.43#ibcon#flushed, iclass 38, count 0 2006.211.07:42:01.43#ibcon#about to write, iclass 38, count 0 2006.211.07:42:01.43#ibcon#wrote, iclass 38, count 0 2006.211.07:42:01.43#ibcon#about to read 3, iclass 38, count 0 2006.211.07:42:01.46#ibcon#read 3, iclass 38, count 0 2006.211.07:42:01.46#ibcon#about to read 4, iclass 38, count 0 2006.211.07:42:01.46#ibcon#read 4, iclass 38, count 0 2006.211.07:42:01.46#ibcon#about to read 5, iclass 38, count 0 2006.211.07:42:01.46#ibcon#read 5, iclass 38, count 0 2006.211.07:42:01.46#ibcon#about to read 6, iclass 38, count 0 2006.211.07:42:01.46#ibcon#read 6, iclass 38, count 0 2006.211.07:42:01.46#ibcon#end of sib2, iclass 38, count 0 2006.211.07:42:01.46#ibcon#*after write, iclass 38, count 0 2006.211.07:42:01.46#ibcon#*before return 0, iclass 38, count 0 2006.211.07:42:01.46#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:42:01.46#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:42:01.46#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:42:01.46#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:42:01.46$vc4f8/vblo=5,744.99 2006.211.07:42:01.46#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:42:01.46#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:42:01.46#ibcon#ireg 17 cls_cnt 0 2006.211.07:42:01.46#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:42:01.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:42:01.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:42:01.46#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:42:01.46#ibcon#first serial, iclass 40, count 0 2006.211.07:42:01.46#ibcon#enter sib2, iclass 40, count 0 2006.211.07:42:01.46#ibcon#flushed, iclass 40, count 0 2006.211.07:42:01.46#ibcon#about to write, iclass 40, count 0 2006.211.07:42:01.46#ibcon#wrote, iclass 40, count 0 2006.211.07:42:01.46#ibcon#about to read 3, iclass 40, count 0 2006.211.07:42:01.48#ibcon#read 3, iclass 40, count 0 2006.211.07:42:01.48#ibcon#about to read 4, iclass 40, count 0 2006.211.07:42:01.48#ibcon#read 4, iclass 40, count 0 2006.211.07:42:01.48#ibcon#about to read 5, iclass 40, count 0 2006.211.07:42:01.48#ibcon#read 5, iclass 40, count 0 2006.211.07:42:01.48#ibcon#about to read 6, iclass 40, count 0 2006.211.07:42:01.48#ibcon#read 6, iclass 40, count 0 2006.211.07:42:01.48#ibcon#end of sib2, iclass 40, count 0 2006.211.07:42:01.48#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:42:01.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:42:01.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:42:01.48#ibcon#*before write, iclass 40, count 0 2006.211.07:42:01.48#ibcon#enter sib2, iclass 40, count 0 2006.211.07:42:01.48#ibcon#flushed, iclass 40, count 0 2006.211.07:42:01.48#ibcon#about to write, iclass 40, count 0 2006.211.07:42:01.48#ibcon#wrote, iclass 40, count 0 2006.211.07:42:01.48#ibcon#about to read 3, iclass 40, count 0 2006.211.07:42:01.52#ibcon#read 3, iclass 40, count 0 2006.211.07:42:01.52#ibcon#about to read 4, iclass 40, count 0 2006.211.07:42:01.52#ibcon#read 4, iclass 40, count 0 2006.211.07:42:01.52#ibcon#about to read 5, iclass 40, count 0 2006.211.07:42:01.52#ibcon#read 5, iclass 40, count 0 2006.211.07:42:01.52#ibcon#about to read 6, iclass 40, count 0 2006.211.07:42:01.52#ibcon#read 6, iclass 40, count 0 2006.211.07:42:01.52#ibcon#end of sib2, iclass 40, count 0 2006.211.07:42:01.52#ibcon#*after write, iclass 40, count 0 2006.211.07:42:01.52#ibcon#*before return 0, iclass 40, count 0 2006.211.07:42:01.52#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:42:01.52#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:42:01.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:42:01.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:42:01.52$vc4f8/vb=5,3 2006.211.07:42:01.52#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:42:01.52#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:42:01.52#ibcon#ireg 11 cls_cnt 2 2006.211.07:42:01.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:42:01.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:42:01.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:42:01.58#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:42:01.58#ibcon#first serial, iclass 4, count 2 2006.211.07:42:01.58#ibcon#enter sib2, iclass 4, count 2 2006.211.07:42:01.58#ibcon#flushed, iclass 4, count 2 2006.211.07:42:01.58#ibcon#about to write, iclass 4, count 2 2006.211.07:42:01.58#ibcon#wrote, iclass 4, count 2 2006.211.07:42:01.58#ibcon#about to read 3, iclass 4, count 2 2006.211.07:42:01.60#ibcon#read 3, iclass 4, count 2 2006.211.07:42:01.60#ibcon#about to read 4, iclass 4, count 2 2006.211.07:42:01.60#ibcon#read 4, iclass 4, count 2 2006.211.07:42:01.60#ibcon#about to read 5, iclass 4, count 2 2006.211.07:42:01.60#ibcon#read 5, iclass 4, count 2 2006.211.07:42:01.60#ibcon#about to read 6, iclass 4, count 2 2006.211.07:42:01.60#ibcon#read 6, iclass 4, count 2 2006.211.07:42:01.60#ibcon#end of sib2, iclass 4, count 2 2006.211.07:42:01.60#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:42:01.60#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:42:01.60#ibcon#[27=AT05-03\r\n] 2006.211.07:42:01.60#ibcon#*before write, iclass 4, count 2 2006.211.07:42:01.60#ibcon#enter sib2, iclass 4, count 2 2006.211.07:42:01.60#ibcon#flushed, iclass 4, count 2 2006.211.07:42:01.60#ibcon#about to write, iclass 4, count 2 2006.211.07:42:01.60#ibcon#wrote, iclass 4, count 2 2006.211.07:42:01.60#ibcon#about to read 3, iclass 4, count 2 2006.211.07:42:01.63#ibcon#read 3, iclass 4, count 2 2006.211.07:42:01.63#ibcon#about to read 4, iclass 4, count 2 2006.211.07:42:01.63#ibcon#read 4, iclass 4, count 2 2006.211.07:42:01.63#ibcon#about to read 5, iclass 4, count 2 2006.211.07:42:01.63#ibcon#read 5, iclass 4, count 2 2006.211.07:42:01.63#ibcon#about to read 6, iclass 4, count 2 2006.211.07:42:01.63#ibcon#read 6, iclass 4, count 2 2006.211.07:42:01.63#ibcon#end of sib2, iclass 4, count 2 2006.211.07:42:01.63#ibcon#*after write, iclass 4, count 2 2006.211.07:42:01.63#ibcon#*before return 0, iclass 4, count 2 2006.211.07:42:01.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:42:01.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:42:01.63#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:42:01.63#ibcon#ireg 7 cls_cnt 0 2006.211.07:42:01.63#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:42:01.75#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:42:01.75#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:42:01.75#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:42:01.75#ibcon#first serial, iclass 4, count 0 2006.211.07:42:01.75#ibcon#enter sib2, iclass 4, count 0 2006.211.07:42:01.75#ibcon#flushed, iclass 4, count 0 2006.211.07:42:01.75#ibcon#about to write, iclass 4, count 0 2006.211.07:42:01.75#ibcon#wrote, iclass 4, count 0 2006.211.07:42:01.75#ibcon#about to read 3, iclass 4, count 0 2006.211.07:42:01.77#ibcon#read 3, iclass 4, count 0 2006.211.07:42:01.77#ibcon#about to read 4, iclass 4, count 0 2006.211.07:42:01.77#ibcon#read 4, iclass 4, count 0 2006.211.07:42:01.77#ibcon#about to read 5, iclass 4, count 0 2006.211.07:42:01.77#ibcon#read 5, iclass 4, count 0 2006.211.07:42:01.77#ibcon#about to read 6, iclass 4, count 0 2006.211.07:42:01.77#ibcon#read 6, iclass 4, count 0 2006.211.07:42:01.77#ibcon#end of sib2, iclass 4, count 0 2006.211.07:42:01.77#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:42:01.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:42:01.77#ibcon#[27=USB\r\n] 2006.211.07:42:01.77#ibcon#*before write, iclass 4, count 0 2006.211.07:42:01.77#ibcon#enter sib2, iclass 4, count 0 2006.211.07:42:01.77#ibcon#flushed, iclass 4, count 0 2006.211.07:42:01.77#ibcon#about to write, iclass 4, count 0 2006.211.07:42:01.77#ibcon#wrote, iclass 4, count 0 2006.211.07:42:01.77#ibcon#about to read 3, iclass 4, count 0 2006.211.07:42:01.80#ibcon#read 3, iclass 4, count 0 2006.211.07:42:01.80#ibcon#about to read 4, iclass 4, count 0 2006.211.07:42:01.80#ibcon#read 4, iclass 4, count 0 2006.211.07:42:01.80#ibcon#about to read 5, iclass 4, count 0 2006.211.07:42:01.80#ibcon#read 5, iclass 4, count 0 2006.211.07:42:01.80#ibcon#about to read 6, iclass 4, count 0 2006.211.07:42:01.80#ibcon#read 6, iclass 4, count 0 2006.211.07:42:01.80#ibcon#end of sib2, iclass 4, count 0 2006.211.07:42:01.80#ibcon#*after write, iclass 4, count 0 2006.211.07:42:01.80#ibcon#*before return 0, iclass 4, count 0 2006.211.07:42:01.80#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:42:01.80#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:42:01.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:42:01.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:42:01.80$vc4f8/vblo=6,752.99 2006.211.07:42:01.80#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:42:01.80#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:42:01.80#ibcon#ireg 17 cls_cnt 0 2006.211.07:42:01.80#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:42:01.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:42:01.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:42:01.80#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:42:01.80#ibcon#first serial, iclass 6, count 0 2006.211.07:42:01.80#ibcon#enter sib2, iclass 6, count 0 2006.211.07:42:01.80#ibcon#flushed, iclass 6, count 0 2006.211.07:42:01.80#ibcon#about to write, iclass 6, count 0 2006.211.07:42:01.80#ibcon#wrote, iclass 6, count 0 2006.211.07:42:01.80#ibcon#about to read 3, iclass 6, count 0 2006.211.07:42:01.82#ibcon#read 3, iclass 6, count 0 2006.211.07:42:01.82#ibcon#about to read 4, iclass 6, count 0 2006.211.07:42:01.82#ibcon#read 4, iclass 6, count 0 2006.211.07:42:01.82#ibcon#about to read 5, iclass 6, count 0 2006.211.07:42:01.82#ibcon#read 5, iclass 6, count 0 2006.211.07:42:01.82#ibcon#about to read 6, iclass 6, count 0 2006.211.07:42:01.82#ibcon#read 6, iclass 6, count 0 2006.211.07:42:01.82#ibcon#end of sib2, iclass 6, count 0 2006.211.07:42:01.82#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:42:01.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:42:01.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:42:01.82#ibcon#*before write, iclass 6, count 0 2006.211.07:42:01.82#ibcon#enter sib2, iclass 6, count 0 2006.211.07:42:01.82#ibcon#flushed, iclass 6, count 0 2006.211.07:42:01.82#ibcon#about to write, iclass 6, count 0 2006.211.07:42:01.82#ibcon#wrote, iclass 6, count 0 2006.211.07:42:01.82#ibcon#about to read 3, iclass 6, count 0 2006.211.07:42:01.86#ibcon#read 3, iclass 6, count 0 2006.211.07:42:01.86#ibcon#about to read 4, iclass 6, count 0 2006.211.07:42:01.86#ibcon#read 4, iclass 6, count 0 2006.211.07:42:01.86#ibcon#about to read 5, iclass 6, count 0 2006.211.07:42:01.86#ibcon#read 5, iclass 6, count 0 2006.211.07:42:01.86#ibcon#about to read 6, iclass 6, count 0 2006.211.07:42:01.86#ibcon#read 6, iclass 6, count 0 2006.211.07:42:01.86#ibcon#end of sib2, iclass 6, count 0 2006.211.07:42:01.86#ibcon#*after write, iclass 6, count 0 2006.211.07:42:01.86#ibcon#*before return 0, iclass 6, count 0 2006.211.07:42:01.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:42:01.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:42:01.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:42:01.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:42:01.86$vc4f8/vb=6,3 2006.211.07:42:01.86#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:42:01.86#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:42:01.86#ibcon#ireg 11 cls_cnt 2 2006.211.07:42:01.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:42:01.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:42:01.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:42:01.92#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:42:01.92#ibcon#first serial, iclass 10, count 2 2006.211.07:42:01.92#ibcon#enter sib2, iclass 10, count 2 2006.211.07:42:01.92#ibcon#flushed, iclass 10, count 2 2006.211.07:42:01.92#ibcon#about to write, iclass 10, count 2 2006.211.07:42:01.92#ibcon#wrote, iclass 10, count 2 2006.211.07:42:01.92#ibcon#about to read 3, iclass 10, count 2 2006.211.07:42:01.94#ibcon#read 3, iclass 10, count 2 2006.211.07:42:01.94#ibcon#about to read 4, iclass 10, count 2 2006.211.07:42:01.94#ibcon#read 4, iclass 10, count 2 2006.211.07:42:01.94#ibcon#about to read 5, iclass 10, count 2 2006.211.07:42:01.94#ibcon#read 5, iclass 10, count 2 2006.211.07:42:01.94#ibcon#about to read 6, iclass 10, count 2 2006.211.07:42:01.94#ibcon#read 6, iclass 10, count 2 2006.211.07:42:01.94#ibcon#end of sib2, iclass 10, count 2 2006.211.07:42:01.94#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:42:01.94#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:42:01.94#ibcon#[27=AT06-03\r\n] 2006.211.07:42:01.94#ibcon#*before write, iclass 10, count 2 2006.211.07:42:01.94#ibcon#enter sib2, iclass 10, count 2 2006.211.07:42:01.94#ibcon#flushed, iclass 10, count 2 2006.211.07:42:01.94#ibcon#about to write, iclass 10, count 2 2006.211.07:42:01.94#ibcon#wrote, iclass 10, count 2 2006.211.07:42:01.94#ibcon#about to read 3, iclass 10, count 2 2006.211.07:42:01.97#ibcon#read 3, iclass 10, count 2 2006.211.07:42:01.97#ibcon#about to read 4, iclass 10, count 2 2006.211.07:42:01.97#ibcon#read 4, iclass 10, count 2 2006.211.07:42:01.97#ibcon#about to read 5, iclass 10, count 2 2006.211.07:42:01.97#ibcon#read 5, iclass 10, count 2 2006.211.07:42:01.97#ibcon#about to read 6, iclass 10, count 2 2006.211.07:42:01.97#ibcon#read 6, iclass 10, count 2 2006.211.07:42:01.97#ibcon#end of sib2, iclass 10, count 2 2006.211.07:42:01.97#ibcon#*after write, iclass 10, count 2 2006.211.07:42:01.97#ibcon#*before return 0, iclass 10, count 2 2006.211.07:42:01.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:42:01.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:42:01.97#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:42:01.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:42:01.97#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:42:02.09#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:42:02.09#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:42:02.09#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:42:02.09#ibcon#first serial, iclass 10, count 0 2006.211.07:42:02.09#ibcon#enter sib2, iclass 10, count 0 2006.211.07:42:02.09#ibcon#flushed, iclass 10, count 0 2006.211.07:42:02.09#ibcon#about to write, iclass 10, count 0 2006.211.07:42:02.09#ibcon#wrote, iclass 10, count 0 2006.211.07:42:02.09#ibcon#about to read 3, iclass 10, count 0 2006.211.07:42:02.11#ibcon#read 3, iclass 10, count 0 2006.211.07:42:02.11#ibcon#about to read 4, iclass 10, count 0 2006.211.07:42:02.11#ibcon#read 4, iclass 10, count 0 2006.211.07:42:02.11#ibcon#about to read 5, iclass 10, count 0 2006.211.07:42:02.11#ibcon#read 5, iclass 10, count 0 2006.211.07:42:02.11#ibcon#about to read 6, iclass 10, count 0 2006.211.07:42:02.11#ibcon#read 6, iclass 10, count 0 2006.211.07:42:02.11#ibcon#end of sib2, iclass 10, count 0 2006.211.07:42:02.11#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:42:02.11#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:42:02.11#ibcon#[27=USB\r\n] 2006.211.07:42:02.11#ibcon#*before write, iclass 10, count 0 2006.211.07:42:02.11#ibcon#enter sib2, iclass 10, count 0 2006.211.07:42:02.11#ibcon#flushed, iclass 10, count 0 2006.211.07:42:02.11#ibcon#about to write, iclass 10, count 0 2006.211.07:42:02.11#ibcon#wrote, iclass 10, count 0 2006.211.07:42:02.11#ibcon#about to read 3, iclass 10, count 0 2006.211.07:42:02.14#ibcon#read 3, iclass 10, count 0 2006.211.07:42:02.14#ibcon#about to read 4, iclass 10, count 0 2006.211.07:42:02.14#ibcon#read 4, iclass 10, count 0 2006.211.07:42:02.14#ibcon#about to read 5, iclass 10, count 0 2006.211.07:42:02.14#ibcon#read 5, iclass 10, count 0 2006.211.07:42:02.14#ibcon#about to read 6, iclass 10, count 0 2006.211.07:42:02.14#ibcon#read 6, iclass 10, count 0 2006.211.07:42:02.14#ibcon#end of sib2, iclass 10, count 0 2006.211.07:42:02.14#ibcon#*after write, iclass 10, count 0 2006.211.07:42:02.14#ibcon#*before return 0, iclass 10, count 0 2006.211.07:42:02.14#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:42:02.14#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:42:02.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:42:02.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:42:02.14$vc4f8/vabw=wide 2006.211.07:42:02.14#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:42:02.14#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:42:02.14#ibcon#ireg 8 cls_cnt 0 2006.211.07:42:02.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:42:02.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:42:02.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:42:02.14#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:42:02.14#ibcon#first serial, iclass 12, count 0 2006.211.07:42:02.14#ibcon#enter sib2, iclass 12, count 0 2006.211.07:42:02.14#ibcon#flushed, iclass 12, count 0 2006.211.07:42:02.14#ibcon#about to write, iclass 12, count 0 2006.211.07:42:02.14#ibcon#wrote, iclass 12, count 0 2006.211.07:42:02.14#ibcon#about to read 3, iclass 12, count 0 2006.211.07:42:02.16#ibcon#read 3, iclass 12, count 0 2006.211.07:42:02.16#ibcon#about to read 4, iclass 12, count 0 2006.211.07:42:02.16#ibcon#read 4, iclass 12, count 0 2006.211.07:42:02.16#ibcon#about to read 5, iclass 12, count 0 2006.211.07:42:02.16#ibcon#read 5, iclass 12, count 0 2006.211.07:42:02.16#ibcon#about to read 6, iclass 12, count 0 2006.211.07:42:02.16#ibcon#read 6, iclass 12, count 0 2006.211.07:42:02.16#ibcon#end of sib2, iclass 12, count 0 2006.211.07:42:02.16#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:42:02.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:42:02.16#ibcon#[25=BW32\r\n] 2006.211.07:42:02.16#ibcon#*before write, iclass 12, count 0 2006.211.07:42:02.16#ibcon#enter sib2, iclass 12, count 0 2006.211.07:42:02.16#ibcon#flushed, iclass 12, count 0 2006.211.07:42:02.16#ibcon#about to write, iclass 12, count 0 2006.211.07:42:02.16#ibcon#wrote, iclass 12, count 0 2006.211.07:42:02.16#ibcon#about to read 3, iclass 12, count 0 2006.211.07:42:02.19#ibcon#read 3, iclass 12, count 0 2006.211.07:42:02.19#ibcon#about to read 4, iclass 12, count 0 2006.211.07:42:02.19#ibcon#read 4, iclass 12, count 0 2006.211.07:42:02.19#ibcon#about to read 5, iclass 12, count 0 2006.211.07:42:02.19#ibcon#read 5, iclass 12, count 0 2006.211.07:42:02.19#ibcon#about to read 6, iclass 12, count 0 2006.211.07:42:02.19#ibcon#read 6, iclass 12, count 0 2006.211.07:42:02.19#ibcon#end of sib2, iclass 12, count 0 2006.211.07:42:02.19#ibcon#*after write, iclass 12, count 0 2006.211.07:42:02.19#ibcon#*before return 0, iclass 12, count 0 2006.211.07:42:02.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:42:02.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:42:02.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:42:02.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:42:02.19$vc4f8/vbbw=wide 2006.211.07:42:02.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.07:42:02.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.07:42:02.19#ibcon#ireg 8 cls_cnt 0 2006.211.07:42:02.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:42:02.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:42:02.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:42:02.26#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:42:02.26#ibcon#first serial, iclass 14, count 0 2006.211.07:42:02.26#ibcon#enter sib2, iclass 14, count 0 2006.211.07:42:02.26#ibcon#flushed, iclass 14, count 0 2006.211.07:42:02.26#ibcon#about to write, iclass 14, count 0 2006.211.07:42:02.26#ibcon#wrote, iclass 14, count 0 2006.211.07:42:02.26#ibcon#about to read 3, iclass 14, count 0 2006.211.07:42:02.28#ibcon#read 3, iclass 14, count 0 2006.211.07:42:02.28#ibcon#about to read 4, iclass 14, count 0 2006.211.07:42:02.28#ibcon#read 4, iclass 14, count 0 2006.211.07:42:02.28#ibcon#about to read 5, iclass 14, count 0 2006.211.07:42:02.28#ibcon#read 5, iclass 14, count 0 2006.211.07:42:02.28#ibcon#about to read 6, iclass 14, count 0 2006.211.07:42:02.28#ibcon#read 6, iclass 14, count 0 2006.211.07:42:02.28#ibcon#end of sib2, iclass 14, count 0 2006.211.07:42:02.28#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:42:02.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:42:02.28#ibcon#[27=BW32\r\n] 2006.211.07:42:02.28#ibcon#*before write, iclass 14, count 0 2006.211.07:42:02.28#ibcon#enter sib2, iclass 14, count 0 2006.211.07:42:02.28#ibcon#flushed, iclass 14, count 0 2006.211.07:42:02.28#ibcon#about to write, iclass 14, count 0 2006.211.07:42:02.28#ibcon#wrote, iclass 14, count 0 2006.211.07:42:02.28#ibcon#about to read 3, iclass 14, count 0 2006.211.07:42:02.31#ibcon#read 3, iclass 14, count 0 2006.211.07:42:02.31#ibcon#about to read 4, iclass 14, count 0 2006.211.07:42:02.31#ibcon#read 4, iclass 14, count 0 2006.211.07:42:02.31#ibcon#about to read 5, iclass 14, count 0 2006.211.07:42:02.31#ibcon#read 5, iclass 14, count 0 2006.211.07:42:02.31#ibcon#about to read 6, iclass 14, count 0 2006.211.07:42:02.31#ibcon#read 6, iclass 14, count 0 2006.211.07:42:02.31#ibcon#end of sib2, iclass 14, count 0 2006.211.07:42:02.31#ibcon#*after write, iclass 14, count 0 2006.211.07:42:02.31#ibcon#*before return 0, iclass 14, count 0 2006.211.07:42:02.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:42:02.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:42:02.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:42:02.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:42:02.31$4f8m12a/ifd4f 2006.211.07:42:02.31$ifd4f/lo= 2006.211.07:42:02.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:42:02.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:42:02.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:42:02.31$ifd4f/patch= 2006.211.07:42:02.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:42:02.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:42:02.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:42:02.31$4f8m12a/"form=m,16.000,1:2 2006.211.07:42:02.31$4f8m12a/"tpicd 2006.211.07:42:02.31$4f8m12a/echo=off 2006.211.07:42:02.31$4f8m12a/xlog=off 2006.211.07:42:02.31:!2006.211.07:42:30 2006.211.07:42:13.14#trakl#Source acquired 2006.211.07:42:15.14#flagr#flagr/antenna,acquired 2006.211.07:42:30.00:preob 2006.211.07:42:31.14/onsource/TRACKING 2006.211.07:42:31.14:!2006.211.07:42:40 2006.211.07:42:40.00:data_valid=on 2006.211.07:42:40.00:midob 2006.211.07:42:40.14/onsource/TRACKING 2006.211.07:42:40.14/wx/24.95,1010.1,75 2006.211.07:42:40.26/cable/+6.4376E-03 2006.211.07:42:41.35/va/01,08,usb,yes,28,30 2006.211.07:42:41.35/va/02,07,usb,yes,28,30 2006.211.07:42:41.35/va/03,06,usb,yes,30,30 2006.211.07:42:41.35/va/04,07,usb,yes,29,31 2006.211.07:42:41.35/va/05,07,usb,yes,32,34 2006.211.07:42:41.35/va/06,06,usb,yes,31,31 2006.211.07:42:41.35/va/07,06,usb,yes,32,31 2006.211.07:42:41.35/va/08,07,usb,yes,30,29 2006.211.07:42:41.58/valo/01,532.99,yes,locked 2006.211.07:42:41.58/valo/02,572.99,yes,locked 2006.211.07:42:41.58/valo/03,672.99,yes,locked 2006.211.07:42:41.58/valo/04,832.99,yes,locked 2006.211.07:42:41.58/valo/05,652.99,yes,locked 2006.211.07:42:41.58/valo/06,772.99,yes,locked 2006.211.07:42:41.58/valo/07,832.99,yes,locked 2006.211.07:42:41.58/valo/08,852.99,yes,locked 2006.211.07:42:42.67/vb/01,04,usb,yes,28,27 2006.211.07:42:42.67/vb/02,04,usb,yes,31,32 2006.211.07:42:42.67/vb/03,03,usb,yes,33,39 2006.211.07:42:42.67/vb/04,03,usb,yes,34,34 2006.211.07:42:42.67/vb/05,03,usb,yes,32,37 2006.211.07:42:42.67/vb/06,03,usb,yes,33,36 2006.211.07:42:42.67/vb/07,04,usb,yes,29,29 2006.211.07:42:42.67/vb/08,03,usb,yes,33,37 2006.211.07:42:42.90/vblo/01,632.99,yes,locked 2006.211.07:42:42.90/vblo/02,640.99,yes,locked 2006.211.07:42:42.90/vblo/03,656.99,yes,locked 2006.211.07:42:42.90/vblo/04,712.99,yes,locked 2006.211.07:42:42.90/vblo/05,744.99,yes,locked 2006.211.07:42:42.90/vblo/06,752.99,yes,locked 2006.211.07:42:42.90/vblo/07,734.99,yes,locked 2006.211.07:42:42.90/vblo/08,744.99,yes,locked 2006.211.07:42:43.05/vabw/8 2006.211.07:42:43.20/vbbw/8 2006.211.07:42:43.29/xfe/off,on,15.2 2006.211.07:42:43.68/ifatt/23,28,28,28 2006.211.07:42:44.07/fmout-gps/S +4.48E-07 2006.211.07:42:44.11:!2006.211.07:43:40 2006.211.07:43:40.00:data_valid=off 2006.211.07:43:40.00:postob 2006.211.07:43:40.11/cable/+6.4372E-03 2006.211.07:43:40.11/wx/24.94,1010.1,76 2006.211.07:43:41.08/fmout-gps/S +4.48E-07 2006.211.07:43:41.08:scan_name=211-0744,k06211,60 2006.211.07:43:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.211.07:43:41.14#flagr#flagr/antenna,new-source 2006.211.07:43:42.14:checkk5 2006.211.07:43:42.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:43:42.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:43:43.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:43:43.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:43:43.84/chk_obsdata//k5ts1/T2110742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:43:44.18/chk_obsdata//k5ts2/T2110742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:43:44.51/chk_obsdata//k5ts3/T2110742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:43:44.84/chk_obsdata//k5ts4/T2110742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:43:45.49/k5log//k5ts1_log_newline 2006.211.07:43:46.15/k5log//k5ts2_log_newline 2006.211.07:43:46.81/k5log//k5ts3_log_newline 2006.211.07:43:47.46/k5log//k5ts4_log_newline 2006.211.07:43:47.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:43:47.48:4f8m12a=1 2006.211.07:43:47.48$4f8m12a/echo=on 2006.211.07:43:47.48$4f8m12a/pcalon 2006.211.07:43:47.48$pcalon/"no phase cal control is implemented here 2006.211.07:43:47.48$4f8m12a/"tpicd=stop 2006.211.07:43:47.48$4f8m12a/vc4f8 2006.211.07:43:47.48$vc4f8/valo=1,532.99 2006.211.07:43:47.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.07:43:47.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.07:43:47.48#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:47.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:47.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:47.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:47.48#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:43:47.48#ibcon#first serial, iclass 21, count 0 2006.211.07:43:47.48#ibcon#enter sib2, iclass 21, count 0 2006.211.07:43:47.48#ibcon#flushed, iclass 21, count 0 2006.211.07:43:47.48#ibcon#about to write, iclass 21, count 0 2006.211.07:43:47.48#ibcon#wrote, iclass 21, count 0 2006.211.07:43:47.48#ibcon#about to read 3, iclass 21, count 0 2006.211.07:43:47.50#ibcon#read 3, iclass 21, count 0 2006.211.07:43:47.50#ibcon#about to read 4, iclass 21, count 0 2006.211.07:43:47.50#ibcon#read 4, iclass 21, count 0 2006.211.07:43:47.50#ibcon#about to read 5, iclass 21, count 0 2006.211.07:43:47.50#ibcon#read 5, iclass 21, count 0 2006.211.07:43:47.50#ibcon#about to read 6, iclass 21, count 0 2006.211.07:43:47.50#ibcon#read 6, iclass 21, count 0 2006.211.07:43:47.50#ibcon#end of sib2, iclass 21, count 0 2006.211.07:43:47.50#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:43:47.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:43:47.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:43:47.50#ibcon#*before write, iclass 21, count 0 2006.211.07:43:47.50#ibcon#enter sib2, iclass 21, count 0 2006.211.07:43:47.50#ibcon#flushed, iclass 21, count 0 2006.211.07:43:47.50#ibcon#about to write, iclass 21, count 0 2006.211.07:43:47.50#ibcon#wrote, iclass 21, count 0 2006.211.07:43:47.50#ibcon#about to read 3, iclass 21, count 0 2006.211.07:43:47.55#ibcon#read 3, iclass 21, count 0 2006.211.07:43:47.55#ibcon#about to read 4, iclass 21, count 0 2006.211.07:43:47.55#ibcon#read 4, iclass 21, count 0 2006.211.07:43:47.55#ibcon#about to read 5, iclass 21, count 0 2006.211.07:43:47.55#ibcon#read 5, iclass 21, count 0 2006.211.07:43:47.55#ibcon#about to read 6, iclass 21, count 0 2006.211.07:43:47.55#ibcon#read 6, iclass 21, count 0 2006.211.07:43:47.55#ibcon#end of sib2, iclass 21, count 0 2006.211.07:43:47.55#ibcon#*after write, iclass 21, count 0 2006.211.07:43:47.55#ibcon#*before return 0, iclass 21, count 0 2006.211.07:43:47.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:47.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:47.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:43:47.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:43:47.55$vc4f8/va=1,8 2006.211.07:43:47.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.07:43:47.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.07:43:47.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:47.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:47.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:47.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:47.55#ibcon#enter wrdev, iclass 23, count 2 2006.211.07:43:47.55#ibcon#first serial, iclass 23, count 2 2006.211.07:43:47.55#ibcon#enter sib2, iclass 23, count 2 2006.211.07:43:47.55#ibcon#flushed, iclass 23, count 2 2006.211.07:43:47.55#ibcon#about to write, iclass 23, count 2 2006.211.07:43:47.55#ibcon#wrote, iclass 23, count 2 2006.211.07:43:47.55#ibcon#about to read 3, iclass 23, count 2 2006.211.07:43:47.57#ibcon#read 3, iclass 23, count 2 2006.211.07:43:47.57#ibcon#about to read 4, iclass 23, count 2 2006.211.07:43:47.57#ibcon#read 4, iclass 23, count 2 2006.211.07:43:47.57#ibcon#about to read 5, iclass 23, count 2 2006.211.07:43:47.57#ibcon#read 5, iclass 23, count 2 2006.211.07:43:47.57#ibcon#about to read 6, iclass 23, count 2 2006.211.07:43:47.57#ibcon#read 6, iclass 23, count 2 2006.211.07:43:47.57#ibcon#end of sib2, iclass 23, count 2 2006.211.07:43:47.57#ibcon#*mode == 0, iclass 23, count 2 2006.211.07:43:47.57#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.07:43:47.57#ibcon#[25=AT01-08\r\n] 2006.211.07:43:47.57#ibcon#*before write, iclass 23, count 2 2006.211.07:43:47.57#ibcon#enter sib2, iclass 23, count 2 2006.211.07:43:47.57#ibcon#flushed, iclass 23, count 2 2006.211.07:43:47.57#ibcon#about to write, iclass 23, count 2 2006.211.07:43:47.57#ibcon#wrote, iclass 23, count 2 2006.211.07:43:47.57#ibcon#about to read 3, iclass 23, count 2 2006.211.07:43:47.60#ibcon#read 3, iclass 23, count 2 2006.211.07:43:47.60#ibcon#about to read 4, iclass 23, count 2 2006.211.07:43:47.60#ibcon#read 4, iclass 23, count 2 2006.211.07:43:47.60#ibcon#about to read 5, iclass 23, count 2 2006.211.07:43:47.60#ibcon#read 5, iclass 23, count 2 2006.211.07:43:47.60#ibcon#about to read 6, iclass 23, count 2 2006.211.07:43:47.60#ibcon#read 6, iclass 23, count 2 2006.211.07:43:47.60#ibcon#end of sib2, iclass 23, count 2 2006.211.07:43:47.60#ibcon#*after write, iclass 23, count 2 2006.211.07:43:47.60#ibcon#*before return 0, iclass 23, count 2 2006.211.07:43:47.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:47.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:47.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.07:43:47.60#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:47.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:47.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:47.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:47.72#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:43:47.72#ibcon#first serial, iclass 23, count 0 2006.211.07:43:47.72#ibcon#enter sib2, iclass 23, count 0 2006.211.07:43:47.72#ibcon#flushed, iclass 23, count 0 2006.211.07:43:47.72#ibcon#about to write, iclass 23, count 0 2006.211.07:43:47.72#ibcon#wrote, iclass 23, count 0 2006.211.07:43:47.72#ibcon#about to read 3, iclass 23, count 0 2006.211.07:43:47.74#ibcon#read 3, iclass 23, count 0 2006.211.07:43:47.74#ibcon#about to read 4, iclass 23, count 0 2006.211.07:43:47.74#ibcon#read 4, iclass 23, count 0 2006.211.07:43:47.74#ibcon#about to read 5, iclass 23, count 0 2006.211.07:43:47.74#ibcon#read 5, iclass 23, count 0 2006.211.07:43:47.74#ibcon#about to read 6, iclass 23, count 0 2006.211.07:43:47.74#ibcon#read 6, iclass 23, count 0 2006.211.07:43:47.74#ibcon#end of sib2, iclass 23, count 0 2006.211.07:43:47.74#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:43:47.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:43:47.74#ibcon#[25=USB\r\n] 2006.211.07:43:47.74#ibcon#*before write, iclass 23, count 0 2006.211.07:43:47.74#ibcon#enter sib2, iclass 23, count 0 2006.211.07:43:47.74#ibcon#flushed, iclass 23, count 0 2006.211.07:43:47.74#ibcon#about to write, iclass 23, count 0 2006.211.07:43:47.74#ibcon#wrote, iclass 23, count 0 2006.211.07:43:47.74#ibcon#about to read 3, iclass 23, count 0 2006.211.07:43:47.77#ibcon#read 3, iclass 23, count 0 2006.211.07:43:47.77#ibcon#about to read 4, iclass 23, count 0 2006.211.07:43:47.77#ibcon#read 4, iclass 23, count 0 2006.211.07:43:47.77#ibcon#about to read 5, iclass 23, count 0 2006.211.07:43:47.77#ibcon#read 5, iclass 23, count 0 2006.211.07:43:47.77#ibcon#about to read 6, iclass 23, count 0 2006.211.07:43:47.77#ibcon#read 6, iclass 23, count 0 2006.211.07:43:47.77#ibcon#end of sib2, iclass 23, count 0 2006.211.07:43:47.77#ibcon#*after write, iclass 23, count 0 2006.211.07:43:47.77#ibcon#*before return 0, iclass 23, count 0 2006.211.07:43:47.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:47.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:47.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:43:47.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:43:47.77$vc4f8/valo=2,572.99 2006.211.07:43:47.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:43:47.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:43:47.77#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:47.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:47.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:47.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:47.77#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:43:47.77#ibcon#first serial, iclass 25, count 0 2006.211.07:43:47.77#ibcon#enter sib2, iclass 25, count 0 2006.211.07:43:47.77#ibcon#flushed, iclass 25, count 0 2006.211.07:43:47.77#ibcon#about to write, iclass 25, count 0 2006.211.07:43:47.77#ibcon#wrote, iclass 25, count 0 2006.211.07:43:47.77#ibcon#about to read 3, iclass 25, count 0 2006.211.07:43:47.79#ibcon#read 3, iclass 25, count 0 2006.211.07:43:47.79#ibcon#about to read 4, iclass 25, count 0 2006.211.07:43:47.79#ibcon#read 4, iclass 25, count 0 2006.211.07:43:47.79#ibcon#about to read 5, iclass 25, count 0 2006.211.07:43:47.79#ibcon#read 5, iclass 25, count 0 2006.211.07:43:47.79#ibcon#about to read 6, iclass 25, count 0 2006.211.07:43:47.79#ibcon#read 6, iclass 25, count 0 2006.211.07:43:47.79#ibcon#end of sib2, iclass 25, count 0 2006.211.07:43:47.79#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:43:47.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:43:47.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:43:47.79#ibcon#*before write, iclass 25, count 0 2006.211.07:43:47.79#ibcon#enter sib2, iclass 25, count 0 2006.211.07:43:47.79#ibcon#flushed, iclass 25, count 0 2006.211.07:43:47.79#ibcon#about to write, iclass 25, count 0 2006.211.07:43:47.79#ibcon#wrote, iclass 25, count 0 2006.211.07:43:47.79#ibcon#about to read 3, iclass 25, count 0 2006.211.07:43:47.83#ibcon#read 3, iclass 25, count 0 2006.211.07:43:47.83#ibcon#about to read 4, iclass 25, count 0 2006.211.07:43:47.83#ibcon#read 4, iclass 25, count 0 2006.211.07:43:47.83#ibcon#about to read 5, iclass 25, count 0 2006.211.07:43:47.83#ibcon#read 5, iclass 25, count 0 2006.211.07:43:47.83#ibcon#about to read 6, iclass 25, count 0 2006.211.07:43:47.83#ibcon#read 6, iclass 25, count 0 2006.211.07:43:47.83#ibcon#end of sib2, iclass 25, count 0 2006.211.07:43:47.83#ibcon#*after write, iclass 25, count 0 2006.211.07:43:47.83#ibcon#*before return 0, iclass 25, count 0 2006.211.07:43:47.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:47.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:47.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:43:47.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:43:47.83$vc4f8/va=2,7 2006.211.07:43:47.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.07:43:47.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.07:43:47.83#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:47.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:47.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:47.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:47.89#ibcon#enter wrdev, iclass 27, count 2 2006.211.07:43:47.89#ibcon#first serial, iclass 27, count 2 2006.211.07:43:47.89#ibcon#enter sib2, iclass 27, count 2 2006.211.07:43:47.89#ibcon#flushed, iclass 27, count 2 2006.211.07:43:47.89#ibcon#about to write, iclass 27, count 2 2006.211.07:43:47.89#ibcon#wrote, iclass 27, count 2 2006.211.07:43:47.89#ibcon#about to read 3, iclass 27, count 2 2006.211.07:43:47.91#ibcon#read 3, iclass 27, count 2 2006.211.07:43:47.91#ibcon#about to read 4, iclass 27, count 2 2006.211.07:43:47.91#ibcon#read 4, iclass 27, count 2 2006.211.07:43:47.91#ibcon#about to read 5, iclass 27, count 2 2006.211.07:43:47.91#ibcon#read 5, iclass 27, count 2 2006.211.07:43:47.91#ibcon#about to read 6, iclass 27, count 2 2006.211.07:43:47.91#ibcon#read 6, iclass 27, count 2 2006.211.07:43:47.91#ibcon#end of sib2, iclass 27, count 2 2006.211.07:43:47.91#ibcon#*mode == 0, iclass 27, count 2 2006.211.07:43:47.91#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.07:43:47.91#ibcon#[25=AT02-07\r\n] 2006.211.07:43:47.91#ibcon#*before write, iclass 27, count 2 2006.211.07:43:47.91#ibcon#enter sib2, iclass 27, count 2 2006.211.07:43:47.91#ibcon#flushed, iclass 27, count 2 2006.211.07:43:47.91#ibcon#about to write, iclass 27, count 2 2006.211.07:43:47.91#ibcon#wrote, iclass 27, count 2 2006.211.07:43:47.91#ibcon#about to read 3, iclass 27, count 2 2006.211.07:43:47.94#ibcon#read 3, iclass 27, count 2 2006.211.07:43:47.94#ibcon#about to read 4, iclass 27, count 2 2006.211.07:43:47.94#ibcon#read 4, iclass 27, count 2 2006.211.07:43:47.94#ibcon#about to read 5, iclass 27, count 2 2006.211.07:43:47.94#ibcon#read 5, iclass 27, count 2 2006.211.07:43:47.94#ibcon#about to read 6, iclass 27, count 2 2006.211.07:43:47.94#ibcon#read 6, iclass 27, count 2 2006.211.07:43:47.94#ibcon#end of sib2, iclass 27, count 2 2006.211.07:43:47.94#ibcon#*after write, iclass 27, count 2 2006.211.07:43:47.94#ibcon#*before return 0, iclass 27, count 2 2006.211.07:43:47.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:47.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:47.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.07:43:47.94#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:47.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:48.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:48.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:48.06#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:43:48.06#ibcon#first serial, iclass 27, count 0 2006.211.07:43:48.06#ibcon#enter sib2, iclass 27, count 0 2006.211.07:43:48.06#ibcon#flushed, iclass 27, count 0 2006.211.07:43:48.06#ibcon#about to write, iclass 27, count 0 2006.211.07:43:48.06#ibcon#wrote, iclass 27, count 0 2006.211.07:43:48.06#ibcon#about to read 3, iclass 27, count 0 2006.211.07:43:48.08#ibcon#read 3, iclass 27, count 0 2006.211.07:43:48.08#ibcon#about to read 4, iclass 27, count 0 2006.211.07:43:48.08#ibcon#read 4, iclass 27, count 0 2006.211.07:43:48.08#ibcon#about to read 5, iclass 27, count 0 2006.211.07:43:48.08#ibcon#read 5, iclass 27, count 0 2006.211.07:43:48.08#ibcon#about to read 6, iclass 27, count 0 2006.211.07:43:48.08#ibcon#read 6, iclass 27, count 0 2006.211.07:43:48.08#ibcon#end of sib2, iclass 27, count 0 2006.211.07:43:48.08#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:43:48.08#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:43:48.08#ibcon#[25=USB\r\n] 2006.211.07:43:48.08#ibcon#*before write, iclass 27, count 0 2006.211.07:43:48.08#ibcon#enter sib2, iclass 27, count 0 2006.211.07:43:48.08#ibcon#flushed, iclass 27, count 0 2006.211.07:43:48.08#ibcon#about to write, iclass 27, count 0 2006.211.07:43:48.08#ibcon#wrote, iclass 27, count 0 2006.211.07:43:48.08#ibcon#about to read 3, iclass 27, count 0 2006.211.07:43:48.11#ibcon#read 3, iclass 27, count 0 2006.211.07:43:48.11#ibcon#about to read 4, iclass 27, count 0 2006.211.07:43:48.11#ibcon#read 4, iclass 27, count 0 2006.211.07:43:48.11#ibcon#about to read 5, iclass 27, count 0 2006.211.07:43:48.11#ibcon#read 5, iclass 27, count 0 2006.211.07:43:48.11#ibcon#about to read 6, iclass 27, count 0 2006.211.07:43:48.11#ibcon#read 6, iclass 27, count 0 2006.211.07:43:48.11#ibcon#end of sib2, iclass 27, count 0 2006.211.07:43:48.11#ibcon#*after write, iclass 27, count 0 2006.211.07:43:48.11#ibcon#*before return 0, iclass 27, count 0 2006.211.07:43:48.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:48.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:48.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:43:48.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:43:48.11$vc4f8/valo=3,672.99 2006.211.07:43:48.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:43:48.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:43:48.11#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:48.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:48.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:48.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:48.11#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:43:48.11#ibcon#first serial, iclass 29, count 0 2006.211.07:43:48.11#ibcon#enter sib2, iclass 29, count 0 2006.211.07:43:48.11#ibcon#flushed, iclass 29, count 0 2006.211.07:43:48.11#ibcon#about to write, iclass 29, count 0 2006.211.07:43:48.11#ibcon#wrote, iclass 29, count 0 2006.211.07:43:48.11#ibcon#about to read 3, iclass 29, count 0 2006.211.07:43:48.13#ibcon#read 3, iclass 29, count 0 2006.211.07:43:48.13#ibcon#about to read 4, iclass 29, count 0 2006.211.07:43:48.13#ibcon#read 4, iclass 29, count 0 2006.211.07:43:48.13#ibcon#about to read 5, iclass 29, count 0 2006.211.07:43:48.13#ibcon#read 5, iclass 29, count 0 2006.211.07:43:48.13#ibcon#about to read 6, iclass 29, count 0 2006.211.07:43:48.13#ibcon#read 6, iclass 29, count 0 2006.211.07:43:48.13#ibcon#end of sib2, iclass 29, count 0 2006.211.07:43:48.13#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:43:48.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:43:48.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:43:48.13#ibcon#*before write, iclass 29, count 0 2006.211.07:43:48.13#ibcon#enter sib2, iclass 29, count 0 2006.211.07:43:48.13#ibcon#flushed, iclass 29, count 0 2006.211.07:43:48.13#ibcon#about to write, iclass 29, count 0 2006.211.07:43:48.13#ibcon#wrote, iclass 29, count 0 2006.211.07:43:48.13#ibcon#about to read 3, iclass 29, count 0 2006.211.07:43:48.17#ibcon#read 3, iclass 29, count 0 2006.211.07:43:48.17#ibcon#about to read 4, iclass 29, count 0 2006.211.07:43:48.17#ibcon#read 4, iclass 29, count 0 2006.211.07:43:48.17#ibcon#about to read 5, iclass 29, count 0 2006.211.07:43:48.17#ibcon#read 5, iclass 29, count 0 2006.211.07:43:48.17#ibcon#about to read 6, iclass 29, count 0 2006.211.07:43:48.17#ibcon#read 6, iclass 29, count 0 2006.211.07:43:48.17#ibcon#end of sib2, iclass 29, count 0 2006.211.07:43:48.17#ibcon#*after write, iclass 29, count 0 2006.211.07:43:48.17#ibcon#*before return 0, iclass 29, count 0 2006.211.07:43:48.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:48.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:48.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:43:48.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:43:48.17$vc4f8/va=3,6 2006.211.07:43:48.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:43:48.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:43:48.17#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:48.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:48.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:48.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:48.23#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:43:48.23#ibcon#first serial, iclass 31, count 2 2006.211.07:43:48.23#ibcon#enter sib2, iclass 31, count 2 2006.211.07:43:48.23#ibcon#flushed, iclass 31, count 2 2006.211.07:43:48.23#ibcon#about to write, iclass 31, count 2 2006.211.07:43:48.23#ibcon#wrote, iclass 31, count 2 2006.211.07:43:48.23#ibcon#about to read 3, iclass 31, count 2 2006.211.07:43:48.25#ibcon#read 3, iclass 31, count 2 2006.211.07:43:48.25#ibcon#about to read 4, iclass 31, count 2 2006.211.07:43:48.25#ibcon#read 4, iclass 31, count 2 2006.211.07:43:48.25#ibcon#about to read 5, iclass 31, count 2 2006.211.07:43:48.25#ibcon#read 5, iclass 31, count 2 2006.211.07:43:48.25#ibcon#about to read 6, iclass 31, count 2 2006.211.07:43:48.25#ibcon#read 6, iclass 31, count 2 2006.211.07:43:48.25#ibcon#end of sib2, iclass 31, count 2 2006.211.07:43:48.25#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:43:48.25#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:43:48.25#ibcon#[25=AT03-06\r\n] 2006.211.07:43:48.25#ibcon#*before write, iclass 31, count 2 2006.211.07:43:48.25#ibcon#enter sib2, iclass 31, count 2 2006.211.07:43:48.25#ibcon#flushed, iclass 31, count 2 2006.211.07:43:48.25#ibcon#about to write, iclass 31, count 2 2006.211.07:43:48.25#ibcon#wrote, iclass 31, count 2 2006.211.07:43:48.25#ibcon#about to read 3, iclass 31, count 2 2006.211.07:43:48.28#ibcon#read 3, iclass 31, count 2 2006.211.07:43:48.28#ibcon#about to read 4, iclass 31, count 2 2006.211.07:43:48.28#ibcon#read 4, iclass 31, count 2 2006.211.07:43:48.28#ibcon#about to read 5, iclass 31, count 2 2006.211.07:43:48.28#ibcon#read 5, iclass 31, count 2 2006.211.07:43:48.28#ibcon#about to read 6, iclass 31, count 2 2006.211.07:43:48.28#ibcon#read 6, iclass 31, count 2 2006.211.07:43:48.28#ibcon#end of sib2, iclass 31, count 2 2006.211.07:43:48.28#ibcon#*after write, iclass 31, count 2 2006.211.07:43:48.28#ibcon#*before return 0, iclass 31, count 2 2006.211.07:43:48.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:48.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:48.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:43:48.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:48.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:48.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:48.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:48.40#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:43:48.40#ibcon#first serial, iclass 31, count 0 2006.211.07:43:48.40#ibcon#enter sib2, iclass 31, count 0 2006.211.07:43:48.40#ibcon#flushed, iclass 31, count 0 2006.211.07:43:48.40#ibcon#about to write, iclass 31, count 0 2006.211.07:43:48.40#ibcon#wrote, iclass 31, count 0 2006.211.07:43:48.40#ibcon#about to read 3, iclass 31, count 0 2006.211.07:43:48.42#ibcon#read 3, iclass 31, count 0 2006.211.07:43:48.42#ibcon#about to read 4, iclass 31, count 0 2006.211.07:43:48.42#ibcon#read 4, iclass 31, count 0 2006.211.07:43:48.42#ibcon#about to read 5, iclass 31, count 0 2006.211.07:43:48.42#ibcon#read 5, iclass 31, count 0 2006.211.07:43:48.42#ibcon#about to read 6, iclass 31, count 0 2006.211.07:43:48.42#ibcon#read 6, iclass 31, count 0 2006.211.07:43:48.42#ibcon#end of sib2, iclass 31, count 0 2006.211.07:43:48.42#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:43:48.42#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:43:48.42#ibcon#[25=USB\r\n] 2006.211.07:43:48.42#ibcon#*before write, iclass 31, count 0 2006.211.07:43:48.42#ibcon#enter sib2, iclass 31, count 0 2006.211.07:43:48.42#ibcon#flushed, iclass 31, count 0 2006.211.07:43:48.42#ibcon#about to write, iclass 31, count 0 2006.211.07:43:48.42#ibcon#wrote, iclass 31, count 0 2006.211.07:43:48.42#ibcon#about to read 3, iclass 31, count 0 2006.211.07:43:48.45#ibcon#read 3, iclass 31, count 0 2006.211.07:43:48.45#ibcon#about to read 4, iclass 31, count 0 2006.211.07:43:48.45#ibcon#read 4, iclass 31, count 0 2006.211.07:43:48.45#ibcon#about to read 5, iclass 31, count 0 2006.211.07:43:48.45#ibcon#read 5, iclass 31, count 0 2006.211.07:43:48.45#ibcon#about to read 6, iclass 31, count 0 2006.211.07:43:48.45#ibcon#read 6, iclass 31, count 0 2006.211.07:43:48.45#ibcon#end of sib2, iclass 31, count 0 2006.211.07:43:48.45#ibcon#*after write, iclass 31, count 0 2006.211.07:43:48.45#ibcon#*before return 0, iclass 31, count 0 2006.211.07:43:48.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:48.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:48.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:43:48.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:43:48.45$vc4f8/valo=4,832.99 2006.211.07:43:48.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:43:48.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:43:48.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:48.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:48.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:48.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:48.45#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:43:48.45#ibcon#first serial, iclass 33, count 0 2006.211.07:43:48.45#ibcon#enter sib2, iclass 33, count 0 2006.211.07:43:48.45#ibcon#flushed, iclass 33, count 0 2006.211.07:43:48.45#ibcon#about to write, iclass 33, count 0 2006.211.07:43:48.45#ibcon#wrote, iclass 33, count 0 2006.211.07:43:48.45#ibcon#about to read 3, iclass 33, count 0 2006.211.07:43:48.47#ibcon#read 3, iclass 33, count 0 2006.211.07:43:48.47#ibcon#about to read 4, iclass 33, count 0 2006.211.07:43:48.47#ibcon#read 4, iclass 33, count 0 2006.211.07:43:48.47#ibcon#about to read 5, iclass 33, count 0 2006.211.07:43:48.47#ibcon#read 5, iclass 33, count 0 2006.211.07:43:48.47#ibcon#about to read 6, iclass 33, count 0 2006.211.07:43:48.47#ibcon#read 6, iclass 33, count 0 2006.211.07:43:48.47#ibcon#end of sib2, iclass 33, count 0 2006.211.07:43:48.47#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:43:48.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:43:48.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:43:48.47#ibcon#*before write, iclass 33, count 0 2006.211.07:43:48.47#ibcon#enter sib2, iclass 33, count 0 2006.211.07:43:48.47#ibcon#flushed, iclass 33, count 0 2006.211.07:43:48.47#ibcon#about to write, iclass 33, count 0 2006.211.07:43:48.47#ibcon#wrote, iclass 33, count 0 2006.211.07:43:48.47#ibcon#about to read 3, iclass 33, count 0 2006.211.07:43:48.51#ibcon#read 3, iclass 33, count 0 2006.211.07:43:48.51#ibcon#about to read 4, iclass 33, count 0 2006.211.07:43:48.51#ibcon#read 4, iclass 33, count 0 2006.211.07:43:48.51#ibcon#about to read 5, iclass 33, count 0 2006.211.07:43:48.51#ibcon#read 5, iclass 33, count 0 2006.211.07:43:48.51#ibcon#about to read 6, iclass 33, count 0 2006.211.07:43:48.51#ibcon#read 6, iclass 33, count 0 2006.211.07:43:48.51#ibcon#end of sib2, iclass 33, count 0 2006.211.07:43:48.51#ibcon#*after write, iclass 33, count 0 2006.211.07:43:48.51#ibcon#*before return 0, iclass 33, count 0 2006.211.07:43:48.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:48.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:48.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:43:48.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:43:48.51$vc4f8/va=4,7 2006.211.07:43:48.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:43:48.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:43:48.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:48.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:48.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:48.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:48.57#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:43:48.57#ibcon#first serial, iclass 35, count 2 2006.211.07:43:48.57#ibcon#enter sib2, iclass 35, count 2 2006.211.07:43:48.57#ibcon#flushed, iclass 35, count 2 2006.211.07:43:48.57#ibcon#about to write, iclass 35, count 2 2006.211.07:43:48.57#ibcon#wrote, iclass 35, count 2 2006.211.07:43:48.57#ibcon#about to read 3, iclass 35, count 2 2006.211.07:43:48.59#ibcon#read 3, iclass 35, count 2 2006.211.07:43:48.59#ibcon#about to read 4, iclass 35, count 2 2006.211.07:43:48.59#ibcon#read 4, iclass 35, count 2 2006.211.07:43:48.59#ibcon#about to read 5, iclass 35, count 2 2006.211.07:43:48.59#ibcon#read 5, iclass 35, count 2 2006.211.07:43:48.59#ibcon#about to read 6, iclass 35, count 2 2006.211.07:43:48.59#ibcon#read 6, iclass 35, count 2 2006.211.07:43:48.59#ibcon#end of sib2, iclass 35, count 2 2006.211.07:43:48.59#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:43:48.59#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:43:48.59#ibcon#[25=AT04-07\r\n] 2006.211.07:43:48.59#ibcon#*before write, iclass 35, count 2 2006.211.07:43:48.59#ibcon#enter sib2, iclass 35, count 2 2006.211.07:43:48.59#ibcon#flushed, iclass 35, count 2 2006.211.07:43:48.59#ibcon#about to write, iclass 35, count 2 2006.211.07:43:48.59#ibcon#wrote, iclass 35, count 2 2006.211.07:43:48.59#ibcon#about to read 3, iclass 35, count 2 2006.211.07:43:48.62#ibcon#read 3, iclass 35, count 2 2006.211.07:43:48.62#ibcon#about to read 4, iclass 35, count 2 2006.211.07:43:48.62#ibcon#read 4, iclass 35, count 2 2006.211.07:43:48.62#ibcon#about to read 5, iclass 35, count 2 2006.211.07:43:48.62#ibcon#read 5, iclass 35, count 2 2006.211.07:43:48.62#ibcon#about to read 6, iclass 35, count 2 2006.211.07:43:48.62#ibcon#read 6, iclass 35, count 2 2006.211.07:43:48.62#ibcon#end of sib2, iclass 35, count 2 2006.211.07:43:48.62#ibcon#*after write, iclass 35, count 2 2006.211.07:43:48.62#ibcon#*before return 0, iclass 35, count 2 2006.211.07:43:48.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:48.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:48.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:43:48.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:48.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:48.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:48.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:48.74#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:43:48.74#ibcon#first serial, iclass 35, count 0 2006.211.07:43:48.74#ibcon#enter sib2, iclass 35, count 0 2006.211.07:43:48.74#ibcon#flushed, iclass 35, count 0 2006.211.07:43:48.74#ibcon#about to write, iclass 35, count 0 2006.211.07:43:48.74#ibcon#wrote, iclass 35, count 0 2006.211.07:43:48.74#ibcon#about to read 3, iclass 35, count 0 2006.211.07:43:48.76#ibcon#read 3, iclass 35, count 0 2006.211.07:43:48.76#ibcon#about to read 4, iclass 35, count 0 2006.211.07:43:48.76#ibcon#read 4, iclass 35, count 0 2006.211.07:43:48.76#ibcon#about to read 5, iclass 35, count 0 2006.211.07:43:48.76#ibcon#read 5, iclass 35, count 0 2006.211.07:43:48.76#ibcon#about to read 6, iclass 35, count 0 2006.211.07:43:48.76#ibcon#read 6, iclass 35, count 0 2006.211.07:43:48.76#ibcon#end of sib2, iclass 35, count 0 2006.211.07:43:48.76#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:43:48.76#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:43:48.76#ibcon#[25=USB\r\n] 2006.211.07:43:48.76#ibcon#*before write, iclass 35, count 0 2006.211.07:43:48.76#ibcon#enter sib2, iclass 35, count 0 2006.211.07:43:48.76#ibcon#flushed, iclass 35, count 0 2006.211.07:43:48.76#ibcon#about to write, iclass 35, count 0 2006.211.07:43:48.76#ibcon#wrote, iclass 35, count 0 2006.211.07:43:48.76#ibcon#about to read 3, iclass 35, count 0 2006.211.07:43:48.79#ibcon#read 3, iclass 35, count 0 2006.211.07:43:48.79#ibcon#about to read 4, iclass 35, count 0 2006.211.07:43:48.79#ibcon#read 4, iclass 35, count 0 2006.211.07:43:48.79#ibcon#about to read 5, iclass 35, count 0 2006.211.07:43:48.79#ibcon#read 5, iclass 35, count 0 2006.211.07:43:48.79#ibcon#about to read 6, iclass 35, count 0 2006.211.07:43:48.79#ibcon#read 6, iclass 35, count 0 2006.211.07:43:48.79#ibcon#end of sib2, iclass 35, count 0 2006.211.07:43:48.79#ibcon#*after write, iclass 35, count 0 2006.211.07:43:48.79#ibcon#*before return 0, iclass 35, count 0 2006.211.07:43:48.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:48.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:48.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:43:48.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:43:48.79$vc4f8/valo=5,652.99 2006.211.07:43:48.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:43:48.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:43:48.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:48.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:48.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:48.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:48.79#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:43:48.79#ibcon#first serial, iclass 37, count 0 2006.211.07:43:48.79#ibcon#enter sib2, iclass 37, count 0 2006.211.07:43:48.79#ibcon#flushed, iclass 37, count 0 2006.211.07:43:48.79#ibcon#about to write, iclass 37, count 0 2006.211.07:43:48.79#ibcon#wrote, iclass 37, count 0 2006.211.07:43:48.79#ibcon#about to read 3, iclass 37, count 0 2006.211.07:43:48.81#ibcon#read 3, iclass 37, count 0 2006.211.07:43:48.81#ibcon#about to read 4, iclass 37, count 0 2006.211.07:43:48.81#ibcon#read 4, iclass 37, count 0 2006.211.07:43:48.81#ibcon#about to read 5, iclass 37, count 0 2006.211.07:43:48.81#ibcon#read 5, iclass 37, count 0 2006.211.07:43:48.81#ibcon#about to read 6, iclass 37, count 0 2006.211.07:43:48.81#ibcon#read 6, iclass 37, count 0 2006.211.07:43:48.81#ibcon#end of sib2, iclass 37, count 0 2006.211.07:43:48.81#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:43:48.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:43:48.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:43:48.81#ibcon#*before write, iclass 37, count 0 2006.211.07:43:48.81#ibcon#enter sib2, iclass 37, count 0 2006.211.07:43:48.81#ibcon#flushed, iclass 37, count 0 2006.211.07:43:48.81#ibcon#about to write, iclass 37, count 0 2006.211.07:43:48.81#ibcon#wrote, iclass 37, count 0 2006.211.07:43:48.81#ibcon#about to read 3, iclass 37, count 0 2006.211.07:43:48.85#ibcon#read 3, iclass 37, count 0 2006.211.07:43:48.85#ibcon#about to read 4, iclass 37, count 0 2006.211.07:43:48.85#ibcon#read 4, iclass 37, count 0 2006.211.07:43:48.85#ibcon#about to read 5, iclass 37, count 0 2006.211.07:43:48.85#ibcon#read 5, iclass 37, count 0 2006.211.07:43:48.85#ibcon#about to read 6, iclass 37, count 0 2006.211.07:43:48.85#ibcon#read 6, iclass 37, count 0 2006.211.07:43:48.85#ibcon#end of sib2, iclass 37, count 0 2006.211.07:43:48.85#ibcon#*after write, iclass 37, count 0 2006.211.07:43:48.85#ibcon#*before return 0, iclass 37, count 0 2006.211.07:43:48.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:48.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:48.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:43:48.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:43:48.85$vc4f8/va=5,7 2006.211.07:43:48.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:43:48.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:43:48.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:48.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:48.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:48.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:48.91#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:43:48.91#ibcon#first serial, iclass 39, count 2 2006.211.07:43:48.91#ibcon#enter sib2, iclass 39, count 2 2006.211.07:43:48.91#ibcon#flushed, iclass 39, count 2 2006.211.07:43:48.91#ibcon#about to write, iclass 39, count 2 2006.211.07:43:48.91#ibcon#wrote, iclass 39, count 2 2006.211.07:43:48.91#ibcon#about to read 3, iclass 39, count 2 2006.211.07:43:48.93#ibcon#read 3, iclass 39, count 2 2006.211.07:43:48.93#ibcon#about to read 4, iclass 39, count 2 2006.211.07:43:48.93#ibcon#read 4, iclass 39, count 2 2006.211.07:43:48.93#ibcon#about to read 5, iclass 39, count 2 2006.211.07:43:48.93#ibcon#read 5, iclass 39, count 2 2006.211.07:43:48.93#ibcon#about to read 6, iclass 39, count 2 2006.211.07:43:48.93#ibcon#read 6, iclass 39, count 2 2006.211.07:43:48.93#ibcon#end of sib2, iclass 39, count 2 2006.211.07:43:48.93#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:43:48.93#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:43:48.93#ibcon#[25=AT05-07\r\n] 2006.211.07:43:48.93#ibcon#*before write, iclass 39, count 2 2006.211.07:43:48.93#ibcon#enter sib2, iclass 39, count 2 2006.211.07:43:48.93#ibcon#flushed, iclass 39, count 2 2006.211.07:43:48.93#ibcon#about to write, iclass 39, count 2 2006.211.07:43:48.93#ibcon#wrote, iclass 39, count 2 2006.211.07:43:48.93#ibcon#about to read 3, iclass 39, count 2 2006.211.07:43:48.96#ibcon#read 3, iclass 39, count 2 2006.211.07:43:48.96#ibcon#about to read 4, iclass 39, count 2 2006.211.07:43:48.96#ibcon#read 4, iclass 39, count 2 2006.211.07:43:48.96#ibcon#about to read 5, iclass 39, count 2 2006.211.07:43:48.96#ibcon#read 5, iclass 39, count 2 2006.211.07:43:48.96#ibcon#about to read 6, iclass 39, count 2 2006.211.07:43:48.96#ibcon#read 6, iclass 39, count 2 2006.211.07:43:48.96#ibcon#end of sib2, iclass 39, count 2 2006.211.07:43:48.96#ibcon#*after write, iclass 39, count 2 2006.211.07:43:48.96#ibcon#*before return 0, iclass 39, count 2 2006.211.07:43:48.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:48.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:48.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:43:48.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:48.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:49.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:49.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:49.08#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:43:49.08#ibcon#first serial, iclass 39, count 0 2006.211.07:43:49.08#ibcon#enter sib2, iclass 39, count 0 2006.211.07:43:49.08#ibcon#flushed, iclass 39, count 0 2006.211.07:43:49.08#ibcon#about to write, iclass 39, count 0 2006.211.07:43:49.08#ibcon#wrote, iclass 39, count 0 2006.211.07:43:49.08#ibcon#about to read 3, iclass 39, count 0 2006.211.07:43:49.10#ibcon#read 3, iclass 39, count 0 2006.211.07:43:49.10#ibcon#about to read 4, iclass 39, count 0 2006.211.07:43:49.10#ibcon#read 4, iclass 39, count 0 2006.211.07:43:49.10#ibcon#about to read 5, iclass 39, count 0 2006.211.07:43:49.10#ibcon#read 5, iclass 39, count 0 2006.211.07:43:49.10#ibcon#about to read 6, iclass 39, count 0 2006.211.07:43:49.10#ibcon#read 6, iclass 39, count 0 2006.211.07:43:49.10#ibcon#end of sib2, iclass 39, count 0 2006.211.07:43:49.10#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:43:49.10#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:43:49.10#ibcon#[25=USB\r\n] 2006.211.07:43:49.10#ibcon#*before write, iclass 39, count 0 2006.211.07:43:49.10#ibcon#enter sib2, iclass 39, count 0 2006.211.07:43:49.10#ibcon#flushed, iclass 39, count 0 2006.211.07:43:49.10#ibcon#about to write, iclass 39, count 0 2006.211.07:43:49.10#ibcon#wrote, iclass 39, count 0 2006.211.07:43:49.10#ibcon#about to read 3, iclass 39, count 0 2006.211.07:43:49.13#abcon#<5=/04 5.010.4 24.94 761010.1\r\n> 2006.211.07:43:49.13#ibcon#read 3, iclass 39, count 0 2006.211.07:43:49.13#ibcon#about to read 4, iclass 39, count 0 2006.211.07:43:49.13#ibcon#read 4, iclass 39, count 0 2006.211.07:43:49.13#ibcon#about to read 5, iclass 39, count 0 2006.211.07:43:49.13#ibcon#read 5, iclass 39, count 0 2006.211.07:43:49.13#ibcon#about to read 6, iclass 39, count 0 2006.211.07:43:49.13#ibcon#read 6, iclass 39, count 0 2006.211.07:43:49.13#ibcon#end of sib2, iclass 39, count 0 2006.211.07:43:49.13#ibcon#*after write, iclass 39, count 0 2006.211.07:43:49.13#ibcon#*before return 0, iclass 39, count 0 2006.211.07:43:49.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:49.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:49.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:43:49.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:43:49.13$vc4f8/valo=6,772.99 2006.211.07:43:49.13#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:43:49.13#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:43:49.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:49.13#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:43:49.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:43:49.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:43:49.13#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:43:49.13#ibcon#first serial, iclass 6, count 0 2006.211.07:43:49.13#ibcon#enter sib2, iclass 6, count 0 2006.211.07:43:49.13#ibcon#flushed, iclass 6, count 0 2006.211.07:43:49.13#ibcon#about to write, iclass 6, count 0 2006.211.07:43:49.13#ibcon#wrote, iclass 6, count 0 2006.211.07:43:49.13#ibcon#about to read 3, iclass 6, count 0 2006.211.07:43:49.15#abcon#{5=INTERFACE CLEAR} 2006.211.07:43:49.15#ibcon#read 3, iclass 6, count 0 2006.211.07:43:49.15#ibcon#about to read 4, iclass 6, count 0 2006.211.07:43:49.15#ibcon#read 4, iclass 6, count 0 2006.211.07:43:49.15#ibcon#about to read 5, iclass 6, count 0 2006.211.07:43:49.15#ibcon#read 5, iclass 6, count 0 2006.211.07:43:49.15#ibcon#about to read 6, iclass 6, count 0 2006.211.07:43:49.15#ibcon#read 6, iclass 6, count 0 2006.211.07:43:49.15#ibcon#end of sib2, iclass 6, count 0 2006.211.07:43:49.15#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:43:49.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:43:49.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:43:49.15#ibcon#*before write, iclass 6, count 0 2006.211.07:43:49.15#ibcon#enter sib2, iclass 6, count 0 2006.211.07:43:49.15#ibcon#flushed, iclass 6, count 0 2006.211.07:43:49.15#ibcon#about to write, iclass 6, count 0 2006.211.07:43:49.15#ibcon#wrote, iclass 6, count 0 2006.211.07:43:49.15#ibcon#about to read 3, iclass 6, count 0 2006.211.07:43:49.19#ibcon#read 3, iclass 6, count 0 2006.211.07:43:49.19#ibcon#about to read 4, iclass 6, count 0 2006.211.07:43:49.19#ibcon#read 4, iclass 6, count 0 2006.211.07:43:49.19#ibcon#about to read 5, iclass 6, count 0 2006.211.07:43:49.19#ibcon#read 5, iclass 6, count 0 2006.211.07:43:49.19#ibcon#about to read 6, iclass 6, count 0 2006.211.07:43:49.19#ibcon#read 6, iclass 6, count 0 2006.211.07:43:49.19#ibcon#end of sib2, iclass 6, count 0 2006.211.07:43:49.19#ibcon#*after write, iclass 6, count 0 2006.211.07:43:49.19#ibcon#*before return 0, iclass 6, count 0 2006.211.07:43:49.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:43:49.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:43:49.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:43:49.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:43:49.19$vc4f8/va=6,6 2006.211.07:43:49.19#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:43:49.19#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:43:49.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:49.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:43:49.21#abcon#[5=S1D000X0/0*\r\n] 2006.211.07:43:49.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:43:49.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:43:49.25#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:43:49.25#ibcon#first serial, iclass 10, count 2 2006.211.07:43:49.25#ibcon#enter sib2, iclass 10, count 2 2006.211.07:43:49.25#ibcon#flushed, iclass 10, count 2 2006.211.07:43:49.25#ibcon#about to write, iclass 10, count 2 2006.211.07:43:49.25#ibcon#wrote, iclass 10, count 2 2006.211.07:43:49.25#ibcon#about to read 3, iclass 10, count 2 2006.211.07:43:49.27#ibcon#read 3, iclass 10, count 2 2006.211.07:43:49.27#ibcon#about to read 4, iclass 10, count 2 2006.211.07:43:49.27#ibcon#read 4, iclass 10, count 2 2006.211.07:43:49.27#ibcon#about to read 5, iclass 10, count 2 2006.211.07:43:49.27#ibcon#read 5, iclass 10, count 2 2006.211.07:43:49.27#ibcon#about to read 6, iclass 10, count 2 2006.211.07:43:49.27#ibcon#read 6, iclass 10, count 2 2006.211.07:43:49.27#ibcon#end of sib2, iclass 10, count 2 2006.211.07:43:49.27#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:43:49.27#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:43:49.27#ibcon#[25=AT06-06\r\n] 2006.211.07:43:49.27#ibcon#*before write, iclass 10, count 2 2006.211.07:43:49.27#ibcon#enter sib2, iclass 10, count 2 2006.211.07:43:49.27#ibcon#flushed, iclass 10, count 2 2006.211.07:43:49.27#ibcon#about to write, iclass 10, count 2 2006.211.07:43:49.27#ibcon#wrote, iclass 10, count 2 2006.211.07:43:49.27#ibcon#about to read 3, iclass 10, count 2 2006.211.07:43:49.30#ibcon#read 3, iclass 10, count 2 2006.211.07:43:49.30#ibcon#about to read 4, iclass 10, count 2 2006.211.07:43:49.30#ibcon#read 4, iclass 10, count 2 2006.211.07:43:49.30#ibcon#about to read 5, iclass 10, count 2 2006.211.07:43:49.30#ibcon#read 5, iclass 10, count 2 2006.211.07:43:49.30#ibcon#about to read 6, iclass 10, count 2 2006.211.07:43:49.30#ibcon#read 6, iclass 10, count 2 2006.211.07:43:49.30#ibcon#end of sib2, iclass 10, count 2 2006.211.07:43:49.30#ibcon#*after write, iclass 10, count 2 2006.211.07:43:49.30#ibcon#*before return 0, iclass 10, count 2 2006.211.07:43:49.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:43:49.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:43:49.30#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:43:49.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:49.30#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:43:49.42#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:43:49.42#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:43:49.42#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:43:49.42#ibcon#first serial, iclass 10, count 0 2006.211.07:43:49.42#ibcon#enter sib2, iclass 10, count 0 2006.211.07:43:49.42#ibcon#flushed, iclass 10, count 0 2006.211.07:43:49.42#ibcon#about to write, iclass 10, count 0 2006.211.07:43:49.42#ibcon#wrote, iclass 10, count 0 2006.211.07:43:49.42#ibcon#about to read 3, iclass 10, count 0 2006.211.07:43:49.44#ibcon#read 3, iclass 10, count 0 2006.211.07:43:49.44#ibcon#about to read 4, iclass 10, count 0 2006.211.07:43:49.44#ibcon#read 4, iclass 10, count 0 2006.211.07:43:49.44#ibcon#about to read 5, iclass 10, count 0 2006.211.07:43:49.44#ibcon#read 5, iclass 10, count 0 2006.211.07:43:49.44#ibcon#about to read 6, iclass 10, count 0 2006.211.07:43:49.44#ibcon#read 6, iclass 10, count 0 2006.211.07:43:49.44#ibcon#end of sib2, iclass 10, count 0 2006.211.07:43:49.44#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:43:49.44#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:43:49.44#ibcon#[25=USB\r\n] 2006.211.07:43:49.44#ibcon#*before write, iclass 10, count 0 2006.211.07:43:49.44#ibcon#enter sib2, iclass 10, count 0 2006.211.07:43:49.44#ibcon#flushed, iclass 10, count 0 2006.211.07:43:49.44#ibcon#about to write, iclass 10, count 0 2006.211.07:43:49.44#ibcon#wrote, iclass 10, count 0 2006.211.07:43:49.44#ibcon#about to read 3, iclass 10, count 0 2006.211.07:43:49.47#ibcon#read 3, iclass 10, count 0 2006.211.07:43:49.47#ibcon#about to read 4, iclass 10, count 0 2006.211.07:43:49.47#ibcon#read 4, iclass 10, count 0 2006.211.07:43:49.47#ibcon#about to read 5, iclass 10, count 0 2006.211.07:43:49.47#ibcon#read 5, iclass 10, count 0 2006.211.07:43:49.47#ibcon#about to read 6, iclass 10, count 0 2006.211.07:43:49.47#ibcon#read 6, iclass 10, count 0 2006.211.07:43:49.47#ibcon#end of sib2, iclass 10, count 0 2006.211.07:43:49.47#ibcon#*after write, iclass 10, count 0 2006.211.07:43:49.47#ibcon#*before return 0, iclass 10, count 0 2006.211.07:43:49.47#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:43:49.47#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:43:49.47#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:43:49.47#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:43:49.47$vc4f8/valo=7,832.99 2006.211.07:43:49.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:43:49.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:43:49.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:49.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:43:49.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:43:49.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:43:49.47#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:43:49.47#ibcon#first serial, iclass 13, count 0 2006.211.07:43:49.47#ibcon#enter sib2, iclass 13, count 0 2006.211.07:43:49.47#ibcon#flushed, iclass 13, count 0 2006.211.07:43:49.47#ibcon#about to write, iclass 13, count 0 2006.211.07:43:49.47#ibcon#wrote, iclass 13, count 0 2006.211.07:43:49.47#ibcon#about to read 3, iclass 13, count 0 2006.211.07:43:49.49#ibcon#read 3, iclass 13, count 0 2006.211.07:43:49.49#ibcon#about to read 4, iclass 13, count 0 2006.211.07:43:49.49#ibcon#read 4, iclass 13, count 0 2006.211.07:43:49.49#ibcon#about to read 5, iclass 13, count 0 2006.211.07:43:49.49#ibcon#read 5, iclass 13, count 0 2006.211.07:43:49.49#ibcon#about to read 6, iclass 13, count 0 2006.211.07:43:49.49#ibcon#read 6, iclass 13, count 0 2006.211.07:43:49.49#ibcon#end of sib2, iclass 13, count 0 2006.211.07:43:49.49#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:43:49.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:43:49.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:43:49.49#ibcon#*before write, iclass 13, count 0 2006.211.07:43:49.49#ibcon#enter sib2, iclass 13, count 0 2006.211.07:43:49.49#ibcon#flushed, iclass 13, count 0 2006.211.07:43:49.49#ibcon#about to write, iclass 13, count 0 2006.211.07:43:49.49#ibcon#wrote, iclass 13, count 0 2006.211.07:43:49.49#ibcon#about to read 3, iclass 13, count 0 2006.211.07:43:49.53#ibcon#read 3, iclass 13, count 0 2006.211.07:43:49.53#ibcon#about to read 4, iclass 13, count 0 2006.211.07:43:49.53#ibcon#read 4, iclass 13, count 0 2006.211.07:43:49.53#ibcon#about to read 5, iclass 13, count 0 2006.211.07:43:49.53#ibcon#read 5, iclass 13, count 0 2006.211.07:43:49.53#ibcon#about to read 6, iclass 13, count 0 2006.211.07:43:49.53#ibcon#read 6, iclass 13, count 0 2006.211.07:43:49.53#ibcon#end of sib2, iclass 13, count 0 2006.211.07:43:49.53#ibcon#*after write, iclass 13, count 0 2006.211.07:43:49.53#ibcon#*before return 0, iclass 13, count 0 2006.211.07:43:49.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:43:49.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:43:49.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:43:49.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:43:49.53$vc4f8/va=7,6 2006.211.07:43:49.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.07:43:49.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.07:43:49.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:49.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:43:49.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:43:49.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:43:49.59#ibcon#enter wrdev, iclass 15, count 2 2006.211.07:43:49.59#ibcon#first serial, iclass 15, count 2 2006.211.07:43:49.59#ibcon#enter sib2, iclass 15, count 2 2006.211.07:43:49.59#ibcon#flushed, iclass 15, count 2 2006.211.07:43:49.59#ibcon#about to write, iclass 15, count 2 2006.211.07:43:49.59#ibcon#wrote, iclass 15, count 2 2006.211.07:43:49.59#ibcon#about to read 3, iclass 15, count 2 2006.211.07:43:49.61#ibcon#read 3, iclass 15, count 2 2006.211.07:43:49.61#ibcon#about to read 4, iclass 15, count 2 2006.211.07:43:49.61#ibcon#read 4, iclass 15, count 2 2006.211.07:43:49.61#ibcon#about to read 5, iclass 15, count 2 2006.211.07:43:49.61#ibcon#read 5, iclass 15, count 2 2006.211.07:43:49.61#ibcon#about to read 6, iclass 15, count 2 2006.211.07:43:49.61#ibcon#read 6, iclass 15, count 2 2006.211.07:43:49.61#ibcon#end of sib2, iclass 15, count 2 2006.211.07:43:49.61#ibcon#*mode == 0, iclass 15, count 2 2006.211.07:43:49.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.07:43:49.61#ibcon#[25=AT07-06\r\n] 2006.211.07:43:49.61#ibcon#*before write, iclass 15, count 2 2006.211.07:43:49.61#ibcon#enter sib2, iclass 15, count 2 2006.211.07:43:49.61#ibcon#flushed, iclass 15, count 2 2006.211.07:43:49.61#ibcon#about to write, iclass 15, count 2 2006.211.07:43:49.61#ibcon#wrote, iclass 15, count 2 2006.211.07:43:49.61#ibcon#about to read 3, iclass 15, count 2 2006.211.07:43:49.64#ibcon#read 3, iclass 15, count 2 2006.211.07:43:49.64#ibcon#about to read 4, iclass 15, count 2 2006.211.07:43:49.64#ibcon#read 4, iclass 15, count 2 2006.211.07:43:49.64#ibcon#about to read 5, iclass 15, count 2 2006.211.07:43:49.64#ibcon#read 5, iclass 15, count 2 2006.211.07:43:49.64#ibcon#about to read 6, iclass 15, count 2 2006.211.07:43:49.64#ibcon#read 6, iclass 15, count 2 2006.211.07:43:49.64#ibcon#end of sib2, iclass 15, count 2 2006.211.07:43:49.64#ibcon#*after write, iclass 15, count 2 2006.211.07:43:49.64#ibcon#*before return 0, iclass 15, count 2 2006.211.07:43:49.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:43:49.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:43:49.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.07:43:49.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:49.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:43:49.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:43:49.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:43:49.76#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:43:49.76#ibcon#first serial, iclass 15, count 0 2006.211.07:43:49.76#ibcon#enter sib2, iclass 15, count 0 2006.211.07:43:49.76#ibcon#flushed, iclass 15, count 0 2006.211.07:43:49.76#ibcon#about to write, iclass 15, count 0 2006.211.07:43:49.76#ibcon#wrote, iclass 15, count 0 2006.211.07:43:49.76#ibcon#about to read 3, iclass 15, count 0 2006.211.07:43:49.78#ibcon#read 3, iclass 15, count 0 2006.211.07:43:49.78#ibcon#about to read 4, iclass 15, count 0 2006.211.07:43:49.78#ibcon#read 4, iclass 15, count 0 2006.211.07:43:49.78#ibcon#about to read 5, iclass 15, count 0 2006.211.07:43:49.78#ibcon#read 5, iclass 15, count 0 2006.211.07:43:49.78#ibcon#about to read 6, iclass 15, count 0 2006.211.07:43:49.78#ibcon#read 6, iclass 15, count 0 2006.211.07:43:49.78#ibcon#end of sib2, iclass 15, count 0 2006.211.07:43:49.78#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:43:49.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:43:49.78#ibcon#[25=USB\r\n] 2006.211.07:43:49.78#ibcon#*before write, iclass 15, count 0 2006.211.07:43:49.78#ibcon#enter sib2, iclass 15, count 0 2006.211.07:43:49.78#ibcon#flushed, iclass 15, count 0 2006.211.07:43:49.78#ibcon#about to write, iclass 15, count 0 2006.211.07:43:49.78#ibcon#wrote, iclass 15, count 0 2006.211.07:43:49.78#ibcon#about to read 3, iclass 15, count 0 2006.211.07:43:49.81#ibcon#read 3, iclass 15, count 0 2006.211.07:43:49.81#ibcon#about to read 4, iclass 15, count 0 2006.211.07:43:49.81#ibcon#read 4, iclass 15, count 0 2006.211.07:43:49.81#ibcon#about to read 5, iclass 15, count 0 2006.211.07:43:49.81#ibcon#read 5, iclass 15, count 0 2006.211.07:43:49.81#ibcon#about to read 6, iclass 15, count 0 2006.211.07:43:49.81#ibcon#read 6, iclass 15, count 0 2006.211.07:43:49.81#ibcon#end of sib2, iclass 15, count 0 2006.211.07:43:49.81#ibcon#*after write, iclass 15, count 0 2006.211.07:43:49.81#ibcon#*before return 0, iclass 15, count 0 2006.211.07:43:49.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:43:49.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:43:49.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:43:49.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:43:49.81$vc4f8/valo=8,852.99 2006.211.07:43:49.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.07:43:49.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.07:43:49.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:49.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:43:49.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:43:49.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:43:49.81#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:43:49.81#ibcon#first serial, iclass 17, count 0 2006.211.07:43:49.81#ibcon#enter sib2, iclass 17, count 0 2006.211.07:43:49.81#ibcon#flushed, iclass 17, count 0 2006.211.07:43:49.81#ibcon#about to write, iclass 17, count 0 2006.211.07:43:49.81#ibcon#wrote, iclass 17, count 0 2006.211.07:43:49.81#ibcon#about to read 3, iclass 17, count 0 2006.211.07:43:49.83#ibcon#read 3, iclass 17, count 0 2006.211.07:43:49.83#ibcon#about to read 4, iclass 17, count 0 2006.211.07:43:49.83#ibcon#read 4, iclass 17, count 0 2006.211.07:43:49.83#ibcon#about to read 5, iclass 17, count 0 2006.211.07:43:49.83#ibcon#read 5, iclass 17, count 0 2006.211.07:43:49.83#ibcon#about to read 6, iclass 17, count 0 2006.211.07:43:49.83#ibcon#read 6, iclass 17, count 0 2006.211.07:43:49.83#ibcon#end of sib2, iclass 17, count 0 2006.211.07:43:49.83#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:43:49.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:43:49.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:43:49.83#ibcon#*before write, iclass 17, count 0 2006.211.07:43:49.83#ibcon#enter sib2, iclass 17, count 0 2006.211.07:43:49.83#ibcon#flushed, iclass 17, count 0 2006.211.07:43:49.83#ibcon#about to write, iclass 17, count 0 2006.211.07:43:49.83#ibcon#wrote, iclass 17, count 0 2006.211.07:43:49.83#ibcon#about to read 3, iclass 17, count 0 2006.211.07:43:49.87#ibcon#read 3, iclass 17, count 0 2006.211.07:43:49.87#ibcon#about to read 4, iclass 17, count 0 2006.211.07:43:49.87#ibcon#read 4, iclass 17, count 0 2006.211.07:43:49.87#ibcon#about to read 5, iclass 17, count 0 2006.211.07:43:49.87#ibcon#read 5, iclass 17, count 0 2006.211.07:43:49.87#ibcon#about to read 6, iclass 17, count 0 2006.211.07:43:49.87#ibcon#read 6, iclass 17, count 0 2006.211.07:43:49.87#ibcon#end of sib2, iclass 17, count 0 2006.211.07:43:49.87#ibcon#*after write, iclass 17, count 0 2006.211.07:43:49.87#ibcon#*before return 0, iclass 17, count 0 2006.211.07:43:49.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:43:49.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:43:49.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:43:49.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:43:49.87$vc4f8/va=8,7 2006.211.07:43:49.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.07:43:49.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.07:43:49.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:49.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:43:49.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:43:49.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:43:49.93#ibcon#enter wrdev, iclass 19, count 2 2006.211.07:43:49.93#ibcon#first serial, iclass 19, count 2 2006.211.07:43:49.93#ibcon#enter sib2, iclass 19, count 2 2006.211.07:43:49.93#ibcon#flushed, iclass 19, count 2 2006.211.07:43:49.93#ibcon#about to write, iclass 19, count 2 2006.211.07:43:49.93#ibcon#wrote, iclass 19, count 2 2006.211.07:43:49.93#ibcon#about to read 3, iclass 19, count 2 2006.211.07:43:49.95#ibcon#read 3, iclass 19, count 2 2006.211.07:43:49.95#ibcon#about to read 4, iclass 19, count 2 2006.211.07:43:49.95#ibcon#read 4, iclass 19, count 2 2006.211.07:43:49.95#ibcon#about to read 5, iclass 19, count 2 2006.211.07:43:49.95#ibcon#read 5, iclass 19, count 2 2006.211.07:43:49.95#ibcon#about to read 6, iclass 19, count 2 2006.211.07:43:49.95#ibcon#read 6, iclass 19, count 2 2006.211.07:43:49.95#ibcon#end of sib2, iclass 19, count 2 2006.211.07:43:49.95#ibcon#*mode == 0, iclass 19, count 2 2006.211.07:43:49.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.07:43:49.95#ibcon#[25=AT08-07\r\n] 2006.211.07:43:49.95#ibcon#*before write, iclass 19, count 2 2006.211.07:43:49.95#ibcon#enter sib2, iclass 19, count 2 2006.211.07:43:49.95#ibcon#flushed, iclass 19, count 2 2006.211.07:43:49.95#ibcon#about to write, iclass 19, count 2 2006.211.07:43:49.95#ibcon#wrote, iclass 19, count 2 2006.211.07:43:49.95#ibcon#about to read 3, iclass 19, count 2 2006.211.07:43:49.98#ibcon#read 3, iclass 19, count 2 2006.211.07:43:49.98#ibcon#about to read 4, iclass 19, count 2 2006.211.07:43:49.98#ibcon#read 4, iclass 19, count 2 2006.211.07:43:49.98#ibcon#about to read 5, iclass 19, count 2 2006.211.07:43:49.98#ibcon#read 5, iclass 19, count 2 2006.211.07:43:49.98#ibcon#about to read 6, iclass 19, count 2 2006.211.07:43:49.98#ibcon#read 6, iclass 19, count 2 2006.211.07:43:49.98#ibcon#end of sib2, iclass 19, count 2 2006.211.07:43:49.98#ibcon#*after write, iclass 19, count 2 2006.211.07:43:49.98#ibcon#*before return 0, iclass 19, count 2 2006.211.07:43:49.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:43:49.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:43:49.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.07:43:49.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:49.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:43:50.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:43:50.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:43:50.10#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:43:50.10#ibcon#first serial, iclass 19, count 0 2006.211.07:43:50.10#ibcon#enter sib2, iclass 19, count 0 2006.211.07:43:50.10#ibcon#flushed, iclass 19, count 0 2006.211.07:43:50.10#ibcon#about to write, iclass 19, count 0 2006.211.07:43:50.10#ibcon#wrote, iclass 19, count 0 2006.211.07:43:50.10#ibcon#about to read 3, iclass 19, count 0 2006.211.07:43:50.12#ibcon#read 3, iclass 19, count 0 2006.211.07:43:50.12#ibcon#about to read 4, iclass 19, count 0 2006.211.07:43:50.12#ibcon#read 4, iclass 19, count 0 2006.211.07:43:50.12#ibcon#about to read 5, iclass 19, count 0 2006.211.07:43:50.12#ibcon#read 5, iclass 19, count 0 2006.211.07:43:50.12#ibcon#about to read 6, iclass 19, count 0 2006.211.07:43:50.12#ibcon#read 6, iclass 19, count 0 2006.211.07:43:50.12#ibcon#end of sib2, iclass 19, count 0 2006.211.07:43:50.12#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:43:50.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:43:50.12#ibcon#[25=USB\r\n] 2006.211.07:43:50.12#ibcon#*before write, iclass 19, count 0 2006.211.07:43:50.12#ibcon#enter sib2, iclass 19, count 0 2006.211.07:43:50.12#ibcon#flushed, iclass 19, count 0 2006.211.07:43:50.12#ibcon#about to write, iclass 19, count 0 2006.211.07:43:50.12#ibcon#wrote, iclass 19, count 0 2006.211.07:43:50.12#ibcon#about to read 3, iclass 19, count 0 2006.211.07:43:50.15#ibcon#read 3, iclass 19, count 0 2006.211.07:43:50.15#ibcon#about to read 4, iclass 19, count 0 2006.211.07:43:50.15#ibcon#read 4, iclass 19, count 0 2006.211.07:43:50.15#ibcon#about to read 5, iclass 19, count 0 2006.211.07:43:50.15#ibcon#read 5, iclass 19, count 0 2006.211.07:43:50.15#ibcon#about to read 6, iclass 19, count 0 2006.211.07:43:50.15#ibcon#read 6, iclass 19, count 0 2006.211.07:43:50.15#ibcon#end of sib2, iclass 19, count 0 2006.211.07:43:50.15#ibcon#*after write, iclass 19, count 0 2006.211.07:43:50.15#ibcon#*before return 0, iclass 19, count 0 2006.211.07:43:50.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:43:50.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:43:50.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:43:50.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:43:50.15$vc4f8/vblo=1,632.99 2006.211.07:43:50.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.07:43:50.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.07:43:50.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:50.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:50.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:50.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:50.15#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:43:50.15#ibcon#first serial, iclass 21, count 0 2006.211.07:43:50.15#ibcon#enter sib2, iclass 21, count 0 2006.211.07:43:50.15#ibcon#flushed, iclass 21, count 0 2006.211.07:43:50.15#ibcon#about to write, iclass 21, count 0 2006.211.07:43:50.15#ibcon#wrote, iclass 21, count 0 2006.211.07:43:50.15#ibcon#about to read 3, iclass 21, count 0 2006.211.07:43:50.17#ibcon#read 3, iclass 21, count 0 2006.211.07:43:50.17#ibcon#about to read 4, iclass 21, count 0 2006.211.07:43:50.17#ibcon#read 4, iclass 21, count 0 2006.211.07:43:50.17#ibcon#about to read 5, iclass 21, count 0 2006.211.07:43:50.17#ibcon#read 5, iclass 21, count 0 2006.211.07:43:50.17#ibcon#about to read 6, iclass 21, count 0 2006.211.07:43:50.17#ibcon#read 6, iclass 21, count 0 2006.211.07:43:50.17#ibcon#end of sib2, iclass 21, count 0 2006.211.07:43:50.17#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:43:50.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:43:50.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:43:50.17#ibcon#*before write, iclass 21, count 0 2006.211.07:43:50.17#ibcon#enter sib2, iclass 21, count 0 2006.211.07:43:50.17#ibcon#flushed, iclass 21, count 0 2006.211.07:43:50.17#ibcon#about to write, iclass 21, count 0 2006.211.07:43:50.17#ibcon#wrote, iclass 21, count 0 2006.211.07:43:50.17#ibcon#about to read 3, iclass 21, count 0 2006.211.07:43:50.21#ibcon#read 3, iclass 21, count 0 2006.211.07:43:50.21#ibcon#about to read 4, iclass 21, count 0 2006.211.07:43:50.21#ibcon#read 4, iclass 21, count 0 2006.211.07:43:50.21#ibcon#about to read 5, iclass 21, count 0 2006.211.07:43:50.21#ibcon#read 5, iclass 21, count 0 2006.211.07:43:50.21#ibcon#about to read 6, iclass 21, count 0 2006.211.07:43:50.21#ibcon#read 6, iclass 21, count 0 2006.211.07:43:50.21#ibcon#end of sib2, iclass 21, count 0 2006.211.07:43:50.21#ibcon#*after write, iclass 21, count 0 2006.211.07:43:50.21#ibcon#*before return 0, iclass 21, count 0 2006.211.07:43:50.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:50.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:43:50.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:43:50.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:43:50.21$vc4f8/vb=1,4 2006.211.07:43:50.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.07:43:50.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.07:43:50.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:50.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:50.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:50.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:50.21#ibcon#enter wrdev, iclass 23, count 2 2006.211.07:43:50.21#ibcon#first serial, iclass 23, count 2 2006.211.07:43:50.21#ibcon#enter sib2, iclass 23, count 2 2006.211.07:43:50.21#ibcon#flushed, iclass 23, count 2 2006.211.07:43:50.21#ibcon#about to write, iclass 23, count 2 2006.211.07:43:50.21#ibcon#wrote, iclass 23, count 2 2006.211.07:43:50.21#ibcon#about to read 3, iclass 23, count 2 2006.211.07:43:50.23#ibcon#read 3, iclass 23, count 2 2006.211.07:43:50.23#ibcon#about to read 4, iclass 23, count 2 2006.211.07:43:50.23#ibcon#read 4, iclass 23, count 2 2006.211.07:43:50.23#ibcon#about to read 5, iclass 23, count 2 2006.211.07:43:50.23#ibcon#read 5, iclass 23, count 2 2006.211.07:43:50.23#ibcon#about to read 6, iclass 23, count 2 2006.211.07:43:50.23#ibcon#read 6, iclass 23, count 2 2006.211.07:43:50.23#ibcon#end of sib2, iclass 23, count 2 2006.211.07:43:50.23#ibcon#*mode == 0, iclass 23, count 2 2006.211.07:43:50.23#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.07:43:50.23#ibcon#[27=AT01-04\r\n] 2006.211.07:43:50.23#ibcon#*before write, iclass 23, count 2 2006.211.07:43:50.23#ibcon#enter sib2, iclass 23, count 2 2006.211.07:43:50.23#ibcon#flushed, iclass 23, count 2 2006.211.07:43:50.23#ibcon#about to write, iclass 23, count 2 2006.211.07:43:50.23#ibcon#wrote, iclass 23, count 2 2006.211.07:43:50.23#ibcon#about to read 3, iclass 23, count 2 2006.211.07:43:50.26#ibcon#read 3, iclass 23, count 2 2006.211.07:43:50.26#ibcon#about to read 4, iclass 23, count 2 2006.211.07:43:50.26#ibcon#read 4, iclass 23, count 2 2006.211.07:43:50.26#ibcon#about to read 5, iclass 23, count 2 2006.211.07:43:50.26#ibcon#read 5, iclass 23, count 2 2006.211.07:43:50.26#ibcon#about to read 6, iclass 23, count 2 2006.211.07:43:50.26#ibcon#read 6, iclass 23, count 2 2006.211.07:43:50.26#ibcon#end of sib2, iclass 23, count 2 2006.211.07:43:50.26#ibcon#*after write, iclass 23, count 2 2006.211.07:43:50.26#ibcon#*before return 0, iclass 23, count 2 2006.211.07:43:50.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:50.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:43:50.26#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.07:43:50.26#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:50.26#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:50.38#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:50.38#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:50.38#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:43:50.38#ibcon#first serial, iclass 23, count 0 2006.211.07:43:50.38#ibcon#enter sib2, iclass 23, count 0 2006.211.07:43:50.38#ibcon#flushed, iclass 23, count 0 2006.211.07:43:50.38#ibcon#about to write, iclass 23, count 0 2006.211.07:43:50.38#ibcon#wrote, iclass 23, count 0 2006.211.07:43:50.38#ibcon#about to read 3, iclass 23, count 0 2006.211.07:43:50.40#ibcon#read 3, iclass 23, count 0 2006.211.07:43:50.40#ibcon#about to read 4, iclass 23, count 0 2006.211.07:43:50.40#ibcon#read 4, iclass 23, count 0 2006.211.07:43:50.40#ibcon#about to read 5, iclass 23, count 0 2006.211.07:43:50.40#ibcon#read 5, iclass 23, count 0 2006.211.07:43:50.40#ibcon#about to read 6, iclass 23, count 0 2006.211.07:43:50.40#ibcon#read 6, iclass 23, count 0 2006.211.07:43:50.40#ibcon#end of sib2, iclass 23, count 0 2006.211.07:43:50.40#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:43:50.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:43:50.40#ibcon#[27=USB\r\n] 2006.211.07:43:50.40#ibcon#*before write, iclass 23, count 0 2006.211.07:43:50.40#ibcon#enter sib2, iclass 23, count 0 2006.211.07:43:50.40#ibcon#flushed, iclass 23, count 0 2006.211.07:43:50.40#ibcon#about to write, iclass 23, count 0 2006.211.07:43:50.40#ibcon#wrote, iclass 23, count 0 2006.211.07:43:50.40#ibcon#about to read 3, iclass 23, count 0 2006.211.07:43:50.43#ibcon#read 3, iclass 23, count 0 2006.211.07:43:50.43#ibcon#about to read 4, iclass 23, count 0 2006.211.07:43:50.43#ibcon#read 4, iclass 23, count 0 2006.211.07:43:50.43#ibcon#about to read 5, iclass 23, count 0 2006.211.07:43:50.43#ibcon#read 5, iclass 23, count 0 2006.211.07:43:50.43#ibcon#about to read 6, iclass 23, count 0 2006.211.07:43:50.43#ibcon#read 6, iclass 23, count 0 2006.211.07:43:50.43#ibcon#end of sib2, iclass 23, count 0 2006.211.07:43:50.43#ibcon#*after write, iclass 23, count 0 2006.211.07:43:50.43#ibcon#*before return 0, iclass 23, count 0 2006.211.07:43:50.43#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:50.43#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:43:50.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:43:50.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:43:50.43$vc4f8/vblo=2,640.99 2006.211.07:43:50.43#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:43:50.43#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:43:50.43#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:50.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:50.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:50.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:50.43#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:43:50.43#ibcon#first serial, iclass 25, count 0 2006.211.07:43:50.43#ibcon#enter sib2, iclass 25, count 0 2006.211.07:43:50.43#ibcon#flushed, iclass 25, count 0 2006.211.07:43:50.43#ibcon#about to write, iclass 25, count 0 2006.211.07:43:50.43#ibcon#wrote, iclass 25, count 0 2006.211.07:43:50.43#ibcon#about to read 3, iclass 25, count 0 2006.211.07:43:50.45#ibcon#read 3, iclass 25, count 0 2006.211.07:43:50.45#ibcon#about to read 4, iclass 25, count 0 2006.211.07:43:50.45#ibcon#read 4, iclass 25, count 0 2006.211.07:43:50.45#ibcon#about to read 5, iclass 25, count 0 2006.211.07:43:50.45#ibcon#read 5, iclass 25, count 0 2006.211.07:43:50.45#ibcon#about to read 6, iclass 25, count 0 2006.211.07:43:50.45#ibcon#read 6, iclass 25, count 0 2006.211.07:43:50.45#ibcon#end of sib2, iclass 25, count 0 2006.211.07:43:50.45#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:43:50.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:43:50.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:43:50.45#ibcon#*before write, iclass 25, count 0 2006.211.07:43:50.45#ibcon#enter sib2, iclass 25, count 0 2006.211.07:43:50.45#ibcon#flushed, iclass 25, count 0 2006.211.07:43:50.45#ibcon#about to write, iclass 25, count 0 2006.211.07:43:50.45#ibcon#wrote, iclass 25, count 0 2006.211.07:43:50.45#ibcon#about to read 3, iclass 25, count 0 2006.211.07:43:50.49#ibcon#read 3, iclass 25, count 0 2006.211.07:43:50.49#ibcon#about to read 4, iclass 25, count 0 2006.211.07:43:50.49#ibcon#read 4, iclass 25, count 0 2006.211.07:43:50.49#ibcon#about to read 5, iclass 25, count 0 2006.211.07:43:50.49#ibcon#read 5, iclass 25, count 0 2006.211.07:43:50.49#ibcon#about to read 6, iclass 25, count 0 2006.211.07:43:50.49#ibcon#read 6, iclass 25, count 0 2006.211.07:43:50.49#ibcon#end of sib2, iclass 25, count 0 2006.211.07:43:50.49#ibcon#*after write, iclass 25, count 0 2006.211.07:43:50.49#ibcon#*before return 0, iclass 25, count 0 2006.211.07:43:50.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:50.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:43:50.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:43:50.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:43:50.49$vc4f8/vb=2,4 2006.211.07:43:50.49#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.07:43:50.49#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.07:43:50.49#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:50.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:50.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:50.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:50.55#ibcon#enter wrdev, iclass 27, count 2 2006.211.07:43:50.55#ibcon#first serial, iclass 27, count 2 2006.211.07:43:50.55#ibcon#enter sib2, iclass 27, count 2 2006.211.07:43:50.55#ibcon#flushed, iclass 27, count 2 2006.211.07:43:50.55#ibcon#about to write, iclass 27, count 2 2006.211.07:43:50.55#ibcon#wrote, iclass 27, count 2 2006.211.07:43:50.55#ibcon#about to read 3, iclass 27, count 2 2006.211.07:43:50.57#ibcon#read 3, iclass 27, count 2 2006.211.07:43:50.57#ibcon#about to read 4, iclass 27, count 2 2006.211.07:43:50.57#ibcon#read 4, iclass 27, count 2 2006.211.07:43:50.57#ibcon#about to read 5, iclass 27, count 2 2006.211.07:43:50.57#ibcon#read 5, iclass 27, count 2 2006.211.07:43:50.57#ibcon#about to read 6, iclass 27, count 2 2006.211.07:43:50.57#ibcon#read 6, iclass 27, count 2 2006.211.07:43:50.57#ibcon#end of sib2, iclass 27, count 2 2006.211.07:43:50.57#ibcon#*mode == 0, iclass 27, count 2 2006.211.07:43:50.57#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.07:43:50.57#ibcon#[27=AT02-04\r\n] 2006.211.07:43:50.57#ibcon#*before write, iclass 27, count 2 2006.211.07:43:50.57#ibcon#enter sib2, iclass 27, count 2 2006.211.07:43:50.57#ibcon#flushed, iclass 27, count 2 2006.211.07:43:50.57#ibcon#about to write, iclass 27, count 2 2006.211.07:43:50.57#ibcon#wrote, iclass 27, count 2 2006.211.07:43:50.57#ibcon#about to read 3, iclass 27, count 2 2006.211.07:43:50.60#ibcon#read 3, iclass 27, count 2 2006.211.07:43:50.60#ibcon#about to read 4, iclass 27, count 2 2006.211.07:43:50.60#ibcon#read 4, iclass 27, count 2 2006.211.07:43:50.60#ibcon#about to read 5, iclass 27, count 2 2006.211.07:43:50.60#ibcon#read 5, iclass 27, count 2 2006.211.07:43:50.60#ibcon#about to read 6, iclass 27, count 2 2006.211.07:43:50.60#ibcon#read 6, iclass 27, count 2 2006.211.07:43:50.60#ibcon#end of sib2, iclass 27, count 2 2006.211.07:43:50.60#ibcon#*after write, iclass 27, count 2 2006.211.07:43:50.60#ibcon#*before return 0, iclass 27, count 2 2006.211.07:43:50.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:50.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:43:50.60#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.07:43:50.60#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:50.60#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:50.72#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:50.72#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:50.72#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:43:50.72#ibcon#first serial, iclass 27, count 0 2006.211.07:43:50.72#ibcon#enter sib2, iclass 27, count 0 2006.211.07:43:50.72#ibcon#flushed, iclass 27, count 0 2006.211.07:43:50.72#ibcon#about to write, iclass 27, count 0 2006.211.07:43:50.72#ibcon#wrote, iclass 27, count 0 2006.211.07:43:50.72#ibcon#about to read 3, iclass 27, count 0 2006.211.07:43:50.74#ibcon#read 3, iclass 27, count 0 2006.211.07:43:50.74#ibcon#about to read 4, iclass 27, count 0 2006.211.07:43:50.74#ibcon#read 4, iclass 27, count 0 2006.211.07:43:50.74#ibcon#about to read 5, iclass 27, count 0 2006.211.07:43:50.74#ibcon#read 5, iclass 27, count 0 2006.211.07:43:50.74#ibcon#about to read 6, iclass 27, count 0 2006.211.07:43:50.74#ibcon#read 6, iclass 27, count 0 2006.211.07:43:50.74#ibcon#end of sib2, iclass 27, count 0 2006.211.07:43:50.74#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:43:50.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:43:50.74#ibcon#[27=USB\r\n] 2006.211.07:43:50.74#ibcon#*before write, iclass 27, count 0 2006.211.07:43:50.74#ibcon#enter sib2, iclass 27, count 0 2006.211.07:43:50.74#ibcon#flushed, iclass 27, count 0 2006.211.07:43:50.74#ibcon#about to write, iclass 27, count 0 2006.211.07:43:50.74#ibcon#wrote, iclass 27, count 0 2006.211.07:43:50.74#ibcon#about to read 3, iclass 27, count 0 2006.211.07:43:50.77#ibcon#read 3, iclass 27, count 0 2006.211.07:43:50.77#ibcon#about to read 4, iclass 27, count 0 2006.211.07:43:50.77#ibcon#read 4, iclass 27, count 0 2006.211.07:43:50.77#ibcon#about to read 5, iclass 27, count 0 2006.211.07:43:50.77#ibcon#read 5, iclass 27, count 0 2006.211.07:43:50.77#ibcon#about to read 6, iclass 27, count 0 2006.211.07:43:50.77#ibcon#read 6, iclass 27, count 0 2006.211.07:43:50.77#ibcon#end of sib2, iclass 27, count 0 2006.211.07:43:50.77#ibcon#*after write, iclass 27, count 0 2006.211.07:43:50.77#ibcon#*before return 0, iclass 27, count 0 2006.211.07:43:50.77#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:50.77#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:43:50.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:43:50.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:43:50.77$vc4f8/vblo=3,656.99 2006.211.07:43:50.77#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:43:50.77#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:43:50.77#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:50.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:50.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:50.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:50.77#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:43:50.77#ibcon#first serial, iclass 29, count 0 2006.211.07:43:50.77#ibcon#enter sib2, iclass 29, count 0 2006.211.07:43:50.77#ibcon#flushed, iclass 29, count 0 2006.211.07:43:50.77#ibcon#about to write, iclass 29, count 0 2006.211.07:43:50.77#ibcon#wrote, iclass 29, count 0 2006.211.07:43:50.77#ibcon#about to read 3, iclass 29, count 0 2006.211.07:43:50.79#ibcon#read 3, iclass 29, count 0 2006.211.07:43:50.79#ibcon#about to read 4, iclass 29, count 0 2006.211.07:43:50.79#ibcon#read 4, iclass 29, count 0 2006.211.07:43:50.79#ibcon#about to read 5, iclass 29, count 0 2006.211.07:43:50.79#ibcon#read 5, iclass 29, count 0 2006.211.07:43:50.79#ibcon#about to read 6, iclass 29, count 0 2006.211.07:43:50.79#ibcon#read 6, iclass 29, count 0 2006.211.07:43:50.79#ibcon#end of sib2, iclass 29, count 0 2006.211.07:43:50.79#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:43:50.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:43:50.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:43:50.79#ibcon#*before write, iclass 29, count 0 2006.211.07:43:50.79#ibcon#enter sib2, iclass 29, count 0 2006.211.07:43:50.79#ibcon#flushed, iclass 29, count 0 2006.211.07:43:50.79#ibcon#about to write, iclass 29, count 0 2006.211.07:43:50.79#ibcon#wrote, iclass 29, count 0 2006.211.07:43:50.79#ibcon#about to read 3, iclass 29, count 0 2006.211.07:43:50.83#ibcon#read 3, iclass 29, count 0 2006.211.07:43:50.83#ibcon#about to read 4, iclass 29, count 0 2006.211.07:43:50.83#ibcon#read 4, iclass 29, count 0 2006.211.07:43:50.83#ibcon#about to read 5, iclass 29, count 0 2006.211.07:43:50.83#ibcon#read 5, iclass 29, count 0 2006.211.07:43:50.83#ibcon#about to read 6, iclass 29, count 0 2006.211.07:43:50.83#ibcon#read 6, iclass 29, count 0 2006.211.07:43:50.83#ibcon#end of sib2, iclass 29, count 0 2006.211.07:43:50.83#ibcon#*after write, iclass 29, count 0 2006.211.07:43:50.83#ibcon#*before return 0, iclass 29, count 0 2006.211.07:43:50.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:50.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:43:50.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:43:50.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:43:50.83$vc4f8/vb=3,3 2006.211.07:43:50.83#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:43:50.83#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:43:50.83#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:50.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:50.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:50.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:50.89#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:43:50.89#ibcon#first serial, iclass 31, count 2 2006.211.07:43:50.89#ibcon#enter sib2, iclass 31, count 2 2006.211.07:43:50.89#ibcon#flushed, iclass 31, count 2 2006.211.07:43:50.89#ibcon#about to write, iclass 31, count 2 2006.211.07:43:50.89#ibcon#wrote, iclass 31, count 2 2006.211.07:43:50.89#ibcon#about to read 3, iclass 31, count 2 2006.211.07:43:50.91#ibcon#read 3, iclass 31, count 2 2006.211.07:43:50.91#ibcon#about to read 4, iclass 31, count 2 2006.211.07:43:50.91#ibcon#read 4, iclass 31, count 2 2006.211.07:43:50.91#ibcon#about to read 5, iclass 31, count 2 2006.211.07:43:50.91#ibcon#read 5, iclass 31, count 2 2006.211.07:43:50.91#ibcon#about to read 6, iclass 31, count 2 2006.211.07:43:50.91#ibcon#read 6, iclass 31, count 2 2006.211.07:43:50.91#ibcon#end of sib2, iclass 31, count 2 2006.211.07:43:50.91#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:43:50.91#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:43:50.91#ibcon#[27=AT03-03\r\n] 2006.211.07:43:50.91#ibcon#*before write, iclass 31, count 2 2006.211.07:43:50.91#ibcon#enter sib2, iclass 31, count 2 2006.211.07:43:50.91#ibcon#flushed, iclass 31, count 2 2006.211.07:43:50.91#ibcon#about to write, iclass 31, count 2 2006.211.07:43:50.91#ibcon#wrote, iclass 31, count 2 2006.211.07:43:50.91#ibcon#about to read 3, iclass 31, count 2 2006.211.07:43:50.94#ibcon#read 3, iclass 31, count 2 2006.211.07:43:50.94#ibcon#about to read 4, iclass 31, count 2 2006.211.07:43:50.94#ibcon#read 4, iclass 31, count 2 2006.211.07:43:50.94#ibcon#about to read 5, iclass 31, count 2 2006.211.07:43:50.94#ibcon#read 5, iclass 31, count 2 2006.211.07:43:50.94#ibcon#about to read 6, iclass 31, count 2 2006.211.07:43:50.94#ibcon#read 6, iclass 31, count 2 2006.211.07:43:50.94#ibcon#end of sib2, iclass 31, count 2 2006.211.07:43:50.94#ibcon#*after write, iclass 31, count 2 2006.211.07:43:50.94#ibcon#*before return 0, iclass 31, count 2 2006.211.07:43:50.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:50.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:43:50.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:43:50.94#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:50.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:51.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:51.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:51.06#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:43:51.06#ibcon#first serial, iclass 31, count 0 2006.211.07:43:51.06#ibcon#enter sib2, iclass 31, count 0 2006.211.07:43:51.06#ibcon#flushed, iclass 31, count 0 2006.211.07:43:51.06#ibcon#about to write, iclass 31, count 0 2006.211.07:43:51.06#ibcon#wrote, iclass 31, count 0 2006.211.07:43:51.06#ibcon#about to read 3, iclass 31, count 0 2006.211.07:43:51.08#ibcon#read 3, iclass 31, count 0 2006.211.07:43:51.08#ibcon#about to read 4, iclass 31, count 0 2006.211.07:43:51.08#ibcon#read 4, iclass 31, count 0 2006.211.07:43:51.08#ibcon#about to read 5, iclass 31, count 0 2006.211.07:43:51.08#ibcon#read 5, iclass 31, count 0 2006.211.07:43:51.08#ibcon#about to read 6, iclass 31, count 0 2006.211.07:43:51.08#ibcon#read 6, iclass 31, count 0 2006.211.07:43:51.08#ibcon#end of sib2, iclass 31, count 0 2006.211.07:43:51.08#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:43:51.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:43:51.08#ibcon#[27=USB\r\n] 2006.211.07:43:51.08#ibcon#*before write, iclass 31, count 0 2006.211.07:43:51.08#ibcon#enter sib2, iclass 31, count 0 2006.211.07:43:51.08#ibcon#flushed, iclass 31, count 0 2006.211.07:43:51.08#ibcon#about to write, iclass 31, count 0 2006.211.07:43:51.08#ibcon#wrote, iclass 31, count 0 2006.211.07:43:51.08#ibcon#about to read 3, iclass 31, count 0 2006.211.07:43:51.11#ibcon#read 3, iclass 31, count 0 2006.211.07:43:51.11#ibcon#about to read 4, iclass 31, count 0 2006.211.07:43:51.11#ibcon#read 4, iclass 31, count 0 2006.211.07:43:51.11#ibcon#about to read 5, iclass 31, count 0 2006.211.07:43:51.11#ibcon#read 5, iclass 31, count 0 2006.211.07:43:51.11#ibcon#about to read 6, iclass 31, count 0 2006.211.07:43:51.11#ibcon#read 6, iclass 31, count 0 2006.211.07:43:51.11#ibcon#end of sib2, iclass 31, count 0 2006.211.07:43:51.11#ibcon#*after write, iclass 31, count 0 2006.211.07:43:51.11#ibcon#*before return 0, iclass 31, count 0 2006.211.07:43:51.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:51.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:43:51.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:43:51.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:43:51.11$vc4f8/vblo=4,712.99 2006.211.07:43:51.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:43:51.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:43:51.11#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:51.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:51.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:51.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:51.11#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:43:51.11#ibcon#first serial, iclass 33, count 0 2006.211.07:43:51.11#ibcon#enter sib2, iclass 33, count 0 2006.211.07:43:51.11#ibcon#flushed, iclass 33, count 0 2006.211.07:43:51.11#ibcon#about to write, iclass 33, count 0 2006.211.07:43:51.11#ibcon#wrote, iclass 33, count 0 2006.211.07:43:51.11#ibcon#about to read 3, iclass 33, count 0 2006.211.07:43:51.13#ibcon#read 3, iclass 33, count 0 2006.211.07:43:51.13#ibcon#about to read 4, iclass 33, count 0 2006.211.07:43:51.13#ibcon#read 4, iclass 33, count 0 2006.211.07:43:51.13#ibcon#about to read 5, iclass 33, count 0 2006.211.07:43:51.13#ibcon#read 5, iclass 33, count 0 2006.211.07:43:51.13#ibcon#about to read 6, iclass 33, count 0 2006.211.07:43:51.13#ibcon#read 6, iclass 33, count 0 2006.211.07:43:51.13#ibcon#end of sib2, iclass 33, count 0 2006.211.07:43:51.13#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:43:51.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:43:51.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:43:51.13#ibcon#*before write, iclass 33, count 0 2006.211.07:43:51.13#ibcon#enter sib2, iclass 33, count 0 2006.211.07:43:51.13#ibcon#flushed, iclass 33, count 0 2006.211.07:43:51.13#ibcon#about to write, iclass 33, count 0 2006.211.07:43:51.13#ibcon#wrote, iclass 33, count 0 2006.211.07:43:51.13#ibcon#about to read 3, iclass 33, count 0 2006.211.07:43:51.17#ibcon#read 3, iclass 33, count 0 2006.211.07:43:51.17#ibcon#about to read 4, iclass 33, count 0 2006.211.07:43:51.17#ibcon#read 4, iclass 33, count 0 2006.211.07:43:51.17#ibcon#about to read 5, iclass 33, count 0 2006.211.07:43:51.17#ibcon#read 5, iclass 33, count 0 2006.211.07:43:51.17#ibcon#about to read 6, iclass 33, count 0 2006.211.07:43:51.17#ibcon#read 6, iclass 33, count 0 2006.211.07:43:51.17#ibcon#end of sib2, iclass 33, count 0 2006.211.07:43:51.17#ibcon#*after write, iclass 33, count 0 2006.211.07:43:51.17#ibcon#*before return 0, iclass 33, count 0 2006.211.07:43:51.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:51.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:43:51.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:43:51.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:43:51.17$vc4f8/vb=4,3 2006.211.07:43:51.17#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:43:51.17#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:43:51.17#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:51.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:51.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:51.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:51.23#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:43:51.23#ibcon#first serial, iclass 35, count 2 2006.211.07:43:51.23#ibcon#enter sib2, iclass 35, count 2 2006.211.07:43:51.23#ibcon#flushed, iclass 35, count 2 2006.211.07:43:51.23#ibcon#about to write, iclass 35, count 2 2006.211.07:43:51.23#ibcon#wrote, iclass 35, count 2 2006.211.07:43:51.23#ibcon#about to read 3, iclass 35, count 2 2006.211.07:43:51.25#ibcon#read 3, iclass 35, count 2 2006.211.07:43:51.25#ibcon#about to read 4, iclass 35, count 2 2006.211.07:43:51.25#ibcon#read 4, iclass 35, count 2 2006.211.07:43:51.25#ibcon#about to read 5, iclass 35, count 2 2006.211.07:43:51.25#ibcon#read 5, iclass 35, count 2 2006.211.07:43:51.25#ibcon#about to read 6, iclass 35, count 2 2006.211.07:43:51.25#ibcon#read 6, iclass 35, count 2 2006.211.07:43:51.25#ibcon#end of sib2, iclass 35, count 2 2006.211.07:43:51.25#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:43:51.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:43:51.25#ibcon#[27=AT04-03\r\n] 2006.211.07:43:51.25#ibcon#*before write, iclass 35, count 2 2006.211.07:43:51.25#ibcon#enter sib2, iclass 35, count 2 2006.211.07:43:51.25#ibcon#flushed, iclass 35, count 2 2006.211.07:43:51.25#ibcon#about to write, iclass 35, count 2 2006.211.07:43:51.25#ibcon#wrote, iclass 35, count 2 2006.211.07:43:51.25#ibcon#about to read 3, iclass 35, count 2 2006.211.07:43:51.28#ibcon#read 3, iclass 35, count 2 2006.211.07:43:51.28#ibcon#about to read 4, iclass 35, count 2 2006.211.07:43:51.28#ibcon#read 4, iclass 35, count 2 2006.211.07:43:51.28#ibcon#about to read 5, iclass 35, count 2 2006.211.07:43:51.28#ibcon#read 5, iclass 35, count 2 2006.211.07:43:51.28#ibcon#about to read 6, iclass 35, count 2 2006.211.07:43:51.28#ibcon#read 6, iclass 35, count 2 2006.211.07:43:51.28#ibcon#end of sib2, iclass 35, count 2 2006.211.07:43:51.28#ibcon#*after write, iclass 35, count 2 2006.211.07:43:51.28#ibcon#*before return 0, iclass 35, count 2 2006.211.07:43:51.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:51.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:43:51.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:43:51.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:51.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:51.40#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:51.40#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:51.40#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:43:51.40#ibcon#first serial, iclass 35, count 0 2006.211.07:43:51.40#ibcon#enter sib2, iclass 35, count 0 2006.211.07:43:51.40#ibcon#flushed, iclass 35, count 0 2006.211.07:43:51.40#ibcon#about to write, iclass 35, count 0 2006.211.07:43:51.40#ibcon#wrote, iclass 35, count 0 2006.211.07:43:51.40#ibcon#about to read 3, iclass 35, count 0 2006.211.07:43:51.42#ibcon#read 3, iclass 35, count 0 2006.211.07:43:51.42#ibcon#about to read 4, iclass 35, count 0 2006.211.07:43:51.42#ibcon#read 4, iclass 35, count 0 2006.211.07:43:51.42#ibcon#about to read 5, iclass 35, count 0 2006.211.07:43:51.42#ibcon#read 5, iclass 35, count 0 2006.211.07:43:51.42#ibcon#about to read 6, iclass 35, count 0 2006.211.07:43:51.42#ibcon#read 6, iclass 35, count 0 2006.211.07:43:51.42#ibcon#end of sib2, iclass 35, count 0 2006.211.07:43:51.42#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:43:51.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:43:51.42#ibcon#[27=USB\r\n] 2006.211.07:43:51.42#ibcon#*before write, iclass 35, count 0 2006.211.07:43:51.42#ibcon#enter sib2, iclass 35, count 0 2006.211.07:43:51.42#ibcon#flushed, iclass 35, count 0 2006.211.07:43:51.42#ibcon#about to write, iclass 35, count 0 2006.211.07:43:51.42#ibcon#wrote, iclass 35, count 0 2006.211.07:43:51.42#ibcon#about to read 3, iclass 35, count 0 2006.211.07:43:51.45#ibcon#read 3, iclass 35, count 0 2006.211.07:43:51.45#ibcon#about to read 4, iclass 35, count 0 2006.211.07:43:51.45#ibcon#read 4, iclass 35, count 0 2006.211.07:43:51.45#ibcon#about to read 5, iclass 35, count 0 2006.211.07:43:51.45#ibcon#read 5, iclass 35, count 0 2006.211.07:43:51.45#ibcon#about to read 6, iclass 35, count 0 2006.211.07:43:51.45#ibcon#read 6, iclass 35, count 0 2006.211.07:43:51.45#ibcon#end of sib2, iclass 35, count 0 2006.211.07:43:51.45#ibcon#*after write, iclass 35, count 0 2006.211.07:43:51.45#ibcon#*before return 0, iclass 35, count 0 2006.211.07:43:51.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:51.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:43:51.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:43:51.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:43:51.45$vc4f8/vblo=5,744.99 2006.211.07:43:51.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:43:51.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:43:51.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:51.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:51.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:51.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:51.45#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:43:51.45#ibcon#first serial, iclass 37, count 0 2006.211.07:43:51.45#ibcon#enter sib2, iclass 37, count 0 2006.211.07:43:51.45#ibcon#flushed, iclass 37, count 0 2006.211.07:43:51.45#ibcon#about to write, iclass 37, count 0 2006.211.07:43:51.45#ibcon#wrote, iclass 37, count 0 2006.211.07:43:51.45#ibcon#about to read 3, iclass 37, count 0 2006.211.07:43:51.47#ibcon#read 3, iclass 37, count 0 2006.211.07:43:51.47#ibcon#about to read 4, iclass 37, count 0 2006.211.07:43:51.47#ibcon#read 4, iclass 37, count 0 2006.211.07:43:51.47#ibcon#about to read 5, iclass 37, count 0 2006.211.07:43:51.47#ibcon#read 5, iclass 37, count 0 2006.211.07:43:51.47#ibcon#about to read 6, iclass 37, count 0 2006.211.07:43:51.47#ibcon#read 6, iclass 37, count 0 2006.211.07:43:51.47#ibcon#end of sib2, iclass 37, count 0 2006.211.07:43:51.47#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:43:51.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:43:51.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:43:51.47#ibcon#*before write, iclass 37, count 0 2006.211.07:43:51.47#ibcon#enter sib2, iclass 37, count 0 2006.211.07:43:51.47#ibcon#flushed, iclass 37, count 0 2006.211.07:43:51.47#ibcon#about to write, iclass 37, count 0 2006.211.07:43:51.47#ibcon#wrote, iclass 37, count 0 2006.211.07:43:51.47#ibcon#about to read 3, iclass 37, count 0 2006.211.07:43:51.51#ibcon#read 3, iclass 37, count 0 2006.211.07:43:51.51#ibcon#about to read 4, iclass 37, count 0 2006.211.07:43:51.51#ibcon#read 4, iclass 37, count 0 2006.211.07:43:51.51#ibcon#about to read 5, iclass 37, count 0 2006.211.07:43:51.51#ibcon#read 5, iclass 37, count 0 2006.211.07:43:51.51#ibcon#about to read 6, iclass 37, count 0 2006.211.07:43:51.51#ibcon#read 6, iclass 37, count 0 2006.211.07:43:51.51#ibcon#end of sib2, iclass 37, count 0 2006.211.07:43:51.51#ibcon#*after write, iclass 37, count 0 2006.211.07:43:51.51#ibcon#*before return 0, iclass 37, count 0 2006.211.07:43:51.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:51.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:43:51.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:43:51.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:43:51.51$vc4f8/vb=5,3 2006.211.07:43:51.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:43:51.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:43:51.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:51.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:51.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:51.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:51.57#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:43:51.57#ibcon#first serial, iclass 39, count 2 2006.211.07:43:51.57#ibcon#enter sib2, iclass 39, count 2 2006.211.07:43:51.57#ibcon#flushed, iclass 39, count 2 2006.211.07:43:51.57#ibcon#about to write, iclass 39, count 2 2006.211.07:43:51.57#ibcon#wrote, iclass 39, count 2 2006.211.07:43:51.57#ibcon#about to read 3, iclass 39, count 2 2006.211.07:43:51.59#ibcon#read 3, iclass 39, count 2 2006.211.07:43:51.59#ibcon#about to read 4, iclass 39, count 2 2006.211.07:43:51.59#ibcon#read 4, iclass 39, count 2 2006.211.07:43:51.59#ibcon#about to read 5, iclass 39, count 2 2006.211.07:43:51.59#ibcon#read 5, iclass 39, count 2 2006.211.07:43:51.59#ibcon#about to read 6, iclass 39, count 2 2006.211.07:43:51.59#ibcon#read 6, iclass 39, count 2 2006.211.07:43:51.59#ibcon#end of sib2, iclass 39, count 2 2006.211.07:43:51.59#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:43:51.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:43:51.59#ibcon#[27=AT05-03\r\n] 2006.211.07:43:51.59#ibcon#*before write, iclass 39, count 2 2006.211.07:43:51.59#ibcon#enter sib2, iclass 39, count 2 2006.211.07:43:51.59#ibcon#flushed, iclass 39, count 2 2006.211.07:43:51.59#ibcon#about to write, iclass 39, count 2 2006.211.07:43:51.59#ibcon#wrote, iclass 39, count 2 2006.211.07:43:51.59#ibcon#about to read 3, iclass 39, count 2 2006.211.07:43:51.62#ibcon#read 3, iclass 39, count 2 2006.211.07:43:51.62#ibcon#about to read 4, iclass 39, count 2 2006.211.07:43:51.62#ibcon#read 4, iclass 39, count 2 2006.211.07:43:51.62#ibcon#about to read 5, iclass 39, count 2 2006.211.07:43:51.62#ibcon#read 5, iclass 39, count 2 2006.211.07:43:51.62#ibcon#about to read 6, iclass 39, count 2 2006.211.07:43:51.62#ibcon#read 6, iclass 39, count 2 2006.211.07:43:51.62#ibcon#end of sib2, iclass 39, count 2 2006.211.07:43:51.62#ibcon#*after write, iclass 39, count 2 2006.211.07:43:51.62#ibcon#*before return 0, iclass 39, count 2 2006.211.07:43:51.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:51.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:43:51.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:43:51.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:51.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:51.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:51.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:51.74#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:43:51.74#ibcon#first serial, iclass 39, count 0 2006.211.07:43:51.74#ibcon#enter sib2, iclass 39, count 0 2006.211.07:43:51.74#ibcon#flushed, iclass 39, count 0 2006.211.07:43:51.74#ibcon#about to write, iclass 39, count 0 2006.211.07:43:51.74#ibcon#wrote, iclass 39, count 0 2006.211.07:43:51.74#ibcon#about to read 3, iclass 39, count 0 2006.211.07:43:51.76#ibcon#read 3, iclass 39, count 0 2006.211.07:43:51.76#ibcon#about to read 4, iclass 39, count 0 2006.211.07:43:51.76#ibcon#read 4, iclass 39, count 0 2006.211.07:43:51.76#ibcon#about to read 5, iclass 39, count 0 2006.211.07:43:51.76#ibcon#read 5, iclass 39, count 0 2006.211.07:43:51.76#ibcon#about to read 6, iclass 39, count 0 2006.211.07:43:51.76#ibcon#read 6, iclass 39, count 0 2006.211.07:43:51.76#ibcon#end of sib2, iclass 39, count 0 2006.211.07:43:51.76#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:43:51.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:43:51.76#ibcon#[27=USB\r\n] 2006.211.07:43:51.76#ibcon#*before write, iclass 39, count 0 2006.211.07:43:51.76#ibcon#enter sib2, iclass 39, count 0 2006.211.07:43:51.76#ibcon#flushed, iclass 39, count 0 2006.211.07:43:51.76#ibcon#about to write, iclass 39, count 0 2006.211.07:43:51.76#ibcon#wrote, iclass 39, count 0 2006.211.07:43:51.76#ibcon#about to read 3, iclass 39, count 0 2006.211.07:43:51.79#ibcon#read 3, iclass 39, count 0 2006.211.07:43:51.79#ibcon#about to read 4, iclass 39, count 0 2006.211.07:43:51.79#ibcon#read 4, iclass 39, count 0 2006.211.07:43:51.79#ibcon#about to read 5, iclass 39, count 0 2006.211.07:43:51.79#ibcon#read 5, iclass 39, count 0 2006.211.07:43:51.79#ibcon#about to read 6, iclass 39, count 0 2006.211.07:43:51.79#ibcon#read 6, iclass 39, count 0 2006.211.07:43:51.79#ibcon#end of sib2, iclass 39, count 0 2006.211.07:43:51.79#ibcon#*after write, iclass 39, count 0 2006.211.07:43:51.79#ibcon#*before return 0, iclass 39, count 0 2006.211.07:43:51.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:51.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:43:51.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:43:51.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:43:51.79$vc4f8/vblo=6,752.99 2006.211.07:43:51.79#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:43:51.79#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:43:51.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:43:51.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:43:51.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:43:51.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:43:51.79#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:43:51.79#ibcon#first serial, iclass 3, count 0 2006.211.07:43:51.79#ibcon#enter sib2, iclass 3, count 0 2006.211.07:43:51.79#ibcon#flushed, iclass 3, count 0 2006.211.07:43:51.79#ibcon#about to write, iclass 3, count 0 2006.211.07:43:51.79#ibcon#wrote, iclass 3, count 0 2006.211.07:43:51.79#ibcon#about to read 3, iclass 3, count 0 2006.211.07:43:51.81#ibcon#read 3, iclass 3, count 0 2006.211.07:43:51.81#ibcon#about to read 4, iclass 3, count 0 2006.211.07:43:51.81#ibcon#read 4, iclass 3, count 0 2006.211.07:43:51.81#ibcon#about to read 5, iclass 3, count 0 2006.211.07:43:51.81#ibcon#read 5, iclass 3, count 0 2006.211.07:43:51.81#ibcon#about to read 6, iclass 3, count 0 2006.211.07:43:51.81#ibcon#read 6, iclass 3, count 0 2006.211.07:43:51.81#ibcon#end of sib2, iclass 3, count 0 2006.211.07:43:51.81#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:43:51.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:43:51.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:43:51.81#ibcon#*before write, iclass 3, count 0 2006.211.07:43:51.81#ibcon#enter sib2, iclass 3, count 0 2006.211.07:43:51.81#ibcon#flushed, iclass 3, count 0 2006.211.07:43:51.81#ibcon#about to write, iclass 3, count 0 2006.211.07:43:51.81#ibcon#wrote, iclass 3, count 0 2006.211.07:43:51.81#ibcon#about to read 3, iclass 3, count 0 2006.211.07:43:51.85#ibcon#read 3, iclass 3, count 0 2006.211.07:43:51.85#ibcon#about to read 4, iclass 3, count 0 2006.211.07:43:51.85#ibcon#read 4, iclass 3, count 0 2006.211.07:43:51.85#ibcon#about to read 5, iclass 3, count 0 2006.211.07:43:51.85#ibcon#read 5, iclass 3, count 0 2006.211.07:43:51.85#ibcon#about to read 6, iclass 3, count 0 2006.211.07:43:51.85#ibcon#read 6, iclass 3, count 0 2006.211.07:43:51.85#ibcon#end of sib2, iclass 3, count 0 2006.211.07:43:51.85#ibcon#*after write, iclass 3, count 0 2006.211.07:43:51.85#ibcon#*before return 0, iclass 3, count 0 2006.211.07:43:51.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:43:51.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:43:51.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:43:51.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:43:51.85$vc4f8/vb=6,3 2006.211.07:43:51.85#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:43:51.85#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:43:51.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:43:51.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:43:51.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:43:51.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:43:51.91#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:43:51.91#ibcon#first serial, iclass 5, count 2 2006.211.07:43:51.91#ibcon#enter sib2, iclass 5, count 2 2006.211.07:43:51.91#ibcon#flushed, iclass 5, count 2 2006.211.07:43:51.91#ibcon#about to write, iclass 5, count 2 2006.211.07:43:51.91#ibcon#wrote, iclass 5, count 2 2006.211.07:43:51.91#ibcon#about to read 3, iclass 5, count 2 2006.211.07:43:51.93#ibcon#read 3, iclass 5, count 2 2006.211.07:43:51.93#ibcon#about to read 4, iclass 5, count 2 2006.211.07:43:51.93#ibcon#read 4, iclass 5, count 2 2006.211.07:43:51.93#ibcon#about to read 5, iclass 5, count 2 2006.211.07:43:51.93#ibcon#read 5, iclass 5, count 2 2006.211.07:43:51.93#ibcon#about to read 6, iclass 5, count 2 2006.211.07:43:51.93#ibcon#read 6, iclass 5, count 2 2006.211.07:43:51.93#ibcon#end of sib2, iclass 5, count 2 2006.211.07:43:51.93#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:43:51.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:43:51.93#ibcon#[27=AT06-03\r\n] 2006.211.07:43:51.93#ibcon#*before write, iclass 5, count 2 2006.211.07:43:51.93#ibcon#enter sib2, iclass 5, count 2 2006.211.07:43:51.93#ibcon#flushed, iclass 5, count 2 2006.211.07:43:51.93#ibcon#about to write, iclass 5, count 2 2006.211.07:43:51.93#ibcon#wrote, iclass 5, count 2 2006.211.07:43:51.93#ibcon#about to read 3, iclass 5, count 2 2006.211.07:43:51.96#ibcon#read 3, iclass 5, count 2 2006.211.07:43:51.96#ibcon#about to read 4, iclass 5, count 2 2006.211.07:43:51.96#ibcon#read 4, iclass 5, count 2 2006.211.07:43:51.96#ibcon#about to read 5, iclass 5, count 2 2006.211.07:43:51.96#ibcon#read 5, iclass 5, count 2 2006.211.07:43:51.96#ibcon#about to read 6, iclass 5, count 2 2006.211.07:43:51.96#ibcon#read 6, iclass 5, count 2 2006.211.07:43:51.96#ibcon#end of sib2, iclass 5, count 2 2006.211.07:43:51.96#ibcon#*after write, iclass 5, count 2 2006.211.07:43:51.96#ibcon#*before return 0, iclass 5, count 2 2006.211.07:43:51.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:43:51.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:43:51.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:43:51.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:43:51.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:43:52.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:43:52.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:43:52.08#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:43:52.08#ibcon#first serial, iclass 5, count 0 2006.211.07:43:52.08#ibcon#enter sib2, iclass 5, count 0 2006.211.07:43:52.08#ibcon#flushed, iclass 5, count 0 2006.211.07:43:52.08#ibcon#about to write, iclass 5, count 0 2006.211.07:43:52.08#ibcon#wrote, iclass 5, count 0 2006.211.07:43:52.08#ibcon#about to read 3, iclass 5, count 0 2006.211.07:43:52.10#ibcon#read 3, iclass 5, count 0 2006.211.07:43:52.10#ibcon#about to read 4, iclass 5, count 0 2006.211.07:43:52.10#ibcon#read 4, iclass 5, count 0 2006.211.07:43:52.10#ibcon#about to read 5, iclass 5, count 0 2006.211.07:43:52.10#ibcon#read 5, iclass 5, count 0 2006.211.07:43:52.10#ibcon#about to read 6, iclass 5, count 0 2006.211.07:43:52.10#ibcon#read 6, iclass 5, count 0 2006.211.07:43:52.10#ibcon#end of sib2, iclass 5, count 0 2006.211.07:43:52.10#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:43:52.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:43:52.10#ibcon#[27=USB\r\n] 2006.211.07:43:52.10#ibcon#*before write, iclass 5, count 0 2006.211.07:43:52.10#ibcon#enter sib2, iclass 5, count 0 2006.211.07:43:52.10#ibcon#flushed, iclass 5, count 0 2006.211.07:43:52.10#ibcon#about to write, iclass 5, count 0 2006.211.07:43:52.10#ibcon#wrote, iclass 5, count 0 2006.211.07:43:52.10#ibcon#about to read 3, iclass 5, count 0 2006.211.07:43:52.13#ibcon#read 3, iclass 5, count 0 2006.211.07:43:52.13#ibcon#about to read 4, iclass 5, count 0 2006.211.07:43:52.13#ibcon#read 4, iclass 5, count 0 2006.211.07:43:52.13#ibcon#about to read 5, iclass 5, count 0 2006.211.07:43:52.13#ibcon#read 5, iclass 5, count 0 2006.211.07:43:52.13#ibcon#about to read 6, iclass 5, count 0 2006.211.07:43:52.13#ibcon#read 6, iclass 5, count 0 2006.211.07:43:52.13#ibcon#end of sib2, iclass 5, count 0 2006.211.07:43:52.13#ibcon#*after write, iclass 5, count 0 2006.211.07:43:52.13#ibcon#*before return 0, iclass 5, count 0 2006.211.07:43:52.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:43:52.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:43:52.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:43:52.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:43:52.13$vc4f8/vabw=wide 2006.211.07:43:52.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:43:52.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:43:52.13#ibcon#ireg 8 cls_cnt 0 2006.211.07:43:52.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:43:52.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:43:52.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:43:52.13#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:43:52.13#ibcon#first serial, iclass 7, count 0 2006.211.07:43:52.13#ibcon#enter sib2, iclass 7, count 0 2006.211.07:43:52.13#ibcon#flushed, iclass 7, count 0 2006.211.07:43:52.13#ibcon#about to write, iclass 7, count 0 2006.211.07:43:52.13#ibcon#wrote, iclass 7, count 0 2006.211.07:43:52.13#ibcon#about to read 3, iclass 7, count 0 2006.211.07:43:52.15#ibcon#read 3, iclass 7, count 0 2006.211.07:43:52.15#ibcon#about to read 4, iclass 7, count 0 2006.211.07:43:52.15#ibcon#read 4, iclass 7, count 0 2006.211.07:43:52.15#ibcon#about to read 5, iclass 7, count 0 2006.211.07:43:52.15#ibcon#read 5, iclass 7, count 0 2006.211.07:43:52.15#ibcon#about to read 6, iclass 7, count 0 2006.211.07:43:52.15#ibcon#read 6, iclass 7, count 0 2006.211.07:43:52.15#ibcon#end of sib2, iclass 7, count 0 2006.211.07:43:52.15#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:43:52.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:43:52.15#ibcon#[25=BW32\r\n] 2006.211.07:43:52.15#ibcon#*before write, iclass 7, count 0 2006.211.07:43:52.15#ibcon#enter sib2, iclass 7, count 0 2006.211.07:43:52.15#ibcon#flushed, iclass 7, count 0 2006.211.07:43:52.15#ibcon#about to write, iclass 7, count 0 2006.211.07:43:52.15#ibcon#wrote, iclass 7, count 0 2006.211.07:43:52.15#ibcon#about to read 3, iclass 7, count 0 2006.211.07:43:52.18#ibcon#read 3, iclass 7, count 0 2006.211.07:43:52.18#ibcon#about to read 4, iclass 7, count 0 2006.211.07:43:52.18#ibcon#read 4, iclass 7, count 0 2006.211.07:43:52.18#ibcon#about to read 5, iclass 7, count 0 2006.211.07:43:52.18#ibcon#read 5, iclass 7, count 0 2006.211.07:43:52.18#ibcon#about to read 6, iclass 7, count 0 2006.211.07:43:52.18#ibcon#read 6, iclass 7, count 0 2006.211.07:43:52.18#ibcon#end of sib2, iclass 7, count 0 2006.211.07:43:52.18#ibcon#*after write, iclass 7, count 0 2006.211.07:43:52.18#ibcon#*before return 0, iclass 7, count 0 2006.211.07:43:52.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:43:52.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:43:52.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:43:52.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:43:52.18$vc4f8/vbbw=wide 2006.211.07:43:52.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:43:52.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:43:52.18#ibcon#ireg 8 cls_cnt 0 2006.211.07:43:52.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:43:52.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:43:52.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:43:52.25#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:43:52.25#ibcon#first serial, iclass 11, count 0 2006.211.07:43:52.25#ibcon#enter sib2, iclass 11, count 0 2006.211.07:43:52.25#ibcon#flushed, iclass 11, count 0 2006.211.07:43:52.25#ibcon#about to write, iclass 11, count 0 2006.211.07:43:52.25#ibcon#wrote, iclass 11, count 0 2006.211.07:43:52.25#ibcon#about to read 3, iclass 11, count 0 2006.211.07:43:52.27#ibcon#read 3, iclass 11, count 0 2006.211.07:43:52.27#ibcon#about to read 4, iclass 11, count 0 2006.211.07:43:52.27#ibcon#read 4, iclass 11, count 0 2006.211.07:43:52.27#ibcon#about to read 5, iclass 11, count 0 2006.211.07:43:52.27#ibcon#read 5, iclass 11, count 0 2006.211.07:43:52.27#ibcon#about to read 6, iclass 11, count 0 2006.211.07:43:52.27#ibcon#read 6, iclass 11, count 0 2006.211.07:43:52.27#ibcon#end of sib2, iclass 11, count 0 2006.211.07:43:52.27#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:43:52.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:43:52.27#ibcon#[27=BW32\r\n] 2006.211.07:43:52.27#ibcon#*before write, iclass 11, count 0 2006.211.07:43:52.27#ibcon#enter sib2, iclass 11, count 0 2006.211.07:43:52.27#ibcon#flushed, iclass 11, count 0 2006.211.07:43:52.27#ibcon#about to write, iclass 11, count 0 2006.211.07:43:52.27#ibcon#wrote, iclass 11, count 0 2006.211.07:43:52.27#ibcon#about to read 3, iclass 11, count 0 2006.211.07:43:52.30#ibcon#read 3, iclass 11, count 0 2006.211.07:43:52.30#ibcon#about to read 4, iclass 11, count 0 2006.211.07:43:52.30#ibcon#read 4, iclass 11, count 0 2006.211.07:43:52.30#ibcon#about to read 5, iclass 11, count 0 2006.211.07:43:52.30#ibcon#read 5, iclass 11, count 0 2006.211.07:43:52.30#ibcon#about to read 6, iclass 11, count 0 2006.211.07:43:52.30#ibcon#read 6, iclass 11, count 0 2006.211.07:43:52.30#ibcon#end of sib2, iclass 11, count 0 2006.211.07:43:52.30#ibcon#*after write, iclass 11, count 0 2006.211.07:43:52.30#ibcon#*before return 0, iclass 11, count 0 2006.211.07:43:52.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:43:52.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:43:52.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:43:52.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:43:52.30$4f8m12a/ifd4f 2006.211.07:43:52.30$ifd4f/lo= 2006.211.07:43:52.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:43:52.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:43:52.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:43:52.30$ifd4f/patch= 2006.211.07:43:52.30$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:43:52.30$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:43:52.30$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:43:52.30$4f8m12a/"form=m,16.000,1:2 2006.211.07:43:52.30$4f8m12a/"tpicd 2006.211.07:43:52.30$4f8m12a/echo=off 2006.211.07:43:52.30$4f8m12a/xlog=off 2006.211.07:43:52.30:!2006.211.07:44:20 2006.211.07:43:59.14#trakl#Source acquired 2006.211.07:43:59.14#flagr#flagr/antenna,acquired 2006.211.07:44:20.00:preob 2006.211.07:44:21.14/onsource/TRACKING 2006.211.07:44:21.14:!2006.211.07:44:30 2006.211.07:44:30.00:data_valid=on 2006.211.07:44:30.00:midob 2006.211.07:44:30.14/onsource/TRACKING 2006.211.07:44:30.14/wx/24.94,1010.1,76 2006.211.07:44:30.23/cable/+6.4388E-03 2006.211.07:44:31.32/va/01,08,usb,yes,28,30 2006.211.07:44:31.32/va/02,07,usb,yes,29,30 2006.211.07:44:31.32/va/03,06,usb,yes,30,30 2006.211.07:44:31.32/va/04,07,usb,yes,29,32 2006.211.07:44:31.32/va/05,07,usb,yes,32,34 2006.211.07:44:31.32/va/06,06,usb,yes,31,31 2006.211.07:44:31.32/va/07,06,usb,yes,32,31 2006.211.07:44:31.32/va/08,07,usb,yes,30,29 2006.211.07:44:31.55/valo/01,532.99,yes,locked 2006.211.07:44:31.55/valo/02,572.99,yes,locked 2006.211.07:44:31.55/valo/03,672.99,yes,locked 2006.211.07:44:31.55/valo/04,832.99,yes,locked 2006.211.07:44:31.55/valo/05,652.99,yes,locked 2006.211.07:44:31.55/valo/06,772.99,yes,locked 2006.211.07:44:31.55/valo/07,832.99,yes,locked 2006.211.07:44:31.55/valo/08,852.99,yes,locked 2006.211.07:44:32.64/vb/01,04,usb,yes,29,27 2006.211.07:44:32.64/vb/02,04,usb,yes,31,32 2006.211.07:44:32.64/vb/03,03,usb,yes,33,39 2006.211.07:44:32.64/vb/04,03,usb,yes,34,34 2006.211.07:44:32.64/vb/05,03,usb,yes,33,37 2006.211.07:44:32.64/vb/06,03,usb,yes,33,36 2006.211.07:44:32.64/vb/07,04,usb,yes,29,29 2006.211.07:44:32.64/vb/08,03,usb,yes,33,37 2006.211.07:44:32.88/vblo/01,632.99,yes,locked 2006.211.07:44:32.88/vblo/02,640.99,yes,locked 2006.211.07:44:32.88/vblo/03,656.99,yes,locked 2006.211.07:44:32.88/vblo/04,712.99,yes,locked 2006.211.07:44:32.88/vblo/05,744.99,yes,locked 2006.211.07:44:32.88/vblo/06,752.99,yes,locked 2006.211.07:44:32.88/vblo/07,734.99,yes,locked 2006.211.07:44:32.88/vblo/08,744.99,yes,locked 2006.211.07:44:33.03/vabw/8 2006.211.07:44:33.18/vbbw/8 2006.211.07:44:33.27/xfe/off,on,15.2 2006.211.07:44:33.64/ifatt/23,28,28,28 2006.211.07:44:34.08/fmout-gps/S +4.49E-07 2006.211.07:44:34.12:!2006.211.07:45:30 2006.211.07:45:30.00:data_valid=off 2006.211.07:45:30.00:postob 2006.211.07:45:30.15/cable/+6.4379E-03 2006.211.07:45:30.15/wx/24.94,1010.1,77 2006.211.07:45:31.07/fmout-gps/S +4.47E-07 2006.211.07:45:31.07:scan_name=211-0746,k06211,100 2006.211.07:45:31.07:source=1004+141,100741.50,135629.6,2000.0,ccw 2006.211.07:45:31.14#flagr#flagr/antenna,new-source 2006.211.07:45:32.14:checkk5 2006.211.07:45:32.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:45:32.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:45:33.18/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:45:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:45:33.84/chk_obsdata//k5ts1/T2110744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:45:34.18/chk_obsdata//k5ts2/T2110744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:45:34.51/chk_obsdata//k5ts3/T2110744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:45:34.84/chk_obsdata//k5ts4/T2110744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:45:35.50/k5log//k5ts1_log_newline 2006.211.07:45:36.16/k5log//k5ts2_log_newline 2006.211.07:45:36.83/k5log//k5ts3_log_newline 2006.211.07:45:37.50/k5log//k5ts4_log_newline 2006.211.07:45:37.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:45:37.52:4f8m12a=1 2006.211.07:45:37.52$4f8m12a/echo=on 2006.211.07:45:37.52$4f8m12a/pcalon 2006.211.07:45:37.52$pcalon/"no phase cal control is implemented here 2006.211.07:45:37.52$4f8m12a/"tpicd=stop 2006.211.07:45:37.52$4f8m12a/vc4f8 2006.211.07:45:37.52$vc4f8/valo=1,532.99 2006.211.07:45:37.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:45:37.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:45:37.52#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:37.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:37.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:37.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:37.52#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:45:37.52#ibcon#first serial, iclass 18, count 0 2006.211.07:45:37.52#ibcon#enter sib2, iclass 18, count 0 2006.211.07:45:37.52#ibcon#flushed, iclass 18, count 0 2006.211.07:45:37.52#ibcon#about to write, iclass 18, count 0 2006.211.07:45:37.52#ibcon#wrote, iclass 18, count 0 2006.211.07:45:37.52#ibcon#about to read 3, iclass 18, count 0 2006.211.07:45:37.54#ibcon#read 3, iclass 18, count 0 2006.211.07:45:37.54#ibcon#about to read 4, iclass 18, count 0 2006.211.07:45:37.54#ibcon#read 4, iclass 18, count 0 2006.211.07:45:37.54#ibcon#about to read 5, iclass 18, count 0 2006.211.07:45:37.54#ibcon#read 5, iclass 18, count 0 2006.211.07:45:37.54#ibcon#about to read 6, iclass 18, count 0 2006.211.07:45:37.54#ibcon#read 6, iclass 18, count 0 2006.211.07:45:37.54#ibcon#end of sib2, iclass 18, count 0 2006.211.07:45:37.54#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:45:37.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:45:37.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:45:37.54#ibcon#*before write, iclass 18, count 0 2006.211.07:45:37.54#ibcon#enter sib2, iclass 18, count 0 2006.211.07:45:37.54#ibcon#flushed, iclass 18, count 0 2006.211.07:45:37.54#ibcon#about to write, iclass 18, count 0 2006.211.07:45:37.54#ibcon#wrote, iclass 18, count 0 2006.211.07:45:37.54#ibcon#about to read 3, iclass 18, count 0 2006.211.07:45:37.59#ibcon#read 3, iclass 18, count 0 2006.211.07:45:37.59#ibcon#about to read 4, iclass 18, count 0 2006.211.07:45:37.59#ibcon#read 4, iclass 18, count 0 2006.211.07:45:37.59#ibcon#about to read 5, iclass 18, count 0 2006.211.07:45:37.59#ibcon#read 5, iclass 18, count 0 2006.211.07:45:37.59#ibcon#about to read 6, iclass 18, count 0 2006.211.07:45:37.59#ibcon#read 6, iclass 18, count 0 2006.211.07:45:37.59#ibcon#end of sib2, iclass 18, count 0 2006.211.07:45:37.59#ibcon#*after write, iclass 18, count 0 2006.211.07:45:37.59#ibcon#*before return 0, iclass 18, count 0 2006.211.07:45:37.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:37.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:37.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:45:37.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:45:37.59$vc4f8/va=1,8 2006.211.07:45:37.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:45:37.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:45:37.59#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:37.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:37.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:37.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:37.59#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:45:37.59#ibcon#first serial, iclass 20, count 2 2006.211.07:45:37.59#ibcon#enter sib2, iclass 20, count 2 2006.211.07:45:37.59#ibcon#flushed, iclass 20, count 2 2006.211.07:45:37.59#ibcon#about to write, iclass 20, count 2 2006.211.07:45:37.59#ibcon#wrote, iclass 20, count 2 2006.211.07:45:37.59#ibcon#about to read 3, iclass 20, count 2 2006.211.07:45:37.61#ibcon#read 3, iclass 20, count 2 2006.211.07:45:37.61#ibcon#about to read 4, iclass 20, count 2 2006.211.07:45:37.61#ibcon#read 4, iclass 20, count 2 2006.211.07:45:37.61#ibcon#about to read 5, iclass 20, count 2 2006.211.07:45:37.61#ibcon#read 5, iclass 20, count 2 2006.211.07:45:37.61#ibcon#about to read 6, iclass 20, count 2 2006.211.07:45:37.61#ibcon#read 6, iclass 20, count 2 2006.211.07:45:37.61#ibcon#end of sib2, iclass 20, count 2 2006.211.07:45:37.61#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:45:37.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:45:37.61#ibcon#[25=AT01-08\r\n] 2006.211.07:45:37.61#ibcon#*before write, iclass 20, count 2 2006.211.07:45:37.61#ibcon#enter sib2, iclass 20, count 2 2006.211.07:45:37.61#ibcon#flushed, iclass 20, count 2 2006.211.07:45:37.61#ibcon#about to write, iclass 20, count 2 2006.211.07:45:37.61#ibcon#wrote, iclass 20, count 2 2006.211.07:45:37.61#ibcon#about to read 3, iclass 20, count 2 2006.211.07:45:37.64#ibcon#read 3, iclass 20, count 2 2006.211.07:45:37.64#ibcon#about to read 4, iclass 20, count 2 2006.211.07:45:37.64#ibcon#read 4, iclass 20, count 2 2006.211.07:45:37.64#ibcon#about to read 5, iclass 20, count 2 2006.211.07:45:37.64#ibcon#read 5, iclass 20, count 2 2006.211.07:45:37.64#ibcon#about to read 6, iclass 20, count 2 2006.211.07:45:37.64#ibcon#read 6, iclass 20, count 2 2006.211.07:45:37.64#ibcon#end of sib2, iclass 20, count 2 2006.211.07:45:37.64#ibcon#*after write, iclass 20, count 2 2006.211.07:45:37.64#ibcon#*before return 0, iclass 20, count 2 2006.211.07:45:37.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:37.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:37.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:45:37.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:37.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:37.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:37.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:37.76#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:45:37.76#ibcon#first serial, iclass 20, count 0 2006.211.07:45:37.76#ibcon#enter sib2, iclass 20, count 0 2006.211.07:45:37.76#ibcon#flushed, iclass 20, count 0 2006.211.07:45:37.76#ibcon#about to write, iclass 20, count 0 2006.211.07:45:37.76#ibcon#wrote, iclass 20, count 0 2006.211.07:45:37.76#ibcon#about to read 3, iclass 20, count 0 2006.211.07:45:37.78#ibcon#read 3, iclass 20, count 0 2006.211.07:45:37.78#ibcon#about to read 4, iclass 20, count 0 2006.211.07:45:37.78#ibcon#read 4, iclass 20, count 0 2006.211.07:45:37.78#ibcon#about to read 5, iclass 20, count 0 2006.211.07:45:37.78#ibcon#read 5, iclass 20, count 0 2006.211.07:45:37.78#ibcon#about to read 6, iclass 20, count 0 2006.211.07:45:37.78#ibcon#read 6, iclass 20, count 0 2006.211.07:45:37.78#ibcon#end of sib2, iclass 20, count 0 2006.211.07:45:37.78#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:45:37.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:45:37.78#ibcon#[25=USB\r\n] 2006.211.07:45:37.78#ibcon#*before write, iclass 20, count 0 2006.211.07:45:37.78#ibcon#enter sib2, iclass 20, count 0 2006.211.07:45:37.78#ibcon#flushed, iclass 20, count 0 2006.211.07:45:37.78#ibcon#about to write, iclass 20, count 0 2006.211.07:45:37.78#ibcon#wrote, iclass 20, count 0 2006.211.07:45:37.78#ibcon#about to read 3, iclass 20, count 0 2006.211.07:45:37.81#ibcon#read 3, iclass 20, count 0 2006.211.07:45:37.81#ibcon#about to read 4, iclass 20, count 0 2006.211.07:45:37.81#ibcon#read 4, iclass 20, count 0 2006.211.07:45:37.81#ibcon#about to read 5, iclass 20, count 0 2006.211.07:45:37.81#ibcon#read 5, iclass 20, count 0 2006.211.07:45:37.81#ibcon#about to read 6, iclass 20, count 0 2006.211.07:45:37.81#ibcon#read 6, iclass 20, count 0 2006.211.07:45:37.81#ibcon#end of sib2, iclass 20, count 0 2006.211.07:45:37.81#ibcon#*after write, iclass 20, count 0 2006.211.07:45:37.81#ibcon#*before return 0, iclass 20, count 0 2006.211.07:45:37.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:37.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:37.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:45:37.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:45:37.81$vc4f8/valo=2,572.99 2006.211.07:45:37.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:45:37.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:45:37.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:37.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:37.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:37.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:37.81#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:45:37.81#ibcon#first serial, iclass 22, count 0 2006.211.07:45:37.81#ibcon#enter sib2, iclass 22, count 0 2006.211.07:45:37.81#ibcon#flushed, iclass 22, count 0 2006.211.07:45:37.81#ibcon#about to write, iclass 22, count 0 2006.211.07:45:37.81#ibcon#wrote, iclass 22, count 0 2006.211.07:45:37.81#ibcon#about to read 3, iclass 22, count 0 2006.211.07:45:37.83#ibcon#read 3, iclass 22, count 0 2006.211.07:45:37.83#ibcon#about to read 4, iclass 22, count 0 2006.211.07:45:37.83#ibcon#read 4, iclass 22, count 0 2006.211.07:45:37.83#ibcon#about to read 5, iclass 22, count 0 2006.211.07:45:37.83#ibcon#read 5, iclass 22, count 0 2006.211.07:45:37.83#ibcon#about to read 6, iclass 22, count 0 2006.211.07:45:37.83#ibcon#read 6, iclass 22, count 0 2006.211.07:45:37.83#ibcon#end of sib2, iclass 22, count 0 2006.211.07:45:37.83#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:45:37.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:45:37.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:45:37.83#ibcon#*before write, iclass 22, count 0 2006.211.07:45:37.83#ibcon#enter sib2, iclass 22, count 0 2006.211.07:45:37.83#ibcon#flushed, iclass 22, count 0 2006.211.07:45:37.83#ibcon#about to write, iclass 22, count 0 2006.211.07:45:37.83#ibcon#wrote, iclass 22, count 0 2006.211.07:45:37.83#ibcon#about to read 3, iclass 22, count 0 2006.211.07:45:37.87#ibcon#read 3, iclass 22, count 0 2006.211.07:45:37.87#ibcon#about to read 4, iclass 22, count 0 2006.211.07:45:37.87#ibcon#read 4, iclass 22, count 0 2006.211.07:45:37.87#ibcon#about to read 5, iclass 22, count 0 2006.211.07:45:37.87#ibcon#read 5, iclass 22, count 0 2006.211.07:45:37.87#ibcon#about to read 6, iclass 22, count 0 2006.211.07:45:37.87#ibcon#read 6, iclass 22, count 0 2006.211.07:45:37.87#ibcon#end of sib2, iclass 22, count 0 2006.211.07:45:37.87#ibcon#*after write, iclass 22, count 0 2006.211.07:45:37.87#ibcon#*before return 0, iclass 22, count 0 2006.211.07:45:37.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:37.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:37.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:45:37.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:45:37.87$vc4f8/va=2,7 2006.211.07:45:37.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:45:37.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:45:37.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:37.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:37.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:37.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:37.93#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:45:37.93#ibcon#first serial, iclass 24, count 2 2006.211.07:45:37.93#ibcon#enter sib2, iclass 24, count 2 2006.211.07:45:37.93#ibcon#flushed, iclass 24, count 2 2006.211.07:45:37.93#ibcon#about to write, iclass 24, count 2 2006.211.07:45:37.93#ibcon#wrote, iclass 24, count 2 2006.211.07:45:37.93#ibcon#about to read 3, iclass 24, count 2 2006.211.07:45:37.95#ibcon#read 3, iclass 24, count 2 2006.211.07:45:37.95#ibcon#about to read 4, iclass 24, count 2 2006.211.07:45:37.95#ibcon#read 4, iclass 24, count 2 2006.211.07:45:37.95#ibcon#about to read 5, iclass 24, count 2 2006.211.07:45:37.95#ibcon#read 5, iclass 24, count 2 2006.211.07:45:37.95#ibcon#about to read 6, iclass 24, count 2 2006.211.07:45:37.95#ibcon#read 6, iclass 24, count 2 2006.211.07:45:37.95#ibcon#end of sib2, iclass 24, count 2 2006.211.07:45:37.95#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:45:37.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:45:37.95#ibcon#[25=AT02-07\r\n] 2006.211.07:45:37.95#ibcon#*before write, iclass 24, count 2 2006.211.07:45:37.95#ibcon#enter sib2, iclass 24, count 2 2006.211.07:45:37.95#ibcon#flushed, iclass 24, count 2 2006.211.07:45:37.95#ibcon#about to write, iclass 24, count 2 2006.211.07:45:37.95#ibcon#wrote, iclass 24, count 2 2006.211.07:45:37.95#ibcon#about to read 3, iclass 24, count 2 2006.211.07:45:37.98#ibcon#read 3, iclass 24, count 2 2006.211.07:45:37.98#ibcon#about to read 4, iclass 24, count 2 2006.211.07:45:37.98#ibcon#read 4, iclass 24, count 2 2006.211.07:45:37.98#ibcon#about to read 5, iclass 24, count 2 2006.211.07:45:37.98#ibcon#read 5, iclass 24, count 2 2006.211.07:45:37.98#ibcon#about to read 6, iclass 24, count 2 2006.211.07:45:37.98#ibcon#read 6, iclass 24, count 2 2006.211.07:45:37.98#ibcon#end of sib2, iclass 24, count 2 2006.211.07:45:37.98#ibcon#*after write, iclass 24, count 2 2006.211.07:45:37.98#ibcon#*before return 0, iclass 24, count 2 2006.211.07:45:37.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:37.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:37.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:45:37.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:37.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:38.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:38.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:38.10#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:45:38.10#ibcon#first serial, iclass 24, count 0 2006.211.07:45:38.10#ibcon#enter sib2, iclass 24, count 0 2006.211.07:45:38.10#ibcon#flushed, iclass 24, count 0 2006.211.07:45:38.10#ibcon#about to write, iclass 24, count 0 2006.211.07:45:38.10#ibcon#wrote, iclass 24, count 0 2006.211.07:45:38.10#ibcon#about to read 3, iclass 24, count 0 2006.211.07:45:38.12#ibcon#read 3, iclass 24, count 0 2006.211.07:45:38.12#ibcon#about to read 4, iclass 24, count 0 2006.211.07:45:38.12#ibcon#read 4, iclass 24, count 0 2006.211.07:45:38.12#ibcon#about to read 5, iclass 24, count 0 2006.211.07:45:38.12#ibcon#read 5, iclass 24, count 0 2006.211.07:45:38.12#ibcon#about to read 6, iclass 24, count 0 2006.211.07:45:38.12#ibcon#read 6, iclass 24, count 0 2006.211.07:45:38.12#ibcon#end of sib2, iclass 24, count 0 2006.211.07:45:38.12#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:45:38.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:45:38.12#ibcon#[25=USB\r\n] 2006.211.07:45:38.12#ibcon#*before write, iclass 24, count 0 2006.211.07:45:38.12#ibcon#enter sib2, iclass 24, count 0 2006.211.07:45:38.12#ibcon#flushed, iclass 24, count 0 2006.211.07:45:38.12#ibcon#about to write, iclass 24, count 0 2006.211.07:45:38.12#ibcon#wrote, iclass 24, count 0 2006.211.07:45:38.12#ibcon#about to read 3, iclass 24, count 0 2006.211.07:45:38.15#ibcon#read 3, iclass 24, count 0 2006.211.07:45:38.15#ibcon#about to read 4, iclass 24, count 0 2006.211.07:45:38.15#ibcon#read 4, iclass 24, count 0 2006.211.07:45:38.15#ibcon#about to read 5, iclass 24, count 0 2006.211.07:45:38.15#ibcon#read 5, iclass 24, count 0 2006.211.07:45:38.15#ibcon#about to read 6, iclass 24, count 0 2006.211.07:45:38.15#ibcon#read 6, iclass 24, count 0 2006.211.07:45:38.15#ibcon#end of sib2, iclass 24, count 0 2006.211.07:45:38.15#ibcon#*after write, iclass 24, count 0 2006.211.07:45:38.15#ibcon#*before return 0, iclass 24, count 0 2006.211.07:45:38.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:38.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:38.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:45:38.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:45:38.15$vc4f8/valo=3,672.99 2006.211.07:45:38.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:45:38.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:45:38.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:38.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:45:38.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:45:38.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:45:38.15#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:45:38.15#ibcon#first serial, iclass 26, count 0 2006.211.07:45:38.15#ibcon#enter sib2, iclass 26, count 0 2006.211.07:45:38.15#ibcon#flushed, iclass 26, count 0 2006.211.07:45:38.15#ibcon#about to write, iclass 26, count 0 2006.211.07:45:38.15#ibcon#wrote, iclass 26, count 0 2006.211.07:45:38.15#ibcon#about to read 3, iclass 26, count 0 2006.211.07:45:38.17#ibcon#read 3, iclass 26, count 0 2006.211.07:45:38.17#ibcon#about to read 4, iclass 26, count 0 2006.211.07:45:38.17#ibcon#read 4, iclass 26, count 0 2006.211.07:45:38.17#ibcon#about to read 5, iclass 26, count 0 2006.211.07:45:38.17#ibcon#read 5, iclass 26, count 0 2006.211.07:45:38.17#ibcon#about to read 6, iclass 26, count 0 2006.211.07:45:38.17#ibcon#read 6, iclass 26, count 0 2006.211.07:45:38.17#ibcon#end of sib2, iclass 26, count 0 2006.211.07:45:38.17#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:45:38.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:45:38.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:45:38.17#ibcon#*before write, iclass 26, count 0 2006.211.07:45:38.17#ibcon#enter sib2, iclass 26, count 0 2006.211.07:45:38.17#ibcon#flushed, iclass 26, count 0 2006.211.07:45:38.17#ibcon#about to write, iclass 26, count 0 2006.211.07:45:38.17#ibcon#wrote, iclass 26, count 0 2006.211.07:45:38.17#ibcon#about to read 3, iclass 26, count 0 2006.211.07:45:38.21#ibcon#read 3, iclass 26, count 0 2006.211.07:45:38.21#ibcon#about to read 4, iclass 26, count 0 2006.211.07:45:38.21#ibcon#read 4, iclass 26, count 0 2006.211.07:45:38.21#ibcon#about to read 5, iclass 26, count 0 2006.211.07:45:38.21#ibcon#read 5, iclass 26, count 0 2006.211.07:45:38.21#ibcon#about to read 6, iclass 26, count 0 2006.211.07:45:38.21#ibcon#read 6, iclass 26, count 0 2006.211.07:45:38.21#ibcon#end of sib2, iclass 26, count 0 2006.211.07:45:38.21#ibcon#*after write, iclass 26, count 0 2006.211.07:45:38.21#ibcon#*before return 0, iclass 26, count 0 2006.211.07:45:38.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:45:38.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:45:38.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:45:38.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:45:38.21$vc4f8/va=3,6 2006.211.07:45:38.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.07:45:38.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.07:45:38.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:38.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:45:38.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:45:38.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:45:38.27#ibcon#enter wrdev, iclass 28, count 2 2006.211.07:45:38.27#ibcon#first serial, iclass 28, count 2 2006.211.07:45:38.27#ibcon#enter sib2, iclass 28, count 2 2006.211.07:45:38.27#ibcon#flushed, iclass 28, count 2 2006.211.07:45:38.27#ibcon#about to write, iclass 28, count 2 2006.211.07:45:38.27#ibcon#wrote, iclass 28, count 2 2006.211.07:45:38.27#ibcon#about to read 3, iclass 28, count 2 2006.211.07:45:38.29#ibcon#read 3, iclass 28, count 2 2006.211.07:45:38.29#ibcon#about to read 4, iclass 28, count 2 2006.211.07:45:38.29#ibcon#read 4, iclass 28, count 2 2006.211.07:45:38.29#ibcon#about to read 5, iclass 28, count 2 2006.211.07:45:38.29#ibcon#read 5, iclass 28, count 2 2006.211.07:45:38.29#ibcon#about to read 6, iclass 28, count 2 2006.211.07:45:38.29#ibcon#read 6, iclass 28, count 2 2006.211.07:45:38.29#ibcon#end of sib2, iclass 28, count 2 2006.211.07:45:38.29#ibcon#*mode == 0, iclass 28, count 2 2006.211.07:45:38.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.07:45:38.29#ibcon#[25=AT03-06\r\n] 2006.211.07:45:38.29#ibcon#*before write, iclass 28, count 2 2006.211.07:45:38.29#ibcon#enter sib2, iclass 28, count 2 2006.211.07:45:38.29#ibcon#flushed, iclass 28, count 2 2006.211.07:45:38.29#ibcon#about to write, iclass 28, count 2 2006.211.07:45:38.29#ibcon#wrote, iclass 28, count 2 2006.211.07:45:38.29#ibcon#about to read 3, iclass 28, count 2 2006.211.07:45:38.32#ibcon#read 3, iclass 28, count 2 2006.211.07:45:38.32#ibcon#about to read 4, iclass 28, count 2 2006.211.07:45:38.32#ibcon#read 4, iclass 28, count 2 2006.211.07:45:38.32#ibcon#about to read 5, iclass 28, count 2 2006.211.07:45:38.32#ibcon#read 5, iclass 28, count 2 2006.211.07:45:38.32#ibcon#about to read 6, iclass 28, count 2 2006.211.07:45:38.32#ibcon#read 6, iclass 28, count 2 2006.211.07:45:38.32#ibcon#end of sib2, iclass 28, count 2 2006.211.07:45:38.32#ibcon#*after write, iclass 28, count 2 2006.211.07:45:38.32#ibcon#*before return 0, iclass 28, count 2 2006.211.07:45:38.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:45:38.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:45:38.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.07:45:38.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:38.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:45:38.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:45:38.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:45:38.44#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:45:38.44#ibcon#first serial, iclass 28, count 0 2006.211.07:45:38.44#ibcon#enter sib2, iclass 28, count 0 2006.211.07:45:38.44#ibcon#flushed, iclass 28, count 0 2006.211.07:45:38.44#ibcon#about to write, iclass 28, count 0 2006.211.07:45:38.44#ibcon#wrote, iclass 28, count 0 2006.211.07:45:38.44#ibcon#about to read 3, iclass 28, count 0 2006.211.07:45:38.46#ibcon#read 3, iclass 28, count 0 2006.211.07:45:38.46#ibcon#about to read 4, iclass 28, count 0 2006.211.07:45:38.46#ibcon#read 4, iclass 28, count 0 2006.211.07:45:38.46#ibcon#about to read 5, iclass 28, count 0 2006.211.07:45:38.46#ibcon#read 5, iclass 28, count 0 2006.211.07:45:38.46#ibcon#about to read 6, iclass 28, count 0 2006.211.07:45:38.46#ibcon#read 6, iclass 28, count 0 2006.211.07:45:38.46#ibcon#end of sib2, iclass 28, count 0 2006.211.07:45:38.46#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:45:38.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:45:38.46#ibcon#[25=USB\r\n] 2006.211.07:45:38.46#ibcon#*before write, iclass 28, count 0 2006.211.07:45:38.46#ibcon#enter sib2, iclass 28, count 0 2006.211.07:45:38.46#ibcon#flushed, iclass 28, count 0 2006.211.07:45:38.46#ibcon#about to write, iclass 28, count 0 2006.211.07:45:38.46#ibcon#wrote, iclass 28, count 0 2006.211.07:45:38.46#ibcon#about to read 3, iclass 28, count 0 2006.211.07:45:38.49#ibcon#read 3, iclass 28, count 0 2006.211.07:45:38.49#ibcon#about to read 4, iclass 28, count 0 2006.211.07:45:38.49#ibcon#read 4, iclass 28, count 0 2006.211.07:45:38.49#ibcon#about to read 5, iclass 28, count 0 2006.211.07:45:38.49#ibcon#read 5, iclass 28, count 0 2006.211.07:45:38.49#ibcon#about to read 6, iclass 28, count 0 2006.211.07:45:38.49#ibcon#read 6, iclass 28, count 0 2006.211.07:45:38.49#ibcon#end of sib2, iclass 28, count 0 2006.211.07:45:38.49#ibcon#*after write, iclass 28, count 0 2006.211.07:45:38.49#ibcon#*before return 0, iclass 28, count 0 2006.211.07:45:38.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:45:38.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:45:38.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:45:38.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:45:38.49$vc4f8/valo=4,832.99 2006.211.07:45:38.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.07:45:38.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.07:45:38.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:38.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:38.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:38.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:38.49#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:45:38.49#ibcon#first serial, iclass 30, count 0 2006.211.07:45:38.49#ibcon#enter sib2, iclass 30, count 0 2006.211.07:45:38.49#ibcon#flushed, iclass 30, count 0 2006.211.07:45:38.49#ibcon#about to write, iclass 30, count 0 2006.211.07:45:38.49#ibcon#wrote, iclass 30, count 0 2006.211.07:45:38.49#ibcon#about to read 3, iclass 30, count 0 2006.211.07:45:38.51#ibcon#read 3, iclass 30, count 0 2006.211.07:45:38.51#ibcon#about to read 4, iclass 30, count 0 2006.211.07:45:38.51#ibcon#read 4, iclass 30, count 0 2006.211.07:45:38.51#ibcon#about to read 5, iclass 30, count 0 2006.211.07:45:38.51#ibcon#read 5, iclass 30, count 0 2006.211.07:45:38.51#ibcon#about to read 6, iclass 30, count 0 2006.211.07:45:38.51#ibcon#read 6, iclass 30, count 0 2006.211.07:45:38.51#ibcon#end of sib2, iclass 30, count 0 2006.211.07:45:38.51#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:45:38.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:45:38.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:45:38.51#ibcon#*before write, iclass 30, count 0 2006.211.07:45:38.51#ibcon#enter sib2, iclass 30, count 0 2006.211.07:45:38.51#ibcon#flushed, iclass 30, count 0 2006.211.07:45:38.51#ibcon#about to write, iclass 30, count 0 2006.211.07:45:38.51#ibcon#wrote, iclass 30, count 0 2006.211.07:45:38.51#ibcon#about to read 3, iclass 30, count 0 2006.211.07:45:38.55#ibcon#read 3, iclass 30, count 0 2006.211.07:45:38.55#ibcon#about to read 4, iclass 30, count 0 2006.211.07:45:38.55#ibcon#read 4, iclass 30, count 0 2006.211.07:45:38.55#ibcon#about to read 5, iclass 30, count 0 2006.211.07:45:38.55#ibcon#read 5, iclass 30, count 0 2006.211.07:45:38.55#ibcon#about to read 6, iclass 30, count 0 2006.211.07:45:38.55#ibcon#read 6, iclass 30, count 0 2006.211.07:45:38.55#ibcon#end of sib2, iclass 30, count 0 2006.211.07:45:38.55#ibcon#*after write, iclass 30, count 0 2006.211.07:45:38.55#ibcon#*before return 0, iclass 30, count 0 2006.211.07:45:38.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:38.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:38.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:45:38.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:45:38.55$vc4f8/va=4,7 2006.211.07:45:38.55#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.07:45:38.55#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.07:45:38.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:38.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:38.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:38.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:38.61#ibcon#enter wrdev, iclass 32, count 2 2006.211.07:45:38.61#ibcon#first serial, iclass 32, count 2 2006.211.07:45:38.61#ibcon#enter sib2, iclass 32, count 2 2006.211.07:45:38.61#ibcon#flushed, iclass 32, count 2 2006.211.07:45:38.61#ibcon#about to write, iclass 32, count 2 2006.211.07:45:38.61#ibcon#wrote, iclass 32, count 2 2006.211.07:45:38.61#ibcon#about to read 3, iclass 32, count 2 2006.211.07:45:38.63#ibcon#read 3, iclass 32, count 2 2006.211.07:45:38.63#ibcon#about to read 4, iclass 32, count 2 2006.211.07:45:38.63#ibcon#read 4, iclass 32, count 2 2006.211.07:45:38.63#ibcon#about to read 5, iclass 32, count 2 2006.211.07:45:38.63#ibcon#read 5, iclass 32, count 2 2006.211.07:45:38.63#ibcon#about to read 6, iclass 32, count 2 2006.211.07:45:38.63#ibcon#read 6, iclass 32, count 2 2006.211.07:45:38.63#ibcon#end of sib2, iclass 32, count 2 2006.211.07:45:38.63#ibcon#*mode == 0, iclass 32, count 2 2006.211.07:45:38.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.07:45:38.63#ibcon#[25=AT04-07\r\n] 2006.211.07:45:38.63#ibcon#*before write, iclass 32, count 2 2006.211.07:45:38.63#ibcon#enter sib2, iclass 32, count 2 2006.211.07:45:38.63#ibcon#flushed, iclass 32, count 2 2006.211.07:45:38.63#ibcon#about to write, iclass 32, count 2 2006.211.07:45:38.63#ibcon#wrote, iclass 32, count 2 2006.211.07:45:38.63#ibcon#about to read 3, iclass 32, count 2 2006.211.07:45:38.66#ibcon#read 3, iclass 32, count 2 2006.211.07:45:38.66#ibcon#about to read 4, iclass 32, count 2 2006.211.07:45:38.66#ibcon#read 4, iclass 32, count 2 2006.211.07:45:38.66#ibcon#about to read 5, iclass 32, count 2 2006.211.07:45:38.66#ibcon#read 5, iclass 32, count 2 2006.211.07:45:38.66#ibcon#about to read 6, iclass 32, count 2 2006.211.07:45:38.66#ibcon#read 6, iclass 32, count 2 2006.211.07:45:38.66#ibcon#end of sib2, iclass 32, count 2 2006.211.07:45:38.66#ibcon#*after write, iclass 32, count 2 2006.211.07:45:38.66#ibcon#*before return 0, iclass 32, count 2 2006.211.07:45:38.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:38.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:38.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.07:45:38.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:38.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:38.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:38.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:38.78#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:45:38.78#ibcon#first serial, iclass 32, count 0 2006.211.07:45:38.78#ibcon#enter sib2, iclass 32, count 0 2006.211.07:45:38.78#ibcon#flushed, iclass 32, count 0 2006.211.07:45:38.78#ibcon#about to write, iclass 32, count 0 2006.211.07:45:38.78#ibcon#wrote, iclass 32, count 0 2006.211.07:45:38.78#ibcon#about to read 3, iclass 32, count 0 2006.211.07:45:38.80#ibcon#read 3, iclass 32, count 0 2006.211.07:45:38.80#ibcon#about to read 4, iclass 32, count 0 2006.211.07:45:38.80#ibcon#read 4, iclass 32, count 0 2006.211.07:45:38.80#ibcon#about to read 5, iclass 32, count 0 2006.211.07:45:38.80#ibcon#read 5, iclass 32, count 0 2006.211.07:45:38.80#ibcon#about to read 6, iclass 32, count 0 2006.211.07:45:38.80#ibcon#read 6, iclass 32, count 0 2006.211.07:45:38.80#ibcon#end of sib2, iclass 32, count 0 2006.211.07:45:38.80#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:45:38.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:45:38.80#ibcon#[25=USB\r\n] 2006.211.07:45:38.80#ibcon#*before write, iclass 32, count 0 2006.211.07:45:38.80#ibcon#enter sib2, iclass 32, count 0 2006.211.07:45:38.80#ibcon#flushed, iclass 32, count 0 2006.211.07:45:38.80#ibcon#about to write, iclass 32, count 0 2006.211.07:45:38.80#ibcon#wrote, iclass 32, count 0 2006.211.07:45:38.80#ibcon#about to read 3, iclass 32, count 0 2006.211.07:45:38.83#ibcon#read 3, iclass 32, count 0 2006.211.07:45:38.83#ibcon#about to read 4, iclass 32, count 0 2006.211.07:45:38.83#ibcon#read 4, iclass 32, count 0 2006.211.07:45:38.83#ibcon#about to read 5, iclass 32, count 0 2006.211.07:45:38.83#ibcon#read 5, iclass 32, count 0 2006.211.07:45:38.83#ibcon#about to read 6, iclass 32, count 0 2006.211.07:45:38.83#ibcon#read 6, iclass 32, count 0 2006.211.07:45:38.83#ibcon#end of sib2, iclass 32, count 0 2006.211.07:45:38.83#ibcon#*after write, iclass 32, count 0 2006.211.07:45:38.83#ibcon#*before return 0, iclass 32, count 0 2006.211.07:45:38.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:38.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:38.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:45:38.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:45:38.83$vc4f8/valo=5,652.99 2006.211.07:45:38.83#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.07:45:38.83#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.07:45:38.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:38.83#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:38.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:38.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:38.83#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:45:38.83#ibcon#first serial, iclass 34, count 0 2006.211.07:45:38.83#ibcon#enter sib2, iclass 34, count 0 2006.211.07:45:38.83#ibcon#flushed, iclass 34, count 0 2006.211.07:45:38.83#ibcon#about to write, iclass 34, count 0 2006.211.07:45:38.83#ibcon#wrote, iclass 34, count 0 2006.211.07:45:38.83#ibcon#about to read 3, iclass 34, count 0 2006.211.07:45:38.85#ibcon#read 3, iclass 34, count 0 2006.211.07:45:38.85#ibcon#about to read 4, iclass 34, count 0 2006.211.07:45:38.85#ibcon#read 4, iclass 34, count 0 2006.211.07:45:38.85#ibcon#about to read 5, iclass 34, count 0 2006.211.07:45:38.85#ibcon#read 5, iclass 34, count 0 2006.211.07:45:38.85#ibcon#about to read 6, iclass 34, count 0 2006.211.07:45:38.85#ibcon#read 6, iclass 34, count 0 2006.211.07:45:38.85#ibcon#end of sib2, iclass 34, count 0 2006.211.07:45:38.85#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:45:38.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:45:38.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:45:38.85#ibcon#*before write, iclass 34, count 0 2006.211.07:45:38.85#ibcon#enter sib2, iclass 34, count 0 2006.211.07:45:38.85#ibcon#flushed, iclass 34, count 0 2006.211.07:45:38.85#ibcon#about to write, iclass 34, count 0 2006.211.07:45:38.85#ibcon#wrote, iclass 34, count 0 2006.211.07:45:38.85#ibcon#about to read 3, iclass 34, count 0 2006.211.07:45:38.89#ibcon#read 3, iclass 34, count 0 2006.211.07:45:38.89#ibcon#about to read 4, iclass 34, count 0 2006.211.07:45:38.89#ibcon#read 4, iclass 34, count 0 2006.211.07:45:38.89#ibcon#about to read 5, iclass 34, count 0 2006.211.07:45:38.89#ibcon#read 5, iclass 34, count 0 2006.211.07:45:38.89#ibcon#about to read 6, iclass 34, count 0 2006.211.07:45:38.89#ibcon#read 6, iclass 34, count 0 2006.211.07:45:38.89#ibcon#end of sib2, iclass 34, count 0 2006.211.07:45:38.89#ibcon#*after write, iclass 34, count 0 2006.211.07:45:38.89#ibcon#*before return 0, iclass 34, count 0 2006.211.07:45:38.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:38.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:38.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:45:38.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:45:38.89$vc4f8/va=5,7 2006.211.07:45:38.89#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.07:45:38.89#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.07:45:38.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:38.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:38.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:38.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:38.95#ibcon#enter wrdev, iclass 36, count 2 2006.211.07:45:38.95#ibcon#first serial, iclass 36, count 2 2006.211.07:45:38.95#ibcon#enter sib2, iclass 36, count 2 2006.211.07:45:38.95#ibcon#flushed, iclass 36, count 2 2006.211.07:45:38.95#ibcon#about to write, iclass 36, count 2 2006.211.07:45:38.95#ibcon#wrote, iclass 36, count 2 2006.211.07:45:38.95#ibcon#about to read 3, iclass 36, count 2 2006.211.07:45:38.97#ibcon#read 3, iclass 36, count 2 2006.211.07:45:38.97#ibcon#about to read 4, iclass 36, count 2 2006.211.07:45:38.97#ibcon#read 4, iclass 36, count 2 2006.211.07:45:38.97#ibcon#about to read 5, iclass 36, count 2 2006.211.07:45:38.97#ibcon#read 5, iclass 36, count 2 2006.211.07:45:38.97#ibcon#about to read 6, iclass 36, count 2 2006.211.07:45:38.97#ibcon#read 6, iclass 36, count 2 2006.211.07:45:38.97#ibcon#end of sib2, iclass 36, count 2 2006.211.07:45:38.97#ibcon#*mode == 0, iclass 36, count 2 2006.211.07:45:38.97#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.07:45:38.97#ibcon#[25=AT05-07\r\n] 2006.211.07:45:38.97#ibcon#*before write, iclass 36, count 2 2006.211.07:45:38.97#ibcon#enter sib2, iclass 36, count 2 2006.211.07:45:38.97#ibcon#flushed, iclass 36, count 2 2006.211.07:45:38.97#ibcon#about to write, iclass 36, count 2 2006.211.07:45:38.97#ibcon#wrote, iclass 36, count 2 2006.211.07:45:38.97#ibcon#about to read 3, iclass 36, count 2 2006.211.07:45:39.00#ibcon#read 3, iclass 36, count 2 2006.211.07:45:39.00#ibcon#about to read 4, iclass 36, count 2 2006.211.07:45:39.00#ibcon#read 4, iclass 36, count 2 2006.211.07:45:39.00#ibcon#about to read 5, iclass 36, count 2 2006.211.07:45:39.00#ibcon#read 5, iclass 36, count 2 2006.211.07:45:39.00#ibcon#about to read 6, iclass 36, count 2 2006.211.07:45:39.00#ibcon#read 6, iclass 36, count 2 2006.211.07:45:39.00#ibcon#end of sib2, iclass 36, count 2 2006.211.07:45:39.00#ibcon#*after write, iclass 36, count 2 2006.211.07:45:39.00#ibcon#*before return 0, iclass 36, count 2 2006.211.07:45:39.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:39.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:39.00#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.07:45:39.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:39.00#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:39.12#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:39.12#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:39.12#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:45:39.12#ibcon#first serial, iclass 36, count 0 2006.211.07:45:39.12#ibcon#enter sib2, iclass 36, count 0 2006.211.07:45:39.12#ibcon#flushed, iclass 36, count 0 2006.211.07:45:39.12#ibcon#about to write, iclass 36, count 0 2006.211.07:45:39.12#ibcon#wrote, iclass 36, count 0 2006.211.07:45:39.12#ibcon#about to read 3, iclass 36, count 0 2006.211.07:45:39.14#ibcon#read 3, iclass 36, count 0 2006.211.07:45:39.14#ibcon#about to read 4, iclass 36, count 0 2006.211.07:45:39.14#ibcon#read 4, iclass 36, count 0 2006.211.07:45:39.14#ibcon#about to read 5, iclass 36, count 0 2006.211.07:45:39.14#ibcon#read 5, iclass 36, count 0 2006.211.07:45:39.14#ibcon#about to read 6, iclass 36, count 0 2006.211.07:45:39.14#ibcon#read 6, iclass 36, count 0 2006.211.07:45:39.14#ibcon#end of sib2, iclass 36, count 0 2006.211.07:45:39.14#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:45:39.14#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:45:39.14#ibcon#[25=USB\r\n] 2006.211.07:45:39.14#ibcon#*before write, iclass 36, count 0 2006.211.07:45:39.14#ibcon#enter sib2, iclass 36, count 0 2006.211.07:45:39.14#ibcon#flushed, iclass 36, count 0 2006.211.07:45:39.14#ibcon#about to write, iclass 36, count 0 2006.211.07:45:39.14#ibcon#wrote, iclass 36, count 0 2006.211.07:45:39.14#ibcon#about to read 3, iclass 36, count 0 2006.211.07:45:39.17#ibcon#read 3, iclass 36, count 0 2006.211.07:45:39.17#ibcon#about to read 4, iclass 36, count 0 2006.211.07:45:39.17#ibcon#read 4, iclass 36, count 0 2006.211.07:45:39.17#ibcon#about to read 5, iclass 36, count 0 2006.211.07:45:39.17#ibcon#read 5, iclass 36, count 0 2006.211.07:45:39.17#ibcon#about to read 6, iclass 36, count 0 2006.211.07:45:39.17#ibcon#read 6, iclass 36, count 0 2006.211.07:45:39.17#ibcon#end of sib2, iclass 36, count 0 2006.211.07:45:39.17#ibcon#*after write, iclass 36, count 0 2006.211.07:45:39.17#ibcon#*before return 0, iclass 36, count 0 2006.211.07:45:39.17#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:39.17#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:39.17#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:45:39.17#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:45:39.17$vc4f8/valo=6,772.99 2006.211.07:45:39.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.07:45:39.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.07:45:39.17#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:39.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:39.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:39.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:39.17#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:45:39.17#ibcon#first serial, iclass 38, count 0 2006.211.07:45:39.17#ibcon#enter sib2, iclass 38, count 0 2006.211.07:45:39.17#ibcon#flushed, iclass 38, count 0 2006.211.07:45:39.17#ibcon#about to write, iclass 38, count 0 2006.211.07:45:39.17#ibcon#wrote, iclass 38, count 0 2006.211.07:45:39.17#ibcon#about to read 3, iclass 38, count 0 2006.211.07:45:39.19#ibcon#read 3, iclass 38, count 0 2006.211.07:45:39.19#ibcon#about to read 4, iclass 38, count 0 2006.211.07:45:39.19#ibcon#read 4, iclass 38, count 0 2006.211.07:45:39.19#ibcon#about to read 5, iclass 38, count 0 2006.211.07:45:39.19#ibcon#read 5, iclass 38, count 0 2006.211.07:45:39.19#ibcon#about to read 6, iclass 38, count 0 2006.211.07:45:39.19#ibcon#read 6, iclass 38, count 0 2006.211.07:45:39.19#ibcon#end of sib2, iclass 38, count 0 2006.211.07:45:39.19#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:45:39.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:45:39.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:45:39.19#ibcon#*before write, iclass 38, count 0 2006.211.07:45:39.19#ibcon#enter sib2, iclass 38, count 0 2006.211.07:45:39.19#ibcon#flushed, iclass 38, count 0 2006.211.07:45:39.19#ibcon#about to write, iclass 38, count 0 2006.211.07:45:39.19#ibcon#wrote, iclass 38, count 0 2006.211.07:45:39.19#ibcon#about to read 3, iclass 38, count 0 2006.211.07:45:39.23#ibcon#read 3, iclass 38, count 0 2006.211.07:45:39.23#ibcon#about to read 4, iclass 38, count 0 2006.211.07:45:39.23#ibcon#read 4, iclass 38, count 0 2006.211.07:45:39.23#ibcon#about to read 5, iclass 38, count 0 2006.211.07:45:39.23#ibcon#read 5, iclass 38, count 0 2006.211.07:45:39.23#ibcon#about to read 6, iclass 38, count 0 2006.211.07:45:39.23#ibcon#read 6, iclass 38, count 0 2006.211.07:45:39.23#ibcon#end of sib2, iclass 38, count 0 2006.211.07:45:39.23#ibcon#*after write, iclass 38, count 0 2006.211.07:45:39.23#ibcon#*before return 0, iclass 38, count 0 2006.211.07:45:39.23#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:39.23#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:39.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:45:39.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:45:39.23$vc4f8/va=6,6 2006.211.07:45:39.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.07:45:39.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.07:45:39.23#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:39.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:39.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:39.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:39.29#ibcon#enter wrdev, iclass 40, count 2 2006.211.07:45:39.29#ibcon#first serial, iclass 40, count 2 2006.211.07:45:39.29#ibcon#enter sib2, iclass 40, count 2 2006.211.07:45:39.29#ibcon#flushed, iclass 40, count 2 2006.211.07:45:39.29#ibcon#about to write, iclass 40, count 2 2006.211.07:45:39.29#ibcon#wrote, iclass 40, count 2 2006.211.07:45:39.29#ibcon#about to read 3, iclass 40, count 2 2006.211.07:45:39.31#ibcon#read 3, iclass 40, count 2 2006.211.07:45:39.31#ibcon#about to read 4, iclass 40, count 2 2006.211.07:45:39.31#ibcon#read 4, iclass 40, count 2 2006.211.07:45:39.31#ibcon#about to read 5, iclass 40, count 2 2006.211.07:45:39.31#ibcon#read 5, iclass 40, count 2 2006.211.07:45:39.31#ibcon#about to read 6, iclass 40, count 2 2006.211.07:45:39.31#ibcon#read 6, iclass 40, count 2 2006.211.07:45:39.31#ibcon#end of sib2, iclass 40, count 2 2006.211.07:45:39.31#ibcon#*mode == 0, iclass 40, count 2 2006.211.07:45:39.31#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.07:45:39.31#ibcon#[25=AT06-06\r\n] 2006.211.07:45:39.31#ibcon#*before write, iclass 40, count 2 2006.211.07:45:39.31#ibcon#enter sib2, iclass 40, count 2 2006.211.07:45:39.31#ibcon#flushed, iclass 40, count 2 2006.211.07:45:39.31#ibcon#about to write, iclass 40, count 2 2006.211.07:45:39.31#ibcon#wrote, iclass 40, count 2 2006.211.07:45:39.31#ibcon#about to read 3, iclass 40, count 2 2006.211.07:45:39.34#ibcon#read 3, iclass 40, count 2 2006.211.07:45:39.34#ibcon#about to read 4, iclass 40, count 2 2006.211.07:45:39.34#ibcon#read 4, iclass 40, count 2 2006.211.07:45:39.34#ibcon#about to read 5, iclass 40, count 2 2006.211.07:45:39.34#ibcon#read 5, iclass 40, count 2 2006.211.07:45:39.34#ibcon#about to read 6, iclass 40, count 2 2006.211.07:45:39.34#ibcon#read 6, iclass 40, count 2 2006.211.07:45:39.34#ibcon#end of sib2, iclass 40, count 2 2006.211.07:45:39.34#ibcon#*after write, iclass 40, count 2 2006.211.07:45:39.34#ibcon#*before return 0, iclass 40, count 2 2006.211.07:45:39.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:39.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:39.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.07:45:39.34#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:39.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:39.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:39.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:39.46#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:45:39.46#ibcon#first serial, iclass 40, count 0 2006.211.07:45:39.46#ibcon#enter sib2, iclass 40, count 0 2006.211.07:45:39.46#ibcon#flushed, iclass 40, count 0 2006.211.07:45:39.46#ibcon#about to write, iclass 40, count 0 2006.211.07:45:39.46#ibcon#wrote, iclass 40, count 0 2006.211.07:45:39.46#ibcon#about to read 3, iclass 40, count 0 2006.211.07:45:39.48#ibcon#read 3, iclass 40, count 0 2006.211.07:45:39.48#ibcon#about to read 4, iclass 40, count 0 2006.211.07:45:39.48#ibcon#read 4, iclass 40, count 0 2006.211.07:45:39.48#ibcon#about to read 5, iclass 40, count 0 2006.211.07:45:39.48#ibcon#read 5, iclass 40, count 0 2006.211.07:45:39.48#ibcon#about to read 6, iclass 40, count 0 2006.211.07:45:39.48#ibcon#read 6, iclass 40, count 0 2006.211.07:45:39.48#ibcon#end of sib2, iclass 40, count 0 2006.211.07:45:39.48#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:45:39.48#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:45:39.48#ibcon#[25=USB\r\n] 2006.211.07:45:39.48#ibcon#*before write, iclass 40, count 0 2006.211.07:45:39.48#ibcon#enter sib2, iclass 40, count 0 2006.211.07:45:39.48#ibcon#flushed, iclass 40, count 0 2006.211.07:45:39.48#ibcon#about to write, iclass 40, count 0 2006.211.07:45:39.48#ibcon#wrote, iclass 40, count 0 2006.211.07:45:39.48#ibcon#about to read 3, iclass 40, count 0 2006.211.07:45:39.51#ibcon#read 3, iclass 40, count 0 2006.211.07:45:39.51#ibcon#about to read 4, iclass 40, count 0 2006.211.07:45:39.51#ibcon#read 4, iclass 40, count 0 2006.211.07:45:39.51#ibcon#about to read 5, iclass 40, count 0 2006.211.07:45:39.51#ibcon#read 5, iclass 40, count 0 2006.211.07:45:39.51#ibcon#about to read 6, iclass 40, count 0 2006.211.07:45:39.51#ibcon#read 6, iclass 40, count 0 2006.211.07:45:39.51#ibcon#end of sib2, iclass 40, count 0 2006.211.07:45:39.51#ibcon#*after write, iclass 40, count 0 2006.211.07:45:39.51#ibcon#*before return 0, iclass 40, count 0 2006.211.07:45:39.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:39.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:39.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:45:39.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:45:39.51$vc4f8/valo=7,832.99 2006.211.07:45:39.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.07:45:39.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.07:45:39.51#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:39.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:39.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:39.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:39.51#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:45:39.51#ibcon#first serial, iclass 4, count 0 2006.211.07:45:39.51#ibcon#enter sib2, iclass 4, count 0 2006.211.07:45:39.51#ibcon#flushed, iclass 4, count 0 2006.211.07:45:39.51#ibcon#about to write, iclass 4, count 0 2006.211.07:45:39.51#ibcon#wrote, iclass 4, count 0 2006.211.07:45:39.51#ibcon#about to read 3, iclass 4, count 0 2006.211.07:45:39.53#ibcon#read 3, iclass 4, count 0 2006.211.07:45:39.53#ibcon#about to read 4, iclass 4, count 0 2006.211.07:45:39.53#ibcon#read 4, iclass 4, count 0 2006.211.07:45:39.53#ibcon#about to read 5, iclass 4, count 0 2006.211.07:45:39.53#ibcon#read 5, iclass 4, count 0 2006.211.07:45:39.53#ibcon#about to read 6, iclass 4, count 0 2006.211.07:45:39.53#ibcon#read 6, iclass 4, count 0 2006.211.07:45:39.53#ibcon#end of sib2, iclass 4, count 0 2006.211.07:45:39.53#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:45:39.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:45:39.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:45:39.53#ibcon#*before write, iclass 4, count 0 2006.211.07:45:39.53#ibcon#enter sib2, iclass 4, count 0 2006.211.07:45:39.53#ibcon#flushed, iclass 4, count 0 2006.211.07:45:39.53#ibcon#about to write, iclass 4, count 0 2006.211.07:45:39.53#ibcon#wrote, iclass 4, count 0 2006.211.07:45:39.53#ibcon#about to read 3, iclass 4, count 0 2006.211.07:45:39.57#ibcon#read 3, iclass 4, count 0 2006.211.07:45:39.57#ibcon#about to read 4, iclass 4, count 0 2006.211.07:45:39.57#ibcon#read 4, iclass 4, count 0 2006.211.07:45:39.57#ibcon#about to read 5, iclass 4, count 0 2006.211.07:45:39.57#ibcon#read 5, iclass 4, count 0 2006.211.07:45:39.57#ibcon#about to read 6, iclass 4, count 0 2006.211.07:45:39.57#ibcon#read 6, iclass 4, count 0 2006.211.07:45:39.57#ibcon#end of sib2, iclass 4, count 0 2006.211.07:45:39.57#ibcon#*after write, iclass 4, count 0 2006.211.07:45:39.57#ibcon#*before return 0, iclass 4, count 0 2006.211.07:45:39.57#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:39.57#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:39.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:45:39.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:45:39.57$vc4f8/va=7,6 2006.211.07:45:39.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.07:45:39.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.07:45:39.57#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:39.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:45:39.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:45:39.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:45:39.63#ibcon#enter wrdev, iclass 6, count 2 2006.211.07:45:39.63#ibcon#first serial, iclass 6, count 2 2006.211.07:45:39.63#ibcon#enter sib2, iclass 6, count 2 2006.211.07:45:39.63#ibcon#flushed, iclass 6, count 2 2006.211.07:45:39.63#ibcon#about to write, iclass 6, count 2 2006.211.07:45:39.63#ibcon#wrote, iclass 6, count 2 2006.211.07:45:39.63#ibcon#about to read 3, iclass 6, count 2 2006.211.07:45:39.65#ibcon#read 3, iclass 6, count 2 2006.211.07:45:39.65#ibcon#about to read 4, iclass 6, count 2 2006.211.07:45:39.65#ibcon#read 4, iclass 6, count 2 2006.211.07:45:39.65#ibcon#about to read 5, iclass 6, count 2 2006.211.07:45:39.65#ibcon#read 5, iclass 6, count 2 2006.211.07:45:39.65#ibcon#about to read 6, iclass 6, count 2 2006.211.07:45:39.65#ibcon#read 6, iclass 6, count 2 2006.211.07:45:39.65#ibcon#end of sib2, iclass 6, count 2 2006.211.07:45:39.65#ibcon#*mode == 0, iclass 6, count 2 2006.211.07:45:39.65#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.07:45:39.65#ibcon#[25=AT07-06\r\n] 2006.211.07:45:39.65#ibcon#*before write, iclass 6, count 2 2006.211.07:45:39.65#ibcon#enter sib2, iclass 6, count 2 2006.211.07:45:39.65#ibcon#flushed, iclass 6, count 2 2006.211.07:45:39.65#ibcon#about to write, iclass 6, count 2 2006.211.07:45:39.65#ibcon#wrote, iclass 6, count 2 2006.211.07:45:39.65#ibcon#about to read 3, iclass 6, count 2 2006.211.07:45:39.68#ibcon#read 3, iclass 6, count 2 2006.211.07:45:39.68#ibcon#about to read 4, iclass 6, count 2 2006.211.07:45:39.68#ibcon#read 4, iclass 6, count 2 2006.211.07:45:39.68#ibcon#about to read 5, iclass 6, count 2 2006.211.07:45:39.68#ibcon#read 5, iclass 6, count 2 2006.211.07:45:39.68#ibcon#about to read 6, iclass 6, count 2 2006.211.07:45:39.68#ibcon#read 6, iclass 6, count 2 2006.211.07:45:39.68#ibcon#end of sib2, iclass 6, count 2 2006.211.07:45:39.68#ibcon#*after write, iclass 6, count 2 2006.211.07:45:39.68#ibcon#*before return 0, iclass 6, count 2 2006.211.07:45:39.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:45:39.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:45:39.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.07:45:39.68#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:39.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:45:39.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:45:39.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:45:39.80#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:45:39.80#ibcon#first serial, iclass 6, count 0 2006.211.07:45:39.80#ibcon#enter sib2, iclass 6, count 0 2006.211.07:45:39.80#ibcon#flushed, iclass 6, count 0 2006.211.07:45:39.80#ibcon#about to write, iclass 6, count 0 2006.211.07:45:39.80#ibcon#wrote, iclass 6, count 0 2006.211.07:45:39.80#ibcon#about to read 3, iclass 6, count 0 2006.211.07:45:39.82#ibcon#read 3, iclass 6, count 0 2006.211.07:45:39.82#ibcon#about to read 4, iclass 6, count 0 2006.211.07:45:39.82#ibcon#read 4, iclass 6, count 0 2006.211.07:45:39.82#ibcon#about to read 5, iclass 6, count 0 2006.211.07:45:39.82#ibcon#read 5, iclass 6, count 0 2006.211.07:45:39.82#ibcon#about to read 6, iclass 6, count 0 2006.211.07:45:39.82#ibcon#read 6, iclass 6, count 0 2006.211.07:45:39.82#ibcon#end of sib2, iclass 6, count 0 2006.211.07:45:39.82#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:45:39.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:45:39.82#ibcon#[25=USB\r\n] 2006.211.07:45:39.82#ibcon#*before write, iclass 6, count 0 2006.211.07:45:39.82#ibcon#enter sib2, iclass 6, count 0 2006.211.07:45:39.82#ibcon#flushed, iclass 6, count 0 2006.211.07:45:39.82#ibcon#about to write, iclass 6, count 0 2006.211.07:45:39.82#ibcon#wrote, iclass 6, count 0 2006.211.07:45:39.82#ibcon#about to read 3, iclass 6, count 0 2006.211.07:45:39.85#ibcon#read 3, iclass 6, count 0 2006.211.07:45:39.85#ibcon#about to read 4, iclass 6, count 0 2006.211.07:45:39.85#ibcon#read 4, iclass 6, count 0 2006.211.07:45:39.85#ibcon#about to read 5, iclass 6, count 0 2006.211.07:45:39.85#ibcon#read 5, iclass 6, count 0 2006.211.07:45:39.85#ibcon#about to read 6, iclass 6, count 0 2006.211.07:45:39.85#ibcon#read 6, iclass 6, count 0 2006.211.07:45:39.85#ibcon#end of sib2, iclass 6, count 0 2006.211.07:45:39.85#ibcon#*after write, iclass 6, count 0 2006.211.07:45:39.85#ibcon#*before return 0, iclass 6, count 0 2006.211.07:45:39.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:45:39.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:45:39.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:45:39.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:45:39.85$vc4f8/valo=8,852.99 2006.211.07:45:39.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.07:45:39.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.07:45:39.85#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:39.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:45:39.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:45:39.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:45:39.85#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:45:39.85#ibcon#first serial, iclass 10, count 0 2006.211.07:45:39.85#ibcon#enter sib2, iclass 10, count 0 2006.211.07:45:39.85#ibcon#flushed, iclass 10, count 0 2006.211.07:45:39.85#ibcon#about to write, iclass 10, count 0 2006.211.07:45:39.85#ibcon#wrote, iclass 10, count 0 2006.211.07:45:39.85#ibcon#about to read 3, iclass 10, count 0 2006.211.07:45:39.87#ibcon#read 3, iclass 10, count 0 2006.211.07:45:39.87#ibcon#about to read 4, iclass 10, count 0 2006.211.07:45:39.87#ibcon#read 4, iclass 10, count 0 2006.211.07:45:39.87#ibcon#about to read 5, iclass 10, count 0 2006.211.07:45:39.87#ibcon#read 5, iclass 10, count 0 2006.211.07:45:39.87#ibcon#about to read 6, iclass 10, count 0 2006.211.07:45:39.87#ibcon#read 6, iclass 10, count 0 2006.211.07:45:39.87#ibcon#end of sib2, iclass 10, count 0 2006.211.07:45:39.87#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:45:39.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:45:39.87#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:45:39.87#ibcon#*before write, iclass 10, count 0 2006.211.07:45:39.87#ibcon#enter sib2, iclass 10, count 0 2006.211.07:45:39.87#ibcon#flushed, iclass 10, count 0 2006.211.07:45:39.87#ibcon#about to write, iclass 10, count 0 2006.211.07:45:39.87#ibcon#wrote, iclass 10, count 0 2006.211.07:45:39.87#ibcon#about to read 3, iclass 10, count 0 2006.211.07:45:39.91#ibcon#read 3, iclass 10, count 0 2006.211.07:45:39.91#ibcon#about to read 4, iclass 10, count 0 2006.211.07:45:39.91#ibcon#read 4, iclass 10, count 0 2006.211.07:45:39.91#ibcon#about to read 5, iclass 10, count 0 2006.211.07:45:39.91#ibcon#read 5, iclass 10, count 0 2006.211.07:45:39.91#ibcon#about to read 6, iclass 10, count 0 2006.211.07:45:39.91#ibcon#read 6, iclass 10, count 0 2006.211.07:45:39.91#ibcon#end of sib2, iclass 10, count 0 2006.211.07:45:39.91#ibcon#*after write, iclass 10, count 0 2006.211.07:45:39.91#ibcon#*before return 0, iclass 10, count 0 2006.211.07:45:39.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:45:39.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:45:39.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:45:39.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:45:39.91$vc4f8/va=8,7 2006.211.07:45:39.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.07:45:39.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.07:45:39.91#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:39.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:45:39.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:45:39.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:45:39.97#ibcon#enter wrdev, iclass 12, count 2 2006.211.07:45:39.97#ibcon#first serial, iclass 12, count 2 2006.211.07:45:39.97#ibcon#enter sib2, iclass 12, count 2 2006.211.07:45:39.97#ibcon#flushed, iclass 12, count 2 2006.211.07:45:39.97#ibcon#about to write, iclass 12, count 2 2006.211.07:45:39.97#ibcon#wrote, iclass 12, count 2 2006.211.07:45:39.97#ibcon#about to read 3, iclass 12, count 2 2006.211.07:45:39.99#ibcon#read 3, iclass 12, count 2 2006.211.07:45:39.99#ibcon#about to read 4, iclass 12, count 2 2006.211.07:45:39.99#ibcon#read 4, iclass 12, count 2 2006.211.07:45:39.99#ibcon#about to read 5, iclass 12, count 2 2006.211.07:45:39.99#ibcon#read 5, iclass 12, count 2 2006.211.07:45:39.99#ibcon#about to read 6, iclass 12, count 2 2006.211.07:45:39.99#ibcon#read 6, iclass 12, count 2 2006.211.07:45:39.99#ibcon#end of sib2, iclass 12, count 2 2006.211.07:45:39.99#ibcon#*mode == 0, iclass 12, count 2 2006.211.07:45:39.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.07:45:39.99#ibcon#[25=AT08-07\r\n] 2006.211.07:45:39.99#ibcon#*before write, iclass 12, count 2 2006.211.07:45:39.99#ibcon#enter sib2, iclass 12, count 2 2006.211.07:45:39.99#ibcon#flushed, iclass 12, count 2 2006.211.07:45:39.99#ibcon#about to write, iclass 12, count 2 2006.211.07:45:39.99#ibcon#wrote, iclass 12, count 2 2006.211.07:45:39.99#ibcon#about to read 3, iclass 12, count 2 2006.211.07:45:40.02#ibcon#read 3, iclass 12, count 2 2006.211.07:45:40.02#ibcon#about to read 4, iclass 12, count 2 2006.211.07:45:40.02#ibcon#read 4, iclass 12, count 2 2006.211.07:45:40.02#ibcon#about to read 5, iclass 12, count 2 2006.211.07:45:40.02#ibcon#read 5, iclass 12, count 2 2006.211.07:45:40.02#ibcon#about to read 6, iclass 12, count 2 2006.211.07:45:40.02#ibcon#read 6, iclass 12, count 2 2006.211.07:45:40.02#ibcon#end of sib2, iclass 12, count 2 2006.211.07:45:40.02#ibcon#*after write, iclass 12, count 2 2006.211.07:45:40.02#ibcon#*before return 0, iclass 12, count 2 2006.211.07:45:40.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:45:40.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:45:40.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.07:45:40.02#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:40.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:45:40.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:45:40.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:45:40.14#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:45:40.14#ibcon#first serial, iclass 12, count 0 2006.211.07:45:40.14#ibcon#enter sib2, iclass 12, count 0 2006.211.07:45:40.14#ibcon#flushed, iclass 12, count 0 2006.211.07:45:40.14#ibcon#about to write, iclass 12, count 0 2006.211.07:45:40.14#ibcon#wrote, iclass 12, count 0 2006.211.07:45:40.14#ibcon#about to read 3, iclass 12, count 0 2006.211.07:45:40.16#ibcon#read 3, iclass 12, count 0 2006.211.07:45:40.16#ibcon#about to read 4, iclass 12, count 0 2006.211.07:45:40.16#ibcon#read 4, iclass 12, count 0 2006.211.07:45:40.16#ibcon#about to read 5, iclass 12, count 0 2006.211.07:45:40.16#ibcon#read 5, iclass 12, count 0 2006.211.07:45:40.16#ibcon#about to read 6, iclass 12, count 0 2006.211.07:45:40.16#ibcon#read 6, iclass 12, count 0 2006.211.07:45:40.16#ibcon#end of sib2, iclass 12, count 0 2006.211.07:45:40.16#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:45:40.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:45:40.16#ibcon#[25=USB\r\n] 2006.211.07:45:40.16#ibcon#*before write, iclass 12, count 0 2006.211.07:45:40.16#ibcon#enter sib2, iclass 12, count 0 2006.211.07:45:40.16#ibcon#flushed, iclass 12, count 0 2006.211.07:45:40.16#ibcon#about to write, iclass 12, count 0 2006.211.07:45:40.16#ibcon#wrote, iclass 12, count 0 2006.211.07:45:40.16#ibcon#about to read 3, iclass 12, count 0 2006.211.07:45:40.19#ibcon#read 3, iclass 12, count 0 2006.211.07:45:40.19#ibcon#about to read 4, iclass 12, count 0 2006.211.07:45:40.19#ibcon#read 4, iclass 12, count 0 2006.211.07:45:40.19#ibcon#about to read 5, iclass 12, count 0 2006.211.07:45:40.19#ibcon#read 5, iclass 12, count 0 2006.211.07:45:40.19#ibcon#about to read 6, iclass 12, count 0 2006.211.07:45:40.19#ibcon#read 6, iclass 12, count 0 2006.211.07:45:40.19#ibcon#end of sib2, iclass 12, count 0 2006.211.07:45:40.19#ibcon#*after write, iclass 12, count 0 2006.211.07:45:40.19#ibcon#*before return 0, iclass 12, count 0 2006.211.07:45:40.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:45:40.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:45:40.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:45:40.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:45:40.19$vc4f8/vblo=1,632.99 2006.211.07:45:40.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.07:45:40.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.07:45:40.19#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:40.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:45:40.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:45:40.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:45:40.19#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:45:40.19#ibcon#first serial, iclass 14, count 0 2006.211.07:45:40.19#ibcon#enter sib2, iclass 14, count 0 2006.211.07:45:40.19#ibcon#flushed, iclass 14, count 0 2006.211.07:45:40.19#ibcon#about to write, iclass 14, count 0 2006.211.07:45:40.19#ibcon#wrote, iclass 14, count 0 2006.211.07:45:40.19#ibcon#about to read 3, iclass 14, count 0 2006.211.07:45:40.21#ibcon#read 3, iclass 14, count 0 2006.211.07:45:40.21#ibcon#about to read 4, iclass 14, count 0 2006.211.07:45:40.21#ibcon#read 4, iclass 14, count 0 2006.211.07:45:40.21#ibcon#about to read 5, iclass 14, count 0 2006.211.07:45:40.21#ibcon#read 5, iclass 14, count 0 2006.211.07:45:40.21#ibcon#about to read 6, iclass 14, count 0 2006.211.07:45:40.21#ibcon#read 6, iclass 14, count 0 2006.211.07:45:40.21#ibcon#end of sib2, iclass 14, count 0 2006.211.07:45:40.21#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:45:40.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:45:40.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:45:40.21#ibcon#*before write, iclass 14, count 0 2006.211.07:45:40.21#ibcon#enter sib2, iclass 14, count 0 2006.211.07:45:40.21#ibcon#flushed, iclass 14, count 0 2006.211.07:45:40.21#ibcon#about to write, iclass 14, count 0 2006.211.07:45:40.21#ibcon#wrote, iclass 14, count 0 2006.211.07:45:40.21#ibcon#about to read 3, iclass 14, count 0 2006.211.07:45:40.25#ibcon#read 3, iclass 14, count 0 2006.211.07:45:40.25#ibcon#about to read 4, iclass 14, count 0 2006.211.07:45:40.25#ibcon#read 4, iclass 14, count 0 2006.211.07:45:40.25#ibcon#about to read 5, iclass 14, count 0 2006.211.07:45:40.25#ibcon#read 5, iclass 14, count 0 2006.211.07:45:40.25#ibcon#about to read 6, iclass 14, count 0 2006.211.07:45:40.25#ibcon#read 6, iclass 14, count 0 2006.211.07:45:40.25#ibcon#end of sib2, iclass 14, count 0 2006.211.07:45:40.25#ibcon#*after write, iclass 14, count 0 2006.211.07:45:40.25#ibcon#*before return 0, iclass 14, count 0 2006.211.07:45:40.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:45:40.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:45:40.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:45:40.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:45:40.25$vc4f8/vb=1,4 2006.211.07:45:40.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.07:45:40.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.07:45:40.25#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:40.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:45:40.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:45:40.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:45:40.25#ibcon#enter wrdev, iclass 16, count 2 2006.211.07:45:40.25#ibcon#first serial, iclass 16, count 2 2006.211.07:45:40.25#ibcon#enter sib2, iclass 16, count 2 2006.211.07:45:40.25#ibcon#flushed, iclass 16, count 2 2006.211.07:45:40.25#ibcon#about to write, iclass 16, count 2 2006.211.07:45:40.25#ibcon#wrote, iclass 16, count 2 2006.211.07:45:40.25#ibcon#about to read 3, iclass 16, count 2 2006.211.07:45:40.27#ibcon#read 3, iclass 16, count 2 2006.211.07:45:40.27#ibcon#about to read 4, iclass 16, count 2 2006.211.07:45:40.27#ibcon#read 4, iclass 16, count 2 2006.211.07:45:40.27#ibcon#about to read 5, iclass 16, count 2 2006.211.07:45:40.27#ibcon#read 5, iclass 16, count 2 2006.211.07:45:40.27#ibcon#about to read 6, iclass 16, count 2 2006.211.07:45:40.27#ibcon#read 6, iclass 16, count 2 2006.211.07:45:40.27#ibcon#end of sib2, iclass 16, count 2 2006.211.07:45:40.27#ibcon#*mode == 0, iclass 16, count 2 2006.211.07:45:40.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.07:45:40.27#ibcon#[27=AT01-04\r\n] 2006.211.07:45:40.27#ibcon#*before write, iclass 16, count 2 2006.211.07:45:40.27#ibcon#enter sib2, iclass 16, count 2 2006.211.07:45:40.27#ibcon#flushed, iclass 16, count 2 2006.211.07:45:40.27#ibcon#about to write, iclass 16, count 2 2006.211.07:45:40.27#ibcon#wrote, iclass 16, count 2 2006.211.07:45:40.27#ibcon#about to read 3, iclass 16, count 2 2006.211.07:45:40.30#ibcon#read 3, iclass 16, count 2 2006.211.07:45:40.30#ibcon#about to read 4, iclass 16, count 2 2006.211.07:45:40.30#ibcon#read 4, iclass 16, count 2 2006.211.07:45:40.30#ibcon#about to read 5, iclass 16, count 2 2006.211.07:45:40.30#ibcon#read 5, iclass 16, count 2 2006.211.07:45:40.30#ibcon#about to read 6, iclass 16, count 2 2006.211.07:45:40.30#ibcon#read 6, iclass 16, count 2 2006.211.07:45:40.30#ibcon#end of sib2, iclass 16, count 2 2006.211.07:45:40.30#ibcon#*after write, iclass 16, count 2 2006.211.07:45:40.30#ibcon#*before return 0, iclass 16, count 2 2006.211.07:45:40.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:45:40.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:45:40.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.07:45:40.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:40.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:45:40.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:45:40.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:45:40.42#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:45:40.42#ibcon#first serial, iclass 16, count 0 2006.211.07:45:40.42#ibcon#enter sib2, iclass 16, count 0 2006.211.07:45:40.42#ibcon#flushed, iclass 16, count 0 2006.211.07:45:40.42#ibcon#about to write, iclass 16, count 0 2006.211.07:45:40.42#ibcon#wrote, iclass 16, count 0 2006.211.07:45:40.42#ibcon#about to read 3, iclass 16, count 0 2006.211.07:45:40.44#ibcon#read 3, iclass 16, count 0 2006.211.07:45:40.44#ibcon#about to read 4, iclass 16, count 0 2006.211.07:45:40.44#ibcon#read 4, iclass 16, count 0 2006.211.07:45:40.44#ibcon#about to read 5, iclass 16, count 0 2006.211.07:45:40.44#ibcon#read 5, iclass 16, count 0 2006.211.07:45:40.44#ibcon#about to read 6, iclass 16, count 0 2006.211.07:45:40.44#ibcon#read 6, iclass 16, count 0 2006.211.07:45:40.44#ibcon#end of sib2, iclass 16, count 0 2006.211.07:45:40.44#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:45:40.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:45:40.44#ibcon#[27=USB\r\n] 2006.211.07:45:40.44#ibcon#*before write, iclass 16, count 0 2006.211.07:45:40.44#ibcon#enter sib2, iclass 16, count 0 2006.211.07:45:40.44#ibcon#flushed, iclass 16, count 0 2006.211.07:45:40.44#ibcon#about to write, iclass 16, count 0 2006.211.07:45:40.44#ibcon#wrote, iclass 16, count 0 2006.211.07:45:40.44#ibcon#about to read 3, iclass 16, count 0 2006.211.07:45:40.47#ibcon#read 3, iclass 16, count 0 2006.211.07:45:40.47#ibcon#about to read 4, iclass 16, count 0 2006.211.07:45:40.47#ibcon#read 4, iclass 16, count 0 2006.211.07:45:40.47#ibcon#about to read 5, iclass 16, count 0 2006.211.07:45:40.47#ibcon#read 5, iclass 16, count 0 2006.211.07:45:40.47#ibcon#about to read 6, iclass 16, count 0 2006.211.07:45:40.47#ibcon#read 6, iclass 16, count 0 2006.211.07:45:40.47#ibcon#end of sib2, iclass 16, count 0 2006.211.07:45:40.47#ibcon#*after write, iclass 16, count 0 2006.211.07:45:40.47#ibcon#*before return 0, iclass 16, count 0 2006.211.07:45:40.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:45:40.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:45:40.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:45:40.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:45:40.47$vc4f8/vblo=2,640.99 2006.211.07:45:40.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:45:40.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:45:40.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:40.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:40.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:40.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:40.47#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:45:40.47#ibcon#first serial, iclass 18, count 0 2006.211.07:45:40.47#ibcon#enter sib2, iclass 18, count 0 2006.211.07:45:40.47#ibcon#flushed, iclass 18, count 0 2006.211.07:45:40.47#ibcon#about to write, iclass 18, count 0 2006.211.07:45:40.47#ibcon#wrote, iclass 18, count 0 2006.211.07:45:40.47#ibcon#about to read 3, iclass 18, count 0 2006.211.07:45:40.49#ibcon#read 3, iclass 18, count 0 2006.211.07:45:40.49#ibcon#about to read 4, iclass 18, count 0 2006.211.07:45:40.49#ibcon#read 4, iclass 18, count 0 2006.211.07:45:40.49#ibcon#about to read 5, iclass 18, count 0 2006.211.07:45:40.49#ibcon#read 5, iclass 18, count 0 2006.211.07:45:40.49#ibcon#about to read 6, iclass 18, count 0 2006.211.07:45:40.49#ibcon#read 6, iclass 18, count 0 2006.211.07:45:40.49#ibcon#end of sib2, iclass 18, count 0 2006.211.07:45:40.49#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:45:40.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:45:40.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:45:40.49#ibcon#*before write, iclass 18, count 0 2006.211.07:45:40.49#ibcon#enter sib2, iclass 18, count 0 2006.211.07:45:40.49#ibcon#flushed, iclass 18, count 0 2006.211.07:45:40.49#ibcon#about to write, iclass 18, count 0 2006.211.07:45:40.49#ibcon#wrote, iclass 18, count 0 2006.211.07:45:40.49#ibcon#about to read 3, iclass 18, count 0 2006.211.07:45:40.53#ibcon#read 3, iclass 18, count 0 2006.211.07:45:40.53#ibcon#about to read 4, iclass 18, count 0 2006.211.07:45:40.53#ibcon#read 4, iclass 18, count 0 2006.211.07:45:40.53#ibcon#about to read 5, iclass 18, count 0 2006.211.07:45:40.53#ibcon#read 5, iclass 18, count 0 2006.211.07:45:40.53#ibcon#about to read 6, iclass 18, count 0 2006.211.07:45:40.53#ibcon#read 6, iclass 18, count 0 2006.211.07:45:40.53#ibcon#end of sib2, iclass 18, count 0 2006.211.07:45:40.53#ibcon#*after write, iclass 18, count 0 2006.211.07:45:40.53#ibcon#*before return 0, iclass 18, count 0 2006.211.07:45:40.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:40.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:45:40.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:45:40.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:45:40.53$vc4f8/vb=2,4 2006.211.07:45:40.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:45:40.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:45:40.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:40.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:40.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:40.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:40.59#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:45:40.59#ibcon#first serial, iclass 20, count 2 2006.211.07:45:40.59#ibcon#enter sib2, iclass 20, count 2 2006.211.07:45:40.59#ibcon#flushed, iclass 20, count 2 2006.211.07:45:40.59#ibcon#about to write, iclass 20, count 2 2006.211.07:45:40.59#ibcon#wrote, iclass 20, count 2 2006.211.07:45:40.59#ibcon#about to read 3, iclass 20, count 2 2006.211.07:45:40.61#ibcon#read 3, iclass 20, count 2 2006.211.07:45:40.61#ibcon#about to read 4, iclass 20, count 2 2006.211.07:45:40.61#ibcon#read 4, iclass 20, count 2 2006.211.07:45:40.61#ibcon#about to read 5, iclass 20, count 2 2006.211.07:45:40.61#ibcon#read 5, iclass 20, count 2 2006.211.07:45:40.61#ibcon#about to read 6, iclass 20, count 2 2006.211.07:45:40.61#ibcon#read 6, iclass 20, count 2 2006.211.07:45:40.61#ibcon#end of sib2, iclass 20, count 2 2006.211.07:45:40.61#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:45:40.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:45:40.61#ibcon#[27=AT02-04\r\n] 2006.211.07:45:40.61#ibcon#*before write, iclass 20, count 2 2006.211.07:45:40.61#ibcon#enter sib2, iclass 20, count 2 2006.211.07:45:40.61#ibcon#flushed, iclass 20, count 2 2006.211.07:45:40.61#ibcon#about to write, iclass 20, count 2 2006.211.07:45:40.61#ibcon#wrote, iclass 20, count 2 2006.211.07:45:40.61#ibcon#about to read 3, iclass 20, count 2 2006.211.07:45:40.64#ibcon#read 3, iclass 20, count 2 2006.211.07:45:40.64#ibcon#about to read 4, iclass 20, count 2 2006.211.07:45:40.64#ibcon#read 4, iclass 20, count 2 2006.211.07:45:40.64#ibcon#about to read 5, iclass 20, count 2 2006.211.07:45:40.64#ibcon#read 5, iclass 20, count 2 2006.211.07:45:40.64#ibcon#about to read 6, iclass 20, count 2 2006.211.07:45:40.64#ibcon#read 6, iclass 20, count 2 2006.211.07:45:40.64#ibcon#end of sib2, iclass 20, count 2 2006.211.07:45:40.64#ibcon#*after write, iclass 20, count 2 2006.211.07:45:40.64#ibcon#*before return 0, iclass 20, count 2 2006.211.07:45:40.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:40.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:45:40.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:45:40.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:40.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:40.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:40.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:40.76#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:45:40.76#ibcon#first serial, iclass 20, count 0 2006.211.07:45:40.76#ibcon#enter sib2, iclass 20, count 0 2006.211.07:45:40.76#ibcon#flushed, iclass 20, count 0 2006.211.07:45:40.76#ibcon#about to write, iclass 20, count 0 2006.211.07:45:40.76#ibcon#wrote, iclass 20, count 0 2006.211.07:45:40.76#ibcon#about to read 3, iclass 20, count 0 2006.211.07:45:40.78#ibcon#read 3, iclass 20, count 0 2006.211.07:45:40.78#ibcon#about to read 4, iclass 20, count 0 2006.211.07:45:40.78#ibcon#read 4, iclass 20, count 0 2006.211.07:45:40.78#ibcon#about to read 5, iclass 20, count 0 2006.211.07:45:40.78#ibcon#read 5, iclass 20, count 0 2006.211.07:45:40.78#ibcon#about to read 6, iclass 20, count 0 2006.211.07:45:40.78#ibcon#read 6, iclass 20, count 0 2006.211.07:45:40.78#ibcon#end of sib2, iclass 20, count 0 2006.211.07:45:40.78#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:45:40.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:45:40.78#ibcon#[27=USB\r\n] 2006.211.07:45:40.78#ibcon#*before write, iclass 20, count 0 2006.211.07:45:40.78#ibcon#enter sib2, iclass 20, count 0 2006.211.07:45:40.78#ibcon#flushed, iclass 20, count 0 2006.211.07:45:40.78#ibcon#about to write, iclass 20, count 0 2006.211.07:45:40.78#ibcon#wrote, iclass 20, count 0 2006.211.07:45:40.78#ibcon#about to read 3, iclass 20, count 0 2006.211.07:45:40.81#ibcon#read 3, iclass 20, count 0 2006.211.07:45:40.81#ibcon#about to read 4, iclass 20, count 0 2006.211.07:45:40.81#ibcon#read 4, iclass 20, count 0 2006.211.07:45:40.81#ibcon#about to read 5, iclass 20, count 0 2006.211.07:45:40.81#ibcon#read 5, iclass 20, count 0 2006.211.07:45:40.81#ibcon#about to read 6, iclass 20, count 0 2006.211.07:45:40.81#ibcon#read 6, iclass 20, count 0 2006.211.07:45:40.81#ibcon#end of sib2, iclass 20, count 0 2006.211.07:45:40.81#ibcon#*after write, iclass 20, count 0 2006.211.07:45:40.81#ibcon#*before return 0, iclass 20, count 0 2006.211.07:45:40.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:40.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:45:40.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:45:40.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:45:40.81$vc4f8/vblo=3,656.99 2006.211.07:45:40.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:45:40.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:45:40.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:40.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:40.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:40.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:40.81#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:45:40.81#ibcon#first serial, iclass 22, count 0 2006.211.07:45:40.81#ibcon#enter sib2, iclass 22, count 0 2006.211.07:45:40.81#ibcon#flushed, iclass 22, count 0 2006.211.07:45:40.81#ibcon#about to write, iclass 22, count 0 2006.211.07:45:40.81#ibcon#wrote, iclass 22, count 0 2006.211.07:45:40.81#ibcon#about to read 3, iclass 22, count 0 2006.211.07:45:40.83#ibcon#read 3, iclass 22, count 0 2006.211.07:45:40.83#ibcon#about to read 4, iclass 22, count 0 2006.211.07:45:40.83#ibcon#read 4, iclass 22, count 0 2006.211.07:45:40.83#ibcon#about to read 5, iclass 22, count 0 2006.211.07:45:40.83#ibcon#read 5, iclass 22, count 0 2006.211.07:45:40.83#ibcon#about to read 6, iclass 22, count 0 2006.211.07:45:40.83#ibcon#read 6, iclass 22, count 0 2006.211.07:45:40.83#ibcon#end of sib2, iclass 22, count 0 2006.211.07:45:40.83#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:45:40.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:45:40.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:45:40.83#ibcon#*before write, iclass 22, count 0 2006.211.07:45:40.83#ibcon#enter sib2, iclass 22, count 0 2006.211.07:45:40.83#ibcon#flushed, iclass 22, count 0 2006.211.07:45:40.83#ibcon#about to write, iclass 22, count 0 2006.211.07:45:40.83#ibcon#wrote, iclass 22, count 0 2006.211.07:45:40.83#ibcon#about to read 3, iclass 22, count 0 2006.211.07:45:40.87#ibcon#read 3, iclass 22, count 0 2006.211.07:45:40.87#ibcon#about to read 4, iclass 22, count 0 2006.211.07:45:40.87#ibcon#read 4, iclass 22, count 0 2006.211.07:45:40.87#ibcon#about to read 5, iclass 22, count 0 2006.211.07:45:40.87#ibcon#read 5, iclass 22, count 0 2006.211.07:45:40.87#ibcon#about to read 6, iclass 22, count 0 2006.211.07:45:40.87#ibcon#read 6, iclass 22, count 0 2006.211.07:45:40.87#ibcon#end of sib2, iclass 22, count 0 2006.211.07:45:40.87#ibcon#*after write, iclass 22, count 0 2006.211.07:45:40.87#ibcon#*before return 0, iclass 22, count 0 2006.211.07:45:40.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:40.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:45:40.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:45:40.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:45:40.87$vc4f8/vb=3,3 2006.211.07:45:40.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:45:40.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:45:40.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:40.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:40.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:40.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:40.93#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:45:40.93#ibcon#first serial, iclass 24, count 2 2006.211.07:45:40.93#ibcon#enter sib2, iclass 24, count 2 2006.211.07:45:40.93#ibcon#flushed, iclass 24, count 2 2006.211.07:45:40.93#ibcon#about to write, iclass 24, count 2 2006.211.07:45:40.93#ibcon#wrote, iclass 24, count 2 2006.211.07:45:40.93#ibcon#about to read 3, iclass 24, count 2 2006.211.07:45:40.95#ibcon#read 3, iclass 24, count 2 2006.211.07:45:40.95#ibcon#about to read 4, iclass 24, count 2 2006.211.07:45:40.95#ibcon#read 4, iclass 24, count 2 2006.211.07:45:40.95#ibcon#about to read 5, iclass 24, count 2 2006.211.07:45:40.95#ibcon#read 5, iclass 24, count 2 2006.211.07:45:40.95#ibcon#about to read 6, iclass 24, count 2 2006.211.07:45:40.95#ibcon#read 6, iclass 24, count 2 2006.211.07:45:40.95#ibcon#end of sib2, iclass 24, count 2 2006.211.07:45:40.95#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:45:40.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:45:40.95#ibcon#[27=AT03-03\r\n] 2006.211.07:45:40.95#ibcon#*before write, iclass 24, count 2 2006.211.07:45:40.95#ibcon#enter sib2, iclass 24, count 2 2006.211.07:45:40.95#ibcon#flushed, iclass 24, count 2 2006.211.07:45:40.95#ibcon#about to write, iclass 24, count 2 2006.211.07:45:40.95#ibcon#wrote, iclass 24, count 2 2006.211.07:45:40.95#ibcon#about to read 3, iclass 24, count 2 2006.211.07:45:40.98#ibcon#read 3, iclass 24, count 2 2006.211.07:45:40.98#ibcon#about to read 4, iclass 24, count 2 2006.211.07:45:40.98#ibcon#read 4, iclass 24, count 2 2006.211.07:45:40.98#ibcon#about to read 5, iclass 24, count 2 2006.211.07:45:40.98#ibcon#read 5, iclass 24, count 2 2006.211.07:45:40.98#ibcon#about to read 6, iclass 24, count 2 2006.211.07:45:40.98#ibcon#read 6, iclass 24, count 2 2006.211.07:45:40.98#ibcon#end of sib2, iclass 24, count 2 2006.211.07:45:40.98#ibcon#*after write, iclass 24, count 2 2006.211.07:45:40.98#ibcon#*before return 0, iclass 24, count 2 2006.211.07:45:40.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:40.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:45:40.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:45:40.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:40.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:41.00#abcon#<5=/04 4.710.4 24.94 771010.1\r\n> 2006.211.07:45:41.02#abcon#{5=INTERFACE CLEAR} 2006.211.07:45:41.08#abcon#[5=S1D000X0/0*\r\n] 2006.211.07:45:41.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:41.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:41.10#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:45:41.10#ibcon#first serial, iclass 24, count 0 2006.211.07:45:41.10#ibcon#enter sib2, iclass 24, count 0 2006.211.07:45:41.10#ibcon#flushed, iclass 24, count 0 2006.211.07:45:41.10#ibcon#about to write, iclass 24, count 0 2006.211.07:45:41.10#ibcon#wrote, iclass 24, count 0 2006.211.07:45:41.10#ibcon#about to read 3, iclass 24, count 0 2006.211.07:45:41.12#ibcon#read 3, iclass 24, count 0 2006.211.07:45:41.12#ibcon#about to read 4, iclass 24, count 0 2006.211.07:45:41.12#ibcon#read 4, iclass 24, count 0 2006.211.07:45:41.12#ibcon#about to read 5, iclass 24, count 0 2006.211.07:45:41.12#ibcon#read 5, iclass 24, count 0 2006.211.07:45:41.12#ibcon#about to read 6, iclass 24, count 0 2006.211.07:45:41.12#ibcon#read 6, iclass 24, count 0 2006.211.07:45:41.12#ibcon#end of sib2, iclass 24, count 0 2006.211.07:45:41.12#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:45:41.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:45:41.12#ibcon#[27=USB\r\n] 2006.211.07:45:41.12#ibcon#*before write, iclass 24, count 0 2006.211.07:45:41.12#ibcon#enter sib2, iclass 24, count 0 2006.211.07:45:41.12#ibcon#flushed, iclass 24, count 0 2006.211.07:45:41.12#ibcon#about to write, iclass 24, count 0 2006.211.07:45:41.12#ibcon#wrote, iclass 24, count 0 2006.211.07:45:41.12#ibcon#about to read 3, iclass 24, count 0 2006.211.07:45:41.15#ibcon#read 3, iclass 24, count 0 2006.211.07:45:41.15#ibcon#about to read 4, iclass 24, count 0 2006.211.07:45:41.15#ibcon#read 4, iclass 24, count 0 2006.211.07:45:41.15#ibcon#about to read 5, iclass 24, count 0 2006.211.07:45:41.15#ibcon#read 5, iclass 24, count 0 2006.211.07:45:41.15#ibcon#about to read 6, iclass 24, count 0 2006.211.07:45:41.15#ibcon#read 6, iclass 24, count 0 2006.211.07:45:41.15#ibcon#end of sib2, iclass 24, count 0 2006.211.07:45:41.15#ibcon#*after write, iclass 24, count 0 2006.211.07:45:41.15#ibcon#*before return 0, iclass 24, count 0 2006.211.07:45:41.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:41.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:45:41.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:45:41.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:45:41.15$vc4f8/vblo=4,712.99 2006.211.07:45:41.15#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.07:45:41.15#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.07:45:41.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:41.15#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:41.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:41.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:41.15#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:45:41.15#ibcon#first serial, iclass 30, count 0 2006.211.07:45:41.15#ibcon#enter sib2, iclass 30, count 0 2006.211.07:45:41.15#ibcon#flushed, iclass 30, count 0 2006.211.07:45:41.15#ibcon#about to write, iclass 30, count 0 2006.211.07:45:41.15#ibcon#wrote, iclass 30, count 0 2006.211.07:45:41.15#ibcon#about to read 3, iclass 30, count 0 2006.211.07:45:41.17#ibcon#read 3, iclass 30, count 0 2006.211.07:45:41.17#ibcon#about to read 4, iclass 30, count 0 2006.211.07:45:41.17#ibcon#read 4, iclass 30, count 0 2006.211.07:45:41.17#ibcon#about to read 5, iclass 30, count 0 2006.211.07:45:41.17#ibcon#read 5, iclass 30, count 0 2006.211.07:45:41.17#ibcon#about to read 6, iclass 30, count 0 2006.211.07:45:41.17#ibcon#read 6, iclass 30, count 0 2006.211.07:45:41.17#ibcon#end of sib2, iclass 30, count 0 2006.211.07:45:41.17#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:45:41.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:45:41.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:45:41.17#ibcon#*before write, iclass 30, count 0 2006.211.07:45:41.17#ibcon#enter sib2, iclass 30, count 0 2006.211.07:45:41.17#ibcon#flushed, iclass 30, count 0 2006.211.07:45:41.17#ibcon#about to write, iclass 30, count 0 2006.211.07:45:41.17#ibcon#wrote, iclass 30, count 0 2006.211.07:45:41.17#ibcon#about to read 3, iclass 30, count 0 2006.211.07:45:41.21#ibcon#read 3, iclass 30, count 0 2006.211.07:45:41.21#ibcon#about to read 4, iclass 30, count 0 2006.211.07:45:41.21#ibcon#read 4, iclass 30, count 0 2006.211.07:45:41.21#ibcon#about to read 5, iclass 30, count 0 2006.211.07:45:41.21#ibcon#read 5, iclass 30, count 0 2006.211.07:45:41.21#ibcon#about to read 6, iclass 30, count 0 2006.211.07:45:41.21#ibcon#read 6, iclass 30, count 0 2006.211.07:45:41.21#ibcon#end of sib2, iclass 30, count 0 2006.211.07:45:41.21#ibcon#*after write, iclass 30, count 0 2006.211.07:45:41.21#ibcon#*before return 0, iclass 30, count 0 2006.211.07:45:41.21#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:41.21#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:45:41.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:45:41.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:45:41.21$vc4f8/vb=4,3 2006.211.07:45:41.21#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.07:45:41.21#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.07:45:41.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:41.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:41.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:41.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:41.27#ibcon#enter wrdev, iclass 32, count 2 2006.211.07:45:41.27#ibcon#first serial, iclass 32, count 2 2006.211.07:45:41.27#ibcon#enter sib2, iclass 32, count 2 2006.211.07:45:41.27#ibcon#flushed, iclass 32, count 2 2006.211.07:45:41.27#ibcon#about to write, iclass 32, count 2 2006.211.07:45:41.27#ibcon#wrote, iclass 32, count 2 2006.211.07:45:41.27#ibcon#about to read 3, iclass 32, count 2 2006.211.07:45:41.29#ibcon#read 3, iclass 32, count 2 2006.211.07:45:41.29#ibcon#about to read 4, iclass 32, count 2 2006.211.07:45:41.29#ibcon#read 4, iclass 32, count 2 2006.211.07:45:41.29#ibcon#about to read 5, iclass 32, count 2 2006.211.07:45:41.29#ibcon#read 5, iclass 32, count 2 2006.211.07:45:41.29#ibcon#about to read 6, iclass 32, count 2 2006.211.07:45:41.29#ibcon#read 6, iclass 32, count 2 2006.211.07:45:41.29#ibcon#end of sib2, iclass 32, count 2 2006.211.07:45:41.29#ibcon#*mode == 0, iclass 32, count 2 2006.211.07:45:41.29#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.07:45:41.29#ibcon#[27=AT04-03\r\n] 2006.211.07:45:41.29#ibcon#*before write, iclass 32, count 2 2006.211.07:45:41.29#ibcon#enter sib2, iclass 32, count 2 2006.211.07:45:41.29#ibcon#flushed, iclass 32, count 2 2006.211.07:45:41.29#ibcon#about to write, iclass 32, count 2 2006.211.07:45:41.29#ibcon#wrote, iclass 32, count 2 2006.211.07:45:41.29#ibcon#about to read 3, iclass 32, count 2 2006.211.07:45:41.32#ibcon#read 3, iclass 32, count 2 2006.211.07:45:41.32#ibcon#about to read 4, iclass 32, count 2 2006.211.07:45:41.32#ibcon#read 4, iclass 32, count 2 2006.211.07:45:41.32#ibcon#about to read 5, iclass 32, count 2 2006.211.07:45:41.32#ibcon#read 5, iclass 32, count 2 2006.211.07:45:41.32#ibcon#about to read 6, iclass 32, count 2 2006.211.07:45:41.32#ibcon#read 6, iclass 32, count 2 2006.211.07:45:41.32#ibcon#end of sib2, iclass 32, count 2 2006.211.07:45:41.32#ibcon#*after write, iclass 32, count 2 2006.211.07:45:41.32#ibcon#*before return 0, iclass 32, count 2 2006.211.07:45:41.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:41.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:45:41.32#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.07:45:41.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:41.32#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:41.44#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:41.44#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:41.44#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:45:41.44#ibcon#first serial, iclass 32, count 0 2006.211.07:45:41.44#ibcon#enter sib2, iclass 32, count 0 2006.211.07:45:41.44#ibcon#flushed, iclass 32, count 0 2006.211.07:45:41.44#ibcon#about to write, iclass 32, count 0 2006.211.07:45:41.44#ibcon#wrote, iclass 32, count 0 2006.211.07:45:41.44#ibcon#about to read 3, iclass 32, count 0 2006.211.07:45:41.46#ibcon#read 3, iclass 32, count 0 2006.211.07:45:41.46#ibcon#about to read 4, iclass 32, count 0 2006.211.07:45:41.46#ibcon#read 4, iclass 32, count 0 2006.211.07:45:41.46#ibcon#about to read 5, iclass 32, count 0 2006.211.07:45:41.46#ibcon#read 5, iclass 32, count 0 2006.211.07:45:41.46#ibcon#about to read 6, iclass 32, count 0 2006.211.07:45:41.46#ibcon#read 6, iclass 32, count 0 2006.211.07:45:41.46#ibcon#end of sib2, iclass 32, count 0 2006.211.07:45:41.46#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:45:41.46#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:45:41.46#ibcon#[27=USB\r\n] 2006.211.07:45:41.46#ibcon#*before write, iclass 32, count 0 2006.211.07:45:41.46#ibcon#enter sib2, iclass 32, count 0 2006.211.07:45:41.46#ibcon#flushed, iclass 32, count 0 2006.211.07:45:41.46#ibcon#about to write, iclass 32, count 0 2006.211.07:45:41.46#ibcon#wrote, iclass 32, count 0 2006.211.07:45:41.46#ibcon#about to read 3, iclass 32, count 0 2006.211.07:45:41.49#ibcon#read 3, iclass 32, count 0 2006.211.07:45:41.49#ibcon#about to read 4, iclass 32, count 0 2006.211.07:45:41.49#ibcon#read 4, iclass 32, count 0 2006.211.07:45:41.49#ibcon#about to read 5, iclass 32, count 0 2006.211.07:45:41.49#ibcon#read 5, iclass 32, count 0 2006.211.07:45:41.49#ibcon#about to read 6, iclass 32, count 0 2006.211.07:45:41.49#ibcon#read 6, iclass 32, count 0 2006.211.07:45:41.49#ibcon#end of sib2, iclass 32, count 0 2006.211.07:45:41.49#ibcon#*after write, iclass 32, count 0 2006.211.07:45:41.49#ibcon#*before return 0, iclass 32, count 0 2006.211.07:45:41.49#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:41.49#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:45:41.49#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:45:41.49#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:45:41.49$vc4f8/vblo=5,744.99 2006.211.07:45:41.49#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.07:45:41.49#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.07:45:41.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:41.49#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:41.49#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:41.49#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:41.49#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:45:41.49#ibcon#first serial, iclass 34, count 0 2006.211.07:45:41.49#ibcon#enter sib2, iclass 34, count 0 2006.211.07:45:41.49#ibcon#flushed, iclass 34, count 0 2006.211.07:45:41.49#ibcon#about to write, iclass 34, count 0 2006.211.07:45:41.49#ibcon#wrote, iclass 34, count 0 2006.211.07:45:41.49#ibcon#about to read 3, iclass 34, count 0 2006.211.07:45:41.51#ibcon#read 3, iclass 34, count 0 2006.211.07:45:41.51#ibcon#about to read 4, iclass 34, count 0 2006.211.07:45:41.51#ibcon#read 4, iclass 34, count 0 2006.211.07:45:41.51#ibcon#about to read 5, iclass 34, count 0 2006.211.07:45:41.51#ibcon#read 5, iclass 34, count 0 2006.211.07:45:41.51#ibcon#about to read 6, iclass 34, count 0 2006.211.07:45:41.51#ibcon#read 6, iclass 34, count 0 2006.211.07:45:41.51#ibcon#end of sib2, iclass 34, count 0 2006.211.07:45:41.51#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:45:41.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:45:41.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:45:41.51#ibcon#*before write, iclass 34, count 0 2006.211.07:45:41.51#ibcon#enter sib2, iclass 34, count 0 2006.211.07:45:41.51#ibcon#flushed, iclass 34, count 0 2006.211.07:45:41.51#ibcon#about to write, iclass 34, count 0 2006.211.07:45:41.51#ibcon#wrote, iclass 34, count 0 2006.211.07:45:41.51#ibcon#about to read 3, iclass 34, count 0 2006.211.07:45:41.55#ibcon#read 3, iclass 34, count 0 2006.211.07:45:41.55#ibcon#about to read 4, iclass 34, count 0 2006.211.07:45:41.55#ibcon#read 4, iclass 34, count 0 2006.211.07:45:41.55#ibcon#about to read 5, iclass 34, count 0 2006.211.07:45:41.55#ibcon#read 5, iclass 34, count 0 2006.211.07:45:41.55#ibcon#about to read 6, iclass 34, count 0 2006.211.07:45:41.55#ibcon#read 6, iclass 34, count 0 2006.211.07:45:41.55#ibcon#end of sib2, iclass 34, count 0 2006.211.07:45:41.55#ibcon#*after write, iclass 34, count 0 2006.211.07:45:41.55#ibcon#*before return 0, iclass 34, count 0 2006.211.07:45:41.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:41.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:45:41.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:45:41.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:45:41.55$vc4f8/vb=5,3 2006.211.07:45:41.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.07:45:41.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.07:45:41.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:41.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:41.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:41.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:41.61#ibcon#enter wrdev, iclass 36, count 2 2006.211.07:45:41.61#ibcon#first serial, iclass 36, count 2 2006.211.07:45:41.61#ibcon#enter sib2, iclass 36, count 2 2006.211.07:45:41.61#ibcon#flushed, iclass 36, count 2 2006.211.07:45:41.61#ibcon#about to write, iclass 36, count 2 2006.211.07:45:41.61#ibcon#wrote, iclass 36, count 2 2006.211.07:45:41.61#ibcon#about to read 3, iclass 36, count 2 2006.211.07:45:41.63#ibcon#read 3, iclass 36, count 2 2006.211.07:45:41.63#ibcon#about to read 4, iclass 36, count 2 2006.211.07:45:41.63#ibcon#read 4, iclass 36, count 2 2006.211.07:45:41.63#ibcon#about to read 5, iclass 36, count 2 2006.211.07:45:41.63#ibcon#read 5, iclass 36, count 2 2006.211.07:45:41.63#ibcon#about to read 6, iclass 36, count 2 2006.211.07:45:41.63#ibcon#read 6, iclass 36, count 2 2006.211.07:45:41.63#ibcon#end of sib2, iclass 36, count 2 2006.211.07:45:41.63#ibcon#*mode == 0, iclass 36, count 2 2006.211.07:45:41.63#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.07:45:41.63#ibcon#[27=AT05-03\r\n] 2006.211.07:45:41.63#ibcon#*before write, iclass 36, count 2 2006.211.07:45:41.63#ibcon#enter sib2, iclass 36, count 2 2006.211.07:45:41.63#ibcon#flushed, iclass 36, count 2 2006.211.07:45:41.63#ibcon#about to write, iclass 36, count 2 2006.211.07:45:41.63#ibcon#wrote, iclass 36, count 2 2006.211.07:45:41.63#ibcon#about to read 3, iclass 36, count 2 2006.211.07:45:41.66#ibcon#read 3, iclass 36, count 2 2006.211.07:45:41.66#ibcon#about to read 4, iclass 36, count 2 2006.211.07:45:41.66#ibcon#read 4, iclass 36, count 2 2006.211.07:45:41.66#ibcon#about to read 5, iclass 36, count 2 2006.211.07:45:41.66#ibcon#read 5, iclass 36, count 2 2006.211.07:45:41.66#ibcon#about to read 6, iclass 36, count 2 2006.211.07:45:41.66#ibcon#read 6, iclass 36, count 2 2006.211.07:45:41.66#ibcon#end of sib2, iclass 36, count 2 2006.211.07:45:41.66#ibcon#*after write, iclass 36, count 2 2006.211.07:45:41.66#ibcon#*before return 0, iclass 36, count 2 2006.211.07:45:41.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:41.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.07:45:41.66#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.07:45:41.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:41.66#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:41.78#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:41.78#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:41.78#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:45:41.78#ibcon#first serial, iclass 36, count 0 2006.211.07:45:41.78#ibcon#enter sib2, iclass 36, count 0 2006.211.07:45:41.78#ibcon#flushed, iclass 36, count 0 2006.211.07:45:41.78#ibcon#about to write, iclass 36, count 0 2006.211.07:45:41.78#ibcon#wrote, iclass 36, count 0 2006.211.07:45:41.78#ibcon#about to read 3, iclass 36, count 0 2006.211.07:45:41.80#ibcon#read 3, iclass 36, count 0 2006.211.07:45:41.80#ibcon#about to read 4, iclass 36, count 0 2006.211.07:45:41.80#ibcon#read 4, iclass 36, count 0 2006.211.07:45:41.80#ibcon#about to read 5, iclass 36, count 0 2006.211.07:45:41.80#ibcon#read 5, iclass 36, count 0 2006.211.07:45:41.80#ibcon#about to read 6, iclass 36, count 0 2006.211.07:45:41.80#ibcon#read 6, iclass 36, count 0 2006.211.07:45:41.80#ibcon#end of sib2, iclass 36, count 0 2006.211.07:45:41.80#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:45:41.80#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:45:41.80#ibcon#[27=USB\r\n] 2006.211.07:45:41.80#ibcon#*before write, iclass 36, count 0 2006.211.07:45:41.80#ibcon#enter sib2, iclass 36, count 0 2006.211.07:45:41.80#ibcon#flushed, iclass 36, count 0 2006.211.07:45:41.80#ibcon#about to write, iclass 36, count 0 2006.211.07:45:41.80#ibcon#wrote, iclass 36, count 0 2006.211.07:45:41.80#ibcon#about to read 3, iclass 36, count 0 2006.211.07:45:41.83#ibcon#read 3, iclass 36, count 0 2006.211.07:45:41.83#ibcon#about to read 4, iclass 36, count 0 2006.211.07:45:41.83#ibcon#read 4, iclass 36, count 0 2006.211.07:45:41.83#ibcon#about to read 5, iclass 36, count 0 2006.211.07:45:41.83#ibcon#read 5, iclass 36, count 0 2006.211.07:45:41.83#ibcon#about to read 6, iclass 36, count 0 2006.211.07:45:41.83#ibcon#read 6, iclass 36, count 0 2006.211.07:45:41.83#ibcon#end of sib2, iclass 36, count 0 2006.211.07:45:41.83#ibcon#*after write, iclass 36, count 0 2006.211.07:45:41.83#ibcon#*before return 0, iclass 36, count 0 2006.211.07:45:41.83#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:41.83#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.07:45:41.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:45:41.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:45:41.83$vc4f8/vblo=6,752.99 2006.211.07:45:41.83#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.07:45:41.83#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.07:45:41.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:45:41.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:41.83#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:41.83#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:41.83#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:45:41.83#ibcon#first serial, iclass 38, count 0 2006.211.07:45:41.83#ibcon#enter sib2, iclass 38, count 0 2006.211.07:45:41.83#ibcon#flushed, iclass 38, count 0 2006.211.07:45:41.83#ibcon#about to write, iclass 38, count 0 2006.211.07:45:41.83#ibcon#wrote, iclass 38, count 0 2006.211.07:45:41.83#ibcon#about to read 3, iclass 38, count 0 2006.211.07:45:41.85#ibcon#read 3, iclass 38, count 0 2006.211.07:45:41.85#ibcon#about to read 4, iclass 38, count 0 2006.211.07:45:41.85#ibcon#read 4, iclass 38, count 0 2006.211.07:45:41.85#ibcon#about to read 5, iclass 38, count 0 2006.211.07:45:41.85#ibcon#read 5, iclass 38, count 0 2006.211.07:45:41.85#ibcon#about to read 6, iclass 38, count 0 2006.211.07:45:41.85#ibcon#read 6, iclass 38, count 0 2006.211.07:45:41.85#ibcon#end of sib2, iclass 38, count 0 2006.211.07:45:41.85#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:45:41.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:45:41.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:45:41.85#ibcon#*before write, iclass 38, count 0 2006.211.07:45:41.85#ibcon#enter sib2, iclass 38, count 0 2006.211.07:45:41.85#ibcon#flushed, iclass 38, count 0 2006.211.07:45:41.85#ibcon#about to write, iclass 38, count 0 2006.211.07:45:41.85#ibcon#wrote, iclass 38, count 0 2006.211.07:45:41.85#ibcon#about to read 3, iclass 38, count 0 2006.211.07:45:41.89#ibcon#read 3, iclass 38, count 0 2006.211.07:45:41.89#ibcon#about to read 4, iclass 38, count 0 2006.211.07:45:41.89#ibcon#read 4, iclass 38, count 0 2006.211.07:45:41.89#ibcon#about to read 5, iclass 38, count 0 2006.211.07:45:41.89#ibcon#read 5, iclass 38, count 0 2006.211.07:45:41.89#ibcon#about to read 6, iclass 38, count 0 2006.211.07:45:41.89#ibcon#read 6, iclass 38, count 0 2006.211.07:45:41.89#ibcon#end of sib2, iclass 38, count 0 2006.211.07:45:41.89#ibcon#*after write, iclass 38, count 0 2006.211.07:45:41.89#ibcon#*before return 0, iclass 38, count 0 2006.211.07:45:41.89#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:41.89#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.07:45:41.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:45:41.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:45:41.89$vc4f8/vb=6,3 2006.211.07:45:41.89#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.07:45:41.89#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.07:45:41.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:45:41.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:41.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:41.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:41.95#ibcon#enter wrdev, iclass 40, count 2 2006.211.07:45:41.95#ibcon#first serial, iclass 40, count 2 2006.211.07:45:41.95#ibcon#enter sib2, iclass 40, count 2 2006.211.07:45:41.95#ibcon#flushed, iclass 40, count 2 2006.211.07:45:41.95#ibcon#about to write, iclass 40, count 2 2006.211.07:45:41.95#ibcon#wrote, iclass 40, count 2 2006.211.07:45:41.95#ibcon#about to read 3, iclass 40, count 2 2006.211.07:45:41.97#ibcon#read 3, iclass 40, count 2 2006.211.07:45:41.97#ibcon#about to read 4, iclass 40, count 2 2006.211.07:45:41.97#ibcon#read 4, iclass 40, count 2 2006.211.07:45:41.97#ibcon#about to read 5, iclass 40, count 2 2006.211.07:45:41.97#ibcon#read 5, iclass 40, count 2 2006.211.07:45:41.97#ibcon#about to read 6, iclass 40, count 2 2006.211.07:45:41.97#ibcon#read 6, iclass 40, count 2 2006.211.07:45:41.97#ibcon#end of sib2, iclass 40, count 2 2006.211.07:45:41.97#ibcon#*mode == 0, iclass 40, count 2 2006.211.07:45:41.97#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.07:45:41.97#ibcon#[27=AT06-03\r\n] 2006.211.07:45:41.97#ibcon#*before write, iclass 40, count 2 2006.211.07:45:41.97#ibcon#enter sib2, iclass 40, count 2 2006.211.07:45:41.97#ibcon#flushed, iclass 40, count 2 2006.211.07:45:41.97#ibcon#about to write, iclass 40, count 2 2006.211.07:45:41.97#ibcon#wrote, iclass 40, count 2 2006.211.07:45:41.97#ibcon#about to read 3, iclass 40, count 2 2006.211.07:45:42.00#ibcon#read 3, iclass 40, count 2 2006.211.07:45:42.00#ibcon#about to read 4, iclass 40, count 2 2006.211.07:45:42.00#ibcon#read 4, iclass 40, count 2 2006.211.07:45:42.00#ibcon#about to read 5, iclass 40, count 2 2006.211.07:45:42.00#ibcon#read 5, iclass 40, count 2 2006.211.07:45:42.00#ibcon#about to read 6, iclass 40, count 2 2006.211.07:45:42.00#ibcon#read 6, iclass 40, count 2 2006.211.07:45:42.00#ibcon#end of sib2, iclass 40, count 2 2006.211.07:45:42.00#ibcon#*after write, iclass 40, count 2 2006.211.07:45:42.00#ibcon#*before return 0, iclass 40, count 2 2006.211.07:45:42.00#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:42.00#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.07:45:42.00#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.07:45:42.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:45:42.00#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:42.12#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:42.12#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:42.12#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:45:42.12#ibcon#first serial, iclass 40, count 0 2006.211.07:45:42.12#ibcon#enter sib2, iclass 40, count 0 2006.211.07:45:42.12#ibcon#flushed, iclass 40, count 0 2006.211.07:45:42.12#ibcon#about to write, iclass 40, count 0 2006.211.07:45:42.12#ibcon#wrote, iclass 40, count 0 2006.211.07:45:42.12#ibcon#about to read 3, iclass 40, count 0 2006.211.07:45:42.14#ibcon#read 3, iclass 40, count 0 2006.211.07:45:42.14#ibcon#about to read 4, iclass 40, count 0 2006.211.07:45:42.14#ibcon#read 4, iclass 40, count 0 2006.211.07:45:42.14#ibcon#about to read 5, iclass 40, count 0 2006.211.07:45:42.14#ibcon#read 5, iclass 40, count 0 2006.211.07:45:42.14#ibcon#about to read 6, iclass 40, count 0 2006.211.07:45:42.14#ibcon#read 6, iclass 40, count 0 2006.211.07:45:42.14#ibcon#end of sib2, iclass 40, count 0 2006.211.07:45:42.14#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:45:42.14#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:45:42.14#ibcon#[27=USB\r\n] 2006.211.07:45:42.14#ibcon#*before write, iclass 40, count 0 2006.211.07:45:42.14#ibcon#enter sib2, iclass 40, count 0 2006.211.07:45:42.14#ibcon#flushed, iclass 40, count 0 2006.211.07:45:42.14#ibcon#about to write, iclass 40, count 0 2006.211.07:45:42.14#ibcon#wrote, iclass 40, count 0 2006.211.07:45:42.14#ibcon#about to read 3, iclass 40, count 0 2006.211.07:45:42.17#ibcon#read 3, iclass 40, count 0 2006.211.07:45:42.17#ibcon#about to read 4, iclass 40, count 0 2006.211.07:45:42.17#ibcon#read 4, iclass 40, count 0 2006.211.07:45:42.17#ibcon#about to read 5, iclass 40, count 0 2006.211.07:45:42.17#ibcon#read 5, iclass 40, count 0 2006.211.07:45:42.17#ibcon#about to read 6, iclass 40, count 0 2006.211.07:45:42.17#ibcon#read 6, iclass 40, count 0 2006.211.07:45:42.17#ibcon#end of sib2, iclass 40, count 0 2006.211.07:45:42.17#ibcon#*after write, iclass 40, count 0 2006.211.07:45:42.17#ibcon#*before return 0, iclass 40, count 0 2006.211.07:45:42.17#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:42.17#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.07:45:42.17#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:45:42.17#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:45:42.17$vc4f8/vabw=wide 2006.211.07:45:42.17#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.07:45:42.17#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.07:45:42.17#ibcon#ireg 8 cls_cnt 0 2006.211.07:45:42.17#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:42.17#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:42.17#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:42.17#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:45:42.17#ibcon#first serial, iclass 4, count 0 2006.211.07:45:42.17#ibcon#enter sib2, iclass 4, count 0 2006.211.07:45:42.17#ibcon#flushed, iclass 4, count 0 2006.211.07:45:42.17#ibcon#about to write, iclass 4, count 0 2006.211.07:45:42.17#ibcon#wrote, iclass 4, count 0 2006.211.07:45:42.17#ibcon#about to read 3, iclass 4, count 0 2006.211.07:45:42.19#ibcon#read 3, iclass 4, count 0 2006.211.07:45:42.19#ibcon#about to read 4, iclass 4, count 0 2006.211.07:45:42.19#ibcon#read 4, iclass 4, count 0 2006.211.07:45:42.19#ibcon#about to read 5, iclass 4, count 0 2006.211.07:45:42.19#ibcon#read 5, iclass 4, count 0 2006.211.07:45:42.19#ibcon#about to read 6, iclass 4, count 0 2006.211.07:45:42.19#ibcon#read 6, iclass 4, count 0 2006.211.07:45:42.19#ibcon#end of sib2, iclass 4, count 0 2006.211.07:45:42.19#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:45:42.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:45:42.19#ibcon#[25=BW32\r\n] 2006.211.07:45:42.19#ibcon#*before write, iclass 4, count 0 2006.211.07:45:42.19#ibcon#enter sib2, iclass 4, count 0 2006.211.07:45:42.19#ibcon#flushed, iclass 4, count 0 2006.211.07:45:42.19#ibcon#about to write, iclass 4, count 0 2006.211.07:45:42.19#ibcon#wrote, iclass 4, count 0 2006.211.07:45:42.19#ibcon#about to read 3, iclass 4, count 0 2006.211.07:45:42.22#ibcon#read 3, iclass 4, count 0 2006.211.07:45:42.22#ibcon#about to read 4, iclass 4, count 0 2006.211.07:45:42.22#ibcon#read 4, iclass 4, count 0 2006.211.07:45:42.22#ibcon#about to read 5, iclass 4, count 0 2006.211.07:45:42.22#ibcon#read 5, iclass 4, count 0 2006.211.07:45:42.22#ibcon#about to read 6, iclass 4, count 0 2006.211.07:45:42.22#ibcon#read 6, iclass 4, count 0 2006.211.07:45:42.22#ibcon#end of sib2, iclass 4, count 0 2006.211.07:45:42.22#ibcon#*after write, iclass 4, count 0 2006.211.07:45:42.22#ibcon#*before return 0, iclass 4, count 0 2006.211.07:45:42.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:42.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:45:42.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:45:42.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:45:42.22$vc4f8/vbbw=wide 2006.211.07:45:42.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:45:42.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:45:42.22#ibcon#ireg 8 cls_cnt 0 2006.211.07:45:42.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:45:42.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:45:42.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:45:42.29#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:45:42.29#ibcon#first serial, iclass 6, count 0 2006.211.07:45:42.29#ibcon#enter sib2, iclass 6, count 0 2006.211.07:45:42.29#ibcon#flushed, iclass 6, count 0 2006.211.07:45:42.29#ibcon#about to write, iclass 6, count 0 2006.211.07:45:42.29#ibcon#wrote, iclass 6, count 0 2006.211.07:45:42.29#ibcon#about to read 3, iclass 6, count 0 2006.211.07:45:42.31#ibcon#read 3, iclass 6, count 0 2006.211.07:45:42.31#ibcon#about to read 4, iclass 6, count 0 2006.211.07:45:42.31#ibcon#read 4, iclass 6, count 0 2006.211.07:45:42.31#ibcon#about to read 5, iclass 6, count 0 2006.211.07:45:42.31#ibcon#read 5, iclass 6, count 0 2006.211.07:45:42.31#ibcon#about to read 6, iclass 6, count 0 2006.211.07:45:42.31#ibcon#read 6, iclass 6, count 0 2006.211.07:45:42.31#ibcon#end of sib2, iclass 6, count 0 2006.211.07:45:42.31#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:45:42.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:45:42.31#ibcon#[27=BW32\r\n] 2006.211.07:45:42.31#ibcon#*before write, iclass 6, count 0 2006.211.07:45:42.31#ibcon#enter sib2, iclass 6, count 0 2006.211.07:45:42.31#ibcon#flushed, iclass 6, count 0 2006.211.07:45:42.31#ibcon#about to write, iclass 6, count 0 2006.211.07:45:42.31#ibcon#wrote, iclass 6, count 0 2006.211.07:45:42.31#ibcon#about to read 3, iclass 6, count 0 2006.211.07:45:42.34#ibcon#read 3, iclass 6, count 0 2006.211.07:45:42.34#ibcon#about to read 4, iclass 6, count 0 2006.211.07:45:42.34#ibcon#read 4, iclass 6, count 0 2006.211.07:45:42.34#ibcon#about to read 5, iclass 6, count 0 2006.211.07:45:42.34#ibcon#read 5, iclass 6, count 0 2006.211.07:45:42.34#ibcon#about to read 6, iclass 6, count 0 2006.211.07:45:42.34#ibcon#read 6, iclass 6, count 0 2006.211.07:45:42.34#ibcon#end of sib2, iclass 6, count 0 2006.211.07:45:42.34#ibcon#*after write, iclass 6, count 0 2006.211.07:45:42.34#ibcon#*before return 0, iclass 6, count 0 2006.211.07:45:42.34#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:45:42.34#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:45:42.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:45:42.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:45:42.34$4f8m12a/ifd4f 2006.211.07:45:42.34$ifd4f/lo= 2006.211.07:45:42.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:45:42.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:45:42.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:45:42.34$ifd4f/patch= 2006.211.07:45:42.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:45:42.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:45:42.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:45:42.34$4f8m12a/"form=m,16.000,1:2 2006.211.07:45:42.34$4f8m12a/"tpicd 2006.211.07:45:42.34$4f8m12a/echo=off 2006.211.07:45:42.34$4f8m12a/xlog=off 2006.211.07:45:42.34:!2006.211.07:46:40 2006.211.07:46:20.13#trakl#Source acquired 2006.211.07:46:22.13#flagr#flagr/antenna,acquired 2006.211.07:46:40.00:preob 2006.211.07:46:41.13/onsource/TRACKING 2006.211.07:46:41.13:!2006.211.07:46:50 2006.211.07:46:50.00:data_valid=on 2006.211.07:46:50.00:midob 2006.211.07:46:50.13/onsource/TRACKING 2006.211.07:46:50.13/wx/24.95,1010.1,76 2006.211.07:46:50.23/cable/+6.4389E-03 2006.211.07:46:51.32/va/01,08,usb,yes,28,30 2006.211.07:46:51.32/va/02,07,usb,yes,29,30 2006.211.07:46:51.32/va/03,06,usb,yes,30,30 2006.211.07:46:51.32/va/04,07,usb,yes,29,32 2006.211.07:46:51.32/va/05,07,usb,yes,32,33 2006.211.07:46:51.32/va/06,06,usb,yes,31,30 2006.211.07:46:51.32/va/07,06,usb,yes,31,31 2006.211.07:46:51.32/va/08,07,usb,yes,30,29 2006.211.07:46:51.55/valo/01,532.99,yes,locked 2006.211.07:46:51.55/valo/02,572.99,yes,locked 2006.211.07:46:51.55/valo/03,672.99,yes,locked 2006.211.07:46:51.55/valo/04,832.99,yes,locked 2006.211.07:46:51.55/valo/05,652.99,yes,locked 2006.211.07:46:51.55/valo/06,772.99,yes,locked 2006.211.07:46:51.55/valo/07,832.99,yes,locked 2006.211.07:46:51.55/valo/08,852.99,yes,locked 2006.211.07:46:52.64/vb/01,04,usb,yes,28,27 2006.211.07:46:52.64/vb/02,04,usb,yes,30,31 2006.211.07:46:52.64/vb/03,03,usb,yes,33,37 2006.211.07:46:52.64/vb/04,03,usb,yes,34,34 2006.211.07:46:52.64/vb/05,03,usb,yes,32,37 2006.211.07:46:52.64/vb/06,03,usb,yes,33,36 2006.211.07:46:52.64/vb/07,04,usb,yes,29,29 2006.211.07:46:52.64/vb/08,03,usb,yes,33,37 2006.211.07:46:52.87/vblo/01,632.99,yes,locked 2006.211.07:46:52.87/vblo/02,640.99,yes,locked 2006.211.07:46:52.87/vblo/03,656.99,yes,locked 2006.211.07:46:52.87/vblo/04,712.99,yes,locked 2006.211.07:46:52.87/vblo/05,744.99,yes,locked 2006.211.07:46:52.87/vblo/06,752.99,yes,locked 2006.211.07:46:52.87/vblo/07,734.99,yes,locked 2006.211.07:46:52.87/vblo/08,744.99,yes,locked 2006.211.07:46:53.02/vabw/8 2006.211.07:46:53.17/vbbw/8 2006.211.07:46:53.37/xfe/off,on,12.5 2006.211.07:46:53.75/ifatt/23,28,28,28 2006.211.07:46:54.08/fmout-gps/S +4.48E-07 2006.211.07:46:54.12:!2006.211.07:48:30 2006.211.07:48:30.00:data_valid=off 2006.211.07:48:30.00:postob 2006.211.07:48:30.18/cable/+6.4390E-03 2006.211.07:48:30.18/wx/24.96,1010.1,77 2006.211.07:48:31.08/fmout-gps/S +4.48E-07 2006.211.07:48:31.08:scan_name=211-0749,k06211,60 2006.211.07:48:31.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.211.07:48:32.14#flagr#flagr/antenna,new-source 2006.211.07:48:32.14:checkk5 2006.211.07:48:32.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:48:32.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:48:33.18/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:48:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:48:33.85/chk_obsdata//k5ts1/T2110746??a.dat file size is correct (nominal:800MB, actual:792MB). 2006.211.07:48:34.19/chk_obsdata//k5ts2/T2110746??b.dat file size is correct (nominal:800MB, actual:792MB). 2006.211.07:48:34.52/chk_obsdata//k5ts3/T2110746??c.dat file size is correct (nominal:800MB, actual:792MB). 2006.211.07:48:34.87/chk_obsdata//k5ts4/T2110746??d.dat file size is correct (nominal:800MB, actual:792MB). 2006.211.07:48:35.53/k5log//k5ts1_log_newline 2006.211.07:48:36.18/k5log//k5ts2_log_newline 2006.211.07:48:36.84/k5log//k5ts3_log_newline 2006.211.07:48:37.50/k5log//k5ts4_log_newline 2006.211.07:48:37.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:48:37.52:4f8m12a=1 2006.211.07:48:37.52$4f8m12a/echo=on 2006.211.07:48:37.52$4f8m12a/pcalon 2006.211.07:48:37.52$pcalon/"no phase cal control is implemented here 2006.211.07:48:37.52$4f8m12a/"tpicd=stop 2006.211.07:48:37.52$4f8m12a/vc4f8 2006.211.07:48:37.52$vc4f8/valo=1,532.99 2006.211.07:48:37.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.07:48:37.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.07:48:37.52#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:37.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:37.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:37.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:37.52#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:48:37.52#ibcon#first serial, iclass 5, count 0 2006.211.07:48:37.52#ibcon#enter sib2, iclass 5, count 0 2006.211.07:48:37.52#ibcon#flushed, iclass 5, count 0 2006.211.07:48:37.52#ibcon#about to write, iclass 5, count 0 2006.211.07:48:37.52#ibcon#wrote, iclass 5, count 0 2006.211.07:48:37.52#ibcon#about to read 3, iclass 5, count 0 2006.211.07:48:37.54#ibcon#read 3, iclass 5, count 0 2006.211.07:48:37.54#ibcon#about to read 4, iclass 5, count 0 2006.211.07:48:37.54#ibcon#read 4, iclass 5, count 0 2006.211.07:48:37.54#ibcon#about to read 5, iclass 5, count 0 2006.211.07:48:37.54#ibcon#read 5, iclass 5, count 0 2006.211.07:48:37.54#ibcon#about to read 6, iclass 5, count 0 2006.211.07:48:37.54#ibcon#read 6, iclass 5, count 0 2006.211.07:48:37.54#ibcon#end of sib2, iclass 5, count 0 2006.211.07:48:37.54#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:48:37.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:48:37.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:48:37.54#ibcon#*before write, iclass 5, count 0 2006.211.07:48:37.54#ibcon#enter sib2, iclass 5, count 0 2006.211.07:48:37.54#ibcon#flushed, iclass 5, count 0 2006.211.07:48:37.54#ibcon#about to write, iclass 5, count 0 2006.211.07:48:37.54#ibcon#wrote, iclass 5, count 0 2006.211.07:48:37.54#ibcon#about to read 3, iclass 5, count 0 2006.211.07:48:37.59#ibcon#read 3, iclass 5, count 0 2006.211.07:48:37.59#ibcon#about to read 4, iclass 5, count 0 2006.211.07:48:37.59#ibcon#read 4, iclass 5, count 0 2006.211.07:48:37.59#ibcon#about to read 5, iclass 5, count 0 2006.211.07:48:37.59#ibcon#read 5, iclass 5, count 0 2006.211.07:48:37.59#ibcon#about to read 6, iclass 5, count 0 2006.211.07:48:37.59#ibcon#read 6, iclass 5, count 0 2006.211.07:48:37.59#ibcon#end of sib2, iclass 5, count 0 2006.211.07:48:37.59#ibcon#*after write, iclass 5, count 0 2006.211.07:48:37.59#ibcon#*before return 0, iclass 5, count 0 2006.211.07:48:37.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:37.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:37.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:48:37.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:48:37.59$vc4f8/va=1,8 2006.211.07:48:37.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.07:48:37.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.07:48:37.59#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:37.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:37.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:37.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:37.59#ibcon#enter wrdev, iclass 7, count 2 2006.211.07:48:37.59#ibcon#first serial, iclass 7, count 2 2006.211.07:48:37.59#ibcon#enter sib2, iclass 7, count 2 2006.211.07:48:37.59#ibcon#flushed, iclass 7, count 2 2006.211.07:48:37.59#ibcon#about to write, iclass 7, count 2 2006.211.07:48:37.59#ibcon#wrote, iclass 7, count 2 2006.211.07:48:37.59#ibcon#about to read 3, iclass 7, count 2 2006.211.07:48:37.61#ibcon#read 3, iclass 7, count 2 2006.211.07:48:37.61#ibcon#about to read 4, iclass 7, count 2 2006.211.07:48:37.61#ibcon#read 4, iclass 7, count 2 2006.211.07:48:37.61#ibcon#about to read 5, iclass 7, count 2 2006.211.07:48:37.61#ibcon#read 5, iclass 7, count 2 2006.211.07:48:37.61#ibcon#about to read 6, iclass 7, count 2 2006.211.07:48:37.61#ibcon#read 6, iclass 7, count 2 2006.211.07:48:37.61#ibcon#end of sib2, iclass 7, count 2 2006.211.07:48:37.61#ibcon#*mode == 0, iclass 7, count 2 2006.211.07:48:37.61#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.07:48:37.61#ibcon#[25=AT01-08\r\n] 2006.211.07:48:37.61#ibcon#*before write, iclass 7, count 2 2006.211.07:48:37.61#ibcon#enter sib2, iclass 7, count 2 2006.211.07:48:37.61#ibcon#flushed, iclass 7, count 2 2006.211.07:48:37.61#ibcon#about to write, iclass 7, count 2 2006.211.07:48:37.61#ibcon#wrote, iclass 7, count 2 2006.211.07:48:37.61#ibcon#about to read 3, iclass 7, count 2 2006.211.07:48:37.64#ibcon#read 3, iclass 7, count 2 2006.211.07:48:37.64#ibcon#about to read 4, iclass 7, count 2 2006.211.07:48:37.64#ibcon#read 4, iclass 7, count 2 2006.211.07:48:37.64#ibcon#about to read 5, iclass 7, count 2 2006.211.07:48:37.64#ibcon#read 5, iclass 7, count 2 2006.211.07:48:37.64#ibcon#about to read 6, iclass 7, count 2 2006.211.07:48:37.64#ibcon#read 6, iclass 7, count 2 2006.211.07:48:37.64#ibcon#end of sib2, iclass 7, count 2 2006.211.07:48:37.64#ibcon#*after write, iclass 7, count 2 2006.211.07:48:37.64#ibcon#*before return 0, iclass 7, count 2 2006.211.07:48:37.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:37.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:37.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.07:48:37.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:37.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:37.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:37.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:37.76#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:48:37.76#ibcon#first serial, iclass 7, count 0 2006.211.07:48:37.76#ibcon#enter sib2, iclass 7, count 0 2006.211.07:48:37.76#ibcon#flushed, iclass 7, count 0 2006.211.07:48:37.76#ibcon#about to write, iclass 7, count 0 2006.211.07:48:37.76#ibcon#wrote, iclass 7, count 0 2006.211.07:48:37.76#ibcon#about to read 3, iclass 7, count 0 2006.211.07:48:37.78#ibcon#read 3, iclass 7, count 0 2006.211.07:48:37.78#ibcon#about to read 4, iclass 7, count 0 2006.211.07:48:37.78#ibcon#read 4, iclass 7, count 0 2006.211.07:48:37.78#ibcon#about to read 5, iclass 7, count 0 2006.211.07:48:37.78#ibcon#read 5, iclass 7, count 0 2006.211.07:48:37.78#ibcon#about to read 6, iclass 7, count 0 2006.211.07:48:37.78#ibcon#read 6, iclass 7, count 0 2006.211.07:48:37.78#ibcon#end of sib2, iclass 7, count 0 2006.211.07:48:37.78#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:48:37.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:48:37.78#ibcon#[25=USB\r\n] 2006.211.07:48:37.78#ibcon#*before write, iclass 7, count 0 2006.211.07:48:37.78#ibcon#enter sib2, iclass 7, count 0 2006.211.07:48:37.78#ibcon#flushed, iclass 7, count 0 2006.211.07:48:37.78#ibcon#about to write, iclass 7, count 0 2006.211.07:48:37.78#ibcon#wrote, iclass 7, count 0 2006.211.07:48:37.78#ibcon#about to read 3, iclass 7, count 0 2006.211.07:48:37.81#ibcon#read 3, iclass 7, count 0 2006.211.07:48:37.81#ibcon#about to read 4, iclass 7, count 0 2006.211.07:48:37.81#ibcon#read 4, iclass 7, count 0 2006.211.07:48:37.81#ibcon#about to read 5, iclass 7, count 0 2006.211.07:48:37.81#ibcon#read 5, iclass 7, count 0 2006.211.07:48:37.81#ibcon#about to read 6, iclass 7, count 0 2006.211.07:48:37.81#ibcon#read 6, iclass 7, count 0 2006.211.07:48:37.81#ibcon#end of sib2, iclass 7, count 0 2006.211.07:48:37.81#ibcon#*after write, iclass 7, count 0 2006.211.07:48:37.81#ibcon#*before return 0, iclass 7, count 0 2006.211.07:48:37.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:37.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:37.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:48:37.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:48:37.81$vc4f8/valo=2,572.99 2006.211.07:48:37.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:48:37.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:48:37.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:37.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:37.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:37.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:37.81#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:48:37.81#ibcon#first serial, iclass 11, count 0 2006.211.07:48:37.81#ibcon#enter sib2, iclass 11, count 0 2006.211.07:48:37.81#ibcon#flushed, iclass 11, count 0 2006.211.07:48:37.81#ibcon#about to write, iclass 11, count 0 2006.211.07:48:37.81#ibcon#wrote, iclass 11, count 0 2006.211.07:48:37.81#ibcon#about to read 3, iclass 11, count 0 2006.211.07:48:37.83#ibcon#read 3, iclass 11, count 0 2006.211.07:48:37.83#ibcon#about to read 4, iclass 11, count 0 2006.211.07:48:37.83#ibcon#read 4, iclass 11, count 0 2006.211.07:48:37.83#ibcon#about to read 5, iclass 11, count 0 2006.211.07:48:37.83#ibcon#read 5, iclass 11, count 0 2006.211.07:48:37.83#ibcon#about to read 6, iclass 11, count 0 2006.211.07:48:37.83#ibcon#read 6, iclass 11, count 0 2006.211.07:48:37.83#ibcon#end of sib2, iclass 11, count 0 2006.211.07:48:37.83#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:48:37.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:48:37.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:48:37.83#ibcon#*before write, iclass 11, count 0 2006.211.07:48:37.83#ibcon#enter sib2, iclass 11, count 0 2006.211.07:48:37.83#ibcon#flushed, iclass 11, count 0 2006.211.07:48:37.83#ibcon#about to write, iclass 11, count 0 2006.211.07:48:37.83#ibcon#wrote, iclass 11, count 0 2006.211.07:48:37.83#ibcon#about to read 3, iclass 11, count 0 2006.211.07:48:37.87#ibcon#read 3, iclass 11, count 0 2006.211.07:48:37.87#ibcon#about to read 4, iclass 11, count 0 2006.211.07:48:37.87#ibcon#read 4, iclass 11, count 0 2006.211.07:48:37.87#ibcon#about to read 5, iclass 11, count 0 2006.211.07:48:37.87#ibcon#read 5, iclass 11, count 0 2006.211.07:48:37.87#ibcon#about to read 6, iclass 11, count 0 2006.211.07:48:37.87#ibcon#read 6, iclass 11, count 0 2006.211.07:48:37.87#ibcon#end of sib2, iclass 11, count 0 2006.211.07:48:37.87#ibcon#*after write, iclass 11, count 0 2006.211.07:48:37.87#ibcon#*before return 0, iclass 11, count 0 2006.211.07:48:37.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:37.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:37.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:48:37.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:48:37.87$vc4f8/va=2,7 2006.211.07:48:37.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.07:48:37.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.07:48:37.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:37.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:37.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:37.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:37.93#ibcon#enter wrdev, iclass 13, count 2 2006.211.07:48:37.93#ibcon#first serial, iclass 13, count 2 2006.211.07:48:37.93#ibcon#enter sib2, iclass 13, count 2 2006.211.07:48:37.93#ibcon#flushed, iclass 13, count 2 2006.211.07:48:37.93#ibcon#about to write, iclass 13, count 2 2006.211.07:48:37.93#ibcon#wrote, iclass 13, count 2 2006.211.07:48:37.93#ibcon#about to read 3, iclass 13, count 2 2006.211.07:48:37.95#ibcon#read 3, iclass 13, count 2 2006.211.07:48:37.95#ibcon#about to read 4, iclass 13, count 2 2006.211.07:48:37.95#ibcon#read 4, iclass 13, count 2 2006.211.07:48:37.95#ibcon#about to read 5, iclass 13, count 2 2006.211.07:48:37.95#ibcon#read 5, iclass 13, count 2 2006.211.07:48:37.95#ibcon#about to read 6, iclass 13, count 2 2006.211.07:48:37.95#ibcon#read 6, iclass 13, count 2 2006.211.07:48:37.95#ibcon#end of sib2, iclass 13, count 2 2006.211.07:48:37.95#ibcon#*mode == 0, iclass 13, count 2 2006.211.07:48:37.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.07:48:37.95#ibcon#[25=AT02-07\r\n] 2006.211.07:48:37.95#ibcon#*before write, iclass 13, count 2 2006.211.07:48:37.95#ibcon#enter sib2, iclass 13, count 2 2006.211.07:48:37.95#ibcon#flushed, iclass 13, count 2 2006.211.07:48:37.95#ibcon#about to write, iclass 13, count 2 2006.211.07:48:37.95#ibcon#wrote, iclass 13, count 2 2006.211.07:48:37.95#ibcon#about to read 3, iclass 13, count 2 2006.211.07:48:37.98#ibcon#read 3, iclass 13, count 2 2006.211.07:48:37.98#ibcon#about to read 4, iclass 13, count 2 2006.211.07:48:37.98#ibcon#read 4, iclass 13, count 2 2006.211.07:48:37.98#ibcon#about to read 5, iclass 13, count 2 2006.211.07:48:37.98#ibcon#read 5, iclass 13, count 2 2006.211.07:48:37.98#ibcon#about to read 6, iclass 13, count 2 2006.211.07:48:37.98#ibcon#read 6, iclass 13, count 2 2006.211.07:48:37.98#ibcon#end of sib2, iclass 13, count 2 2006.211.07:48:37.98#ibcon#*after write, iclass 13, count 2 2006.211.07:48:37.98#ibcon#*before return 0, iclass 13, count 2 2006.211.07:48:37.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:37.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:37.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.07:48:37.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:37.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:38.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:38.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:38.10#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:48:38.10#ibcon#first serial, iclass 13, count 0 2006.211.07:48:38.10#ibcon#enter sib2, iclass 13, count 0 2006.211.07:48:38.10#ibcon#flushed, iclass 13, count 0 2006.211.07:48:38.10#ibcon#about to write, iclass 13, count 0 2006.211.07:48:38.10#ibcon#wrote, iclass 13, count 0 2006.211.07:48:38.10#ibcon#about to read 3, iclass 13, count 0 2006.211.07:48:38.12#ibcon#read 3, iclass 13, count 0 2006.211.07:48:38.12#ibcon#about to read 4, iclass 13, count 0 2006.211.07:48:38.12#ibcon#read 4, iclass 13, count 0 2006.211.07:48:38.12#ibcon#about to read 5, iclass 13, count 0 2006.211.07:48:38.12#ibcon#read 5, iclass 13, count 0 2006.211.07:48:38.12#ibcon#about to read 6, iclass 13, count 0 2006.211.07:48:38.12#ibcon#read 6, iclass 13, count 0 2006.211.07:48:38.12#ibcon#end of sib2, iclass 13, count 0 2006.211.07:48:38.12#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:48:38.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:48:38.12#ibcon#[25=USB\r\n] 2006.211.07:48:38.12#ibcon#*before write, iclass 13, count 0 2006.211.07:48:38.12#ibcon#enter sib2, iclass 13, count 0 2006.211.07:48:38.12#ibcon#flushed, iclass 13, count 0 2006.211.07:48:38.12#ibcon#about to write, iclass 13, count 0 2006.211.07:48:38.12#ibcon#wrote, iclass 13, count 0 2006.211.07:48:38.12#ibcon#about to read 3, iclass 13, count 0 2006.211.07:48:38.15#ibcon#read 3, iclass 13, count 0 2006.211.07:48:38.15#ibcon#about to read 4, iclass 13, count 0 2006.211.07:48:38.15#ibcon#read 4, iclass 13, count 0 2006.211.07:48:38.15#ibcon#about to read 5, iclass 13, count 0 2006.211.07:48:38.15#ibcon#read 5, iclass 13, count 0 2006.211.07:48:38.15#ibcon#about to read 6, iclass 13, count 0 2006.211.07:48:38.15#ibcon#read 6, iclass 13, count 0 2006.211.07:48:38.15#ibcon#end of sib2, iclass 13, count 0 2006.211.07:48:38.15#ibcon#*after write, iclass 13, count 0 2006.211.07:48:38.15#ibcon#*before return 0, iclass 13, count 0 2006.211.07:48:38.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:38.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:38.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:48:38.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:48:38.15$vc4f8/valo=3,672.99 2006.211.07:48:38.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:48:38.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:48:38.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:38.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:38.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:38.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:38.15#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:48:38.15#ibcon#first serial, iclass 15, count 0 2006.211.07:48:38.15#ibcon#enter sib2, iclass 15, count 0 2006.211.07:48:38.15#ibcon#flushed, iclass 15, count 0 2006.211.07:48:38.15#ibcon#about to write, iclass 15, count 0 2006.211.07:48:38.15#ibcon#wrote, iclass 15, count 0 2006.211.07:48:38.15#ibcon#about to read 3, iclass 15, count 0 2006.211.07:48:38.17#ibcon#read 3, iclass 15, count 0 2006.211.07:48:38.17#ibcon#about to read 4, iclass 15, count 0 2006.211.07:48:38.17#ibcon#read 4, iclass 15, count 0 2006.211.07:48:38.17#ibcon#about to read 5, iclass 15, count 0 2006.211.07:48:38.17#ibcon#read 5, iclass 15, count 0 2006.211.07:48:38.17#ibcon#about to read 6, iclass 15, count 0 2006.211.07:48:38.17#ibcon#read 6, iclass 15, count 0 2006.211.07:48:38.17#ibcon#end of sib2, iclass 15, count 0 2006.211.07:48:38.17#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:48:38.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:48:38.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:48:38.17#ibcon#*before write, iclass 15, count 0 2006.211.07:48:38.17#ibcon#enter sib2, iclass 15, count 0 2006.211.07:48:38.17#ibcon#flushed, iclass 15, count 0 2006.211.07:48:38.17#ibcon#about to write, iclass 15, count 0 2006.211.07:48:38.17#ibcon#wrote, iclass 15, count 0 2006.211.07:48:38.17#ibcon#about to read 3, iclass 15, count 0 2006.211.07:48:38.21#ibcon#read 3, iclass 15, count 0 2006.211.07:48:38.21#ibcon#about to read 4, iclass 15, count 0 2006.211.07:48:38.21#ibcon#read 4, iclass 15, count 0 2006.211.07:48:38.21#ibcon#about to read 5, iclass 15, count 0 2006.211.07:48:38.21#ibcon#read 5, iclass 15, count 0 2006.211.07:48:38.21#ibcon#about to read 6, iclass 15, count 0 2006.211.07:48:38.21#ibcon#read 6, iclass 15, count 0 2006.211.07:48:38.21#ibcon#end of sib2, iclass 15, count 0 2006.211.07:48:38.21#ibcon#*after write, iclass 15, count 0 2006.211.07:48:38.21#ibcon#*before return 0, iclass 15, count 0 2006.211.07:48:38.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:38.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:38.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:48:38.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:48:38.21$vc4f8/va=3,6 2006.211.07:48:38.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.07:48:38.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.07:48:38.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:38.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:38.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:38.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:38.27#ibcon#enter wrdev, iclass 17, count 2 2006.211.07:48:38.27#ibcon#first serial, iclass 17, count 2 2006.211.07:48:38.27#ibcon#enter sib2, iclass 17, count 2 2006.211.07:48:38.27#ibcon#flushed, iclass 17, count 2 2006.211.07:48:38.27#ibcon#about to write, iclass 17, count 2 2006.211.07:48:38.27#ibcon#wrote, iclass 17, count 2 2006.211.07:48:38.27#ibcon#about to read 3, iclass 17, count 2 2006.211.07:48:38.29#ibcon#read 3, iclass 17, count 2 2006.211.07:48:38.29#ibcon#about to read 4, iclass 17, count 2 2006.211.07:48:38.29#ibcon#read 4, iclass 17, count 2 2006.211.07:48:38.29#ibcon#about to read 5, iclass 17, count 2 2006.211.07:48:38.29#ibcon#read 5, iclass 17, count 2 2006.211.07:48:38.29#ibcon#about to read 6, iclass 17, count 2 2006.211.07:48:38.29#ibcon#read 6, iclass 17, count 2 2006.211.07:48:38.29#ibcon#end of sib2, iclass 17, count 2 2006.211.07:48:38.29#ibcon#*mode == 0, iclass 17, count 2 2006.211.07:48:38.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.07:48:38.29#ibcon#[25=AT03-06\r\n] 2006.211.07:48:38.29#ibcon#*before write, iclass 17, count 2 2006.211.07:48:38.29#ibcon#enter sib2, iclass 17, count 2 2006.211.07:48:38.29#ibcon#flushed, iclass 17, count 2 2006.211.07:48:38.29#ibcon#about to write, iclass 17, count 2 2006.211.07:48:38.29#ibcon#wrote, iclass 17, count 2 2006.211.07:48:38.29#ibcon#about to read 3, iclass 17, count 2 2006.211.07:48:38.32#ibcon#read 3, iclass 17, count 2 2006.211.07:48:38.32#ibcon#about to read 4, iclass 17, count 2 2006.211.07:48:38.32#ibcon#read 4, iclass 17, count 2 2006.211.07:48:38.32#ibcon#about to read 5, iclass 17, count 2 2006.211.07:48:38.32#ibcon#read 5, iclass 17, count 2 2006.211.07:48:38.32#ibcon#about to read 6, iclass 17, count 2 2006.211.07:48:38.32#ibcon#read 6, iclass 17, count 2 2006.211.07:48:38.32#ibcon#end of sib2, iclass 17, count 2 2006.211.07:48:38.32#ibcon#*after write, iclass 17, count 2 2006.211.07:48:38.32#ibcon#*before return 0, iclass 17, count 2 2006.211.07:48:38.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:38.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:38.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.07:48:38.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:38.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:38.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:38.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:38.44#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:48:38.44#ibcon#first serial, iclass 17, count 0 2006.211.07:48:38.44#ibcon#enter sib2, iclass 17, count 0 2006.211.07:48:38.44#ibcon#flushed, iclass 17, count 0 2006.211.07:48:38.44#ibcon#about to write, iclass 17, count 0 2006.211.07:48:38.44#ibcon#wrote, iclass 17, count 0 2006.211.07:48:38.44#ibcon#about to read 3, iclass 17, count 0 2006.211.07:48:38.46#ibcon#read 3, iclass 17, count 0 2006.211.07:48:38.46#ibcon#about to read 4, iclass 17, count 0 2006.211.07:48:38.46#ibcon#read 4, iclass 17, count 0 2006.211.07:48:38.46#ibcon#about to read 5, iclass 17, count 0 2006.211.07:48:38.46#ibcon#read 5, iclass 17, count 0 2006.211.07:48:38.46#ibcon#about to read 6, iclass 17, count 0 2006.211.07:48:38.46#ibcon#read 6, iclass 17, count 0 2006.211.07:48:38.46#ibcon#end of sib2, iclass 17, count 0 2006.211.07:48:38.46#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:48:38.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:48:38.46#ibcon#[25=USB\r\n] 2006.211.07:48:38.46#ibcon#*before write, iclass 17, count 0 2006.211.07:48:38.46#ibcon#enter sib2, iclass 17, count 0 2006.211.07:48:38.46#ibcon#flushed, iclass 17, count 0 2006.211.07:48:38.46#ibcon#about to write, iclass 17, count 0 2006.211.07:48:38.46#ibcon#wrote, iclass 17, count 0 2006.211.07:48:38.46#ibcon#about to read 3, iclass 17, count 0 2006.211.07:48:38.49#ibcon#read 3, iclass 17, count 0 2006.211.07:48:38.49#ibcon#about to read 4, iclass 17, count 0 2006.211.07:48:38.49#ibcon#read 4, iclass 17, count 0 2006.211.07:48:38.49#ibcon#about to read 5, iclass 17, count 0 2006.211.07:48:38.49#ibcon#read 5, iclass 17, count 0 2006.211.07:48:38.49#ibcon#about to read 6, iclass 17, count 0 2006.211.07:48:38.49#ibcon#read 6, iclass 17, count 0 2006.211.07:48:38.49#ibcon#end of sib2, iclass 17, count 0 2006.211.07:48:38.49#ibcon#*after write, iclass 17, count 0 2006.211.07:48:38.49#ibcon#*before return 0, iclass 17, count 0 2006.211.07:48:38.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:38.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:38.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:48:38.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:48:38.49$vc4f8/valo=4,832.99 2006.211.07:48:38.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.07:48:38.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.07:48:38.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:38.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:38.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:38.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:38.49#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:48:38.49#ibcon#first serial, iclass 19, count 0 2006.211.07:48:38.49#ibcon#enter sib2, iclass 19, count 0 2006.211.07:48:38.49#ibcon#flushed, iclass 19, count 0 2006.211.07:48:38.49#ibcon#about to write, iclass 19, count 0 2006.211.07:48:38.49#ibcon#wrote, iclass 19, count 0 2006.211.07:48:38.49#ibcon#about to read 3, iclass 19, count 0 2006.211.07:48:38.51#ibcon#read 3, iclass 19, count 0 2006.211.07:48:38.51#ibcon#about to read 4, iclass 19, count 0 2006.211.07:48:38.51#ibcon#read 4, iclass 19, count 0 2006.211.07:48:38.51#ibcon#about to read 5, iclass 19, count 0 2006.211.07:48:38.51#ibcon#read 5, iclass 19, count 0 2006.211.07:48:38.51#ibcon#about to read 6, iclass 19, count 0 2006.211.07:48:38.51#ibcon#read 6, iclass 19, count 0 2006.211.07:48:38.51#ibcon#end of sib2, iclass 19, count 0 2006.211.07:48:38.51#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:48:38.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:48:38.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:48:38.51#ibcon#*before write, iclass 19, count 0 2006.211.07:48:38.51#ibcon#enter sib2, iclass 19, count 0 2006.211.07:48:38.51#ibcon#flushed, iclass 19, count 0 2006.211.07:48:38.51#ibcon#about to write, iclass 19, count 0 2006.211.07:48:38.51#ibcon#wrote, iclass 19, count 0 2006.211.07:48:38.51#ibcon#about to read 3, iclass 19, count 0 2006.211.07:48:38.55#ibcon#read 3, iclass 19, count 0 2006.211.07:48:38.55#ibcon#about to read 4, iclass 19, count 0 2006.211.07:48:38.55#ibcon#read 4, iclass 19, count 0 2006.211.07:48:38.55#ibcon#about to read 5, iclass 19, count 0 2006.211.07:48:38.55#ibcon#read 5, iclass 19, count 0 2006.211.07:48:38.55#ibcon#about to read 6, iclass 19, count 0 2006.211.07:48:38.55#ibcon#read 6, iclass 19, count 0 2006.211.07:48:38.55#ibcon#end of sib2, iclass 19, count 0 2006.211.07:48:38.55#ibcon#*after write, iclass 19, count 0 2006.211.07:48:38.55#ibcon#*before return 0, iclass 19, count 0 2006.211.07:48:38.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:38.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:38.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:48:38.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:48:38.55$vc4f8/va=4,7 2006.211.07:48:38.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.07:48:38.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.07:48:38.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:38.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:38.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:38.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:38.61#ibcon#enter wrdev, iclass 21, count 2 2006.211.07:48:38.61#ibcon#first serial, iclass 21, count 2 2006.211.07:48:38.61#ibcon#enter sib2, iclass 21, count 2 2006.211.07:48:38.61#ibcon#flushed, iclass 21, count 2 2006.211.07:48:38.61#ibcon#about to write, iclass 21, count 2 2006.211.07:48:38.61#ibcon#wrote, iclass 21, count 2 2006.211.07:48:38.61#ibcon#about to read 3, iclass 21, count 2 2006.211.07:48:38.63#ibcon#read 3, iclass 21, count 2 2006.211.07:48:38.63#ibcon#about to read 4, iclass 21, count 2 2006.211.07:48:38.63#ibcon#read 4, iclass 21, count 2 2006.211.07:48:38.63#ibcon#about to read 5, iclass 21, count 2 2006.211.07:48:38.63#ibcon#read 5, iclass 21, count 2 2006.211.07:48:38.63#ibcon#about to read 6, iclass 21, count 2 2006.211.07:48:38.63#ibcon#read 6, iclass 21, count 2 2006.211.07:48:38.63#ibcon#end of sib2, iclass 21, count 2 2006.211.07:48:38.63#ibcon#*mode == 0, iclass 21, count 2 2006.211.07:48:38.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.07:48:38.63#ibcon#[25=AT04-07\r\n] 2006.211.07:48:38.63#ibcon#*before write, iclass 21, count 2 2006.211.07:48:38.63#ibcon#enter sib2, iclass 21, count 2 2006.211.07:48:38.63#ibcon#flushed, iclass 21, count 2 2006.211.07:48:38.63#ibcon#about to write, iclass 21, count 2 2006.211.07:48:38.63#ibcon#wrote, iclass 21, count 2 2006.211.07:48:38.63#ibcon#about to read 3, iclass 21, count 2 2006.211.07:48:38.66#ibcon#read 3, iclass 21, count 2 2006.211.07:48:38.66#ibcon#about to read 4, iclass 21, count 2 2006.211.07:48:38.66#ibcon#read 4, iclass 21, count 2 2006.211.07:48:38.66#ibcon#about to read 5, iclass 21, count 2 2006.211.07:48:38.66#ibcon#read 5, iclass 21, count 2 2006.211.07:48:38.66#ibcon#about to read 6, iclass 21, count 2 2006.211.07:48:38.66#ibcon#read 6, iclass 21, count 2 2006.211.07:48:38.66#ibcon#end of sib2, iclass 21, count 2 2006.211.07:48:38.66#ibcon#*after write, iclass 21, count 2 2006.211.07:48:38.66#ibcon#*before return 0, iclass 21, count 2 2006.211.07:48:38.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:38.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:38.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.07:48:38.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:38.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:38.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:38.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:38.78#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:48:38.78#ibcon#first serial, iclass 21, count 0 2006.211.07:48:38.78#ibcon#enter sib2, iclass 21, count 0 2006.211.07:48:38.78#ibcon#flushed, iclass 21, count 0 2006.211.07:48:38.78#ibcon#about to write, iclass 21, count 0 2006.211.07:48:38.78#ibcon#wrote, iclass 21, count 0 2006.211.07:48:38.78#ibcon#about to read 3, iclass 21, count 0 2006.211.07:48:38.80#ibcon#read 3, iclass 21, count 0 2006.211.07:48:38.80#ibcon#about to read 4, iclass 21, count 0 2006.211.07:48:38.80#ibcon#read 4, iclass 21, count 0 2006.211.07:48:38.80#ibcon#about to read 5, iclass 21, count 0 2006.211.07:48:38.80#ibcon#read 5, iclass 21, count 0 2006.211.07:48:38.80#ibcon#about to read 6, iclass 21, count 0 2006.211.07:48:38.80#ibcon#read 6, iclass 21, count 0 2006.211.07:48:38.80#ibcon#end of sib2, iclass 21, count 0 2006.211.07:48:38.80#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:48:38.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:48:38.80#ibcon#[25=USB\r\n] 2006.211.07:48:38.80#ibcon#*before write, iclass 21, count 0 2006.211.07:48:38.80#ibcon#enter sib2, iclass 21, count 0 2006.211.07:48:38.80#ibcon#flushed, iclass 21, count 0 2006.211.07:48:38.80#ibcon#about to write, iclass 21, count 0 2006.211.07:48:38.80#ibcon#wrote, iclass 21, count 0 2006.211.07:48:38.80#ibcon#about to read 3, iclass 21, count 0 2006.211.07:48:38.83#ibcon#read 3, iclass 21, count 0 2006.211.07:48:38.83#ibcon#about to read 4, iclass 21, count 0 2006.211.07:48:38.83#ibcon#read 4, iclass 21, count 0 2006.211.07:48:38.83#ibcon#about to read 5, iclass 21, count 0 2006.211.07:48:38.83#ibcon#read 5, iclass 21, count 0 2006.211.07:48:38.83#ibcon#about to read 6, iclass 21, count 0 2006.211.07:48:38.83#ibcon#read 6, iclass 21, count 0 2006.211.07:48:38.83#ibcon#end of sib2, iclass 21, count 0 2006.211.07:48:38.83#ibcon#*after write, iclass 21, count 0 2006.211.07:48:38.83#ibcon#*before return 0, iclass 21, count 0 2006.211.07:48:38.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:38.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:38.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:48:38.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:48:38.83$vc4f8/valo=5,652.99 2006.211.07:48:38.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:48:38.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:48:38.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:38.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:38.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:38.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:38.83#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:48:38.83#ibcon#first serial, iclass 23, count 0 2006.211.07:48:38.83#ibcon#enter sib2, iclass 23, count 0 2006.211.07:48:38.83#ibcon#flushed, iclass 23, count 0 2006.211.07:48:38.83#ibcon#about to write, iclass 23, count 0 2006.211.07:48:38.83#ibcon#wrote, iclass 23, count 0 2006.211.07:48:38.83#ibcon#about to read 3, iclass 23, count 0 2006.211.07:48:38.85#ibcon#read 3, iclass 23, count 0 2006.211.07:48:38.85#ibcon#about to read 4, iclass 23, count 0 2006.211.07:48:38.85#ibcon#read 4, iclass 23, count 0 2006.211.07:48:38.85#ibcon#about to read 5, iclass 23, count 0 2006.211.07:48:38.85#ibcon#read 5, iclass 23, count 0 2006.211.07:48:38.85#ibcon#about to read 6, iclass 23, count 0 2006.211.07:48:38.85#ibcon#read 6, iclass 23, count 0 2006.211.07:48:38.85#ibcon#end of sib2, iclass 23, count 0 2006.211.07:48:38.85#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:48:38.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:48:38.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:48:38.85#ibcon#*before write, iclass 23, count 0 2006.211.07:48:38.85#ibcon#enter sib2, iclass 23, count 0 2006.211.07:48:38.85#ibcon#flushed, iclass 23, count 0 2006.211.07:48:38.85#ibcon#about to write, iclass 23, count 0 2006.211.07:48:38.85#ibcon#wrote, iclass 23, count 0 2006.211.07:48:38.85#ibcon#about to read 3, iclass 23, count 0 2006.211.07:48:38.89#ibcon#read 3, iclass 23, count 0 2006.211.07:48:38.89#ibcon#about to read 4, iclass 23, count 0 2006.211.07:48:38.89#ibcon#read 4, iclass 23, count 0 2006.211.07:48:38.89#ibcon#about to read 5, iclass 23, count 0 2006.211.07:48:38.89#ibcon#read 5, iclass 23, count 0 2006.211.07:48:38.89#ibcon#about to read 6, iclass 23, count 0 2006.211.07:48:38.89#ibcon#read 6, iclass 23, count 0 2006.211.07:48:38.89#ibcon#end of sib2, iclass 23, count 0 2006.211.07:48:38.89#ibcon#*after write, iclass 23, count 0 2006.211.07:48:38.89#ibcon#*before return 0, iclass 23, count 0 2006.211.07:48:38.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:38.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:38.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:48:38.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:48:38.89$vc4f8/va=5,7 2006.211.07:48:38.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.07:48:38.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.07:48:38.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:38.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:38.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:38.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:38.95#ibcon#enter wrdev, iclass 25, count 2 2006.211.07:48:38.95#ibcon#first serial, iclass 25, count 2 2006.211.07:48:38.95#ibcon#enter sib2, iclass 25, count 2 2006.211.07:48:38.95#ibcon#flushed, iclass 25, count 2 2006.211.07:48:38.95#ibcon#about to write, iclass 25, count 2 2006.211.07:48:38.95#ibcon#wrote, iclass 25, count 2 2006.211.07:48:38.95#ibcon#about to read 3, iclass 25, count 2 2006.211.07:48:38.97#ibcon#read 3, iclass 25, count 2 2006.211.07:48:38.97#ibcon#about to read 4, iclass 25, count 2 2006.211.07:48:38.97#ibcon#read 4, iclass 25, count 2 2006.211.07:48:38.97#ibcon#about to read 5, iclass 25, count 2 2006.211.07:48:38.97#ibcon#read 5, iclass 25, count 2 2006.211.07:48:38.97#ibcon#about to read 6, iclass 25, count 2 2006.211.07:48:38.97#ibcon#read 6, iclass 25, count 2 2006.211.07:48:38.97#ibcon#end of sib2, iclass 25, count 2 2006.211.07:48:38.97#ibcon#*mode == 0, iclass 25, count 2 2006.211.07:48:38.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.07:48:38.97#ibcon#[25=AT05-07\r\n] 2006.211.07:48:38.97#ibcon#*before write, iclass 25, count 2 2006.211.07:48:38.97#ibcon#enter sib2, iclass 25, count 2 2006.211.07:48:38.97#ibcon#flushed, iclass 25, count 2 2006.211.07:48:38.97#ibcon#about to write, iclass 25, count 2 2006.211.07:48:38.97#ibcon#wrote, iclass 25, count 2 2006.211.07:48:38.97#ibcon#about to read 3, iclass 25, count 2 2006.211.07:48:39.00#ibcon#read 3, iclass 25, count 2 2006.211.07:48:39.00#ibcon#about to read 4, iclass 25, count 2 2006.211.07:48:39.00#ibcon#read 4, iclass 25, count 2 2006.211.07:48:39.00#ibcon#about to read 5, iclass 25, count 2 2006.211.07:48:39.00#ibcon#read 5, iclass 25, count 2 2006.211.07:48:39.00#ibcon#about to read 6, iclass 25, count 2 2006.211.07:48:39.00#ibcon#read 6, iclass 25, count 2 2006.211.07:48:39.00#ibcon#end of sib2, iclass 25, count 2 2006.211.07:48:39.00#ibcon#*after write, iclass 25, count 2 2006.211.07:48:39.00#ibcon#*before return 0, iclass 25, count 2 2006.211.07:48:39.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:39.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:39.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.07:48:39.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:39.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:39.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:39.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:39.12#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:48:39.12#ibcon#first serial, iclass 25, count 0 2006.211.07:48:39.12#ibcon#enter sib2, iclass 25, count 0 2006.211.07:48:39.12#ibcon#flushed, iclass 25, count 0 2006.211.07:48:39.12#ibcon#about to write, iclass 25, count 0 2006.211.07:48:39.12#ibcon#wrote, iclass 25, count 0 2006.211.07:48:39.12#ibcon#about to read 3, iclass 25, count 0 2006.211.07:48:39.14#ibcon#read 3, iclass 25, count 0 2006.211.07:48:39.14#ibcon#about to read 4, iclass 25, count 0 2006.211.07:48:39.14#ibcon#read 4, iclass 25, count 0 2006.211.07:48:39.14#ibcon#about to read 5, iclass 25, count 0 2006.211.07:48:39.14#ibcon#read 5, iclass 25, count 0 2006.211.07:48:39.14#ibcon#about to read 6, iclass 25, count 0 2006.211.07:48:39.14#ibcon#read 6, iclass 25, count 0 2006.211.07:48:39.14#ibcon#end of sib2, iclass 25, count 0 2006.211.07:48:39.14#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:48:39.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:48:39.14#ibcon#[25=USB\r\n] 2006.211.07:48:39.14#ibcon#*before write, iclass 25, count 0 2006.211.07:48:39.14#ibcon#enter sib2, iclass 25, count 0 2006.211.07:48:39.14#ibcon#flushed, iclass 25, count 0 2006.211.07:48:39.14#ibcon#about to write, iclass 25, count 0 2006.211.07:48:39.14#ibcon#wrote, iclass 25, count 0 2006.211.07:48:39.14#ibcon#about to read 3, iclass 25, count 0 2006.211.07:48:39.17#ibcon#read 3, iclass 25, count 0 2006.211.07:48:39.17#ibcon#about to read 4, iclass 25, count 0 2006.211.07:48:39.17#ibcon#read 4, iclass 25, count 0 2006.211.07:48:39.17#ibcon#about to read 5, iclass 25, count 0 2006.211.07:48:39.17#ibcon#read 5, iclass 25, count 0 2006.211.07:48:39.17#ibcon#about to read 6, iclass 25, count 0 2006.211.07:48:39.17#ibcon#read 6, iclass 25, count 0 2006.211.07:48:39.17#ibcon#end of sib2, iclass 25, count 0 2006.211.07:48:39.17#ibcon#*after write, iclass 25, count 0 2006.211.07:48:39.17#ibcon#*before return 0, iclass 25, count 0 2006.211.07:48:39.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:39.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:39.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:48:39.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:48:39.17$vc4f8/valo=6,772.99 2006.211.07:48:39.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.07:48:39.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.07:48:39.17#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:39.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:39.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:39.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:39.17#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:48:39.17#ibcon#first serial, iclass 27, count 0 2006.211.07:48:39.17#ibcon#enter sib2, iclass 27, count 0 2006.211.07:48:39.17#ibcon#flushed, iclass 27, count 0 2006.211.07:48:39.17#ibcon#about to write, iclass 27, count 0 2006.211.07:48:39.17#ibcon#wrote, iclass 27, count 0 2006.211.07:48:39.17#ibcon#about to read 3, iclass 27, count 0 2006.211.07:48:39.19#ibcon#read 3, iclass 27, count 0 2006.211.07:48:39.19#ibcon#about to read 4, iclass 27, count 0 2006.211.07:48:39.19#ibcon#read 4, iclass 27, count 0 2006.211.07:48:39.19#ibcon#about to read 5, iclass 27, count 0 2006.211.07:48:39.19#ibcon#read 5, iclass 27, count 0 2006.211.07:48:39.19#ibcon#about to read 6, iclass 27, count 0 2006.211.07:48:39.19#ibcon#read 6, iclass 27, count 0 2006.211.07:48:39.19#ibcon#end of sib2, iclass 27, count 0 2006.211.07:48:39.19#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:48:39.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:48:39.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:48:39.19#ibcon#*before write, iclass 27, count 0 2006.211.07:48:39.19#ibcon#enter sib2, iclass 27, count 0 2006.211.07:48:39.19#ibcon#flushed, iclass 27, count 0 2006.211.07:48:39.19#ibcon#about to write, iclass 27, count 0 2006.211.07:48:39.19#ibcon#wrote, iclass 27, count 0 2006.211.07:48:39.19#ibcon#about to read 3, iclass 27, count 0 2006.211.07:48:39.23#ibcon#read 3, iclass 27, count 0 2006.211.07:48:39.23#ibcon#about to read 4, iclass 27, count 0 2006.211.07:48:39.23#ibcon#read 4, iclass 27, count 0 2006.211.07:48:39.23#ibcon#about to read 5, iclass 27, count 0 2006.211.07:48:39.23#ibcon#read 5, iclass 27, count 0 2006.211.07:48:39.23#ibcon#about to read 6, iclass 27, count 0 2006.211.07:48:39.23#ibcon#read 6, iclass 27, count 0 2006.211.07:48:39.23#ibcon#end of sib2, iclass 27, count 0 2006.211.07:48:39.23#ibcon#*after write, iclass 27, count 0 2006.211.07:48:39.23#ibcon#*before return 0, iclass 27, count 0 2006.211.07:48:39.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:39.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:39.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:48:39.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:48:39.23$vc4f8/va=6,6 2006.211.07:48:39.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.07:48:39.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.07:48:39.23#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:39.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:48:39.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:48:39.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:48:39.29#ibcon#enter wrdev, iclass 29, count 2 2006.211.07:48:39.29#ibcon#first serial, iclass 29, count 2 2006.211.07:48:39.29#ibcon#enter sib2, iclass 29, count 2 2006.211.07:48:39.29#ibcon#flushed, iclass 29, count 2 2006.211.07:48:39.29#ibcon#about to write, iclass 29, count 2 2006.211.07:48:39.29#ibcon#wrote, iclass 29, count 2 2006.211.07:48:39.29#ibcon#about to read 3, iclass 29, count 2 2006.211.07:48:39.31#ibcon#read 3, iclass 29, count 2 2006.211.07:48:39.31#ibcon#about to read 4, iclass 29, count 2 2006.211.07:48:39.31#ibcon#read 4, iclass 29, count 2 2006.211.07:48:39.31#ibcon#about to read 5, iclass 29, count 2 2006.211.07:48:39.31#ibcon#read 5, iclass 29, count 2 2006.211.07:48:39.31#ibcon#about to read 6, iclass 29, count 2 2006.211.07:48:39.31#ibcon#read 6, iclass 29, count 2 2006.211.07:48:39.31#ibcon#end of sib2, iclass 29, count 2 2006.211.07:48:39.31#ibcon#*mode == 0, iclass 29, count 2 2006.211.07:48:39.31#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.07:48:39.31#ibcon#[25=AT06-06\r\n] 2006.211.07:48:39.31#ibcon#*before write, iclass 29, count 2 2006.211.07:48:39.31#ibcon#enter sib2, iclass 29, count 2 2006.211.07:48:39.31#ibcon#flushed, iclass 29, count 2 2006.211.07:48:39.31#ibcon#about to write, iclass 29, count 2 2006.211.07:48:39.31#ibcon#wrote, iclass 29, count 2 2006.211.07:48:39.31#ibcon#about to read 3, iclass 29, count 2 2006.211.07:48:39.34#ibcon#read 3, iclass 29, count 2 2006.211.07:48:39.34#ibcon#about to read 4, iclass 29, count 2 2006.211.07:48:39.34#ibcon#read 4, iclass 29, count 2 2006.211.07:48:39.34#ibcon#about to read 5, iclass 29, count 2 2006.211.07:48:39.34#ibcon#read 5, iclass 29, count 2 2006.211.07:48:39.34#ibcon#about to read 6, iclass 29, count 2 2006.211.07:48:39.34#ibcon#read 6, iclass 29, count 2 2006.211.07:48:39.34#ibcon#end of sib2, iclass 29, count 2 2006.211.07:48:39.34#ibcon#*after write, iclass 29, count 2 2006.211.07:48:39.34#ibcon#*before return 0, iclass 29, count 2 2006.211.07:48:39.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:48:39.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:48:39.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.07:48:39.34#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:39.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:48:39.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:48:39.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:48:39.46#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:48:39.46#ibcon#first serial, iclass 29, count 0 2006.211.07:48:39.46#ibcon#enter sib2, iclass 29, count 0 2006.211.07:48:39.46#ibcon#flushed, iclass 29, count 0 2006.211.07:48:39.46#ibcon#about to write, iclass 29, count 0 2006.211.07:48:39.46#ibcon#wrote, iclass 29, count 0 2006.211.07:48:39.46#ibcon#about to read 3, iclass 29, count 0 2006.211.07:48:39.48#ibcon#read 3, iclass 29, count 0 2006.211.07:48:39.48#ibcon#about to read 4, iclass 29, count 0 2006.211.07:48:39.48#ibcon#read 4, iclass 29, count 0 2006.211.07:48:39.48#ibcon#about to read 5, iclass 29, count 0 2006.211.07:48:39.48#ibcon#read 5, iclass 29, count 0 2006.211.07:48:39.48#ibcon#about to read 6, iclass 29, count 0 2006.211.07:48:39.48#ibcon#read 6, iclass 29, count 0 2006.211.07:48:39.48#ibcon#end of sib2, iclass 29, count 0 2006.211.07:48:39.48#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:48:39.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:48:39.48#ibcon#[25=USB\r\n] 2006.211.07:48:39.48#ibcon#*before write, iclass 29, count 0 2006.211.07:48:39.48#ibcon#enter sib2, iclass 29, count 0 2006.211.07:48:39.48#ibcon#flushed, iclass 29, count 0 2006.211.07:48:39.48#ibcon#about to write, iclass 29, count 0 2006.211.07:48:39.48#ibcon#wrote, iclass 29, count 0 2006.211.07:48:39.48#ibcon#about to read 3, iclass 29, count 0 2006.211.07:48:39.51#ibcon#read 3, iclass 29, count 0 2006.211.07:48:39.51#ibcon#about to read 4, iclass 29, count 0 2006.211.07:48:39.51#ibcon#read 4, iclass 29, count 0 2006.211.07:48:39.51#ibcon#about to read 5, iclass 29, count 0 2006.211.07:48:39.51#ibcon#read 5, iclass 29, count 0 2006.211.07:48:39.51#ibcon#about to read 6, iclass 29, count 0 2006.211.07:48:39.51#ibcon#read 6, iclass 29, count 0 2006.211.07:48:39.51#ibcon#end of sib2, iclass 29, count 0 2006.211.07:48:39.51#ibcon#*after write, iclass 29, count 0 2006.211.07:48:39.51#ibcon#*before return 0, iclass 29, count 0 2006.211.07:48:39.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:48:39.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:48:39.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:48:39.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:48:39.51$vc4f8/valo=7,832.99 2006.211.07:48:39.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.07:48:39.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.07:48:39.51#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:39.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:48:39.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:48:39.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:48:39.51#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:48:39.51#ibcon#first serial, iclass 31, count 0 2006.211.07:48:39.51#ibcon#enter sib2, iclass 31, count 0 2006.211.07:48:39.51#ibcon#flushed, iclass 31, count 0 2006.211.07:48:39.51#ibcon#about to write, iclass 31, count 0 2006.211.07:48:39.51#ibcon#wrote, iclass 31, count 0 2006.211.07:48:39.51#ibcon#about to read 3, iclass 31, count 0 2006.211.07:48:39.53#ibcon#read 3, iclass 31, count 0 2006.211.07:48:39.53#ibcon#about to read 4, iclass 31, count 0 2006.211.07:48:39.53#ibcon#read 4, iclass 31, count 0 2006.211.07:48:39.53#ibcon#about to read 5, iclass 31, count 0 2006.211.07:48:39.53#ibcon#read 5, iclass 31, count 0 2006.211.07:48:39.53#ibcon#about to read 6, iclass 31, count 0 2006.211.07:48:39.53#ibcon#read 6, iclass 31, count 0 2006.211.07:48:39.53#ibcon#end of sib2, iclass 31, count 0 2006.211.07:48:39.53#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:48:39.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:48:39.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:48:39.53#ibcon#*before write, iclass 31, count 0 2006.211.07:48:39.53#ibcon#enter sib2, iclass 31, count 0 2006.211.07:48:39.53#ibcon#flushed, iclass 31, count 0 2006.211.07:48:39.53#ibcon#about to write, iclass 31, count 0 2006.211.07:48:39.53#ibcon#wrote, iclass 31, count 0 2006.211.07:48:39.53#ibcon#about to read 3, iclass 31, count 0 2006.211.07:48:39.57#ibcon#read 3, iclass 31, count 0 2006.211.07:48:39.57#ibcon#about to read 4, iclass 31, count 0 2006.211.07:48:39.57#ibcon#read 4, iclass 31, count 0 2006.211.07:48:39.57#ibcon#about to read 5, iclass 31, count 0 2006.211.07:48:39.57#ibcon#read 5, iclass 31, count 0 2006.211.07:48:39.57#ibcon#about to read 6, iclass 31, count 0 2006.211.07:48:39.57#ibcon#read 6, iclass 31, count 0 2006.211.07:48:39.57#ibcon#end of sib2, iclass 31, count 0 2006.211.07:48:39.57#ibcon#*after write, iclass 31, count 0 2006.211.07:48:39.57#ibcon#*before return 0, iclass 31, count 0 2006.211.07:48:39.57#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:48:39.57#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:48:39.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:48:39.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:48:39.57$vc4f8/va=7,6 2006.211.07:48:39.57#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.07:48:39.57#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.07:48:39.57#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:39.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:48:39.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:48:39.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:48:39.63#ibcon#enter wrdev, iclass 33, count 2 2006.211.07:48:39.63#ibcon#first serial, iclass 33, count 2 2006.211.07:48:39.63#ibcon#enter sib2, iclass 33, count 2 2006.211.07:48:39.63#ibcon#flushed, iclass 33, count 2 2006.211.07:48:39.63#ibcon#about to write, iclass 33, count 2 2006.211.07:48:39.63#ibcon#wrote, iclass 33, count 2 2006.211.07:48:39.63#ibcon#about to read 3, iclass 33, count 2 2006.211.07:48:39.65#ibcon#read 3, iclass 33, count 2 2006.211.07:48:39.65#ibcon#about to read 4, iclass 33, count 2 2006.211.07:48:39.65#ibcon#read 4, iclass 33, count 2 2006.211.07:48:39.65#ibcon#about to read 5, iclass 33, count 2 2006.211.07:48:39.65#ibcon#read 5, iclass 33, count 2 2006.211.07:48:39.65#ibcon#about to read 6, iclass 33, count 2 2006.211.07:48:39.65#ibcon#read 6, iclass 33, count 2 2006.211.07:48:39.65#ibcon#end of sib2, iclass 33, count 2 2006.211.07:48:39.65#ibcon#*mode == 0, iclass 33, count 2 2006.211.07:48:39.65#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.07:48:39.65#ibcon#[25=AT07-06\r\n] 2006.211.07:48:39.65#ibcon#*before write, iclass 33, count 2 2006.211.07:48:39.65#ibcon#enter sib2, iclass 33, count 2 2006.211.07:48:39.65#ibcon#flushed, iclass 33, count 2 2006.211.07:48:39.65#ibcon#about to write, iclass 33, count 2 2006.211.07:48:39.65#ibcon#wrote, iclass 33, count 2 2006.211.07:48:39.65#ibcon#about to read 3, iclass 33, count 2 2006.211.07:48:39.68#ibcon#read 3, iclass 33, count 2 2006.211.07:48:39.68#ibcon#about to read 4, iclass 33, count 2 2006.211.07:48:39.68#ibcon#read 4, iclass 33, count 2 2006.211.07:48:39.68#ibcon#about to read 5, iclass 33, count 2 2006.211.07:48:39.68#ibcon#read 5, iclass 33, count 2 2006.211.07:48:39.68#ibcon#about to read 6, iclass 33, count 2 2006.211.07:48:39.68#ibcon#read 6, iclass 33, count 2 2006.211.07:48:39.68#ibcon#end of sib2, iclass 33, count 2 2006.211.07:48:39.68#ibcon#*after write, iclass 33, count 2 2006.211.07:48:39.68#ibcon#*before return 0, iclass 33, count 2 2006.211.07:48:39.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:48:39.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:48:39.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.07:48:39.68#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:39.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:48:39.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:48:39.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:48:39.80#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:48:39.80#ibcon#first serial, iclass 33, count 0 2006.211.07:48:39.80#ibcon#enter sib2, iclass 33, count 0 2006.211.07:48:39.80#ibcon#flushed, iclass 33, count 0 2006.211.07:48:39.80#ibcon#about to write, iclass 33, count 0 2006.211.07:48:39.80#ibcon#wrote, iclass 33, count 0 2006.211.07:48:39.80#ibcon#about to read 3, iclass 33, count 0 2006.211.07:48:39.82#ibcon#read 3, iclass 33, count 0 2006.211.07:48:39.82#ibcon#about to read 4, iclass 33, count 0 2006.211.07:48:39.82#ibcon#read 4, iclass 33, count 0 2006.211.07:48:39.82#ibcon#about to read 5, iclass 33, count 0 2006.211.07:48:39.82#ibcon#read 5, iclass 33, count 0 2006.211.07:48:39.82#ibcon#about to read 6, iclass 33, count 0 2006.211.07:48:39.82#ibcon#read 6, iclass 33, count 0 2006.211.07:48:39.82#ibcon#end of sib2, iclass 33, count 0 2006.211.07:48:39.82#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:48:39.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:48:39.82#ibcon#[25=USB\r\n] 2006.211.07:48:39.82#ibcon#*before write, iclass 33, count 0 2006.211.07:48:39.82#ibcon#enter sib2, iclass 33, count 0 2006.211.07:48:39.82#ibcon#flushed, iclass 33, count 0 2006.211.07:48:39.82#ibcon#about to write, iclass 33, count 0 2006.211.07:48:39.82#ibcon#wrote, iclass 33, count 0 2006.211.07:48:39.82#ibcon#about to read 3, iclass 33, count 0 2006.211.07:48:39.85#ibcon#read 3, iclass 33, count 0 2006.211.07:48:39.85#ibcon#about to read 4, iclass 33, count 0 2006.211.07:48:39.85#ibcon#read 4, iclass 33, count 0 2006.211.07:48:39.85#ibcon#about to read 5, iclass 33, count 0 2006.211.07:48:39.85#ibcon#read 5, iclass 33, count 0 2006.211.07:48:39.85#ibcon#about to read 6, iclass 33, count 0 2006.211.07:48:39.85#ibcon#read 6, iclass 33, count 0 2006.211.07:48:39.85#ibcon#end of sib2, iclass 33, count 0 2006.211.07:48:39.85#ibcon#*after write, iclass 33, count 0 2006.211.07:48:39.85#ibcon#*before return 0, iclass 33, count 0 2006.211.07:48:39.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:48:39.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:48:39.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:48:39.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:48:39.85$vc4f8/valo=8,852.99 2006.211.07:48:39.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.07:48:39.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.07:48:39.85#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:39.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:48:39.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:48:39.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:48:39.85#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:48:39.85#ibcon#first serial, iclass 35, count 0 2006.211.07:48:39.85#ibcon#enter sib2, iclass 35, count 0 2006.211.07:48:39.85#ibcon#flushed, iclass 35, count 0 2006.211.07:48:39.85#ibcon#about to write, iclass 35, count 0 2006.211.07:48:39.85#ibcon#wrote, iclass 35, count 0 2006.211.07:48:39.85#ibcon#about to read 3, iclass 35, count 0 2006.211.07:48:39.87#ibcon#read 3, iclass 35, count 0 2006.211.07:48:39.87#ibcon#about to read 4, iclass 35, count 0 2006.211.07:48:39.87#ibcon#read 4, iclass 35, count 0 2006.211.07:48:39.87#ibcon#about to read 5, iclass 35, count 0 2006.211.07:48:39.87#ibcon#read 5, iclass 35, count 0 2006.211.07:48:39.87#ibcon#about to read 6, iclass 35, count 0 2006.211.07:48:39.87#ibcon#read 6, iclass 35, count 0 2006.211.07:48:39.87#ibcon#end of sib2, iclass 35, count 0 2006.211.07:48:39.87#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:48:39.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:48:39.87#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:48:39.87#ibcon#*before write, iclass 35, count 0 2006.211.07:48:39.87#ibcon#enter sib2, iclass 35, count 0 2006.211.07:48:39.87#ibcon#flushed, iclass 35, count 0 2006.211.07:48:39.87#ibcon#about to write, iclass 35, count 0 2006.211.07:48:39.87#ibcon#wrote, iclass 35, count 0 2006.211.07:48:39.87#ibcon#about to read 3, iclass 35, count 0 2006.211.07:48:39.91#ibcon#read 3, iclass 35, count 0 2006.211.07:48:39.91#ibcon#about to read 4, iclass 35, count 0 2006.211.07:48:39.91#ibcon#read 4, iclass 35, count 0 2006.211.07:48:39.91#ibcon#about to read 5, iclass 35, count 0 2006.211.07:48:39.91#ibcon#read 5, iclass 35, count 0 2006.211.07:48:39.91#ibcon#about to read 6, iclass 35, count 0 2006.211.07:48:39.91#ibcon#read 6, iclass 35, count 0 2006.211.07:48:39.91#ibcon#end of sib2, iclass 35, count 0 2006.211.07:48:39.91#ibcon#*after write, iclass 35, count 0 2006.211.07:48:39.91#ibcon#*before return 0, iclass 35, count 0 2006.211.07:48:39.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:48:39.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:48:39.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:48:39.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:48:39.91$vc4f8/va=8,7 2006.211.07:48:39.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.07:48:39.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.07:48:39.91#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:39.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:48:39.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:48:39.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:48:39.97#ibcon#enter wrdev, iclass 37, count 2 2006.211.07:48:39.97#ibcon#first serial, iclass 37, count 2 2006.211.07:48:39.97#ibcon#enter sib2, iclass 37, count 2 2006.211.07:48:39.97#ibcon#flushed, iclass 37, count 2 2006.211.07:48:39.97#ibcon#about to write, iclass 37, count 2 2006.211.07:48:39.97#ibcon#wrote, iclass 37, count 2 2006.211.07:48:39.97#ibcon#about to read 3, iclass 37, count 2 2006.211.07:48:39.99#ibcon#read 3, iclass 37, count 2 2006.211.07:48:39.99#ibcon#about to read 4, iclass 37, count 2 2006.211.07:48:39.99#ibcon#read 4, iclass 37, count 2 2006.211.07:48:39.99#ibcon#about to read 5, iclass 37, count 2 2006.211.07:48:39.99#ibcon#read 5, iclass 37, count 2 2006.211.07:48:39.99#ibcon#about to read 6, iclass 37, count 2 2006.211.07:48:39.99#ibcon#read 6, iclass 37, count 2 2006.211.07:48:39.99#ibcon#end of sib2, iclass 37, count 2 2006.211.07:48:39.99#ibcon#*mode == 0, iclass 37, count 2 2006.211.07:48:39.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.07:48:39.99#ibcon#[25=AT08-07\r\n] 2006.211.07:48:39.99#ibcon#*before write, iclass 37, count 2 2006.211.07:48:39.99#ibcon#enter sib2, iclass 37, count 2 2006.211.07:48:39.99#ibcon#flushed, iclass 37, count 2 2006.211.07:48:39.99#ibcon#about to write, iclass 37, count 2 2006.211.07:48:39.99#ibcon#wrote, iclass 37, count 2 2006.211.07:48:39.99#ibcon#about to read 3, iclass 37, count 2 2006.211.07:48:40.02#ibcon#read 3, iclass 37, count 2 2006.211.07:48:40.02#ibcon#about to read 4, iclass 37, count 2 2006.211.07:48:40.02#ibcon#read 4, iclass 37, count 2 2006.211.07:48:40.02#ibcon#about to read 5, iclass 37, count 2 2006.211.07:48:40.02#ibcon#read 5, iclass 37, count 2 2006.211.07:48:40.02#ibcon#about to read 6, iclass 37, count 2 2006.211.07:48:40.02#ibcon#read 6, iclass 37, count 2 2006.211.07:48:40.02#ibcon#end of sib2, iclass 37, count 2 2006.211.07:48:40.02#ibcon#*after write, iclass 37, count 2 2006.211.07:48:40.02#ibcon#*before return 0, iclass 37, count 2 2006.211.07:48:40.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:48:40.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:48:40.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.07:48:40.02#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:40.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:48:40.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:48:40.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:48:40.14#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:48:40.14#ibcon#first serial, iclass 37, count 0 2006.211.07:48:40.14#ibcon#enter sib2, iclass 37, count 0 2006.211.07:48:40.14#ibcon#flushed, iclass 37, count 0 2006.211.07:48:40.14#ibcon#about to write, iclass 37, count 0 2006.211.07:48:40.14#ibcon#wrote, iclass 37, count 0 2006.211.07:48:40.14#ibcon#about to read 3, iclass 37, count 0 2006.211.07:48:40.16#ibcon#read 3, iclass 37, count 0 2006.211.07:48:40.16#ibcon#about to read 4, iclass 37, count 0 2006.211.07:48:40.16#ibcon#read 4, iclass 37, count 0 2006.211.07:48:40.16#ibcon#about to read 5, iclass 37, count 0 2006.211.07:48:40.16#ibcon#read 5, iclass 37, count 0 2006.211.07:48:40.16#ibcon#about to read 6, iclass 37, count 0 2006.211.07:48:40.16#ibcon#read 6, iclass 37, count 0 2006.211.07:48:40.16#ibcon#end of sib2, iclass 37, count 0 2006.211.07:48:40.16#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:48:40.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:48:40.16#ibcon#[25=USB\r\n] 2006.211.07:48:40.16#ibcon#*before write, iclass 37, count 0 2006.211.07:48:40.16#ibcon#enter sib2, iclass 37, count 0 2006.211.07:48:40.16#ibcon#flushed, iclass 37, count 0 2006.211.07:48:40.16#ibcon#about to write, iclass 37, count 0 2006.211.07:48:40.16#ibcon#wrote, iclass 37, count 0 2006.211.07:48:40.16#ibcon#about to read 3, iclass 37, count 0 2006.211.07:48:40.19#ibcon#read 3, iclass 37, count 0 2006.211.07:48:40.19#ibcon#about to read 4, iclass 37, count 0 2006.211.07:48:40.19#ibcon#read 4, iclass 37, count 0 2006.211.07:48:40.19#ibcon#about to read 5, iclass 37, count 0 2006.211.07:48:40.19#ibcon#read 5, iclass 37, count 0 2006.211.07:48:40.19#ibcon#about to read 6, iclass 37, count 0 2006.211.07:48:40.19#ibcon#read 6, iclass 37, count 0 2006.211.07:48:40.19#ibcon#end of sib2, iclass 37, count 0 2006.211.07:48:40.19#ibcon#*after write, iclass 37, count 0 2006.211.07:48:40.19#ibcon#*before return 0, iclass 37, count 0 2006.211.07:48:40.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:48:40.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:48:40.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:48:40.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:48:40.19$vc4f8/vblo=1,632.99 2006.211.07:48:40.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.07:48:40.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.07:48:40.19#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:40.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:48:40.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:48:40.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:48:40.19#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:48:40.19#ibcon#first serial, iclass 39, count 0 2006.211.07:48:40.19#ibcon#enter sib2, iclass 39, count 0 2006.211.07:48:40.19#ibcon#flushed, iclass 39, count 0 2006.211.07:48:40.19#ibcon#about to write, iclass 39, count 0 2006.211.07:48:40.19#ibcon#wrote, iclass 39, count 0 2006.211.07:48:40.19#ibcon#about to read 3, iclass 39, count 0 2006.211.07:48:40.21#ibcon#read 3, iclass 39, count 0 2006.211.07:48:40.21#ibcon#about to read 4, iclass 39, count 0 2006.211.07:48:40.21#ibcon#read 4, iclass 39, count 0 2006.211.07:48:40.21#ibcon#about to read 5, iclass 39, count 0 2006.211.07:48:40.21#ibcon#read 5, iclass 39, count 0 2006.211.07:48:40.21#ibcon#about to read 6, iclass 39, count 0 2006.211.07:48:40.21#ibcon#read 6, iclass 39, count 0 2006.211.07:48:40.21#ibcon#end of sib2, iclass 39, count 0 2006.211.07:48:40.21#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:48:40.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:48:40.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:48:40.21#ibcon#*before write, iclass 39, count 0 2006.211.07:48:40.21#ibcon#enter sib2, iclass 39, count 0 2006.211.07:48:40.21#ibcon#flushed, iclass 39, count 0 2006.211.07:48:40.21#ibcon#about to write, iclass 39, count 0 2006.211.07:48:40.21#ibcon#wrote, iclass 39, count 0 2006.211.07:48:40.21#ibcon#about to read 3, iclass 39, count 0 2006.211.07:48:40.25#ibcon#read 3, iclass 39, count 0 2006.211.07:48:40.25#ibcon#about to read 4, iclass 39, count 0 2006.211.07:48:40.25#ibcon#read 4, iclass 39, count 0 2006.211.07:48:40.25#ibcon#about to read 5, iclass 39, count 0 2006.211.07:48:40.25#ibcon#read 5, iclass 39, count 0 2006.211.07:48:40.25#ibcon#about to read 6, iclass 39, count 0 2006.211.07:48:40.25#ibcon#read 6, iclass 39, count 0 2006.211.07:48:40.25#ibcon#end of sib2, iclass 39, count 0 2006.211.07:48:40.25#ibcon#*after write, iclass 39, count 0 2006.211.07:48:40.25#ibcon#*before return 0, iclass 39, count 0 2006.211.07:48:40.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:48:40.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:48:40.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:48:40.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:48:40.25$vc4f8/vb=1,4 2006.211.07:48:40.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.07:48:40.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.07:48:40.25#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:40.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:48:40.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:48:40.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:48:40.25#ibcon#enter wrdev, iclass 3, count 2 2006.211.07:48:40.25#ibcon#first serial, iclass 3, count 2 2006.211.07:48:40.25#ibcon#enter sib2, iclass 3, count 2 2006.211.07:48:40.25#ibcon#flushed, iclass 3, count 2 2006.211.07:48:40.25#ibcon#about to write, iclass 3, count 2 2006.211.07:48:40.25#ibcon#wrote, iclass 3, count 2 2006.211.07:48:40.25#ibcon#about to read 3, iclass 3, count 2 2006.211.07:48:40.27#ibcon#read 3, iclass 3, count 2 2006.211.07:48:40.27#ibcon#about to read 4, iclass 3, count 2 2006.211.07:48:40.27#ibcon#read 4, iclass 3, count 2 2006.211.07:48:40.27#ibcon#about to read 5, iclass 3, count 2 2006.211.07:48:40.27#ibcon#read 5, iclass 3, count 2 2006.211.07:48:40.27#ibcon#about to read 6, iclass 3, count 2 2006.211.07:48:40.27#ibcon#read 6, iclass 3, count 2 2006.211.07:48:40.27#ibcon#end of sib2, iclass 3, count 2 2006.211.07:48:40.27#ibcon#*mode == 0, iclass 3, count 2 2006.211.07:48:40.27#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.07:48:40.27#ibcon#[27=AT01-04\r\n] 2006.211.07:48:40.27#ibcon#*before write, iclass 3, count 2 2006.211.07:48:40.27#ibcon#enter sib2, iclass 3, count 2 2006.211.07:48:40.27#ibcon#flushed, iclass 3, count 2 2006.211.07:48:40.27#ibcon#about to write, iclass 3, count 2 2006.211.07:48:40.27#ibcon#wrote, iclass 3, count 2 2006.211.07:48:40.27#ibcon#about to read 3, iclass 3, count 2 2006.211.07:48:40.30#ibcon#read 3, iclass 3, count 2 2006.211.07:48:40.30#ibcon#about to read 4, iclass 3, count 2 2006.211.07:48:40.30#ibcon#read 4, iclass 3, count 2 2006.211.07:48:40.30#ibcon#about to read 5, iclass 3, count 2 2006.211.07:48:40.30#ibcon#read 5, iclass 3, count 2 2006.211.07:48:40.30#ibcon#about to read 6, iclass 3, count 2 2006.211.07:48:40.30#ibcon#read 6, iclass 3, count 2 2006.211.07:48:40.30#ibcon#end of sib2, iclass 3, count 2 2006.211.07:48:40.30#ibcon#*after write, iclass 3, count 2 2006.211.07:48:40.30#ibcon#*before return 0, iclass 3, count 2 2006.211.07:48:40.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:48:40.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:48:40.30#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.07:48:40.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:40.30#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:48:40.42#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:48:40.42#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:48:40.42#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:48:40.42#ibcon#first serial, iclass 3, count 0 2006.211.07:48:40.42#ibcon#enter sib2, iclass 3, count 0 2006.211.07:48:40.42#ibcon#flushed, iclass 3, count 0 2006.211.07:48:40.42#ibcon#about to write, iclass 3, count 0 2006.211.07:48:40.42#ibcon#wrote, iclass 3, count 0 2006.211.07:48:40.42#ibcon#about to read 3, iclass 3, count 0 2006.211.07:48:40.44#ibcon#read 3, iclass 3, count 0 2006.211.07:48:40.44#ibcon#about to read 4, iclass 3, count 0 2006.211.07:48:40.44#ibcon#read 4, iclass 3, count 0 2006.211.07:48:40.44#ibcon#about to read 5, iclass 3, count 0 2006.211.07:48:40.44#ibcon#read 5, iclass 3, count 0 2006.211.07:48:40.44#ibcon#about to read 6, iclass 3, count 0 2006.211.07:48:40.44#ibcon#read 6, iclass 3, count 0 2006.211.07:48:40.44#ibcon#end of sib2, iclass 3, count 0 2006.211.07:48:40.44#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:48:40.44#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:48:40.44#ibcon#[27=USB\r\n] 2006.211.07:48:40.44#ibcon#*before write, iclass 3, count 0 2006.211.07:48:40.44#ibcon#enter sib2, iclass 3, count 0 2006.211.07:48:40.44#ibcon#flushed, iclass 3, count 0 2006.211.07:48:40.44#ibcon#about to write, iclass 3, count 0 2006.211.07:48:40.44#ibcon#wrote, iclass 3, count 0 2006.211.07:48:40.44#ibcon#about to read 3, iclass 3, count 0 2006.211.07:48:40.47#ibcon#read 3, iclass 3, count 0 2006.211.07:48:40.47#ibcon#about to read 4, iclass 3, count 0 2006.211.07:48:40.47#ibcon#read 4, iclass 3, count 0 2006.211.07:48:40.47#ibcon#about to read 5, iclass 3, count 0 2006.211.07:48:40.47#ibcon#read 5, iclass 3, count 0 2006.211.07:48:40.47#ibcon#about to read 6, iclass 3, count 0 2006.211.07:48:40.47#ibcon#read 6, iclass 3, count 0 2006.211.07:48:40.47#ibcon#end of sib2, iclass 3, count 0 2006.211.07:48:40.47#ibcon#*after write, iclass 3, count 0 2006.211.07:48:40.47#ibcon#*before return 0, iclass 3, count 0 2006.211.07:48:40.47#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:48:40.47#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:48:40.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:48:40.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:48:40.47$vc4f8/vblo=2,640.99 2006.211.07:48:40.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.07:48:40.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.07:48:40.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:40.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:40.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:40.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:40.47#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:48:40.47#ibcon#first serial, iclass 5, count 0 2006.211.07:48:40.47#ibcon#enter sib2, iclass 5, count 0 2006.211.07:48:40.47#ibcon#flushed, iclass 5, count 0 2006.211.07:48:40.47#ibcon#about to write, iclass 5, count 0 2006.211.07:48:40.47#ibcon#wrote, iclass 5, count 0 2006.211.07:48:40.47#ibcon#about to read 3, iclass 5, count 0 2006.211.07:48:40.49#ibcon#read 3, iclass 5, count 0 2006.211.07:48:40.49#ibcon#about to read 4, iclass 5, count 0 2006.211.07:48:40.49#ibcon#read 4, iclass 5, count 0 2006.211.07:48:40.49#ibcon#about to read 5, iclass 5, count 0 2006.211.07:48:40.49#ibcon#read 5, iclass 5, count 0 2006.211.07:48:40.49#ibcon#about to read 6, iclass 5, count 0 2006.211.07:48:40.49#ibcon#read 6, iclass 5, count 0 2006.211.07:48:40.49#ibcon#end of sib2, iclass 5, count 0 2006.211.07:48:40.49#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:48:40.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:48:40.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:48:40.49#ibcon#*before write, iclass 5, count 0 2006.211.07:48:40.49#ibcon#enter sib2, iclass 5, count 0 2006.211.07:48:40.49#ibcon#flushed, iclass 5, count 0 2006.211.07:48:40.49#ibcon#about to write, iclass 5, count 0 2006.211.07:48:40.49#ibcon#wrote, iclass 5, count 0 2006.211.07:48:40.49#ibcon#about to read 3, iclass 5, count 0 2006.211.07:48:40.53#ibcon#read 3, iclass 5, count 0 2006.211.07:48:40.53#ibcon#about to read 4, iclass 5, count 0 2006.211.07:48:40.53#ibcon#read 4, iclass 5, count 0 2006.211.07:48:40.53#ibcon#about to read 5, iclass 5, count 0 2006.211.07:48:40.53#ibcon#read 5, iclass 5, count 0 2006.211.07:48:40.53#ibcon#about to read 6, iclass 5, count 0 2006.211.07:48:40.53#ibcon#read 6, iclass 5, count 0 2006.211.07:48:40.53#ibcon#end of sib2, iclass 5, count 0 2006.211.07:48:40.53#ibcon#*after write, iclass 5, count 0 2006.211.07:48:40.53#ibcon#*before return 0, iclass 5, count 0 2006.211.07:48:40.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:40.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:48:40.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:48:40.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:48:40.53$vc4f8/vb=2,4 2006.211.07:48:40.53#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.07:48:40.53#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.07:48:40.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:40.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:40.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:40.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:40.59#ibcon#enter wrdev, iclass 7, count 2 2006.211.07:48:40.59#ibcon#first serial, iclass 7, count 2 2006.211.07:48:40.59#ibcon#enter sib2, iclass 7, count 2 2006.211.07:48:40.59#ibcon#flushed, iclass 7, count 2 2006.211.07:48:40.59#ibcon#about to write, iclass 7, count 2 2006.211.07:48:40.59#ibcon#wrote, iclass 7, count 2 2006.211.07:48:40.59#ibcon#about to read 3, iclass 7, count 2 2006.211.07:48:40.61#ibcon#read 3, iclass 7, count 2 2006.211.07:48:40.61#ibcon#about to read 4, iclass 7, count 2 2006.211.07:48:40.61#ibcon#read 4, iclass 7, count 2 2006.211.07:48:40.61#ibcon#about to read 5, iclass 7, count 2 2006.211.07:48:40.61#ibcon#read 5, iclass 7, count 2 2006.211.07:48:40.61#ibcon#about to read 6, iclass 7, count 2 2006.211.07:48:40.61#ibcon#read 6, iclass 7, count 2 2006.211.07:48:40.61#ibcon#end of sib2, iclass 7, count 2 2006.211.07:48:40.61#ibcon#*mode == 0, iclass 7, count 2 2006.211.07:48:40.61#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.07:48:40.61#ibcon#[27=AT02-04\r\n] 2006.211.07:48:40.61#ibcon#*before write, iclass 7, count 2 2006.211.07:48:40.61#ibcon#enter sib2, iclass 7, count 2 2006.211.07:48:40.61#ibcon#flushed, iclass 7, count 2 2006.211.07:48:40.61#ibcon#about to write, iclass 7, count 2 2006.211.07:48:40.61#ibcon#wrote, iclass 7, count 2 2006.211.07:48:40.61#ibcon#about to read 3, iclass 7, count 2 2006.211.07:48:40.64#ibcon#read 3, iclass 7, count 2 2006.211.07:48:40.64#ibcon#about to read 4, iclass 7, count 2 2006.211.07:48:40.64#ibcon#read 4, iclass 7, count 2 2006.211.07:48:40.64#ibcon#about to read 5, iclass 7, count 2 2006.211.07:48:40.64#ibcon#read 5, iclass 7, count 2 2006.211.07:48:40.64#ibcon#about to read 6, iclass 7, count 2 2006.211.07:48:40.64#ibcon#read 6, iclass 7, count 2 2006.211.07:48:40.64#ibcon#end of sib2, iclass 7, count 2 2006.211.07:48:40.64#ibcon#*after write, iclass 7, count 2 2006.211.07:48:40.64#ibcon#*before return 0, iclass 7, count 2 2006.211.07:48:40.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:40.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:48:40.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.07:48:40.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:40.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:40.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:40.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:40.76#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:48:40.76#ibcon#first serial, iclass 7, count 0 2006.211.07:48:40.76#ibcon#enter sib2, iclass 7, count 0 2006.211.07:48:40.76#ibcon#flushed, iclass 7, count 0 2006.211.07:48:40.76#ibcon#about to write, iclass 7, count 0 2006.211.07:48:40.76#ibcon#wrote, iclass 7, count 0 2006.211.07:48:40.76#ibcon#about to read 3, iclass 7, count 0 2006.211.07:48:40.78#ibcon#read 3, iclass 7, count 0 2006.211.07:48:40.78#ibcon#about to read 4, iclass 7, count 0 2006.211.07:48:40.78#ibcon#read 4, iclass 7, count 0 2006.211.07:48:40.78#ibcon#about to read 5, iclass 7, count 0 2006.211.07:48:40.78#ibcon#read 5, iclass 7, count 0 2006.211.07:48:40.78#ibcon#about to read 6, iclass 7, count 0 2006.211.07:48:40.78#ibcon#read 6, iclass 7, count 0 2006.211.07:48:40.78#ibcon#end of sib2, iclass 7, count 0 2006.211.07:48:40.78#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:48:40.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:48:40.78#ibcon#[27=USB\r\n] 2006.211.07:48:40.78#ibcon#*before write, iclass 7, count 0 2006.211.07:48:40.78#ibcon#enter sib2, iclass 7, count 0 2006.211.07:48:40.78#ibcon#flushed, iclass 7, count 0 2006.211.07:48:40.78#ibcon#about to write, iclass 7, count 0 2006.211.07:48:40.78#ibcon#wrote, iclass 7, count 0 2006.211.07:48:40.78#ibcon#about to read 3, iclass 7, count 0 2006.211.07:48:40.81#ibcon#read 3, iclass 7, count 0 2006.211.07:48:40.81#ibcon#about to read 4, iclass 7, count 0 2006.211.07:48:40.81#ibcon#read 4, iclass 7, count 0 2006.211.07:48:40.81#ibcon#about to read 5, iclass 7, count 0 2006.211.07:48:40.81#ibcon#read 5, iclass 7, count 0 2006.211.07:48:40.81#ibcon#about to read 6, iclass 7, count 0 2006.211.07:48:40.81#ibcon#read 6, iclass 7, count 0 2006.211.07:48:40.81#ibcon#end of sib2, iclass 7, count 0 2006.211.07:48:40.81#ibcon#*after write, iclass 7, count 0 2006.211.07:48:40.81#ibcon#*before return 0, iclass 7, count 0 2006.211.07:48:40.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:40.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:48:40.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:48:40.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:48:40.81$vc4f8/vblo=3,656.99 2006.211.07:48:40.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:48:40.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:48:40.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:40.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:40.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:40.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:40.81#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:48:40.81#ibcon#first serial, iclass 11, count 0 2006.211.07:48:40.81#ibcon#enter sib2, iclass 11, count 0 2006.211.07:48:40.81#ibcon#flushed, iclass 11, count 0 2006.211.07:48:40.81#ibcon#about to write, iclass 11, count 0 2006.211.07:48:40.81#ibcon#wrote, iclass 11, count 0 2006.211.07:48:40.81#ibcon#about to read 3, iclass 11, count 0 2006.211.07:48:40.83#ibcon#read 3, iclass 11, count 0 2006.211.07:48:40.83#ibcon#about to read 4, iclass 11, count 0 2006.211.07:48:40.83#ibcon#read 4, iclass 11, count 0 2006.211.07:48:40.83#ibcon#about to read 5, iclass 11, count 0 2006.211.07:48:40.83#ibcon#read 5, iclass 11, count 0 2006.211.07:48:40.83#ibcon#about to read 6, iclass 11, count 0 2006.211.07:48:40.83#ibcon#read 6, iclass 11, count 0 2006.211.07:48:40.83#ibcon#end of sib2, iclass 11, count 0 2006.211.07:48:40.83#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:48:40.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:48:40.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:48:40.83#ibcon#*before write, iclass 11, count 0 2006.211.07:48:40.83#ibcon#enter sib2, iclass 11, count 0 2006.211.07:48:40.83#ibcon#flushed, iclass 11, count 0 2006.211.07:48:40.83#ibcon#about to write, iclass 11, count 0 2006.211.07:48:40.83#ibcon#wrote, iclass 11, count 0 2006.211.07:48:40.83#ibcon#about to read 3, iclass 11, count 0 2006.211.07:48:40.87#ibcon#read 3, iclass 11, count 0 2006.211.07:48:40.87#ibcon#about to read 4, iclass 11, count 0 2006.211.07:48:40.87#ibcon#read 4, iclass 11, count 0 2006.211.07:48:40.87#ibcon#about to read 5, iclass 11, count 0 2006.211.07:48:40.87#ibcon#read 5, iclass 11, count 0 2006.211.07:48:40.87#ibcon#about to read 6, iclass 11, count 0 2006.211.07:48:40.87#ibcon#read 6, iclass 11, count 0 2006.211.07:48:40.87#ibcon#end of sib2, iclass 11, count 0 2006.211.07:48:40.87#ibcon#*after write, iclass 11, count 0 2006.211.07:48:40.87#ibcon#*before return 0, iclass 11, count 0 2006.211.07:48:40.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:40.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:48:40.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:48:40.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:48:40.87$vc4f8/vb=3,3 2006.211.07:48:40.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.07:48:40.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.07:48:40.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:40.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:40.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:40.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:40.93#ibcon#enter wrdev, iclass 13, count 2 2006.211.07:48:40.93#ibcon#first serial, iclass 13, count 2 2006.211.07:48:40.93#ibcon#enter sib2, iclass 13, count 2 2006.211.07:48:40.93#ibcon#flushed, iclass 13, count 2 2006.211.07:48:40.93#ibcon#about to write, iclass 13, count 2 2006.211.07:48:40.93#ibcon#wrote, iclass 13, count 2 2006.211.07:48:40.93#ibcon#about to read 3, iclass 13, count 2 2006.211.07:48:40.95#ibcon#read 3, iclass 13, count 2 2006.211.07:48:40.95#ibcon#about to read 4, iclass 13, count 2 2006.211.07:48:40.95#ibcon#read 4, iclass 13, count 2 2006.211.07:48:40.95#ibcon#about to read 5, iclass 13, count 2 2006.211.07:48:40.95#ibcon#read 5, iclass 13, count 2 2006.211.07:48:40.95#ibcon#about to read 6, iclass 13, count 2 2006.211.07:48:40.95#ibcon#read 6, iclass 13, count 2 2006.211.07:48:40.95#ibcon#end of sib2, iclass 13, count 2 2006.211.07:48:40.95#ibcon#*mode == 0, iclass 13, count 2 2006.211.07:48:40.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.07:48:40.95#ibcon#[27=AT03-03\r\n] 2006.211.07:48:40.95#ibcon#*before write, iclass 13, count 2 2006.211.07:48:40.95#ibcon#enter sib2, iclass 13, count 2 2006.211.07:48:40.95#ibcon#flushed, iclass 13, count 2 2006.211.07:48:40.95#ibcon#about to write, iclass 13, count 2 2006.211.07:48:40.95#ibcon#wrote, iclass 13, count 2 2006.211.07:48:40.95#ibcon#about to read 3, iclass 13, count 2 2006.211.07:48:40.98#ibcon#read 3, iclass 13, count 2 2006.211.07:48:40.98#ibcon#about to read 4, iclass 13, count 2 2006.211.07:48:40.98#ibcon#read 4, iclass 13, count 2 2006.211.07:48:40.98#ibcon#about to read 5, iclass 13, count 2 2006.211.07:48:40.98#ibcon#read 5, iclass 13, count 2 2006.211.07:48:40.98#ibcon#about to read 6, iclass 13, count 2 2006.211.07:48:40.98#ibcon#read 6, iclass 13, count 2 2006.211.07:48:40.98#ibcon#end of sib2, iclass 13, count 2 2006.211.07:48:40.98#ibcon#*after write, iclass 13, count 2 2006.211.07:48:40.98#ibcon#*before return 0, iclass 13, count 2 2006.211.07:48:40.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:40.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:48:40.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.07:48:40.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:40.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:41.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:41.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:41.10#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:48:41.10#ibcon#first serial, iclass 13, count 0 2006.211.07:48:41.10#ibcon#enter sib2, iclass 13, count 0 2006.211.07:48:41.10#ibcon#flushed, iclass 13, count 0 2006.211.07:48:41.10#ibcon#about to write, iclass 13, count 0 2006.211.07:48:41.10#ibcon#wrote, iclass 13, count 0 2006.211.07:48:41.10#ibcon#about to read 3, iclass 13, count 0 2006.211.07:48:41.12#ibcon#read 3, iclass 13, count 0 2006.211.07:48:41.12#ibcon#about to read 4, iclass 13, count 0 2006.211.07:48:41.12#ibcon#read 4, iclass 13, count 0 2006.211.07:48:41.12#ibcon#about to read 5, iclass 13, count 0 2006.211.07:48:41.12#ibcon#read 5, iclass 13, count 0 2006.211.07:48:41.12#ibcon#about to read 6, iclass 13, count 0 2006.211.07:48:41.12#ibcon#read 6, iclass 13, count 0 2006.211.07:48:41.12#ibcon#end of sib2, iclass 13, count 0 2006.211.07:48:41.12#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:48:41.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:48:41.12#ibcon#[27=USB\r\n] 2006.211.07:48:41.12#ibcon#*before write, iclass 13, count 0 2006.211.07:48:41.12#ibcon#enter sib2, iclass 13, count 0 2006.211.07:48:41.12#ibcon#flushed, iclass 13, count 0 2006.211.07:48:41.12#ibcon#about to write, iclass 13, count 0 2006.211.07:48:41.12#ibcon#wrote, iclass 13, count 0 2006.211.07:48:41.12#ibcon#about to read 3, iclass 13, count 0 2006.211.07:48:41.15#ibcon#read 3, iclass 13, count 0 2006.211.07:48:41.15#ibcon#about to read 4, iclass 13, count 0 2006.211.07:48:41.15#ibcon#read 4, iclass 13, count 0 2006.211.07:48:41.15#ibcon#about to read 5, iclass 13, count 0 2006.211.07:48:41.15#ibcon#read 5, iclass 13, count 0 2006.211.07:48:41.15#ibcon#about to read 6, iclass 13, count 0 2006.211.07:48:41.15#ibcon#read 6, iclass 13, count 0 2006.211.07:48:41.15#ibcon#end of sib2, iclass 13, count 0 2006.211.07:48:41.15#ibcon#*after write, iclass 13, count 0 2006.211.07:48:41.15#ibcon#*before return 0, iclass 13, count 0 2006.211.07:48:41.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:41.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:48:41.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:48:41.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:48:41.15$vc4f8/vblo=4,712.99 2006.211.07:48:41.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:48:41.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:48:41.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:41.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:41.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:41.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:41.15#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:48:41.15#ibcon#first serial, iclass 15, count 0 2006.211.07:48:41.15#ibcon#enter sib2, iclass 15, count 0 2006.211.07:48:41.15#ibcon#flushed, iclass 15, count 0 2006.211.07:48:41.15#ibcon#about to write, iclass 15, count 0 2006.211.07:48:41.15#ibcon#wrote, iclass 15, count 0 2006.211.07:48:41.15#ibcon#about to read 3, iclass 15, count 0 2006.211.07:48:41.17#ibcon#read 3, iclass 15, count 0 2006.211.07:48:41.17#ibcon#about to read 4, iclass 15, count 0 2006.211.07:48:41.17#ibcon#read 4, iclass 15, count 0 2006.211.07:48:41.17#ibcon#about to read 5, iclass 15, count 0 2006.211.07:48:41.17#ibcon#read 5, iclass 15, count 0 2006.211.07:48:41.17#ibcon#about to read 6, iclass 15, count 0 2006.211.07:48:41.17#ibcon#read 6, iclass 15, count 0 2006.211.07:48:41.17#ibcon#end of sib2, iclass 15, count 0 2006.211.07:48:41.17#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:48:41.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:48:41.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:48:41.17#ibcon#*before write, iclass 15, count 0 2006.211.07:48:41.17#ibcon#enter sib2, iclass 15, count 0 2006.211.07:48:41.17#ibcon#flushed, iclass 15, count 0 2006.211.07:48:41.17#ibcon#about to write, iclass 15, count 0 2006.211.07:48:41.17#ibcon#wrote, iclass 15, count 0 2006.211.07:48:41.17#ibcon#about to read 3, iclass 15, count 0 2006.211.07:48:41.21#ibcon#read 3, iclass 15, count 0 2006.211.07:48:41.21#ibcon#about to read 4, iclass 15, count 0 2006.211.07:48:41.21#ibcon#read 4, iclass 15, count 0 2006.211.07:48:41.21#ibcon#about to read 5, iclass 15, count 0 2006.211.07:48:41.21#ibcon#read 5, iclass 15, count 0 2006.211.07:48:41.21#ibcon#about to read 6, iclass 15, count 0 2006.211.07:48:41.21#ibcon#read 6, iclass 15, count 0 2006.211.07:48:41.21#ibcon#end of sib2, iclass 15, count 0 2006.211.07:48:41.21#ibcon#*after write, iclass 15, count 0 2006.211.07:48:41.21#ibcon#*before return 0, iclass 15, count 0 2006.211.07:48:41.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:41.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:48:41.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:48:41.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:48:41.21$vc4f8/vb=4,3 2006.211.07:48:41.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.07:48:41.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.07:48:41.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:41.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:41.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:41.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:41.27#ibcon#enter wrdev, iclass 17, count 2 2006.211.07:48:41.27#ibcon#first serial, iclass 17, count 2 2006.211.07:48:41.27#ibcon#enter sib2, iclass 17, count 2 2006.211.07:48:41.27#ibcon#flushed, iclass 17, count 2 2006.211.07:48:41.27#ibcon#about to write, iclass 17, count 2 2006.211.07:48:41.27#ibcon#wrote, iclass 17, count 2 2006.211.07:48:41.27#ibcon#about to read 3, iclass 17, count 2 2006.211.07:48:41.29#ibcon#read 3, iclass 17, count 2 2006.211.07:48:41.29#ibcon#about to read 4, iclass 17, count 2 2006.211.07:48:41.29#ibcon#read 4, iclass 17, count 2 2006.211.07:48:41.29#ibcon#about to read 5, iclass 17, count 2 2006.211.07:48:41.29#ibcon#read 5, iclass 17, count 2 2006.211.07:48:41.29#ibcon#about to read 6, iclass 17, count 2 2006.211.07:48:41.29#ibcon#read 6, iclass 17, count 2 2006.211.07:48:41.29#ibcon#end of sib2, iclass 17, count 2 2006.211.07:48:41.29#ibcon#*mode == 0, iclass 17, count 2 2006.211.07:48:41.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.07:48:41.29#ibcon#[27=AT04-03\r\n] 2006.211.07:48:41.29#ibcon#*before write, iclass 17, count 2 2006.211.07:48:41.29#ibcon#enter sib2, iclass 17, count 2 2006.211.07:48:41.29#ibcon#flushed, iclass 17, count 2 2006.211.07:48:41.29#ibcon#about to write, iclass 17, count 2 2006.211.07:48:41.29#ibcon#wrote, iclass 17, count 2 2006.211.07:48:41.29#ibcon#about to read 3, iclass 17, count 2 2006.211.07:48:41.32#ibcon#read 3, iclass 17, count 2 2006.211.07:48:41.32#ibcon#about to read 4, iclass 17, count 2 2006.211.07:48:41.32#ibcon#read 4, iclass 17, count 2 2006.211.07:48:41.32#ibcon#about to read 5, iclass 17, count 2 2006.211.07:48:41.32#ibcon#read 5, iclass 17, count 2 2006.211.07:48:41.32#ibcon#about to read 6, iclass 17, count 2 2006.211.07:48:41.32#ibcon#read 6, iclass 17, count 2 2006.211.07:48:41.32#ibcon#end of sib2, iclass 17, count 2 2006.211.07:48:41.32#ibcon#*after write, iclass 17, count 2 2006.211.07:48:41.32#ibcon#*before return 0, iclass 17, count 2 2006.211.07:48:41.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:41.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:48:41.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.07:48:41.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:41.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:41.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:41.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:41.44#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:48:41.44#ibcon#first serial, iclass 17, count 0 2006.211.07:48:41.44#ibcon#enter sib2, iclass 17, count 0 2006.211.07:48:41.44#ibcon#flushed, iclass 17, count 0 2006.211.07:48:41.44#ibcon#about to write, iclass 17, count 0 2006.211.07:48:41.44#ibcon#wrote, iclass 17, count 0 2006.211.07:48:41.44#ibcon#about to read 3, iclass 17, count 0 2006.211.07:48:41.46#ibcon#read 3, iclass 17, count 0 2006.211.07:48:41.46#ibcon#about to read 4, iclass 17, count 0 2006.211.07:48:41.46#ibcon#read 4, iclass 17, count 0 2006.211.07:48:41.46#ibcon#about to read 5, iclass 17, count 0 2006.211.07:48:41.46#ibcon#read 5, iclass 17, count 0 2006.211.07:48:41.46#ibcon#about to read 6, iclass 17, count 0 2006.211.07:48:41.46#ibcon#read 6, iclass 17, count 0 2006.211.07:48:41.46#ibcon#end of sib2, iclass 17, count 0 2006.211.07:48:41.46#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:48:41.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:48:41.46#ibcon#[27=USB\r\n] 2006.211.07:48:41.46#ibcon#*before write, iclass 17, count 0 2006.211.07:48:41.46#ibcon#enter sib2, iclass 17, count 0 2006.211.07:48:41.46#ibcon#flushed, iclass 17, count 0 2006.211.07:48:41.46#ibcon#about to write, iclass 17, count 0 2006.211.07:48:41.46#ibcon#wrote, iclass 17, count 0 2006.211.07:48:41.46#ibcon#about to read 3, iclass 17, count 0 2006.211.07:48:41.49#ibcon#read 3, iclass 17, count 0 2006.211.07:48:41.49#ibcon#about to read 4, iclass 17, count 0 2006.211.07:48:41.49#ibcon#read 4, iclass 17, count 0 2006.211.07:48:41.49#ibcon#about to read 5, iclass 17, count 0 2006.211.07:48:41.49#ibcon#read 5, iclass 17, count 0 2006.211.07:48:41.49#ibcon#about to read 6, iclass 17, count 0 2006.211.07:48:41.49#ibcon#read 6, iclass 17, count 0 2006.211.07:48:41.49#ibcon#end of sib2, iclass 17, count 0 2006.211.07:48:41.49#ibcon#*after write, iclass 17, count 0 2006.211.07:48:41.49#ibcon#*before return 0, iclass 17, count 0 2006.211.07:48:41.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:41.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:48:41.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:48:41.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:48:41.49$vc4f8/vblo=5,744.99 2006.211.07:48:41.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.07:48:41.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.07:48:41.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:41.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:41.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:41.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:41.49#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:48:41.49#ibcon#first serial, iclass 19, count 0 2006.211.07:48:41.49#ibcon#enter sib2, iclass 19, count 0 2006.211.07:48:41.49#ibcon#flushed, iclass 19, count 0 2006.211.07:48:41.49#ibcon#about to write, iclass 19, count 0 2006.211.07:48:41.49#ibcon#wrote, iclass 19, count 0 2006.211.07:48:41.49#ibcon#about to read 3, iclass 19, count 0 2006.211.07:48:41.51#ibcon#read 3, iclass 19, count 0 2006.211.07:48:41.51#ibcon#about to read 4, iclass 19, count 0 2006.211.07:48:41.51#ibcon#read 4, iclass 19, count 0 2006.211.07:48:41.51#ibcon#about to read 5, iclass 19, count 0 2006.211.07:48:41.51#ibcon#read 5, iclass 19, count 0 2006.211.07:48:41.51#ibcon#about to read 6, iclass 19, count 0 2006.211.07:48:41.51#ibcon#read 6, iclass 19, count 0 2006.211.07:48:41.51#ibcon#end of sib2, iclass 19, count 0 2006.211.07:48:41.51#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:48:41.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:48:41.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:48:41.51#ibcon#*before write, iclass 19, count 0 2006.211.07:48:41.51#ibcon#enter sib2, iclass 19, count 0 2006.211.07:48:41.51#ibcon#flushed, iclass 19, count 0 2006.211.07:48:41.51#ibcon#about to write, iclass 19, count 0 2006.211.07:48:41.51#ibcon#wrote, iclass 19, count 0 2006.211.07:48:41.51#ibcon#about to read 3, iclass 19, count 0 2006.211.07:48:41.55#ibcon#read 3, iclass 19, count 0 2006.211.07:48:41.55#ibcon#about to read 4, iclass 19, count 0 2006.211.07:48:41.55#ibcon#read 4, iclass 19, count 0 2006.211.07:48:41.55#ibcon#about to read 5, iclass 19, count 0 2006.211.07:48:41.55#ibcon#read 5, iclass 19, count 0 2006.211.07:48:41.55#ibcon#about to read 6, iclass 19, count 0 2006.211.07:48:41.55#ibcon#read 6, iclass 19, count 0 2006.211.07:48:41.55#ibcon#end of sib2, iclass 19, count 0 2006.211.07:48:41.55#ibcon#*after write, iclass 19, count 0 2006.211.07:48:41.55#ibcon#*before return 0, iclass 19, count 0 2006.211.07:48:41.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:41.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:48:41.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:48:41.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:48:41.55$vc4f8/vb=5,3 2006.211.07:48:41.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.07:48:41.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.07:48:41.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:41.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:41.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:41.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:41.61#ibcon#enter wrdev, iclass 21, count 2 2006.211.07:48:41.61#ibcon#first serial, iclass 21, count 2 2006.211.07:48:41.61#ibcon#enter sib2, iclass 21, count 2 2006.211.07:48:41.61#ibcon#flushed, iclass 21, count 2 2006.211.07:48:41.61#ibcon#about to write, iclass 21, count 2 2006.211.07:48:41.61#ibcon#wrote, iclass 21, count 2 2006.211.07:48:41.61#ibcon#about to read 3, iclass 21, count 2 2006.211.07:48:41.63#ibcon#read 3, iclass 21, count 2 2006.211.07:48:41.63#ibcon#about to read 4, iclass 21, count 2 2006.211.07:48:41.63#ibcon#read 4, iclass 21, count 2 2006.211.07:48:41.63#ibcon#about to read 5, iclass 21, count 2 2006.211.07:48:41.63#ibcon#read 5, iclass 21, count 2 2006.211.07:48:41.63#ibcon#about to read 6, iclass 21, count 2 2006.211.07:48:41.63#ibcon#read 6, iclass 21, count 2 2006.211.07:48:41.63#ibcon#end of sib2, iclass 21, count 2 2006.211.07:48:41.63#ibcon#*mode == 0, iclass 21, count 2 2006.211.07:48:41.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.07:48:41.63#ibcon#[27=AT05-03\r\n] 2006.211.07:48:41.63#ibcon#*before write, iclass 21, count 2 2006.211.07:48:41.63#ibcon#enter sib2, iclass 21, count 2 2006.211.07:48:41.63#ibcon#flushed, iclass 21, count 2 2006.211.07:48:41.63#ibcon#about to write, iclass 21, count 2 2006.211.07:48:41.63#ibcon#wrote, iclass 21, count 2 2006.211.07:48:41.63#ibcon#about to read 3, iclass 21, count 2 2006.211.07:48:41.66#ibcon#read 3, iclass 21, count 2 2006.211.07:48:41.66#ibcon#about to read 4, iclass 21, count 2 2006.211.07:48:41.66#ibcon#read 4, iclass 21, count 2 2006.211.07:48:41.66#ibcon#about to read 5, iclass 21, count 2 2006.211.07:48:41.66#ibcon#read 5, iclass 21, count 2 2006.211.07:48:41.66#ibcon#about to read 6, iclass 21, count 2 2006.211.07:48:41.66#ibcon#read 6, iclass 21, count 2 2006.211.07:48:41.66#ibcon#end of sib2, iclass 21, count 2 2006.211.07:48:41.66#ibcon#*after write, iclass 21, count 2 2006.211.07:48:41.66#ibcon#*before return 0, iclass 21, count 2 2006.211.07:48:41.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:41.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:48:41.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.07:48:41.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:41.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:41.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:41.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:41.78#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:48:41.78#ibcon#first serial, iclass 21, count 0 2006.211.07:48:41.78#ibcon#enter sib2, iclass 21, count 0 2006.211.07:48:41.78#ibcon#flushed, iclass 21, count 0 2006.211.07:48:41.78#ibcon#about to write, iclass 21, count 0 2006.211.07:48:41.78#ibcon#wrote, iclass 21, count 0 2006.211.07:48:41.78#ibcon#about to read 3, iclass 21, count 0 2006.211.07:48:41.80#ibcon#read 3, iclass 21, count 0 2006.211.07:48:41.80#ibcon#about to read 4, iclass 21, count 0 2006.211.07:48:41.80#ibcon#read 4, iclass 21, count 0 2006.211.07:48:41.80#ibcon#about to read 5, iclass 21, count 0 2006.211.07:48:41.80#ibcon#read 5, iclass 21, count 0 2006.211.07:48:41.80#ibcon#about to read 6, iclass 21, count 0 2006.211.07:48:41.80#ibcon#read 6, iclass 21, count 0 2006.211.07:48:41.80#ibcon#end of sib2, iclass 21, count 0 2006.211.07:48:41.80#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:48:41.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:48:41.80#ibcon#[27=USB\r\n] 2006.211.07:48:41.80#ibcon#*before write, iclass 21, count 0 2006.211.07:48:41.80#ibcon#enter sib2, iclass 21, count 0 2006.211.07:48:41.80#ibcon#flushed, iclass 21, count 0 2006.211.07:48:41.80#ibcon#about to write, iclass 21, count 0 2006.211.07:48:41.80#ibcon#wrote, iclass 21, count 0 2006.211.07:48:41.80#ibcon#about to read 3, iclass 21, count 0 2006.211.07:48:41.83#ibcon#read 3, iclass 21, count 0 2006.211.07:48:41.83#ibcon#about to read 4, iclass 21, count 0 2006.211.07:48:41.83#ibcon#read 4, iclass 21, count 0 2006.211.07:48:41.83#ibcon#about to read 5, iclass 21, count 0 2006.211.07:48:41.83#ibcon#read 5, iclass 21, count 0 2006.211.07:48:41.83#ibcon#about to read 6, iclass 21, count 0 2006.211.07:48:41.83#ibcon#read 6, iclass 21, count 0 2006.211.07:48:41.83#ibcon#end of sib2, iclass 21, count 0 2006.211.07:48:41.83#ibcon#*after write, iclass 21, count 0 2006.211.07:48:41.83#ibcon#*before return 0, iclass 21, count 0 2006.211.07:48:41.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:41.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:48:41.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:48:41.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:48:41.83$vc4f8/vblo=6,752.99 2006.211.07:48:41.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:48:41.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:48:41.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:48:41.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:41.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:41.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:41.83#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:48:41.83#ibcon#first serial, iclass 23, count 0 2006.211.07:48:41.83#ibcon#enter sib2, iclass 23, count 0 2006.211.07:48:41.83#ibcon#flushed, iclass 23, count 0 2006.211.07:48:41.83#ibcon#about to write, iclass 23, count 0 2006.211.07:48:41.83#ibcon#wrote, iclass 23, count 0 2006.211.07:48:41.83#ibcon#about to read 3, iclass 23, count 0 2006.211.07:48:41.85#ibcon#read 3, iclass 23, count 0 2006.211.07:48:41.85#ibcon#about to read 4, iclass 23, count 0 2006.211.07:48:41.85#ibcon#read 4, iclass 23, count 0 2006.211.07:48:41.85#ibcon#about to read 5, iclass 23, count 0 2006.211.07:48:41.85#ibcon#read 5, iclass 23, count 0 2006.211.07:48:41.85#ibcon#about to read 6, iclass 23, count 0 2006.211.07:48:41.85#ibcon#read 6, iclass 23, count 0 2006.211.07:48:41.85#ibcon#end of sib2, iclass 23, count 0 2006.211.07:48:41.85#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:48:41.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:48:41.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:48:41.85#ibcon#*before write, iclass 23, count 0 2006.211.07:48:41.85#ibcon#enter sib2, iclass 23, count 0 2006.211.07:48:41.85#ibcon#flushed, iclass 23, count 0 2006.211.07:48:41.85#ibcon#about to write, iclass 23, count 0 2006.211.07:48:41.85#ibcon#wrote, iclass 23, count 0 2006.211.07:48:41.85#ibcon#about to read 3, iclass 23, count 0 2006.211.07:48:41.89#ibcon#read 3, iclass 23, count 0 2006.211.07:48:41.89#ibcon#about to read 4, iclass 23, count 0 2006.211.07:48:41.89#ibcon#read 4, iclass 23, count 0 2006.211.07:48:41.89#ibcon#about to read 5, iclass 23, count 0 2006.211.07:48:41.89#ibcon#read 5, iclass 23, count 0 2006.211.07:48:41.89#ibcon#about to read 6, iclass 23, count 0 2006.211.07:48:41.89#ibcon#read 6, iclass 23, count 0 2006.211.07:48:41.89#ibcon#end of sib2, iclass 23, count 0 2006.211.07:48:41.89#ibcon#*after write, iclass 23, count 0 2006.211.07:48:41.89#ibcon#*before return 0, iclass 23, count 0 2006.211.07:48:41.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:41.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:48:41.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:48:41.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:48:41.89$vc4f8/vb=6,3 2006.211.07:48:41.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.07:48:41.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.07:48:41.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:48:41.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:41.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:41.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:41.95#ibcon#enter wrdev, iclass 25, count 2 2006.211.07:48:41.95#ibcon#first serial, iclass 25, count 2 2006.211.07:48:41.95#ibcon#enter sib2, iclass 25, count 2 2006.211.07:48:41.95#ibcon#flushed, iclass 25, count 2 2006.211.07:48:41.95#ibcon#about to write, iclass 25, count 2 2006.211.07:48:41.95#ibcon#wrote, iclass 25, count 2 2006.211.07:48:41.95#ibcon#about to read 3, iclass 25, count 2 2006.211.07:48:41.97#ibcon#read 3, iclass 25, count 2 2006.211.07:48:41.97#ibcon#about to read 4, iclass 25, count 2 2006.211.07:48:41.97#ibcon#read 4, iclass 25, count 2 2006.211.07:48:41.97#ibcon#about to read 5, iclass 25, count 2 2006.211.07:48:41.97#ibcon#read 5, iclass 25, count 2 2006.211.07:48:41.97#ibcon#about to read 6, iclass 25, count 2 2006.211.07:48:41.97#ibcon#read 6, iclass 25, count 2 2006.211.07:48:41.97#ibcon#end of sib2, iclass 25, count 2 2006.211.07:48:41.97#ibcon#*mode == 0, iclass 25, count 2 2006.211.07:48:41.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.07:48:41.97#ibcon#[27=AT06-03\r\n] 2006.211.07:48:41.97#ibcon#*before write, iclass 25, count 2 2006.211.07:48:41.97#ibcon#enter sib2, iclass 25, count 2 2006.211.07:48:41.97#ibcon#flushed, iclass 25, count 2 2006.211.07:48:41.97#ibcon#about to write, iclass 25, count 2 2006.211.07:48:41.97#ibcon#wrote, iclass 25, count 2 2006.211.07:48:41.97#ibcon#about to read 3, iclass 25, count 2 2006.211.07:48:42.00#ibcon#read 3, iclass 25, count 2 2006.211.07:48:42.00#ibcon#about to read 4, iclass 25, count 2 2006.211.07:48:42.00#ibcon#read 4, iclass 25, count 2 2006.211.07:48:42.00#ibcon#about to read 5, iclass 25, count 2 2006.211.07:48:42.00#ibcon#read 5, iclass 25, count 2 2006.211.07:48:42.00#ibcon#about to read 6, iclass 25, count 2 2006.211.07:48:42.00#ibcon#read 6, iclass 25, count 2 2006.211.07:48:42.00#ibcon#end of sib2, iclass 25, count 2 2006.211.07:48:42.00#ibcon#*after write, iclass 25, count 2 2006.211.07:48:42.00#ibcon#*before return 0, iclass 25, count 2 2006.211.07:48:42.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:42.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:48:42.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.07:48:42.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:48:42.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:42.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:42.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:42.12#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:48:42.12#ibcon#first serial, iclass 25, count 0 2006.211.07:48:42.12#ibcon#enter sib2, iclass 25, count 0 2006.211.07:48:42.12#ibcon#flushed, iclass 25, count 0 2006.211.07:48:42.12#ibcon#about to write, iclass 25, count 0 2006.211.07:48:42.12#ibcon#wrote, iclass 25, count 0 2006.211.07:48:42.12#ibcon#about to read 3, iclass 25, count 0 2006.211.07:48:42.14#ibcon#read 3, iclass 25, count 0 2006.211.07:48:42.14#ibcon#about to read 4, iclass 25, count 0 2006.211.07:48:42.14#ibcon#read 4, iclass 25, count 0 2006.211.07:48:42.14#ibcon#about to read 5, iclass 25, count 0 2006.211.07:48:42.14#ibcon#read 5, iclass 25, count 0 2006.211.07:48:42.14#ibcon#about to read 6, iclass 25, count 0 2006.211.07:48:42.14#ibcon#read 6, iclass 25, count 0 2006.211.07:48:42.14#ibcon#end of sib2, iclass 25, count 0 2006.211.07:48:42.14#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:48:42.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:48:42.14#ibcon#[27=USB\r\n] 2006.211.07:48:42.14#ibcon#*before write, iclass 25, count 0 2006.211.07:48:42.14#ibcon#enter sib2, iclass 25, count 0 2006.211.07:48:42.14#ibcon#flushed, iclass 25, count 0 2006.211.07:48:42.14#ibcon#about to write, iclass 25, count 0 2006.211.07:48:42.14#ibcon#wrote, iclass 25, count 0 2006.211.07:48:42.14#ibcon#about to read 3, iclass 25, count 0 2006.211.07:48:42.17#ibcon#read 3, iclass 25, count 0 2006.211.07:48:42.17#ibcon#about to read 4, iclass 25, count 0 2006.211.07:48:42.17#ibcon#read 4, iclass 25, count 0 2006.211.07:48:42.17#ibcon#about to read 5, iclass 25, count 0 2006.211.07:48:42.17#ibcon#read 5, iclass 25, count 0 2006.211.07:48:42.17#ibcon#about to read 6, iclass 25, count 0 2006.211.07:48:42.17#ibcon#read 6, iclass 25, count 0 2006.211.07:48:42.17#ibcon#end of sib2, iclass 25, count 0 2006.211.07:48:42.17#ibcon#*after write, iclass 25, count 0 2006.211.07:48:42.17#ibcon#*before return 0, iclass 25, count 0 2006.211.07:48:42.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:42.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:48:42.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:48:42.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:48:42.17$vc4f8/vabw=wide 2006.211.07:48:42.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.07:48:42.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.07:48:42.17#ibcon#ireg 8 cls_cnt 0 2006.211.07:48:42.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:42.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:42.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:42.17#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:48:42.17#ibcon#first serial, iclass 27, count 0 2006.211.07:48:42.17#ibcon#enter sib2, iclass 27, count 0 2006.211.07:48:42.17#ibcon#flushed, iclass 27, count 0 2006.211.07:48:42.17#ibcon#about to write, iclass 27, count 0 2006.211.07:48:42.17#ibcon#wrote, iclass 27, count 0 2006.211.07:48:42.17#ibcon#about to read 3, iclass 27, count 0 2006.211.07:48:42.19#ibcon#read 3, iclass 27, count 0 2006.211.07:48:42.19#ibcon#about to read 4, iclass 27, count 0 2006.211.07:48:42.19#ibcon#read 4, iclass 27, count 0 2006.211.07:48:42.19#ibcon#about to read 5, iclass 27, count 0 2006.211.07:48:42.19#ibcon#read 5, iclass 27, count 0 2006.211.07:48:42.19#ibcon#about to read 6, iclass 27, count 0 2006.211.07:48:42.19#ibcon#read 6, iclass 27, count 0 2006.211.07:48:42.19#ibcon#end of sib2, iclass 27, count 0 2006.211.07:48:42.19#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:48:42.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:48:42.19#ibcon#[25=BW32\r\n] 2006.211.07:48:42.19#ibcon#*before write, iclass 27, count 0 2006.211.07:48:42.19#ibcon#enter sib2, iclass 27, count 0 2006.211.07:48:42.19#ibcon#flushed, iclass 27, count 0 2006.211.07:48:42.19#ibcon#about to write, iclass 27, count 0 2006.211.07:48:42.19#ibcon#wrote, iclass 27, count 0 2006.211.07:48:42.19#ibcon#about to read 3, iclass 27, count 0 2006.211.07:48:42.22#ibcon#read 3, iclass 27, count 0 2006.211.07:48:42.22#ibcon#about to read 4, iclass 27, count 0 2006.211.07:48:42.22#ibcon#read 4, iclass 27, count 0 2006.211.07:48:42.22#ibcon#about to read 5, iclass 27, count 0 2006.211.07:48:42.22#ibcon#read 5, iclass 27, count 0 2006.211.07:48:42.22#ibcon#about to read 6, iclass 27, count 0 2006.211.07:48:42.22#ibcon#read 6, iclass 27, count 0 2006.211.07:48:42.22#ibcon#end of sib2, iclass 27, count 0 2006.211.07:48:42.22#ibcon#*after write, iclass 27, count 0 2006.211.07:48:42.22#ibcon#*before return 0, iclass 27, count 0 2006.211.07:48:42.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:42.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:48:42.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:48:42.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:48:42.22$vc4f8/vbbw=wide 2006.211.07:48:42.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:48:42.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:48:42.22#ibcon#ireg 8 cls_cnt 0 2006.211.07:48:42.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:48:42.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:48:42.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:48:42.29#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:48:42.29#ibcon#first serial, iclass 29, count 0 2006.211.07:48:42.29#ibcon#enter sib2, iclass 29, count 0 2006.211.07:48:42.29#ibcon#flushed, iclass 29, count 0 2006.211.07:48:42.29#ibcon#about to write, iclass 29, count 0 2006.211.07:48:42.29#ibcon#wrote, iclass 29, count 0 2006.211.07:48:42.29#ibcon#about to read 3, iclass 29, count 0 2006.211.07:48:42.31#ibcon#read 3, iclass 29, count 0 2006.211.07:48:42.31#ibcon#about to read 4, iclass 29, count 0 2006.211.07:48:42.31#ibcon#read 4, iclass 29, count 0 2006.211.07:48:42.31#ibcon#about to read 5, iclass 29, count 0 2006.211.07:48:42.31#ibcon#read 5, iclass 29, count 0 2006.211.07:48:42.31#ibcon#about to read 6, iclass 29, count 0 2006.211.07:48:42.31#ibcon#read 6, iclass 29, count 0 2006.211.07:48:42.31#ibcon#end of sib2, iclass 29, count 0 2006.211.07:48:42.31#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:48:42.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:48:42.31#ibcon#[27=BW32\r\n] 2006.211.07:48:42.31#ibcon#*before write, iclass 29, count 0 2006.211.07:48:42.31#ibcon#enter sib2, iclass 29, count 0 2006.211.07:48:42.31#ibcon#flushed, iclass 29, count 0 2006.211.07:48:42.31#ibcon#about to write, iclass 29, count 0 2006.211.07:48:42.31#ibcon#wrote, iclass 29, count 0 2006.211.07:48:42.31#ibcon#about to read 3, iclass 29, count 0 2006.211.07:48:42.34#ibcon#read 3, iclass 29, count 0 2006.211.07:48:42.34#ibcon#about to read 4, iclass 29, count 0 2006.211.07:48:42.34#ibcon#read 4, iclass 29, count 0 2006.211.07:48:42.34#ibcon#about to read 5, iclass 29, count 0 2006.211.07:48:42.34#ibcon#read 5, iclass 29, count 0 2006.211.07:48:42.34#ibcon#about to read 6, iclass 29, count 0 2006.211.07:48:42.34#ibcon#read 6, iclass 29, count 0 2006.211.07:48:42.34#ibcon#end of sib2, iclass 29, count 0 2006.211.07:48:42.34#ibcon#*after write, iclass 29, count 0 2006.211.07:48:42.34#ibcon#*before return 0, iclass 29, count 0 2006.211.07:48:42.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:48:42.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:48:42.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:48:42.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:48:42.34$4f8m12a/ifd4f 2006.211.07:48:42.34$ifd4f/lo= 2006.211.07:48:42.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:48:42.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:48:42.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:48:42.34$ifd4f/patch= 2006.211.07:48:42.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:48:42.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:48:42.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:48:42.34$4f8m12a/"form=m,16.000,1:2 2006.211.07:48:42.34$4f8m12a/"tpicd 2006.211.07:48:42.34$4f8m12a/echo=off 2006.211.07:48:42.34$4f8m12a/xlog=off 2006.211.07:48:42.34:!2006.211.07:49:20 2006.211.07:48:58.14#trakl#Source acquired 2006.211.07:49:00.14#flagr#flagr/antenna,acquired 2006.211.07:49:20.00:preob 2006.211.07:49:20.14/onsource/TRACKING 2006.211.07:49:20.14:!2006.211.07:49:30 2006.211.07:49:30.00:data_valid=on 2006.211.07:49:30.00:midob 2006.211.07:49:30.14/onsource/TRACKING 2006.211.07:49:30.14/wx/24.96,1010.1,77 2006.211.07:49:30.27/cable/+6.4395E-03 2006.211.07:49:31.36/va/01,08,usb,yes,29,31 2006.211.07:49:31.36/va/02,07,usb,yes,29,31 2006.211.07:49:31.36/va/03,06,usb,yes,31,31 2006.211.07:49:31.36/va/04,07,usb,yes,30,32 2006.211.07:49:31.36/va/05,07,usb,yes,33,35 2006.211.07:49:31.36/va/06,06,usb,yes,32,32 2006.211.07:49:31.36/va/07,06,usb,yes,32,32 2006.211.07:49:31.36/va/08,07,usb,yes,31,30 2006.211.07:49:31.59/valo/01,532.99,yes,locked 2006.211.07:49:31.59/valo/02,572.99,yes,locked 2006.211.07:49:31.59/valo/03,672.99,yes,locked 2006.211.07:49:31.59/valo/04,832.99,yes,locked 2006.211.07:49:31.59/valo/05,652.99,yes,locked 2006.211.07:49:31.59/valo/06,772.99,yes,locked 2006.211.07:49:31.59/valo/07,832.99,yes,locked 2006.211.07:49:31.59/valo/08,852.99,yes,locked 2006.211.07:49:32.68/vb/01,04,usb,yes,29,27 2006.211.07:49:32.68/vb/02,04,usb,yes,30,32 2006.211.07:49:32.68/vb/03,03,usb,yes,34,38 2006.211.07:49:32.68/vb/04,03,usb,yes,35,35 2006.211.07:49:32.68/vb/05,03,usb,yes,33,37 2006.211.07:49:32.68/vb/06,03,usb,yes,34,37 2006.211.07:49:32.68/vb/07,04,usb,yes,29,29 2006.211.07:49:32.68/vb/08,03,usb,yes,34,37 2006.211.07:49:32.91/vblo/01,632.99,yes,locked 2006.211.07:49:32.91/vblo/02,640.99,yes,locked 2006.211.07:49:32.91/vblo/03,656.99,yes,locked 2006.211.07:49:32.91/vblo/04,712.99,yes,locked 2006.211.07:49:32.91/vblo/05,744.99,yes,locked 2006.211.07:49:32.91/vblo/06,752.99,yes,locked 2006.211.07:49:32.91/vblo/07,734.99,yes,locked 2006.211.07:49:32.91/vblo/08,744.99,yes,locked 2006.211.07:49:33.06/vabw/8 2006.211.07:49:33.21/vbbw/8 2006.211.07:49:33.32/xfe/off,on,15.2 2006.211.07:49:33.69/ifatt/23,28,28,28 2006.211.07:49:34.08/fmout-gps/S +4.46E-07 2006.211.07:49:34.12:!2006.211.07:50:30 2006.211.07:50:30.00:data_valid=off 2006.211.07:50:30.00:postob 2006.211.07:50:30.14/cable/+6.4398E-03 2006.211.07:50:30.14/wx/24.95,1010.1,76 2006.211.07:50:31.07/fmout-gps/S +4.45E-07 2006.211.07:50:31.07:scan_name=211-0751,k06211,60 2006.211.07:50:31.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.211.07:50:31.14#flagr#flagr/antenna,new-source 2006.211.07:50:32.14:checkk5 2006.211.07:50:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:50:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:50:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:50:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:50:33.83/chk_obsdata//k5ts1/T2110749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:50:34.16/chk_obsdata//k5ts2/T2110749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:50:34.51/chk_obsdata//k5ts3/T2110749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:50:34.84/chk_obsdata//k5ts4/T2110749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:50:35.50/k5log//k5ts1_log_newline 2006.211.07:50:36.15/k5log//k5ts2_log_newline 2006.211.07:50:36.81/k5log//k5ts3_log_newline 2006.211.07:50:37.47/k5log//k5ts4_log_newline 2006.211.07:50:37.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:50:37.49:4f8m12a=1 2006.211.07:50:37.49$4f8m12a/echo=on 2006.211.07:50:37.49$4f8m12a/pcalon 2006.211.07:50:37.49$pcalon/"no phase cal control is implemented here 2006.211.07:50:37.49$4f8m12a/"tpicd=stop 2006.211.07:50:37.49$4f8m12a/vc4f8 2006.211.07:50:37.49$vc4f8/valo=1,532.99 2006.211.07:50:37.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:50:37.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:50:37.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:37.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:50:37.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:50:37.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:50:37.49#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:50:37.49#ibcon#first serial, iclass 37, count 0 2006.211.07:50:37.49#ibcon#enter sib2, iclass 37, count 0 2006.211.07:50:37.49#ibcon#flushed, iclass 37, count 0 2006.211.07:50:37.49#ibcon#about to write, iclass 37, count 0 2006.211.07:50:37.49#ibcon#wrote, iclass 37, count 0 2006.211.07:50:37.49#ibcon#about to read 3, iclass 37, count 0 2006.211.07:50:37.51#ibcon#read 3, iclass 37, count 0 2006.211.07:50:37.51#ibcon#about to read 4, iclass 37, count 0 2006.211.07:50:37.51#ibcon#read 4, iclass 37, count 0 2006.211.07:50:37.51#ibcon#about to read 5, iclass 37, count 0 2006.211.07:50:37.51#ibcon#read 5, iclass 37, count 0 2006.211.07:50:37.51#ibcon#about to read 6, iclass 37, count 0 2006.211.07:50:37.51#ibcon#read 6, iclass 37, count 0 2006.211.07:50:37.51#ibcon#end of sib2, iclass 37, count 0 2006.211.07:50:37.51#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:50:37.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:50:37.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:50:37.51#ibcon#*before write, iclass 37, count 0 2006.211.07:50:37.51#ibcon#enter sib2, iclass 37, count 0 2006.211.07:50:37.51#ibcon#flushed, iclass 37, count 0 2006.211.07:50:37.51#ibcon#about to write, iclass 37, count 0 2006.211.07:50:37.51#ibcon#wrote, iclass 37, count 0 2006.211.07:50:37.51#ibcon#about to read 3, iclass 37, count 0 2006.211.07:50:37.56#ibcon#read 3, iclass 37, count 0 2006.211.07:50:37.56#ibcon#about to read 4, iclass 37, count 0 2006.211.07:50:37.56#ibcon#read 4, iclass 37, count 0 2006.211.07:50:37.56#ibcon#about to read 5, iclass 37, count 0 2006.211.07:50:37.56#ibcon#read 5, iclass 37, count 0 2006.211.07:50:37.56#ibcon#about to read 6, iclass 37, count 0 2006.211.07:50:37.56#ibcon#read 6, iclass 37, count 0 2006.211.07:50:37.56#ibcon#end of sib2, iclass 37, count 0 2006.211.07:50:37.56#ibcon#*after write, iclass 37, count 0 2006.211.07:50:37.56#ibcon#*before return 0, iclass 37, count 0 2006.211.07:50:37.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:50:37.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:50:37.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:50:37.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:50:37.56$vc4f8/va=1,8 2006.211.07:50:37.56#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:50:37.56#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:50:37.56#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:37.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:50:37.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:50:37.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:50:37.56#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:50:37.56#ibcon#first serial, iclass 39, count 2 2006.211.07:50:37.56#ibcon#enter sib2, iclass 39, count 2 2006.211.07:50:37.56#ibcon#flushed, iclass 39, count 2 2006.211.07:50:37.56#ibcon#about to write, iclass 39, count 2 2006.211.07:50:37.56#ibcon#wrote, iclass 39, count 2 2006.211.07:50:37.56#ibcon#about to read 3, iclass 39, count 2 2006.211.07:50:37.58#ibcon#read 3, iclass 39, count 2 2006.211.07:50:37.58#ibcon#about to read 4, iclass 39, count 2 2006.211.07:50:37.58#ibcon#read 4, iclass 39, count 2 2006.211.07:50:37.58#ibcon#about to read 5, iclass 39, count 2 2006.211.07:50:37.58#ibcon#read 5, iclass 39, count 2 2006.211.07:50:37.58#ibcon#about to read 6, iclass 39, count 2 2006.211.07:50:37.58#ibcon#read 6, iclass 39, count 2 2006.211.07:50:37.58#ibcon#end of sib2, iclass 39, count 2 2006.211.07:50:37.58#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:50:37.58#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:50:37.58#ibcon#[25=AT01-08\r\n] 2006.211.07:50:37.58#ibcon#*before write, iclass 39, count 2 2006.211.07:50:37.58#ibcon#enter sib2, iclass 39, count 2 2006.211.07:50:37.58#ibcon#flushed, iclass 39, count 2 2006.211.07:50:37.58#ibcon#about to write, iclass 39, count 2 2006.211.07:50:37.58#ibcon#wrote, iclass 39, count 2 2006.211.07:50:37.58#ibcon#about to read 3, iclass 39, count 2 2006.211.07:50:37.61#ibcon#read 3, iclass 39, count 2 2006.211.07:50:37.61#ibcon#about to read 4, iclass 39, count 2 2006.211.07:50:37.61#ibcon#read 4, iclass 39, count 2 2006.211.07:50:37.61#ibcon#about to read 5, iclass 39, count 2 2006.211.07:50:37.61#ibcon#read 5, iclass 39, count 2 2006.211.07:50:37.61#ibcon#about to read 6, iclass 39, count 2 2006.211.07:50:37.61#ibcon#read 6, iclass 39, count 2 2006.211.07:50:37.61#ibcon#end of sib2, iclass 39, count 2 2006.211.07:50:37.61#ibcon#*after write, iclass 39, count 2 2006.211.07:50:37.61#ibcon#*before return 0, iclass 39, count 2 2006.211.07:50:37.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:50:37.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:50:37.61#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:50:37.61#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:37.61#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:50:37.73#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:50:37.73#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:50:37.73#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:50:37.73#ibcon#first serial, iclass 39, count 0 2006.211.07:50:37.73#ibcon#enter sib2, iclass 39, count 0 2006.211.07:50:37.73#ibcon#flushed, iclass 39, count 0 2006.211.07:50:37.73#ibcon#about to write, iclass 39, count 0 2006.211.07:50:37.73#ibcon#wrote, iclass 39, count 0 2006.211.07:50:37.73#ibcon#about to read 3, iclass 39, count 0 2006.211.07:50:37.75#ibcon#read 3, iclass 39, count 0 2006.211.07:50:37.75#ibcon#about to read 4, iclass 39, count 0 2006.211.07:50:37.75#ibcon#read 4, iclass 39, count 0 2006.211.07:50:37.75#ibcon#about to read 5, iclass 39, count 0 2006.211.07:50:37.75#ibcon#read 5, iclass 39, count 0 2006.211.07:50:37.75#ibcon#about to read 6, iclass 39, count 0 2006.211.07:50:37.75#ibcon#read 6, iclass 39, count 0 2006.211.07:50:37.75#ibcon#end of sib2, iclass 39, count 0 2006.211.07:50:37.75#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:50:37.75#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:50:37.75#ibcon#[25=USB\r\n] 2006.211.07:50:37.75#ibcon#*before write, iclass 39, count 0 2006.211.07:50:37.75#ibcon#enter sib2, iclass 39, count 0 2006.211.07:50:37.75#ibcon#flushed, iclass 39, count 0 2006.211.07:50:37.75#ibcon#about to write, iclass 39, count 0 2006.211.07:50:37.75#ibcon#wrote, iclass 39, count 0 2006.211.07:50:37.75#ibcon#about to read 3, iclass 39, count 0 2006.211.07:50:37.78#ibcon#read 3, iclass 39, count 0 2006.211.07:50:37.78#ibcon#about to read 4, iclass 39, count 0 2006.211.07:50:37.78#ibcon#read 4, iclass 39, count 0 2006.211.07:50:37.78#ibcon#about to read 5, iclass 39, count 0 2006.211.07:50:37.78#ibcon#read 5, iclass 39, count 0 2006.211.07:50:37.78#ibcon#about to read 6, iclass 39, count 0 2006.211.07:50:37.78#ibcon#read 6, iclass 39, count 0 2006.211.07:50:37.78#ibcon#end of sib2, iclass 39, count 0 2006.211.07:50:37.78#ibcon#*after write, iclass 39, count 0 2006.211.07:50:37.78#ibcon#*before return 0, iclass 39, count 0 2006.211.07:50:37.78#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:50:37.78#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:50:37.78#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:50:37.78#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:50:37.78$vc4f8/valo=2,572.99 2006.211.07:50:37.78#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:50:37.78#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:50:37.78#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:37.78#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:50:37.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:50:37.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:50:37.78#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:50:37.78#ibcon#first serial, iclass 3, count 0 2006.211.07:50:37.78#ibcon#enter sib2, iclass 3, count 0 2006.211.07:50:37.78#ibcon#flushed, iclass 3, count 0 2006.211.07:50:37.78#ibcon#about to write, iclass 3, count 0 2006.211.07:50:37.78#ibcon#wrote, iclass 3, count 0 2006.211.07:50:37.78#ibcon#about to read 3, iclass 3, count 0 2006.211.07:50:37.80#ibcon#read 3, iclass 3, count 0 2006.211.07:50:37.80#ibcon#about to read 4, iclass 3, count 0 2006.211.07:50:37.80#ibcon#read 4, iclass 3, count 0 2006.211.07:50:37.80#ibcon#about to read 5, iclass 3, count 0 2006.211.07:50:37.80#ibcon#read 5, iclass 3, count 0 2006.211.07:50:37.80#ibcon#about to read 6, iclass 3, count 0 2006.211.07:50:37.80#ibcon#read 6, iclass 3, count 0 2006.211.07:50:37.80#ibcon#end of sib2, iclass 3, count 0 2006.211.07:50:37.80#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:50:37.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:50:37.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:50:37.80#ibcon#*before write, iclass 3, count 0 2006.211.07:50:37.80#ibcon#enter sib2, iclass 3, count 0 2006.211.07:50:37.80#ibcon#flushed, iclass 3, count 0 2006.211.07:50:37.80#ibcon#about to write, iclass 3, count 0 2006.211.07:50:37.80#ibcon#wrote, iclass 3, count 0 2006.211.07:50:37.80#ibcon#about to read 3, iclass 3, count 0 2006.211.07:50:37.84#ibcon#read 3, iclass 3, count 0 2006.211.07:50:37.84#ibcon#about to read 4, iclass 3, count 0 2006.211.07:50:37.84#ibcon#read 4, iclass 3, count 0 2006.211.07:50:37.84#ibcon#about to read 5, iclass 3, count 0 2006.211.07:50:37.84#ibcon#read 5, iclass 3, count 0 2006.211.07:50:37.84#ibcon#about to read 6, iclass 3, count 0 2006.211.07:50:37.84#ibcon#read 6, iclass 3, count 0 2006.211.07:50:37.84#ibcon#end of sib2, iclass 3, count 0 2006.211.07:50:37.84#ibcon#*after write, iclass 3, count 0 2006.211.07:50:37.84#ibcon#*before return 0, iclass 3, count 0 2006.211.07:50:37.84#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:50:37.84#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:50:37.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:50:37.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:50:37.84$vc4f8/va=2,7 2006.211.07:50:37.84#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:50:37.84#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:50:37.84#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:37.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:50:37.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:50:37.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:50:37.90#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:50:37.90#ibcon#first serial, iclass 5, count 2 2006.211.07:50:37.90#ibcon#enter sib2, iclass 5, count 2 2006.211.07:50:37.90#ibcon#flushed, iclass 5, count 2 2006.211.07:50:37.90#ibcon#about to write, iclass 5, count 2 2006.211.07:50:37.90#ibcon#wrote, iclass 5, count 2 2006.211.07:50:37.90#ibcon#about to read 3, iclass 5, count 2 2006.211.07:50:37.92#ibcon#read 3, iclass 5, count 2 2006.211.07:50:37.92#ibcon#about to read 4, iclass 5, count 2 2006.211.07:50:37.92#ibcon#read 4, iclass 5, count 2 2006.211.07:50:37.92#ibcon#about to read 5, iclass 5, count 2 2006.211.07:50:37.92#ibcon#read 5, iclass 5, count 2 2006.211.07:50:37.92#ibcon#about to read 6, iclass 5, count 2 2006.211.07:50:37.92#ibcon#read 6, iclass 5, count 2 2006.211.07:50:37.92#ibcon#end of sib2, iclass 5, count 2 2006.211.07:50:37.92#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:50:37.92#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:50:37.92#ibcon#[25=AT02-07\r\n] 2006.211.07:50:37.92#ibcon#*before write, iclass 5, count 2 2006.211.07:50:37.92#ibcon#enter sib2, iclass 5, count 2 2006.211.07:50:37.92#ibcon#flushed, iclass 5, count 2 2006.211.07:50:37.92#ibcon#about to write, iclass 5, count 2 2006.211.07:50:37.92#ibcon#wrote, iclass 5, count 2 2006.211.07:50:37.92#ibcon#about to read 3, iclass 5, count 2 2006.211.07:50:37.95#ibcon#read 3, iclass 5, count 2 2006.211.07:50:37.95#ibcon#about to read 4, iclass 5, count 2 2006.211.07:50:37.95#ibcon#read 4, iclass 5, count 2 2006.211.07:50:37.95#ibcon#about to read 5, iclass 5, count 2 2006.211.07:50:37.95#ibcon#read 5, iclass 5, count 2 2006.211.07:50:37.95#ibcon#about to read 6, iclass 5, count 2 2006.211.07:50:37.95#ibcon#read 6, iclass 5, count 2 2006.211.07:50:37.95#ibcon#end of sib2, iclass 5, count 2 2006.211.07:50:37.95#ibcon#*after write, iclass 5, count 2 2006.211.07:50:37.95#ibcon#*before return 0, iclass 5, count 2 2006.211.07:50:37.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:50:37.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:50:37.95#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:50:37.95#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:37.95#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:50:38.07#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:50:38.07#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:50:38.07#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:50:38.07#ibcon#first serial, iclass 5, count 0 2006.211.07:50:38.07#ibcon#enter sib2, iclass 5, count 0 2006.211.07:50:38.07#ibcon#flushed, iclass 5, count 0 2006.211.07:50:38.07#ibcon#about to write, iclass 5, count 0 2006.211.07:50:38.07#ibcon#wrote, iclass 5, count 0 2006.211.07:50:38.07#ibcon#about to read 3, iclass 5, count 0 2006.211.07:50:38.09#ibcon#read 3, iclass 5, count 0 2006.211.07:50:38.09#ibcon#about to read 4, iclass 5, count 0 2006.211.07:50:38.09#ibcon#read 4, iclass 5, count 0 2006.211.07:50:38.09#ibcon#about to read 5, iclass 5, count 0 2006.211.07:50:38.09#ibcon#read 5, iclass 5, count 0 2006.211.07:50:38.09#ibcon#about to read 6, iclass 5, count 0 2006.211.07:50:38.09#ibcon#read 6, iclass 5, count 0 2006.211.07:50:38.09#ibcon#end of sib2, iclass 5, count 0 2006.211.07:50:38.09#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:50:38.09#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:50:38.09#ibcon#[25=USB\r\n] 2006.211.07:50:38.09#ibcon#*before write, iclass 5, count 0 2006.211.07:50:38.09#ibcon#enter sib2, iclass 5, count 0 2006.211.07:50:38.09#ibcon#flushed, iclass 5, count 0 2006.211.07:50:38.09#ibcon#about to write, iclass 5, count 0 2006.211.07:50:38.09#ibcon#wrote, iclass 5, count 0 2006.211.07:50:38.09#ibcon#about to read 3, iclass 5, count 0 2006.211.07:50:38.12#ibcon#read 3, iclass 5, count 0 2006.211.07:50:38.12#ibcon#about to read 4, iclass 5, count 0 2006.211.07:50:38.12#ibcon#read 4, iclass 5, count 0 2006.211.07:50:38.12#ibcon#about to read 5, iclass 5, count 0 2006.211.07:50:38.12#ibcon#read 5, iclass 5, count 0 2006.211.07:50:38.12#ibcon#about to read 6, iclass 5, count 0 2006.211.07:50:38.12#ibcon#read 6, iclass 5, count 0 2006.211.07:50:38.12#ibcon#end of sib2, iclass 5, count 0 2006.211.07:50:38.12#ibcon#*after write, iclass 5, count 0 2006.211.07:50:38.12#ibcon#*before return 0, iclass 5, count 0 2006.211.07:50:38.12#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:50:38.12#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:50:38.12#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:50:38.12#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:50:38.12$vc4f8/valo=3,672.99 2006.211.07:50:38.12#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:50:38.12#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:50:38.12#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:38.12#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:50:38.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:50:38.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:50:38.12#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:50:38.12#ibcon#first serial, iclass 7, count 0 2006.211.07:50:38.12#ibcon#enter sib2, iclass 7, count 0 2006.211.07:50:38.12#ibcon#flushed, iclass 7, count 0 2006.211.07:50:38.12#ibcon#about to write, iclass 7, count 0 2006.211.07:50:38.12#ibcon#wrote, iclass 7, count 0 2006.211.07:50:38.12#ibcon#about to read 3, iclass 7, count 0 2006.211.07:50:38.14#ibcon#read 3, iclass 7, count 0 2006.211.07:50:38.14#ibcon#about to read 4, iclass 7, count 0 2006.211.07:50:38.14#ibcon#read 4, iclass 7, count 0 2006.211.07:50:38.14#ibcon#about to read 5, iclass 7, count 0 2006.211.07:50:38.14#ibcon#read 5, iclass 7, count 0 2006.211.07:50:38.14#ibcon#about to read 6, iclass 7, count 0 2006.211.07:50:38.14#ibcon#read 6, iclass 7, count 0 2006.211.07:50:38.14#ibcon#end of sib2, iclass 7, count 0 2006.211.07:50:38.14#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:50:38.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:50:38.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:50:38.14#ibcon#*before write, iclass 7, count 0 2006.211.07:50:38.14#ibcon#enter sib2, iclass 7, count 0 2006.211.07:50:38.14#ibcon#flushed, iclass 7, count 0 2006.211.07:50:38.14#ibcon#about to write, iclass 7, count 0 2006.211.07:50:38.14#ibcon#wrote, iclass 7, count 0 2006.211.07:50:38.14#ibcon#about to read 3, iclass 7, count 0 2006.211.07:50:38.18#ibcon#read 3, iclass 7, count 0 2006.211.07:50:38.18#ibcon#about to read 4, iclass 7, count 0 2006.211.07:50:38.18#ibcon#read 4, iclass 7, count 0 2006.211.07:50:38.18#ibcon#about to read 5, iclass 7, count 0 2006.211.07:50:38.18#ibcon#read 5, iclass 7, count 0 2006.211.07:50:38.18#ibcon#about to read 6, iclass 7, count 0 2006.211.07:50:38.18#ibcon#read 6, iclass 7, count 0 2006.211.07:50:38.18#ibcon#end of sib2, iclass 7, count 0 2006.211.07:50:38.18#ibcon#*after write, iclass 7, count 0 2006.211.07:50:38.18#ibcon#*before return 0, iclass 7, count 0 2006.211.07:50:38.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:50:38.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:50:38.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:50:38.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:50:38.18$vc4f8/va=3,6 2006.211.07:50:38.18#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:50:38.18#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:50:38.18#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:38.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:50:38.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:50:38.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:50:38.24#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:50:38.24#ibcon#first serial, iclass 11, count 2 2006.211.07:50:38.24#ibcon#enter sib2, iclass 11, count 2 2006.211.07:50:38.24#ibcon#flushed, iclass 11, count 2 2006.211.07:50:38.24#ibcon#about to write, iclass 11, count 2 2006.211.07:50:38.24#ibcon#wrote, iclass 11, count 2 2006.211.07:50:38.24#ibcon#about to read 3, iclass 11, count 2 2006.211.07:50:38.26#ibcon#read 3, iclass 11, count 2 2006.211.07:50:38.26#ibcon#about to read 4, iclass 11, count 2 2006.211.07:50:38.26#ibcon#read 4, iclass 11, count 2 2006.211.07:50:38.26#ibcon#about to read 5, iclass 11, count 2 2006.211.07:50:38.26#ibcon#read 5, iclass 11, count 2 2006.211.07:50:38.26#ibcon#about to read 6, iclass 11, count 2 2006.211.07:50:38.26#ibcon#read 6, iclass 11, count 2 2006.211.07:50:38.26#ibcon#end of sib2, iclass 11, count 2 2006.211.07:50:38.26#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:50:38.26#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:50:38.26#ibcon#[25=AT03-06\r\n] 2006.211.07:50:38.26#ibcon#*before write, iclass 11, count 2 2006.211.07:50:38.26#ibcon#enter sib2, iclass 11, count 2 2006.211.07:50:38.26#ibcon#flushed, iclass 11, count 2 2006.211.07:50:38.26#ibcon#about to write, iclass 11, count 2 2006.211.07:50:38.26#ibcon#wrote, iclass 11, count 2 2006.211.07:50:38.26#ibcon#about to read 3, iclass 11, count 2 2006.211.07:50:38.29#ibcon#read 3, iclass 11, count 2 2006.211.07:50:38.29#ibcon#about to read 4, iclass 11, count 2 2006.211.07:50:38.29#ibcon#read 4, iclass 11, count 2 2006.211.07:50:38.29#ibcon#about to read 5, iclass 11, count 2 2006.211.07:50:38.29#ibcon#read 5, iclass 11, count 2 2006.211.07:50:38.29#ibcon#about to read 6, iclass 11, count 2 2006.211.07:50:38.29#ibcon#read 6, iclass 11, count 2 2006.211.07:50:38.29#ibcon#end of sib2, iclass 11, count 2 2006.211.07:50:38.29#ibcon#*after write, iclass 11, count 2 2006.211.07:50:38.29#ibcon#*before return 0, iclass 11, count 2 2006.211.07:50:38.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:50:38.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:50:38.29#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:50:38.29#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:38.29#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:50:38.41#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:50:38.41#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:50:38.41#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:50:38.41#ibcon#first serial, iclass 11, count 0 2006.211.07:50:38.41#ibcon#enter sib2, iclass 11, count 0 2006.211.07:50:38.41#ibcon#flushed, iclass 11, count 0 2006.211.07:50:38.41#ibcon#about to write, iclass 11, count 0 2006.211.07:50:38.41#ibcon#wrote, iclass 11, count 0 2006.211.07:50:38.41#ibcon#about to read 3, iclass 11, count 0 2006.211.07:50:38.43#ibcon#read 3, iclass 11, count 0 2006.211.07:50:38.43#ibcon#about to read 4, iclass 11, count 0 2006.211.07:50:38.43#ibcon#read 4, iclass 11, count 0 2006.211.07:50:38.43#ibcon#about to read 5, iclass 11, count 0 2006.211.07:50:38.43#ibcon#read 5, iclass 11, count 0 2006.211.07:50:38.43#ibcon#about to read 6, iclass 11, count 0 2006.211.07:50:38.43#ibcon#read 6, iclass 11, count 0 2006.211.07:50:38.43#ibcon#end of sib2, iclass 11, count 0 2006.211.07:50:38.43#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:50:38.43#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:50:38.43#ibcon#[25=USB\r\n] 2006.211.07:50:38.43#ibcon#*before write, iclass 11, count 0 2006.211.07:50:38.43#ibcon#enter sib2, iclass 11, count 0 2006.211.07:50:38.43#ibcon#flushed, iclass 11, count 0 2006.211.07:50:38.43#ibcon#about to write, iclass 11, count 0 2006.211.07:50:38.43#ibcon#wrote, iclass 11, count 0 2006.211.07:50:38.43#ibcon#about to read 3, iclass 11, count 0 2006.211.07:50:38.46#ibcon#read 3, iclass 11, count 0 2006.211.07:50:38.46#ibcon#about to read 4, iclass 11, count 0 2006.211.07:50:38.46#ibcon#read 4, iclass 11, count 0 2006.211.07:50:38.46#ibcon#about to read 5, iclass 11, count 0 2006.211.07:50:38.46#ibcon#read 5, iclass 11, count 0 2006.211.07:50:38.46#ibcon#about to read 6, iclass 11, count 0 2006.211.07:50:38.46#ibcon#read 6, iclass 11, count 0 2006.211.07:50:38.46#ibcon#end of sib2, iclass 11, count 0 2006.211.07:50:38.46#ibcon#*after write, iclass 11, count 0 2006.211.07:50:38.46#ibcon#*before return 0, iclass 11, count 0 2006.211.07:50:38.46#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:50:38.46#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:50:38.46#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:50:38.46#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:50:38.46$vc4f8/valo=4,832.99 2006.211.07:50:38.46#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:50:38.46#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:50:38.46#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:38.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:50:38.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:50:38.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:50:38.46#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:50:38.46#ibcon#first serial, iclass 13, count 0 2006.211.07:50:38.46#ibcon#enter sib2, iclass 13, count 0 2006.211.07:50:38.46#ibcon#flushed, iclass 13, count 0 2006.211.07:50:38.46#ibcon#about to write, iclass 13, count 0 2006.211.07:50:38.46#ibcon#wrote, iclass 13, count 0 2006.211.07:50:38.46#ibcon#about to read 3, iclass 13, count 0 2006.211.07:50:38.48#ibcon#read 3, iclass 13, count 0 2006.211.07:50:38.48#ibcon#about to read 4, iclass 13, count 0 2006.211.07:50:38.48#ibcon#read 4, iclass 13, count 0 2006.211.07:50:38.48#ibcon#about to read 5, iclass 13, count 0 2006.211.07:50:38.48#ibcon#read 5, iclass 13, count 0 2006.211.07:50:38.48#ibcon#about to read 6, iclass 13, count 0 2006.211.07:50:38.48#ibcon#read 6, iclass 13, count 0 2006.211.07:50:38.48#ibcon#end of sib2, iclass 13, count 0 2006.211.07:50:38.48#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:50:38.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:50:38.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:50:38.48#ibcon#*before write, iclass 13, count 0 2006.211.07:50:38.48#ibcon#enter sib2, iclass 13, count 0 2006.211.07:50:38.48#ibcon#flushed, iclass 13, count 0 2006.211.07:50:38.48#ibcon#about to write, iclass 13, count 0 2006.211.07:50:38.48#ibcon#wrote, iclass 13, count 0 2006.211.07:50:38.48#ibcon#about to read 3, iclass 13, count 0 2006.211.07:50:38.52#ibcon#read 3, iclass 13, count 0 2006.211.07:50:38.52#ibcon#about to read 4, iclass 13, count 0 2006.211.07:50:38.52#ibcon#read 4, iclass 13, count 0 2006.211.07:50:38.52#ibcon#about to read 5, iclass 13, count 0 2006.211.07:50:38.52#ibcon#read 5, iclass 13, count 0 2006.211.07:50:38.52#ibcon#about to read 6, iclass 13, count 0 2006.211.07:50:38.52#ibcon#read 6, iclass 13, count 0 2006.211.07:50:38.52#ibcon#end of sib2, iclass 13, count 0 2006.211.07:50:38.52#ibcon#*after write, iclass 13, count 0 2006.211.07:50:38.52#ibcon#*before return 0, iclass 13, count 0 2006.211.07:50:38.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:50:38.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:50:38.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:50:38.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:50:38.52$vc4f8/va=4,7 2006.211.07:50:38.52#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.07:50:38.52#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.07:50:38.52#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:38.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:50:38.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:50:38.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:50:38.58#ibcon#enter wrdev, iclass 15, count 2 2006.211.07:50:38.58#ibcon#first serial, iclass 15, count 2 2006.211.07:50:38.58#ibcon#enter sib2, iclass 15, count 2 2006.211.07:50:38.58#ibcon#flushed, iclass 15, count 2 2006.211.07:50:38.58#ibcon#about to write, iclass 15, count 2 2006.211.07:50:38.58#ibcon#wrote, iclass 15, count 2 2006.211.07:50:38.58#ibcon#about to read 3, iclass 15, count 2 2006.211.07:50:38.60#ibcon#read 3, iclass 15, count 2 2006.211.07:50:38.60#ibcon#about to read 4, iclass 15, count 2 2006.211.07:50:38.60#ibcon#read 4, iclass 15, count 2 2006.211.07:50:38.60#ibcon#about to read 5, iclass 15, count 2 2006.211.07:50:38.60#ibcon#read 5, iclass 15, count 2 2006.211.07:50:38.60#ibcon#about to read 6, iclass 15, count 2 2006.211.07:50:38.60#ibcon#read 6, iclass 15, count 2 2006.211.07:50:38.60#ibcon#end of sib2, iclass 15, count 2 2006.211.07:50:38.60#ibcon#*mode == 0, iclass 15, count 2 2006.211.07:50:38.60#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.07:50:38.60#ibcon#[25=AT04-07\r\n] 2006.211.07:50:38.60#ibcon#*before write, iclass 15, count 2 2006.211.07:50:38.60#ibcon#enter sib2, iclass 15, count 2 2006.211.07:50:38.60#ibcon#flushed, iclass 15, count 2 2006.211.07:50:38.60#ibcon#about to write, iclass 15, count 2 2006.211.07:50:38.60#ibcon#wrote, iclass 15, count 2 2006.211.07:50:38.60#ibcon#about to read 3, iclass 15, count 2 2006.211.07:50:38.63#ibcon#read 3, iclass 15, count 2 2006.211.07:50:38.63#ibcon#about to read 4, iclass 15, count 2 2006.211.07:50:38.63#ibcon#read 4, iclass 15, count 2 2006.211.07:50:38.63#ibcon#about to read 5, iclass 15, count 2 2006.211.07:50:38.63#ibcon#read 5, iclass 15, count 2 2006.211.07:50:38.63#ibcon#about to read 6, iclass 15, count 2 2006.211.07:50:38.63#ibcon#read 6, iclass 15, count 2 2006.211.07:50:38.63#ibcon#end of sib2, iclass 15, count 2 2006.211.07:50:38.63#ibcon#*after write, iclass 15, count 2 2006.211.07:50:38.63#ibcon#*before return 0, iclass 15, count 2 2006.211.07:50:38.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:50:38.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:50:38.63#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.07:50:38.63#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:38.63#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:50:38.75#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:50:38.75#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:50:38.75#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:50:38.75#ibcon#first serial, iclass 15, count 0 2006.211.07:50:38.75#ibcon#enter sib2, iclass 15, count 0 2006.211.07:50:38.75#ibcon#flushed, iclass 15, count 0 2006.211.07:50:38.75#ibcon#about to write, iclass 15, count 0 2006.211.07:50:38.75#ibcon#wrote, iclass 15, count 0 2006.211.07:50:38.75#ibcon#about to read 3, iclass 15, count 0 2006.211.07:50:38.77#ibcon#read 3, iclass 15, count 0 2006.211.07:50:38.77#ibcon#about to read 4, iclass 15, count 0 2006.211.07:50:38.77#ibcon#read 4, iclass 15, count 0 2006.211.07:50:38.77#ibcon#about to read 5, iclass 15, count 0 2006.211.07:50:38.77#ibcon#read 5, iclass 15, count 0 2006.211.07:50:38.77#ibcon#about to read 6, iclass 15, count 0 2006.211.07:50:38.77#ibcon#read 6, iclass 15, count 0 2006.211.07:50:38.77#ibcon#end of sib2, iclass 15, count 0 2006.211.07:50:38.77#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:50:38.77#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:50:38.77#ibcon#[25=USB\r\n] 2006.211.07:50:38.77#ibcon#*before write, iclass 15, count 0 2006.211.07:50:38.77#ibcon#enter sib2, iclass 15, count 0 2006.211.07:50:38.77#ibcon#flushed, iclass 15, count 0 2006.211.07:50:38.77#ibcon#about to write, iclass 15, count 0 2006.211.07:50:38.77#ibcon#wrote, iclass 15, count 0 2006.211.07:50:38.77#ibcon#about to read 3, iclass 15, count 0 2006.211.07:50:38.80#ibcon#read 3, iclass 15, count 0 2006.211.07:50:38.80#ibcon#about to read 4, iclass 15, count 0 2006.211.07:50:38.80#ibcon#read 4, iclass 15, count 0 2006.211.07:50:38.80#ibcon#about to read 5, iclass 15, count 0 2006.211.07:50:38.80#ibcon#read 5, iclass 15, count 0 2006.211.07:50:38.80#ibcon#about to read 6, iclass 15, count 0 2006.211.07:50:38.80#ibcon#read 6, iclass 15, count 0 2006.211.07:50:38.80#ibcon#end of sib2, iclass 15, count 0 2006.211.07:50:38.80#ibcon#*after write, iclass 15, count 0 2006.211.07:50:38.80#ibcon#*before return 0, iclass 15, count 0 2006.211.07:50:38.80#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:50:38.80#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:50:38.80#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:50:38.80#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:50:38.80$vc4f8/valo=5,652.99 2006.211.07:50:38.80#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.07:50:38.80#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.07:50:38.80#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:38.80#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:50:38.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:50:38.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:50:38.80#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:50:38.80#ibcon#first serial, iclass 17, count 0 2006.211.07:50:38.80#ibcon#enter sib2, iclass 17, count 0 2006.211.07:50:38.80#ibcon#flushed, iclass 17, count 0 2006.211.07:50:38.80#ibcon#about to write, iclass 17, count 0 2006.211.07:50:38.80#ibcon#wrote, iclass 17, count 0 2006.211.07:50:38.80#ibcon#about to read 3, iclass 17, count 0 2006.211.07:50:38.82#ibcon#read 3, iclass 17, count 0 2006.211.07:50:38.82#ibcon#about to read 4, iclass 17, count 0 2006.211.07:50:38.82#ibcon#read 4, iclass 17, count 0 2006.211.07:50:38.82#ibcon#about to read 5, iclass 17, count 0 2006.211.07:50:38.82#ibcon#read 5, iclass 17, count 0 2006.211.07:50:38.82#ibcon#about to read 6, iclass 17, count 0 2006.211.07:50:38.82#ibcon#read 6, iclass 17, count 0 2006.211.07:50:38.82#ibcon#end of sib2, iclass 17, count 0 2006.211.07:50:38.82#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:50:38.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:50:38.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:50:38.82#ibcon#*before write, iclass 17, count 0 2006.211.07:50:38.82#ibcon#enter sib2, iclass 17, count 0 2006.211.07:50:38.82#ibcon#flushed, iclass 17, count 0 2006.211.07:50:38.82#ibcon#about to write, iclass 17, count 0 2006.211.07:50:38.82#ibcon#wrote, iclass 17, count 0 2006.211.07:50:38.82#ibcon#about to read 3, iclass 17, count 0 2006.211.07:50:38.86#ibcon#read 3, iclass 17, count 0 2006.211.07:50:38.86#ibcon#about to read 4, iclass 17, count 0 2006.211.07:50:38.86#ibcon#read 4, iclass 17, count 0 2006.211.07:50:38.86#ibcon#about to read 5, iclass 17, count 0 2006.211.07:50:38.86#ibcon#read 5, iclass 17, count 0 2006.211.07:50:38.86#ibcon#about to read 6, iclass 17, count 0 2006.211.07:50:38.86#ibcon#read 6, iclass 17, count 0 2006.211.07:50:38.86#ibcon#end of sib2, iclass 17, count 0 2006.211.07:50:38.86#ibcon#*after write, iclass 17, count 0 2006.211.07:50:38.86#ibcon#*before return 0, iclass 17, count 0 2006.211.07:50:38.86#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:50:38.86#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:50:38.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:50:38.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:50:38.86$vc4f8/va=5,7 2006.211.07:50:38.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:50:38.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:50:38.86#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:38.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:50:38.87#abcon#{5=INTERFACE CLEAR} 2006.211.07:50:38.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:50:38.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:50:38.92#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:50:38.92#ibcon#first serial, iclass 20, count 2 2006.211.07:50:38.92#ibcon#enter sib2, iclass 20, count 2 2006.211.07:50:38.92#ibcon#flushed, iclass 20, count 2 2006.211.07:50:38.92#ibcon#about to write, iclass 20, count 2 2006.211.07:50:38.92#ibcon#wrote, iclass 20, count 2 2006.211.07:50:38.92#ibcon#about to read 3, iclass 20, count 2 2006.211.07:50:38.93#abcon#[5=S1D000X0/0*\r\n] 2006.211.07:50:38.94#ibcon#read 3, iclass 20, count 2 2006.211.07:50:38.94#ibcon#about to read 4, iclass 20, count 2 2006.211.07:50:38.94#ibcon#read 4, iclass 20, count 2 2006.211.07:50:38.94#ibcon#about to read 5, iclass 20, count 2 2006.211.07:50:38.94#ibcon#read 5, iclass 20, count 2 2006.211.07:50:38.94#ibcon#about to read 6, iclass 20, count 2 2006.211.07:50:38.94#ibcon#read 6, iclass 20, count 2 2006.211.07:50:38.94#ibcon#end of sib2, iclass 20, count 2 2006.211.07:50:38.94#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:50:38.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:50:38.94#ibcon#[25=AT05-07\r\n] 2006.211.07:50:38.94#ibcon#*before write, iclass 20, count 2 2006.211.07:50:38.94#ibcon#enter sib2, iclass 20, count 2 2006.211.07:50:38.94#ibcon#flushed, iclass 20, count 2 2006.211.07:50:38.94#ibcon#about to write, iclass 20, count 2 2006.211.07:50:38.94#ibcon#wrote, iclass 20, count 2 2006.211.07:50:38.94#ibcon#about to read 3, iclass 20, count 2 2006.211.07:50:38.97#ibcon#read 3, iclass 20, count 2 2006.211.07:50:38.97#ibcon#about to read 4, iclass 20, count 2 2006.211.07:50:38.97#ibcon#read 4, iclass 20, count 2 2006.211.07:50:38.97#ibcon#about to read 5, iclass 20, count 2 2006.211.07:50:38.97#ibcon#read 5, iclass 20, count 2 2006.211.07:50:38.97#ibcon#about to read 6, iclass 20, count 2 2006.211.07:50:38.97#ibcon#read 6, iclass 20, count 2 2006.211.07:50:38.97#ibcon#end of sib2, iclass 20, count 2 2006.211.07:50:38.97#ibcon#*after write, iclass 20, count 2 2006.211.07:50:38.97#ibcon#*before return 0, iclass 20, count 2 2006.211.07:50:38.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:50:38.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:50:38.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:50:38.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:38.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:50:39.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:50:39.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:50:39.09#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:50:39.09#ibcon#first serial, iclass 20, count 0 2006.211.07:50:39.09#ibcon#enter sib2, iclass 20, count 0 2006.211.07:50:39.09#ibcon#flushed, iclass 20, count 0 2006.211.07:50:39.09#ibcon#about to write, iclass 20, count 0 2006.211.07:50:39.09#ibcon#wrote, iclass 20, count 0 2006.211.07:50:39.09#ibcon#about to read 3, iclass 20, count 0 2006.211.07:50:39.11#ibcon#read 3, iclass 20, count 0 2006.211.07:50:39.11#ibcon#about to read 4, iclass 20, count 0 2006.211.07:50:39.11#ibcon#read 4, iclass 20, count 0 2006.211.07:50:39.11#ibcon#about to read 5, iclass 20, count 0 2006.211.07:50:39.11#ibcon#read 5, iclass 20, count 0 2006.211.07:50:39.11#ibcon#about to read 6, iclass 20, count 0 2006.211.07:50:39.11#ibcon#read 6, iclass 20, count 0 2006.211.07:50:39.11#ibcon#end of sib2, iclass 20, count 0 2006.211.07:50:39.11#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:50:39.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:50:39.11#ibcon#[25=USB\r\n] 2006.211.07:50:39.11#ibcon#*before write, iclass 20, count 0 2006.211.07:50:39.11#ibcon#enter sib2, iclass 20, count 0 2006.211.07:50:39.11#ibcon#flushed, iclass 20, count 0 2006.211.07:50:39.11#ibcon#about to write, iclass 20, count 0 2006.211.07:50:39.11#ibcon#wrote, iclass 20, count 0 2006.211.07:50:39.11#ibcon#about to read 3, iclass 20, count 0 2006.211.07:50:39.14#ibcon#read 3, iclass 20, count 0 2006.211.07:50:39.14#ibcon#about to read 4, iclass 20, count 0 2006.211.07:50:39.14#ibcon#read 4, iclass 20, count 0 2006.211.07:50:39.14#ibcon#about to read 5, iclass 20, count 0 2006.211.07:50:39.14#ibcon#read 5, iclass 20, count 0 2006.211.07:50:39.14#ibcon#about to read 6, iclass 20, count 0 2006.211.07:50:39.14#ibcon#read 6, iclass 20, count 0 2006.211.07:50:39.14#ibcon#end of sib2, iclass 20, count 0 2006.211.07:50:39.14#ibcon#*after write, iclass 20, count 0 2006.211.07:50:39.14#ibcon#*before return 0, iclass 20, count 0 2006.211.07:50:39.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:50:39.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:50:39.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:50:39.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:50:39.14$vc4f8/valo=6,772.99 2006.211.07:50:39.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:50:39.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:50:39.14#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:39.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:39.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:39.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:39.14#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:50:39.14#ibcon#first serial, iclass 23, count 0 2006.211.07:50:39.14#ibcon#enter sib2, iclass 23, count 0 2006.211.07:50:39.14#ibcon#flushed, iclass 23, count 0 2006.211.07:50:39.14#ibcon#about to write, iclass 23, count 0 2006.211.07:50:39.14#ibcon#wrote, iclass 23, count 0 2006.211.07:50:39.14#ibcon#about to read 3, iclass 23, count 0 2006.211.07:50:39.16#ibcon#read 3, iclass 23, count 0 2006.211.07:50:39.16#ibcon#about to read 4, iclass 23, count 0 2006.211.07:50:39.16#ibcon#read 4, iclass 23, count 0 2006.211.07:50:39.16#ibcon#about to read 5, iclass 23, count 0 2006.211.07:50:39.16#ibcon#read 5, iclass 23, count 0 2006.211.07:50:39.16#ibcon#about to read 6, iclass 23, count 0 2006.211.07:50:39.16#ibcon#read 6, iclass 23, count 0 2006.211.07:50:39.16#ibcon#end of sib2, iclass 23, count 0 2006.211.07:50:39.16#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:50:39.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:50:39.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:50:39.16#ibcon#*before write, iclass 23, count 0 2006.211.07:50:39.16#ibcon#enter sib2, iclass 23, count 0 2006.211.07:50:39.16#ibcon#flushed, iclass 23, count 0 2006.211.07:50:39.16#ibcon#about to write, iclass 23, count 0 2006.211.07:50:39.16#ibcon#wrote, iclass 23, count 0 2006.211.07:50:39.16#ibcon#about to read 3, iclass 23, count 0 2006.211.07:50:39.20#ibcon#read 3, iclass 23, count 0 2006.211.07:50:39.20#ibcon#about to read 4, iclass 23, count 0 2006.211.07:50:39.20#ibcon#read 4, iclass 23, count 0 2006.211.07:50:39.20#ibcon#about to read 5, iclass 23, count 0 2006.211.07:50:39.20#ibcon#read 5, iclass 23, count 0 2006.211.07:50:39.20#ibcon#about to read 6, iclass 23, count 0 2006.211.07:50:39.20#ibcon#read 6, iclass 23, count 0 2006.211.07:50:39.20#ibcon#end of sib2, iclass 23, count 0 2006.211.07:50:39.20#ibcon#*after write, iclass 23, count 0 2006.211.07:50:39.20#ibcon#*before return 0, iclass 23, count 0 2006.211.07:50:39.20#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:39.20#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:39.20#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:50:39.20#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:50:39.20$vc4f8/va=6,6 2006.211.07:50:39.20#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.07:50:39.20#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.07:50:39.20#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:39.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:50:39.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:50:39.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:50:39.26#ibcon#enter wrdev, iclass 25, count 2 2006.211.07:50:39.26#ibcon#first serial, iclass 25, count 2 2006.211.07:50:39.26#ibcon#enter sib2, iclass 25, count 2 2006.211.07:50:39.26#ibcon#flushed, iclass 25, count 2 2006.211.07:50:39.26#ibcon#about to write, iclass 25, count 2 2006.211.07:50:39.26#ibcon#wrote, iclass 25, count 2 2006.211.07:50:39.26#ibcon#about to read 3, iclass 25, count 2 2006.211.07:50:39.28#ibcon#read 3, iclass 25, count 2 2006.211.07:50:39.28#ibcon#about to read 4, iclass 25, count 2 2006.211.07:50:39.28#ibcon#read 4, iclass 25, count 2 2006.211.07:50:39.28#ibcon#about to read 5, iclass 25, count 2 2006.211.07:50:39.28#ibcon#read 5, iclass 25, count 2 2006.211.07:50:39.28#ibcon#about to read 6, iclass 25, count 2 2006.211.07:50:39.28#ibcon#read 6, iclass 25, count 2 2006.211.07:50:39.28#ibcon#end of sib2, iclass 25, count 2 2006.211.07:50:39.28#ibcon#*mode == 0, iclass 25, count 2 2006.211.07:50:39.28#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.07:50:39.28#ibcon#[25=AT06-06\r\n] 2006.211.07:50:39.28#ibcon#*before write, iclass 25, count 2 2006.211.07:50:39.28#ibcon#enter sib2, iclass 25, count 2 2006.211.07:50:39.28#ibcon#flushed, iclass 25, count 2 2006.211.07:50:39.28#ibcon#about to write, iclass 25, count 2 2006.211.07:50:39.28#ibcon#wrote, iclass 25, count 2 2006.211.07:50:39.28#ibcon#about to read 3, iclass 25, count 2 2006.211.07:50:39.31#ibcon#read 3, iclass 25, count 2 2006.211.07:50:39.31#ibcon#about to read 4, iclass 25, count 2 2006.211.07:50:39.31#ibcon#read 4, iclass 25, count 2 2006.211.07:50:39.31#ibcon#about to read 5, iclass 25, count 2 2006.211.07:50:39.31#ibcon#read 5, iclass 25, count 2 2006.211.07:50:39.31#ibcon#about to read 6, iclass 25, count 2 2006.211.07:50:39.31#ibcon#read 6, iclass 25, count 2 2006.211.07:50:39.31#ibcon#end of sib2, iclass 25, count 2 2006.211.07:50:39.31#ibcon#*after write, iclass 25, count 2 2006.211.07:50:39.31#ibcon#*before return 0, iclass 25, count 2 2006.211.07:50:39.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:50:39.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:50:39.31#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.07:50:39.31#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:39.31#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:50:39.43#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:50:39.43#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:50:39.43#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:50:39.43#ibcon#first serial, iclass 25, count 0 2006.211.07:50:39.43#ibcon#enter sib2, iclass 25, count 0 2006.211.07:50:39.43#ibcon#flushed, iclass 25, count 0 2006.211.07:50:39.43#ibcon#about to write, iclass 25, count 0 2006.211.07:50:39.43#ibcon#wrote, iclass 25, count 0 2006.211.07:50:39.43#ibcon#about to read 3, iclass 25, count 0 2006.211.07:50:39.45#ibcon#read 3, iclass 25, count 0 2006.211.07:50:39.45#ibcon#about to read 4, iclass 25, count 0 2006.211.07:50:39.45#ibcon#read 4, iclass 25, count 0 2006.211.07:50:39.45#ibcon#about to read 5, iclass 25, count 0 2006.211.07:50:39.45#ibcon#read 5, iclass 25, count 0 2006.211.07:50:39.45#ibcon#about to read 6, iclass 25, count 0 2006.211.07:50:39.45#ibcon#read 6, iclass 25, count 0 2006.211.07:50:39.45#ibcon#end of sib2, iclass 25, count 0 2006.211.07:50:39.45#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:50:39.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:50:39.45#ibcon#[25=USB\r\n] 2006.211.07:50:39.45#ibcon#*before write, iclass 25, count 0 2006.211.07:50:39.45#ibcon#enter sib2, iclass 25, count 0 2006.211.07:50:39.45#ibcon#flushed, iclass 25, count 0 2006.211.07:50:39.45#ibcon#about to write, iclass 25, count 0 2006.211.07:50:39.45#ibcon#wrote, iclass 25, count 0 2006.211.07:50:39.45#ibcon#about to read 3, iclass 25, count 0 2006.211.07:50:39.48#ibcon#read 3, iclass 25, count 0 2006.211.07:50:39.48#ibcon#about to read 4, iclass 25, count 0 2006.211.07:50:39.48#ibcon#read 4, iclass 25, count 0 2006.211.07:50:39.48#ibcon#about to read 5, iclass 25, count 0 2006.211.07:50:39.48#ibcon#read 5, iclass 25, count 0 2006.211.07:50:39.48#ibcon#about to read 6, iclass 25, count 0 2006.211.07:50:39.48#ibcon#read 6, iclass 25, count 0 2006.211.07:50:39.48#ibcon#end of sib2, iclass 25, count 0 2006.211.07:50:39.48#ibcon#*after write, iclass 25, count 0 2006.211.07:50:39.48#ibcon#*before return 0, iclass 25, count 0 2006.211.07:50:39.48#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:50:39.48#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:50:39.48#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:50:39.48#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:50:39.48$vc4f8/valo=7,832.99 2006.211.07:50:39.48#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.07:50:39.48#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.07:50:39.48#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:39.48#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:50:39.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:50:39.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:50:39.48#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:50:39.48#ibcon#first serial, iclass 27, count 0 2006.211.07:50:39.48#ibcon#enter sib2, iclass 27, count 0 2006.211.07:50:39.48#ibcon#flushed, iclass 27, count 0 2006.211.07:50:39.48#ibcon#about to write, iclass 27, count 0 2006.211.07:50:39.48#ibcon#wrote, iclass 27, count 0 2006.211.07:50:39.48#ibcon#about to read 3, iclass 27, count 0 2006.211.07:50:39.50#ibcon#read 3, iclass 27, count 0 2006.211.07:50:39.50#ibcon#about to read 4, iclass 27, count 0 2006.211.07:50:39.50#ibcon#read 4, iclass 27, count 0 2006.211.07:50:39.50#ibcon#about to read 5, iclass 27, count 0 2006.211.07:50:39.50#ibcon#read 5, iclass 27, count 0 2006.211.07:50:39.50#ibcon#about to read 6, iclass 27, count 0 2006.211.07:50:39.50#ibcon#read 6, iclass 27, count 0 2006.211.07:50:39.50#ibcon#end of sib2, iclass 27, count 0 2006.211.07:50:39.50#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:50:39.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:50:39.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:50:39.50#ibcon#*before write, iclass 27, count 0 2006.211.07:50:39.50#ibcon#enter sib2, iclass 27, count 0 2006.211.07:50:39.50#ibcon#flushed, iclass 27, count 0 2006.211.07:50:39.50#ibcon#about to write, iclass 27, count 0 2006.211.07:50:39.50#ibcon#wrote, iclass 27, count 0 2006.211.07:50:39.50#ibcon#about to read 3, iclass 27, count 0 2006.211.07:50:39.54#ibcon#read 3, iclass 27, count 0 2006.211.07:50:39.54#ibcon#about to read 4, iclass 27, count 0 2006.211.07:50:39.54#ibcon#read 4, iclass 27, count 0 2006.211.07:50:39.54#ibcon#about to read 5, iclass 27, count 0 2006.211.07:50:39.54#ibcon#read 5, iclass 27, count 0 2006.211.07:50:39.54#ibcon#about to read 6, iclass 27, count 0 2006.211.07:50:39.54#ibcon#read 6, iclass 27, count 0 2006.211.07:50:39.54#ibcon#end of sib2, iclass 27, count 0 2006.211.07:50:39.54#ibcon#*after write, iclass 27, count 0 2006.211.07:50:39.54#ibcon#*before return 0, iclass 27, count 0 2006.211.07:50:39.54#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:50:39.54#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:50:39.54#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:50:39.54#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:50:39.54$vc4f8/va=7,6 2006.211.07:50:39.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.07:50:39.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.07:50:39.54#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:39.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:50:39.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:50:39.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:50:39.60#ibcon#enter wrdev, iclass 29, count 2 2006.211.07:50:39.60#ibcon#first serial, iclass 29, count 2 2006.211.07:50:39.60#ibcon#enter sib2, iclass 29, count 2 2006.211.07:50:39.60#ibcon#flushed, iclass 29, count 2 2006.211.07:50:39.60#ibcon#about to write, iclass 29, count 2 2006.211.07:50:39.60#ibcon#wrote, iclass 29, count 2 2006.211.07:50:39.60#ibcon#about to read 3, iclass 29, count 2 2006.211.07:50:39.62#ibcon#read 3, iclass 29, count 2 2006.211.07:50:39.62#ibcon#about to read 4, iclass 29, count 2 2006.211.07:50:39.62#ibcon#read 4, iclass 29, count 2 2006.211.07:50:39.62#ibcon#about to read 5, iclass 29, count 2 2006.211.07:50:39.62#ibcon#read 5, iclass 29, count 2 2006.211.07:50:39.62#ibcon#about to read 6, iclass 29, count 2 2006.211.07:50:39.62#ibcon#read 6, iclass 29, count 2 2006.211.07:50:39.62#ibcon#end of sib2, iclass 29, count 2 2006.211.07:50:39.62#ibcon#*mode == 0, iclass 29, count 2 2006.211.07:50:39.62#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.07:50:39.62#ibcon#[25=AT07-06\r\n] 2006.211.07:50:39.62#ibcon#*before write, iclass 29, count 2 2006.211.07:50:39.62#ibcon#enter sib2, iclass 29, count 2 2006.211.07:50:39.62#ibcon#flushed, iclass 29, count 2 2006.211.07:50:39.62#ibcon#about to write, iclass 29, count 2 2006.211.07:50:39.62#ibcon#wrote, iclass 29, count 2 2006.211.07:50:39.62#ibcon#about to read 3, iclass 29, count 2 2006.211.07:50:39.65#ibcon#read 3, iclass 29, count 2 2006.211.07:50:39.65#ibcon#about to read 4, iclass 29, count 2 2006.211.07:50:39.65#ibcon#read 4, iclass 29, count 2 2006.211.07:50:39.65#ibcon#about to read 5, iclass 29, count 2 2006.211.07:50:39.65#ibcon#read 5, iclass 29, count 2 2006.211.07:50:39.65#ibcon#about to read 6, iclass 29, count 2 2006.211.07:50:39.65#ibcon#read 6, iclass 29, count 2 2006.211.07:50:39.65#ibcon#end of sib2, iclass 29, count 2 2006.211.07:50:39.65#ibcon#*after write, iclass 29, count 2 2006.211.07:50:39.65#ibcon#*before return 0, iclass 29, count 2 2006.211.07:50:39.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:50:39.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.07:50:39.65#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.07:50:39.65#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:39.65#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:50:39.77#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:50:39.77#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:50:39.77#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:50:39.77#ibcon#first serial, iclass 29, count 0 2006.211.07:50:39.77#ibcon#enter sib2, iclass 29, count 0 2006.211.07:50:39.77#ibcon#flushed, iclass 29, count 0 2006.211.07:50:39.77#ibcon#about to write, iclass 29, count 0 2006.211.07:50:39.77#ibcon#wrote, iclass 29, count 0 2006.211.07:50:39.77#ibcon#about to read 3, iclass 29, count 0 2006.211.07:50:39.79#ibcon#read 3, iclass 29, count 0 2006.211.07:50:39.79#ibcon#about to read 4, iclass 29, count 0 2006.211.07:50:39.79#ibcon#read 4, iclass 29, count 0 2006.211.07:50:39.79#ibcon#about to read 5, iclass 29, count 0 2006.211.07:50:39.79#ibcon#read 5, iclass 29, count 0 2006.211.07:50:39.79#ibcon#about to read 6, iclass 29, count 0 2006.211.07:50:39.79#ibcon#read 6, iclass 29, count 0 2006.211.07:50:39.79#ibcon#end of sib2, iclass 29, count 0 2006.211.07:50:39.79#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:50:39.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:50:39.79#ibcon#[25=USB\r\n] 2006.211.07:50:39.79#ibcon#*before write, iclass 29, count 0 2006.211.07:50:39.79#ibcon#enter sib2, iclass 29, count 0 2006.211.07:50:39.79#ibcon#flushed, iclass 29, count 0 2006.211.07:50:39.79#ibcon#about to write, iclass 29, count 0 2006.211.07:50:39.79#ibcon#wrote, iclass 29, count 0 2006.211.07:50:39.79#ibcon#about to read 3, iclass 29, count 0 2006.211.07:50:39.82#ibcon#read 3, iclass 29, count 0 2006.211.07:50:39.82#ibcon#about to read 4, iclass 29, count 0 2006.211.07:50:39.82#ibcon#read 4, iclass 29, count 0 2006.211.07:50:39.82#ibcon#about to read 5, iclass 29, count 0 2006.211.07:50:39.82#ibcon#read 5, iclass 29, count 0 2006.211.07:50:39.82#ibcon#about to read 6, iclass 29, count 0 2006.211.07:50:39.82#ibcon#read 6, iclass 29, count 0 2006.211.07:50:39.82#ibcon#end of sib2, iclass 29, count 0 2006.211.07:50:39.82#ibcon#*after write, iclass 29, count 0 2006.211.07:50:39.82#ibcon#*before return 0, iclass 29, count 0 2006.211.07:50:39.82#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:50:39.82#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.07:50:39.82#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:50:39.82#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:50:39.82$vc4f8/valo=8,852.99 2006.211.07:50:39.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.07:50:39.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.07:50:39.82#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:39.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:50:39.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:50:39.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:50:39.82#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:50:39.82#ibcon#first serial, iclass 31, count 0 2006.211.07:50:39.82#ibcon#enter sib2, iclass 31, count 0 2006.211.07:50:39.82#ibcon#flushed, iclass 31, count 0 2006.211.07:50:39.82#ibcon#about to write, iclass 31, count 0 2006.211.07:50:39.82#ibcon#wrote, iclass 31, count 0 2006.211.07:50:39.82#ibcon#about to read 3, iclass 31, count 0 2006.211.07:50:39.84#ibcon#read 3, iclass 31, count 0 2006.211.07:50:39.84#ibcon#about to read 4, iclass 31, count 0 2006.211.07:50:39.84#ibcon#read 4, iclass 31, count 0 2006.211.07:50:39.84#ibcon#about to read 5, iclass 31, count 0 2006.211.07:50:39.84#ibcon#read 5, iclass 31, count 0 2006.211.07:50:39.84#ibcon#about to read 6, iclass 31, count 0 2006.211.07:50:39.84#ibcon#read 6, iclass 31, count 0 2006.211.07:50:39.84#ibcon#end of sib2, iclass 31, count 0 2006.211.07:50:39.84#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:50:39.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:50:39.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:50:39.84#ibcon#*before write, iclass 31, count 0 2006.211.07:50:39.84#ibcon#enter sib2, iclass 31, count 0 2006.211.07:50:39.84#ibcon#flushed, iclass 31, count 0 2006.211.07:50:39.84#ibcon#about to write, iclass 31, count 0 2006.211.07:50:39.84#ibcon#wrote, iclass 31, count 0 2006.211.07:50:39.84#ibcon#about to read 3, iclass 31, count 0 2006.211.07:50:39.88#ibcon#read 3, iclass 31, count 0 2006.211.07:50:39.88#ibcon#about to read 4, iclass 31, count 0 2006.211.07:50:39.88#ibcon#read 4, iclass 31, count 0 2006.211.07:50:39.88#ibcon#about to read 5, iclass 31, count 0 2006.211.07:50:39.88#ibcon#read 5, iclass 31, count 0 2006.211.07:50:39.88#ibcon#about to read 6, iclass 31, count 0 2006.211.07:50:39.88#ibcon#read 6, iclass 31, count 0 2006.211.07:50:39.88#ibcon#end of sib2, iclass 31, count 0 2006.211.07:50:39.88#ibcon#*after write, iclass 31, count 0 2006.211.07:50:39.88#ibcon#*before return 0, iclass 31, count 0 2006.211.07:50:39.88#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:50:39.88#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.07:50:39.88#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:50:39.88#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:50:39.88$vc4f8/va=8,7 2006.211.07:50:39.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.07:50:39.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.07:50:39.88#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:39.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:50:39.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:50:39.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:50:39.94#ibcon#enter wrdev, iclass 33, count 2 2006.211.07:50:39.94#ibcon#first serial, iclass 33, count 2 2006.211.07:50:39.94#ibcon#enter sib2, iclass 33, count 2 2006.211.07:50:39.94#ibcon#flushed, iclass 33, count 2 2006.211.07:50:39.94#ibcon#about to write, iclass 33, count 2 2006.211.07:50:39.94#ibcon#wrote, iclass 33, count 2 2006.211.07:50:39.94#ibcon#about to read 3, iclass 33, count 2 2006.211.07:50:39.96#ibcon#read 3, iclass 33, count 2 2006.211.07:50:39.96#ibcon#about to read 4, iclass 33, count 2 2006.211.07:50:39.96#ibcon#read 4, iclass 33, count 2 2006.211.07:50:39.96#ibcon#about to read 5, iclass 33, count 2 2006.211.07:50:39.96#ibcon#read 5, iclass 33, count 2 2006.211.07:50:39.96#ibcon#about to read 6, iclass 33, count 2 2006.211.07:50:39.96#ibcon#read 6, iclass 33, count 2 2006.211.07:50:39.96#ibcon#end of sib2, iclass 33, count 2 2006.211.07:50:39.96#ibcon#*mode == 0, iclass 33, count 2 2006.211.07:50:39.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.07:50:39.96#ibcon#[25=AT08-07\r\n] 2006.211.07:50:39.96#ibcon#*before write, iclass 33, count 2 2006.211.07:50:39.96#ibcon#enter sib2, iclass 33, count 2 2006.211.07:50:39.96#ibcon#flushed, iclass 33, count 2 2006.211.07:50:39.96#ibcon#about to write, iclass 33, count 2 2006.211.07:50:39.96#ibcon#wrote, iclass 33, count 2 2006.211.07:50:39.96#ibcon#about to read 3, iclass 33, count 2 2006.211.07:50:39.99#ibcon#read 3, iclass 33, count 2 2006.211.07:50:39.99#ibcon#about to read 4, iclass 33, count 2 2006.211.07:50:39.99#ibcon#read 4, iclass 33, count 2 2006.211.07:50:39.99#ibcon#about to read 5, iclass 33, count 2 2006.211.07:50:39.99#ibcon#read 5, iclass 33, count 2 2006.211.07:50:39.99#ibcon#about to read 6, iclass 33, count 2 2006.211.07:50:39.99#ibcon#read 6, iclass 33, count 2 2006.211.07:50:39.99#ibcon#end of sib2, iclass 33, count 2 2006.211.07:50:39.99#ibcon#*after write, iclass 33, count 2 2006.211.07:50:39.99#ibcon#*before return 0, iclass 33, count 2 2006.211.07:50:39.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:50:39.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.07:50:39.99#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.07:50:39.99#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:39.99#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:50:40.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:50:40.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:50:40.11#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:50:40.11#ibcon#first serial, iclass 33, count 0 2006.211.07:50:40.11#ibcon#enter sib2, iclass 33, count 0 2006.211.07:50:40.11#ibcon#flushed, iclass 33, count 0 2006.211.07:50:40.11#ibcon#about to write, iclass 33, count 0 2006.211.07:50:40.11#ibcon#wrote, iclass 33, count 0 2006.211.07:50:40.11#ibcon#about to read 3, iclass 33, count 0 2006.211.07:50:40.13#ibcon#read 3, iclass 33, count 0 2006.211.07:50:40.13#ibcon#about to read 4, iclass 33, count 0 2006.211.07:50:40.13#ibcon#read 4, iclass 33, count 0 2006.211.07:50:40.13#ibcon#about to read 5, iclass 33, count 0 2006.211.07:50:40.13#ibcon#read 5, iclass 33, count 0 2006.211.07:50:40.13#ibcon#about to read 6, iclass 33, count 0 2006.211.07:50:40.13#ibcon#read 6, iclass 33, count 0 2006.211.07:50:40.13#ibcon#end of sib2, iclass 33, count 0 2006.211.07:50:40.13#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:50:40.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:50:40.13#ibcon#[25=USB\r\n] 2006.211.07:50:40.13#ibcon#*before write, iclass 33, count 0 2006.211.07:50:40.13#ibcon#enter sib2, iclass 33, count 0 2006.211.07:50:40.13#ibcon#flushed, iclass 33, count 0 2006.211.07:50:40.13#ibcon#about to write, iclass 33, count 0 2006.211.07:50:40.13#ibcon#wrote, iclass 33, count 0 2006.211.07:50:40.13#ibcon#about to read 3, iclass 33, count 0 2006.211.07:50:40.16#ibcon#read 3, iclass 33, count 0 2006.211.07:50:40.16#ibcon#about to read 4, iclass 33, count 0 2006.211.07:50:40.16#ibcon#read 4, iclass 33, count 0 2006.211.07:50:40.16#ibcon#about to read 5, iclass 33, count 0 2006.211.07:50:40.16#ibcon#read 5, iclass 33, count 0 2006.211.07:50:40.16#ibcon#about to read 6, iclass 33, count 0 2006.211.07:50:40.16#ibcon#read 6, iclass 33, count 0 2006.211.07:50:40.16#ibcon#end of sib2, iclass 33, count 0 2006.211.07:50:40.16#ibcon#*after write, iclass 33, count 0 2006.211.07:50:40.16#ibcon#*before return 0, iclass 33, count 0 2006.211.07:50:40.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:50:40.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.07:50:40.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:50:40.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:50:40.16$vc4f8/vblo=1,632.99 2006.211.07:50:40.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.07:50:40.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.07:50:40.16#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:40.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:50:40.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:50:40.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:50:40.16#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:50:40.16#ibcon#first serial, iclass 35, count 0 2006.211.07:50:40.16#ibcon#enter sib2, iclass 35, count 0 2006.211.07:50:40.16#ibcon#flushed, iclass 35, count 0 2006.211.07:50:40.16#ibcon#about to write, iclass 35, count 0 2006.211.07:50:40.16#ibcon#wrote, iclass 35, count 0 2006.211.07:50:40.16#ibcon#about to read 3, iclass 35, count 0 2006.211.07:50:40.18#ibcon#read 3, iclass 35, count 0 2006.211.07:50:40.18#ibcon#about to read 4, iclass 35, count 0 2006.211.07:50:40.18#ibcon#read 4, iclass 35, count 0 2006.211.07:50:40.18#ibcon#about to read 5, iclass 35, count 0 2006.211.07:50:40.18#ibcon#read 5, iclass 35, count 0 2006.211.07:50:40.18#ibcon#about to read 6, iclass 35, count 0 2006.211.07:50:40.18#ibcon#read 6, iclass 35, count 0 2006.211.07:50:40.18#ibcon#end of sib2, iclass 35, count 0 2006.211.07:50:40.18#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:50:40.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:50:40.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:50:40.18#ibcon#*before write, iclass 35, count 0 2006.211.07:50:40.18#ibcon#enter sib2, iclass 35, count 0 2006.211.07:50:40.18#ibcon#flushed, iclass 35, count 0 2006.211.07:50:40.18#ibcon#about to write, iclass 35, count 0 2006.211.07:50:40.18#ibcon#wrote, iclass 35, count 0 2006.211.07:50:40.18#ibcon#about to read 3, iclass 35, count 0 2006.211.07:50:40.22#ibcon#read 3, iclass 35, count 0 2006.211.07:50:40.22#ibcon#about to read 4, iclass 35, count 0 2006.211.07:50:40.22#ibcon#read 4, iclass 35, count 0 2006.211.07:50:40.22#ibcon#about to read 5, iclass 35, count 0 2006.211.07:50:40.22#ibcon#read 5, iclass 35, count 0 2006.211.07:50:40.22#ibcon#about to read 6, iclass 35, count 0 2006.211.07:50:40.22#ibcon#read 6, iclass 35, count 0 2006.211.07:50:40.22#ibcon#end of sib2, iclass 35, count 0 2006.211.07:50:40.22#ibcon#*after write, iclass 35, count 0 2006.211.07:50:40.22#ibcon#*before return 0, iclass 35, count 0 2006.211.07:50:40.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:50:40.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.07:50:40.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:50:40.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:50:40.22$vc4f8/vb=1,4 2006.211.07:50:40.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.07:50:40.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.07:50:40.22#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:40.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:50:40.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:50:40.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:50:40.22#ibcon#enter wrdev, iclass 37, count 2 2006.211.07:50:40.22#ibcon#first serial, iclass 37, count 2 2006.211.07:50:40.22#ibcon#enter sib2, iclass 37, count 2 2006.211.07:50:40.22#ibcon#flushed, iclass 37, count 2 2006.211.07:50:40.22#ibcon#about to write, iclass 37, count 2 2006.211.07:50:40.22#ibcon#wrote, iclass 37, count 2 2006.211.07:50:40.22#ibcon#about to read 3, iclass 37, count 2 2006.211.07:50:40.24#ibcon#read 3, iclass 37, count 2 2006.211.07:50:40.24#ibcon#about to read 4, iclass 37, count 2 2006.211.07:50:40.24#ibcon#read 4, iclass 37, count 2 2006.211.07:50:40.24#ibcon#about to read 5, iclass 37, count 2 2006.211.07:50:40.24#ibcon#read 5, iclass 37, count 2 2006.211.07:50:40.24#ibcon#about to read 6, iclass 37, count 2 2006.211.07:50:40.24#ibcon#read 6, iclass 37, count 2 2006.211.07:50:40.24#ibcon#end of sib2, iclass 37, count 2 2006.211.07:50:40.24#ibcon#*mode == 0, iclass 37, count 2 2006.211.07:50:40.24#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.07:50:40.24#ibcon#[27=AT01-04\r\n] 2006.211.07:50:40.24#ibcon#*before write, iclass 37, count 2 2006.211.07:50:40.24#ibcon#enter sib2, iclass 37, count 2 2006.211.07:50:40.24#ibcon#flushed, iclass 37, count 2 2006.211.07:50:40.24#ibcon#about to write, iclass 37, count 2 2006.211.07:50:40.24#ibcon#wrote, iclass 37, count 2 2006.211.07:50:40.24#ibcon#about to read 3, iclass 37, count 2 2006.211.07:50:40.27#ibcon#read 3, iclass 37, count 2 2006.211.07:50:40.27#ibcon#about to read 4, iclass 37, count 2 2006.211.07:50:40.27#ibcon#read 4, iclass 37, count 2 2006.211.07:50:40.27#ibcon#about to read 5, iclass 37, count 2 2006.211.07:50:40.27#ibcon#read 5, iclass 37, count 2 2006.211.07:50:40.27#ibcon#about to read 6, iclass 37, count 2 2006.211.07:50:40.27#ibcon#read 6, iclass 37, count 2 2006.211.07:50:40.27#ibcon#end of sib2, iclass 37, count 2 2006.211.07:50:40.27#ibcon#*after write, iclass 37, count 2 2006.211.07:50:40.27#ibcon#*before return 0, iclass 37, count 2 2006.211.07:50:40.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:50:40.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:50:40.27#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.07:50:40.27#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:40.27#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:50:40.39#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:50:40.39#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:50:40.39#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:50:40.39#ibcon#first serial, iclass 37, count 0 2006.211.07:50:40.39#ibcon#enter sib2, iclass 37, count 0 2006.211.07:50:40.39#ibcon#flushed, iclass 37, count 0 2006.211.07:50:40.39#ibcon#about to write, iclass 37, count 0 2006.211.07:50:40.39#ibcon#wrote, iclass 37, count 0 2006.211.07:50:40.39#ibcon#about to read 3, iclass 37, count 0 2006.211.07:50:40.41#ibcon#read 3, iclass 37, count 0 2006.211.07:50:40.41#ibcon#about to read 4, iclass 37, count 0 2006.211.07:50:40.41#ibcon#read 4, iclass 37, count 0 2006.211.07:50:40.41#ibcon#about to read 5, iclass 37, count 0 2006.211.07:50:40.41#ibcon#read 5, iclass 37, count 0 2006.211.07:50:40.41#ibcon#about to read 6, iclass 37, count 0 2006.211.07:50:40.41#ibcon#read 6, iclass 37, count 0 2006.211.07:50:40.41#ibcon#end of sib2, iclass 37, count 0 2006.211.07:50:40.41#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:50:40.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:50:40.41#ibcon#[27=USB\r\n] 2006.211.07:50:40.41#ibcon#*before write, iclass 37, count 0 2006.211.07:50:40.41#ibcon#enter sib2, iclass 37, count 0 2006.211.07:50:40.41#ibcon#flushed, iclass 37, count 0 2006.211.07:50:40.41#ibcon#about to write, iclass 37, count 0 2006.211.07:50:40.41#ibcon#wrote, iclass 37, count 0 2006.211.07:50:40.41#ibcon#about to read 3, iclass 37, count 0 2006.211.07:50:40.44#ibcon#read 3, iclass 37, count 0 2006.211.07:50:40.44#ibcon#about to read 4, iclass 37, count 0 2006.211.07:50:40.44#ibcon#read 4, iclass 37, count 0 2006.211.07:50:40.44#ibcon#about to read 5, iclass 37, count 0 2006.211.07:50:40.44#ibcon#read 5, iclass 37, count 0 2006.211.07:50:40.44#ibcon#about to read 6, iclass 37, count 0 2006.211.07:50:40.44#ibcon#read 6, iclass 37, count 0 2006.211.07:50:40.44#ibcon#end of sib2, iclass 37, count 0 2006.211.07:50:40.44#ibcon#*after write, iclass 37, count 0 2006.211.07:50:40.44#ibcon#*before return 0, iclass 37, count 0 2006.211.07:50:40.44#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:50:40.44#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:50:40.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:50:40.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:50:40.44$vc4f8/vblo=2,640.99 2006.211.07:50:40.44#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.07:50:40.44#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.07:50:40.44#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:40.44#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:50:40.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:50:40.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:50:40.44#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:50:40.44#ibcon#first serial, iclass 39, count 0 2006.211.07:50:40.44#ibcon#enter sib2, iclass 39, count 0 2006.211.07:50:40.44#ibcon#flushed, iclass 39, count 0 2006.211.07:50:40.44#ibcon#about to write, iclass 39, count 0 2006.211.07:50:40.44#ibcon#wrote, iclass 39, count 0 2006.211.07:50:40.44#ibcon#about to read 3, iclass 39, count 0 2006.211.07:50:40.46#ibcon#read 3, iclass 39, count 0 2006.211.07:50:40.46#ibcon#about to read 4, iclass 39, count 0 2006.211.07:50:40.46#ibcon#read 4, iclass 39, count 0 2006.211.07:50:40.46#ibcon#about to read 5, iclass 39, count 0 2006.211.07:50:40.46#ibcon#read 5, iclass 39, count 0 2006.211.07:50:40.46#ibcon#about to read 6, iclass 39, count 0 2006.211.07:50:40.46#ibcon#read 6, iclass 39, count 0 2006.211.07:50:40.46#ibcon#end of sib2, iclass 39, count 0 2006.211.07:50:40.46#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:50:40.46#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:50:40.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:50:40.46#ibcon#*before write, iclass 39, count 0 2006.211.07:50:40.46#ibcon#enter sib2, iclass 39, count 0 2006.211.07:50:40.46#ibcon#flushed, iclass 39, count 0 2006.211.07:50:40.46#ibcon#about to write, iclass 39, count 0 2006.211.07:50:40.46#ibcon#wrote, iclass 39, count 0 2006.211.07:50:40.46#ibcon#about to read 3, iclass 39, count 0 2006.211.07:50:40.50#ibcon#read 3, iclass 39, count 0 2006.211.07:50:40.50#ibcon#about to read 4, iclass 39, count 0 2006.211.07:50:40.50#ibcon#read 4, iclass 39, count 0 2006.211.07:50:40.50#ibcon#about to read 5, iclass 39, count 0 2006.211.07:50:40.50#ibcon#read 5, iclass 39, count 0 2006.211.07:50:40.50#ibcon#about to read 6, iclass 39, count 0 2006.211.07:50:40.50#ibcon#read 6, iclass 39, count 0 2006.211.07:50:40.50#ibcon#end of sib2, iclass 39, count 0 2006.211.07:50:40.50#ibcon#*after write, iclass 39, count 0 2006.211.07:50:40.50#ibcon#*before return 0, iclass 39, count 0 2006.211.07:50:40.50#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:50:40.50#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:50:40.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:50:40.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:50:40.50$vc4f8/vb=2,4 2006.211.07:50:40.50#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.07:50:40.50#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.07:50:40.50#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:40.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:50:40.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:50:40.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:50:40.56#ibcon#enter wrdev, iclass 3, count 2 2006.211.07:50:40.56#ibcon#first serial, iclass 3, count 2 2006.211.07:50:40.56#ibcon#enter sib2, iclass 3, count 2 2006.211.07:50:40.56#ibcon#flushed, iclass 3, count 2 2006.211.07:50:40.56#ibcon#about to write, iclass 3, count 2 2006.211.07:50:40.56#ibcon#wrote, iclass 3, count 2 2006.211.07:50:40.56#ibcon#about to read 3, iclass 3, count 2 2006.211.07:50:40.58#ibcon#read 3, iclass 3, count 2 2006.211.07:50:40.58#ibcon#about to read 4, iclass 3, count 2 2006.211.07:50:40.58#ibcon#read 4, iclass 3, count 2 2006.211.07:50:40.58#ibcon#about to read 5, iclass 3, count 2 2006.211.07:50:40.58#ibcon#read 5, iclass 3, count 2 2006.211.07:50:40.58#ibcon#about to read 6, iclass 3, count 2 2006.211.07:50:40.58#ibcon#read 6, iclass 3, count 2 2006.211.07:50:40.58#ibcon#end of sib2, iclass 3, count 2 2006.211.07:50:40.58#ibcon#*mode == 0, iclass 3, count 2 2006.211.07:50:40.58#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.07:50:40.58#ibcon#[27=AT02-04\r\n] 2006.211.07:50:40.58#ibcon#*before write, iclass 3, count 2 2006.211.07:50:40.58#ibcon#enter sib2, iclass 3, count 2 2006.211.07:50:40.58#ibcon#flushed, iclass 3, count 2 2006.211.07:50:40.58#ibcon#about to write, iclass 3, count 2 2006.211.07:50:40.58#ibcon#wrote, iclass 3, count 2 2006.211.07:50:40.58#ibcon#about to read 3, iclass 3, count 2 2006.211.07:50:40.61#ibcon#read 3, iclass 3, count 2 2006.211.07:50:40.61#ibcon#about to read 4, iclass 3, count 2 2006.211.07:50:40.61#ibcon#read 4, iclass 3, count 2 2006.211.07:50:40.61#ibcon#about to read 5, iclass 3, count 2 2006.211.07:50:40.61#ibcon#read 5, iclass 3, count 2 2006.211.07:50:40.61#ibcon#about to read 6, iclass 3, count 2 2006.211.07:50:40.61#ibcon#read 6, iclass 3, count 2 2006.211.07:50:40.61#ibcon#end of sib2, iclass 3, count 2 2006.211.07:50:40.61#ibcon#*after write, iclass 3, count 2 2006.211.07:50:40.61#ibcon#*before return 0, iclass 3, count 2 2006.211.07:50:40.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:50:40.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:50:40.61#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.07:50:40.61#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:40.61#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:50:40.73#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:50:40.73#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:50:40.73#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:50:40.73#ibcon#first serial, iclass 3, count 0 2006.211.07:50:40.73#ibcon#enter sib2, iclass 3, count 0 2006.211.07:50:40.73#ibcon#flushed, iclass 3, count 0 2006.211.07:50:40.73#ibcon#about to write, iclass 3, count 0 2006.211.07:50:40.73#ibcon#wrote, iclass 3, count 0 2006.211.07:50:40.73#ibcon#about to read 3, iclass 3, count 0 2006.211.07:50:40.75#ibcon#read 3, iclass 3, count 0 2006.211.07:50:40.75#ibcon#about to read 4, iclass 3, count 0 2006.211.07:50:40.75#ibcon#read 4, iclass 3, count 0 2006.211.07:50:40.75#ibcon#about to read 5, iclass 3, count 0 2006.211.07:50:40.75#ibcon#read 5, iclass 3, count 0 2006.211.07:50:40.75#ibcon#about to read 6, iclass 3, count 0 2006.211.07:50:40.75#ibcon#read 6, iclass 3, count 0 2006.211.07:50:40.75#ibcon#end of sib2, iclass 3, count 0 2006.211.07:50:40.75#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:50:40.75#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:50:40.75#ibcon#[27=USB\r\n] 2006.211.07:50:40.75#ibcon#*before write, iclass 3, count 0 2006.211.07:50:40.75#ibcon#enter sib2, iclass 3, count 0 2006.211.07:50:40.75#ibcon#flushed, iclass 3, count 0 2006.211.07:50:40.75#ibcon#about to write, iclass 3, count 0 2006.211.07:50:40.75#ibcon#wrote, iclass 3, count 0 2006.211.07:50:40.75#ibcon#about to read 3, iclass 3, count 0 2006.211.07:50:40.78#ibcon#read 3, iclass 3, count 0 2006.211.07:50:40.78#ibcon#about to read 4, iclass 3, count 0 2006.211.07:50:40.78#ibcon#read 4, iclass 3, count 0 2006.211.07:50:40.78#ibcon#about to read 5, iclass 3, count 0 2006.211.07:50:40.78#ibcon#read 5, iclass 3, count 0 2006.211.07:50:40.78#ibcon#about to read 6, iclass 3, count 0 2006.211.07:50:40.78#ibcon#read 6, iclass 3, count 0 2006.211.07:50:40.78#ibcon#end of sib2, iclass 3, count 0 2006.211.07:50:40.78#ibcon#*after write, iclass 3, count 0 2006.211.07:50:40.78#ibcon#*before return 0, iclass 3, count 0 2006.211.07:50:40.78#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:50:40.78#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:50:40.78#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:50:40.78#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:50:40.78$vc4f8/vblo=3,656.99 2006.211.07:50:40.78#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.07:50:40.78#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.07:50:40.78#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:40.78#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:50:40.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:50:40.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:50:40.78#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:50:40.78#ibcon#first serial, iclass 5, count 0 2006.211.07:50:40.78#ibcon#enter sib2, iclass 5, count 0 2006.211.07:50:40.78#ibcon#flushed, iclass 5, count 0 2006.211.07:50:40.78#ibcon#about to write, iclass 5, count 0 2006.211.07:50:40.78#ibcon#wrote, iclass 5, count 0 2006.211.07:50:40.78#ibcon#about to read 3, iclass 5, count 0 2006.211.07:50:40.80#ibcon#read 3, iclass 5, count 0 2006.211.07:50:40.80#ibcon#about to read 4, iclass 5, count 0 2006.211.07:50:40.80#ibcon#read 4, iclass 5, count 0 2006.211.07:50:40.80#ibcon#about to read 5, iclass 5, count 0 2006.211.07:50:40.80#ibcon#read 5, iclass 5, count 0 2006.211.07:50:40.80#ibcon#about to read 6, iclass 5, count 0 2006.211.07:50:40.80#ibcon#read 6, iclass 5, count 0 2006.211.07:50:40.80#ibcon#end of sib2, iclass 5, count 0 2006.211.07:50:40.80#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:50:40.80#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:50:40.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:50:40.80#ibcon#*before write, iclass 5, count 0 2006.211.07:50:40.80#ibcon#enter sib2, iclass 5, count 0 2006.211.07:50:40.80#ibcon#flushed, iclass 5, count 0 2006.211.07:50:40.80#ibcon#about to write, iclass 5, count 0 2006.211.07:50:40.80#ibcon#wrote, iclass 5, count 0 2006.211.07:50:40.80#ibcon#about to read 3, iclass 5, count 0 2006.211.07:50:40.84#ibcon#read 3, iclass 5, count 0 2006.211.07:50:40.84#ibcon#about to read 4, iclass 5, count 0 2006.211.07:50:40.84#ibcon#read 4, iclass 5, count 0 2006.211.07:50:40.84#ibcon#about to read 5, iclass 5, count 0 2006.211.07:50:40.84#ibcon#read 5, iclass 5, count 0 2006.211.07:50:40.84#ibcon#about to read 6, iclass 5, count 0 2006.211.07:50:40.84#ibcon#read 6, iclass 5, count 0 2006.211.07:50:40.84#ibcon#end of sib2, iclass 5, count 0 2006.211.07:50:40.84#ibcon#*after write, iclass 5, count 0 2006.211.07:50:40.84#ibcon#*before return 0, iclass 5, count 0 2006.211.07:50:40.84#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:50:40.84#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:50:40.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:50:40.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:50:40.84$vc4f8/vb=3,3 2006.211.07:50:40.84#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.07:50:40.84#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.07:50:40.84#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:40.84#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:50:40.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:50:40.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:50:40.90#ibcon#enter wrdev, iclass 7, count 2 2006.211.07:50:40.90#ibcon#first serial, iclass 7, count 2 2006.211.07:50:40.90#ibcon#enter sib2, iclass 7, count 2 2006.211.07:50:40.90#ibcon#flushed, iclass 7, count 2 2006.211.07:50:40.90#ibcon#about to write, iclass 7, count 2 2006.211.07:50:40.90#ibcon#wrote, iclass 7, count 2 2006.211.07:50:40.90#ibcon#about to read 3, iclass 7, count 2 2006.211.07:50:40.92#ibcon#read 3, iclass 7, count 2 2006.211.07:50:40.92#ibcon#about to read 4, iclass 7, count 2 2006.211.07:50:40.92#ibcon#read 4, iclass 7, count 2 2006.211.07:50:40.92#ibcon#about to read 5, iclass 7, count 2 2006.211.07:50:40.92#ibcon#read 5, iclass 7, count 2 2006.211.07:50:40.92#ibcon#about to read 6, iclass 7, count 2 2006.211.07:50:40.92#ibcon#read 6, iclass 7, count 2 2006.211.07:50:40.92#ibcon#end of sib2, iclass 7, count 2 2006.211.07:50:40.92#ibcon#*mode == 0, iclass 7, count 2 2006.211.07:50:40.92#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.07:50:40.92#ibcon#[27=AT03-03\r\n] 2006.211.07:50:40.92#ibcon#*before write, iclass 7, count 2 2006.211.07:50:40.92#ibcon#enter sib2, iclass 7, count 2 2006.211.07:50:40.92#ibcon#flushed, iclass 7, count 2 2006.211.07:50:40.92#ibcon#about to write, iclass 7, count 2 2006.211.07:50:40.92#ibcon#wrote, iclass 7, count 2 2006.211.07:50:40.92#ibcon#about to read 3, iclass 7, count 2 2006.211.07:50:40.95#ibcon#read 3, iclass 7, count 2 2006.211.07:50:40.95#ibcon#about to read 4, iclass 7, count 2 2006.211.07:50:40.95#ibcon#read 4, iclass 7, count 2 2006.211.07:50:40.95#ibcon#about to read 5, iclass 7, count 2 2006.211.07:50:40.95#ibcon#read 5, iclass 7, count 2 2006.211.07:50:40.95#ibcon#about to read 6, iclass 7, count 2 2006.211.07:50:40.95#ibcon#read 6, iclass 7, count 2 2006.211.07:50:40.95#ibcon#end of sib2, iclass 7, count 2 2006.211.07:50:40.95#ibcon#*after write, iclass 7, count 2 2006.211.07:50:40.95#ibcon#*before return 0, iclass 7, count 2 2006.211.07:50:40.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:50:40.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:50:40.95#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.07:50:40.95#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:40.95#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:50:41.07#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:50:41.07#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:50:41.07#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:50:41.07#ibcon#first serial, iclass 7, count 0 2006.211.07:50:41.07#ibcon#enter sib2, iclass 7, count 0 2006.211.07:50:41.07#ibcon#flushed, iclass 7, count 0 2006.211.07:50:41.07#ibcon#about to write, iclass 7, count 0 2006.211.07:50:41.07#ibcon#wrote, iclass 7, count 0 2006.211.07:50:41.07#ibcon#about to read 3, iclass 7, count 0 2006.211.07:50:41.09#ibcon#read 3, iclass 7, count 0 2006.211.07:50:41.09#ibcon#about to read 4, iclass 7, count 0 2006.211.07:50:41.09#ibcon#read 4, iclass 7, count 0 2006.211.07:50:41.09#ibcon#about to read 5, iclass 7, count 0 2006.211.07:50:41.09#ibcon#read 5, iclass 7, count 0 2006.211.07:50:41.09#ibcon#about to read 6, iclass 7, count 0 2006.211.07:50:41.09#ibcon#read 6, iclass 7, count 0 2006.211.07:50:41.09#ibcon#end of sib2, iclass 7, count 0 2006.211.07:50:41.09#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:50:41.09#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:50:41.09#ibcon#[27=USB\r\n] 2006.211.07:50:41.09#ibcon#*before write, iclass 7, count 0 2006.211.07:50:41.09#ibcon#enter sib2, iclass 7, count 0 2006.211.07:50:41.09#ibcon#flushed, iclass 7, count 0 2006.211.07:50:41.09#ibcon#about to write, iclass 7, count 0 2006.211.07:50:41.09#ibcon#wrote, iclass 7, count 0 2006.211.07:50:41.09#ibcon#about to read 3, iclass 7, count 0 2006.211.07:50:41.12#ibcon#read 3, iclass 7, count 0 2006.211.07:50:41.12#ibcon#about to read 4, iclass 7, count 0 2006.211.07:50:41.12#ibcon#read 4, iclass 7, count 0 2006.211.07:50:41.12#ibcon#about to read 5, iclass 7, count 0 2006.211.07:50:41.12#ibcon#read 5, iclass 7, count 0 2006.211.07:50:41.12#ibcon#about to read 6, iclass 7, count 0 2006.211.07:50:41.12#ibcon#read 6, iclass 7, count 0 2006.211.07:50:41.12#ibcon#end of sib2, iclass 7, count 0 2006.211.07:50:41.12#ibcon#*after write, iclass 7, count 0 2006.211.07:50:41.12#ibcon#*before return 0, iclass 7, count 0 2006.211.07:50:41.12#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:50:41.12#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:50:41.12#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:50:41.12#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:50:41.12$vc4f8/vblo=4,712.99 2006.211.07:50:41.12#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:50:41.12#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:50:41.12#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:41.12#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:50:41.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:50:41.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:50:41.12#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:50:41.12#ibcon#first serial, iclass 11, count 0 2006.211.07:50:41.12#ibcon#enter sib2, iclass 11, count 0 2006.211.07:50:41.12#ibcon#flushed, iclass 11, count 0 2006.211.07:50:41.12#ibcon#about to write, iclass 11, count 0 2006.211.07:50:41.12#ibcon#wrote, iclass 11, count 0 2006.211.07:50:41.12#ibcon#about to read 3, iclass 11, count 0 2006.211.07:50:41.14#ibcon#read 3, iclass 11, count 0 2006.211.07:50:41.14#ibcon#about to read 4, iclass 11, count 0 2006.211.07:50:41.14#ibcon#read 4, iclass 11, count 0 2006.211.07:50:41.14#ibcon#about to read 5, iclass 11, count 0 2006.211.07:50:41.14#ibcon#read 5, iclass 11, count 0 2006.211.07:50:41.14#ibcon#about to read 6, iclass 11, count 0 2006.211.07:50:41.14#ibcon#read 6, iclass 11, count 0 2006.211.07:50:41.14#ibcon#end of sib2, iclass 11, count 0 2006.211.07:50:41.14#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:50:41.14#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:50:41.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:50:41.14#ibcon#*before write, iclass 11, count 0 2006.211.07:50:41.14#ibcon#enter sib2, iclass 11, count 0 2006.211.07:50:41.14#ibcon#flushed, iclass 11, count 0 2006.211.07:50:41.14#ibcon#about to write, iclass 11, count 0 2006.211.07:50:41.14#ibcon#wrote, iclass 11, count 0 2006.211.07:50:41.14#ibcon#about to read 3, iclass 11, count 0 2006.211.07:50:41.18#ibcon#read 3, iclass 11, count 0 2006.211.07:50:41.18#ibcon#about to read 4, iclass 11, count 0 2006.211.07:50:41.18#ibcon#read 4, iclass 11, count 0 2006.211.07:50:41.18#ibcon#about to read 5, iclass 11, count 0 2006.211.07:50:41.18#ibcon#read 5, iclass 11, count 0 2006.211.07:50:41.18#ibcon#about to read 6, iclass 11, count 0 2006.211.07:50:41.18#ibcon#read 6, iclass 11, count 0 2006.211.07:50:41.18#ibcon#end of sib2, iclass 11, count 0 2006.211.07:50:41.18#ibcon#*after write, iclass 11, count 0 2006.211.07:50:41.18#ibcon#*before return 0, iclass 11, count 0 2006.211.07:50:41.18#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:50:41.18#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:50:41.18#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:50:41.18#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:50:41.18$vc4f8/vb=4,3 2006.211.07:50:41.18#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.07:50:41.18#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.07:50:41.18#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:41.18#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:50:41.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:50:41.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:50:41.24#ibcon#enter wrdev, iclass 13, count 2 2006.211.07:50:41.24#ibcon#first serial, iclass 13, count 2 2006.211.07:50:41.24#ibcon#enter sib2, iclass 13, count 2 2006.211.07:50:41.24#ibcon#flushed, iclass 13, count 2 2006.211.07:50:41.24#ibcon#about to write, iclass 13, count 2 2006.211.07:50:41.24#ibcon#wrote, iclass 13, count 2 2006.211.07:50:41.24#ibcon#about to read 3, iclass 13, count 2 2006.211.07:50:41.26#ibcon#read 3, iclass 13, count 2 2006.211.07:50:41.26#ibcon#about to read 4, iclass 13, count 2 2006.211.07:50:41.26#ibcon#read 4, iclass 13, count 2 2006.211.07:50:41.26#ibcon#about to read 5, iclass 13, count 2 2006.211.07:50:41.26#ibcon#read 5, iclass 13, count 2 2006.211.07:50:41.26#ibcon#about to read 6, iclass 13, count 2 2006.211.07:50:41.26#ibcon#read 6, iclass 13, count 2 2006.211.07:50:41.26#ibcon#end of sib2, iclass 13, count 2 2006.211.07:50:41.26#ibcon#*mode == 0, iclass 13, count 2 2006.211.07:50:41.26#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.07:50:41.26#ibcon#[27=AT04-03\r\n] 2006.211.07:50:41.26#ibcon#*before write, iclass 13, count 2 2006.211.07:50:41.26#ibcon#enter sib2, iclass 13, count 2 2006.211.07:50:41.26#ibcon#flushed, iclass 13, count 2 2006.211.07:50:41.26#ibcon#about to write, iclass 13, count 2 2006.211.07:50:41.26#ibcon#wrote, iclass 13, count 2 2006.211.07:50:41.26#ibcon#about to read 3, iclass 13, count 2 2006.211.07:50:41.29#ibcon#read 3, iclass 13, count 2 2006.211.07:50:41.29#ibcon#about to read 4, iclass 13, count 2 2006.211.07:50:41.29#ibcon#read 4, iclass 13, count 2 2006.211.07:50:41.29#ibcon#about to read 5, iclass 13, count 2 2006.211.07:50:41.29#ibcon#read 5, iclass 13, count 2 2006.211.07:50:41.29#ibcon#about to read 6, iclass 13, count 2 2006.211.07:50:41.29#ibcon#read 6, iclass 13, count 2 2006.211.07:50:41.29#ibcon#end of sib2, iclass 13, count 2 2006.211.07:50:41.29#ibcon#*after write, iclass 13, count 2 2006.211.07:50:41.29#ibcon#*before return 0, iclass 13, count 2 2006.211.07:50:41.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:50:41.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:50:41.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.07:50:41.29#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:41.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:50:41.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:50:41.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:50:41.41#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:50:41.41#ibcon#first serial, iclass 13, count 0 2006.211.07:50:41.41#ibcon#enter sib2, iclass 13, count 0 2006.211.07:50:41.41#ibcon#flushed, iclass 13, count 0 2006.211.07:50:41.41#ibcon#about to write, iclass 13, count 0 2006.211.07:50:41.41#ibcon#wrote, iclass 13, count 0 2006.211.07:50:41.41#ibcon#about to read 3, iclass 13, count 0 2006.211.07:50:41.43#ibcon#read 3, iclass 13, count 0 2006.211.07:50:41.43#ibcon#about to read 4, iclass 13, count 0 2006.211.07:50:41.43#ibcon#read 4, iclass 13, count 0 2006.211.07:50:41.43#ibcon#about to read 5, iclass 13, count 0 2006.211.07:50:41.43#ibcon#read 5, iclass 13, count 0 2006.211.07:50:41.43#ibcon#about to read 6, iclass 13, count 0 2006.211.07:50:41.43#ibcon#read 6, iclass 13, count 0 2006.211.07:50:41.43#ibcon#end of sib2, iclass 13, count 0 2006.211.07:50:41.43#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:50:41.43#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:50:41.43#ibcon#[27=USB\r\n] 2006.211.07:50:41.43#ibcon#*before write, iclass 13, count 0 2006.211.07:50:41.43#ibcon#enter sib2, iclass 13, count 0 2006.211.07:50:41.43#ibcon#flushed, iclass 13, count 0 2006.211.07:50:41.43#ibcon#about to write, iclass 13, count 0 2006.211.07:50:41.43#ibcon#wrote, iclass 13, count 0 2006.211.07:50:41.43#ibcon#about to read 3, iclass 13, count 0 2006.211.07:50:41.46#ibcon#read 3, iclass 13, count 0 2006.211.07:50:41.46#ibcon#about to read 4, iclass 13, count 0 2006.211.07:50:41.46#ibcon#read 4, iclass 13, count 0 2006.211.07:50:41.46#ibcon#about to read 5, iclass 13, count 0 2006.211.07:50:41.46#ibcon#read 5, iclass 13, count 0 2006.211.07:50:41.46#ibcon#about to read 6, iclass 13, count 0 2006.211.07:50:41.46#ibcon#read 6, iclass 13, count 0 2006.211.07:50:41.46#ibcon#end of sib2, iclass 13, count 0 2006.211.07:50:41.46#ibcon#*after write, iclass 13, count 0 2006.211.07:50:41.46#ibcon#*before return 0, iclass 13, count 0 2006.211.07:50:41.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:50:41.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:50:41.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:50:41.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:50:41.46$vc4f8/vblo=5,744.99 2006.211.07:50:41.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:50:41.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:50:41.46#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:41.46#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:50:41.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:50:41.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:50:41.46#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:50:41.46#ibcon#first serial, iclass 15, count 0 2006.211.07:50:41.46#ibcon#enter sib2, iclass 15, count 0 2006.211.07:50:41.46#ibcon#flushed, iclass 15, count 0 2006.211.07:50:41.46#ibcon#about to write, iclass 15, count 0 2006.211.07:50:41.46#ibcon#wrote, iclass 15, count 0 2006.211.07:50:41.46#ibcon#about to read 3, iclass 15, count 0 2006.211.07:50:41.48#ibcon#read 3, iclass 15, count 0 2006.211.07:50:41.48#ibcon#about to read 4, iclass 15, count 0 2006.211.07:50:41.48#ibcon#read 4, iclass 15, count 0 2006.211.07:50:41.48#ibcon#about to read 5, iclass 15, count 0 2006.211.07:50:41.48#ibcon#read 5, iclass 15, count 0 2006.211.07:50:41.48#ibcon#about to read 6, iclass 15, count 0 2006.211.07:50:41.48#ibcon#read 6, iclass 15, count 0 2006.211.07:50:41.48#ibcon#end of sib2, iclass 15, count 0 2006.211.07:50:41.48#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:50:41.48#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:50:41.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:50:41.48#ibcon#*before write, iclass 15, count 0 2006.211.07:50:41.48#ibcon#enter sib2, iclass 15, count 0 2006.211.07:50:41.48#ibcon#flushed, iclass 15, count 0 2006.211.07:50:41.48#ibcon#about to write, iclass 15, count 0 2006.211.07:50:41.48#ibcon#wrote, iclass 15, count 0 2006.211.07:50:41.48#ibcon#about to read 3, iclass 15, count 0 2006.211.07:50:41.52#ibcon#read 3, iclass 15, count 0 2006.211.07:50:41.52#ibcon#about to read 4, iclass 15, count 0 2006.211.07:50:41.52#ibcon#read 4, iclass 15, count 0 2006.211.07:50:41.52#ibcon#about to read 5, iclass 15, count 0 2006.211.07:50:41.52#ibcon#read 5, iclass 15, count 0 2006.211.07:50:41.52#ibcon#about to read 6, iclass 15, count 0 2006.211.07:50:41.52#ibcon#read 6, iclass 15, count 0 2006.211.07:50:41.52#ibcon#end of sib2, iclass 15, count 0 2006.211.07:50:41.52#ibcon#*after write, iclass 15, count 0 2006.211.07:50:41.52#ibcon#*before return 0, iclass 15, count 0 2006.211.07:50:41.52#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:50:41.52#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:50:41.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:50:41.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:50:41.52$vc4f8/vb=5,3 2006.211.07:50:41.52#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.07:50:41.52#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.07:50:41.52#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:41.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:50:41.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:50:41.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:50:41.58#ibcon#enter wrdev, iclass 17, count 2 2006.211.07:50:41.58#ibcon#first serial, iclass 17, count 2 2006.211.07:50:41.58#ibcon#enter sib2, iclass 17, count 2 2006.211.07:50:41.58#ibcon#flushed, iclass 17, count 2 2006.211.07:50:41.58#ibcon#about to write, iclass 17, count 2 2006.211.07:50:41.58#ibcon#wrote, iclass 17, count 2 2006.211.07:50:41.58#ibcon#about to read 3, iclass 17, count 2 2006.211.07:50:41.60#ibcon#read 3, iclass 17, count 2 2006.211.07:50:41.60#ibcon#about to read 4, iclass 17, count 2 2006.211.07:50:41.60#ibcon#read 4, iclass 17, count 2 2006.211.07:50:41.60#ibcon#about to read 5, iclass 17, count 2 2006.211.07:50:41.60#ibcon#read 5, iclass 17, count 2 2006.211.07:50:41.60#ibcon#about to read 6, iclass 17, count 2 2006.211.07:50:41.60#ibcon#read 6, iclass 17, count 2 2006.211.07:50:41.60#ibcon#end of sib2, iclass 17, count 2 2006.211.07:50:41.60#ibcon#*mode == 0, iclass 17, count 2 2006.211.07:50:41.60#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.07:50:41.60#ibcon#[27=AT05-03\r\n] 2006.211.07:50:41.60#ibcon#*before write, iclass 17, count 2 2006.211.07:50:41.60#ibcon#enter sib2, iclass 17, count 2 2006.211.07:50:41.60#ibcon#flushed, iclass 17, count 2 2006.211.07:50:41.60#ibcon#about to write, iclass 17, count 2 2006.211.07:50:41.60#ibcon#wrote, iclass 17, count 2 2006.211.07:50:41.60#ibcon#about to read 3, iclass 17, count 2 2006.211.07:50:41.63#ibcon#read 3, iclass 17, count 2 2006.211.07:50:41.63#ibcon#about to read 4, iclass 17, count 2 2006.211.07:50:41.63#ibcon#read 4, iclass 17, count 2 2006.211.07:50:41.63#ibcon#about to read 5, iclass 17, count 2 2006.211.07:50:41.63#ibcon#read 5, iclass 17, count 2 2006.211.07:50:41.63#ibcon#about to read 6, iclass 17, count 2 2006.211.07:50:41.63#ibcon#read 6, iclass 17, count 2 2006.211.07:50:41.63#ibcon#end of sib2, iclass 17, count 2 2006.211.07:50:41.63#ibcon#*after write, iclass 17, count 2 2006.211.07:50:41.63#ibcon#*before return 0, iclass 17, count 2 2006.211.07:50:41.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:50:41.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:50:41.63#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.07:50:41.63#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:41.63#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:50:41.75#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:50:41.75#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:50:41.75#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:50:41.75#ibcon#first serial, iclass 17, count 0 2006.211.07:50:41.75#ibcon#enter sib2, iclass 17, count 0 2006.211.07:50:41.75#ibcon#flushed, iclass 17, count 0 2006.211.07:50:41.75#ibcon#about to write, iclass 17, count 0 2006.211.07:50:41.75#ibcon#wrote, iclass 17, count 0 2006.211.07:50:41.75#ibcon#about to read 3, iclass 17, count 0 2006.211.07:50:41.77#ibcon#read 3, iclass 17, count 0 2006.211.07:50:41.77#ibcon#about to read 4, iclass 17, count 0 2006.211.07:50:41.77#ibcon#read 4, iclass 17, count 0 2006.211.07:50:41.77#ibcon#about to read 5, iclass 17, count 0 2006.211.07:50:41.77#ibcon#read 5, iclass 17, count 0 2006.211.07:50:41.77#ibcon#about to read 6, iclass 17, count 0 2006.211.07:50:41.77#ibcon#read 6, iclass 17, count 0 2006.211.07:50:41.77#ibcon#end of sib2, iclass 17, count 0 2006.211.07:50:41.77#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:50:41.77#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:50:41.77#ibcon#[27=USB\r\n] 2006.211.07:50:41.77#ibcon#*before write, iclass 17, count 0 2006.211.07:50:41.77#ibcon#enter sib2, iclass 17, count 0 2006.211.07:50:41.77#ibcon#flushed, iclass 17, count 0 2006.211.07:50:41.77#ibcon#about to write, iclass 17, count 0 2006.211.07:50:41.77#ibcon#wrote, iclass 17, count 0 2006.211.07:50:41.77#ibcon#about to read 3, iclass 17, count 0 2006.211.07:50:41.80#ibcon#read 3, iclass 17, count 0 2006.211.07:50:41.80#ibcon#about to read 4, iclass 17, count 0 2006.211.07:50:41.80#ibcon#read 4, iclass 17, count 0 2006.211.07:50:41.80#ibcon#about to read 5, iclass 17, count 0 2006.211.07:50:41.80#ibcon#read 5, iclass 17, count 0 2006.211.07:50:41.80#ibcon#about to read 6, iclass 17, count 0 2006.211.07:50:41.80#ibcon#read 6, iclass 17, count 0 2006.211.07:50:41.80#ibcon#end of sib2, iclass 17, count 0 2006.211.07:50:41.80#ibcon#*after write, iclass 17, count 0 2006.211.07:50:41.80#ibcon#*before return 0, iclass 17, count 0 2006.211.07:50:41.80#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:50:41.80#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:50:41.80#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:50:41.80#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:50:41.80$vc4f8/vblo=6,752.99 2006.211.07:50:41.80#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.07:50:41.80#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.07:50:41.80#ibcon#ireg 17 cls_cnt 0 2006.211.07:50:41.80#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:50:41.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:50:41.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:50:41.80#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:50:41.80#ibcon#first serial, iclass 19, count 0 2006.211.07:50:41.80#ibcon#enter sib2, iclass 19, count 0 2006.211.07:50:41.80#ibcon#flushed, iclass 19, count 0 2006.211.07:50:41.80#ibcon#about to write, iclass 19, count 0 2006.211.07:50:41.80#ibcon#wrote, iclass 19, count 0 2006.211.07:50:41.80#ibcon#about to read 3, iclass 19, count 0 2006.211.07:50:41.82#ibcon#read 3, iclass 19, count 0 2006.211.07:50:41.82#ibcon#about to read 4, iclass 19, count 0 2006.211.07:50:41.82#ibcon#read 4, iclass 19, count 0 2006.211.07:50:41.82#ibcon#about to read 5, iclass 19, count 0 2006.211.07:50:41.82#ibcon#read 5, iclass 19, count 0 2006.211.07:50:41.82#ibcon#about to read 6, iclass 19, count 0 2006.211.07:50:41.82#ibcon#read 6, iclass 19, count 0 2006.211.07:50:41.82#ibcon#end of sib2, iclass 19, count 0 2006.211.07:50:41.82#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:50:41.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:50:41.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:50:41.82#ibcon#*before write, iclass 19, count 0 2006.211.07:50:41.82#ibcon#enter sib2, iclass 19, count 0 2006.211.07:50:41.82#ibcon#flushed, iclass 19, count 0 2006.211.07:50:41.82#ibcon#about to write, iclass 19, count 0 2006.211.07:50:41.82#ibcon#wrote, iclass 19, count 0 2006.211.07:50:41.82#ibcon#about to read 3, iclass 19, count 0 2006.211.07:50:41.86#ibcon#read 3, iclass 19, count 0 2006.211.07:50:41.86#ibcon#about to read 4, iclass 19, count 0 2006.211.07:50:41.86#ibcon#read 4, iclass 19, count 0 2006.211.07:50:41.86#ibcon#about to read 5, iclass 19, count 0 2006.211.07:50:41.86#ibcon#read 5, iclass 19, count 0 2006.211.07:50:41.86#ibcon#about to read 6, iclass 19, count 0 2006.211.07:50:41.86#ibcon#read 6, iclass 19, count 0 2006.211.07:50:41.86#ibcon#end of sib2, iclass 19, count 0 2006.211.07:50:41.86#ibcon#*after write, iclass 19, count 0 2006.211.07:50:41.86#ibcon#*before return 0, iclass 19, count 0 2006.211.07:50:41.86#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:50:41.86#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:50:41.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:50:41.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:50:41.86$vc4f8/vb=6,3 2006.211.07:50:41.86#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.07:50:41.86#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.07:50:41.86#ibcon#ireg 11 cls_cnt 2 2006.211.07:50:41.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:50:41.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:50:41.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:50:41.92#ibcon#enter wrdev, iclass 21, count 2 2006.211.07:50:41.92#ibcon#first serial, iclass 21, count 2 2006.211.07:50:41.92#ibcon#enter sib2, iclass 21, count 2 2006.211.07:50:41.92#ibcon#flushed, iclass 21, count 2 2006.211.07:50:41.92#ibcon#about to write, iclass 21, count 2 2006.211.07:50:41.92#ibcon#wrote, iclass 21, count 2 2006.211.07:50:41.92#ibcon#about to read 3, iclass 21, count 2 2006.211.07:50:41.94#ibcon#read 3, iclass 21, count 2 2006.211.07:50:41.94#ibcon#about to read 4, iclass 21, count 2 2006.211.07:50:41.94#ibcon#read 4, iclass 21, count 2 2006.211.07:50:41.94#ibcon#about to read 5, iclass 21, count 2 2006.211.07:50:41.94#ibcon#read 5, iclass 21, count 2 2006.211.07:50:41.94#ibcon#about to read 6, iclass 21, count 2 2006.211.07:50:41.94#ibcon#read 6, iclass 21, count 2 2006.211.07:50:41.94#ibcon#end of sib2, iclass 21, count 2 2006.211.07:50:41.94#ibcon#*mode == 0, iclass 21, count 2 2006.211.07:50:41.94#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.07:50:41.94#ibcon#[27=AT06-03\r\n] 2006.211.07:50:41.94#ibcon#*before write, iclass 21, count 2 2006.211.07:50:41.94#ibcon#enter sib2, iclass 21, count 2 2006.211.07:50:41.94#ibcon#flushed, iclass 21, count 2 2006.211.07:50:41.94#ibcon#about to write, iclass 21, count 2 2006.211.07:50:41.94#ibcon#wrote, iclass 21, count 2 2006.211.07:50:41.94#ibcon#about to read 3, iclass 21, count 2 2006.211.07:50:41.97#ibcon#read 3, iclass 21, count 2 2006.211.07:50:41.97#ibcon#about to read 4, iclass 21, count 2 2006.211.07:50:41.97#ibcon#read 4, iclass 21, count 2 2006.211.07:50:41.97#ibcon#about to read 5, iclass 21, count 2 2006.211.07:50:41.97#ibcon#read 5, iclass 21, count 2 2006.211.07:50:41.97#ibcon#about to read 6, iclass 21, count 2 2006.211.07:50:41.97#ibcon#read 6, iclass 21, count 2 2006.211.07:50:41.97#ibcon#end of sib2, iclass 21, count 2 2006.211.07:50:41.97#ibcon#*after write, iclass 21, count 2 2006.211.07:50:41.97#ibcon#*before return 0, iclass 21, count 2 2006.211.07:50:41.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:50:41.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:50:41.97#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.07:50:41.97#ibcon#ireg 7 cls_cnt 0 2006.211.07:50:41.97#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:50:42.09#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:50:42.09#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:50:42.09#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:50:42.09#ibcon#first serial, iclass 21, count 0 2006.211.07:50:42.09#ibcon#enter sib2, iclass 21, count 0 2006.211.07:50:42.09#ibcon#flushed, iclass 21, count 0 2006.211.07:50:42.09#ibcon#about to write, iclass 21, count 0 2006.211.07:50:42.09#ibcon#wrote, iclass 21, count 0 2006.211.07:50:42.09#ibcon#about to read 3, iclass 21, count 0 2006.211.07:50:42.11#ibcon#read 3, iclass 21, count 0 2006.211.07:50:42.11#ibcon#about to read 4, iclass 21, count 0 2006.211.07:50:42.11#ibcon#read 4, iclass 21, count 0 2006.211.07:50:42.11#ibcon#about to read 5, iclass 21, count 0 2006.211.07:50:42.11#ibcon#read 5, iclass 21, count 0 2006.211.07:50:42.11#ibcon#about to read 6, iclass 21, count 0 2006.211.07:50:42.11#ibcon#read 6, iclass 21, count 0 2006.211.07:50:42.11#ibcon#end of sib2, iclass 21, count 0 2006.211.07:50:42.11#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:50:42.11#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:50:42.11#ibcon#[27=USB\r\n] 2006.211.07:50:42.11#ibcon#*before write, iclass 21, count 0 2006.211.07:50:42.11#ibcon#enter sib2, iclass 21, count 0 2006.211.07:50:42.11#ibcon#flushed, iclass 21, count 0 2006.211.07:50:42.11#ibcon#about to write, iclass 21, count 0 2006.211.07:50:42.11#ibcon#wrote, iclass 21, count 0 2006.211.07:50:42.11#ibcon#about to read 3, iclass 21, count 0 2006.211.07:50:42.14#ibcon#read 3, iclass 21, count 0 2006.211.07:50:42.14#ibcon#about to read 4, iclass 21, count 0 2006.211.07:50:42.14#ibcon#read 4, iclass 21, count 0 2006.211.07:50:42.14#ibcon#about to read 5, iclass 21, count 0 2006.211.07:50:42.14#ibcon#read 5, iclass 21, count 0 2006.211.07:50:42.14#ibcon#about to read 6, iclass 21, count 0 2006.211.07:50:42.14#ibcon#read 6, iclass 21, count 0 2006.211.07:50:42.14#ibcon#end of sib2, iclass 21, count 0 2006.211.07:50:42.14#ibcon#*after write, iclass 21, count 0 2006.211.07:50:42.14#ibcon#*before return 0, iclass 21, count 0 2006.211.07:50:42.14#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:50:42.14#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:50:42.14#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:50:42.14#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:50:42.14$vc4f8/vabw=wide 2006.211.07:50:42.14#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:50:42.14#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:50:42.14#ibcon#ireg 8 cls_cnt 0 2006.211.07:50:42.14#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:42.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:42.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:42.14#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:50:42.14#ibcon#first serial, iclass 23, count 0 2006.211.07:50:42.14#ibcon#enter sib2, iclass 23, count 0 2006.211.07:50:42.14#ibcon#flushed, iclass 23, count 0 2006.211.07:50:42.14#ibcon#about to write, iclass 23, count 0 2006.211.07:50:42.14#ibcon#wrote, iclass 23, count 0 2006.211.07:50:42.14#ibcon#about to read 3, iclass 23, count 0 2006.211.07:50:42.16#ibcon#read 3, iclass 23, count 0 2006.211.07:50:42.16#ibcon#about to read 4, iclass 23, count 0 2006.211.07:50:42.16#ibcon#read 4, iclass 23, count 0 2006.211.07:50:42.16#ibcon#about to read 5, iclass 23, count 0 2006.211.07:50:42.16#ibcon#read 5, iclass 23, count 0 2006.211.07:50:42.16#ibcon#about to read 6, iclass 23, count 0 2006.211.07:50:42.16#ibcon#read 6, iclass 23, count 0 2006.211.07:50:42.16#ibcon#end of sib2, iclass 23, count 0 2006.211.07:50:42.16#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:50:42.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:50:42.16#ibcon#[25=BW32\r\n] 2006.211.07:50:42.16#ibcon#*before write, iclass 23, count 0 2006.211.07:50:42.16#ibcon#enter sib2, iclass 23, count 0 2006.211.07:50:42.16#ibcon#flushed, iclass 23, count 0 2006.211.07:50:42.16#ibcon#about to write, iclass 23, count 0 2006.211.07:50:42.16#ibcon#wrote, iclass 23, count 0 2006.211.07:50:42.16#ibcon#about to read 3, iclass 23, count 0 2006.211.07:50:42.19#ibcon#read 3, iclass 23, count 0 2006.211.07:50:42.19#ibcon#about to read 4, iclass 23, count 0 2006.211.07:50:42.19#ibcon#read 4, iclass 23, count 0 2006.211.07:50:42.19#ibcon#about to read 5, iclass 23, count 0 2006.211.07:50:42.19#ibcon#read 5, iclass 23, count 0 2006.211.07:50:42.19#ibcon#about to read 6, iclass 23, count 0 2006.211.07:50:42.19#ibcon#read 6, iclass 23, count 0 2006.211.07:50:42.19#ibcon#end of sib2, iclass 23, count 0 2006.211.07:50:42.19#ibcon#*after write, iclass 23, count 0 2006.211.07:50:42.19#ibcon#*before return 0, iclass 23, count 0 2006.211.07:50:42.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:42.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:50:42.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:50:42.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:50:42.19$vc4f8/vbbw=wide 2006.211.07:50:42.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:50:42.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:50:42.19#ibcon#ireg 8 cls_cnt 0 2006.211.07:50:42.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:50:42.26#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:50:42.26#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:50:42.26#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:50:42.26#ibcon#first serial, iclass 25, count 0 2006.211.07:50:42.26#ibcon#enter sib2, iclass 25, count 0 2006.211.07:50:42.26#ibcon#flushed, iclass 25, count 0 2006.211.07:50:42.26#ibcon#about to write, iclass 25, count 0 2006.211.07:50:42.26#ibcon#wrote, iclass 25, count 0 2006.211.07:50:42.26#ibcon#about to read 3, iclass 25, count 0 2006.211.07:50:42.28#ibcon#read 3, iclass 25, count 0 2006.211.07:50:42.28#ibcon#about to read 4, iclass 25, count 0 2006.211.07:50:42.28#ibcon#read 4, iclass 25, count 0 2006.211.07:50:42.28#ibcon#about to read 5, iclass 25, count 0 2006.211.07:50:42.28#ibcon#read 5, iclass 25, count 0 2006.211.07:50:42.28#ibcon#about to read 6, iclass 25, count 0 2006.211.07:50:42.28#ibcon#read 6, iclass 25, count 0 2006.211.07:50:42.28#ibcon#end of sib2, iclass 25, count 0 2006.211.07:50:42.28#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:50:42.28#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:50:42.28#ibcon#[27=BW32\r\n] 2006.211.07:50:42.28#ibcon#*before write, iclass 25, count 0 2006.211.07:50:42.28#ibcon#enter sib2, iclass 25, count 0 2006.211.07:50:42.28#ibcon#flushed, iclass 25, count 0 2006.211.07:50:42.28#ibcon#about to write, iclass 25, count 0 2006.211.07:50:42.28#ibcon#wrote, iclass 25, count 0 2006.211.07:50:42.28#ibcon#about to read 3, iclass 25, count 0 2006.211.07:50:42.31#ibcon#read 3, iclass 25, count 0 2006.211.07:50:42.31#ibcon#about to read 4, iclass 25, count 0 2006.211.07:50:42.31#ibcon#read 4, iclass 25, count 0 2006.211.07:50:42.31#ibcon#about to read 5, iclass 25, count 0 2006.211.07:50:42.31#ibcon#read 5, iclass 25, count 0 2006.211.07:50:42.31#ibcon#about to read 6, iclass 25, count 0 2006.211.07:50:42.31#ibcon#read 6, iclass 25, count 0 2006.211.07:50:42.31#ibcon#end of sib2, iclass 25, count 0 2006.211.07:50:42.31#ibcon#*after write, iclass 25, count 0 2006.211.07:50:42.31#ibcon#*before return 0, iclass 25, count 0 2006.211.07:50:42.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:50:42.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:50:42.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:50:42.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:50:42.31$4f8m12a/ifd4f 2006.211.07:50:42.31$ifd4f/lo= 2006.211.07:50:42.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:50:42.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:50:42.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:50:42.31$ifd4f/patch= 2006.211.07:50:42.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:50:42.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:50:42.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:50:42.31$4f8m12a/"form=m,16.000,1:2 2006.211.07:50:42.31$4f8m12a/"tpicd 2006.211.07:50:42.31$4f8m12a/echo=off 2006.211.07:50:42.31$4f8m12a/xlog=off 2006.211.07:50:42.31:!2006.211.07:51:10 2006.211.07:50:53.14#trakl#Source acquired 2006.211.07:50:55.14#flagr#flagr/antenna,acquired 2006.211.07:51:10.00:preob 2006.211.07:51:11.14/onsource/TRACKING 2006.211.07:51:11.14:!2006.211.07:51:20 2006.211.07:51:20.00:data_valid=on 2006.211.07:51:20.00:midob 2006.211.07:51:20.14/onsource/TRACKING 2006.211.07:51:20.14/wx/24.94,1010.1,77 2006.211.07:51:20.30/cable/+6.4398E-03 2006.211.07:51:21.39/va/01,08,usb,yes,28,29 2006.211.07:51:21.39/va/02,07,usb,yes,28,29 2006.211.07:51:21.39/va/03,06,usb,yes,29,30 2006.211.07:51:21.39/va/04,07,usb,yes,29,31 2006.211.07:51:21.39/va/05,07,usb,yes,31,33 2006.211.07:51:21.39/va/06,06,usb,yes,30,30 2006.211.07:51:21.39/va/07,06,usb,yes,31,30 2006.211.07:51:21.39/va/08,07,usb,yes,29,29 2006.211.07:51:21.62/valo/01,532.99,yes,locked 2006.211.07:51:21.62/valo/02,572.99,yes,locked 2006.211.07:51:21.62/valo/03,672.99,yes,locked 2006.211.07:51:21.62/valo/04,832.99,yes,locked 2006.211.07:51:21.62/valo/05,652.99,yes,locked 2006.211.07:51:21.62/valo/06,772.99,yes,locked 2006.211.07:51:21.62/valo/07,832.99,yes,locked 2006.211.07:51:21.62/valo/08,852.99,yes,locked 2006.211.07:51:22.71/vb/01,04,usb,yes,28,27 2006.211.07:51:22.71/vb/02,04,usb,yes,30,31 2006.211.07:51:22.71/vb/03,03,usb,yes,33,37 2006.211.07:51:22.71/vb/04,03,usb,yes,33,34 2006.211.07:51:22.71/vb/05,03,usb,yes,32,36 2006.211.07:51:22.71/vb/06,03,usb,yes,32,36 2006.211.07:51:22.71/vb/07,04,usb,yes,28,28 2006.211.07:51:22.71/vb/08,03,usb,yes,33,36 2006.211.07:51:22.95/vblo/01,632.99,yes,locked 2006.211.07:51:22.95/vblo/02,640.99,yes,locked 2006.211.07:51:22.95/vblo/03,656.99,yes,locked 2006.211.07:51:22.95/vblo/04,712.99,yes,locked 2006.211.07:51:22.95/vblo/05,744.99,yes,locked 2006.211.07:51:22.95/vblo/06,752.99,yes,locked 2006.211.07:51:22.95/vblo/07,734.99,yes,locked 2006.211.07:51:22.95/vblo/08,744.99,yes,locked 2006.211.07:51:23.10/vabw/8 2006.211.07:51:23.25/vbbw/8 2006.211.07:51:23.34/xfe/off,on,13.7 2006.211.07:51:23.73/ifatt/23,28,28,28 2006.211.07:51:24.08/fmout-gps/S +4.46E-07 2006.211.07:51:24.12:!2006.211.07:52:20 2006.211.07:52:20.00:data_valid=off 2006.211.07:52:20.00:postob 2006.211.07:52:20.11/cable/+6.4390E-03 2006.211.07:52:20.11/wx/24.93,1010.1,77 2006.211.07:52:21.08/fmout-gps/S +4.46E-07 2006.211.07:52:21.08:scan_name=211-0753,k06211,60 2006.211.07:52:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.211.07:52:21.14#flagr#flagr/antenna,new-source 2006.211.07:52:22.14:checkk5 2006.211.07:52:22.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:52:22.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:52:23.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:52:23.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:52:23.83/chk_obsdata//k5ts1/T2110751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:52:24.17/chk_obsdata//k5ts2/T2110751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:52:24.50/chk_obsdata//k5ts3/T2110751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:52:24.84/chk_obsdata//k5ts4/T2110751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:52:25.49/k5log//k5ts1_log_newline 2006.211.07:52:26.15/k5log//k5ts2_log_newline 2006.211.07:52:26.81/k5log//k5ts3_log_newline 2006.211.07:52:27.47/k5log//k5ts4_log_newline 2006.211.07:52:27.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:52:27.49:4f8m12a=1 2006.211.07:52:27.49$4f8m12a/echo=on 2006.211.07:52:27.49$4f8m12a/pcalon 2006.211.07:52:27.49$pcalon/"no phase cal control is implemented here 2006.211.07:52:27.49$4f8m12a/"tpicd=stop 2006.211.07:52:27.49$4f8m12a/vc4f8 2006.211.07:52:27.49$vc4f8/valo=1,532.99 2006.211.07:52:27.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:52:27.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:52:27.50#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:27.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:27.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:27.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:27.50#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:52:27.50#ibcon#first serial, iclass 32, count 0 2006.211.07:52:27.50#ibcon#enter sib2, iclass 32, count 0 2006.211.07:52:27.50#ibcon#flushed, iclass 32, count 0 2006.211.07:52:27.50#ibcon#about to write, iclass 32, count 0 2006.211.07:52:27.50#ibcon#wrote, iclass 32, count 0 2006.211.07:52:27.50#ibcon#about to read 3, iclass 32, count 0 2006.211.07:52:27.52#ibcon#read 3, iclass 32, count 0 2006.211.07:52:27.52#ibcon#about to read 4, iclass 32, count 0 2006.211.07:52:27.52#ibcon#read 4, iclass 32, count 0 2006.211.07:52:27.52#ibcon#about to read 5, iclass 32, count 0 2006.211.07:52:27.52#ibcon#read 5, iclass 32, count 0 2006.211.07:52:27.52#ibcon#about to read 6, iclass 32, count 0 2006.211.07:52:27.52#ibcon#read 6, iclass 32, count 0 2006.211.07:52:27.52#ibcon#end of sib2, iclass 32, count 0 2006.211.07:52:27.52#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:52:27.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:52:27.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:52:27.52#ibcon#*before write, iclass 32, count 0 2006.211.07:52:27.52#ibcon#enter sib2, iclass 32, count 0 2006.211.07:52:27.52#ibcon#flushed, iclass 32, count 0 2006.211.07:52:27.52#ibcon#about to write, iclass 32, count 0 2006.211.07:52:27.52#ibcon#wrote, iclass 32, count 0 2006.211.07:52:27.52#ibcon#about to read 3, iclass 32, count 0 2006.211.07:52:27.57#ibcon#read 3, iclass 32, count 0 2006.211.07:52:27.57#ibcon#about to read 4, iclass 32, count 0 2006.211.07:52:27.57#ibcon#read 4, iclass 32, count 0 2006.211.07:52:27.57#ibcon#about to read 5, iclass 32, count 0 2006.211.07:52:27.57#ibcon#read 5, iclass 32, count 0 2006.211.07:52:27.57#ibcon#about to read 6, iclass 32, count 0 2006.211.07:52:27.57#ibcon#read 6, iclass 32, count 0 2006.211.07:52:27.57#ibcon#end of sib2, iclass 32, count 0 2006.211.07:52:27.57#ibcon#*after write, iclass 32, count 0 2006.211.07:52:27.57#ibcon#*before return 0, iclass 32, count 0 2006.211.07:52:27.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:27.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:27.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:52:27.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:52:27.57$vc4f8/va=1,8 2006.211.07:52:27.57#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:52:27.57#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:52:27.57#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:27.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:27.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:27.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:27.57#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:52:27.57#ibcon#first serial, iclass 34, count 2 2006.211.07:52:27.57#ibcon#enter sib2, iclass 34, count 2 2006.211.07:52:27.57#ibcon#flushed, iclass 34, count 2 2006.211.07:52:27.57#ibcon#about to write, iclass 34, count 2 2006.211.07:52:27.57#ibcon#wrote, iclass 34, count 2 2006.211.07:52:27.57#ibcon#about to read 3, iclass 34, count 2 2006.211.07:52:27.59#ibcon#read 3, iclass 34, count 2 2006.211.07:52:27.59#ibcon#about to read 4, iclass 34, count 2 2006.211.07:52:27.59#ibcon#read 4, iclass 34, count 2 2006.211.07:52:27.59#ibcon#about to read 5, iclass 34, count 2 2006.211.07:52:27.59#ibcon#read 5, iclass 34, count 2 2006.211.07:52:27.59#ibcon#about to read 6, iclass 34, count 2 2006.211.07:52:27.59#ibcon#read 6, iclass 34, count 2 2006.211.07:52:27.59#ibcon#end of sib2, iclass 34, count 2 2006.211.07:52:27.59#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:52:27.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:52:27.59#ibcon#[25=AT01-08\r\n] 2006.211.07:52:27.59#ibcon#*before write, iclass 34, count 2 2006.211.07:52:27.59#ibcon#enter sib2, iclass 34, count 2 2006.211.07:52:27.59#ibcon#flushed, iclass 34, count 2 2006.211.07:52:27.59#ibcon#about to write, iclass 34, count 2 2006.211.07:52:27.59#ibcon#wrote, iclass 34, count 2 2006.211.07:52:27.59#ibcon#about to read 3, iclass 34, count 2 2006.211.07:52:27.62#ibcon#read 3, iclass 34, count 2 2006.211.07:52:27.62#ibcon#about to read 4, iclass 34, count 2 2006.211.07:52:27.62#ibcon#read 4, iclass 34, count 2 2006.211.07:52:27.62#ibcon#about to read 5, iclass 34, count 2 2006.211.07:52:27.62#ibcon#read 5, iclass 34, count 2 2006.211.07:52:27.62#ibcon#about to read 6, iclass 34, count 2 2006.211.07:52:27.62#ibcon#read 6, iclass 34, count 2 2006.211.07:52:27.62#ibcon#end of sib2, iclass 34, count 2 2006.211.07:52:27.62#ibcon#*after write, iclass 34, count 2 2006.211.07:52:27.62#ibcon#*before return 0, iclass 34, count 2 2006.211.07:52:27.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:27.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:27.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:52:27.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:27.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:27.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:27.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:27.74#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:52:27.74#ibcon#first serial, iclass 34, count 0 2006.211.07:52:27.74#ibcon#enter sib2, iclass 34, count 0 2006.211.07:52:27.74#ibcon#flushed, iclass 34, count 0 2006.211.07:52:27.74#ibcon#about to write, iclass 34, count 0 2006.211.07:52:27.74#ibcon#wrote, iclass 34, count 0 2006.211.07:52:27.74#ibcon#about to read 3, iclass 34, count 0 2006.211.07:52:27.76#ibcon#read 3, iclass 34, count 0 2006.211.07:52:27.76#ibcon#about to read 4, iclass 34, count 0 2006.211.07:52:27.76#ibcon#read 4, iclass 34, count 0 2006.211.07:52:27.76#ibcon#about to read 5, iclass 34, count 0 2006.211.07:52:27.76#ibcon#read 5, iclass 34, count 0 2006.211.07:52:27.76#ibcon#about to read 6, iclass 34, count 0 2006.211.07:52:27.76#ibcon#read 6, iclass 34, count 0 2006.211.07:52:27.76#ibcon#end of sib2, iclass 34, count 0 2006.211.07:52:27.76#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:52:27.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:52:27.76#ibcon#[25=USB\r\n] 2006.211.07:52:27.76#ibcon#*before write, iclass 34, count 0 2006.211.07:52:27.76#ibcon#enter sib2, iclass 34, count 0 2006.211.07:52:27.76#ibcon#flushed, iclass 34, count 0 2006.211.07:52:27.76#ibcon#about to write, iclass 34, count 0 2006.211.07:52:27.76#ibcon#wrote, iclass 34, count 0 2006.211.07:52:27.76#ibcon#about to read 3, iclass 34, count 0 2006.211.07:52:27.79#ibcon#read 3, iclass 34, count 0 2006.211.07:52:27.79#ibcon#about to read 4, iclass 34, count 0 2006.211.07:52:27.79#ibcon#read 4, iclass 34, count 0 2006.211.07:52:27.79#ibcon#about to read 5, iclass 34, count 0 2006.211.07:52:27.79#ibcon#read 5, iclass 34, count 0 2006.211.07:52:27.79#ibcon#about to read 6, iclass 34, count 0 2006.211.07:52:27.79#ibcon#read 6, iclass 34, count 0 2006.211.07:52:27.79#ibcon#end of sib2, iclass 34, count 0 2006.211.07:52:27.79#ibcon#*after write, iclass 34, count 0 2006.211.07:52:27.79#ibcon#*before return 0, iclass 34, count 0 2006.211.07:52:27.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:27.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:27.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:52:27.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:52:27.79$vc4f8/valo=2,572.99 2006.211.07:52:27.79#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.07:52:27.79#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.07:52:27.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:27.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:52:27.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:52:27.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:52:27.79#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:52:27.79#ibcon#first serial, iclass 36, count 0 2006.211.07:52:27.79#ibcon#enter sib2, iclass 36, count 0 2006.211.07:52:27.79#ibcon#flushed, iclass 36, count 0 2006.211.07:52:27.79#ibcon#about to write, iclass 36, count 0 2006.211.07:52:27.79#ibcon#wrote, iclass 36, count 0 2006.211.07:52:27.79#ibcon#about to read 3, iclass 36, count 0 2006.211.07:52:27.81#ibcon#read 3, iclass 36, count 0 2006.211.07:52:27.81#ibcon#about to read 4, iclass 36, count 0 2006.211.07:52:27.81#ibcon#read 4, iclass 36, count 0 2006.211.07:52:27.81#ibcon#about to read 5, iclass 36, count 0 2006.211.07:52:27.81#ibcon#read 5, iclass 36, count 0 2006.211.07:52:27.81#ibcon#about to read 6, iclass 36, count 0 2006.211.07:52:27.81#ibcon#read 6, iclass 36, count 0 2006.211.07:52:27.81#ibcon#end of sib2, iclass 36, count 0 2006.211.07:52:27.81#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:52:27.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:52:27.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:52:27.81#ibcon#*before write, iclass 36, count 0 2006.211.07:52:27.81#ibcon#enter sib2, iclass 36, count 0 2006.211.07:52:27.81#ibcon#flushed, iclass 36, count 0 2006.211.07:52:27.81#ibcon#about to write, iclass 36, count 0 2006.211.07:52:27.81#ibcon#wrote, iclass 36, count 0 2006.211.07:52:27.81#ibcon#about to read 3, iclass 36, count 0 2006.211.07:52:27.85#ibcon#read 3, iclass 36, count 0 2006.211.07:52:27.85#ibcon#about to read 4, iclass 36, count 0 2006.211.07:52:27.85#ibcon#read 4, iclass 36, count 0 2006.211.07:52:27.85#ibcon#about to read 5, iclass 36, count 0 2006.211.07:52:27.85#ibcon#read 5, iclass 36, count 0 2006.211.07:52:27.85#ibcon#about to read 6, iclass 36, count 0 2006.211.07:52:27.85#ibcon#read 6, iclass 36, count 0 2006.211.07:52:27.85#ibcon#end of sib2, iclass 36, count 0 2006.211.07:52:27.85#ibcon#*after write, iclass 36, count 0 2006.211.07:52:27.85#ibcon#*before return 0, iclass 36, count 0 2006.211.07:52:27.85#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:52:27.85#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:52:27.85#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:52:27.85#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:52:27.85$vc4f8/va=2,7 2006.211.07:52:27.85#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.07:52:27.85#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.07:52:27.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:27.85#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:52:27.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:52:27.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:52:27.91#ibcon#enter wrdev, iclass 38, count 2 2006.211.07:52:27.91#ibcon#first serial, iclass 38, count 2 2006.211.07:52:27.91#ibcon#enter sib2, iclass 38, count 2 2006.211.07:52:27.91#ibcon#flushed, iclass 38, count 2 2006.211.07:52:27.91#ibcon#about to write, iclass 38, count 2 2006.211.07:52:27.91#ibcon#wrote, iclass 38, count 2 2006.211.07:52:27.91#ibcon#about to read 3, iclass 38, count 2 2006.211.07:52:27.93#ibcon#read 3, iclass 38, count 2 2006.211.07:52:27.93#ibcon#about to read 4, iclass 38, count 2 2006.211.07:52:27.93#ibcon#read 4, iclass 38, count 2 2006.211.07:52:27.93#ibcon#about to read 5, iclass 38, count 2 2006.211.07:52:27.93#ibcon#read 5, iclass 38, count 2 2006.211.07:52:27.93#ibcon#about to read 6, iclass 38, count 2 2006.211.07:52:27.93#ibcon#read 6, iclass 38, count 2 2006.211.07:52:27.93#ibcon#end of sib2, iclass 38, count 2 2006.211.07:52:27.93#ibcon#*mode == 0, iclass 38, count 2 2006.211.07:52:27.93#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.07:52:27.93#ibcon#[25=AT02-07\r\n] 2006.211.07:52:27.93#ibcon#*before write, iclass 38, count 2 2006.211.07:52:27.93#ibcon#enter sib2, iclass 38, count 2 2006.211.07:52:27.93#ibcon#flushed, iclass 38, count 2 2006.211.07:52:27.93#ibcon#about to write, iclass 38, count 2 2006.211.07:52:27.93#ibcon#wrote, iclass 38, count 2 2006.211.07:52:27.93#ibcon#about to read 3, iclass 38, count 2 2006.211.07:52:27.96#ibcon#read 3, iclass 38, count 2 2006.211.07:52:27.96#ibcon#about to read 4, iclass 38, count 2 2006.211.07:52:27.96#ibcon#read 4, iclass 38, count 2 2006.211.07:52:27.96#ibcon#about to read 5, iclass 38, count 2 2006.211.07:52:27.96#ibcon#read 5, iclass 38, count 2 2006.211.07:52:27.96#ibcon#about to read 6, iclass 38, count 2 2006.211.07:52:27.96#ibcon#read 6, iclass 38, count 2 2006.211.07:52:27.96#ibcon#end of sib2, iclass 38, count 2 2006.211.07:52:27.96#ibcon#*after write, iclass 38, count 2 2006.211.07:52:27.96#ibcon#*before return 0, iclass 38, count 2 2006.211.07:52:27.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:52:27.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:52:27.96#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.07:52:27.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:27.96#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:52:28.08#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:52:28.08#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:52:28.08#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:52:28.08#ibcon#first serial, iclass 38, count 0 2006.211.07:52:28.08#ibcon#enter sib2, iclass 38, count 0 2006.211.07:52:28.08#ibcon#flushed, iclass 38, count 0 2006.211.07:52:28.08#ibcon#about to write, iclass 38, count 0 2006.211.07:52:28.08#ibcon#wrote, iclass 38, count 0 2006.211.07:52:28.08#ibcon#about to read 3, iclass 38, count 0 2006.211.07:52:28.10#ibcon#read 3, iclass 38, count 0 2006.211.07:52:28.10#ibcon#about to read 4, iclass 38, count 0 2006.211.07:52:28.10#ibcon#read 4, iclass 38, count 0 2006.211.07:52:28.10#ibcon#about to read 5, iclass 38, count 0 2006.211.07:52:28.10#ibcon#read 5, iclass 38, count 0 2006.211.07:52:28.10#ibcon#about to read 6, iclass 38, count 0 2006.211.07:52:28.10#ibcon#read 6, iclass 38, count 0 2006.211.07:52:28.10#ibcon#end of sib2, iclass 38, count 0 2006.211.07:52:28.10#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:52:28.10#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:52:28.10#ibcon#[25=USB\r\n] 2006.211.07:52:28.10#ibcon#*before write, iclass 38, count 0 2006.211.07:52:28.10#ibcon#enter sib2, iclass 38, count 0 2006.211.07:52:28.10#ibcon#flushed, iclass 38, count 0 2006.211.07:52:28.10#ibcon#about to write, iclass 38, count 0 2006.211.07:52:28.10#ibcon#wrote, iclass 38, count 0 2006.211.07:52:28.10#ibcon#about to read 3, iclass 38, count 0 2006.211.07:52:28.13#ibcon#read 3, iclass 38, count 0 2006.211.07:52:28.13#ibcon#about to read 4, iclass 38, count 0 2006.211.07:52:28.13#ibcon#read 4, iclass 38, count 0 2006.211.07:52:28.13#ibcon#about to read 5, iclass 38, count 0 2006.211.07:52:28.13#ibcon#read 5, iclass 38, count 0 2006.211.07:52:28.13#ibcon#about to read 6, iclass 38, count 0 2006.211.07:52:28.13#ibcon#read 6, iclass 38, count 0 2006.211.07:52:28.13#ibcon#end of sib2, iclass 38, count 0 2006.211.07:52:28.13#ibcon#*after write, iclass 38, count 0 2006.211.07:52:28.13#ibcon#*before return 0, iclass 38, count 0 2006.211.07:52:28.13#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:52:28.13#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:52:28.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:52:28.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:52:28.13$vc4f8/valo=3,672.99 2006.211.07:52:28.13#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:52:28.13#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:52:28.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:28.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:28.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:28.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:28.13#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:52:28.13#ibcon#first serial, iclass 40, count 0 2006.211.07:52:28.13#ibcon#enter sib2, iclass 40, count 0 2006.211.07:52:28.13#ibcon#flushed, iclass 40, count 0 2006.211.07:52:28.13#ibcon#about to write, iclass 40, count 0 2006.211.07:52:28.13#ibcon#wrote, iclass 40, count 0 2006.211.07:52:28.13#ibcon#about to read 3, iclass 40, count 0 2006.211.07:52:28.15#ibcon#read 3, iclass 40, count 0 2006.211.07:52:28.15#ibcon#about to read 4, iclass 40, count 0 2006.211.07:52:28.15#ibcon#read 4, iclass 40, count 0 2006.211.07:52:28.15#ibcon#about to read 5, iclass 40, count 0 2006.211.07:52:28.15#ibcon#read 5, iclass 40, count 0 2006.211.07:52:28.15#ibcon#about to read 6, iclass 40, count 0 2006.211.07:52:28.15#ibcon#read 6, iclass 40, count 0 2006.211.07:52:28.15#ibcon#end of sib2, iclass 40, count 0 2006.211.07:52:28.15#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:52:28.15#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:52:28.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:52:28.15#ibcon#*before write, iclass 40, count 0 2006.211.07:52:28.15#ibcon#enter sib2, iclass 40, count 0 2006.211.07:52:28.15#ibcon#flushed, iclass 40, count 0 2006.211.07:52:28.15#ibcon#about to write, iclass 40, count 0 2006.211.07:52:28.15#ibcon#wrote, iclass 40, count 0 2006.211.07:52:28.15#ibcon#about to read 3, iclass 40, count 0 2006.211.07:52:28.19#ibcon#read 3, iclass 40, count 0 2006.211.07:52:28.19#ibcon#about to read 4, iclass 40, count 0 2006.211.07:52:28.19#ibcon#read 4, iclass 40, count 0 2006.211.07:52:28.19#ibcon#about to read 5, iclass 40, count 0 2006.211.07:52:28.19#ibcon#read 5, iclass 40, count 0 2006.211.07:52:28.19#ibcon#about to read 6, iclass 40, count 0 2006.211.07:52:28.19#ibcon#read 6, iclass 40, count 0 2006.211.07:52:28.19#ibcon#end of sib2, iclass 40, count 0 2006.211.07:52:28.19#ibcon#*after write, iclass 40, count 0 2006.211.07:52:28.19#ibcon#*before return 0, iclass 40, count 0 2006.211.07:52:28.19#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:28.19#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:28.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:52:28.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:52:28.19$vc4f8/va=3,6 2006.211.07:52:28.19#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:52:28.19#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:52:28.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:28.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:28.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:28.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:28.25#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:52:28.25#ibcon#first serial, iclass 4, count 2 2006.211.07:52:28.25#ibcon#enter sib2, iclass 4, count 2 2006.211.07:52:28.25#ibcon#flushed, iclass 4, count 2 2006.211.07:52:28.25#ibcon#about to write, iclass 4, count 2 2006.211.07:52:28.25#ibcon#wrote, iclass 4, count 2 2006.211.07:52:28.25#ibcon#about to read 3, iclass 4, count 2 2006.211.07:52:28.27#ibcon#read 3, iclass 4, count 2 2006.211.07:52:28.27#ibcon#about to read 4, iclass 4, count 2 2006.211.07:52:28.27#ibcon#read 4, iclass 4, count 2 2006.211.07:52:28.27#ibcon#about to read 5, iclass 4, count 2 2006.211.07:52:28.27#ibcon#read 5, iclass 4, count 2 2006.211.07:52:28.27#ibcon#about to read 6, iclass 4, count 2 2006.211.07:52:28.27#ibcon#read 6, iclass 4, count 2 2006.211.07:52:28.27#ibcon#end of sib2, iclass 4, count 2 2006.211.07:52:28.27#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:52:28.27#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:52:28.27#ibcon#[25=AT03-06\r\n] 2006.211.07:52:28.27#ibcon#*before write, iclass 4, count 2 2006.211.07:52:28.27#ibcon#enter sib2, iclass 4, count 2 2006.211.07:52:28.27#ibcon#flushed, iclass 4, count 2 2006.211.07:52:28.27#ibcon#about to write, iclass 4, count 2 2006.211.07:52:28.27#ibcon#wrote, iclass 4, count 2 2006.211.07:52:28.27#ibcon#about to read 3, iclass 4, count 2 2006.211.07:52:28.30#ibcon#read 3, iclass 4, count 2 2006.211.07:52:28.30#ibcon#about to read 4, iclass 4, count 2 2006.211.07:52:28.30#ibcon#read 4, iclass 4, count 2 2006.211.07:52:28.30#ibcon#about to read 5, iclass 4, count 2 2006.211.07:52:28.30#ibcon#read 5, iclass 4, count 2 2006.211.07:52:28.30#ibcon#about to read 6, iclass 4, count 2 2006.211.07:52:28.30#ibcon#read 6, iclass 4, count 2 2006.211.07:52:28.30#ibcon#end of sib2, iclass 4, count 2 2006.211.07:52:28.30#ibcon#*after write, iclass 4, count 2 2006.211.07:52:28.30#ibcon#*before return 0, iclass 4, count 2 2006.211.07:52:28.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:28.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:28.30#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:52:28.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:28.30#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:28.42#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:28.42#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:28.42#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:52:28.42#ibcon#first serial, iclass 4, count 0 2006.211.07:52:28.42#ibcon#enter sib2, iclass 4, count 0 2006.211.07:52:28.42#ibcon#flushed, iclass 4, count 0 2006.211.07:52:28.42#ibcon#about to write, iclass 4, count 0 2006.211.07:52:28.42#ibcon#wrote, iclass 4, count 0 2006.211.07:52:28.42#ibcon#about to read 3, iclass 4, count 0 2006.211.07:52:28.44#ibcon#read 3, iclass 4, count 0 2006.211.07:52:28.44#ibcon#about to read 4, iclass 4, count 0 2006.211.07:52:28.44#ibcon#read 4, iclass 4, count 0 2006.211.07:52:28.44#ibcon#about to read 5, iclass 4, count 0 2006.211.07:52:28.44#ibcon#read 5, iclass 4, count 0 2006.211.07:52:28.44#ibcon#about to read 6, iclass 4, count 0 2006.211.07:52:28.44#ibcon#read 6, iclass 4, count 0 2006.211.07:52:28.44#ibcon#end of sib2, iclass 4, count 0 2006.211.07:52:28.44#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:52:28.44#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:52:28.44#ibcon#[25=USB\r\n] 2006.211.07:52:28.44#ibcon#*before write, iclass 4, count 0 2006.211.07:52:28.44#ibcon#enter sib2, iclass 4, count 0 2006.211.07:52:28.44#ibcon#flushed, iclass 4, count 0 2006.211.07:52:28.44#ibcon#about to write, iclass 4, count 0 2006.211.07:52:28.44#ibcon#wrote, iclass 4, count 0 2006.211.07:52:28.44#ibcon#about to read 3, iclass 4, count 0 2006.211.07:52:28.47#ibcon#read 3, iclass 4, count 0 2006.211.07:52:28.47#ibcon#about to read 4, iclass 4, count 0 2006.211.07:52:28.47#ibcon#read 4, iclass 4, count 0 2006.211.07:52:28.47#ibcon#about to read 5, iclass 4, count 0 2006.211.07:52:28.47#ibcon#read 5, iclass 4, count 0 2006.211.07:52:28.47#ibcon#about to read 6, iclass 4, count 0 2006.211.07:52:28.47#ibcon#read 6, iclass 4, count 0 2006.211.07:52:28.47#ibcon#end of sib2, iclass 4, count 0 2006.211.07:52:28.47#ibcon#*after write, iclass 4, count 0 2006.211.07:52:28.47#ibcon#*before return 0, iclass 4, count 0 2006.211.07:52:28.47#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:28.47#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:28.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:52:28.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:52:28.47$vc4f8/valo=4,832.99 2006.211.07:52:28.47#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:52:28.47#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:52:28.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:28.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:28.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:28.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:28.47#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:52:28.47#ibcon#first serial, iclass 6, count 0 2006.211.07:52:28.47#ibcon#enter sib2, iclass 6, count 0 2006.211.07:52:28.47#ibcon#flushed, iclass 6, count 0 2006.211.07:52:28.47#ibcon#about to write, iclass 6, count 0 2006.211.07:52:28.47#ibcon#wrote, iclass 6, count 0 2006.211.07:52:28.47#ibcon#about to read 3, iclass 6, count 0 2006.211.07:52:28.49#ibcon#read 3, iclass 6, count 0 2006.211.07:52:28.49#ibcon#about to read 4, iclass 6, count 0 2006.211.07:52:28.49#ibcon#read 4, iclass 6, count 0 2006.211.07:52:28.49#ibcon#about to read 5, iclass 6, count 0 2006.211.07:52:28.49#ibcon#read 5, iclass 6, count 0 2006.211.07:52:28.49#ibcon#about to read 6, iclass 6, count 0 2006.211.07:52:28.49#ibcon#read 6, iclass 6, count 0 2006.211.07:52:28.49#ibcon#end of sib2, iclass 6, count 0 2006.211.07:52:28.49#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:52:28.49#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:52:28.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:52:28.49#ibcon#*before write, iclass 6, count 0 2006.211.07:52:28.49#ibcon#enter sib2, iclass 6, count 0 2006.211.07:52:28.49#ibcon#flushed, iclass 6, count 0 2006.211.07:52:28.49#ibcon#about to write, iclass 6, count 0 2006.211.07:52:28.49#ibcon#wrote, iclass 6, count 0 2006.211.07:52:28.49#ibcon#about to read 3, iclass 6, count 0 2006.211.07:52:28.53#ibcon#read 3, iclass 6, count 0 2006.211.07:52:28.53#ibcon#about to read 4, iclass 6, count 0 2006.211.07:52:28.53#ibcon#read 4, iclass 6, count 0 2006.211.07:52:28.53#ibcon#about to read 5, iclass 6, count 0 2006.211.07:52:28.53#ibcon#read 5, iclass 6, count 0 2006.211.07:52:28.53#ibcon#about to read 6, iclass 6, count 0 2006.211.07:52:28.53#ibcon#read 6, iclass 6, count 0 2006.211.07:52:28.53#ibcon#end of sib2, iclass 6, count 0 2006.211.07:52:28.53#ibcon#*after write, iclass 6, count 0 2006.211.07:52:28.53#ibcon#*before return 0, iclass 6, count 0 2006.211.07:52:28.53#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:28.53#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:28.53#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:52:28.53#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:52:28.53$vc4f8/va=4,7 2006.211.07:52:28.53#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:52:28.53#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:52:28.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:28.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:28.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:28.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:28.59#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:52:28.59#ibcon#first serial, iclass 10, count 2 2006.211.07:52:28.59#ibcon#enter sib2, iclass 10, count 2 2006.211.07:52:28.59#ibcon#flushed, iclass 10, count 2 2006.211.07:52:28.59#ibcon#about to write, iclass 10, count 2 2006.211.07:52:28.59#ibcon#wrote, iclass 10, count 2 2006.211.07:52:28.59#ibcon#about to read 3, iclass 10, count 2 2006.211.07:52:28.61#ibcon#read 3, iclass 10, count 2 2006.211.07:52:28.61#ibcon#about to read 4, iclass 10, count 2 2006.211.07:52:28.61#ibcon#read 4, iclass 10, count 2 2006.211.07:52:28.61#ibcon#about to read 5, iclass 10, count 2 2006.211.07:52:28.61#ibcon#read 5, iclass 10, count 2 2006.211.07:52:28.61#ibcon#about to read 6, iclass 10, count 2 2006.211.07:52:28.61#ibcon#read 6, iclass 10, count 2 2006.211.07:52:28.61#ibcon#end of sib2, iclass 10, count 2 2006.211.07:52:28.61#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:52:28.61#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:52:28.61#ibcon#[25=AT04-07\r\n] 2006.211.07:52:28.61#ibcon#*before write, iclass 10, count 2 2006.211.07:52:28.61#ibcon#enter sib2, iclass 10, count 2 2006.211.07:52:28.61#ibcon#flushed, iclass 10, count 2 2006.211.07:52:28.61#ibcon#about to write, iclass 10, count 2 2006.211.07:52:28.61#ibcon#wrote, iclass 10, count 2 2006.211.07:52:28.61#ibcon#about to read 3, iclass 10, count 2 2006.211.07:52:28.64#ibcon#read 3, iclass 10, count 2 2006.211.07:52:28.64#ibcon#about to read 4, iclass 10, count 2 2006.211.07:52:28.64#ibcon#read 4, iclass 10, count 2 2006.211.07:52:28.64#ibcon#about to read 5, iclass 10, count 2 2006.211.07:52:28.64#ibcon#read 5, iclass 10, count 2 2006.211.07:52:28.64#ibcon#about to read 6, iclass 10, count 2 2006.211.07:52:28.64#ibcon#read 6, iclass 10, count 2 2006.211.07:52:28.64#ibcon#end of sib2, iclass 10, count 2 2006.211.07:52:28.64#ibcon#*after write, iclass 10, count 2 2006.211.07:52:28.64#ibcon#*before return 0, iclass 10, count 2 2006.211.07:52:28.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:28.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:28.64#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:52:28.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:28.64#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:28.76#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:28.76#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:28.76#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:52:28.76#ibcon#first serial, iclass 10, count 0 2006.211.07:52:28.76#ibcon#enter sib2, iclass 10, count 0 2006.211.07:52:28.76#ibcon#flushed, iclass 10, count 0 2006.211.07:52:28.76#ibcon#about to write, iclass 10, count 0 2006.211.07:52:28.76#ibcon#wrote, iclass 10, count 0 2006.211.07:52:28.76#ibcon#about to read 3, iclass 10, count 0 2006.211.07:52:28.78#ibcon#read 3, iclass 10, count 0 2006.211.07:52:28.78#ibcon#about to read 4, iclass 10, count 0 2006.211.07:52:28.78#ibcon#read 4, iclass 10, count 0 2006.211.07:52:28.78#ibcon#about to read 5, iclass 10, count 0 2006.211.07:52:28.78#ibcon#read 5, iclass 10, count 0 2006.211.07:52:28.78#ibcon#about to read 6, iclass 10, count 0 2006.211.07:52:28.78#ibcon#read 6, iclass 10, count 0 2006.211.07:52:28.78#ibcon#end of sib2, iclass 10, count 0 2006.211.07:52:28.78#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:52:28.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:52:28.78#ibcon#[25=USB\r\n] 2006.211.07:52:28.78#ibcon#*before write, iclass 10, count 0 2006.211.07:52:28.78#ibcon#enter sib2, iclass 10, count 0 2006.211.07:52:28.78#ibcon#flushed, iclass 10, count 0 2006.211.07:52:28.78#ibcon#about to write, iclass 10, count 0 2006.211.07:52:28.78#ibcon#wrote, iclass 10, count 0 2006.211.07:52:28.78#ibcon#about to read 3, iclass 10, count 0 2006.211.07:52:28.81#ibcon#read 3, iclass 10, count 0 2006.211.07:52:28.81#ibcon#about to read 4, iclass 10, count 0 2006.211.07:52:28.81#ibcon#read 4, iclass 10, count 0 2006.211.07:52:28.81#ibcon#about to read 5, iclass 10, count 0 2006.211.07:52:28.81#ibcon#read 5, iclass 10, count 0 2006.211.07:52:28.81#ibcon#about to read 6, iclass 10, count 0 2006.211.07:52:28.81#ibcon#read 6, iclass 10, count 0 2006.211.07:52:28.81#ibcon#end of sib2, iclass 10, count 0 2006.211.07:52:28.81#ibcon#*after write, iclass 10, count 0 2006.211.07:52:28.81#ibcon#*before return 0, iclass 10, count 0 2006.211.07:52:28.81#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:28.81#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:28.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:52:28.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:52:28.81$vc4f8/valo=5,652.99 2006.211.07:52:28.81#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:52:28.81#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:52:28.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:28.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:28.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:28.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:28.81#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:52:28.81#ibcon#first serial, iclass 12, count 0 2006.211.07:52:28.81#ibcon#enter sib2, iclass 12, count 0 2006.211.07:52:28.81#ibcon#flushed, iclass 12, count 0 2006.211.07:52:28.81#ibcon#about to write, iclass 12, count 0 2006.211.07:52:28.81#ibcon#wrote, iclass 12, count 0 2006.211.07:52:28.81#ibcon#about to read 3, iclass 12, count 0 2006.211.07:52:28.83#ibcon#read 3, iclass 12, count 0 2006.211.07:52:28.83#ibcon#about to read 4, iclass 12, count 0 2006.211.07:52:28.83#ibcon#read 4, iclass 12, count 0 2006.211.07:52:28.83#ibcon#about to read 5, iclass 12, count 0 2006.211.07:52:28.83#ibcon#read 5, iclass 12, count 0 2006.211.07:52:28.83#ibcon#about to read 6, iclass 12, count 0 2006.211.07:52:28.83#ibcon#read 6, iclass 12, count 0 2006.211.07:52:28.83#ibcon#end of sib2, iclass 12, count 0 2006.211.07:52:28.83#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:52:28.83#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:52:28.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:52:28.83#ibcon#*before write, iclass 12, count 0 2006.211.07:52:28.83#ibcon#enter sib2, iclass 12, count 0 2006.211.07:52:28.83#ibcon#flushed, iclass 12, count 0 2006.211.07:52:28.83#ibcon#about to write, iclass 12, count 0 2006.211.07:52:28.83#ibcon#wrote, iclass 12, count 0 2006.211.07:52:28.83#ibcon#about to read 3, iclass 12, count 0 2006.211.07:52:28.87#ibcon#read 3, iclass 12, count 0 2006.211.07:52:28.87#ibcon#about to read 4, iclass 12, count 0 2006.211.07:52:28.87#ibcon#read 4, iclass 12, count 0 2006.211.07:52:28.87#ibcon#about to read 5, iclass 12, count 0 2006.211.07:52:28.87#ibcon#read 5, iclass 12, count 0 2006.211.07:52:28.87#ibcon#about to read 6, iclass 12, count 0 2006.211.07:52:28.87#ibcon#read 6, iclass 12, count 0 2006.211.07:52:28.87#ibcon#end of sib2, iclass 12, count 0 2006.211.07:52:28.87#ibcon#*after write, iclass 12, count 0 2006.211.07:52:28.87#ibcon#*before return 0, iclass 12, count 0 2006.211.07:52:28.87#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:28.87#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:28.87#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:52:28.87#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:52:28.87$vc4f8/va=5,7 2006.211.07:52:28.87#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:52:28.87#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:52:28.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:28.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:28.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:28.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:28.93#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:52:28.93#ibcon#first serial, iclass 14, count 2 2006.211.07:52:28.93#ibcon#enter sib2, iclass 14, count 2 2006.211.07:52:28.93#ibcon#flushed, iclass 14, count 2 2006.211.07:52:28.93#ibcon#about to write, iclass 14, count 2 2006.211.07:52:28.93#ibcon#wrote, iclass 14, count 2 2006.211.07:52:28.93#ibcon#about to read 3, iclass 14, count 2 2006.211.07:52:28.95#ibcon#read 3, iclass 14, count 2 2006.211.07:52:28.95#ibcon#about to read 4, iclass 14, count 2 2006.211.07:52:28.95#ibcon#read 4, iclass 14, count 2 2006.211.07:52:28.95#ibcon#about to read 5, iclass 14, count 2 2006.211.07:52:28.95#ibcon#read 5, iclass 14, count 2 2006.211.07:52:28.95#ibcon#about to read 6, iclass 14, count 2 2006.211.07:52:28.95#ibcon#read 6, iclass 14, count 2 2006.211.07:52:28.95#ibcon#end of sib2, iclass 14, count 2 2006.211.07:52:28.95#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:52:28.95#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:52:28.95#ibcon#[25=AT05-07\r\n] 2006.211.07:52:28.95#ibcon#*before write, iclass 14, count 2 2006.211.07:52:28.95#ibcon#enter sib2, iclass 14, count 2 2006.211.07:52:28.95#ibcon#flushed, iclass 14, count 2 2006.211.07:52:28.95#ibcon#about to write, iclass 14, count 2 2006.211.07:52:28.95#ibcon#wrote, iclass 14, count 2 2006.211.07:52:28.95#ibcon#about to read 3, iclass 14, count 2 2006.211.07:52:28.98#ibcon#read 3, iclass 14, count 2 2006.211.07:52:28.98#ibcon#about to read 4, iclass 14, count 2 2006.211.07:52:28.98#ibcon#read 4, iclass 14, count 2 2006.211.07:52:28.98#ibcon#about to read 5, iclass 14, count 2 2006.211.07:52:28.98#ibcon#read 5, iclass 14, count 2 2006.211.07:52:28.98#ibcon#about to read 6, iclass 14, count 2 2006.211.07:52:28.98#ibcon#read 6, iclass 14, count 2 2006.211.07:52:28.98#ibcon#end of sib2, iclass 14, count 2 2006.211.07:52:28.98#ibcon#*after write, iclass 14, count 2 2006.211.07:52:28.98#ibcon#*before return 0, iclass 14, count 2 2006.211.07:52:28.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:28.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:28.98#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:52:28.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:28.98#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:29.10#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:29.10#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:29.10#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:52:29.10#ibcon#first serial, iclass 14, count 0 2006.211.07:52:29.10#ibcon#enter sib2, iclass 14, count 0 2006.211.07:52:29.10#ibcon#flushed, iclass 14, count 0 2006.211.07:52:29.10#ibcon#about to write, iclass 14, count 0 2006.211.07:52:29.10#ibcon#wrote, iclass 14, count 0 2006.211.07:52:29.10#ibcon#about to read 3, iclass 14, count 0 2006.211.07:52:29.12#ibcon#read 3, iclass 14, count 0 2006.211.07:52:29.12#ibcon#about to read 4, iclass 14, count 0 2006.211.07:52:29.12#ibcon#read 4, iclass 14, count 0 2006.211.07:52:29.12#ibcon#about to read 5, iclass 14, count 0 2006.211.07:52:29.12#ibcon#read 5, iclass 14, count 0 2006.211.07:52:29.12#ibcon#about to read 6, iclass 14, count 0 2006.211.07:52:29.12#ibcon#read 6, iclass 14, count 0 2006.211.07:52:29.12#ibcon#end of sib2, iclass 14, count 0 2006.211.07:52:29.12#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:52:29.12#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:52:29.12#ibcon#[25=USB\r\n] 2006.211.07:52:29.12#ibcon#*before write, iclass 14, count 0 2006.211.07:52:29.12#ibcon#enter sib2, iclass 14, count 0 2006.211.07:52:29.12#ibcon#flushed, iclass 14, count 0 2006.211.07:52:29.12#ibcon#about to write, iclass 14, count 0 2006.211.07:52:29.12#ibcon#wrote, iclass 14, count 0 2006.211.07:52:29.12#ibcon#about to read 3, iclass 14, count 0 2006.211.07:52:29.15#ibcon#read 3, iclass 14, count 0 2006.211.07:52:29.15#ibcon#about to read 4, iclass 14, count 0 2006.211.07:52:29.15#ibcon#read 4, iclass 14, count 0 2006.211.07:52:29.15#ibcon#about to read 5, iclass 14, count 0 2006.211.07:52:29.15#ibcon#read 5, iclass 14, count 0 2006.211.07:52:29.15#ibcon#about to read 6, iclass 14, count 0 2006.211.07:52:29.15#ibcon#read 6, iclass 14, count 0 2006.211.07:52:29.15#ibcon#end of sib2, iclass 14, count 0 2006.211.07:52:29.15#ibcon#*after write, iclass 14, count 0 2006.211.07:52:29.15#ibcon#*before return 0, iclass 14, count 0 2006.211.07:52:29.15#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:29.15#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:29.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:52:29.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:52:29.15$vc4f8/valo=6,772.99 2006.211.07:52:29.15#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:52:29.15#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:52:29.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:29.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:29.15#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:29.15#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:29.15#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:52:29.15#ibcon#first serial, iclass 16, count 0 2006.211.07:52:29.15#ibcon#enter sib2, iclass 16, count 0 2006.211.07:52:29.15#ibcon#flushed, iclass 16, count 0 2006.211.07:52:29.15#ibcon#about to write, iclass 16, count 0 2006.211.07:52:29.15#ibcon#wrote, iclass 16, count 0 2006.211.07:52:29.15#ibcon#about to read 3, iclass 16, count 0 2006.211.07:52:29.17#ibcon#read 3, iclass 16, count 0 2006.211.07:52:29.17#ibcon#about to read 4, iclass 16, count 0 2006.211.07:52:29.17#ibcon#read 4, iclass 16, count 0 2006.211.07:52:29.17#ibcon#about to read 5, iclass 16, count 0 2006.211.07:52:29.17#ibcon#read 5, iclass 16, count 0 2006.211.07:52:29.17#ibcon#about to read 6, iclass 16, count 0 2006.211.07:52:29.17#ibcon#read 6, iclass 16, count 0 2006.211.07:52:29.17#ibcon#end of sib2, iclass 16, count 0 2006.211.07:52:29.17#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:52:29.17#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:52:29.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:52:29.17#ibcon#*before write, iclass 16, count 0 2006.211.07:52:29.17#ibcon#enter sib2, iclass 16, count 0 2006.211.07:52:29.17#ibcon#flushed, iclass 16, count 0 2006.211.07:52:29.17#ibcon#about to write, iclass 16, count 0 2006.211.07:52:29.17#ibcon#wrote, iclass 16, count 0 2006.211.07:52:29.17#ibcon#about to read 3, iclass 16, count 0 2006.211.07:52:29.21#ibcon#read 3, iclass 16, count 0 2006.211.07:52:29.21#ibcon#about to read 4, iclass 16, count 0 2006.211.07:52:29.21#ibcon#read 4, iclass 16, count 0 2006.211.07:52:29.21#ibcon#about to read 5, iclass 16, count 0 2006.211.07:52:29.21#ibcon#read 5, iclass 16, count 0 2006.211.07:52:29.21#ibcon#about to read 6, iclass 16, count 0 2006.211.07:52:29.21#ibcon#read 6, iclass 16, count 0 2006.211.07:52:29.21#ibcon#end of sib2, iclass 16, count 0 2006.211.07:52:29.21#ibcon#*after write, iclass 16, count 0 2006.211.07:52:29.21#ibcon#*before return 0, iclass 16, count 0 2006.211.07:52:29.21#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:29.21#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:29.21#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:52:29.21#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:52:29.21$vc4f8/va=6,6 2006.211.07:52:29.21#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.07:52:29.21#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.07:52:29.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:29.21#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:29.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:29.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:29.27#ibcon#enter wrdev, iclass 18, count 2 2006.211.07:52:29.27#ibcon#first serial, iclass 18, count 2 2006.211.07:52:29.27#ibcon#enter sib2, iclass 18, count 2 2006.211.07:52:29.27#ibcon#flushed, iclass 18, count 2 2006.211.07:52:29.27#ibcon#about to write, iclass 18, count 2 2006.211.07:52:29.27#ibcon#wrote, iclass 18, count 2 2006.211.07:52:29.27#ibcon#about to read 3, iclass 18, count 2 2006.211.07:52:29.29#ibcon#read 3, iclass 18, count 2 2006.211.07:52:29.29#ibcon#about to read 4, iclass 18, count 2 2006.211.07:52:29.29#ibcon#read 4, iclass 18, count 2 2006.211.07:52:29.29#ibcon#about to read 5, iclass 18, count 2 2006.211.07:52:29.29#ibcon#read 5, iclass 18, count 2 2006.211.07:52:29.29#ibcon#about to read 6, iclass 18, count 2 2006.211.07:52:29.29#ibcon#read 6, iclass 18, count 2 2006.211.07:52:29.29#ibcon#end of sib2, iclass 18, count 2 2006.211.07:52:29.29#ibcon#*mode == 0, iclass 18, count 2 2006.211.07:52:29.29#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.07:52:29.29#ibcon#[25=AT06-06\r\n] 2006.211.07:52:29.29#ibcon#*before write, iclass 18, count 2 2006.211.07:52:29.29#ibcon#enter sib2, iclass 18, count 2 2006.211.07:52:29.29#ibcon#flushed, iclass 18, count 2 2006.211.07:52:29.29#ibcon#about to write, iclass 18, count 2 2006.211.07:52:29.29#ibcon#wrote, iclass 18, count 2 2006.211.07:52:29.29#ibcon#about to read 3, iclass 18, count 2 2006.211.07:52:29.32#ibcon#read 3, iclass 18, count 2 2006.211.07:52:29.32#ibcon#about to read 4, iclass 18, count 2 2006.211.07:52:29.32#ibcon#read 4, iclass 18, count 2 2006.211.07:52:29.32#ibcon#about to read 5, iclass 18, count 2 2006.211.07:52:29.32#ibcon#read 5, iclass 18, count 2 2006.211.07:52:29.32#ibcon#about to read 6, iclass 18, count 2 2006.211.07:52:29.32#ibcon#read 6, iclass 18, count 2 2006.211.07:52:29.32#ibcon#end of sib2, iclass 18, count 2 2006.211.07:52:29.32#ibcon#*after write, iclass 18, count 2 2006.211.07:52:29.32#ibcon#*before return 0, iclass 18, count 2 2006.211.07:52:29.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:29.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:29.32#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.07:52:29.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:29.32#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:29.44#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:29.44#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:29.44#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:52:29.44#ibcon#first serial, iclass 18, count 0 2006.211.07:52:29.44#ibcon#enter sib2, iclass 18, count 0 2006.211.07:52:29.44#ibcon#flushed, iclass 18, count 0 2006.211.07:52:29.44#ibcon#about to write, iclass 18, count 0 2006.211.07:52:29.44#ibcon#wrote, iclass 18, count 0 2006.211.07:52:29.44#ibcon#about to read 3, iclass 18, count 0 2006.211.07:52:29.46#ibcon#read 3, iclass 18, count 0 2006.211.07:52:29.46#ibcon#about to read 4, iclass 18, count 0 2006.211.07:52:29.46#ibcon#read 4, iclass 18, count 0 2006.211.07:52:29.46#ibcon#about to read 5, iclass 18, count 0 2006.211.07:52:29.46#ibcon#read 5, iclass 18, count 0 2006.211.07:52:29.46#ibcon#about to read 6, iclass 18, count 0 2006.211.07:52:29.46#ibcon#read 6, iclass 18, count 0 2006.211.07:52:29.46#ibcon#end of sib2, iclass 18, count 0 2006.211.07:52:29.46#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:52:29.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:52:29.46#ibcon#[25=USB\r\n] 2006.211.07:52:29.46#ibcon#*before write, iclass 18, count 0 2006.211.07:52:29.46#ibcon#enter sib2, iclass 18, count 0 2006.211.07:52:29.46#ibcon#flushed, iclass 18, count 0 2006.211.07:52:29.46#ibcon#about to write, iclass 18, count 0 2006.211.07:52:29.46#ibcon#wrote, iclass 18, count 0 2006.211.07:52:29.46#ibcon#about to read 3, iclass 18, count 0 2006.211.07:52:29.49#ibcon#read 3, iclass 18, count 0 2006.211.07:52:29.49#ibcon#about to read 4, iclass 18, count 0 2006.211.07:52:29.49#ibcon#read 4, iclass 18, count 0 2006.211.07:52:29.49#ibcon#about to read 5, iclass 18, count 0 2006.211.07:52:29.49#ibcon#read 5, iclass 18, count 0 2006.211.07:52:29.49#ibcon#about to read 6, iclass 18, count 0 2006.211.07:52:29.49#ibcon#read 6, iclass 18, count 0 2006.211.07:52:29.49#ibcon#end of sib2, iclass 18, count 0 2006.211.07:52:29.49#ibcon#*after write, iclass 18, count 0 2006.211.07:52:29.49#ibcon#*before return 0, iclass 18, count 0 2006.211.07:52:29.49#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:29.49#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:29.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:52:29.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:52:29.49$vc4f8/valo=7,832.99 2006.211.07:52:29.49#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.07:52:29.49#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.07:52:29.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:29.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:29.49#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:29.49#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:29.49#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:52:29.49#ibcon#first serial, iclass 20, count 0 2006.211.07:52:29.49#ibcon#enter sib2, iclass 20, count 0 2006.211.07:52:29.49#ibcon#flushed, iclass 20, count 0 2006.211.07:52:29.49#ibcon#about to write, iclass 20, count 0 2006.211.07:52:29.49#ibcon#wrote, iclass 20, count 0 2006.211.07:52:29.49#ibcon#about to read 3, iclass 20, count 0 2006.211.07:52:29.51#ibcon#read 3, iclass 20, count 0 2006.211.07:52:29.51#ibcon#about to read 4, iclass 20, count 0 2006.211.07:52:29.51#ibcon#read 4, iclass 20, count 0 2006.211.07:52:29.51#ibcon#about to read 5, iclass 20, count 0 2006.211.07:52:29.51#ibcon#read 5, iclass 20, count 0 2006.211.07:52:29.51#ibcon#about to read 6, iclass 20, count 0 2006.211.07:52:29.51#ibcon#read 6, iclass 20, count 0 2006.211.07:52:29.51#ibcon#end of sib2, iclass 20, count 0 2006.211.07:52:29.51#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:52:29.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:52:29.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:52:29.51#ibcon#*before write, iclass 20, count 0 2006.211.07:52:29.51#ibcon#enter sib2, iclass 20, count 0 2006.211.07:52:29.51#ibcon#flushed, iclass 20, count 0 2006.211.07:52:29.51#ibcon#about to write, iclass 20, count 0 2006.211.07:52:29.51#ibcon#wrote, iclass 20, count 0 2006.211.07:52:29.51#ibcon#about to read 3, iclass 20, count 0 2006.211.07:52:29.55#ibcon#read 3, iclass 20, count 0 2006.211.07:52:29.55#ibcon#about to read 4, iclass 20, count 0 2006.211.07:52:29.55#ibcon#read 4, iclass 20, count 0 2006.211.07:52:29.55#ibcon#about to read 5, iclass 20, count 0 2006.211.07:52:29.55#ibcon#read 5, iclass 20, count 0 2006.211.07:52:29.55#ibcon#about to read 6, iclass 20, count 0 2006.211.07:52:29.55#ibcon#read 6, iclass 20, count 0 2006.211.07:52:29.55#ibcon#end of sib2, iclass 20, count 0 2006.211.07:52:29.55#ibcon#*after write, iclass 20, count 0 2006.211.07:52:29.55#ibcon#*before return 0, iclass 20, count 0 2006.211.07:52:29.55#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:29.55#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:29.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:52:29.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:52:29.55$vc4f8/va=7,6 2006.211.07:52:29.55#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.07:52:29.55#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.07:52:29.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:29.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:52:29.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:52:29.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:52:29.61#ibcon#enter wrdev, iclass 22, count 2 2006.211.07:52:29.61#ibcon#first serial, iclass 22, count 2 2006.211.07:52:29.61#ibcon#enter sib2, iclass 22, count 2 2006.211.07:52:29.61#ibcon#flushed, iclass 22, count 2 2006.211.07:52:29.61#ibcon#about to write, iclass 22, count 2 2006.211.07:52:29.61#ibcon#wrote, iclass 22, count 2 2006.211.07:52:29.61#ibcon#about to read 3, iclass 22, count 2 2006.211.07:52:29.63#ibcon#read 3, iclass 22, count 2 2006.211.07:52:29.63#ibcon#about to read 4, iclass 22, count 2 2006.211.07:52:29.63#ibcon#read 4, iclass 22, count 2 2006.211.07:52:29.63#ibcon#about to read 5, iclass 22, count 2 2006.211.07:52:29.63#ibcon#read 5, iclass 22, count 2 2006.211.07:52:29.63#ibcon#about to read 6, iclass 22, count 2 2006.211.07:52:29.63#ibcon#read 6, iclass 22, count 2 2006.211.07:52:29.63#ibcon#end of sib2, iclass 22, count 2 2006.211.07:52:29.63#ibcon#*mode == 0, iclass 22, count 2 2006.211.07:52:29.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.07:52:29.63#ibcon#[25=AT07-06\r\n] 2006.211.07:52:29.63#ibcon#*before write, iclass 22, count 2 2006.211.07:52:29.63#ibcon#enter sib2, iclass 22, count 2 2006.211.07:52:29.63#ibcon#flushed, iclass 22, count 2 2006.211.07:52:29.63#ibcon#about to write, iclass 22, count 2 2006.211.07:52:29.63#ibcon#wrote, iclass 22, count 2 2006.211.07:52:29.63#ibcon#about to read 3, iclass 22, count 2 2006.211.07:52:29.66#ibcon#read 3, iclass 22, count 2 2006.211.07:52:29.66#ibcon#about to read 4, iclass 22, count 2 2006.211.07:52:29.66#ibcon#read 4, iclass 22, count 2 2006.211.07:52:29.66#ibcon#about to read 5, iclass 22, count 2 2006.211.07:52:29.66#ibcon#read 5, iclass 22, count 2 2006.211.07:52:29.66#ibcon#about to read 6, iclass 22, count 2 2006.211.07:52:29.66#ibcon#read 6, iclass 22, count 2 2006.211.07:52:29.66#ibcon#end of sib2, iclass 22, count 2 2006.211.07:52:29.66#ibcon#*after write, iclass 22, count 2 2006.211.07:52:29.66#ibcon#*before return 0, iclass 22, count 2 2006.211.07:52:29.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:52:29.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:52:29.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.07:52:29.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:29.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:52:29.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:52:29.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:52:29.78#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:52:29.78#ibcon#first serial, iclass 22, count 0 2006.211.07:52:29.78#ibcon#enter sib2, iclass 22, count 0 2006.211.07:52:29.78#ibcon#flushed, iclass 22, count 0 2006.211.07:52:29.78#ibcon#about to write, iclass 22, count 0 2006.211.07:52:29.78#ibcon#wrote, iclass 22, count 0 2006.211.07:52:29.78#ibcon#about to read 3, iclass 22, count 0 2006.211.07:52:29.80#ibcon#read 3, iclass 22, count 0 2006.211.07:52:29.80#ibcon#about to read 4, iclass 22, count 0 2006.211.07:52:29.80#ibcon#read 4, iclass 22, count 0 2006.211.07:52:29.80#ibcon#about to read 5, iclass 22, count 0 2006.211.07:52:29.80#ibcon#read 5, iclass 22, count 0 2006.211.07:52:29.80#ibcon#about to read 6, iclass 22, count 0 2006.211.07:52:29.80#ibcon#read 6, iclass 22, count 0 2006.211.07:52:29.80#ibcon#end of sib2, iclass 22, count 0 2006.211.07:52:29.80#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:52:29.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:52:29.80#ibcon#[25=USB\r\n] 2006.211.07:52:29.80#ibcon#*before write, iclass 22, count 0 2006.211.07:52:29.80#ibcon#enter sib2, iclass 22, count 0 2006.211.07:52:29.80#ibcon#flushed, iclass 22, count 0 2006.211.07:52:29.80#ibcon#about to write, iclass 22, count 0 2006.211.07:52:29.80#ibcon#wrote, iclass 22, count 0 2006.211.07:52:29.80#ibcon#about to read 3, iclass 22, count 0 2006.211.07:52:29.83#ibcon#read 3, iclass 22, count 0 2006.211.07:52:29.83#ibcon#about to read 4, iclass 22, count 0 2006.211.07:52:29.83#ibcon#read 4, iclass 22, count 0 2006.211.07:52:29.83#ibcon#about to read 5, iclass 22, count 0 2006.211.07:52:29.83#ibcon#read 5, iclass 22, count 0 2006.211.07:52:29.83#ibcon#about to read 6, iclass 22, count 0 2006.211.07:52:29.83#ibcon#read 6, iclass 22, count 0 2006.211.07:52:29.83#ibcon#end of sib2, iclass 22, count 0 2006.211.07:52:29.83#ibcon#*after write, iclass 22, count 0 2006.211.07:52:29.83#ibcon#*before return 0, iclass 22, count 0 2006.211.07:52:29.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:52:29.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:52:29.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:52:29.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:52:29.83$vc4f8/valo=8,852.99 2006.211.07:52:29.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.07:52:29.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.07:52:29.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:29.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:52:29.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:52:29.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:52:29.83#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:52:29.83#ibcon#first serial, iclass 24, count 0 2006.211.07:52:29.83#ibcon#enter sib2, iclass 24, count 0 2006.211.07:52:29.83#ibcon#flushed, iclass 24, count 0 2006.211.07:52:29.83#ibcon#about to write, iclass 24, count 0 2006.211.07:52:29.83#ibcon#wrote, iclass 24, count 0 2006.211.07:52:29.83#ibcon#about to read 3, iclass 24, count 0 2006.211.07:52:29.85#ibcon#read 3, iclass 24, count 0 2006.211.07:52:29.85#ibcon#about to read 4, iclass 24, count 0 2006.211.07:52:29.85#ibcon#read 4, iclass 24, count 0 2006.211.07:52:29.85#ibcon#about to read 5, iclass 24, count 0 2006.211.07:52:29.85#ibcon#read 5, iclass 24, count 0 2006.211.07:52:29.85#ibcon#about to read 6, iclass 24, count 0 2006.211.07:52:29.85#ibcon#read 6, iclass 24, count 0 2006.211.07:52:29.85#ibcon#end of sib2, iclass 24, count 0 2006.211.07:52:29.85#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:52:29.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:52:29.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:52:29.85#ibcon#*before write, iclass 24, count 0 2006.211.07:52:29.85#ibcon#enter sib2, iclass 24, count 0 2006.211.07:52:29.85#ibcon#flushed, iclass 24, count 0 2006.211.07:52:29.85#ibcon#about to write, iclass 24, count 0 2006.211.07:52:29.85#ibcon#wrote, iclass 24, count 0 2006.211.07:52:29.85#ibcon#about to read 3, iclass 24, count 0 2006.211.07:52:29.89#ibcon#read 3, iclass 24, count 0 2006.211.07:52:29.89#ibcon#about to read 4, iclass 24, count 0 2006.211.07:52:29.89#ibcon#read 4, iclass 24, count 0 2006.211.07:52:29.89#ibcon#about to read 5, iclass 24, count 0 2006.211.07:52:29.89#ibcon#read 5, iclass 24, count 0 2006.211.07:52:29.89#ibcon#about to read 6, iclass 24, count 0 2006.211.07:52:29.89#ibcon#read 6, iclass 24, count 0 2006.211.07:52:29.89#ibcon#end of sib2, iclass 24, count 0 2006.211.07:52:29.89#ibcon#*after write, iclass 24, count 0 2006.211.07:52:29.89#ibcon#*before return 0, iclass 24, count 0 2006.211.07:52:29.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:52:29.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:52:29.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:52:29.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:52:29.89$vc4f8/va=8,7 2006.211.07:52:29.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.07:52:29.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.07:52:29.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:29.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:52:29.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:52:29.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:52:29.95#ibcon#enter wrdev, iclass 26, count 2 2006.211.07:52:29.95#ibcon#first serial, iclass 26, count 2 2006.211.07:52:29.95#ibcon#enter sib2, iclass 26, count 2 2006.211.07:52:29.95#ibcon#flushed, iclass 26, count 2 2006.211.07:52:29.95#ibcon#about to write, iclass 26, count 2 2006.211.07:52:29.95#ibcon#wrote, iclass 26, count 2 2006.211.07:52:29.95#ibcon#about to read 3, iclass 26, count 2 2006.211.07:52:29.97#ibcon#read 3, iclass 26, count 2 2006.211.07:52:29.97#ibcon#about to read 4, iclass 26, count 2 2006.211.07:52:29.97#ibcon#read 4, iclass 26, count 2 2006.211.07:52:29.97#ibcon#about to read 5, iclass 26, count 2 2006.211.07:52:29.97#ibcon#read 5, iclass 26, count 2 2006.211.07:52:29.97#ibcon#about to read 6, iclass 26, count 2 2006.211.07:52:29.97#ibcon#read 6, iclass 26, count 2 2006.211.07:52:29.97#ibcon#end of sib2, iclass 26, count 2 2006.211.07:52:29.97#ibcon#*mode == 0, iclass 26, count 2 2006.211.07:52:29.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.07:52:29.97#ibcon#[25=AT08-07\r\n] 2006.211.07:52:29.97#ibcon#*before write, iclass 26, count 2 2006.211.07:52:29.97#ibcon#enter sib2, iclass 26, count 2 2006.211.07:52:29.97#ibcon#flushed, iclass 26, count 2 2006.211.07:52:29.97#ibcon#about to write, iclass 26, count 2 2006.211.07:52:29.97#ibcon#wrote, iclass 26, count 2 2006.211.07:52:29.97#ibcon#about to read 3, iclass 26, count 2 2006.211.07:52:30.00#ibcon#read 3, iclass 26, count 2 2006.211.07:52:30.00#ibcon#about to read 4, iclass 26, count 2 2006.211.07:52:30.00#ibcon#read 4, iclass 26, count 2 2006.211.07:52:30.00#ibcon#about to read 5, iclass 26, count 2 2006.211.07:52:30.00#ibcon#read 5, iclass 26, count 2 2006.211.07:52:30.00#ibcon#about to read 6, iclass 26, count 2 2006.211.07:52:30.00#ibcon#read 6, iclass 26, count 2 2006.211.07:52:30.00#ibcon#end of sib2, iclass 26, count 2 2006.211.07:52:30.00#ibcon#*after write, iclass 26, count 2 2006.211.07:52:30.00#ibcon#*before return 0, iclass 26, count 2 2006.211.07:52:30.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:52:30.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:52:30.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.07:52:30.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:30.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:52:30.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:52:30.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:52:30.12#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:52:30.12#ibcon#first serial, iclass 26, count 0 2006.211.07:52:30.12#ibcon#enter sib2, iclass 26, count 0 2006.211.07:52:30.12#ibcon#flushed, iclass 26, count 0 2006.211.07:52:30.12#ibcon#about to write, iclass 26, count 0 2006.211.07:52:30.12#ibcon#wrote, iclass 26, count 0 2006.211.07:52:30.12#ibcon#about to read 3, iclass 26, count 0 2006.211.07:52:30.14#ibcon#read 3, iclass 26, count 0 2006.211.07:52:30.14#ibcon#about to read 4, iclass 26, count 0 2006.211.07:52:30.14#ibcon#read 4, iclass 26, count 0 2006.211.07:52:30.14#ibcon#about to read 5, iclass 26, count 0 2006.211.07:52:30.14#ibcon#read 5, iclass 26, count 0 2006.211.07:52:30.14#ibcon#about to read 6, iclass 26, count 0 2006.211.07:52:30.14#ibcon#read 6, iclass 26, count 0 2006.211.07:52:30.14#ibcon#end of sib2, iclass 26, count 0 2006.211.07:52:30.14#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:52:30.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:52:30.14#ibcon#[25=USB\r\n] 2006.211.07:52:30.14#ibcon#*before write, iclass 26, count 0 2006.211.07:52:30.14#ibcon#enter sib2, iclass 26, count 0 2006.211.07:52:30.14#ibcon#flushed, iclass 26, count 0 2006.211.07:52:30.14#ibcon#about to write, iclass 26, count 0 2006.211.07:52:30.14#ibcon#wrote, iclass 26, count 0 2006.211.07:52:30.14#ibcon#about to read 3, iclass 26, count 0 2006.211.07:52:30.17#ibcon#read 3, iclass 26, count 0 2006.211.07:52:30.17#ibcon#about to read 4, iclass 26, count 0 2006.211.07:52:30.17#ibcon#read 4, iclass 26, count 0 2006.211.07:52:30.17#ibcon#about to read 5, iclass 26, count 0 2006.211.07:52:30.17#ibcon#read 5, iclass 26, count 0 2006.211.07:52:30.17#ibcon#about to read 6, iclass 26, count 0 2006.211.07:52:30.17#ibcon#read 6, iclass 26, count 0 2006.211.07:52:30.17#ibcon#end of sib2, iclass 26, count 0 2006.211.07:52:30.17#ibcon#*after write, iclass 26, count 0 2006.211.07:52:30.17#ibcon#*before return 0, iclass 26, count 0 2006.211.07:52:30.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:52:30.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:52:30.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:52:30.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:52:30.17$vc4f8/vblo=1,632.99 2006.211.07:52:30.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.07:52:30.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.07:52:30.17#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:30.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:52:30.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:52:30.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:52:30.17#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:52:30.17#ibcon#first serial, iclass 28, count 0 2006.211.07:52:30.17#ibcon#enter sib2, iclass 28, count 0 2006.211.07:52:30.17#ibcon#flushed, iclass 28, count 0 2006.211.07:52:30.17#ibcon#about to write, iclass 28, count 0 2006.211.07:52:30.17#ibcon#wrote, iclass 28, count 0 2006.211.07:52:30.17#ibcon#about to read 3, iclass 28, count 0 2006.211.07:52:30.19#ibcon#read 3, iclass 28, count 0 2006.211.07:52:30.19#ibcon#about to read 4, iclass 28, count 0 2006.211.07:52:30.19#ibcon#read 4, iclass 28, count 0 2006.211.07:52:30.19#ibcon#about to read 5, iclass 28, count 0 2006.211.07:52:30.19#ibcon#read 5, iclass 28, count 0 2006.211.07:52:30.19#ibcon#about to read 6, iclass 28, count 0 2006.211.07:52:30.19#ibcon#read 6, iclass 28, count 0 2006.211.07:52:30.19#ibcon#end of sib2, iclass 28, count 0 2006.211.07:52:30.19#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:52:30.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:52:30.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:52:30.19#ibcon#*before write, iclass 28, count 0 2006.211.07:52:30.19#ibcon#enter sib2, iclass 28, count 0 2006.211.07:52:30.19#ibcon#flushed, iclass 28, count 0 2006.211.07:52:30.19#ibcon#about to write, iclass 28, count 0 2006.211.07:52:30.19#ibcon#wrote, iclass 28, count 0 2006.211.07:52:30.19#ibcon#about to read 3, iclass 28, count 0 2006.211.07:52:30.23#ibcon#read 3, iclass 28, count 0 2006.211.07:52:30.23#ibcon#about to read 4, iclass 28, count 0 2006.211.07:52:30.23#ibcon#read 4, iclass 28, count 0 2006.211.07:52:30.23#ibcon#about to read 5, iclass 28, count 0 2006.211.07:52:30.23#ibcon#read 5, iclass 28, count 0 2006.211.07:52:30.23#ibcon#about to read 6, iclass 28, count 0 2006.211.07:52:30.23#ibcon#read 6, iclass 28, count 0 2006.211.07:52:30.23#ibcon#end of sib2, iclass 28, count 0 2006.211.07:52:30.23#ibcon#*after write, iclass 28, count 0 2006.211.07:52:30.23#ibcon#*before return 0, iclass 28, count 0 2006.211.07:52:30.23#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:52:30.23#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:52:30.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:52:30.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:52:30.23$vc4f8/vb=1,4 2006.211.07:52:30.23#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.07:52:30.23#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.07:52:30.23#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:30.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:52:30.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:52:30.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:52:30.23#ibcon#enter wrdev, iclass 30, count 2 2006.211.07:52:30.23#ibcon#first serial, iclass 30, count 2 2006.211.07:52:30.23#ibcon#enter sib2, iclass 30, count 2 2006.211.07:52:30.23#ibcon#flushed, iclass 30, count 2 2006.211.07:52:30.23#ibcon#about to write, iclass 30, count 2 2006.211.07:52:30.23#ibcon#wrote, iclass 30, count 2 2006.211.07:52:30.23#ibcon#about to read 3, iclass 30, count 2 2006.211.07:52:30.25#ibcon#read 3, iclass 30, count 2 2006.211.07:52:30.25#ibcon#about to read 4, iclass 30, count 2 2006.211.07:52:30.25#ibcon#read 4, iclass 30, count 2 2006.211.07:52:30.25#ibcon#about to read 5, iclass 30, count 2 2006.211.07:52:30.25#ibcon#read 5, iclass 30, count 2 2006.211.07:52:30.25#ibcon#about to read 6, iclass 30, count 2 2006.211.07:52:30.25#ibcon#read 6, iclass 30, count 2 2006.211.07:52:30.25#ibcon#end of sib2, iclass 30, count 2 2006.211.07:52:30.25#ibcon#*mode == 0, iclass 30, count 2 2006.211.07:52:30.25#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.07:52:30.25#ibcon#[27=AT01-04\r\n] 2006.211.07:52:30.25#ibcon#*before write, iclass 30, count 2 2006.211.07:52:30.25#ibcon#enter sib2, iclass 30, count 2 2006.211.07:52:30.25#ibcon#flushed, iclass 30, count 2 2006.211.07:52:30.25#ibcon#about to write, iclass 30, count 2 2006.211.07:52:30.25#ibcon#wrote, iclass 30, count 2 2006.211.07:52:30.25#ibcon#about to read 3, iclass 30, count 2 2006.211.07:52:30.28#ibcon#read 3, iclass 30, count 2 2006.211.07:52:30.28#ibcon#about to read 4, iclass 30, count 2 2006.211.07:52:30.28#ibcon#read 4, iclass 30, count 2 2006.211.07:52:30.28#ibcon#about to read 5, iclass 30, count 2 2006.211.07:52:30.28#ibcon#read 5, iclass 30, count 2 2006.211.07:52:30.28#ibcon#about to read 6, iclass 30, count 2 2006.211.07:52:30.28#ibcon#read 6, iclass 30, count 2 2006.211.07:52:30.28#ibcon#end of sib2, iclass 30, count 2 2006.211.07:52:30.28#ibcon#*after write, iclass 30, count 2 2006.211.07:52:30.28#ibcon#*before return 0, iclass 30, count 2 2006.211.07:52:30.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:52:30.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:52:30.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.07:52:30.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:30.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:52:30.40#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:52:30.40#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:52:30.40#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:52:30.40#ibcon#first serial, iclass 30, count 0 2006.211.07:52:30.40#ibcon#enter sib2, iclass 30, count 0 2006.211.07:52:30.40#ibcon#flushed, iclass 30, count 0 2006.211.07:52:30.40#ibcon#about to write, iclass 30, count 0 2006.211.07:52:30.40#ibcon#wrote, iclass 30, count 0 2006.211.07:52:30.40#ibcon#about to read 3, iclass 30, count 0 2006.211.07:52:30.42#ibcon#read 3, iclass 30, count 0 2006.211.07:52:30.42#ibcon#about to read 4, iclass 30, count 0 2006.211.07:52:30.42#ibcon#read 4, iclass 30, count 0 2006.211.07:52:30.42#ibcon#about to read 5, iclass 30, count 0 2006.211.07:52:30.42#ibcon#read 5, iclass 30, count 0 2006.211.07:52:30.42#ibcon#about to read 6, iclass 30, count 0 2006.211.07:52:30.42#ibcon#read 6, iclass 30, count 0 2006.211.07:52:30.42#ibcon#end of sib2, iclass 30, count 0 2006.211.07:52:30.42#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:52:30.42#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:52:30.42#ibcon#[27=USB\r\n] 2006.211.07:52:30.42#ibcon#*before write, iclass 30, count 0 2006.211.07:52:30.42#ibcon#enter sib2, iclass 30, count 0 2006.211.07:52:30.42#ibcon#flushed, iclass 30, count 0 2006.211.07:52:30.42#ibcon#about to write, iclass 30, count 0 2006.211.07:52:30.42#ibcon#wrote, iclass 30, count 0 2006.211.07:52:30.42#ibcon#about to read 3, iclass 30, count 0 2006.211.07:52:30.45#ibcon#read 3, iclass 30, count 0 2006.211.07:52:30.45#ibcon#about to read 4, iclass 30, count 0 2006.211.07:52:30.45#ibcon#read 4, iclass 30, count 0 2006.211.07:52:30.45#ibcon#about to read 5, iclass 30, count 0 2006.211.07:52:30.45#ibcon#read 5, iclass 30, count 0 2006.211.07:52:30.45#ibcon#about to read 6, iclass 30, count 0 2006.211.07:52:30.45#ibcon#read 6, iclass 30, count 0 2006.211.07:52:30.45#ibcon#end of sib2, iclass 30, count 0 2006.211.07:52:30.45#ibcon#*after write, iclass 30, count 0 2006.211.07:52:30.45#ibcon#*before return 0, iclass 30, count 0 2006.211.07:52:30.45#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:52:30.45#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:52:30.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:52:30.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:52:30.45$vc4f8/vblo=2,640.99 2006.211.07:52:30.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:52:30.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:52:30.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:30.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:30.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:30.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:30.45#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:52:30.45#ibcon#first serial, iclass 32, count 0 2006.211.07:52:30.45#ibcon#enter sib2, iclass 32, count 0 2006.211.07:52:30.45#ibcon#flushed, iclass 32, count 0 2006.211.07:52:30.45#ibcon#about to write, iclass 32, count 0 2006.211.07:52:30.45#ibcon#wrote, iclass 32, count 0 2006.211.07:52:30.45#ibcon#about to read 3, iclass 32, count 0 2006.211.07:52:30.47#ibcon#read 3, iclass 32, count 0 2006.211.07:52:30.47#ibcon#about to read 4, iclass 32, count 0 2006.211.07:52:30.47#ibcon#read 4, iclass 32, count 0 2006.211.07:52:30.47#ibcon#about to read 5, iclass 32, count 0 2006.211.07:52:30.47#ibcon#read 5, iclass 32, count 0 2006.211.07:52:30.47#ibcon#about to read 6, iclass 32, count 0 2006.211.07:52:30.47#ibcon#read 6, iclass 32, count 0 2006.211.07:52:30.47#ibcon#end of sib2, iclass 32, count 0 2006.211.07:52:30.47#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:52:30.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:52:30.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:52:30.47#ibcon#*before write, iclass 32, count 0 2006.211.07:52:30.47#ibcon#enter sib2, iclass 32, count 0 2006.211.07:52:30.47#ibcon#flushed, iclass 32, count 0 2006.211.07:52:30.47#ibcon#about to write, iclass 32, count 0 2006.211.07:52:30.47#ibcon#wrote, iclass 32, count 0 2006.211.07:52:30.47#ibcon#about to read 3, iclass 32, count 0 2006.211.07:52:30.51#ibcon#read 3, iclass 32, count 0 2006.211.07:52:30.51#ibcon#about to read 4, iclass 32, count 0 2006.211.07:52:30.51#ibcon#read 4, iclass 32, count 0 2006.211.07:52:30.51#ibcon#about to read 5, iclass 32, count 0 2006.211.07:52:30.51#ibcon#read 5, iclass 32, count 0 2006.211.07:52:30.51#ibcon#about to read 6, iclass 32, count 0 2006.211.07:52:30.51#ibcon#read 6, iclass 32, count 0 2006.211.07:52:30.51#ibcon#end of sib2, iclass 32, count 0 2006.211.07:52:30.51#ibcon#*after write, iclass 32, count 0 2006.211.07:52:30.51#ibcon#*before return 0, iclass 32, count 0 2006.211.07:52:30.51#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:30.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:52:30.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:52:30.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:52:30.51$vc4f8/vb=2,4 2006.211.07:52:30.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:52:30.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:52:30.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:30.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:30.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:30.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:30.57#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:52:30.57#ibcon#first serial, iclass 34, count 2 2006.211.07:52:30.57#ibcon#enter sib2, iclass 34, count 2 2006.211.07:52:30.57#ibcon#flushed, iclass 34, count 2 2006.211.07:52:30.57#ibcon#about to write, iclass 34, count 2 2006.211.07:52:30.57#ibcon#wrote, iclass 34, count 2 2006.211.07:52:30.57#ibcon#about to read 3, iclass 34, count 2 2006.211.07:52:30.59#ibcon#read 3, iclass 34, count 2 2006.211.07:52:30.59#ibcon#about to read 4, iclass 34, count 2 2006.211.07:52:30.59#ibcon#read 4, iclass 34, count 2 2006.211.07:52:30.59#ibcon#about to read 5, iclass 34, count 2 2006.211.07:52:30.59#ibcon#read 5, iclass 34, count 2 2006.211.07:52:30.59#ibcon#about to read 6, iclass 34, count 2 2006.211.07:52:30.59#ibcon#read 6, iclass 34, count 2 2006.211.07:52:30.59#ibcon#end of sib2, iclass 34, count 2 2006.211.07:52:30.59#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:52:30.59#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:52:30.59#ibcon#[27=AT02-04\r\n] 2006.211.07:52:30.59#ibcon#*before write, iclass 34, count 2 2006.211.07:52:30.59#ibcon#enter sib2, iclass 34, count 2 2006.211.07:52:30.59#ibcon#flushed, iclass 34, count 2 2006.211.07:52:30.59#ibcon#about to write, iclass 34, count 2 2006.211.07:52:30.59#ibcon#wrote, iclass 34, count 2 2006.211.07:52:30.59#ibcon#about to read 3, iclass 34, count 2 2006.211.07:52:30.62#ibcon#read 3, iclass 34, count 2 2006.211.07:52:30.62#ibcon#about to read 4, iclass 34, count 2 2006.211.07:52:30.62#ibcon#read 4, iclass 34, count 2 2006.211.07:52:30.62#ibcon#about to read 5, iclass 34, count 2 2006.211.07:52:30.62#ibcon#read 5, iclass 34, count 2 2006.211.07:52:30.62#ibcon#about to read 6, iclass 34, count 2 2006.211.07:52:30.62#ibcon#read 6, iclass 34, count 2 2006.211.07:52:30.62#ibcon#end of sib2, iclass 34, count 2 2006.211.07:52:30.62#ibcon#*after write, iclass 34, count 2 2006.211.07:52:30.62#ibcon#*before return 0, iclass 34, count 2 2006.211.07:52:30.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:30.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:52:30.62#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:52:30.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:30.62#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:30.72#abcon#<5=/04 3.9 8.0 24.93 771010.1\r\n> 2006.211.07:52:30.74#abcon#{5=INTERFACE CLEAR} 2006.211.07:52:30.74#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:30.74#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:30.74#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:52:30.74#ibcon#first serial, iclass 34, count 0 2006.211.07:52:30.74#ibcon#enter sib2, iclass 34, count 0 2006.211.07:52:30.74#ibcon#flushed, iclass 34, count 0 2006.211.07:52:30.74#ibcon#about to write, iclass 34, count 0 2006.211.07:52:30.74#ibcon#wrote, iclass 34, count 0 2006.211.07:52:30.74#ibcon#about to read 3, iclass 34, count 0 2006.211.07:52:30.76#ibcon#read 3, iclass 34, count 0 2006.211.07:52:30.76#ibcon#about to read 4, iclass 34, count 0 2006.211.07:52:30.76#ibcon#read 4, iclass 34, count 0 2006.211.07:52:30.76#ibcon#about to read 5, iclass 34, count 0 2006.211.07:52:30.76#ibcon#read 5, iclass 34, count 0 2006.211.07:52:30.76#ibcon#about to read 6, iclass 34, count 0 2006.211.07:52:30.76#ibcon#read 6, iclass 34, count 0 2006.211.07:52:30.76#ibcon#end of sib2, iclass 34, count 0 2006.211.07:52:30.76#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:52:30.76#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:52:30.76#ibcon#[27=USB\r\n] 2006.211.07:52:30.76#ibcon#*before write, iclass 34, count 0 2006.211.07:52:30.76#ibcon#enter sib2, iclass 34, count 0 2006.211.07:52:30.76#ibcon#flushed, iclass 34, count 0 2006.211.07:52:30.76#ibcon#about to write, iclass 34, count 0 2006.211.07:52:30.76#ibcon#wrote, iclass 34, count 0 2006.211.07:52:30.76#ibcon#about to read 3, iclass 34, count 0 2006.211.07:52:30.79#ibcon#read 3, iclass 34, count 0 2006.211.07:52:30.79#ibcon#about to read 4, iclass 34, count 0 2006.211.07:52:30.79#ibcon#read 4, iclass 34, count 0 2006.211.07:52:30.79#ibcon#about to read 5, iclass 34, count 0 2006.211.07:52:30.79#ibcon#read 5, iclass 34, count 0 2006.211.07:52:30.79#ibcon#about to read 6, iclass 34, count 0 2006.211.07:52:30.79#ibcon#read 6, iclass 34, count 0 2006.211.07:52:30.79#ibcon#end of sib2, iclass 34, count 0 2006.211.07:52:30.79#ibcon#*after write, iclass 34, count 0 2006.211.07:52:30.79#ibcon#*before return 0, iclass 34, count 0 2006.211.07:52:30.79#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:30.79#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:52:30.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:52:30.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:52:30.79$vc4f8/vblo=3,656.99 2006.211.07:52:30.79#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:52:30.79#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:52:30.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:30.79#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:30.79#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:30.79#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:30.79#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:52:30.79#ibcon#first serial, iclass 40, count 0 2006.211.07:52:30.79#ibcon#enter sib2, iclass 40, count 0 2006.211.07:52:30.79#ibcon#flushed, iclass 40, count 0 2006.211.07:52:30.79#ibcon#about to write, iclass 40, count 0 2006.211.07:52:30.79#ibcon#wrote, iclass 40, count 0 2006.211.07:52:30.79#ibcon#about to read 3, iclass 40, count 0 2006.211.07:52:30.80#abcon#[5=S1D000X0/0*\r\n] 2006.211.07:52:30.81#ibcon#read 3, iclass 40, count 0 2006.211.07:52:30.81#ibcon#about to read 4, iclass 40, count 0 2006.211.07:52:30.81#ibcon#read 4, iclass 40, count 0 2006.211.07:52:30.81#ibcon#about to read 5, iclass 40, count 0 2006.211.07:52:30.81#ibcon#read 5, iclass 40, count 0 2006.211.07:52:30.81#ibcon#about to read 6, iclass 40, count 0 2006.211.07:52:30.81#ibcon#read 6, iclass 40, count 0 2006.211.07:52:30.81#ibcon#end of sib2, iclass 40, count 0 2006.211.07:52:30.81#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:52:30.81#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:52:30.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:52:30.81#ibcon#*before write, iclass 40, count 0 2006.211.07:52:30.81#ibcon#enter sib2, iclass 40, count 0 2006.211.07:52:30.81#ibcon#flushed, iclass 40, count 0 2006.211.07:52:30.81#ibcon#about to write, iclass 40, count 0 2006.211.07:52:30.81#ibcon#wrote, iclass 40, count 0 2006.211.07:52:30.81#ibcon#about to read 3, iclass 40, count 0 2006.211.07:52:30.85#ibcon#read 3, iclass 40, count 0 2006.211.07:52:30.85#ibcon#about to read 4, iclass 40, count 0 2006.211.07:52:30.85#ibcon#read 4, iclass 40, count 0 2006.211.07:52:30.85#ibcon#about to read 5, iclass 40, count 0 2006.211.07:52:30.85#ibcon#read 5, iclass 40, count 0 2006.211.07:52:30.85#ibcon#about to read 6, iclass 40, count 0 2006.211.07:52:30.85#ibcon#read 6, iclass 40, count 0 2006.211.07:52:30.85#ibcon#end of sib2, iclass 40, count 0 2006.211.07:52:30.85#ibcon#*after write, iclass 40, count 0 2006.211.07:52:30.85#ibcon#*before return 0, iclass 40, count 0 2006.211.07:52:30.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:30.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:52:30.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:52:30.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:52:30.85$vc4f8/vb=3,3 2006.211.07:52:30.85#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:52:30.85#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:52:30.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:30.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:30.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:30.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:30.91#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:52:30.91#ibcon#first serial, iclass 4, count 2 2006.211.07:52:30.91#ibcon#enter sib2, iclass 4, count 2 2006.211.07:52:30.91#ibcon#flushed, iclass 4, count 2 2006.211.07:52:30.91#ibcon#about to write, iclass 4, count 2 2006.211.07:52:30.91#ibcon#wrote, iclass 4, count 2 2006.211.07:52:30.91#ibcon#about to read 3, iclass 4, count 2 2006.211.07:52:30.93#ibcon#read 3, iclass 4, count 2 2006.211.07:52:30.93#ibcon#about to read 4, iclass 4, count 2 2006.211.07:52:30.93#ibcon#read 4, iclass 4, count 2 2006.211.07:52:30.93#ibcon#about to read 5, iclass 4, count 2 2006.211.07:52:30.93#ibcon#read 5, iclass 4, count 2 2006.211.07:52:30.93#ibcon#about to read 6, iclass 4, count 2 2006.211.07:52:30.93#ibcon#read 6, iclass 4, count 2 2006.211.07:52:30.93#ibcon#end of sib2, iclass 4, count 2 2006.211.07:52:30.93#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:52:30.93#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:52:30.93#ibcon#[27=AT03-03\r\n] 2006.211.07:52:30.93#ibcon#*before write, iclass 4, count 2 2006.211.07:52:30.93#ibcon#enter sib2, iclass 4, count 2 2006.211.07:52:30.93#ibcon#flushed, iclass 4, count 2 2006.211.07:52:30.93#ibcon#about to write, iclass 4, count 2 2006.211.07:52:30.93#ibcon#wrote, iclass 4, count 2 2006.211.07:52:30.93#ibcon#about to read 3, iclass 4, count 2 2006.211.07:52:30.96#ibcon#read 3, iclass 4, count 2 2006.211.07:52:30.96#ibcon#about to read 4, iclass 4, count 2 2006.211.07:52:30.96#ibcon#read 4, iclass 4, count 2 2006.211.07:52:30.96#ibcon#about to read 5, iclass 4, count 2 2006.211.07:52:30.96#ibcon#read 5, iclass 4, count 2 2006.211.07:52:30.96#ibcon#about to read 6, iclass 4, count 2 2006.211.07:52:30.96#ibcon#read 6, iclass 4, count 2 2006.211.07:52:30.96#ibcon#end of sib2, iclass 4, count 2 2006.211.07:52:30.96#ibcon#*after write, iclass 4, count 2 2006.211.07:52:30.96#ibcon#*before return 0, iclass 4, count 2 2006.211.07:52:30.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:30.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:52:30.96#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:52:30.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:30.96#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:31.08#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:31.08#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:31.08#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:52:31.08#ibcon#first serial, iclass 4, count 0 2006.211.07:52:31.08#ibcon#enter sib2, iclass 4, count 0 2006.211.07:52:31.08#ibcon#flushed, iclass 4, count 0 2006.211.07:52:31.08#ibcon#about to write, iclass 4, count 0 2006.211.07:52:31.08#ibcon#wrote, iclass 4, count 0 2006.211.07:52:31.08#ibcon#about to read 3, iclass 4, count 0 2006.211.07:52:31.10#ibcon#read 3, iclass 4, count 0 2006.211.07:52:31.10#ibcon#about to read 4, iclass 4, count 0 2006.211.07:52:31.10#ibcon#read 4, iclass 4, count 0 2006.211.07:52:31.10#ibcon#about to read 5, iclass 4, count 0 2006.211.07:52:31.10#ibcon#read 5, iclass 4, count 0 2006.211.07:52:31.10#ibcon#about to read 6, iclass 4, count 0 2006.211.07:52:31.10#ibcon#read 6, iclass 4, count 0 2006.211.07:52:31.10#ibcon#end of sib2, iclass 4, count 0 2006.211.07:52:31.10#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:52:31.10#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:52:31.10#ibcon#[27=USB\r\n] 2006.211.07:52:31.10#ibcon#*before write, iclass 4, count 0 2006.211.07:52:31.10#ibcon#enter sib2, iclass 4, count 0 2006.211.07:52:31.10#ibcon#flushed, iclass 4, count 0 2006.211.07:52:31.10#ibcon#about to write, iclass 4, count 0 2006.211.07:52:31.10#ibcon#wrote, iclass 4, count 0 2006.211.07:52:31.10#ibcon#about to read 3, iclass 4, count 0 2006.211.07:52:31.13#ibcon#read 3, iclass 4, count 0 2006.211.07:52:31.13#ibcon#about to read 4, iclass 4, count 0 2006.211.07:52:31.13#ibcon#read 4, iclass 4, count 0 2006.211.07:52:31.13#ibcon#about to read 5, iclass 4, count 0 2006.211.07:52:31.13#ibcon#read 5, iclass 4, count 0 2006.211.07:52:31.13#ibcon#about to read 6, iclass 4, count 0 2006.211.07:52:31.13#ibcon#read 6, iclass 4, count 0 2006.211.07:52:31.13#ibcon#end of sib2, iclass 4, count 0 2006.211.07:52:31.13#ibcon#*after write, iclass 4, count 0 2006.211.07:52:31.13#ibcon#*before return 0, iclass 4, count 0 2006.211.07:52:31.13#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:31.13#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:52:31.13#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:52:31.13#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:52:31.13$vc4f8/vblo=4,712.99 2006.211.07:52:31.13#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:52:31.13#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:52:31.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:31.13#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:31.13#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:31.13#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:31.13#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:52:31.13#ibcon#first serial, iclass 6, count 0 2006.211.07:52:31.13#ibcon#enter sib2, iclass 6, count 0 2006.211.07:52:31.13#ibcon#flushed, iclass 6, count 0 2006.211.07:52:31.13#ibcon#about to write, iclass 6, count 0 2006.211.07:52:31.13#ibcon#wrote, iclass 6, count 0 2006.211.07:52:31.13#ibcon#about to read 3, iclass 6, count 0 2006.211.07:52:31.15#ibcon#read 3, iclass 6, count 0 2006.211.07:52:31.15#ibcon#about to read 4, iclass 6, count 0 2006.211.07:52:31.15#ibcon#read 4, iclass 6, count 0 2006.211.07:52:31.15#ibcon#about to read 5, iclass 6, count 0 2006.211.07:52:31.15#ibcon#read 5, iclass 6, count 0 2006.211.07:52:31.15#ibcon#about to read 6, iclass 6, count 0 2006.211.07:52:31.15#ibcon#read 6, iclass 6, count 0 2006.211.07:52:31.15#ibcon#end of sib2, iclass 6, count 0 2006.211.07:52:31.15#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:52:31.15#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:52:31.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:52:31.15#ibcon#*before write, iclass 6, count 0 2006.211.07:52:31.15#ibcon#enter sib2, iclass 6, count 0 2006.211.07:52:31.15#ibcon#flushed, iclass 6, count 0 2006.211.07:52:31.15#ibcon#about to write, iclass 6, count 0 2006.211.07:52:31.15#ibcon#wrote, iclass 6, count 0 2006.211.07:52:31.15#ibcon#about to read 3, iclass 6, count 0 2006.211.07:52:31.19#ibcon#read 3, iclass 6, count 0 2006.211.07:52:31.19#ibcon#about to read 4, iclass 6, count 0 2006.211.07:52:31.19#ibcon#read 4, iclass 6, count 0 2006.211.07:52:31.19#ibcon#about to read 5, iclass 6, count 0 2006.211.07:52:31.19#ibcon#read 5, iclass 6, count 0 2006.211.07:52:31.19#ibcon#about to read 6, iclass 6, count 0 2006.211.07:52:31.19#ibcon#read 6, iclass 6, count 0 2006.211.07:52:31.19#ibcon#end of sib2, iclass 6, count 0 2006.211.07:52:31.19#ibcon#*after write, iclass 6, count 0 2006.211.07:52:31.19#ibcon#*before return 0, iclass 6, count 0 2006.211.07:52:31.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:31.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:52:31.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:52:31.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:52:31.19$vc4f8/vb=4,3 2006.211.07:52:31.19#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:52:31.19#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:52:31.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:31.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:31.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:31.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:31.25#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:52:31.25#ibcon#first serial, iclass 10, count 2 2006.211.07:52:31.25#ibcon#enter sib2, iclass 10, count 2 2006.211.07:52:31.25#ibcon#flushed, iclass 10, count 2 2006.211.07:52:31.25#ibcon#about to write, iclass 10, count 2 2006.211.07:52:31.25#ibcon#wrote, iclass 10, count 2 2006.211.07:52:31.25#ibcon#about to read 3, iclass 10, count 2 2006.211.07:52:31.27#ibcon#read 3, iclass 10, count 2 2006.211.07:52:31.27#ibcon#about to read 4, iclass 10, count 2 2006.211.07:52:31.27#ibcon#read 4, iclass 10, count 2 2006.211.07:52:31.27#ibcon#about to read 5, iclass 10, count 2 2006.211.07:52:31.27#ibcon#read 5, iclass 10, count 2 2006.211.07:52:31.27#ibcon#about to read 6, iclass 10, count 2 2006.211.07:52:31.27#ibcon#read 6, iclass 10, count 2 2006.211.07:52:31.27#ibcon#end of sib2, iclass 10, count 2 2006.211.07:52:31.27#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:52:31.27#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:52:31.27#ibcon#[27=AT04-03\r\n] 2006.211.07:52:31.27#ibcon#*before write, iclass 10, count 2 2006.211.07:52:31.27#ibcon#enter sib2, iclass 10, count 2 2006.211.07:52:31.27#ibcon#flushed, iclass 10, count 2 2006.211.07:52:31.27#ibcon#about to write, iclass 10, count 2 2006.211.07:52:31.27#ibcon#wrote, iclass 10, count 2 2006.211.07:52:31.27#ibcon#about to read 3, iclass 10, count 2 2006.211.07:52:31.30#ibcon#read 3, iclass 10, count 2 2006.211.07:52:31.30#ibcon#about to read 4, iclass 10, count 2 2006.211.07:52:31.30#ibcon#read 4, iclass 10, count 2 2006.211.07:52:31.30#ibcon#about to read 5, iclass 10, count 2 2006.211.07:52:31.30#ibcon#read 5, iclass 10, count 2 2006.211.07:52:31.30#ibcon#about to read 6, iclass 10, count 2 2006.211.07:52:31.30#ibcon#read 6, iclass 10, count 2 2006.211.07:52:31.30#ibcon#end of sib2, iclass 10, count 2 2006.211.07:52:31.30#ibcon#*after write, iclass 10, count 2 2006.211.07:52:31.30#ibcon#*before return 0, iclass 10, count 2 2006.211.07:52:31.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:31.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:52:31.30#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:52:31.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:31.30#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:31.42#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:31.42#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:31.42#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:52:31.42#ibcon#first serial, iclass 10, count 0 2006.211.07:52:31.42#ibcon#enter sib2, iclass 10, count 0 2006.211.07:52:31.42#ibcon#flushed, iclass 10, count 0 2006.211.07:52:31.42#ibcon#about to write, iclass 10, count 0 2006.211.07:52:31.42#ibcon#wrote, iclass 10, count 0 2006.211.07:52:31.42#ibcon#about to read 3, iclass 10, count 0 2006.211.07:52:31.44#ibcon#read 3, iclass 10, count 0 2006.211.07:52:31.44#ibcon#about to read 4, iclass 10, count 0 2006.211.07:52:31.44#ibcon#read 4, iclass 10, count 0 2006.211.07:52:31.44#ibcon#about to read 5, iclass 10, count 0 2006.211.07:52:31.44#ibcon#read 5, iclass 10, count 0 2006.211.07:52:31.44#ibcon#about to read 6, iclass 10, count 0 2006.211.07:52:31.44#ibcon#read 6, iclass 10, count 0 2006.211.07:52:31.44#ibcon#end of sib2, iclass 10, count 0 2006.211.07:52:31.44#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:52:31.44#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:52:31.44#ibcon#[27=USB\r\n] 2006.211.07:52:31.44#ibcon#*before write, iclass 10, count 0 2006.211.07:52:31.44#ibcon#enter sib2, iclass 10, count 0 2006.211.07:52:31.44#ibcon#flushed, iclass 10, count 0 2006.211.07:52:31.44#ibcon#about to write, iclass 10, count 0 2006.211.07:52:31.44#ibcon#wrote, iclass 10, count 0 2006.211.07:52:31.44#ibcon#about to read 3, iclass 10, count 0 2006.211.07:52:31.47#ibcon#read 3, iclass 10, count 0 2006.211.07:52:31.47#ibcon#about to read 4, iclass 10, count 0 2006.211.07:52:31.47#ibcon#read 4, iclass 10, count 0 2006.211.07:52:31.47#ibcon#about to read 5, iclass 10, count 0 2006.211.07:52:31.47#ibcon#read 5, iclass 10, count 0 2006.211.07:52:31.47#ibcon#about to read 6, iclass 10, count 0 2006.211.07:52:31.47#ibcon#read 6, iclass 10, count 0 2006.211.07:52:31.47#ibcon#end of sib2, iclass 10, count 0 2006.211.07:52:31.47#ibcon#*after write, iclass 10, count 0 2006.211.07:52:31.47#ibcon#*before return 0, iclass 10, count 0 2006.211.07:52:31.47#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:31.47#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:52:31.47#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:52:31.47#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:52:31.47$vc4f8/vblo=5,744.99 2006.211.07:52:31.47#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:52:31.47#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:52:31.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:31.47#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:31.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:31.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:31.47#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:52:31.47#ibcon#first serial, iclass 12, count 0 2006.211.07:52:31.47#ibcon#enter sib2, iclass 12, count 0 2006.211.07:52:31.47#ibcon#flushed, iclass 12, count 0 2006.211.07:52:31.47#ibcon#about to write, iclass 12, count 0 2006.211.07:52:31.47#ibcon#wrote, iclass 12, count 0 2006.211.07:52:31.47#ibcon#about to read 3, iclass 12, count 0 2006.211.07:52:31.49#ibcon#read 3, iclass 12, count 0 2006.211.07:52:31.49#ibcon#about to read 4, iclass 12, count 0 2006.211.07:52:31.49#ibcon#read 4, iclass 12, count 0 2006.211.07:52:31.49#ibcon#about to read 5, iclass 12, count 0 2006.211.07:52:31.49#ibcon#read 5, iclass 12, count 0 2006.211.07:52:31.49#ibcon#about to read 6, iclass 12, count 0 2006.211.07:52:31.49#ibcon#read 6, iclass 12, count 0 2006.211.07:52:31.49#ibcon#end of sib2, iclass 12, count 0 2006.211.07:52:31.49#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:52:31.49#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:52:31.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:52:31.49#ibcon#*before write, iclass 12, count 0 2006.211.07:52:31.49#ibcon#enter sib2, iclass 12, count 0 2006.211.07:52:31.49#ibcon#flushed, iclass 12, count 0 2006.211.07:52:31.49#ibcon#about to write, iclass 12, count 0 2006.211.07:52:31.49#ibcon#wrote, iclass 12, count 0 2006.211.07:52:31.49#ibcon#about to read 3, iclass 12, count 0 2006.211.07:52:31.53#ibcon#read 3, iclass 12, count 0 2006.211.07:52:31.53#ibcon#about to read 4, iclass 12, count 0 2006.211.07:52:31.53#ibcon#read 4, iclass 12, count 0 2006.211.07:52:31.53#ibcon#about to read 5, iclass 12, count 0 2006.211.07:52:31.53#ibcon#read 5, iclass 12, count 0 2006.211.07:52:31.53#ibcon#about to read 6, iclass 12, count 0 2006.211.07:52:31.53#ibcon#read 6, iclass 12, count 0 2006.211.07:52:31.53#ibcon#end of sib2, iclass 12, count 0 2006.211.07:52:31.53#ibcon#*after write, iclass 12, count 0 2006.211.07:52:31.53#ibcon#*before return 0, iclass 12, count 0 2006.211.07:52:31.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:31.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:52:31.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:52:31.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:52:31.53$vc4f8/vb=5,3 2006.211.07:52:31.53#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:52:31.53#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:52:31.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:31.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:31.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:31.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:31.59#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:52:31.59#ibcon#first serial, iclass 14, count 2 2006.211.07:52:31.59#ibcon#enter sib2, iclass 14, count 2 2006.211.07:52:31.59#ibcon#flushed, iclass 14, count 2 2006.211.07:52:31.59#ibcon#about to write, iclass 14, count 2 2006.211.07:52:31.59#ibcon#wrote, iclass 14, count 2 2006.211.07:52:31.59#ibcon#about to read 3, iclass 14, count 2 2006.211.07:52:31.61#ibcon#read 3, iclass 14, count 2 2006.211.07:52:31.61#ibcon#about to read 4, iclass 14, count 2 2006.211.07:52:31.61#ibcon#read 4, iclass 14, count 2 2006.211.07:52:31.61#ibcon#about to read 5, iclass 14, count 2 2006.211.07:52:31.61#ibcon#read 5, iclass 14, count 2 2006.211.07:52:31.61#ibcon#about to read 6, iclass 14, count 2 2006.211.07:52:31.61#ibcon#read 6, iclass 14, count 2 2006.211.07:52:31.61#ibcon#end of sib2, iclass 14, count 2 2006.211.07:52:31.61#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:52:31.61#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:52:31.61#ibcon#[27=AT05-03\r\n] 2006.211.07:52:31.61#ibcon#*before write, iclass 14, count 2 2006.211.07:52:31.61#ibcon#enter sib2, iclass 14, count 2 2006.211.07:52:31.61#ibcon#flushed, iclass 14, count 2 2006.211.07:52:31.61#ibcon#about to write, iclass 14, count 2 2006.211.07:52:31.61#ibcon#wrote, iclass 14, count 2 2006.211.07:52:31.61#ibcon#about to read 3, iclass 14, count 2 2006.211.07:52:31.64#ibcon#read 3, iclass 14, count 2 2006.211.07:52:31.64#ibcon#about to read 4, iclass 14, count 2 2006.211.07:52:31.64#ibcon#read 4, iclass 14, count 2 2006.211.07:52:31.64#ibcon#about to read 5, iclass 14, count 2 2006.211.07:52:31.64#ibcon#read 5, iclass 14, count 2 2006.211.07:52:31.64#ibcon#about to read 6, iclass 14, count 2 2006.211.07:52:31.64#ibcon#read 6, iclass 14, count 2 2006.211.07:52:31.64#ibcon#end of sib2, iclass 14, count 2 2006.211.07:52:31.64#ibcon#*after write, iclass 14, count 2 2006.211.07:52:31.64#ibcon#*before return 0, iclass 14, count 2 2006.211.07:52:31.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:31.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:52:31.64#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:52:31.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:31.64#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:31.76#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:31.76#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:31.76#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:52:31.76#ibcon#first serial, iclass 14, count 0 2006.211.07:52:31.76#ibcon#enter sib2, iclass 14, count 0 2006.211.07:52:31.76#ibcon#flushed, iclass 14, count 0 2006.211.07:52:31.76#ibcon#about to write, iclass 14, count 0 2006.211.07:52:31.76#ibcon#wrote, iclass 14, count 0 2006.211.07:52:31.76#ibcon#about to read 3, iclass 14, count 0 2006.211.07:52:31.78#ibcon#read 3, iclass 14, count 0 2006.211.07:52:31.78#ibcon#about to read 4, iclass 14, count 0 2006.211.07:52:31.78#ibcon#read 4, iclass 14, count 0 2006.211.07:52:31.78#ibcon#about to read 5, iclass 14, count 0 2006.211.07:52:31.78#ibcon#read 5, iclass 14, count 0 2006.211.07:52:31.78#ibcon#about to read 6, iclass 14, count 0 2006.211.07:52:31.78#ibcon#read 6, iclass 14, count 0 2006.211.07:52:31.78#ibcon#end of sib2, iclass 14, count 0 2006.211.07:52:31.78#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:52:31.78#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:52:31.78#ibcon#[27=USB\r\n] 2006.211.07:52:31.78#ibcon#*before write, iclass 14, count 0 2006.211.07:52:31.78#ibcon#enter sib2, iclass 14, count 0 2006.211.07:52:31.78#ibcon#flushed, iclass 14, count 0 2006.211.07:52:31.78#ibcon#about to write, iclass 14, count 0 2006.211.07:52:31.78#ibcon#wrote, iclass 14, count 0 2006.211.07:52:31.78#ibcon#about to read 3, iclass 14, count 0 2006.211.07:52:31.81#ibcon#read 3, iclass 14, count 0 2006.211.07:52:31.81#ibcon#about to read 4, iclass 14, count 0 2006.211.07:52:31.81#ibcon#read 4, iclass 14, count 0 2006.211.07:52:31.81#ibcon#about to read 5, iclass 14, count 0 2006.211.07:52:31.81#ibcon#read 5, iclass 14, count 0 2006.211.07:52:31.81#ibcon#about to read 6, iclass 14, count 0 2006.211.07:52:31.81#ibcon#read 6, iclass 14, count 0 2006.211.07:52:31.81#ibcon#end of sib2, iclass 14, count 0 2006.211.07:52:31.81#ibcon#*after write, iclass 14, count 0 2006.211.07:52:31.81#ibcon#*before return 0, iclass 14, count 0 2006.211.07:52:31.81#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:31.81#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:52:31.81#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:52:31.81#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:52:31.81$vc4f8/vblo=6,752.99 2006.211.07:52:31.81#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:52:31.81#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:52:31.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:52:31.81#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:31.81#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:31.81#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:31.81#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:52:31.81#ibcon#first serial, iclass 16, count 0 2006.211.07:52:31.81#ibcon#enter sib2, iclass 16, count 0 2006.211.07:52:31.81#ibcon#flushed, iclass 16, count 0 2006.211.07:52:31.81#ibcon#about to write, iclass 16, count 0 2006.211.07:52:31.81#ibcon#wrote, iclass 16, count 0 2006.211.07:52:31.81#ibcon#about to read 3, iclass 16, count 0 2006.211.07:52:31.83#ibcon#read 3, iclass 16, count 0 2006.211.07:52:31.83#ibcon#about to read 4, iclass 16, count 0 2006.211.07:52:31.83#ibcon#read 4, iclass 16, count 0 2006.211.07:52:31.83#ibcon#about to read 5, iclass 16, count 0 2006.211.07:52:31.83#ibcon#read 5, iclass 16, count 0 2006.211.07:52:31.83#ibcon#about to read 6, iclass 16, count 0 2006.211.07:52:31.83#ibcon#read 6, iclass 16, count 0 2006.211.07:52:31.83#ibcon#end of sib2, iclass 16, count 0 2006.211.07:52:31.83#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:52:31.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:52:31.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:52:31.83#ibcon#*before write, iclass 16, count 0 2006.211.07:52:31.83#ibcon#enter sib2, iclass 16, count 0 2006.211.07:52:31.83#ibcon#flushed, iclass 16, count 0 2006.211.07:52:31.83#ibcon#about to write, iclass 16, count 0 2006.211.07:52:31.83#ibcon#wrote, iclass 16, count 0 2006.211.07:52:31.83#ibcon#about to read 3, iclass 16, count 0 2006.211.07:52:31.87#ibcon#read 3, iclass 16, count 0 2006.211.07:52:31.87#ibcon#about to read 4, iclass 16, count 0 2006.211.07:52:31.87#ibcon#read 4, iclass 16, count 0 2006.211.07:52:31.87#ibcon#about to read 5, iclass 16, count 0 2006.211.07:52:31.87#ibcon#read 5, iclass 16, count 0 2006.211.07:52:31.87#ibcon#about to read 6, iclass 16, count 0 2006.211.07:52:31.87#ibcon#read 6, iclass 16, count 0 2006.211.07:52:31.87#ibcon#end of sib2, iclass 16, count 0 2006.211.07:52:31.87#ibcon#*after write, iclass 16, count 0 2006.211.07:52:31.87#ibcon#*before return 0, iclass 16, count 0 2006.211.07:52:31.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:31.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:52:31.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:52:31.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:52:31.87$vc4f8/vb=6,3 2006.211.07:52:31.87#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.07:52:31.87#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.07:52:31.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:52:31.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:31.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:31.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:31.93#ibcon#enter wrdev, iclass 18, count 2 2006.211.07:52:31.93#ibcon#first serial, iclass 18, count 2 2006.211.07:52:31.93#ibcon#enter sib2, iclass 18, count 2 2006.211.07:52:31.93#ibcon#flushed, iclass 18, count 2 2006.211.07:52:31.93#ibcon#about to write, iclass 18, count 2 2006.211.07:52:31.93#ibcon#wrote, iclass 18, count 2 2006.211.07:52:31.93#ibcon#about to read 3, iclass 18, count 2 2006.211.07:52:31.95#ibcon#read 3, iclass 18, count 2 2006.211.07:52:31.95#ibcon#about to read 4, iclass 18, count 2 2006.211.07:52:31.95#ibcon#read 4, iclass 18, count 2 2006.211.07:52:31.95#ibcon#about to read 5, iclass 18, count 2 2006.211.07:52:31.95#ibcon#read 5, iclass 18, count 2 2006.211.07:52:31.95#ibcon#about to read 6, iclass 18, count 2 2006.211.07:52:31.95#ibcon#read 6, iclass 18, count 2 2006.211.07:52:31.95#ibcon#end of sib2, iclass 18, count 2 2006.211.07:52:31.95#ibcon#*mode == 0, iclass 18, count 2 2006.211.07:52:31.95#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.07:52:31.95#ibcon#[27=AT06-03\r\n] 2006.211.07:52:31.95#ibcon#*before write, iclass 18, count 2 2006.211.07:52:31.95#ibcon#enter sib2, iclass 18, count 2 2006.211.07:52:31.95#ibcon#flushed, iclass 18, count 2 2006.211.07:52:31.95#ibcon#about to write, iclass 18, count 2 2006.211.07:52:31.95#ibcon#wrote, iclass 18, count 2 2006.211.07:52:31.95#ibcon#about to read 3, iclass 18, count 2 2006.211.07:52:31.98#ibcon#read 3, iclass 18, count 2 2006.211.07:52:31.98#ibcon#about to read 4, iclass 18, count 2 2006.211.07:52:31.98#ibcon#read 4, iclass 18, count 2 2006.211.07:52:31.98#ibcon#about to read 5, iclass 18, count 2 2006.211.07:52:31.98#ibcon#read 5, iclass 18, count 2 2006.211.07:52:31.98#ibcon#about to read 6, iclass 18, count 2 2006.211.07:52:31.98#ibcon#read 6, iclass 18, count 2 2006.211.07:52:31.98#ibcon#end of sib2, iclass 18, count 2 2006.211.07:52:31.98#ibcon#*after write, iclass 18, count 2 2006.211.07:52:31.98#ibcon#*before return 0, iclass 18, count 2 2006.211.07:52:31.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:31.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:52:31.98#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.07:52:31.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:52:31.98#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:32.10#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:32.10#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:32.10#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:52:32.10#ibcon#first serial, iclass 18, count 0 2006.211.07:52:32.10#ibcon#enter sib2, iclass 18, count 0 2006.211.07:52:32.10#ibcon#flushed, iclass 18, count 0 2006.211.07:52:32.10#ibcon#about to write, iclass 18, count 0 2006.211.07:52:32.10#ibcon#wrote, iclass 18, count 0 2006.211.07:52:32.10#ibcon#about to read 3, iclass 18, count 0 2006.211.07:52:32.12#ibcon#read 3, iclass 18, count 0 2006.211.07:52:32.12#ibcon#about to read 4, iclass 18, count 0 2006.211.07:52:32.12#ibcon#read 4, iclass 18, count 0 2006.211.07:52:32.12#ibcon#about to read 5, iclass 18, count 0 2006.211.07:52:32.12#ibcon#read 5, iclass 18, count 0 2006.211.07:52:32.12#ibcon#about to read 6, iclass 18, count 0 2006.211.07:52:32.12#ibcon#read 6, iclass 18, count 0 2006.211.07:52:32.12#ibcon#end of sib2, iclass 18, count 0 2006.211.07:52:32.12#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:52:32.12#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:52:32.12#ibcon#[27=USB\r\n] 2006.211.07:52:32.12#ibcon#*before write, iclass 18, count 0 2006.211.07:52:32.12#ibcon#enter sib2, iclass 18, count 0 2006.211.07:52:32.12#ibcon#flushed, iclass 18, count 0 2006.211.07:52:32.12#ibcon#about to write, iclass 18, count 0 2006.211.07:52:32.12#ibcon#wrote, iclass 18, count 0 2006.211.07:52:32.12#ibcon#about to read 3, iclass 18, count 0 2006.211.07:52:32.15#ibcon#read 3, iclass 18, count 0 2006.211.07:52:32.15#ibcon#about to read 4, iclass 18, count 0 2006.211.07:52:32.15#ibcon#read 4, iclass 18, count 0 2006.211.07:52:32.15#ibcon#about to read 5, iclass 18, count 0 2006.211.07:52:32.15#ibcon#read 5, iclass 18, count 0 2006.211.07:52:32.15#ibcon#about to read 6, iclass 18, count 0 2006.211.07:52:32.15#ibcon#read 6, iclass 18, count 0 2006.211.07:52:32.15#ibcon#end of sib2, iclass 18, count 0 2006.211.07:52:32.15#ibcon#*after write, iclass 18, count 0 2006.211.07:52:32.15#ibcon#*before return 0, iclass 18, count 0 2006.211.07:52:32.15#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:32.15#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:52:32.15#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:52:32.15#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:52:32.15$vc4f8/vabw=wide 2006.211.07:52:32.15#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.07:52:32.15#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.07:52:32.15#ibcon#ireg 8 cls_cnt 0 2006.211.07:52:32.15#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:32.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:32.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:32.15#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:52:32.15#ibcon#first serial, iclass 20, count 0 2006.211.07:52:32.15#ibcon#enter sib2, iclass 20, count 0 2006.211.07:52:32.15#ibcon#flushed, iclass 20, count 0 2006.211.07:52:32.15#ibcon#about to write, iclass 20, count 0 2006.211.07:52:32.15#ibcon#wrote, iclass 20, count 0 2006.211.07:52:32.15#ibcon#about to read 3, iclass 20, count 0 2006.211.07:52:32.17#ibcon#read 3, iclass 20, count 0 2006.211.07:52:32.17#ibcon#about to read 4, iclass 20, count 0 2006.211.07:52:32.17#ibcon#read 4, iclass 20, count 0 2006.211.07:52:32.17#ibcon#about to read 5, iclass 20, count 0 2006.211.07:52:32.17#ibcon#read 5, iclass 20, count 0 2006.211.07:52:32.17#ibcon#about to read 6, iclass 20, count 0 2006.211.07:52:32.17#ibcon#read 6, iclass 20, count 0 2006.211.07:52:32.17#ibcon#end of sib2, iclass 20, count 0 2006.211.07:52:32.17#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:52:32.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:52:32.17#ibcon#[25=BW32\r\n] 2006.211.07:52:32.17#ibcon#*before write, iclass 20, count 0 2006.211.07:52:32.17#ibcon#enter sib2, iclass 20, count 0 2006.211.07:52:32.17#ibcon#flushed, iclass 20, count 0 2006.211.07:52:32.17#ibcon#about to write, iclass 20, count 0 2006.211.07:52:32.17#ibcon#wrote, iclass 20, count 0 2006.211.07:52:32.17#ibcon#about to read 3, iclass 20, count 0 2006.211.07:52:32.20#ibcon#read 3, iclass 20, count 0 2006.211.07:52:32.20#ibcon#about to read 4, iclass 20, count 0 2006.211.07:52:32.20#ibcon#read 4, iclass 20, count 0 2006.211.07:52:32.20#ibcon#about to read 5, iclass 20, count 0 2006.211.07:52:32.20#ibcon#read 5, iclass 20, count 0 2006.211.07:52:32.20#ibcon#about to read 6, iclass 20, count 0 2006.211.07:52:32.20#ibcon#read 6, iclass 20, count 0 2006.211.07:52:32.20#ibcon#end of sib2, iclass 20, count 0 2006.211.07:52:32.20#ibcon#*after write, iclass 20, count 0 2006.211.07:52:32.20#ibcon#*before return 0, iclass 20, count 0 2006.211.07:52:32.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:32.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:52:32.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:52:32.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:52:32.20$vc4f8/vbbw=wide 2006.211.07:52:32.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:52:32.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:52:32.20#ibcon#ireg 8 cls_cnt 0 2006.211.07:52:32.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:52:32.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:52:32.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:52:32.27#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:52:32.27#ibcon#first serial, iclass 22, count 0 2006.211.07:52:32.27#ibcon#enter sib2, iclass 22, count 0 2006.211.07:52:32.27#ibcon#flushed, iclass 22, count 0 2006.211.07:52:32.27#ibcon#about to write, iclass 22, count 0 2006.211.07:52:32.27#ibcon#wrote, iclass 22, count 0 2006.211.07:52:32.27#ibcon#about to read 3, iclass 22, count 0 2006.211.07:52:32.29#ibcon#read 3, iclass 22, count 0 2006.211.07:52:32.29#ibcon#about to read 4, iclass 22, count 0 2006.211.07:52:32.29#ibcon#read 4, iclass 22, count 0 2006.211.07:52:32.29#ibcon#about to read 5, iclass 22, count 0 2006.211.07:52:32.29#ibcon#read 5, iclass 22, count 0 2006.211.07:52:32.29#ibcon#about to read 6, iclass 22, count 0 2006.211.07:52:32.29#ibcon#read 6, iclass 22, count 0 2006.211.07:52:32.29#ibcon#end of sib2, iclass 22, count 0 2006.211.07:52:32.29#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:52:32.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:52:32.29#ibcon#[27=BW32\r\n] 2006.211.07:52:32.29#ibcon#*before write, iclass 22, count 0 2006.211.07:52:32.29#ibcon#enter sib2, iclass 22, count 0 2006.211.07:52:32.29#ibcon#flushed, iclass 22, count 0 2006.211.07:52:32.29#ibcon#about to write, iclass 22, count 0 2006.211.07:52:32.29#ibcon#wrote, iclass 22, count 0 2006.211.07:52:32.29#ibcon#about to read 3, iclass 22, count 0 2006.211.07:52:32.32#ibcon#read 3, iclass 22, count 0 2006.211.07:52:32.32#ibcon#about to read 4, iclass 22, count 0 2006.211.07:52:32.32#ibcon#read 4, iclass 22, count 0 2006.211.07:52:32.32#ibcon#about to read 5, iclass 22, count 0 2006.211.07:52:32.32#ibcon#read 5, iclass 22, count 0 2006.211.07:52:32.32#ibcon#about to read 6, iclass 22, count 0 2006.211.07:52:32.32#ibcon#read 6, iclass 22, count 0 2006.211.07:52:32.32#ibcon#end of sib2, iclass 22, count 0 2006.211.07:52:32.32#ibcon#*after write, iclass 22, count 0 2006.211.07:52:32.32#ibcon#*before return 0, iclass 22, count 0 2006.211.07:52:32.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:52:32.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:52:32.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:52:32.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:52:32.32$4f8m12a/ifd4f 2006.211.07:52:32.32$ifd4f/lo= 2006.211.07:52:32.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:52:32.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:52:32.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:52:32.32$ifd4f/patch= 2006.211.07:52:32.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:52:32.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:52:32.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:52:32.32$4f8m12a/"form=m,16.000,1:2 2006.211.07:52:32.32$4f8m12a/"tpicd 2006.211.07:52:32.32$4f8m12a/echo=off 2006.211.07:52:32.32$4f8m12a/xlog=off 2006.211.07:52:32.32:!2006.211.07:53:00 2006.211.07:52:42.14#trakl#Source acquired 2006.211.07:52:42.14#flagr#flagr/antenna,acquired 2006.211.07:53:00.00:preob 2006.211.07:53:01.14/onsource/TRACKING 2006.211.07:53:01.14:!2006.211.07:53:10 2006.211.07:53:10.00:data_valid=on 2006.211.07:53:10.00:midob 2006.211.07:53:10.14/onsource/TRACKING 2006.211.07:53:10.14/wx/24.92,1010.1,78 2006.211.07:53:10.30/cable/+6.4393E-03 2006.211.07:53:11.39/va/01,08,usb,yes,29,31 2006.211.07:53:11.39/va/02,07,usb,yes,29,31 2006.211.07:53:11.39/va/03,06,usb,yes,31,31 2006.211.07:53:11.39/va/04,07,usb,yes,30,32 2006.211.07:53:11.39/va/05,07,usb,yes,33,34 2006.211.07:53:11.39/va/06,06,usb,yes,32,31 2006.211.07:53:11.39/va/07,06,usb,yes,32,32 2006.211.07:53:11.39/va/08,07,usb,yes,30,30 2006.211.07:53:11.62/valo/01,532.99,yes,locked 2006.211.07:53:11.62/valo/02,572.99,yes,locked 2006.211.07:53:11.62/valo/03,672.99,yes,locked 2006.211.07:53:11.62/valo/04,832.99,yes,locked 2006.211.07:53:11.62/valo/05,652.99,yes,locked 2006.211.07:53:11.62/valo/06,772.99,yes,locked 2006.211.07:53:11.62/valo/07,832.99,yes,locked 2006.211.07:53:11.62/valo/08,852.99,yes,locked 2006.211.07:53:12.71/vb/01,04,usb,yes,29,27 2006.211.07:53:12.71/vb/02,04,usb,yes,30,32 2006.211.07:53:12.71/vb/03,03,usb,yes,33,38 2006.211.07:53:12.71/vb/04,03,usb,yes,34,34 2006.211.07:53:12.71/vb/05,03,usb,yes,33,37 2006.211.07:53:12.71/vb/06,03,usb,yes,33,37 2006.211.07:53:12.71/vb/07,04,usb,yes,29,29 2006.211.07:53:12.71/vb/08,03,usb,yes,33,37 2006.211.07:53:12.95/vblo/01,632.99,yes,locked 2006.211.07:53:12.95/vblo/02,640.99,yes,locked 2006.211.07:53:12.95/vblo/03,656.99,yes,locked 2006.211.07:53:12.95/vblo/04,712.99,yes,locked 2006.211.07:53:12.95/vblo/05,744.99,yes,locked 2006.211.07:53:12.95/vblo/06,752.99,yes,locked 2006.211.07:53:12.95/vblo/07,734.99,yes,locked 2006.211.07:53:12.95/vblo/08,744.99,yes,locked 2006.211.07:53:13.10/vabw/8 2006.211.07:53:13.25/vbbw/8 2006.211.07:53:13.34/xfe/off,on,13.2 2006.211.07:53:13.74/ifatt/23,28,28,28 2006.211.07:53:14.08/fmout-gps/S +4.47E-07 2006.211.07:53:14.12:!2006.211.07:54:10 2006.211.07:54:10.00:data_valid=off 2006.211.07:54:10.00:postob 2006.211.07:54:10.11/cable/+6.4381E-03 2006.211.07:54:10.11/wx/24.91,1010.1,77 2006.211.07:54:11.08/fmout-gps/S +4.46E-07 2006.211.07:54:11.08:scan_name=211-0755,k06211,60 2006.211.07:54:11.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.211.07:54:11.14#flagr#flagr/antenna,new-source 2006.211.07:54:12.14:checkk5 2006.211.07:54:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:54:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:54:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:54:13.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:54:13.83/chk_obsdata//k5ts1/T2110753??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:54:14.17/chk_obsdata//k5ts2/T2110753??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:54:14.50/chk_obsdata//k5ts3/T2110753??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:54:14.84/chk_obsdata//k5ts4/T2110753??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:54:15.49/k5log//k5ts1_log_newline 2006.211.07:54:16.15/k5log//k5ts2_log_newline 2006.211.07:54:16.81/k5log//k5ts3_log_newline 2006.211.07:54:17.47/k5log//k5ts4_log_newline 2006.211.07:54:17.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:54:17.49:4f8m12a=2 2006.211.07:54:17.49$4f8m12a/echo=on 2006.211.07:54:17.49$4f8m12a/pcalon 2006.211.07:54:17.49$pcalon/"no phase cal control is implemented here 2006.211.07:54:17.49$4f8m12a/"tpicd=stop 2006.211.07:54:17.49$4f8m12a/vc4f8 2006.211.07:54:17.49$vc4f8/valo=1,532.99 2006.211.07:54:17.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:54:17.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:54:17.50#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:17.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:17.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:17.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:17.50#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:54:17.50#ibcon#first serial, iclass 29, count 0 2006.211.07:54:17.50#ibcon#enter sib2, iclass 29, count 0 2006.211.07:54:17.50#ibcon#flushed, iclass 29, count 0 2006.211.07:54:17.50#ibcon#about to write, iclass 29, count 0 2006.211.07:54:17.50#ibcon#wrote, iclass 29, count 0 2006.211.07:54:17.50#ibcon#about to read 3, iclass 29, count 0 2006.211.07:54:17.52#ibcon#read 3, iclass 29, count 0 2006.211.07:54:17.52#ibcon#about to read 4, iclass 29, count 0 2006.211.07:54:17.52#ibcon#read 4, iclass 29, count 0 2006.211.07:54:17.52#ibcon#about to read 5, iclass 29, count 0 2006.211.07:54:17.52#ibcon#read 5, iclass 29, count 0 2006.211.07:54:17.52#ibcon#about to read 6, iclass 29, count 0 2006.211.07:54:17.52#ibcon#read 6, iclass 29, count 0 2006.211.07:54:17.52#ibcon#end of sib2, iclass 29, count 0 2006.211.07:54:17.52#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:54:17.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:54:17.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:54:17.52#ibcon#*before write, iclass 29, count 0 2006.211.07:54:17.52#ibcon#enter sib2, iclass 29, count 0 2006.211.07:54:17.52#ibcon#flushed, iclass 29, count 0 2006.211.07:54:17.52#ibcon#about to write, iclass 29, count 0 2006.211.07:54:17.52#ibcon#wrote, iclass 29, count 0 2006.211.07:54:17.52#ibcon#about to read 3, iclass 29, count 0 2006.211.07:54:17.57#ibcon#read 3, iclass 29, count 0 2006.211.07:54:17.57#ibcon#about to read 4, iclass 29, count 0 2006.211.07:54:17.57#ibcon#read 4, iclass 29, count 0 2006.211.07:54:17.57#ibcon#about to read 5, iclass 29, count 0 2006.211.07:54:17.57#ibcon#read 5, iclass 29, count 0 2006.211.07:54:17.57#ibcon#about to read 6, iclass 29, count 0 2006.211.07:54:17.57#ibcon#read 6, iclass 29, count 0 2006.211.07:54:17.57#ibcon#end of sib2, iclass 29, count 0 2006.211.07:54:17.57#ibcon#*after write, iclass 29, count 0 2006.211.07:54:17.57#ibcon#*before return 0, iclass 29, count 0 2006.211.07:54:17.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:17.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:17.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:54:17.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:54:17.57$vc4f8/va=1,8 2006.211.07:54:17.57#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:54:17.57#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:54:17.57#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:17.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:17.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:17.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:17.57#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:54:17.57#ibcon#first serial, iclass 31, count 2 2006.211.07:54:17.57#ibcon#enter sib2, iclass 31, count 2 2006.211.07:54:17.57#ibcon#flushed, iclass 31, count 2 2006.211.07:54:17.57#ibcon#about to write, iclass 31, count 2 2006.211.07:54:17.57#ibcon#wrote, iclass 31, count 2 2006.211.07:54:17.57#ibcon#about to read 3, iclass 31, count 2 2006.211.07:54:17.59#ibcon#read 3, iclass 31, count 2 2006.211.07:54:17.59#ibcon#about to read 4, iclass 31, count 2 2006.211.07:54:17.59#ibcon#read 4, iclass 31, count 2 2006.211.07:54:17.59#ibcon#about to read 5, iclass 31, count 2 2006.211.07:54:17.59#ibcon#read 5, iclass 31, count 2 2006.211.07:54:17.59#ibcon#about to read 6, iclass 31, count 2 2006.211.07:54:17.59#ibcon#read 6, iclass 31, count 2 2006.211.07:54:17.59#ibcon#end of sib2, iclass 31, count 2 2006.211.07:54:17.59#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:54:17.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:54:17.59#ibcon#[25=AT01-08\r\n] 2006.211.07:54:17.59#ibcon#*before write, iclass 31, count 2 2006.211.07:54:17.59#ibcon#enter sib2, iclass 31, count 2 2006.211.07:54:17.59#ibcon#flushed, iclass 31, count 2 2006.211.07:54:17.59#ibcon#about to write, iclass 31, count 2 2006.211.07:54:17.59#ibcon#wrote, iclass 31, count 2 2006.211.07:54:17.59#ibcon#about to read 3, iclass 31, count 2 2006.211.07:54:17.62#ibcon#read 3, iclass 31, count 2 2006.211.07:54:17.62#ibcon#about to read 4, iclass 31, count 2 2006.211.07:54:17.62#ibcon#read 4, iclass 31, count 2 2006.211.07:54:17.62#ibcon#about to read 5, iclass 31, count 2 2006.211.07:54:17.62#ibcon#read 5, iclass 31, count 2 2006.211.07:54:17.62#ibcon#about to read 6, iclass 31, count 2 2006.211.07:54:17.62#ibcon#read 6, iclass 31, count 2 2006.211.07:54:17.62#ibcon#end of sib2, iclass 31, count 2 2006.211.07:54:17.62#ibcon#*after write, iclass 31, count 2 2006.211.07:54:17.62#ibcon#*before return 0, iclass 31, count 2 2006.211.07:54:17.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:17.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:17.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:54:17.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:17.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:17.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:17.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:17.74#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:54:17.74#ibcon#first serial, iclass 31, count 0 2006.211.07:54:17.74#ibcon#enter sib2, iclass 31, count 0 2006.211.07:54:17.74#ibcon#flushed, iclass 31, count 0 2006.211.07:54:17.74#ibcon#about to write, iclass 31, count 0 2006.211.07:54:17.74#ibcon#wrote, iclass 31, count 0 2006.211.07:54:17.74#ibcon#about to read 3, iclass 31, count 0 2006.211.07:54:17.76#ibcon#read 3, iclass 31, count 0 2006.211.07:54:17.76#ibcon#about to read 4, iclass 31, count 0 2006.211.07:54:17.76#ibcon#read 4, iclass 31, count 0 2006.211.07:54:17.76#ibcon#about to read 5, iclass 31, count 0 2006.211.07:54:17.76#ibcon#read 5, iclass 31, count 0 2006.211.07:54:17.76#ibcon#about to read 6, iclass 31, count 0 2006.211.07:54:17.76#ibcon#read 6, iclass 31, count 0 2006.211.07:54:17.76#ibcon#end of sib2, iclass 31, count 0 2006.211.07:54:17.76#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:54:17.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:54:17.76#ibcon#[25=USB\r\n] 2006.211.07:54:17.76#ibcon#*before write, iclass 31, count 0 2006.211.07:54:17.76#ibcon#enter sib2, iclass 31, count 0 2006.211.07:54:17.76#ibcon#flushed, iclass 31, count 0 2006.211.07:54:17.76#ibcon#about to write, iclass 31, count 0 2006.211.07:54:17.76#ibcon#wrote, iclass 31, count 0 2006.211.07:54:17.76#ibcon#about to read 3, iclass 31, count 0 2006.211.07:54:17.79#ibcon#read 3, iclass 31, count 0 2006.211.07:54:17.79#ibcon#about to read 4, iclass 31, count 0 2006.211.07:54:17.79#ibcon#read 4, iclass 31, count 0 2006.211.07:54:17.79#ibcon#about to read 5, iclass 31, count 0 2006.211.07:54:17.79#ibcon#read 5, iclass 31, count 0 2006.211.07:54:17.79#ibcon#about to read 6, iclass 31, count 0 2006.211.07:54:17.79#ibcon#read 6, iclass 31, count 0 2006.211.07:54:17.79#ibcon#end of sib2, iclass 31, count 0 2006.211.07:54:17.79#ibcon#*after write, iclass 31, count 0 2006.211.07:54:17.79#ibcon#*before return 0, iclass 31, count 0 2006.211.07:54:17.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:17.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:17.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:54:17.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:54:17.79$vc4f8/valo=2,572.99 2006.211.07:54:17.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:54:17.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:54:17.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:17.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:17.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:17.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:17.79#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:54:17.79#ibcon#first serial, iclass 33, count 0 2006.211.07:54:17.79#ibcon#enter sib2, iclass 33, count 0 2006.211.07:54:17.79#ibcon#flushed, iclass 33, count 0 2006.211.07:54:17.79#ibcon#about to write, iclass 33, count 0 2006.211.07:54:17.79#ibcon#wrote, iclass 33, count 0 2006.211.07:54:17.79#ibcon#about to read 3, iclass 33, count 0 2006.211.07:54:17.81#ibcon#read 3, iclass 33, count 0 2006.211.07:54:17.81#ibcon#about to read 4, iclass 33, count 0 2006.211.07:54:17.81#ibcon#read 4, iclass 33, count 0 2006.211.07:54:17.81#ibcon#about to read 5, iclass 33, count 0 2006.211.07:54:17.81#ibcon#read 5, iclass 33, count 0 2006.211.07:54:17.81#ibcon#about to read 6, iclass 33, count 0 2006.211.07:54:17.81#ibcon#read 6, iclass 33, count 0 2006.211.07:54:17.81#ibcon#end of sib2, iclass 33, count 0 2006.211.07:54:17.81#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:54:17.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:54:17.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:54:17.81#ibcon#*before write, iclass 33, count 0 2006.211.07:54:17.81#ibcon#enter sib2, iclass 33, count 0 2006.211.07:54:17.81#ibcon#flushed, iclass 33, count 0 2006.211.07:54:17.81#ibcon#about to write, iclass 33, count 0 2006.211.07:54:17.81#ibcon#wrote, iclass 33, count 0 2006.211.07:54:17.81#ibcon#about to read 3, iclass 33, count 0 2006.211.07:54:17.85#ibcon#read 3, iclass 33, count 0 2006.211.07:54:17.85#ibcon#about to read 4, iclass 33, count 0 2006.211.07:54:17.85#ibcon#read 4, iclass 33, count 0 2006.211.07:54:17.85#ibcon#about to read 5, iclass 33, count 0 2006.211.07:54:17.85#ibcon#read 5, iclass 33, count 0 2006.211.07:54:17.85#ibcon#about to read 6, iclass 33, count 0 2006.211.07:54:17.85#ibcon#read 6, iclass 33, count 0 2006.211.07:54:17.85#ibcon#end of sib2, iclass 33, count 0 2006.211.07:54:17.85#ibcon#*after write, iclass 33, count 0 2006.211.07:54:17.85#ibcon#*before return 0, iclass 33, count 0 2006.211.07:54:17.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:17.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:17.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:54:17.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:54:17.85$vc4f8/va=2,7 2006.211.07:54:17.85#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:54:17.85#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:54:17.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:17.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:17.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:17.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:17.91#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:54:17.91#ibcon#first serial, iclass 35, count 2 2006.211.07:54:17.91#ibcon#enter sib2, iclass 35, count 2 2006.211.07:54:17.91#ibcon#flushed, iclass 35, count 2 2006.211.07:54:17.91#ibcon#about to write, iclass 35, count 2 2006.211.07:54:17.91#ibcon#wrote, iclass 35, count 2 2006.211.07:54:17.91#ibcon#about to read 3, iclass 35, count 2 2006.211.07:54:17.93#ibcon#read 3, iclass 35, count 2 2006.211.07:54:17.93#ibcon#about to read 4, iclass 35, count 2 2006.211.07:54:17.93#ibcon#read 4, iclass 35, count 2 2006.211.07:54:17.93#ibcon#about to read 5, iclass 35, count 2 2006.211.07:54:17.93#ibcon#read 5, iclass 35, count 2 2006.211.07:54:17.93#ibcon#about to read 6, iclass 35, count 2 2006.211.07:54:17.93#ibcon#read 6, iclass 35, count 2 2006.211.07:54:17.93#ibcon#end of sib2, iclass 35, count 2 2006.211.07:54:17.93#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:54:17.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:54:17.93#ibcon#[25=AT02-07\r\n] 2006.211.07:54:17.93#ibcon#*before write, iclass 35, count 2 2006.211.07:54:17.93#ibcon#enter sib2, iclass 35, count 2 2006.211.07:54:17.93#ibcon#flushed, iclass 35, count 2 2006.211.07:54:17.93#ibcon#about to write, iclass 35, count 2 2006.211.07:54:17.93#ibcon#wrote, iclass 35, count 2 2006.211.07:54:17.93#ibcon#about to read 3, iclass 35, count 2 2006.211.07:54:17.96#ibcon#read 3, iclass 35, count 2 2006.211.07:54:17.96#ibcon#about to read 4, iclass 35, count 2 2006.211.07:54:17.96#ibcon#read 4, iclass 35, count 2 2006.211.07:54:17.96#ibcon#about to read 5, iclass 35, count 2 2006.211.07:54:17.96#ibcon#read 5, iclass 35, count 2 2006.211.07:54:17.96#ibcon#about to read 6, iclass 35, count 2 2006.211.07:54:17.96#ibcon#read 6, iclass 35, count 2 2006.211.07:54:17.96#ibcon#end of sib2, iclass 35, count 2 2006.211.07:54:17.96#ibcon#*after write, iclass 35, count 2 2006.211.07:54:17.96#ibcon#*before return 0, iclass 35, count 2 2006.211.07:54:17.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:17.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:17.96#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:54:17.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:17.96#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:18.08#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:18.08#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:18.08#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:54:18.08#ibcon#first serial, iclass 35, count 0 2006.211.07:54:18.08#ibcon#enter sib2, iclass 35, count 0 2006.211.07:54:18.08#ibcon#flushed, iclass 35, count 0 2006.211.07:54:18.08#ibcon#about to write, iclass 35, count 0 2006.211.07:54:18.08#ibcon#wrote, iclass 35, count 0 2006.211.07:54:18.08#ibcon#about to read 3, iclass 35, count 0 2006.211.07:54:18.10#ibcon#read 3, iclass 35, count 0 2006.211.07:54:18.10#ibcon#about to read 4, iclass 35, count 0 2006.211.07:54:18.10#ibcon#read 4, iclass 35, count 0 2006.211.07:54:18.10#ibcon#about to read 5, iclass 35, count 0 2006.211.07:54:18.10#ibcon#read 5, iclass 35, count 0 2006.211.07:54:18.10#ibcon#about to read 6, iclass 35, count 0 2006.211.07:54:18.10#ibcon#read 6, iclass 35, count 0 2006.211.07:54:18.10#ibcon#end of sib2, iclass 35, count 0 2006.211.07:54:18.10#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:54:18.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:54:18.10#ibcon#[25=USB\r\n] 2006.211.07:54:18.10#ibcon#*before write, iclass 35, count 0 2006.211.07:54:18.10#ibcon#enter sib2, iclass 35, count 0 2006.211.07:54:18.10#ibcon#flushed, iclass 35, count 0 2006.211.07:54:18.10#ibcon#about to write, iclass 35, count 0 2006.211.07:54:18.10#ibcon#wrote, iclass 35, count 0 2006.211.07:54:18.10#ibcon#about to read 3, iclass 35, count 0 2006.211.07:54:18.13#ibcon#read 3, iclass 35, count 0 2006.211.07:54:18.13#ibcon#about to read 4, iclass 35, count 0 2006.211.07:54:18.13#ibcon#read 4, iclass 35, count 0 2006.211.07:54:18.13#ibcon#about to read 5, iclass 35, count 0 2006.211.07:54:18.13#ibcon#read 5, iclass 35, count 0 2006.211.07:54:18.13#ibcon#about to read 6, iclass 35, count 0 2006.211.07:54:18.13#ibcon#read 6, iclass 35, count 0 2006.211.07:54:18.13#ibcon#end of sib2, iclass 35, count 0 2006.211.07:54:18.13#ibcon#*after write, iclass 35, count 0 2006.211.07:54:18.13#ibcon#*before return 0, iclass 35, count 0 2006.211.07:54:18.13#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:18.13#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:18.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:54:18.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:54:18.13$vc4f8/valo=3,672.99 2006.211.07:54:18.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:54:18.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:54:18.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:18.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:18.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:18.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:18.13#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:54:18.13#ibcon#first serial, iclass 37, count 0 2006.211.07:54:18.13#ibcon#enter sib2, iclass 37, count 0 2006.211.07:54:18.13#ibcon#flushed, iclass 37, count 0 2006.211.07:54:18.13#ibcon#about to write, iclass 37, count 0 2006.211.07:54:18.13#ibcon#wrote, iclass 37, count 0 2006.211.07:54:18.13#ibcon#about to read 3, iclass 37, count 0 2006.211.07:54:18.15#ibcon#read 3, iclass 37, count 0 2006.211.07:54:18.15#ibcon#about to read 4, iclass 37, count 0 2006.211.07:54:18.15#ibcon#read 4, iclass 37, count 0 2006.211.07:54:18.15#ibcon#about to read 5, iclass 37, count 0 2006.211.07:54:18.15#ibcon#read 5, iclass 37, count 0 2006.211.07:54:18.15#ibcon#about to read 6, iclass 37, count 0 2006.211.07:54:18.15#ibcon#read 6, iclass 37, count 0 2006.211.07:54:18.15#ibcon#end of sib2, iclass 37, count 0 2006.211.07:54:18.15#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:54:18.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:54:18.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:54:18.15#ibcon#*before write, iclass 37, count 0 2006.211.07:54:18.15#ibcon#enter sib2, iclass 37, count 0 2006.211.07:54:18.15#ibcon#flushed, iclass 37, count 0 2006.211.07:54:18.15#ibcon#about to write, iclass 37, count 0 2006.211.07:54:18.15#ibcon#wrote, iclass 37, count 0 2006.211.07:54:18.15#ibcon#about to read 3, iclass 37, count 0 2006.211.07:54:18.19#ibcon#read 3, iclass 37, count 0 2006.211.07:54:18.19#ibcon#about to read 4, iclass 37, count 0 2006.211.07:54:18.19#ibcon#read 4, iclass 37, count 0 2006.211.07:54:18.19#ibcon#about to read 5, iclass 37, count 0 2006.211.07:54:18.19#ibcon#read 5, iclass 37, count 0 2006.211.07:54:18.19#ibcon#about to read 6, iclass 37, count 0 2006.211.07:54:18.19#ibcon#read 6, iclass 37, count 0 2006.211.07:54:18.19#ibcon#end of sib2, iclass 37, count 0 2006.211.07:54:18.19#ibcon#*after write, iclass 37, count 0 2006.211.07:54:18.19#ibcon#*before return 0, iclass 37, count 0 2006.211.07:54:18.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:18.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:18.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:54:18.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:54:18.19$vc4f8/va=3,6 2006.211.07:54:18.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:54:18.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:54:18.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:18.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:18.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:18.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:18.25#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:54:18.25#ibcon#first serial, iclass 39, count 2 2006.211.07:54:18.25#ibcon#enter sib2, iclass 39, count 2 2006.211.07:54:18.25#ibcon#flushed, iclass 39, count 2 2006.211.07:54:18.25#ibcon#about to write, iclass 39, count 2 2006.211.07:54:18.25#ibcon#wrote, iclass 39, count 2 2006.211.07:54:18.25#ibcon#about to read 3, iclass 39, count 2 2006.211.07:54:18.27#ibcon#read 3, iclass 39, count 2 2006.211.07:54:18.27#ibcon#about to read 4, iclass 39, count 2 2006.211.07:54:18.27#ibcon#read 4, iclass 39, count 2 2006.211.07:54:18.27#ibcon#about to read 5, iclass 39, count 2 2006.211.07:54:18.27#ibcon#read 5, iclass 39, count 2 2006.211.07:54:18.27#ibcon#about to read 6, iclass 39, count 2 2006.211.07:54:18.27#ibcon#read 6, iclass 39, count 2 2006.211.07:54:18.27#ibcon#end of sib2, iclass 39, count 2 2006.211.07:54:18.27#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:54:18.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:54:18.27#ibcon#[25=AT03-06\r\n] 2006.211.07:54:18.27#ibcon#*before write, iclass 39, count 2 2006.211.07:54:18.27#ibcon#enter sib2, iclass 39, count 2 2006.211.07:54:18.27#ibcon#flushed, iclass 39, count 2 2006.211.07:54:18.27#ibcon#about to write, iclass 39, count 2 2006.211.07:54:18.27#ibcon#wrote, iclass 39, count 2 2006.211.07:54:18.27#ibcon#about to read 3, iclass 39, count 2 2006.211.07:54:18.30#ibcon#read 3, iclass 39, count 2 2006.211.07:54:18.30#ibcon#about to read 4, iclass 39, count 2 2006.211.07:54:18.30#ibcon#read 4, iclass 39, count 2 2006.211.07:54:18.30#ibcon#about to read 5, iclass 39, count 2 2006.211.07:54:18.30#ibcon#read 5, iclass 39, count 2 2006.211.07:54:18.30#ibcon#about to read 6, iclass 39, count 2 2006.211.07:54:18.30#ibcon#read 6, iclass 39, count 2 2006.211.07:54:18.30#ibcon#end of sib2, iclass 39, count 2 2006.211.07:54:18.30#ibcon#*after write, iclass 39, count 2 2006.211.07:54:18.30#ibcon#*before return 0, iclass 39, count 2 2006.211.07:54:18.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:18.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:18.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:54:18.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:18.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:18.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:18.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:18.42#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:54:18.42#ibcon#first serial, iclass 39, count 0 2006.211.07:54:18.42#ibcon#enter sib2, iclass 39, count 0 2006.211.07:54:18.42#ibcon#flushed, iclass 39, count 0 2006.211.07:54:18.42#ibcon#about to write, iclass 39, count 0 2006.211.07:54:18.42#ibcon#wrote, iclass 39, count 0 2006.211.07:54:18.42#ibcon#about to read 3, iclass 39, count 0 2006.211.07:54:18.44#ibcon#read 3, iclass 39, count 0 2006.211.07:54:18.44#ibcon#about to read 4, iclass 39, count 0 2006.211.07:54:18.44#ibcon#read 4, iclass 39, count 0 2006.211.07:54:18.44#ibcon#about to read 5, iclass 39, count 0 2006.211.07:54:18.44#ibcon#read 5, iclass 39, count 0 2006.211.07:54:18.44#ibcon#about to read 6, iclass 39, count 0 2006.211.07:54:18.44#ibcon#read 6, iclass 39, count 0 2006.211.07:54:18.44#ibcon#end of sib2, iclass 39, count 0 2006.211.07:54:18.44#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:54:18.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:54:18.44#ibcon#[25=USB\r\n] 2006.211.07:54:18.44#ibcon#*before write, iclass 39, count 0 2006.211.07:54:18.44#ibcon#enter sib2, iclass 39, count 0 2006.211.07:54:18.44#ibcon#flushed, iclass 39, count 0 2006.211.07:54:18.44#ibcon#about to write, iclass 39, count 0 2006.211.07:54:18.44#ibcon#wrote, iclass 39, count 0 2006.211.07:54:18.44#ibcon#about to read 3, iclass 39, count 0 2006.211.07:54:18.47#ibcon#read 3, iclass 39, count 0 2006.211.07:54:18.47#ibcon#about to read 4, iclass 39, count 0 2006.211.07:54:18.47#ibcon#read 4, iclass 39, count 0 2006.211.07:54:18.47#ibcon#about to read 5, iclass 39, count 0 2006.211.07:54:18.47#ibcon#read 5, iclass 39, count 0 2006.211.07:54:18.47#ibcon#about to read 6, iclass 39, count 0 2006.211.07:54:18.47#ibcon#read 6, iclass 39, count 0 2006.211.07:54:18.47#ibcon#end of sib2, iclass 39, count 0 2006.211.07:54:18.47#ibcon#*after write, iclass 39, count 0 2006.211.07:54:18.47#ibcon#*before return 0, iclass 39, count 0 2006.211.07:54:18.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:18.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:18.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:54:18.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:54:18.47$vc4f8/valo=4,832.99 2006.211.07:54:18.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:54:18.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:54:18.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:18.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:18.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:18.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:18.47#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:54:18.47#ibcon#first serial, iclass 3, count 0 2006.211.07:54:18.47#ibcon#enter sib2, iclass 3, count 0 2006.211.07:54:18.47#ibcon#flushed, iclass 3, count 0 2006.211.07:54:18.47#ibcon#about to write, iclass 3, count 0 2006.211.07:54:18.47#ibcon#wrote, iclass 3, count 0 2006.211.07:54:18.47#ibcon#about to read 3, iclass 3, count 0 2006.211.07:54:18.49#ibcon#read 3, iclass 3, count 0 2006.211.07:54:18.49#ibcon#about to read 4, iclass 3, count 0 2006.211.07:54:18.49#ibcon#read 4, iclass 3, count 0 2006.211.07:54:18.49#ibcon#about to read 5, iclass 3, count 0 2006.211.07:54:18.49#ibcon#read 5, iclass 3, count 0 2006.211.07:54:18.49#ibcon#about to read 6, iclass 3, count 0 2006.211.07:54:18.49#ibcon#read 6, iclass 3, count 0 2006.211.07:54:18.49#ibcon#end of sib2, iclass 3, count 0 2006.211.07:54:18.49#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:54:18.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:54:18.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:54:18.49#ibcon#*before write, iclass 3, count 0 2006.211.07:54:18.49#ibcon#enter sib2, iclass 3, count 0 2006.211.07:54:18.49#ibcon#flushed, iclass 3, count 0 2006.211.07:54:18.49#ibcon#about to write, iclass 3, count 0 2006.211.07:54:18.49#ibcon#wrote, iclass 3, count 0 2006.211.07:54:18.49#ibcon#about to read 3, iclass 3, count 0 2006.211.07:54:18.53#ibcon#read 3, iclass 3, count 0 2006.211.07:54:18.53#ibcon#about to read 4, iclass 3, count 0 2006.211.07:54:18.53#ibcon#read 4, iclass 3, count 0 2006.211.07:54:18.53#ibcon#about to read 5, iclass 3, count 0 2006.211.07:54:18.53#ibcon#read 5, iclass 3, count 0 2006.211.07:54:18.53#ibcon#about to read 6, iclass 3, count 0 2006.211.07:54:18.53#ibcon#read 6, iclass 3, count 0 2006.211.07:54:18.53#ibcon#end of sib2, iclass 3, count 0 2006.211.07:54:18.53#ibcon#*after write, iclass 3, count 0 2006.211.07:54:18.53#ibcon#*before return 0, iclass 3, count 0 2006.211.07:54:18.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:18.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:18.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:54:18.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:54:18.53$vc4f8/va=4,7 2006.211.07:54:18.53#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:54:18.53#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:54:18.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:18.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:18.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:18.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:18.59#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:54:18.59#ibcon#first serial, iclass 5, count 2 2006.211.07:54:18.59#ibcon#enter sib2, iclass 5, count 2 2006.211.07:54:18.59#ibcon#flushed, iclass 5, count 2 2006.211.07:54:18.59#ibcon#about to write, iclass 5, count 2 2006.211.07:54:18.59#ibcon#wrote, iclass 5, count 2 2006.211.07:54:18.59#ibcon#about to read 3, iclass 5, count 2 2006.211.07:54:18.61#ibcon#read 3, iclass 5, count 2 2006.211.07:54:18.61#ibcon#about to read 4, iclass 5, count 2 2006.211.07:54:18.61#ibcon#read 4, iclass 5, count 2 2006.211.07:54:18.61#ibcon#about to read 5, iclass 5, count 2 2006.211.07:54:18.61#ibcon#read 5, iclass 5, count 2 2006.211.07:54:18.61#ibcon#about to read 6, iclass 5, count 2 2006.211.07:54:18.61#ibcon#read 6, iclass 5, count 2 2006.211.07:54:18.61#ibcon#end of sib2, iclass 5, count 2 2006.211.07:54:18.61#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:54:18.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:54:18.61#ibcon#[25=AT04-07\r\n] 2006.211.07:54:18.61#ibcon#*before write, iclass 5, count 2 2006.211.07:54:18.61#ibcon#enter sib2, iclass 5, count 2 2006.211.07:54:18.61#ibcon#flushed, iclass 5, count 2 2006.211.07:54:18.61#ibcon#about to write, iclass 5, count 2 2006.211.07:54:18.61#ibcon#wrote, iclass 5, count 2 2006.211.07:54:18.61#ibcon#about to read 3, iclass 5, count 2 2006.211.07:54:18.64#ibcon#read 3, iclass 5, count 2 2006.211.07:54:18.64#ibcon#about to read 4, iclass 5, count 2 2006.211.07:54:18.64#ibcon#read 4, iclass 5, count 2 2006.211.07:54:18.64#ibcon#about to read 5, iclass 5, count 2 2006.211.07:54:18.64#ibcon#read 5, iclass 5, count 2 2006.211.07:54:18.64#ibcon#about to read 6, iclass 5, count 2 2006.211.07:54:18.64#ibcon#read 6, iclass 5, count 2 2006.211.07:54:18.64#ibcon#end of sib2, iclass 5, count 2 2006.211.07:54:18.64#ibcon#*after write, iclass 5, count 2 2006.211.07:54:18.64#ibcon#*before return 0, iclass 5, count 2 2006.211.07:54:18.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:18.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:18.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:54:18.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:18.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:18.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:18.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:18.76#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:54:18.76#ibcon#first serial, iclass 5, count 0 2006.211.07:54:18.76#ibcon#enter sib2, iclass 5, count 0 2006.211.07:54:18.76#ibcon#flushed, iclass 5, count 0 2006.211.07:54:18.76#ibcon#about to write, iclass 5, count 0 2006.211.07:54:18.76#ibcon#wrote, iclass 5, count 0 2006.211.07:54:18.76#ibcon#about to read 3, iclass 5, count 0 2006.211.07:54:18.78#ibcon#read 3, iclass 5, count 0 2006.211.07:54:18.78#ibcon#about to read 4, iclass 5, count 0 2006.211.07:54:18.78#ibcon#read 4, iclass 5, count 0 2006.211.07:54:18.78#ibcon#about to read 5, iclass 5, count 0 2006.211.07:54:18.78#ibcon#read 5, iclass 5, count 0 2006.211.07:54:18.78#ibcon#about to read 6, iclass 5, count 0 2006.211.07:54:18.78#ibcon#read 6, iclass 5, count 0 2006.211.07:54:18.78#ibcon#end of sib2, iclass 5, count 0 2006.211.07:54:18.78#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:54:18.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:54:18.78#ibcon#[25=USB\r\n] 2006.211.07:54:18.78#ibcon#*before write, iclass 5, count 0 2006.211.07:54:18.78#ibcon#enter sib2, iclass 5, count 0 2006.211.07:54:18.78#ibcon#flushed, iclass 5, count 0 2006.211.07:54:18.78#ibcon#about to write, iclass 5, count 0 2006.211.07:54:18.78#ibcon#wrote, iclass 5, count 0 2006.211.07:54:18.78#ibcon#about to read 3, iclass 5, count 0 2006.211.07:54:18.81#ibcon#read 3, iclass 5, count 0 2006.211.07:54:18.81#ibcon#about to read 4, iclass 5, count 0 2006.211.07:54:18.81#ibcon#read 4, iclass 5, count 0 2006.211.07:54:18.81#ibcon#about to read 5, iclass 5, count 0 2006.211.07:54:18.81#ibcon#read 5, iclass 5, count 0 2006.211.07:54:18.81#ibcon#about to read 6, iclass 5, count 0 2006.211.07:54:18.81#ibcon#read 6, iclass 5, count 0 2006.211.07:54:18.81#ibcon#end of sib2, iclass 5, count 0 2006.211.07:54:18.81#ibcon#*after write, iclass 5, count 0 2006.211.07:54:18.81#ibcon#*before return 0, iclass 5, count 0 2006.211.07:54:18.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:18.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:18.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:54:18.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:54:18.81$vc4f8/valo=5,652.99 2006.211.07:54:18.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:54:18.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:54:18.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:18.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:18.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:18.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:18.81#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:54:18.81#ibcon#first serial, iclass 7, count 0 2006.211.07:54:18.81#ibcon#enter sib2, iclass 7, count 0 2006.211.07:54:18.81#ibcon#flushed, iclass 7, count 0 2006.211.07:54:18.81#ibcon#about to write, iclass 7, count 0 2006.211.07:54:18.81#ibcon#wrote, iclass 7, count 0 2006.211.07:54:18.81#ibcon#about to read 3, iclass 7, count 0 2006.211.07:54:18.83#ibcon#read 3, iclass 7, count 0 2006.211.07:54:18.83#ibcon#about to read 4, iclass 7, count 0 2006.211.07:54:18.83#ibcon#read 4, iclass 7, count 0 2006.211.07:54:18.83#ibcon#about to read 5, iclass 7, count 0 2006.211.07:54:18.83#ibcon#read 5, iclass 7, count 0 2006.211.07:54:18.83#ibcon#about to read 6, iclass 7, count 0 2006.211.07:54:18.83#ibcon#read 6, iclass 7, count 0 2006.211.07:54:18.83#ibcon#end of sib2, iclass 7, count 0 2006.211.07:54:18.83#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:54:18.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:54:18.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:54:18.83#ibcon#*before write, iclass 7, count 0 2006.211.07:54:18.83#ibcon#enter sib2, iclass 7, count 0 2006.211.07:54:18.83#ibcon#flushed, iclass 7, count 0 2006.211.07:54:18.83#ibcon#about to write, iclass 7, count 0 2006.211.07:54:18.83#ibcon#wrote, iclass 7, count 0 2006.211.07:54:18.83#ibcon#about to read 3, iclass 7, count 0 2006.211.07:54:18.87#ibcon#read 3, iclass 7, count 0 2006.211.07:54:18.87#ibcon#about to read 4, iclass 7, count 0 2006.211.07:54:18.87#ibcon#read 4, iclass 7, count 0 2006.211.07:54:18.87#ibcon#about to read 5, iclass 7, count 0 2006.211.07:54:18.87#ibcon#read 5, iclass 7, count 0 2006.211.07:54:18.87#ibcon#about to read 6, iclass 7, count 0 2006.211.07:54:18.87#ibcon#read 6, iclass 7, count 0 2006.211.07:54:18.87#ibcon#end of sib2, iclass 7, count 0 2006.211.07:54:18.87#ibcon#*after write, iclass 7, count 0 2006.211.07:54:18.87#ibcon#*before return 0, iclass 7, count 0 2006.211.07:54:18.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:18.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:18.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:54:18.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:54:18.87$vc4f8/va=5,7 2006.211.07:54:18.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:54:18.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:54:18.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:18.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:18.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:18.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:18.93#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:54:18.93#ibcon#first serial, iclass 11, count 2 2006.211.07:54:18.93#ibcon#enter sib2, iclass 11, count 2 2006.211.07:54:18.93#ibcon#flushed, iclass 11, count 2 2006.211.07:54:18.93#ibcon#about to write, iclass 11, count 2 2006.211.07:54:18.93#ibcon#wrote, iclass 11, count 2 2006.211.07:54:18.93#ibcon#about to read 3, iclass 11, count 2 2006.211.07:54:18.95#ibcon#read 3, iclass 11, count 2 2006.211.07:54:18.95#ibcon#about to read 4, iclass 11, count 2 2006.211.07:54:18.95#ibcon#read 4, iclass 11, count 2 2006.211.07:54:18.95#ibcon#about to read 5, iclass 11, count 2 2006.211.07:54:18.95#ibcon#read 5, iclass 11, count 2 2006.211.07:54:18.95#ibcon#about to read 6, iclass 11, count 2 2006.211.07:54:18.95#ibcon#read 6, iclass 11, count 2 2006.211.07:54:18.95#ibcon#end of sib2, iclass 11, count 2 2006.211.07:54:18.95#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:54:18.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:54:18.95#ibcon#[25=AT05-07\r\n] 2006.211.07:54:18.95#ibcon#*before write, iclass 11, count 2 2006.211.07:54:18.95#ibcon#enter sib2, iclass 11, count 2 2006.211.07:54:18.95#ibcon#flushed, iclass 11, count 2 2006.211.07:54:18.95#ibcon#about to write, iclass 11, count 2 2006.211.07:54:18.95#ibcon#wrote, iclass 11, count 2 2006.211.07:54:18.95#ibcon#about to read 3, iclass 11, count 2 2006.211.07:54:18.98#ibcon#read 3, iclass 11, count 2 2006.211.07:54:18.98#ibcon#about to read 4, iclass 11, count 2 2006.211.07:54:18.98#ibcon#read 4, iclass 11, count 2 2006.211.07:54:18.98#ibcon#about to read 5, iclass 11, count 2 2006.211.07:54:18.98#ibcon#read 5, iclass 11, count 2 2006.211.07:54:18.98#ibcon#about to read 6, iclass 11, count 2 2006.211.07:54:18.98#ibcon#read 6, iclass 11, count 2 2006.211.07:54:18.98#ibcon#end of sib2, iclass 11, count 2 2006.211.07:54:18.98#ibcon#*after write, iclass 11, count 2 2006.211.07:54:18.98#ibcon#*before return 0, iclass 11, count 2 2006.211.07:54:18.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:18.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:18.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:54:18.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:18.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:19.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:19.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:19.10#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:54:19.10#ibcon#first serial, iclass 11, count 0 2006.211.07:54:19.10#ibcon#enter sib2, iclass 11, count 0 2006.211.07:54:19.10#ibcon#flushed, iclass 11, count 0 2006.211.07:54:19.10#ibcon#about to write, iclass 11, count 0 2006.211.07:54:19.10#ibcon#wrote, iclass 11, count 0 2006.211.07:54:19.10#ibcon#about to read 3, iclass 11, count 0 2006.211.07:54:19.12#ibcon#read 3, iclass 11, count 0 2006.211.07:54:19.12#ibcon#about to read 4, iclass 11, count 0 2006.211.07:54:19.12#ibcon#read 4, iclass 11, count 0 2006.211.07:54:19.12#ibcon#about to read 5, iclass 11, count 0 2006.211.07:54:19.12#ibcon#read 5, iclass 11, count 0 2006.211.07:54:19.12#ibcon#about to read 6, iclass 11, count 0 2006.211.07:54:19.12#ibcon#read 6, iclass 11, count 0 2006.211.07:54:19.12#ibcon#end of sib2, iclass 11, count 0 2006.211.07:54:19.12#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:54:19.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:54:19.12#ibcon#[25=USB\r\n] 2006.211.07:54:19.12#ibcon#*before write, iclass 11, count 0 2006.211.07:54:19.12#ibcon#enter sib2, iclass 11, count 0 2006.211.07:54:19.12#ibcon#flushed, iclass 11, count 0 2006.211.07:54:19.12#ibcon#about to write, iclass 11, count 0 2006.211.07:54:19.12#ibcon#wrote, iclass 11, count 0 2006.211.07:54:19.12#ibcon#about to read 3, iclass 11, count 0 2006.211.07:54:19.15#ibcon#read 3, iclass 11, count 0 2006.211.07:54:19.15#ibcon#about to read 4, iclass 11, count 0 2006.211.07:54:19.15#ibcon#read 4, iclass 11, count 0 2006.211.07:54:19.15#ibcon#about to read 5, iclass 11, count 0 2006.211.07:54:19.15#ibcon#read 5, iclass 11, count 0 2006.211.07:54:19.15#ibcon#about to read 6, iclass 11, count 0 2006.211.07:54:19.15#ibcon#read 6, iclass 11, count 0 2006.211.07:54:19.15#ibcon#end of sib2, iclass 11, count 0 2006.211.07:54:19.15#ibcon#*after write, iclass 11, count 0 2006.211.07:54:19.15#ibcon#*before return 0, iclass 11, count 0 2006.211.07:54:19.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:19.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:19.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:54:19.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:54:19.15$vc4f8/valo=6,772.99 2006.211.07:54:19.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:54:19.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:54:19.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:19.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:19.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:19.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:19.15#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:54:19.15#ibcon#first serial, iclass 13, count 0 2006.211.07:54:19.15#ibcon#enter sib2, iclass 13, count 0 2006.211.07:54:19.15#ibcon#flushed, iclass 13, count 0 2006.211.07:54:19.15#ibcon#about to write, iclass 13, count 0 2006.211.07:54:19.15#ibcon#wrote, iclass 13, count 0 2006.211.07:54:19.15#ibcon#about to read 3, iclass 13, count 0 2006.211.07:54:19.17#ibcon#read 3, iclass 13, count 0 2006.211.07:54:19.17#ibcon#about to read 4, iclass 13, count 0 2006.211.07:54:19.17#ibcon#read 4, iclass 13, count 0 2006.211.07:54:19.17#ibcon#about to read 5, iclass 13, count 0 2006.211.07:54:19.17#ibcon#read 5, iclass 13, count 0 2006.211.07:54:19.17#ibcon#about to read 6, iclass 13, count 0 2006.211.07:54:19.17#ibcon#read 6, iclass 13, count 0 2006.211.07:54:19.17#ibcon#end of sib2, iclass 13, count 0 2006.211.07:54:19.17#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:54:19.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:54:19.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:54:19.17#ibcon#*before write, iclass 13, count 0 2006.211.07:54:19.17#ibcon#enter sib2, iclass 13, count 0 2006.211.07:54:19.17#ibcon#flushed, iclass 13, count 0 2006.211.07:54:19.17#ibcon#about to write, iclass 13, count 0 2006.211.07:54:19.17#ibcon#wrote, iclass 13, count 0 2006.211.07:54:19.17#ibcon#about to read 3, iclass 13, count 0 2006.211.07:54:19.21#ibcon#read 3, iclass 13, count 0 2006.211.07:54:19.21#ibcon#about to read 4, iclass 13, count 0 2006.211.07:54:19.21#ibcon#read 4, iclass 13, count 0 2006.211.07:54:19.21#ibcon#about to read 5, iclass 13, count 0 2006.211.07:54:19.21#ibcon#read 5, iclass 13, count 0 2006.211.07:54:19.21#ibcon#about to read 6, iclass 13, count 0 2006.211.07:54:19.21#ibcon#read 6, iclass 13, count 0 2006.211.07:54:19.21#ibcon#end of sib2, iclass 13, count 0 2006.211.07:54:19.21#ibcon#*after write, iclass 13, count 0 2006.211.07:54:19.21#ibcon#*before return 0, iclass 13, count 0 2006.211.07:54:19.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:19.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:19.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:54:19.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:54:19.21$vc4f8/va=6,6 2006.211.07:54:19.21#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.07:54:19.21#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.07:54:19.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:19.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:54:19.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:54:19.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:54:19.27#ibcon#enter wrdev, iclass 15, count 2 2006.211.07:54:19.27#ibcon#first serial, iclass 15, count 2 2006.211.07:54:19.27#ibcon#enter sib2, iclass 15, count 2 2006.211.07:54:19.27#ibcon#flushed, iclass 15, count 2 2006.211.07:54:19.27#ibcon#about to write, iclass 15, count 2 2006.211.07:54:19.27#ibcon#wrote, iclass 15, count 2 2006.211.07:54:19.27#ibcon#about to read 3, iclass 15, count 2 2006.211.07:54:19.29#ibcon#read 3, iclass 15, count 2 2006.211.07:54:19.29#ibcon#about to read 4, iclass 15, count 2 2006.211.07:54:19.29#ibcon#read 4, iclass 15, count 2 2006.211.07:54:19.29#ibcon#about to read 5, iclass 15, count 2 2006.211.07:54:19.29#ibcon#read 5, iclass 15, count 2 2006.211.07:54:19.29#ibcon#about to read 6, iclass 15, count 2 2006.211.07:54:19.29#ibcon#read 6, iclass 15, count 2 2006.211.07:54:19.29#ibcon#end of sib2, iclass 15, count 2 2006.211.07:54:19.29#ibcon#*mode == 0, iclass 15, count 2 2006.211.07:54:19.29#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.07:54:19.29#ibcon#[25=AT06-06\r\n] 2006.211.07:54:19.29#ibcon#*before write, iclass 15, count 2 2006.211.07:54:19.29#ibcon#enter sib2, iclass 15, count 2 2006.211.07:54:19.29#ibcon#flushed, iclass 15, count 2 2006.211.07:54:19.29#ibcon#about to write, iclass 15, count 2 2006.211.07:54:19.29#ibcon#wrote, iclass 15, count 2 2006.211.07:54:19.29#ibcon#about to read 3, iclass 15, count 2 2006.211.07:54:19.32#ibcon#read 3, iclass 15, count 2 2006.211.07:54:19.32#ibcon#about to read 4, iclass 15, count 2 2006.211.07:54:19.32#ibcon#read 4, iclass 15, count 2 2006.211.07:54:19.32#ibcon#about to read 5, iclass 15, count 2 2006.211.07:54:19.32#ibcon#read 5, iclass 15, count 2 2006.211.07:54:19.32#ibcon#about to read 6, iclass 15, count 2 2006.211.07:54:19.32#ibcon#read 6, iclass 15, count 2 2006.211.07:54:19.32#ibcon#end of sib2, iclass 15, count 2 2006.211.07:54:19.32#ibcon#*after write, iclass 15, count 2 2006.211.07:54:19.32#ibcon#*before return 0, iclass 15, count 2 2006.211.07:54:19.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:54:19.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.07:54:19.32#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.07:54:19.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:19.32#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:54:19.44#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:54:19.44#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:54:19.44#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:54:19.44#ibcon#first serial, iclass 15, count 0 2006.211.07:54:19.44#ibcon#enter sib2, iclass 15, count 0 2006.211.07:54:19.44#ibcon#flushed, iclass 15, count 0 2006.211.07:54:19.44#ibcon#about to write, iclass 15, count 0 2006.211.07:54:19.44#ibcon#wrote, iclass 15, count 0 2006.211.07:54:19.44#ibcon#about to read 3, iclass 15, count 0 2006.211.07:54:19.46#ibcon#read 3, iclass 15, count 0 2006.211.07:54:19.46#ibcon#about to read 4, iclass 15, count 0 2006.211.07:54:19.46#ibcon#read 4, iclass 15, count 0 2006.211.07:54:19.46#ibcon#about to read 5, iclass 15, count 0 2006.211.07:54:19.46#ibcon#read 5, iclass 15, count 0 2006.211.07:54:19.46#ibcon#about to read 6, iclass 15, count 0 2006.211.07:54:19.46#ibcon#read 6, iclass 15, count 0 2006.211.07:54:19.46#ibcon#end of sib2, iclass 15, count 0 2006.211.07:54:19.46#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:54:19.46#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:54:19.46#ibcon#[25=USB\r\n] 2006.211.07:54:19.46#ibcon#*before write, iclass 15, count 0 2006.211.07:54:19.46#ibcon#enter sib2, iclass 15, count 0 2006.211.07:54:19.46#ibcon#flushed, iclass 15, count 0 2006.211.07:54:19.46#ibcon#about to write, iclass 15, count 0 2006.211.07:54:19.46#ibcon#wrote, iclass 15, count 0 2006.211.07:54:19.46#ibcon#about to read 3, iclass 15, count 0 2006.211.07:54:19.49#ibcon#read 3, iclass 15, count 0 2006.211.07:54:19.49#ibcon#about to read 4, iclass 15, count 0 2006.211.07:54:19.49#ibcon#read 4, iclass 15, count 0 2006.211.07:54:19.49#ibcon#about to read 5, iclass 15, count 0 2006.211.07:54:19.49#ibcon#read 5, iclass 15, count 0 2006.211.07:54:19.49#ibcon#about to read 6, iclass 15, count 0 2006.211.07:54:19.49#ibcon#read 6, iclass 15, count 0 2006.211.07:54:19.49#ibcon#end of sib2, iclass 15, count 0 2006.211.07:54:19.49#ibcon#*after write, iclass 15, count 0 2006.211.07:54:19.49#ibcon#*before return 0, iclass 15, count 0 2006.211.07:54:19.49#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:54:19.49#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.07:54:19.49#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:54:19.49#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:54:19.49$vc4f8/valo=7,832.99 2006.211.07:54:19.49#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.07:54:19.49#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.07:54:19.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:19.49#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:54:19.49#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:54:19.49#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:54:19.49#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:54:19.49#ibcon#first serial, iclass 17, count 0 2006.211.07:54:19.49#ibcon#enter sib2, iclass 17, count 0 2006.211.07:54:19.49#ibcon#flushed, iclass 17, count 0 2006.211.07:54:19.49#ibcon#about to write, iclass 17, count 0 2006.211.07:54:19.49#ibcon#wrote, iclass 17, count 0 2006.211.07:54:19.49#ibcon#about to read 3, iclass 17, count 0 2006.211.07:54:19.51#ibcon#read 3, iclass 17, count 0 2006.211.07:54:19.51#ibcon#about to read 4, iclass 17, count 0 2006.211.07:54:19.51#ibcon#read 4, iclass 17, count 0 2006.211.07:54:19.51#ibcon#about to read 5, iclass 17, count 0 2006.211.07:54:19.51#ibcon#read 5, iclass 17, count 0 2006.211.07:54:19.51#ibcon#about to read 6, iclass 17, count 0 2006.211.07:54:19.51#ibcon#read 6, iclass 17, count 0 2006.211.07:54:19.51#ibcon#end of sib2, iclass 17, count 0 2006.211.07:54:19.51#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:54:19.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:54:19.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:54:19.51#ibcon#*before write, iclass 17, count 0 2006.211.07:54:19.51#ibcon#enter sib2, iclass 17, count 0 2006.211.07:54:19.51#ibcon#flushed, iclass 17, count 0 2006.211.07:54:19.51#ibcon#about to write, iclass 17, count 0 2006.211.07:54:19.51#ibcon#wrote, iclass 17, count 0 2006.211.07:54:19.51#ibcon#about to read 3, iclass 17, count 0 2006.211.07:54:19.55#ibcon#read 3, iclass 17, count 0 2006.211.07:54:19.55#ibcon#about to read 4, iclass 17, count 0 2006.211.07:54:19.55#ibcon#read 4, iclass 17, count 0 2006.211.07:54:19.55#ibcon#about to read 5, iclass 17, count 0 2006.211.07:54:19.55#ibcon#read 5, iclass 17, count 0 2006.211.07:54:19.55#ibcon#about to read 6, iclass 17, count 0 2006.211.07:54:19.55#ibcon#read 6, iclass 17, count 0 2006.211.07:54:19.55#ibcon#end of sib2, iclass 17, count 0 2006.211.07:54:19.55#ibcon#*after write, iclass 17, count 0 2006.211.07:54:19.55#ibcon#*before return 0, iclass 17, count 0 2006.211.07:54:19.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:54:19.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.07:54:19.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:54:19.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:54:19.55$vc4f8/va=7,6 2006.211.07:54:19.55#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.07:54:19.55#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.07:54:19.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:19.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:54:19.61#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:54:19.61#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:54:19.61#ibcon#enter wrdev, iclass 19, count 2 2006.211.07:54:19.61#ibcon#first serial, iclass 19, count 2 2006.211.07:54:19.61#ibcon#enter sib2, iclass 19, count 2 2006.211.07:54:19.61#ibcon#flushed, iclass 19, count 2 2006.211.07:54:19.61#ibcon#about to write, iclass 19, count 2 2006.211.07:54:19.61#ibcon#wrote, iclass 19, count 2 2006.211.07:54:19.61#ibcon#about to read 3, iclass 19, count 2 2006.211.07:54:19.63#ibcon#read 3, iclass 19, count 2 2006.211.07:54:19.63#ibcon#about to read 4, iclass 19, count 2 2006.211.07:54:19.63#ibcon#read 4, iclass 19, count 2 2006.211.07:54:19.63#ibcon#about to read 5, iclass 19, count 2 2006.211.07:54:19.63#ibcon#read 5, iclass 19, count 2 2006.211.07:54:19.63#ibcon#about to read 6, iclass 19, count 2 2006.211.07:54:19.63#ibcon#read 6, iclass 19, count 2 2006.211.07:54:19.63#ibcon#end of sib2, iclass 19, count 2 2006.211.07:54:19.63#ibcon#*mode == 0, iclass 19, count 2 2006.211.07:54:19.63#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.07:54:19.63#ibcon#[25=AT07-06\r\n] 2006.211.07:54:19.63#ibcon#*before write, iclass 19, count 2 2006.211.07:54:19.63#ibcon#enter sib2, iclass 19, count 2 2006.211.07:54:19.63#ibcon#flushed, iclass 19, count 2 2006.211.07:54:19.63#ibcon#about to write, iclass 19, count 2 2006.211.07:54:19.63#ibcon#wrote, iclass 19, count 2 2006.211.07:54:19.63#ibcon#about to read 3, iclass 19, count 2 2006.211.07:54:19.66#ibcon#read 3, iclass 19, count 2 2006.211.07:54:19.66#ibcon#about to read 4, iclass 19, count 2 2006.211.07:54:19.66#ibcon#read 4, iclass 19, count 2 2006.211.07:54:19.66#ibcon#about to read 5, iclass 19, count 2 2006.211.07:54:19.66#ibcon#read 5, iclass 19, count 2 2006.211.07:54:19.66#ibcon#about to read 6, iclass 19, count 2 2006.211.07:54:19.66#ibcon#read 6, iclass 19, count 2 2006.211.07:54:19.66#ibcon#end of sib2, iclass 19, count 2 2006.211.07:54:19.66#ibcon#*after write, iclass 19, count 2 2006.211.07:54:19.66#ibcon#*before return 0, iclass 19, count 2 2006.211.07:54:19.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:54:19.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.07:54:19.66#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.07:54:19.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:19.66#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:54:19.78#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:54:19.78#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:54:19.78#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:54:19.78#ibcon#first serial, iclass 19, count 0 2006.211.07:54:19.78#ibcon#enter sib2, iclass 19, count 0 2006.211.07:54:19.78#ibcon#flushed, iclass 19, count 0 2006.211.07:54:19.78#ibcon#about to write, iclass 19, count 0 2006.211.07:54:19.78#ibcon#wrote, iclass 19, count 0 2006.211.07:54:19.78#ibcon#about to read 3, iclass 19, count 0 2006.211.07:54:19.80#ibcon#read 3, iclass 19, count 0 2006.211.07:54:19.80#ibcon#about to read 4, iclass 19, count 0 2006.211.07:54:19.80#ibcon#read 4, iclass 19, count 0 2006.211.07:54:19.80#ibcon#about to read 5, iclass 19, count 0 2006.211.07:54:19.80#ibcon#read 5, iclass 19, count 0 2006.211.07:54:19.80#ibcon#about to read 6, iclass 19, count 0 2006.211.07:54:19.80#ibcon#read 6, iclass 19, count 0 2006.211.07:54:19.80#ibcon#end of sib2, iclass 19, count 0 2006.211.07:54:19.80#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:54:19.80#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:54:19.80#ibcon#[25=USB\r\n] 2006.211.07:54:19.80#ibcon#*before write, iclass 19, count 0 2006.211.07:54:19.80#ibcon#enter sib2, iclass 19, count 0 2006.211.07:54:19.80#ibcon#flushed, iclass 19, count 0 2006.211.07:54:19.80#ibcon#about to write, iclass 19, count 0 2006.211.07:54:19.80#ibcon#wrote, iclass 19, count 0 2006.211.07:54:19.80#ibcon#about to read 3, iclass 19, count 0 2006.211.07:54:19.83#ibcon#read 3, iclass 19, count 0 2006.211.07:54:19.83#ibcon#about to read 4, iclass 19, count 0 2006.211.07:54:19.83#ibcon#read 4, iclass 19, count 0 2006.211.07:54:19.83#ibcon#about to read 5, iclass 19, count 0 2006.211.07:54:19.83#ibcon#read 5, iclass 19, count 0 2006.211.07:54:19.83#ibcon#about to read 6, iclass 19, count 0 2006.211.07:54:19.83#ibcon#read 6, iclass 19, count 0 2006.211.07:54:19.83#ibcon#end of sib2, iclass 19, count 0 2006.211.07:54:19.83#ibcon#*after write, iclass 19, count 0 2006.211.07:54:19.83#ibcon#*before return 0, iclass 19, count 0 2006.211.07:54:19.83#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:54:19.83#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.07:54:19.83#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:54:19.83#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:54:19.83$vc4f8/valo=8,852.99 2006.211.07:54:19.83#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.07:54:19.83#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.07:54:19.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:19.83#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:54:19.83#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:54:19.83#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:54:19.83#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:54:19.83#ibcon#first serial, iclass 21, count 0 2006.211.07:54:19.83#ibcon#enter sib2, iclass 21, count 0 2006.211.07:54:19.83#ibcon#flushed, iclass 21, count 0 2006.211.07:54:19.83#ibcon#about to write, iclass 21, count 0 2006.211.07:54:19.83#ibcon#wrote, iclass 21, count 0 2006.211.07:54:19.83#ibcon#about to read 3, iclass 21, count 0 2006.211.07:54:19.85#ibcon#read 3, iclass 21, count 0 2006.211.07:54:19.85#ibcon#about to read 4, iclass 21, count 0 2006.211.07:54:19.85#ibcon#read 4, iclass 21, count 0 2006.211.07:54:19.85#ibcon#about to read 5, iclass 21, count 0 2006.211.07:54:19.85#ibcon#read 5, iclass 21, count 0 2006.211.07:54:19.85#ibcon#about to read 6, iclass 21, count 0 2006.211.07:54:19.85#ibcon#read 6, iclass 21, count 0 2006.211.07:54:19.85#ibcon#end of sib2, iclass 21, count 0 2006.211.07:54:19.85#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:54:19.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:54:19.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:54:19.85#ibcon#*before write, iclass 21, count 0 2006.211.07:54:19.85#ibcon#enter sib2, iclass 21, count 0 2006.211.07:54:19.85#ibcon#flushed, iclass 21, count 0 2006.211.07:54:19.85#ibcon#about to write, iclass 21, count 0 2006.211.07:54:19.85#ibcon#wrote, iclass 21, count 0 2006.211.07:54:19.85#ibcon#about to read 3, iclass 21, count 0 2006.211.07:54:19.89#ibcon#read 3, iclass 21, count 0 2006.211.07:54:19.89#ibcon#about to read 4, iclass 21, count 0 2006.211.07:54:19.89#ibcon#read 4, iclass 21, count 0 2006.211.07:54:19.89#ibcon#about to read 5, iclass 21, count 0 2006.211.07:54:19.89#ibcon#read 5, iclass 21, count 0 2006.211.07:54:19.89#ibcon#about to read 6, iclass 21, count 0 2006.211.07:54:19.89#ibcon#read 6, iclass 21, count 0 2006.211.07:54:19.89#ibcon#end of sib2, iclass 21, count 0 2006.211.07:54:19.89#ibcon#*after write, iclass 21, count 0 2006.211.07:54:19.89#ibcon#*before return 0, iclass 21, count 0 2006.211.07:54:19.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:54:19.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.07:54:19.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:54:19.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:54:19.89$vc4f8/va=8,7 2006.211.07:54:19.89#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.07:54:19.89#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.07:54:19.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:19.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:54:19.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:54:19.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:54:19.95#ibcon#enter wrdev, iclass 23, count 2 2006.211.07:54:19.95#ibcon#first serial, iclass 23, count 2 2006.211.07:54:19.95#ibcon#enter sib2, iclass 23, count 2 2006.211.07:54:19.95#ibcon#flushed, iclass 23, count 2 2006.211.07:54:19.95#ibcon#about to write, iclass 23, count 2 2006.211.07:54:19.95#ibcon#wrote, iclass 23, count 2 2006.211.07:54:19.95#ibcon#about to read 3, iclass 23, count 2 2006.211.07:54:19.97#ibcon#read 3, iclass 23, count 2 2006.211.07:54:19.97#ibcon#about to read 4, iclass 23, count 2 2006.211.07:54:19.97#ibcon#read 4, iclass 23, count 2 2006.211.07:54:19.97#ibcon#about to read 5, iclass 23, count 2 2006.211.07:54:19.97#ibcon#read 5, iclass 23, count 2 2006.211.07:54:19.97#ibcon#about to read 6, iclass 23, count 2 2006.211.07:54:19.97#ibcon#read 6, iclass 23, count 2 2006.211.07:54:19.97#ibcon#end of sib2, iclass 23, count 2 2006.211.07:54:19.97#ibcon#*mode == 0, iclass 23, count 2 2006.211.07:54:19.97#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.07:54:19.97#ibcon#[25=AT08-07\r\n] 2006.211.07:54:19.97#ibcon#*before write, iclass 23, count 2 2006.211.07:54:19.97#ibcon#enter sib2, iclass 23, count 2 2006.211.07:54:19.97#ibcon#flushed, iclass 23, count 2 2006.211.07:54:19.97#ibcon#about to write, iclass 23, count 2 2006.211.07:54:19.97#ibcon#wrote, iclass 23, count 2 2006.211.07:54:19.97#ibcon#about to read 3, iclass 23, count 2 2006.211.07:54:20.00#ibcon#read 3, iclass 23, count 2 2006.211.07:54:20.00#ibcon#about to read 4, iclass 23, count 2 2006.211.07:54:20.00#ibcon#read 4, iclass 23, count 2 2006.211.07:54:20.00#ibcon#about to read 5, iclass 23, count 2 2006.211.07:54:20.00#ibcon#read 5, iclass 23, count 2 2006.211.07:54:20.00#ibcon#about to read 6, iclass 23, count 2 2006.211.07:54:20.00#ibcon#read 6, iclass 23, count 2 2006.211.07:54:20.00#ibcon#end of sib2, iclass 23, count 2 2006.211.07:54:20.00#ibcon#*after write, iclass 23, count 2 2006.211.07:54:20.00#ibcon#*before return 0, iclass 23, count 2 2006.211.07:54:20.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:54:20.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.07:54:20.00#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.07:54:20.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:20.00#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:54:20.12#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:54:20.12#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:54:20.12#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:54:20.12#ibcon#first serial, iclass 23, count 0 2006.211.07:54:20.12#ibcon#enter sib2, iclass 23, count 0 2006.211.07:54:20.12#ibcon#flushed, iclass 23, count 0 2006.211.07:54:20.12#ibcon#about to write, iclass 23, count 0 2006.211.07:54:20.12#ibcon#wrote, iclass 23, count 0 2006.211.07:54:20.12#ibcon#about to read 3, iclass 23, count 0 2006.211.07:54:20.14#ibcon#read 3, iclass 23, count 0 2006.211.07:54:20.14#ibcon#about to read 4, iclass 23, count 0 2006.211.07:54:20.14#ibcon#read 4, iclass 23, count 0 2006.211.07:54:20.14#ibcon#about to read 5, iclass 23, count 0 2006.211.07:54:20.14#ibcon#read 5, iclass 23, count 0 2006.211.07:54:20.14#ibcon#about to read 6, iclass 23, count 0 2006.211.07:54:20.14#ibcon#read 6, iclass 23, count 0 2006.211.07:54:20.14#ibcon#end of sib2, iclass 23, count 0 2006.211.07:54:20.14#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:54:20.14#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:54:20.14#ibcon#[25=USB\r\n] 2006.211.07:54:20.14#ibcon#*before write, iclass 23, count 0 2006.211.07:54:20.14#ibcon#enter sib2, iclass 23, count 0 2006.211.07:54:20.14#ibcon#flushed, iclass 23, count 0 2006.211.07:54:20.14#ibcon#about to write, iclass 23, count 0 2006.211.07:54:20.14#ibcon#wrote, iclass 23, count 0 2006.211.07:54:20.14#ibcon#about to read 3, iclass 23, count 0 2006.211.07:54:20.17#ibcon#read 3, iclass 23, count 0 2006.211.07:54:20.17#ibcon#about to read 4, iclass 23, count 0 2006.211.07:54:20.17#ibcon#read 4, iclass 23, count 0 2006.211.07:54:20.17#ibcon#about to read 5, iclass 23, count 0 2006.211.07:54:20.17#ibcon#read 5, iclass 23, count 0 2006.211.07:54:20.17#ibcon#about to read 6, iclass 23, count 0 2006.211.07:54:20.17#ibcon#read 6, iclass 23, count 0 2006.211.07:54:20.17#ibcon#end of sib2, iclass 23, count 0 2006.211.07:54:20.17#ibcon#*after write, iclass 23, count 0 2006.211.07:54:20.17#ibcon#*before return 0, iclass 23, count 0 2006.211.07:54:20.17#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:54:20.17#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.07:54:20.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:54:20.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:54:20.17$vc4f8/vblo=1,632.99 2006.211.07:54:20.17#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.07:54:20.17#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.07:54:20.17#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:20.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:54:20.17#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:54:20.17#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:54:20.17#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:54:20.17#ibcon#first serial, iclass 25, count 0 2006.211.07:54:20.17#ibcon#enter sib2, iclass 25, count 0 2006.211.07:54:20.17#ibcon#flushed, iclass 25, count 0 2006.211.07:54:20.17#ibcon#about to write, iclass 25, count 0 2006.211.07:54:20.17#ibcon#wrote, iclass 25, count 0 2006.211.07:54:20.17#ibcon#about to read 3, iclass 25, count 0 2006.211.07:54:20.19#ibcon#read 3, iclass 25, count 0 2006.211.07:54:20.19#ibcon#about to read 4, iclass 25, count 0 2006.211.07:54:20.19#ibcon#read 4, iclass 25, count 0 2006.211.07:54:20.19#ibcon#about to read 5, iclass 25, count 0 2006.211.07:54:20.19#ibcon#read 5, iclass 25, count 0 2006.211.07:54:20.19#ibcon#about to read 6, iclass 25, count 0 2006.211.07:54:20.19#ibcon#read 6, iclass 25, count 0 2006.211.07:54:20.19#ibcon#end of sib2, iclass 25, count 0 2006.211.07:54:20.19#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:54:20.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:54:20.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:54:20.19#ibcon#*before write, iclass 25, count 0 2006.211.07:54:20.19#ibcon#enter sib2, iclass 25, count 0 2006.211.07:54:20.19#ibcon#flushed, iclass 25, count 0 2006.211.07:54:20.19#ibcon#about to write, iclass 25, count 0 2006.211.07:54:20.19#ibcon#wrote, iclass 25, count 0 2006.211.07:54:20.19#ibcon#about to read 3, iclass 25, count 0 2006.211.07:54:20.23#ibcon#read 3, iclass 25, count 0 2006.211.07:54:20.23#ibcon#about to read 4, iclass 25, count 0 2006.211.07:54:20.23#ibcon#read 4, iclass 25, count 0 2006.211.07:54:20.23#ibcon#about to read 5, iclass 25, count 0 2006.211.07:54:20.23#ibcon#read 5, iclass 25, count 0 2006.211.07:54:20.23#ibcon#about to read 6, iclass 25, count 0 2006.211.07:54:20.23#ibcon#read 6, iclass 25, count 0 2006.211.07:54:20.23#ibcon#end of sib2, iclass 25, count 0 2006.211.07:54:20.23#ibcon#*after write, iclass 25, count 0 2006.211.07:54:20.23#ibcon#*before return 0, iclass 25, count 0 2006.211.07:54:20.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:54:20.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.07:54:20.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:54:20.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:54:20.23$vc4f8/vb=1,4 2006.211.07:54:20.23#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.07:54:20.23#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.07:54:20.23#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:20.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:54:20.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:54:20.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:54:20.23#ibcon#enter wrdev, iclass 27, count 2 2006.211.07:54:20.23#ibcon#first serial, iclass 27, count 2 2006.211.07:54:20.23#ibcon#enter sib2, iclass 27, count 2 2006.211.07:54:20.23#ibcon#flushed, iclass 27, count 2 2006.211.07:54:20.23#ibcon#about to write, iclass 27, count 2 2006.211.07:54:20.23#ibcon#wrote, iclass 27, count 2 2006.211.07:54:20.23#ibcon#about to read 3, iclass 27, count 2 2006.211.07:54:20.25#ibcon#read 3, iclass 27, count 2 2006.211.07:54:20.25#ibcon#about to read 4, iclass 27, count 2 2006.211.07:54:20.25#ibcon#read 4, iclass 27, count 2 2006.211.07:54:20.25#ibcon#about to read 5, iclass 27, count 2 2006.211.07:54:20.25#ibcon#read 5, iclass 27, count 2 2006.211.07:54:20.25#ibcon#about to read 6, iclass 27, count 2 2006.211.07:54:20.25#ibcon#read 6, iclass 27, count 2 2006.211.07:54:20.25#ibcon#end of sib2, iclass 27, count 2 2006.211.07:54:20.25#ibcon#*mode == 0, iclass 27, count 2 2006.211.07:54:20.25#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.07:54:20.25#ibcon#[27=AT01-04\r\n] 2006.211.07:54:20.25#ibcon#*before write, iclass 27, count 2 2006.211.07:54:20.25#ibcon#enter sib2, iclass 27, count 2 2006.211.07:54:20.25#ibcon#flushed, iclass 27, count 2 2006.211.07:54:20.25#ibcon#about to write, iclass 27, count 2 2006.211.07:54:20.25#ibcon#wrote, iclass 27, count 2 2006.211.07:54:20.25#ibcon#about to read 3, iclass 27, count 2 2006.211.07:54:20.28#ibcon#read 3, iclass 27, count 2 2006.211.07:54:20.28#ibcon#about to read 4, iclass 27, count 2 2006.211.07:54:20.28#ibcon#read 4, iclass 27, count 2 2006.211.07:54:20.28#ibcon#about to read 5, iclass 27, count 2 2006.211.07:54:20.28#ibcon#read 5, iclass 27, count 2 2006.211.07:54:20.28#ibcon#about to read 6, iclass 27, count 2 2006.211.07:54:20.28#ibcon#read 6, iclass 27, count 2 2006.211.07:54:20.28#ibcon#end of sib2, iclass 27, count 2 2006.211.07:54:20.28#ibcon#*after write, iclass 27, count 2 2006.211.07:54:20.28#ibcon#*before return 0, iclass 27, count 2 2006.211.07:54:20.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:54:20.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.07:54:20.28#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.07:54:20.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:20.28#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:54:20.40#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:54:20.40#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:54:20.40#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:54:20.40#ibcon#first serial, iclass 27, count 0 2006.211.07:54:20.40#ibcon#enter sib2, iclass 27, count 0 2006.211.07:54:20.40#ibcon#flushed, iclass 27, count 0 2006.211.07:54:20.40#ibcon#about to write, iclass 27, count 0 2006.211.07:54:20.40#ibcon#wrote, iclass 27, count 0 2006.211.07:54:20.40#ibcon#about to read 3, iclass 27, count 0 2006.211.07:54:20.42#ibcon#read 3, iclass 27, count 0 2006.211.07:54:20.42#ibcon#about to read 4, iclass 27, count 0 2006.211.07:54:20.42#ibcon#read 4, iclass 27, count 0 2006.211.07:54:20.42#ibcon#about to read 5, iclass 27, count 0 2006.211.07:54:20.42#ibcon#read 5, iclass 27, count 0 2006.211.07:54:20.42#ibcon#about to read 6, iclass 27, count 0 2006.211.07:54:20.42#ibcon#read 6, iclass 27, count 0 2006.211.07:54:20.42#ibcon#end of sib2, iclass 27, count 0 2006.211.07:54:20.42#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:54:20.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:54:20.42#ibcon#[27=USB\r\n] 2006.211.07:54:20.42#ibcon#*before write, iclass 27, count 0 2006.211.07:54:20.42#ibcon#enter sib2, iclass 27, count 0 2006.211.07:54:20.42#ibcon#flushed, iclass 27, count 0 2006.211.07:54:20.42#ibcon#about to write, iclass 27, count 0 2006.211.07:54:20.42#ibcon#wrote, iclass 27, count 0 2006.211.07:54:20.42#ibcon#about to read 3, iclass 27, count 0 2006.211.07:54:20.45#ibcon#read 3, iclass 27, count 0 2006.211.07:54:20.45#ibcon#about to read 4, iclass 27, count 0 2006.211.07:54:20.45#ibcon#read 4, iclass 27, count 0 2006.211.07:54:20.45#ibcon#about to read 5, iclass 27, count 0 2006.211.07:54:20.45#ibcon#read 5, iclass 27, count 0 2006.211.07:54:20.45#ibcon#about to read 6, iclass 27, count 0 2006.211.07:54:20.45#ibcon#read 6, iclass 27, count 0 2006.211.07:54:20.45#ibcon#end of sib2, iclass 27, count 0 2006.211.07:54:20.45#ibcon#*after write, iclass 27, count 0 2006.211.07:54:20.45#ibcon#*before return 0, iclass 27, count 0 2006.211.07:54:20.45#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:54:20.45#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.07:54:20.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:54:20.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:54:20.45$vc4f8/vblo=2,640.99 2006.211.07:54:20.45#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:54:20.45#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:54:20.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:20.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:20.45#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:20.45#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:20.45#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:54:20.45#ibcon#first serial, iclass 29, count 0 2006.211.07:54:20.45#ibcon#enter sib2, iclass 29, count 0 2006.211.07:54:20.45#ibcon#flushed, iclass 29, count 0 2006.211.07:54:20.45#ibcon#about to write, iclass 29, count 0 2006.211.07:54:20.45#ibcon#wrote, iclass 29, count 0 2006.211.07:54:20.45#ibcon#about to read 3, iclass 29, count 0 2006.211.07:54:20.47#ibcon#read 3, iclass 29, count 0 2006.211.07:54:20.47#ibcon#about to read 4, iclass 29, count 0 2006.211.07:54:20.47#ibcon#read 4, iclass 29, count 0 2006.211.07:54:20.47#ibcon#about to read 5, iclass 29, count 0 2006.211.07:54:20.47#ibcon#read 5, iclass 29, count 0 2006.211.07:54:20.47#ibcon#about to read 6, iclass 29, count 0 2006.211.07:54:20.47#ibcon#read 6, iclass 29, count 0 2006.211.07:54:20.47#ibcon#end of sib2, iclass 29, count 0 2006.211.07:54:20.47#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:54:20.47#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:54:20.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:54:20.47#ibcon#*before write, iclass 29, count 0 2006.211.07:54:20.47#ibcon#enter sib2, iclass 29, count 0 2006.211.07:54:20.47#ibcon#flushed, iclass 29, count 0 2006.211.07:54:20.47#ibcon#about to write, iclass 29, count 0 2006.211.07:54:20.47#ibcon#wrote, iclass 29, count 0 2006.211.07:54:20.47#ibcon#about to read 3, iclass 29, count 0 2006.211.07:54:20.51#ibcon#read 3, iclass 29, count 0 2006.211.07:54:20.51#ibcon#about to read 4, iclass 29, count 0 2006.211.07:54:20.51#ibcon#read 4, iclass 29, count 0 2006.211.07:54:20.51#ibcon#about to read 5, iclass 29, count 0 2006.211.07:54:20.51#ibcon#read 5, iclass 29, count 0 2006.211.07:54:20.51#ibcon#about to read 6, iclass 29, count 0 2006.211.07:54:20.51#ibcon#read 6, iclass 29, count 0 2006.211.07:54:20.51#ibcon#end of sib2, iclass 29, count 0 2006.211.07:54:20.51#ibcon#*after write, iclass 29, count 0 2006.211.07:54:20.51#ibcon#*before return 0, iclass 29, count 0 2006.211.07:54:20.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:20.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:54:20.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:54:20.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:54:20.51$vc4f8/vb=2,4 2006.211.07:54:20.51#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.07:54:20.51#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.07:54:20.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:20.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:20.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:20.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:20.57#ibcon#enter wrdev, iclass 31, count 2 2006.211.07:54:20.57#ibcon#first serial, iclass 31, count 2 2006.211.07:54:20.57#ibcon#enter sib2, iclass 31, count 2 2006.211.07:54:20.57#ibcon#flushed, iclass 31, count 2 2006.211.07:54:20.57#ibcon#about to write, iclass 31, count 2 2006.211.07:54:20.57#ibcon#wrote, iclass 31, count 2 2006.211.07:54:20.57#ibcon#about to read 3, iclass 31, count 2 2006.211.07:54:20.59#ibcon#read 3, iclass 31, count 2 2006.211.07:54:20.59#ibcon#about to read 4, iclass 31, count 2 2006.211.07:54:20.59#ibcon#read 4, iclass 31, count 2 2006.211.07:54:20.59#ibcon#about to read 5, iclass 31, count 2 2006.211.07:54:20.59#ibcon#read 5, iclass 31, count 2 2006.211.07:54:20.59#ibcon#about to read 6, iclass 31, count 2 2006.211.07:54:20.59#ibcon#read 6, iclass 31, count 2 2006.211.07:54:20.59#ibcon#end of sib2, iclass 31, count 2 2006.211.07:54:20.59#ibcon#*mode == 0, iclass 31, count 2 2006.211.07:54:20.59#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.07:54:20.59#ibcon#[27=AT02-04\r\n] 2006.211.07:54:20.59#ibcon#*before write, iclass 31, count 2 2006.211.07:54:20.59#ibcon#enter sib2, iclass 31, count 2 2006.211.07:54:20.59#ibcon#flushed, iclass 31, count 2 2006.211.07:54:20.59#ibcon#about to write, iclass 31, count 2 2006.211.07:54:20.59#ibcon#wrote, iclass 31, count 2 2006.211.07:54:20.59#ibcon#about to read 3, iclass 31, count 2 2006.211.07:54:20.62#ibcon#read 3, iclass 31, count 2 2006.211.07:54:20.62#ibcon#about to read 4, iclass 31, count 2 2006.211.07:54:20.62#ibcon#read 4, iclass 31, count 2 2006.211.07:54:20.62#ibcon#about to read 5, iclass 31, count 2 2006.211.07:54:20.62#ibcon#read 5, iclass 31, count 2 2006.211.07:54:20.62#ibcon#about to read 6, iclass 31, count 2 2006.211.07:54:20.62#ibcon#read 6, iclass 31, count 2 2006.211.07:54:20.62#ibcon#end of sib2, iclass 31, count 2 2006.211.07:54:20.62#ibcon#*after write, iclass 31, count 2 2006.211.07:54:20.62#ibcon#*before return 0, iclass 31, count 2 2006.211.07:54:20.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:20.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.07:54:20.62#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.07:54:20.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:20.62#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:20.74#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:20.74#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:20.74#ibcon#enter wrdev, iclass 31, count 0 2006.211.07:54:20.74#ibcon#first serial, iclass 31, count 0 2006.211.07:54:20.74#ibcon#enter sib2, iclass 31, count 0 2006.211.07:54:20.74#ibcon#flushed, iclass 31, count 0 2006.211.07:54:20.74#ibcon#about to write, iclass 31, count 0 2006.211.07:54:20.74#ibcon#wrote, iclass 31, count 0 2006.211.07:54:20.74#ibcon#about to read 3, iclass 31, count 0 2006.211.07:54:20.76#ibcon#read 3, iclass 31, count 0 2006.211.07:54:20.76#ibcon#about to read 4, iclass 31, count 0 2006.211.07:54:20.76#ibcon#read 4, iclass 31, count 0 2006.211.07:54:20.76#ibcon#about to read 5, iclass 31, count 0 2006.211.07:54:20.76#ibcon#read 5, iclass 31, count 0 2006.211.07:54:20.76#ibcon#about to read 6, iclass 31, count 0 2006.211.07:54:20.76#ibcon#read 6, iclass 31, count 0 2006.211.07:54:20.76#ibcon#end of sib2, iclass 31, count 0 2006.211.07:54:20.76#ibcon#*mode == 0, iclass 31, count 0 2006.211.07:54:20.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.07:54:20.76#ibcon#[27=USB\r\n] 2006.211.07:54:20.76#ibcon#*before write, iclass 31, count 0 2006.211.07:54:20.76#ibcon#enter sib2, iclass 31, count 0 2006.211.07:54:20.76#ibcon#flushed, iclass 31, count 0 2006.211.07:54:20.76#ibcon#about to write, iclass 31, count 0 2006.211.07:54:20.76#ibcon#wrote, iclass 31, count 0 2006.211.07:54:20.76#ibcon#about to read 3, iclass 31, count 0 2006.211.07:54:20.79#ibcon#read 3, iclass 31, count 0 2006.211.07:54:20.79#ibcon#about to read 4, iclass 31, count 0 2006.211.07:54:20.79#ibcon#read 4, iclass 31, count 0 2006.211.07:54:20.79#ibcon#about to read 5, iclass 31, count 0 2006.211.07:54:20.79#ibcon#read 5, iclass 31, count 0 2006.211.07:54:20.79#ibcon#about to read 6, iclass 31, count 0 2006.211.07:54:20.79#ibcon#read 6, iclass 31, count 0 2006.211.07:54:20.79#ibcon#end of sib2, iclass 31, count 0 2006.211.07:54:20.79#ibcon#*after write, iclass 31, count 0 2006.211.07:54:20.79#ibcon#*before return 0, iclass 31, count 0 2006.211.07:54:20.79#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:20.79#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.07:54:20.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.07:54:20.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.07:54:20.79$vc4f8/vblo=3,656.99 2006.211.07:54:20.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.07:54:20.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.07:54:20.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:20.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:20.79#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:20.79#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:20.79#ibcon#enter wrdev, iclass 33, count 0 2006.211.07:54:20.79#ibcon#first serial, iclass 33, count 0 2006.211.07:54:20.79#ibcon#enter sib2, iclass 33, count 0 2006.211.07:54:20.79#ibcon#flushed, iclass 33, count 0 2006.211.07:54:20.79#ibcon#about to write, iclass 33, count 0 2006.211.07:54:20.79#ibcon#wrote, iclass 33, count 0 2006.211.07:54:20.79#ibcon#about to read 3, iclass 33, count 0 2006.211.07:54:20.81#ibcon#read 3, iclass 33, count 0 2006.211.07:54:20.81#ibcon#about to read 4, iclass 33, count 0 2006.211.07:54:20.81#ibcon#read 4, iclass 33, count 0 2006.211.07:54:20.81#ibcon#about to read 5, iclass 33, count 0 2006.211.07:54:20.81#ibcon#read 5, iclass 33, count 0 2006.211.07:54:20.81#ibcon#about to read 6, iclass 33, count 0 2006.211.07:54:20.81#ibcon#read 6, iclass 33, count 0 2006.211.07:54:20.81#ibcon#end of sib2, iclass 33, count 0 2006.211.07:54:20.81#ibcon#*mode == 0, iclass 33, count 0 2006.211.07:54:20.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.07:54:20.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:54:20.81#ibcon#*before write, iclass 33, count 0 2006.211.07:54:20.81#ibcon#enter sib2, iclass 33, count 0 2006.211.07:54:20.81#ibcon#flushed, iclass 33, count 0 2006.211.07:54:20.81#ibcon#about to write, iclass 33, count 0 2006.211.07:54:20.81#ibcon#wrote, iclass 33, count 0 2006.211.07:54:20.81#ibcon#about to read 3, iclass 33, count 0 2006.211.07:54:20.85#ibcon#read 3, iclass 33, count 0 2006.211.07:54:20.85#ibcon#about to read 4, iclass 33, count 0 2006.211.07:54:20.85#ibcon#read 4, iclass 33, count 0 2006.211.07:54:20.85#ibcon#about to read 5, iclass 33, count 0 2006.211.07:54:20.85#ibcon#read 5, iclass 33, count 0 2006.211.07:54:20.85#ibcon#about to read 6, iclass 33, count 0 2006.211.07:54:20.85#ibcon#read 6, iclass 33, count 0 2006.211.07:54:20.85#ibcon#end of sib2, iclass 33, count 0 2006.211.07:54:20.85#ibcon#*after write, iclass 33, count 0 2006.211.07:54:20.85#ibcon#*before return 0, iclass 33, count 0 2006.211.07:54:20.85#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:20.85#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.07:54:20.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.07:54:20.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.07:54:20.85$vc4f8/vb=3,3 2006.211.07:54:20.85#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.07:54:20.85#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.07:54:20.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:20.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:20.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:20.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:20.91#ibcon#enter wrdev, iclass 35, count 2 2006.211.07:54:20.91#ibcon#first serial, iclass 35, count 2 2006.211.07:54:20.91#ibcon#enter sib2, iclass 35, count 2 2006.211.07:54:20.91#ibcon#flushed, iclass 35, count 2 2006.211.07:54:20.91#ibcon#about to write, iclass 35, count 2 2006.211.07:54:20.91#ibcon#wrote, iclass 35, count 2 2006.211.07:54:20.91#ibcon#about to read 3, iclass 35, count 2 2006.211.07:54:20.93#ibcon#read 3, iclass 35, count 2 2006.211.07:54:20.93#ibcon#about to read 4, iclass 35, count 2 2006.211.07:54:20.93#ibcon#read 4, iclass 35, count 2 2006.211.07:54:20.93#ibcon#about to read 5, iclass 35, count 2 2006.211.07:54:20.93#ibcon#read 5, iclass 35, count 2 2006.211.07:54:20.93#ibcon#about to read 6, iclass 35, count 2 2006.211.07:54:20.93#ibcon#read 6, iclass 35, count 2 2006.211.07:54:20.93#ibcon#end of sib2, iclass 35, count 2 2006.211.07:54:20.93#ibcon#*mode == 0, iclass 35, count 2 2006.211.07:54:20.93#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.07:54:20.93#ibcon#[27=AT03-03\r\n] 2006.211.07:54:20.93#ibcon#*before write, iclass 35, count 2 2006.211.07:54:20.93#ibcon#enter sib2, iclass 35, count 2 2006.211.07:54:20.93#ibcon#flushed, iclass 35, count 2 2006.211.07:54:20.93#ibcon#about to write, iclass 35, count 2 2006.211.07:54:20.93#ibcon#wrote, iclass 35, count 2 2006.211.07:54:20.93#ibcon#about to read 3, iclass 35, count 2 2006.211.07:54:20.96#ibcon#read 3, iclass 35, count 2 2006.211.07:54:20.96#ibcon#about to read 4, iclass 35, count 2 2006.211.07:54:20.96#ibcon#read 4, iclass 35, count 2 2006.211.07:54:20.96#ibcon#about to read 5, iclass 35, count 2 2006.211.07:54:20.96#ibcon#read 5, iclass 35, count 2 2006.211.07:54:20.96#ibcon#about to read 6, iclass 35, count 2 2006.211.07:54:20.96#ibcon#read 6, iclass 35, count 2 2006.211.07:54:20.96#ibcon#end of sib2, iclass 35, count 2 2006.211.07:54:20.96#ibcon#*after write, iclass 35, count 2 2006.211.07:54:20.96#ibcon#*before return 0, iclass 35, count 2 2006.211.07:54:20.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:20.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.07:54:20.96#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.07:54:20.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:20.96#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:21.08#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:21.08#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:21.08#ibcon#enter wrdev, iclass 35, count 0 2006.211.07:54:21.08#ibcon#first serial, iclass 35, count 0 2006.211.07:54:21.08#ibcon#enter sib2, iclass 35, count 0 2006.211.07:54:21.08#ibcon#flushed, iclass 35, count 0 2006.211.07:54:21.08#ibcon#about to write, iclass 35, count 0 2006.211.07:54:21.08#ibcon#wrote, iclass 35, count 0 2006.211.07:54:21.08#ibcon#about to read 3, iclass 35, count 0 2006.211.07:54:21.10#ibcon#read 3, iclass 35, count 0 2006.211.07:54:21.10#ibcon#about to read 4, iclass 35, count 0 2006.211.07:54:21.10#ibcon#read 4, iclass 35, count 0 2006.211.07:54:21.10#ibcon#about to read 5, iclass 35, count 0 2006.211.07:54:21.10#ibcon#read 5, iclass 35, count 0 2006.211.07:54:21.10#ibcon#about to read 6, iclass 35, count 0 2006.211.07:54:21.10#ibcon#read 6, iclass 35, count 0 2006.211.07:54:21.10#ibcon#end of sib2, iclass 35, count 0 2006.211.07:54:21.10#ibcon#*mode == 0, iclass 35, count 0 2006.211.07:54:21.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.07:54:21.10#ibcon#[27=USB\r\n] 2006.211.07:54:21.10#ibcon#*before write, iclass 35, count 0 2006.211.07:54:21.10#ibcon#enter sib2, iclass 35, count 0 2006.211.07:54:21.10#ibcon#flushed, iclass 35, count 0 2006.211.07:54:21.10#ibcon#about to write, iclass 35, count 0 2006.211.07:54:21.10#ibcon#wrote, iclass 35, count 0 2006.211.07:54:21.10#ibcon#about to read 3, iclass 35, count 0 2006.211.07:54:21.13#ibcon#read 3, iclass 35, count 0 2006.211.07:54:21.13#ibcon#about to read 4, iclass 35, count 0 2006.211.07:54:21.13#ibcon#read 4, iclass 35, count 0 2006.211.07:54:21.13#ibcon#about to read 5, iclass 35, count 0 2006.211.07:54:21.13#ibcon#read 5, iclass 35, count 0 2006.211.07:54:21.13#ibcon#about to read 6, iclass 35, count 0 2006.211.07:54:21.13#ibcon#read 6, iclass 35, count 0 2006.211.07:54:21.13#ibcon#end of sib2, iclass 35, count 0 2006.211.07:54:21.13#ibcon#*after write, iclass 35, count 0 2006.211.07:54:21.13#ibcon#*before return 0, iclass 35, count 0 2006.211.07:54:21.13#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:21.13#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.07:54:21.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.07:54:21.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.07:54:21.13$vc4f8/vblo=4,712.99 2006.211.07:54:21.13#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.07:54:21.13#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.07:54:21.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:21.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:21.13#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:21.13#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:21.13#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:54:21.13#ibcon#first serial, iclass 37, count 0 2006.211.07:54:21.13#ibcon#enter sib2, iclass 37, count 0 2006.211.07:54:21.13#ibcon#flushed, iclass 37, count 0 2006.211.07:54:21.13#ibcon#about to write, iclass 37, count 0 2006.211.07:54:21.13#ibcon#wrote, iclass 37, count 0 2006.211.07:54:21.13#ibcon#about to read 3, iclass 37, count 0 2006.211.07:54:21.15#ibcon#read 3, iclass 37, count 0 2006.211.07:54:21.15#ibcon#about to read 4, iclass 37, count 0 2006.211.07:54:21.15#ibcon#read 4, iclass 37, count 0 2006.211.07:54:21.15#ibcon#about to read 5, iclass 37, count 0 2006.211.07:54:21.15#ibcon#read 5, iclass 37, count 0 2006.211.07:54:21.15#ibcon#about to read 6, iclass 37, count 0 2006.211.07:54:21.15#ibcon#read 6, iclass 37, count 0 2006.211.07:54:21.15#ibcon#end of sib2, iclass 37, count 0 2006.211.07:54:21.15#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:54:21.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:54:21.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:54:21.15#ibcon#*before write, iclass 37, count 0 2006.211.07:54:21.15#ibcon#enter sib2, iclass 37, count 0 2006.211.07:54:21.15#ibcon#flushed, iclass 37, count 0 2006.211.07:54:21.15#ibcon#about to write, iclass 37, count 0 2006.211.07:54:21.15#ibcon#wrote, iclass 37, count 0 2006.211.07:54:21.15#ibcon#about to read 3, iclass 37, count 0 2006.211.07:54:21.19#ibcon#read 3, iclass 37, count 0 2006.211.07:54:21.19#ibcon#about to read 4, iclass 37, count 0 2006.211.07:54:21.19#ibcon#read 4, iclass 37, count 0 2006.211.07:54:21.19#ibcon#about to read 5, iclass 37, count 0 2006.211.07:54:21.19#ibcon#read 5, iclass 37, count 0 2006.211.07:54:21.19#ibcon#about to read 6, iclass 37, count 0 2006.211.07:54:21.19#ibcon#read 6, iclass 37, count 0 2006.211.07:54:21.19#ibcon#end of sib2, iclass 37, count 0 2006.211.07:54:21.19#ibcon#*after write, iclass 37, count 0 2006.211.07:54:21.19#ibcon#*before return 0, iclass 37, count 0 2006.211.07:54:21.19#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:21.19#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.07:54:21.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:54:21.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:54:21.19$vc4f8/vb=4,3 2006.211.07:54:21.19#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.07:54:21.19#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.07:54:21.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:21.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:21.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:21.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:21.25#ibcon#enter wrdev, iclass 39, count 2 2006.211.07:54:21.25#ibcon#first serial, iclass 39, count 2 2006.211.07:54:21.25#ibcon#enter sib2, iclass 39, count 2 2006.211.07:54:21.25#ibcon#flushed, iclass 39, count 2 2006.211.07:54:21.25#ibcon#about to write, iclass 39, count 2 2006.211.07:54:21.25#ibcon#wrote, iclass 39, count 2 2006.211.07:54:21.25#ibcon#about to read 3, iclass 39, count 2 2006.211.07:54:21.27#ibcon#read 3, iclass 39, count 2 2006.211.07:54:21.27#ibcon#about to read 4, iclass 39, count 2 2006.211.07:54:21.27#ibcon#read 4, iclass 39, count 2 2006.211.07:54:21.27#ibcon#about to read 5, iclass 39, count 2 2006.211.07:54:21.27#ibcon#read 5, iclass 39, count 2 2006.211.07:54:21.27#ibcon#about to read 6, iclass 39, count 2 2006.211.07:54:21.27#ibcon#read 6, iclass 39, count 2 2006.211.07:54:21.27#ibcon#end of sib2, iclass 39, count 2 2006.211.07:54:21.27#ibcon#*mode == 0, iclass 39, count 2 2006.211.07:54:21.27#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.07:54:21.27#ibcon#[27=AT04-03\r\n] 2006.211.07:54:21.27#ibcon#*before write, iclass 39, count 2 2006.211.07:54:21.27#ibcon#enter sib2, iclass 39, count 2 2006.211.07:54:21.27#ibcon#flushed, iclass 39, count 2 2006.211.07:54:21.27#ibcon#about to write, iclass 39, count 2 2006.211.07:54:21.27#ibcon#wrote, iclass 39, count 2 2006.211.07:54:21.27#ibcon#about to read 3, iclass 39, count 2 2006.211.07:54:21.30#ibcon#read 3, iclass 39, count 2 2006.211.07:54:21.30#ibcon#about to read 4, iclass 39, count 2 2006.211.07:54:21.30#ibcon#read 4, iclass 39, count 2 2006.211.07:54:21.30#ibcon#about to read 5, iclass 39, count 2 2006.211.07:54:21.30#ibcon#read 5, iclass 39, count 2 2006.211.07:54:21.30#ibcon#about to read 6, iclass 39, count 2 2006.211.07:54:21.30#ibcon#read 6, iclass 39, count 2 2006.211.07:54:21.30#ibcon#end of sib2, iclass 39, count 2 2006.211.07:54:21.30#ibcon#*after write, iclass 39, count 2 2006.211.07:54:21.30#ibcon#*before return 0, iclass 39, count 2 2006.211.07:54:21.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:21.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.07:54:21.30#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.07:54:21.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:21.30#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:21.42#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:21.42#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:21.42#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:54:21.42#ibcon#first serial, iclass 39, count 0 2006.211.07:54:21.42#ibcon#enter sib2, iclass 39, count 0 2006.211.07:54:21.42#ibcon#flushed, iclass 39, count 0 2006.211.07:54:21.42#ibcon#about to write, iclass 39, count 0 2006.211.07:54:21.42#ibcon#wrote, iclass 39, count 0 2006.211.07:54:21.42#ibcon#about to read 3, iclass 39, count 0 2006.211.07:54:21.44#ibcon#read 3, iclass 39, count 0 2006.211.07:54:21.44#ibcon#about to read 4, iclass 39, count 0 2006.211.07:54:21.44#ibcon#read 4, iclass 39, count 0 2006.211.07:54:21.44#ibcon#about to read 5, iclass 39, count 0 2006.211.07:54:21.44#ibcon#read 5, iclass 39, count 0 2006.211.07:54:21.44#ibcon#about to read 6, iclass 39, count 0 2006.211.07:54:21.44#ibcon#read 6, iclass 39, count 0 2006.211.07:54:21.44#ibcon#end of sib2, iclass 39, count 0 2006.211.07:54:21.44#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:54:21.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:54:21.44#ibcon#[27=USB\r\n] 2006.211.07:54:21.44#ibcon#*before write, iclass 39, count 0 2006.211.07:54:21.44#ibcon#enter sib2, iclass 39, count 0 2006.211.07:54:21.44#ibcon#flushed, iclass 39, count 0 2006.211.07:54:21.44#ibcon#about to write, iclass 39, count 0 2006.211.07:54:21.44#ibcon#wrote, iclass 39, count 0 2006.211.07:54:21.44#ibcon#about to read 3, iclass 39, count 0 2006.211.07:54:21.47#ibcon#read 3, iclass 39, count 0 2006.211.07:54:21.47#ibcon#about to read 4, iclass 39, count 0 2006.211.07:54:21.47#ibcon#read 4, iclass 39, count 0 2006.211.07:54:21.47#ibcon#about to read 5, iclass 39, count 0 2006.211.07:54:21.47#ibcon#read 5, iclass 39, count 0 2006.211.07:54:21.47#ibcon#about to read 6, iclass 39, count 0 2006.211.07:54:21.47#ibcon#read 6, iclass 39, count 0 2006.211.07:54:21.47#ibcon#end of sib2, iclass 39, count 0 2006.211.07:54:21.47#ibcon#*after write, iclass 39, count 0 2006.211.07:54:21.47#ibcon#*before return 0, iclass 39, count 0 2006.211.07:54:21.47#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:21.47#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.07:54:21.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:54:21.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:54:21.47$vc4f8/vblo=5,744.99 2006.211.07:54:21.47#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.07:54:21.47#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.07:54:21.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:21.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:21.47#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:21.47#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:21.47#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:54:21.47#ibcon#first serial, iclass 3, count 0 2006.211.07:54:21.47#ibcon#enter sib2, iclass 3, count 0 2006.211.07:54:21.47#ibcon#flushed, iclass 3, count 0 2006.211.07:54:21.47#ibcon#about to write, iclass 3, count 0 2006.211.07:54:21.47#ibcon#wrote, iclass 3, count 0 2006.211.07:54:21.47#ibcon#about to read 3, iclass 3, count 0 2006.211.07:54:21.49#ibcon#read 3, iclass 3, count 0 2006.211.07:54:21.49#ibcon#about to read 4, iclass 3, count 0 2006.211.07:54:21.49#ibcon#read 4, iclass 3, count 0 2006.211.07:54:21.49#ibcon#about to read 5, iclass 3, count 0 2006.211.07:54:21.49#ibcon#read 5, iclass 3, count 0 2006.211.07:54:21.49#ibcon#about to read 6, iclass 3, count 0 2006.211.07:54:21.49#ibcon#read 6, iclass 3, count 0 2006.211.07:54:21.49#ibcon#end of sib2, iclass 3, count 0 2006.211.07:54:21.49#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:54:21.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:54:21.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:54:21.49#ibcon#*before write, iclass 3, count 0 2006.211.07:54:21.49#ibcon#enter sib2, iclass 3, count 0 2006.211.07:54:21.49#ibcon#flushed, iclass 3, count 0 2006.211.07:54:21.49#ibcon#about to write, iclass 3, count 0 2006.211.07:54:21.49#ibcon#wrote, iclass 3, count 0 2006.211.07:54:21.49#ibcon#about to read 3, iclass 3, count 0 2006.211.07:54:21.53#ibcon#read 3, iclass 3, count 0 2006.211.07:54:21.53#ibcon#about to read 4, iclass 3, count 0 2006.211.07:54:21.53#ibcon#read 4, iclass 3, count 0 2006.211.07:54:21.53#ibcon#about to read 5, iclass 3, count 0 2006.211.07:54:21.53#ibcon#read 5, iclass 3, count 0 2006.211.07:54:21.53#ibcon#about to read 6, iclass 3, count 0 2006.211.07:54:21.53#ibcon#read 6, iclass 3, count 0 2006.211.07:54:21.53#ibcon#end of sib2, iclass 3, count 0 2006.211.07:54:21.53#ibcon#*after write, iclass 3, count 0 2006.211.07:54:21.53#ibcon#*before return 0, iclass 3, count 0 2006.211.07:54:21.53#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:21.53#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.07:54:21.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:54:21.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:54:21.53$vc4f8/vb=5,3 2006.211.07:54:21.53#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.07:54:21.53#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.07:54:21.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:21.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:21.59#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:21.59#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:21.59#ibcon#enter wrdev, iclass 5, count 2 2006.211.07:54:21.59#ibcon#first serial, iclass 5, count 2 2006.211.07:54:21.59#ibcon#enter sib2, iclass 5, count 2 2006.211.07:54:21.59#ibcon#flushed, iclass 5, count 2 2006.211.07:54:21.59#ibcon#about to write, iclass 5, count 2 2006.211.07:54:21.59#ibcon#wrote, iclass 5, count 2 2006.211.07:54:21.59#ibcon#about to read 3, iclass 5, count 2 2006.211.07:54:21.61#ibcon#read 3, iclass 5, count 2 2006.211.07:54:21.61#ibcon#about to read 4, iclass 5, count 2 2006.211.07:54:21.61#ibcon#read 4, iclass 5, count 2 2006.211.07:54:21.61#ibcon#about to read 5, iclass 5, count 2 2006.211.07:54:21.61#ibcon#read 5, iclass 5, count 2 2006.211.07:54:21.61#ibcon#about to read 6, iclass 5, count 2 2006.211.07:54:21.61#ibcon#read 6, iclass 5, count 2 2006.211.07:54:21.61#ibcon#end of sib2, iclass 5, count 2 2006.211.07:54:21.61#ibcon#*mode == 0, iclass 5, count 2 2006.211.07:54:21.61#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.07:54:21.61#ibcon#[27=AT05-03\r\n] 2006.211.07:54:21.61#ibcon#*before write, iclass 5, count 2 2006.211.07:54:21.61#ibcon#enter sib2, iclass 5, count 2 2006.211.07:54:21.61#ibcon#flushed, iclass 5, count 2 2006.211.07:54:21.61#ibcon#about to write, iclass 5, count 2 2006.211.07:54:21.61#ibcon#wrote, iclass 5, count 2 2006.211.07:54:21.61#ibcon#about to read 3, iclass 5, count 2 2006.211.07:54:21.64#ibcon#read 3, iclass 5, count 2 2006.211.07:54:21.64#ibcon#about to read 4, iclass 5, count 2 2006.211.07:54:21.64#ibcon#read 4, iclass 5, count 2 2006.211.07:54:21.64#ibcon#about to read 5, iclass 5, count 2 2006.211.07:54:21.64#ibcon#read 5, iclass 5, count 2 2006.211.07:54:21.64#ibcon#about to read 6, iclass 5, count 2 2006.211.07:54:21.64#ibcon#read 6, iclass 5, count 2 2006.211.07:54:21.64#ibcon#end of sib2, iclass 5, count 2 2006.211.07:54:21.64#ibcon#*after write, iclass 5, count 2 2006.211.07:54:21.64#ibcon#*before return 0, iclass 5, count 2 2006.211.07:54:21.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:21.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.07:54:21.64#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.07:54:21.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:21.64#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:21.76#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:21.76#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:21.76#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:54:21.76#ibcon#first serial, iclass 5, count 0 2006.211.07:54:21.76#ibcon#enter sib2, iclass 5, count 0 2006.211.07:54:21.76#ibcon#flushed, iclass 5, count 0 2006.211.07:54:21.76#ibcon#about to write, iclass 5, count 0 2006.211.07:54:21.76#ibcon#wrote, iclass 5, count 0 2006.211.07:54:21.76#ibcon#about to read 3, iclass 5, count 0 2006.211.07:54:21.78#ibcon#read 3, iclass 5, count 0 2006.211.07:54:21.78#ibcon#about to read 4, iclass 5, count 0 2006.211.07:54:21.78#ibcon#read 4, iclass 5, count 0 2006.211.07:54:21.78#ibcon#about to read 5, iclass 5, count 0 2006.211.07:54:21.78#ibcon#read 5, iclass 5, count 0 2006.211.07:54:21.78#ibcon#about to read 6, iclass 5, count 0 2006.211.07:54:21.78#ibcon#read 6, iclass 5, count 0 2006.211.07:54:21.78#ibcon#end of sib2, iclass 5, count 0 2006.211.07:54:21.78#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:54:21.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:54:21.78#ibcon#[27=USB\r\n] 2006.211.07:54:21.78#ibcon#*before write, iclass 5, count 0 2006.211.07:54:21.78#ibcon#enter sib2, iclass 5, count 0 2006.211.07:54:21.78#ibcon#flushed, iclass 5, count 0 2006.211.07:54:21.78#ibcon#about to write, iclass 5, count 0 2006.211.07:54:21.78#ibcon#wrote, iclass 5, count 0 2006.211.07:54:21.78#ibcon#about to read 3, iclass 5, count 0 2006.211.07:54:21.81#ibcon#read 3, iclass 5, count 0 2006.211.07:54:21.81#ibcon#about to read 4, iclass 5, count 0 2006.211.07:54:21.81#ibcon#read 4, iclass 5, count 0 2006.211.07:54:21.81#ibcon#about to read 5, iclass 5, count 0 2006.211.07:54:21.81#ibcon#read 5, iclass 5, count 0 2006.211.07:54:21.81#ibcon#about to read 6, iclass 5, count 0 2006.211.07:54:21.81#ibcon#read 6, iclass 5, count 0 2006.211.07:54:21.81#ibcon#end of sib2, iclass 5, count 0 2006.211.07:54:21.81#ibcon#*after write, iclass 5, count 0 2006.211.07:54:21.81#ibcon#*before return 0, iclass 5, count 0 2006.211.07:54:21.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:21.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.07:54:21.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:54:21.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:54:21.81$vc4f8/vblo=6,752.99 2006.211.07:54:21.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.07:54:21.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.07:54:21.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:54:21.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:21.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:21.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:21.81#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:54:21.81#ibcon#first serial, iclass 7, count 0 2006.211.07:54:21.81#ibcon#enter sib2, iclass 7, count 0 2006.211.07:54:21.81#ibcon#flushed, iclass 7, count 0 2006.211.07:54:21.81#ibcon#about to write, iclass 7, count 0 2006.211.07:54:21.81#ibcon#wrote, iclass 7, count 0 2006.211.07:54:21.81#ibcon#about to read 3, iclass 7, count 0 2006.211.07:54:21.83#ibcon#read 3, iclass 7, count 0 2006.211.07:54:21.83#ibcon#about to read 4, iclass 7, count 0 2006.211.07:54:21.83#ibcon#read 4, iclass 7, count 0 2006.211.07:54:21.83#ibcon#about to read 5, iclass 7, count 0 2006.211.07:54:21.83#ibcon#read 5, iclass 7, count 0 2006.211.07:54:21.83#ibcon#about to read 6, iclass 7, count 0 2006.211.07:54:21.83#ibcon#read 6, iclass 7, count 0 2006.211.07:54:21.83#ibcon#end of sib2, iclass 7, count 0 2006.211.07:54:21.83#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:54:21.83#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:54:21.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:54:21.83#ibcon#*before write, iclass 7, count 0 2006.211.07:54:21.83#ibcon#enter sib2, iclass 7, count 0 2006.211.07:54:21.83#ibcon#flushed, iclass 7, count 0 2006.211.07:54:21.83#ibcon#about to write, iclass 7, count 0 2006.211.07:54:21.83#ibcon#wrote, iclass 7, count 0 2006.211.07:54:21.83#ibcon#about to read 3, iclass 7, count 0 2006.211.07:54:21.87#ibcon#read 3, iclass 7, count 0 2006.211.07:54:21.87#ibcon#about to read 4, iclass 7, count 0 2006.211.07:54:21.87#ibcon#read 4, iclass 7, count 0 2006.211.07:54:21.87#ibcon#about to read 5, iclass 7, count 0 2006.211.07:54:21.87#ibcon#read 5, iclass 7, count 0 2006.211.07:54:21.87#ibcon#about to read 6, iclass 7, count 0 2006.211.07:54:21.87#ibcon#read 6, iclass 7, count 0 2006.211.07:54:21.87#ibcon#end of sib2, iclass 7, count 0 2006.211.07:54:21.87#ibcon#*after write, iclass 7, count 0 2006.211.07:54:21.87#ibcon#*before return 0, iclass 7, count 0 2006.211.07:54:21.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:21.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.07:54:21.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:54:21.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:54:21.87$vc4f8/vb=6,3 2006.211.07:54:21.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.07:54:21.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.07:54:21.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:54:21.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:21.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:21.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:21.93#ibcon#enter wrdev, iclass 11, count 2 2006.211.07:54:21.93#ibcon#first serial, iclass 11, count 2 2006.211.07:54:21.93#ibcon#enter sib2, iclass 11, count 2 2006.211.07:54:21.93#ibcon#flushed, iclass 11, count 2 2006.211.07:54:21.93#ibcon#about to write, iclass 11, count 2 2006.211.07:54:21.93#ibcon#wrote, iclass 11, count 2 2006.211.07:54:21.93#ibcon#about to read 3, iclass 11, count 2 2006.211.07:54:21.95#ibcon#read 3, iclass 11, count 2 2006.211.07:54:21.95#ibcon#about to read 4, iclass 11, count 2 2006.211.07:54:21.95#ibcon#read 4, iclass 11, count 2 2006.211.07:54:21.95#ibcon#about to read 5, iclass 11, count 2 2006.211.07:54:21.95#ibcon#read 5, iclass 11, count 2 2006.211.07:54:21.95#ibcon#about to read 6, iclass 11, count 2 2006.211.07:54:21.95#ibcon#read 6, iclass 11, count 2 2006.211.07:54:21.95#ibcon#end of sib2, iclass 11, count 2 2006.211.07:54:21.95#ibcon#*mode == 0, iclass 11, count 2 2006.211.07:54:21.95#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.07:54:21.95#ibcon#[27=AT06-03\r\n] 2006.211.07:54:21.95#ibcon#*before write, iclass 11, count 2 2006.211.07:54:21.95#ibcon#enter sib2, iclass 11, count 2 2006.211.07:54:21.95#ibcon#flushed, iclass 11, count 2 2006.211.07:54:21.95#ibcon#about to write, iclass 11, count 2 2006.211.07:54:21.95#ibcon#wrote, iclass 11, count 2 2006.211.07:54:21.95#ibcon#about to read 3, iclass 11, count 2 2006.211.07:54:21.98#ibcon#read 3, iclass 11, count 2 2006.211.07:54:21.98#ibcon#about to read 4, iclass 11, count 2 2006.211.07:54:21.98#ibcon#read 4, iclass 11, count 2 2006.211.07:54:21.98#ibcon#about to read 5, iclass 11, count 2 2006.211.07:54:21.98#ibcon#read 5, iclass 11, count 2 2006.211.07:54:21.98#ibcon#about to read 6, iclass 11, count 2 2006.211.07:54:21.98#ibcon#read 6, iclass 11, count 2 2006.211.07:54:21.98#ibcon#end of sib2, iclass 11, count 2 2006.211.07:54:21.98#ibcon#*after write, iclass 11, count 2 2006.211.07:54:21.98#ibcon#*before return 0, iclass 11, count 2 2006.211.07:54:21.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:21.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.07:54:21.98#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.07:54:21.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:54:21.98#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:22.10#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:22.10#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:22.10#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:54:22.10#ibcon#first serial, iclass 11, count 0 2006.211.07:54:22.10#ibcon#enter sib2, iclass 11, count 0 2006.211.07:54:22.10#ibcon#flushed, iclass 11, count 0 2006.211.07:54:22.10#ibcon#about to write, iclass 11, count 0 2006.211.07:54:22.10#ibcon#wrote, iclass 11, count 0 2006.211.07:54:22.10#ibcon#about to read 3, iclass 11, count 0 2006.211.07:54:22.12#ibcon#read 3, iclass 11, count 0 2006.211.07:54:22.12#ibcon#about to read 4, iclass 11, count 0 2006.211.07:54:22.12#ibcon#read 4, iclass 11, count 0 2006.211.07:54:22.12#ibcon#about to read 5, iclass 11, count 0 2006.211.07:54:22.12#ibcon#read 5, iclass 11, count 0 2006.211.07:54:22.12#ibcon#about to read 6, iclass 11, count 0 2006.211.07:54:22.12#ibcon#read 6, iclass 11, count 0 2006.211.07:54:22.12#ibcon#end of sib2, iclass 11, count 0 2006.211.07:54:22.12#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:54:22.12#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:54:22.12#ibcon#[27=USB\r\n] 2006.211.07:54:22.12#ibcon#*before write, iclass 11, count 0 2006.211.07:54:22.12#ibcon#enter sib2, iclass 11, count 0 2006.211.07:54:22.12#ibcon#flushed, iclass 11, count 0 2006.211.07:54:22.12#ibcon#about to write, iclass 11, count 0 2006.211.07:54:22.12#ibcon#wrote, iclass 11, count 0 2006.211.07:54:22.12#ibcon#about to read 3, iclass 11, count 0 2006.211.07:54:22.15#ibcon#read 3, iclass 11, count 0 2006.211.07:54:22.15#ibcon#about to read 4, iclass 11, count 0 2006.211.07:54:22.15#ibcon#read 4, iclass 11, count 0 2006.211.07:54:22.15#ibcon#about to read 5, iclass 11, count 0 2006.211.07:54:22.15#ibcon#read 5, iclass 11, count 0 2006.211.07:54:22.15#ibcon#about to read 6, iclass 11, count 0 2006.211.07:54:22.15#ibcon#read 6, iclass 11, count 0 2006.211.07:54:22.15#ibcon#end of sib2, iclass 11, count 0 2006.211.07:54:22.15#ibcon#*after write, iclass 11, count 0 2006.211.07:54:22.15#ibcon#*before return 0, iclass 11, count 0 2006.211.07:54:22.15#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:22.15#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.07:54:22.15#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:54:22.15#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:54:22.15$vc4f8/vabw=wide 2006.211.07:54:22.15#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.07:54:22.15#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.07:54:22.15#ibcon#ireg 8 cls_cnt 0 2006.211.07:54:22.15#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:22.15#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:22.15#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:22.15#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:54:22.15#ibcon#first serial, iclass 13, count 0 2006.211.07:54:22.15#ibcon#enter sib2, iclass 13, count 0 2006.211.07:54:22.15#ibcon#flushed, iclass 13, count 0 2006.211.07:54:22.15#ibcon#about to write, iclass 13, count 0 2006.211.07:54:22.15#ibcon#wrote, iclass 13, count 0 2006.211.07:54:22.15#ibcon#about to read 3, iclass 13, count 0 2006.211.07:54:22.17#ibcon#read 3, iclass 13, count 0 2006.211.07:54:22.17#ibcon#about to read 4, iclass 13, count 0 2006.211.07:54:22.17#ibcon#read 4, iclass 13, count 0 2006.211.07:54:22.17#ibcon#about to read 5, iclass 13, count 0 2006.211.07:54:22.17#ibcon#read 5, iclass 13, count 0 2006.211.07:54:22.17#ibcon#about to read 6, iclass 13, count 0 2006.211.07:54:22.17#ibcon#read 6, iclass 13, count 0 2006.211.07:54:22.17#ibcon#end of sib2, iclass 13, count 0 2006.211.07:54:22.17#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:54:22.17#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:54:22.17#ibcon#[25=BW32\r\n] 2006.211.07:54:22.17#ibcon#*before write, iclass 13, count 0 2006.211.07:54:22.17#ibcon#enter sib2, iclass 13, count 0 2006.211.07:54:22.17#ibcon#flushed, iclass 13, count 0 2006.211.07:54:22.17#ibcon#about to write, iclass 13, count 0 2006.211.07:54:22.17#ibcon#wrote, iclass 13, count 0 2006.211.07:54:22.17#ibcon#about to read 3, iclass 13, count 0 2006.211.07:54:22.20#ibcon#read 3, iclass 13, count 0 2006.211.07:54:22.20#ibcon#about to read 4, iclass 13, count 0 2006.211.07:54:22.20#ibcon#read 4, iclass 13, count 0 2006.211.07:54:22.20#ibcon#about to read 5, iclass 13, count 0 2006.211.07:54:22.20#ibcon#read 5, iclass 13, count 0 2006.211.07:54:22.20#ibcon#about to read 6, iclass 13, count 0 2006.211.07:54:22.20#ibcon#read 6, iclass 13, count 0 2006.211.07:54:22.20#ibcon#end of sib2, iclass 13, count 0 2006.211.07:54:22.20#ibcon#*after write, iclass 13, count 0 2006.211.07:54:22.20#ibcon#*before return 0, iclass 13, count 0 2006.211.07:54:22.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:22.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.07:54:22.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:54:22.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:54:22.20$vc4f8/vbbw=wide 2006.211.07:54:22.20#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:54:22.20#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:54:22.20#ibcon#ireg 8 cls_cnt 0 2006.211.07:54:22.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:54:22.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:54:22.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:54:22.27#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:54:22.27#ibcon#first serial, iclass 15, count 0 2006.211.07:54:22.27#ibcon#enter sib2, iclass 15, count 0 2006.211.07:54:22.27#ibcon#flushed, iclass 15, count 0 2006.211.07:54:22.27#ibcon#about to write, iclass 15, count 0 2006.211.07:54:22.27#ibcon#wrote, iclass 15, count 0 2006.211.07:54:22.27#ibcon#about to read 3, iclass 15, count 0 2006.211.07:54:22.29#ibcon#read 3, iclass 15, count 0 2006.211.07:54:22.29#ibcon#about to read 4, iclass 15, count 0 2006.211.07:54:22.29#ibcon#read 4, iclass 15, count 0 2006.211.07:54:22.29#ibcon#about to read 5, iclass 15, count 0 2006.211.07:54:22.29#ibcon#read 5, iclass 15, count 0 2006.211.07:54:22.29#ibcon#about to read 6, iclass 15, count 0 2006.211.07:54:22.29#ibcon#read 6, iclass 15, count 0 2006.211.07:54:22.29#ibcon#end of sib2, iclass 15, count 0 2006.211.07:54:22.29#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:54:22.29#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:54:22.29#ibcon#[27=BW32\r\n] 2006.211.07:54:22.29#ibcon#*before write, iclass 15, count 0 2006.211.07:54:22.29#ibcon#enter sib2, iclass 15, count 0 2006.211.07:54:22.29#ibcon#flushed, iclass 15, count 0 2006.211.07:54:22.29#ibcon#about to write, iclass 15, count 0 2006.211.07:54:22.29#ibcon#wrote, iclass 15, count 0 2006.211.07:54:22.29#ibcon#about to read 3, iclass 15, count 0 2006.211.07:54:22.32#ibcon#read 3, iclass 15, count 0 2006.211.07:54:22.32#ibcon#about to read 4, iclass 15, count 0 2006.211.07:54:22.32#ibcon#read 4, iclass 15, count 0 2006.211.07:54:22.32#ibcon#about to read 5, iclass 15, count 0 2006.211.07:54:22.32#ibcon#read 5, iclass 15, count 0 2006.211.07:54:22.32#ibcon#about to read 6, iclass 15, count 0 2006.211.07:54:22.32#ibcon#read 6, iclass 15, count 0 2006.211.07:54:22.32#ibcon#end of sib2, iclass 15, count 0 2006.211.07:54:22.32#ibcon#*after write, iclass 15, count 0 2006.211.07:54:22.32#ibcon#*before return 0, iclass 15, count 0 2006.211.07:54:22.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:54:22.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:54:22.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:54:22.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:54:22.32$4f8m12a/ifd4f 2006.211.07:54:22.32$ifd4f/lo= 2006.211.07:54:22.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:54:22.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:54:22.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:54:22.32$ifd4f/patch= 2006.211.07:54:22.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:54:22.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:54:22.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:54:22.32$4f8m12a/"form=m,16.000,1:2 2006.211.07:54:22.32$4f8m12a/"tpicd 2006.211.07:54:22.32$4f8m12a/echo=off 2006.211.07:54:22.32$4f8m12a/xlog=off 2006.211.07:54:22.32:!2006.211.07:55:20 2006.211.07:54:54.13#trakl#Source acquired 2006.211.07:54:56.13#flagr#flagr/antenna,acquired 2006.211.07:54:58.13#trakl#Off source 2006.211.07:54:58.13?ERROR st -7 Antenna off-source! 2006.211.07:54:58.13#trakl#az 40.424 el 20.239 azerr*cos(el) 0.0199 elerr 0.0021 2006.211.07:54:59.13#flagr#flagr/antenna,off-source 2006.211.07:55:04.13#trakl#Source re-acquired 2006.211.07:55:05.13#flagr#flagr/antenna,re-acquired 2006.211.07:55:20.00:preob 2006.211.07:55:21.13/onsource/TRACKING 2006.211.07:55:21.13:!2006.211.07:55:30 2006.211.07:55:30.00:data_valid=on 2006.211.07:55:30.00:midob 2006.211.07:55:30.13/onsource/TRACKING 2006.211.07:55:30.13/wx/24.89,1010.1,77 2006.211.07:55:30.18/cable/+6.4397E-03 2006.211.07:55:31.27/va/01,08,usb,yes,30,32 2006.211.07:55:31.27/va/02,07,usb,yes,30,32 2006.211.07:55:31.27/va/03,06,usb,yes,32,32 2006.211.07:55:31.27/va/04,07,usb,yes,31,33 2006.211.07:55:31.27/va/05,07,usb,yes,34,36 2006.211.07:55:31.27/va/06,06,usb,yes,33,33 2006.211.07:55:31.27/va/07,06,usb,yes,34,33 2006.211.07:55:31.27/va/08,07,usb,yes,32,31 2006.211.07:55:31.50/valo/01,532.99,yes,locked 2006.211.07:55:31.50/valo/02,572.99,yes,locked 2006.211.07:55:31.50/valo/03,672.99,yes,locked 2006.211.07:55:31.50/valo/04,832.99,yes,locked 2006.211.07:55:31.50/valo/05,652.99,yes,locked 2006.211.07:55:31.50/valo/06,772.99,yes,locked 2006.211.07:55:31.50/valo/07,832.99,yes,locked 2006.211.07:55:31.50/valo/08,852.99,yes,locked 2006.211.07:55:32.59/vb/01,04,usb,yes,29,28 2006.211.07:55:32.59/vb/02,04,usb,yes,31,33 2006.211.07:55:32.59/vb/03,03,usb,yes,34,39 2006.211.07:55:32.59/vb/04,03,usb,yes,36,36 2006.211.07:55:32.59/vb/05,03,usb,yes,34,38 2006.211.07:55:32.59/vb/06,03,usb,yes,35,38 2006.211.07:55:32.59/vb/07,04,usb,yes,30,30 2006.211.07:55:32.59/vb/08,03,usb,yes,35,38 2006.211.07:55:32.83/vblo/01,632.99,yes,locked 2006.211.07:55:32.83/vblo/02,640.99,yes,locked 2006.211.07:55:32.83/vblo/03,656.99,yes,locked 2006.211.07:55:32.83/vblo/04,712.99,yes,locked 2006.211.07:55:32.83/vblo/05,744.99,yes,locked 2006.211.07:55:32.83/vblo/06,752.99,yes,locked 2006.211.07:55:32.83/vblo/07,734.99,yes,locked 2006.211.07:55:32.83/vblo/08,744.99,yes,locked 2006.211.07:55:32.98/vabw/8 2006.211.07:55:33.13/vbbw/8 2006.211.07:55:33.22/xfe/off,on,12.2 2006.211.07:55:33.60/ifatt/23,28,28,28 2006.211.07:55:34.08/fmout-gps/S +4.48E-07 2006.211.07:55:34.12:!2006.211.07:56:30 2006.211.07:56:30.00:data_valid=off 2006.211.07:56:30.00:postob 2006.211.07:56:30.05/cable/+6.4388E-03 2006.211.07:56:30.05/wx/24.87,1010.1,77 2006.211.07:56:31.07/fmout-gps/S +4.46E-07 2006.211.07:56:31.07:scan_name=211-0759,k06211,60 2006.211.07:56:31.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.211.07:56:31.13#flagr#flagr/antenna,new-source 2006.211.07:56:32.13:checkk5 2006.211.07:56:32.47/chk_autoobs//k5ts1/ autoobs is running! 2006.211.07:56:32.81/chk_autoobs//k5ts2/ autoobs is running! 2006.211.07:56:33.15/chk_autoobs//k5ts3/ autoobs is running! 2006.211.07:56:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.07:56:33.83/chk_obsdata//k5ts1/T2110755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:56:34.17/chk_obsdata//k5ts2/T2110755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:56:34.50/chk_obsdata//k5ts3/T2110755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:56:34.84/chk_obsdata//k5ts4/T2110755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.07:56:35.50/k5log//k5ts1_log_newline 2006.211.07:56:36.16/k5log//k5ts2_log_newline 2006.211.07:56:36.81/k5log//k5ts3_log_newline 2006.211.07:56:37.47/k5log//k5ts4_log_newline 2006.211.07:56:37.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.07:56:37.49:4f8m12a=2 2006.211.07:56:37.49$4f8m12a/echo=on 2006.211.07:56:37.49$4f8m12a/pcalon 2006.211.07:56:37.49$pcalon/"no phase cal control is implemented here 2006.211.07:56:37.49$4f8m12a/"tpicd=stop 2006.211.07:56:37.49$4f8m12a/vc4f8 2006.211.07:56:37.49$vc4f8/valo=1,532.99 2006.211.07:56:37.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:56:37.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:56:37.50#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:37.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:37.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:37.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:37.50#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:56:37.50#ibcon#first serial, iclass 40, count 0 2006.211.07:56:37.50#ibcon#enter sib2, iclass 40, count 0 2006.211.07:56:37.50#ibcon#flushed, iclass 40, count 0 2006.211.07:56:37.50#ibcon#about to write, iclass 40, count 0 2006.211.07:56:37.50#ibcon#wrote, iclass 40, count 0 2006.211.07:56:37.50#ibcon#about to read 3, iclass 40, count 0 2006.211.07:56:37.52#ibcon#read 3, iclass 40, count 0 2006.211.07:56:37.52#ibcon#about to read 4, iclass 40, count 0 2006.211.07:56:37.52#ibcon#read 4, iclass 40, count 0 2006.211.07:56:37.52#ibcon#about to read 5, iclass 40, count 0 2006.211.07:56:37.52#ibcon#read 5, iclass 40, count 0 2006.211.07:56:37.52#ibcon#about to read 6, iclass 40, count 0 2006.211.07:56:37.52#ibcon#read 6, iclass 40, count 0 2006.211.07:56:37.52#ibcon#end of sib2, iclass 40, count 0 2006.211.07:56:37.52#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:56:37.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:56:37.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:56:37.52#ibcon#*before write, iclass 40, count 0 2006.211.07:56:37.52#ibcon#enter sib2, iclass 40, count 0 2006.211.07:56:37.52#ibcon#flushed, iclass 40, count 0 2006.211.07:56:37.52#ibcon#about to write, iclass 40, count 0 2006.211.07:56:37.52#ibcon#wrote, iclass 40, count 0 2006.211.07:56:37.52#ibcon#about to read 3, iclass 40, count 0 2006.211.07:56:37.57#ibcon#read 3, iclass 40, count 0 2006.211.07:56:37.57#ibcon#about to read 4, iclass 40, count 0 2006.211.07:56:37.57#ibcon#read 4, iclass 40, count 0 2006.211.07:56:37.57#ibcon#about to read 5, iclass 40, count 0 2006.211.07:56:37.57#ibcon#read 5, iclass 40, count 0 2006.211.07:56:37.57#ibcon#about to read 6, iclass 40, count 0 2006.211.07:56:37.57#ibcon#read 6, iclass 40, count 0 2006.211.07:56:37.57#ibcon#end of sib2, iclass 40, count 0 2006.211.07:56:37.57#ibcon#*after write, iclass 40, count 0 2006.211.07:56:37.57#ibcon#*before return 0, iclass 40, count 0 2006.211.07:56:37.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:37.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:37.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:56:37.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:56:37.57$vc4f8/va=1,8 2006.211.07:56:37.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:56:37.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:56:37.57#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:37.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:37.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:37.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:37.57#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:56:37.57#ibcon#first serial, iclass 4, count 2 2006.211.07:56:37.57#ibcon#enter sib2, iclass 4, count 2 2006.211.07:56:37.57#ibcon#flushed, iclass 4, count 2 2006.211.07:56:37.57#ibcon#about to write, iclass 4, count 2 2006.211.07:56:37.57#ibcon#wrote, iclass 4, count 2 2006.211.07:56:37.57#ibcon#about to read 3, iclass 4, count 2 2006.211.07:56:37.59#ibcon#read 3, iclass 4, count 2 2006.211.07:56:37.59#ibcon#about to read 4, iclass 4, count 2 2006.211.07:56:37.59#ibcon#read 4, iclass 4, count 2 2006.211.07:56:37.59#ibcon#about to read 5, iclass 4, count 2 2006.211.07:56:37.59#ibcon#read 5, iclass 4, count 2 2006.211.07:56:37.59#ibcon#about to read 6, iclass 4, count 2 2006.211.07:56:37.59#ibcon#read 6, iclass 4, count 2 2006.211.07:56:37.59#ibcon#end of sib2, iclass 4, count 2 2006.211.07:56:37.59#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:56:37.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:56:37.59#ibcon#[25=AT01-08\r\n] 2006.211.07:56:37.59#ibcon#*before write, iclass 4, count 2 2006.211.07:56:37.59#ibcon#enter sib2, iclass 4, count 2 2006.211.07:56:37.59#ibcon#flushed, iclass 4, count 2 2006.211.07:56:37.59#ibcon#about to write, iclass 4, count 2 2006.211.07:56:37.59#ibcon#wrote, iclass 4, count 2 2006.211.07:56:37.59#ibcon#about to read 3, iclass 4, count 2 2006.211.07:56:37.62#ibcon#read 3, iclass 4, count 2 2006.211.07:56:37.62#ibcon#about to read 4, iclass 4, count 2 2006.211.07:56:37.62#ibcon#read 4, iclass 4, count 2 2006.211.07:56:37.62#ibcon#about to read 5, iclass 4, count 2 2006.211.07:56:37.62#ibcon#read 5, iclass 4, count 2 2006.211.07:56:37.62#ibcon#about to read 6, iclass 4, count 2 2006.211.07:56:37.62#ibcon#read 6, iclass 4, count 2 2006.211.07:56:37.62#ibcon#end of sib2, iclass 4, count 2 2006.211.07:56:37.62#ibcon#*after write, iclass 4, count 2 2006.211.07:56:37.62#ibcon#*before return 0, iclass 4, count 2 2006.211.07:56:37.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:37.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:37.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:56:37.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:37.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:37.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:37.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:37.74#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:56:37.74#ibcon#first serial, iclass 4, count 0 2006.211.07:56:37.74#ibcon#enter sib2, iclass 4, count 0 2006.211.07:56:37.74#ibcon#flushed, iclass 4, count 0 2006.211.07:56:37.74#ibcon#about to write, iclass 4, count 0 2006.211.07:56:37.74#ibcon#wrote, iclass 4, count 0 2006.211.07:56:37.74#ibcon#about to read 3, iclass 4, count 0 2006.211.07:56:37.76#ibcon#read 3, iclass 4, count 0 2006.211.07:56:37.76#ibcon#about to read 4, iclass 4, count 0 2006.211.07:56:37.76#ibcon#read 4, iclass 4, count 0 2006.211.07:56:37.76#ibcon#about to read 5, iclass 4, count 0 2006.211.07:56:37.76#ibcon#read 5, iclass 4, count 0 2006.211.07:56:37.76#ibcon#about to read 6, iclass 4, count 0 2006.211.07:56:37.76#ibcon#read 6, iclass 4, count 0 2006.211.07:56:37.76#ibcon#end of sib2, iclass 4, count 0 2006.211.07:56:37.76#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:56:37.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:56:37.76#ibcon#[25=USB\r\n] 2006.211.07:56:37.76#ibcon#*before write, iclass 4, count 0 2006.211.07:56:37.76#ibcon#enter sib2, iclass 4, count 0 2006.211.07:56:37.76#ibcon#flushed, iclass 4, count 0 2006.211.07:56:37.76#ibcon#about to write, iclass 4, count 0 2006.211.07:56:37.76#ibcon#wrote, iclass 4, count 0 2006.211.07:56:37.76#ibcon#about to read 3, iclass 4, count 0 2006.211.07:56:37.79#ibcon#read 3, iclass 4, count 0 2006.211.07:56:37.79#ibcon#about to read 4, iclass 4, count 0 2006.211.07:56:37.79#ibcon#read 4, iclass 4, count 0 2006.211.07:56:37.79#ibcon#about to read 5, iclass 4, count 0 2006.211.07:56:37.79#ibcon#read 5, iclass 4, count 0 2006.211.07:56:37.79#ibcon#about to read 6, iclass 4, count 0 2006.211.07:56:37.79#ibcon#read 6, iclass 4, count 0 2006.211.07:56:37.79#ibcon#end of sib2, iclass 4, count 0 2006.211.07:56:37.79#ibcon#*after write, iclass 4, count 0 2006.211.07:56:37.79#ibcon#*before return 0, iclass 4, count 0 2006.211.07:56:37.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:37.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:37.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:56:37.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:56:37.79$vc4f8/valo=2,572.99 2006.211.07:56:37.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:56:37.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:56:37.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:37.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:37.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:37.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:37.79#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:56:37.79#ibcon#first serial, iclass 6, count 0 2006.211.07:56:37.79#ibcon#enter sib2, iclass 6, count 0 2006.211.07:56:37.79#ibcon#flushed, iclass 6, count 0 2006.211.07:56:37.79#ibcon#about to write, iclass 6, count 0 2006.211.07:56:37.79#ibcon#wrote, iclass 6, count 0 2006.211.07:56:37.79#ibcon#about to read 3, iclass 6, count 0 2006.211.07:56:37.81#ibcon#read 3, iclass 6, count 0 2006.211.07:56:37.81#ibcon#about to read 4, iclass 6, count 0 2006.211.07:56:37.81#ibcon#read 4, iclass 6, count 0 2006.211.07:56:37.81#ibcon#about to read 5, iclass 6, count 0 2006.211.07:56:37.81#ibcon#read 5, iclass 6, count 0 2006.211.07:56:37.81#ibcon#about to read 6, iclass 6, count 0 2006.211.07:56:37.81#ibcon#read 6, iclass 6, count 0 2006.211.07:56:37.81#ibcon#end of sib2, iclass 6, count 0 2006.211.07:56:37.81#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:56:37.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:56:37.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:56:37.81#ibcon#*before write, iclass 6, count 0 2006.211.07:56:37.81#ibcon#enter sib2, iclass 6, count 0 2006.211.07:56:37.81#ibcon#flushed, iclass 6, count 0 2006.211.07:56:37.81#ibcon#about to write, iclass 6, count 0 2006.211.07:56:37.81#ibcon#wrote, iclass 6, count 0 2006.211.07:56:37.81#ibcon#about to read 3, iclass 6, count 0 2006.211.07:56:37.85#ibcon#read 3, iclass 6, count 0 2006.211.07:56:37.85#ibcon#about to read 4, iclass 6, count 0 2006.211.07:56:37.85#ibcon#read 4, iclass 6, count 0 2006.211.07:56:37.85#ibcon#about to read 5, iclass 6, count 0 2006.211.07:56:37.85#ibcon#read 5, iclass 6, count 0 2006.211.07:56:37.85#ibcon#about to read 6, iclass 6, count 0 2006.211.07:56:37.85#ibcon#read 6, iclass 6, count 0 2006.211.07:56:37.85#ibcon#end of sib2, iclass 6, count 0 2006.211.07:56:37.85#ibcon#*after write, iclass 6, count 0 2006.211.07:56:37.85#ibcon#*before return 0, iclass 6, count 0 2006.211.07:56:37.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:37.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:37.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:56:37.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:56:37.85$vc4f8/va=2,7 2006.211.07:56:37.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:56:37.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:56:37.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:37.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:37.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:37.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:37.91#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:56:37.91#ibcon#first serial, iclass 10, count 2 2006.211.07:56:37.91#ibcon#enter sib2, iclass 10, count 2 2006.211.07:56:37.91#ibcon#flushed, iclass 10, count 2 2006.211.07:56:37.91#ibcon#about to write, iclass 10, count 2 2006.211.07:56:37.91#ibcon#wrote, iclass 10, count 2 2006.211.07:56:37.91#ibcon#about to read 3, iclass 10, count 2 2006.211.07:56:37.93#ibcon#read 3, iclass 10, count 2 2006.211.07:56:37.93#ibcon#about to read 4, iclass 10, count 2 2006.211.07:56:37.93#ibcon#read 4, iclass 10, count 2 2006.211.07:56:37.93#ibcon#about to read 5, iclass 10, count 2 2006.211.07:56:37.93#ibcon#read 5, iclass 10, count 2 2006.211.07:56:37.93#ibcon#about to read 6, iclass 10, count 2 2006.211.07:56:37.93#ibcon#read 6, iclass 10, count 2 2006.211.07:56:37.93#ibcon#end of sib2, iclass 10, count 2 2006.211.07:56:37.93#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:56:37.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:56:37.93#ibcon#[25=AT02-07\r\n] 2006.211.07:56:37.93#ibcon#*before write, iclass 10, count 2 2006.211.07:56:37.93#ibcon#enter sib2, iclass 10, count 2 2006.211.07:56:37.93#ibcon#flushed, iclass 10, count 2 2006.211.07:56:37.93#ibcon#about to write, iclass 10, count 2 2006.211.07:56:37.93#ibcon#wrote, iclass 10, count 2 2006.211.07:56:37.93#ibcon#about to read 3, iclass 10, count 2 2006.211.07:56:37.96#ibcon#read 3, iclass 10, count 2 2006.211.07:56:37.96#ibcon#about to read 4, iclass 10, count 2 2006.211.07:56:37.96#ibcon#read 4, iclass 10, count 2 2006.211.07:56:37.96#ibcon#about to read 5, iclass 10, count 2 2006.211.07:56:37.96#ibcon#read 5, iclass 10, count 2 2006.211.07:56:37.96#ibcon#about to read 6, iclass 10, count 2 2006.211.07:56:37.96#ibcon#read 6, iclass 10, count 2 2006.211.07:56:37.96#ibcon#end of sib2, iclass 10, count 2 2006.211.07:56:37.96#ibcon#*after write, iclass 10, count 2 2006.211.07:56:37.96#ibcon#*before return 0, iclass 10, count 2 2006.211.07:56:37.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:37.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:37.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:56:37.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:37.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:38.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:38.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:38.08#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:56:38.08#ibcon#first serial, iclass 10, count 0 2006.211.07:56:38.08#ibcon#enter sib2, iclass 10, count 0 2006.211.07:56:38.08#ibcon#flushed, iclass 10, count 0 2006.211.07:56:38.08#ibcon#about to write, iclass 10, count 0 2006.211.07:56:38.08#ibcon#wrote, iclass 10, count 0 2006.211.07:56:38.08#ibcon#about to read 3, iclass 10, count 0 2006.211.07:56:38.10#ibcon#read 3, iclass 10, count 0 2006.211.07:56:38.10#ibcon#about to read 4, iclass 10, count 0 2006.211.07:56:38.10#ibcon#read 4, iclass 10, count 0 2006.211.07:56:38.10#ibcon#about to read 5, iclass 10, count 0 2006.211.07:56:38.10#ibcon#read 5, iclass 10, count 0 2006.211.07:56:38.10#ibcon#about to read 6, iclass 10, count 0 2006.211.07:56:38.10#ibcon#read 6, iclass 10, count 0 2006.211.07:56:38.10#ibcon#end of sib2, iclass 10, count 0 2006.211.07:56:38.10#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:56:38.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:56:38.10#ibcon#[25=USB\r\n] 2006.211.07:56:38.10#ibcon#*before write, iclass 10, count 0 2006.211.07:56:38.10#ibcon#enter sib2, iclass 10, count 0 2006.211.07:56:38.10#ibcon#flushed, iclass 10, count 0 2006.211.07:56:38.10#ibcon#about to write, iclass 10, count 0 2006.211.07:56:38.10#ibcon#wrote, iclass 10, count 0 2006.211.07:56:38.10#ibcon#about to read 3, iclass 10, count 0 2006.211.07:56:38.13#ibcon#read 3, iclass 10, count 0 2006.211.07:56:38.13#ibcon#about to read 4, iclass 10, count 0 2006.211.07:56:38.13#ibcon#read 4, iclass 10, count 0 2006.211.07:56:38.13#ibcon#about to read 5, iclass 10, count 0 2006.211.07:56:38.13#ibcon#read 5, iclass 10, count 0 2006.211.07:56:38.13#ibcon#about to read 6, iclass 10, count 0 2006.211.07:56:38.13#ibcon#read 6, iclass 10, count 0 2006.211.07:56:38.13#ibcon#end of sib2, iclass 10, count 0 2006.211.07:56:38.13#ibcon#*after write, iclass 10, count 0 2006.211.07:56:38.13#ibcon#*before return 0, iclass 10, count 0 2006.211.07:56:38.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:38.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:38.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:56:38.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:56:38.13$vc4f8/valo=3,672.99 2006.211.07:56:38.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:56:38.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:56:38.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:38.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:38.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:38.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:38.13#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:56:38.13#ibcon#first serial, iclass 12, count 0 2006.211.07:56:38.13#ibcon#enter sib2, iclass 12, count 0 2006.211.07:56:38.13#ibcon#flushed, iclass 12, count 0 2006.211.07:56:38.13#ibcon#about to write, iclass 12, count 0 2006.211.07:56:38.13#ibcon#wrote, iclass 12, count 0 2006.211.07:56:38.13#ibcon#about to read 3, iclass 12, count 0 2006.211.07:56:38.15#ibcon#read 3, iclass 12, count 0 2006.211.07:56:38.15#ibcon#about to read 4, iclass 12, count 0 2006.211.07:56:38.15#ibcon#read 4, iclass 12, count 0 2006.211.07:56:38.15#ibcon#about to read 5, iclass 12, count 0 2006.211.07:56:38.15#ibcon#read 5, iclass 12, count 0 2006.211.07:56:38.15#ibcon#about to read 6, iclass 12, count 0 2006.211.07:56:38.15#ibcon#read 6, iclass 12, count 0 2006.211.07:56:38.15#ibcon#end of sib2, iclass 12, count 0 2006.211.07:56:38.15#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:56:38.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:56:38.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:56:38.15#ibcon#*before write, iclass 12, count 0 2006.211.07:56:38.15#ibcon#enter sib2, iclass 12, count 0 2006.211.07:56:38.15#ibcon#flushed, iclass 12, count 0 2006.211.07:56:38.15#ibcon#about to write, iclass 12, count 0 2006.211.07:56:38.15#ibcon#wrote, iclass 12, count 0 2006.211.07:56:38.15#ibcon#about to read 3, iclass 12, count 0 2006.211.07:56:38.19#ibcon#read 3, iclass 12, count 0 2006.211.07:56:38.19#ibcon#about to read 4, iclass 12, count 0 2006.211.07:56:38.19#ibcon#read 4, iclass 12, count 0 2006.211.07:56:38.19#ibcon#about to read 5, iclass 12, count 0 2006.211.07:56:38.19#ibcon#read 5, iclass 12, count 0 2006.211.07:56:38.19#ibcon#about to read 6, iclass 12, count 0 2006.211.07:56:38.19#ibcon#read 6, iclass 12, count 0 2006.211.07:56:38.19#ibcon#end of sib2, iclass 12, count 0 2006.211.07:56:38.19#ibcon#*after write, iclass 12, count 0 2006.211.07:56:38.19#ibcon#*before return 0, iclass 12, count 0 2006.211.07:56:38.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:38.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:38.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:56:38.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:56:38.19$vc4f8/va=3,6 2006.211.07:56:38.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:56:38.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:56:38.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:38.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:38.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:38.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:38.25#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:56:38.25#ibcon#first serial, iclass 14, count 2 2006.211.07:56:38.25#ibcon#enter sib2, iclass 14, count 2 2006.211.07:56:38.25#ibcon#flushed, iclass 14, count 2 2006.211.07:56:38.25#ibcon#about to write, iclass 14, count 2 2006.211.07:56:38.25#ibcon#wrote, iclass 14, count 2 2006.211.07:56:38.25#ibcon#about to read 3, iclass 14, count 2 2006.211.07:56:38.27#ibcon#read 3, iclass 14, count 2 2006.211.07:56:38.27#ibcon#about to read 4, iclass 14, count 2 2006.211.07:56:38.27#ibcon#read 4, iclass 14, count 2 2006.211.07:56:38.27#ibcon#about to read 5, iclass 14, count 2 2006.211.07:56:38.27#ibcon#read 5, iclass 14, count 2 2006.211.07:56:38.27#ibcon#about to read 6, iclass 14, count 2 2006.211.07:56:38.27#ibcon#read 6, iclass 14, count 2 2006.211.07:56:38.27#ibcon#end of sib2, iclass 14, count 2 2006.211.07:56:38.27#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:56:38.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:56:38.27#ibcon#[25=AT03-06\r\n] 2006.211.07:56:38.27#ibcon#*before write, iclass 14, count 2 2006.211.07:56:38.27#ibcon#enter sib2, iclass 14, count 2 2006.211.07:56:38.27#ibcon#flushed, iclass 14, count 2 2006.211.07:56:38.27#ibcon#about to write, iclass 14, count 2 2006.211.07:56:38.27#ibcon#wrote, iclass 14, count 2 2006.211.07:56:38.27#ibcon#about to read 3, iclass 14, count 2 2006.211.07:56:38.30#ibcon#read 3, iclass 14, count 2 2006.211.07:56:38.30#ibcon#about to read 4, iclass 14, count 2 2006.211.07:56:38.30#ibcon#read 4, iclass 14, count 2 2006.211.07:56:38.30#ibcon#about to read 5, iclass 14, count 2 2006.211.07:56:38.30#ibcon#read 5, iclass 14, count 2 2006.211.07:56:38.30#ibcon#about to read 6, iclass 14, count 2 2006.211.07:56:38.30#ibcon#read 6, iclass 14, count 2 2006.211.07:56:38.30#ibcon#end of sib2, iclass 14, count 2 2006.211.07:56:38.30#ibcon#*after write, iclass 14, count 2 2006.211.07:56:38.30#ibcon#*before return 0, iclass 14, count 2 2006.211.07:56:38.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:38.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:38.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:56:38.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:38.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:38.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:38.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:38.42#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:56:38.42#ibcon#first serial, iclass 14, count 0 2006.211.07:56:38.42#ibcon#enter sib2, iclass 14, count 0 2006.211.07:56:38.42#ibcon#flushed, iclass 14, count 0 2006.211.07:56:38.42#ibcon#about to write, iclass 14, count 0 2006.211.07:56:38.42#ibcon#wrote, iclass 14, count 0 2006.211.07:56:38.42#ibcon#about to read 3, iclass 14, count 0 2006.211.07:56:38.44#ibcon#read 3, iclass 14, count 0 2006.211.07:56:38.44#ibcon#about to read 4, iclass 14, count 0 2006.211.07:56:38.44#ibcon#read 4, iclass 14, count 0 2006.211.07:56:38.44#ibcon#about to read 5, iclass 14, count 0 2006.211.07:56:38.44#ibcon#read 5, iclass 14, count 0 2006.211.07:56:38.44#ibcon#about to read 6, iclass 14, count 0 2006.211.07:56:38.44#ibcon#read 6, iclass 14, count 0 2006.211.07:56:38.44#ibcon#end of sib2, iclass 14, count 0 2006.211.07:56:38.44#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:56:38.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:56:38.44#ibcon#[25=USB\r\n] 2006.211.07:56:38.44#ibcon#*before write, iclass 14, count 0 2006.211.07:56:38.44#ibcon#enter sib2, iclass 14, count 0 2006.211.07:56:38.44#ibcon#flushed, iclass 14, count 0 2006.211.07:56:38.44#ibcon#about to write, iclass 14, count 0 2006.211.07:56:38.44#ibcon#wrote, iclass 14, count 0 2006.211.07:56:38.44#ibcon#about to read 3, iclass 14, count 0 2006.211.07:56:38.47#ibcon#read 3, iclass 14, count 0 2006.211.07:56:38.47#ibcon#about to read 4, iclass 14, count 0 2006.211.07:56:38.47#ibcon#read 4, iclass 14, count 0 2006.211.07:56:38.47#ibcon#about to read 5, iclass 14, count 0 2006.211.07:56:38.47#ibcon#read 5, iclass 14, count 0 2006.211.07:56:38.47#ibcon#about to read 6, iclass 14, count 0 2006.211.07:56:38.47#ibcon#read 6, iclass 14, count 0 2006.211.07:56:38.47#ibcon#end of sib2, iclass 14, count 0 2006.211.07:56:38.47#ibcon#*after write, iclass 14, count 0 2006.211.07:56:38.47#ibcon#*before return 0, iclass 14, count 0 2006.211.07:56:38.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:38.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:38.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:56:38.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:56:38.47$vc4f8/valo=4,832.99 2006.211.07:56:38.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:56:38.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:56:38.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:38.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:38.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:38.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:38.47#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:56:38.47#ibcon#first serial, iclass 16, count 0 2006.211.07:56:38.47#ibcon#enter sib2, iclass 16, count 0 2006.211.07:56:38.47#ibcon#flushed, iclass 16, count 0 2006.211.07:56:38.47#ibcon#about to write, iclass 16, count 0 2006.211.07:56:38.47#ibcon#wrote, iclass 16, count 0 2006.211.07:56:38.47#ibcon#about to read 3, iclass 16, count 0 2006.211.07:56:38.49#ibcon#read 3, iclass 16, count 0 2006.211.07:56:38.49#ibcon#about to read 4, iclass 16, count 0 2006.211.07:56:38.49#ibcon#read 4, iclass 16, count 0 2006.211.07:56:38.49#ibcon#about to read 5, iclass 16, count 0 2006.211.07:56:38.49#ibcon#read 5, iclass 16, count 0 2006.211.07:56:38.49#ibcon#about to read 6, iclass 16, count 0 2006.211.07:56:38.49#ibcon#read 6, iclass 16, count 0 2006.211.07:56:38.49#ibcon#end of sib2, iclass 16, count 0 2006.211.07:56:38.49#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:56:38.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:56:38.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:56:38.49#ibcon#*before write, iclass 16, count 0 2006.211.07:56:38.49#ibcon#enter sib2, iclass 16, count 0 2006.211.07:56:38.49#ibcon#flushed, iclass 16, count 0 2006.211.07:56:38.49#ibcon#about to write, iclass 16, count 0 2006.211.07:56:38.49#ibcon#wrote, iclass 16, count 0 2006.211.07:56:38.49#ibcon#about to read 3, iclass 16, count 0 2006.211.07:56:38.53#ibcon#read 3, iclass 16, count 0 2006.211.07:56:38.53#ibcon#about to read 4, iclass 16, count 0 2006.211.07:56:38.53#ibcon#read 4, iclass 16, count 0 2006.211.07:56:38.53#ibcon#about to read 5, iclass 16, count 0 2006.211.07:56:38.53#ibcon#read 5, iclass 16, count 0 2006.211.07:56:38.53#ibcon#about to read 6, iclass 16, count 0 2006.211.07:56:38.53#ibcon#read 6, iclass 16, count 0 2006.211.07:56:38.53#ibcon#end of sib2, iclass 16, count 0 2006.211.07:56:38.53#ibcon#*after write, iclass 16, count 0 2006.211.07:56:38.53#ibcon#*before return 0, iclass 16, count 0 2006.211.07:56:38.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:38.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:38.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:56:38.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:56:38.53$vc4f8/va=4,7 2006.211.07:56:38.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.07:56:38.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.07:56:38.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:38.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:38.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:38.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:38.59#ibcon#enter wrdev, iclass 18, count 2 2006.211.07:56:38.59#ibcon#first serial, iclass 18, count 2 2006.211.07:56:38.59#ibcon#enter sib2, iclass 18, count 2 2006.211.07:56:38.59#ibcon#flushed, iclass 18, count 2 2006.211.07:56:38.59#ibcon#about to write, iclass 18, count 2 2006.211.07:56:38.59#ibcon#wrote, iclass 18, count 2 2006.211.07:56:38.59#ibcon#about to read 3, iclass 18, count 2 2006.211.07:56:38.61#ibcon#read 3, iclass 18, count 2 2006.211.07:56:38.61#ibcon#about to read 4, iclass 18, count 2 2006.211.07:56:38.61#ibcon#read 4, iclass 18, count 2 2006.211.07:56:38.61#ibcon#about to read 5, iclass 18, count 2 2006.211.07:56:38.61#ibcon#read 5, iclass 18, count 2 2006.211.07:56:38.61#ibcon#about to read 6, iclass 18, count 2 2006.211.07:56:38.61#ibcon#read 6, iclass 18, count 2 2006.211.07:56:38.61#ibcon#end of sib2, iclass 18, count 2 2006.211.07:56:38.61#ibcon#*mode == 0, iclass 18, count 2 2006.211.07:56:38.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.07:56:38.61#ibcon#[25=AT04-07\r\n] 2006.211.07:56:38.61#ibcon#*before write, iclass 18, count 2 2006.211.07:56:38.61#ibcon#enter sib2, iclass 18, count 2 2006.211.07:56:38.61#ibcon#flushed, iclass 18, count 2 2006.211.07:56:38.61#ibcon#about to write, iclass 18, count 2 2006.211.07:56:38.61#ibcon#wrote, iclass 18, count 2 2006.211.07:56:38.61#ibcon#about to read 3, iclass 18, count 2 2006.211.07:56:38.64#ibcon#read 3, iclass 18, count 2 2006.211.07:56:38.64#ibcon#about to read 4, iclass 18, count 2 2006.211.07:56:38.64#ibcon#read 4, iclass 18, count 2 2006.211.07:56:38.64#ibcon#about to read 5, iclass 18, count 2 2006.211.07:56:38.64#ibcon#read 5, iclass 18, count 2 2006.211.07:56:38.64#ibcon#about to read 6, iclass 18, count 2 2006.211.07:56:38.64#ibcon#read 6, iclass 18, count 2 2006.211.07:56:38.64#ibcon#end of sib2, iclass 18, count 2 2006.211.07:56:38.64#ibcon#*after write, iclass 18, count 2 2006.211.07:56:38.64#ibcon#*before return 0, iclass 18, count 2 2006.211.07:56:38.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:38.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:38.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.07:56:38.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:38.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:38.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:38.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:38.76#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:56:38.76#ibcon#first serial, iclass 18, count 0 2006.211.07:56:38.76#ibcon#enter sib2, iclass 18, count 0 2006.211.07:56:38.76#ibcon#flushed, iclass 18, count 0 2006.211.07:56:38.76#ibcon#about to write, iclass 18, count 0 2006.211.07:56:38.76#ibcon#wrote, iclass 18, count 0 2006.211.07:56:38.76#ibcon#about to read 3, iclass 18, count 0 2006.211.07:56:38.78#ibcon#read 3, iclass 18, count 0 2006.211.07:56:38.78#ibcon#about to read 4, iclass 18, count 0 2006.211.07:56:38.78#ibcon#read 4, iclass 18, count 0 2006.211.07:56:38.78#ibcon#about to read 5, iclass 18, count 0 2006.211.07:56:38.78#ibcon#read 5, iclass 18, count 0 2006.211.07:56:38.78#ibcon#about to read 6, iclass 18, count 0 2006.211.07:56:38.78#ibcon#read 6, iclass 18, count 0 2006.211.07:56:38.78#ibcon#end of sib2, iclass 18, count 0 2006.211.07:56:38.78#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:56:38.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:56:38.78#ibcon#[25=USB\r\n] 2006.211.07:56:38.78#ibcon#*before write, iclass 18, count 0 2006.211.07:56:38.78#ibcon#enter sib2, iclass 18, count 0 2006.211.07:56:38.78#ibcon#flushed, iclass 18, count 0 2006.211.07:56:38.78#ibcon#about to write, iclass 18, count 0 2006.211.07:56:38.78#ibcon#wrote, iclass 18, count 0 2006.211.07:56:38.78#ibcon#about to read 3, iclass 18, count 0 2006.211.07:56:38.81#ibcon#read 3, iclass 18, count 0 2006.211.07:56:38.81#ibcon#about to read 4, iclass 18, count 0 2006.211.07:56:38.81#ibcon#read 4, iclass 18, count 0 2006.211.07:56:38.81#ibcon#about to read 5, iclass 18, count 0 2006.211.07:56:38.81#ibcon#read 5, iclass 18, count 0 2006.211.07:56:38.81#ibcon#about to read 6, iclass 18, count 0 2006.211.07:56:38.81#ibcon#read 6, iclass 18, count 0 2006.211.07:56:38.81#ibcon#end of sib2, iclass 18, count 0 2006.211.07:56:38.81#ibcon#*after write, iclass 18, count 0 2006.211.07:56:38.81#ibcon#*before return 0, iclass 18, count 0 2006.211.07:56:38.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:38.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:38.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:56:38.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:56:38.81$vc4f8/valo=5,652.99 2006.211.07:56:38.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.07:56:38.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.07:56:38.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:38.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:38.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:38.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:38.81#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:56:38.81#ibcon#first serial, iclass 20, count 0 2006.211.07:56:38.81#ibcon#enter sib2, iclass 20, count 0 2006.211.07:56:38.81#ibcon#flushed, iclass 20, count 0 2006.211.07:56:38.81#ibcon#about to write, iclass 20, count 0 2006.211.07:56:38.81#ibcon#wrote, iclass 20, count 0 2006.211.07:56:38.81#ibcon#about to read 3, iclass 20, count 0 2006.211.07:56:38.83#ibcon#read 3, iclass 20, count 0 2006.211.07:56:38.83#ibcon#about to read 4, iclass 20, count 0 2006.211.07:56:38.83#ibcon#read 4, iclass 20, count 0 2006.211.07:56:38.83#ibcon#about to read 5, iclass 20, count 0 2006.211.07:56:38.83#ibcon#read 5, iclass 20, count 0 2006.211.07:56:38.83#ibcon#about to read 6, iclass 20, count 0 2006.211.07:56:38.83#ibcon#read 6, iclass 20, count 0 2006.211.07:56:38.83#ibcon#end of sib2, iclass 20, count 0 2006.211.07:56:38.83#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:56:38.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:56:38.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:56:38.83#ibcon#*before write, iclass 20, count 0 2006.211.07:56:38.83#ibcon#enter sib2, iclass 20, count 0 2006.211.07:56:38.83#ibcon#flushed, iclass 20, count 0 2006.211.07:56:38.83#ibcon#about to write, iclass 20, count 0 2006.211.07:56:38.83#ibcon#wrote, iclass 20, count 0 2006.211.07:56:38.83#ibcon#about to read 3, iclass 20, count 0 2006.211.07:56:38.87#ibcon#read 3, iclass 20, count 0 2006.211.07:56:38.87#ibcon#about to read 4, iclass 20, count 0 2006.211.07:56:38.87#ibcon#read 4, iclass 20, count 0 2006.211.07:56:38.87#ibcon#about to read 5, iclass 20, count 0 2006.211.07:56:38.87#ibcon#read 5, iclass 20, count 0 2006.211.07:56:38.87#ibcon#about to read 6, iclass 20, count 0 2006.211.07:56:38.87#ibcon#read 6, iclass 20, count 0 2006.211.07:56:38.87#ibcon#end of sib2, iclass 20, count 0 2006.211.07:56:38.87#ibcon#*after write, iclass 20, count 0 2006.211.07:56:38.87#ibcon#*before return 0, iclass 20, count 0 2006.211.07:56:38.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:38.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:38.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:56:38.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:56:38.87$vc4f8/va=5,7 2006.211.07:56:38.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.07:56:38.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.07:56:38.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:38.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:38.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:38.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:38.93#ibcon#enter wrdev, iclass 22, count 2 2006.211.07:56:38.93#ibcon#first serial, iclass 22, count 2 2006.211.07:56:38.93#ibcon#enter sib2, iclass 22, count 2 2006.211.07:56:38.93#ibcon#flushed, iclass 22, count 2 2006.211.07:56:38.93#ibcon#about to write, iclass 22, count 2 2006.211.07:56:38.93#ibcon#wrote, iclass 22, count 2 2006.211.07:56:38.93#ibcon#about to read 3, iclass 22, count 2 2006.211.07:56:38.95#ibcon#read 3, iclass 22, count 2 2006.211.07:56:38.95#ibcon#about to read 4, iclass 22, count 2 2006.211.07:56:38.95#ibcon#read 4, iclass 22, count 2 2006.211.07:56:38.95#ibcon#about to read 5, iclass 22, count 2 2006.211.07:56:38.95#ibcon#read 5, iclass 22, count 2 2006.211.07:56:38.95#ibcon#about to read 6, iclass 22, count 2 2006.211.07:56:38.95#ibcon#read 6, iclass 22, count 2 2006.211.07:56:38.95#ibcon#end of sib2, iclass 22, count 2 2006.211.07:56:38.95#ibcon#*mode == 0, iclass 22, count 2 2006.211.07:56:38.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.07:56:38.95#ibcon#[25=AT05-07\r\n] 2006.211.07:56:38.95#ibcon#*before write, iclass 22, count 2 2006.211.07:56:38.95#ibcon#enter sib2, iclass 22, count 2 2006.211.07:56:38.95#ibcon#flushed, iclass 22, count 2 2006.211.07:56:38.95#ibcon#about to write, iclass 22, count 2 2006.211.07:56:38.95#ibcon#wrote, iclass 22, count 2 2006.211.07:56:38.95#ibcon#about to read 3, iclass 22, count 2 2006.211.07:56:38.98#ibcon#read 3, iclass 22, count 2 2006.211.07:56:38.98#ibcon#about to read 4, iclass 22, count 2 2006.211.07:56:38.98#ibcon#read 4, iclass 22, count 2 2006.211.07:56:38.98#ibcon#about to read 5, iclass 22, count 2 2006.211.07:56:38.98#ibcon#read 5, iclass 22, count 2 2006.211.07:56:38.98#ibcon#about to read 6, iclass 22, count 2 2006.211.07:56:38.98#ibcon#read 6, iclass 22, count 2 2006.211.07:56:38.98#ibcon#end of sib2, iclass 22, count 2 2006.211.07:56:38.98#ibcon#*after write, iclass 22, count 2 2006.211.07:56:38.98#ibcon#*before return 0, iclass 22, count 2 2006.211.07:56:38.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:38.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:38.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.07:56:38.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:38.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:39.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:39.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:39.10#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:56:39.10#ibcon#first serial, iclass 22, count 0 2006.211.07:56:39.10#ibcon#enter sib2, iclass 22, count 0 2006.211.07:56:39.10#ibcon#flushed, iclass 22, count 0 2006.211.07:56:39.10#ibcon#about to write, iclass 22, count 0 2006.211.07:56:39.10#ibcon#wrote, iclass 22, count 0 2006.211.07:56:39.10#ibcon#about to read 3, iclass 22, count 0 2006.211.07:56:39.12#ibcon#read 3, iclass 22, count 0 2006.211.07:56:39.12#ibcon#about to read 4, iclass 22, count 0 2006.211.07:56:39.12#ibcon#read 4, iclass 22, count 0 2006.211.07:56:39.12#ibcon#about to read 5, iclass 22, count 0 2006.211.07:56:39.12#ibcon#read 5, iclass 22, count 0 2006.211.07:56:39.12#ibcon#about to read 6, iclass 22, count 0 2006.211.07:56:39.12#ibcon#read 6, iclass 22, count 0 2006.211.07:56:39.12#ibcon#end of sib2, iclass 22, count 0 2006.211.07:56:39.12#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:56:39.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:56:39.12#ibcon#[25=USB\r\n] 2006.211.07:56:39.12#ibcon#*before write, iclass 22, count 0 2006.211.07:56:39.12#ibcon#enter sib2, iclass 22, count 0 2006.211.07:56:39.12#ibcon#flushed, iclass 22, count 0 2006.211.07:56:39.12#ibcon#about to write, iclass 22, count 0 2006.211.07:56:39.12#ibcon#wrote, iclass 22, count 0 2006.211.07:56:39.12#ibcon#about to read 3, iclass 22, count 0 2006.211.07:56:39.15#ibcon#read 3, iclass 22, count 0 2006.211.07:56:39.15#ibcon#about to read 4, iclass 22, count 0 2006.211.07:56:39.15#ibcon#read 4, iclass 22, count 0 2006.211.07:56:39.15#ibcon#about to read 5, iclass 22, count 0 2006.211.07:56:39.15#ibcon#read 5, iclass 22, count 0 2006.211.07:56:39.15#ibcon#about to read 6, iclass 22, count 0 2006.211.07:56:39.15#ibcon#read 6, iclass 22, count 0 2006.211.07:56:39.15#ibcon#end of sib2, iclass 22, count 0 2006.211.07:56:39.15#ibcon#*after write, iclass 22, count 0 2006.211.07:56:39.15#ibcon#*before return 0, iclass 22, count 0 2006.211.07:56:39.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:39.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:39.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:56:39.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:56:39.15$vc4f8/valo=6,772.99 2006.211.07:56:39.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.07:56:39.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.07:56:39.15#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:39.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:39.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:39.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:39.15#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:56:39.15#ibcon#first serial, iclass 24, count 0 2006.211.07:56:39.15#ibcon#enter sib2, iclass 24, count 0 2006.211.07:56:39.15#ibcon#flushed, iclass 24, count 0 2006.211.07:56:39.15#ibcon#about to write, iclass 24, count 0 2006.211.07:56:39.15#ibcon#wrote, iclass 24, count 0 2006.211.07:56:39.15#ibcon#about to read 3, iclass 24, count 0 2006.211.07:56:39.17#ibcon#read 3, iclass 24, count 0 2006.211.07:56:39.17#ibcon#about to read 4, iclass 24, count 0 2006.211.07:56:39.17#ibcon#read 4, iclass 24, count 0 2006.211.07:56:39.17#ibcon#about to read 5, iclass 24, count 0 2006.211.07:56:39.17#ibcon#read 5, iclass 24, count 0 2006.211.07:56:39.17#ibcon#about to read 6, iclass 24, count 0 2006.211.07:56:39.17#ibcon#read 6, iclass 24, count 0 2006.211.07:56:39.17#ibcon#end of sib2, iclass 24, count 0 2006.211.07:56:39.17#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:56:39.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:56:39.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:56:39.17#ibcon#*before write, iclass 24, count 0 2006.211.07:56:39.17#ibcon#enter sib2, iclass 24, count 0 2006.211.07:56:39.17#ibcon#flushed, iclass 24, count 0 2006.211.07:56:39.17#ibcon#about to write, iclass 24, count 0 2006.211.07:56:39.17#ibcon#wrote, iclass 24, count 0 2006.211.07:56:39.17#ibcon#about to read 3, iclass 24, count 0 2006.211.07:56:39.21#ibcon#read 3, iclass 24, count 0 2006.211.07:56:39.21#ibcon#about to read 4, iclass 24, count 0 2006.211.07:56:39.21#ibcon#read 4, iclass 24, count 0 2006.211.07:56:39.21#ibcon#about to read 5, iclass 24, count 0 2006.211.07:56:39.21#ibcon#read 5, iclass 24, count 0 2006.211.07:56:39.21#ibcon#about to read 6, iclass 24, count 0 2006.211.07:56:39.21#ibcon#read 6, iclass 24, count 0 2006.211.07:56:39.21#ibcon#end of sib2, iclass 24, count 0 2006.211.07:56:39.21#ibcon#*after write, iclass 24, count 0 2006.211.07:56:39.21#ibcon#*before return 0, iclass 24, count 0 2006.211.07:56:39.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:39.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:39.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:56:39.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:56:39.21$vc4f8/va=6,6 2006.211.07:56:39.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.07:56:39.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.07:56:39.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:39.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:56:39.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:56:39.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:56:39.27#ibcon#enter wrdev, iclass 26, count 2 2006.211.07:56:39.27#ibcon#first serial, iclass 26, count 2 2006.211.07:56:39.27#ibcon#enter sib2, iclass 26, count 2 2006.211.07:56:39.27#ibcon#flushed, iclass 26, count 2 2006.211.07:56:39.27#ibcon#about to write, iclass 26, count 2 2006.211.07:56:39.27#ibcon#wrote, iclass 26, count 2 2006.211.07:56:39.27#ibcon#about to read 3, iclass 26, count 2 2006.211.07:56:39.29#ibcon#read 3, iclass 26, count 2 2006.211.07:56:39.29#ibcon#about to read 4, iclass 26, count 2 2006.211.07:56:39.29#ibcon#read 4, iclass 26, count 2 2006.211.07:56:39.29#ibcon#about to read 5, iclass 26, count 2 2006.211.07:56:39.29#ibcon#read 5, iclass 26, count 2 2006.211.07:56:39.29#ibcon#about to read 6, iclass 26, count 2 2006.211.07:56:39.29#ibcon#read 6, iclass 26, count 2 2006.211.07:56:39.29#ibcon#end of sib2, iclass 26, count 2 2006.211.07:56:39.29#ibcon#*mode == 0, iclass 26, count 2 2006.211.07:56:39.29#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.07:56:39.29#ibcon#[25=AT06-06\r\n] 2006.211.07:56:39.29#ibcon#*before write, iclass 26, count 2 2006.211.07:56:39.29#ibcon#enter sib2, iclass 26, count 2 2006.211.07:56:39.29#ibcon#flushed, iclass 26, count 2 2006.211.07:56:39.29#ibcon#about to write, iclass 26, count 2 2006.211.07:56:39.29#ibcon#wrote, iclass 26, count 2 2006.211.07:56:39.29#ibcon#about to read 3, iclass 26, count 2 2006.211.07:56:39.32#ibcon#read 3, iclass 26, count 2 2006.211.07:56:39.32#ibcon#about to read 4, iclass 26, count 2 2006.211.07:56:39.32#ibcon#read 4, iclass 26, count 2 2006.211.07:56:39.32#ibcon#about to read 5, iclass 26, count 2 2006.211.07:56:39.32#ibcon#read 5, iclass 26, count 2 2006.211.07:56:39.32#ibcon#about to read 6, iclass 26, count 2 2006.211.07:56:39.32#ibcon#read 6, iclass 26, count 2 2006.211.07:56:39.32#ibcon#end of sib2, iclass 26, count 2 2006.211.07:56:39.32#ibcon#*after write, iclass 26, count 2 2006.211.07:56:39.32#ibcon#*before return 0, iclass 26, count 2 2006.211.07:56:39.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:56:39.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.07:56:39.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.07:56:39.32#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:39.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:56:39.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:56:39.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:56:39.44#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:56:39.44#ibcon#first serial, iclass 26, count 0 2006.211.07:56:39.44#ibcon#enter sib2, iclass 26, count 0 2006.211.07:56:39.44#ibcon#flushed, iclass 26, count 0 2006.211.07:56:39.44#ibcon#about to write, iclass 26, count 0 2006.211.07:56:39.44#ibcon#wrote, iclass 26, count 0 2006.211.07:56:39.44#ibcon#about to read 3, iclass 26, count 0 2006.211.07:56:39.46#ibcon#read 3, iclass 26, count 0 2006.211.07:56:39.46#ibcon#about to read 4, iclass 26, count 0 2006.211.07:56:39.46#ibcon#read 4, iclass 26, count 0 2006.211.07:56:39.46#ibcon#about to read 5, iclass 26, count 0 2006.211.07:56:39.46#ibcon#read 5, iclass 26, count 0 2006.211.07:56:39.46#ibcon#about to read 6, iclass 26, count 0 2006.211.07:56:39.46#ibcon#read 6, iclass 26, count 0 2006.211.07:56:39.46#ibcon#end of sib2, iclass 26, count 0 2006.211.07:56:39.46#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:56:39.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:56:39.46#ibcon#[25=USB\r\n] 2006.211.07:56:39.46#ibcon#*before write, iclass 26, count 0 2006.211.07:56:39.46#ibcon#enter sib2, iclass 26, count 0 2006.211.07:56:39.46#ibcon#flushed, iclass 26, count 0 2006.211.07:56:39.46#ibcon#about to write, iclass 26, count 0 2006.211.07:56:39.46#ibcon#wrote, iclass 26, count 0 2006.211.07:56:39.46#ibcon#about to read 3, iclass 26, count 0 2006.211.07:56:39.49#ibcon#read 3, iclass 26, count 0 2006.211.07:56:39.49#ibcon#about to read 4, iclass 26, count 0 2006.211.07:56:39.49#ibcon#read 4, iclass 26, count 0 2006.211.07:56:39.49#ibcon#about to read 5, iclass 26, count 0 2006.211.07:56:39.49#ibcon#read 5, iclass 26, count 0 2006.211.07:56:39.49#ibcon#about to read 6, iclass 26, count 0 2006.211.07:56:39.49#ibcon#read 6, iclass 26, count 0 2006.211.07:56:39.49#ibcon#end of sib2, iclass 26, count 0 2006.211.07:56:39.49#ibcon#*after write, iclass 26, count 0 2006.211.07:56:39.49#ibcon#*before return 0, iclass 26, count 0 2006.211.07:56:39.49#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:56:39.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.07:56:39.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:56:39.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:56:39.49$vc4f8/valo=7,832.99 2006.211.07:56:39.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.07:56:39.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.07:56:39.49#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:39.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:56:39.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:56:39.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:56:39.49#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:56:39.49#ibcon#first serial, iclass 28, count 0 2006.211.07:56:39.49#ibcon#enter sib2, iclass 28, count 0 2006.211.07:56:39.49#ibcon#flushed, iclass 28, count 0 2006.211.07:56:39.49#ibcon#about to write, iclass 28, count 0 2006.211.07:56:39.49#ibcon#wrote, iclass 28, count 0 2006.211.07:56:39.49#ibcon#about to read 3, iclass 28, count 0 2006.211.07:56:39.51#ibcon#read 3, iclass 28, count 0 2006.211.07:56:39.51#ibcon#about to read 4, iclass 28, count 0 2006.211.07:56:39.51#ibcon#read 4, iclass 28, count 0 2006.211.07:56:39.51#ibcon#about to read 5, iclass 28, count 0 2006.211.07:56:39.51#ibcon#read 5, iclass 28, count 0 2006.211.07:56:39.51#ibcon#about to read 6, iclass 28, count 0 2006.211.07:56:39.51#ibcon#read 6, iclass 28, count 0 2006.211.07:56:39.51#ibcon#end of sib2, iclass 28, count 0 2006.211.07:56:39.51#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:56:39.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:56:39.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:56:39.51#ibcon#*before write, iclass 28, count 0 2006.211.07:56:39.51#ibcon#enter sib2, iclass 28, count 0 2006.211.07:56:39.51#ibcon#flushed, iclass 28, count 0 2006.211.07:56:39.51#ibcon#about to write, iclass 28, count 0 2006.211.07:56:39.51#ibcon#wrote, iclass 28, count 0 2006.211.07:56:39.51#ibcon#about to read 3, iclass 28, count 0 2006.211.07:56:39.55#ibcon#read 3, iclass 28, count 0 2006.211.07:56:39.55#ibcon#about to read 4, iclass 28, count 0 2006.211.07:56:39.55#ibcon#read 4, iclass 28, count 0 2006.211.07:56:39.55#ibcon#about to read 5, iclass 28, count 0 2006.211.07:56:39.55#ibcon#read 5, iclass 28, count 0 2006.211.07:56:39.55#ibcon#about to read 6, iclass 28, count 0 2006.211.07:56:39.55#ibcon#read 6, iclass 28, count 0 2006.211.07:56:39.55#ibcon#end of sib2, iclass 28, count 0 2006.211.07:56:39.55#ibcon#*after write, iclass 28, count 0 2006.211.07:56:39.55#ibcon#*before return 0, iclass 28, count 0 2006.211.07:56:39.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:56:39.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.07:56:39.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:56:39.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:56:39.55$vc4f8/va=7,6 2006.211.07:56:39.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.07:56:39.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.07:56:39.55#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:39.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:56:39.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:56:39.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:56:39.61#ibcon#enter wrdev, iclass 30, count 2 2006.211.07:56:39.61#ibcon#first serial, iclass 30, count 2 2006.211.07:56:39.61#ibcon#enter sib2, iclass 30, count 2 2006.211.07:56:39.61#ibcon#flushed, iclass 30, count 2 2006.211.07:56:39.61#ibcon#about to write, iclass 30, count 2 2006.211.07:56:39.61#ibcon#wrote, iclass 30, count 2 2006.211.07:56:39.61#ibcon#about to read 3, iclass 30, count 2 2006.211.07:56:39.63#ibcon#read 3, iclass 30, count 2 2006.211.07:56:39.63#ibcon#about to read 4, iclass 30, count 2 2006.211.07:56:39.63#ibcon#read 4, iclass 30, count 2 2006.211.07:56:39.63#ibcon#about to read 5, iclass 30, count 2 2006.211.07:56:39.63#ibcon#read 5, iclass 30, count 2 2006.211.07:56:39.63#ibcon#about to read 6, iclass 30, count 2 2006.211.07:56:39.63#ibcon#read 6, iclass 30, count 2 2006.211.07:56:39.63#ibcon#end of sib2, iclass 30, count 2 2006.211.07:56:39.63#ibcon#*mode == 0, iclass 30, count 2 2006.211.07:56:39.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.07:56:39.63#ibcon#[25=AT07-06\r\n] 2006.211.07:56:39.63#ibcon#*before write, iclass 30, count 2 2006.211.07:56:39.63#ibcon#enter sib2, iclass 30, count 2 2006.211.07:56:39.63#ibcon#flushed, iclass 30, count 2 2006.211.07:56:39.63#ibcon#about to write, iclass 30, count 2 2006.211.07:56:39.63#ibcon#wrote, iclass 30, count 2 2006.211.07:56:39.63#ibcon#about to read 3, iclass 30, count 2 2006.211.07:56:39.66#ibcon#read 3, iclass 30, count 2 2006.211.07:56:39.66#ibcon#about to read 4, iclass 30, count 2 2006.211.07:56:39.66#ibcon#read 4, iclass 30, count 2 2006.211.07:56:39.66#ibcon#about to read 5, iclass 30, count 2 2006.211.07:56:39.66#ibcon#read 5, iclass 30, count 2 2006.211.07:56:39.66#ibcon#about to read 6, iclass 30, count 2 2006.211.07:56:39.66#ibcon#read 6, iclass 30, count 2 2006.211.07:56:39.66#ibcon#end of sib2, iclass 30, count 2 2006.211.07:56:39.66#ibcon#*after write, iclass 30, count 2 2006.211.07:56:39.66#ibcon#*before return 0, iclass 30, count 2 2006.211.07:56:39.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:56:39.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.07:56:39.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.07:56:39.66#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:39.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:56:39.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:56:39.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:56:39.78#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:56:39.78#ibcon#first serial, iclass 30, count 0 2006.211.07:56:39.78#ibcon#enter sib2, iclass 30, count 0 2006.211.07:56:39.78#ibcon#flushed, iclass 30, count 0 2006.211.07:56:39.78#ibcon#about to write, iclass 30, count 0 2006.211.07:56:39.78#ibcon#wrote, iclass 30, count 0 2006.211.07:56:39.78#ibcon#about to read 3, iclass 30, count 0 2006.211.07:56:39.80#ibcon#read 3, iclass 30, count 0 2006.211.07:56:39.80#ibcon#about to read 4, iclass 30, count 0 2006.211.07:56:39.80#ibcon#read 4, iclass 30, count 0 2006.211.07:56:39.80#ibcon#about to read 5, iclass 30, count 0 2006.211.07:56:39.80#ibcon#read 5, iclass 30, count 0 2006.211.07:56:39.80#ibcon#about to read 6, iclass 30, count 0 2006.211.07:56:39.80#ibcon#read 6, iclass 30, count 0 2006.211.07:56:39.80#ibcon#end of sib2, iclass 30, count 0 2006.211.07:56:39.80#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:56:39.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:56:39.80#ibcon#[25=USB\r\n] 2006.211.07:56:39.80#ibcon#*before write, iclass 30, count 0 2006.211.07:56:39.80#ibcon#enter sib2, iclass 30, count 0 2006.211.07:56:39.80#ibcon#flushed, iclass 30, count 0 2006.211.07:56:39.80#ibcon#about to write, iclass 30, count 0 2006.211.07:56:39.80#ibcon#wrote, iclass 30, count 0 2006.211.07:56:39.80#ibcon#about to read 3, iclass 30, count 0 2006.211.07:56:39.83#ibcon#read 3, iclass 30, count 0 2006.211.07:56:39.83#ibcon#about to read 4, iclass 30, count 0 2006.211.07:56:39.83#ibcon#read 4, iclass 30, count 0 2006.211.07:56:39.83#ibcon#about to read 5, iclass 30, count 0 2006.211.07:56:39.83#ibcon#read 5, iclass 30, count 0 2006.211.07:56:39.83#ibcon#about to read 6, iclass 30, count 0 2006.211.07:56:39.83#ibcon#read 6, iclass 30, count 0 2006.211.07:56:39.83#ibcon#end of sib2, iclass 30, count 0 2006.211.07:56:39.83#ibcon#*after write, iclass 30, count 0 2006.211.07:56:39.83#ibcon#*before return 0, iclass 30, count 0 2006.211.07:56:39.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:56:39.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.07:56:39.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:56:39.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:56:39.83$vc4f8/valo=8,852.99 2006.211.07:56:39.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.07:56:39.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.07:56:39.83#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:39.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:56:39.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:56:39.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:56:39.83#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:56:39.83#ibcon#first serial, iclass 32, count 0 2006.211.07:56:39.83#ibcon#enter sib2, iclass 32, count 0 2006.211.07:56:39.83#ibcon#flushed, iclass 32, count 0 2006.211.07:56:39.83#ibcon#about to write, iclass 32, count 0 2006.211.07:56:39.83#ibcon#wrote, iclass 32, count 0 2006.211.07:56:39.83#ibcon#about to read 3, iclass 32, count 0 2006.211.07:56:39.85#ibcon#read 3, iclass 32, count 0 2006.211.07:56:39.85#ibcon#about to read 4, iclass 32, count 0 2006.211.07:56:39.85#ibcon#read 4, iclass 32, count 0 2006.211.07:56:39.85#ibcon#about to read 5, iclass 32, count 0 2006.211.07:56:39.85#ibcon#read 5, iclass 32, count 0 2006.211.07:56:39.85#ibcon#about to read 6, iclass 32, count 0 2006.211.07:56:39.85#ibcon#read 6, iclass 32, count 0 2006.211.07:56:39.85#ibcon#end of sib2, iclass 32, count 0 2006.211.07:56:39.85#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:56:39.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:56:39.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:56:39.85#ibcon#*before write, iclass 32, count 0 2006.211.07:56:39.85#ibcon#enter sib2, iclass 32, count 0 2006.211.07:56:39.85#ibcon#flushed, iclass 32, count 0 2006.211.07:56:39.85#ibcon#about to write, iclass 32, count 0 2006.211.07:56:39.85#ibcon#wrote, iclass 32, count 0 2006.211.07:56:39.85#ibcon#about to read 3, iclass 32, count 0 2006.211.07:56:39.89#ibcon#read 3, iclass 32, count 0 2006.211.07:56:39.89#ibcon#about to read 4, iclass 32, count 0 2006.211.07:56:39.89#ibcon#read 4, iclass 32, count 0 2006.211.07:56:39.89#ibcon#about to read 5, iclass 32, count 0 2006.211.07:56:39.89#ibcon#read 5, iclass 32, count 0 2006.211.07:56:39.89#ibcon#about to read 6, iclass 32, count 0 2006.211.07:56:39.89#ibcon#read 6, iclass 32, count 0 2006.211.07:56:39.89#ibcon#end of sib2, iclass 32, count 0 2006.211.07:56:39.89#ibcon#*after write, iclass 32, count 0 2006.211.07:56:39.89#ibcon#*before return 0, iclass 32, count 0 2006.211.07:56:39.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:56:39.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.07:56:39.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:56:39.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:56:39.89$vc4f8/va=8,7 2006.211.07:56:39.89#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.07:56:39.89#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.07:56:39.89#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:39.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:56:39.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:56:39.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:56:39.95#ibcon#enter wrdev, iclass 34, count 2 2006.211.07:56:39.95#ibcon#first serial, iclass 34, count 2 2006.211.07:56:39.95#ibcon#enter sib2, iclass 34, count 2 2006.211.07:56:39.95#ibcon#flushed, iclass 34, count 2 2006.211.07:56:39.95#ibcon#about to write, iclass 34, count 2 2006.211.07:56:39.95#ibcon#wrote, iclass 34, count 2 2006.211.07:56:39.95#ibcon#about to read 3, iclass 34, count 2 2006.211.07:56:39.97#ibcon#read 3, iclass 34, count 2 2006.211.07:56:39.97#ibcon#about to read 4, iclass 34, count 2 2006.211.07:56:39.97#ibcon#read 4, iclass 34, count 2 2006.211.07:56:39.97#ibcon#about to read 5, iclass 34, count 2 2006.211.07:56:39.97#ibcon#read 5, iclass 34, count 2 2006.211.07:56:39.97#ibcon#about to read 6, iclass 34, count 2 2006.211.07:56:39.97#ibcon#read 6, iclass 34, count 2 2006.211.07:56:39.97#ibcon#end of sib2, iclass 34, count 2 2006.211.07:56:39.97#ibcon#*mode == 0, iclass 34, count 2 2006.211.07:56:39.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.07:56:39.97#ibcon#[25=AT08-07\r\n] 2006.211.07:56:39.97#ibcon#*before write, iclass 34, count 2 2006.211.07:56:39.97#ibcon#enter sib2, iclass 34, count 2 2006.211.07:56:39.97#ibcon#flushed, iclass 34, count 2 2006.211.07:56:39.97#ibcon#about to write, iclass 34, count 2 2006.211.07:56:39.97#ibcon#wrote, iclass 34, count 2 2006.211.07:56:39.97#ibcon#about to read 3, iclass 34, count 2 2006.211.07:56:40.00#ibcon#read 3, iclass 34, count 2 2006.211.07:56:40.00#ibcon#about to read 4, iclass 34, count 2 2006.211.07:56:40.00#ibcon#read 4, iclass 34, count 2 2006.211.07:56:40.00#ibcon#about to read 5, iclass 34, count 2 2006.211.07:56:40.00#ibcon#read 5, iclass 34, count 2 2006.211.07:56:40.00#ibcon#about to read 6, iclass 34, count 2 2006.211.07:56:40.00#ibcon#read 6, iclass 34, count 2 2006.211.07:56:40.00#ibcon#end of sib2, iclass 34, count 2 2006.211.07:56:40.00#ibcon#*after write, iclass 34, count 2 2006.211.07:56:40.00#ibcon#*before return 0, iclass 34, count 2 2006.211.07:56:40.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:56:40.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.07:56:40.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.07:56:40.00#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:40.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:56:40.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:56:40.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:56:40.12#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:56:40.12#ibcon#first serial, iclass 34, count 0 2006.211.07:56:40.12#ibcon#enter sib2, iclass 34, count 0 2006.211.07:56:40.12#ibcon#flushed, iclass 34, count 0 2006.211.07:56:40.12#ibcon#about to write, iclass 34, count 0 2006.211.07:56:40.12#ibcon#wrote, iclass 34, count 0 2006.211.07:56:40.12#ibcon#about to read 3, iclass 34, count 0 2006.211.07:56:40.14#ibcon#read 3, iclass 34, count 0 2006.211.07:56:40.14#ibcon#about to read 4, iclass 34, count 0 2006.211.07:56:40.14#ibcon#read 4, iclass 34, count 0 2006.211.07:56:40.14#ibcon#about to read 5, iclass 34, count 0 2006.211.07:56:40.14#ibcon#read 5, iclass 34, count 0 2006.211.07:56:40.14#ibcon#about to read 6, iclass 34, count 0 2006.211.07:56:40.14#ibcon#read 6, iclass 34, count 0 2006.211.07:56:40.14#ibcon#end of sib2, iclass 34, count 0 2006.211.07:56:40.14#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:56:40.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:56:40.14#ibcon#[25=USB\r\n] 2006.211.07:56:40.14#ibcon#*before write, iclass 34, count 0 2006.211.07:56:40.14#ibcon#enter sib2, iclass 34, count 0 2006.211.07:56:40.14#ibcon#flushed, iclass 34, count 0 2006.211.07:56:40.14#ibcon#about to write, iclass 34, count 0 2006.211.07:56:40.14#ibcon#wrote, iclass 34, count 0 2006.211.07:56:40.14#ibcon#about to read 3, iclass 34, count 0 2006.211.07:56:40.17#ibcon#read 3, iclass 34, count 0 2006.211.07:56:40.17#ibcon#about to read 4, iclass 34, count 0 2006.211.07:56:40.17#ibcon#read 4, iclass 34, count 0 2006.211.07:56:40.17#ibcon#about to read 5, iclass 34, count 0 2006.211.07:56:40.17#ibcon#read 5, iclass 34, count 0 2006.211.07:56:40.17#ibcon#about to read 6, iclass 34, count 0 2006.211.07:56:40.17#ibcon#read 6, iclass 34, count 0 2006.211.07:56:40.17#ibcon#end of sib2, iclass 34, count 0 2006.211.07:56:40.17#ibcon#*after write, iclass 34, count 0 2006.211.07:56:40.17#ibcon#*before return 0, iclass 34, count 0 2006.211.07:56:40.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:56:40.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.07:56:40.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:56:40.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:56:40.17$vc4f8/vblo=1,632.99 2006.211.07:56:40.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.07:56:40.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.07:56:40.17#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:40.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:56:40.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:56:40.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:56:40.17#ibcon#enter wrdev, iclass 36, count 0 2006.211.07:56:40.17#ibcon#first serial, iclass 36, count 0 2006.211.07:56:40.17#ibcon#enter sib2, iclass 36, count 0 2006.211.07:56:40.17#ibcon#flushed, iclass 36, count 0 2006.211.07:56:40.17#ibcon#about to write, iclass 36, count 0 2006.211.07:56:40.17#ibcon#wrote, iclass 36, count 0 2006.211.07:56:40.17#ibcon#about to read 3, iclass 36, count 0 2006.211.07:56:40.19#ibcon#read 3, iclass 36, count 0 2006.211.07:56:40.19#ibcon#about to read 4, iclass 36, count 0 2006.211.07:56:40.19#ibcon#read 4, iclass 36, count 0 2006.211.07:56:40.19#ibcon#about to read 5, iclass 36, count 0 2006.211.07:56:40.19#ibcon#read 5, iclass 36, count 0 2006.211.07:56:40.19#ibcon#about to read 6, iclass 36, count 0 2006.211.07:56:40.19#ibcon#read 6, iclass 36, count 0 2006.211.07:56:40.19#ibcon#end of sib2, iclass 36, count 0 2006.211.07:56:40.19#ibcon#*mode == 0, iclass 36, count 0 2006.211.07:56:40.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.07:56:40.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:56:40.19#ibcon#*before write, iclass 36, count 0 2006.211.07:56:40.19#ibcon#enter sib2, iclass 36, count 0 2006.211.07:56:40.19#ibcon#flushed, iclass 36, count 0 2006.211.07:56:40.19#ibcon#about to write, iclass 36, count 0 2006.211.07:56:40.19#ibcon#wrote, iclass 36, count 0 2006.211.07:56:40.19#ibcon#about to read 3, iclass 36, count 0 2006.211.07:56:40.23#ibcon#read 3, iclass 36, count 0 2006.211.07:56:40.23#ibcon#about to read 4, iclass 36, count 0 2006.211.07:56:40.23#ibcon#read 4, iclass 36, count 0 2006.211.07:56:40.23#ibcon#about to read 5, iclass 36, count 0 2006.211.07:56:40.23#ibcon#read 5, iclass 36, count 0 2006.211.07:56:40.23#ibcon#about to read 6, iclass 36, count 0 2006.211.07:56:40.23#ibcon#read 6, iclass 36, count 0 2006.211.07:56:40.23#ibcon#end of sib2, iclass 36, count 0 2006.211.07:56:40.23#ibcon#*after write, iclass 36, count 0 2006.211.07:56:40.23#ibcon#*before return 0, iclass 36, count 0 2006.211.07:56:40.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:56:40.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.07:56:40.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.07:56:40.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.07:56:40.23$vc4f8/vb=1,4 2006.211.07:56:40.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.07:56:40.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.07:56:40.23#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:40.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:56:40.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:56:40.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:56:40.23#ibcon#enter wrdev, iclass 38, count 2 2006.211.07:56:40.23#ibcon#first serial, iclass 38, count 2 2006.211.07:56:40.23#ibcon#enter sib2, iclass 38, count 2 2006.211.07:56:40.23#ibcon#flushed, iclass 38, count 2 2006.211.07:56:40.23#ibcon#about to write, iclass 38, count 2 2006.211.07:56:40.23#ibcon#wrote, iclass 38, count 2 2006.211.07:56:40.23#ibcon#about to read 3, iclass 38, count 2 2006.211.07:56:40.25#ibcon#read 3, iclass 38, count 2 2006.211.07:56:40.25#ibcon#about to read 4, iclass 38, count 2 2006.211.07:56:40.25#ibcon#read 4, iclass 38, count 2 2006.211.07:56:40.25#ibcon#about to read 5, iclass 38, count 2 2006.211.07:56:40.25#ibcon#read 5, iclass 38, count 2 2006.211.07:56:40.25#ibcon#about to read 6, iclass 38, count 2 2006.211.07:56:40.25#ibcon#read 6, iclass 38, count 2 2006.211.07:56:40.25#ibcon#end of sib2, iclass 38, count 2 2006.211.07:56:40.25#ibcon#*mode == 0, iclass 38, count 2 2006.211.07:56:40.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.07:56:40.25#ibcon#[27=AT01-04\r\n] 2006.211.07:56:40.25#ibcon#*before write, iclass 38, count 2 2006.211.07:56:40.25#ibcon#enter sib2, iclass 38, count 2 2006.211.07:56:40.25#ibcon#flushed, iclass 38, count 2 2006.211.07:56:40.25#ibcon#about to write, iclass 38, count 2 2006.211.07:56:40.25#ibcon#wrote, iclass 38, count 2 2006.211.07:56:40.25#ibcon#about to read 3, iclass 38, count 2 2006.211.07:56:40.28#ibcon#read 3, iclass 38, count 2 2006.211.07:56:40.28#ibcon#about to read 4, iclass 38, count 2 2006.211.07:56:40.28#ibcon#read 4, iclass 38, count 2 2006.211.07:56:40.28#ibcon#about to read 5, iclass 38, count 2 2006.211.07:56:40.28#ibcon#read 5, iclass 38, count 2 2006.211.07:56:40.28#ibcon#about to read 6, iclass 38, count 2 2006.211.07:56:40.28#ibcon#read 6, iclass 38, count 2 2006.211.07:56:40.28#ibcon#end of sib2, iclass 38, count 2 2006.211.07:56:40.28#ibcon#*after write, iclass 38, count 2 2006.211.07:56:40.28#ibcon#*before return 0, iclass 38, count 2 2006.211.07:56:40.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:56:40.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.07:56:40.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.07:56:40.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:40.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:56:40.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:56:40.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:56:40.40#ibcon#enter wrdev, iclass 38, count 0 2006.211.07:56:40.40#ibcon#first serial, iclass 38, count 0 2006.211.07:56:40.40#ibcon#enter sib2, iclass 38, count 0 2006.211.07:56:40.40#ibcon#flushed, iclass 38, count 0 2006.211.07:56:40.40#ibcon#about to write, iclass 38, count 0 2006.211.07:56:40.40#ibcon#wrote, iclass 38, count 0 2006.211.07:56:40.40#ibcon#about to read 3, iclass 38, count 0 2006.211.07:56:40.42#ibcon#read 3, iclass 38, count 0 2006.211.07:56:40.42#ibcon#about to read 4, iclass 38, count 0 2006.211.07:56:40.42#ibcon#read 4, iclass 38, count 0 2006.211.07:56:40.42#ibcon#about to read 5, iclass 38, count 0 2006.211.07:56:40.42#ibcon#read 5, iclass 38, count 0 2006.211.07:56:40.42#ibcon#about to read 6, iclass 38, count 0 2006.211.07:56:40.42#ibcon#read 6, iclass 38, count 0 2006.211.07:56:40.42#ibcon#end of sib2, iclass 38, count 0 2006.211.07:56:40.42#ibcon#*mode == 0, iclass 38, count 0 2006.211.07:56:40.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.07:56:40.42#ibcon#[27=USB\r\n] 2006.211.07:56:40.42#ibcon#*before write, iclass 38, count 0 2006.211.07:56:40.42#ibcon#enter sib2, iclass 38, count 0 2006.211.07:56:40.42#ibcon#flushed, iclass 38, count 0 2006.211.07:56:40.42#ibcon#about to write, iclass 38, count 0 2006.211.07:56:40.42#ibcon#wrote, iclass 38, count 0 2006.211.07:56:40.42#ibcon#about to read 3, iclass 38, count 0 2006.211.07:56:40.45#ibcon#read 3, iclass 38, count 0 2006.211.07:56:40.45#ibcon#about to read 4, iclass 38, count 0 2006.211.07:56:40.45#ibcon#read 4, iclass 38, count 0 2006.211.07:56:40.45#ibcon#about to read 5, iclass 38, count 0 2006.211.07:56:40.45#ibcon#read 5, iclass 38, count 0 2006.211.07:56:40.45#ibcon#about to read 6, iclass 38, count 0 2006.211.07:56:40.45#ibcon#read 6, iclass 38, count 0 2006.211.07:56:40.45#ibcon#end of sib2, iclass 38, count 0 2006.211.07:56:40.45#ibcon#*after write, iclass 38, count 0 2006.211.07:56:40.45#ibcon#*before return 0, iclass 38, count 0 2006.211.07:56:40.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:56:40.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.07:56:40.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.07:56:40.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.07:56:40.45$vc4f8/vblo=2,640.99 2006.211.07:56:40.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.07:56:40.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.07:56:40.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:40.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:40.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:40.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:40.45#ibcon#enter wrdev, iclass 40, count 0 2006.211.07:56:40.45#ibcon#first serial, iclass 40, count 0 2006.211.07:56:40.45#ibcon#enter sib2, iclass 40, count 0 2006.211.07:56:40.45#ibcon#flushed, iclass 40, count 0 2006.211.07:56:40.45#ibcon#about to write, iclass 40, count 0 2006.211.07:56:40.45#ibcon#wrote, iclass 40, count 0 2006.211.07:56:40.45#ibcon#about to read 3, iclass 40, count 0 2006.211.07:56:40.47#ibcon#read 3, iclass 40, count 0 2006.211.07:56:40.47#ibcon#about to read 4, iclass 40, count 0 2006.211.07:56:40.47#ibcon#read 4, iclass 40, count 0 2006.211.07:56:40.47#ibcon#about to read 5, iclass 40, count 0 2006.211.07:56:40.47#ibcon#read 5, iclass 40, count 0 2006.211.07:56:40.47#ibcon#about to read 6, iclass 40, count 0 2006.211.07:56:40.47#ibcon#read 6, iclass 40, count 0 2006.211.07:56:40.47#ibcon#end of sib2, iclass 40, count 0 2006.211.07:56:40.47#ibcon#*mode == 0, iclass 40, count 0 2006.211.07:56:40.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.07:56:40.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:56:40.47#ibcon#*before write, iclass 40, count 0 2006.211.07:56:40.47#ibcon#enter sib2, iclass 40, count 0 2006.211.07:56:40.47#ibcon#flushed, iclass 40, count 0 2006.211.07:56:40.47#ibcon#about to write, iclass 40, count 0 2006.211.07:56:40.47#ibcon#wrote, iclass 40, count 0 2006.211.07:56:40.47#ibcon#about to read 3, iclass 40, count 0 2006.211.07:56:40.51#ibcon#read 3, iclass 40, count 0 2006.211.07:56:40.51#ibcon#about to read 4, iclass 40, count 0 2006.211.07:56:40.51#ibcon#read 4, iclass 40, count 0 2006.211.07:56:40.51#ibcon#about to read 5, iclass 40, count 0 2006.211.07:56:40.51#ibcon#read 5, iclass 40, count 0 2006.211.07:56:40.51#ibcon#about to read 6, iclass 40, count 0 2006.211.07:56:40.51#ibcon#read 6, iclass 40, count 0 2006.211.07:56:40.51#ibcon#end of sib2, iclass 40, count 0 2006.211.07:56:40.51#ibcon#*after write, iclass 40, count 0 2006.211.07:56:40.51#ibcon#*before return 0, iclass 40, count 0 2006.211.07:56:40.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:40.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.07:56:40.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.07:56:40.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.07:56:40.51$vc4f8/vb=2,4 2006.211.07:56:40.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.07:56:40.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.07:56:40.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:40.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:40.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:40.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:40.57#ibcon#enter wrdev, iclass 4, count 2 2006.211.07:56:40.57#ibcon#first serial, iclass 4, count 2 2006.211.07:56:40.57#ibcon#enter sib2, iclass 4, count 2 2006.211.07:56:40.57#ibcon#flushed, iclass 4, count 2 2006.211.07:56:40.57#ibcon#about to write, iclass 4, count 2 2006.211.07:56:40.57#ibcon#wrote, iclass 4, count 2 2006.211.07:56:40.57#ibcon#about to read 3, iclass 4, count 2 2006.211.07:56:40.59#ibcon#read 3, iclass 4, count 2 2006.211.07:56:40.59#ibcon#about to read 4, iclass 4, count 2 2006.211.07:56:40.59#ibcon#read 4, iclass 4, count 2 2006.211.07:56:40.59#ibcon#about to read 5, iclass 4, count 2 2006.211.07:56:40.59#ibcon#read 5, iclass 4, count 2 2006.211.07:56:40.59#ibcon#about to read 6, iclass 4, count 2 2006.211.07:56:40.59#ibcon#read 6, iclass 4, count 2 2006.211.07:56:40.59#ibcon#end of sib2, iclass 4, count 2 2006.211.07:56:40.59#ibcon#*mode == 0, iclass 4, count 2 2006.211.07:56:40.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.07:56:40.59#ibcon#[27=AT02-04\r\n] 2006.211.07:56:40.59#ibcon#*before write, iclass 4, count 2 2006.211.07:56:40.59#ibcon#enter sib2, iclass 4, count 2 2006.211.07:56:40.59#ibcon#flushed, iclass 4, count 2 2006.211.07:56:40.59#ibcon#about to write, iclass 4, count 2 2006.211.07:56:40.59#ibcon#wrote, iclass 4, count 2 2006.211.07:56:40.59#ibcon#about to read 3, iclass 4, count 2 2006.211.07:56:40.62#ibcon#read 3, iclass 4, count 2 2006.211.07:56:40.62#ibcon#about to read 4, iclass 4, count 2 2006.211.07:56:40.62#ibcon#read 4, iclass 4, count 2 2006.211.07:56:40.62#ibcon#about to read 5, iclass 4, count 2 2006.211.07:56:40.62#ibcon#read 5, iclass 4, count 2 2006.211.07:56:40.62#ibcon#about to read 6, iclass 4, count 2 2006.211.07:56:40.62#ibcon#read 6, iclass 4, count 2 2006.211.07:56:40.62#ibcon#end of sib2, iclass 4, count 2 2006.211.07:56:40.62#ibcon#*after write, iclass 4, count 2 2006.211.07:56:40.62#ibcon#*before return 0, iclass 4, count 2 2006.211.07:56:40.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:40.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.07:56:40.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.07:56:40.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:40.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:40.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:40.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:40.74#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:56:40.74#ibcon#first serial, iclass 4, count 0 2006.211.07:56:40.74#ibcon#enter sib2, iclass 4, count 0 2006.211.07:56:40.74#ibcon#flushed, iclass 4, count 0 2006.211.07:56:40.74#ibcon#about to write, iclass 4, count 0 2006.211.07:56:40.74#ibcon#wrote, iclass 4, count 0 2006.211.07:56:40.74#ibcon#about to read 3, iclass 4, count 0 2006.211.07:56:40.76#ibcon#read 3, iclass 4, count 0 2006.211.07:56:40.76#ibcon#about to read 4, iclass 4, count 0 2006.211.07:56:40.76#ibcon#read 4, iclass 4, count 0 2006.211.07:56:40.76#ibcon#about to read 5, iclass 4, count 0 2006.211.07:56:40.76#ibcon#read 5, iclass 4, count 0 2006.211.07:56:40.76#ibcon#about to read 6, iclass 4, count 0 2006.211.07:56:40.76#ibcon#read 6, iclass 4, count 0 2006.211.07:56:40.76#ibcon#end of sib2, iclass 4, count 0 2006.211.07:56:40.76#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:56:40.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:56:40.76#ibcon#[27=USB\r\n] 2006.211.07:56:40.76#ibcon#*before write, iclass 4, count 0 2006.211.07:56:40.76#ibcon#enter sib2, iclass 4, count 0 2006.211.07:56:40.76#ibcon#flushed, iclass 4, count 0 2006.211.07:56:40.76#ibcon#about to write, iclass 4, count 0 2006.211.07:56:40.76#ibcon#wrote, iclass 4, count 0 2006.211.07:56:40.76#ibcon#about to read 3, iclass 4, count 0 2006.211.07:56:40.79#ibcon#read 3, iclass 4, count 0 2006.211.07:56:40.79#ibcon#about to read 4, iclass 4, count 0 2006.211.07:56:40.79#ibcon#read 4, iclass 4, count 0 2006.211.07:56:40.79#ibcon#about to read 5, iclass 4, count 0 2006.211.07:56:40.79#ibcon#read 5, iclass 4, count 0 2006.211.07:56:40.79#ibcon#about to read 6, iclass 4, count 0 2006.211.07:56:40.79#ibcon#read 6, iclass 4, count 0 2006.211.07:56:40.79#ibcon#end of sib2, iclass 4, count 0 2006.211.07:56:40.79#ibcon#*after write, iclass 4, count 0 2006.211.07:56:40.79#ibcon#*before return 0, iclass 4, count 0 2006.211.07:56:40.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:40.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.07:56:40.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:56:40.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:56:40.79$vc4f8/vblo=3,656.99 2006.211.07:56:40.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.07:56:40.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.07:56:40.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:40.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:40.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:40.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:40.79#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:56:40.79#ibcon#first serial, iclass 6, count 0 2006.211.07:56:40.79#ibcon#enter sib2, iclass 6, count 0 2006.211.07:56:40.79#ibcon#flushed, iclass 6, count 0 2006.211.07:56:40.79#ibcon#about to write, iclass 6, count 0 2006.211.07:56:40.79#ibcon#wrote, iclass 6, count 0 2006.211.07:56:40.79#ibcon#about to read 3, iclass 6, count 0 2006.211.07:56:40.81#ibcon#read 3, iclass 6, count 0 2006.211.07:56:40.81#ibcon#about to read 4, iclass 6, count 0 2006.211.07:56:40.81#ibcon#read 4, iclass 6, count 0 2006.211.07:56:40.81#ibcon#about to read 5, iclass 6, count 0 2006.211.07:56:40.81#ibcon#read 5, iclass 6, count 0 2006.211.07:56:40.81#ibcon#about to read 6, iclass 6, count 0 2006.211.07:56:40.81#ibcon#read 6, iclass 6, count 0 2006.211.07:56:40.81#ibcon#end of sib2, iclass 6, count 0 2006.211.07:56:40.81#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:56:40.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:56:40.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:56:40.81#ibcon#*before write, iclass 6, count 0 2006.211.07:56:40.81#ibcon#enter sib2, iclass 6, count 0 2006.211.07:56:40.81#ibcon#flushed, iclass 6, count 0 2006.211.07:56:40.81#ibcon#about to write, iclass 6, count 0 2006.211.07:56:40.81#ibcon#wrote, iclass 6, count 0 2006.211.07:56:40.81#ibcon#about to read 3, iclass 6, count 0 2006.211.07:56:40.85#ibcon#read 3, iclass 6, count 0 2006.211.07:56:40.85#ibcon#about to read 4, iclass 6, count 0 2006.211.07:56:40.85#ibcon#read 4, iclass 6, count 0 2006.211.07:56:40.85#ibcon#about to read 5, iclass 6, count 0 2006.211.07:56:40.85#ibcon#read 5, iclass 6, count 0 2006.211.07:56:40.85#ibcon#about to read 6, iclass 6, count 0 2006.211.07:56:40.85#ibcon#read 6, iclass 6, count 0 2006.211.07:56:40.85#ibcon#end of sib2, iclass 6, count 0 2006.211.07:56:40.85#ibcon#*after write, iclass 6, count 0 2006.211.07:56:40.85#ibcon#*before return 0, iclass 6, count 0 2006.211.07:56:40.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:40.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.07:56:40.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:56:40.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:56:40.85$vc4f8/vb=3,3 2006.211.07:56:40.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.07:56:40.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.07:56:40.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:40.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:40.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:40.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:40.91#ibcon#enter wrdev, iclass 10, count 2 2006.211.07:56:40.91#ibcon#first serial, iclass 10, count 2 2006.211.07:56:40.91#ibcon#enter sib2, iclass 10, count 2 2006.211.07:56:40.91#ibcon#flushed, iclass 10, count 2 2006.211.07:56:40.91#ibcon#about to write, iclass 10, count 2 2006.211.07:56:40.91#ibcon#wrote, iclass 10, count 2 2006.211.07:56:40.91#ibcon#about to read 3, iclass 10, count 2 2006.211.07:56:40.93#ibcon#read 3, iclass 10, count 2 2006.211.07:56:40.93#ibcon#about to read 4, iclass 10, count 2 2006.211.07:56:40.93#ibcon#read 4, iclass 10, count 2 2006.211.07:56:40.93#ibcon#about to read 5, iclass 10, count 2 2006.211.07:56:40.93#ibcon#read 5, iclass 10, count 2 2006.211.07:56:40.93#ibcon#about to read 6, iclass 10, count 2 2006.211.07:56:40.93#ibcon#read 6, iclass 10, count 2 2006.211.07:56:40.93#ibcon#end of sib2, iclass 10, count 2 2006.211.07:56:40.93#ibcon#*mode == 0, iclass 10, count 2 2006.211.07:56:40.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.07:56:40.93#ibcon#[27=AT03-03\r\n] 2006.211.07:56:40.93#ibcon#*before write, iclass 10, count 2 2006.211.07:56:40.93#ibcon#enter sib2, iclass 10, count 2 2006.211.07:56:40.93#ibcon#flushed, iclass 10, count 2 2006.211.07:56:40.93#ibcon#about to write, iclass 10, count 2 2006.211.07:56:40.93#ibcon#wrote, iclass 10, count 2 2006.211.07:56:40.93#ibcon#about to read 3, iclass 10, count 2 2006.211.07:56:40.96#ibcon#read 3, iclass 10, count 2 2006.211.07:56:40.96#ibcon#about to read 4, iclass 10, count 2 2006.211.07:56:40.96#ibcon#read 4, iclass 10, count 2 2006.211.07:56:40.96#ibcon#about to read 5, iclass 10, count 2 2006.211.07:56:40.96#ibcon#read 5, iclass 10, count 2 2006.211.07:56:40.96#ibcon#about to read 6, iclass 10, count 2 2006.211.07:56:40.96#ibcon#read 6, iclass 10, count 2 2006.211.07:56:40.96#ibcon#end of sib2, iclass 10, count 2 2006.211.07:56:40.96#ibcon#*after write, iclass 10, count 2 2006.211.07:56:40.96#ibcon#*before return 0, iclass 10, count 2 2006.211.07:56:40.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:40.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.07:56:40.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.07:56:40.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:40.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:41.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:41.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:41.08#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:56:41.08#ibcon#first serial, iclass 10, count 0 2006.211.07:56:41.08#ibcon#enter sib2, iclass 10, count 0 2006.211.07:56:41.08#ibcon#flushed, iclass 10, count 0 2006.211.07:56:41.08#ibcon#about to write, iclass 10, count 0 2006.211.07:56:41.08#ibcon#wrote, iclass 10, count 0 2006.211.07:56:41.08#ibcon#about to read 3, iclass 10, count 0 2006.211.07:56:41.10#ibcon#read 3, iclass 10, count 0 2006.211.07:56:41.10#ibcon#about to read 4, iclass 10, count 0 2006.211.07:56:41.10#ibcon#read 4, iclass 10, count 0 2006.211.07:56:41.10#ibcon#about to read 5, iclass 10, count 0 2006.211.07:56:41.10#ibcon#read 5, iclass 10, count 0 2006.211.07:56:41.10#ibcon#about to read 6, iclass 10, count 0 2006.211.07:56:41.10#ibcon#read 6, iclass 10, count 0 2006.211.07:56:41.10#ibcon#end of sib2, iclass 10, count 0 2006.211.07:56:41.10#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:56:41.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:56:41.10#ibcon#[27=USB\r\n] 2006.211.07:56:41.10#ibcon#*before write, iclass 10, count 0 2006.211.07:56:41.10#ibcon#enter sib2, iclass 10, count 0 2006.211.07:56:41.10#ibcon#flushed, iclass 10, count 0 2006.211.07:56:41.10#ibcon#about to write, iclass 10, count 0 2006.211.07:56:41.10#ibcon#wrote, iclass 10, count 0 2006.211.07:56:41.10#ibcon#about to read 3, iclass 10, count 0 2006.211.07:56:41.13#ibcon#read 3, iclass 10, count 0 2006.211.07:56:41.13#ibcon#about to read 4, iclass 10, count 0 2006.211.07:56:41.13#ibcon#read 4, iclass 10, count 0 2006.211.07:56:41.13#ibcon#about to read 5, iclass 10, count 0 2006.211.07:56:41.13#ibcon#read 5, iclass 10, count 0 2006.211.07:56:41.13#ibcon#about to read 6, iclass 10, count 0 2006.211.07:56:41.13#ibcon#read 6, iclass 10, count 0 2006.211.07:56:41.13#ibcon#end of sib2, iclass 10, count 0 2006.211.07:56:41.13#ibcon#*after write, iclass 10, count 0 2006.211.07:56:41.13#ibcon#*before return 0, iclass 10, count 0 2006.211.07:56:41.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:41.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.07:56:41.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:56:41.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:56:41.13$vc4f8/vblo=4,712.99 2006.211.07:56:41.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.07:56:41.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.07:56:41.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:41.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:41.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:41.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:41.13#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:56:41.13#ibcon#first serial, iclass 12, count 0 2006.211.07:56:41.13#ibcon#enter sib2, iclass 12, count 0 2006.211.07:56:41.13#ibcon#flushed, iclass 12, count 0 2006.211.07:56:41.13#ibcon#about to write, iclass 12, count 0 2006.211.07:56:41.13#ibcon#wrote, iclass 12, count 0 2006.211.07:56:41.13#ibcon#about to read 3, iclass 12, count 0 2006.211.07:56:41.15#ibcon#read 3, iclass 12, count 0 2006.211.07:56:41.15#ibcon#about to read 4, iclass 12, count 0 2006.211.07:56:41.15#ibcon#read 4, iclass 12, count 0 2006.211.07:56:41.15#ibcon#about to read 5, iclass 12, count 0 2006.211.07:56:41.15#ibcon#read 5, iclass 12, count 0 2006.211.07:56:41.15#ibcon#about to read 6, iclass 12, count 0 2006.211.07:56:41.15#ibcon#read 6, iclass 12, count 0 2006.211.07:56:41.15#ibcon#end of sib2, iclass 12, count 0 2006.211.07:56:41.15#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:56:41.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:56:41.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:56:41.15#ibcon#*before write, iclass 12, count 0 2006.211.07:56:41.15#ibcon#enter sib2, iclass 12, count 0 2006.211.07:56:41.15#ibcon#flushed, iclass 12, count 0 2006.211.07:56:41.15#ibcon#about to write, iclass 12, count 0 2006.211.07:56:41.15#ibcon#wrote, iclass 12, count 0 2006.211.07:56:41.15#ibcon#about to read 3, iclass 12, count 0 2006.211.07:56:41.19#ibcon#read 3, iclass 12, count 0 2006.211.07:56:41.19#ibcon#about to read 4, iclass 12, count 0 2006.211.07:56:41.19#ibcon#read 4, iclass 12, count 0 2006.211.07:56:41.19#ibcon#about to read 5, iclass 12, count 0 2006.211.07:56:41.19#ibcon#read 5, iclass 12, count 0 2006.211.07:56:41.19#ibcon#about to read 6, iclass 12, count 0 2006.211.07:56:41.19#ibcon#read 6, iclass 12, count 0 2006.211.07:56:41.19#ibcon#end of sib2, iclass 12, count 0 2006.211.07:56:41.19#ibcon#*after write, iclass 12, count 0 2006.211.07:56:41.19#ibcon#*before return 0, iclass 12, count 0 2006.211.07:56:41.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:41.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.07:56:41.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:56:41.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:56:41.19$vc4f8/vb=4,3 2006.211.07:56:41.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.07:56:41.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.07:56:41.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:41.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:41.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:41.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:41.25#ibcon#enter wrdev, iclass 14, count 2 2006.211.07:56:41.25#ibcon#first serial, iclass 14, count 2 2006.211.07:56:41.25#ibcon#enter sib2, iclass 14, count 2 2006.211.07:56:41.25#ibcon#flushed, iclass 14, count 2 2006.211.07:56:41.25#ibcon#about to write, iclass 14, count 2 2006.211.07:56:41.25#ibcon#wrote, iclass 14, count 2 2006.211.07:56:41.25#ibcon#about to read 3, iclass 14, count 2 2006.211.07:56:41.27#ibcon#read 3, iclass 14, count 2 2006.211.07:56:41.27#ibcon#about to read 4, iclass 14, count 2 2006.211.07:56:41.27#ibcon#read 4, iclass 14, count 2 2006.211.07:56:41.27#ibcon#about to read 5, iclass 14, count 2 2006.211.07:56:41.27#ibcon#read 5, iclass 14, count 2 2006.211.07:56:41.27#ibcon#about to read 6, iclass 14, count 2 2006.211.07:56:41.27#ibcon#read 6, iclass 14, count 2 2006.211.07:56:41.27#ibcon#end of sib2, iclass 14, count 2 2006.211.07:56:41.27#ibcon#*mode == 0, iclass 14, count 2 2006.211.07:56:41.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.07:56:41.27#ibcon#[27=AT04-03\r\n] 2006.211.07:56:41.27#ibcon#*before write, iclass 14, count 2 2006.211.07:56:41.27#ibcon#enter sib2, iclass 14, count 2 2006.211.07:56:41.27#ibcon#flushed, iclass 14, count 2 2006.211.07:56:41.27#ibcon#about to write, iclass 14, count 2 2006.211.07:56:41.27#ibcon#wrote, iclass 14, count 2 2006.211.07:56:41.27#ibcon#about to read 3, iclass 14, count 2 2006.211.07:56:41.30#ibcon#read 3, iclass 14, count 2 2006.211.07:56:41.30#ibcon#about to read 4, iclass 14, count 2 2006.211.07:56:41.30#ibcon#read 4, iclass 14, count 2 2006.211.07:56:41.30#ibcon#about to read 5, iclass 14, count 2 2006.211.07:56:41.30#ibcon#read 5, iclass 14, count 2 2006.211.07:56:41.30#ibcon#about to read 6, iclass 14, count 2 2006.211.07:56:41.30#ibcon#read 6, iclass 14, count 2 2006.211.07:56:41.30#ibcon#end of sib2, iclass 14, count 2 2006.211.07:56:41.30#ibcon#*after write, iclass 14, count 2 2006.211.07:56:41.30#ibcon#*before return 0, iclass 14, count 2 2006.211.07:56:41.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:41.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.07:56:41.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.07:56:41.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:41.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:41.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:41.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:41.42#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:56:41.42#ibcon#first serial, iclass 14, count 0 2006.211.07:56:41.42#ibcon#enter sib2, iclass 14, count 0 2006.211.07:56:41.42#ibcon#flushed, iclass 14, count 0 2006.211.07:56:41.42#ibcon#about to write, iclass 14, count 0 2006.211.07:56:41.42#ibcon#wrote, iclass 14, count 0 2006.211.07:56:41.42#ibcon#about to read 3, iclass 14, count 0 2006.211.07:56:41.44#ibcon#read 3, iclass 14, count 0 2006.211.07:56:41.44#ibcon#about to read 4, iclass 14, count 0 2006.211.07:56:41.44#ibcon#read 4, iclass 14, count 0 2006.211.07:56:41.44#ibcon#about to read 5, iclass 14, count 0 2006.211.07:56:41.44#ibcon#read 5, iclass 14, count 0 2006.211.07:56:41.44#ibcon#about to read 6, iclass 14, count 0 2006.211.07:56:41.44#ibcon#read 6, iclass 14, count 0 2006.211.07:56:41.44#ibcon#end of sib2, iclass 14, count 0 2006.211.07:56:41.44#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:56:41.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:56:41.44#ibcon#[27=USB\r\n] 2006.211.07:56:41.44#ibcon#*before write, iclass 14, count 0 2006.211.07:56:41.44#ibcon#enter sib2, iclass 14, count 0 2006.211.07:56:41.44#ibcon#flushed, iclass 14, count 0 2006.211.07:56:41.44#ibcon#about to write, iclass 14, count 0 2006.211.07:56:41.44#ibcon#wrote, iclass 14, count 0 2006.211.07:56:41.44#ibcon#about to read 3, iclass 14, count 0 2006.211.07:56:41.47#ibcon#read 3, iclass 14, count 0 2006.211.07:56:41.47#ibcon#about to read 4, iclass 14, count 0 2006.211.07:56:41.47#ibcon#read 4, iclass 14, count 0 2006.211.07:56:41.47#ibcon#about to read 5, iclass 14, count 0 2006.211.07:56:41.47#ibcon#read 5, iclass 14, count 0 2006.211.07:56:41.47#ibcon#about to read 6, iclass 14, count 0 2006.211.07:56:41.47#ibcon#read 6, iclass 14, count 0 2006.211.07:56:41.47#ibcon#end of sib2, iclass 14, count 0 2006.211.07:56:41.47#ibcon#*after write, iclass 14, count 0 2006.211.07:56:41.47#ibcon#*before return 0, iclass 14, count 0 2006.211.07:56:41.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:41.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.07:56:41.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:56:41.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:56:41.47$vc4f8/vblo=5,744.99 2006.211.07:56:41.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.07:56:41.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.07:56:41.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:41.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:41.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:41.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:41.47#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:56:41.47#ibcon#first serial, iclass 16, count 0 2006.211.07:56:41.47#ibcon#enter sib2, iclass 16, count 0 2006.211.07:56:41.47#ibcon#flushed, iclass 16, count 0 2006.211.07:56:41.47#ibcon#about to write, iclass 16, count 0 2006.211.07:56:41.47#ibcon#wrote, iclass 16, count 0 2006.211.07:56:41.47#ibcon#about to read 3, iclass 16, count 0 2006.211.07:56:41.49#ibcon#read 3, iclass 16, count 0 2006.211.07:56:41.49#ibcon#about to read 4, iclass 16, count 0 2006.211.07:56:41.49#ibcon#read 4, iclass 16, count 0 2006.211.07:56:41.49#ibcon#about to read 5, iclass 16, count 0 2006.211.07:56:41.49#ibcon#read 5, iclass 16, count 0 2006.211.07:56:41.49#ibcon#about to read 6, iclass 16, count 0 2006.211.07:56:41.49#ibcon#read 6, iclass 16, count 0 2006.211.07:56:41.49#ibcon#end of sib2, iclass 16, count 0 2006.211.07:56:41.49#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:56:41.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:56:41.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:56:41.49#ibcon#*before write, iclass 16, count 0 2006.211.07:56:41.49#ibcon#enter sib2, iclass 16, count 0 2006.211.07:56:41.49#ibcon#flushed, iclass 16, count 0 2006.211.07:56:41.49#ibcon#about to write, iclass 16, count 0 2006.211.07:56:41.49#ibcon#wrote, iclass 16, count 0 2006.211.07:56:41.49#ibcon#about to read 3, iclass 16, count 0 2006.211.07:56:41.53#ibcon#read 3, iclass 16, count 0 2006.211.07:56:41.53#ibcon#about to read 4, iclass 16, count 0 2006.211.07:56:41.53#ibcon#read 4, iclass 16, count 0 2006.211.07:56:41.53#ibcon#about to read 5, iclass 16, count 0 2006.211.07:56:41.53#ibcon#read 5, iclass 16, count 0 2006.211.07:56:41.53#ibcon#about to read 6, iclass 16, count 0 2006.211.07:56:41.53#ibcon#read 6, iclass 16, count 0 2006.211.07:56:41.53#ibcon#end of sib2, iclass 16, count 0 2006.211.07:56:41.53#ibcon#*after write, iclass 16, count 0 2006.211.07:56:41.53#ibcon#*before return 0, iclass 16, count 0 2006.211.07:56:41.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:41.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.07:56:41.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:56:41.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:56:41.53$vc4f8/vb=5,3 2006.211.07:56:41.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.07:56:41.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.07:56:41.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:41.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:41.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:41.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:41.59#ibcon#enter wrdev, iclass 18, count 2 2006.211.07:56:41.59#ibcon#first serial, iclass 18, count 2 2006.211.07:56:41.59#ibcon#enter sib2, iclass 18, count 2 2006.211.07:56:41.59#ibcon#flushed, iclass 18, count 2 2006.211.07:56:41.59#ibcon#about to write, iclass 18, count 2 2006.211.07:56:41.59#ibcon#wrote, iclass 18, count 2 2006.211.07:56:41.59#ibcon#about to read 3, iclass 18, count 2 2006.211.07:56:41.61#ibcon#read 3, iclass 18, count 2 2006.211.07:56:41.61#ibcon#about to read 4, iclass 18, count 2 2006.211.07:56:41.61#ibcon#read 4, iclass 18, count 2 2006.211.07:56:41.61#ibcon#about to read 5, iclass 18, count 2 2006.211.07:56:41.61#ibcon#read 5, iclass 18, count 2 2006.211.07:56:41.61#ibcon#about to read 6, iclass 18, count 2 2006.211.07:56:41.61#ibcon#read 6, iclass 18, count 2 2006.211.07:56:41.61#ibcon#end of sib2, iclass 18, count 2 2006.211.07:56:41.61#ibcon#*mode == 0, iclass 18, count 2 2006.211.07:56:41.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.07:56:41.61#ibcon#[27=AT05-03\r\n] 2006.211.07:56:41.61#ibcon#*before write, iclass 18, count 2 2006.211.07:56:41.61#ibcon#enter sib2, iclass 18, count 2 2006.211.07:56:41.61#ibcon#flushed, iclass 18, count 2 2006.211.07:56:41.61#ibcon#about to write, iclass 18, count 2 2006.211.07:56:41.61#ibcon#wrote, iclass 18, count 2 2006.211.07:56:41.61#ibcon#about to read 3, iclass 18, count 2 2006.211.07:56:41.64#ibcon#read 3, iclass 18, count 2 2006.211.07:56:41.64#ibcon#about to read 4, iclass 18, count 2 2006.211.07:56:41.64#ibcon#read 4, iclass 18, count 2 2006.211.07:56:41.64#ibcon#about to read 5, iclass 18, count 2 2006.211.07:56:41.64#ibcon#read 5, iclass 18, count 2 2006.211.07:56:41.64#ibcon#about to read 6, iclass 18, count 2 2006.211.07:56:41.64#ibcon#read 6, iclass 18, count 2 2006.211.07:56:41.64#ibcon#end of sib2, iclass 18, count 2 2006.211.07:56:41.64#ibcon#*after write, iclass 18, count 2 2006.211.07:56:41.64#ibcon#*before return 0, iclass 18, count 2 2006.211.07:56:41.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:41.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.07:56:41.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.07:56:41.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:41.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:41.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:41.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:41.76#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:56:41.76#ibcon#first serial, iclass 18, count 0 2006.211.07:56:41.76#ibcon#enter sib2, iclass 18, count 0 2006.211.07:56:41.76#ibcon#flushed, iclass 18, count 0 2006.211.07:56:41.76#ibcon#about to write, iclass 18, count 0 2006.211.07:56:41.76#ibcon#wrote, iclass 18, count 0 2006.211.07:56:41.76#ibcon#about to read 3, iclass 18, count 0 2006.211.07:56:41.78#ibcon#read 3, iclass 18, count 0 2006.211.07:56:41.78#ibcon#about to read 4, iclass 18, count 0 2006.211.07:56:41.78#ibcon#read 4, iclass 18, count 0 2006.211.07:56:41.78#ibcon#about to read 5, iclass 18, count 0 2006.211.07:56:41.78#ibcon#read 5, iclass 18, count 0 2006.211.07:56:41.78#ibcon#about to read 6, iclass 18, count 0 2006.211.07:56:41.78#ibcon#read 6, iclass 18, count 0 2006.211.07:56:41.78#ibcon#end of sib2, iclass 18, count 0 2006.211.07:56:41.78#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:56:41.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:56:41.78#ibcon#[27=USB\r\n] 2006.211.07:56:41.78#ibcon#*before write, iclass 18, count 0 2006.211.07:56:41.78#ibcon#enter sib2, iclass 18, count 0 2006.211.07:56:41.78#ibcon#flushed, iclass 18, count 0 2006.211.07:56:41.78#ibcon#about to write, iclass 18, count 0 2006.211.07:56:41.78#ibcon#wrote, iclass 18, count 0 2006.211.07:56:41.78#ibcon#about to read 3, iclass 18, count 0 2006.211.07:56:41.81#ibcon#read 3, iclass 18, count 0 2006.211.07:56:41.81#ibcon#about to read 4, iclass 18, count 0 2006.211.07:56:41.81#ibcon#read 4, iclass 18, count 0 2006.211.07:56:41.81#ibcon#about to read 5, iclass 18, count 0 2006.211.07:56:41.81#ibcon#read 5, iclass 18, count 0 2006.211.07:56:41.81#ibcon#about to read 6, iclass 18, count 0 2006.211.07:56:41.81#ibcon#read 6, iclass 18, count 0 2006.211.07:56:41.81#ibcon#end of sib2, iclass 18, count 0 2006.211.07:56:41.81#ibcon#*after write, iclass 18, count 0 2006.211.07:56:41.81#ibcon#*before return 0, iclass 18, count 0 2006.211.07:56:41.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:41.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.07:56:41.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:56:41.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:56:41.81$vc4f8/vblo=6,752.99 2006.211.07:56:41.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.07:56:41.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.07:56:41.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:56:41.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:41.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:41.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:41.81#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:56:41.81#ibcon#first serial, iclass 20, count 0 2006.211.07:56:41.81#ibcon#enter sib2, iclass 20, count 0 2006.211.07:56:41.81#ibcon#flushed, iclass 20, count 0 2006.211.07:56:41.81#ibcon#about to write, iclass 20, count 0 2006.211.07:56:41.81#ibcon#wrote, iclass 20, count 0 2006.211.07:56:41.81#ibcon#about to read 3, iclass 20, count 0 2006.211.07:56:41.83#ibcon#read 3, iclass 20, count 0 2006.211.07:56:41.83#ibcon#about to read 4, iclass 20, count 0 2006.211.07:56:41.83#ibcon#read 4, iclass 20, count 0 2006.211.07:56:41.83#ibcon#about to read 5, iclass 20, count 0 2006.211.07:56:41.83#ibcon#read 5, iclass 20, count 0 2006.211.07:56:41.83#ibcon#about to read 6, iclass 20, count 0 2006.211.07:56:41.83#ibcon#read 6, iclass 20, count 0 2006.211.07:56:41.83#ibcon#end of sib2, iclass 20, count 0 2006.211.07:56:41.83#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:56:41.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:56:41.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:56:41.83#ibcon#*before write, iclass 20, count 0 2006.211.07:56:41.83#ibcon#enter sib2, iclass 20, count 0 2006.211.07:56:41.83#ibcon#flushed, iclass 20, count 0 2006.211.07:56:41.83#ibcon#about to write, iclass 20, count 0 2006.211.07:56:41.83#ibcon#wrote, iclass 20, count 0 2006.211.07:56:41.83#ibcon#about to read 3, iclass 20, count 0 2006.211.07:56:41.87#ibcon#read 3, iclass 20, count 0 2006.211.07:56:41.87#ibcon#about to read 4, iclass 20, count 0 2006.211.07:56:41.87#ibcon#read 4, iclass 20, count 0 2006.211.07:56:41.87#ibcon#about to read 5, iclass 20, count 0 2006.211.07:56:41.87#ibcon#read 5, iclass 20, count 0 2006.211.07:56:41.87#ibcon#about to read 6, iclass 20, count 0 2006.211.07:56:41.87#ibcon#read 6, iclass 20, count 0 2006.211.07:56:41.87#ibcon#end of sib2, iclass 20, count 0 2006.211.07:56:41.87#ibcon#*after write, iclass 20, count 0 2006.211.07:56:41.87#ibcon#*before return 0, iclass 20, count 0 2006.211.07:56:41.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:41.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.07:56:41.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:56:41.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:56:41.87$vc4f8/vb=6,3 2006.211.07:56:41.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.07:56:41.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.07:56:41.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:56:41.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:41.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:41.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:41.93#ibcon#enter wrdev, iclass 22, count 2 2006.211.07:56:41.93#ibcon#first serial, iclass 22, count 2 2006.211.07:56:41.93#ibcon#enter sib2, iclass 22, count 2 2006.211.07:56:41.93#ibcon#flushed, iclass 22, count 2 2006.211.07:56:41.93#ibcon#about to write, iclass 22, count 2 2006.211.07:56:41.93#ibcon#wrote, iclass 22, count 2 2006.211.07:56:41.93#ibcon#about to read 3, iclass 22, count 2 2006.211.07:56:41.95#ibcon#read 3, iclass 22, count 2 2006.211.07:56:41.95#ibcon#about to read 4, iclass 22, count 2 2006.211.07:56:41.95#ibcon#read 4, iclass 22, count 2 2006.211.07:56:41.95#ibcon#about to read 5, iclass 22, count 2 2006.211.07:56:41.95#ibcon#read 5, iclass 22, count 2 2006.211.07:56:41.95#ibcon#about to read 6, iclass 22, count 2 2006.211.07:56:41.95#ibcon#read 6, iclass 22, count 2 2006.211.07:56:41.95#ibcon#end of sib2, iclass 22, count 2 2006.211.07:56:41.95#ibcon#*mode == 0, iclass 22, count 2 2006.211.07:56:41.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.07:56:41.95#ibcon#[27=AT06-03\r\n] 2006.211.07:56:41.95#ibcon#*before write, iclass 22, count 2 2006.211.07:56:41.95#ibcon#enter sib2, iclass 22, count 2 2006.211.07:56:41.95#ibcon#flushed, iclass 22, count 2 2006.211.07:56:41.95#ibcon#about to write, iclass 22, count 2 2006.211.07:56:41.95#ibcon#wrote, iclass 22, count 2 2006.211.07:56:41.95#ibcon#about to read 3, iclass 22, count 2 2006.211.07:56:41.98#ibcon#read 3, iclass 22, count 2 2006.211.07:56:41.98#ibcon#about to read 4, iclass 22, count 2 2006.211.07:56:41.98#ibcon#read 4, iclass 22, count 2 2006.211.07:56:41.98#ibcon#about to read 5, iclass 22, count 2 2006.211.07:56:41.98#ibcon#read 5, iclass 22, count 2 2006.211.07:56:41.98#ibcon#about to read 6, iclass 22, count 2 2006.211.07:56:41.98#ibcon#read 6, iclass 22, count 2 2006.211.07:56:41.98#ibcon#end of sib2, iclass 22, count 2 2006.211.07:56:41.98#ibcon#*after write, iclass 22, count 2 2006.211.07:56:41.98#ibcon#*before return 0, iclass 22, count 2 2006.211.07:56:41.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:41.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.07:56:41.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.07:56:41.98#ibcon#ireg 7 cls_cnt 0 2006.211.07:56:41.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:42.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:42.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:42.10#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:56:42.10#ibcon#first serial, iclass 22, count 0 2006.211.07:56:42.10#ibcon#enter sib2, iclass 22, count 0 2006.211.07:56:42.10#ibcon#flushed, iclass 22, count 0 2006.211.07:56:42.10#ibcon#about to write, iclass 22, count 0 2006.211.07:56:42.10#ibcon#wrote, iclass 22, count 0 2006.211.07:56:42.10#ibcon#about to read 3, iclass 22, count 0 2006.211.07:56:42.12#ibcon#read 3, iclass 22, count 0 2006.211.07:56:42.12#ibcon#about to read 4, iclass 22, count 0 2006.211.07:56:42.12#ibcon#read 4, iclass 22, count 0 2006.211.07:56:42.12#ibcon#about to read 5, iclass 22, count 0 2006.211.07:56:42.12#ibcon#read 5, iclass 22, count 0 2006.211.07:56:42.12#ibcon#about to read 6, iclass 22, count 0 2006.211.07:56:42.12#ibcon#read 6, iclass 22, count 0 2006.211.07:56:42.12#ibcon#end of sib2, iclass 22, count 0 2006.211.07:56:42.12#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:56:42.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:56:42.12#ibcon#[27=USB\r\n] 2006.211.07:56:42.12#ibcon#*before write, iclass 22, count 0 2006.211.07:56:42.12#ibcon#enter sib2, iclass 22, count 0 2006.211.07:56:42.12#ibcon#flushed, iclass 22, count 0 2006.211.07:56:42.12#ibcon#about to write, iclass 22, count 0 2006.211.07:56:42.12#ibcon#wrote, iclass 22, count 0 2006.211.07:56:42.12#ibcon#about to read 3, iclass 22, count 0 2006.211.07:56:42.15#ibcon#read 3, iclass 22, count 0 2006.211.07:56:42.15#ibcon#about to read 4, iclass 22, count 0 2006.211.07:56:42.15#ibcon#read 4, iclass 22, count 0 2006.211.07:56:42.15#ibcon#about to read 5, iclass 22, count 0 2006.211.07:56:42.15#ibcon#read 5, iclass 22, count 0 2006.211.07:56:42.15#ibcon#about to read 6, iclass 22, count 0 2006.211.07:56:42.15#ibcon#read 6, iclass 22, count 0 2006.211.07:56:42.15#ibcon#end of sib2, iclass 22, count 0 2006.211.07:56:42.15#ibcon#*after write, iclass 22, count 0 2006.211.07:56:42.15#ibcon#*before return 0, iclass 22, count 0 2006.211.07:56:42.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:42.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.07:56:42.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:56:42.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:56:42.15$vc4f8/vabw=wide 2006.211.07:56:42.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.07:56:42.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.07:56:42.15#ibcon#ireg 8 cls_cnt 0 2006.211.07:56:42.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:42.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:42.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:42.15#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:56:42.15#ibcon#first serial, iclass 24, count 0 2006.211.07:56:42.15#ibcon#enter sib2, iclass 24, count 0 2006.211.07:56:42.15#ibcon#flushed, iclass 24, count 0 2006.211.07:56:42.15#ibcon#about to write, iclass 24, count 0 2006.211.07:56:42.15#ibcon#wrote, iclass 24, count 0 2006.211.07:56:42.15#ibcon#about to read 3, iclass 24, count 0 2006.211.07:56:42.17#ibcon#read 3, iclass 24, count 0 2006.211.07:56:42.17#ibcon#about to read 4, iclass 24, count 0 2006.211.07:56:42.17#ibcon#read 4, iclass 24, count 0 2006.211.07:56:42.17#ibcon#about to read 5, iclass 24, count 0 2006.211.07:56:42.17#ibcon#read 5, iclass 24, count 0 2006.211.07:56:42.17#ibcon#about to read 6, iclass 24, count 0 2006.211.07:56:42.17#ibcon#read 6, iclass 24, count 0 2006.211.07:56:42.17#ibcon#end of sib2, iclass 24, count 0 2006.211.07:56:42.17#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:56:42.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:56:42.17#ibcon#[25=BW32\r\n] 2006.211.07:56:42.17#ibcon#*before write, iclass 24, count 0 2006.211.07:56:42.17#ibcon#enter sib2, iclass 24, count 0 2006.211.07:56:42.17#ibcon#flushed, iclass 24, count 0 2006.211.07:56:42.17#ibcon#about to write, iclass 24, count 0 2006.211.07:56:42.17#ibcon#wrote, iclass 24, count 0 2006.211.07:56:42.17#ibcon#about to read 3, iclass 24, count 0 2006.211.07:56:42.20#ibcon#read 3, iclass 24, count 0 2006.211.07:56:42.20#ibcon#about to read 4, iclass 24, count 0 2006.211.07:56:42.20#ibcon#read 4, iclass 24, count 0 2006.211.07:56:42.20#ibcon#about to read 5, iclass 24, count 0 2006.211.07:56:42.20#ibcon#read 5, iclass 24, count 0 2006.211.07:56:42.20#ibcon#about to read 6, iclass 24, count 0 2006.211.07:56:42.20#ibcon#read 6, iclass 24, count 0 2006.211.07:56:42.20#ibcon#end of sib2, iclass 24, count 0 2006.211.07:56:42.20#ibcon#*after write, iclass 24, count 0 2006.211.07:56:42.20#ibcon#*before return 0, iclass 24, count 0 2006.211.07:56:42.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:42.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.07:56:42.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:56:42.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:56:42.20$vc4f8/vbbw=wide 2006.211.07:56:42.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:56:42.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:56:42.20#ibcon#ireg 8 cls_cnt 0 2006.211.07:56:42.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:56:42.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:56:42.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:56:42.27#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:56:42.27#ibcon#first serial, iclass 26, count 0 2006.211.07:56:42.27#ibcon#enter sib2, iclass 26, count 0 2006.211.07:56:42.27#ibcon#flushed, iclass 26, count 0 2006.211.07:56:42.27#ibcon#about to write, iclass 26, count 0 2006.211.07:56:42.27#ibcon#wrote, iclass 26, count 0 2006.211.07:56:42.27#ibcon#about to read 3, iclass 26, count 0 2006.211.07:56:42.29#ibcon#read 3, iclass 26, count 0 2006.211.07:56:42.29#ibcon#about to read 4, iclass 26, count 0 2006.211.07:56:42.29#ibcon#read 4, iclass 26, count 0 2006.211.07:56:42.29#ibcon#about to read 5, iclass 26, count 0 2006.211.07:56:42.29#ibcon#read 5, iclass 26, count 0 2006.211.07:56:42.29#ibcon#about to read 6, iclass 26, count 0 2006.211.07:56:42.29#ibcon#read 6, iclass 26, count 0 2006.211.07:56:42.29#ibcon#end of sib2, iclass 26, count 0 2006.211.07:56:42.29#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:56:42.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:56:42.29#ibcon#[27=BW32\r\n] 2006.211.07:56:42.29#ibcon#*before write, iclass 26, count 0 2006.211.07:56:42.29#ibcon#enter sib2, iclass 26, count 0 2006.211.07:56:42.29#ibcon#flushed, iclass 26, count 0 2006.211.07:56:42.29#ibcon#about to write, iclass 26, count 0 2006.211.07:56:42.29#ibcon#wrote, iclass 26, count 0 2006.211.07:56:42.29#ibcon#about to read 3, iclass 26, count 0 2006.211.07:56:42.32#ibcon#read 3, iclass 26, count 0 2006.211.07:56:42.32#ibcon#about to read 4, iclass 26, count 0 2006.211.07:56:42.32#ibcon#read 4, iclass 26, count 0 2006.211.07:56:42.32#ibcon#about to read 5, iclass 26, count 0 2006.211.07:56:42.32#ibcon#read 5, iclass 26, count 0 2006.211.07:56:42.32#ibcon#about to read 6, iclass 26, count 0 2006.211.07:56:42.32#ibcon#read 6, iclass 26, count 0 2006.211.07:56:42.32#ibcon#end of sib2, iclass 26, count 0 2006.211.07:56:42.32#ibcon#*after write, iclass 26, count 0 2006.211.07:56:42.32#ibcon#*before return 0, iclass 26, count 0 2006.211.07:56:42.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:56:42.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:56:42.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:56:42.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:56:42.32$4f8m12a/ifd4f 2006.211.07:56:42.32$ifd4f/lo= 2006.211.07:56:42.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:56:42.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:56:42.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:56:42.32$ifd4f/patch= 2006.211.07:56:42.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:56:42.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:56:42.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:56:42.32$4f8m12a/"form=m,16.000,1:2 2006.211.07:56:42.32$4f8m12a/"tpicd 2006.211.07:56:42.32$4f8m12a/echo=off 2006.211.07:56:42.32$4f8m12a/xlog=off 2006.211.07:56:42.32:!2006.211.07:58:50 2006.211.07:56:51.13#trakl#Source acquired 2006.211.07:56:52.14#flagr#flagr/antenna,acquired 2006.211.07:57:39.14#trakl#Off source 2006.211.07:57:39.14?ERROR st -7 Antenna off-source! 2006.211.07:57:39.14#trakl#az 49.297 el 46.768 azerr*cos(el) -0.0012 elerr 0.0169 2006.211.07:57:40.14#flagr#flagr/antenna,off-source 2006.211.07:57:46.14#trakl#Source re-acquired 2006.211.07:57:46.14#flagr#flagr/antenna,re-acquired 2006.211.07:58:50.00:preob 2006.211.07:58:50.14/onsource/TRACKING 2006.211.07:58:50.14:!2006.211.07:59:00 2006.211.07:59:00.00:data_valid=on 2006.211.07:59:00.00:midob 2006.211.07:59:01.14/onsource/TRACKING 2006.211.07:59:01.14/wx/24.82,1010.0,77 2006.211.07:59:01.30/cable/+6.4386E-03 2006.211.07:59:02.39/va/01,08,usb,yes,28,30 2006.211.07:59:02.39/va/02,07,usb,yes,28,30 2006.211.07:59:02.39/va/03,06,usb,yes,30,30 2006.211.07:59:02.39/va/04,07,usb,yes,29,31 2006.211.07:59:02.39/va/05,07,usb,yes,32,34 2006.211.07:59:02.39/va/06,06,usb,yes,31,31 2006.211.07:59:02.39/va/07,06,usb,yes,31,31 2006.211.07:59:02.39/va/08,07,usb,yes,30,29 2006.211.07:59:02.62/valo/01,532.99,yes,locked 2006.211.07:59:02.62/valo/02,572.99,yes,locked 2006.211.07:59:02.62/valo/03,672.99,yes,locked 2006.211.07:59:02.62/valo/04,832.99,yes,locked 2006.211.07:59:02.62/valo/05,652.99,yes,locked 2006.211.07:59:02.62/valo/06,772.99,yes,locked 2006.211.07:59:02.62/valo/07,832.99,yes,locked 2006.211.07:59:02.62/valo/08,852.99,yes,locked 2006.211.07:59:03.71/vb/01,04,usb,yes,28,27 2006.211.07:59:03.71/vb/02,04,usb,yes,30,31 2006.211.07:59:03.71/vb/03,03,usb,yes,33,37 2006.211.07:59:03.71/vb/04,03,usb,yes,34,34 2006.211.07:59:03.71/vb/05,03,usb,yes,32,37 2006.211.07:59:03.71/vb/06,03,usb,yes,33,36 2006.211.07:59:03.71/vb/07,04,usb,yes,29,29 2006.211.07:59:03.71/vb/08,03,usb,yes,33,37 2006.211.07:59:03.94/vblo/01,632.99,yes,locked 2006.211.07:59:03.94/vblo/02,640.99,yes,locked 2006.211.07:59:03.94/vblo/03,656.99,yes,locked 2006.211.07:59:03.94/vblo/04,712.99,yes,locked 2006.211.07:59:03.94/vblo/05,744.99,yes,locked 2006.211.07:59:03.94/vblo/06,752.99,yes,locked 2006.211.07:59:03.94/vblo/07,734.99,yes,locked 2006.211.07:59:03.94/vblo/08,744.99,yes,locked 2006.211.07:59:04.09/vabw/8 2006.211.07:59:04.24/vbbw/8 2006.211.07:59:04.33/xfe/off,on,12.0 2006.211.07:59:04.71/ifatt/23,28,28,28 2006.211.07:59:05.08/fmout-gps/S +4.47E-07 2006.211.07:59:05.12:!2006.211.08:00:00 2006.211.07:59:39.14#trakl#Off source 2006.211.07:59:39.14?ERROR st -7 Antenna off-source! 2006.211.07:59:39.14#trakl#az 49.310 el 47.075 azerr*cos(el) 0.0024 elerr 0.0266 2006.211.07:59:41.14#flagr#flagr/antenna,off-source 2006.211.07:59:45.14#trakl#Source re-acquired 2006.211.07:59:47.14#flagr#flagr/antenna,re-acquired 2006.211.08:00:00.00:data_valid=off 2006.211.08:00:00.00:postob 2006.211.08:00:00.10/cable/+6.4380E-03 2006.211.08:00:00.10/wx/24.80,1010.0,77 2006.211.08:00:01.08/fmout-gps/S +4.48E-07 2006.211.08:00:01.08:scan_name=211-0801,k06211,60 2006.211.08:00:01.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.211.08:00:01.14#flagr#flagr/antenna,new-source 2006.211.08:00:02.14:checkk5 2006.211.08:00:02.47/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:00:02.81/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:00:03.15/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:00:03.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:00:03.84/chk_obsdata//k5ts1/T2110759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:00:04.17/chk_obsdata//k5ts2/T2110759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:00:04.50/chk_obsdata//k5ts3/T2110759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:00:04.83/chk_obsdata//k5ts4/T2110759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:00:05.49/k5log//k5ts1_log_newline 2006.211.08:00:06.15/k5log//k5ts2_log_newline 2006.211.08:00:06.80/k5log//k5ts3_log_newline 2006.211.08:00:07.45/k5log//k5ts4_log_newline 2006.211.08:00:07.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:00:07.47:4f8m12a=2 2006.211.08:00:07.47$4f8m12a/echo=on 2006.211.08:00:07.47$4f8m12a/pcalon 2006.211.08:00:07.47$pcalon/"no phase cal control is implemented here 2006.211.08:00:07.47$4f8m12a/"tpicd=stop 2006.211.08:00:07.47$4f8m12a/vc4f8 2006.211.08:00:07.47$vc4f8/valo=1,532.99 2006.211.08:00:07.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:00:07.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:00:07.48#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:07.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:07.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:07.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:07.48#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:00:07.48#ibcon#first serial, iclass 3, count 0 2006.211.08:00:07.48#ibcon#enter sib2, iclass 3, count 0 2006.211.08:00:07.48#ibcon#flushed, iclass 3, count 0 2006.211.08:00:07.48#ibcon#about to write, iclass 3, count 0 2006.211.08:00:07.48#ibcon#wrote, iclass 3, count 0 2006.211.08:00:07.48#ibcon#about to read 3, iclass 3, count 0 2006.211.08:00:07.50#ibcon#read 3, iclass 3, count 0 2006.211.08:00:07.50#ibcon#about to read 4, iclass 3, count 0 2006.211.08:00:07.50#ibcon#read 4, iclass 3, count 0 2006.211.08:00:07.50#ibcon#about to read 5, iclass 3, count 0 2006.211.08:00:07.50#ibcon#read 5, iclass 3, count 0 2006.211.08:00:07.50#ibcon#about to read 6, iclass 3, count 0 2006.211.08:00:07.50#ibcon#read 6, iclass 3, count 0 2006.211.08:00:07.50#ibcon#end of sib2, iclass 3, count 0 2006.211.08:00:07.50#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:00:07.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:00:07.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:00:07.50#ibcon#*before write, iclass 3, count 0 2006.211.08:00:07.50#ibcon#enter sib2, iclass 3, count 0 2006.211.08:00:07.50#ibcon#flushed, iclass 3, count 0 2006.211.08:00:07.50#ibcon#about to write, iclass 3, count 0 2006.211.08:00:07.50#ibcon#wrote, iclass 3, count 0 2006.211.08:00:07.50#ibcon#about to read 3, iclass 3, count 0 2006.211.08:00:07.55#ibcon#read 3, iclass 3, count 0 2006.211.08:00:07.55#ibcon#about to read 4, iclass 3, count 0 2006.211.08:00:07.55#ibcon#read 4, iclass 3, count 0 2006.211.08:00:07.55#ibcon#about to read 5, iclass 3, count 0 2006.211.08:00:07.55#ibcon#read 5, iclass 3, count 0 2006.211.08:00:07.55#ibcon#about to read 6, iclass 3, count 0 2006.211.08:00:07.55#ibcon#read 6, iclass 3, count 0 2006.211.08:00:07.55#ibcon#end of sib2, iclass 3, count 0 2006.211.08:00:07.55#ibcon#*after write, iclass 3, count 0 2006.211.08:00:07.55#ibcon#*before return 0, iclass 3, count 0 2006.211.08:00:07.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:07.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:07.55#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:00:07.55#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:00:07.55$vc4f8/va=1,8 2006.211.08:00:07.55#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:00:07.55#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:00:07.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:07.55#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:07.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:07.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:07.55#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:00:07.55#ibcon#first serial, iclass 5, count 2 2006.211.08:00:07.55#ibcon#enter sib2, iclass 5, count 2 2006.211.08:00:07.55#ibcon#flushed, iclass 5, count 2 2006.211.08:00:07.55#ibcon#about to write, iclass 5, count 2 2006.211.08:00:07.55#ibcon#wrote, iclass 5, count 2 2006.211.08:00:07.55#ibcon#about to read 3, iclass 5, count 2 2006.211.08:00:07.57#ibcon#read 3, iclass 5, count 2 2006.211.08:00:07.57#ibcon#about to read 4, iclass 5, count 2 2006.211.08:00:07.57#ibcon#read 4, iclass 5, count 2 2006.211.08:00:07.57#ibcon#about to read 5, iclass 5, count 2 2006.211.08:00:07.57#ibcon#read 5, iclass 5, count 2 2006.211.08:00:07.57#ibcon#about to read 6, iclass 5, count 2 2006.211.08:00:07.57#ibcon#read 6, iclass 5, count 2 2006.211.08:00:07.57#ibcon#end of sib2, iclass 5, count 2 2006.211.08:00:07.57#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:00:07.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:00:07.57#ibcon#[25=AT01-08\r\n] 2006.211.08:00:07.57#ibcon#*before write, iclass 5, count 2 2006.211.08:00:07.57#ibcon#enter sib2, iclass 5, count 2 2006.211.08:00:07.57#ibcon#flushed, iclass 5, count 2 2006.211.08:00:07.57#ibcon#about to write, iclass 5, count 2 2006.211.08:00:07.57#ibcon#wrote, iclass 5, count 2 2006.211.08:00:07.57#ibcon#about to read 3, iclass 5, count 2 2006.211.08:00:07.60#ibcon#read 3, iclass 5, count 2 2006.211.08:00:07.60#ibcon#about to read 4, iclass 5, count 2 2006.211.08:00:07.60#ibcon#read 4, iclass 5, count 2 2006.211.08:00:07.60#ibcon#about to read 5, iclass 5, count 2 2006.211.08:00:07.60#ibcon#read 5, iclass 5, count 2 2006.211.08:00:07.60#ibcon#about to read 6, iclass 5, count 2 2006.211.08:00:07.60#ibcon#read 6, iclass 5, count 2 2006.211.08:00:07.60#ibcon#end of sib2, iclass 5, count 2 2006.211.08:00:07.60#ibcon#*after write, iclass 5, count 2 2006.211.08:00:07.60#ibcon#*before return 0, iclass 5, count 2 2006.211.08:00:07.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:07.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:07.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:00:07.60#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:07.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:07.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:07.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:07.72#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:00:07.72#ibcon#first serial, iclass 5, count 0 2006.211.08:00:07.72#ibcon#enter sib2, iclass 5, count 0 2006.211.08:00:07.72#ibcon#flushed, iclass 5, count 0 2006.211.08:00:07.72#ibcon#about to write, iclass 5, count 0 2006.211.08:00:07.72#ibcon#wrote, iclass 5, count 0 2006.211.08:00:07.72#ibcon#about to read 3, iclass 5, count 0 2006.211.08:00:07.74#ibcon#read 3, iclass 5, count 0 2006.211.08:00:07.74#ibcon#about to read 4, iclass 5, count 0 2006.211.08:00:07.74#ibcon#read 4, iclass 5, count 0 2006.211.08:00:07.74#ibcon#about to read 5, iclass 5, count 0 2006.211.08:00:07.74#ibcon#read 5, iclass 5, count 0 2006.211.08:00:07.74#ibcon#about to read 6, iclass 5, count 0 2006.211.08:00:07.74#ibcon#read 6, iclass 5, count 0 2006.211.08:00:07.74#ibcon#end of sib2, iclass 5, count 0 2006.211.08:00:07.74#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:00:07.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:00:07.74#ibcon#[25=USB\r\n] 2006.211.08:00:07.74#ibcon#*before write, iclass 5, count 0 2006.211.08:00:07.74#ibcon#enter sib2, iclass 5, count 0 2006.211.08:00:07.74#ibcon#flushed, iclass 5, count 0 2006.211.08:00:07.74#ibcon#about to write, iclass 5, count 0 2006.211.08:00:07.74#ibcon#wrote, iclass 5, count 0 2006.211.08:00:07.74#ibcon#about to read 3, iclass 5, count 0 2006.211.08:00:07.77#ibcon#read 3, iclass 5, count 0 2006.211.08:00:07.77#ibcon#about to read 4, iclass 5, count 0 2006.211.08:00:07.77#ibcon#read 4, iclass 5, count 0 2006.211.08:00:07.77#ibcon#about to read 5, iclass 5, count 0 2006.211.08:00:07.77#ibcon#read 5, iclass 5, count 0 2006.211.08:00:07.77#ibcon#about to read 6, iclass 5, count 0 2006.211.08:00:07.77#ibcon#read 6, iclass 5, count 0 2006.211.08:00:07.77#ibcon#end of sib2, iclass 5, count 0 2006.211.08:00:07.77#ibcon#*after write, iclass 5, count 0 2006.211.08:00:07.77#ibcon#*before return 0, iclass 5, count 0 2006.211.08:00:07.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:07.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:07.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:00:07.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:00:07.77$vc4f8/valo=2,572.99 2006.211.08:00:07.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:00:07.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:00:07.77#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:07.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:07.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:07.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:07.77#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:00:07.77#ibcon#first serial, iclass 7, count 0 2006.211.08:00:07.77#ibcon#enter sib2, iclass 7, count 0 2006.211.08:00:07.77#ibcon#flushed, iclass 7, count 0 2006.211.08:00:07.77#ibcon#about to write, iclass 7, count 0 2006.211.08:00:07.77#ibcon#wrote, iclass 7, count 0 2006.211.08:00:07.77#ibcon#about to read 3, iclass 7, count 0 2006.211.08:00:07.79#ibcon#read 3, iclass 7, count 0 2006.211.08:00:07.79#ibcon#about to read 4, iclass 7, count 0 2006.211.08:00:07.79#ibcon#read 4, iclass 7, count 0 2006.211.08:00:07.79#ibcon#about to read 5, iclass 7, count 0 2006.211.08:00:07.79#ibcon#read 5, iclass 7, count 0 2006.211.08:00:07.79#ibcon#about to read 6, iclass 7, count 0 2006.211.08:00:07.79#ibcon#read 6, iclass 7, count 0 2006.211.08:00:07.79#ibcon#end of sib2, iclass 7, count 0 2006.211.08:00:07.79#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:00:07.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:00:07.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:00:07.79#ibcon#*before write, iclass 7, count 0 2006.211.08:00:07.79#ibcon#enter sib2, iclass 7, count 0 2006.211.08:00:07.79#ibcon#flushed, iclass 7, count 0 2006.211.08:00:07.79#ibcon#about to write, iclass 7, count 0 2006.211.08:00:07.79#ibcon#wrote, iclass 7, count 0 2006.211.08:00:07.79#ibcon#about to read 3, iclass 7, count 0 2006.211.08:00:07.83#ibcon#read 3, iclass 7, count 0 2006.211.08:00:07.83#ibcon#about to read 4, iclass 7, count 0 2006.211.08:00:07.83#ibcon#read 4, iclass 7, count 0 2006.211.08:00:07.83#ibcon#about to read 5, iclass 7, count 0 2006.211.08:00:07.83#ibcon#read 5, iclass 7, count 0 2006.211.08:00:07.83#ibcon#about to read 6, iclass 7, count 0 2006.211.08:00:07.83#ibcon#read 6, iclass 7, count 0 2006.211.08:00:07.83#ibcon#end of sib2, iclass 7, count 0 2006.211.08:00:07.83#ibcon#*after write, iclass 7, count 0 2006.211.08:00:07.83#ibcon#*before return 0, iclass 7, count 0 2006.211.08:00:07.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:07.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:07.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:00:07.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:00:07.83$vc4f8/va=2,7 2006.211.08:00:07.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:00:07.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:00:07.83#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:07.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:07.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:07.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:07.89#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:00:07.89#ibcon#first serial, iclass 11, count 2 2006.211.08:00:07.89#ibcon#enter sib2, iclass 11, count 2 2006.211.08:00:07.89#ibcon#flushed, iclass 11, count 2 2006.211.08:00:07.89#ibcon#about to write, iclass 11, count 2 2006.211.08:00:07.89#ibcon#wrote, iclass 11, count 2 2006.211.08:00:07.89#ibcon#about to read 3, iclass 11, count 2 2006.211.08:00:07.91#ibcon#read 3, iclass 11, count 2 2006.211.08:00:07.91#ibcon#about to read 4, iclass 11, count 2 2006.211.08:00:07.91#ibcon#read 4, iclass 11, count 2 2006.211.08:00:07.91#ibcon#about to read 5, iclass 11, count 2 2006.211.08:00:07.91#ibcon#read 5, iclass 11, count 2 2006.211.08:00:07.91#ibcon#about to read 6, iclass 11, count 2 2006.211.08:00:07.91#ibcon#read 6, iclass 11, count 2 2006.211.08:00:07.91#ibcon#end of sib2, iclass 11, count 2 2006.211.08:00:07.91#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:00:07.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:00:07.91#ibcon#[25=AT02-07\r\n] 2006.211.08:00:07.91#ibcon#*before write, iclass 11, count 2 2006.211.08:00:07.91#ibcon#enter sib2, iclass 11, count 2 2006.211.08:00:07.91#ibcon#flushed, iclass 11, count 2 2006.211.08:00:07.91#ibcon#about to write, iclass 11, count 2 2006.211.08:00:07.91#ibcon#wrote, iclass 11, count 2 2006.211.08:00:07.91#ibcon#about to read 3, iclass 11, count 2 2006.211.08:00:07.94#ibcon#read 3, iclass 11, count 2 2006.211.08:00:07.94#ibcon#about to read 4, iclass 11, count 2 2006.211.08:00:07.94#ibcon#read 4, iclass 11, count 2 2006.211.08:00:07.94#ibcon#about to read 5, iclass 11, count 2 2006.211.08:00:07.94#ibcon#read 5, iclass 11, count 2 2006.211.08:00:07.94#ibcon#about to read 6, iclass 11, count 2 2006.211.08:00:07.94#ibcon#read 6, iclass 11, count 2 2006.211.08:00:07.94#ibcon#end of sib2, iclass 11, count 2 2006.211.08:00:07.94#ibcon#*after write, iclass 11, count 2 2006.211.08:00:07.94#ibcon#*before return 0, iclass 11, count 2 2006.211.08:00:07.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:07.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:07.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:00:07.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:07.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:08.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:08.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:08.06#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:00:08.06#ibcon#first serial, iclass 11, count 0 2006.211.08:00:08.06#ibcon#enter sib2, iclass 11, count 0 2006.211.08:00:08.06#ibcon#flushed, iclass 11, count 0 2006.211.08:00:08.06#ibcon#about to write, iclass 11, count 0 2006.211.08:00:08.06#ibcon#wrote, iclass 11, count 0 2006.211.08:00:08.06#ibcon#about to read 3, iclass 11, count 0 2006.211.08:00:08.08#ibcon#read 3, iclass 11, count 0 2006.211.08:00:08.08#ibcon#about to read 4, iclass 11, count 0 2006.211.08:00:08.08#ibcon#read 4, iclass 11, count 0 2006.211.08:00:08.08#ibcon#about to read 5, iclass 11, count 0 2006.211.08:00:08.08#ibcon#read 5, iclass 11, count 0 2006.211.08:00:08.08#ibcon#about to read 6, iclass 11, count 0 2006.211.08:00:08.08#ibcon#read 6, iclass 11, count 0 2006.211.08:00:08.08#ibcon#end of sib2, iclass 11, count 0 2006.211.08:00:08.08#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:00:08.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:00:08.08#ibcon#[25=USB\r\n] 2006.211.08:00:08.08#ibcon#*before write, iclass 11, count 0 2006.211.08:00:08.08#ibcon#enter sib2, iclass 11, count 0 2006.211.08:00:08.08#ibcon#flushed, iclass 11, count 0 2006.211.08:00:08.08#ibcon#about to write, iclass 11, count 0 2006.211.08:00:08.08#ibcon#wrote, iclass 11, count 0 2006.211.08:00:08.08#ibcon#about to read 3, iclass 11, count 0 2006.211.08:00:08.11#ibcon#read 3, iclass 11, count 0 2006.211.08:00:08.11#ibcon#about to read 4, iclass 11, count 0 2006.211.08:00:08.11#ibcon#read 4, iclass 11, count 0 2006.211.08:00:08.11#ibcon#about to read 5, iclass 11, count 0 2006.211.08:00:08.11#ibcon#read 5, iclass 11, count 0 2006.211.08:00:08.11#ibcon#about to read 6, iclass 11, count 0 2006.211.08:00:08.11#ibcon#read 6, iclass 11, count 0 2006.211.08:00:08.11#ibcon#end of sib2, iclass 11, count 0 2006.211.08:00:08.11#ibcon#*after write, iclass 11, count 0 2006.211.08:00:08.11#ibcon#*before return 0, iclass 11, count 0 2006.211.08:00:08.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:08.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:08.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:00:08.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:00:08.11$vc4f8/valo=3,672.99 2006.211.08:00:08.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:00:08.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:00:08.11#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:08.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:08.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:08.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:08.11#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:00:08.11#ibcon#first serial, iclass 13, count 0 2006.211.08:00:08.11#ibcon#enter sib2, iclass 13, count 0 2006.211.08:00:08.11#ibcon#flushed, iclass 13, count 0 2006.211.08:00:08.11#ibcon#about to write, iclass 13, count 0 2006.211.08:00:08.11#ibcon#wrote, iclass 13, count 0 2006.211.08:00:08.11#ibcon#about to read 3, iclass 13, count 0 2006.211.08:00:08.13#ibcon#read 3, iclass 13, count 0 2006.211.08:00:08.13#ibcon#about to read 4, iclass 13, count 0 2006.211.08:00:08.13#ibcon#read 4, iclass 13, count 0 2006.211.08:00:08.13#ibcon#about to read 5, iclass 13, count 0 2006.211.08:00:08.13#ibcon#read 5, iclass 13, count 0 2006.211.08:00:08.13#ibcon#about to read 6, iclass 13, count 0 2006.211.08:00:08.13#ibcon#read 6, iclass 13, count 0 2006.211.08:00:08.13#ibcon#end of sib2, iclass 13, count 0 2006.211.08:00:08.13#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:00:08.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:00:08.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:00:08.13#ibcon#*before write, iclass 13, count 0 2006.211.08:00:08.13#ibcon#enter sib2, iclass 13, count 0 2006.211.08:00:08.13#ibcon#flushed, iclass 13, count 0 2006.211.08:00:08.13#ibcon#about to write, iclass 13, count 0 2006.211.08:00:08.13#ibcon#wrote, iclass 13, count 0 2006.211.08:00:08.13#ibcon#about to read 3, iclass 13, count 0 2006.211.08:00:08.17#ibcon#read 3, iclass 13, count 0 2006.211.08:00:08.17#ibcon#about to read 4, iclass 13, count 0 2006.211.08:00:08.17#ibcon#read 4, iclass 13, count 0 2006.211.08:00:08.17#ibcon#about to read 5, iclass 13, count 0 2006.211.08:00:08.17#ibcon#read 5, iclass 13, count 0 2006.211.08:00:08.17#ibcon#about to read 6, iclass 13, count 0 2006.211.08:00:08.17#ibcon#read 6, iclass 13, count 0 2006.211.08:00:08.17#ibcon#end of sib2, iclass 13, count 0 2006.211.08:00:08.17#ibcon#*after write, iclass 13, count 0 2006.211.08:00:08.17#ibcon#*before return 0, iclass 13, count 0 2006.211.08:00:08.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:08.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:08.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:00:08.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:00:08.17$vc4f8/va=3,6 2006.211.08:00:08.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:00:08.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:00:08.17#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:08.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:08.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:08.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:08.23#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:00:08.23#ibcon#first serial, iclass 15, count 2 2006.211.08:00:08.23#ibcon#enter sib2, iclass 15, count 2 2006.211.08:00:08.23#ibcon#flushed, iclass 15, count 2 2006.211.08:00:08.23#ibcon#about to write, iclass 15, count 2 2006.211.08:00:08.23#ibcon#wrote, iclass 15, count 2 2006.211.08:00:08.23#ibcon#about to read 3, iclass 15, count 2 2006.211.08:00:08.25#ibcon#read 3, iclass 15, count 2 2006.211.08:00:08.25#ibcon#about to read 4, iclass 15, count 2 2006.211.08:00:08.25#ibcon#read 4, iclass 15, count 2 2006.211.08:00:08.25#ibcon#about to read 5, iclass 15, count 2 2006.211.08:00:08.25#ibcon#read 5, iclass 15, count 2 2006.211.08:00:08.25#ibcon#about to read 6, iclass 15, count 2 2006.211.08:00:08.25#ibcon#read 6, iclass 15, count 2 2006.211.08:00:08.25#ibcon#end of sib2, iclass 15, count 2 2006.211.08:00:08.25#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:00:08.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:00:08.25#ibcon#[25=AT03-06\r\n] 2006.211.08:00:08.25#ibcon#*before write, iclass 15, count 2 2006.211.08:00:08.25#ibcon#enter sib2, iclass 15, count 2 2006.211.08:00:08.25#ibcon#flushed, iclass 15, count 2 2006.211.08:00:08.25#ibcon#about to write, iclass 15, count 2 2006.211.08:00:08.25#ibcon#wrote, iclass 15, count 2 2006.211.08:00:08.25#ibcon#about to read 3, iclass 15, count 2 2006.211.08:00:08.28#ibcon#read 3, iclass 15, count 2 2006.211.08:00:08.28#ibcon#about to read 4, iclass 15, count 2 2006.211.08:00:08.28#ibcon#read 4, iclass 15, count 2 2006.211.08:00:08.28#ibcon#about to read 5, iclass 15, count 2 2006.211.08:00:08.28#ibcon#read 5, iclass 15, count 2 2006.211.08:00:08.28#ibcon#about to read 6, iclass 15, count 2 2006.211.08:00:08.28#ibcon#read 6, iclass 15, count 2 2006.211.08:00:08.28#ibcon#end of sib2, iclass 15, count 2 2006.211.08:00:08.28#ibcon#*after write, iclass 15, count 2 2006.211.08:00:08.28#ibcon#*before return 0, iclass 15, count 2 2006.211.08:00:08.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:08.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:08.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:00:08.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:08.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:08.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:08.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:08.40#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:00:08.40#ibcon#first serial, iclass 15, count 0 2006.211.08:00:08.40#ibcon#enter sib2, iclass 15, count 0 2006.211.08:00:08.40#ibcon#flushed, iclass 15, count 0 2006.211.08:00:08.40#ibcon#about to write, iclass 15, count 0 2006.211.08:00:08.40#ibcon#wrote, iclass 15, count 0 2006.211.08:00:08.40#ibcon#about to read 3, iclass 15, count 0 2006.211.08:00:08.42#ibcon#read 3, iclass 15, count 0 2006.211.08:00:08.42#ibcon#about to read 4, iclass 15, count 0 2006.211.08:00:08.42#ibcon#read 4, iclass 15, count 0 2006.211.08:00:08.42#ibcon#about to read 5, iclass 15, count 0 2006.211.08:00:08.42#ibcon#read 5, iclass 15, count 0 2006.211.08:00:08.42#ibcon#about to read 6, iclass 15, count 0 2006.211.08:00:08.42#ibcon#read 6, iclass 15, count 0 2006.211.08:00:08.42#ibcon#end of sib2, iclass 15, count 0 2006.211.08:00:08.42#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:00:08.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:00:08.42#ibcon#[25=USB\r\n] 2006.211.08:00:08.42#ibcon#*before write, iclass 15, count 0 2006.211.08:00:08.42#ibcon#enter sib2, iclass 15, count 0 2006.211.08:00:08.42#ibcon#flushed, iclass 15, count 0 2006.211.08:00:08.42#ibcon#about to write, iclass 15, count 0 2006.211.08:00:08.42#ibcon#wrote, iclass 15, count 0 2006.211.08:00:08.42#ibcon#about to read 3, iclass 15, count 0 2006.211.08:00:08.45#abcon#<5=/04 4.4 8.5 24.80 771010.0\r\n> 2006.211.08:00:08.45#ibcon#read 3, iclass 15, count 0 2006.211.08:00:08.45#ibcon#about to read 4, iclass 15, count 0 2006.211.08:00:08.45#ibcon#read 4, iclass 15, count 0 2006.211.08:00:08.45#ibcon#about to read 5, iclass 15, count 0 2006.211.08:00:08.45#ibcon#read 5, iclass 15, count 0 2006.211.08:00:08.45#ibcon#about to read 6, iclass 15, count 0 2006.211.08:00:08.45#ibcon#read 6, iclass 15, count 0 2006.211.08:00:08.45#ibcon#end of sib2, iclass 15, count 0 2006.211.08:00:08.45#ibcon#*after write, iclass 15, count 0 2006.211.08:00:08.45#ibcon#*before return 0, iclass 15, count 0 2006.211.08:00:08.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:08.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:08.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:00:08.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:00:08.45$vc4f8/valo=4,832.99 2006.211.08:00:08.45#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.08:00:08.45#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.08:00:08.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:08.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:00:08.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:00:08.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:00:08.45#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:00:08.45#ibcon#first serial, iclass 20, count 0 2006.211.08:00:08.45#ibcon#enter sib2, iclass 20, count 0 2006.211.08:00:08.45#ibcon#flushed, iclass 20, count 0 2006.211.08:00:08.45#ibcon#about to write, iclass 20, count 0 2006.211.08:00:08.45#ibcon#wrote, iclass 20, count 0 2006.211.08:00:08.45#ibcon#about to read 3, iclass 20, count 0 2006.211.08:00:08.47#abcon#{5=INTERFACE CLEAR} 2006.211.08:00:08.47#ibcon#read 3, iclass 20, count 0 2006.211.08:00:08.47#ibcon#about to read 4, iclass 20, count 0 2006.211.08:00:08.47#ibcon#read 4, iclass 20, count 0 2006.211.08:00:08.47#ibcon#about to read 5, iclass 20, count 0 2006.211.08:00:08.47#ibcon#read 5, iclass 20, count 0 2006.211.08:00:08.47#ibcon#about to read 6, iclass 20, count 0 2006.211.08:00:08.47#ibcon#read 6, iclass 20, count 0 2006.211.08:00:08.47#ibcon#end of sib2, iclass 20, count 0 2006.211.08:00:08.47#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:00:08.47#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:00:08.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:00:08.47#ibcon#*before write, iclass 20, count 0 2006.211.08:00:08.47#ibcon#enter sib2, iclass 20, count 0 2006.211.08:00:08.47#ibcon#flushed, iclass 20, count 0 2006.211.08:00:08.47#ibcon#about to write, iclass 20, count 0 2006.211.08:00:08.47#ibcon#wrote, iclass 20, count 0 2006.211.08:00:08.47#ibcon#about to read 3, iclass 20, count 0 2006.211.08:00:08.51#ibcon#read 3, iclass 20, count 0 2006.211.08:00:08.51#ibcon#about to read 4, iclass 20, count 0 2006.211.08:00:08.51#ibcon#read 4, iclass 20, count 0 2006.211.08:00:08.51#ibcon#about to read 5, iclass 20, count 0 2006.211.08:00:08.51#ibcon#read 5, iclass 20, count 0 2006.211.08:00:08.51#ibcon#about to read 6, iclass 20, count 0 2006.211.08:00:08.51#ibcon#read 6, iclass 20, count 0 2006.211.08:00:08.51#ibcon#end of sib2, iclass 20, count 0 2006.211.08:00:08.51#ibcon#*after write, iclass 20, count 0 2006.211.08:00:08.51#ibcon#*before return 0, iclass 20, count 0 2006.211.08:00:08.51#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:00:08.51#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:00:08.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:00:08.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:00:08.51$vc4f8/va=4,7 2006.211.08:00:08.51#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.08:00:08.51#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.08:00:08.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:08.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:00:08.53#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:00:08.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:00:08.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:00:08.57#ibcon#enter wrdev, iclass 22, count 2 2006.211.08:00:08.57#ibcon#first serial, iclass 22, count 2 2006.211.08:00:08.57#ibcon#enter sib2, iclass 22, count 2 2006.211.08:00:08.57#ibcon#flushed, iclass 22, count 2 2006.211.08:00:08.57#ibcon#about to write, iclass 22, count 2 2006.211.08:00:08.57#ibcon#wrote, iclass 22, count 2 2006.211.08:00:08.57#ibcon#about to read 3, iclass 22, count 2 2006.211.08:00:08.59#ibcon#read 3, iclass 22, count 2 2006.211.08:00:08.59#ibcon#about to read 4, iclass 22, count 2 2006.211.08:00:08.59#ibcon#read 4, iclass 22, count 2 2006.211.08:00:08.59#ibcon#about to read 5, iclass 22, count 2 2006.211.08:00:08.59#ibcon#read 5, iclass 22, count 2 2006.211.08:00:08.59#ibcon#about to read 6, iclass 22, count 2 2006.211.08:00:08.59#ibcon#read 6, iclass 22, count 2 2006.211.08:00:08.59#ibcon#end of sib2, iclass 22, count 2 2006.211.08:00:08.59#ibcon#*mode == 0, iclass 22, count 2 2006.211.08:00:08.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.08:00:08.59#ibcon#[25=AT04-07\r\n] 2006.211.08:00:08.59#ibcon#*before write, iclass 22, count 2 2006.211.08:00:08.59#ibcon#enter sib2, iclass 22, count 2 2006.211.08:00:08.59#ibcon#flushed, iclass 22, count 2 2006.211.08:00:08.59#ibcon#about to write, iclass 22, count 2 2006.211.08:00:08.59#ibcon#wrote, iclass 22, count 2 2006.211.08:00:08.59#ibcon#about to read 3, iclass 22, count 2 2006.211.08:00:08.62#ibcon#read 3, iclass 22, count 2 2006.211.08:00:08.62#ibcon#about to read 4, iclass 22, count 2 2006.211.08:00:08.62#ibcon#read 4, iclass 22, count 2 2006.211.08:00:08.62#ibcon#about to read 5, iclass 22, count 2 2006.211.08:00:08.62#ibcon#read 5, iclass 22, count 2 2006.211.08:00:08.62#ibcon#about to read 6, iclass 22, count 2 2006.211.08:00:08.62#ibcon#read 6, iclass 22, count 2 2006.211.08:00:08.62#ibcon#end of sib2, iclass 22, count 2 2006.211.08:00:08.62#ibcon#*after write, iclass 22, count 2 2006.211.08:00:08.62#ibcon#*before return 0, iclass 22, count 2 2006.211.08:00:08.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:00:08.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:00:08.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.08:00:08.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:08.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:00:08.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:00:08.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:00:08.74#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:00:08.74#ibcon#first serial, iclass 22, count 0 2006.211.08:00:08.74#ibcon#enter sib2, iclass 22, count 0 2006.211.08:00:08.74#ibcon#flushed, iclass 22, count 0 2006.211.08:00:08.74#ibcon#about to write, iclass 22, count 0 2006.211.08:00:08.74#ibcon#wrote, iclass 22, count 0 2006.211.08:00:08.74#ibcon#about to read 3, iclass 22, count 0 2006.211.08:00:08.76#ibcon#read 3, iclass 22, count 0 2006.211.08:00:08.76#ibcon#about to read 4, iclass 22, count 0 2006.211.08:00:08.76#ibcon#read 4, iclass 22, count 0 2006.211.08:00:08.76#ibcon#about to read 5, iclass 22, count 0 2006.211.08:00:08.76#ibcon#read 5, iclass 22, count 0 2006.211.08:00:08.76#ibcon#about to read 6, iclass 22, count 0 2006.211.08:00:08.76#ibcon#read 6, iclass 22, count 0 2006.211.08:00:08.76#ibcon#end of sib2, iclass 22, count 0 2006.211.08:00:08.76#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:00:08.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:00:08.76#ibcon#[25=USB\r\n] 2006.211.08:00:08.76#ibcon#*before write, iclass 22, count 0 2006.211.08:00:08.76#ibcon#enter sib2, iclass 22, count 0 2006.211.08:00:08.76#ibcon#flushed, iclass 22, count 0 2006.211.08:00:08.76#ibcon#about to write, iclass 22, count 0 2006.211.08:00:08.76#ibcon#wrote, iclass 22, count 0 2006.211.08:00:08.76#ibcon#about to read 3, iclass 22, count 0 2006.211.08:00:08.79#ibcon#read 3, iclass 22, count 0 2006.211.08:00:08.79#ibcon#about to read 4, iclass 22, count 0 2006.211.08:00:08.79#ibcon#read 4, iclass 22, count 0 2006.211.08:00:08.79#ibcon#about to read 5, iclass 22, count 0 2006.211.08:00:08.79#ibcon#read 5, iclass 22, count 0 2006.211.08:00:08.79#ibcon#about to read 6, iclass 22, count 0 2006.211.08:00:08.79#ibcon#read 6, iclass 22, count 0 2006.211.08:00:08.79#ibcon#end of sib2, iclass 22, count 0 2006.211.08:00:08.79#ibcon#*after write, iclass 22, count 0 2006.211.08:00:08.79#ibcon#*before return 0, iclass 22, count 0 2006.211.08:00:08.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:00:08.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:00:08.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:00:08.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:00:08.79$vc4f8/valo=5,652.99 2006.211.08:00:08.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:00:08.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:00:08.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:08.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:08.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:08.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:08.79#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:00:08.79#ibcon#first serial, iclass 25, count 0 2006.211.08:00:08.79#ibcon#enter sib2, iclass 25, count 0 2006.211.08:00:08.79#ibcon#flushed, iclass 25, count 0 2006.211.08:00:08.79#ibcon#about to write, iclass 25, count 0 2006.211.08:00:08.79#ibcon#wrote, iclass 25, count 0 2006.211.08:00:08.79#ibcon#about to read 3, iclass 25, count 0 2006.211.08:00:08.81#ibcon#read 3, iclass 25, count 0 2006.211.08:00:08.81#ibcon#about to read 4, iclass 25, count 0 2006.211.08:00:08.81#ibcon#read 4, iclass 25, count 0 2006.211.08:00:08.81#ibcon#about to read 5, iclass 25, count 0 2006.211.08:00:08.81#ibcon#read 5, iclass 25, count 0 2006.211.08:00:08.81#ibcon#about to read 6, iclass 25, count 0 2006.211.08:00:08.81#ibcon#read 6, iclass 25, count 0 2006.211.08:00:08.81#ibcon#end of sib2, iclass 25, count 0 2006.211.08:00:08.81#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:00:08.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:00:08.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:00:08.81#ibcon#*before write, iclass 25, count 0 2006.211.08:00:08.81#ibcon#enter sib2, iclass 25, count 0 2006.211.08:00:08.81#ibcon#flushed, iclass 25, count 0 2006.211.08:00:08.81#ibcon#about to write, iclass 25, count 0 2006.211.08:00:08.81#ibcon#wrote, iclass 25, count 0 2006.211.08:00:08.81#ibcon#about to read 3, iclass 25, count 0 2006.211.08:00:08.85#ibcon#read 3, iclass 25, count 0 2006.211.08:00:08.85#ibcon#about to read 4, iclass 25, count 0 2006.211.08:00:08.85#ibcon#read 4, iclass 25, count 0 2006.211.08:00:08.85#ibcon#about to read 5, iclass 25, count 0 2006.211.08:00:08.85#ibcon#read 5, iclass 25, count 0 2006.211.08:00:08.85#ibcon#about to read 6, iclass 25, count 0 2006.211.08:00:08.85#ibcon#read 6, iclass 25, count 0 2006.211.08:00:08.85#ibcon#end of sib2, iclass 25, count 0 2006.211.08:00:08.85#ibcon#*after write, iclass 25, count 0 2006.211.08:00:08.85#ibcon#*before return 0, iclass 25, count 0 2006.211.08:00:08.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:08.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:08.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:00:08.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:00:08.85$vc4f8/va=5,7 2006.211.08:00:08.85#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:00:08.85#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:00:08.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:08.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:08.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:08.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:08.91#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:00:08.91#ibcon#first serial, iclass 27, count 2 2006.211.08:00:08.91#ibcon#enter sib2, iclass 27, count 2 2006.211.08:00:08.91#ibcon#flushed, iclass 27, count 2 2006.211.08:00:08.91#ibcon#about to write, iclass 27, count 2 2006.211.08:00:08.91#ibcon#wrote, iclass 27, count 2 2006.211.08:00:08.91#ibcon#about to read 3, iclass 27, count 2 2006.211.08:00:08.93#ibcon#read 3, iclass 27, count 2 2006.211.08:00:08.93#ibcon#about to read 4, iclass 27, count 2 2006.211.08:00:08.93#ibcon#read 4, iclass 27, count 2 2006.211.08:00:08.93#ibcon#about to read 5, iclass 27, count 2 2006.211.08:00:08.93#ibcon#read 5, iclass 27, count 2 2006.211.08:00:08.93#ibcon#about to read 6, iclass 27, count 2 2006.211.08:00:08.93#ibcon#read 6, iclass 27, count 2 2006.211.08:00:08.93#ibcon#end of sib2, iclass 27, count 2 2006.211.08:00:08.93#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:00:08.93#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:00:08.93#ibcon#[25=AT05-07\r\n] 2006.211.08:00:08.93#ibcon#*before write, iclass 27, count 2 2006.211.08:00:08.93#ibcon#enter sib2, iclass 27, count 2 2006.211.08:00:08.93#ibcon#flushed, iclass 27, count 2 2006.211.08:00:08.93#ibcon#about to write, iclass 27, count 2 2006.211.08:00:08.93#ibcon#wrote, iclass 27, count 2 2006.211.08:00:08.93#ibcon#about to read 3, iclass 27, count 2 2006.211.08:00:08.96#ibcon#read 3, iclass 27, count 2 2006.211.08:00:08.96#ibcon#about to read 4, iclass 27, count 2 2006.211.08:00:08.96#ibcon#read 4, iclass 27, count 2 2006.211.08:00:08.96#ibcon#about to read 5, iclass 27, count 2 2006.211.08:00:08.96#ibcon#read 5, iclass 27, count 2 2006.211.08:00:08.96#ibcon#about to read 6, iclass 27, count 2 2006.211.08:00:08.96#ibcon#read 6, iclass 27, count 2 2006.211.08:00:08.96#ibcon#end of sib2, iclass 27, count 2 2006.211.08:00:08.96#ibcon#*after write, iclass 27, count 2 2006.211.08:00:08.96#ibcon#*before return 0, iclass 27, count 2 2006.211.08:00:08.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:08.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:08.96#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:00:08.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:08.96#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:09.08#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:09.08#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:09.08#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:00:09.08#ibcon#first serial, iclass 27, count 0 2006.211.08:00:09.08#ibcon#enter sib2, iclass 27, count 0 2006.211.08:00:09.08#ibcon#flushed, iclass 27, count 0 2006.211.08:00:09.08#ibcon#about to write, iclass 27, count 0 2006.211.08:00:09.08#ibcon#wrote, iclass 27, count 0 2006.211.08:00:09.08#ibcon#about to read 3, iclass 27, count 0 2006.211.08:00:09.10#ibcon#read 3, iclass 27, count 0 2006.211.08:00:09.10#ibcon#about to read 4, iclass 27, count 0 2006.211.08:00:09.10#ibcon#read 4, iclass 27, count 0 2006.211.08:00:09.10#ibcon#about to read 5, iclass 27, count 0 2006.211.08:00:09.10#ibcon#read 5, iclass 27, count 0 2006.211.08:00:09.10#ibcon#about to read 6, iclass 27, count 0 2006.211.08:00:09.10#ibcon#read 6, iclass 27, count 0 2006.211.08:00:09.10#ibcon#end of sib2, iclass 27, count 0 2006.211.08:00:09.10#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:00:09.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:00:09.10#ibcon#[25=USB\r\n] 2006.211.08:00:09.10#ibcon#*before write, iclass 27, count 0 2006.211.08:00:09.10#ibcon#enter sib2, iclass 27, count 0 2006.211.08:00:09.10#ibcon#flushed, iclass 27, count 0 2006.211.08:00:09.10#ibcon#about to write, iclass 27, count 0 2006.211.08:00:09.10#ibcon#wrote, iclass 27, count 0 2006.211.08:00:09.10#ibcon#about to read 3, iclass 27, count 0 2006.211.08:00:09.13#ibcon#read 3, iclass 27, count 0 2006.211.08:00:09.13#ibcon#about to read 4, iclass 27, count 0 2006.211.08:00:09.13#ibcon#read 4, iclass 27, count 0 2006.211.08:00:09.13#ibcon#about to read 5, iclass 27, count 0 2006.211.08:00:09.13#ibcon#read 5, iclass 27, count 0 2006.211.08:00:09.13#ibcon#about to read 6, iclass 27, count 0 2006.211.08:00:09.13#ibcon#read 6, iclass 27, count 0 2006.211.08:00:09.13#ibcon#end of sib2, iclass 27, count 0 2006.211.08:00:09.13#ibcon#*after write, iclass 27, count 0 2006.211.08:00:09.13#ibcon#*before return 0, iclass 27, count 0 2006.211.08:00:09.13#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:09.13#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:09.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:00:09.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:00:09.13$vc4f8/valo=6,772.99 2006.211.08:00:09.13#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:00:09.13#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:00:09.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:09.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:09.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:09.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:09.13#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:00:09.13#ibcon#first serial, iclass 29, count 0 2006.211.08:00:09.13#ibcon#enter sib2, iclass 29, count 0 2006.211.08:00:09.13#ibcon#flushed, iclass 29, count 0 2006.211.08:00:09.13#ibcon#about to write, iclass 29, count 0 2006.211.08:00:09.13#ibcon#wrote, iclass 29, count 0 2006.211.08:00:09.13#ibcon#about to read 3, iclass 29, count 0 2006.211.08:00:09.15#ibcon#read 3, iclass 29, count 0 2006.211.08:00:09.15#ibcon#about to read 4, iclass 29, count 0 2006.211.08:00:09.15#ibcon#read 4, iclass 29, count 0 2006.211.08:00:09.15#ibcon#about to read 5, iclass 29, count 0 2006.211.08:00:09.15#ibcon#read 5, iclass 29, count 0 2006.211.08:00:09.15#ibcon#about to read 6, iclass 29, count 0 2006.211.08:00:09.15#ibcon#read 6, iclass 29, count 0 2006.211.08:00:09.15#ibcon#end of sib2, iclass 29, count 0 2006.211.08:00:09.15#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:00:09.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:00:09.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:00:09.15#ibcon#*before write, iclass 29, count 0 2006.211.08:00:09.15#ibcon#enter sib2, iclass 29, count 0 2006.211.08:00:09.15#ibcon#flushed, iclass 29, count 0 2006.211.08:00:09.15#ibcon#about to write, iclass 29, count 0 2006.211.08:00:09.15#ibcon#wrote, iclass 29, count 0 2006.211.08:00:09.15#ibcon#about to read 3, iclass 29, count 0 2006.211.08:00:09.19#ibcon#read 3, iclass 29, count 0 2006.211.08:00:09.19#ibcon#about to read 4, iclass 29, count 0 2006.211.08:00:09.19#ibcon#read 4, iclass 29, count 0 2006.211.08:00:09.19#ibcon#about to read 5, iclass 29, count 0 2006.211.08:00:09.19#ibcon#read 5, iclass 29, count 0 2006.211.08:00:09.19#ibcon#about to read 6, iclass 29, count 0 2006.211.08:00:09.19#ibcon#read 6, iclass 29, count 0 2006.211.08:00:09.19#ibcon#end of sib2, iclass 29, count 0 2006.211.08:00:09.19#ibcon#*after write, iclass 29, count 0 2006.211.08:00:09.19#ibcon#*before return 0, iclass 29, count 0 2006.211.08:00:09.19#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:09.19#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:09.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:00:09.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:00:09.19$vc4f8/va=6,6 2006.211.08:00:09.19#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.08:00:09.19#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.08:00:09.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:09.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:00:09.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:00:09.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:00:09.25#ibcon#enter wrdev, iclass 31, count 2 2006.211.08:00:09.25#ibcon#first serial, iclass 31, count 2 2006.211.08:00:09.25#ibcon#enter sib2, iclass 31, count 2 2006.211.08:00:09.25#ibcon#flushed, iclass 31, count 2 2006.211.08:00:09.25#ibcon#about to write, iclass 31, count 2 2006.211.08:00:09.25#ibcon#wrote, iclass 31, count 2 2006.211.08:00:09.25#ibcon#about to read 3, iclass 31, count 2 2006.211.08:00:09.27#ibcon#read 3, iclass 31, count 2 2006.211.08:00:09.27#ibcon#about to read 4, iclass 31, count 2 2006.211.08:00:09.27#ibcon#read 4, iclass 31, count 2 2006.211.08:00:09.27#ibcon#about to read 5, iclass 31, count 2 2006.211.08:00:09.27#ibcon#read 5, iclass 31, count 2 2006.211.08:00:09.27#ibcon#about to read 6, iclass 31, count 2 2006.211.08:00:09.27#ibcon#read 6, iclass 31, count 2 2006.211.08:00:09.27#ibcon#end of sib2, iclass 31, count 2 2006.211.08:00:09.27#ibcon#*mode == 0, iclass 31, count 2 2006.211.08:00:09.27#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.08:00:09.27#ibcon#[25=AT06-06\r\n] 2006.211.08:00:09.27#ibcon#*before write, iclass 31, count 2 2006.211.08:00:09.27#ibcon#enter sib2, iclass 31, count 2 2006.211.08:00:09.27#ibcon#flushed, iclass 31, count 2 2006.211.08:00:09.27#ibcon#about to write, iclass 31, count 2 2006.211.08:00:09.27#ibcon#wrote, iclass 31, count 2 2006.211.08:00:09.27#ibcon#about to read 3, iclass 31, count 2 2006.211.08:00:09.30#ibcon#read 3, iclass 31, count 2 2006.211.08:00:09.30#ibcon#about to read 4, iclass 31, count 2 2006.211.08:00:09.30#ibcon#read 4, iclass 31, count 2 2006.211.08:00:09.30#ibcon#about to read 5, iclass 31, count 2 2006.211.08:00:09.30#ibcon#read 5, iclass 31, count 2 2006.211.08:00:09.30#ibcon#about to read 6, iclass 31, count 2 2006.211.08:00:09.30#ibcon#read 6, iclass 31, count 2 2006.211.08:00:09.30#ibcon#end of sib2, iclass 31, count 2 2006.211.08:00:09.30#ibcon#*after write, iclass 31, count 2 2006.211.08:00:09.30#ibcon#*before return 0, iclass 31, count 2 2006.211.08:00:09.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:00:09.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:00:09.30#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.08:00:09.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:09.30#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:00:09.42#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:00:09.42#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:00:09.42#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:00:09.42#ibcon#first serial, iclass 31, count 0 2006.211.08:00:09.42#ibcon#enter sib2, iclass 31, count 0 2006.211.08:00:09.42#ibcon#flushed, iclass 31, count 0 2006.211.08:00:09.42#ibcon#about to write, iclass 31, count 0 2006.211.08:00:09.42#ibcon#wrote, iclass 31, count 0 2006.211.08:00:09.42#ibcon#about to read 3, iclass 31, count 0 2006.211.08:00:09.44#ibcon#read 3, iclass 31, count 0 2006.211.08:00:09.44#ibcon#about to read 4, iclass 31, count 0 2006.211.08:00:09.44#ibcon#read 4, iclass 31, count 0 2006.211.08:00:09.44#ibcon#about to read 5, iclass 31, count 0 2006.211.08:00:09.44#ibcon#read 5, iclass 31, count 0 2006.211.08:00:09.44#ibcon#about to read 6, iclass 31, count 0 2006.211.08:00:09.44#ibcon#read 6, iclass 31, count 0 2006.211.08:00:09.44#ibcon#end of sib2, iclass 31, count 0 2006.211.08:00:09.44#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:00:09.44#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:00:09.44#ibcon#[25=USB\r\n] 2006.211.08:00:09.44#ibcon#*before write, iclass 31, count 0 2006.211.08:00:09.44#ibcon#enter sib2, iclass 31, count 0 2006.211.08:00:09.44#ibcon#flushed, iclass 31, count 0 2006.211.08:00:09.44#ibcon#about to write, iclass 31, count 0 2006.211.08:00:09.44#ibcon#wrote, iclass 31, count 0 2006.211.08:00:09.44#ibcon#about to read 3, iclass 31, count 0 2006.211.08:00:09.47#ibcon#read 3, iclass 31, count 0 2006.211.08:00:09.47#ibcon#about to read 4, iclass 31, count 0 2006.211.08:00:09.47#ibcon#read 4, iclass 31, count 0 2006.211.08:00:09.47#ibcon#about to read 5, iclass 31, count 0 2006.211.08:00:09.47#ibcon#read 5, iclass 31, count 0 2006.211.08:00:09.47#ibcon#about to read 6, iclass 31, count 0 2006.211.08:00:09.47#ibcon#read 6, iclass 31, count 0 2006.211.08:00:09.47#ibcon#end of sib2, iclass 31, count 0 2006.211.08:00:09.47#ibcon#*after write, iclass 31, count 0 2006.211.08:00:09.47#ibcon#*before return 0, iclass 31, count 0 2006.211.08:00:09.47#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:00:09.47#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:00:09.47#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:00:09.47#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:00:09.47$vc4f8/valo=7,832.99 2006.211.08:00:09.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.08:00:09.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.08:00:09.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:09.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:00:09.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:00:09.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:00:09.47#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:00:09.47#ibcon#first serial, iclass 33, count 0 2006.211.08:00:09.47#ibcon#enter sib2, iclass 33, count 0 2006.211.08:00:09.47#ibcon#flushed, iclass 33, count 0 2006.211.08:00:09.47#ibcon#about to write, iclass 33, count 0 2006.211.08:00:09.47#ibcon#wrote, iclass 33, count 0 2006.211.08:00:09.47#ibcon#about to read 3, iclass 33, count 0 2006.211.08:00:09.49#ibcon#read 3, iclass 33, count 0 2006.211.08:00:09.49#ibcon#about to read 4, iclass 33, count 0 2006.211.08:00:09.49#ibcon#read 4, iclass 33, count 0 2006.211.08:00:09.49#ibcon#about to read 5, iclass 33, count 0 2006.211.08:00:09.49#ibcon#read 5, iclass 33, count 0 2006.211.08:00:09.49#ibcon#about to read 6, iclass 33, count 0 2006.211.08:00:09.49#ibcon#read 6, iclass 33, count 0 2006.211.08:00:09.49#ibcon#end of sib2, iclass 33, count 0 2006.211.08:00:09.49#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:00:09.49#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:00:09.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:00:09.49#ibcon#*before write, iclass 33, count 0 2006.211.08:00:09.49#ibcon#enter sib2, iclass 33, count 0 2006.211.08:00:09.49#ibcon#flushed, iclass 33, count 0 2006.211.08:00:09.49#ibcon#about to write, iclass 33, count 0 2006.211.08:00:09.49#ibcon#wrote, iclass 33, count 0 2006.211.08:00:09.49#ibcon#about to read 3, iclass 33, count 0 2006.211.08:00:09.53#ibcon#read 3, iclass 33, count 0 2006.211.08:00:09.53#ibcon#about to read 4, iclass 33, count 0 2006.211.08:00:09.53#ibcon#read 4, iclass 33, count 0 2006.211.08:00:09.53#ibcon#about to read 5, iclass 33, count 0 2006.211.08:00:09.53#ibcon#read 5, iclass 33, count 0 2006.211.08:00:09.53#ibcon#about to read 6, iclass 33, count 0 2006.211.08:00:09.53#ibcon#read 6, iclass 33, count 0 2006.211.08:00:09.53#ibcon#end of sib2, iclass 33, count 0 2006.211.08:00:09.53#ibcon#*after write, iclass 33, count 0 2006.211.08:00:09.53#ibcon#*before return 0, iclass 33, count 0 2006.211.08:00:09.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:00:09.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:00:09.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:00:09.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:00:09.53$vc4f8/va=7,6 2006.211.08:00:09.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:00:09.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:00:09.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:09.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:00:09.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:00:09.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:00:09.59#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:00:09.59#ibcon#first serial, iclass 35, count 2 2006.211.08:00:09.59#ibcon#enter sib2, iclass 35, count 2 2006.211.08:00:09.59#ibcon#flushed, iclass 35, count 2 2006.211.08:00:09.59#ibcon#about to write, iclass 35, count 2 2006.211.08:00:09.59#ibcon#wrote, iclass 35, count 2 2006.211.08:00:09.59#ibcon#about to read 3, iclass 35, count 2 2006.211.08:00:09.61#ibcon#read 3, iclass 35, count 2 2006.211.08:00:09.61#ibcon#about to read 4, iclass 35, count 2 2006.211.08:00:09.61#ibcon#read 4, iclass 35, count 2 2006.211.08:00:09.61#ibcon#about to read 5, iclass 35, count 2 2006.211.08:00:09.61#ibcon#read 5, iclass 35, count 2 2006.211.08:00:09.61#ibcon#about to read 6, iclass 35, count 2 2006.211.08:00:09.61#ibcon#read 6, iclass 35, count 2 2006.211.08:00:09.61#ibcon#end of sib2, iclass 35, count 2 2006.211.08:00:09.61#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:00:09.61#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:00:09.61#ibcon#[25=AT07-06\r\n] 2006.211.08:00:09.61#ibcon#*before write, iclass 35, count 2 2006.211.08:00:09.61#ibcon#enter sib2, iclass 35, count 2 2006.211.08:00:09.61#ibcon#flushed, iclass 35, count 2 2006.211.08:00:09.61#ibcon#about to write, iclass 35, count 2 2006.211.08:00:09.61#ibcon#wrote, iclass 35, count 2 2006.211.08:00:09.61#ibcon#about to read 3, iclass 35, count 2 2006.211.08:00:09.64#ibcon#read 3, iclass 35, count 2 2006.211.08:00:09.64#ibcon#about to read 4, iclass 35, count 2 2006.211.08:00:09.64#ibcon#read 4, iclass 35, count 2 2006.211.08:00:09.64#ibcon#about to read 5, iclass 35, count 2 2006.211.08:00:09.64#ibcon#read 5, iclass 35, count 2 2006.211.08:00:09.64#ibcon#about to read 6, iclass 35, count 2 2006.211.08:00:09.64#ibcon#read 6, iclass 35, count 2 2006.211.08:00:09.64#ibcon#end of sib2, iclass 35, count 2 2006.211.08:00:09.64#ibcon#*after write, iclass 35, count 2 2006.211.08:00:09.64#ibcon#*before return 0, iclass 35, count 2 2006.211.08:00:09.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:00:09.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:00:09.64#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:00:09.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:09.64#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:00:09.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:00:09.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:00:09.76#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:00:09.76#ibcon#first serial, iclass 35, count 0 2006.211.08:00:09.76#ibcon#enter sib2, iclass 35, count 0 2006.211.08:00:09.76#ibcon#flushed, iclass 35, count 0 2006.211.08:00:09.76#ibcon#about to write, iclass 35, count 0 2006.211.08:00:09.76#ibcon#wrote, iclass 35, count 0 2006.211.08:00:09.76#ibcon#about to read 3, iclass 35, count 0 2006.211.08:00:09.78#ibcon#read 3, iclass 35, count 0 2006.211.08:00:09.78#ibcon#about to read 4, iclass 35, count 0 2006.211.08:00:09.78#ibcon#read 4, iclass 35, count 0 2006.211.08:00:09.78#ibcon#about to read 5, iclass 35, count 0 2006.211.08:00:09.78#ibcon#read 5, iclass 35, count 0 2006.211.08:00:09.78#ibcon#about to read 6, iclass 35, count 0 2006.211.08:00:09.78#ibcon#read 6, iclass 35, count 0 2006.211.08:00:09.78#ibcon#end of sib2, iclass 35, count 0 2006.211.08:00:09.78#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:00:09.78#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:00:09.78#ibcon#[25=USB\r\n] 2006.211.08:00:09.78#ibcon#*before write, iclass 35, count 0 2006.211.08:00:09.78#ibcon#enter sib2, iclass 35, count 0 2006.211.08:00:09.78#ibcon#flushed, iclass 35, count 0 2006.211.08:00:09.78#ibcon#about to write, iclass 35, count 0 2006.211.08:00:09.78#ibcon#wrote, iclass 35, count 0 2006.211.08:00:09.78#ibcon#about to read 3, iclass 35, count 0 2006.211.08:00:09.81#ibcon#read 3, iclass 35, count 0 2006.211.08:00:09.81#ibcon#about to read 4, iclass 35, count 0 2006.211.08:00:09.81#ibcon#read 4, iclass 35, count 0 2006.211.08:00:09.81#ibcon#about to read 5, iclass 35, count 0 2006.211.08:00:09.81#ibcon#read 5, iclass 35, count 0 2006.211.08:00:09.81#ibcon#about to read 6, iclass 35, count 0 2006.211.08:00:09.81#ibcon#read 6, iclass 35, count 0 2006.211.08:00:09.81#ibcon#end of sib2, iclass 35, count 0 2006.211.08:00:09.81#ibcon#*after write, iclass 35, count 0 2006.211.08:00:09.81#ibcon#*before return 0, iclass 35, count 0 2006.211.08:00:09.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:00:09.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:00:09.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:00:09.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:00:09.81$vc4f8/valo=8,852.99 2006.211.08:00:09.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:00:09.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:00:09.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:09.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:00:09.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:00:09.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:00:09.81#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:00:09.81#ibcon#first serial, iclass 37, count 0 2006.211.08:00:09.81#ibcon#enter sib2, iclass 37, count 0 2006.211.08:00:09.81#ibcon#flushed, iclass 37, count 0 2006.211.08:00:09.81#ibcon#about to write, iclass 37, count 0 2006.211.08:00:09.81#ibcon#wrote, iclass 37, count 0 2006.211.08:00:09.81#ibcon#about to read 3, iclass 37, count 0 2006.211.08:00:09.83#ibcon#read 3, iclass 37, count 0 2006.211.08:00:09.83#ibcon#about to read 4, iclass 37, count 0 2006.211.08:00:09.83#ibcon#read 4, iclass 37, count 0 2006.211.08:00:09.83#ibcon#about to read 5, iclass 37, count 0 2006.211.08:00:09.83#ibcon#read 5, iclass 37, count 0 2006.211.08:00:09.83#ibcon#about to read 6, iclass 37, count 0 2006.211.08:00:09.83#ibcon#read 6, iclass 37, count 0 2006.211.08:00:09.83#ibcon#end of sib2, iclass 37, count 0 2006.211.08:00:09.83#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:00:09.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:00:09.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:00:09.83#ibcon#*before write, iclass 37, count 0 2006.211.08:00:09.83#ibcon#enter sib2, iclass 37, count 0 2006.211.08:00:09.83#ibcon#flushed, iclass 37, count 0 2006.211.08:00:09.83#ibcon#about to write, iclass 37, count 0 2006.211.08:00:09.83#ibcon#wrote, iclass 37, count 0 2006.211.08:00:09.83#ibcon#about to read 3, iclass 37, count 0 2006.211.08:00:09.87#ibcon#read 3, iclass 37, count 0 2006.211.08:00:09.87#ibcon#about to read 4, iclass 37, count 0 2006.211.08:00:09.87#ibcon#read 4, iclass 37, count 0 2006.211.08:00:09.87#ibcon#about to read 5, iclass 37, count 0 2006.211.08:00:09.87#ibcon#read 5, iclass 37, count 0 2006.211.08:00:09.87#ibcon#about to read 6, iclass 37, count 0 2006.211.08:00:09.87#ibcon#read 6, iclass 37, count 0 2006.211.08:00:09.87#ibcon#end of sib2, iclass 37, count 0 2006.211.08:00:09.87#ibcon#*after write, iclass 37, count 0 2006.211.08:00:09.87#ibcon#*before return 0, iclass 37, count 0 2006.211.08:00:09.87#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:00:09.87#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:00:09.87#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:00:09.87#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:00:09.87$vc4f8/va=8,7 2006.211.08:00:09.87#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:00:09.87#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:00:09.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:09.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:00:09.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:00:09.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:00:09.93#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:00:09.93#ibcon#first serial, iclass 39, count 2 2006.211.08:00:09.93#ibcon#enter sib2, iclass 39, count 2 2006.211.08:00:09.93#ibcon#flushed, iclass 39, count 2 2006.211.08:00:09.93#ibcon#about to write, iclass 39, count 2 2006.211.08:00:09.93#ibcon#wrote, iclass 39, count 2 2006.211.08:00:09.93#ibcon#about to read 3, iclass 39, count 2 2006.211.08:00:09.95#ibcon#read 3, iclass 39, count 2 2006.211.08:00:09.95#ibcon#about to read 4, iclass 39, count 2 2006.211.08:00:09.95#ibcon#read 4, iclass 39, count 2 2006.211.08:00:09.95#ibcon#about to read 5, iclass 39, count 2 2006.211.08:00:09.95#ibcon#read 5, iclass 39, count 2 2006.211.08:00:09.95#ibcon#about to read 6, iclass 39, count 2 2006.211.08:00:09.95#ibcon#read 6, iclass 39, count 2 2006.211.08:00:09.95#ibcon#end of sib2, iclass 39, count 2 2006.211.08:00:09.95#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:00:09.95#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:00:09.95#ibcon#[25=AT08-07\r\n] 2006.211.08:00:09.95#ibcon#*before write, iclass 39, count 2 2006.211.08:00:09.95#ibcon#enter sib2, iclass 39, count 2 2006.211.08:00:09.95#ibcon#flushed, iclass 39, count 2 2006.211.08:00:09.95#ibcon#about to write, iclass 39, count 2 2006.211.08:00:09.95#ibcon#wrote, iclass 39, count 2 2006.211.08:00:09.95#ibcon#about to read 3, iclass 39, count 2 2006.211.08:00:09.98#ibcon#read 3, iclass 39, count 2 2006.211.08:00:09.98#ibcon#about to read 4, iclass 39, count 2 2006.211.08:00:09.98#ibcon#read 4, iclass 39, count 2 2006.211.08:00:09.98#ibcon#about to read 5, iclass 39, count 2 2006.211.08:00:09.98#ibcon#read 5, iclass 39, count 2 2006.211.08:00:09.98#ibcon#about to read 6, iclass 39, count 2 2006.211.08:00:09.98#ibcon#read 6, iclass 39, count 2 2006.211.08:00:09.98#ibcon#end of sib2, iclass 39, count 2 2006.211.08:00:09.98#ibcon#*after write, iclass 39, count 2 2006.211.08:00:09.98#ibcon#*before return 0, iclass 39, count 2 2006.211.08:00:09.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:00:09.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:00:09.98#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:00:09.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:09.98#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:00:10.10#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:00:10.10#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:00:10.10#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:00:10.10#ibcon#first serial, iclass 39, count 0 2006.211.08:00:10.10#ibcon#enter sib2, iclass 39, count 0 2006.211.08:00:10.10#ibcon#flushed, iclass 39, count 0 2006.211.08:00:10.10#ibcon#about to write, iclass 39, count 0 2006.211.08:00:10.10#ibcon#wrote, iclass 39, count 0 2006.211.08:00:10.10#ibcon#about to read 3, iclass 39, count 0 2006.211.08:00:10.12#ibcon#read 3, iclass 39, count 0 2006.211.08:00:10.12#ibcon#about to read 4, iclass 39, count 0 2006.211.08:00:10.12#ibcon#read 4, iclass 39, count 0 2006.211.08:00:10.12#ibcon#about to read 5, iclass 39, count 0 2006.211.08:00:10.12#ibcon#read 5, iclass 39, count 0 2006.211.08:00:10.12#ibcon#about to read 6, iclass 39, count 0 2006.211.08:00:10.12#ibcon#read 6, iclass 39, count 0 2006.211.08:00:10.12#ibcon#end of sib2, iclass 39, count 0 2006.211.08:00:10.12#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:00:10.12#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:00:10.12#ibcon#[25=USB\r\n] 2006.211.08:00:10.12#ibcon#*before write, iclass 39, count 0 2006.211.08:00:10.12#ibcon#enter sib2, iclass 39, count 0 2006.211.08:00:10.12#ibcon#flushed, iclass 39, count 0 2006.211.08:00:10.12#ibcon#about to write, iclass 39, count 0 2006.211.08:00:10.12#ibcon#wrote, iclass 39, count 0 2006.211.08:00:10.12#ibcon#about to read 3, iclass 39, count 0 2006.211.08:00:10.15#ibcon#read 3, iclass 39, count 0 2006.211.08:00:10.15#ibcon#about to read 4, iclass 39, count 0 2006.211.08:00:10.15#ibcon#read 4, iclass 39, count 0 2006.211.08:00:10.15#ibcon#about to read 5, iclass 39, count 0 2006.211.08:00:10.15#ibcon#read 5, iclass 39, count 0 2006.211.08:00:10.15#ibcon#about to read 6, iclass 39, count 0 2006.211.08:00:10.15#ibcon#read 6, iclass 39, count 0 2006.211.08:00:10.15#ibcon#end of sib2, iclass 39, count 0 2006.211.08:00:10.15#ibcon#*after write, iclass 39, count 0 2006.211.08:00:10.15#ibcon#*before return 0, iclass 39, count 0 2006.211.08:00:10.15#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:00:10.15#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:00:10.15#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:00:10.15#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:00:10.15$vc4f8/vblo=1,632.99 2006.211.08:00:10.15#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:00:10.15#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:00:10.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:10.15#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:10.15#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:10.15#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:10.15#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:00:10.15#ibcon#first serial, iclass 3, count 0 2006.211.08:00:10.15#ibcon#enter sib2, iclass 3, count 0 2006.211.08:00:10.15#ibcon#flushed, iclass 3, count 0 2006.211.08:00:10.15#ibcon#about to write, iclass 3, count 0 2006.211.08:00:10.15#ibcon#wrote, iclass 3, count 0 2006.211.08:00:10.15#ibcon#about to read 3, iclass 3, count 0 2006.211.08:00:10.17#ibcon#read 3, iclass 3, count 0 2006.211.08:00:10.17#ibcon#about to read 4, iclass 3, count 0 2006.211.08:00:10.17#ibcon#read 4, iclass 3, count 0 2006.211.08:00:10.17#ibcon#about to read 5, iclass 3, count 0 2006.211.08:00:10.17#ibcon#read 5, iclass 3, count 0 2006.211.08:00:10.17#ibcon#about to read 6, iclass 3, count 0 2006.211.08:00:10.17#ibcon#read 6, iclass 3, count 0 2006.211.08:00:10.17#ibcon#end of sib2, iclass 3, count 0 2006.211.08:00:10.17#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:00:10.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:00:10.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:00:10.17#ibcon#*before write, iclass 3, count 0 2006.211.08:00:10.17#ibcon#enter sib2, iclass 3, count 0 2006.211.08:00:10.17#ibcon#flushed, iclass 3, count 0 2006.211.08:00:10.17#ibcon#about to write, iclass 3, count 0 2006.211.08:00:10.17#ibcon#wrote, iclass 3, count 0 2006.211.08:00:10.17#ibcon#about to read 3, iclass 3, count 0 2006.211.08:00:10.21#ibcon#read 3, iclass 3, count 0 2006.211.08:00:10.21#ibcon#about to read 4, iclass 3, count 0 2006.211.08:00:10.21#ibcon#read 4, iclass 3, count 0 2006.211.08:00:10.21#ibcon#about to read 5, iclass 3, count 0 2006.211.08:00:10.21#ibcon#read 5, iclass 3, count 0 2006.211.08:00:10.21#ibcon#about to read 6, iclass 3, count 0 2006.211.08:00:10.21#ibcon#read 6, iclass 3, count 0 2006.211.08:00:10.21#ibcon#end of sib2, iclass 3, count 0 2006.211.08:00:10.21#ibcon#*after write, iclass 3, count 0 2006.211.08:00:10.21#ibcon#*before return 0, iclass 3, count 0 2006.211.08:00:10.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:10.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:00:10.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:00:10.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:00:10.21$vc4f8/vb=1,4 2006.211.08:00:10.21#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:00:10.21#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:00:10.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:10.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:10.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:10.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:10.21#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:00:10.21#ibcon#first serial, iclass 5, count 2 2006.211.08:00:10.21#ibcon#enter sib2, iclass 5, count 2 2006.211.08:00:10.21#ibcon#flushed, iclass 5, count 2 2006.211.08:00:10.21#ibcon#about to write, iclass 5, count 2 2006.211.08:00:10.21#ibcon#wrote, iclass 5, count 2 2006.211.08:00:10.21#ibcon#about to read 3, iclass 5, count 2 2006.211.08:00:10.23#ibcon#read 3, iclass 5, count 2 2006.211.08:00:10.23#ibcon#about to read 4, iclass 5, count 2 2006.211.08:00:10.23#ibcon#read 4, iclass 5, count 2 2006.211.08:00:10.23#ibcon#about to read 5, iclass 5, count 2 2006.211.08:00:10.23#ibcon#read 5, iclass 5, count 2 2006.211.08:00:10.23#ibcon#about to read 6, iclass 5, count 2 2006.211.08:00:10.23#ibcon#read 6, iclass 5, count 2 2006.211.08:00:10.23#ibcon#end of sib2, iclass 5, count 2 2006.211.08:00:10.23#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:00:10.23#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:00:10.23#ibcon#[27=AT01-04\r\n] 2006.211.08:00:10.23#ibcon#*before write, iclass 5, count 2 2006.211.08:00:10.23#ibcon#enter sib2, iclass 5, count 2 2006.211.08:00:10.23#ibcon#flushed, iclass 5, count 2 2006.211.08:00:10.23#ibcon#about to write, iclass 5, count 2 2006.211.08:00:10.23#ibcon#wrote, iclass 5, count 2 2006.211.08:00:10.23#ibcon#about to read 3, iclass 5, count 2 2006.211.08:00:10.26#ibcon#read 3, iclass 5, count 2 2006.211.08:00:10.26#ibcon#about to read 4, iclass 5, count 2 2006.211.08:00:10.26#ibcon#read 4, iclass 5, count 2 2006.211.08:00:10.26#ibcon#about to read 5, iclass 5, count 2 2006.211.08:00:10.26#ibcon#read 5, iclass 5, count 2 2006.211.08:00:10.26#ibcon#about to read 6, iclass 5, count 2 2006.211.08:00:10.26#ibcon#read 6, iclass 5, count 2 2006.211.08:00:10.26#ibcon#end of sib2, iclass 5, count 2 2006.211.08:00:10.26#ibcon#*after write, iclass 5, count 2 2006.211.08:00:10.26#ibcon#*before return 0, iclass 5, count 2 2006.211.08:00:10.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:10.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:00:10.26#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:00:10.26#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:10.26#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:10.38#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:10.38#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:10.38#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:00:10.38#ibcon#first serial, iclass 5, count 0 2006.211.08:00:10.38#ibcon#enter sib2, iclass 5, count 0 2006.211.08:00:10.38#ibcon#flushed, iclass 5, count 0 2006.211.08:00:10.38#ibcon#about to write, iclass 5, count 0 2006.211.08:00:10.38#ibcon#wrote, iclass 5, count 0 2006.211.08:00:10.38#ibcon#about to read 3, iclass 5, count 0 2006.211.08:00:10.40#ibcon#read 3, iclass 5, count 0 2006.211.08:00:10.40#ibcon#about to read 4, iclass 5, count 0 2006.211.08:00:10.40#ibcon#read 4, iclass 5, count 0 2006.211.08:00:10.40#ibcon#about to read 5, iclass 5, count 0 2006.211.08:00:10.40#ibcon#read 5, iclass 5, count 0 2006.211.08:00:10.40#ibcon#about to read 6, iclass 5, count 0 2006.211.08:00:10.40#ibcon#read 6, iclass 5, count 0 2006.211.08:00:10.40#ibcon#end of sib2, iclass 5, count 0 2006.211.08:00:10.40#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:00:10.40#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:00:10.40#ibcon#[27=USB\r\n] 2006.211.08:00:10.40#ibcon#*before write, iclass 5, count 0 2006.211.08:00:10.40#ibcon#enter sib2, iclass 5, count 0 2006.211.08:00:10.40#ibcon#flushed, iclass 5, count 0 2006.211.08:00:10.40#ibcon#about to write, iclass 5, count 0 2006.211.08:00:10.40#ibcon#wrote, iclass 5, count 0 2006.211.08:00:10.40#ibcon#about to read 3, iclass 5, count 0 2006.211.08:00:10.43#ibcon#read 3, iclass 5, count 0 2006.211.08:00:10.43#ibcon#about to read 4, iclass 5, count 0 2006.211.08:00:10.43#ibcon#read 4, iclass 5, count 0 2006.211.08:00:10.43#ibcon#about to read 5, iclass 5, count 0 2006.211.08:00:10.43#ibcon#read 5, iclass 5, count 0 2006.211.08:00:10.43#ibcon#about to read 6, iclass 5, count 0 2006.211.08:00:10.43#ibcon#read 6, iclass 5, count 0 2006.211.08:00:10.43#ibcon#end of sib2, iclass 5, count 0 2006.211.08:00:10.43#ibcon#*after write, iclass 5, count 0 2006.211.08:00:10.43#ibcon#*before return 0, iclass 5, count 0 2006.211.08:00:10.43#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:10.43#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:00:10.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:00:10.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:00:10.43$vc4f8/vblo=2,640.99 2006.211.08:00:10.43#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:00:10.43#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:00:10.43#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:10.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:10.43#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:10.43#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:10.43#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:00:10.43#ibcon#first serial, iclass 7, count 0 2006.211.08:00:10.43#ibcon#enter sib2, iclass 7, count 0 2006.211.08:00:10.43#ibcon#flushed, iclass 7, count 0 2006.211.08:00:10.43#ibcon#about to write, iclass 7, count 0 2006.211.08:00:10.43#ibcon#wrote, iclass 7, count 0 2006.211.08:00:10.43#ibcon#about to read 3, iclass 7, count 0 2006.211.08:00:10.45#ibcon#read 3, iclass 7, count 0 2006.211.08:00:10.45#ibcon#about to read 4, iclass 7, count 0 2006.211.08:00:10.45#ibcon#read 4, iclass 7, count 0 2006.211.08:00:10.45#ibcon#about to read 5, iclass 7, count 0 2006.211.08:00:10.45#ibcon#read 5, iclass 7, count 0 2006.211.08:00:10.45#ibcon#about to read 6, iclass 7, count 0 2006.211.08:00:10.45#ibcon#read 6, iclass 7, count 0 2006.211.08:00:10.45#ibcon#end of sib2, iclass 7, count 0 2006.211.08:00:10.45#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:00:10.45#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:00:10.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:00:10.45#ibcon#*before write, iclass 7, count 0 2006.211.08:00:10.45#ibcon#enter sib2, iclass 7, count 0 2006.211.08:00:10.45#ibcon#flushed, iclass 7, count 0 2006.211.08:00:10.45#ibcon#about to write, iclass 7, count 0 2006.211.08:00:10.45#ibcon#wrote, iclass 7, count 0 2006.211.08:00:10.45#ibcon#about to read 3, iclass 7, count 0 2006.211.08:00:10.49#ibcon#read 3, iclass 7, count 0 2006.211.08:00:10.49#ibcon#about to read 4, iclass 7, count 0 2006.211.08:00:10.49#ibcon#read 4, iclass 7, count 0 2006.211.08:00:10.49#ibcon#about to read 5, iclass 7, count 0 2006.211.08:00:10.49#ibcon#read 5, iclass 7, count 0 2006.211.08:00:10.49#ibcon#about to read 6, iclass 7, count 0 2006.211.08:00:10.49#ibcon#read 6, iclass 7, count 0 2006.211.08:00:10.49#ibcon#end of sib2, iclass 7, count 0 2006.211.08:00:10.49#ibcon#*after write, iclass 7, count 0 2006.211.08:00:10.49#ibcon#*before return 0, iclass 7, count 0 2006.211.08:00:10.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:10.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:00:10.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:00:10.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:00:10.49$vc4f8/vb=2,4 2006.211.08:00:10.49#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:00:10.49#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:00:10.49#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:10.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:10.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:10.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:10.55#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:00:10.55#ibcon#first serial, iclass 11, count 2 2006.211.08:00:10.55#ibcon#enter sib2, iclass 11, count 2 2006.211.08:00:10.55#ibcon#flushed, iclass 11, count 2 2006.211.08:00:10.55#ibcon#about to write, iclass 11, count 2 2006.211.08:00:10.55#ibcon#wrote, iclass 11, count 2 2006.211.08:00:10.55#ibcon#about to read 3, iclass 11, count 2 2006.211.08:00:10.57#ibcon#read 3, iclass 11, count 2 2006.211.08:00:10.57#ibcon#about to read 4, iclass 11, count 2 2006.211.08:00:10.57#ibcon#read 4, iclass 11, count 2 2006.211.08:00:10.57#ibcon#about to read 5, iclass 11, count 2 2006.211.08:00:10.57#ibcon#read 5, iclass 11, count 2 2006.211.08:00:10.57#ibcon#about to read 6, iclass 11, count 2 2006.211.08:00:10.57#ibcon#read 6, iclass 11, count 2 2006.211.08:00:10.57#ibcon#end of sib2, iclass 11, count 2 2006.211.08:00:10.57#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:00:10.57#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:00:10.57#ibcon#[27=AT02-04\r\n] 2006.211.08:00:10.57#ibcon#*before write, iclass 11, count 2 2006.211.08:00:10.57#ibcon#enter sib2, iclass 11, count 2 2006.211.08:00:10.57#ibcon#flushed, iclass 11, count 2 2006.211.08:00:10.57#ibcon#about to write, iclass 11, count 2 2006.211.08:00:10.57#ibcon#wrote, iclass 11, count 2 2006.211.08:00:10.57#ibcon#about to read 3, iclass 11, count 2 2006.211.08:00:10.60#ibcon#read 3, iclass 11, count 2 2006.211.08:00:10.60#ibcon#about to read 4, iclass 11, count 2 2006.211.08:00:10.60#ibcon#read 4, iclass 11, count 2 2006.211.08:00:10.60#ibcon#about to read 5, iclass 11, count 2 2006.211.08:00:10.60#ibcon#read 5, iclass 11, count 2 2006.211.08:00:10.60#ibcon#about to read 6, iclass 11, count 2 2006.211.08:00:10.60#ibcon#read 6, iclass 11, count 2 2006.211.08:00:10.60#ibcon#end of sib2, iclass 11, count 2 2006.211.08:00:10.60#ibcon#*after write, iclass 11, count 2 2006.211.08:00:10.60#ibcon#*before return 0, iclass 11, count 2 2006.211.08:00:10.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:10.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:00:10.60#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:00:10.60#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:10.60#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:10.72#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:10.72#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:10.72#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:00:10.72#ibcon#first serial, iclass 11, count 0 2006.211.08:00:10.72#ibcon#enter sib2, iclass 11, count 0 2006.211.08:00:10.72#ibcon#flushed, iclass 11, count 0 2006.211.08:00:10.72#ibcon#about to write, iclass 11, count 0 2006.211.08:00:10.72#ibcon#wrote, iclass 11, count 0 2006.211.08:00:10.72#ibcon#about to read 3, iclass 11, count 0 2006.211.08:00:10.74#ibcon#read 3, iclass 11, count 0 2006.211.08:00:10.74#ibcon#about to read 4, iclass 11, count 0 2006.211.08:00:10.74#ibcon#read 4, iclass 11, count 0 2006.211.08:00:10.74#ibcon#about to read 5, iclass 11, count 0 2006.211.08:00:10.74#ibcon#read 5, iclass 11, count 0 2006.211.08:00:10.74#ibcon#about to read 6, iclass 11, count 0 2006.211.08:00:10.74#ibcon#read 6, iclass 11, count 0 2006.211.08:00:10.74#ibcon#end of sib2, iclass 11, count 0 2006.211.08:00:10.74#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:00:10.74#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:00:10.74#ibcon#[27=USB\r\n] 2006.211.08:00:10.74#ibcon#*before write, iclass 11, count 0 2006.211.08:00:10.74#ibcon#enter sib2, iclass 11, count 0 2006.211.08:00:10.74#ibcon#flushed, iclass 11, count 0 2006.211.08:00:10.74#ibcon#about to write, iclass 11, count 0 2006.211.08:00:10.74#ibcon#wrote, iclass 11, count 0 2006.211.08:00:10.74#ibcon#about to read 3, iclass 11, count 0 2006.211.08:00:10.77#ibcon#read 3, iclass 11, count 0 2006.211.08:00:10.77#ibcon#about to read 4, iclass 11, count 0 2006.211.08:00:10.77#ibcon#read 4, iclass 11, count 0 2006.211.08:00:10.77#ibcon#about to read 5, iclass 11, count 0 2006.211.08:00:10.77#ibcon#read 5, iclass 11, count 0 2006.211.08:00:10.77#ibcon#about to read 6, iclass 11, count 0 2006.211.08:00:10.77#ibcon#read 6, iclass 11, count 0 2006.211.08:00:10.77#ibcon#end of sib2, iclass 11, count 0 2006.211.08:00:10.77#ibcon#*after write, iclass 11, count 0 2006.211.08:00:10.77#ibcon#*before return 0, iclass 11, count 0 2006.211.08:00:10.77#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:10.77#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:00:10.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:00:10.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:00:10.77$vc4f8/vblo=3,656.99 2006.211.08:00:10.77#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:00:10.77#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:00:10.77#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:10.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:10.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:10.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:10.77#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:00:10.77#ibcon#first serial, iclass 13, count 0 2006.211.08:00:10.77#ibcon#enter sib2, iclass 13, count 0 2006.211.08:00:10.77#ibcon#flushed, iclass 13, count 0 2006.211.08:00:10.77#ibcon#about to write, iclass 13, count 0 2006.211.08:00:10.77#ibcon#wrote, iclass 13, count 0 2006.211.08:00:10.77#ibcon#about to read 3, iclass 13, count 0 2006.211.08:00:10.79#ibcon#read 3, iclass 13, count 0 2006.211.08:00:10.79#ibcon#about to read 4, iclass 13, count 0 2006.211.08:00:10.79#ibcon#read 4, iclass 13, count 0 2006.211.08:00:10.79#ibcon#about to read 5, iclass 13, count 0 2006.211.08:00:10.79#ibcon#read 5, iclass 13, count 0 2006.211.08:00:10.79#ibcon#about to read 6, iclass 13, count 0 2006.211.08:00:10.79#ibcon#read 6, iclass 13, count 0 2006.211.08:00:10.79#ibcon#end of sib2, iclass 13, count 0 2006.211.08:00:10.79#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:00:10.79#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:00:10.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:00:10.79#ibcon#*before write, iclass 13, count 0 2006.211.08:00:10.79#ibcon#enter sib2, iclass 13, count 0 2006.211.08:00:10.79#ibcon#flushed, iclass 13, count 0 2006.211.08:00:10.79#ibcon#about to write, iclass 13, count 0 2006.211.08:00:10.79#ibcon#wrote, iclass 13, count 0 2006.211.08:00:10.79#ibcon#about to read 3, iclass 13, count 0 2006.211.08:00:10.83#ibcon#read 3, iclass 13, count 0 2006.211.08:00:10.83#ibcon#about to read 4, iclass 13, count 0 2006.211.08:00:10.83#ibcon#read 4, iclass 13, count 0 2006.211.08:00:10.83#ibcon#about to read 5, iclass 13, count 0 2006.211.08:00:10.83#ibcon#read 5, iclass 13, count 0 2006.211.08:00:10.83#ibcon#about to read 6, iclass 13, count 0 2006.211.08:00:10.83#ibcon#read 6, iclass 13, count 0 2006.211.08:00:10.83#ibcon#end of sib2, iclass 13, count 0 2006.211.08:00:10.83#ibcon#*after write, iclass 13, count 0 2006.211.08:00:10.83#ibcon#*before return 0, iclass 13, count 0 2006.211.08:00:10.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:10.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:00:10.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:00:10.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:00:10.83$vc4f8/vb=3,3 2006.211.08:00:10.83#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:00:10.83#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:00:10.83#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:10.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:10.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:10.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:10.89#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:00:10.89#ibcon#first serial, iclass 15, count 2 2006.211.08:00:10.89#ibcon#enter sib2, iclass 15, count 2 2006.211.08:00:10.89#ibcon#flushed, iclass 15, count 2 2006.211.08:00:10.89#ibcon#about to write, iclass 15, count 2 2006.211.08:00:10.89#ibcon#wrote, iclass 15, count 2 2006.211.08:00:10.89#ibcon#about to read 3, iclass 15, count 2 2006.211.08:00:10.91#ibcon#read 3, iclass 15, count 2 2006.211.08:00:10.91#ibcon#about to read 4, iclass 15, count 2 2006.211.08:00:10.91#ibcon#read 4, iclass 15, count 2 2006.211.08:00:10.91#ibcon#about to read 5, iclass 15, count 2 2006.211.08:00:10.91#ibcon#read 5, iclass 15, count 2 2006.211.08:00:10.91#ibcon#about to read 6, iclass 15, count 2 2006.211.08:00:10.91#ibcon#read 6, iclass 15, count 2 2006.211.08:00:10.91#ibcon#end of sib2, iclass 15, count 2 2006.211.08:00:10.91#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:00:10.91#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:00:10.91#ibcon#[27=AT03-03\r\n] 2006.211.08:00:10.91#ibcon#*before write, iclass 15, count 2 2006.211.08:00:10.91#ibcon#enter sib2, iclass 15, count 2 2006.211.08:00:10.91#ibcon#flushed, iclass 15, count 2 2006.211.08:00:10.91#ibcon#about to write, iclass 15, count 2 2006.211.08:00:10.91#ibcon#wrote, iclass 15, count 2 2006.211.08:00:10.91#ibcon#about to read 3, iclass 15, count 2 2006.211.08:00:10.94#ibcon#read 3, iclass 15, count 2 2006.211.08:00:10.94#ibcon#about to read 4, iclass 15, count 2 2006.211.08:00:10.94#ibcon#read 4, iclass 15, count 2 2006.211.08:00:10.94#ibcon#about to read 5, iclass 15, count 2 2006.211.08:00:10.94#ibcon#read 5, iclass 15, count 2 2006.211.08:00:10.94#ibcon#about to read 6, iclass 15, count 2 2006.211.08:00:10.94#ibcon#read 6, iclass 15, count 2 2006.211.08:00:10.94#ibcon#end of sib2, iclass 15, count 2 2006.211.08:00:10.94#ibcon#*after write, iclass 15, count 2 2006.211.08:00:10.94#ibcon#*before return 0, iclass 15, count 2 2006.211.08:00:10.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:10.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:00:10.94#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:00:10.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:10.94#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:11.06#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:11.06#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:11.06#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:00:11.06#ibcon#first serial, iclass 15, count 0 2006.211.08:00:11.06#ibcon#enter sib2, iclass 15, count 0 2006.211.08:00:11.06#ibcon#flushed, iclass 15, count 0 2006.211.08:00:11.06#ibcon#about to write, iclass 15, count 0 2006.211.08:00:11.06#ibcon#wrote, iclass 15, count 0 2006.211.08:00:11.06#ibcon#about to read 3, iclass 15, count 0 2006.211.08:00:11.08#ibcon#read 3, iclass 15, count 0 2006.211.08:00:11.08#ibcon#about to read 4, iclass 15, count 0 2006.211.08:00:11.08#ibcon#read 4, iclass 15, count 0 2006.211.08:00:11.08#ibcon#about to read 5, iclass 15, count 0 2006.211.08:00:11.08#ibcon#read 5, iclass 15, count 0 2006.211.08:00:11.08#ibcon#about to read 6, iclass 15, count 0 2006.211.08:00:11.08#ibcon#read 6, iclass 15, count 0 2006.211.08:00:11.08#ibcon#end of sib2, iclass 15, count 0 2006.211.08:00:11.08#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:00:11.08#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:00:11.08#ibcon#[27=USB\r\n] 2006.211.08:00:11.08#ibcon#*before write, iclass 15, count 0 2006.211.08:00:11.08#ibcon#enter sib2, iclass 15, count 0 2006.211.08:00:11.08#ibcon#flushed, iclass 15, count 0 2006.211.08:00:11.08#ibcon#about to write, iclass 15, count 0 2006.211.08:00:11.08#ibcon#wrote, iclass 15, count 0 2006.211.08:00:11.08#ibcon#about to read 3, iclass 15, count 0 2006.211.08:00:11.11#ibcon#read 3, iclass 15, count 0 2006.211.08:00:11.11#ibcon#about to read 4, iclass 15, count 0 2006.211.08:00:11.11#ibcon#read 4, iclass 15, count 0 2006.211.08:00:11.11#ibcon#about to read 5, iclass 15, count 0 2006.211.08:00:11.11#ibcon#read 5, iclass 15, count 0 2006.211.08:00:11.11#ibcon#about to read 6, iclass 15, count 0 2006.211.08:00:11.11#ibcon#read 6, iclass 15, count 0 2006.211.08:00:11.11#ibcon#end of sib2, iclass 15, count 0 2006.211.08:00:11.11#ibcon#*after write, iclass 15, count 0 2006.211.08:00:11.11#ibcon#*before return 0, iclass 15, count 0 2006.211.08:00:11.11#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:11.11#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:00:11.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:00:11.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:00:11.11$vc4f8/vblo=4,712.99 2006.211.08:00:11.11#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:00:11.11#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:00:11.11#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:11.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:00:11.11#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:00:11.11#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:00:11.11#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:00:11.11#ibcon#first serial, iclass 17, count 0 2006.211.08:00:11.11#ibcon#enter sib2, iclass 17, count 0 2006.211.08:00:11.11#ibcon#flushed, iclass 17, count 0 2006.211.08:00:11.11#ibcon#about to write, iclass 17, count 0 2006.211.08:00:11.11#ibcon#wrote, iclass 17, count 0 2006.211.08:00:11.11#ibcon#about to read 3, iclass 17, count 0 2006.211.08:00:11.13#ibcon#read 3, iclass 17, count 0 2006.211.08:00:11.13#ibcon#about to read 4, iclass 17, count 0 2006.211.08:00:11.13#ibcon#read 4, iclass 17, count 0 2006.211.08:00:11.13#ibcon#about to read 5, iclass 17, count 0 2006.211.08:00:11.13#ibcon#read 5, iclass 17, count 0 2006.211.08:00:11.13#ibcon#about to read 6, iclass 17, count 0 2006.211.08:00:11.13#ibcon#read 6, iclass 17, count 0 2006.211.08:00:11.13#ibcon#end of sib2, iclass 17, count 0 2006.211.08:00:11.13#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:00:11.13#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:00:11.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:00:11.13#ibcon#*before write, iclass 17, count 0 2006.211.08:00:11.13#ibcon#enter sib2, iclass 17, count 0 2006.211.08:00:11.13#ibcon#flushed, iclass 17, count 0 2006.211.08:00:11.13#ibcon#about to write, iclass 17, count 0 2006.211.08:00:11.13#ibcon#wrote, iclass 17, count 0 2006.211.08:00:11.13#ibcon#about to read 3, iclass 17, count 0 2006.211.08:00:11.17#ibcon#read 3, iclass 17, count 0 2006.211.08:00:11.17#ibcon#about to read 4, iclass 17, count 0 2006.211.08:00:11.17#ibcon#read 4, iclass 17, count 0 2006.211.08:00:11.17#ibcon#about to read 5, iclass 17, count 0 2006.211.08:00:11.17#ibcon#read 5, iclass 17, count 0 2006.211.08:00:11.17#ibcon#about to read 6, iclass 17, count 0 2006.211.08:00:11.17#ibcon#read 6, iclass 17, count 0 2006.211.08:00:11.17#ibcon#end of sib2, iclass 17, count 0 2006.211.08:00:11.17#ibcon#*after write, iclass 17, count 0 2006.211.08:00:11.17#ibcon#*before return 0, iclass 17, count 0 2006.211.08:00:11.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:00:11.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:00:11.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:00:11.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:00:11.17$vc4f8/vb=4,3 2006.211.08:00:11.17#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:00:11.17#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:00:11.17#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:11.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:00:11.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:00:11.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:00:11.23#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:00:11.23#ibcon#first serial, iclass 19, count 2 2006.211.08:00:11.23#ibcon#enter sib2, iclass 19, count 2 2006.211.08:00:11.23#ibcon#flushed, iclass 19, count 2 2006.211.08:00:11.23#ibcon#about to write, iclass 19, count 2 2006.211.08:00:11.23#ibcon#wrote, iclass 19, count 2 2006.211.08:00:11.23#ibcon#about to read 3, iclass 19, count 2 2006.211.08:00:11.25#ibcon#read 3, iclass 19, count 2 2006.211.08:00:11.25#ibcon#about to read 4, iclass 19, count 2 2006.211.08:00:11.25#ibcon#read 4, iclass 19, count 2 2006.211.08:00:11.25#ibcon#about to read 5, iclass 19, count 2 2006.211.08:00:11.25#ibcon#read 5, iclass 19, count 2 2006.211.08:00:11.25#ibcon#about to read 6, iclass 19, count 2 2006.211.08:00:11.25#ibcon#read 6, iclass 19, count 2 2006.211.08:00:11.25#ibcon#end of sib2, iclass 19, count 2 2006.211.08:00:11.25#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:00:11.25#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:00:11.25#ibcon#[27=AT04-03\r\n] 2006.211.08:00:11.25#ibcon#*before write, iclass 19, count 2 2006.211.08:00:11.25#ibcon#enter sib2, iclass 19, count 2 2006.211.08:00:11.25#ibcon#flushed, iclass 19, count 2 2006.211.08:00:11.25#ibcon#about to write, iclass 19, count 2 2006.211.08:00:11.25#ibcon#wrote, iclass 19, count 2 2006.211.08:00:11.25#ibcon#about to read 3, iclass 19, count 2 2006.211.08:00:11.28#ibcon#read 3, iclass 19, count 2 2006.211.08:00:11.28#ibcon#about to read 4, iclass 19, count 2 2006.211.08:00:11.28#ibcon#read 4, iclass 19, count 2 2006.211.08:00:11.28#ibcon#about to read 5, iclass 19, count 2 2006.211.08:00:11.28#ibcon#read 5, iclass 19, count 2 2006.211.08:00:11.28#ibcon#about to read 6, iclass 19, count 2 2006.211.08:00:11.28#ibcon#read 6, iclass 19, count 2 2006.211.08:00:11.28#ibcon#end of sib2, iclass 19, count 2 2006.211.08:00:11.28#ibcon#*after write, iclass 19, count 2 2006.211.08:00:11.28#ibcon#*before return 0, iclass 19, count 2 2006.211.08:00:11.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:00:11.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:00:11.28#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:00:11.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:11.28#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:00:11.40#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:00:11.40#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:00:11.40#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:00:11.40#ibcon#first serial, iclass 19, count 0 2006.211.08:00:11.40#ibcon#enter sib2, iclass 19, count 0 2006.211.08:00:11.40#ibcon#flushed, iclass 19, count 0 2006.211.08:00:11.40#ibcon#about to write, iclass 19, count 0 2006.211.08:00:11.40#ibcon#wrote, iclass 19, count 0 2006.211.08:00:11.40#ibcon#about to read 3, iclass 19, count 0 2006.211.08:00:11.42#ibcon#read 3, iclass 19, count 0 2006.211.08:00:11.42#ibcon#about to read 4, iclass 19, count 0 2006.211.08:00:11.42#ibcon#read 4, iclass 19, count 0 2006.211.08:00:11.42#ibcon#about to read 5, iclass 19, count 0 2006.211.08:00:11.42#ibcon#read 5, iclass 19, count 0 2006.211.08:00:11.42#ibcon#about to read 6, iclass 19, count 0 2006.211.08:00:11.42#ibcon#read 6, iclass 19, count 0 2006.211.08:00:11.42#ibcon#end of sib2, iclass 19, count 0 2006.211.08:00:11.42#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:00:11.42#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:00:11.42#ibcon#[27=USB\r\n] 2006.211.08:00:11.42#ibcon#*before write, iclass 19, count 0 2006.211.08:00:11.42#ibcon#enter sib2, iclass 19, count 0 2006.211.08:00:11.42#ibcon#flushed, iclass 19, count 0 2006.211.08:00:11.42#ibcon#about to write, iclass 19, count 0 2006.211.08:00:11.42#ibcon#wrote, iclass 19, count 0 2006.211.08:00:11.42#ibcon#about to read 3, iclass 19, count 0 2006.211.08:00:11.45#ibcon#read 3, iclass 19, count 0 2006.211.08:00:11.45#ibcon#about to read 4, iclass 19, count 0 2006.211.08:00:11.45#ibcon#read 4, iclass 19, count 0 2006.211.08:00:11.45#ibcon#about to read 5, iclass 19, count 0 2006.211.08:00:11.45#ibcon#read 5, iclass 19, count 0 2006.211.08:00:11.45#ibcon#about to read 6, iclass 19, count 0 2006.211.08:00:11.45#ibcon#read 6, iclass 19, count 0 2006.211.08:00:11.45#ibcon#end of sib2, iclass 19, count 0 2006.211.08:00:11.45#ibcon#*after write, iclass 19, count 0 2006.211.08:00:11.45#ibcon#*before return 0, iclass 19, count 0 2006.211.08:00:11.45#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:00:11.45#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:00:11.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:00:11.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:00:11.45$vc4f8/vblo=5,744.99 2006.211.08:00:11.45#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:00:11.45#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:00:11.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:11.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:00:11.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:00:11.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:00:11.45#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:00:11.45#ibcon#first serial, iclass 21, count 0 2006.211.08:00:11.45#ibcon#enter sib2, iclass 21, count 0 2006.211.08:00:11.45#ibcon#flushed, iclass 21, count 0 2006.211.08:00:11.45#ibcon#about to write, iclass 21, count 0 2006.211.08:00:11.45#ibcon#wrote, iclass 21, count 0 2006.211.08:00:11.45#ibcon#about to read 3, iclass 21, count 0 2006.211.08:00:11.47#ibcon#read 3, iclass 21, count 0 2006.211.08:00:11.47#ibcon#about to read 4, iclass 21, count 0 2006.211.08:00:11.47#ibcon#read 4, iclass 21, count 0 2006.211.08:00:11.47#ibcon#about to read 5, iclass 21, count 0 2006.211.08:00:11.47#ibcon#read 5, iclass 21, count 0 2006.211.08:00:11.47#ibcon#about to read 6, iclass 21, count 0 2006.211.08:00:11.47#ibcon#read 6, iclass 21, count 0 2006.211.08:00:11.47#ibcon#end of sib2, iclass 21, count 0 2006.211.08:00:11.47#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:00:11.47#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:00:11.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:00:11.47#ibcon#*before write, iclass 21, count 0 2006.211.08:00:11.47#ibcon#enter sib2, iclass 21, count 0 2006.211.08:00:11.47#ibcon#flushed, iclass 21, count 0 2006.211.08:00:11.47#ibcon#about to write, iclass 21, count 0 2006.211.08:00:11.47#ibcon#wrote, iclass 21, count 0 2006.211.08:00:11.47#ibcon#about to read 3, iclass 21, count 0 2006.211.08:00:11.51#ibcon#read 3, iclass 21, count 0 2006.211.08:00:11.51#ibcon#about to read 4, iclass 21, count 0 2006.211.08:00:11.51#ibcon#read 4, iclass 21, count 0 2006.211.08:00:11.51#ibcon#about to read 5, iclass 21, count 0 2006.211.08:00:11.51#ibcon#read 5, iclass 21, count 0 2006.211.08:00:11.51#ibcon#about to read 6, iclass 21, count 0 2006.211.08:00:11.51#ibcon#read 6, iclass 21, count 0 2006.211.08:00:11.51#ibcon#end of sib2, iclass 21, count 0 2006.211.08:00:11.51#ibcon#*after write, iclass 21, count 0 2006.211.08:00:11.51#ibcon#*before return 0, iclass 21, count 0 2006.211.08:00:11.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:00:11.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:00:11.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:00:11.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:00:11.51$vc4f8/vb=5,3 2006.211.08:00:11.51#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:00:11.51#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:00:11.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:11.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:00:11.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:00:11.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:00:11.57#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:00:11.57#ibcon#first serial, iclass 23, count 2 2006.211.08:00:11.57#ibcon#enter sib2, iclass 23, count 2 2006.211.08:00:11.57#ibcon#flushed, iclass 23, count 2 2006.211.08:00:11.57#ibcon#about to write, iclass 23, count 2 2006.211.08:00:11.57#ibcon#wrote, iclass 23, count 2 2006.211.08:00:11.57#ibcon#about to read 3, iclass 23, count 2 2006.211.08:00:11.59#ibcon#read 3, iclass 23, count 2 2006.211.08:00:11.59#ibcon#about to read 4, iclass 23, count 2 2006.211.08:00:11.59#ibcon#read 4, iclass 23, count 2 2006.211.08:00:11.59#ibcon#about to read 5, iclass 23, count 2 2006.211.08:00:11.59#ibcon#read 5, iclass 23, count 2 2006.211.08:00:11.59#ibcon#about to read 6, iclass 23, count 2 2006.211.08:00:11.59#ibcon#read 6, iclass 23, count 2 2006.211.08:00:11.59#ibcon#end of sib2, iclass 23, count 2 2006.211.08:00:11.59#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:00:11.59#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:00:11.59#ibcon#[27=AT05-03\r\n] 2006.211.08:00:11.59#ibcon#*before write, iclass 23, count 2 2006.211.08:00:11.59#ibcon#enter sib2, iclass 23, count 2 2006.211.08:00:11.59#ibcon#flushed, iclass 23, count 2 2006.211.08:00:11.59#ibcon#about to write, iclass 23, count 2 2006.211.08:00:11.59#ibcon#wrote, iclass 23, count 2 2006.211.08:00:11.59#ibcon#about to read 3, iclass 23, count 2 2006.211.08:00:11.62#ibcon#read 3, iclass 23, count 2 2006.211.08:00:11.62#ibcon#about to read 4, iclass 23, count 2 2006.211.08:00:11.62#ibcon#read 4, iclass 23, count 2 2006.211.08:00:11.62#ibcon#about to read 5, iclass 23, count 2 2006.211.08:00:11.62#ibcon#read 5, iclass 23, count 2 2006.211.08:00:11.62#ibcon#about to read 6, iclass 23, count 2 2006.211.08:00:11.62#ibcon#read 6, iclass 23, count 2 2006.211.08:00:11.62#ibcon#end of sib2, iclass 23, count 2 2006.211.08:00:11.62#ibcon#*after write, iclass 23, count 2 2006.211.08:00:11.62#ibcon#*before return 0, iclass 23, count 2 2006.211.08:00:11.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:00:11.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:00:11.62#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:00:11.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:11.62#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:00:11.74#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:00:11.74#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:00:11.74#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:00:11.74#ibcon#first serial, iclass 23, count 0 2006.211.08:00:11.74#ibcon#enter sib2, iclass 23, count 0 2006.211.08:00:11.74#ibcon#flushed, iclass 23, count 0 2006.211.08:00:11.74#ibcon#about to write, iclass 23, count 0 2006.211.08:00:11.74#ibcon#wrote, iclass 23, count 0 2006.211.08:00:11.74#ibcon#about to read 3, iclass 23, count 0 2006.211.08:00:11.76#ibcon#read 3, iclass 23, count 0 2006.211.08:00:11.76#ibcon#about to read 4, iclass 23, count 0 2006.211.08:00:11.76#ibcon#read 4, iclass 23, count 0 2006.211.08:00:11.76#ibcon#about to read 5, iclass 23, count 0 2006.211.08:00:11.76#ibcon#read 5, iclass 23, count 0 2006.211.08:00:11.76#ibcon#about to read 6, iclass 23, count 0 2006.211.08:00:11.76#ibcon#read 6, iclass 23, count 0 2006.211.08:00:11.76#ibcon#end of sib2, iclass 23, count 0 2006.211.08:00:11.76#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:00:11.76#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:00:11.76#ibcon#[27=USB\r\n] 2006.211.08:00:11.76#ibcon#*before write, iclass 23, count 0 2006.211.08:00:11.76#ibcon#enter sib2, iclass 23, count 0 2006.211.08:00:11.76#ibcon#flushed, iclass 23, count 0 2006.211.08:00:11.76#ibcon#about to write, iclass 23, count 0 2006.211.08:00:11.76#ibcon#wrote, iclass 23, count 0 2006.211.08:00:11.76#ibcon#about to read 3, iclass 23, count 0 2006.211.08:00:11.79#ibcon#read 3, iclass 23, count 0 2006.211.08:00:11.79#ibcon#about to read 4, iclass 23, count 0 2006.211.08:00:11.79#ibcon#read 4, iclass 23, count 0 2006.211.08:00:11.79#ibcon#about to read 5, iclass 23, count 0 2006.211.08:00:11.79#ibcon#read 5, iclass 23, count 0 2006.211.08:00:11.79#ibcon#about to read 6, iclass 23, count 0 2006.211.08:00:11.79#ibcon#read 6, iclass 23, count 0 2006.211.08:00:11.79#ibcon#end of sib2, iclass 23, count 0 2006.211.08:00:11.79#ibcon#*after write, iclass 23, count 0 2006.211.08:00:11.79#ibcon#*before return 0, iclass 23, count 0 2006.211.08:00:11.79#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:00:11.79#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:00:11.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:00:11.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:00:11.79$vc4f8/vblo=6,752.99 2006.211.08:00:11.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:00:11.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:00:11.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:00:11.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:11.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:11.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:11.79#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:00:11.79#ibcon#first serial, iclass 25, count 0 2006.211.08:00:11.79#ibcon#enter sib2, iclass 25, count 0 2006.211.08:00:11.79#ibcon#flushed, iclass 25, count 0 2006.211.08:00:11.79#ibcon#about to write, iclass 25, count 0 2006.211.08:00:11.79#ibcon#wrote, iclass 25, count 0 2006.211.08:00:11.79#ibcon#about to read 3, iclass 25, count 0 2006.211.08:00:11.81#ibcon#read 3, iclass 25, count 0 2006.211.08:00:11.81#ibcon#about to read 4, iclass 25, count 0 2006.211.08:00:11.81#ibcon#read 4, iclass 25, count 0 2006.211.08:00:11.81#ibcon#about to read 5, iclass 25, count 0 2006.211.08:00:11.81#ibcon#read 5, iclass 25, count 0 2006.211.08:00:11.81#ibcon#about to read 6, iclass 25, count 0 2006.211.08:00:11.81#ibcon#read 6, iclass 25, count 0 2006.211.08:00:11.81#ibcon#end of sib2, iclass 25, count 0 2006.211.08:00:11.81#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:00:11.81#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:00:11.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:00:11.81#ibcon#*before write, iclass 25, count 0 2006.211.08:00:11.81#ibcon#enter sib2, iclass 25, count 0 2006.211.08:00:11.81#ibcon#flushed, iclass 25, count 0 2006.211.08:00:11.81#ibcon#about to write, iclass 25, count 0 2006.211.08:00:11.81#ibcon#wrote, iclass 25, count 0 2006.211.08:00:11.81#ibcon#about to read 3, iclass 25, count 0 2006.211.08:00:11.85#ibcon#read 3, iclass 25, count 0 2006.211.08:00:11.85#ibcon#about to read 4, iclass 25, count 0 2006.211.08:00:11.85#ibcon#read 4, iclass 25, count 0 2006.211.08:00:11.85#ibcon#about to read 5, iclass 25, count 0 2006.211.08:00:11.85#ibcon#read 5, iclass 25, count 0 2006.211.08:00:11.85#ibcon#about to read 6, iclass 25, count 0 2006.211.08:00:11.85#ibcon#read 6, iclass 25, count 0 2006.211.08:00:11.85#ibcon#end of sib2, iclass 25, count 0 2006.211.08:00:11.85#ibcon#*after write, iclass 25, count 0 2006.211.08:00:11.85#ibcon#*before return 0, iclass 25, count 0 2006.211.08:00:11.85#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:11.85#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:00:11.85#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:00:11.85#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:00:11.85$vc4f8/vb=6,3 2006.211.08:00:11.85#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:00:11.85#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:00:11.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:00:11.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:11.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:11.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:11.91#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:00:11.91#ibcon#first serial, iclass 27, count 2 2006.211.08:00:11.91#ibcon#enter sib2, iclass 27, count 2 2006.211.08:00:11.91#ibcon#flushed, iclass 27, count 2 2006.211.08:00:11.91#ibcon#about to write, iclass 27, count 2 2006.211.08:00:11.91#ibcon#wrote, iclass 27, count 2 2006.211.08:00:11.91#ibcon#about to read 3, iclass 27, count 2 2006.211.08:00:11.93#ibcon#read 3, iclass 27, count 2 2006.211.08:00:11.93#ibcon#about to read 4, iclass 27, count 2 2006.211.08:00:11.93#ibcon#read 4, iclass 27, count 2 2006.211.08:00:11.93#ibcon#about to read 5, iclass 27, count 2 2006.211.08:00:11.93#ibcon#read 5, iclass 27, count 2 2006.211.08:00:11.93#ibcon#about to read 6, iclass 27, count 2 2006.211.08:00:11.93#ibcon#read 6, iclass 27, count 2 2006.211.08:00:11.93#ibcon#end of sib2, iclass 27, count 2 2006.211.08:00:11.93#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:00:11.93#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:00:11.93#ibcon#[27=AT06-03\r\n] 2006.211.08:00:11.93#ibcon#*before write, iclass 27, count 2 2006.211.08:00:11.93#ibcon#enter sib2, iclass 27, count 2 2006.211.08:00:11.93#ibcon#flushed, iclass 27, count 2 2006.211.08:00:11.93#ibcon#about to write, iclass 27, count 2 2006.211.08:00:11.93#ibcon#wrote, iclass 27, count 2 2006.211.08:00:11.93#ibcon#about to read 3, iclass 27, count 2 2006.211.08:00:11.96#ibcon#read 3, iclass 27, count 2 2006.211.08:00:11.96#ibcon#about to read 4, iclass 27, count 2 2006.211.08:00:11.96#ibcon#read 4, iclass 27, count 2 2006.211.08:00:11.96#ibcon#about to read 5, iclass 27, count 2 2006.211.08:00:11.96#ibcon#read 5, iclass 27, count 2 2006.211.08:00:11.96#ibcon#about to read 6, iclass 27, count 2 2006.211.08:00:11.96#ibcon#read 6, iclass 27, count 2 2006.211.08:00:11.96#ibcon#end of sib2, iclass 27, count 2 2006.211.08:00:11.96#ibcon#*after write, iclass 27, count 2 2006.211.08:00:11.96#ibcon#*before return 0, iclass 27, count 2 2006.211.08:00:11.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:11.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:00:11.96#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:00:11.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:00:11.96#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:12.08#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:12.08#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:12.08#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:00:12.08#ibcon#first serial, iclass 27, count 0 2006.211.08:00:12.08#ibcon#enter sib2, iclass 27, count 0 2006.211.08:00:12.08#ibcon#flushed, iclass 27, count 0 2006.211.08:00:12.08#ibcon#about to write, iclass 27, count 0 2006.211.08:00:12.08#ibcon#wrote, iclass 27, count 0 2006.211.08:00:12.08#ibcon#about to read 3, iclass 27, count 0 2006.211.08:00:12.10#ibcon#read 3, iclass 27, count 0 2006.211.08:00:12.10#ibcon#about to read 4, iclass 27, count 0 2006.211.08:00:12.10#ibcon#read 4, iclass 27, count 0 2006.211.08:00:12.10#ibcon#about to read 5, iclass 27, count 0 2006.211.08:00:12.10#ibcon#read 5, iclass 27, count 0 2006.211.08:00:12.10#ibcon#about to read 6, iclass 27, count 0 2006.211.08:00:12.10#ibcon#read 6, iclass 27, count 0 2006.211.08:00:12.10#ibcon#end of sib2, iclass 27, count 0 2006.211.08:00:12.10#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:00:12.10#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:00:12.10#ibcon#[27=USB\r\n] 2006.211.08:00:12.10#ibcon#*before write, iclass 27, count 0 2006.211.08:00:12.10#ibcon#enter sib2, iclass 27, count 0 2006.211.08:00:12.10#ibcon#flushed, iclass 27, count 0 2006.211.08:00:12.10#ibcon#about to write, iclass 27, count 0 2006.211.08:00:12.10#ibcon#wrote, iclass 27, count 0 2006.211.08:00:12.10#ibcon#about to read 3, iclass 27, count 0 2006.211.08:00:12.13#ibcon#read 3, iclass 27, count 0 2006.211.08:00:12.13#ibcon#about to read 4, iclass 27, count 0 2006.211.08:00:12.13#ibcon#read 4, iclass 27, count 0 2006.211.08:00:12.13#ibcon#about to read 5, iclass 27, count 0 2006.211.08:00:12.13#ibcon#read 5, iclass 27, count 0 2006.211.08:00:12.13#ibcon#about to read 6, iclass 27, count 0 2006.211.08:00:12.13#ibcon#read 6, iclass 27, count 0 2006.211.08:00:12.13#ibcon#end of sib2, iclass 27, count 0 2006.211.08:00:12.13#ibcon#*after write, iclass 27, count 0 2006.211.08:00:12.13#ibcon#*before return 0, iclass 27, count 0 2006.211.08:00:12.13#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:12.13#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:00:12.13#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:00:12.13#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:00:12.13$vc4f8/vabw=wide 2006.211.08:00:12.13#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:00:12.13#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:00:12.13#ibcon#ireg 8 cls_cnt 0 2006.211.08:00:12.13#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:12.13#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:12.13#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:12.13#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:00:12.13#ibcon#first serial, iclass 29, count 0 2006.211.08:00:12.13#ibcon#enter sib2, iclass 29, count 0 2006.211.08:00:12.13#ibcon#flushed, iclass 29, count 0 2006.211.08:00:12.13#ibcon#about to write, iclass 29, count 0 2006.211.08:00:12.13#ibcon#wrote, iclass 29, count 0 2006.211.08:00:12.13#ibcon#about to read 3, iclass 29, count 0 2006.211.08:00:12.15#ibcon#read 3, iclass 29, count 0 2006.211.08:00:12.15#ibcon#about to read 4, iclass 29, count 0 2006.211.08:00:12.15#ibcon#read 4, iclass 29, count 0 2006.211.08:00:12.15#ibcon#about to read 5, iclass 29, count 0 2006.211.08:00:12.15#ibcon#read 5, iclass 29, count 0 2006.211.08:00:12.15#ibcon#about to read 6, iclass 29, count 0 2006.211.08:00:12.15#ibcon#read 6, iclass 29, count 0 2006.211.08:00:12.15#ibcon#end of sib2, iclass 29, count 0 2006.211.08:00:12.15#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:00:12.15#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:00:12.15#ibcon#[25=BW32\r\n] 2006.211.08:00:12.15#ibcon#*before write, iclass 29, count 0 2006.211.08:00:12.15#ibcon#enter sib2, iclass 29, count 0 2006.211.08:00:12.15#ibcon#flushed, iclass 29, count 0 2006.211.08:00:12.15#ibcon#about to write, iclass 29, count 0 2006.211.08:00:12.15#ibcon#wrote, iclass 29, count 0 2006.211.08:00:12.15#ibcon#about to read 3, iclass 29, count 0 2006.211.08:00:12.18#ibcon#read 3, iclass 29, count 0 2006.211.08:00:12.18#ibcon#about to read 4, iclass 29, count 0 2006.211.08:00:12.18#ibcon#read 4, iclass 29, count 0 2006.211.08:00:12.18#ibcon#about to read 5, iclass 29, count 0 2006.211.08:00:12.18#ibcon#read 5, iclass 29, count 0 2006.211.08:00:12.18#ibcon#about to read 6, iclass 29, count 0 2006.211.08:00:12.18#ibcon#read 6, iclass 29, count 0 2006.211.08:00:12.18#ibcon#end of sib2, iclass 29, count 0 2006.211.08:00:12.18#ibcon#*after write, iclass 29, count 0 2006.211.08:00:12.18#ibcon#*before return 0, iclass 29, count 0 2006.211.08:00:12.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:12.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:00:12.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:00:12.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:00:12.18$vc4f8/vbbw=wide 2006.211.08:00:12.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.08:00:12.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.08:00:12.18#ibcon#ireg 8 cls_cnt 0 2006.211.08:00:12.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:00:12.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:00:12.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:00:12.25#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:00:12.25#ibcon#first serial, iclass 31, count 0 2006.211.08:00:12.25#ibcon#enter sib2, iclass 31, count 0 2006.211.08:00:12.25#ibcon#flushed, iclass 31, count 0 2006.211.08:00:12.25#ibcon#about to write, iclass 31, count 0 2006.211.08:00:12.25#ibcon#wrote, iclass 31, count 0 2006.211.08:00:12.25#ibcon#about to read 3, iclass 31, count 0 2006.211.08:00:12.27#ibcon#read 3, iclass 31, count 0 2006.211.08:00:12.27#ibcon#about to read 4, iclass 31, count 0 2006.211.08:00:12.27#ibcon#read 4, iclass 31, count 0 2006.211.08:00:12.27#ibcon#about to read 5, iclass 31, count 0 2006.211.08:00:12.27#ibcon#read 5, iclass 31, count 0 2006.211.08:00:12.27#ibcon#about to read 6, iclass 31, count 0 2006.211.08:00:12.27#ibcon#read 6, iclass 31, count 0 2006.211.08:00:12.27#ibcon#end of sib2, iclass 31, count 0 2006.211.08:00:12.27#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:00:12.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:00:12.27#ibcon#[27=BW32\r\n] 2006.211.08:00:12.27#ibcon#*before write, iclass 31, count 0 2006.211.08:00:12.27#ibcon#enter sib2, iclass 31, count 0 2006.211.08:00:12.27#ibcon#flushed, iclass 31, count 0 2006.211.08:00:12.27#ibcon#about to write, iclass 31, count 0 2006.211.08:00:12.27#ibcon#wrote, iclass 31, count 0 2006.211.08:00:12.27#ibcon#about to read 3, iclass 31, count 0 2006.211.08:00:12.30#ibcon#read 3, iclass 31, count 0 2006.211.08:00:12.30#ibcon#about to read 4, iclass 31, count 0 2006.211.08:00:12.30#ibcon#read 4, iclass 31, count 0 2006.211.08:00:12.30#ibcon#about to read 5, iclass 31, count 0 2006.211.08:00:12.30#ibcon#read 5, iclass 31, count 0 2006.211.08:00:12.30#ibcon#about to read 6, iclass 31, count 0 2006.211.08:00:12.30#ibcon#read 6, iclass 31, count 0 2006.211.08:00:12.30#ibcon#end of sib2, iclass 31, count 0 2006.211.08:00:12.30#ibcon#*after write, iclass 31, count 0 2006.211.08:00:12.30#ibcon#*before return 0, iclass 31, count 0 2006.211.08:00:12.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:00:12.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:00:12.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:00:12.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:00:12.30$4f8m12a/ifd4f 2006.211.08:00:12.30$ifd4f/lo= 2006.211.08:00:12.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:00:12.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:00:12.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:00:12.30$ifd4f/patch= 2006.211.08:00:12.30$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:00:12.30$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:00:12.30$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:00:12.30$4f8m12a/"form=m,16.000,1:2 2006.211.08:00:12.30$4f8m12a/"tpicd 2006.211.08:00:12.30$4f8m12a/echo=off 2006.211.08:00:12.30$4f8m12a/xlog=off 2006.211.08:00:12.30:!2006.211.08:01:20 2006.211.08:00:58.14#trakl#Source acquired 2006.211.08:00:58.14#flagr#flagr/antenna,acquired 2006.211.08:01:20.00:preob 2006.211.08:01:20.14/onsource/TRACKING 2006.211.08:01:20.14:!2006.211.08:01:30 2006.211.08:01:30.00:data_valid=on 2006.211.08:01:30.00:midob 2006.211.08:01:31.14/onsource/TRACKING 2006.211.08:01:31.14/wx/24.78,1010.0,77 2006.211.08:01:31.26/cable/+6.4390E-03 2006.211.08:01:32.35/va/01,08,usb,yes,35,37 2006.211.08:01:32.35/va/02,07,usb,yes,35,37 2006.211.08:01:32.35/va/03,06,usb,yes,37,37 2006.211.08:01:32.35/va/04,07,usb,yes,36,38 2006.211.08:01:32.35/va/05,07,usb,yes,39,41 2006.211.08:01:32.35/va/06,06,usb,yes,38,38 2006.211.08:01:32.35/va/07,06,usb,yes,39,38 2006.211.08:01:32.35/va/08,07,usb,yes,37,36 2006.211.08:01:32.58/valo/01,532.99,yes,locked 2006.211.08:01:32.58/valo/02,572.99,yes,locked 2006.211.08:01:32.58/valo/03,672.99,yes,locked 2006.211.08:01:32.58/valo/04,832.99,yes,locked 2006.211.08:01:32.58/valo/05,652.99,yes,locked 2006.211.08:01:32.58/valo/06,772.99,yes,locked 2006.211.08:01:32.58/valo/07,832.99,yes,locked 2006.211.08:01:32.58/valo/08,852.99,yes,locked 2006.211.08:01:33.67/vb/01,04,usb,yes,27,26 2006.211.08:01:33.67/vb/02,04,usb,yes,29,30 2006.211.08:01:33.67/vb/03,03,usb,yes,32,36 2006.211.08:01:33.67/vb/04,03,usb,yes,33,33 2006.211.08:01:33.67/vb/05,03,usb,yes,31,36 2006.211.08:01:33.67/vb/06,03,usb,yes,32,35 2006.211.08:01:33.67/vb/07,04,usb,yes,28,28 2006.211.08:01:33.67/vb/08,03,usb,yes,32,36 2006.211.08:01:33.90/vblo/01,632.99,yes,locked 2006.211.08:01:33.90/vblo/02,640.99,yes,locked 2006.211.08:01:33.90/vblo/03,656.99,yes,locked 2006.211.08:01:33.90/vblo/04,712.99,yes,locked 2006.211.08:01:33.90/vblo/05,744.99,yes,locked 2006.211.08:01:33.90/vblo/06,752.99,yes,locked 2006.211.08:01:33.90/vblo/07,734.99,yes,locked 2006.211.08:01:33.90/vblo/08,744.99,yes,locked 2006.211.08:01:34.05/vabw/8 2006.211.08:01:34.20/vbbw/8 2006.211.08:01:34.29/xfe/off,on,12.0 2006.211.08:01:34.66/ifatt/23,28,28,28 2006.211.08:01:35.08/fmout-gps/S +4.47E-07 2006.211.08:01:35.12:!2006.211.08:02:30 2006.211.08:02:30.02:data_valid=off 2006.211.08:02:30.02:postob 2006.211.08:02:30.26/cable/+6.4374E-03 2006.211.08:02:30.26/wx/24.76,1010.0,78 2006.211.08:02:31.08/fmout-gps/S +4.46E-07 2006.211.08:02:31.08:scan_name=211-0803,k06211,60 2006.211.08:02:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.211.08:02:31.15#flagr#flagr/antenna,new-source 2006.211.08:02:32.15:checkk5 2006.211.08:02:32.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:02:32.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:02:33.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:02:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:02:33.84/chk_obsdata//k5ts1/T2110801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:02:34.18/chk_obsdata//k5ts2/T2110801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:02:34.52/chk_obsdata//k5ts3/T2110801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:02:34.85/chk_obsdata//k5ts4/T2110801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:02:35.51/k5log//k5ts1_log_newline 2006.211.08:02:36.16/k5log//k5ts2_log_newline 2006.211.08:02:36.81/k5log//k5ts3_log_newline 2006.211.08:02:37.46/k5log//k5ts4_log_newline 2006.211.08:02:37.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:02:37.48:4f8m12a=2 2006.211.08:02:37.48$4f8m12a/echo=on 2006.211.08:02:37.48$4f8m12a/pcalon 2006.211.08:02:37.48$pcalon/"no phase cal control is implemented here 2006.211.08:02:37.48$4f8m12a/"tpicd=stop 2006.211.08:02:37.48$4f8m12a/vc4f8 2006.211.08:02:37.48$vc4f8/valo=1,532.99 2006.211.08:02:37.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:02:37.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:02:37.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:37.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:37.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:37.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:37.49#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:02:37.49#ibcon#first serial, iclass 18, count 0 2006.211.08:02:37.49#ibcon#enter sib2, iclass 18, count 0 2006.211.08:02:37.49#ibcon#flushed, iclass 18, count 0 2006.211.08:02:37.49#ibcon#about to write, iclass 18, count 0 2006.211.08:02:37.49#ibcon#wrote, iclass 18, count 0 2006.211.08:02:37.49#ibcon#about to read 3, iclass 18, count 0 2006.211.08:02:37.50#ibcon#read 3, iclass 18, count 0 2006.211.08:02:37.50#ibcon#about to read 4, iclass 18, count 0 2006.211.08:02:37.50#ibcon#read 4, iclass 18, count 0 2006.211.08:02:37.50#ibcon#about to read 5, iclass 18, count 0 2006.211.08:02:37.50#ibcon#read 5, iclass 18, count 0 2006.211.08:02:37.50#ibcon#about to read 6, iclass 18, count 0 2006.211.08:02:37.50#ibcon#read 6, iclass 18, count 0 2006.211.08:02:37.50#ibcon#end of sib2, iclass 18, count 0 2006.211.08:02:37.51#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:02:37.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:02:37.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:02:37.51#ibcon#*before write, iclass 18, count 0 2006.211.08:02:37.51#ibcon#enter sib2, iclass 18, count 0 2006.211.08:02:37.51#ibcon#flushed, iclass 18, count 0 2006.211.08:02:37.51#ibcon#about to write, iclass 18, count 0 2006.211.08:02:37.51#ibcon#wrote, iclass 18, count 0 2006.211.08:02:37.51#ibcon#about to read 3, iclass 18, count 0 2006.211.08:02:37.55#ibcon#read 3, iclass 18, count 0 2006.211.08:02:37.55#ibcon#about to read 4, iclass 18, count 0 2006.211.08:02:37.55#ibcon#read 4, iclass 18, count 0 2006.211.08:02:37.55#ibcon#about to read 5, iclass 18, count 0 2006.211.08:02:37.55#ibcon#read 5, iclass 18, count 0 2006.211.08:02:37.55#ibcon#about to read 6, iclass 18, count 0 2006.211.08:02:37.55#ibcon#read 6, iclass 18, count 0 2006.211.08:02:37.55#ibcon#end of sib2, iclass 18, count 0 2006.211.08:02:37.55#ibcon#*after write, iclass 18, count 0 2006.211.08:02:37.56#ibcon#*before return 0, iclass 18, count 0 2006.211.08:02:37.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:37.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:37.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:02:37.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:02:37.56$vc4f8/va=1,8 2006.211.08:02:37.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:02:37.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:02:37.56#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:37.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:37.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:37.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:37.56#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:02:37.56#ibcon#first serial, iclass 20, count 2 2006.211.08:02:37.56#ibcon#enter sib2, iclass 20, count 2 2006.211.08:02:37.56#ibcon#flushed, iclass 20, count 2 2006.211.08:02:37.56#ibcon#about to write, iclass 20, count 2 2006.211.08:02:37.56#ibcon#wrote, iclass 20, count 2 2006.211.08:02:37.56#ibcon#about to read 3, iclass 20, count 2 2006.211.08:02:37.57#ibcon#read 3, iclass 20, count 2 2006.211.08:02:37.57#ibcon#about to read 4, iclass 20, count 2 2006.211.08:02:37.57#ibcon#read 4, iclass 20, count 2 2006.211.08:02:37.57#ibcon#about to read 5, iclass 20, count 2 2006.211.08:02:37.57#ibcon#read 5, iclass 20, count 2 2006.211.08:02:37.57#ibcon#about to read 6, iclass 20, count 2 2006.211.08:02:37.57#ibcon#read 6, iclass 20, count 2 2006.211.08:02:37.57#ibcon#end of sib2, iclass 20, count 2 2006.211.08:02:37.57#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:02:37.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:02:37.58#ibcon#[25=AT01-08\r\n] 2006.211.08:02:37.58#ibcon#*before write, iclass 20, count 2 2006.211.08:02:37.58#ibcon#enter sib2, iclass 20, count 2 2006.211.08:02:37.58#ibcon#flushed, iclass 20, count 2 2006.211.08:02:37.58#ibcon#about to write, iclass 20, count 2 2006.211.08:02:37.58#ibcon#wrote, iclass 20, count 2 2006.211.08:02:37.58#ibcon#about to read 3, iclass 20, count 2 2006.211.08:02:37.60#ibcon#read 3, iclass 20, count 2 2006.211.08:02:37.60#ibcon#about to read 4, iclass 20, count 2 2006.211.08:02:37.60#ibcon#read 4, iclass 20, count 2 2006.211.08:02:37.60#ibcon#about to read 5, iclass 20, count 2 2006.211.08:02:37.60#ibcon#read 5, iclass 20, count 2 2006.211.08:02:37.60#ibcon#about to read 6, iclass 20, count 2 2006.211.08:02:37.60#ibcon#read 6, iclass 20, count 2 2006.211.08:02:37.60#ibcon#end of sib2, iclass 20, count 2 2006.211.08:02:37.60#ibcon#*after write, iclass 20, count 2 2006.211.08:02:37.61#ibcon#*before return 0, iclass 20, count 2 2006.211.08:02:37.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:37.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:37.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:02:37.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:37.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:37.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:37.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:37.72#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:02:37.72#ibcon#first serial, iclass 20, count 0 2006.211.08:02:37.72#ibcon#enter sib2, iclass 20, count 0 2006.211.08:02:37.72#ibcon#flushed, iclass 20, count 0 2006.211.08:02:37.72#ibcon#about to write, iclass 20, count 0 2006.211.08:02:37.72#ibcon#wrote, iclass 20, count 0 2006.211.08:02:37.72#ibcon#about to read 3, iclass 20, count 0 2006.211.08:02:37.74#ibcon#read 3, iclass 20, count 0 2006.211.08:02:37.74#ibcon#about to read 4, iclass 20, count 0 2006.211.08:02:37.74#ibcon#read 4, iclass 20, count 0 2006.211.08:02:37.74#ibcon#about to read 5, iclass 20, count 0 2006.211.08:02:37.74#ibcon#read 5, iclass 20, count 0 2006.211.08:02:37.74#ibcon#about to read 6, iclass 20, count 0 2006.211.08:02:37.74#ibcon#read 6, iclass 20, count 0 2006.211.08:02:37.74#ibcon#end of sib2, iclass 20, count 0 2006.211.08:02:37.74#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:02:37.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:02:37.75#ibcon#[25=USB\r\n] 2006.211.08:02:37.75#ibcon#*before write, iclass 20, count 0 2006.211.08:02:37.75#ibcon#enter sib2, iclass 20, count 0 2006.211.08:02:37.75#ibcon#flushed, iclass 20, count 0 2006.211.08:02:37.75#ibcon#about to write, iclass 20, count 0 2006.211.08:02:37.75#ibcon#wrote, iclass 20, count 0 2006.211.08:02:37.75#ibcon#about to read 3, iclass 20, count 0 2006.211.08:02:37.77#ibcon#read 3, iclass 20, count 0 2006.211.08:02:37.77#ibcon#about to read 4, iclass 20, count 0 2006.211.08:02:37.77#ibcon#read 4, iclass 20, count 0 2006.211.08:02:37.77#ibcon#about to read 5, iclass 20, count 0 2006.211.08:02:37.77#ibcon#read 5, iclass 20, count 0 2006.211.08:02:37.77#ibcon#about to read 6, iclass 20, count 0 2006.211.08:02:37.77#ibcon#read 6, iclass 20, count 0 2006.211.08:02:37.77#ibcon#end of sib2, iclass 20, count 0 2006.211.08:02:37.77#ibcon#*after write, iclass 20, count 0 2006.211.08:02:37.77#ibcon#*before return 0, iclass 20, count 0 2006.211.08:02:37.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:37.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:37.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:02:37.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:02:37.78$vc4f8/valo=2,572.99 2006.211.08:02:37.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:02:37.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:02:37.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:37.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:37.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:37.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:37.78#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:02:37.78#ibcon#first serial, iclass 22, count 0 2006.211.08:02:37.78#ibcon#enter sib2, iclass 22, count 0 2006.211.08:02:37.78#ibcon#flushed, iclass 22, count 0 2006.211.08:02:37.78#ibcon#about to write, iclass 22, count 0 2006.211.08:02:37.78#ibcon#wrote, iclass 22, count 0 2006.211.08:02:37.78#ibcon#about to read 3, iclass 22, count 0 2006.211.08:02:37.79#ibcon#read 3, iclass 22, count 0 2006.211.08:02:37.79#ibcon#about to read 4, iclass 22, count 0 2006.211.08:02:37.79#ibcon#read 4, iclass 22, count 0 2006.211.08:02:37.79#ibcon#about to read 5, iclass 22, count 0 2006.211.08:02:37.79#ibcon#read 5, iclass 22, count 0 2006.211.08:02:37.79#ibcon#about to read 6, iclass 22, count 0 2006.211.08:02:37.79#ibcon#read 6, iclass 22, count 0 2006.211.08:02:37.79#ibcon#end of sib2, iclass 22, count 0 2006.211.08:02:37.79#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:02:37.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:02:37.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:02:37.80#ibcon#*before write, iclass 22, count 0 2006.211.08:02:37.80#ibcon#enter sib2, iclass 22, count 0 2006.211.08:02:37.80#ibcon#flushed, iclass 22, count 0 2006.211.08:02:37.80#ibcon#about to write, iclass 22, count 0 2006.211.08:02:37.80#ibcon#wrote, iclass 22, count 0 2006.211.08:02:37.80#ibcon#about to read 3, iclass 22, count 0 2006.211.08:02:37.83#ibcon#read 3, iclass 22, count 0 2006.211.08:02:37.83#ibcon#about to read 4, iclass 22, count 0 2006.211.08:02:37.83#ibcon#read 4, iclass 22, count 0 2006.211.08:02:37.83#ibcon#about to read 5, iclass 22, count 0 2006.211.08:02:37.83#ibcon#read 5, iclass 22, count 0 2006.211.08:02:37.83#ibcon#about to read 6, iclass 22, count 0 2006.211.08:02:37.83#ibcon#read 6, iclass 22, count 0 2006.211.08:02:37.83#ibcon#end of sib2, iclass 22, count 0 2006.211.08:02:37.83#ibcon#*after write, iclass 22, count 0 2006.211.08:02:37.84#ibcon#*before return 0, iclass 22, count 0 2006.211.08:02:37.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:37.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:37.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:02:37.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:02:37.84$vc4f8/va=2,7 2006.211.08:02:37.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:02:37.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:02:37.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:37.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:37.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:37.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:37.89#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:02:37.89#ibcon#first serial, iclass 24, count 2 2006.211.08:02:37.89#ibcon#enter sib2, iclass 24, count 2 2006.211.08:02:37.89#ibcon#flushed, iclass 24, count 2 2006.211.08:02:37.89#ibcon#about to write, iclass 24, count 2 2006.211.08:02:37.89#ibcon#wrote, iclass 24, count 2 2006.211.08:02:37.89#ibcon#about to read 3, iclass 24, count 2 2006.211.08:02:37.91#ibcon#read 3, iclass 24, count 2 2006.211.08:02:37.91#ibcon#about to read 4, iclass 24, count 2 2006.211.08:02:37.91#ibcon#read 4, iclass 24, count 2 2006.211.08:02:37.91#ibcon#about to read 5, iclass 24, count 2 2006.211.08:02:37.91#ibcon#read 5, iclass 24, count 2 2006.211.08:02:37.91#ibcon#about to read 6, iclass 24, count 2 2006.211.08:02:37.91#ibcon#read 6, iclass 24, count 2 2006.211.08:02:37.91#ibcon#end of sib2, iclass 24, count 2 2006.211.08:02:37.91#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:02:37.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:02:37.92#ibcon#[25=AT02-07\r\n] 2006.211.08:02:37.92#ibcon#*before write, iclass 24, count 2 2006.211.08:02:37.92#ibcon#enter sib2, iclass 24, count 2 2006.211.08:02:37.92#ibcon#flushed, iclass 24, count 2 2006.211.08:02:37.92#ibcon#about to write, iclass 24, count 2 2006.211.08:02:37.92#ibcon#wrote, iclass 24, count 2 2006.211.08:02:37.92#ibcon#about to read 3, iclass 24, count 2 2006.211.08:02:37.94#ibcon#read 3, iclass 24, count 2 2006.211.08:02:37.94#ibcon#about to read 4, iclass 24, count 2 2006.211.08:02:37.94#ibcon#read 4, iclass 24, count 2 2006.211.08:02:37.94#ibcon#about to read 5, iclass 24, count 2 2006.211.08:02:37.94#ibcon#read 5, iclass 24, count 2 2006.211.08:02:37.94#ibcon#about to read 6, iclass 24, count 2 2006.211.08:02:37.94#ibcon#read 6, iclass 24, count 2 2006.211.08:02:37.94#ibcon#end of sib2, iclass 24, count 2 2006.211.08:02:37.94#ibcon#*after write, iclass 24, count 2 2006.211.08:02:37.95#ibcon#*before return 0, iclass 24, count 2 2006.211.08:02:37.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:37.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:37.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:02:37.95#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:37.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:38.06#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:38.06#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:38.06#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:02:38.06#ibcon#first serial, iclass 24, count 0 2006.211.08:02:38.06#ibcon#enter sib2, iclass 24, count 0 2006.211.08:02:38.06#ibcon#flushed, iclass 24, count 0 2006.211.08:02:38.06#ibcon#about to write, iclass 24, count 0 2006.211.08:02:38.06#ibcon#wrote, iclass 24, count 0 2006.211.08:02:38.06#ibcon#about to read 3, iclass 24, count 0 2006.211.08:02:38.08#ibcon#read 3, iclass 24, count 0 2006.211.08:02:38.08#ibcon#about to read 4, iclass 24, count 0 2006.211.08:02:38.08#ibcon#read 4, iclass 24, count 0 2006.211.08:02:38.08#ibcon#about to read 5, iclass 24, count 0 2006.211.08:02:38.08#ibcon#read 5, iclass 24, count 0 2006.211.08:02:38.08#ibcon#about to read 6, iclass 24, count 0 2006.211.08:02:38.08#ibcon#read 6, iclass 24, count 0 2006.211.08:02:38.08#ibcon#end of sib2, iclass 24, count 0 2006.211.08:02:38.08#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:02:38.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:02:38.09#ibcon#[25=USB\r\n] 2006.211.08:02:38.09#ibcon#*before write, iclass 24, count 0 2006.211.08:02:38.09#ibcon#enter sib2, iclass 24, count 0 2006.211.08:02:38.09#ibcon#flushed, iclass 24, count 0 2006.211.08:02:38.09#ibcon#about to write, iclass 24, count 0 2006.211.08:02:38.09#ibcon#wrote, iclass 24, count 0 2006.211.08:02:38.09#ibcon#about to read 3, iclass 24, count 0 2006.211.08:02:38.11#ibcon#read 3, iclass 24, count 0 2006.211.08:02:38.11#ibcon#about to read 4, iclass 24, count 0 2006.211.08:02:38.11#ibcon#read 4, iclass 24, count 0 2006.211.08:02:38.11#ibcon#about to read 5, iclass 24, count 0 2006.211.08:02:38.11#ibcon#read 5, iclass 24, count 0 2006.211.08:02:38.11#ibcon#about to read 6, iclass 24, count 0 2006.211.08:02:38.11#ibcon#read 6, iclass 24, count 0 2006.211.08:02:38.11#ibcon#end of sib2, iclass 24, count 0 2006.211.08:02:38.11#ibcon#*after write, iclass 24, count 0 2006.211.08:02:38.12#ibcon#*before return 0, iclass 24, count 0 2006.211.08:02:38.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:38.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:38.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:02:38.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:02:38.12$vc4f8/valo=3,672.99 2006.211.08:02:38.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:02:38.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:02:38.12#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:38.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:02:38.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:02:38.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:02:38.12#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:02:38.12#ibcon#first serial, iclass 26, count 0 2006.211.08:02:38.12#ibcon#enter sib2, iclass 26, count 0 2006.211.08:02:38.12#ibcon#flushed, iclass 26, count 0 2006.211.08:02:38.12#ibcon#about to write, iclass 26, count 0 2006.211.08:02:38.12#ibcon#wrote, iclass 26, count 0 2006.211.08:02:38.12#ibcon#about to read 3, iclass 26, count 0 2006.211.08:02:38.13#ibcon#read 3, iclass 26, count 0 2006.211.08:02:38.13#ibcon#about to read 4, iclass 26, count 0 2006.211.08:02:38.13#ibcon#read 4, iclass 26, count 0 2006.211.08:02:38.13#ibcon#about to read 5, iclass 26, count 0 2006.211.08:02:38.13#ibcon#read 5, iclass 26, count 0 2006.211.08:02:38.13#ibcon#about to read 6, iclass 26, count 0 2006.211.08:02:38.13#ibcon#read 6, iclass 26, count 0 2006.211.08:02:38.13#ibcon#end of sib2, iclass 26, count 0 2006.211.08:02:38.13#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:02:38.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:02:38.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:02:38.14#ibcon#*before write, iclass 26, count 0 2006.211.08:02:38.14#ibcon#enter sib2, iclass 26, count 0 2006.211.08:02:38.14#ibcon#flushed, iclass 26, count 0 2006.211.08:02:38.14#ibcon#about to write, iclass 26, count 0 2006.211.08:02:38.14#ibcon#wrote, iclass 26, count 0 2006.211.08:02:38.14#ibcon#about to read 3, iclass 26, count 0 2006.211.08:02:38.17#ibcon#read 3, iclass 26, count 0 2006.211.08:02:38.17#ibcon#about to read 4, iclass 26, count 0 2006.211.08:02:38.17#ibcon#read 4, iclass 26, count 0 2006.211.08:02:38.17#ibcon#about to read 5, iclass 26, count 0 2006.211.08:02:38.17#ibcon#read 5, iclass 26, count 0 2006.211.08:02:38.17#ibcon#about to read 6, iclass 26, count 0 2006.211.08:02:38.17#ibcon#read 6, iclass 26, count 0 2006.211.08:02:38.17#ibcon#end of sib2, iclass 26, count 0 2006.211.08:02:38.17#ibcon#*after write, iclass 26, count 0 2006.211.08:02:38.18#ibcon#*before return 0, iclass 26, count 0 2006.211.08:02:38.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:02:38.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:02:38.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:02:38.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:02:38.18$vc4f8/va=3,6 2006.211.08:02:38.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:02:38.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:02:38.18#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:38.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:02:38.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:02:38.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:02:38.23#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:02:38.23#ibcon#first serial, iclass 28, count 2 2006.211.08:02:38.23#ibcon#enter sib2, iclass 28, count 2 2006.211.08:02:38.23#ibcon#flushed, iclass 28, count 2 2006.211.08:02:38.23#ibcon#about to write, iclass 28, count 2 2006.211.08:02:38.23#ibcon#wrote, iclass 28, count 2 2006.211.08:02:38.23#ibcon#about to read 3, iclass 28, count 2 2006.211.08:02:38.25#ibcon#read 3, iclass 28, count 2 2006.211.08:02:38.25#ibcon#about to read 4, iclass 28, count 2 2006.211.08:02:38.25#ibcon#read 4, iclass 28, count 2 2006.211.08:02:38.25#ibcon#about to read 5, iclass 28, count 2 2006.211.08:02:38.25#ibcon#read 5, iclass 28, count 2 2006.211.08:02:38.25#ibcon#about to read 6, iclass 28, count 2 2006.211.08:02:38.25#ibcon#read 6, iclass 28, count 2 2006.211.08:02:38.25#ibcon#end of sib2, iclass 28, count 2 2006.211.08:02:38.25#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:02:38.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:02:38.26#ibcon#[25=AT03-06\r\n] 2006.211.08:02:38.26#ibcon#*before write, iclass 28, count 2 2006.211.08:02:38.26#ibcon#enter sib2, iclass 28, count 2 2006.211.08:02:38.26#ibcon#flushed, iclass 28, count 2 2006.211.08:02:38.26#ibcon#about to write, iclass 28, count 2 2006.211.08:02:38.26#ibcon#wrote, iclass 28, count 2 2006.211.08:02:38.26#ibcon#about to read 3, iclass 28, count 2 2006.211.08:02:38.28#ibcon#read 3, iclass 28, count 2 2006.211.08:02:38.28#ibcon#about to read 4, iclass 28, count 2 2006.211.08:02:38.28#ibcon#read 4, iclass 28, count 2 2006.211.08:02:38.28#ibcon#about to read 5, iclass 28, count 2 2006.211.08:02:38.28#ibcon#read 5, iclass 28, count 2 2006.211.08:02:38.28#ibcon#about to read 6, iclass 28, count 2 2006.211.08:02:38.28#ibcon#read 6, iclass 28, count 2 2006.211.08:02:38.28#ibcon#end of sib2, iclass 28, count 2 2006.211.08:02:38.28#ibcon#*after write, iclass 28, count 2 2006.211.08:02:38.29#ibcon#*before return 0, iclass 28, count 2 2006.211.08:02:38.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:02:38.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:02:38.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:02:38.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:38.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:02:38.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:02:38.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:02:38.40#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:02:38.40#ibcon#first serial, iclass 28, count 0 2006.211.08:02:38.40#ibcon#enter sib2, iclass 28, count 0 2006.211.08:02:38.40#ibcon#flushed, iclass 28, count 0 2006.211.08:02:38.40#ibcon#about to write, iclass 28, count 0 2006.211.08:02:38.40#ibcon#wrote, iclass 28, count 0 2006.211.08:02:38.40#ibcon#about to read 3, iclass 28, count 0 2006.211.08:02:38.42#ibcon#read 3, iclass 28, count 0 2006.211.08:02:38.42#ibcon#about to read 4, iclass 28, count 0 2006.211.08:02:38.42#ibcon#read 4, iclass 28, count 0 2006.211.08:02:38.42#ibcon#about to read 5, iclass 28, count 0 2006.211.08:02:38.42#ibcon#read 5, iclass 28, count 0 2006.211.08:02:38.42#ibcon#about to read 6, iclass 28, count 0 2006.211.08:02:38.42#ibcon#read 6, iclass 28, count 0 2006.211.08:02:38.42#ibcon#end of sib2, iclass 28, count 0 2006.211.08:02:38.42#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:02:38.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:02:38.43#ibcon#[25=USB\r\n] 2006.211.08:02:38.43#ibcon#*before write, iclass 28, count 0 2006.211.08:02:38.43#ibcon#enter sib2, iclass 28, count 0 2006.211.08:02:38.43#ibcon#flushed, iclass 28, count 0 2006.211.08:02:38.43#ibcon#about to write, iclass 28, count 0 2006.211.08:02:38.43#ibcon#wrote, iclass 28, count 0 2006.211.08:02:38.43#ibcon#about to read 3, iclass 28, count 0 2006.211.08:02:38.45#ibcon#read 3, iclass 28, count 0 2006.211.08:02:38.45#ibcon#about to read 4, iclass 28, count 0 2006.211.08:02:38.45#ibcon#read 4, iclass 28, count 0 2006.211.08:02:38.45#ibcon#about to read 5, iclass 28, count 0 2006.211.08:02:38.45#ibcon#read 5, iclass 28, count 0 2006.211.08:02:38.45#ibcon#about to read 6, iclass 28, count 0 2006.211.08:02:38.45#ibcon#read 6, iclass 28, count 0 2006.211.08:02:38.45#ibcon#end of sib2, iclass 28, count 0 2006.211.08:02:38.45#ibcon#*after write, iclass 28, count 0 2006.211.08:02:38.45#ibcon#*before return 0, iclass 28, count 0 2006.211.08:02:38.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:02:38.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:02:38.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:02:38.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:02:38.46$vc4f8/valo=4,832.99 2006.211.08:02:38.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:02:38.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:02:38.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:38.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:38.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:38.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:38.46#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:02:38.46#ibcon#first serial, iclass 30, count 0 2006.211.08:02:38.46#ibcon#enter sib2, iclass 30, count 0 2006.211.08:02:38.46#ibcon#flushed, iclass 30, count 0 2006.211.08:02:38.46#ibcon#about to write, iclass 30, count 0 2006.211.08:02:38.46#ibcon#wrote, iclass 30, count 0 2006.211.08:02:38.46#ibcon#about to read 3, iclass 30, count 0 2006.211.08:02:38.47#ibcon#read 3, iclass 30, count 0 2006.211.08:02:38.47#ibcon#about to read 4, iclass 30, count 0 2006.211.08:02:38.47#ibcon#read 4, iclass 30, count 0 2006.211.08:02:38.47#ibcon#about to read 5, iclass 30, count 0 2006.211.08:02:38.47#ibcon#read 5, iclass 30, count 0 2006.211.08:02:38.47#ibcon#about to read 6, iclass 30, count 0 2006.211.08:02:38.47#ibcon#read 6, iclass 30, count 0 2006.211.08:02:38.47#ibcon#end of sib2, iclass 30, count 0 2006.211.08:02:38.47#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:02:38.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:02:38.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:02:38.48#ibcon#*before write, iclass 30, count 0 2006.211.08:02:38.48#ibcon#enter sib2, iclass 30, count 0 2006.211.08:02:38.48#ibcon#flushed, iclass 30, count 0 2006.211.08:02:38.48#ibcon#about to write, iclass 30, count 0 2006.211.08:02:38.48#ibcon#wrote, iclass 30, count 0 2006.211.08:02:38.48#ibcon#about to read 3, iclass 30, count 0 2006.211.08:02:38.51#ibcon#read 3, iclass 30, count 0 2006.211.08:02:38.51#ibcon#about to read 4, iclass 30, count 0 2006.211.08:02:38.51#ibcon#read 4, iclass 30, count 0 2006.211.08:02:38.51#ibcon#about to read 5, iclass 30, count 0 2006.211.08:02:38.51#ibcon#read 5, iclass 30, count 0 2006.211.08:02:38.51#ibcon#about to read 6, iclass 30, count 0 2006.211.08:02:38.51#ibcon#read 6, iclass 30, count 0 2006.211.08:02:38.51#ibcon#end of sib2, iclass 30, count 0 2006.211.08:02:38.51#ibcon#*after write, iclass 30, count 0 2006.211.08:02:38.52#ibcon#*before return 0, iclass 30, count 0 2006.211.08:02:38.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:38.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:38.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:02:38.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:02:38.52$vc4f8/va=4,7 2006.211.08:02:38.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:02:38.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:02:38.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:38.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:38.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:38.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:38.57#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:02:38.57#ibcon#first serial, iclass 32, count 2 2006.211.08:02:38.57#ibcon#enter sib2, iclass 32, count 2 2006.211.08:02:38.57#ibcon#flushed, iclass 32, count 2 2006.211.08:02:38.57#ibcon#about to write, iclass 32, count 2 2006.211.08:02:38.57#ibcon#wrote, iclass 32, count 2 2006.211.08:02:38.57#ibcon#about to read 3, iclass 32, count 2 2006.211.08:02:38.59#ibcon#read 3, iclass 32, count 2 2006.211.08:02:38.59#ibcon#about to read 4, iclass 32, count 2 2006.211.08:02:38.59#ibcon#read 4, iclass 32, count 2 2006.211.08:02:38.59#ibcon#about to read 5, iclass 32, count 2 2006.211.08:02:38.59#ibcon#read 5, iclass 32, count 2 2006.211.08:02:38.59#ibcon#about to read 6, iclass 32, count 2 2006.211.08:02:38.59#ibcon#read 6, iclass 32, count 2 2006.211.08:02:38.59#ibcon#end of sib2, iclass 32, count 2 2006.211.08:02:38.59#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:02:38.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:02:38.60#ibcon#[25=AT04-07\r\n] 2006.211.08:02:38.60#ibcon#*before write, iclass 32, count 2 2006.211.08:02:38.60#ibcon#enter sib2, iclass 32, count 2 2006.211.08:02:38.60#ibcon#flushed, iclass 32, count 2 2006.211.08:02:38.60#ibcon#about to write, iclass 32, count 2 2006.211.08:02:38.60#ibcon#wrote, iclass 32, count 2 2006.211.08:02:38.60#ibcon#about to read 3, iclass 32, count 2 2006.211.08:02:38.62#ibcon#read 3, iclass 32, count 2 2006.211.08:02:38.62#ibcon#about to read 4, iclass 32, count 2 2006.211.08:02:38.62#ibcon#read 4, iclass 32, count 2 2006.211.08:02:38.62#ibcon#about to read 5, iclass 32, count 2 2006.211.08:02:38.62#ibcon#read 5, iclass 32, count 2 2006.211.08:02:38.62#ibcon#about to read 6, iclass 32, count 2 2006.211.08:02:38.62#ibcon#read 6, iclass 32, count 2 2006.211.08:02:38.62#ibcon#end of sib2, iclass 32, count 2 2006.211.08:02:38.62#ibcon#*after write, iclass 32, count 2 2006.211.08:02:38.62#ibcon#*before return 0, iclass 32, count 2 2006.211.08:02:38.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:38.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:38.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:02:38.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:38.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:38.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:38.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:38.74#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:02:38.74#ibcon#first serial, iclass 32, count 0 2006.211.08:02:38.74#ibcon#enter sib2, iclass 32, count 0 2006.211.08:02:38.74#ibcon#flushed, iclass 32, count 0 2006.211.08:02:38.74#ibcon#about to write, iclass 32, count 0 2006.211.08:02:38.74#ibcon#wrote, iclass 32, count 0 2006.211.08:02:38.74#ibcon#about to read 3, iclass 32, count 0 2006.211.08:02:38.76#ibcon#read 3, iclass 32, count 0 2006.211.08:02:38.76#ibcon#about to read 4, iclass 32, count 0 2006.211.08:02:38.76#ibcon#read 4, iclass 32, count 0 2006.211.08:02:38.76#ibcon#about to read 5, iclass 32, count 0 2006.211.08:02:38.76#ibcon#read 5, iclass 32, count 0 2006.211.08:02:38.76#ibcon#about to read 6, iclass 32, count 0 2006.211.08:02:38.76#ibcon#read 6, iclass 32, count 0 2006.211.08:02:38.76#ibcon#end of sib2, iclass 32, count 0 2006.211.08:02:38.76#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:02:38.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:02:38.77#ibcon#[25=USB\r\n] 2006.211.08:02:38.77#ibcon#*before write, iclass 32, count 0 2006.211.08:02:38.77#ibcon#enter sib2, iclass 32, count 0 2006.211.08:02:38.77#ibcon#flushed, iclass 32, count 0 2006.211.08:02:38.77#ibcon#about to write, iclass 32, count 0 2006.211.08:02:38.77#ibcon#wrote, iclass 32, count 0 2006.211.08:02:38.77#ibcon#about to read 3, iclass 32, count 0 2006.211.08:02:38.79#ibcon#read 3, iclass 32, count 0 2006.211.08:02:38.79#ibcon#about to read 4, iclass 32, count 0 2006.211.08:02:38.79#ibcon#read 4, iclass 32, count 0 2006.211.08:02:38.79#ibcon#about to read 5, iclass 32, count 0 2006.211.08:02:38.79#ibcon#read 5, iclass 32, count 0 2006.211.08:02:38.79#ibcon#about to read 6, iclass 32, count 0 2006.211.08:02:38.79#ibcon#read 6, iclass 32, count 0 2006.211.08:02:38.79#ibcon#end of sib2, iclass 32, count 0 2006.211.08:02:38.79#ibcon#*after write, iclass 32, count 0 2006.211.08:02:38.79#ibcon#*before return 0, iclass 32, count 0 2006.211.08:02:38.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:38.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:38.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:02:38.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:02:38.80$vc4f8/valo=5,652.99 2006.211.08:02:38.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:02:38.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:02:38.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:38.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:38.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:38.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:38.80#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:02:38.80#ibcon#first serial, iclass 34, count 0 2006.211.08:02:38.80#ibcon#enter sib2, iclass 34, count 0 2006.211.08:02:38.80#ibcon#flushed, iclass 34, count 0 2006.211.08:02:38.80#ibcon#about to write, iclass 34, count 0 2006.211.08:02:38.80#ibcon#wrote, iclass 34, count 0 2006.211.08:02:38.80#ibcon#about to read 3, iclass 34, count 0 2006.211.08:02:38.81#ibcon#read 3, iclass 34, count 0 2006.211.08:02:38.81#ibcon#about to read 4, iclass 34, count 0 2006.211.08:02:38.81#ibcon#read 4, iclass 34, count 0 2006.211.08:02:38.81#ibcon#about to read 5, iclass 34, count 0 2006.211.08:02:38.81#ibcon#read 5, iclass 34, count 0 2006.211.08:02:38.81#ibcon#about to read 6, iclass 34, count 0 2006.211.08:02:38.81#ibcon#read 6, iclass 34, count 0 2006.211.08:02:38.81#ibcon#end of sib2, iclass 34, count 0 2006.211.08:02:38.81#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:02:38.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:02:38.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:02:38.82#ibcon#*before write, iclass 34, count 0 2006.211.08:02:38.82#ibcon#enter sib2, iclass 34, count 0 2006.211.08:02:38.82#ibcon#flushed, iclass 34, count 0 2006.211.08:02:38.82#ibcon#about to write, iclass 34, count 0 2006.211.08:02:38.82#ibcon#wrote, iclass 34, count 0 2006.211.08:02:38.82#ibcon#about to read 3, iclass 34, count 0 2006.211.08:02:38.85#ibcon#read 3, iclass 34, count 0 2006.211.08:02:38.85#ibcon#about to read 4, iclass 34, count 0 2006.211.08:02:38.85#ibcon#read 4, iclass 34, count 0 2006.211.08:02:38.85#ibcon#about to read 5, iclass 34, count 0 2006.211.08:02:38.85#ibcon#read 5, iclass 34, count 0 2006.211.08:02:38.85#ibcon#about to read 6, iclass 34, count 0 2006.211.08:02:38.85#ibcon#read 6, iclass 34, count 0 2006.211.08:02:38.85#ibcon#end of sib2, iclass 34, count 0 2006.211.08:02:38.85#ibcon#*after write, iclass 34, count 0 2006.211.08:02:38.85#ibcon#*before return 0, iclass 34, count 0 2006.211.08:02:38.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:38.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:38.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:02:38.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:02:38.86$vc4f8/va=5,7 2006.211.08:02:38.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:02:38.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:02:38.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:38.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:38.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:38.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:38.91#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:02:38.91#ibcon#first serial, iclass 36, count 2 2006.211.08:02:38.91#ibcon#enter sib2, iclass 36, count 2 2006.211.08:02:38.91#ibcon#flushed, iclass 36, count 2 2006.211.08:02:38.91#ibcon#about to write, iclass 36, count 2 2006.211.08:02:38.91#ibcon#wrote, iclass 36, count 2 2006.211.08:02:38.91#ibcon#about to read 3, iclass 36, count 2 2006.211.08:02:38.93#ibcon#read 3, iclass 36, count 2 2006.211.08:02:38.93#ibcon#about to read 4, iclass 36, count 2 2006.211.08:02:38.93#ibcon#read 4, iclass 36, count 2 2006.211.08:02:38.93#ibcon#about to read 5, iclass 36, count 2 2006.211.08:02:38.93#ibcon#read 5, iclass 36, count 2 2006.211.08:02:38.93#ibcon#about to read 6, iclass 36, count 2 2006.211.08:02:38.93#ibcon#read 6, iclass 36, count 2 2006.211.08:02:38.93#ibcon#end of sib2, iclass 36, count 2 2006.211.08:02:38.93#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:02:38.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:02:38.94#ibcon#[25=AT05-07\r\n] 2006.211.08:02:38.94#ibcon#*before write, iclass 36, count 2 2006.211.08:02:38.94#ibcon#enter sib2, iclass 36, count 2 2006.211.08:02:38.94#ibcon#flushed, iclass 36, count 2 2006.211.08:02:38.94#ibcon#about to write, iclass 36, count 2 2006.211.08:02:38.94#ibcon#wrote, iclass 36, count 2 2006.211.08:02:38.94#ibcon#about to read 3, iclass 36, count 2 2006.211.08:02:38.96#ibcon#read 3, iclass 36, count 2 2006.211.08:02:38.96#ibcon#about to read 4, iclass 36, count 2 2006.211.08:02:38.96#ibcon#read 4, iclass 36, count 2 2006.211.08:02:38.96#ibcon#about to read 5, iclass 36, count 2 2006.211.08:02:38.96#ibcon#read 5, iclass 36, count 2 2006.211.08:02:38.96#ibcon#about to read 6, iclass 36, count 2 2006.211.08:02:38.96#ibcon#read 6, iclass 36, count 2 2006.211.08:02:38.96#ibcon#end of sib2, iclass 36, count 2 2006.211.08:02:38.96#ibcon#*after write, iclass 36, count 2 2006.211.08:02:38.96#ibcon#*before return 0, iclass 36, count 2 2006.211.08:02:38.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:38.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:38.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:02:38.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:38.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:39.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:39.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:39.08#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:02:39.08#ibcon#first serial, iclass 36, count 0 2006.211.08:02:39.08#ibcon#enter sib2, iclass 36, count 0 2006.211.08:02:39.08#ibcon#flushed, iclass 36, count 0 2006.211.08:02:39.08#ibcon#about to write, iclass 36, count 0 2006.211.08:02:39.08#ibcon#wrote, iclass 36, count 0 2006.211.08:02:39.08#ibcon#about to read 3, iclass 36, count 0 2006.211.08:02:39.10#ibcon#read 3, iclass 36, count 0 2006.211.08:02:39.10#ibcon#about to read 4, iclass 36, count 0 2006.211.08:02:39.10#ibcon#read 4, iclass 36, count 0 2006.211.08:02:39.10#ibcon#about to read 5, iclass 36, count 0 2006.211.08:02:39.10#ibcon#read 5, iclass 36, count 0 2006.211.08:02:39.10#ibcon#about to read 6, iclass 36, count 0 2006.211.08:02:39.10#ibcon#read 6, iclass 36, count 0 2006.211.08:02:39.10#ibcon#end of sib2, iclass 36, count 0 2006.211.08:02:39.10#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:02:39.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:02:39.11#ibcon#[25=USB\r\n] 2006.211.08:02:39.11#ibcon#*before write, iclass 36, count 0 2006.211.08:02:39.11#ibcon#enter sib2, iclass 36, count 0 2006.211.08:02:39.11#ibcon#flushed, iclass 36, count 0 2006.211.08:02:39.11#ibcon#about to write, iclass 36, count 0 2006.211.08:02:39.11#ibcon#wrote, iclass 36, count 0 2006.211.08:02:39.11#ibcon#about to read 3, iclass 36, count 0 2006.211.08:02:39.13#ibcon#read 3, iclass 36, count 0 2006.211.08:02:39.13#ibcon#about to read 4, iclass 36, count 0 2006.211.08:02:39.13#ibcon#read 4, iclass 36, count 0 2006.211.08:02:39.13#ibcon#about to read 5, iclass 36, count 0 2006.211.08:02:39.13#ibcon#read 5, iclass 36, count 0 2006.211.08:02:39.13#ibcon#about to read 6, iclass 36, count 0 2006.211.08:02:39.13#ibcon#read 6, iclass 36, count 0 2006.211.08:02:39.13#ibcon#end of sib2, iclass 36, count 0 2006.211.08:02:39.13#ibcon#*after write, iclass 36, count 0 2006.211.08:02:39.13#ibcon#*before return 0, iclass 36, count 0 2006.211.08:02:39.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:39.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:39.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:02:39.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:02:39.14$vc4f8/valo=6,772.99 2006.211.08:02:39.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:02:39.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:02:39.14#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:39.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:39.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:39.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:39.14#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:02:39.14#ibcon#first serial, iclass 38, count 0 2006.211.08:02:39.14#ibcon#enter sib2, iclass 38, count 0 2006.211.08:02:39.14#ibcon#flushed, iclass 38, count 0 2006.211.08:02:39.14#ibcon#about to write, iclass 38, count 0 2006.211.08:02:39.14#ibcon#wrote, iclass 38, count 0 2006.211.08:02:39.14#ibcon#about to read 3, iclass 38, count 0 2006.211.08:02:39.15#ibcon#read 3, iclass 38, count 0 2006.211.08:02:39.15#ibcon#about to read 4, iclass 38, count 0 2006.211.08:02:39.15#ibcon#read 4, iclass 38, count 0 2006.211.08:02:39.15#ibcon#about to read 5, iclass 38, count 0 2006.211.08:02:39.15#ibcon#read 5, iclass 38, count 0 2006.211.08:02:39.15#ibcon#about to read 6, iclass 38, count 0 2006.211.08:02:39.15#ibcon#read 6, iclass 38, count 0 2006.211.08:02:39.15#ibcon#end of sib2, iclass 38, count 0 2006.211.08:02:39.15#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:02:39.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:02:39.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:02:39.16#ibcon#*before write, iclass 38, count 0 2006.211.08:02:39.16#ibcon#enter sib2, iclass 38, count 0 2006.211.08:02:39.16#ibcon#flushed, iclass 38, count 0 2006.211.08:02:39.16#ibcon#about to write, iclass 38, count 0 2006.211.08:02:39.16#ibcon#wrote, iclass 38, count 0 2006.211.08:02:39.16#ibcon#about to read 3, iclass 38, count 0 2006.211.08:02:39.19#ibcon#read 3, iclass 38, count 0 2006.211.08:02:39.19#ibcon#about to read 4, iclass 38, count 0 2006.211.08:02:39.19#ibcon#read 4, iclass 38, count 0 2006.211.08:02:39.19#ibcon#about to read 5, iclass 38, count 0 2006.211.08:02:39.19#ibcon#read 5, iclass 38, count 0 2006.211.08:02:39.19#ibcon#about to read 6, iclass 38, count 0 2006.211.08:02:39.19#ibcon#read 6, iclass 38, count 0 2006.211.08:02:39.19#ibcon#end of sib2, iclass 38, count 0 2006.211.08:02:39.19#ibcon#*after write, iclass 38, count 0 2006.211.08:02:39.19#ibcon#*before return 0, iclass 38, count 0 2006.211.08:02:39.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:39.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:39.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:02:39.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:02:39.20$vc4f8/va=6,6 2006.211.08:02:39.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:02:39.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:02:39.20#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:39.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:39.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:39.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:39.25#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:02:39.25#ibcon#first serial, iclass 40, count 2 2006.211.08:02:39.25#ibcon#enter sib2, iclass 40, count 2 2006.211.08:02:39.25#ibcon#flushed, iclass 40, count 2 2006.211.08:02:39.25#ibcon#about to write, iclass 40, count 2 2006.211.08:02:39.25#ibcon#wrote, iclass 40, count 2 2006.211.08:02:39.25#ibcon#about to read 3, iclass 40, count 2 2006.211.08:02:39.27#ibcon#read 3, iclass 40, count 2 2006.211.08:02:39.27#ibcon#about to read 4, iclass 40, count 2 2006.211.08:02:39.27#ibcon#read 4, iclass 40, count 2 2006.211.08:02:39.27#ibcon#about to read 5, iclass 40, count 2 2006.211.08:02:39.27#ibcon#read 5, iclass 40, count 2 2006.211.08:02:39.27#ibcon#about to read 6, iclass 40, count 2 2006.211.08:02:39.27#ibcon#read 6, iclass 40, count 2 2006.211.08:02:39.27#ibcon#end of sib2, iclass 40, count 2 2006.211.08:02:39.27#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:02:39.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:02:39.28#ibcon#[25=AT06-06\r\n] 2006.211.08:02:39.28#ibcon#*before write, iclass 40, count 2 2006.211.08:02:39.28#ibcon#enter sib2, iclass 40, count 2 2006.211.08:02:39.28#ibcon#flushed, iclass 40, count 2 2006.211.08:02:39.28#ibcon#about to write, iclass 40, count 2 2006.211.08:02:39.28#ibcon#wrote, iclass 40, count 2 2006.211.08:02:39.28#ibcon#about to read 3, iclass 40, count 2 2006.211.08:02:39.30#ibcon#read 3, iclass 40, count 2 2006.211.08:02:39.30#ibcon#about to read 4, iclass 40, count 2 2006.211.08:02:39.30#ibcon#read 4, iclass 40, count 2 2006.211.08:02:39.30#ibcon#about to read 5, iclass 40, count 2 2006.211.08:02:39.30#ibcon#read 5, iclass 40, count 2 2006.211.08:02:39.30#ibcon#about to read 6, iclass 40, count 2 2006.211.08:02:39.30#ibcon#read 6, iclass 40, count 2 2006.211.08:02:39.30#ibcon#end of sib2, iclass 40, count 2 2006.211.08:02:39.30#ibcon#*after write, iclass 40, count 2 2006.211.08:02:39.30#ibcon#*before return 0, iclass 40, count 2 2006.211.08:02:39.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:39.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:39.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:02:39.31#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:39.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:39.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:39.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:39.43#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:02:39.43#ibcon#first serial, iclass 40, count 0 2006.211.08:02:39.43#ibcon#enter sib2, iclass 40, count 0 2006.211.08:02:39.43#ibcon#flushed, iclass 40, count 0 2006.211.08:02:39.43#ibcon#about to write, iclass 40, count 0 2006.211.08:02:39.43#ibcon#wrote, iclass 40, count 0 2006.211.08:02:39.43#ibcon#about to read 3, iclass 40, count 0 2006.211.08:02:39.44#ibcon#read 3, iclass 40, count 0 2006.211.08:02:39.44#ibcon#about to read 4, iclass 40, count 0 2006.211.08:02:39.44#ibcon#read 4, iclass 40, count 0 2006.211.08:02:39.44#ibcon#about to read 5, iclass 40, count 0 2006.211.08:02:39.44#ibcon#read 5, iclass 40, count 0 2006.211.08:02:39.44#ibcon#about to read 6, iclass 40, count 0 2006.211.08:02:39.44#ibcon#read 6, iclass 40, count 0 2006.211.08:02:39.44#ibcon#end of sib2, iclass 40, count 0 2006.211.08:02:39.44#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:02:39.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:02:39.45#ibcon#[25=USB\r\n] 2006.211.08:02:39.45#ibcon#*before write, iclass 40, count 0 2006.211.08:02:39.45#ibcon#enter sib2, iclass 40, count 0 2006.211.08:02:39.45#ibcon#flushed, iclass 40, count 0 2006.211.08:02:39.45#ibcon#about to write, iclass 40, count 0 2006.211.08:02:39.45#ibcon#wrote, iclass 40, count 0 2006.211.08:02:39.45#ibcon#about to read 3, iclass 40, count 0 2006.211.08:02:39.47#ibcon#read 3, iclass 40, count 0 2006.211.08:02:39.47#ibcon#about to read 4, iclass 40, count 0 2006.211.08:02:39.47#ibcon#read 4, iclass 40, count 0 2006.211.08:02:39.47#ibcon#about to read 5, iclass 40, count 0 2006.211.08:02:39.47#ibcon#read 5, iclass 40, count 0 2006.211.08:02:39.47#ibcon#about to read 6, iclass 40, count 0 2006.211.08:02:39.47#ibcon#read 6, iclass 40, count 0 2006.211.08:02:39.47#ibcon#end of sib2, iclass 40, count 0 2006.211.08:02:39.47#ibcon#*after write, iclass 40, count 0 2006.211.08:02:39.47#ibcon#*before return 0, iclass 40, count 0 2006.211.08:02:39.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:39.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:39.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:02:39.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:02:39.48$vc4f8/valo=7,832.99 2006.211.08:02:39.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:02:39.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:02:39.48#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:39.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:39.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:39.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:39.48#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:02:39.48#ibcon#first serial, iclass 4, count 0 2006.211.08:02:39.48#ibcon#enter sib2, iclass 4, count 0 2006.211.08:02:39.48#ibcon#flushed, iclass 4, count 0 2006.211.08:02:39.48#ibcon#about to write, iclass 4, count 0 2006.211.08:02:39.48#ibcon#wrote, iclass 4, count 0 2006.211.08:02:39.48#ibcon#about to read 3, iclass 4, count 0 2006.211.08:02:39.49#ibcon#read 3, iclass 4, count 0 2006.211.08:02:39.49#ibcon#about to read 4, iclass 4, count 0 2006.211.08:02:39.49#ibcon#read 4, iclass 4, count 0 2006.211.08:02:39.49#ibcon#about to read 5, iclass 4, count 0 2006.211.08:02:39.49#ibcon#read 5, iclass 4, count 0 2006.211.08:02:39.49#ibcon#about to read 6, iclass 4, count 0 2006.211.08:02:39.49#ibcon#read 6, iclass 4, count 0 2006.211.08:02:39.49#ibcon#end of sib2, iclass 4, count 0 2006.211.08:02:39.49#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:02:39.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:02:39.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:02:39.50#ibcon#*before write, iclass 4, count 0 2006.211.08:02:39.50#ibcon#enter sib2, iclass 4, count 0 2006.211.08:02:39.50#ibcon#flushed, iclass 4, count 0 2006.211.08:02:39.50#ibcon#about to write, iclass 4, count 0 2006.211.08:02:39.50#ibcon#wrote, iclass 4, count 0 2006.211.08:02:39.50#ibcon#about to read 3, iclass 4, count 0 2006.211.08:02:39.53#ibcon#read 3, iclass 4, count 0 2006.211.08:02:39.53#ibcon#about to read 4, iclass 4, count 0 2006.211.08:02:39.53#ibcon#read 4, iclass 4, count 0 2006.211.08:02:39.53#ibcon#about to read 5, iclass 4, count 0 2006.211.08:02:39.53#ibcon#read 5, iclass 4, count 0 2006.211.08:02:39.53#ibcon#about to read 6, iclass 4, count 0 2006.211.08:02:39.53#ibcon#read 6, iclass 4, count 0 2006.211.08:02:39.53#ibcon#end of sib2, iclass 4, count 0 2006.211.08:02:39.53#ibcon#*after write, iclass 4, count 0 2006.211.08:02:39.53#ibcon#*before return 0, iclass 4, count 0 2006.211.08:02:39.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:39.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:39.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:02:39.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:02:39.54$vc4f8/va=7,6 2006.211.08:02:39.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:02:39.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:02:39.54#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:39.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:02:39.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:02:39.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:02:39.59#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:02:39.59#ibcon#first serial, iclass 6, count 2 2006.211.08:02:39.59#ibcon#enter sib2, iclass 6, count 2 2006.211.08:02:39.59#ibcon#flushed, iclass 6, count 2 2006.211.08:02:39.59#ibcon#about to write, iclass 6, count 2 2006.211.08:02:39.59#ibcon#wrote, iclass 6, count 2 2006.211.08:02:39.59#ibcon#about to read 3, iclass 6, count 2 2006.211.08:02:39.61#ibcon#read 3, iclass 6, count 2 2006.211.08:02:39.61#ibcon#about to read 4, iclass 6, count 2 2006.211.08:02:39.61#ibcon#read 4, iclass 6, count 2 2006.211.08:02:39.61#ibcon#about to read 5, iclass 6, count 2 2006.211.08:02:39.61#ibcon#read 5, iclass 6, count 2 2006.211.08:02:39.61#ibcon#about to read 6, iclass 6, count 2 2006.211.08:02:39.61#ibcon#read 6, iclass 6, count 2 2006.211.08:02:39.61#ibcon#end of sib2, iclass 6, count 2 2006.211.08:02:39.61#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:02:39.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:02:39.62#ibcon#[25=AT07-06\r\n] 2006.211.08:02:39.62#ibcon#*before write, iclass 6, count 2 2006.211.08:02:39.62#ibcon#enter sib2, iclass 6, count 2 2006.211.08:02:39.62#ibcon#flushed, iclass 6, count 2 2006.211.08:02:39.62#ibcon#about to write, iclass 6, count 2 2006.211.08:02:39.62#ibcon#wrote, iclass 6, count 2 2006.211.08:02:39.62#ibcon#about to read 3, iclass 6, count 2 2006.211.08:02:39.64#ibcon#read 3, iclass 6, count 2 2006.211.08:02:39.64#ibcon#about to read 4, iclass 6, count 2 2006.211.08:02:39.64#ibcon#read 4, iclass 6, count 2 2006.211.08:02:39.64#ibcon#about to read 5, iclass 6, count 2 2006.211.08:02:39.64#ibcon#read 5, iclass 6, count 2 2006.211.08:02:39.64#ibcon#about to read 6, iclass 6, count 2 2006.211.08:02:39.64#ibcon#read 6, iclass 6, count 2 2006.211.08:02:39.64#ibcon#end of sib2, iclass 6, count 2 2006.211.08:02:39.64#ibcon#*after write, iclass 6, count 2 2006.211.08:02:39.64#ibcon#*before return 0, iclass 6, count 2 2006.211.08:02:39.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:02:39.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:02:39.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:02:39.65#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:39.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:02:39.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:02:39.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:02:39.76#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:02:39.76#ibcon#first serial, iclass 6, count 0 2006.211.08:02:39.76#ibcon#enter sib2, iclass 6, count 0 2006.211.08:02:39.76#ibcon#flushed, iclass 6, count 0 2006.211.08:02:39.76#ibcon#about to write, iclass 6, count 0 2006.211.08:02:39.76#ibcon#wrote, iclass 6, count 0 2006.211.08:02:39.76#ibcon#about to read 3, iclass 6, count 0 2006.211.08:02:39.78#ibcon#read 3, iclass 6, count 0 2006.211.08:02:39.78#ibcon#about to read 4, iclass 6, count 0 2006.211.08:02:39.78#ibcon#read 4, iclass 6, count 0 2006.211.08:02:39.78#ibcon#about to read 5, iclass 6, count 0 2006.211.08:02:39.78#ibcon#read 5, iclass 6, count 0 2006.211.08:02:39.78#ibcon#about to read 6, iclass 6, count 0 2006.211.08:02:39.78#ibcon#read 6, iclass 6, count 0 2006.211.08:02:39.78#ibcon#end of sib2, iclass 6, count 0 2006.211.08:02:39.78#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:02:39.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:02:39.79#ibcon#[25=USB\r\n] 2006.211.08:02:39.79#ibcon#*before write, iclass 6, count 0 2006.211.08:02:39.79#ibcon#enter sib2, iclass 6, count 0 2006.211.08:02:39.79#ibcon#flushed, iclass 6, count 0 2006.211.08:02:39.79#ibcon#about to write, iclass 6, count 0 2006.211.08:02:39.79#ibcon#wrote, iclass 6, count 0 2006.211.08:02:39.79#ibcon#about to read 3, iclass 6, count 0 2006.211.08:02:39.81#ibcon#read 3, iclass 6, count 0 2006.211.08:02:39.81#ibcon#about to read 4, iclass 6, count 0 2006.211.08:02:39.81#ibcon#read 4, iclass 6, count 0 2006.211.08:02:39.81#ibcon#about to read 5, iclass 6, count 0 2006.211.08:02:39.81#ibcon#read 5, iclass 6, count 0 2006.211.08:02:39.81#ibcon#about to read 6, iclass 6, count 0 2006.211.08:02:39.81#ibcon#read 6, iclass 6, count 0 2006.211.08:02:39.81#ibcon#end of sib2, iclass 6, count 0 2006.211.08:02:39.81#ibcon#*after write, iclass 6, count 0 2006.211.08:02:39.81#ibcon#*before return 0, iclass 6, count 0 2006.211.08:02:39.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:02:39.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:02:39.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:02:39.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:02:39.82$vc4f8/valo=8,852.99 2006.211.08:02:39.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:02:39.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:02:39.82#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:39.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:02:39.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:02:39.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:02:39.82#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:02:39.82#ibcon#first serial, iclass 10, count 0 2006.211.08:02:39.82#ibcon#enter sib2, iclass 10, count 0 2006.211.08:02:39.82#ibcon#flushed, iclass 10, count 0 2006.211.08:02:39.82#ibcon#about to write, iclass 10, count 0 2006.211.08:02:39.82#ibcon#wrote, iclass 10, count 0 2006.211.08:02:39.82#ibcon#about to read 3, iclass 10, count 0 2006.211.08:02:39.83#ibcon#read 3, iclass 10, count 0 2006.211.08:02:39.83#ibcon#about to read 4, iclass 10, count 0 2006.211.08:02:39.83#ibcon#read 4, iclass 10, count 0 2006.211.08:02:39.83#ibcon#about to read 5, iclass 10, count 0 2006.211.08:02:39.83#ibcon#read 5, iclass 10, count 0 2006.211.08:02:39.83#ibcon#about to read 6, iclass 10, count 0 2006.211.08:02:39.83#ibcon#read 6, iclass 10, count 0 2006.211.08:02:39.83#ibcon#end of sib2, iclass 10, count 0 2006.211.08:02:39.83#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:02:39.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:02:39.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:02:39.84#ibcon#*before write, iclass 10, count 0 2006.211.08:02:39.84#ibcon#enter sib2, iclass 10, count 0 2006.211.08:02:39.84#ibcon#flushed, iclass 10, count 0 2006.211.08:02:39.84#ibcon#about to write, iclass 10, count 0 2006.211.08:02:39.84#ibcon#wrote, iclass 10, count 0 2006.211.08:02:39.84#ibcon#about to read 3, iclass 10, count 0 2006.211.08:02:39.87#ibcon#read 3, iclass 10, count 0 2006.211.08:02:39.87#ibcon#about to read 4, iclass 10, count 0 2006.211.08:02:39.87#ibcon#read 4, iclass 10, count 0 2006.211.08:02:39.87#ibcon#about to read 5, iclass 10, count 0 2006.211.08:02:39.87#ibcon#read 5, iclass 10, count 0 2006.211.08:02:39.87#ibcon#about to read 6, iclass 10, count 0 2006.211.08:02:39.87#ibcon#read 6, iclass 10, count 0 2006.211.08:02:39.87#ibcon#end of sib2, iclass 10, count 0 2006.211.08:02:39.87#ibcon#*after write, iclass 10, count 0 2006.211.08:02:39.87#ibcon#*before return 0, iclass 10, count 0 2006.211.08:02:39.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:02:39.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:02:39.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:02:39.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:02:39.88$vc4f8/va=8,7 2006.211.08:02:39.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:02:39.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:02:39.88#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:39.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:02:39.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:02:39.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:02:39.93#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:02:39.93#ibcon#first serial, iclass 12, count 2 2006.211.08:02:39.93#ibcon#enter sib2, iclass 12, count 2 2006.211.08:02:39.93#ibcon#flushed, iclass 12, count 2 2006.211.08:02:39.93#ibcon#about to write, iclass 12, count 2 2006.211.08:02:39.93#ibcon#wrote, iclass 12, count 2 2006.211.08:02:39.93#ibcon#about to read 3, iclass 12, count 2 2006.211.08:02:39.95#ibcon#read 3, iclass 12, count 2 2006.211.08:02:39.95#ibcon#about to read 4, iclass 12, count 2 2006.211.08:02:39.95#ibcon#read 4, iclass 12, count 2 2006.211.08:02:39.95#ibcon#about to read 5, iclass 12, count 2 2006.211.08:02:39.95#ibcon#read 5, iclass 12, count 2 2006.211.08:02:39.95#ibcon#about to read 6, iclass 12, count 2 2006.211.08:02:39.95#ibcon#read 6, iclass 12, count 2 2006.211.08:02:39.95#ibcon#end of sib2, iclass 12, count 2 2006.211.08:02:39.95#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:02:39.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:02:39.96#ibcon#[25=AT08-07\r\n] 2006.211.08:02:39.96#ibcon#*before write, iclass 12, count 2 2006.211.08:02:39.96#ibcon#enter sib2, iclass 12, count 2 2006.211.08:02:39.96#ibcon#flushed, iclass 12, count 2 2006.211.08:02:39.96#ibcon#about to write, iclass 12, count 2 2006.211.08:02:39.96#ibcon#wrote, iclass 12, count 2 2006.211.08:02:39.96#ibcon#about to read 3, iclass 12, count 2 2006.211.08:02:39.98#ibcon#read 3, iclass 12, count 2 2006.211.08:02:39.98#ibcon#about to read 4, iclass 12, count 2 2006.211.08:02:39.98#ibcon#read 4, iclass 12, count 2 2006.211.08:02:39.98#ibcon#about to read 5, iclass 12, count 2 2006.211.08:02:39.98#ibcon#read 5, iclass 12, count 2 2006.211.08:02:39.98#ibcon#about to read 6, iclass 12, count 2 2006.211.08:02:39.98#ibcon#read 6, iclass 12, count 2 2006.211.08:02:39.98#ibcon#end of sib2, iclass 12, count 2 2006.211.08:02:39.98#ibcon#*after write, iclass 12, count 2 2006.211.08:02:39.98#ibcon#*before return 0, iclass 12, count 2 2006.211.08:02:39.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:02:39.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:02:39.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:02:39.99#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:39.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:02:40.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:02:40.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:02:40.10#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:02:40.10#ibcon#first serial, iclass 12, count 0 2006.211.08:02:40.10#ibcon#enter sib2, iclass 12, count 0 2006.211.08:02:40.10#ibcon#flushed, iclass 12, count 0 2006.211.08:02:40.10#ibcon#about to write, iclass 12, count 0 2006.211.08:02:40.10#ibcon#wrote, iclass 12, count 0 2006.211.08:02:40.10#ibcon#about to read 3, iclass 12, count 0 2006.211.08:02:40.12#ibcon#read 3, iclass 12, count 0 2006.211.08:02:40.12#ibcon#about to read 4, iclass 12, count 0 2006.211.08:02:40.12#ibcon#read 4, iclass 12, count 0 2006.211.08:02:40.12#ibcon#about to read 5, iclass 12, count 0 2006.211.08:02:40.12#ibcon#read 5, iclass 12, count 0 2006.211.08:02:40.12#ibcon#about to read 6, iclass 12, count 0 2006.211.08:02:40.12#ibcon#read 6, iclass 12, count 0 2006.211.08:02:40.12#ibcon#end of sib2, iclass 12, count 0 2006.211.08:02:40.12#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:02:40.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:02:40.13#ibcon#[25=USB\r\n] 2006.211.08:02:40.13#ibcon#*before write, iclass 12, count 0 2006.211.08:02:40.13#ibcon#enter sib2, iclass 12, count 0 2006.211.08:02:40.13#ibcon#flushed, iclass 12, count 0 2006.211.08:02:40.13#ibcon#about to write, iclass 12, count 0 2006.211.08:02:40.13#ibcon#wrote, iclass 12, count 0 2006.211.08:02:40.13#ibcon#about to read 3, iclass 12, count 0 2006.211.08:02:40.15#ibcon#read 3, iclass 12, count 0 2006.211.08:02:40.15#ibcon#about to read 4, iclass 12, count 0 2006.211.08:02:40.15#ibcon#read 4, iclass 12, count 0 2006.211.08:02:40.15#ibcon#about to read 5, iclass 12, count 0 2006.211.08:02:40.15#ibcon#read 5, iclass 12, count 0 2006.211.08:02:40.15#ibcon#about to read 6, iclass 12, count 0 2006.211.08:02:40.15#ibcon#read 6, iclass 12, count 0 2006.211.08:02:40.15#ibcon#end of sib2, iclass 12, count 0 2006.211.08:02:40.15#ibcon#*after write, iclass 12, count 0 2006.211.08:02:40.15#ibcon#*before return 0, iclass 12, count 0 2006.211.08:02:40.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:02:40.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:02:40.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:02:40.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:02:40.16$vc4f8/vblo=1,632.99 2006.211.08:02:40.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:02:40.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:02:40.16#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:40.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:02:40.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:02:40.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:02:40.16#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:02:40.16#ibcon#first serial, iclass 14, count 0 2006.211.08:02:40.16#ibcon#enter sib2, iclass 14, count 0 2006.211.08:02:40.16#ibcon#flushed, iclass 14, count 0 2006.211.08:02:40.16#ibcon#about to write, iclass 14, count 0 2006.211.08:02:40.16#ibcon#wrote, iclass 14, count 0 2006.211.08:02:40.16#ibcon#about to read 3, iclass 14, count 0 2006.211.08:02:40.17#ibcon#read 3, iclass 14, count 0 2006.211.08:02:40.17#ibcon#about to read 4, iclass 14, count 0 2006.211.08:02:40.17#ibcon#read 4, iclass 14, count 0 2006.211.08:02:40.17#ibcon#about to read 5, iclass 14, count 0 2006.211.08:02:40.17#ibcon#read 5, iclass 14, count 0 2006.211.08:02:40.17#ibcon#about to read 6, iclass 14, count 0 2006.211.08:02:40.17#ibcon#read 6, iclass 14, count 0 2006.211.08:02:40.17#ibcon#end of sib2, iclass 14, count 0 2006.211.08:02:40.17#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:02:40.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:02:40.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:02:40.18#ibcon#*before write, iclass 14, count 0 2006.211.08:02:40.18#ibcon#enter sib2, iclass 14, count 0 2006.211.08:02:40.18#ibcon#flushed, iclass 14, count 0 2006.211.08:02:40.18#ibcon#about to write, iclass 14, count 0 2006.211.08:02:40.18#ibcon#wrote, iclass 14, count 0 2006.211.08:02:40.18#ibcon#about to read 3, iclass 14, count 0 2006.211.08:02:40.21#ibcon#read 3, iclass 14, count 0 2006.211.08:02:40.21#ibcon#about to read 4, iclass 14, count 0 2006.211.08:02:40.21#ibcon#read 4, iclass 14, count 0 2006.211.08:02:40.21#ibcon#about to read 5, iclass 14, count 0 2006.211.08:02:40.21#ibcon#read 5, iclass 14, count 0 2006.211.08:02:40.21#ibcon#about to read 6, iclass 14, count 0 2006.211.08:02:40.21#ibcon#read 6, iclass 14, count 0 2006.211.08:02:40.21#ibcon#end of sib2, iclass 14, count 0 2006.211.08:02:40.21#ibcon#*after write, iclass 14, count 0 2006.211.08:02:40.21#ibcon#*before return 0, iclass 14, count 0 2006.211.08:02:40.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:02:40.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:02:40.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:02:40.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:02:40.22$vc4f8/vb=1,4 2006.211.08:02:40.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:02:40.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:02:40.22#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:40.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:02:40.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:02:40.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:02:40.22#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:02:40.22#ibcon#first serial, iclass 16, count 2 2006.211.08:02:40.22#ibcon#enter sib2, iclass 16, count 2 2006.211.08:02:40.22#ibcon#flushed, iclass 16, count 2 2006.211.08:02:40.22#ibcon#about to write, iclass 16, count 2 2006.211.08:02:40.22#ibcon#wrote, iclass 16, count 2 2006.211.08:02:40.22#ibcon#about to read 3, iclass 16, count 2 2006.211.08:02:40.23#ibcon#read 3, iclass 16, count 2 2006.211.08:02:40.23#ibcon#about to read 4, iclass 16, count 2 2006.211.08:02:40.23#ibcon#read 4, iclass 16, count 2 2006.211.08:02:40.23#ibcon#about to read 5, iclass 16, count 2 2006.211.08:02:40.23#ibcon#read 5, iclass 16, count 2 2006.211.08:02:40.23#ibcon#about to read 6, iclass 16, count 2 2006.211.08:02:40.23#ibcon#read 6, iclass 16, count 2 2006.211.08:02:40.23#ibcon#end of sib2, iclass 16, count 2 2006.211.08:02:40.23#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:02:40.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:02:40.24#ibcon#[27=AT01-04\r\n] 2006.211.08:02:40.24#ibcon#*before write, iclass 16, count 2 2006.211.08:02:40.24#ibcon#enter sib2, iclass 16, count 2 2006.211.08:02:40.24#ibcon#flushed, iclass 16, count 2 2006.211.08:02:40.24#ibcon#about to write, iclass 16, count 2 2006.211.08:02:40.24#ibcon#wrote, iclass 16, count 2 2006.211.08:02:40.24#ibcon#about to read 3, iclass 16, count 2 2006.211.08:02:40.26#ibcon#read 3, iclass 16, count 2 2006.211.08:02:40.26#ibcon#about to read 4, iclass 16, count 2 2006.211.08:02:40.26#ibcon#read 4, iclass 16, count 2 2006.211.08:02:40.26#ibcon#about to read 5, iclass 16, count 2 2006.211.08:02:40.26#ibcon#read 5, iclass 16, count 2 2006.211.08:02:40.26#ibcon#about to read 6, iclass 16, count 2 2006.211.08:02:40.26#ibcon#read 6, iclass 16, count 2 2006.211.08:02:40.26#ibcon#end of sib2, iclass 16, count 2 2006.211.08:02:40.26#ibcon#*after write, iclass 16, count 2 2006.211.08:02:40.26#ibcon#*before return 0, iclass 16, count 2 2006.211.08:02:40.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:02:40.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:02:40.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:02:40.27#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:40.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:02:40.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:02:40.38#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:02:40.38#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:02:40.38#ibcon#first serial, iclass 16, count 0 2006.211.08:02:40.38#ibcon#enter sib2, iclass 16, count 0 2006.211.08:02:40.38#ibcon#flushed, iclass 16, count 0 2006.211.08:02:40.38#ibcon#about to write, iclass 16, count 0 2006.211.08:02:40.38#ibcon#wrote, iclass 16, count 0 2006.211.08:02:40.38#ibcon#about to read 3, iclass 16, count 0 2006.211.08:02:40.40#ibcon#read 3, iclass 16, count 0 2006.211.08:02:40.40#ibcon#about to read 4, iclass 16, count 0 2006.211.08:02:40.40#ibcon#read 4, iclass 16, count 0 2006.211.08:02:40.40#ibcon#about to read 5, iclass 16, count 0 2006.211.08:02:40.40#ibcon#read 5, iclass 16, count 0 2006.211.08:02:40.40#ibcon#about to read 6, iclass 16, count 0 2006.211.08:02:40.40#ibcon#read 6, iclass 16, count 0 2006.211.08:02:40.40#ibcon#end of sib2, iclass 16, count 0 2006.211.08:02:40.40#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:02:40.40#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:02:40.41#ibcon#[27=USB\r\n] 2006.211.08:02:40.41#ibcon#*before write, iclass 16, count 0 2006.211.08:02:40.41#ibcon#enter sib2, iclass 16, count 0 2006.211.08:02:40.41#ibcon#flushed, iclass 16, count 0 2006.211.08:02:40.41#ibcon#about to write, iclass 16, count 0 2006.211.08:02:40.41#ibcon#wrote, iclass 16, count 0 2006.211.08:02:40.41#ibcon#about to read 3, iclass 16, count 0 2006.211.08:02:40.43#ibcon#read 3, iclass 16, count 0 2006.211.08:02:40.43#ibcon#about to read 4, iclass 16, count 0 2006.211.08:02:40.43#ibcon#read 4, iclass 16, count 0 2006.211.08:02:40.43#ibcon#about to read 5, iclass 16, count 0 2006.211.08:02:40.43#ibcon#read 5, iclass 16, count 0 2006.211.08:02:40.43#ibcon#about to read 6, iclass 16, count 0 2006.211.08:02:40.43#ibcon#read 6, iclass 16, count 0 2006.211.08:02:40.43#ibcon#end of sib2, iclass 16, count 0 2006.211.08:02:40.43#ibcon#*after write, iclass 16, count 0 2006.211.08:02:40.43#ibcon#*before return 0, iclass 16, count 0 2006.211.08:02:40.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:02:40.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:02:40.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:02:40.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:02:40.44$vc4f8/vblo=2,640.99 2006.211.08:02:40.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:02:40.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:02:40.44#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:40.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:40.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:40.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:40.44#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:02:40.44#ibcon#first serial, iclass 18, count 0 2006.211.08:02:40.44#ibcon#enter sib2, iclass 18, count 0 2006.211.08:02:40.44#ibcon#flushed, iclass 18, count 0 2006.211.08:02:40.44#ibcon#about to write, iclass 18, count 0 2006.211.08:02:40.44#ibcon#wrote, iclass 18, count 0 2006.211.08:02:40.44#ibcon#about to read 3, iclass 18, count 0 2006.211.08:02:40.45#ibcon#read 3, iclass 18, count 0 2006.211.08:02:40.45#ibcon#about to read 4, iclass 18, count 0 2006.211.08:02:40.45#ibcon#read 4, iclass 18, count 0 2006.211.08:02:40.45#ibcon#about to read 5, iclass 18, count 0 2006.211.08:02:40.45#ibcon#read 5, iclass 18, count 0 2006.211.08:02:40.45#ibcon#about to read 6, iclass 18, count 0 2006.211.08:02:40.45#ibcon#read 6, iclass 18, count 0 2006.211.08:02:40.45#ibcon#end of sib2, iclass 18, count 0 2006.211.08:02:40.45#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:02:40.45#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:02:40.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:02:40.46#ibcon#*before write, iclass 18, count 0 2006.211.08:02:40.46#ibcon#enter sib2, iclass 18, count 0 2006.211.08:02:40.46#ibcon#flushed, iclass 18, count 0 2006.211.08:02:40.46#ibcon#about to write, iclass 18, count 0 2006.211.08:02:40.46#ibcon#wrote, iclass 18, count 0 2006.211.08:02:40.46#ibcon#about to read 3, iclass 18, count 0 2006.211.08:02:40.49#ibcon#read 3, iclass 18, count 0 2006.211.08:02:40.49#ibcon#about to read 4, iclass 18, count 0 2006.211.08:02:40.49#ibcon#read 4, iclass 18, count 0 2006.211.08:02:40.49#ibcon#about to read 5, iclass 18, count 0 2006.211.08:02:40.49#ibcon#read 5, iclass 18, count 0 2006.211.08:02:40.49#ibcon#about to read 6, iclass 18, count 0 2006.211.08:02:40.49#ibcon#read 6, iclass 18, count 0 2006.211.08:02:40.49#ibcon#end of sib2, iclass 18, count 0 2006.211.08:02:40.49#ibcon#*after write, iclass 18, count 0 2006.211.08:02:40.49#ibcon#*before return 0, iclass 18, count 0 2006.211.08:02:40.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:40.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:02:40.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:02:40.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:02:40.50$vc4f8/vb=2,4 2006.211.08:02:40.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:02:40.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:02:40.50#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:40.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:40.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:40.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:40.55#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:02:40.55#ibcon#first serial, iclass 20, count 2 2006.211.08:02:40.55#ibcon#enter sib2, iclass 20, count 2 2006.211.08:02:40.55#ibcon#flushed, iclass 20, count 2 2006.211.08:02:40.55#ibcon#about to write, iclass 20, count 2 2006.211.08:02:40.55#ibcon#wrote, iclass 20, count 2 2006.211.08:02:40.55#ibcon#about to read 3, iclass 20, count 2 2006.211.08:02:40.57#ibcon#read 3, iclass 20, count 2 2006.211.08:02:40.57#ibcon#about to read 4, iclass 20, count 2 2006.211.08:02:40.57#ibcon#read 4, iclass 20, count 2 2006.211.08:02:40.57#ibcon#about to read 5, iclass 20, count 2 2006.211.08:02:40.57#ibcon#read 5, iclass 20, count 2 2006.211.08:02:40.57#ibcon#about to read 6, iclass 20, count 2 2006.211.08:02:40.57#ibcon#read 6, iclass 20, count 2 2006.211.08:02:40.57#ibcon#end of sib2, iclass 20, count 2 2006.211.08:02:40.57#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:02:40.57#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:02:40.58#ibcon#[27=AT02-04\r\n] 2006.211.08:02:40.58#ibcon#*before write, iclass 20, count 2 2006.211.08:02:40.58#ibcon#enter sib2, iclass 20, count 2 2006.211.08:02:40.58#ibcon#flushed, iclass 20, count 2 2006.211.08:02:40.58#ibcon#about to write, iclass 20, count 2 2006.211.08:02:40.58#ibcon#wrote, iclass 20, count 2 2006.211.08:02:40.58#ibcon#about to read 3, iclass 20, count 2 2006.211.08:02:40.60#ibcon#read 3, iclass 20, count 2 2006.211.08:02:40.60#ibcon#about to read 4, iclass 20, count 2 2006.211.08:02:40.60#ibcon#read 4, iclass 20, count 2 2006.211.08:02:40.60#ibcon#about to read 5, iclass 20, count 2 2006.211.08:02:40.60#ibcon#read 5, iclass 20, count 2 2006.211.08:02:40.60#ibcon#about to read 6, iclass 20, count 2 2006.211.08:02:40.60#ibcon#read 6, iclass 20, count 2 2006.211.08:02:40.60#ibcon#end of sib2, iclass 20, count 2 2006.211.08:02:40.60#ibcon#*after write, iclass 20, count 2 2006.211.08:02:40.60#ibcon#*before return 0, iclass 20, count 2 2006.211.08:02:40.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:40.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:02:40.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:02:40.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:40.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:40.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:40.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:40.72#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:02:40.72#ibcon#first serial, iclass 20, count 0 2006.211.08:02:40.72#ibcon#enter sib2, iclass 20, count 0 2006.211.08:02:40.72#ibcon#flushed, iclass 20, count 0 2006.211.08:02:40.72#ibcon#about to write, iclass 20, count 0 2006.211.08:02:40.72#ibcon#wrote, iclass 20, count 0 2006.211.08:02:40.72#ibcon#about to read 3, iclass 20, count 0 2006.211.08:02:40.74#ibcon#read 3, iclass 20, count 0 2006.211.08:02:40.74#ibcon#about to read 4, iclass 20, count 0 2006.211.08:02:40.74#ibcon#read 4, iclass 20, count 0 2006.211.08:02:40.74#ibcon#about to read 5, iclass 20, count 0 2006.211.08:02:40.74#ibcon#read 5, iclass 20, count 0 2006.211.08:02:40.74#ibcon#about to read 6, iclass 20, count 0 2006.211.08:02:40.74#ibcon#read 6, iclass 20, count 0 2006.211.08:02:40.74#ibcon#end of sib2, iclass 20, count 0 2006.211.08:02:40.74#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:02:40.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:02:40.75#ibcon#[27=USB\r\n] 2006.211.08:02:40.75#ibcon#*before write, iclass 20, count 0 2006.211.08:02:40.75#ibcon#enter sib2, iclass 20, count 0 2006.211.08:02:40.75#ibcon#flushed, iclass 20, count 0 2006.211.08:02:40.75#ibcon#about to write, iclass 20, count 0 2006.211.08:02:40.75#ibcon#wrote, iclass 20, count 0 2006.211.08:02:40.75#ibcon#about to read 3, iclass 20, count 0 2006.211.08:02:40.77#ibcon#read 3, iclass 20, count 0 2006.211.08:02:40.77#ibcon#about to read 4, iclass 20, count 0 2006.211.08:02:40.77#ibcon#read 4, iclass 20, count 0 2006.211.08:02:40.77#ibcon#about to read 5, iclass 20, count 0 2006.211.08:02:40.77#ibcon#read 5, iclass 20, count 0 2006.211.08:02:40.77#ibcon#about to read 6, iclass 20, count 0 2006.211.08:02:40.77#ibcon#read 6, iclass 20, count 0 2006.211.08:02:40.77#ibcon#end of sib2, iclass 20, count 0 2006.211.08:02:40.77#ibcon#*after write, iclass 20, count 0 2006.211.08:02:40.77#ibcon#*before return 0, iclass 20, count 0 2006.211.08:02:40.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:40.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:02:40.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:02:40.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:02:40.78$vc4f8/vblo=3,656.99 2006.211.08:02:40.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:02:40.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:02:40.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:40.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:40.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:40.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:40.78#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:02:40.78#ibcon#first serial, iclass 22, count 0 2006.211.08:02:40.78#ibcon#enter sib2, iclass 22, count 0 2006.211.08:02:40.78#ibcon#flushed, iclass 22, count 0 2006.211.08:02:40.78#ibcon#about to write, iclass 22, count 0 2006.211.08:02:40.78#ibcon#wrote, iclass 22, count 0 2006.211.08:02:40.78#ibcon#about to read 3, iclass 22, count 0 2006.211.08:02:40.79#ibcon#read 3, iclass 22, count 0 2006.211.08:02:40.79#ibcon#about to read 4, iclass 22, count 0 2006.211.08:02:40.79#ibcon#read 4, iclass 22, count 0 2006.211.08:02:40.79#ibcon#about to read 5, iclass 22, count 0 2006.211.08:02:40.79#ibcon#read 5, iclass 22, count 0 2006.211.08:02:40.79#ibcon#about to read 6, iclass 22, count 0 2006.211.08:02:40.79#ibcon#read 6, iclass 22, count 0 2006.211.08:02:40.79#ibcon#end of sib2, iclass 22, count 0 2006.211.08:02:40.79#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:02:40.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:02:40.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:02:40.80#ibcon#*before write, iclass 22, count 0 2006.211.08:02:40.80#ibcon#enter sib2, iclass 22, count 0 2006.211.08:02:40.80#ibcon#flushed, iclass 22, count 0 2006.211.08:02:40.80#ibcon#about to write, iclass 22, count 0 2006.211.08:02:40.80#ibcon#wrote, iclass 22, count 0 2006.211.08:02:40.80#ibcon#about to read 3, iclass 22, count 0 2006.211.08:02:40.83#ibcon#read 3, iclass 22, count 0 2006.211.08:02:40.83#ibcon#about to read 4, iclass 22, count 0 2006.211.08:02:40.83#ibcon#read 4, iclass 22, count 0 2006.211.08:02:40.83#ibcon#about to read 5, iclass 22, count 0 2006.211.08:02:40.83#ibcon#read 5, iclass 22, count 0 2006.211.08:02:40.83#ibcon#about to read 6, iclass 22, count 0 2006.211.08:02:40.83#ibcon#read 6, iclass 22, count 0 2006.211.08:02:40.83#ibcon#end of sib2, iclass 22, count 0 2006.211.08:02:40.83#ibcon#*after write, iclass 22, count 0 2006.211.08:02:40.83#ibcon#*before return 0, iclass 22, count 0 2006.211.08:02:40.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:40.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:02:40.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:02:40.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:02:40.84$vc4f8/vb=3,3 2006.211.08:02:40.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:02:40.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:02:40.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:40.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:40.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:40.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:40.89#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:02:40.89#ibcon#first serial, iclass 24, count 2 2006.211.08:02:40.89#ibcon#enter sib2, iclass 24, count 2 2006.211.08:02:40.89#ibcon#flushed, iclass 24, count 2 2006.211.08:02:40.89#ibcon#about to write, iclass 24, count 2 2006.211.08:02:40.89#ibcon#wrote, iclass 24, count 2 2006.211.08:02:40.89#ibcon#about to read 3, iclass 24, count 2 2006.211.08:02:40.91#ibcon#read 3, iclass 24, count 2 2006.211.08:02:40.91#ibcon#about to read 4, iclass 24, count 2 2006.211.08:02:40.91#ibcon#read 4, iclass 24, count 2 2006.211.08:02:40.91#ibcon#about to read 5, iclass 24, count 2 2006.211.08:02:40.91#ibcon#read 5, iclass 24, count 2 2006.211.08:02:40.91#ibcon#about to read 6, iclass 24, count 2 2006.211.08:02:40.91#ibcon#read 6, iclass 24, count 2 2006.211.08:02:40.91#ibcon#end of sib2, iclass 24, count 2 2006.211.08:02:40.91#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:02:40.91#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:02:40.92#ibcon#[27=AT03-03\r\n] 2006.211.08:02:40.92#ibcon#*before write, iclass 24, count 2 2006.211.08:02:40.92#ibcon#enter sib2, iclass 24, count 2 2006.211.08:02:40.92#ibcon#flushed, iclass 24, count 2 2006.211.08:02:40.92#ibcon#about to write, iclass 24, count 2 2006.211.08:02:40.92#ibcon#wrote, iclass 24, count 2 2006.211.08:02:40.92#ibcon#about to read 3, iclass 24, count 2 2006.211.08:02:40.94#ibcon#read 3, iclass 24, count 2 2006.211.08:02:40.94#ibcon#about to read 4, iclass 24, count 2 2006.211.08:02:40.94#ibcon#read 4, iclass 24, count 2 2006.211.08:02:40.94#ibcon#about to read 5, iclass 24, count 2 2006.211.08:02:40.94#ibcon#read 5, iclass 24, count 2 2006.211.08:02:40.94#ibcon#about to read 6, iclass 24, count 2 2006.211.08:02:40.94#ibcon#read 6, iclass 24, count 2 2006.211.08:02:40.94#ibcon#end of sib2, iclass 24, count 2 2006.211.08:02:40.94#ibcon#*after write, iclass 24, count 2 2006.211.08:02:40.94#ibcon#*before return 0, iclass 24, count 2 2006.211.08:02:40.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:40.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:02:40.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:02:40.95#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:40.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:40.99#abcon#<5=/04 4.3 8.5 24.76 771010.0\r\n> 2006.211.08:02:41.01#abcon#{5=INTERFACE CLEAR} 2006.211.08:02:41.06#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:41.06#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:41.06#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:02:41.06#ibcon#first serial, iclass 24, count 0 2006.211.08:02:41.06#ibcon#enter sib2, iclass 24, count 0 2006.211.08:02:41.06#ibcon#flushed, iclass 24, count 0 2006.211.08:02:41.06#ibcon#about to write, iclass 24, count 0 2006.211.08:02:41.06#ibcon#wrote, iclass 24, count 0 2006.211.08:02:41.06#ibcon#about to read 3, iclass 24, count 0 2006.211.08:02:41.07#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:02:41.08#ibcon#read 3, iclass 24, count 0 2006.211.08:02:41.08#ibcon#about to read 4, iclass 24, count 0 2006.211.08:02:41.08#ibcon#read 4, iclass 24, count 0 2006.211.08:02:41.08#ibcon#about to read 5, iclass 24, count 0 2006.211.08:02:41.08#ibcon#read 5, iclass 24, count 0 2006.211.08:02:41.08#ibcon#about to read 6, iclass 24, count 0 2006.211.08:02:41.08#ibcon#read 6, iclass 24, count 0 2006.211.08:02:41.08#ibcon#end of sib2, iclass 24, count 0 2006.211.08:02:41.08#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:02:41.08#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:02:41.09#ibcon#[27=USB\r\n] 2006.211.08:02:41.09#ibcon#*before write, iclass 24, count 0 2006.211.08:02:41.09#ibcon#enter sib2, iclass 24, count 0 2006.211.08:02:41.09#ibcon#flushed, iclass 24, count 0 2006.211.08:02:41.09#ibcon#about to write, iclass 24, count 0 2006.211.08:02:41.09#ibcon#wrote, iclass 24, count 0 2006.211.08:02:41.09#ibcon#about to read 3, iclass 24, count 0 2006.211.08:02:41.11#ibcon#read 3, iclass 24, count 0 2006.211.08:02:41.11#ibcon#about to read 4, iclass 24, count 0 2006.211.08:02:41.11#ibcon#read 4, iclass 24, count 0 2006.211.08:02:41.11#ibcon#about to read 5, iclass 24, count 0 2006.211.08:02:41.11#ibcon#read 5, iclass 24, count 0 2006.211.08:02:41.11#ibcon#about to read 6, iclass 24, count 0 2006.211.08:02:41.11#ibcon#read 6, iclass 24, count 0 2006.211.08:02:41.11#ibcon#end of sib2, iclass 24, count 0 2006.211.08:02:41.11#ibcon#*after write, iclass 24, count 0 2006.211.08:02:41.11#ibcon#*before return 0, iclass 24, count 0 2006.211.08:02:41.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:41.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:02:41.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:02:41.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:02:41.12$vc4f8/vblo=4,712.99 2006.211.08:02:41.12#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:02:41.12#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:02:41.12#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:41.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:41.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:41.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:41.12#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:02:41.12#ibcon#first serial, iclass 30, count 0 2006.211.08:02:41.12#ibcon#enter sib2, iclass 30, count 0 2006.211.08:02:41.12#ibcon#flushed, iclass 30, count 0 2006.211.08:02:41.12#ibcon#about to write, iclass 30, count 0 2006.211.08:02:41.12#ibcon#wrote, iclass 30, count 0 2006.211.08:02:41.12#ibcon#about to read 3, iclass 30, count 0 2006.211.08:02:41.13#ibcon#read 3, iclass 30, count 0 2006.211.08:02:41.13#ibcon#about to read 4, iclass 30, count 0 2006.211.08:02:41.13#ibcon#read 4, iclass 30, count 0 2006.211.08:02:41.13#ibcon#about to read 5, iclass 30, count 0 2006.211.08:02:41.13#ibcon#read 5, iclass 30, count 0 2006.211.08:02:41.13#ibcon#about to read 6, iclass 30, count 0 2006.211.08:02:41.13#ibcon#read 6, iclass 30, count 0 2006.211.08:02:41.13#ibcon#end of sib2, iclass 30, count 0 2006.211.08:02:41.13#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:02:41.13#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:02:41.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:02:41.14#ibcon#*before write, iclass 30, count 0 2006.211.08:02:41.14#ibcon#enter sib2, iclass 30, count 0 2006.211.08:02:41.14#ibcon#flushed, iclass 30, count 0 2006.211.08:02:41.14#ibcon#about to write, iclass 30, count 0 2006.211.08:02:41.14#ibcon#wrote, iclass 30, count 0 2006.211.08:02:41.14#ibcon#about to read 3, iclass 30, count 0 2006.211.08:02:41.17#ibcon#read 3, iclass 30, count 0 2006.211.08:02:41.17#ibcon#about to read 4, iclass 30, count 0 2006.211.08:02:41.17#ibcon#read 4, iclass 30, count 0 2006.211.08:02:41.17#ibcon#about to read 5, iclass 30, count 0 2006.211.08:02:41.17#ibcon#read 5, iclass 30, count 0 2006.211.08:02:41.17#ibcon#about to read 6, iclass 30, count 0 2006.211.08:02:41.17#ibcon#read 6, iclass 30, count 0 2006.211.08:02:41.17#ibcon#end of sib2, iclass 30, count 0 2006.211.08:02:41.17#ibcon#*after write, iclass 30, count 0 2006.211.08:02:41.17#ibcon#*before return 0, iclass 30, count 0 2006.211.08:02:41.18#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:41.18#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:02:41.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:02:41.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:02:41.18$vc4f8/vb=4,3 2006.211.08:02:41.18#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:02:41.18#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:02:41.18#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:41.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:41.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:41.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:41.23#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:02:41.23#ibcon#first serial, iclass 32, count 2 2006.211.08:02:41.23#ibcon#enter sib2, iclass 32, count 2 2006.211.08:02:41.23#ibcon#flushed, iclass 32, count 2 2006.211.08:02:41.23#ibcon#about to write, iclass 32, count 2 2006.211.08:02:41.23#ibcon#wrote, iclass 32, count 2 2006.211.08:02:41.23#ibcon#about to read 3, iclass 32, count 2 2006.211.08:02:41.25#ibcon#read 3, iclass 32, count 2 2006.211.08:02:41.25#ibcon#about to read 4, iclass 32, count 2 2006.211.08:02:41.25#ibcon#read 4, iclass 32, count 2 2006.211.08:02:41.25#ibcon#about to read 5, iclass 32, count 2 2006.211.08:02:41.25#ibcon#read 5, iclass 32, count 2 2006.211.08:02:41.25#ibcon#about to read 6, iclass 32, count 2 2006.211.08:02:41.25#ibcon#read 6, iclass 32, count 2 2006.211.08:02:41.25#ibcon#end of sib2, iclass 32, count 2 2006.211.08:02:41.25#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:02:41.25#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:02:41.26#ibcon#[27=AT04-03\r\n] 2006.211.08:02:41.26#ibcon#*before write, iclass 32, count 2 2006.211.08:02:41.26#ibcon#enter sib2, iclass 32, count 2 2006.211.08:02:41.26#ibcon#flushed, iclass 32, count 2 2006.211.08:02:41.26#ibcon#about to write, iclass 32, count 2 2006.211.08:02:41.26#ibcon#wrote, iclass 32, count 2 2006.211.08:02:41.26#ibcon#about to read 3, iclass 32, count 2 2006.211.08:02:41.28#ibcon#read 3, iclass 32, count 2 2006.211.08:02:41.28#ibcon#about to read 4, iclass 32, count 2 2006.211.08:02:41.28#ibcon#read 4, iclass 32, count 2 2006.211.08:02:41.28#ibcon#about to read 5, iclass 32, count 2 2006.211.08:02:41.28#ibcon#read 5, iclass 32, count 2 2006.211.08:02:41.28#ibcon#about to read 6, iclass 32, count 2 2006.211.08:02:41.28#ibcon#read 6, iclass 32, count 2 2006.211.08:02:41.28#ibcon#end of sib2, iclass 32, count 2 2006.211.08:02:41.28#ibcon#*after write, iclass 32, count 2 2006.211.08:02:41.28#ibcon#*before return 0, iclass 32, count 2 2006.211.08:02:41.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:41.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:02:41.29#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:02:41.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:41.29#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:41.40#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:41.40#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:41.40#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:02:41.40#ibcon#first serial, iclass 32, count 0 2006.211.08:02:41.40#ibcon#enter sib2, iclass 32, count 0 2006.211.08:02:41.40#ibcon#flushed, iclass 32, count 0 2006.211.08:02:41.40#ibcon#about to write, iclass 32, count 0 2006.211.08:02:41.40#ibcon#wrote, iclass 32, count 0 2006.211.08:02:41.40#ibcon#about to read 3, iclass 32, count 0 2006.211.08:02:41.42#ibcon#read 3, iclass 32, count 0 2006.211.08:02:41.42#ibcon#about to read 4, iclass 32, count 0 2006.211.08:02:41.42#ibcon#read 4, iclass 32, count 0 2006.211.08:02:41.42#ibcon#about to read 5, iclass 32, count 0 2006.211.08:02:41.42#ibcon#read 5, iclass 32, count 0 2006.211.08:02:41.42#ibcon#about to read 6, iclass 32, count 0 2006.211.08:02:41.42#ibcon#read 6, iclass 32, count 0 2006.211.08:02:41.42#ibcon#end of sib2, iclass 32, count 0 2006.211.08:02:41.42#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:02:41.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:02:41.43#ibcon#[27=USB\r\n] 2006.211.08:02:41.43#ibcon#*before write, iclass 32, count 0 2006.211.08:02:41.43#ibcon#enter sib2, iclass 32, count 0 2006.211.08:02:41.43#ibcon#flushed, iclass 32, count 0 2006.211.08:02:41.43#ibcon#about to write, iclass 32, count 0 2006.211.08:02:41.43#ibcon#wrote, iclass 32, count 0 2006.211.08:02:41.43#ibcon#about to read 3, iclass 32, count 0 2006.211.08:02:41.45#ibcon#read 3, iclass 32, count 0 2006.211.08:02:41.45#ibcon#about to read 4, iclass 32, count 0 2006.211.08:02:41.45#ibcon#read 4, iclass 32, count 0 2006.211.08:02:41.45#ibcon#about to read 5, iclass 32, count 0 2006.211.08:02:41.45#ibcon#read 5, iclass 32, count 0 2006.211.08:02:41.45#ibcon#about to read 6, iclass 32, count 0 2006.211.08:02:41.45#ibcon#read 6, iclass 32, count 0 2006.211.08:02:41.45#ibcon#end of sib2, iclass 32, count 0 2006.211.08:02:41.45#ibcon#*after write, iclass 32, count 0 2006.211.08:02:41.45#ibcon#*before return 0, iclass 32, count 0 2006.211.08:02:41.46#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:41.46#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:02:41.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:02:41.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:02:41.46$vc4f8/vblo=5,744.99 2006.211.08:02:41.46#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:02:41.46#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:02:41.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:41.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:41.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:41.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:41.46#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:02:41.46#ibcon#first serial, iclass 34, count 0 2006.211.08:02:41.46#ibcon#enter sib2, iclass 34, count 0 2006.211.08:02:41.46#ibcon#flushed, iclass 34, count 0 2006.211.08:02:41.46#ibcon#about to write, iclass 34, count 0 2006.211.08:02:41.46#ibcon#wrote, iclass 34, count 0 2006.211.08:02:41.46#ibcon#about to read 3, iclass 34, count 0 2006.211.08:02:41.47#ibcon#read 3, iclass 34, count 0 2006.211.08:02:41.47#ibcon#about to read 4, iclass 34, count 0 2006.211.08:02:41.47#ibcon#read 4, iclass 34, count 0 2006.211.08:02:41.47#ibcon#about to read 5, iclass 34, count 0 2006.211.08:02:41.47#ibcon#read 5, iclass 34, count 0 2006.211.08:02:41.47#ibcon#about to read 6, iclass 34, count 0 2006.211.08:02:41.47#ibcon#read 6, iclass 34, count 0 2006.211.08:02:41.47#ibcon#end of sib2, iclass 34, count 0 2006.211.08:02:41.47#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:02:41.47#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:02:41.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:02:41.48#ibcon#*before write, iclass 34, count 0 2006.211.08:02:41.48#ibcon#enter sib2, iclass 34, count 0 2006.211.08:02:41.48#ibcon#flushed, iclass 34, count 0 2006.211.08:02:41.48#ibcon#about to write, iclass 34, count 0 2006.211.08:02:41.48#ibcon#wrote, iclass 34, count 0 2006.211.08:02:41.48#ibcon#about to read 3, iclass 34, count 0 2006.211.08:02:41.51#ibcon#read 3, iclass 34, count 0 2006.211.08:02:41.51#ibcon#about to read 4, iclass 34, count 0 2006.211.08:02:41.51#ibcon#read 4, iclass 34, count 0 2006.211.08:02:41.51#ibcon#about to read 5, iclass 34, count 0 2006.211.08:02:41.51#ibcon#read 5, iclass 34, count 0 2006.211.08:02:41.51#ibcon#about to read 6, iclass 34, count 0 2006.211.08:02:41.51#ibcon#read 6, iclass 34, count 0 2006.211.08:02:41.51#ibcon#end of sib2, iclass 34, count 0 2006.211.08:02:41.51#ibcon#*after write, iclass 34, count 0 2006.211.08:02:41.51#ibcon#*before return 0, iclass 34, count 0 2006.211.08:02:41.52#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:41.52#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:02:41.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:02:41.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:02:41.52$vc4f8/vb=5,3 2006.211.08:02:41.52#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:02:41.52#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:02:41.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:41.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:41.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:41.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:41.57#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:02:41.57#ibcon#first serial, iclass 36, count 2 2006.211.08:02:41.57#ibcon#enter sib2, iclass 36, count 2 2006.211.08:02:41.57#ibcon#flushed, iclass 36, count 2 2006.211.08:02:41.57#ibcon#about to write, iclass 36, count 2 2006.211.08:02:41.57#ibcon#wrote, iclass 36, count 2 2006.211.08:02:41.57#ibcon#about to read 3, iclass 36, count 2 2006.211.08:02:41.59#ibcon#read 3, iclass 36, count 2 2006.211.08:02:41.59#ibcon#about to read 4, iclass 36, count 2 2006.211.08:02:41.59#ibcon#read 4, iclass 36, count 2 2006.211.08:02:41.59#ibcon#about to read 5, iclass 36, count 2 2006.211.08:02:41.59#ibcon#read 5, iclass 36, count 2 2006.211.08:02:41.59#ibcon#about to read 6, iclass 36, count 2 2006.211.08:02:41.59#ibcon#read 6, iclass 36, count 2 2006.211.08:02:41.59#ibcon#end of sib2, iclass 36, count 2 2006.211.08:02:41.59#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:02:41.59#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:02:41.60#ibcon#[27=AT05-03\r\n] 2006.211.08:02:41.60#ibcon#*before write, iclass 36, count 2 2006.211.08:02:41.60#ibcon#enter sib2, iclass 36, count 2 2006.211.08:02:41.60#ibcon#flushed, iclass 36, count 2 2006.211.08:02:41.60#ibcon#about to write, iclass 36, count 2 2006.211.08:02:41.60#ibcon#wrote, iclass 36, count 2 2006.211.08:02:41.60#ibcon#about to read 3, iclass 36, count 2 2006.211.08:02:41.62#ibcon#read 3, iclass 36, count 2 2006.211.08:02:41.62#ibcon#about to read 4, iclass 36, count 2 2006.211.08:02:41.62#ibcon#read 4, iclass 36, count 2 2006.211.08:02:41.62#ibcon#about to read 5, iclass 36, count 2 2006.211.08:02:41.62#ibcon#read 5, iclass 36, count 2 2006.211.08:02:41.62#ibcon#about to read 6, iclass 36, count 2 2006.211.08:02:41.62#ibcon#read 6, iclass 36, count 2 2006.211.08:02:41.62#ibcon#end of sib2, iclass 36, count 2 2006.211.08:02:41.62#ibcon#*after write, iclass 36, count 2 2006.211.08:02:41.62#ibcon#*before return 0, iclass 36, count 2 2006.211.08:02:41.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:41.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:02:41.63#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:02:41.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:41.63#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:41.74#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:41.74#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:41.74#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:02:41.74#ibcon#first serial, iclass 36, count 0 2006.211.08:02:41.74#ibcon#enter sib2, iclass 36, count 0 2006.211.08:02:41.74#ibcon#flushed, iclass 36, count 0 2006.211.08:02:41.74#ibcon#about to write, iclass 36, count 0 2006.211.08:02:41.74#ibcon#wrote, iclass 36, count 0 2006.211.08:02:41.74#ibcon#about to read 3, iclass 36, count 0 2006.211.08:02:41.76#ibcon#read 3, iclass 36, count 0 2006.211.08:02:41.76#ibcon#about to read 4, iclass 36, count 0 2006.211.08:02:41.76#ibcon#read 4, iclass 36, count 0 2006.211.08:02:41.76#ibcon#about to read 5, iclass 36, count 0 2006.211.08:02:41.76#ibcon#read 5, iclass 36, count 0 2006.211.08:02:41.76#ibcon#about to read 6, iclass 36, count 0 2006.211.08:02:41.76#ibcon#read 6, iclass 36, count 0 2006.211.08:02:41.76#ibcon#end of sib2, iclass 36, count 0 2006.211.08:02:41.76#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:02:41.76#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:02:41.77#ibcon#[27=USB\r\n] 2006.211.08:02:41.77#ibcon#*before write, iclass 36, count 0 2006.211.08:02:41.77#ibcon#enter sib2, iclass 36, count 0 2006.211.08:02:41.77#ibcon#flushed, iclass 36, count 0 2006.211.08:02:41.77#ibcon#about to write, iclass 36, count 0 2006.211.08:02:41.77#ibcon#wrote, iclass 36, count 0 2006.211.08:02:41.77#ibcon#about to read 3, iclass 36, count 0 2006.211.08:02:41.79#ibcon#read 3, iclass 36, count 0 2006.211.08:02:41.79#ibcon#about to read 4, iclass 36, count 0 2006.211.08:02:41.79#ibcon#read 4, iclass 36, count 0 2006.211.08:02:41.79#ibcon#about to read 5, iclass 36, count 0 2006.211.08:02:41.79#ibcon#read 5, iclass 36, count 0 2006.211.08:02:41.79#ibcon#about to read 6, iclass 36, count 0 2006.211.08:02:41.79#ibcon#read 6, iclass 36, count 0 2006.211.08:02:41.79#ibcon#end of sib2, iclass 36, count 0 2006.211.08:02:41.79#ibcon#*after write, iclass 36, count 0 2006.211.08:02:41.79#ibcon#*before return 0, iclass 36, count 0 2006.211.08:02:41.80#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:41.80#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:02:41.80#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:02:41.80#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:02:41.80$vc4f8/vblo=6,752.99 2006.211.08:02:41.80#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:02:41.80#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:02:41.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:02:41.80#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:41.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:41.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:41.80#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:02:41.80#ibcon#first serial, iclass 38, count 0 2006.211.08:02:41.80#ibcon#enter sib2, iclass 38, count 0 2006.211.08:02:41.80#ibcon#flushed, iclass 38, count 0 2006.211.08:02:41.80#ibcon#about to write, iclass 38, count 0 2006.211.08:02:41.80#ibcon#wrote, iclass 38, count 0 2006.211.08:02:41.80#ibcon#about to read 3, iclass 38, count 0 2006.211.08:02:41.81#ibcon#read 3, iclass 38, count 0 2006.211.08:02:41.81#ibcon#about to read 4, iclass 38, count 0 2006.211.08:02:41.81#ibcon#read 4, iclass 38, count 0 2006.211.08:02:41.81#ibcon#about to read 5, iclass 38, count 0 2006.211.08:02:41.81#ibcon#read 5, iclass 38, count 0 2006.211.08:02:41.81#ibcon#about to read 6, iclass 38, count 0 2006.211.08:02:41.81#ibcon#read 6, iclass 38, count 0 2006.211.08:02:41.81#ibcon#end of sib2, iclass 38, count 0 2006.211.08:02:41.81#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:02:41.81#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:02:41.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:02:41.82#ibcon#*before write, iclass 38, count 0 2006.211.08:02:41.82#ibcon#enter sib2, iclass 38, count 0 2006.211.08:02:41.82#ibcon#flushed, iclass 38, count 0 2006.211.08:02:41.82#ibcon#about to write, iclass 38, count 0 2006.211.08:02:41.82#ibcon#wrote, iclass 38, count 0 2006.211.08:02:41.82#ibcon#about to read 3, iclass 38, count 0 2006.211.08:02:41.85#ibcon#read 3, iclass 38, count 0 2006.211.08:02:41.85#ibcon#about to read 4, iclass 38, count 0 2006.211.08:02:41.85#ibcon#read 4, iclass 38, count 0 2006.211.08:02:41.85#ibcon#about to read 5, iclass 38, count 0 2006.211.08:02:41.85#ibcon#read 5, iclass 38, count 0 2006.211.08:02:41.85#ibcon#about to read 6, iclass 38, count 0 2006.211.08:02:41.85#ibcon#read 6, iclass 38, count 0 2006.211.08:02:41.85#ibcon#end of sib2, iclass 38, count 0 2006.211.08:02:41.85#ibcon#*after write, iclass 38, count 0 2006.211.08:02:41.85#ibcon#*before return 0, iclass 38, count 0 2006.211.08:02:41.86#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:41.86#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:02:41.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:02:41.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:02:41.86$vc4f8/vb=6,3 2006.211.08:02:41.86#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:02:41.86#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:02:41.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:02:41.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:41.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:41.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:41.91#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:02:41.91#ibcon#first serial, iclass 40, count 2 2006.211.08:02:41.91#ibcon#enter sib2, iclass 40, count 2 2006.211.08:02:41.91#ibcon#flushed, iclass 40, count 2 2006.211.08:02:41.91#ibcon#about to write, iclass 40, count 2 2006.211.08:02:41.91#ibcon#wrote, iclass 40, count 2 2006.211.08:02:41.91#ibcon#about to read 3, iclass 40, count 2 2006.211.08:02:41.93#ibcon#read 3, iclass 40, count 2 2006.211.08:02:41.93#ibcon#about to read 4, iclass 40, count 2 2006.211.08:02:41.93#ibcon#read 4, iclass 40, count 2 2006.211.08:02:41.93#ibcon#about to read 5, iclass 40, count 2 2006.211.08:02:41.93#ibcon#read 5, iclass 40, count 2 2006.211.08:02:41.93#ibcon#about to read 6, iclass 40, count 2 2006.211.08:02:41.93#ibcon#read 6, iclass 40, count 2 2006.211.08:02:41.93#ibcon#end of sib2, iclass 40, count 2 2006.211.08:02:41.93#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:02:41.93#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:02:41.94#ibcon#[27=AT06-03\r\n] 2006.211.08:02:41.94#ibcon#*before write, iclass 40, count 2 2006.211.08:02:41.94#ibcon#enter sib2, iclass 40, count 2 2006.211.08:02:41.94#ibcon#flushed, iclass 40, count 2 2006.211.08:02:41.94#ibcon#about to write, iclass 40, count 2 2006.211.08:02:41.94#ibcon#wrote, iclass 40, count 2 2006.211.08:02:41.94#ibcon#about to read 3, iclass 40, count 2 2006.211.08:02:41.96#ibcon#read 3, iclass 40, count 2 2006.211.08:02:41.96#ibcon#about to read 4, iclass 40, count 2 2006.211.08:02:41.96#ibcon#read 4, iclass 40, count 2 2006.211.08:02:41.96#ibcon#about to read 5, iclass 40, count 2 2006.211.08:02:41.96#ibcon#read 5, iclass 40, count 2 2006.211.08:02:41.96#ibcon#about to read 6, iclass 40, count 2 2006.211.08:02:41.96#ibcon#read 6, iclass 40, count 2 2006.211.08:02:41.96#ibcon#end of sib2, iclass 40, count 2 2006.211.08:02:41.96#ibcon#*after write, iclass 40, count 2 2006.211.08:02:41.96#ibcon#*before return 0, iclass 40, count 2 2006.211.08:02:41.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:41.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:02:41.97#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:02:41.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:02:41.97#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:42.08#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:42.08#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:42.08#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:02:42.08#ibcon#first serial, iclass 40, count 0 2006.211.08:02:42.08#ibcon#enter sib2, iclass 40, count 0 2006.211.08:02:42.08#ibcon#flushed, iclass 40, count 0 2006.211.08:02:42.08#ibcon#about to write, iclass 40, count 0 2006.211.08:02:42.08#ibcon#wrote, iclass 40, count 0 2006.211.08:02:42.08#ibcon#about to read 3, iclass 40, count 0 2006.211.08:02:42.10#ibcon#read 3, iclass 40, count 0 2006.211.08:02:42.10#ibcon#about to read 4, iclass 40, count 0 2006.211.08:02:42.10#ibcon#read 4, iclass 40, count 0 2006.211.08:02:42.10#ibcon#about to read 5, iclass 40, count 0 2006.211.08:02:42.10#ibcon#read 5, iclass 40, count 0 2006.211.08:02:42.10#ibcon#about to read 6, iclass 40, count 0 2006.211.08:02:42.10#ibcon#read 6, iclass 40, count 0 2006.211.08:02:42.10#ibcon#end of sib2, iclass 40, count 0 2006.211.08:02:42.10#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:02:42.10#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:02:42.11#ibcon#[27=USB\r\n] 2006.211.08:02:42.11#ibcon#*before write, iclass 40, count 0 2006.211.08:02:42.11#ibcon#enter sib2, iclass 40, count 0 2006.211.08:02:42.11#ibcon#flushed, iclass 40, count 0 2006.211.08:02:42.11#ibcon#about to write, iclass 40, count 0 2006.211.08:02:42.11#ibcon#wrote, iclass 40, count 0 2006.211.08:02:42.11#ibcon#about to read 3, iclass 40, count 0 2006.211.08:02:42.13#ibcon#read 3, iclass 40, count 0 2006.211.08:02:42.13#ibcon#about to read 4, iclass 40, count 0 2006.211.08:02:42.13#ibcon#read 4, iclass 40, count 0 2006.211.08:02:42.13#ibcon#about to read 5, iclass 40, count 0 2006.211.08:02:42.13#ibcon#read 5, iclass 40, count 0 2006.211.08:02:42.13#ibcon#about to read 6, iclass 40, count 0 2006.211.08:02:42.13#ibcon#read 6, iclass 40, count 0 2006.211.08:02:42.13#ibcon#end of sib2, iclass 40, count 0 2006.211.08:02:42.13#ibcon#*after write, iclass 40, count 0 2006.211.08:02:42.13#ibcon#*before return 0, iclass 40, count 0 2006.211.08:02:42.14#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:42.14#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:02:42.14#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:02:42.14#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:02:42.14$vc4f8/vabw=wide 2006.211.08:02:42.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:02:42.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:02:42.14#ibcon#ireg 8 cls_cnt 0 2006.211.08:02:42.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:42.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:42.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:42.14#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:02:42.14#ibcon#first serial, iclass 4, count 0 2006.211.08:02:42.14#ibcon#enter sib2, iclass 4, count 0 2006.211.08:02:42.14#ibcon#flushed, iclass 4, count 0 2006.211.08:02:42.14#ibcon#about to write, iclass 4, count 0 2006.211.08:02:42.14#ibcon#wrote, iclass 4, count 0 2006.211.08:02:42.14#ibcon#about to read 3, iclass 4, count 0 2006.211.08:02:42.15#ibcon#read 3, iclass 4, count 0 2006.211.08:02:42.15#ibcon#about to read 4, iclass 4, count 0 2006.211.08:02:42.15#ibcon#read 4, iclass 4, count 0 2006.211.08:02:42.15#ibcon#about to read 5, iclass 4, count 0 2006.211.08:02:42.15#ibcon#read 5, iclass 4, count 0 2006.211.08:02:42.15#ibcon#about to read 6, iclass 4, count 0 2006.211.08:02:42.15#ibcon#read 6, iclass 4, count 0 2006.211.08:02:42.15#ibcon#end of sib2, iclass 4, count 0 2006.211.08:02:42.15#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:02:42.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:02:42.16#ibcon#[25=BW32\r\n] 2006.211.08:02:42.16#ibcon#*before write, iclass 4, count 0 2006.211.08:02:42.16#ibcon#enter sib2, iclass 4, count 0 2006.211.08:02:42.16#ibcon#flushed, iclass 4, count 0 2006.211.08:02:42.16#ibcon#about to write, iclass 4, count 0 2006.211.08:02:42.16#ibcon#wrote, iclass 4, count 0 2006.211.08:02:42.16#ibcon#about to read 3, iclass 4, count 0 2006.211.08:02:42.18#ibcon#read 3, iclass 4, count 0 2006.211.08:02:42.18#ibcon#about to read 4, iclass 4, count 0 2006.211.08:02:42.18#ibcon#read 4, iclass 4, count 0 2006.211.08:02:42.18#ibcon#about to read 5, iclass 4, count 0 2006.211.08:02:42.18#ibcon#read 5, iclass 4, count 0 2006.211.08:02:42.18#ibcon#about to read 6, iclass 4, count 0 2006.211.08:02:42.18#ibcon#read 6, iclass 4, count 0 2006.211.08:02:42.18#ibcon#end of sib2, iclass 4, count 0 2006.211.08:02:42.18#ibcon#*after write, iclass 4, count 0 2006.211.08:02:42.18#ibcon#*before return 0, iclass 4, count 0 2006.211.08:02:42.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:42.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:02:42.19#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:02:42.19#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:02:42.19$vc4f8/vbbw=wide 2006.211.08:02:42.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.08:02:42.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.08:02:42.19#ibcon#ireg 8 cls_cnt 0 2006.211.08:02:42.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:02:42.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:02:42.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:02:42.25#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:02:42.25#ibcon#first serial, iclass 6, count 0 2006.211.08:02:42.25#ibcon#enter sib2, iclass 6, count 0 2006.211.08:02:42.25#ibcon#flushed, iclass 6, count 0 2006.211.08:02:42.25#ibcon#about to write, iclass 6, count 0 2006.211.08:02:42.25#ibcon#wrote, iclass 6, count 0 2006.211.08:02:42.25#ibcon#about to read 3, iclass 6, count 0 2006.211.08:02:42.27#ibcon#read 3, iclass 6, count 0 2006.211.08:02:42.27#ibcon#about to read 4, iclass 6, count 0 2006.211.08:02:42.27#ibcon#read 4, iclass 6, count 0 2006.211.08:02:42.27#ibcon#about to read 5, iclass 6, count 0 2006.211.08:02:42.27#ibcon#read 5, iclass 6, count 0 2006.211.08:02:42.27#ibcon#about to read 6, iclass 6, count 0 2006.211.08:02:42.27#ibcon#read 6, iclass 6, count 0 2006.211.08:02:42.27#ibcon#end of sib2, iclass 6, count 0 2006.211.08:02:42.27#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:02:42.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:02:42.28#ibcon#[27=BW32\r\n] 2006.211.08:02:42.28#ibcon#*before write, iclass 6, count 0 2006.211.08:02:42.28#ibcon#enter sib2, iclass 6, count 0 2006.211.08:02:42.28#ibcon#flushed, iclass 6, count 0 2006.211.08:02:42.28#ibcon#about to write, iclass 6, count 0 2006.211.08:02:42.28#ibcon#wrote, iclass 6, count 0 2006.211.08:02:42.28#ibcon#about to read 3, iclass 6, count 0 2006.211.08:02:42.30#ibcon#read 3, iclass 6, count 0 2006.211.08:02:42.30#ibcon#about to read 4, iclass 6, count 0 2006.211.08:02:42.30#ibcon#read 4, iclass 6, count 0 2006.211.08:02:42.30#ibcon#about to read 5, iclass 6, count 0 2006.211.08:02:42.30#ibcon#read 5, iclass 6, count 0 2006.211.08:02:42.30#ibcon#about to read 6, iclass 6, count 0 2006.211.08:02:42.30#ibcon#read 6, iclass 6, count 0 2006.211.08:02:42.30#ibcon#end of sib2, iclass 6, count 0 2006.211.08:02:42.30#ibcon#*after write, iclass 6, count 0 2006.211.08:02:42.30#ibcon#*before return 0, iclass 6, count 0 2006.211.08:02:42.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:02:42.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:02:42.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:02:42.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:02:42.31$4f8m12a/ifd4f 2006.211.08:02:42.31$ifd4f/lo= 2006.211.08:02:42.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:02:42.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:02:42.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:02:42.31$ifd4f/patch= 2006.211.08:02:42.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:02:42.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:02:42.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:02:42.31$4f8m12a/"form=m,16.000,1:2 2006.211.08:02:42.31$4f8m12a/"tpicd 2006.211.08:02:42.31$4f8m12a/echo=off 2006.211.08:02:42.31$4f8m12a/xlog=off 2006.211.08:02:42.31:!2006.211.08:03:40 2006.211.08:03:14.13#trakl#Source acquired 2006.211.08:03:16.14#flagr#flagr/antenna,acquired 2006.211.08:03:40.02:preob 2006.211.08:03:41.14/onsource/TRACKING 2006.211.08:03:41.14:!2006.211.08:03:50 2006.211.08:03:48.13#trakl#Off source 2006.211.08:03:48.13?ERROR st -7 Antenna off-source! 2006.211.08:03:48.13#trakl#az 13.397 el 40.897 azerr*cos(el) -0.0179 elerr -0.0012 2006.211.08:03:48.14#flagr#flagr/antenna,off-source 2006.211.08:03:50.02:data_valid=on 2006.211.08:03:50.02:midob 2006.211.08:03:51.13?ERROR an -103 Pointing computer tracking errors are too large. 2006.211.08:03:51.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.211.08:03:51.14/onsource/SLEWING 2006.211.08:03:51.14/wx/24.74,1010.0,79 2006.211.08:03:51.34/cable/+6.4376E-03 2006.211.08:03:52.43/va/01,08,usb,yes,28,30 2006.211.08:03:52.43/va/02,07,usb,yes,29,30 2006.211.08:03:52.43/va/03,06,usb,yes,30,30 2006.211.08:03:52.43/va/04,07,usb,yes,29,32 2006.211.08:03:52.43/va/05,07,usb,yes,32,33 2006.211.08:03:52.43/va/06,06,usb,yes,31,31 2006.211.08:03:52.43/va/07,06,usb,yes,31,31 2006.211.08:03:52.43/va/08,07,usb,yes,30,29 2006.211.08:03:52.66/valo/01,532.99,yes,locked 2006.211.08:03:52.66/valo/02,572.99,yes,locked 2006.211.08:03:52.66/valo/03,672.99,yes,locked 2006.211.08:03:52.66/valo/04,832.99,yes,locked 2006.211.08:03:52.66/valo/05,652.99,yes,locked 2006.211.08:03:52.66/valo/06,772.99,yes,locked 2006.211.08:03:52.66/valo/07,832.99,yes,locked 2006.211.08:03:52.66/valo/08,852.99,yes,locked 2006.211.08:03:53.75/vb/01,04,usb,yes,28,27 2006.211.08:03:53.75/vb/02,04,usb,yes,30,31 2006.211.08:03:53.75/vb/03,03,usb,yes,33,37 2006.211.08:03:53.75/vb/04,03,usb,yes,34,34 2006.211.08:03:53.75/vb/05,03,usb,yes,32,36 2006.211.08:03:53.75/vb/06,03,usb,yes,33,36 2006.211.08:03:53.75/vb/07,04,usb,yes,29,28 2006.211.08:03:53.75/vb/08,03,usb,yes,33,36 2006.211.08:03:53.98/vblo/01,632.99,yes,locked 2006.211.08:03:53.98/vblo/02,640.99,yes,locked 2006.211.08:03:53.98/vblo/03,656.99,yes,locked 2006.211.08:03:53.98/vblo/04,712.99,yes,locked 2006.211.08:03:53.98/vblo/05,744.99,yes,locked 2006.211.08:03:53.98/vblo/06,752.99,yes,locked 2006.211.08:03:53.98/vblo/07,734.99,yes,locked 2006.211.08:03:53.98/vblo/08,744.99,yes,locked 2006.211.08:03:54.13/vabw/8 2006.211.08:03:54.28/vbbw/8 2006.211.08:03:54.37/xfe/off,on,12.0 2006.211.08:03:54.75/ifatt/23,28,28,28 2006.211.08:03:55.07/fmout-gps/S +4.45E-07 2006.211.08:03:55.12:!2006.211.08:04:50 2006.211.08:03:55.12#trakl#Source re-acquired 2006.211.08:03:56.13#flagr#flagr/antenna,re-acquired 2006.211.08:04:50.01:data_valid=off 2006.211.08:04:50.02:postob 2006.211.08:04:50.17/cable/+6.4378E-03 2006.211.08:04:50.17/wx/24.73,1010.0,78 2006.211.08:04:51.07/fmout-gps/S +4.44E-07 2006.211.08:04:51.07:scan_name=211-0805,k06211,60 2006.211.08:04:51.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.211.08:04:52.13#flagr#flagr/antenna,new-source 2006.211.08:04:52.14:checkk5 2006.211.08:04:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:04:52.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:04:53.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:04:53.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:04:53.83/chk_obsdata//k5ts1/T2110803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:04:54.17/chk_obsdata//k5ts2/T2110803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:04:54.50/chk_obsdata//k5ts3/T2110803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:04:54.83/chk_obsdata//k5ts4/T2110803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:04:55.48/k5log//k5ts1_log_newline 2006.211.08:04:56.14/k5log//k5ts2_log_newline 2006.211.08:04:56.80/k5log//k5ts3_log_newline 2006.211.08:04:57.46/k5log//k5ts4_log_newline 2006.211.08:04:57.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:04:57.49:4f8m12a=2 2006.211.08:04:57.49$4f8m12a/echo=on 2006.211.08:04:57.49$4f8m12a/pcalon 2006.211.08:04:57.49$pcalon/"no phase cal control is implemented here 2006.211.08:04:57.49$4f8m12a/"tpicd=stop 2006.211.08:04:57.49$4f8m12a/vc4f8 2006.211.08:04:57.49$vc4f8/valo=1,532.99 2006.211.08:04:57.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.08:04:57.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.08:04:57.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:57.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:04:57.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:04:57.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:04:57.49#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:04:57.49#ibcon#first serial, iclass 33, count 0 2006.211.08:04:57.49#ibcon#enter sib2, iclass 33, count 0 2006.211.08:04:57.49#ibcon#flushed, iclass 33, count 0 2006.211.08:04:57.49#ibcon#about to write, iclass 33, count 0 2006.211.08:04:57.49#ibcon#wrote, iclass 33, count 0 2006.211.08:04:57.49#ibcon#about to read 3, iclass 33, count 0 2006.211.08:04:57.50#ibcon#read 3, iclass 33, count 0 2006.211.08:04:57.50#ibcon#about to read 4, iclass 33, count 0 2006.211.08:04:57.50#ibcon#read 4, iclass 33, count 0 2006.211.08:04:57.50#ibcon#about to read 5, iclass 33, count 0 2006.211.08:04:57.50#ibcon#read 5, iclass 33, count 0 2006.211.08:04:57.50#ibcon#about to read 6, iclass 33, count 0 2006.211.08:04:57.50#ibcon#read 6, iclass 33, count 0 2006.211.08:04:57.50#ibcon#end of sib2, iclass 33, count 0 2006.211.08:04:57.50#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:04:57.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:04:57.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:04:57.50#ibcon#*before write, iclass 33, count 0 2006.211.08:04:57.50#ibcon#enter sib2, iclass 33, count 0 2006.211.08:04:57.50#ibcon#flushed, iclass 33, count 0 2006.211.08:04:57.50#ibcon#about to write, iclass 33, count 0 2006.211.08:04:57.50#ibcon#wrote, iclass 33, count 0 2006.211.08:04:57.50#ibcon#about to read 3, iclass 33, count 0 2006.211.08:04:57.55#ibcon#read 3, iclass 33, count 0 2006.211.08:04:57.55#ibcon#about to read 4, iclass 33, count 0 2006.211.08:04:57.55#ibcon#read 4, iclass 33, count 0 2006.211.08:04:57.55#ibcon#about to read 5, iclass 33, count 0 2006.211.08:04:57.55#ibcon#read 5, iclass 33, count 0 2006.211.08:04:57.55#ibcon#about to read 6, iclass 33, count 0 2006.211.08:04:57.55#ibcon#read 6, iclass 33, count 0 2006.211.08:04:57.55#ibcon#end of sib2, iclass 33, count 0 2006.211.08:04:57.55#ibcon#*after write, iclass 33, count 0 2006.211.08:04:57.55#ibcon#*before return 0, iclass 33, count 0 2006.211.08:04:57.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:04:57.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:04:57.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:04:57.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:04:57.55$vc4f8/va=1,8 2006.211.08:04:57.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:04:57.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:04:57.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:57.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:04:57.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:04:57.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:04:57.55#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:04:57.55#ibcon#first serial, iclass 35, count 2 2006.211.08:04:57.55#ibcon#enter sib2, iclass 35, count 2 2006.211.08:04:57.55#ibcon#flushed, iclass 35, count 2 2006.211.08:04:57.55#ibcon#about to write, iclass 35, count 2 2006.211.08:04:57.56#ibcon#wrote, iclass 35, count 2 2006.211.08:04:57.56#ibcon#about to read 3, iclass 35, count 2 2006.211.08:04:57.57#ibcon#read 3, iclass 35, count 2 2006.211.08:04:57.57#ibcon#about to read 4, iclass 35, count 2 2006.211.08:04:57.57#ibcon#read 4, iclass 35, count 2 2006.211.08:04:57.57#ibcon#about to read 5, iclass 35, count 2 2006.211.08:04:57.57#ibcon#read 5, iclass 35, count 2 2006.211.08:04:57.57#ibcon#about to read 6, iclass 35, count 2 2006.211.08:04:57.57#ibcon#read 6, iclass 35, count 2 2006.211.08:04:57.57#ibcon#end of sib2, iclass 35, count 2 2006.211.08:04:57.57#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:04:57.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:04:57.57#ibcon#[25=AT01-08\r\n] 2006.211.08:04:57.57#ibcon#*before write, iclass 35, count 2 2006.211.08:04:57.57#ibcon#enter sib2, iclass 35, count 2 2006.211.08:04:57.57#ibcon#flushed, iclass 35, count 2 2006.211.08:04:57.57#ibcon#about to write, iclass 35, count 2 2006.211.08:04:57.57#ibcon#wrote, iclass 35, count 2 2006.211.08:04:57.57#ibcon#about to read 3, iclass 35, count 2 2006.211.08:04:57.60#ibcon#read 3, iclass 35, count 2 2006.211.08:04:57.60#ibcon#about to read 4, iclass 35, count 2 2006.211.08:04:57.60#ibcon#read 4, iclass 35, count 2 2006.211.08:04:57.60#ibcon#about to read 5, iclass 35, count 2 2006.211.08:04:57.60#ibcon#read 5, iclass 35, count 2 2006.211.08:04:57.60#ibcon#about to read 6, iclass 35, count 2 2006.211.08:04:57.60#ibcon#read 6, iclass 35, count 2 2006.211.08:04:57.60#ibcon#end of sib2, iclass 35, count 2 2006.211.08:04:57.60#ibcon#*after write, iclass 35, count 2 2006.211.08:04:57.60#ibcon#*before return 0, iclass 35, count 2 2006.211.08:04:57.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:04:57.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:04:57.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:04:57.60#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:57.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:04:57.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:04:57.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:04:57.72#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:04:57.72#ibcon#first serial, iclass 35, count 0 2006.211.08:04:57.72#ibcon#enter sib2, iclass 35, count 0 2006.211.08:04:57.72#ibcon#flushed, iclass 35, count 0 2006.211.08:04:57.72#ibcon#about to write, iclass 35, count 0 2006.211.08:04:57.72#ibcon#wrote, iclass 35, count 0 2006.211.08:04:57.72#ibcon#about to read 3, iclass 35, count 0 2006.211.08:04:57.74#ibcon#read 3, iclass 35, count 0 2006.211.08:04:57.74#ibcon#about to read 4, iclass 35, count 0 2006.211.08:04:57.74#ibcon#read 4, iclass 35, count 0 2006.211.08:04:57.74#ibcon#about to read 5, iclass 35, count 0 2006.211.08:04:57.74#ibcon#read 5, iclass 35, count 0 2006.211.08:04:57.74#ibcon#about to read 6, iclass 35, count 0 2006.211.08:04:57.74#ibcon#read 6, iclass 35, count 0 2006.211.08:04:57.74#ibcon#end of sib2, iclass 35, count 0 2006.211.08:04:57.74#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:04:57.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:04:57.74#ibcon#[25=USB\r\n] 2006.211.08:04:57.74#ibcon#*before write, iclass 35, count 0 2006.211.08:04:57.74#ibcon#enter sib2, iclass 35, count 0 2006.211.08:04:57.74#ibcon#flushed, iclass 35, count 0 2006.211.08:04:57.74#ibcon#about to write, iclass 35, count 0 2006.211.08:04:57.74#ibcon#wrote, iclass 35, count 0 2006.211.08:04:57.74#ibcon#about to read 3, iclass 35, count 0 2006.211.08:04:57.77#ibcon#read 3, iclass 35, count 0 2006.211.08:04:57.77#ibcon#about to read 4, iclass 35, count 0 2006.211.08:04:57.77#ibcon#read 4, iclass 35, count 0 2006.211.08:04:57.77#ibcon#about to read 5, iclass 35, count 0 2006.211.08:04:57.77#ibcon#read 5, iclass 35, count 0 2006.211.08:04:57.77#ibcon#about to read 6, iclass 35, count 0 2006.211.08:04:57.77#ibcon#read 6, iclass 35, count 0 2006.211.08:04:57.77#ibcon#end of sib2, iclass 35, count 0 2006.211.08:04:57.77#ibcon#*after write, iclass 35, count 0 2006.211.08:04:57.77#ibcon#*before return 0, iclass 35, count 0 2006.211.08:04:57.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:04:57.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:04:57.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:04:57.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:04:57.77$vc4f8/valo=2,572.99 2006.211.08:04:57.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:04:57.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:04:57.77#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:57.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:04:57.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:04:57.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:04:57.77#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:04:57.77#ibcon#first serial, iclass 37, count 0 2006.211.08:04:57.77#ibcon#enter sib2, iclass 37, count 0 2006.211.08:04:57.77#ibcon#flushed, iclass 37, count 0 2006.211.08:04:57.78#ibcon#about to write, iclass 37, count 0 2006.211.08:04:57.78#ibcon#wrote, iclass 37, count 0 2006.211.08:04:57.78#ibcon#about to read 3, iclass 37, count 0 2006.211.08:04:57.79#ibcon#read 3, iclass 37, count 0 2006.211.08:04:57.79#ibcon#about to read 4, iclass 37, count 0 2006.211.08:04:57.79#ibcon#read 4, iclass 37, count 0 2006.211.08:04:57.79#ibcon#about to read 5, iclass 37, count 0 2006.211.08:04:57.79#ibcon#read 5, iclass 37, count 0 2006.211.08:04:57.79#ibcon#about to read 6, iclass 37, count 0 2006.211.08:04:57.79#ibcon#read 6, iclass 37, count 0 2006.211.08:04:57.79#ibcon#end of sib2, iclass 37, count 0 2006.211.08:04:57.79#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:04:57.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:04:57.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:04:57.79#ibcon#*before write, iclass 37, count 0 2006.211.08:04:57.79#ibcon#enter sib2, iclass 37, count 0 2006.211.08:04:57.79#ibcon#flushed, iclass 37, count 0 2006.211.08:04:57.79#ibcon#about to write, iclass 37, count 0 2006.211.08:04:57.79#ibcon#wrote, iclass 37, count 0 2006.211.08:04:57.79#ibcon#about to read 3, iclass 37, count 0 2006.211.08:04:57.83#ibcon#read 3, iclass 37, count 0 2006.211.08:04:57.83#ibcon#about to read 4, iclass 37, count 0 2006.211.08:04:57.83#ibcon#read 4, iclass 37, count 0 2006.211.08:04:57.83#ibcon#about to read 5, iclass 37, count 0 2006.211.08:04:57.83#ibcon#read 5, iclass 37, count 0 2006.211.08:04:57.83#ibcon#about to read 6, iclass 37, count 0 2006.211.08:04:57.83#ibcon#read 6, iclass 37, count 0 2006.211.08:04:57.83#ibcon#end of sib2, iclass 37, count 0 2006.211.08:04:57.83#ibcon#*after write, iclass 37, count 0 2006.211.08:04:57.83#ibcon#*before return 0, iclass 37, count 0 2006.211.08:04:57.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:04:57.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:04:57.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:04:57.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:04:57.83$vc4f8/va=2,7 2006.211.08:04:57.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:04:57.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:04:57.83#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:57.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:04:57.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:04:57.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:04:57.89#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:04:57.89#ibcon#first serial, iclass 39, count 2 2006.211.08:04:57.89#ibcon#enter sib2, iclass 39, count 2 2006.211.08:04:57.89#ibcon#flushed, iclass 39, count 2 2006.211.08:04:57.89#ibcon#about to write, iclass 39, count 2 2006.211.08:04:57.89#ibcon#wrote, iclass 39, count 2 2006.211.08:04:57.89#ibcon#about to read 3, iclass 39, count 2 2006.211.08:04:57.91#ibcon#read 3, iclass 39, count 2 2006.211.08:04:57.91#ibcon#about to read 4, iclass 39, count 2 2006.211.08:04:57.91#ibcon#read 4, iclass 39, count 2 2006.211.08:04:57.91#ibcon#about to read 5, iclass 39, count 2 2006.211.08:04:57.91#ibcon#read 5, iclass 39, count 2 2006.211.08:04:57.91#ibcon#about to read 6, iclass 39, count 2 2006.211.08:04:57.91#ibcon#read 6, iclass 39, count 2 2006.211.08:04:57.91#ibcon#end of sib2, iclass 39, count 2 2006.211.08:04:57.91#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:04:57.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:04:57.91#ibcon#[25=AT02-07\r\n] 2006.211.08:04:57.91#ibcon#*before write, iclass 39, count 2 2006.211.08:04:57.91#ibcon#enter sib2, iclass 39, count 2 2006.211.08:04:57.91#ibcon#flushed, iclass 39, count 2 2006.211.08:04:57.91#ibcon#about to write, iclass 39, count 2 2006.211.08:04:57.91#ibcon#wrote, iclass 39, count 2 2006.211.08:04:57.91#ibcon#about to read 3, iclass 39, count 2 2006.211.08:04:57.94#ibcon#read 3, iclass 39, count 2 2006.211.08:04:57.94#ibcon#about to read 4, iclass 39, count 2 2006.211.08:04:57.94#ibcon#read 4, iclass 39, count 2 2006.211.08:04:57.94#ibcon#about to read 5, iclass 39, count 2 2006.211.08:04:57.94#ibcon#read 5, iclass 39, count 2 2006.211.08:04:57.94#ibcon#about to read 6, iclass 39, count 2 2006.211.08:04:57.94#ibcon#read 6, iclass 39, count 2 2006.211.08:04:57.94#ibcon#end of sib2, iclass 39, count 2 2006.211.08:04:57.94#ibcon#*after write, iclass 39, count 2 2006.211.08:04:57.94#ibcon#*before return 0, iclass 39, count 2 2006.211.08:04:57.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:04:57.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:04:57.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:04:57.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:57.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:04:58.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:04:58.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:04:58.06#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:04:58.06#ibcon#first serial, iclass 39, count 0 2006.211.08:04:58.06#ibcon#enter sib2, iclass 39, count 0 2006.211.08:04:58.06#ibcon#flushed, iclass 39, count 0 2006.211.08:04:58.06#ibcon#about to write, iclass 39, count 0 2006.211.08:04:58.06#ibcon#wrote, iclass 39, count 0 2006.211.08:04:58.06#ibcon#about to read 3, iclass 39, count 0 2006.211.08:04:58.08#ibcon#read 3, iclass 39, count 0 2006.211.08:04:58.08#ibcon#about to read 4, iclass 39, count 0 2006.211.08:04:58.08#ibcon#read 4, iclass 39, count 0 2006.211.08:04:58.08#ibcon#about to read 5, iclass 39, count 0 2006.211.08:04:58.08#ibcon#read 5, iclass 39, count 0 2006.211.08:04:58.08#ibcon#about to read 6, iclass 39, count 0 2006.211.08:04:58.08#ibcon#read 6, iclass 39, count 0 2006.211.08:04:58.08#ibcon#end of sib2, iclass 39, count 0 2006.211.08:04:58.08#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:04:58.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:04:58.08#ibcon#[25=USB\r\n] 2006.211.08:04:58.08#ibcon#*before write, iclass 39, count 0 2006.211.08:04:58.08#ibcon#enter sib2, iclass 39, count 0 2006.211.08:04:58.08#ibcon#flushed, iclass 39, count 0 2006.211.08:04:58.08#ibcon#about to write, iclass 39, count 0 2006.211.08:04:58.08#ibcon#wrote, iclass 39, count 0 2006.211.08:04:58.08#ibcon#about to read 3, iclass 39, count 0 2006.211.08:04:58.11#ibcon#read 3, iclass 39, count 0 2006.211.08:04:58.11#ibcon#about to read 4, iclass 39, count 0 2006.211.08:04:58.11#ibcon#read 4, iclass 39, count 0 2006.211.08:04:58.11#ibcon#about to read 5, iclass 39, count 0 2006.211.08:04:58.11#ibcon#read 5, iclass 39, count 0 2006.211.08:04:58.11#ibcon#about to read 6, iclass 39, count 0 2006.211.08:04:58.11#ibcon#read 6, iclass 39, count 0 2006.211.08:04:58.11#ibcon#end of sib2, iclass 39, count 0 2006.211.08:04:58.11#ibcon#*after write, iclass 39, count 0 2006.211.08:04:58.11#ibcon#*before return 0, iclass 39, count 0 2006.211.08:04:58.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:04:58.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:04:58.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:04:58.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:04:58.11$vc4f8/valo=3,672.99 2006.211.08:04:58.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:04:58.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:04:58.11#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:58.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:04:58.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:04:58.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:04:58.11#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:04:58.11#ibcon#first serial, iclass 3, count 0 2006.211.08:04:58.11#ibcon#enter sib2, iclass 3, count 0 2006.211.08:04:58.11#ibcon#flushed, iclass 3, count 0 2006.211.08:04:58.12#ibcon#about to write, iclass 3, count 0 2006.211.08:04:58.12#ibcon#wrote, iclass 3, count 0 2006.211.08:04:58.12#ibcon#about to read 3, iclass 3, count 0 2006.211.08:04:58.13#ibcon#read 3, iclass 3, count 0 2006.211.08:04:58.13#ibcon#about to read 4, iclass 3, count 0 2006.211.08:04:58.13#ibcon#read 4, iclass 3, count 0 2006.211.08:04:58.13#ibcon#about to read 5, iclass 3, count 0 2006.211.08:04:58.13#ibcon#read 5, iclass 3, count 0 2006.211.08:04:58.13#ibcon#about to read 6, iclass 3, count 0 2006.211.08:04:58.13#ibcon#read 6, iclass 3, count 0 2006.211.08:04:58.13#ibcon#end of sib2, iclass 3, count 0 2006.211.08:04:58.13#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:04:58.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:04:58.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:04:58.13#ibcon#*before write, iclass 3, count 0 2006.211.08:04:58.13#ibcon#enter sib2, iclass 3, count 0 2006.211.08:04:58.13#ibcon#flushed, iclass 3, count 0 2006.211.08:04:58.13#ibcon#about to write, iclass 3, count 0 2006.211.08:04:58.13#ibcon#wrote, iclass 3, count 0 2006.211.08:04:58.13#ibcon#about to read 3, iclass 3, count 0 2006.211.08:04:58.17#ibcon#read 3, iclass 3, count 0 2006.211.08:04:58.17#ibcon#about to read 4, iclass 3, count 0 2006.211.08:04:58.17#ibcon#read 4, iclass 3, count 0 2006.211.08:04:58.17#ibcon#about to read 5, iclass 3, count 0 2006.211.08:04:58.17#ibcon#read 5, iclass 3, count 0 2006.211.08:04:58.17#ibcon#about to read 6, iclass 3, count 0 2006.211.08:04:58.17#ibcon#read 6, iclass 3, count 0 2006.211.08:04:58.17#ibcon#end of sib2, iclass 3, count 0 2006.211.08:04:58.17#ibcon#*after write, iclass 3, count 0 2006.211.08:04:58.17#ibcon#*before return 0, iclass 3, count 0 2006.211.08:04:58.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:04:58.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:04:58.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:04:58.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:04:58.17$vc4f8/va=3,6 2006.211.08:04:58.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:04:58.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:04:58.17#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:58.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:04:58.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:04:58.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:04:58.23#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:04:58.23#ibcon#first serial, iclass 5, count 2 2006.211.08:04:58.23#ibcon#enter sib2, iclass 5, count 2 2006.211.08:04:58.23#ibcon#flushed, iclass 5, count 2 2006.211.08:04:58.23#ibcon#about to write, iclass 5, count 2 2006.211.08:04:58.23#ibcon#wrote, iclass 5, count 2 2006.211.08:04:58.23#ibcon#about to read 3, iclass 5, count 2 2006.211.08:04:58.25#ibcon#read 3, iclass 5, count 2 2006.211.08:04:58.25#ibcon#about to read 4, iclass 5, count 2 2006.211.08:04:58.25#ibcon#read 4, iclass 5, count 2 2006.211.08:04:58.25#ibcon#about to read 5, iclass 5, count 2 2006.211.08:04:58.25#ibcon#read 5, iclass 5, count 2 2006.211.08:04:58.25#ibcon#about to read 6, iclass 5, count 2 2006.211.08:04:58.25#ibcon#read 6, iclass 5, count 2 2006.211.08:04:58.25#ibcon#end of sib2, iclass 5, count 2 2006.211.08:04:58.25#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:04:58.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:04:58.25#ibcon#[25=AT03-06\r\n] 2006.211.08:04:58.25#ibcon#*before write, iclass 5, count 2 2006.211.08:04:58.25#ibcon#enter sib2, iclass 5, count 2 2006.211.08:04:58.25#ibcon#flushed, iclass 5, count 2 2006.211.08:04:58.25#ibcon#about to write, iclass 5, count 2 2006.211.08:04:58.25#ibcon#wrote, iclass 5, count 2 2006.211.08:04:58.25#ibcon#about to read 3, iclass 5, count 2 2006.211.08:04:58.28#ibcon#read 3, iclass 5, count 2 2006.211.08:04:58.28#ibcon#about to read 4, iclass 5, count 2 2006.211.08:04:58.28#ibcon#read 4, iclass 5, count 2 2006.211.08:04:58.28#ibcon#about to read 5, iclass 5, count 2 2006.211.08:04:58.28#ibcon#read 5, iclass 5, count 2 2006.211.08:04:58.28#ibcon#about to read 6, iclass 5, count 2 2006.211.08:04:58.28#ibcon#read 6, iclass 5, count 2 2006.211.08:04:58.28#ibcon#end of sib2, iclass 5, count 2 2006.211.08:04:58.28#ibcon#*after write, iclass 5, count 2 2006.211.08:04:58.28#ibcon#*before return 0, iclass 5, count 2 2006.211.08:04:58.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:04:58.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:04:58.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:04:58.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:58.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:04:58.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:04:58.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:04:58.40#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:04:58.40#ibcon#first serial, iclass 5, count 0 2006.211.08:04:58.40#ibcon#enter sib2, iclass 5, count 0 2006.211.08:04:58.40#ibcon#flushed, iclass 5, count 0 2006.211.08:04:58.40#ibcon#about to write, iclass 5, count 0 2006.211.08:04:58.40#ibcon#wrote, iclass 5, count 0 2006.211.08:04:58.40#ibcon#about to read 3, iclass 5, count 0 2006.211.08:04:58.42#ibcon#read 3, iclass 5, count 0 2006.211.08:04:58.42#ibcon#about to read 4, iclass 5, count 0 2006.211.08:04:58.42#ibcon#read 4, iclass 5, count 0 2006.211.08:04:58.42#ibcon#about to read 5, iclass 5, count 0 2006.211.08:04:58.42#ibcon#read 5, iclass 5, count 0 2006.211.08:04:58.42#ibcon#about to read 6, iclass 5, count 0 2006.211.08:04:58.42#ibcon#read 6, iclass 5, count 0 2006.211.08:04:58.42#ibcon#end of sib2, iclass 5, count 0 2006.211.08:04:58.42#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:04:58.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:04:58.42#ibcon#[25=USB\r\n] 2006.211.08:04:58.42#ibcon#*before write, iclass 5, count 0 2006.211.08:04:58.42#ibcon#enter sib2, iclass 5, count 0 2006.211.08:04:58.42#ibcon#flushed, iclass 5, count 0 2006.211.08:04:58.42#ibcon#about to write, iclass 5, count 0 2006.211.08:04:58.42#ibcon#wrote, iclass 5, count 0 2006.211.08:04:58.42#ibcon#about to read 3, iclass 5, count 0 2006.211.08:04:58.45#ibcon#read 3, iclass 5, count 0 2006.211.08:04:58.45#ibcon#about to read 4, iclass 5, count 0 2006.211.08:04:58.45#ibcon#read 4, iclass 5, count 0 2006.211.08:04:58.45#ibcon#about to read 5, iclass 5, count 0 2006.211.08:04:58.45#ibcon#read 5, iclass 5, count 0 2006.211.08:04:58.45#ibcon#about to read 6, iclass 5, count 0 2006.211.08:04:58.45#ibcon#read 6, iclass 5, count 0 2006.211.08:04:58.45#ibcon#end of sib2, iclass 5, count 0 2006.211.08:04:58.45#ibcon#*after write, iclass 5, count 0 2006.211.08:04:58.45#ibcon#*before return 0, iclass 5, count 0 2006.211.08:04:58.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:04:58.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:04:58.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:04:58.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:04:58.45$vc4f8/valo=4,832.99 2006.211.08:04:58.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:04:58.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:04:58.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:58.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:04:58.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:04:58.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:04:58.45#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:04:58.45#ibcon#first serial, iclass 7, count 0 2006.211.08:04:58.45#ibcon#enter sib2, iclass 7, count 0 2006.211.08:04:58.45#ibcon#flushed, iclass 7, count 0 2006.211.08:04:58.46#ibcon#about to write, iclass 7, count 0 2006.211.08:04:58.46#ibcon#wrote, iclass 7, count 0 2006.211.08:04:58.46#ibcon#about to read 3, iclass 7, count 0 2006.211.08:04:58.47#ibcon#read 3, iclass 7, count 0 2006.211.08:04:58.47#ibcon#about to read 4, iclass 7, count 0 2006.211.08:04:58.47#ibcon#read 4, iclass 7, count 0 2006.211.08:04:58.47#ibcon#about to read 5, iclass 7, count 0 2006.211.08:04:58.47#ibcon#read 5, iclass 7, count 0 2006.211.08:04:58.47#ibcon#about to read 6, iclass 7, count 0 2006.211.08:04:58.47#ibcon#read 6, iclass 7, count 0 2006.211.08:04:58.47#ibcon#end of sib2, iclass 7, count 0 2006.211.08:04:58.47#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:04:58.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:04:58.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:04:58.47#ibcon#*before write, iclass 7, count 0 2006.211.08:04:58.47#ibcon#enter sib2, iclass 7, count 0 2006.211.08:04:58.47#ibcon#flushed, iclass 7, count 0 2006.211.08:04:58.47#ibcon#about to write, iclass 7, count 0 2006.211.08:04:58.47#ibcon#wrote, iclass 7, count 0 2006.211.08:04:58.47#ibcon#about to read 3, iclass 7, count 0 2006.211.08:04:58.51#ibcon#read 3, iclass 7, count 0 2006.211.08:04:58.51#ibcon#about to read 4, iclass 7, count 0 2006.211.08:04:58.51#ibcon#read 4, iclass 7, count 0 2006.211.08:04:58.51#ibcon#about to read 5, iclass 7, count 0 2006.211.08:04:58.51#ibcon#read 5, iclass 7, count 0 2006.211.08:04:58.51#ibcon#about to read 6, iclass 7, count 0 2006.211.08:04:58.51#ibcon#read 6, iclass 7, count 0 2006.211.08:04:58.51#ibcon#end of sib2, iclass 7, count 0 2006.211.08:04:58.51#ibcon#*after write, iclass 7, count 0 2006.211.08:04:58.51#ibcon#*before return 0, iclass 7, count 0 2006.211.08:04:58.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:04:58.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:04:58.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:04:58.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:04:58.51$vc4f8/va=4,7 2006.211.08:04:58.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:04:58.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:04:58.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:58.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:04:58.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:04:58.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:04:58.57#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:04:58.57#ibcon#first serial, iclass 11, count 2 2006.211.08:04:58.57#ibcon#enter sib2, iclass 11, count 2 2006.211.08:04:58.57#ibcon#flushed, iclass 11, count 2 2006.211.08:04:58.57#ibcon#about to write, iclass 11, count 2 2006.211.08:04:58.57#ibcon#wrote, iclass 11, count 2 2006.211.08:04:58.57#ibcon#about to read 3, iclass 11, count 2 2006.211.08:04:58.59#ibcon#read 3, iclass 11, count 2 2006.211.08:04:58.59#ibcon#about to read 4, iclass 11, count 2 2006.211.08:04:58.59#ibcon#read 4, iclass 11, count 2 2006.211.08:04:58.59#ibcon#about to read 5, iclass 11, count 2 2006.211.08:04:58.59#ibcon#read 5, iclass 11, count 2 2006.211.08:04:58.59#ibcon#about to read 6, iclass 11, count 2 2006.211.08:04:58.59#ibcon#read 6, iclass 11, count 2 2006.211.08:04:58.59#ibcon#end of sib2, iclass 11, count 2 2006.211.08:04:58.59#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:04:58.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:04:58.59#ibcon#[25=AT04-07\r\n] 2006.211.08:04:58.59#ibcon#*before write, iclass 11, count 2 2006.211.08:04:58.59#ibcon#enter sib2, iclass 11, count 2 2006.211.08:04:58.59#ibcon#flushed, iclass 11, count 2 2006.211.08:04:58.59#ibcon#about to write, iclass 11, count 2 2006.211.08:04:58.59#ibcon#wrote, iclass 11, count 2 2006.211.08:04:58.59#ibcon#about to read 3, iclass 11, count 2 2006.211.08:04:58.62#ibcon#read 3, iclass 11, count 2 2006.211.08:04:58.62#ibcon#about to read 4, iclass 11, count 2 2006.211.08:04:58.62#ibcon#read 4, iclass 11, count 2 2006.211.08:04:58.62#ibcon#about to read 5, iclass 11, count 2 2006.211.08:04:58.62#ibcon#read 5, iclass 11, count 2 2006.211.08:04:58.62#ibcon#about to read 6, iclass 11, count 2 2006.211.08:04:58.62#ibcon#read 6, iclass 11, count 2 2006.211.08:04:58.62#ibcon#end of sib2, iclass 11, count 2 2006.211.08:04:58.62#ibcon#*after write, iclass 11, count 2 2006.211.08:04:58.62#ibcon#*before return 0, iclass 11, count 2 2006.211.08:04:58.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:04:58.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:04:58.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:04:58.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:58.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:04:58.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:04:58.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:04:58.74#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:04:58.74#ibcon#first serial, iclass 11, count 0 2006.211.08:04:58.74#ibcon#enter sib2, iclass 11, count 0 2006.211.08:04:58.74#ibcon#flushed, iclass 11, count 0 2006.211.08:04:58.74#ibcon#about to write, iclass 11, count 0 2006.211.08:04:58.74#ibcon#wrote, iclass 11, count 0 2006.211.08:04:58.74#ibcon#about to read 3, iclass 11, count 0 2006.211.08:04:58.76#ibcon#read 3, iclass 11, count 0 2006.211.08:04:58.76#ibcon#about to read 4, iclass 11, count 0 2006.211.08:04:58.76#ibcon#read 4, iclass 11, count 0 2006.211.08:04:58.76#ibcon#about to read 5, iclass 11, count 0 2006.211.08:04:58.76#ibcon#read 5, iclass 11, count 0 2006.211.08:04:58.76#ibcon#about to read 6, iclass 11, count 0 2006.211.08:04:58.76#ibcon#read 6, iclass 11, count 0 2006.211.08:04:58.76#ibcon#end of sib2, iclass 11, count 0 2006.211.08:04:58.76#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:04:58.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:04:58.76#ibcon#[25=USB\r\n] 2006.211.08:04:58.76#ibcon#*before write, iclass 11, count 0 2006.211.08:04:58.76#ibcon#enter sib2, iclass 11, count 0 2006.211.08:04:58.76#ibcon#flushed, iclass 11, count 0 2006.211.08:04:58.76#ibcon#about to write, iclass 11, count 0 2006.211.08:04:58.76#ibcon#wrote, iclass 11, count 0 2006.211.08:04:58.76#ibcon#about to read 3, iclass 11, count 0 2006.211.08:04:58.79#ibcon#read 3, iclass 11, count 0 2006.211.08:04:58.79#ibcon#about to read 4, iclass 11, count 0 2006.211.08:04:58.79#ibcon#read 4, iclass 11, count 0 2006.211.08:04:58.79#ibcon#about to read 5, iclass 11, count 0 2006.211.08:04:58.79#ibcon#read 5, iclass 11, count 0 2006.211.08:04:58.79#ibcon#about to read 6, iclass 11, count 0 2006.211.08:04:58.79#ibcon#read 6, iclass 11, count 0 2006.211.08:04:58.79#ibcon#end of sib2, iclass 11, count 0 2006.211.08:04:58.79#ibcon#*after write, iclass 11, count 0 2006.211.08:04:58.79#ibcon#*before return 0, iclass 11, count 0 2006.211.08:04:58.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:04:58.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:04:58.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:04:58.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:04:58.79$vc4f8/valo=5,652.99 2006.211.08:04:58.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:04:58.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:04:58.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:58.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:04:58.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:04:58.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:04:58.79#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:04:58.79#ibcon#first serial, iclass 13, count 0 2006.211.08:04:58.79#ibcon#enter sib2, iclass 13, count 0 2006.211.08:04:58.79#ibcon#flushed, iclass 13, count 0 2006.211.08:04:58.80#ibcon#about to write, iclass 13, count 0 2006.211.08:04:58.80#ibcon#wrote, iclass 13, count 0 2006.211.08:04:58.80#ibcon#about to read 3, iclass 13, count 0 2006.211.08:04:58.81#ibcon#read 3, iclass 13, count 0 2006.211.08:04:58.81#ibcon#about to read 4, iclass 13, count 0 2006.211.08:04:58.81#ibcon#read 4, iclass 13, count 0 2006.211.08:04:58.81#ibcon#about to read 5, iclass 13, count 0 2006.211.08:04:58.81#ibcon#read 5, iclass 13, count 0 2006.211.08:04:58.81#ibcon#about to read 6, iclass 13, count 0 2006.211.08:04:58.81#ibcon#read 6, iclass 13, count 0 2006.211.08:04:58.81#ibcon#end of sib2, iclass 13, count 0 2006.211.08:04:58.81#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:04:58.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:04:58.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:04:58.81#ibcon#*before write, iclass 13, count 0 2006.211.08:04:58.81#ibcon#enter sib2, iclass 13, count 0 2006.211.08:04:58.81#ibcon#flushed, iclass 13, count 0 2006.211.08:04:58.81#ibcon#about to write, iclass 13, count 0 2006.211.08:04:58.81#ibcon#wrote, iclass 13, count 0 2006.211.08:04:58.81#ibcon#about to read 3, iclass 13, count 0 2006.211.08:04:58.85#ibcon#read 3, iclass 13, count 0 2006.211.08:04:58.85#ibcon#about to read 4, iclass 13, count 0 2006.211.08:04:58.85#ibcon#read 4, iclass 13, count 0 2006.211.08:04:58.85#ibcon#about to read 5, iclass 13, count 0 2006.211.08:04:58.85#ibcon#read 5, iclass 13, count 0 2006.211.08:04:58.85#ibcon#about to read 6, iclass 13, count 0 2006.211.08:04:58.85#ibcon#read 6, iclass 13, count 0 2006.211.08:04:58.85#ibcon#end of sib2, iclass 13, count 0 2006.211.08:04:58.85#ibcon#*after write, iclass 13, count 0 2006.211.08:04:58.85#ibcon#*before return 0, iclass 13, count 0 2006.211.08:04:58.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:04:58.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:04:58.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:04:58.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:04:58.85$vc4f8/va=5,7 2006.211.08:04:58.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:04:58.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:04:58.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:58.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:04:58.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:04:58.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:04:58.91#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:04:58.91#ibcon#first serial, iclass 15, count 2 2006.211.08:04:58.91#ibcon#enter sib2, iclass 15, count 2 2006.211.08:04:58.91#ibcon#flushed, iclass 15, count 2 2006.211.08:04:58.91#ibcon#about to write, iclass 15, count 2 2006.211.08:04:58.91#ibcon#wrote, iclass 15, count 2 2006.211.08:04:58.91#ibcon#about to read 3, iclass 15, count 2 2006.211.08:04:58.93#ibcon#read 3, iclass 15, count 2 2006.211.08:04:58.93#ibcon#about to read 4, iclass 15, count 2 2006.211.08:04:58.93#ibcon#read 4, iclass 15, count 2 2006.211.08:04:58.93#ibcon#about to read 5, iclass 15, count 2 2006.211.08:04:58.93#ibcon#read 5, iclass 15, count 2 2006.211.08:04:58.93#ibcon#about to read 6, iclass 15, count 2 2006.211.08:04:58.93#ibcon#read 6, iclass 15, count 2 2006.211.08:04:58.93#ibcon#end of sib2, iclass 15, count 2 2006.211.08:04:58.93#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:04:58.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:04:58.93#ibcon#[25=AT05-07\r\n] 2006.211.08:04:58.93#ibcon#*before write, iclass 15, count 2 2006.211.08:04:58.93#ibcon#enter sib2, iclass 15, count 2 2006.211.08:04:58.93#ibcon#flushed, iclass 15, count 2 2006.211.08:04:58.93#ibcon#about to write, iclass 15, count 2 2006.211.08:04:58.93#ibcon#wrote, iclass 15, count 2 2006.211.08:04:58.93#ibcon#about to read 3, iclass 15, count 2 2006.211.08:04:58.96#ibcon#read 3, iclass 15, count 2 2006.211.08:04:58.96#ibcon#about to read 4, iclass 15, count 2 2006.211.08:04:58.96#ibcon#read 4, iclass 15, count 2 2006.211.08:04:58.96#ibcon#about to read 5, iclass 15, count 2 2006.211.08:04:58.96#ibcon#read 5, iclass 15, count 2 2006.211.08:04:58.96#ibcon#about to read 6, iclass 15, count 2 2006.211.08:04:58.96#ibcon#read 6, iclass 15, count 2 2006.211.08:04:58.96#ibcon#end of sib2, iclass 15, count 2 2006.211.08:04:58.96#ibcon#*after write, iclass 15, count 2 2006.211.08:04:58.96#ibcon#*before return 0, iclass 15, count 2 2006.211.08:04:58.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:04:58.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:04:58.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:04:58.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:58.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:04:59.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:04:59.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:04:59.08#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:04:59.08#ibcon#first serial, iclass 15, count 0 2006.211.08:04:59.08#ibcon#enter sib2, iclass 15, count 0 2006.211.08:04:59.08#ibcon#flushed, iclass 15, count 0 2006.211.08:04:59.08#ibcon#about to write, iclass 15, count 0 2006.211.08:04:59.08#ibcon#wrote, iclass 15, count 0 2006.211.08:04:59.08#ibcon#about to read 3, iclass 15, count 0 2006.211.08:04:59.10#ibcon#read 3, iclass 15, count 0 2006.211.08:04:59.10#ibcon#about to read 4, iclass 15, count 0 2006.211.08:04:59.10#ibcon#read 4, iclass 15, count 0 2006.211.08:04:59.10#ibcon#about to read 5, iclass 15, count 0 2006.211.08:04:59.10#ibcon#read 5, iclass 15, count 0 2006.211.08:04:59.10#ibcon#about to read 6, iclass 15, count 0 2006.211.08:04:59.10#ibcon#read 6, iclass 15, count 0 2006.211.08:04:59.10#ibcon#end of sib2, iclass 15, count 0 2006.211.08:04:59.10#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:04:59.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:04:59.10#ibcon#[25=USB\r\n] 2006.211.08:04:59.10#ibcon#*before write, iclass 15, count 0 2006.211.08:04:59.10#ibcon#enter sib2, iclass 15, count 0 2006.211.08:04:59.10#ibcon#flushed, iclass 15, count 0 2006.211.08:04:59.10#ibcon#about to write, iclass 15, count 0 2006.211.08:04:59.10#ibcon#wrote, iclass 15, count 0 2006.211.08:04:59.10#ibcon#about to read 3, iclass 15, count 0 2006.211.08:04:59.13#ibcon#read 3, iclass 15, count 0 2006.211.08:04:59.13#ibcon#about to read 4, iclass 15, count 0 2006.211.08:04:59.13#ibcon#read 4, iclass 15, count 0 2006.211.08:04:59.13#ibcon#about to read 5, iclass 15, count 0 2006.211.08:04:59.13#ibcon#read 5, iclass 15, count 0 2006.211.08:04:59.13#ibcon#about to read 6, iclass 15, count 0 2006.211.08:04:59.13#ibcon#read 6, iclass 15, count 0 2006.211.08:04:59.13#ibcon#end of sib2, iclass 15, count 0 2006.211.08:04:59.13#ibcon#*after write, iclass 15, count 0 2006.211.08:04:59.13#ibcon#*before return 0, iclass 15, count 0 2006.211.08:04:59.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:04:59.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:04:59.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:04:59.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:04:59.13$vc4f8/valo=6,772.99 2006.211.08:04:59.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:04:59.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:04:59.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:59.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:04:59.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:04:59.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:04:59.13#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:04:59.13#ibcon#first serial, iclass 17, count 0 2006.211.08:04:59.13#ibcon#enter sib2, iclass 17, count 0 2006.211.08:04:59.13#ibcon#flushed, iclass 17, count 0 2006.211.08:04:59.14#ibcon#about to write, iclass 17, count 0 2006.211.08:04:59.14#ibcon#wrote, iclass 17, count 0 2006.211.08:04:59.14#ibcon#about to read 3, iclass 17, count 0 2006.211.08:04:59.15#ibcon#read 3, iclass 17, count 0 2006.211.08:04:59.15#ibcon#about to read 4, iclass 17, count 0 2006.211.08:04:59.15#ibcon#read 4, iclass 17, count 0 2006.211.08:04:59.15#ibcon#about to read 5, iclass 17, count 0 2006.211.08:04:59.15#ibcon#read 5, iclass 17, count 0 2006.211.08:04:59.15#ibcon#about to read 6, iclass 17, count 0 2006.211.08:04:59.15#ibcon#read 6, iclass 17, count 0 2006.211.08:04:59.15#ibcon#end of sib2, iclass 17, count 0 2006.211.08:04:59.15#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:04:59.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:04:59.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:04:59.15#ibcon#*before write, iclass 17, count 0 2006.211.08:04:59.15#ibcon#enter sib2, iclass 17, count 0 2006.211.08:04:59.15#ibcon#flushed, iclass 17, count 0 2006.211.08:04:59.15#ibcon#about to write, iclass 17, count 0 2006.211.08:04:59.15#ibcon#wrote, iclass 17, count 0 2006.211.08:04:59.15#ibcon#about to read 3, iclass 17, count 0 2006.211.08:04:59.19#ibcon#read 3, iclass 17, count 0 2006.211.08:04:59.19#ibcon#about to read 4, iclass 17, count 0 2006.211.08:04:59.19#ibcon#read 4, iclass 17, count 0 2006.211.08:04:59.19#ibcon#about to read 5, iclass 17, count 0 2006.211.08:04:59.19#ibcon#read 5, iclass 17, count 0 2006.211.08:04:59.19#ibcon#about to read 6, iclass 17, count 0 2006.211.08:04:59.19#ibcon#read 6, iclass 17, count 0 2006.211.08:04:59.19#ibcon#end of sib2, iclass 17, count 0 2006.211.08:04:59.19#ibcon#*after write, iclass 17, count 0 2006.211.08:04:59.19#ibcon#*before return 0, iclass 17, count 0 2006.211.08:04:59.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:04:59.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:04:59.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:04:59.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:04:59.19$vc4f8/va=6,6 2006.211.08:04:59.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:04:59.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:04:59.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:59.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:04:59.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:04:59.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:04:59.25#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:04:59.25#ibcon#first serial, iclass 19, count 2 2006.211.08:04:59.25#ibcon#enter sib2, iclass 19, count 2 2006.211.08:04:59.25#ibcon#flushed, iclass 19, count 2 2006.211.08:04:59.25#ibcon#about to write, iclass 19, count 2 2006.211.08:04:59.25#ibcon#wrote, iclass 19, count 2 2006.211.08:04:59.25#ibcon#about to read 3, iclass 19, count 2 2006.211.08:04:59.27#ibcon#read 3, iclass 19, count 2 2006.211.08:04:59.27#ibcon#about to read 4, iclass 19, count 2 2006.211.08:04:59.27#ibcon#read 4, iclass 19, count 2 2006.211.08:04:59.27#ibcon#about to read 5, iclass 19, count 2 2006.211.08:04:59.27#ibcon#read 5, iclass 19, count 2 2006.211.08:04:59.27#ibcon#about to read 6, iclass 19, count 2 2006.211.08:04:59.27#ibcon#read 6, iclass 19, count 2 2006.211.08:04:59.27#ibcon#end of sib2, iclass 19, count 2 2006.211.08:04:59.27#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:04:59.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:04:59.27#ibcon#[25=AT06-06\r\n] 2006.211.08:04:59.27#ibcon#*before write, iclass 19, count 2 2006.211.08:04:59.27#ibcon#enter sib2, iclass 19, count 2 2006.211.08:04:59.27#ibcon#flushed, iclass 19, count 2 2006.211.08:04:59.27#ibcon#about to write, iclass 19, count 2 2006.211.08:04:59.27#ibcon#wrote, iclass 19, count 2 2006.211.08:04:59.27#ibcon#about to read 3, iclass 19, count 2 2006.211.08:04:59.30#ibcon#read 3, iclass 19, count 2 2006.211.08:04:59.30#ibcon#about to read 4, iclass 19, count 2 2006.211.08:04:59.30#ibcon#read 4, iclass 19, count 2 2006.211.08:04:59.30#ibcon#about to read 5, iclass 19, count 2 2006.211.08:04:59.30#ibcon#read 5, iclass 19, count 2 2006.211.08:04:59.30#ibcon#about to read 6, iclass 19, count 2 2006.211.08:04:59.30#ibcon#read 6, iclass 19, count 2 2006.211.08:04:59.30#ibcon#end of sib2, iclass 19, count 2 2006.211.08:04:59.30#ibcon#*after write, iclass 19, count 2 2006.211.08:04:59.30#ibcon#*before return 0, iclass 19, count 2 2006.211.08:04:59.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:04:59.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:04:59.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:04:59.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:59.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:04:59.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:04:59.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:04:59.42#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:04:59.42#ibcon#first serial, iclass 19, count 0 2006.211.08:04:59.42#ibcon#enter sib2, iclass 19, count 0 2006.211.08:04:59.42#ibcon#flushed, iclass 19, count 0 2006.211.08:04:59.42#ibcon#about to write, iclass 19, count 0 2006.211.08:04:59.42#ibcon#wrote, iclass 19, count 0 2006.211.08:04:59.42#ibcon#about to read 3, iclass 19, count 0 2006.211.08:04:59.44#ibcon#read 3, iclass 19, count 0 2006.211.08:04:59.44#ibcon#about to read 4, iclass 19, count 0 2006.211.08:04:59.44#ibcon#read 4, iclass 19, count 0 2006.211.08:04:59.44#ibcon#about to read 5, iclass 19, count 0 2006.211.08:04:59.44#ibcon#read 5, iclass 19, count 0 2006.211.08:04:59.44#ibcon#about to read 6, iclass 19, count 0 2006.211.08:04:59.44#ibcon#read 6, iclass 19, count 0 2006.211.08:04:59.44#ibcon#end of sib2, iclass 19, count 0 2006.211.08:04:59.44#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:04:59.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:04:59.44#ibcon#[25=USB\r\n] 2006.211.08:04:59.44#ibcon#*before write, iclass 19, count 0 2006.211.08:04:59.44#ibcon#enter sib2, iclass 19, count 0 2006.211.08:04:59.44#ibcon#flushed, iclass 19, count 0 2006.211.08:04:59.44#ibcon#about to write, iclass 19, count 0 2006.211.08:04:59.44#ibcon#wrote, iclass 19, count 0 2006.211.08:04:59.44#ibcon#about to read 3, iclass 19, count 0 2006.211.08:04:59.47#ibcon#read 3, iclass 19, count 0 2006.211.08:04:59.47#ibcon#about to read 4, iclass 19, count 0 2006.211.08:04:59.47#ibcon#read 4, iclass 19, count 0 2006.211.08:04:59.47#ibcon#about to read 5, iclass 19, count 0 2006.211.08:04:59.47#ibcon#read 5, iclass 19, count 0 2006.211.08:04:59.47#ibcon#about to read 6, iclass 19, count 0 2006.211.08:04:59.47#ibcon#read 6, iclass 19, count 0 2006.211.08:04:59.47#ibcon#end of sib2, iclass 19, count 0 2006.211.08:04:59.47#ibcon#*after write, iclass 19, count 0 2006.211.08:04:59.47#ibcon#*before return 0, iclass 19, count 0 2006.211.08:04:59.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:04:59.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:04:59.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:04:59.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:04:59.47$vc4f8/valo=7,832.99 2006.211.08:04:59.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:04:59.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:04:59.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:59.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:04:59.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:04:59.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:04:59.47#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:04:59.47#ibcon#first serial, iclass 21, count 0 2006.211.08:04:59.47#ibcon#enter sib2, iclass 21, count 0 2006.211.08:04:59.47#ibcon#flushed, iclass 21, count 0 2006.211.08:04:59.48#ibcon#about to write, iclass 21, count 0 2006.211.08:04:59.48#ibcon#wrote, iclass 21, count 0 2006.211.08:04:59.48#ibcon#about to read 3, iclass 21, count 0 2006.211.08:04:59.49#ibcon#read 3, iclass 21, count 0 2006.211.08:04:59.49#ibcon#about to read 4, iclass 21, count 0 2006.211.08:04:59.49#ibcon#read 4, iclass 21, count 0 2006.211.08:04:59.49#ibcon#about to read 5, iclass 21, count 0 2006.211.08:04:59.49#ibcon#read 5, iclass 21, count 0 2006.211.08:04:59.49#ibcon#about to read 6, iclass 21, count 0 2006.211.08:04:59.49#ibcon#read 6, iclass 21, count 0 2006.211.08:04:59.49#ibcon#end of sib2, iclass 21, count 0 2006.211.08:04:59.49#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:04:59.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:04:59.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:04:59.49#ibcon#*before write, iclass 21, count 0 2006.211.08:04:59.49#ibcon#enter sib2, iclass 21, count 0 2006.211.08:04:59.49#ibcon#flushed, iclass 21, count 0 2006.211.08:04:59.49#ibcon#about to write, iclass 21, count 0 2006.211.08:04:59.49#ibcon#wrote, iclass 21, count 0 2006.211.08:04:59.49#ibcon#about to read 3, iclass 21, count 0 2006.211.08:04:59.53#ibcon#read 3, iclass 21, count 0 2006.211.08:04:59.53#ibcon#about to read 4, iclass 21, count 0 2006.211.08:04:59.53#ibcon#read 4, iclass 21, count 0 2006.211.08:04:59.53#ibcon#about to read 5, iclass 21, count 0 2006.211.08:04:59.53#ibcon#read 5, iclass 21, count 0 2006.211.08:04:59.53#ibcon#about to read 6, iclass 21, count 0 2006.211.08:04:59.53#ibcon#read 6, iclass 21, count 0 2006.211.08:04:59.53#ibcon#end of sib2, iclass 21, count 0 2006.211.08:04:59.53#ibcon#*after write, iclass 21, count 0 2006.211.08:04:59.53#ibcon#*before return 0, iclass 21, count 0 2006.211.08:04:59.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:04:59.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:04:59.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:04:59.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:04:59.53$vc4f8/va=7,6 2006.211.08:04:59.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:04:59.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:04:59.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:59.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:04:59.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:04:59.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:04:59.59#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:04:59.59#ibcon#first serial, iclass 23, count 2 2006.211.08:04:59.59#ibcon#enter sib2, iclass 23, count 2 2006.211.08:04:59.59#ibcon#flushed, iclass 23, count 2 2006.211.08:04:59.59#ibcon#about to write, iclass 23, count 2 2006.211.08:04:59.59#ibcon#wrote, iclass 23, count 2 2006.211.08:04:59.59#ibcon#about to read 3, iclass 23, count 2 2006.211.08:04:59.61#ibcon#read 3, iclass 23, count 2 2006.211.08:04:59.61#ibcon#about to read 4, iclass 23, count 2 2006.211.08:04:59.61#ibcon#read 4, iclass 23, count 2 2006.211.08:04:59.61#ibcon#about to read 5, iclass 23, count 2 2006.211.08:04:59.61#ibcon#read 5, iclass 23, count 2 2006.211.08:04:59.61#ibcon#about to read 6, iclass 23, count 2 2006.211.08:04:59.61#ibcon#read 6, iclass 23, count 2 2006.211.08:04:59.61#ibcon#end of sib2, iclass 23, count 2 2006.211.08:04:59.61#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:04:59.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:04:59.61#ibcon#[25=AT07-06\r\n] 2006.211.08:04:59.61#ibcon#*before write, iclass 23, count 2 2006.211.08:04:59.61#ibcon#enter sib2, iclass 23, count 2 2006.211.08:04:59.61#ibcon#flushed, iclass 23, count 2 2006.211.08:04:59.61#ibcon#about to write, iclass 23, count 2 2006.211.08:04:59.61#ibcon#wrote, iclass 23, count 2 2006.211.08:04:59.61#ibcon#about to read 3, iclass 23, count 2 2006.211.08:04:59.64#ibcon#read 3, iclass 23, count 2 2006.211.08:04:59.64#ibcon#about to read 4, iclass 23, count 2 2006.211.08:04:59.64#ibcon#read 4, iclass 23, count 2 2006.211.08:04:59.64#ibcon#about to read 5, iclass 23, count 2 2006.211.08:04:59.64#ibcon#read 5, iclass 23, count 2 2006.211.08:04:59.64#ibcon#about to read 6, iclass 23, count 2 2006.211.08:04:59.64#ibcon#read 6, iclass 23, count 2 2006.211.08:04:59.64#ibcon#end of sib2, iclass 23, count 2 2006.211.08:04:59.64#ibcon#*after write, iclass 23, count 2 2006.211.08:04:59.64#ibcon#*before return 0, iclass 23, count 2 2006.211.08:04:59.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:04:59.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:04:59.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:04:59.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:59.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:04:59.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:04:59.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:04:59.76#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:04:59.76#ibcon#first serial, iclass 23, count 0 2006.211.08:04:59.76#ibcon#enter sib2, iclass 23, count 0 2006.211.08:04:59.76#ibcon#flushed, iclass 23, count 0 2006.211.08:04:59.76#ibcon#about to write, iclass 23, count 0 2006.211.08:04:59.76#ibcon#wrote, iclass 23, count 0 2006.211.08:04:59.76#ibcon#about to read 3, iclass 23, count 0 2006.211.08:04:59.78#ibcon#read 3, iclass 23, count 0 2006.211.08:04:59.78#ibcon#about to read 4, iclass 23, count 0 2006.211.08:04:59.78#ibcon#read 4, iclass 23, count 0 2006.211.08:04:59.78#ibcon#about to read 5, iclass 23, count 0 2006.211.08:04:59.78#ibcon#read 5, iclass 23, count 0 2006.211.08:04:59.78#ibcon#about to read 6, iclass 23, count 0 2006.211.08:04:59.78#ibcon#read 6, iclass 23, count 0 2006.211.08:04:59.78#ibcon#end of sib2, iclass 23, count 0 2006.211.08:04:59.78#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:04:59.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:04:59.78#ibcon#[25=USB\r\n] 2006.211.08:04:59.78#ibcon#*before write, iclass 23, count 0 2006.211.08:04:59.78#ibcon#enter sib2, iclass 23, count 0 2006.211.08:04:59.78#ibcon#flushed, iclass 23, count 0 2006.211.08:04:59.78#ibcon#about to write, iclass 23, count 0 2006.211.08:04:59.78#ibcon#wrote, iclass 23, count 0 2006.211.08:04:59.78#ibcon#about to read 3, iclass 23, count 0 2006.211.08:04:59.81#ibcon#read 3, iclass 23, count 0 2006.211.08:04:59.81#ibcon#about to read 4, iclass 23, count 0 2006.211.08:04:59.81#ibcon#read 4, iclass 23, count 0 2006.211.08:04:59.81#ibcon#about to read 5, iclass 23, count 0 2006.211.08:04:59.81#ibcon#read 5, iclass 23, count 0 2006.211.08:04:59.81#ibcon#about to read 6, iclass 23, count 0 2006.211.08:04:59.81#ibcon#read 6, iclass 23, count 0 2006.211.08:04:59.81#ibcon#end of sib2, iclass 23, count 0 2006.211.08:04:59.81#ibcon#*after write, iclass 23, count 0 2006.211.08:04:59.81#ibcon#*before return 0, iclass 23, count 0 2006.211.08:04:59.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:04:59.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:04:59.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:04:59.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:04:59.81$vc4f8/valo=8,852.99 2006.211.08:04:59.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:04:59.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:04:59.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:04:59.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:04:59.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:04:59.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:04:59.81#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:04:59.81#ibcon#first serial, iclass 25, count 0 2006.211.08:04:59.81#ibcon#enter sib2, iclass 25, count 0 2006.211.08:04:59.81#ibcon#flushed, iclass 25, count 0 2006.211.08:04:59.82#ibcon#about to write, iclass 25, count 0 2006.211.08:04:59.82#ibcon#wrote, iclass 25, count 0 2006.211.08:04:59.82#ibcon#about to read 3, iclass 25, count 0 2006.211.08:04:59.83#ibcon#read 3, iclass 25, count 0 2006.211.08:04:59.83#ibcon#about to read 4, iclass 25, count 0 2006.211.08:04:59.83#ibcon#read 4, iclass 25, count 0 2006.211.08:04:59.83#ibcon#about to read 5, iclass 25, count 0 2006.211.08:04:59.83#ibcon#read 5, iclass 25, count 0 2006.211.08:04:59.83#ibcon#about to read 6, iclass 25, count 0 2006.211.08:04:59.83#ibcon#read 6, iclass 25, count 0 2006.211.08:04:59.83#ibcon#end of sib2, iclass 25, count 0 2006.211.08:04:59.83#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:04:59.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:04:59.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:04:59.83#ibcon#*before write, iclass 25, count 0 2006.211.08:04:59.83#ibcon#enter sib2, iclass 25, count 0 2006.211.08:04:59.83#ibcon#flushed, iclass 25, count 0 2006.211.08:04:59.83#ibcon#about to write, iclass 25, count 0 2006.211.08:04:59.83#ibcon#wrote, iclass 25, count 0 2006.211.08:04:59.83#ibcon#about to read 3, iclass 25, count 0 2006.211.08:04:59.87#ibcon#read 3, iclass 25, count 0 2006.211.08:04:59.87#ibcon#about to read 4, iclass 25, count 0 2006.211.08:04:59.87#ibcon#read 4, iclass 25, count 0 2006.211.08:04:59.87#ibcon#about to read 5, iclass 25, count 0 2006.211.08:04:59.87#ibcon#read 5, iclass 25, count 0 2006.211.08:04:59.87#ibcon#about to read 6, iclass 25, count 0 2006.211.08:04:59.87#ibcon#read 6, iclass 25, count 0 2006.211.08:04:59.87#ibcon#end of sib2, iclass 25, count 0 2006.211.08:04:59.87#ibcon#*after write, iclass 25, count 0 2006.211.08:04:59.87#ibcon#*before return 0, iclass 25, count 0 2006.211.08:04:59.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:04:59.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:04:59.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:04:59.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:04:59.87$vc4f8/va=8,7 2006.211.08:04:59.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:04:59.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:04:59.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:04:59.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:04:59.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:04:59.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:04:59.93#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:04:59.93#ibcon#first serial, iclass 27, count 2 2006.211.08:04:59.93#ibcon#enter sib2, iclass 27, count 2 2006.211.08:04:59.93#ibcon#flushed, iclass 27, count 2 2006.211.08:04:59.93#ibcon#about to write, iclass 27, count 2 2006.211.08:04:59.93#ibcon#wrote, iclass 27, count 2 2006.211.08:04:59.93#ibcon#about to read 3, iclass 27, count 2 2006.211.08:04:59.95#ibcon#read 3, iclass 27, count 2 2006.211.08:04:59.95#ibcon#about to read 4, iclass 27, count 2 2006.211.08:04:59.95#ibcon#read 4, iclass 27, count 2 2006.211.08:04:59.95#ibcon#about to read 5, iclass 27, count 2 2006.211.08:04:59.95#ibcon#read 5, iclass 27, count 2 2006.211.08:04:59.95#ibcon#about to read 6, iclass 27, count 2 2006.211.08:04:59.95#ibcon#read 6, iclass 27, count 2 2006.211.08:04:59.95#ibcon#end of sib2, iclass 27, count 2 2006.211.08:04:59.95#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:04:59.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:04:59.95#ibcon#[25=AT08-07\r\n] 2006.211.08:04:59.95#ibcon#*before write, iclass 27, count 2 2006.211.08:04:59.95#ibcon#enter sib2, iclass 27, count 2 2006.211.08:04:59.95#ibcon#flushed, iclass 27, count 2 2006.211.08:04:59.95#ibcon#about to write, iclass 27, count 2 2006.211.08:04:59.95#ibcon#wrote, iclass 27, count 2 2006.211.08:04:59.95#ibcon#about to read 3, iclass 27, count 2 2006.211.08:04:59.98#ibcon#read 3, iclass 27, count 2 2006.211.08:04:59.98#ibcon#about to read 4, iclass 27, count 2 2006.211.08:04:59.98#ibcon#read 4, iclass 27, count 2 2006.211.08:04:59.98#ibcon#about to read 5, iclass 27, count 2 2006.211.08:04:59.98#ibcon#read 5, iclass 27, count 2 2006.211.08:04:59.98#ibcon#about to read 6, iclass 27, count 2 2006.211.08:04:59.98#ibcon#read 6, iclass 27, count 2 2006.211.08:04:59.98#ibcon#end of sib2, iclass 27, count 2 2006.211.08:04:59.98#ibcon#*after write, iclass 27, count 2 2006.211.08:04:59.98#ibcon#*before return 0, iclass 27, count 2 2006.211.08:04:59.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:04:59.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:04:59.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:04:59.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:04:59.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:05:00.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:05:00.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:05:00.10#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:05:00.10#ibcon#first serial, iclass 27, count 0 2006.211.08:05:00.10#ibcon#enter sib2, iclass 27, count 0 2006.211.08:05:00.10#ibcon#flushed, iclass 27, count 0 2006.211.08:05:00.10#ibcon#about to write, iclass 27, count 0 2006.211.08:05:00.10#ibcon#wrote, iclass 27, count 0 2006.211.08:05:00.10#ibcon#about to read 3, iclass 27, count 0 2006.211.08:05:00.12#ibcon#read 3, iclass 27, count 0 2006.211.08:05:00.12#ibcon#about to read 4, iclass 27, count 0 2006.211.08:05:00.12#ibcon#read 4, iclass 27, count 0 2006.211.08:05:00.12#ibcon#about to read 5, iclass 27, count 0 2006.211.08:05:00.12#ibcon#read 5, iclass 27, count 0 2006.211.08:05:00.12#ibcon#about to read 6, iclass 27, count 0 2006.211.08:05:00.12#ibcon#read 6, iclass 27, count 0 2006.211.08:05:00.12#ibcon#end of sib2, iclass 27, count 0 2006.211.08:05:00.12#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:05:00.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:05:00.12#ibcon#[25=USB\r\n] 2006.211.08:05:00.12#ibcon#*before write, iclass 27, count 0 2006.211.08:05:00.12#ibcon#enter sib2, iclass 27, count 0 2006.211.08:05:00.12#ibcon#flushed, iclass 27, count 0 2006.211.08:05:00.12#ibcon#about to write, iclass 27, count 0 2006.211.08:05:00.12#ibcon#wrote, iclass 27, count 0 2006.211.08:05:00.12#ibcon#about to read 3, iclass 27, count 0 2006.211.08:05:00.15#ibcon#read 3, iclass 27, count 0 2006.211.08:05:00.15#ibcon#about to read 4, iclass 27, count 0 2006.211.08:05:00.15#ibcon#read 4, iclass 27, count 0 2006.211.08:05:00.15#ibcon#about to read 5, iclass 27, count 0 2006.211.08:05:00.15#ibcon#read 5, iclass 27, count 0 2006.211.08:05:00.15#ibcon#about to read 6, iclass 27, count 0 2006.211.08:05:00.15#ibcon#read 6, iclass 27, count 0 2006.211.08:05:00.15#ibcon#end of sib2, iclass 27, count 0 2006.211.08:05:00.15#ibcon#*after write, iclass 27, count 0 2006.211.08:05:00.15#ibcon#*before return 0, iclass 27, count 0 2006.211.08:05:00.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:05:00.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:05:00.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:05:00.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:05:00.15$vc4f8/vblo=1,632.99 2006.211.08:05:00.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:05:00.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:05:00.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:05:00.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:05:00.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:05:00.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:05:00.15#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:05:00.15#ibcon#first serial, iclass 29, count 0 2006.211.08:05:00.15#ibcon#enter sib2, iclass 29, count 0 2006.211.08:05:00.15#ibcon#flushed, iclass 29, count 0 2006.211.08:05:00.16#ibcon#about to write, iclass 29, count 0 2006.211.08:05:00.16#ibcon#wrote, iclass 29, count 0 2006.211.08:05:00.16#ibcon#about to read 3, iclass 29, count 0 2006.211.08:05:00.17#ibcon#read 3, iclass 29, count 0 2006.211.08:05:00.17#ibcon#about to read 4, iclass 29, count 0 2006.211.08:05:00.17#ibcon#read 4, iclass 29, count 0 2006.211.08:05:00.17#ibcon#about to read 5, iclass 29, count 0 2006.211.08:05:00.17#ibcon#read 5, iclass 29, count 0 2006.211.08:05:00.17#ibcon#about to read 6, iclass 29, count 0 2006.211.08:05:00.17#ibcon#read 6, iclass 29, count 0 2006.211.08:05:00.17#ibcon#end of sib2, iclass 29, count 0 2006.211.08:05:00.17#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:05:00.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:05:00.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:05:00.17#ibcon#*before write, iclass 29, count 0 2006.211.08:05:00.17#ibcon#enter sib2, iclass 29, count 0 2006.211.08:05:00.17#ibcon#flushed, iclass 29, count 0 2006.211.08:05:00.17#ibcon#about to write, iclass 29, count 0 2006.211.08:05:00.17#ibcon#wrote, iclass 29, count 0 2006.211.08:05:00.17#ibcon#about to read 3, iclass 29, count 0 2006.211.08:05:00.21#ibcon#read 3, iclass 29, count 0 2006.211.08:05:00.21#ibcon#about to read 4, iclass 29, count 0 2006.211.08:05:00.21#ibcon#read 4, iclass 29, count 0 2006.211.08:05:00.21#ibcon#about to read 5, iclass 29, count 0 2006.211.08:05:00.21#ibcon#read 5, iclass 29, count 0 2006.211.08:05:00.21#ibcon#about to read 6, iclass 29, count 0 2006.211.08:05:00.21#ibcon#read 6, iclass 29, count 0 2006.211.08:05:00.21#ibcon#end of sib2, iclass 29, count 0 2006.211.08:05:00.21#ibcon#*after write, iclass 29, count 0 2006.211.08:05:00.21#ibcon#*before return 0, iclass 29, count 0 2006.211.08:05:00.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:05:00.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:05:00.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:05:00.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:05:00.21$vc4f8/vb=1,4 2006.211.08:05:00.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.08:05:00.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.08:05:00.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:05:00.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:05:00.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:05:00.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:05:00.21#ibcon#enter wrdev, iclass 31, count 2 2006.211.08:05:00.21#ibcon#first serial, iclass 31, count 2 2006.211.08:05:00.21#ibcon#enter sib2, iclass 31, count 2 2006.211.08:05:00.21#ibcon#flushed, iclass 31, count 2 2006.211.08:05:00.21#ibcon#about to write, iclass 31, count 2 2006.211.08:05:00.22#ibcon#wrote, iclass 31, count 2 2006.211.08:05:00.22#ibcon#about to read 3, iclass 31, count 2 2006.211.08:05:00.23#ibcon#read 3, iclass 31, count 2 2006.211.08:05:00.23#ibcon#about to read 4, iclass 31, count 2 2006.211.08:05:00.23#ibcon#read 4, iclass 31, count 2 2006.211.08:05:00.23#ibcon#about to read 5, iclass 31, count 2 2006.211.08:05:00.23#ibcon#read 5, iclass 31, count 2 2006.211.08:05:00.23#ibcon#about to read 6, iclass 31, count 2 2006.211.08:05:00.23#ibcon#read 6, iclass 31, count 2 2006.211.08:05:00.23#ibcon#end of sib2, iclass 31, count 2 2006.211.08:05:00.23#ibcon#*mode == 0, iclass 31, count 2 2006.211.08:05:00.23#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.08:05:00.23#ibcon#[27=AT01-04\r\n] 2006.211.08:05:00.23#ibcon#*before write, iclass 31, count 2 2006.211.08:05:00.23#ibcon#enter sib2, iclass 31, count 2 2006.211.08:05:00.23#ibcon#flushed, iclass 31, count 2 2006.211.08:05:00.23#ibcon#about to write, iclass 31, count 2 2006.211.08:05:00.23#ibcon#wrote, iclass 31, count 2 2006.211.08:05:00.23#ibcon#about to read 3, iclass 31, count 2 2006.211.08:05:00.26#ibcon#read 3, iclass 31, count 2 2006.211.08:05:00.26#ibcon#about to read 4, iclass 31, count 2 2006.211.08:05:00.26#ibcon#read 4, iclass 31, count 2 2006.211.08:05:00.26#ibcon#about to read 5, iclass 31, count 2 2006.211.08:05:00.26#ibcon#read 5, iclass 31, count 2 2006.211.08:05:00.26#ibcon#about to read 6, iclass 31, count 2 2006.211.08:05:00.26#ibcon#read 6, iclass 31, count 2 2006.211.08:05:00.26#ibcon#end of sib2, iclass 31, count 2 2006.211.08:05:00.26#ibcon#*after write, iclass 31, count 2 2006.211.08:05:00.26#ibcon#*before return 0, iclass 31, count 2 2006.211.08:05:00.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:05:00.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:05:00.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.08:05:00.26#ibcon#ireg 7 cls_cnt 0 2006.211.08:05:00.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:05:00.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:05:00.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:05:00.38#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:05:00.38#ibcon#first serial, iclass 31, count 0 2006.211.08:05:00.38#ibcon#enter sib2, iclass 31, count 0 2006.211.08:05:00.38#ibcon#flushed, iclass 31, count 0 2006.211.08:05:00.38#ibcon#about to write, iclass 31, count 0 2006.211.08:05:00.38#ibcon#wrote, iclass 31, count 0 2006.211.08:05:00.38#ibcon#about to read 3, iclass 31, count 0 2006.211.08:05:00.40#ibcon#read 3, iclass 31, count 0 2006.211.08:05:00.40#ibcon#about to read 4, iclass 31, count 0 2006.211.08:05:00.40#ibcon#read 4, iclass 31, count 0 2006.211.08:05:00.40#ibcon#about to read 5, iclass 31, count 0 2006.211.08:05:00.40#ibcon#read 5, iclass 31, count 0 2006.211.08:05:00.40#ibcon#about to read 6, iclass 31, count 0 2006.211.08:05:00.40#ibcon#read 6, iclass 31, count 0 2006.211.08:05:00.40#ibcon#end of sib2, iclass 31, count 0 2006.211.08:05:00.40#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:05:00.40#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:05:00.40#ibcon#[27=USB\r\n] 2006.211.08:05:00.40#ibcon#*before write, iclass 31, count 0 2006.211.08:05:00.40#ibcon#enter sib2, iclass 31, count 0 2006.211.08:05:00.40#ibcon#flushed, iclass 31, count 0 2006.211.08:05:00.40#ibcon#about to write, iclass 31, count 0 2006.211.08:05:00.40#ibcon#wrote, iclass 31, count 0 2006.211.08:05:00.40#ibcon#about to read 3, iclass 31, count 0 2006.211.08:05:00.43#ibcon#read 3, iclass 31, count 0 2006.211.08:05:00.43#ibcon#about to read 4, iclass 31, count 0 2006.211.08:05:00.43#ibcon#read 4, iclass 31, count 0 2006.211.08:05:00.43#ibcon#about to read 5, iclass 31, count 0 2006.211.08:05:00.43#ibcon#read 5, iclass 31, count 0 2006.211.08:05:00.43#ibcon#about to read 6, iclass 31, count 0 2006.211.08:05:00.43#ibcon#read 6, iclass 31, count 0 2006.211.08:05:00.43#ibcon#end of sib2, iclass 31, count 0 2006.211.08:05:00.43#ibcon#*after write, iclass 31, count 0 2006.211.08:05:00.43#ibcon#*before return 0, iclass 31, count 0 2006.211.08:05:00.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:05:00.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:05:00.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:05:00.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:05:00.43$vc4f8/vblo=2,640.99 2006.211.08:05:00.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.08:05:00.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.08:05:00.43#ibcon#ireg 17 cls_cnt 0 2006.211.08:05:00.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:05:00.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:05:00.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:05:00.43#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:05:00.43#ibcon#first serial, iclass 33, count 0 2006.211.08:05:00.43#ibcon#enter sib2, iclass 33, count 0 2006.211.08:05:00.43#ibcon#flushed, iclass 33, count 0 2006.211.08:05:00.44#ibcon#about to write, iclass 33, count 0 2006.211.08:05:00.44#ibcon#wrote, iclass 33, count 0 2006.211.08:05:00.44#ibcon#about to read 3, iclass 33, count 0 2006.211.08:05:00.45#ibcon#read 3, iclass 33, count 0 2006.211.08:05:00.45#ibcon#about to read 4, iclass 33, count 0 2006.211.08:05:00.45#ibcon#read 4, iclass 33, count 0 2006.211.08:05:00.45#ibcon#about to read 5, iclass 33, count 0 2006.211.08:05:00.45#ibcon#read 5, iclass 33, count 0 2006.211.08:05:00.45#ibcon#about to read 6, iclass 33, count 0 2006.211.08:05:00.45#ibcon#read 6, iclass 33, count 0 2006.211.08:05:00.45#ibcon#end of sib2, iclass 33, count 0 2006.211.08:05:00.45#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:05:00.45#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:05:00.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:05:00.45#ibcon#*before write, iclass 33, count 0 2006.211.08:05:00.45#ibcon#enter sib2, iclass 33, count 0 2006.211.08:05:00.45#ibcon#flushed, iclass 33, count 0 2006.211.08:05:00.45#ibcon#about to write, iclass 33, count 0 2006.211.08:05:00.45#ibcon#wrote, iclass 33, count 0 2006.211.08:05:00.45#ibcon#about to read 3, iclass 33, count 0 2006.211.08:05:00.49#ibcon#read 3, iclass 33, count 0 2006.211.08:05:00.49#ibcon#about to read 4, iclass 33, count 0 2006.211.08:05:00.49#ibcon#read 4, iclass 33, count 0 2006.211.08:05:00.49#ibcon#about to read 5, iclass 33, count 0 2006.211.08:05:00.49#ibcon#read 5, iclass 33, count 0 2006.211.08:05:00.49#ibcon#about to read 6, iclass 33, count 0 2006.211.08:05:00.49#ibcon#read 6, iclass 33, count 0 2006.211.08:05:00.49#ibcon#end of sib2, iclass 33, count 0 2006.211.08:05:00.49#ibcon#*after write, iclass 33, count 0 2006.211.08:05:00.49#ibcon#*before return 0, iclass 33, count 0 2006.211.08:05:00.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:05:00.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:05:00.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:05:00.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:05:00.49$vc4f8/vb=2,4 2006.211.08:05:00.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:05:00.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:05:00.49#ibcon#ireg 11 cls_cnt 2 2006.211.08:05:00.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:05:00.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:05:00.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:05:00.55#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:05:00.55#ibcon#first serial, iclass 35, count 2 2006.211.08:05:00.55#ibcon#enter sib2, iclass 35, count 2 2006.211.08:05:00.55#ibcon#flushed, iclass 35, count 2 2006.211.08:05:00.55#ibcon#about to write, iclass 35, count 2 2006.211.08:05:00.55#ibcon#wrote, iclass 35, count 2 2006.211.08:05:00.55#ibcon#about to read 3, iclass 35, count 2 2006.211.08:05:00.57#ibcon#read 3, iclass 35, count 2 2006.211.08:05:00.57#ibcon#about to read 4, iclass 35, count 2 2006.211.08:05:00.57#ibcon#read 4, iclass 35, count 2 2006.211.08:05:00.57#ibcon#about to read 5, iclass 35, count 2 2006.211.08:05:00.57#ibcon#read 5, iclass 35, count 2 2006.211.08:05:00.57#ibcon#about to read 6, iclass 35, count 2 2006.211.08:05:00.57#ibcon#read 6, iclass 35, count 2 2006.211.08:05:00.57#ibcon#end of sib2, iclass 35, count 2 2006.211.08:05:00.57#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:05:00.57#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:05:00.57#ibcon#[27=AT02-04\r\n] 2006.211.08:05:00.57#ibcon#*before write, iclass 35, count 2 2006.211.08:05:00.57#ibcon#enter sib2, iclass 35, count 2 2006.211.08:05:00.57#ibcon#flushed, iclass 35, count 2 2006.211.08:05:00.57#ibcon#about to write, iclass 35, count 2 2006.211.08:05:00.57#ibcon#wrote, iclass 35, count 2 2006.211.08:05:00.57#ibcon#about to read 3, iclass 35, count 2 2006.211.08:05:00.60#ibcon#read 3, iclass 35, count 2 2006.211.08:05:00.60#ibcon#about to read 4, iclass 35, count 2 2006.211.08:05:00.60#ibcon#read 4, iclass 35, count 2 2006.211.08:05:00.60#ibcon#about to read 5, iclass 35, count 2 2006.211.08:05:00.60#ibcon#read 5, iclass 35, count 2 2006.211.08:05:00.60#ibcon#about to read 6, iclass 35, count 2 2006.211.08:05:00.60#ibcon#read 6, iclass 35, count 2 2006.211.08:05:00.60#ibcon#end of sib2, iclass 35, count 2 2006.211.08:05:00.60#ibcon#*after write, iclass 35, count 2 2006.211.08:05:00.60#ibcon#*before return 0, iclass 35, count 2 2006.211.08:05:00.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:05:00.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:05:00.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:05:00.60#ibcon#ireg 7 cls_cnt 0 2006.211.08:05:00.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:05:00.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:05:00.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:05:00.72#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:05:00.72#ibcon#first serial, iclass 35, count 0 2006.211.08:05:00.72#ibcon#enter sib2, iclass 35, count 0 2006.211.08:05:00.72#ibcon#flushed, iclass 35, count 0 2006.211.08:05:00.72#ibcon#about to write, iclass 35, count 0 2006.211.08:05:00.72#ibcon#wrote, iclass 35, count 0 2006.211.08:05:00.72#ibcon#about to read 3, iclass 35, count 0 2006.211.08:05:00.74#ibcon#read 3, iclass 35, count 0 2006.211.08:05:00.74#ibcon#about to read 4, iclass 35, count 0 2006.211.08:05:00.74#ibcon#read 4, iclass 35, count 0 2006.211.08:05:00.74#ibcon#about to read 5, iclass 35, count 0 2006.211.08:05:00.74#ibcon#read 5, iclass 35, count 0 2006.211.08:05:00.74#ibcon#about to read 6, iclass 35, count 0 2006.211.08:05:00.74#ibcon#read 6, iclass 35, count 0 2006.211.08:05:00.74#ibcon#end of sib2, iclass 35, count 0 2006.211.08:05:00.74#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:05:00.74#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:05:00.74#ibcon#[27=USB\r\n] 2006.211.08:05:00.74#ibcon#*before write, iclass 35, count 0 2006.211.08:05:00.74#ibcon#enter sib2, iclass 35, count 0 2006.211.08:05:00.74#ibcon#flushed, iclass 35, count 0 2006.211.08:05:00.74#ibcon#about to write, iclass 35, count 0 2006.211.08:05:00.74#ibcon#wrote, iclass 35, count 0 2006.211.08:05:00.74#ibcon#about to read 3, iclass 35, count 0 2006.211.08:05:00.77#ibcon#read 3, iclass 35, count 0 2006.211.08:05:00.77#ibcon#about to read 4, iclass 35, count 0 2006.211.08:05:00.77#ibcon#read 4, iclass 35, count 0 2006.211.08:05:00.77#ibcon#about to read 5, iclass 35, count 0 2006.211.08:05:00.77#ibcon#read 5, iclass 35, count 0 2006.211.08:05:00.77#ibcon#about to read 6, iclass 35, count 0 2006.211.08:05:00.77#ibcon#read 6, iclass 35, count 0 2006.211.08:05:00.77#ibcon#end of sib2, iclass 35, count 0 2006.211.08:05:00.77#ibcon#*after write, iclass 35, count 0 2006.211.08:05:00.77#ibcon#*before return 0, iclass 35, count 0 2006.211.08:05:00.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:05:00.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:05:00.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:05:00.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:05:00.77$vc4f8/vblo=3,656.99 2006.211.08:05:00.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:05:00.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:05:00.77#ibcon#ireg 17 cls_cnt 0 2006.211.08:05:00.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:05:00.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:05:00.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:05:00.77#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:05:00.77#ibcon#first serial, iclass 37, count 0 2006.211.08:05:00.77#ibcon#enter sib2, iclass 37, count 0 2006.211.08:05:00.77#ibcon#flushed, iclass 37, count 0 2006.211.08:05:00.77#ibcon#about to write, iclass 37, count 0 2006.211.08:05:00.78#ibcon#wrote, iclass 37, count 0 2006.211.08:05:00.78#ibcon#about to read 3, iclass 37, count 0 2006.211.08:05:00.79#ibcon#read 3, iclass 37, count 0 2006.211.08:05:00.79#ibcon#about to read 4, iclass 37, count 0 2006.211.08:05:00.79#ibcon#read 4, iclass 37, count 0 2006.211.08:05:00.79#ibcon#about to read 5, iclass 37, count 0 2006.211.08:05:00.79#ibcon#read 5, iclass 37, count 0 2006.211.08:05:00.79#ibcon#about to read 6, iclass 37, count 0 2006.211.08:05:00.79#ibcon#read 6, iclass 37, count 0 2006.211.08:05:00.79#ibcon#end of sib2, iclass 37, count 0 2006.211.08:05:00.79#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:05:00.79#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:05:00.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:05:00.79#ibcon#*before write, iclass 37, count 0 2006.211.08:05:00.79#ibcon#enter sib2, iclass 37, count 0 2006.211.08:05:00.79#ibcon#flushed, iclass 37, count 0 2006.211.08:05:00.79#ibcon#about to write, iclass 37, count 0 2006.211.08:05:00.79#ibcon#wrote, iclass 37, count 0 2006.211.08:05:00.79#ibcon#about to read 3, iclass 37, count 0 2006.211.08:05:00.83#ibcon#read 3, iclass 37, count 0 2006.211.08:05:00.83#ibcon#about to read 4, iclass 37, count 0 2006.211.08:05:00.83#ibcon#read 4, iclass 37, count 0 2006.211.08:05:00.83#ibcon#about to read 5, iclass 37, count 0 2006.211.08:05:00.83#ibcon#read 5, iclass 37, count 0 2006.211.08:05:00.83#ibcon#about to read 6, iclass 37, count 0 2006.211.08:05:00.83#ibcon#read 6, iclass 37, count 0 2006.211.08:05:00.83#ibcon#end of sib2, iclass 37, count 0 2006.211.08:05:00.83#ibcon#*after write, iclass 37, count 0 2006.211.08:05:00.83#ibcon#*before return 0, iclass 37, count 0 2006.211.08:05:00.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:05:00.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:05:00.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:05:00.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:05:00.83$vc4f8/vb=3,3 2006.211.08:05:00.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:05:00.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:05:00.83#ibcon#ireg 11 cls_cnt 2 2006.211.08:05:00.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:05:00.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:05:00.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:05:00.89#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:05:00.89#ibcon#first serial, iclass 39, count 2 2006.211.08:05:00.89#ibcon#enter sib2, iclass 39, count 2 2006.211.08:05:00.89#ibcon#flushed, iclass 39, count 2 2006.211.08:05:00.89#ibcon#about to write, iclass 39, count 2 2006.211.08:05:00.89#ibcon#wrote, iclass 39, count 2 2006.211.08:05:00.89#ibcon#about to read 3, iclass 39, count 2 2006.211.08:05:00.91#ibcon#read 3, iclass 39, count 2 2006.211.08:05:00.91#ibcon#about to read 4, iclass 39, count 2 2006.211.08:05:00.91#ibcon#read 4, iclass 39, count 2 2006.211.08:05:00.91#ibcon#about to read 5, iclass 39, count 2 2006.211.08:05:00.91#ibcon#read 5, iclass 39, count 2 2006.211.08:05:00.91#ibcon#about to read 6, iclass 39, count 2 2006.211.08:05:00.91#ibcon#read 6, iclass 39, count 2 2006.211.08:05:00.91#ibcon#end of sib2, iclass 39, count 2 2006.211.08:05:00.91#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:05:00.91#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:05:00.91#ibcon#[27=AT03-03\r\n] 2006.211.08:05:00.91#ibcon#*before write, iclass 39, count 2 2006.211.08:05:00.91#ibcon#enter sib2, iclass 39, count 2 2006.211.08:05:00.91#ibcon#flushed, iclass 39, count 2 2006.211.08:05:00.91#ibcon#about to write, iclass 39, count 2 2006.211.08:05:00.91#ibcon#wrote, iclass 39, count 2 2006.211.08:05:00.91#ibcon#about to read 3, iclass 39, count 2 2006.211.08:05:00.94#ibcon#read 3, iclass 39, count 2 2006.211.08:05:00.94#ibcon#about to read 4, iclass 39, count 2 2006.211.08:05:00.94#ibcon#read 4, iclass 39, count 2 2006.211.08:05:00.94#ibcon#about to read 5, iclass 39, count 2 2006.211.08:05:00.94#ibcon#read 5, iclass 39, count 2 2006.211.08:05:00.94#ibcon#about to read 6, iclass 39, count 2 2006.211.08:05:00.94#ibcon#read 6, iclass 39, count 2 2006.211.08:05:00.94#ibcon#end of sib2, iclass 39, count 2 2006.211.08:05:00.94#ibcon#*after write, iclass 39, count 2 2006.211.08:05:00.94#ibcon#*before return 0, iclass 39, count 2 2006.211.08:05:00.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:05:00.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:05:00.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:05:00.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:05:00.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:05:01.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:05:01.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:05:01.06#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:05:01.06#ibcon#first serial, iclass 39, count 0 2006.211.08:05:01.06#ibcon#enter sib2, iclass 39, count 0 2006.211.08:05:01.06#ibcon#flushed, iclass 39, count 0 2006.211.08:05:01.06#ibcon#about to write, iclass 39, count 0 2006.211.08:05:01.06#ibcon#wrote, iclass 39, count 0 2006.211.08:05:01.06#ibcon#about to read 3, iclass 39, count 0 2006.211.08:05:01.08#ibcon#read 3, iclass 39, count 0 2006.211.08:05:01.08#ibcon#about to read 4, iclass 39, count 0 2006.211.08:05:01.08#ibcon#read 4, iclass 39, count 0 2006.211.08:05:01.08#ibcon#about to read 5, iclass 39, count 0 2006.211.08:05:01.08#ibcon#read 5, iclass 39, count 0 2006.211.08:05:01.08#ibcon#about to read 6, iclass 39, count 0 2006.211.08:05:01.08#ibcon#read 6, iclass 39, count 0 2006.211.08:05:01.08#ibcon#end of sib2, iclass 39, count 0 2006.211.08:05:01.08#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:05:01.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:05:01.08#ibcon#[27=USB\r\n] 2006.211.08:05:01.08#ibcon#*before write, iclass 39, count 0 2006.211.08:05:01.08#ibcon#enter sib2, iclass 39, count 0 2006.211.08:05:01.08#ibcon#flushed, iclass 39, count 0 2006.211.08:05:01.08#ibcon#about to write, iclass 39, count 0 2006.211.08:05:01.08#ibcon#wrote, iclass 39, count 0 2006.211.08:05:01.08#ibcon#about to read 3, iclass 39, count 0 2006.211.08:05:01.11#ibcon#read 3, iclass 39, count 0 2006.211.08:05:01.11#ibcon#about to read 4, iclass 39, count 0 2006.211.08:05:01.11#ibcon#read 4, iclass 39, count 0 2006.211.08:05:01.11#ibcon#about to read 5, iclass 39, count 0 2006.211.08:05:01.11#ibcon#read 5, iclass 39, count 0 2006.211.08:05:01.11#ibcon#about to read 6, iclass 39, count 0 2006.211.08:05:01.11#ibcon#read 6, iclass 39, count 0 2006.211.08:05:01.11#ibcon#end of sib2, iclass 39, count 0 2006.211.08:05:01.11#ibcon#*after write, iclass 39, count 0 2006.211.08:05:01.11#ibcon#*before return 0, iclass 39, count 0 2006.211.08:05:01.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:05:01.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:05:01.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:05:01.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:05:01.11$vc4f8/vblo=4,712.99 2006.211.08:05:01.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:05:01.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:05:01.11#ibcon#ireg 17 cls_cnt 0 2006.211.08:05:01.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:05:01.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:05:01.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:05:01.11#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:05:01.11#ibcon#first serial, iclass 3, count 0 2006.211.08:05:01.11#ibcon#enter sib2, iclass 3, count 0 2006.211.08:05:01.11#ibcon#flushed, iclass 3, count 0 2006.211.08:05:01.11#ibcon#about to write, iclass 3, count 0 2006.211.08:05:01.12#ibcon#wrote, iclass 3, count 0 2006.211.08:05:01.12#ibcon#about to read 3, iclass 3, count 0 2006.211.08:05:01.13#ibcon#read 3, iclass 3, count 0 2006.211.08:05:01.13#ibcon#about to read 4, iclass 3, count 0 2006.211.08:05:01.13#ibcon#read 4, iclass 3, count 0 2006.211.08:05:01.13#ibcon#about to read 5, iclass 3, count 0 2006.211.08:05:01.13#ibcon#read 5, iclass 3, count 0 2006.211.08:05:01.13#ibcon#about to read 6, iclass 3, count 0 2006.211.08:05:01.13#ibcon#read 6, iclass 3, count 0 2006.211.08:05:01.13#ibcon#end of sib2, iclass 3, count 0 2006.211.08:05:01.13#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:05:01.13#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:05:01.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:05:01.13#ibcon#*before write, iclass 3, count 0 2006.211.08:05:01.13#ibcon#enter sib2, iclass 3, count 0 2006.211.08:05:01.13#ibcon#flushed, iclass 3, count 0 2006.211.08:05:01.13#ibcon#about to write, iclass 3, count 0 2006.211.08:05:01.13#ibcon#wrote, iclass 3, count 0 2006.211.08:05:01.13#ibcon#about to read 3, iclass 3, count 0 2006.211.08:05:01.17#ibcon#read 3, iclass 3, count 0 2006.211.08:05:01.17#ibcon#about to read 4, iclass 3, count 0 2006.211.08:05:01.17#ibcon#read 4, iclass 3, count 0 2006.211.08:05:01.17#ibcon#about to read 5, iclass 3, count 0 2006.211.08:05:01.17#ibcon#read 5, iclass 3, count 0 2006.211.08:05:01.17#ibcon#about to read 6, iclass 3, count 0 2006.211.08:05:01.17#ibcon#read 6, iclass 3, count 0 2006.211.08:05:01.17#ibcon#end of sib2, iclass 3, count 0 2006.211.08:05:01.17#ibcon#*after write, iclass 3, count 0 2006.211.08:05:01.17#ibcon#*before return 0, iclass 3, count 0 2006.211.08:05:01.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:05:01.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:05:01.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:05:01.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:05:01.17$vc4f8/vb=4,3 2006.211.08:05:01.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:05:01.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:05:01.17#ibcon#ireg 11 cls_cnt 2 2006.211.08:05:01.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:05:01.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:05:01.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:05:01.23#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:05:01.23#ibcon#first serial, iclass 5, count 2 2006.211.08:05:01.23#ibcon#enter sib2, iclass 5, count 2 2006.211.08:05:01.23#ibcon#flushed, iclass 5, count 2 2006.211.08:05:01.23#ibcon#about to write, iclass 5, count 2 2006.211.08:05:01.23#ibcon#wrote, iclass 5, count 2 2006.211.08:05:01.23#ibcon#about to read 3, iclass 5, count 2 2006.211.08:05:01.25#ibcon#read 3, iclass 5, count 2 2006.211.08:05:01.25#ibcon#about to read 4, iclass 5, count 2 2006.211.08:05:01.25#ibcon#read 4, iclass 5, count 2 2006.211.08:05:01.25#ibcon#about to read 5, iclass 5, count 2 2006.211.08:05:01.25#ibcon#read 5, iclass 5, count 2 2006.211.08:05:01.25#ibcon#about to read 6, iclass 5, count 2 2006.211.08:05:01.25#ibcon#read 6, iclass 5, count 2 2006.211.08:05:01.25#ibcon#end of sib2, iclass 5, count 2 2006.211.08:05:01.25#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:05:01.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:05:01.25#ibcon#[27=AT04-03\r\n] 2006.211.08:05:01.25#ibcon#*before write, iclass 5, count 2 2006.211.08:05:01.25#ibcon#enter sib2, iclass 5, count 2 2006.211.08:05:01.25#ibcon#flushed, iclass 5, count 2 2006.211.08:05:01.25#ibcon#about to write, iclass 5, count 2 2006.211.08:05:01.25#ibcon#wrote, iclass 5, count 2 2006.211.08:05:01.25#ibcon#about to read 3, iclass 5, count 2 2006.211.08:05:01.28#ibcon#read 3, iclass 5, count 2 2006.211.08:05:01.28#ibcon#about to read 4, iclass 5, count 2 2006.211.08:05:01.28#ibcon#read 4, iclass 5, count 2 2006.211.08:05:01.28#ibcon#about to read 5, iclass 5, count 2 2006.211.08:05:01.28#ibcon#read 5, iclass 5, count 2 2006.211.08:05:01.28#ibcon#about to read 6, iclass 5, count 2 2006.211.08:05:01.28#ibcon#read 6, iclass 5, count 2 2006.211.08:05:01.28#ibcon#end of sib2, iclass 5, count 2 2006.211.08:05:01.28#ibcon#*after write, iclass 5, count 2 2006.211.08:05:01.28#ibcon#*before return 0, iclass 5, count 2 2006.211.08:05:01.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:05:01.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:05:01.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:05:01.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:05:01.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:05:01.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:05:01.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:05:01.40#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:05:01.40#ibcon#first serial, iclass 5, count 0 2006.211.08:05:01.40#ibcon#enter sib2, iclass 5, count 0 2006.211.08:05:01.40#ibcon#flushed, iclass 5, count 0 2006.211.08:05:01.40#ibcon#about to write, iclass 5, count 0 2006.211.08:05:01.40#ibcon#wrote, iclass 5, count 0 2006.211.08:05:01.40#ibcon#about to read 3, iclass 5, count 0 2006.211.08:05:01.42#ibcon#read 3, iclass 5, count 0 2006.211.08:05:01.42#ibcon#about to read 4, iclass 5, count 0 2006.211.08:05:01.42#ibcon#read 4, iclass 5, count 0 2006.211.08:05:01.42#ibcon#about to read 5, iclass 5, count 0 2006.211.08:05:01.42#ibcon#read 5, iclass 5, count 0 2006.211.08:05:01.42#ibcon#about to read 6, iclass 5, count 0 2006.211.08:05:01.42#ibcon#read 6, iclass 5, count 0 2006.211.08:05:01.42#ibcon#end of sib2, iclass 5, count 0 2006.211.08:05:01.42#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:05:01.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:05:01.42#ibcon#[27=USB\r\n] 2006.211.08:05:01.42#ibcon#*before write, iclass 5, count 0 2006.211.08:05:01.42#ibcon#enter sib2, iclass 5, count 0 2006.211.08:05:01.42#ibcon#flushed, iclass 5, count 0 2006.211.08:05:01.42#ibcon#about to write, iclass 5, count 0 2006.211.08:05:01.42#ibcon#wrote, iclass 5, count 0 2006.211.08:05:01.42#ibcon#about to read 3, iclass 5, count 0 2006.211.08:05:01.45#ibcon#read 3, iclass 5, count 0 2006.211.08:05:01.45#ibcon#about to read 4, iclass 5, count 0 2006.211.08:05:01.45#ibcon#read 4, iclass 5, count 0 2006.211.08:05:01.45#ibcon#about to read 5, iclass 5, count 0 2006.211.08:05:01.45#ibcon#read 5, iclass 5, count 0 2006.211.08:05:01.45#ibcon#about to read 6, iclass 5, count 0 2006.211.08:05:01.45#ibcon#read 6, iclass 5, count 0 2006.211.08:05:01.45#ibcon#end of sib2, iclass 5, count 0 2006.211.08:05:01.45#ibcon#*after write, iclass 5, count 0 2006.211.08:05:01.45#ibcon#*before return 0, iclass 5, count 0 2006.211.08:05:01.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:05:01.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:05:01.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:05:01.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:05:01.45$vc4f8/vblo=5,744.99 2006.211.08:05:01.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:05:01.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:05:01.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:05:01.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:05:01.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:05:01.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:05:01.45#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:05:01.45#ibcon#first serial, iclass 7, count 0 2006.211.08:05:01.45#ibcon#enter sib2, iclass 7, count 0 2006.211.08:05:01.45#ibcon#flushed, iclass 7, count 0 2006.211.08:05:01.46#ibcon#about to write, iclass 7, count 0 2006.211.08:05:01.46#ibcon#wrote, iclass 7, count 0 2006.211.08:05:01.46#ibcon#about to read 3, iclass 7, count 0 2006.211.08:05:01.47#ibcon#read 3, iclass 7, count 0 2006.211.08:05:01.47#ibcon#about to read 4, iclass 7, count 0 2006.211.08:05:01.47#ibcon#read 4, iclass 7, count 0 2006.211.08:05:01.47#ibcon#about to read 5, iclass 7, count 0 2006.211.08:05:01.47#ibcon#read 5, iclass 7, count 0 2006.211.08:05:01.47#ibcon#about to read 6, iclass 7, count 0 2006.211.08:05:01.47#ibcon#read 6, iclass 7, count 0 2006.211.08:05:01.47#ibcon#end of sib2, iclass 7, count 0 2006.211.08:05:01.47#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:05:01.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:05:01.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:05:01.47#ibcon#*before write, iclass 7, count 0 2006.211.08:05:01.47#ibcon#enter sib2, iclass 7, count 0 2006.211.08:05:01.47#ibcon#flushed, iclass 7, count 0 2006.211.08:05:01.47#ibcon#about to write, iclass 7, count 0 2006.211.08:05:01.47#ibcon#wrote, iclass 7, count 0 2006.211.08:05:01.47#ibcon#about to read 3, iclass 7, count 0 2006.211.08:05:01.51#ibcon#read 3, iclass 7, count 0 2006.211.08:05:01.51#ibcon#about to read 4, iclass 7, count 0 2006.211.08:05:01.51#ibcon#read 4, iclass 7, count 0 2006.211.08:05:01.51#ibcon#about to read 5, iclass 7, count 0 2006.211.08:05:01.51#ibcon#read 5, iclass 7, count 0 2006.211.08:05:01.51#ibcon#about to read 6, iclass 7, count 0 2006.211.08:05:01.51#ibcon#read 6, iclass 7, count 0 2006.211.08:05:01.51#ibcon#end of sib2, iclass 7, count 0 2006.211.08:05:01.51#ibcon#*after write, iclass 7, count 0 2006.211.08:05:01.51#ibcon#*before return 0, iclass 7, count 0 2006.211.08:05:01.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:05:01.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:05:01.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:05:01.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:05:01.51$vc4f8/vb=5,3 2006.211.08:05:01.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:05:01.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:05:01.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:05:01.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:05:01.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:05:01.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:05:01.57#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:05:01.57#ibcon#first serial, iclass 11, count 2 2006.211.08:05:01.57#ibcon#enter sib2, iclass 11, count 2 2006.211.08:05:01.57#ibcon#flushed, iclass 11, count 2 2006.211.08:05:01.57#ibcon#about to write, iclass 11, count 2 2006.211.08:05:01.57#ibcon#wrote, iclass 11, count 2 2006.211.08:05:01.57#ibcon#about to read 3, iclass 11, count 2 2006.211.08:05:01.59#ibcon#read 3, iclass 11, count 2 2006.211.08:05:01.59#ibcon#about to read 4, iclass 11, count 2 2006.211.08:05:01.59#ibcon#read 4, iclass 11, count 2 2006.211.08:05:01.59#ibcon#about to read 5, iclass 11, count 2 2006.211.08:05:01.59#ibcon#read 5, iclass 11, count 2 2006.211.08:05:01.59#ibcon#about to read 6, iclass 11, count 2 2006.211.08:05:01.59#ibcon#read 6, iclass 11, count 2 2006.211.08:05:01.59#ibcon#end of sib2, iclass 11, count 2 2006.211.08:05:01.59#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:05:01.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:05:01.59#ibcon#[27=AT05-03\r\n] 2006.211.08:05:01.59#ibcon#*before write, iclass 11, count 2 2006.211.08:05:01.59#ibcon#enter sib2, iclass 11, count 2 2006.211.08:05:01.59#ibcon#flushed, iclass 11, count 2 2006.211.08:05:01.59#ibcon#about to write, iclass 11, count 2 2006.211.08:05:01.59#ibcon#wrote, iclass 11, count 2 2006.211.08:05:01.59#ibcon#about to read 3, iclass 11, count 2 2006.211.08:05:01.62#ibcon#read 3, iclass 11, count 2 2006.211.08:05:01.62#ibcon#about to read 4, iclass 11, count 2 2006.211.08:05:01.62#ibcon#read 4, iclass 11, count 2 2006.211.08:05:01.62#ibcon#about to read 5, iclass 11, count 2 2006.211.08:05:01.62#ibcon#read 5, iclass 11, count 2 2006.211.08:05:01.62#ibcon#about to read 6, iclass 11, count 2 2006.211.08:05:01.62#ibcon#read 6, iclass 11, count 2 2006.211.08:05:01.62#ibcon#end of sib2, iclass 11, count 2 2006.211.08:05:01.62#ibcon#*after write, iclass 11, count 2 2006.211.08:05:01.62#ibcon#*before return 0, iclass 11, count 2 2006.211.08:05:01.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:05:01.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:05:01.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:05:01.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:05:01.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:05:01.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:05:01.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:05:01.74#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:05:01.74#ibcon#first serial, iclass 11, count 0 2006.211.08:05:01.74#ibcon#enter sib2, iclass 11, count 0 2006.211.08:05:01.74#ibcon#flushed, iclass 11, count 0 2006.211.08:05:01.74#ibcon#about to write, iclass 11, count 0 2006.211.08:05:01.74#ibcon#wrote, iclass 11, count 0 2006.211.08:05:01.74#ibcon#about to read 3, iclass 11, count 0 2006.211.08:05:01.76#ibcon#read 3, iclass 11, count 0 2006.211.08:05:01.76#ibcon#about to read 4, iclass 11, count 0 2006.211.08:05:01.76#ibcon#read 4, iclass 11, count 0 2006.211.08:05:01.76#ibcon#about to read 5, iclass 11, count 0 2006.211.08:05:01.76#ibcon#read 5, iclass 11, count 0 2006.211.08:05:01.76#ibcon#about to read 6, iclass 11, count 0 2006.211.08:05:01.76#ibcon#read 6, iclass 11, count 0 2006.211.08:05:01.76#ibcon#end of sib2, iclass 11, count 0 2006.211.08:05:01.76#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:05:01.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:05:01.76#ibcon#[27=USB\r\n] 2006.211.08:05:01.76#ibcon#*before write, iclass 11, count 0 2006.211.08:05:01.76#ibcon#enter sib2, iclass 11, count 0 2006.211.08:05:01.76#ibcon#flushed, iclass 11, count 0 2006.211.08:05:01.76#ibcon#about to write, iclass 11, count 0 2006.211.08:05:01.76#ibcon#wrote, iclass 11, count 0 2006.211.08:05:01.76#ibcon#about to read 3, iclass 11, count 0 2006.211.08:05:01.79#ibcon#read 3, iclass 11, count 0 2006.211.08:05:01.79#ibcon#about to read 4, iclass 11, count 0 2006.211.08:05:01.79#ibcon#read 4, iclass 11, count 0 2006.211.08:05:01.79#ibcon#about to read 5, iclass 11, count 0 2006.211.08:05:01.79#ibcon#read 5, iclass 11, count 0 2006.211.08:05:01.79#ibcon#about to read 6, iclass 11, count 0 2006.211.08:05:01.79#ibcon#read 6, iclass 11, count 0 2006.211.08:05:01.79#ibcon#end of sib2, iclass 11, count 0 2006.211.08:05:01.79#ibcon#*after write, iclass 11, count 0 2006.211.08:05:01.79#ibcon#*before return 0, iclass 11, count 0 2006.211.08:05:01.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:05:01.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:05:01.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:05:01.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:05:01.79$vc4f8/vblo=6,752.99 2006.211.08:05:01.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:05:01.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:05:01.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:05:01.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:05:01.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:05:01.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:05:01.79#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:05:01.79#ibcon#first serial, iclass 13, count 0 2006.211.08:05:01.79#ibcon#enter sib2, iclass 13, count 0 2006.211.08:05:01.79#ibcon#flushed, iclass 13, count 0 2006.211.08:05:01.79#ibcon#about to write, iclass 13, count 0 2006.211.08:05:01.80#ibcon#wrote, iclass 13, count 0 2006.211.08:05:01.80#ibcon#about to read 3, iclass 13, count 0 2006.211.08:05:01.81#ibcon#read 3, iclass 13, count 0 2006.211.08:05:01.81#ibcon#about to read 4, iclass 13, count 0 2006.211.08:05:01.81#ibcon#read 4, iclass 13, count 0 2006.211.08:05:01.81#ibcon#about to read 5, iclass 13, count 0 2006.211.08:05:01.81#ibcon#read 5, iclass 13, count 0 2006.211.08:05:01.81#ibcon#about to read 6, iclass 13, count 0 2006.211.08:05:01.81#ibcon#read 6, iclass 13, count 0 2006.211.08:05:01.81#ibcon#end of sib2, iclass 13, count 0 2006.211.08:05:01.81#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:05:01.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:05:01.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:05:01.81#ibcon#*before write, iclass 13, count 0 2006.211.08:05:01.81#ibcon#enter sib2, iclass 13, count 0 2006.211.08:05:01.81#ibcon#flushed, iclass 13, count 0 2006.211.08:05:01.81#ibcon#about to write, iclass 13, count 0 2006.211.08:05:01.81#ibcon#wrote, iclass 13, count 0 2006.211.08:05:01.81#ibcon#about to read 3, iclass 13, count 0 2006.211.08:05:01.85#ibcon#read 3, iclass 13, count 0 2006.211.08:05:01.85#ibcon#about to read 4, iclass 13, count 0 2006.211.08:05:01.85#ibcon#read 4, iclass 13, count 0 2006.211.08:05:01.85#ibcon#about to read 5, iclass 13, count 0 2006.211.08:05:01.85#ibcon#read 5, iclass 13, count 0 2006.211.08:05:01.85#ibcon#about to read 6, iclass 13, count 0 2006.211.08:05:01.85#ibcon#read 6, iclass 13, count 0 2006.211.08:05:01.85#ibcon#end of sib2, iclass 13, count 0 2006.211.08:05:01.85#ibcon#*after write, iclass 13, count 0 2006.211.08:05:01.85#ibcon#*before return 0, iclass 13, count 0 2006.211.08:05:01.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:05:01.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:05:01.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:05:01.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:05:01.85$vc4f8/vb=6,3 2006.211.08:05:01.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:05:01.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:05:01.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:05:01.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:05:01.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:05:01.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:05:01.91#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:05:01.91#ibcon#first serial, iclass 15, count 2 2006.211.08:05:01.91#ibcon#enter sib2, iclass 15, count 2 2006.211.08:05:01.91#ibcon#flushed, iclass 15, count 2 2006.211.08:05:01.91#ibcon#about to write, iclass 15, count 2 2006.211.08:05:01.91#ibcon#wrote, iclass 15, count 2 2006.211.08:05:01.91#ibcon#about to read 3, iclass 15, count 2 2006.211.08:05:01.93#ibcon#read 3, iclass 15, count 2 2006.211.08:05:01.93#ibcon#about to read 4, iclass 15, count 2 2006.211.08:05:01.93#ibcon#read 4, iclass 15, count 2 2006.211.08:05:01.93#ibcon#about to read 5, iclass 15, count 2 2006.211.08:05:01.93#ibcon#read 5, iclass 15, count 2 2006.211.08:05:01.93#ibcon#about to read 6, iclass 15, count 2 2006.211.08:05:01.93#ibcon#read 6, iclass 15, count 2 2006.211.08:05:01.93#ibcon#end of sib2, iclass 15, count 2 2006.211.08:05:01.93#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:05:01.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:05:01.93#ibcon#[27=AT06-03\r\n] 2006.211.08:05:01.93#ibcon#*before write, iclass 15, count 2 2006.211.08:05:01.93#ibcon#enter sib2, iclass 15, count 2 2006.211.08:05:01.93#ibcon#flushed, iclass 15, count 2 2006.211.08:05:01.93#ibcon#about to write, iclass 15, count 2 2006.211.08:05:01.93#ibcon#wrote, iclass 15, count 2 2006.211.08:05:01.93#ibcon#about to read 3, iclass 15, count 2 2006.211.08:05:01.96#ibcon#read 3, iclass 15, count 2 2006.211.08:05:01.96#ibcon#about to read 4, iclass 15, count 2 2006.211.08:05:01.96#ibcon#read 4, iclass 15, count 2 2006.211.08:05:01.96#ibcon#about to read 5, iclass 15, count 2 2006.211.08:05:01.96#ibcon#read 5, iclass 15, count 2 2006.211.08:05:01.96#ibcon#about to read 6, iclass 15, count 2 2006.211.08:05:01.96#ibcon#read 6, iclass 15, count 2 2006.211.08:05:01.96#ibcon#end of sib2, iclass 15, count 2 2006.211.08:05:01.96#ibcon#*after write, iclass 15, count 2 2006.211.08:05:01.96#ibcon#*before return 0, iclass 15, count 2 2006.211.08:05:01.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:05:01.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:05:01.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:05:01.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:05:01.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:05:02.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:05:02.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:05:02.08#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:05:02.08#ibcon#first serial, iclass 15, count 0 2006.211.08:05:02.08#ibcon#enter sib2, iclass 15, count 0 2006.211.08:05:02.08#ibcon#flushed, iclass 15, count 0 2006.211.08:05:02.08#ibcon#about to write, iclass 15, count 0 2006.211.08:05:02.08#ibcon#wrote, iclass 15, count 0 2006.211.08:05:02.08#ibcon#about to read 3, iclass 15, count 0 2006.211.08:05:02.10#ibcon#read 3, iclass 15, count 0 2006.211.08:05:02.10#ibcon#about to read 4, iclass 15, count 0 2006.211.08:05:02.10#ibcon#read 4, iclass 15, count 0 2006.211.08:05:02.10#ibcon#about to read 5, iclass 15, count 0 2006.211.08:05:02.10#ibcon#read 5, iclass 15, count 0 2006.211.08:05:02.10#ibcon#about to read 6, iclass 15, count 0 2006.211.08:05:02.10#ibcon#read 6, iclass 15, count 0 2006.211.08:05:02.10#ibcon#end of sib2, iclass 15, count 0 2006.211.08:05:02.10#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:05:02.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:05:02.10#ibcon#[27=USB\r\n] 2006.211.08:05:02.10#ibcon#*before write, iclass 15, count 0 2006.211.08:05:02.10#ibcon#enter sib2, iclass 15, count 0 2006.211.08:05:02.10#ibcon#flushed, iclass 15, count 0 2006.211.08:05:02.10#ibcon#about to write, iclass 15, count 0 2006.211.08:05:02.10#ibcon#wrote, iclass 15, count 0 2006.211.08:05:02.10#ibcon#about to read 3, iclass 15, count 0 2006.211.08:05:02.13#ibcon#read 3, iclass 15, count 0 2006.211.08:05:02.13#ibcon#about to read 4, iclass 15, count 0 2006.211.08:05:02.13#ibcon#read 4, iclass 15, count 0 2006.211.08:05:02.13#ibcon#about to read 5, iclass 15, count 0 2006.211.08:05:02.13#ibcon#read 5, iclass 15, count 0 2006.211.08:05:02.13#ibcon#about to read 6, iclass 15, count 0 2006.211.08:05:02.13#ibcon#read 6, iclass 15, count 0 2006.211.08:05:02.13#ibcon#end of sib2, iclass 15, count 0 2006.211.08:05:02.13#ibcon#*after write, iclass 15, count 0 2006.211.08:05:02.13#ibcon#*before return 0, iclass 15, count 0 2006.211.08:05:02.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:05:02.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:05:02.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:05:02.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:05:02.13$vc4f8/vabw=wide 2006.211.08:05:02.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:05:02.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:05:02.13#ibcon#ireg 8 cls_cnt 0 2006.211.08:05:02.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:05:02.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:05:02.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:05:02.13#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:05:02.13#ibcon#first serial, iclass 17, count 0 2006.211.08:05:02.13#ibcon#enter sib2, iclass 17, count 0 2006.211.08:05:02.13#ibcon#flushed, iclass 17, count 0 2006.211.08:05:02.13#ibcon#about to write, iclass 17, count 0 2006.211.08:05:02.13#ibcon#wrote, iclass 17, count 0 2006.211.08:05:02.13#ibcon#about to read 3, iclass 17, count 0 2006.211.08:05:02.15#ibcon#read 3, iclass 17, count 0 2006.211.08:05:02.15#ibcon#about to read 4, iclass 17, count 0 2006.211.08:05:02.15#ibcon#read 4, iclass 17, count 0 2006.211.08:05:02.15#ibcon#about to read 5, iclass 17, count 0 2006.211.08:05:02.15#ibcon#read 5, iclass 17, count 0 2006.211.08:05:02.15#ibcon#about to read 6, iclass 17, count 0 2006.211.08:05:02.15#ibcon#read 6, iclass 17, count 0 2006.211.08:05:02.15#ibcon#end of sib2, iclass 17, count 0 2006.211.08:05:02.15#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:05:02.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:05:02.15#ibcon#[25=BW32\r\n] 2006.211.08:05:02.15#ibcon#*before write, iclass 17, count 0 2006.211.08:05:02.15#ibcon#enter sib2, iclass 17, count 0 2006.211.08:05:02.15#ibcon#flushed, iclass 17, count 0 2006.211.08:05:02.15#ibcon#about to write, iclass 17, count 0 2006.211.08:05:02.15#ibcon#wrote, iclass 17, count 0 2006.211.08:05:02.15#ibcon#about to read 3, iclass 17, count 0 2006.211.08:05:02.18#ibcon#read 3, iclass 17, count 0 2006.211.08:05:02.18#ibcon#about to read 4, iclass 17, count 0 2006.211.08:05:02.18#ibcon#read 4, iclass 17, count 0 2006.211.08:05:02.18#ibcon#about to read 5, iclass 17, count 0 2006.211.08:05:02.18#ibcon#read 5, iclass 17, count 0 2006.211.08:05:02.18#ibcon#about to read 6, iclass 17, count 0 2006.211.08:05:02.18#ibcon#read 6, iclass 17, count 0 2006.211.08:05:02.18#ibcon#end of sib2, iclass 17, count 0 2006.211.08:05:02.18#ibcon#*after write, iclass 17, count 0 2006.211.08:05:02.18#ibcon#*before return 0, iclass 17, count 0 2006.211.08:05:02.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:05:02.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:05:02.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:05:02.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:05:02.18$vc4f8/vbbw=wide 2006.211.08:05:02.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.08:05:02.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.08:05:02.18#ibcon#ireg 8 cls_cnt 0 2006.211.08:05:02.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:05:02.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:05:02.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:05:02.25#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:05:02.25#ibcon#first serial, iclass 19, count 0 2006.211.08:05:02.25#ibcon#enter sib2, iclass 19, count 0 2006.211.08:05:02.25#ibcon#flushed, iclass 19, count 0 2006.211.08:05:02.25#ibcon#about to write, iclass 19, count 0 2006.211.08:05:02.25#ibcon#wrote, iclass 19, count 0 2006.211.08:05:02.25#ibcon#about to read 3, iclass 19, count 0 2006.211.08:05:02.27#ibcon#read 3, iclass 19, count 0 2006.211.08:05:02.27#ibcon#about to read 4, iclass 19, count 0 2006.211.08:05:02.27#ibcon#read 4, iclass 19, count 0 2006.211.08:05:02.27#ibcon#about to read 5, iclass 19, count 0 2006.211.08:05:02.27#ibcon#read 5, iclass 19, count 0 2006.211.08:05:02.27#ibcon#about to read 6, iclass 19, count 0 2006.211.08:05:02.27#ibcon#read 6, iclass 19, count 0 2006.211.08:05:02.27#ibcon#end of sib2, iclass 19, count 0 2006.211.08:05:02.27#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:05:02.27#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:05:02.27#ibcon#[27=BW32\r\n] 2006.211.08:05:02.27#ibcon#*before write, iclass 19, count 0 2006.211.08:05:02.27#ibcon#enter sib2, iclass 19, count 0 2006.211.08:05:02.27#ibcon#flushed, iclass 19, count 0 2006.211.08:05:02.27#ibcon#about to write, iclass 19, count 0 2006.211.08:05:02.27#ibcon#wrote, iclass 19, count 0 2006.211.08:05:02.27#ibcon#about to read 3, iclass 19, count 0 2006.211.08:05:02.30#ibcon#read 3, iclass 19, count 0 2006.211.08:05:02.30#ibcon#about to read 4, iclass 19, count 0 2006.211.08:05:02.30#ibcon#read 4, iclass 19, count 0 2006.211.08:05:02.30#ibcon#about to read 5, iclass 19, count 0 2006.211.08:05:02.30#ibcon#read 5, iclass 19, count 0 2006.211.08:05:02.30#ibcon#about to read 6, iclass 19, count 0 2006.211.08:05:02.30#ibcon#read 6, iclass 19, count 0 2006.211.08:05:02.30#ibcon#end of sib2, iclass 19, count 0 2006.211.08:05:02.30#ibcon#*after write, iclass 19, count 0 2006.211.08:05:02.30#ibcon#*before return 0, iclass 19, count 0 2006.211.08:05:02.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:05:02.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:05:02.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:05:02.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:05:02.30$4f8m12a/ifd4f 2006.211.08:05:02.30$ifd4f/lo= 2006.211.08:05:02.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:05:02.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:05:02.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:05:02.31$ifd4f/patch= 2006.211.08:05:02.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:05:02.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:05:02.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:05:02.31$4f8m12a/"form=m,16.000,1:2 2006.211.08:05:02.31$4f8m12a/"tpicd 2006.211.08:05:02.31$4f8m12a/echo=off 2006.211.08:05:02.31$4f8m12a/xlog=off 2006.211.08:05:02.31:!2006.211.08:05:30 2006.211.08:05:11.13#trakl#Source acquired 2006.211.08:05:12.14#flagr#flagr/antenna,acquired 2006.211.08:05:30.01:preob 2006.211.08:05:31.14/onsource/TRACKING 2006.211.08:05:31.14:!2006.211.08:05:40 2006.211.08:05:40.00:data_valid=on 2006.211.08:05:40.00:midob 2006.211.08:05:40.14/onsource/TRACKING 2006.211.08:05:40.15/wx/24.72,1010.0,78 2006.211.08:05:40.26/cable/+6.4393E-03 2006.211.08:05:41.35/va/01,08,usb,yes,28,29 2006.211.08:05:41.35/va/02,07,usb,yes,28,29 2006.211.08:05:41.35/va/03,06,usb,yes,29,30 2006.211.08:05:41.35/va/04,07,usb,yes,29,31 2006.211.08:05:41.35/va/05,07,usb,yes,31,33 2006.211.08:05:41.35/va/06,06,usb,yes,30,30 2006.211.08:05:41.35/va/07,06,usb,yes,30,30 2006.211.08:05:41.35/va/08,07,usb,yes,29,28 2006.211.08:05:41.58/valo/01,532.99,yes,locked 2006.211.08:05:41.58/valo/02,572.99,yes,locked 2006.211.08:05:41.58/valo/03,672.99,yes,locked 2006.211.08:05:41.58/valo/04,832.99,yes,locked 2006.211.08:05:41.58/valo/05,652.99,yes,locked 2006.211.08:05:41.58/valo/06,772.99,yes,locked 2006.211.08:05:41.58/valo/07,832.99,yes,locked 2006.211.08:05:41.58/valo/08,852.99,yes,locked 2006.211.08:05:42.67/vb/01,04,usb,yes,28,27 2006.211.08:05:42.67/vb/02,04,usb,yes,30,31 2006.211.08:05:42.67/vb/03,03,usb,yes,33,37 2006.211.08:05:42.67/vb/04,03,usb,yes,33,34 2006.211.08:05:42.67/vb/05,03,usb,yes,32,36 2006.211.08:05:42.67/vb/06,03,usb,yes,33,36 2006.211.08:05:42.67/vb/07,04,usb,yes,28,28 2006.211.08:05:42.67/vb/08,03,usb,yes,33,36 2006.211.08:05:42.90/vblo/01,632.99,yes,locked 2006.211.08:05:42.90/vblo/02,640.99,yes,locked 2006.211.08:05:42.90/vblo/03,656.99,yes,locked 2006.211.08:05:42.90/vblo/04,712.99,yes,locked 2006.211.08:05:42.90/vblo/05,744.99,yes,locked 2006.211.08:05:42.90/vblo/06,752.99,yes,locked 2006.211.08:05:42.90/vblo/07,734.99,yes,locked 2006.211.08:05:42.90/vblo/08,744.99,yes,locked 2006.211.08:05:43.05/vabw/8 2006.211.08:05:43.20/vbbw/8 2006.211.08:05:43.29/xfe/off,on,12.0 2006.211.08:05:43.68/ifatt/23,28,28,28 2006.211.08:05:44.07/fmout-gps/S +4.45E-07 2006.211.08:05:44.12:!2006.211.08:06:40 2006.211.08:06:40.01:data_valid=off 2006.211.08:06:40.01:postob 2006.211.08:06:40.18/cable/+6.4388E-03 2006.211.08:06:40.18/wx/24.70,1010.0,79 2006.211.08:06:41.07/fmout-gps/S +4.47E-07 2006.211.08:06:41.07:scan_name=211-0807,k06211,60 2006.211.08:06:41.07:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.211.08:06:41.14#flagr#flagr/antenna,new-source 2006.211.08:06:42.14:checkk5 2006.211.08:06:42.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:06:42.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:06:43.18/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:06:43.52/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:06:43.85/chk_obsdata//k5ts1/T2110805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:06:44.19/chk_obsdata//k5ts2/T2110805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:06:44.52/chk_obsdata//k5ts3/T2110805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:06:44.86/chk_obsdata//k5ts4/T2110805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:06:45.52/k5log//k5ts1_log_newline 2006.211.08:06:46.18/k5log//k5ts2_log_newline 2006.211.08:06:46.83/k5log//k5ts3_log_newline 2006.211.08:06:47.48/k5log//k5ts4_log_newline 2006.211.08:06:47.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:06:47.50:4f8m12a=2 2006.211.08:06:47.50$4f8m12a/echo=on 2006.211.08:06:47.51$4f8m12a/pcalon 2006.211.08:06:47.51$pcalon/"no phase cal control is implemented here 2006.211.08:06:47.51$4f8m12a/"tpicd=stop 2006.211.08:06:47.51$4f8m12a/vc4f8 2006.211.08:06:47.51$vc4f8/valo=1,532.99 2006.211.08:06:47.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:06:47.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:06:47.51#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:47.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:47.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:47.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:47.51#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:06:47.51#ibcon#first serial, iclass 30, count 0 2006.211.08:06:47.51#ibcon#enter sib2, iclass 30, count 0 2006.211.08:06:47.51#ibcon#flushed, iclass 30, count 0 2006.211.08:06:47.51#ibcon#about to write, iclass 30, count 0 2006.211.08:06:47.51#ibcon#wrote, iclass 30, count 0 2006.211.08:06:47.51#ibcon#about to read 3, iclass 30, count 0 2006.211.08:06:47.52#ibcon#read 3, iclass 30, count 0 2006.211.08:06:47.52#ibcon#about to read 4, iclass 30, count 0 2006.211.08:06:47.52#ibcon#read 4, iclass 30, count 0 2006.211.08:06:47.52#ibcon#about to read 5, iclass 30, count 0 2006.211.08:06:47.52#ibcon#read 5, iclass 30, count 0 2006.211.08:06:47.52#ibcon#about to read 6, iclass 30, count 0 2006.211.08:06:47.52#ibcon#read 6, iclass 30, count 0 2006.211.08:06:47.52#ibcon#end of sib2, iclass 30, count 0 2006.211.08:06:47.52#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:06:47.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:06:47.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:06:47.52#ibcon#*before write, iclass 30, count 0 2006.211.08:06:47.52#ibcon#enter sib2, iclass 30, count 0 2006.211.08:06:47.52#ibcon#flushed, iclass 30, count 0 2006.211.08:06:47.52#ibcon#about to write, iclass 30, count 0 2006.211.08:06:47.52#ibcon#wrote, iclass 30, count 0 2006.211.08:06:47.52#ibcon#about to read 3, iclass 30, count 0 2006.211.08:06:47.57#ibcon#read 3, iclass 30, count 0 2006.211.08:06:47.57#ibcon#about to read 4, iclass 30, count 0 2006.211.08:06:47.57#ibcon#read 4, iclass 30, count 0 2006.211.08:06:47.57#ibcon#about to read 5, iclass 30, count 0 2006.211.08:06:47.57#ibcon#read 5, iclass 30, count 0 2006.211.08:06:47.57#ibcon#about to read 6, iclass 30, count 0 2006.211.08:06:47.57#ibcon#read 6, iclass 30, count 0 2006.211.08:06:47.57#ibcon#end of sib2, iclass 30, count 0 2006.211.08:06:47.57#ibcon#*after write, iclass 30, count 0 2006.211.08:06:47.57#ibcon#*before return 0, iclass 30, count 0 2006.211.08:06:47.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:47.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:47.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:06:47.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:06:47.57$vc4f8/va=1,8 2006.211.08:06:47.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:06:47.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:06:47.57#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:47.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:47.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:47.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:47.57#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:06:47.57#ibcon#first serial, iclass 32, count 2 2006.211.08:06:47.57#ibcon#enter sib2, iclass 32, count 2 2006.211.08:06:47.57#ibcon#flushed, iclass 32, count 2 2006.211.08:06:47.57#ibcon#about to write, iclass 32, count 2 2006.211.08:06:47.57#ibcon#wrote, iclass 32, count 2 2006.211.08:06:47.57#ibcon#about to read 3, iclass 32, count 2 2006.211.08:06:47.59#ibcon#read 3, iclass 32, count 2 2006.211.08:06:47.59#ibcon#about to read 4, iclass 32, count 2 2006.211.08:06:47.59#ibcon#read 4, iclass 32, count 2 2006.211.08:06:47.59#ibcon#about to read 5, iclass 32, count 2 2006.211.08:06:47.59#ibcon#read 5, iclass 32, count 2 2006.211.08:06:47.59#ibcon#about to read 6, iclass 32, count 2 2006.211.08:06:47.59#ibcon#read 6, iclass 32, count 2 2006.211.08:06:47.59#ibcon#end of sib2, iclass 32, count 2 2006.211.08:06:47.59#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:06:47.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:06:47.59#ibcon#[25=AT01-08\r\n] 2006.211.08:06:47.59#ibcon#*before write, iclass 32, count 2 2006.211.08:06:47.59#ibcon#enter sib2, iclass 32, count 2 2006.211.08:06:47.59#ibcon#flushed, iclass 32, count 2 2006.211.08:06:47.59#ibcon#about to write, iclass 32, count 2 2006.211.08:06:47.59#ibcon#wrote, iclass 32, count 2 2006.211.08:06:47.59#ibcon#about to read 3, iclass 32, count 2 2006.211.08:06:47.62#ibcon#read 3, iclass 32, count 2 2006.211.08:06:47.62#ibcon#about to read 4, iclass 32, count 2 2006.211.08:06:47.62#ibcon#read 4, iclass 32, count 2 2006.211.08:06:47.62#ibcon#about to read 5, iclass 32, count 2 2006.211.08:06:47.62#ibcon#read 5, iclass 32, count 2 2006.211.08:06:47.62#ibcon#about to read 6, iclass 32, count 2 2006.211.08:06:47.62#ibcon#read 6, iclass 32, count 2 2006.211.08:06:47.62#ibcon#end of sib2, iclass 32, count 2 2006.211.08:06:47.62#ibcon#*after write, iclass 32, count 2 2006.211.08:06:47.62#ibcon#*before return 0, iclass 32, count 2 2006.211.08:06:47.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:47.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:47.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:06:47.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:47.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:47.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:47.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:47.74#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:06:47.74#ibcon#first serial, iclass 32, count 0 2006.211.08:06:47.74#ibcon#enter sib2, iclass 32, count 0 2006.211.08:06:47.74#ibcon#flushed, iclass 32, count 0 2006.211.08:06:47.74#ibcon#about to write, iclass 32, count 0 2006.211.08:06:47.74#ibcon#wrote, iclass 32, count 0 2006.211.08:06:47.74#ibcon#about to read 3, iclass 32, count 0 2006.211.08:06:47.76#ibcon#read 3, iclass 32, count 0 2006.211.08:06:47.76#ibcon#about to read 4, iclass 32, count 0 2006.211.08:06:47.76#ibcon#read 4, iclass 32, count 0 2006.211.08:06:47.76#ibcon#about to read 5, iclass 32, count 0 2006.211.08:06:47.76#ibcon#read 5, iclass 32, count 0 2006.211.08:06:47.76#ibcon#about to read 6, iclass 32, count 0 2006.211.08:06:47.76#ibcon#read 6, iclass 32, count 0 2006.211.08:06:47.76#ibcon#end of sib2, iclass 32, count 0 2006.211.08:06:47.76#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:06:47.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:06:47.76#ibcon#[25=USB\r\n] 2006.211.08:06:47.76#ibcon#*before write, iclass 32, count 0 2006.211.08:06:47.76#ibcon#enter sib2, iclass 32, count 0 2006.211.08:06:47.76#ibcon#flushed, iclass 32, count 0 2006.211.08:06:47.76#ibcon#about to write, iclass 32, count 0 2006.211.08:06:47.76#ibcon#wrote, iclass 32, count 0 2006.211.08:06:47.76#ibcon#about to read 3, iclass 32, count 0 2006.211.08:06:47.79#ibcon#read 3, iclass 32, count 0 2006.211.08:06:47.79#ibcon#about to read 4, iclass 32, count 0 2006.211.08:06:47.79#ibcon#read 4, iclass 32, count 0 2006.211.08:06:47.79#ibcon#about to read 5, iclass 32, count 0 2006.211.08:06:47.79#ibcon#read 5, iclass 32, count 0 2006.211.08:06:47.79#ibcon#about to read 6, iclass 32, count 0 2006.211.08:06:47.79#ibcon#read 6, iclass 32, count 0 2006.211.08:06:47.79#ibcon#end of sib2, iclass 32, count 0 2006.211.08:06:47.79#ibcon#*after write, iclass 32, count 0 2006.211.08:06:47.79#ibcon#*before return 0, iclass 32, count 0 2006.211.08:06:47.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:47.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:47.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:06:47.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:06:47.79$vc4f8/valo=2,572.99 2006.211.08:06:47.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:06:47.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:06:47.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:47.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:47.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:47.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:47.79#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:06:47.79#ibcon#first serial, iclass 34, count 0 2006.211.08:06:47.79#ibcon#enter sib2, iclass 34, count 0 2006.211.08:06:47.79#ibcon#flushed, iclass 34, count 0 2006.211.08:06:47.79#ibcon#about to write, iclass 34, count 0 2006.211.08:06:47.79#ibcon#wrote, iclass 34, count 0 2006.211.08:06:47.79#ibcon#about to read 3, iclass 34, count 0 2006.211.08:06:47.81#ibcon#read 3, iclass 34, count 0 2006.211.08:06:47.81#ibcon#about to read 4, iclass 34, count 0 2006.211.08:06:47.81#ibcon#read 4, iclass 34, count 0 2006.211.08:06:47.81#ibcon#about to read 5, iclass 34, count 0 2006.211.08:06:47.81#ibcon#read 5, iclass 34, count 0 2006.211.08:06:47.81#ibcon#about to read 6, iclass 34, count 0 2006.211.08:06:47.81#ibcon#read 6, iclass 34, count 0 2006.211.08:06:47.81#ibcon#end of sib2, iclass 34, count 0 2006.211.08:06:47.81#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:06:47.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:06:47.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:06:47.81#ibcon#*before write, iclass 34, count 0 2006.211.08:06:47.81#ibcon#enter sib2, iclass 34, count 0 2006.211.08:06:47.81#ibcon#flushed, iclass 34, count 0 2006.211.08:06:47.81#ibcon#about to write, iclass 34, count 0 2006.211.08:06:47.81#ibcon#wrote, iclass 34, count 0 2006.211.08:06:47.81#ibcon#about to read 3, iclass 34, count 0 2006.211.08:06:47.85#ibcon#read 3, iclass 34, count 0 2006.211.08:06:47.85#ibcon#about to read 4, iclass 34, count 0 2006.211.08:06:47.85#ibcon#read 4, iclass 34, count 0 2006.211.08:06:47.85#ibcon#about to read 5, iclass 34, count 0 2006.211.08:06:47.85#ibcon#read 5, iclass 34, count 0 2006.211.08:06:47.85#ibcon#about to read 6, iclass 34, count 0 2006.211.08:06:47.85#ibcon#read 6, iclass 34, count 0 2006.211.08:06:47.85#ibcon#end of sib2, iclass 34, count 0 2006.211.08:06:47.85#ibcon#*after write, iclass 34, count 0 2006.211.08:06:47.85#ibcon#*before return 0, iclass 34, count 0 2006.211.08:06:47.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:47.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:47.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:06:47.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:06:47.85$vc4f8/va=2,7 2006.211.08:06:47.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:06:47.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:06:47.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:47.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:47.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:47.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:47.91#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:06:47.91#ibcon#first serial, iclass 36, count 2 2006.211.08:06:47.91#ibcon#enter sib2, iclass 36, count 2 2006.211.08:06:47.91#ibcon#flushed, iclass 36, count 2 2006.211.08:06:47.91#ibcon#about to write, iclass 36, count 2 2006.211.08:06:47.91#ibcon#wrote, iclass 36, count 2 2006.211.08:06:47.91#ibcon#about to read 3, iclass 36, count 2 2006.211.08:06:47.93#ibcon#read 3, iclass 36, count 2 2006.211.08:06:47.93#ibcon#about to read 4, iclass 36, count 2 2006.211.08:06:47.93#ibcon#read 4, iclass 36, count 2 2006.211.08:06:47.93#ibcon#about to read 5, iclass 36, count 2 2006.211.08:06:47.93#ibcon#read 5, iclass 36, count 2 2006.211.08:06:47.93#ibcon#about to read 6, iclass 36, count 2 2006.211.08:06:47.93#ibcon#read 6, iclass 36, count 2 2006.211.08:06:47.93#ibcon#end of sib2, iclass 36, count 2 2006.211.08:06:47.93#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:06:47.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:06:47.93#ibcon#[25=AT02-07\r\n] 2006.211.08:06:47.93#ibcon#*before write, iclass 36, count 2 2006.211.08:06:47.93#ibcon#enter sib2, iclass 36, count 2 2006.211.08:06:47.93#ibcon#flushed, iclass 36, count 2 2006.211.08:06:47.93#ibcon#about to write, iclass 36, count 2 2006.211.08:06:47.93#ibcon#wrote, iclass 36, count 2 2006.211.08:06:47.93#ibcon#about to read 3, iclass 36, count 2 2006.211.08:06:47.96#ibcon#read 3, iclass 36, count 2 2006.211.08:06:47.96#ibcon#about to read 4, iclass 36, count 2 2006.211.08:06:47.96#ibcon#read 4, iclass 36, count 2 2006.211.08:06:47.96#ibcon#about to read 5, iclass 36, count 2 2006.211.08:06:47.96#ibcon#read 5, iclass 36, count 2 2006.211.08:06:47.96#ibcon#about to read 6, iclass 36, count 2 2006.211.08:06:47.96#ibcon#read 6, iclass 36, count 2 2006.211.08:06:47.96#ibcon#end of sib2, iclass 36, count 2 2006.211.08:06:47.96#ibcon#*after write, iclass 36, count 2 2006.211.08:06:47.96#ibcon#*before return 0, iclass 36, count 2 2006.211.08:06:47.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:47.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:47.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:06:47.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:47.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:48.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:48.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:48.08#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:06:48.08#ibcon#first serial, iclass 36, count 0 2006.211.08:06:48.08#ibcon#enter sib2, iclass 36, count 0 2006.211.08:06:48.08#ibcon#flushed, iclass 36, count 0 2006.211.08:06:48.08#ibcon#about to write, iclass 36, count 0 2006.211.08:06:48.08#ibcon#wrote, iclass 36, count 0 2006.211.08:06:48.08#ibcon#about to read 3, iclass 36, count 0 2006.211.08:06:48.10#ibcon#read 3, iclass 36, count 0 2006.211.08:06:48.10#ibcon#about to read 4, iclass 36, count 0 2006.211.08:06:48.10#ibcon#read 4, iclass 36, count 0 2006.211.08:06:48.10#ibcon#about to read 5, iclass 36, count 0 2006.211.08:06:48.10#ibcon#read 5, iclass 36, count 0 2006.211.08:06:48.10#ibcon#about to read 6, iclass 36, count 0 2006.211.08:06:48.10#ibcon#read 6, iclass 36, count 0 2006.211.08:06:48.10#ibcon#end of sib2, iclass 36, count 0 2006.211.08:06:48.10#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:06:48.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:06:48.10#ibcon#[25=USB\r\n] 2006.211.08:06:48.10#ibcon#*before write, iclass 36, count 0 2006.211.08:06:48.10#ibcon#enter sib2, iclass 36, count 0 2006.211.08:06:48.10#ibcon#flushed, iclass 36, count 0 2006.211.08:06:48.10#ibcon#about to write, iclass 36, count 0 2006.211.08:06:48.10#ibcon#wrote, iclass 36, count 0 2006.211.08:06:48.10#ibcon#about to read 3, iclass 36, count 0 2006.211.08:06:48.13#ibcon#read 3, iclass 36, count 0 2006.211.08:06:48.13#ibcon#about to read 4, iclass 36, count 0 2006.211.08:06:48.13#ibcon#read 4, iclass 36, count 0 2006.211.08:06:48.13#ibcon#about to read 5, iclass 36, count 0 2006.211.08:06:48.13#ibcon#read 5, iclass 36, count 0 2006.211.08:06:48.13#ibcon#about to read 6, iclass 36, count 0 2006.211.08:06:48.13#ibcon#read 6, iclass 36, count 0 2006.211.08:06:48.13#ibcon#end of sib2, iclass 36, count 0 2006.211.08:06:48.13#ibcon#*after write, iclass 36, count 0 2006.211.08:06:48.13#ibcon#*before return 0, iclass 36, count 0 2006.211.08:06:48.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:48.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:48.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:06:48.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:06:48.13$vc4f8/valo=3,672.99 2006.211.08:06:48.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:06:48.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:06:48.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:48.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:48.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:48.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:48.13#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:06:48.13#ibcon#first serial, iclass 38, count 0 2006.211.08:06:48.13#ibcon#enter sib2, iclass 38, count 0 2006.211.08:06:48.13#ibcon#flushed, iclass 38, count 0 2006.211.08:06:48.13#ibcon#about to write, iclass 38, count 0 2006.211.08:06:48.13#ibcon#wrote, iclass 38, count 0 2006.211.08:06:48.13#ibcon#about to read 3, iclass 38, count 0 2006.211.08:06:48.15#ibcon#read 3, iclass 38, count 0 2006.211.08:06:48.15#ibcon#about to read 4, iclass 38, count 0 2006.211.08:06:48.15#ibcon#read 4, iclass 38, count 0 2006.211.08:06:48.15#ibcon#about to read 5, iclass 38, count 0 2006.211.08:06:48.15#ibcon#read 5, iclass 38, count 0 2006.211.08:06:48.15#ibcon#about to read 6, iclass 38, count 0 2006.211.08:06:48.15#ibcon#read 6, iclass 38, count 0 2006.211.08:06:48.15#ibcon#end of sib2, iclass 38, count 0 2006.211.08:06:48.15#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:06:48.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:06:48.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:06:48.15#ibcon#*before write, iclass 38, count 0 2006.211.08:06:48.15#ibcon#enter sib2, iclass 38, count 0 2006.211.08:06:48.15#ibcon#flushed, iclass 38, count 0 2006.211.08:06:48.15#ibcon#about to write, iclass 38, count 0 2006.211.08:06:48.15#ibcon#wrote, iclass 38, count 0 2006.211.08:06:48.15#ibcon#about to read 3, iclass 38, count 0 2006.211.08:06:48.19#ibcon#read 3, iclass 38, count 0 2006.211.08:06:48.19#ibcon#about to read 4, iclass 38, count 0 2006.211.08:06:48.19#ibcon#read 4, iclass 38, count 0 2006.211.08:06:48.19#ibcon#about to read 5, iclass 38, count 0 2006.211.08:06:48.19#ibcon#read 5, iclass 38, count 0 2006.211.08:06:48.19#ibcon#about to read 6, iclass 38, count 0 2006.211.08:06:48.19#ibcon#read 6, iclass 38, count 0 2006.211.08:06:48.19#ibcon#end of sib2, iclass 38, count 0 2006.211.08:06:48.19#ibcon#*after write, iclass 38, count 0 2006.211.08:06:48.19#ibcon#*before return 0, iclass 38, count 0 2006.211.08:06:48.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:48.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:48.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:06:48.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:06:48.19$vc4f8/va=3,6 2006.211.08:06:48.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:06:48.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:06:48.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:48.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:48.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:48.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:48.25#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:06:48.25#ibcon#first serial, iclass 40, count 2 2006.211.08:06:48.25#ibcon#enter sib2, iclass 40, count 2 2006.211.08:06:48.25#ibcon#flushed, iclass 40, count 2 2006.211.08:06:48.25#ibcon#about to write, iclass 40, count 2 2006.211.08:06:48.25#ibcon#wrote, iclass 40, count 2 2006.211.08:06:48.25#ibcon#about to read 3, iclass 40, count 2 2006.211.08:06:48.27#ibcon#read 3, iclass 40, count 2 2006.211.08:06:48.27#ibcon#about to read 4, iclass 40, count 2 2006.211.08:06:48.27#ibcon#read 4, iclass 40, count 2 2006.211.08:06:48.27#ibcon#about to read 5, iclass 40, count 2 2006.211.08:06:48.27#ibcon#read 5, iclass 40, count 2 2006.211.08:06:48.27#ibcon#about to read 6, iclass 40, count 2 2006.211.08:06:48.27#ibcon#read 6, iclass 40, count 2 2006.211.08:06:48.27#ibcon#end of sib2, iclass 40, count 2 2006.211.08:06:48.27#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:06:48.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:06:48.27#ibcon#[25=AT03-06\r\n] 2006.211.08:06:48.27#ibcon#*before write, iclass 40, count 2 2006.211.08:06:48.27#ibcon#enter sib2, iclass 40, count 2 2006.211.08:06:48.27#ibcon#flushed, iclass 40, count 2 2006.211.08:06:48.27#ibcon#about to write, iclass 40, count 2 2006.211.08:06:48.27#ibcon#wrote, iclass 40, count 2 2006.211.08:06:48.27#ibcon#about to read 3, iclass 40, count 2 2006.211.08:06:48.30#ibcon#read 3, iclass 40, count 2 2006.211.08:06:48.30#ibcon#about to read 4, iclass 40, count 2 2006.211.08:06:48.30#ibcon#read 4, iclass 40, count 2 2006.211.08:06:48.30#ibcon#about to read 5, iclass 40, count 2 2006.211.08:06:48.30#ibcon#read 5, iclass 40, count 2 2006.211.08:06:48.30#ibcon#about to read 6, iclass 40, count 2 2006.211.08:06:48.30#ibcon#read 6, iclass 40, count 2 2006.211.08:06:48.30#ibcon#end of sib2, iclass 40, count 2 2006.211.08:06:48.30#ibcon#*after write, iclass 40, count 2 2006.211.08:06:48.30#ibcon#*before return 0, iclass 40, count 2 2006.211.08:06:48.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:48.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:48.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:06:48.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:48.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:48.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:48.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:48.42#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:06:48.42#ibcon#first serial, iclass 40, count 0 2006.211.08:06:48.42#ibcon#enter sib2, iclass 40, count 0 2006.211.08:06:48.42#ibcon#flushed, iclass 40, count 0 2006.211.08:06:48.42#ibcon#about to write, iclass 40, count 0 2006.211.08:06:48.42#ibcon#wrote, iclass 40, count 0 2006.211.08:06:48.42#ibcon#about to read 3, iclass 40, count 0 2006.211.08:06:48.44#ibcon#read 3, iclass 40, count 0 2006.211.08:06:48.44#ibcon#about to read 4, iclass 40, count 0 2006.211.08:06:48.44#ibcon#read 4, iclass 40, count 0 2006.211.08:06:48.44#ibcon#about to read 5, iclass 40, count 0 2006.211.08:06:48.44#ibcon#read 5, iclass 40, count 0 2006.211.08:06:48.44#ibcon#about to read 6, iclass 40, count 0 2006.211.08:06:48.44#ibcon#read 6, iclass 40, count 0 2006.211.08:06:48.44#ibcon#end of sib2, iclass 40, count 0 2006.211.08:06:48.44#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:06:48.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:06:48.44#ibcon#[25=USB\r\n] 2006.211.08:06:48.44#ibcon#*before write, iclass 40, count 0 2006.211.08:06:48.44#ibcon#enter sib2, iclass 40, count 0 2006.211.08:06:48.44#ibcon#flushed, iclass 40, count 0 2006.211.08:06:48.44#ibcon#about to write, iclass 40, count 0 2006.211.08:06:48.44#ibcon#wrote, iclass 40, count 0 2006.211.08:06:48.44#ibcon#about to read 3, iclass 40, count 0 2006.211.08:06:48.47#ibcon#read 3, iclass 40, count 0 2006.211.08:06:48.47#ibcon#about to read 4, iclass 40, count 0 2006.211.08:06:48.47#ibcon#read 4, iclass 40, count 0 2006.211.08:06:48.47#ibcon#about to read 5, iclass 40, count 0 2006.211.08:06:48.47#ibcon#read 5, iclass 40, count 0 2006.211.08:06:48.47#ibcon#about to read 6, iclass 40, count 0 2006.211.08:06:48.47#ibcon#read 6, iclass 40, count 0 2006.211.08:06:48.47#ibcon#end of sib2, iclass 40, count 0 2006.211.08:06:48.47#ibcon#*after write, iclass 40, count 0 2006.211.08:06:48.47#ibcon#*before return 0, iclass 40, count 0 2006.211.08:06:48.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:48.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:48.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:06:48.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:06:48.47$vc4f8/valo=4,832.99 2006.211.08:06:48.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:06:48.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:06:48.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:48.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:48.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:48.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:48.47#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:06:48.47#ibcon#first serial, iclass 4, count 0 2006.211.08:06:48.47#ibcon#enter sib2, iclass 4, count 0 2006.211.08:06:48.47#ibcon#flushed, iclass 4, count 0 2006.211.08:06:48.47#ibcon#about to write, iclass 4, count 0 2006.211.08:06:48.47#ibcon#wrote, iclass 4, count 0 2006.211.08:06:48.47#ibcon#about to read 3, iclass 4, count 0 2006.211.08:06:48.49#ibcon#read 3, iclass 4, count 0 2006.211.08:06:48.49#ibcon#about to read 4, iclass 4, count 0 2006.211.08:06:48.49#ibcon#read 4, iclass 4, count 0 2006.211.08:06:48.49#ibcon#about to read 5, iclass 4, count 0 2006.211.08:06:48.49#ibcon#read 5, iclass 4, count 0 2006.211.08:06:48.49#ibcon#about to read 6, iclass 4, count 0 2006.211.08:06:48.49#ibcon#read 6, iclass 4, count 0 2006.211.08:06:48.49#ibcon#end of sib2, iclass 4, count 0 2006.211.08:06:48.49#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:06:48.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:06:48.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:06:48.49#ibcon#*before write, iclass 4, count 0 2006.211.08:06:48.49#ibcon#enter sib2, iclass 4, count 0 2006.211.08:06:48.49#ibcon#flushed, iclass 4, count 0 2006.211.08:06:48.49#ibcon#about to write, iclass 4, count 0 2006.211.08:06:48.49#ibcon#wrote, iclass 4, count 0 2006.211.08:06:48.49#ibcon#about to read 3, iclass 4, count 0 2006.211.08:06:48.53#ibcon#read 3, iclass 4, count 0 2006.211.08:06:48.53#ibcon#about to read 4, iclass 4, count 0 2006.211.08:06:48.53#ibcon#read 4, iclass 4, count 0 2006.211.08:06:48.53#ibcon#about to read 5, iclass 4, count 0 2006.211.08:06:48.53#ibcon#read 5, iclass 4, count 0 2006.211.08:06:48.53#ibcon#about to read 6, iclass 4, count 0 2006.211.08:06:48.53#ibcon#read 6, iclass 4, count 0 2006.211.08:06:48.53#ibcon#end of sib2, iclass 4, count 0 2006.211.08:06:48.53#ibcon#*after write, iclass 4, count 0 2006.211.08:06:48.53#ibcon#*before return 0, iclass 4, count 0 2006.211.08:06:48.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:48.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:48.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:06:48.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:06:48.53$vc4f8/va=4,7 2006.211.08:06:48.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:06:48.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:06:48.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:48.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:48.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:48.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:48.59#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:06:48.59#ibcon#first serial, iclass 6, count 2 2006.211.08:06:48.59#ibcon#enter sib2, iclass 6, count 2 2006.211.08:06:48.59#ibcon#flushed, iclass 6, count 2 2006.211.08:06:48.59#ibcon#about to write, iclass 6, count 2 2006.211.08:06:48.59#ibcon#wrote, iclass 6, count 2 2006.211.08:06:48.59#ibcon#about to read 3, iclass 6, count 2 2006.211.08:06:48.61#ibcon#read 3, iclass 6, count 2 2006.211.08:06:48.61#ibcon#about to read 4, iclass 6, count 2 2006.211.08:06:48.61#ibcon#read 4, iclass 6, count 2 2006.211.08:06:48.61#ibcon#about to read 5, iclass 6, count 2 2006.211.08:06:48.61#ibcon#read 5, iclass 6, count 2 2006.211.08:06:48.61#ibcon#about to read 6, iclass 6, count 2 2006.211.08:06:48.61#ibcon#read 6, iclass 6, count 2 2006.211.08:06:48.61#ibcon#end of sib2, iclass 6, count 2 2006.211.08:06:48.61#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:06:48.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:06:48.61#ibcon#[25=AT04-07\r\n] 2006.211.08:06:48.61#ibcon#*before write, iclass 6, count 2 2006.211.08:06:48.61#ibcon#enter sib2, iclass 6, count 2 2006.211.08:06:48.61#ibcon#flushed, iclass 6, count 2 2006.211.08:06:48.61#ibcon#about to write, iclass 6, count 2 2006.211.08:06:48.61#ibcon#wrote, iclass 6, count 2 2006.211.08:06:48.61#ibcon#about to read 3, iclass 6, count 2 2006.211.08:06:48.64#ibcon#read 3, iclass 6, count 2 2006.211.08:06:48.64#ibcon#about to read 4, iclass 6, count 2 2006.211.08:06:48.64#ibcon#read 4, iclass 6, count 2 2006.211.08:06:48.64#ibcon#about to read 5, iclass 6, count 2 2006.211.08:06:48.64#ibcon#read 5, iclass 6, count 2 2006.211.08:06:48.64#ibcon#about to read 6, iclass 6, count 2 2006.211.08:06:48.64#ibcon#read 6, iclass 6, count 2 2006.211.08:06:48.64#ibcon#end of sib2, iclass 6, count 2 2006.211.08:06:48.64#ibcon#*after write, iclass 6, count 2 2006.211.08:06:48.64#ibcon#*before return 0, iclass 6, count 2 2006.211.08:06:48.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:48.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:48.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:06:48.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:48.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:48.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:48.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:48.76#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:06:48.76#ibcon#first serial, iclass 6, count 0 2006.211.08:06:48.76#ibcon#enter sib2, iclass 6, count 0 2006.211.08:06:48.76#ibcon#flushed, iclass 6, count 0 2006.211.08:06:48.76#ibcon#about to write, iclass 6, count 0 2006.211.08:06:48.76#ibcon#wrote, iclass 6, count 0 2006.211.08:06:48.76#ibcon#about to read 3, iclass 6, count 0 2006.211.08:06:48.78#ibcon#read 3, iclass 6, count 0 2006.211.08:06:48.78#ibcon#about to read 4, iclass 6, count 0 2006.211.08:06:48.78#ibcon#read 4, iclass 6, count 0 2006.211.08:06:48.78#ibcon#about to read 5, iclass 6, count 0 2006.211.08:06:48.78#ibcon#read 5, iclass 6, count 0 2006.211.08:06:48.78#ibcon#about to read 6, iclass 6, count 0 2006.211.08:06:48.78#ibcon#read 6, iclass 6, count 0 2006.211.08:06:48.78#ibcon#end of sib2, iclass 6, count 0 2006.211.08:06:48.78#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:06:48.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:06:48.78#ibcon#[25=USB\r\n] 2006.211.08:06:48.78#ibcon#*before write, iclass 6, count 0 2006.211.08:06:48.78#ibcon#enter sib2, iclass 6, count 0 2006.211.08:06:48.78#ibcon#flushed, iclass 6, count 0 2006.211.08:06:48.78#ibcon#about to write, iclass 6, count 0 2006.211.08:06:48.78#ibcon#wrote, iclass 6, count 0 2006.211.08:06:48.78#ibcon#about to read 3, iclass 6, count 0 2006.211.08:06:48.81#ibcon#read 3, iclass 6, count 0 2006.211.08:06:48.81#ibcon#about to read 4, iclass 6, count 0 2006.211.08:06:48.81#ibcon#read 4, iclass 6, count 0 2006.211.08:06:48.81#ibcon#about to read 5, iclass 6, count 0 2006.211.08:06:48.81#ibcon#read 5, iclass 6, count 0 2006.211.08:06:48.81#ibcon#about to read 6, iclass 6, count 0 2006.211.08:06:48.81#ibcon#read 6, iclass 6, count 0 2006.211.08:06:48.81#ibcon#end of sib2, iclass 6, count 0 2006.211.08:06:48.81#ibcon#*after write, iclass 6, count 0 2006.211.08:06:48.81#ibcon#*before return 0, iclass 6, count 0 2006.211.08:06:48.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:48.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:48.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:06:48.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:06:48.81$vc4f8/valo=5,652.99 2006.211.08:06:48.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:06:48.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:06:48.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:48.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:48.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:48.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:48.81#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:06:48.81#ibcon#first serial, iclass 10, count 0 2006.211.08:06:48.81#ibcon#enter sib2, iclass 10, count 0 2006.211.08:06:48.81#ibcon#flushed, iclass 10, count 0 2006.211.08:06:48.81#ibcon#about to write, iclass 10, count 0 2006.211.08:06:48.81#ibcon#wrote, iclass 10, count 0 2006.211.08:06:48.81#ibcon#about to read 3, iclass 10, count 0 2006.211.08:06:48.83#ibcon#read 3, iclass 10, count 0 2006.211.08:06:48.83#ibcon#about to read 4, iclass 10, count 0 2006.211.08:06:48.83#ibcon#read 4, iclass 10, count 0 2006.211.08:06:48.83#ibcon#about to read 5, iclass 10, count 0 2006.211.08:06:48.83#ibcon#read 5, iclass 10, count 0 2006.211.08:06:48.83#ibcon#about to read 6, iclass 10, count 0 2006.211.08:06:48.83#ibcon#read 6, iclass 10, count 0 2006.211.08:06:48.83#ibcon#end of sib2, iclass 10, count 0 2006.211.08:06:48.83#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:06:48.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:06:48.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:06:48.83#ibcon#*before write, iclass 10, count 0 2006.211.08:06:48.83#ibcon#enter sib2, iclass 10, count 0 2006.211.08:06:48.83#ibcon#flushed, iclass 10, count 0 2006.211.08:06:48.83#ibcon#about to write, iclass 10, count 0 2006.211.08:06:48.83#ibcon#wrote, iclass 10, count 0 2006.211.08:06:48.83#ibcon#about to read 3, iclass 10, count 0 2006.211.08:06:48.87#ibcon#read 3, iclass 10, count 0 2006.211.08:06:48.87#ibcon#about to read 4, iclass 10, count 0 2006.211.08:06:48.87#ibcon#read 4, iclass 10, count 0 2006.211.08:06:48.87#ibcon#about to read 5, iclass 10, count 0 2006.211.08:06:48.87#ibcon#read 5, iclass 10, count 0 2006.211.08:06:48.87#ibcon#about to read 6, iclass 10, count 0 2006.211.08:06:48.87#ibcon#read 6, iclass 10, count 0 2006.211.08:06:48.87#ibcon#end of sib2, iclass 10, count 0 2006.211.08:06:48.87#ibcon#*after write, iclass 10, count 0 2006.211.08:06:48.87#ibcon#*before return 0, iclass 10, count 0 2006.211.08:06:48.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:48.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:48.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:06:48.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:06:48.87$vc4f8/va=5,7 2006.211.08:06:48.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:06:48.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:06:48.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:48.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:48.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:48.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:48.93#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:06:48.93#ibcon#first serial, iclass 12, count 2 2006.211.08:06:48.93#ibcon#enter sib2, iclass 12, count 2 2006.211.08:06:48.93#ibcon#flushed, iclass 12, count 2 2006.211.08:06:48.93#ibcon#about to write, iclass 12, count 2 2006.211.08:06:48.93#ibcon#wrote, iclass 12, count 2 2006.211.08:06:48.93#ibcon#about to read 3, iclass 12, count 2 2006.211.08:06:48.95#ibcon#read 3, iclass 12, count 2 2006.211.08:06:48.95#ibcon#about to read 4, iclass 12, count 2 2006.211.08:06:48.95#ibcon#read 4, iclass 12, count 2 2006.211.08:06:48.95#ibcon#about to read 5, iclass 12, count 2 2006.211.08:06:48.95#ibcon#read 5, iclass 12, count 2 2006.211.08:06:48.95#ibcon#about to read 6, iclass 12, count 2 2006.211.08:06:48.95#ibcon#read 6, iclass 12, count 2 2006.211.08:06:48.95#ibcon#end of sib2, iclass 12, count 2 2006.211.08:06:48.95#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:06:48.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:06:48.95#ibcon#[25=AT05-07\r\n] 2006.211.08:06:48.95#ibcon#*before write, iclass 12, count 2 2006.211.08:06:48.95#ibcon#enter sib2, iclass 12, count 2 2006.211.08:06:48.95#ibcon#flushed, iclass 12, count 2 2006.211.08:06:48.95#ibcon#about to write, iclass 12, count 2 2006.211.08:06:48.95#ibcon#wrote, iclass 12, count 2 2006.211.08:06:48.95#ibcon#about to read 3, iclass 12, count 2 2006.211.08:06:48.98#ibcon#read 3, iclass 12, count 2 2006.211.08:06:48.98#ibcon#about to read 4, iclass 12, count 2 2006.211.08:06:48.98#ibcon#read 4, iclass 12, count 2 2006.211.08:06:48.98#ibcon#about to read 5, iclass 12, count 2 2006.211.08:06:48.98#ibcon#read 5, iclass 12, count 2 2006.211.08:06:48.98#ibcon#about to read 6, iclass 12, count 2 2006.211.08:06:48.98#ibcon#read 6, iclass 12, count 2 2006.211.08:06:48.98#ibcon#end of sib2, iclass 12, count 2 2006.211.08:06:48.98#ibcon#*after write, iclass 12, count 2 2006.211.08:06:48.98#ibcon#*before return 0, iclass 12, count 2 2006.211.08:06:48.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:48.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:48.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:06:48.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:48.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:49.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:49.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:49.10#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:06:49.10#ibcon#first serial, iclass 12, count 0 2006.211.08:06:49.10#ibcon#enter sib2, iclass 12, count 0 2006.211.08:06:49.10#ibcon#flushed, iclass 12, count 0 2006.211.08:06:49.10#ibcon#about to write, iclass 12, count 0 2006.211.08:06:49.10#ibcon#wrote, iclass 12, count 0 2006.211.08:06:49.10#ibcon#about to read 3, iclass 12, count 0 2006.211.08:06:49.12#ibcon#read 3, iclass 12, count 0 2006.211.08:06:49.12#ibcon#about to read 4, iclass 12, count 0 2006.211.08:06:49.12#ibcon#read 4, iclass 12, count 0 2006.211.08:06:49.12#ibcon#about to read 5, iclass 12, count 0 2006.211.08:06:49.12#ibcon#read 5, iclass 12, count 0 2006.211.08:06:49.12#ibcon#about to read 6, iclass 12, count 0 2006.211.08:06:49.12#ibcon#read 6, iclass 12, count 0 2006.211.08:06:49.12#ibcon#end of sib2, iclass 12, count 0 2006.211.08:06:49.12#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:06:49.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:06:49.12#ibcon#[25=USB\r\n] 2006.211.08:06:49.12#ibcon#*before write, iclass 12, count 0 2006.211.08:06:49.12#ibcon#enter sib2, iclass 12, count 0 2006.211.08:06:49.12#ibcon#flushed, iclass 12, count 0 2006.211.08:06:49.12#ibcon#about to write, iclass 12, count 0 2006.211.08:06:49.12#ibcon#wrote, iclass 12, count 0 2006.211.08:06:49.12#ibcon#about to read 3, iclass 12, count 0 2006.211.08:06:49.15#ibcon#read 3, iclass 12, count 0 2006.211.08:06:49.15#ibcon#about to read 4, iclass 12, count 0 2006.211.08:06:49.15#ibcon#read 4, iclass 12, count 0 2006.211.08:06:49.15#ibcon#about to read 5, iclass 12, count 0 2006.211.08:06:49.15#ibcon#read 5, iclass 12, count 0 2006.211.08:06:49.15#ibcon#about to read 6, iclass 12, count 0 2006.211.08:06:49.15#ibcon#read 6, iclass 12, count 0 2006.211.08:06:49.15#ibcon#end of sib2, iclass 12, count 0 2006.211.08:06:49.15#ibcon#*after write, iclass 12, count 0 2006.211.08:06:49.15#ibcon#*before return 0, iclass 12, count 0 2006.211.08:06:49.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:49.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:49.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:06:49.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:06:49.15$vc4f8/valo=6,772.99 2006.211.08:06:49.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:06:49.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:06:49.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:49.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:49.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:49.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:49.15#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:06:49.15#ibcon#first serial, iclass 14, count 0 2006.211.08:06:49.15#ibcon#enter sib2, iclass 14, count 0 2006.211.08:06:49.15#ibcon#flushed, iclass 14, count 0 2006.211.08:06:49.15#ibcon#about to write, iclass 14, count 0 2006.211.08:06:49.15#ibcon#wrote, iclass 14, count 0 2006.211.08:06:49.15#ibcon#about to read 3, iclass 14, count 0 2006.211.08:06:49.17#ibcon#read 3, iclass 14, count 0 2006.211.08:06:49.17#ibcon#about to read 4, iclass 14, count 0 2006.211.08:06:49.17#ibcon#read 4, iclass 14, count 0 2006.211.08:06:49.17#ibcon#about to read 5, iclass 14, count 0 2006.211.08:06:49.17#ibcon#read 5, iclass 14, count 0 2006.211.08:06:49.17#ibcon#about to read 6, iclass 14, count 0 2006.211.08:06:49.17#ibcon#read 6, iclass 14, count 0 2006.211.08:06:49.17#ibcon#end of sib2, iclass 14, count 0 2006.211.08:06:49.17#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:06:49.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:06:49.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:06:49.17#ibcon#*before write, iclass 14, count 0 2006.211.08:06:49.17#ibcon#enter sib2, iclass 14, count 0 2006.211.08:06:49.17#ibcon#flushed, iclass 14, count 0 2006.211.08:06:49.17#ibcon#about to write, iclass 14, count 0 2006.211.08:06:49.17#ibcon#wrote, iclass 14, count 0 2006.211.08:06:49.17#ibcon#about to read 3, iclass 14, count 0 2006.211.08:06:49.21#ibcon#read 3, iclass 14, count 0 2006.211.08:06:49.21#ibcon#about to read 4, iclass 14, count 0 2006.211.08:06:49.21#ibcon#read 4, iclass 14, count 0 2006.211.08:06:49.21#ibcon#about to read 5, iclass 14, count 0 2006.211.08:06:49.21#ibcon#read 5, iclass 14, count 0 2006.211.08:06:49.21#ibcon#about to read 6, iclass 14, count 0 2006.211.08:06:49.21#ibcon#read 6, iclass 14, count 0 2006.211.08:06:49.21#ibcon#end of sib2, iclass 14, count 0 2006.211.08:06:49.21#ibcon#*after write, iclass 14, count 0 2006.211.08:06:49.21#ibcon#*before return 0, iclass 14, count 0 2006.211.08:06:49.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:49.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:49.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:06:49.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:06:49.21$vc4f8/va=6,6 2006.211.08:06:49.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:06:49.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:06:49.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:49.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:06:49.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:06:49.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:06:49.27#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:06:49.27#ibcon#first serial, iclass 16, count 2 2006.211.08:06:49.27#ibcon#enter sib2, iclass 16, count 2 2006.211.08:06:49.27#ibcon#flushed, iclass 16, count 2 2006.211.08:06:49.27#ibcon#about to write, iclass 16, count 2 2006.211.08:06:49.27#ibcon#wrote, iclass 16, count 2 2006.211.08:06:49.27#ibcon#about to read 3, iclass 16, count 2 2006.211.08:06:49.29#ibcon#read 3, iclass 16, count 2 2006.211.08:06:49.29#ibcon#about to read 4, iclass 16, count 2 2006.211.08:06:49.29#ibcon#read 4, iclass 16, count 2 2006.211.08:06:49.29#ibcon#about to read 5, iclass 16, count 2 2006.211.08:06:49.29#ibcon#read 5, iclass 16, count 2 2006.211.08:06:49.29#ibcon#about to read 6, iclass 16, count 2 2006.211.08:06:49.29#ibcon#read 6, iclass 16, count 2 2006.211.08:06:49.29#ibcon#end of sib2, iclass 16, count 2 2006.211.08:06:49.29#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:06:49.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:06:49.29#ibcon#[25=AT06-06\r\n] 2006.211.08:06:49.29#ibcon#*before write, iclass 16, count 2 2006.211.08:06:49.29#ibcon#enter sib2, iclass 16, count 2 2006.211.08:06:49.29#ibcon#flushed, iclass 16, count 2 2006.211.08:06:49.29#ibcon#about to write, iclass 16, count 2 2006.211.08:06:49.29#ibcon#wrote, iclass 16, count 2 2006.211.08:06:49.29#ibcon#about to read 3, iclass 16, count 2 2006.211.08:06:49.32#ibcon#read 3, iclass 16, count 2 2006.211.08:06:49.32#ibcon#about to read 4, iclass 16, count 2 2006.211.08:06:49.32#ibcon#read 4, iclass 16, count 2 2006.211.08:06:49.32#ibcon#about to read 5, iclass 16, count 2 2006.211.08:06:49.32#ibcon#read 5, iclass 16, count 2 2006.211.08:06:49.32#ibcon#about to read 6, iclass 16, count 2 2006.211.08:06:49.32#ibcon#read 6, iclass 16, count 2 2006.211.08:06:49.32#ibcon#end of sib2, iclass 16, count 2 2006.211.08:06:49.32#ibcon#*after write, iclass 16, count 2 2006.211.08:06:49.32#ibcon#*before return 0, iclass 16, count 2 2006.211.08:06:49.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:06:49.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:06:49.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:06:49.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:49.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:06:49.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:06:49.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:06:49.44#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:06:49.44#ibcon#first serial, iclass 16, count 0 2006.211.08:06:49.44#ibcon#enter sib2, iclass 16, count 0 2006.211.08:06:49.44#ibcon#flushed, iclass 16, count 0 2006.211.08:06:49.44#ibcon#about to write, iclass 16, count 0 2006.211.08:06:49.44#ibcon#wrote, iclass 16, count 0 2006.211.08:06:49.44#ibcon#about to read 3, iclass 16, count 0 2006.211.08:06:49.46#ibcon#read 3, iclass 16, count 0 2006.211.08:06:49.46#ibcon#about to read 4, iclass 16, count 0 2006.211.08:06:49.46#ibcon#read 4, iclass 16, count 0 2006.211.08:06:49.46#ibcon#about to read 5, iclass 16, count 0 2006.211.08:06:49.46#ibcon#read 5, iclass 16, count 0 2006.211.08:06:49.46#ibcon#about to read 6, iclass 16, count 0 2006.211.08:06:49.46#ibcon#read 6, iclass 16, count 0 2006.211.08:06:49.46#ibcon#end of sib2, iclass 16, count 0 2006.211.08:06:49.46#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:06:49.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:06:49.46#ibcon#[25=USB\r\n] 2006.211.08:06:49.46#ibcon#*before write, iclass 16, count 0 2006.211.08:06:49.46#ibcon#enter sib2, iclass 16, count 0 2006.211.08:06:49.46#ibcon#flushed, iclass 16, count 0 2006.211.08:06:49.46#ibcon#about to write, iclass 16, count 0 2006.211.08:06:49.46#ibcon#wrote, iclass 16, count 0 2006.211.08:06:49.46#ibcon#about to read 3, iclass 16, count 0 2006.211.08:06:49.49#ibcon#read 3, iclass 16, count 0 2006.211.08:06:49.49#ibcon#about to read 4, iclass 16, count 0 2006.211.08:06:49.49#ibcon#read 4, iclass 16, count 0 2006.211.08:06:49.49#ibcon#about to read 5, iclass 16, count 0 2006.211.08:06:49.49#ibcon#read 5, iclass 16, count 0 2006.211.08:06:49.49#ibcon#about to read 6, iclass 16, count 0 2006.211.08:06:49.49#ibcon#read 6, iclass 16, count 0 2006.211.08:06:49.49#ibcon#end of sib2, iclass 16, count 0 2006.211.08:06:49.49#ibcon#*after write, iclass 16, count 0 2006.211.08:06:49.49#ibcon#*before return 0, iclass 16, count 0 2006.211.08:06:49.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:06:49.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:06:49.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:06:49.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:06:49.49$vc4f8/valo=7,832.99 2006.211.08:06:49.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:06:49.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:06:49.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:49.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:06:49.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:06:49.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:06:49.49#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:06:49.49#ibcon#first serial, iclass 18, count 0 2006.211.08:06:49.49#ibcon#enter sib2, iclass 18, count 0 2006.211.08:06:49.49#ibcon#flushed, iclass 18, count 0 2006.211.08:06:49.49#ibcon#about to write, iclass 18, count 0 2006.211.08:06:49.49#ibcon#wrote, iclass 18, count 0 2006.211.08:06:49.49#ibcon#about to read 3, iclass 18, count 0 2006.211.08:06:49.51#ibcon#read 3, iclass 18, count 0 2006.211.08:06:49.51#ibcon#about to read 4, iclass 18, count 0 2006.211.08:06:49.51#ibcon#read 4, iclass 18, count 0 2006.211.08:06:49.51#ibcon#about to read 5, iclass 18, count 0 2006.211.08:06:49.51#ibcon#read 5, iclass 18, count 0 2006.211.08:06:49.51#ibcon#about to read 6, iclass 18, count 0 2006.211.08:06:49.51#ibcon#read 6, iclass 18, count 0 2006.211.08:06:49.51#ibcon#end of sib2, iclass 18, count 0 2006.211.08:06:49.51#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:06:49.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:06:49.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:06:49.51#ibcon#*before write, iclass 18, count 0 2006.211.08:06:49.51#ibcon#enter sib2, iclass 18, count 0 2006.211.08:06:49.51#ibcon#flushed, iclass 18, count 0 2006.211.08:06:49.51#ibcon#about to write, iclass 18, count 0 2006.211.08:06:49.51#ibcon#wrote, iclass 18, count 0 2006.211.08:06:49.51#ibcon#about to read 3, iclass 18, count 0 2006.211.08:06:49.55#ibcon#read 3, iclass 18, count 0 2006.211.08:06:49.55#ibcon#about to read 4, iclass 18, count 0 2006.211.08:06:49.55#ibcon#read 4, iclass 18, count 0 2006.211.08:06:49.55#ibcon#about to read 5, iclass 18, count 0 2006.211.08:06:49.55#ibcon#read 5, iclass 18, count 0 2006.211.08:06:49.55#ibcon#about to read 6, iclass 18, count 0 2006.211.08:06:49.55#ibcon#read 6, iclass 18, count 0 2006.211.08:06:49.55#ibcon#end of sib2, iclass 18, count 0 2006.211.08:06:49.55#ibcon#*after write, iclass 18, count 0 2006.211.08:06:49.55#ibcon#*before return 0, iclass 18, count 0 2006.211.08:06:49.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:06:49.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:06:49.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:06:49.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:06:49.55$vc4f8/va=7,6 2006.211.08:06:49.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:06:49.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:06:49.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:49.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:06:49.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:06:49.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:06:49.61#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:06:49.61#ibcon#first serial, iclass 20, count 2 2006.211.08:06:49.61#ibcon#enter sib2, iclass 20, count 2 2006.211.08:06:49.61#ibcon#flushed, iclass 20, count 2 2006.211.08:06:49.61#ibcon#about to write, iclass 20, count 2 2006.211.08:06:49.61#ibcon#wrote, iclass 20, count 2 2006.211.08:06:49.61#ibcon#about to read 3, iclass 20, count 2 2006.211.08:06:49.63#ibcon#read 3, iclass 20, count 2 2006.211.08:06:49.63#ibcon#about to read 4, iclass 20, count 2 2006.211.08:06:49.63#ibcon#read 4, iclass 20, count 2 2006.211.08:06:49.63#ibcon#about to read 5, iclass 20, count 2 2006.211.08:06:49.63#ibcon#read 5, iclass 20, count 2 2006.211.08:06:49.63#ibcon#about to read 6, iclass 20, count 2 2006.211.08:06:49.63#ibcon#read 6, iclass 20, count 2 2006.211.08:06:49.63#ibcon#end of sib2, iclass 20, count 2 2006.211.08:06:49.63#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:06:49.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:06:49.63#ibcon#[25=AT07-06\r\n] 2006.211.08:06:49.63#ibcon#*before write, iclass 20, count 2 2006.211.08:06:49.63#ibcon#enter sib2, iclass 20, count 2 2006.211.08:06:49.63#ibcon#flushed, iclass 20, count 2 2006.211.08:06:49.63#ibcon#about to write, iclass 20, count 2 2006.211.08:06:49.63#ibcon#wrote, iclass 20, count 2 2006.211.08:06:49.63#ibcon#about to read 3, iclass 20, count 2 2006.211.08:06:49.66#ibcon#read 3, iclass 20, count 2 2006.211.08:06:49.66#ibcon#about to read 4, iclass 20, count 2 2006.211.08:06:49.66#ibcon#read 4, iclass 20, count 2 2006.211.08:06:49.66#ibcon#about to read 5, iclass 20, count 2 2006.211.08:06:49.66#ibcon#read 5, iclass 20, count 2 2006.211.08:06:49.66#ibcon#about to read 6, iclass 20, count 2 2006.211.08:06:49.66#ibcon#read 6, iclass 20, count 2 2006.211.08:06:49.66#ibcon#end of sib2, iclass 20, count 2 2006.211.08:06:49.66#ibcon#*after write, iclass 20, count 2 2006.211.08:06:49.66#ibcon#*before return 0, iclass 20, count 2 2006.211.08:06:49.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:06:49.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:06:49.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:06:49.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:49.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:06:49.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:06:49.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:06:49.78#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:06:49.78#ibcon#first serial, iclass 20, count 0 2006.211.08:06:49.78#ibcon#enter sib2, iclass 20, count 0 2006.211.08:06:49.78#ibcon#flushed, iclass 20, count 0 2006.211.08:06:49.78#ibcon#about to write, iclass 20, count 0 2006.211.08:06:49.78#ibcon#wrote, iclass 20, count 0 2006.211.08:06:49.78#ibcon#about to read 3, iclass 20, count 0 2006.211.08:06:49.80#ibcon#read 3, iclass 20, count 0 2006.211.08:06:49.80#ibcon#about to read 4, iclass 20, count 0 2006.211.08:06:49.80#ibcon#read 4, iclass 20, count 0 2006.211.08:06:49.80#ibcon#about to read 5, iclass 20, count 0 2006.211.08:06:49.80#ibcon#read 5, iclass 20, count 0 2006.211.08:06:49.80#ibcon#about to read 6, iclass 20, count 0 2006.211.08:06:49.80#ibcon#read 6, iclass 20, count 0 2006.211.08:06:49.80#ibcon#end of sib2, iclass 20, count 0 2006.211.08:06:49.80#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:06:49.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:06:49.80#ibcon#[25=USB\r\n] 2006.211.08:06:49.80#ibcon#*before write, iclass 20, count 0 2006.211.08:06:49.80#ibcon#enter sib2, iclass 20, count 0 2006.211.08:06:49.80#ibcon#flushed, iclass 20, count 0 2006.211.08:06:49.80#ibcon#about to write, iclass 20, count 0 2006.211.08:06:49.80#ibcon#wrote, iclass 20, count 0 2006.211.08:06:49.80#ibcon#about to read 3, iclass 20, count 0 2006.211.08:06:49.83#ibcon#read 3, iclass 20, count 0 2006.211.08:06:49.83#ibcon#about to read 4, iclass 20, count 0 2006.211.08:06:49.83#ibcon#read 4, iclass 20, count 0 2006.211.08:06:49.83#ibcon#about to read 5, iclass 20, count 0 2006.211.08:06:49.83#ibcon#read 5, iclass 20, count 0 2006.211.08:06:49.83#ibcon#about to read 6, iclass 20, count 0 2006.211.08:06:49.83#ibcon#read 6, iclass 20, count 0 2006.211.08:06:49.83#ibcon#end of sib2, iclass 20, count 0 2006.211.08:06:49.83#ibcon#*after write, iclass 20, count 0 2006.211.08:06:49.83#ibcon#*before return 0, iclass 20, count 0 2006.211.08:06:49.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:06:49.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:06:49.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:06:49.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:06:49.83$vc4f8/valo=8,852.99 2006.211.08:06:49.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:06:49.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:06:49.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:49.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:06:49.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:06:49.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:06:49.83#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:06:49.83#ibcon#first serial, iclass 22, count 0 2006.211.08:06:49.83#ibcon#enter sib2, iclass 22, count 0 2006.211.08:06:49.83#ibcon#flushed, iclass 22, count 0 2006.211.08:06:49.83#ibcon#about to write, iclass 22, count 0 2006.211.08:06:49.83#ibcon#wrote, iclass 22, count 0 2006.211.08:06:49.83#ibcon#about to read 3, iclass 22, count 0 2006.211.08:06:49.85#ibcon#read 3, iclass 22, count 0 2006.211.08:06:49.85#ibcon#about to read 4, iclass 22, count 0 2006.211.08:06:49.85#ibcon#read 4, iclass 22, count 0 2006.211.08:06:49.85#ibcon#about to read 5, iclass 22, count 0 2006.211.08:06:49.85#ibcon#read 5, iclass 22, count 0 2006.211.08:06:49.85#ibcon#about to read 6, iclass 22, count 0 2006.211.08:06:49.85#ibcon#read 6, iclass 22, count 0 2006.211.08:06:49.85#ibcon#end of sib2, iclass 22, count 0 2006.211.08:06:49.85#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:06:49.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:06:49.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:06:49.85#ibcon#*before write, iclass 22, count 0 2006.211.08:06:49.85#ibcon#enter sib2, iclass 22, count 0 2006.211.08:06:49.85#ibcon#flushed, iclass 22, count 0 2006.211.08:06:49.85#ibcon#about to write, iclass 22, count 0 2006.211.08:06:49.85#ibcon#wrote, iclass 22, count 0 2006.211.08:06:49.85#ibcon#about to read 3, iclass 22, count 0 2006.211.08:06:49.89#ibcon#read 3, iclass 22, count 0 2006.211.08:06:49.89#ibcon#about to read 4, iclass 22, count 0 2006.211.08:06:49.89#ibcon#read 4, iclass 22, count 0 2006.211.08:06:49.89#ibcon#about to read 5, iclass 22, count 0 2006.211.08:06:49.89#ibcon#read 5, iclass 22, count 0 2006.211.08:06:49.89#ibcon#about to read 6, iclass 22, count 0 2006.211.08:06:49.89#ibcon#read 6, iclass 22, count 0 2006.211.08:06:49.89#ibcon#end of sib2, iclass 22, count 0 2006.211.08:06:49.89#ibcon#*after write, iclass 22, count 0 2006.211.08:06:49.89#ibcon#*before return 0, iclass 22, count 0 2006.211.08:06:49.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:06:49.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:06:49.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:06:49.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:06:49.89$vc4f8/va=8,7 2006.211.08:06:49.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:06:49.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:06:49.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:49.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:06:49.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:06:49.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:06:49.95#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:06:49.95#ibcon#first serial, iclass 24, count 2 2006.211.08:06:49.95#ibcon#enter sib2, iclass 24, count 2 2006.211.08:06:49.95#ibcon#flushed, iclass 24, count 2 2006.211.08:06:49.95#ibcon#about to write, iclass 24, count 2 2006.211.08:06:49.95#ibcon#wrote, iclass 24, count 2 2006.211.08:06:49.95#ibcon#about to read 3, iclass 24, count 2 2006.211.08:06:49.97#ibcon#read 3, iclass 24, count 2 2006.211.08:06:49.97#ibcon#about to read 4, iclass 24, count 2 2006.211.08:06:49.97#ibcon#read 4, iclass 24, count 2 2006.211.08:06:49.97#ibcon#about to read 5, iclass 24, count 2 2006.211.08:06:49.97#ibcon#read 5, iclass 24, count 2 2006.211.08:06:49.97#ibcon#about to read 6, iclass 24, count 2 2006.211.08:06:49.97#ibcon#read 6, iclass 24, count 2 2006.211.08:06:49.97#ibcon#end of sib2, iclass 24, count 2 2006.211.08:06:49.97#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:06:49.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:06:49.97#ibcon#[25=AT08-07\r\n] 2006.211.08:06:49.97#ibcon#*before write, iclass 24, count 2 2006.211.08:06:49.97#ibcon#enter sib2, iclass 24, count 2 2006.211.08:06:49.97#ibcon#flushed, iclass 24, count 2 2006.211.08:06:49.97#ibcon#about to write, iclass 24, count 2 2006.211.08:06:49.97#ibcon#wrote, iclass 24, count 2 2006.211.08:06:49.97#ibcon#about to read 3, iclass 24, count 2 2006.211.08:06:50.00#ibcon#read 3, iclass 24, count 2 2006.211.08:06:50.00#ibcon#about to read 4, iclass 24, count 2 2006.211.08:06:50.00#ibcon#read 4, iclass 24, count 2 2006.211.08:06:50.00#ibcon#about to read 5, iclass 24, count 2 2006.211.08:06:50.00#ibcon#read 5, iclass 24, count 2 2006.211.08:06:50.00#ibcon#about to read 6, iclass 24, count 2 2006.211.08:06:50.00#ibcon#read 6, iclass 24, count 2 2006.211.08:06:50.00#ibcon#end of sib2, iclass 24, count 2 2006.211.08:06:50.00#ibcon#*after write, iclass 24, count 2 2006.211.08:06:50.00#ibcon#*before return 0, iclass 24, count 2 2006.211.08:06:50.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:06:50.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:06:50.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:06:50.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:50.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:06:50.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:06:50.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:06:50.12#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:06:50.12#ibcon#first serial, iclass 24, count 0 2006.211.08:06:50.12#ibcon#enter sib2, iclass 24, count 0 2006.211.08:06:50.12#ibcon#flushed, iclass 24, count 0 2006.211.08:06:50.12#ibcon#about to write, iclass 24, count 0 2006.211.08:06:50.12#ibcon#wrote, iclass 24, count 0 2006.211.08:06:50.12#ibcon#about to read 3, iclass 24, count 0 2006.211.08:06:50.14#ibcon#read 3, iclass 24, count 0 2006.211.08:06:50.14#ibcon#about to read 4, iclass 24, count 0 2006.211.08:06:50.14#ibcon#read 4, iclass 24, count 0 2006.211.08:06:50.14#ibcon#about to read 5, iclass 24, count 0 2006.211.08:06:50.14#ibcon#read 5, iclass 24, count 0 2006.211.08:06:50.14#ibcon#about to read 6, iclass 24, count 0 2006.211.08:06:50.14#ibcon#read 6, iclass 24, count 0 2006.211.08:06:50.14#ibcon#end of sib2, iclass 24, count 0 2006.211.08:06:50.14#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:06:50.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:06:50.14#ibcon#[25=USB\r\n] 2006.211.08:06:50.14#ibcon#*before write, iclass 24, count 0 2006.211.08:06:50.14#ibcon#enter sib2, iclass 24, count 0 2006.211.08:06:50.14#ibcon#flushed, iclass 24, count 0 2006.211.08:06:50.14#ibcon#about to write, iclass 24, count 0 2006.211.08:06:50.14#ibcon#wrote, iclass 24, count 0 2006.211.08:06:50.14#ibcon#about to read 3, iclass 24, count 0 2006.211.08:06:50.17#ibcon#read 3, iclass 24, count 0 2006.211.08:06:50.17#ibcon#about to read 4, iclass 24, count 0 2006.211.08:06:50.17#ibcon#read 4, iclass 24, count 0 2006.211.08:06:50.17#ibcon#about to read 5, iclass 24, count 0 2006.211.08:06:50.17#ibcon#read 5, iclass 24, count 0 2006.211.08:06:50.17#ibcon#about to read 6, iclass 24, count 0 2006.211.08:06:50.17#ibcon#read 6, iclass 24, count 0 2006.211.08:06:50.17#ibcon#end of sib2, iclass 24, count 0 2006.211.08:06:50.17#ibcon#*after write, iclass 24, count 0 2006.211.08:06:50.17#ibcon#*before return 0, iclass 24, count 0 2006.211.08:06:50.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:06:50.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:06:50.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:06:50.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:06:50.17$vc4f8/vblo=1,632.99 2006.211.08:06:50.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:06:50.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:06:50.17#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:50.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:06:50.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:06:50.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:06:50.17#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:06:50.17#ibcon#first serial, iclass 26, count 0 2006.211.08:06:50.17#ibcon#enter sib2, iclass 26, count 0 2006.211.08:06:50.17#ibcon#flushed, iclass 26, count 0 2006.211.08:06:50.17#ibcon#about to write, iclass 26, count 0 2006.211.08:06:50.17#ibcon#wrote, iclass 26, count 0 2006.211.08:06:50.17#ibcon#about to read 3, iclass 26, count 0 2006.211.08:06:50.19#ibcon#read 3, iclass 26, count 0 2006.211.08:06:50.19#ibcon#about to read 4, iclass 26, count 0 2006.211.08:06:50.19#ibcon#read 4, iclass 26, count 0 2006.211.08:06:50.19#ibcon#about to read 5, iclass 26, count 0 2006.211.08:06:50.19#ibcon#read 5, iclass 26, count 0 2006.211.08:06:50.19#ibcon#about to read 6, iclass 26, count 0 2006.211.08:06:50.19#ibcon#read 6, iclass 26, count 0 2006.211.08:06:50.19#ibcon#end of sib2, iclass 26, count 0 2006.211.08:06:50.19#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:06:50.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:06:50.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:06:50.19#ibcon#*before write, iclass 26, count 0 2006.211.08:06:50.19#ibcon#enter sib2, iclass 26, count 0 2006.211.08:06:50.19#ibcon#flushed, iclass 26, count 0 2006.211.08:06:50.19#ibcon#about to write, iclass 26, count 0 2006.211.08:06:50.19#ibcon#wrote, iclass 26, count 0 2006.211.08:06:50.19#ibcon#about to read 3, iclass 26, count 0 2006.211.08:06:50.23#ibcon#read 3, iclass 26, count 0 2006.211.08:06:50.23#ibcon#about to read 4, iclass 26, count 0 2006.211.08:06:50.23#ibcon#read 4, iclass 26, count 0 2006.211.08:06:50.23#ibcon#about to read 5, iclass 26, count 0 2006.211.08:06:50.23#ibcon#read 5, iclass 26, count 0 2006.211.08:06:50.23#ibcon#about to read 6, iclass 26, count 0 2006.211.08:06:50.23#ibcon#read 6, iclass 26, count 0 2006.211.08:06:50.23#ibcon#end of sib2, iclass 26, count 0 2006.211.08:06:50.23#ibcon#*after write, iclass 26, count 0 2006.211.08:06:50.23#ibcon#*before return 0, iclass 26, count 0 2006.211.08:06:50.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:06:50.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:06:50.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:06:50.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:06:50.23$vc4f8/vb=1,4 2006.211.08:06:50.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:06:50.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:06:50.23#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:50.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:06:50.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:06:50.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:06:50.23#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:06:50.23#ibcon#first serial, iclass 28, count 2 2006.211.08:06:50.23#ibcon#enter sib2, iclass 28, count 2 2006.211.08:06:50.23#ibcon#flushed, iclass 28, count 2 2006.211.08:06:50.23#ibcon#about to write, iclass 28, count 2 2006.211.08:06:50.23#ibcon#wrote, iclass 28, count 2 2006.211.08:06:50.23#ibcon#about to read 3, iclass 28, count 2 2006.211.08:06:50.25#ibcon#read 3, iclass 28, count 2 2006.211.08:06:50.25#ibcon#about to read 4, iclass 28, count 2 2006.211.08:06:50.25#ibcon#read 4, iclass 28, count 2 2006.211.08:06:50.25#ibcon#about to read 5, iclass 28, count 2 2006.211.08:06:50.25#ibcon#read 5, iclass 28, count 2 2006.211.08:06:50.25#ibcon#about to read 6, iclass 28, count 2 2006.211.08:06:50.25#ibcon#read 6, iclass 28, count 2 2006.211.08:06:50.25#ibcon#end of sib2, iclass 28, count 2 2006.211.08:06:50.25#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:06:50.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:06:50.25#ibcon#[27=AT01-04\r\n] 2006.211.08:06:50.25#ibcon#*before write, iclass 28, count 2 2006.211.08:06:50.25#ibcon#enter sib2, iclass 28, count 2 2006.211.08:06:50.25#ibcon#flushed, iclass 28, count 2 2006.211.08:06:50.25#ibcon#about to write, iclass 28, count 2 2006.211.08:06:50.25#ibcon#wrote, iclass 28, count 2 2006.211.08:06:50.25#ibcon#about to read 3, iclass 28, count 2 2006.211.08:06:50.28#ibcon#read 3, iclass 28, count 2 2006.211.08:06:50.28#ibcon#about to read 4, iclass 28, count 2 2006.211.08:06:50.28#ibcon#read 4, iclass 28, count 2 2006.211.08:06:50.28#ibcon#about to read 5, iclass 28, count 2 2006.211.08:06:50.28#ibcon#read 5, iclass 28, count 2 2006.211.08:06:50.28#ibcon#about to read 6, iclass 28, count 2 2006.211.08:06:50.28#ibcon#read 6, iclass 28, count 2 2006.211.08:06:50.28#ibcon#end of sib2, iclass 28, count 2 2006.211.08:06:50.28#ibcon#*after write, iclass 28, count 2 2006.211.08:06:50.28#ibcon#*before return 0, iclass 28, count 2 2006.211.08:06:50.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:06:50.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:06:50.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:06:50.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:50.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:06:50.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:06:50.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:06:50.40#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:06:50.40#ibcon#first serial, iclass 28, count 0 2006.211.08:06:50.40#ibcon#enter sib2, iclass 28, count 0 2006.211.08:06:50.40#ibcon#flushed, iclass 28, count 0 2006.211.08:06:50.40#ibcon#about to write, iclass 28, count 0 2006.211.08:06:50.40#ibcon#wrote, iclass 28, count 0 2006.211.08:06:50.40#ibcon#about to read 3, iclass 28, count 0 2006.211.08:06:50.42#ibcon#read 3, iclass 28, count 0 2006.211.08:06:50.42#ibcon#about to read 4, iclass 28, count 0 2006.211.08:06:50.42#ibcon#read 4, iclass 28, count 0 2006.211.08:06:50.42#ibcon#about to read 5, iclass 28, count 0 2006.211.08:06:50.42#ibcon#read 5, iclass 28, count 0 2006.211.08:06:50.42#ibcon#about to read 6, iclass 28, count 0 2006.211.08:06:50.42#ibcon#read 6, iclass 28, count 0 2006.211.08:06:50.42#ibcon#end of sib2, iclass 28, count 0 2006.211.08:06:50.42#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:06:50.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:06:50.42#ibcon#[27=USB\r\n] 2006.211.08:06:50.42#ibcon#*before write, iclass 28, count 0 2006.211.08:06:50.42#ibcon#enter sib2, iclass 28, count 0 2006.211.08:06:50.42#ibcon#flushed, iclass 28, count 0 2006.211.08:06:50.42#ibcon#about to write, iclass 28, count 0 2006.211.08:06:50.42#ibcon#wrote, iclass 28, count 0 2006.211.08:06:50.42#ibcon#about to read 3, iclass 28, count 0 2006.211.08:06:50.45#ibcon#read 3, iclass 28, count 0 2006.211.08:06:50.45#ibcon#about to read 4, iclass 28, count 0 2006.211.08:06:50.45#ibcon#read 4, iclass 28, count 0 2006.211.08:06:50.45#ibcon#about to read 5, iclass 28, count 0 2006.211.08:06:50.45#ibcon#read 5, iclass 28, count 0 2006.211.08:06:50.45#ibcon#about to read 6, iclass 28, count 0 2006.211.08:06:50.45#ibcon#read 6, iclass 28, count 0 2006.211.08:06:50.45#ibcon#end of sib2, iclass 28, count 0 2006.211.08:06:50.45#ibcon#*after write, iclass 28, count 0 2006.211.08:06:50.45#ibcon#*before return 0, iclass 28, count 0 2006.211.08:06:50.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:06:50.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:06:50.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:06:50.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:06:50.45$vc4f8/vblo=2,640.99 2006.211.08:06:50.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:06:50.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:06:50.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:50.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:50.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:50.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:50.45#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:06:50.45#ibcon#first serial, iclass 30, count 0 2006.211.08:06:50.45#ibcon#enter sib2, iclass 30, count 0 2006.211.08:06:50.45#ibcon#flushed, iclass 30, count 0 2006.211.08:06:50.45#ibcon#about to write, iclass 30, count 0 2006.211.08:06:50.45#ibcon#wrote, iclass 30, count 0 2006.211.08:06:50.45#ibcon#about to read 3, iclass 30, count 0 2006.211.08:06:50.47#ibcon#read 3, iclass 30, count 0 2006.211.08:06:50.47#ibcon#about to read 4, iclass 30, count 0 2006.211.08:06:50.47#ibcon#read 4, iclass 30, count 0 2006.211.08:06:50.47#ibcon#about to read 5, iclass 30, count 0 2006.211.08:06:50.47#ibcon#read 5, iclass 30, count 0 2006.211.08:06:50.47#ibcon#about to read 6, iclass 30, count 0 2006.211.08:06:50.47#ibcon#read 6, iclass 30, count 0 2006.211.08:06:50.47#ibcon#end of sib2, iclass 30, count 0 2006.211.08:06:50.47#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:06:50.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:06:50.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:06:50.47#ibcon#*before write, iclass 30, count 0 2006.211.08:06:50.47#ibcon#enter sib2, iclass 30, count 0 2006.211.08:06:50.47#ibcon#flushed, iclass 30, count 0 2006.211.08:06:50.47#ibcon#about to write, iclass 30, count 0 2006.211.08:06:50.47#ibcon#wrote, iclass 30, count 0 2006.211.08:06:50.47#ibcon#about to read 3, iclass 30, count 0 2006.211.08:06:50.51#ibcon#read 3, iclass 30, count 0 2006.211.08:06:50.51#ibcon#about to read 4, iclass 30, count 0 2006.211.08:06:50.51#ibcon#read 4, iclass 30, count 0 2006.211.08:06:50.51#ibcon#about to read 5, iclass 30, count 0 2006.211.08:06:50.51#ibcon#read 5, iclass 30, count 0 2006.211.08:06:50.51#ibcon#about to read 6, iclass 30, count 0 2006.211.08:06:50.51#ibcon#read 6, iclass 30, count 0 2006.211.08:06:50.51#ibcon#end of sib2, iclass 30, count 0 2006.211.08:06:50.51#ibcon#*after write, iclass 30, count 0 2006.211.08:06:50.51#ibcon#*before return 0, iclass 30, count 0 2006.211.08:06:50.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:50.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:06:50.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:06:50.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:06:50.51$vc4f8/vb=2,4 2006.211.08:06:50.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:06:50.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:06:50.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:50.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:50.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:50.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:50.57#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:06:50.57#ibcon#first serial, iclass 32, count 2 2006.211.08:06:50.57#ibcon#enter sib2, iclass 32, count 2 2006.211.08:06:50.57#ibcon#flushed, iclass 32, count 2 2006.211.08:06:50.57#ibcon#about to write, iclass 32, count 2 2006.211.08:06:50.57#ibcon#wrote, iclass 32, count 2 2006.211.08:06:50.57#ibcon#about to read 3, iclass 32, count 2 2006.211.08:06:50.59#ibcon#read 3, iclass 32, count 2 2006.211.08:06:50.59#ibcon#about to read 4, iclass 32, count 2 2006.211.08:06:50.59#ibcon#read 4, iclass 32, count 2 2006.211.08:06:50.59#ibcon#about to read 5, iclass 32, count 2 2006.211.08:06:50.59#ibcon#read 5, iclass 32, count 2 2006.211.08:06:50.59#ibcon#about to read 6, iclass 32, count 2 2006.211.08:06:50.59#ibcon#read 6, iclass 32, count 2 2006.211.08:06:50.59#ibcon#end of sib2, iclass 32, count 2 2006.211.08:06:50.59#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:06:50.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:06:50.59#ibcon#[27=AT02-04\r\n] 2006.211.08:06:50.59#ibcon#*before write, iclass 32, count 2 2006.211.08:06:50.59#ibcon#enter sib2, iclass 32, count 2 2006.211.08:06:50.59#ibcon#flushed, iclass 32, count 2 2006.211.08:06:50.59#ibcon#about to write, iclass 32, count 2 2006.211.08:06:50.59#ibcon#wrote, iclass 32, count 2 2006.211.08:06:50.59#ibcon#about to read 3, iclass 32, count 2 2006.211.08:06:50.62#ibcon#read 3, iclass 32, count 2 2006.211.08:06:50.62#ibcon#about to read 4, iclass 32, count 2 2006.211.08:06:50.62#ibcon#read 4, iclass 32, count 2 2006.211.08:06:50.62#ibcon#about to read 5, iclass 32, count 2 2006.211.08:06:50.62#ibcon#read 5, iclass 32, count 2 2006.211.08:06:50.62#ibcon#about to read 6, iclass 32, count 2 2006.211.08:06:50.62#ibcon#read 6, iclass 32, count 2 2006.211.08:06:50.62#ibcon#end of sib2, iclass 32, count 2 2006.211.08:06:50.62#ibcon#*after write, iclass 32, count 2 2006.211.08:06:50.62#ibcon#*before return 0, iclass 32, count 2 2006.211.08:06:50.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:50.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:06:50.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:06:50.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:50.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:50.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:50.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:50.74#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:06:50.74#ibcon#first serial, iclass 32, count 0 2006.211.08:06:50.74#ibcon#enter sib2, iclass 32, count 0 2006.211.08:06:50.74#ibcon#flushed, iclass 32, count 0 2006.211.08:06:50.74#ibcon#about to write, iclass 32, count 0 2006.211.08:06:50.74#ibcon#wrote, iclass 32, count 0 2006.211.08:06:50.74#ibcon#about to read 3, iclass 32, count 0 2006.211.08:06:50.76#ibcon#read 3, iclass 32, count 0 2006.211.08:06:50.76#ibcon#about to read 4, iclass 32, count 0 2006.211.08:06:50.76#ibcon#read 4, iclass 32, count 0 2006.211.08:06:50.76#ibcon#about to read 5, iclass 32, count 0 2006.211.08:06:50.76#ibcon#read 5, iclass 32, count 0 2006.211.08:06:50.76#ibcon#about to read 6, iclass 32, count 0 2006.211.08:06:50.76#ibcon#read 6, iclass 32, count 0 2006.211.08:06:50.76#ibcon#end of sib2, iclass 32, count 0 2006.211.08:06:50.76#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:06:50.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:06:50.76#ibcon#[27=USB\r\n] 2006.211.08:06:50.76#ibcon#*before write, iclass 32, count 0 2006.211.08:06:50.76#ibcon#enter sib2, iclass 32, count 0 2006.211.08:06:50.76#ibcon#flushed, iclass 32, count 0 2006.211.08:06:50.76#ibcon#about to write, iclass 32, count 0 2006.211.08:06:50.76#ibcon#wrote, iclass 32, count 0 2006.211.08:06:50.76#ibcon#about to read 3, iclass 32, count 0 2006.211.08:06:50.79#ibcon#read 3, iclass 32, count 0 2006.211.08:06:50.79#ibcon#about to read 4, iclass 32, count 0 2006.211.08:06:50.79#ibcon#read 4, iclass 32, count 0 2006.211.08:06:50.79#ibcon#about to read 5, iclass 32, count 0 2006.211.08:06:50.79#ibcon#read 5, iclass 32, count 0 2006.211.08:06:50.79#ibcon#about to read 6, iclass 32, count 0 2006.211.08:06:50.79#ibcon#read 6, iclass 32, count 0 2006.211.08:06:50.79#ibcon#end of sib2, iclass 32, count 0 2006.211.08:06:50.79#ibcon#*after write, iclass 32, count 0 2006.211.08:06:50.79#ibcon#*before return 0, iclass 32, count 0 2006.211.08:06:50.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:50.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:06:50.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:06:50.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:06:50.79$vc4f8/vblo=3,656.99 2006.211.08:06:50.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:06:50.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:06:50.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:50.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:50.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:50.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:50.79#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:06:50.79#ibcon#first serial, iclass 34, count 0 2006.211.08:06:50.79#ibcon#enter sib2, iclass 34, count 0 2006.211.08:06:50.79#ibcon#flushed, iclass 34, count 0 2006.211.08:06:50.79#ibcon#about to write, iclass 34, count 0 2006.211.08:06:50.79#ibcon#wrote, iclass 34, count 0 2006.211.08:06:50.79#ibcon#about to read 3, iclass 34, count 0 2006.211.08:06:50.81#ibcon#read 3, iclass 34, count 0 2006.211.08:06:50.81#ibcon#about to read 4, iclass 34, count 0 2006.211.08:06:50.81#ibcon#read 4, iclass 34, count 0 2006.211.08:06:50.81#ibcon#about to read 5, iclass 34, count 0 2006.211.08:06:50.81#ibcon#read 5, iclass 34, count 0 2006.211.08:06:50.81#ibcon#about to read 6, iclass 34, count 0 2006.211.08:06:50.81#ibcon#read 6, iclass 34, count 0 2006.211.08:06:50.81#ibcon#end of sib2, iclass 34, count 0 2006.211.08:06:50.81#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:06:50.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:06:50.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:06:50.81#ibcon#*before write, iclass 34, count 0 2006.211.08:06:50.81#ibcon#enter sib2, iclass 34, count 0 2006.211.08:06:50.81#ibcon#flushed, iclass 34, count 0 2006.211.08:06:50.81#ibcon#about to write, iclass 34, count 0 2006.211.08:06:50.81#ibcon#wrote, iclass 34, count 0 2006.211.08:06:50.81#ibcon#about to read 3, iclass 34, count 0 2006.211.08:06:50.85#ibcon#read 3, iclass 34, count 0 2006.211.08:06:50.85#ibcon#about to read 4, iclass 34, count 0 2006.211.08:06:50.85#ibcon#read 4, iclass 34, count 0 2006.211.08:06:50.85#ibcon#about to read 5, iclass 34, count 0 2006.211.08:06:50.85#ibcon#read 5, iclass 34, count 0 2006.211.08:06:50.85#ibcon#about to read 6, iclass 34, count 0 2006.211.08:06:50.85#ibcon#read 6, iclass 34, count 0 2006.211.08:06:50.85#ibcon#end of sib2, iclass 34, count 0 2006.211.08:06:50.85#ibcon#*after write, iclass 34, count 0 2006.211.08:06:50.85#ibcon#*before return 0, iclass 34, count 0 2006.211.08:06:50.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:50.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:06:50.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:06:50.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:06:50.85$vc4f8/vb=3,3 2006.211.08:06:50.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:06:50.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:06:50.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:50.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:50.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:50.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:50.91#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:06:50.91#ibcon#first serial, iclass 36, count 2 2006.211.08:06:50.91#ibcon#enter sib2, iclass 36, count 2 2006.211.08:06:50.91#ibcon#flushed, iclass 36, count 2 2006.211.08:06:50.91#ibcon#about to write, iclass 36, count 2 2006.211.08:06:50.91#ibcon#wrote, iclass 36, count 2 2006.211.08:06:50.91#ibcon#about to read 3, iclass 36, count 2 2006.211.08:06:50.93#ibcon#read 3, iclass 36, count 2 2006.211.08:06:50.93#ibcon#about to read 4, iclass 36, count 2 2006.211.08:06:50.93#ibcon#read 4, iclass 36, count 2 2006.211.08:06:50.93#ibcon#about to read 5, iclass 36, count 2 2006.211.08:06:50.93#ibcon#read 5, iclass 36, count 2 2006.211.08:06:50.93#ibcon#about to read 6, iclass 36, count 2 2006.211.08:06:50.93#ibcon#read 6, iclass 36, count 2 2006.211.08:06:50.93#ibcon#end of sib2, iclass 36, count 2 2006.211.08:06:50.93#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:06:50.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:06:50.93#ibcon#[27=AT03-03\r\n] 2006.211.08:06:50.93#ibcon#*before write, iclass 36, count 2 2006.211.08:06:50.93#ibcon#enter sib2, iclass 36, count 2 2006.211.08:06:50.93#ibcon#flushed, iclass 36, count 2 2006.211.08:06:50.93#ibcon#about to write, iclass 36, count 2 2006.211.08:06:50.93#ibcon#wrote, iclass 36, count 2 2006.211.08:06:50.93#ibcon#about to read 3, iclass 36, count 2 2006.211.08:06:50.96#ibcon#read 3, iclass 36, count 2 2006.211.08:06:50.96#ibcon#about to read 4, iclass 36, count 2 2006.211.08:06:50.96#ibcon#read 4, iclass 36, count 2 2006.211.08:06:50.96#ibcon#about to read 5, iclass 36, count 2 2006.211.08:06:50.96#ibcon#read 5, iclass 36, count 2 2006.211.08:06:50.96#ibcon#about to read 6, iclass 36, count 2 2006.211.08:06:50.96#ibcon#read 6, iclass 36, count 2 2006.211.08:06:50.96#ibcon#end of sib2, iclass 36, count 2 2006.211.08:06:50.96#ibcon#*after write, iclass 36, count 2 2006.211.08:06:50.96#ibcon#*before return 0, iclass 36, count 2 2006.211.08:06:50.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:50.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:06:50.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:06:50.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:50.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:51.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:51.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:51.08#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:06:51.08#ibcon#first serial, iclass 36, count 0 2006.211.08:06:51.08#ibcon#enter sib2, iclass 36, count 0 2006.211.08:06:51.08#ibcon#flushed, iclass 36, count 0 2006.211.08:06:51.08#ibcon#about to write, iclass 36, count 0 2006.211.08:06:51.08#ibcon#wrote, iclass 36, count 0 2006.211.08:06:51.08#ibcon#about to read 3, iclass 36, count 0 2006.211.08:06:51.10#ibcon#read 3, iclass 36, count 0 2006.211.08:06:51.10#ibcon#about to read 4, iclass 36, count 0 2006.211.08:06:51.10#ibcon#read 4, iclass 36, count 0 2006.211.08:06:51.10#ibcon#about to read 5, iclass 36, count 0 2006.211.08:06:51.10#ibcon#read 5, iclass 36, count 0 2006.211.08:06:51.10#ibcon#about to read 6, iclass 36, count 0 2006.211.08:06:51.10#ibcon#read 6, iclass 36, count 0 2006.211.08:06:51.10#ibcon#end of sib2, iclass 36, count 0 2006.211.08:06:51.10#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:06:51.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:06:51.10#ibcon#[27=USB\r\n] 2006.211.08:06:51.10#ibcon#*before write, iclass 36, count 0 2006.211.08:06:51.10#ibcon#enter sib2, iclass 36, count 0 2006.211.08:06:51.10#ibcon#flushed, iclass 36, count 0 2006.211.08:06:51.10#ibcon#about to write, iclass 36, count 0 2006.211.08:06:51.10#ibcon#wrote, iclass 36, count 0 2006.211.08:06:51.10#ibcon#about to read 3, iclass 36, count 0 2006.211.08:06:51.13#ibcon#read 3, iclass 36, count 0 2006.211.08:06:51.13#ibcon#about to read 4, iclass 36, count 0 2006.211.08:06:51.13#ibcon#read 4, iclass 36, count 0 2006.211.08:06:51.13#ibcon#about to read 5, iclass 36, count 0 2006.211.08:06:51.13#ibcon#read 5, iclass 36, count 0 2006.211.08:06:51.13#ibcon#about to read 6, iclass 36, count 0 2006.211.08:06:51.13#ibcon#read 6, iclass 36, count 0 2006.211.08:06:51.13#ibcon#end of sib2, iclass 36, count 0 2006.211.08:06:51.13#ibcon#*after write, iclass 36, count 0 2006.211.08:06:51.13#ibcon#*before return 0, iclass 36, count 0 2006.211.08:06:51.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:51.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:06:51.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:06:51.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:06:51.13$vc4f8/vblo=4,712.99 2006.211.08:06:51.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:06:51.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:06:51.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:51.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:51.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:51.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:51.13#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:06:51.13#ibcon#first serial, iclass 38, count 0 2006.211.08:06:51.13#ibcon#enter sib2, iclass 38, count 0 2006.211.08:06:51.13#ibcon#flushed, iclass 38, count 0 2006.211.08:06:51.13#ibcon#about to write, iclass 38, count 0 2006.211.08:06:51.13#ibcon#wrote, iclass 38, count 0 2006.211.08:06:51.13#ibcon#about to read 3, iclass 38, count 0 2006.211.08:06:51.15#ibcon#read 3, iclass 38, count 0 2006.211.08:06:51.15#ibcon#about to read 4, iclass 38, count 0 2006.211.08:06:51.15#ibcon#read 4, iclass 38, count 0 2006.211.08:06:51.15#ibcon#about to read 5, iclass 38, count 0 2006.211.08:06:51.15#ibcon#read 5, iclass 38, count 0 2006.211.08:06:51.15#ibcon#about to read 6, iclass 38, count 0 2006.211.08:06:51.15#ibcon#read 6, iclass 38, count 0 2006.211.08:06:51.15#ibcon#end of sib2, iclass 38, count 0 2006.211.08:06:51.15#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:06:51.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:06:51.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:06:51.15#ibcon#*before write, iclass 38, count 0 2006.211.08:06:51.15#ibcon#enter sib2, iclass 38, count 0 2006.211.08:06:51.15#ibcon#flushed, iclass 38, count 0 2006.211.08:06:51.15#ibcon#about to write, iclass 38, count 0 2006.211.08:06:51.15#ibcon#wrote, iclass 38, count 0 2006.211.08:06:51.15#ibcon#about to read 3, iclass 38, count 0 2006.211.08:06:51.19#ibcon#read 3, iclass 38, count 0 2006.211.08:06:51.19#ibcon#about to read 4, iclass 38, count 0 2006.211.08:06:51.19#ibcon#read 4, iclass 38, count 0 2006.211.08:06:51.19#ibcon#about to read 5, iclass 38, count 0 2006.211.08:06:51.19#ibcon#read 5, iclass 38, count 0 2006.211.08:06:51.19#ibcon#about to read 6, iclass 38, count 0 2006.211.08:06:51.19#ibcon#read 6, iclass 38, count 0 2006.211.08:06:51.19#ibcon#end of sib2, iclass 38, count 0 2006.211.08:06:51.19#ibcon#*after write, iclass 38, count 0 2006.211.08:06:51.19#ibcon#*before return 0, iclass 38, count 0 2006.211.08:06:51.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:51.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:06:51.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:06:51.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:06:51.19$vc4f8/vb=4,3 2006.211.08:06:51.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:06:51.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:06:51.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:51.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:51.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:51.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:51.25#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:06:51.25#ibcon#first serial, iclass 40, count 2 2006.211.08:06:51.25#ibcon#enter sib2, iclass 40, count 2 2006.211.08:06:51.25#ibcon#flushed, iclass 40, count 2 2006.211.08:06:51.25#ibcon#about to write, iclass 40, count 2 2006.211.08:06:51.25#ibcon#wrote, iclass 40, count 2 2006.211.08:06:51.25#ibcon#about to read 3, iclass 40, count 2 2006.211.08:06:51.27#ibcon#read 3, iclass 40, count 2 2006.211.08:06:51.27#ibcon#about to read 4, iclass 40, count 2 2006.211.08:06:51.27#ibcon#read 4, iclass 40, count 2 2006.211.08:06:51.27#ibcon#about to read 5, iclass 40, count 2 2006.211.08:06:51.27#ibcon#read 5, iclass 40, count 2 2006.211.08:06:51.27#ibcon#about to read 6, iclass 40, count 2 2006.211.08:06:51.27#ibcon#read 6, iclass 40, count 2 2006.211.08:06:51.27#ibcon#end of sib2, iclass 40, count 2 2006.211.08:06:51.27#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:06:51.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:06:51.27#ibcon#[27=AT04-03\r\n] 2006.211.08:06:51.27#ibcon#*before write, iclass 40, count 2 2006.211.08:06:51.27#ibcon#enter sib2, iclass 40, count 2 2006.211.08:06:51.27#ibcon#flushed, iclass 40, count 2 2006.211.08:06:51.27#ibcon#about to write, iclass 40, count 2 2006.211.08:06:51.27#ibcon#wrote, iclass 40, count 2 2006.211.08:06:51.27#ibcon#about to read 3, iclass 40, count 2 2006.211.08:06:51.30#ibcon#read 3, iclass 40, count 2 2006.211.08:06:51.30#ibcon#about to read 4, iclass 40, count 2 2006.211.08:06:51.30#ibcon#read 4, iclass 40, count 2 2006.211.08:06:51.30#ibcon#about to read 5, iclass 40, count 2 2006.211.08:06:51.30#ibcon#read 5, iclass 40, count 2 2006.211.08:06:51.30#ibcon#about to read 6, iclass 40, count 2 2006.211.08:06:51.30#ibcon#read 6, iclass 40, count 2 2006.211.08:06:51.30#ibcon#end of sib2, iclass 40, count 2 2006.211.08:06:51.30#ibcon#*after write, iclass 40, count 2 2006.211.08:06:51.30#ibcon#*before return 0, iclass 40, count 2 2006.211.08:06:51.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:51.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:06:51.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:06:51.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:51.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:51.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:51.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:51.42#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:06:51.42#ibcon#first serial, iclass 40, count 0 2006.211.08:06:51.42#ibcon#enter sib2, iclass 40, count 0 2006.211.08:06:51.42#ibcon#flushed, iclass 40, count 0 2006.211.08:06:51.42#ibcon#about to write, iclass 40, count 0 2006.211.08:06:51.42#ibcon#wrote, iclass 40, count 0 2006.211.08:06:51.42#ibcon#about to read 3, iclass 40, count 0 2006.211.08:06:51.44#ibcon#read 3, iclass 40, count 0 2006.211.08:06:51.44#ibcon#about to read 4, iclass 40, count 0 2006.211.08:06:51.44#ibcon#read 4, iclass 40, count 0 2006.211.08:06:51.44#ibcon#about to read 5, iclass 40, count 0 2006.211.08:06:51.44#ibcon#read 5, iclass 40, count 0 2006.211.08:06:51.44#ibcon#about to read 6, iclass 40, count 0 2006.211.08:06:51.44#ibcon#read 6, iclass 40, count 0 2006.211.08:06:51.44#ibcon#end of sib2, iclass 40, count 0 2006.211.08:06:51.44#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:06:51.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:06:51.44#ibcon#[27=USB\r\n] 2006.211.08:06:51.44#ibcon#*before write, iclass 40, count 0 2006.211.08:06:51.44#ibcon#enter sib2, iclass 40, count 0 2006.211.08:06:51.44#ibcon#flushed, iclass 40, count 0 2006.211.08:06:51.44#ibcon#about to write, iclass 40, count 0 2006.211.08:06:51.44#ibcon#wrote, iclass 40, count 0 2006.211.08:06:51.44#ibcon#about to read 3, iclass 40, count 0 2006.211.08:06:51.47#ibcon#read 3, iclass 40, count 0 2006.211.08:06:51.47#ibcon#about to read 4, iclass 40, count 0 2006.211.08:06:51.47#ibcon#read 4, iclass 40, count 0 2006.211.08:06:51.47#ibcon#about to read 5, iclass 40, count 0 2006.211.08:06:51.47#ibcon#read 5, iclass 40, count 0 2006.211.08:06:51.47#ibcon#about to read 6, iclass 40, count 0 2006.211.08:06:51.47#ibcon#read 6, iclass 40, count 0 2006.211.08:06:51.47#ibcon#end of sib2, iclass 40, count 0 2006.211.08:06:51.47#ibcon#*after write, iclass 40, count 0 2006.211.08:06:51.47#ibcon#*before return 0, iclass 40, count 0 2006.211.08:06:51.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:51.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:06:51.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:06:51.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:06:51.47$vc4f8/vblo=5,744.99 2006.211.08:06:51.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:06:51.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:06:51.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:51.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:51.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:51.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:51.47#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:06:51.47#ibcon#first serial, iclass 4, count 0 2006.211.08:06:51.47#ibcon#enter sib2, iclass 4, count 0 2006.211.08:06:51.47#ibcon#flushed, iclass 4, count 0 2006.211.08:06:51.47#ibcon#about to write, iclass 4, count 0 2006.211.08:06:51.47#ibcon#wrote, iclass 4, count 0 2006.211.08:06:51.47#ibcon#about to read 3, iclass 4, count 0 2006.211.08:06:51.49#ibcon#read 3, iclass 4, count 0 2006.211.08:06:51.49#ibcon#about to read 4, iclass 4, count 0 2006.211.08:06:51.49#ibcon#read 4, iclass 4, count 0 2006.211.08:06:51.49#ibcon#about to read 5, iclass 4, count 0 2006.211.08:06:51.49#ibcon#read 5, iclass 4, count 0 2006.211.08:06:51.49#ibcon#about to read 6, iclass 4, count 0 2006.211.08:06:51.49#ibcon#read 6, iclass 4, count 0 2006.211.08:06:51.49#ibcon#end of sib2, iclass 4, count 0 2006.211.08:06:51.49#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:06:51.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:06:51.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:06:51.49#ibcon#*before write, iclass 4, count 0 2006.211.08:06:51.49#ibcon#enter sib2, iclass 4, count 0 2006.211.08:06:51.49#ibcon#flushed, iclass 4, count 0 2006.211.08:06:51.49#ibcon#about to write, iclass 4, count 0 2006.211.08:06:51.49#ibcon#wrote, iclass 4, count 0 2006.211.08:06:51.49#ibcon#about to read 3, iclass 4, count 0 2006.211.08:06:51.53#ibcon#read 3, iclass 4, count 0 2006.211.08:06:51.53#ibcon#about to read 4, iclass 4, count 0 2006.211.08:06:51.53#ibcon#read 4, iclass 4, count 0 2006.211.08:06:51.53#ibcon#about to read 5, iclass 4, count 0 2006.211.08:06:51.53#ibcon#read 5, iclass 4, count 0 2006.211.08:06:51.53#ibcon#about to read 6, iclass 4, count 0 2006.211.08:06:51.53#ibcon#read 6, iclass 4, count 0 2006.211.08:06:51.53#ibcon#end of sib2, iclass 4, count 0 2006.211.08:06:51.53#ibcon#*after write, iclass 4, count 0 2006.211.08:06:51.53#ibcon#*before return 0, iclass 4, count 0 2006.211.08:06:51.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:51.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:06:51.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:06:51.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:06:51.53$vc4f8/vb=5,3 2006.211.08:06:51.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:06:51.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:06:51.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:51.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:51.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:51.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:51.59#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:06:51.59#ibcon#first serial, iclass 6, count 2 2006.211.08:06:51.59#ibcon#enter sib2, iclass 6, count 2 2006.211.08:06:51.59#ibcon#flushed, iclass 6, count 2 2006.211.08:06:51.59#ibcon#about to write, iclass 6, count 2 2006.211.08:06:51.59#ibcon#wrote, iclass 6, count 2 2006.211.08:06:51.59#ibcon#about to read 3, iclass 6, count 2 2006.211.08:06:51.61#ibcon#read 3, iclass 6, count 2 2006.211.08:06:51.61#ibcon#about to read 4, iclass 6, count 2 2006.211.08:06:51.61#ibcon#read 4, iclass 6, count 2 2006.211.08:06:51.61#ibcon#about to read 5, iclass 6, count 2 2006.211.08:06:51.61#ibcon#read 5, iclass 6, count 2 2006.211.08:06:51.61#ibcon#about to read 6, iclass 6, count 2 2006.211.08:06:51.61#ibcon#read 6, iclass 6, count 2 2006.211.08:06:51.61#ibcon#end of sib2, iclass 6, count 2 2006.211.08:06:51.61#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:06:51.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:06:51.61#ibcon#[27=AT05-03\r\n] 2006.211.08:06:51.61#ibcon#*before write, iclass 6, count 2 2006.211.08:06:51.61#ibcon#enter sib2, iclass 6, count 2 2006.211.08:06:51.61#ibcon#flushed, iclass 6, count 2 2006.211.08:06:51.61#ibcon#about to write, iclass 6, count 2 2006.211.08:06:51.61#ibcon#wrote, iclass 6, count 2 2006.211.08:06:51.61#ibcon#about to read 3, iclass 6, count 2 2006.211.08:06:51.64#ibcon#read 3, iclass 6, count 2 2006.211.08:06:51.64#ibcon#about to read 4, iclass 6, count 2 2006.211.08:06:51.64#ibcon#read 4, iclass 6, count 2 2006.211.08:06:51.64#ibcon#about to read 5, iclass 6, count 2 2006.211.08:06:51.64#ibcon#read 5, iclass 6, count 2 2006.211.08:06:51.64#ibcon#about to read 6, iclass 6, count 2 2006.211.08:06:51.64#ibcon#read 6, iclass 6, count 2 2006.211.08:06:51.64#ibcon#end of sib2, iclass 6, count 2 2006.211.08:06:51.64#ibcon#*after write, iclass 6, count 2 2006.211.08:06:51.64#ibcon#*before return 0, iclass 6, count 2 2006.211.08:06:51.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:51.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:06:51.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:06:51.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:51.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:51.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:51.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:51.76#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:06:51.76#ibcon#first serial, iclass 6, count 0 2006.211.08:06:51.76#ibcon#enter sib2, iclass 6, count 0 2006.211.08:06:51.76#ibcon#flushed, iclass 6, count 0 2006.211.08:06:51.76#ibcon#about to write, iclass 6, count 0 2006.211.08:06:51.76#ibcon#wrote, iclass 6, count 0 2006.211.08:06:51.76#ibcon#about to read 3, iclass 6, count 0 2006.211.08:06:51.78#ibcon#read 3, iclass 6, count 0 2006.211.08:06:51.78#ibcon#about to read 4, iclass 6, count 0 2006.211.08:06:51.78#ibcon#read 4, iclass 6, count 0 2006.211.08:06:51.78#ibcon#about to read 5, iclass 6, count 0 2006.211.08:06:51.78#ibcon#read 5, iclass 6, count 0 2006.211.08:06:51.78#ibcon#about to read 6, iclass 6, count 0 2006.211.08:06:51.78#ibcon#read 6, iclass 6, count 0 2006.211.08:06:51.78#ibcon#end of sib2, iclass 6, count 0 2006.211.08:06:51.78#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:06:51.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:06:51.78#ibcon#[27=USB\r\n] 2006.211.08:06:51.78#ibcon#*before write, iclass 6, count 0 2006.211.08:06:51.78#ibcon#enter sib2, iclass 6, count 0 2006.211.08:06:51.78#ibcon#flushed, iclass 6, count 0 2006.211.08:06:51.78#ibcon#about to write, iclass 6, count 0 2006.211.08:06:51.78#ibcon#wrote, iclass 6, count 0 2006.211.08:06:51.78#ibcon#about to read 3, iclass 6, count 0 2006.211.08:06:51.81#ibcon#read 3, iclass 6, count 0 2006.211.08:06:51.81#ibcon#about to read 4, iclass 6, count 0 2006.211.08:06:51.81#ibcon#read 4, iclass 6, count 0 2006.211.08:06:51.81#ibcon#about to read 5, iclass 6, count 0 2006.211.08:06:51.81#ibcon#read 5, iclass 6, count 0 2006.211.08:06:51.81#ibcon#about to read 6, iclass 6, count 0 2006.211.08:06:51.81#ibcon#read 6, iclass 6, count 0 2006.211.08:06:51.81#ibcon#end of sib2, iclass 6, count 0 2006.211.08:06:51.81#ibcon#*after write, iclass 6, count 0 2006.211.08:06:51.81#ibcon#*before return 0, iclass 6, count 0 2006.211.08:06:51.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:51.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:06:51.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:06:51.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:06:51.81$vc4f8/vblo=6,752.99 2006.211.08:06:51.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:06:51.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:06:51.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:06:51.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:51.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:51.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:51.81#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:06:51.81#ibcon#first serial, iclass 10, count 0 2006.211.08:06:51.81#ibcon#enter sib2, iclass 10, count 0 2006.211.08:06:51.81#ibcon#flushed, iclass 10, count 0 2006.211.08:06:51.81#ibcon#about to write, iclass 10, count 0 2006.211.08:06:51.81#ibcon#wrote, iclass 10, count 0 2006.211.08:06:51.81#ibcon#about to read 3, iclass 10, count 0 2006.211.08:06:51.83#ibcon#read 3, iclass 10, count 0 2006.211.08:06:51.83#ibcon#about to read 4, iclass 10, count 0 2006.211.08:06:51.83#ibcon#read 4, iclass 10, count 0 2006.211.08:06:51.83#ibcon#about to read 5, iclass 10, count 0 2006.211.08:06:51.83#ibcon#read 5, iclass 10, count 0 2006.211.08:06:51.83#ibcon#about to read 6, iclass 10, count 0 2006.211.08:06:51.83#ibcon#read 6, iclass 10, count 0 2006.211.08:06:51.83#ibcon#end of sib2, iclass 10, count 0 2006.211.08:06:51.83#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:06:51.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:06:51.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:06:51.83#ibcon#*before write, iclass 10, count 0 2006.211.08:06:51.83#ibcon#enter sib2, iclass 10, count 0 2006.211.08:06:51.83#ibcon#flushed, iclass 10, count 0 2006.211.08:06:51.83#ibcon#about to write, iclass 10, count 0 2006.211.08:06:51.83#ibcon#wrote, iclass 10, count 0 2006.211.08:06:51.83#ibcon#about to read 3, iclass 10, count 0 2006.211.08:06:51.87#ibcon#read 3, iclass 10, count 0 2006.211.08:06:51.87#ibcon#about to read 4, iclass 10, count 0 2006.211.08:06:51.87#ibcon#read 4, iclass 10, count 0 2006.211.08:06:51.87#ibcon#about to read 5, iclass 10, count 0 2006.211.08:06:51.87#ibcon#read 5, iclass 10, count 0 2006.211.08:06:51.87#ibcon#about to read 6, iclass 10, count 0 2006.211.08:06:51.87#ibcon#read 6, iclass 10, count 0 2006.211.08:06:51.87#ibcon#end of sib2, iclass 10, count 0 2006.211.08:06:51.87#ibcon#*after write, iclass 10, count 0 2006.211.08:06:51.87#ibcon#*before return 0, iclass 10, count 0 2006.211.08:06:51.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:51.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:06:51.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:06:51.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:06:51.87$vc4f8/vb=6,3 2006.211.08:06:51.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:06:51.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:06:51.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:06:51.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:51.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:51.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:51.93#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:06:51.93#ibcon#first serial, iclass 12, count 2 2006.211.08:06:51.93#ibcon#enter sib2, iclass 12, count 2 2006.211.08:06:51.93#ibcon#flushed, iclass 12, count 2 2006.211.08:06:51.93#ibcon#about to write, iclass 12, count 2 2006.211.08:06:51.93#ibcon#wrote, iclass 12, count 2 2006.211.08:06:51.93#ibcon#about to read 3, iclass 12, count 2 2006.211.08:06:51.95#ibcon#read 3, iclass 12, count 2 2006.211.08:06:51.95#ibcon#about to read 4, iclass 12, count 2 2006.211.08:06:51.95#ibcon#read 4, iclass 12, count 2 2006.211.08:06:51.95#ibcon#about to read 5, iclass 12, count 2 2006.211.08:06:51.95#ibcon#read 5, iclass 12, count 2 2006.211.08:06:51.95#ibcon#about to read 6, iclass 12, count 2 2006.211.08:06:51.95#ibcon#read 6, iclass 12, count 2 2006.211.08:06:51.95#ibcon#end of sib2, iclass 12, count 2 2006.211.08:06:51.95#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:06:51.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:06:51.95#ibcon#[27=AT06-03\r\n] 2006.211.08:06:51.95#ibcon#*before write, iclass 12, count 2 2006.211.08:06:51.95#ibcon#enter sib2, iclass 12, count 2 2006.211.08:06:51.95#ibcon#flushed, iclass 12, count 2 2006.211.08:06:51.95#ibcon#about to write, iclass 12, count 2 2006.211.08:06:51.95#ibcon#wrote, iclass 12, count 2 2006.211.08:06:51.95#ibcon#about to read 3, iclass 12, count 2 2006.211.08:06:51.98#ibcon#read 3, iclass 12, count 2 2006.211.08:06:51.98#ibcon#about to read 4, iclass 12, count 2 2006.211.08:06:51.98#ibcon#read 4, iclass 12, count 2 2006.211.08:06:51.98#ibcon#about to read 5, iclass 12, count 2 2006.211.08:06:51.98#ibcon#read 5, iclass 12, count 2 2006.211.08:06:51.98#ibcon#about to read 6, iclass 12, count 2 2006.211.08:06:51.98#ibcon#read 6, iclass 12, count 2 2006.211.08:06:51.98#ibcon#end of sib2, iclass 12, count 2 2006.211.08:06:51.98#ibcon#*after write, iclass 12, count 2 2006.211.08:06:51.98#ibcon#*before return 0, iclass 12, count 2 2006.211.08:06:51.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:51.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:06:51.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:06:51.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:06:51.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:52.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:52.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:52.10#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:06:52.10#ibcon#first serial, iclass 12, count 0 2006.211.08:06:52.10#ibcon#enter sib2, iclass 12, count 0 2006.211.08:06:52.10#ibcon#flushed, iclass 12, count 0 2006.211.08:06:52.10#ibcon#about to write, iclass 12, count 0 2006.211.08:06:52.10#ibcon#wrote, iclass 12, count 0 2006.211.08:06:52.10#ibcon#about to read 3, iclass 12, count 0 2006.211.08:06:52.12#ibcon#read 3, iclass 12, count 0 2006.211.08:06:52.12#ibcon#about to read 4, iclass 12, count 0 2006.211.08:06:52.12#ibcon#read 4, iclass 12, count 0 2006.211.08:06:52.12#ibcon#about to read 5, iclass 12, count 0 2006.211.08:06:52.12#ibcon#read 5, iclass 12, count 0 2006.211.08:06:52.12#ibcon#about to read 6, iclass 12, count 0 2006.211.08:06:52.12#ibcon#read 6, iclass 12, count 0 2006.211.08:06:52.12#ibcon#end of sib2, iclass 12, count 0 2006.211.08:06:52.12#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:06:52.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:06:52.12#ibcon#[27=USB\r\n] 2006.211.08:06:52.12#ibcon#*before write, iclass 12, count 0 2006.211.08:06:52.12#ibcon#enter sib2, iclass 12, count 0 2006.211.08:06:52.12#ibcon#flushed, iclass 12, count 0 2006.211.08:06:52.12#ibcon#about to write, iclass 12, count 0 2006.211.08:06:52.12#ibcon#wrote, iclass 12, count 0 2006.211.08:06:52.12#ibcon#about to read 3, iclass 12, count 0 2006.211.08:06:52.15#ibcon#read 3, iclass 12, count 0 2006.211.08:06:52.15#ibcon#about to read 4, iclass 12, count 0 2006.211.08:06:52.15#ibcon#read 4, iclass 12, count 0 2006.211.08:06:52.15#ibcon#about to read 5, iclass 12, count 0 2006.211.08:06:52.15#ibcon#read 5, iclass 12, count 0 2006.211.08:06:52.15#ibcon#about to read 6, iclass 12, count 0 2006.211.08:06:52.15#ibcon#read 6, iclass 12, count 0 2006.211.08:06:52.15#ibcon#end of sib2, iclass 12, count 0 2006.211.08:06:52.15#ibcon#*after write, iclass 12, count 0 2006.211.08:06:52.15#ibcon#*before return 0, iclass 12, count 0 2006.211.08:06:52.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:52.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:06:52.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:06:52.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:06:52.15$vc4f8/vabw=wide 2006.211.08:06:52.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:06:52.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:06:52.15#ibcon#ireg 8 cls_cnt 0 2006.211.08:06:52.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:52.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:52.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:52.15#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:06:52.15#ibcon#first serial, iclass 14, count 0 2006.211.08:06:52.15#ibcon#enter sib2, iclass 14, count 0 2006.211.08:06:52.15#ibcon#flushed, iclass 14, count 0 2006.211.08:06:52.15#ibcon#about to write, iclass 14, count 0 2006.211.08:06:52.15#ibcon#wrote, iclass 14, count 0 2006.211.08:06:52.15#ibcon#about to read 3, iclass 14, count 0 2006.211.08:06:52.17#ibcon#read 3, iclass 14, count 0 2006.211.08:06:52.17#ibcon#about to read 4, iclass 14, count 0 2006.211.08:06:52.17#ibcon#read 4, iclass 14, count 0 2006.211.08:06:52.17#ibcon#about to read 5, iclass 14, count 0 2006.211.08:06:52.17#ibcon#read 5, iclass 14, count 0 2006.211.08:06:52.17#ibcon#about to read 6, iclass 14, count 0 2006.211.08:06:52.17#ibcon#read 6, iclass 14, count 0 2006.211.08:06:52.17#ibcon#end of sib2, iclass 14, count 0 2006.211.08:06:52.17#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:06:52.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:06:52.17#ibcon#[25=BW32\r\n] 2006.211.08:06:52.17#ibcon#*before write, iclass 14, count 0 2006.211.08:06:52.17#ibcon#enter sib2, iclass 14, count 0 2006.211.08:06:52.17#ibcon#flushed, iclass 14, count 0 2006.211.08:06:52.17#ibcon#about to write, iclass 14, count 0 2006.211.08:06:52.17#ibcon#wrote, iclass 14, count 0 2006.211.08:06:52.17#ibcon#about to read 3, iclass 14, count 0 2006.211.08:06:52.20#ibcon#read 3, iclass 14, count 0 2006.211.08:06:52.20#ibcon#about to read 4, iclass 14, count 0 2006.211.08:06:52.20#ibcon#read 4, iclass 14, count 0 2006.211.08:06:52.20#ibcon#about to read 5, iclass 14, count 0 2006.211.08:06:52.20#ibcon#read 5, iclass 14, count 0 2006.211.08:06:52.20#ibcon#about to read 6, iclass 14, count 0 2006.211.08:06:52.20#ibcon#read 6, iclass 14, count 0 2006.211.08:06:52.20#ibcon#end of sib2, iclass 14, count 0 2006.211.08:06:52.20#ibcon#*after write, iclass 14, count 0 2006.211.08:06:52.20#ibcon#*before return 0, iclass 14, count 0 2006.211.08:06:52.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:52.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:06:52.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:06:52.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:06:52.20$vc4f8/vbbw=wide 2006.211.08:06:52.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.08:06:52.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.08:06:52.20#ibcon#ireg 8 cls_cnt 0 2006.211.08:06:52.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:06:52.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:06:52.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:06:52.27#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:06:52.27#ibcon#first serial, iclass 16, count 0 2006.211.08:06:52.27#ibcon#enter sib2, iclass 16, count 0 2006.211.08:06:52.27#ibcon#flushed, iclass 16, count 0 2006.211.08:06:52.27#ibcon#about to write, iclass 16, count 0 2006.211.08:06:52.27#ibcon#wrote, iclass 16, count 0 2006.211.08:06:52.27#ibcon#about to read 3, iclass 16, count 0 2006.211.08:06:52.29#ibcon#read 3, iclass 16, count 0 2006.211.08:06:52.29#ibcon#about to read 4, iclass 16, count 0 2006.211.08:06:52.29#ibcon#read 4, iclass 16, count 0 2006.211.08:06:52.29#ibcon#about to read 5, iclass 16, count 0 2006.211.08:06:52.29#ibcon#read 5, iclass 16, count 0 2006.211.08:06:52.29#ibcon#about to read 6, iclass 16, count 0 2006.211.08:06:52.29#ibcon#read 6, iclass 16, count 0 2006.211.08:06:52.29#ibcon#end of sib2, iclass 16, count 0 2006.211.08:06:52.29#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:06:52.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:06:52.29#ibcon#[27=BW32\r\n] 2006.211.08:06:52.29#ibcon#*before write, iclass 16, count 0 2006.211.08:06:52.29#ibcon#enter sib2, iclass 16, count 0 2006.211.08:06:52.29#ibcon#flushed, iclass 16, count 0 2006.211.08:06:52.29#ibcon#about to write, iclass 16, count 0 2006.211.08:06:52.29#ibcon#wrote, iclass 16, count 0 2006.211.08:06:52.29#ibcon#about to read 3, iclass 16, count 0 2006.211.08:06:52.32#ibcon#read 3, iclass 16, count 0 2006.211.08:06:52.32#ibcon#about to read 4, iclass 16, count 0 2006.211.08:06:52.32#ibcon#read 4, iclass 16, count 0 2006.211.08:06:52.32#ibcon#about to read 5, iclass 16, count 0 2006.211.08:06:52.32#ibcon#read 5, iclass 16, count 0 2006.211.08:06:52.32#ibcon#about to read 6, iclass 16, count 0 2006.211.08:06:52.32#ibcon#read 6, iclass 16, count 0 2006.211.08:06:52.32#ibcon#end of sib2, iclass 16, count 0 2006.211.08:06:52.32#ibcon#*after write, iclass 16, count 0 2006.211.08:06:52.32#ibcon#*before return 0, iclass 16, count 0 2006.211.08:06:52.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:06:52.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:06:52.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:06:52.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:06:52.32$4f8m12a/ifd4f 2006.211.08:06:52.32$ifd4f/lo= 2006.211.08:06:52.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:06:52.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:06:52.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:06:52.33$ifd4f/patch= 2006.211.08:06:52.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:06:52.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:06:52.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:06:52.33$4f8m12a/"form=m,16.000,1:2 2006.211.08:06:52.33$4f8m12a/"tpicd 2006.211.08:06:52.33$4f8m12a/echo=off 2006.211.08:06:52.33$4f8m12a/xlog=off 2006.211.08:06:52.33:!2006.211.08:07:20 2006.211.08:07:03.14#trakl#Source acquired 2006.211.08:07:05.14#flagr#flagr/antenna,acquired 2006.211.08:07:20.01:preob 2006.211.08:07:21.14/onsource/TRACKING 2006.211.08:07:21.14:!2006.211.08:07:30 2006.211.08:07:30.00:data_valid=on 2006.211.08:07:30.00:midob 2006.211.08:07:30.14/onsource/TRACKING 2006.211.08:07:30.14/wx/24.68,1010.0,78 2006.211.08:07:30.30/cable/+6.4401E-03 2006.211.08:07:31.39/va/01,08,usb,yes,28,30 2006.211.08:07:31.39/va/02,07,usb,yes,28,35 2006.211.08:07:31.39/va/03,06,usb,yes,30,30 2006.211.08:07:31.39/va/04,07,usb,yes,29,31 2006.211.08:07:31.39/va/05,07,usb,yes,32,33 2006.211.08:07:31.39/va/06,06,usb,yes,31,31 2006.211.08:07:31.39/va/07,06,usb,yes,31,31 2006.211.08:07:31.39/va/08,07,usb,yes,30,29 2006.211.08:07:31.62/valo/01,532.99,yes,locked 2006.211.08:07:31.62/valo/02,572.99,yes,locked 2006.211.08:07:31.62/valo/03,672.99,yes,locked 2006.211.08:07:31.62/valo/04,832.99,yes,locked 2006.211.08:07:31.62/valo/05,652.99,yes,locked 2006.211.08:07:31.62/valo/06,772.99,yes,locked 2006.211.08:07:31.62/valo/07,832.99,yes,locked 2006.211.08:07:31.62/valo/08,852.99,yes,locked 2006.211.08:07:32.71/vb/01,04,usb,yes,28,27 2006.211.08:07:32.71/vb/02,04,usb,yes,30,31 2006.211.08:07:32.71/vb/03,03,usb,yes,33,37 2006.211.08:07:32.71/vb/04,03,usb,yes,34,34 2006.211.08:07:32.71/vb/05,03,usb,yes,32,37 2006.211.08:07:32.71/vb/06,03,usb,yes,33,36 2006.211.08:07:32.71/vb/07,04,usb,yes,29,28 2006.211.08:07:32.71/vb/08,03,usb,yes,33,37 2006.211.08:07:32.94/vblo/01,632.99,yes,locked 2006.211.08:07:32.94/vblo/02,640.99,yes,locked 2006.211.08:07:32.94/vblo/03,656.99,yes,locked 2006.211.08:07:32.94/vblo/04,712.99,yes,locked 2006.211.08:07:32.94/vblo/05,744.99,yes,locked 2006.211.08:07:32.94/vblo/06,752.99,yes,locked 2006.211.08:07:32.94/vblo/07,734.99,yes,locked 2006.211.08:07:32.94/vblo/08,744.99,yes,locked 2006.211.08:07:33.09/vabw/8 2006.211.08:07:33.24/vbbw/8 2006.211.08:07:33.33/xfe/off,on,12.0 2006.211.08:07:33.72/ifatt/23,28,28,28 2006.211.08:07:34.07/fmout-gps/S +4.46E-07 2006.211.08:07:34.12:!2006.211.08:08:30 2006.211.08:08:30.01:data_valid=off 2006.211.08:08:30.01:postob 2006.211.08:08:30.17/cable/+6.4404E-03 2006.211.08:08:30.17/wx/24.66,1010.0,80 2006.211.08:08:31.07/fmout-gps/S +4.46E-07 2006.211.08:08:31.07:scan_name=211-0809,k06211,60 2006.211.08:08:31.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.211.08:08:31.14#flagr#flagr/antenna,new-source 2006.211.08:08:32.14:checkk5 2006.211.08:08:32.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:08:32.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:08:33.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:08:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:08:33.84/chk_obsdata//k5ts1/T2110807??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:08:34.17/chk_obsdata//k5ts2/T2110807??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:08:34.50/chk_obsdata//k5ts3/T2110807??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:08:34.83/chk_obsdata//k5ts4/T2110807??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:08:35.48/k5log//k5ts1_log_newline 2006.211.08:08:36.13/k5log//k5ts2_log_newline 2006.211.08:08:36.78/k5log//k5ts3_log_newline 2006.211.08:08:37.44/k5log//k5ts4_log_newline 2006.211.08:08:37.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:08:37.47:4f8m12a=2 2006.211.08:08:37.47$4f8m12a/echo=on 2006.211.08:08:37.47$4f8m12a/pcalon 2006.211.08:08:37.47$pcalon/"no phase cal control is implemented here 2006.211.08:08:37.47$4f8m12a/"tpicd=stop 2006.211.08:08:37.47$4f8m12a/vc4f8 2006.211.08:08:37.47$vc4f8/valo=1,532.99 2006.211.08:08:37.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.08:08:37.47#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.08:08:37.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:37.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:37.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:37.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:37.47#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:08:37.47#ibcon#first serial, iclass 27, count 0 2006.211.08:08:37.47#ibcon#enter sib2, iclass 27, count 0 2006.211.08:08:37.47#ibcon#flushed, iclass 27, count 0 2006.211.08:08:37.47#ibcon#about to write, iclass 27, count 0 2006.211.08:08:37.47#ibcon#wrote, iclass 27, count 0 2006.211.08:08:37.47#ibcon#about to read 3, iclass 27, count 0 2006.211.08:08:37.48#ibcon#read 3, iclass 27, count 0 2006.211.08:08:37.48#ibcon#about to read 4, iclass 27, count 0 2006.211.08:08:37.48#ibcon#read 4, iclass 27, count 0 2006.211.08:08:37.48#ibcon#about to read 5, iclass 27, count 0 2006.211.08:08:37.48#ibcon#read 5, iclass 27, count 0 2006.211.08:08:37.48#ibcon#about to read 6, iclass 27, count 0 2006.211.08:08:37.48#ibcon#read 6, iclass 27, count 0 2006.211.08:08:37.48#ibcon#end of sib2, iclass 27, count 0 2006.211.08:08:37.48#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:08:37.48#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:08:37.48#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:08:37.48#ibcon#*before write, iclass 27, count 0 2006.211.08:08:37.48#ibcon#enter sib2, iclass 27, count 0 2006.211.08:08:37.48#ibcon#flushed, iclass 27, count 0 2006.211.08:08:37.48#ibcon#about to write, iclass 27, count 0 2006.211.08:08:37.48#ibcon#wrote, iclass 27, count 0 2006.211.08:08:37.48#ibcon#about to read 3, iclass 27, count 0 2006.211.08:08:37.53#ibcon#read 3, iclass 27, count 0 2006.211.08:08:37.53#ibcon#about to read 4, iclass 27, count 0 2006.211.08:08:37.53#ibcon#read 4, iclass 27, count 0 2006.211.08:08:37.53#ibcon#about to read 5, iclass 27, count 0 2006.211.08:08:37.53#ibcon#read 5, iclass 27, count 0 2006.211.08:08:37.53#ibcon#about to read 6, iclass 27, count 0 2006.211.08:08:37.53#ibcon#read 6, iclass 27, count 0 2006.211.08:08:37.53#ibcon#end of sib2, iclass 27, count 0 2006.211.08:08:37.53#ibcon#*after write, iclass 27, count 0 2006.211.08:08:37.53#ibcon#*before return 0, iclass 27, count 0 2006.211.08:08:37.53#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:37.53#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:37.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:08:37.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:08:37.53$vc4f8/va=1,8 2006.211.08:08:37.53#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.08:08:37.53#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.08:08:37.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:37.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:37.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:37.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:37.53#ibcon#enter wrdev, iclass 29, count 2 2006.211.08:08:37.53#ibcon#first serial, iclass 29, count 2 2006.211.08:08:37.53#ibcon#enter sib2, iclass 29, count 2 2006.211.08:08:37.53#ibcon#flushed, iclass 29, count 2 2006.211.08:08:37.53#ibcon#about to write, iclass 29, count 2 2006.211.08:08:37.53#ibcon#wrote, iclass 29, count 2 2006.211.08:08:37.53#ibcon#about to read 3, iclass 29, count 2 2006.211.08:08:37.55#ibcon#read 3, iclass 29, count 2 2006.211.08:08:37.55#ibcon#about to read 4, iclass 29, count 2 2006.211.08:08:37.55#ibcon#read 4, iclass 29, count 2 2006.211.08:08:37.55#ibcon#about to read 5, iclass 29, count 2 2006.211.08:08:37.55#ibcon#read 5, iclass 29, count 2 2006.211.08:08:37.55#ibcon#about to read 6, iclass 29, count 2 2006.211.08:08:37.55#ibcon#read 6, iclass 29, count 2 2006.211.08:08:37.55#ibcon#end of sib2, iclass 29, count 2 2006.211.08:08:37.55#ibcon#*mode == 0, iclass 29, count 2 2006.211.08:08:37.55#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.08:08:37.55#ibcon#[25=AT01-08\r\n] 2006.211.08:08:37.55#ibcon#*before write, iclass 29, count 2 2006.211.08:08:37.55#ibcon#enter sib2, iclass 29, count 2 2006.211.08:08:37.55#ibcon#flushed, iclass 29, count 2 2006.211.08:08:37.55#ibcon#about to write, iclass 29, count 2 2006.211.08:08:37.55#ibcon#wrote, iclass 29, count 2 2006.211.08:08:37.55#ibcon#about to read 3, iclass 29, count 2 2006.211.08:08:37.58#ibcon#read 3, iclass 29, count 2 2006.211.08:08:37.58#ibcon#about to read 4, iclass 29, count 2 2006.211.08:08:37.58#ibcon#read 4, iclass 29, count 2 2006.211.08:08:37.58#ibcon#about to read 5, iclass 29, count 2 2006.211.08:08:37.58#ibcon#read 5, iclass 29, count 2 2006.211.08:08:37.58#ibcon#about to read 6, iclass 29, count 2 2006.211.08:08:37.58#ibcon#read 6, iclass 29, count 2 2006.211.08:08:37.58#ibcon#end of sib2, iclass 29, count 2 2006.211.08:08:37.58#ibcon#*after write, iclass 29, count 2 2006.211.08:08:37.58#ibcon#*before return 0, iclass 29, count 2 2006.211.08:08:37.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:37.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:37.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.08:08:37.58#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:37.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:37.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:37.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:37.70#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:08:37.70#ibcon#first serial, iclass 29, count 0 2006.211.08:08:37.70#ibcon#enter sib2, iclass 29, count 0 2006.211.08:08:37.70#ibcon#flushed, iclass 29, count 0 2006.211.08:08:37.70#ibcon#about to write, iclass 29, count 0 2006.211.08:08:37.70#ibcon#wrote, iclass 29, count 0 2006.211.08:08:37.70#ibcon#about to read 3, iclass 29, count 0 2006.211.08:08:37.72#ibcon#read 3, iclass 29, count 0 2006.211.08:08:37.72#ibcon#about to read 4, iclass 29, count 0 2006.211.08:08:37.72#ibcon#read 4, iclass 29, count 0 2006.211.08:08:37.72#ibcon#about to read 5, iclass 29, count 0 2006.211.08:08:37.72#ibcon#read 5, iclass 29, count 0 2006.211.08:08:37.72#ibcon#about to read 6, iclass 29, count 0 2006.211.08:08:37.72#ibcon#read 6, iclass 29, count 0 2006.211.08:08:37.72#ibcon#end of sib2, iclass 29, count 0 2006.211.08:08:37.72#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:08:37.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:08:37.72#ibcon#[25=USB\r\n] 2006.211.08:08:37.72#ibcon#*before write, iclass 29, count 0 2006.211.08:08:37.72#ibcon#enter sib2, iclass 29, count 0 2006.211.08:08:37.72#ibcon#flushed, iclass 29, count 0 2006.211.08:08:37.72#ibcon#about to write, iclass 29, count 0 2006.211.08:08:37.72#ibcon#wrote, iclass 29, count 0 2006.211.08:08:37.72#ibcon#about to read 3, iclass 29, count 0 2006.211.08:08:37.75#ibcon#read 3, iclass 29, count 0 2006.211.08:08:37.75#ibcon#about to read 4, iclass 29, count 0 2006.211.08:08:37.75#ibcon#read 4, iclass 29, count 0 2006.211.08:08:37.75#ibcon#about to read 5, iclass 29, count 0 2006.211.08:08:37.75#ibcon#read 5, iclass 29, count 0 2006.211.08:08:37.75#ibcon#about to read 6, iclass 29, count 0 2006.211.08:08:37.75#ibcon#read 6, iclass 29, count 0 2006.211.08:08:37.75#ibcon#end of sib2, iclass 29, count 0 2006.211.08:08:37.75#ibcon#*after write, iclass 29, count 0 2006.211.08:08:37.75#ibcon#*before return 0, iclass 29, count 0 2006.211.08:08:37.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:37.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:37.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:08:37.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:08:37.75$vc4f8/valo=2,572.99 2006.211.08:08:37.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.08:08:37.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.08:08:37.75#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:37.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:37.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:37.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:37.75#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:08:37.75#ibcon#first serial, iclass 31, count 0 2006.211.08:08:37.75#ibcon#enter sib2, iclass 31, count 0 2006.211.08:08:37.75#ibcon#flushed, iclass 31, count 0 2006.211.08:08:37.75#ibcon#about to write, iclass 31, count 0 2006.211.08:08:37.75#ibcon#wrote, iclass 31, count 0 2006.211.08:08:37.75#ibcon#about to read 3, iclass 31, count 0 2006.211.08:08:37.77#ibcon#read 3, iclass 31, count 0 2006.211.08:08:37.77#ibcon#about to read 4, iclass 31, count 0 2006.211.08:08:37.77#ibcon#read 4, iclass 31, count 0 2006.211.08:08:37.77#ibcon#about to read 5, iclass 31, count 0 2006.211.08:08:37.77#ibcon#read 5, iclass 31, count 0 2006.211.08:08:37.77#ibcon#about to read 6, iclass 31, count 0 2006.211.08:08:37.77#ibcon#read 6, iclass 31, count 0 2006.211.08:08:37.77#ibcon#end of sib2, iclass 31, count 0 2006.211.08:08:37.77#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:08:37.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:08:37.77#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:08:37.77#ibcon#*before write, iclass 31, count 0 2006.211.08:08:37.77#ibcon#enter sib2, iclass 31, count 0 2006.211.08:08:37.77#ibcon#flushed, iclass 31, count 0 2006.211.08:08:37.77#ibcon#about to write, iclass 31, count 0 2006.211.08:08:37.77#ibcon#wrote, iclass 31, count 0 2006.211.08:08:37.77#ibcon#about to read 3, iclass 31, count 0 2006.211.08:08:37.81#ibcon#read 3, iclass 31, count 0 2006.211.08:08:37.81#ibcon#about to read 4, iclass 31, count 0 2006.211.08:08:37.81#ibcon#read 4, iclass 31, count 0 2006.211.08:08:37.81#ibcon#about to read 5, iclass 31, count 0 2006.211.08:08:37.81#ibcon#read 5, iclass 31, count 0 2006.211.08:08:37.81#ibcon#about to read 6, iclass 31, count 0 2006.211.08:08:37.81#ibcon#read 6, iclass 31, count 0 2006.211.08:08:37.81#ibcon#end of sib2, iclass 31, count 0 2006.211.08:08:37.81#ibcon#*after write, iclass 31, count 0 2006.211.08:08:37.81#ibcon#*before return 0, iclass 31, count 0 2006.211.08:08:37.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:37.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:37.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:08:37.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:08:37.81$vc4f8/va=2,7 2006.211.08:08:37.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.08:08:37.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.08:08:37.81#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:37.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:37.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:37.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:37.87#ibcon#enter wrdev, iclass 33, count 2 2006.211.08:08:37.87#ibcon#first serial, iclass 33, count 2 2006.211.08:08:37.87#ibcon#enter sib2, iclass 33, count 2 2006.211.08:08:37.87#ibcon#flushed, iclass 33, count 2 2006.211.08:08:37.87#ibcon#about to write, iclass 33, count 2 2006.211.08:08:37.87#ibcon#wrote, iclass 33, count 2 2006.211.08:08:37.87#ibcon#about to read 3, iclass 33, count 2 2006.211.08:08:37.89#ibcon#read 3, iclass 33, count 2 2006.211.08:08:37.89#ibcon#about to read 4, iclass 33, count 2 2006.211.08:08:37.89#ibcon#read 4, iclass 33, count 2 2006.211.08:08:37.89#ibcon#about to read 5, iclass 33, count 2 2006.211.08:08:37.89#ibcon#read 5, iclass 33, count 2 2006.211.08:08:37.89#ibcon#about to read 6, iclass 33, count 2 2006.211.08:08:37.89#ibcon#read 6, iclass 33, count 2 2006.211.08:08:37.89#ibcon#end of sib2, iclass 33, count 2 2006.211.08:08:37.89#ibcon#*mode == 0, iclass 33, count 2 2006.211.08:08:37.89#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.08:08:37.89#ibcon#[25=AT02-07\r\n] 2006.211.08:08:37.89#ibcon#*before write, iclass 33, count 2 2006.211.08:08:37.89#ibcon#enter sib2, iclass 33, count 2 2006.211.08:08:37.89#ibcon#flushed, iclass 33, count 2 2006.211.08:08:37.89#ibcon#about to write, iclass 33, count 2 2006.211.08:08:37.89#ibcon#wrote, iclass 33, count 2 2006.211.08:08:37.89#ibcon#about to read 3, iclass 33, count 2 2006.211.08:08:37.92#ibcon#read 3, iclass 33, count 2 2006.211.08:08:37.92#ibcon#about to read 4, iclass 33, count 2 2006.211.08:08:37.92#ibcon#read 4, iclass 33, count 2 2006.211.08:08:37.92#ibcon#about to read 5, iclass 33, count 2 2006.211.08:08:37.92#ibcon#read 5, iclass 33, count 2 2006.211.08:08:37.92#ibcon#about to read 6, iclass 33, count 2 2006.211.08:08:37.92#ibcon#read 6, iclass 33, count 2 2006.211.08:08:37.92#ibcon#end of sib2, iclass 33, count 2 2006.211.08:08:37.92#ibcon#*after write, iclass 33, count 2 2006.211.08:08:37.92#ibcon#*before return 0, iclass 33, count 2 2006.211.08:08:37.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:37.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:37.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.08:08:37.92#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:37.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:38.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:38.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:38.04#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:08:38.04#ibcon#first serial, iclass 33, count 0 2006.211.08:08:38.04#ibcon#enter sib2, iclass 33, count 0 2006.211.08:08:38.04#ibcon#flushed, iclass 33, count 0 2006.211.08:08:38.04#ibcon#about to write, iclass 33, count 0 2006.211.08:08:38.04#ibcon#wrote, iclass 33, count 0 2006.211.08:08:38.04#ibcon#about to read 3, iclass 33, count 0 2006.211.08:08:38.06#ibcon#read 3, iclass 33, count 0 2006.211.08:08:38.06#ibcon#about to read 4, iclass 33, count 0 2006.211.08:08:38.06#ibcon#read 4, iclass 33, count 0 2006.211.08:08:38.06#ibcon#about to read 5, iclass 33, count 0 2006.211.08:08:38.06#ibcon#read 5, iclass 33, count 0 2006.211.08:08:38.06#ibcon#about to read 6, iclass 33, count 0 2006.211.08:08:38.06#ibcon#read 6, iclass 33, count 0 2006.211.08:08:38.06#ibcon#end of sib2, iclass 33, count 0 2006.211.08:08:38.06#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:08:38.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:08:38.06#ibcon#[25=USB\r\n] 2006.211.08:08:38.06#ibcon#*before write, iclass 33, count 0 2006.211.08:08:38.06#ibcon#enter sib2, iclass 33, count 0 2006.211.08:08:38.06#ibcon#flushed, iclass 33, count 0 2006.211.08:08:38.06#ibcon#about to write, iclass 33, count 0 2006.211.08:08:38.06#ibcon#wrote, iclass 33, count 0 2006.211.08:08:38.06#ibcon#about to read 3, iclass 33, count 0 2006.211.08:08:38.09#ibcon#read 3, iclass 33, count 0 2006.211.08:08:38.09#ibcon#about to read 4, iclass 33, count 0 2006.211.08:08:38.09#ibcon#read 4, iclass 33, count 0 2006.211.08:08:38.09#ibcon#about to read 5, iclass 33, count 0 2006.211.08:08:38.09#ibcon#read 5, iclass 33, count 0 2006.211.08:08:38.09#ibcon#about to read 6, iclass 33, count 0 2006.211.08:08:38.09#ibcon#read 6, iclass 33, count 0 2006.211.08:08:38.09#ibcon#end of sib2, iclass 33, count 0 2006.211.08:08:38.09#ibcon#*after write, iclass 33, count 0 2006.211.08:08:38.09#ibcon#*before return 0, iclass 33, count 0 2006.211.08:08:38.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:38.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:38.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:08:38.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:08:38.09$vc4f8/valo=3,672.99 2006.211.08:08:38.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.08:08:38.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.08:08:38.09#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:38.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:38.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:38.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:38.09#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:08:38.09#ibcon#first serial, iclass 35, count 0 2006.211.08:08:38.09#ibcon#enter sib2, iclass 35, count 0 2006.211.08:08:38.09#ibcon#flushed, iclass 35, count 0 2006.211.08:08:38.09#ibcon#about to write, iclass 35, count 0 2006.211.08:08:38.09#ibcon#wrote, iclass 35, count 0 2006.211.08:08:38.09#ibcon#about to read 3, iclass 35, count 0 2006.211.08:08:38.11#ibcon#read 3, iclass 35, count 0 2006.211.08:08:38.11#ibcon#about to read 4, iclass 35, count 0 2006.211.08:08:38.11#ibcon#read 4, iclass 35, count 0 2006.211.08:08:38.11#ibcon#about to read 5, iclass 35, count 0 2006.211.08:08:38.11#ibcon#read 5, iclass 35, count 0 2006.211.08:08:38.11#ibcon#about to read 6, iclass 35, count 0 2006.211.08:08:38.11#ibcon#read 6, iclass 35, count 0 2006.211.08:08:38.11#ibcon#end of sib2, iclass 35, count 0 2006.211.08:08:38.11#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:08:38.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:08:38.11#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:08:38.11#ibcon#*before write, iclass 35, count 0 2006.211.08:08:38.11#ibcon#enter sib2, iclass 35, count 0 2006.211.08:08:38.11#ibcon#flushed, iclass 35, count 0 2006.211.08:08:38.11#ibcon#about to write, iclass 35, count 0 2006.211.08:08:38.11#ibcon#wrote, iclass 35, count 0 2006.211.08:08:38.11#ibcon#about to read 3, iclass 35, count 0 2006.211.08:08:38.15#ibcon#read 3, iclass 35, count 0 2006.211.08:08:38.15#ibcon#about to read 4, iclass 35, count 0 2006.211.08:08:38.15#ibcon#read 4, iclass 35, count 0 2006.211.08:08:38.15#ibcon#about to read 5, iclass 35, count 0 2006.211.08:08:38.15#ibcon#read 5, iclass 35, count 0 2006.211.08:08:38.15#ibcon#about to read 6, iclass 35, count 0 2006.211.08:08:38.15#ibcon#read 6, iclass 35, count 0 2006.211.08:08:38.15#ibcon#end of sib2, iclass 35, count 0 2006.211.08:08:38.15#ibcon#*after write, iclass 35, count 0 2006.211.08:08:38.15#ibcon#*before return 0, iclass 35, count 0 2006.211.08:08:38.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:38.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:38.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:08:38.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:08:38.15$vc4f8/va=3,6 2006.211.08:08:38.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.08:08:38.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.08:08:38.15#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:38.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:38.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:38.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:38.21#ibcon#enter wrdev, iclass 37, count 2 2006.211.08:08:38.21#ibcon#first serial, iclass 37, count 2 2006.211.08:08:38.21#ibcon#enter sib2, iclass 37, count 2 2006.211.08:08:38.21#ibcon#flushed, iclass 37, count 2 2006.211.08:08:38.21#ibcon#about to write, iclass 37, count 2 2006.211.08:08:38.21#ibcon#wrote, iclass 37, count 2 2006.211.08:08:38.21#ibcon#about to read 3, iclass 37, count 2 2006.211.08:08:38.23#ibcon#read 3, iclass 37, count 2 2006.211.08:08:38.23#ibcon#about to read 4, iclass 37, count 2 2006.211.08:08:38.23#ibcon#read 4, iclass 37, count 2 2006.211.08:08:38.23#ibcon#about to read 5, iclass 37, count 2 2006.211.08:08:38.23#ibcon#read 5, iclass 37, count 2 2006.211.08:08:38.23#ibcon#about to read 6, iclass 37, count 2 2006.211.08:08:38.23#ibcon#read 6, iclass 37, count 2 2006.211.08:08:38.23#ibcon#end of sib2, iclass 37, count 2 2006.211.08:08:38.23#ibcon#*mode == 0, iclass 37, count 2 2006.211.08:08:38.23#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.08:08:38.23#ibcon#[25=AT03-06\r\n] 2006.211.08:08:38.23#ibcon#*before write, iclass 37, count 2 2006.211.08:08:38.23#ibcon#enter sib2, iclass 37, count 2 2006.211.08:08:38.23#ibcon#flushed, iclass 37, count 2 2006.211.08:08:38.23#ibcon#about to write, iclass 37, count 2 2006.211.08:08:38.23#ibcon#wrote, iclass 37, count 2 2006.211.08:08:38.23#ibcon#about to read 3, iclass 37, count 2 2006.211.08:08:38.26#ibcon#read 3, iclass 37, count 2 2006.211.08:08:38.26#ibcon#about to read 4, iclass 37, count 2 2006.211.08:08:38.26#ibcon#read 4, iclass 37, count 2 2006.211.08:08:38.26#ibcon#about to read 5, iclass 37, count 2 2006.211.08:08:38.26#ibcon#read 5, iclass 37, count 2 2006.211.08:08:38.26#ibcon#about to read 6, iclass 37, count 2 2006.211.08:08:38.26#ibcon#read 6, iclass 37, count 2 2006.211.08:08:38.26#ibcon#end of sib2, iclass 37, count 2 2006.211.08:08:38.26#ibcon#*after write, iclass 37, count 2 2006.211.08:08:38.26#ibcon#*before return 0, iclass 37, count 2 2006.211.08:08:38.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:38.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:38.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.08:08:38.26#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:38.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:38.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:38.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:38.38#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:08:38.38#ibcon#first serial, iclass 37, count 0 2006.211.08:08:38.38#ibcon#enter sib2, iclass 37, count 0 2006.211.08:08:38.38#ibcon#flushed, iclass 37, count 0 2006.211.08:08:38.38#ibcon#about to write, iclass 37, count 0 2006.211.08:08:38.38#ibcon#wrote, iclass 37, count 0 2006.211.08:08:38.38#ibcon#about to read 3, iclass 37, count 0 2006.211.08:08:38.40#ibcon#read 3, iclass 37, count 0 2006.211.08:08:38.40#ibcon#about to read 4, iclass 37, count 0 2006.211.08:08:38.40#ibcon#read 4, iclass 37, count 0 2006.211.08:08:38.40#ibcon#about to read 5, iclass 37, count 0 2006.211.08:08:38.40#ibcon#read 5, iclass 37, count 0 2006.211.08:08:38.40#ibcon#about to read 6, iclass 37, count 0 2006.211.08:08:38.40#ibcon#read 6, iclass 37, count 0 2006.211.08:08:38.40#ibcon#end of sib2, iclass 37, count 0 2006.211.08:08:38.40#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:08:38.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:08:38.40#ibcon#[25=USB\r\n] 2006.211.08:08:38.40#ibcon#*before write, iclass 37, count 0 2006.211.08:08:38.40#ibcon#enter sib2, iclass 37, count 0 2006.211.08:08:38.40#ibcon#flushed, iclass 37, count 0 2006.211.08:08:38.40#ibcon#about to write, iclass 37, count 0 2006.211.08:08:38.40#ibcon#wrote, iclass 37, count 0 2006.211.08:08:38.40#ibcon#about to read 3, iclass 37, count 0 2006.211.08:08:38.43#ibcon#read 3, iclass 37, count 0 2006.211.08:08:38.43#ibcon#about to read 4, iclass 37, count 0 2006.211.08:08:38.43#ibcon#read 4, iclass 37, count 0 2006.211.08:08:38.43#ibcon#about to read 5, iclass 37, count 0 2006.211.08:08:38.43#ibcon#read 5, iclass 37, count 0 2006.211.08:08:38.43#ibcon#about to read 6, iclass 37, count 0 2006.211.08:08:38.43#ibcon#read 6, iclass 37, count 0 2006.211.08:08:38.43#ibcon#end of sib2, iclass 37, count 0 2006.211.08:08:38.43#ibcon#*after write, iclass 37, count 0 2006.211.08:08:38.43#ibcon#*before return 0, iclass 37, count 0 2006.211.08:08:38.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:38.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:38.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:08:38.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:08:38.43$vc4f8/valo=4,832.99 2006.211.08:08:38.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.08:08:38.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.08:08:38.43#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:38.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:38.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:38.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:38.43#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:08:38.43#ibcon#first serial, iclass 39, count 0 2006.211.08:08:38.43#ibcon#enter sib2, iclass 39, count 0 2006.211.08:08:38.43#ibcon#flushed, iclass 39, count 0 2006.211.08:08:38.43#ibcon#about to write, iclass 39, count 0 2006.211.08:08:38.43#ibcon#wrote, iclass 39, count 0 2006.211.08:08:38.43#ibcon#about to read 3, iclass 39, count 0 2006.211.08:08:38.45#ibcon#read 3, iclass 39, count 0 2006.211.08:08:38.45#ibcon#about to read 4, iclass 39, count 0 2006.211.08:08:38.45#ibcon#read 4, iclass 39, count 0 2006.211.08:08:38.45#ibcon#about to read 5, iclass 39, count 0 2006.211.08:08:38.45#ibcon#read 5, iclass 39, count 0 2006.211.08:08:38.45#ibcon#about to read 6, iclass 39, count 0 2006.211.08:08:38.45#ibcon#read 6, iclass 39, count 0 2006.211.08:08:38.45#ibcon#end of sib2, iclass 39, count 0 2006.211.08:08:38.45#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:08:38.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:08:38.45#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:08:38.45#ibcon#*before write, iclass 39, count 0 2006.211.08:08:38.45#ibcon#enter sib2, iclass 39, count 0 2006.211.08:08:38.45#ibcon#flushed, iclass 39, count 0 2006.211.08:08:38.45#ibcon#about to write, iclass 39, count 0 2006.211.08:08:38.45#ibcon#wrote, iclass 39, count 0 2006.211.08:08:38.45#ibcon#about to read 3, iclass 39, count 0 2006.211.08:08:38.49#ibcon#read 3, iclass 39, count 0 2006.211.08:08:38.49#ibcon#about to read 4, iclass 39, count 0 2006.211.08:08:38.49#ibcon#read 4, iclass 39, count 0 2006.211.08:08:38.49#ibcon#about to read 5, iclass 39, count 0 2006.211.08:08:38.49#ibcon#read 5, iclass 39, count 0 2006.211.08:08:38.49#ibcon#about to read 6, iclass 39, count 0 2006.211.08:08:38.49#ibcon#read 6, iclass 39, count 0 2006.211.08:08:38.49#ibcon#end of sib2, iclass 39, count 0 2006.211.08:08:38.49#ibcon#*after write, iclass 39, count 0 2006.211.08:08:38.49#ibcon#*before return 0, iclass 39, count 0 2006.211.08:08:38.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:38.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:38.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:08:38.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:08:38.49$vc4f8/va=4,7 2006.211.08:08:38.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.08:08:38.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.08:08:38.49#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:38.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:38.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:38.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:38.55#ibcon#enter wrdev, iclass 3, count 2 2006.211.08:08:38.55#ibcon#first serial, iclass 3, count 2 2006.211.08:08:38.55#ibcon#enter sib2, iclass 3, count 2 2006.211.08:08:38.55#ibcon#flushed, iclass 3, count 2 2006.211.08:08:38.55#ibcon#about to write, iclass 3, count 2 2006.211.08:08:38.55#ibcon#wrote, iclass 3, count 2 2006.211.08:08:38.55#ibcon#about to read 3, iclass 3, count 2 2006.211.08:08:38.57#ibcon#read 3, iclass 3, count 2 2006.211.08:08:38.57#ibcon#about to read 4, iclass 3, count 2 2006.211.08:08:38.57#ibcon#read 4, iclass 3, count 2 2006.211.08:08:38.57#ibcon#about to read 5, iclass 3, count 2 2006.211.08:08:38.57#ibcon#read 5, iclass 3, count 2 2006.211.08:08:38.57#ibcon#about to read 6, iclass 3, count 2 2006.211.08:08:38.57#ibcon#read 6, iclass 3, count 2 2006.211.08:08:38.57#ibcon#end of sib2, iclass 3, count 2 2006.211.08:08:38.57#ibcon#*mode == 0, iclass 3, count 2 2006.211.08:08:38.57#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.08:08:38.57#ibcon#[25=AT04-07\r\n] 2006.211.08:08:38.57#ibcon#*before write, iclass 3, count 2 2006.211.08:08:38.57#ibcon#enter sib2, iclass 3, count 2 2006.211.08:08:38.57#ibcon#flushed, iclass 3, count 2 2006.211.08:08:38.57#ibcon#about to write, iclass 3, count 2 2006.211.08:08:38.57#ibcon#wrote, iclass 3, count 2 2006.211.08:08:38.57#ibcon#about to read 3, iclass 3, count 2 2006.211.08:08:38.60#ibcon#read 3, iclass 3, count 2 2006.211.08:08:38.60#ibcon#about to read 4, iclass 3, count 2 2006.211.08:08:38.60#ibcon#read 4, iclass 3, count 2 2006.211.08:08:38.60#ibcon#about to read 5, iclass 3, count 2 2006.211.08:08:38.60#ibcon#read 5, iclass 3, count 2 2006.211.08:08:38.60#ibcon#about to read 6, iclass 3, count 2 2006.211.08:08:38.60#ibcon#read 6, iclass 3, count 2 2006.211.08:08:38.60#ibcon#end of sib2, iclass 3, count 2 2006.211.08:08:38.60#ibcon#*after write, iclass 3, count 2 2006.211.08:08:38.60#ibcon#*before return 0, iclass 3, count 2 2006.211.08:08:38.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:38.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:38.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.08:08:38.60#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:38.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:38.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:38.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:38.72#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:08:38.72#ibcon#first serial, iclass 3, count 0 2006.211.08:08:38.72#ibcon#enter sib2, iclass 3, count 0 2006.211.08:08:38.72#ibcon#flushed, iclass 3, count 0 2006.211.08:08:38.72#ibcon#about to write, iclass 3, count 0 2006.211.08:08:38.72#ibcon#wrote, iclass 3, count 0 2006.211.08:08:38.72#ibcon#about to read 3, iclass 3, count 0 2006.211.08:08:38.74#ibcon#read 3, iclass 3, count 0 2006.211.08:08:38.74#ibcon#about to read 4, iclass 3, count 0 2006.211.08:08:38.74#ibcon#read 4, iclass 3, count 0 2006.211.08:08:38.74#ibcon#about to read 5, iclass 3, count 0 2006.211.08:08:38.74#ibcon#read 5, iclass 3, count 0 2006.211.08:08:38.74#ibcon#about to read 6, iclass 3, count 0 2006.211.08:08:38.74#ibcon#read 6, iclass 3, count 0 2006.211.08:08:38.74#ibcon#end of sib2, iclass 3, count 0 2006.211.08:08:38.74#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:08:38.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:08:38.74#ibcon#[25=USB\r\n] 2006.211.08:08:38.74#ibcon#*before write, iclass 3, count 0 2006.211.08:08:38.74#ibcon#enter sib2, iclass 3, count 0 2006.211.08:08:38.74#ibcon#flushed, iclass 3, count 0 2006.211.08:08:38.74#ibcon#about to write, iclass 3, count 0 2006.211.08:08:38.74#ibcon#wrote, iclass 3, count 0 2006.211.08:08:38.74#ibcon#about to read 3, iclass 3, count 0 2006.211.08:08:38.77#ibcon#read 3, iclass 3, count 0 2006.211.08:08:38.77#ibcon#about to read 4, iclass 3, count 0 2006.211.08:08:38.77#ibcon#read 4, iclass 3, count 0 2006.211.08:08:38.77#ibcon#about to read 5, iclass 3, count 0 2006.211.08:08:38.77#ibcon#read 5, iclass 3, count 0 2006.211.08:08:38.77#ibcon#about to read 6, iclass 3, count 0 2006.211.08:08:38.77#ibcon#read 6, iclass 3, count 0 2006.211.08:08:38.77#ibcon#end of sib2, iclass 3, count 0 2006.211.08:08:38.77#ibcon#*after write, iclass 3, count 0 2006.211.08:08:38.77#ibcon#*before return 0, iclass 3, count 0 2006.211.08:08:38.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:38.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:38.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:08:38.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:08:38.77$vc4f8/valo=5,652.99 2006.211.08:08:38.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.08:08:38.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.08:08:38.77#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:38.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:38.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:38.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:38.77#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:08:38.77#ibcon#first serial, iclass 5, count 0 2006.211.08:08:38.77#ibcon#enter sib2, iclass 5, count 0 2006.211.08:08:38.77#ibcon#flushed, iclass 5, count 0 2006.211.08:08:38.77#ibcon#about to write, iclass 5, count 0 2006.211.08:08:38.77#ibcon#wrote, iclass 5, count 0 2006.211.08:08:38.77#ibcon#about to read 3, iclass 5, count 0 2006.211.08:08:38.79#ibcon#read 3, iclass 5, count 0 2006.211.08:08:38.79#ibcon#about to read 4, iclass 5, count 0 2006.211.08:08:38.79#ibcon#read 4, iclass 5, count 0 2006.211.08:08:38.79#ibcon#about to read 5, iclass 5, count 0 2006.211.08:08:38.79#ibcon#read 5, iclass 5, count 0 2006.211.08:08:38.79#ibcon#about to read 6, iclass 5, count 0 2006.211.08:08:38.79#ibcon#read 6, iclass 5, count 0 2006.211.08:08:38.79#ibcon#end of sib2, iclass 5, count 0 2006.211.08:08:38.79#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:08:38.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:08:38.79#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:08:38.79#ibcon#*before write, iclass 5, count 0 2006.211.08:08:38.79#ibcon#enter sib2, iclass 5, count 0 2006.211.08:08:38.79#ibcon#flushed, iclass 5, count 0 2006.211.08:08:38.79#ibcon#about to write, iclass 5, count 0 2006.211.08:08:38.79#ibcon#wrote, iclass 5, count 0 2006.211.08:08:38.79#ibcon#about to read 3, iclass 5, count 0 2006.211.08:08:38.83#ibcon#read 3, iclass 5, count 0 2006.211.08:08:38.83#ibcon#about to read 4, iclass 5, count 0 2006.211.08:08:38.83#ibcon#read 4, iclass 5, count 0 2006.211.08:08:38.83#ibcon#about to read 5, iclass 5, count 0 2006.211.08:08:38.83#ibcon#read 5, iclass 5, count 0 2006.211.08:08:38.83#ibcon#about to read 6, iclass 5, count 0 2006.211.08:08:38.83#ibcon#read 6, iclass 5, count 0 2006.211.08:08:38.83#ibcon#end of sib2, iclass 5, count 0 2006.211.08:08:38.83#ibcon#*after write, iclass 5, count 0 2006.211.08:08:38.83#ibcon#*before return 0, iclass 5, count 0 2006.211.08:08:38.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:38.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:38.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:08:38.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:08:38.83$vc4f8/va=5,7 2006.211.08:08:38.83#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.08:08:38.83#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.08:08:38.83#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:38.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:38.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:38.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:38.89#ibcon#enter wrdev, iclass 7, count 2 2006.211.08:08:38.89#ibcon#first serial, iclass 7, count 2 2006.211.08:08:38.89#ibcon#enter sib2, iclass 7, count 2 2006.211.08:08:38.89#ibcon#flushed, iclass 7, count 2 2006.211.08:08:38.89#ibcon#about to write, iclass 7, count 2 2006.211.08:08:38.89#ibcon#wrote, iclass 7, count 2 2006.211.08:08:38.89#ibcon#about to read 3, iclass 7, count 2 2006.211.08:08:38.91#ibcon#read 3, iclass 7, count 2 2006.211.08:08:38.91#ibcon#about to read 4, iclass 7, count 2 2006.211.08:08:38.91#ibcon#read 4, iclass 7, count 2 2006.211.08:08:38.91#ibcon#about to read 5, iclass 7, count 2 2006.211.08:08:38.91#ibcon#read 5, iclass 7, count 2 2006.211.08:08:38.91#ibcon#about to read 6, iclass 7, count 2 2006.211.08:08:38.91#ibcon#read 6, iclass 7, count 2 2006.211.08:08:38.91#ibcon#end of sib2, iclass 7, count 2 2006.211.08:08:38.91#ibcon#*mode == 0, iclass 7, count 2 2006.211.08:08:38.91#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.08:08:38.91#ibcon#[25=AT05-07\r\n] 2006.211.08:08:38.91#ibcon#*before write, iclass 7, count 2 2006.211.08:08:38.91#ibcon#enter sib2, iclass 7, count 2 2006.211.08:08:38.91#ibcon#flushed, iclass 7, count 2 2006.211.08:08:38.91#ibcon#about to write, iclass 7, count 2 2006.211.08:08:38.91#ibcon#wrote, iclass 7, count 2 2006.211.08:08:38.91#ibcon#about to read 3, iclass 7, count 2 2006.211.08:08:38.94#ibcon#read 3, iclass 7, count 2 2006.211.08:08:38.94#ibcon#about to read 4, iclass 7, count 2 2006.211.08:08:38.94#ibcon#read 4, iclass 7, count 2 2006.211.08:08:38.94#ibcon#about to read 5, iclass 7, count 2 2006.211.08:08:38.94#ibcon#read 5, iclass 7, count 2 2006.211.08:08:38.94#ibcon#about to read 6, iclass 7, count 2 2006.211.08:08:38.94#ibcon#read 6, iclass 7, count 2 2006.211.08:08:38.94#ibcon#end of sib2, iclass 7, count 2 2006.211.08:08:38.94#ibcon#*after write, iclass 7, count 2 2006.211.08:08:38.94#ibcon#*before return 0, iclass 7, count 2 2006.211.08:08:38.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:38.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:38.94#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.08:08:38.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:38.94#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:39.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:39.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:39.06#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:08:39.06#ibcon#first serial, iclass 7, count 0 2006.211.08:08:39.06#ibcon#enter sib2, iclass 7, count 0 2006.211.08:08:39.06#ibcon#flushed, iclass 7, count 0 2006.211.08:08:39.06#ibcon#about to write, iclass 7, count 0 2006.211.08:08:39.06#ibcon#wrote, iclass 7, count 0 2006.211.08:08:39.06#ibcon#about to read 3, iclass 7, count 0 2006.211.08:08:39.08#ibcon#read 3, iclass 7, count 0 2006.211.08:08:39.08#ibcon#about to read 4, iclass 7, count 0 2006.211.08:08:39.08#ibcon#read 4, iclass 7, count 0 2006.211.08:08:39.08#ibcon#about to read 5, iclass 7, count 0 2006.211.08:08:39.08#ibcon#read 5, iclass 7, count 0 2006.211.08:08:39.08#ibcon#about to read 6, iclass 7, count 0 2006.211.08:08:39.08#ibcon#read 6, iclass 7, count 0 2006.211.08:08:39.08#ibcon#end of sib2, iclass 7, count 0 2006.211.08:08:39.08#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:08:39.08#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:08:39.08#ibcon#[25=USB\r\n] 2006.211.08:08:39.08#ibcon#*before write, iclass 7, count 0 2006.211.08:08:39.08#ibcon#enter sib2, iclass 7, count 0 2006.211.08:08:39.08#ibcon#flushed, iclass 7, count 0 2006.211.08:08:39.08#ibcon#about to write, iclass 7, count 0 2006.211.08:08:39.08#ibcon#wrote, iclass 7, count 0 2006.211.08:08:39.08#ibcon#about to read 3, iclass 7, count 0 2006.211.08:08:39.11#ibcon#read 3, iclass 7, count 0 2006.211.08:08:39.11#ibcon#about to read 4, iclass 7, count 0 2006.211.08:08:39.11#ibcon#read 4, iclass 7, count 0 2006.211.08:08:39.11#ibcon#about to read 5, iclass 7, count 0 2006.211.08:08:39.11#ibcon#read 5, iclass 7, count 0 2006.211.08:08:39.11#ibcon#about to read 6, iclass 7, count 0 2006.211.08:08:39.11#ibcon#read 6, iclass 7, count 0 2006.211.08:08:39.11#ibcon#end of sib2, iclass 7, count 0 2006.211.08:08:39.11#ibcon#*after write, iclass 7, count 0 2006.211.08:08:39.11#ibcon#*before return 0, iclass 7, count 0 2006.211.08:08:39.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:39.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:39.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:08:39.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:08:39.11$vc4f8/valo=6,772.99 2006.211.08:08:39.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.08:08:39.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.08:08:39.11#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:39.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:39.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:39.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:39.11#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:08:39.11#ibcon#first serial, iclass 11, count 0 2006.211.08:08:39.11#ibcon#enter sib2, iclass 11, count 0 2006.211.08:08:39.11#ibcon#flushed, iclass 11, count 0 2006.211.08:08:39.11#ibcon#about to write, iclass 11, count 0 2006.211.08:08:39.11#ibcon#wrote, iclass 11, count 0 2006.211.08:08:39.11#ibcon#about to read 3, iclass 11, count 0 2006.211.08:08:39.13#ibcon#read 3, iclass 11, count 0 2006.211.08:08:39.13#ibcon#about to read 4, iclass 11, count 0 2006.211.08:08:39.13#ibcon#read 4, iclass 11, count 0 2006.211.08:08:39.13#ibcon#about to read 5, iclass 11, count 0 2006.211.08:08:39.13#ibcon#read 5, iclass 11, count 0 2006.211.08:08:39.13#ibcon#about to read 6, iclass 11, count 0 2006.211.08:08:39.13#ibcon#read 6, iclass 11, count 0 2006.211.08:08:39.13#ibcon#end of sib2, iclass 11, count 0 2006.211.08:08:39.13#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:08:39.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:08:39.13#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:08:39.13#ibcon#*before write, iclass 11, count 0 2006.211.08:08:39.13#ibcon#enter sib2, iclass 11, count 0 2006.211.08:08:39.13#ibcon#flushed, iclass 11, count 0 2006.211.08:08:39.13#ibcon#about to write, iclass 11, count 0 2006.211.08:08:39.13#ibcon#wrote, iclass 11, count 0 2006.211.08:08:39.13#ibcon#about to read 3, iclass 11, count 0 2006.211.08:08:39.17#ibcon#read 3, iclass 11, count 0 2006.211.08:08:39.17#ibcon#about to read 4, iclass 11, count 0 2006.211.08:08:39.17#ibcon#read 4, iclass 11, count 0 2006.211.08:08:39.17#ibcon#about to read 5, iclass 11, count 0 2006.211.08:08:39.17#ibcon#read 5, iclass 11, count 0 2006.211.08:08:39.17#ibcon#about to read 6, iclass 11, count 0 2006.211.08:08:39.17#ibcon#read 6, iclass 11, count 0 2006.211.08:08:39.17#ibcon#end of sib2, iclass 11, count 0 2006.211.08:08:39.17#ibcon#*after write, iclass 11, count 0 2006.211.08:08:39.17#ibcon#*before return 0, iclass 11, count 0 2006.211.08:08:39.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:39.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:39.17#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:08:39.17#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:08:39.17$vc4f8/va=6,6 2006.211.08:08:39.17#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.08:08:39.17#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.08:08:39.17#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:39.17#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:08:39.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:08:39.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:08:39.23#ibcon#enter wrdev, iclass 13, count 2 2006.211.08:08:39.23#ibcon#first serial, iclass 13, count 2 2006.211.08:08:39.23#ibcon#enter sib2, iclass 13, count 2 2006.211.08:08:39.23#ibcon#flushed, iclass 13, count 2 2006.211.08:08:39.23#ibcon#about to write, iclass 13, count 2 2006.211.08:08:39.23#ibcon#wrote, iclass 13, count 2 2006.211.08:08:39.23#ibcon#about to read 3, iclass 13, count 2 2006.211.08:08:39.25#ibcon#read 3, iclass 13, count 2 2006.211.08:08:39.25#ibcon#about to read 4, iclass 13, count 2 2006.211.08:08:39.25#ibcon#read 4, iclass 13, count 2 2006.211.08:08:39.25#ibcon#about to read 5, iclass 13, count 2 2006.211.08:08:39.25#ibcon#read 5, iclass 13, count 2 2006.211.08:08:39.25#ibcon#about to read 6, iclass 13, count 2 2006.211.08:08:39.25#ibcon#read 6, iclass 13, count 2 2006.211.08:08:39.25#ibcon#end of sib2, iclass 13, count 2 2006.211.08:08:39.25#ibcon#*mode == 0, iclass 13, count 2 2006.211.08:08:39.25#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.08:08:39.25#ibcon#[25=AT06-06\r\n] 2006.211.08:08:39.25#ibcon#*before write, iclass 13, count 2 2006.211.08:08:39.25#ibcon#enter sib2, iclass 13, count 2 2006.211.08:08:39.25#ibcon#flushed, iclass 13, count 2 2006.211.08:08:39.25#ibcon#about to write, iclass 13, count 2 2006.211.08:08:39.25#ibcon#wrote, iclass 13, count 2 2006.211.08:08:39.25#ibcon#about to read 3, iclass 13, count 2 2006.211.08:08:39.28#ibcon#read 3, iclass 13, count 2 2006.211.08:08:39.28#ibcon#about to read 4, iclass 13, count 2 2006.211.08:08:39.28#ibcon#read 4, iclass 13, count 2 2006.211.08:08:39.28#ibcon#about to read 5, iclass 13, count 2 2006.211.08:08:39.28#ibcon#read 5, iclass 13, count 2 2006.211.08:08:39.28#ibcon#about to read 6, iclass 13, count 2 2006.211.08:08:39.28#ibcon#read 6, iclass 13, count 2 2006.211.08:08:39.28#ibcon#end of sib2, iclass 13, count 2 2006.211.08:08:39.28#ibcon#*after write, iclass 13, count 2 2006.211.08:08:39.28#ibcon#*before return 0, iclass 13, count 2 2006.211.08:08:39.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:08:39.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:08:39.28#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.08:08:39.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:39.28#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:08:39.40#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:08:39.40#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:08:39.40#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:08:39.40#ibcon#first serial, iclass 13, count 0 2006.211.08:08:39.40#ibcon#enter sib2, iclass 13, count 0 2006.211.08:08:39.40#ibcon#flushed, iclass 13, count 0 2006.211.08:08:39.40#ibcon#about to write, iclass 13, count 0 2006.211.08:08:39.40#ibcon#wrote, iclass 13, count 0 2006.211.08:08:39.40#ibcon#about to read 3, iclass 13, count 0 2006.211.08:08:39.42#ibcon#read 3, iclass 13, count 0 2006.211.08:08:39.42#ibcon#about to read 4, iclass 13, count 0 2006.211.08:08:39.42#ibcon#read 4, iclass 13, count 0 2006.211.08:08:39.42#ibcon#about to read 5, iclass 13, count 0 2006.211.08:08:39.42#ibcon#read 5, iclass 13, count 0 2006.211.08:08:39.42#ibcon#about to read 6, iclass 13, count 0 2006.211.08:08:39.42#ibcon#read 6, iclass 13, count 0 2006.211.08:08:39.42#ibcon#end of sib2, iclass 13, count 0 2006.211.08:08:39.42#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:08:39.42#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:08:39.42#ibcon#[25=USB\r\n] 2006.211.08:08:39.42#ibcon#*before write, iclass 13, count 0 2006.211.08:08:39.42#ibcon#enter sib2, iclass 13, count 0 2006.211.08:08:39.42#ibcon#flushed, iclass 13, count 0 2006.211.08:08:39.42#ibcon#about to write, iclass 13, count 0 2006.211.08:08:39.42#ibcon#wrote, iclass 13, count 0 2006.211.08:08:39.42#ibcon#about to read 3, iclass 13, count 0 2006.211.08:08:39.45#ibcon#read 3, iclass 13, count 0 2006.211.08:08:39.45#ibcon#about to read 4, iclass 13, count 0 2006.211.08:08:39.45#ibcon#read 4, iclass 13, count 0 2006.211.08:08:39.45#ibcon#about to read 5, iclass 13, count 0 2006.211.08:08:39.45#ibcon#read 5, iclass 13, count 0 2006.211.08:08:39.45#ibcon#about to read 6, iclass 13, count 0 2006.211.08:08:39.45#ibcon#read 6, iclass 13, count 0 2006.211.08:08:39.45#ibcon#end of sib2, iclass 13, count 0 2006.211.08:08:39.45#ibcon#*after write, iclass 13, count 0 2006.211.08:08:39.45#ibcon#*before return 0, iclass 13, count 0 2006.211.08:08:39.45#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:08:39.45#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:08:39.45#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:08:39.45#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:08:39.45$vc4f8/valo=7,832.99 2006.211.08:08:39.45#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.08:08:39.45#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.08:08:39.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:39.45#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:08:39.45#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:08:39.45#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:08:39.45#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:08:39.45#ibcon#first serial, iclass 15, count 0 2006.211.08:08:39.45#ibcon#enter sib2, iclass 15, count 0 2006.211.08:08:39.45#ibcon#flushed, iclass 15, count 0 2006.211.08:08:39.45#ibcon#about to write, iclass 15, count 0 2006.211.08:08:39.45#ibcon#wrote, iclass 15, count 0 2006.211.08:08:39.45#ibcon#about to read 3, iclass 15, count 0 2006.211.08:08:39.47#ibcon#read 3, iclass 15, count 0 2006.211.08:08:39.47#ibcon#about to read 4, iclass 15, count 0 2006.211.08:08:39.47#ibcon#read 4, iclass 15, count 0 2006.211.08:08:39.47#ibcon#about to read 5, iclass 15, count 0 2006.211.08:08:39.47#ibcon#read 5, iclass 15, count 0 2006.211.08:08:39.47#ibcon#about to read 6, iclass 15, count 0 2006.211.08:08:39.47#ibcon#read 6, iclass 15, count 0 2006.211.08:08:39.47#ibcon#end of sib2, iclass 15, count 0 2006.211.08:08:39.47#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:08:39.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:08:39.47#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:08:39.47#ibcon#*before write, iclass 15, count 0 2006.211.08:08:39.47#ibcon#enter sib2, iclass 15, count 0 2006.211.08:08:39.47#ibcon#flushed, iclass 15, count 0 2006.211.08:08:39.47#ibcon#about to write, iclass 15, count 0 2006.211.08:08:39.47#ibcon#wrote, iclass 15, count 0 2006.211.08:08:39.47#ibcon#about to read 3, iclass 15, count 0 2006.211.08:08:39.51#ibcon#read 3, iclass 15, count 0 2006.211.08:08:39.51#ibcon#about to read 4, iclass 15, count 0 2006.211.08:08:39.51#ibcon#read 4, iclass 15, count 0 2006.211.08:08:39.51#ibcon#about to read 5, iclass 15, count 0 2006.211.08:08:39.51#ibcon#read 5, iclass 15, count 0 2006.211.08:08:39.51#ibcon#about to read 6, iclass 15, count 0 2006.211.08:08:39.51#ibcon#read 6, iclass 15, count 0 2006.211.08:08:39.51#ibcon#end of sib2, iclass 15, count 0 2006.211.08:08:39.51#ibcon#*after write, iclass 15, count 0 2006.211.08:08:39.51#ibcon#*before return 0, iclass 15, count 0 2006.211.08:08:39.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:08:39.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:08:39.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:08:39.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:08:39.51$vc4f8/va=7,6 2006.211.08:08:39.51#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.08:08:39.51#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.08:08:39.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:39.51#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:08:39.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:08:39.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:08:39.57#ibcon#enter wrdev, iclass 17, count 2 2006.211.08:08:39.57#ibcon#first serial, iclass 17, count 2 2006.211.08:08:39.57#ibcon#enter sib2, iclass 17, count 2 2006.211.08:08:39.57#ibcon#flushed, iclass 17, count 2 2006.211.08:08:39.57#ibcon#about to write, iclass 17, count 2 2006.211.08:08:39.57#ibcon#wrote, iclass 17, count 2 2006.211.08:08:39.57#ibcon#about to read 3, iclass 17, count 2 2006.211.08:08:39.59#ibcon#read 3, iclass 17, count 2 2006.211.08:08:39.59#ibcon#about to read 4, iclass 17, count 2 2006.211.08:08:39.59#ibcon#read 4, iclass 17, count 2 2006.211.08:08:39.59#ibcon#about to read 5, iclass 17, count 2 2006.211.08:08:39.59#ibcon#read 5, iclass 17, count 2 2006.211.08:08:39.59#ibcon#about to read 6, iclass 17, count 2 2006.211.08:08:39.59#ibcon#read 6, iclass 17, count 2 2006.211.08:08:39.59#ibcon#end of sib2, iclass 17, count 2 2006.211.08:08:39.59#ibcon#*mode == 0, iclass 17, count 2 2006.211.08:08:39.59#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.08:08:39.59#ibcon#[25=AT07-06\r\n] 2006.211.08:08:39.59#ibcon#*before write, iclass 17, count 2 2006.211.08:08:39.59#ibcon#enter sib2, iclass 17, count 2 2006.211.08:08:39.59#ibcon#flushed, iclass 17, count 2 2006.211.08:08:39.59#ibcon#about to write, iclass 17, count 2 2006.211.08:08:39.59#ibcon#wrote, iclass 17, count 2 2006.211.08:08:39.59#ibcon#about to read 3, iclass 17, count 2 2006.211.08:08:39.62#ibcon#read 3, iclass 17, count 2 2006.211.08:08:39.62#ibcon#about to read 4, iclass 17, count 2 2006.211.08:08:39.62#ibcon#read 4, iclass 17, count 2 2006.211.08:08:39.62#ibcon#about to read 5, iclass 17, count 2 2006.211.08:08:39.62#ibcon#read 5, iclass 17, count 2 2006.211.08:08:39.62#ibcon#about to read 6, iclass 17, count 2 2006.211.08:08:39.62#ibcon#read 6, iclass 17, count 2 2006.211.08:08:39.62#ibcon#end of sib2, iclass 17, count 2 2006.211.08:08:39.62#ibcon#*after write, iclass 17, count 2 2006.211.08:08:39.62#ibcon#*before return 0, iclass 17, count 2 2006.211.08:08:39.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:08:39.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:08:39.62#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.08:08:39.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:39.62#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:08:39.74#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:08:39.74#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:08:39.74#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:08:39.74#ibcon#first serial, iclass 17, count 0 2006.211.08:08:39.74#ibcon#enter sib2, iclass 17, count 0 2006.211.08:08:39.74#ibcon#flushed, iclass 17, count 0 2006.211.08:08:39.74#ibcon#about to write, iclass 17, count 0 2006.211.08:08:39.74#ibcon#wrote, iclass 17, count 0 2006.211.08:08:39.74#ibcon#about to read 3, iclass 17, count 0 2006.211.08:08:39.76#ibcon#read 3, iclass 17, count 0 2006.211.08:08:39.76#ibcon#about to read 4, iclass 17, count 0 2006.211.08:08:39.76#ibcon#read 4, iclass 17, count 0 2006.211.08:08:39.76#ibcon#about to read 5, iclass 17, count 0 2006.211.08:08:39.76#ibcon#read 5, iclass 17, count 0 2006.211.08:08:39.76#ibcon#about to read 6, iclass 17, count 0 2006.211.08:08:39.76#ibcon#read 6, iclass 17, count 0 2006.211.08:08:39.76#ibcon#end of sib2, iclass 17, count 0 2006.211.08:08:39.76#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:08:39.76#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:08:39.76#ibcon#[25=USB\r\n] 2006.211.08:08:39.76#ibcon#*before write, iclass 17, count 0 2006.211.08:08:39.76#ibcon#enter sib2, iclass 17, count 0 2006.211.08:08:39.76#ibcon#flushed, iclass 17, count 0 2006.211.08:08:39.76#ibcon#about to write, iclass 17, count 0 2006.211.08:08:39.76#ibcon#wrote, iclass 17, count 0 2006.211.08:08:39.76#ibcon#about to read 3, iclass 17, count 0 2006.211.08:08:39.79#ibcon#read 3, iclass 17, count 0 2006.211.08:08:39.79#ibcon#about to read 4, iclass 17, count 0 2006.211.08:08:39.79#ibcon#read 4, iclass 17, count 0 2006.211.08:08:39.79#ibcon#about to read 5, iclass 17, count 0 2006.211.08:08:39.79#ibcon#read 5, iclass 17, count 0 2006.211.08:08:39.79#ibcon#about to read 6, iclass 17, count 0 2006.211.08:08:39.79#ibcon#read 6, iclass 17, count 0 2006.211.08:08:39.79#ibcon#end of sib2, iclass 17, count 0 2006.211.08:08:39.79#ibcon#*after write, iclass 17, count 0 2006.211.08:08:39.79#ibcon#*before return 0, iclass 17, count 0 2006.211.08:08:39.79#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:08:39.79#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:08:39.79#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:08:39.79#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:08:39.79$vc4f8/valo=8,852.99 2006.211.08:08:39.79#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.08:08:39.79#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.08:08:39.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:39.79#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:08:39.79#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:08:39.79#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:08:39.79#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:08:39.79#ibcon#first serial, iclass 19, count 0 2006.211.08:08:39.79#ibcon#enter sib2, iclass 19, count 0 2006.211.08:08:39.79#ibcon#flushed, iclass 19, count 0 2006.211.08:08:39.79#ibcon#about to write, iclass 19, count 0 2006.211.08:08:39.79#ibcon#wrote, iclass 19, count 0 2006.211.08:08:39.79#ibcon#about to read 3, iclass 19, count 0 2006.211.08:08:39.81#ibcon#read 3, iclass 19, count 0 2006.211.08:08:39.81#ibcon#about to read 4, iclass 19, count 0 2006.211.08:08:39.81#ibcon#read 4, iclass 19, count 0 2006.211.08:08:39.81#ibcon#about to read 5, iclass 19, count 0 2006.211.08:08:39.81#ibcon#read 5, iclass 19, count 0 2006.211.08:08:39.81#ibcon#about to read 6, iclass 19, count 0 2006.211.08:08:39.81#ibcon#read 6, iclass 19, count 0 2006.211.08:08:39.81#ibcon#end of sib2, iclass 19, count 0 2006.211.08:08:39.81#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:08:39.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:08:39.81#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:08:39.81#ibcon#*before write, iclass 19, count 0 2006.211.08:08:39.81#ibcon#enter sib2, iclass 19, count 0 2006.211.08:08:39.81#ibcon#flushed, iclass 19, count 0 2006.211.08:08:39.81#ibcon#about to write, iclass 19, count 0 2006.211.08:08:39.81#ibcon#wrote, iclass 19, count 0 2006.211.08:08:39.81#ibcon#about to read 3, iclass 19, count 0 2006.211.08:08:39.85#ibcon#read 3, iclass 19, count 0 2006.211.08:08:39.85#ibcon#about to read 4, iclass 19, count 0 2006.211.08:08:39.85#ibcon#read 4, iclass 19, count 0 2006.211.08:08:39.85#ibcon#about to read 5, iclass 19, count 0 2006.211.08:08:39.85#ibcon#read 5, iclass 19, count 0 2006.211.08:08:39.85#ibcon#about to read 6, iclass 19, count 0 2006.211.08:08:39.85#ibcon#read 6, iclass 19, count 0 2006.211.08:08:39.85#ibcon#end of sib2, iclass 19, count 0 2006.211.08:08:39.85#ibcon#*after write, iclass 19, count 0 2006.211.08:08:39.85#ibcon#*before return 0, iclass 19, count 0 2006.211.08:08:39.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:08:39.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:08:39.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:08:39.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:08:39.85$vc4f8/va=8,7 2006.211.08:08:39.85#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.08:08:39.85#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.08:08:39.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:39.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:08:39.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:08:39.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:08:39.91#ibcon#enter wrdev, iclass 21, count 2 2006.211.08:08:39.91#ibcon#first serial, iclass 21, count 2 2006.211.08:08:39.91#ibcon#enter sib2, iclass 21, count 2 2006.211.08:08:39.91#ibcon#flushed, iclass 21, count 2 2006.211.08:08:39.91#ibcon#about to write, iclass 21, count 2 2006.211.08:08:39.91#ibcon#wrote, iclass 21, count 2 2006.211.08:08:39.91#ibcon#about to read 3, iclass 21, count 2 2006.211.08:08:39.93#ibcon#read 3, iclass 21, count 2 2006.211.08:08:39.93#ibcon#about to read 4, iclass 21, count 2 2006.211.08:08:39.93#ibcon#read 4, iclass 21, count 2 2006.211.08:08:39.93#ibcon#about to read 5, iclass 21, count 2 2006.211.08:08:39.93#ibcon#read 5, iclass 21, count 2 2006.211.08:08:39.93#ibcon#about to read 6, iclass 21, count 2 2006.211.08:08:39.93#ibcon#read 6, iclass 21, count 2 2006.211.08:08:39.93#ibcon#end of sib2, iclass 21, count 2 2006.211.08:08:39.93#ibcon#*mode == 0, iclass 21, count 2 2006.211.08:08:39.93#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.08:08:39.93#ibcon#[25=AT08-07\r\n] 2006.211.08:08:39.93#ibcon#*before write, iclass 21, count 2 2006.211.08:08:39.93#ibcon#enter sib2, iclass 21, count 2 2006.211.08:08:39.93#ibcon#flushed, iclass 21, count 2 2006.211.08:08:39.93#ibcon#about to write, iclass 21, count 2 2006.211.08:08:39.93#ibcon#wrote, iclass 21, count 2 2006.211.08:08:39.93#ibcon#about to read 3, iclass 21, count 2 2006.211.08:08:39.96#ibcon#read 3, iclass 21, count 2 2006.211.08:08:39.96#ibcon#about to read 4, iclass 21, count 2 2006.211.08:08:39.96#ibcon#read 4, iclass 21, count 2 2006.211.08:08:39.96#ibcon#about to read 5, iclass 21, count 2 2006.211.08:08:39.96#ibcon#read 5, iclass 21, count 2 2006.211.08:08:39.96#ibcon#about to read 6, iclass 21, count 2 2006.211.08:08:39.96#ibcon#read 6, iclass 21, count 2 2006.211.08:08:39.96#ibcon#end of sib2, iclass 21, count 2 2006.211.08:08:39.96#ibcon#*after write, iclass 21, count 2 2006.211.08:08:39.96#ibcon#*before return 0, iclass 21, count 2 2006.211.08:08:39.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:08:39.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:08:39.96#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.08:08:39.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:39.96#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:08:40.08#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:08:40.08#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:08:40.08#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:08:40.08#ibcon#first serial, iclass 21, count 0 2006.211.08:08:40.08#ibcon#enter sib2, iclass 21, count 0 2006.211.08:08:40.08#ibcon#flushed, iclass 21, count 0 2006.211.08:08:40.08#ibcon#about to write, iclass 21, count 0 2006.211.08:08:40.08#ibcon#wrote, iclass 21, count 0 2006.211.08:08:40.08#ibcon#about to read 3, iclass 21, count 0 2006.211.08:08:40.10#ibcon#read 3, iclass 21, count 0 2006.211.08:08:40.10#ibcon#about to read 4, iclass 21, count 0 2006.211.08:08:40.10#ibcon#read 4, iclass 21, count 0 2006.211.08:08:40.10#ibcon#about to read 5, iclass 21, count 0 2006.211.08:08:40.10#ibcon#read 5, iclass 21, count 0 2006.211.08:08:40.10#ibcon#about to read 6, iclass 21, count 0 2006.211.08:08:40.10#ibcon#read 6, iclass 21, count 0 2006.211.08:08:40.10#ibcon#end of sib2, iclass 21, count 0 2006.211.08:08:40.10#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:08:40.10#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:08:40.10#ibcon#[25=USB\r\n] 2006.211.08:08:40.10#ibcon#*before write, iclass 21, count 0 2006.211.08:08:40.10#ibcon#enter sib2, iclass 21, count 0 2006.211.08:08:40.10#ibcon#flushed, iclass 21, count 0 2006.211.08:08:40.10#ibcon#about to write, iclass 21, count 0 2006.211.08:08:40.10#ibcon#wrote, iclass 21, count 0 2006.211.08:08:40.10#ibcon#about to read 3, iclass 21, count 0 2006.211.08:08:40.13#ibcon#read 3, iclass 21, count 0 2006.211.08:08:40.13#ibcon#about to read 4, iclass 21, count 0 2006.211.08:08:40.13#ibcon#read 4, iclass 21, count 0 2006.211.08:08:40.13#ibcon#about to read 5, iclass 21, count 0 2006.211.08:08:40.13#ibcon#read 5, iclass 21, count 0 2006.211.08:08:40.13#ibcon#about to read 6, iclass 21, count 0 2006.211.08:08:40.13#ibcon#read 6, iclass 21, count 0 2006.211.08:08:40.13#ibcon#end of sib2, iclass 21, count 0 2006.211.08:08:40.13#ibcon#*after write, iclass 21, count 0 2006.211.08:08:40.13#ibcon#*before return 0, iclass 21, count 0 2006.211.08:08:40.13#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:08:40.13#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:08:40.13#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:08:40.13#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:08:40.13$vc4f8/vblo=1,632.99 2006.211.08:08:40.13#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.08:08:40.13#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.08:08:40.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:40.13#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:08:40.13#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:08:40.13#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:08:40.13#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:08:40.13#ibcon#first serial, iclass 23, count 0 2006.211.08:08:40.13#ibcon#enter sib2, iclass 23, count 0 2006.211.08:08:40.13#ibcon#flushed, iclass 23, count 0 2006.211.08:08:40.13#ibcon#about to write, iclass 23, count 0 2006.211.08:08:40.13#ibcon#wrote, iclass 23, count 0 2006.211.08:08:40.13#ibcon#about to read 3, iclass 23, count 0 2006.211.08:08:40.15#ibcon#read 3, iclass 23, count 0 2006.211.08:08:40.15#ibcon#about to read 4, iclass 23, count 0 2006.211.08:08:40.15#ibcon#read 4, iclass 23, count 0 2006.211.08:08:40.15#ibcon#about to read 5, iclass 23, count 0 2006.211.08:08:40.15#ibcon#read 5, iclass 23, count 0 2006.211.08:08:40.15#ibcon#about to read 6, iclass 23, count 0 2006.211.08:08:40.15#ibcon#read 6, iclass 23, count 0 2006.211.08:08:40.15#ibcon#end of sib2, iclass 23, count 0 2006.211.08:08:40.15#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:08:40.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:08:40.15#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:08:40.15#ibcon#*before write, iclass 23, count 0 2006.211.08:08:40.15#ibcon#enter sib2, iclass 23, count 0 2006.211.08:08:40.15#ibcon#flushed, iclass 23, count 0 2006.211.08:08:40.15#ibcon#about to write, iclass 23, count 0 2006.211.08:08:40.15#ibcon#wrote, iclass 23, count 0 2006.211.08:08:40.15#ibcon#about to read 3, iclass 23, count 0 2006.211.08:08:40.19#ibcon#read 3, iclass 23, count 0 2006.211.08:08:40.19#ibcon#about to read 4, iclass 23, count 0 2006.211.08:08:40.19#ibcon#read 4, iclass 23, count 0 2006.211.08:08:40.19#ibcon#about to read 5, iclass 23, count 0 2006.211.08:08:40.19#ibcon#read 5, iclass 23, count 0 2006.211.08:08:40.19#ibcon#about to read 6, iclass 23, count 0 2006.211.08:08:40.19#ibcon#read 6, iclass 23, count 0 2006.211.08:08:40.19#ibcon#end of sib2, iclass 23, count 0 2006.211.08:08:40.19#ibcon#*after write, iclass 23, count 0 2006.211.08:08:40.19#ibcon#*before return 0, iclass 23, count 0 2006.211.08:08:40.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:08:40.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:08:40.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:08:40.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:08:40.19$vc4f8/vb=1,4 2006.211.08:08:40.19#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.08:08:40.19#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.08:08:40.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:40.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:08:40.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:08:40.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:08:40.19#ibcon#enter wrdev, iclass 25, count 2 2006.211.08:08:40.19#ibcon#first serial, iclass 25, count 2 2006.211.08:08:40.19#ibcon#enter sib2, iclass 25, count 2 2006.211.08:08:40.19#ibcon#flushed, iclass 25, count 2 2006.211.08:08:40.19#ibcon#about to write, iclass 25, count 2 2006.211.08:08:40.19#ibcon#wrote, iclass 25, count 2 2006.211.08:08:40.19#ibcon#about to read 3, iclass 25, count 2 2006.211.08:08:40.21#ibcon#read 3, iclass 25, count 2 2006.211.08:08:40.21#ibcon#about to read 4, iclass 25, count 2 2006.211.08:08:40.21#ibcon#read 4, iclass 25, count 2 2006.211.08:08:40.21#ibcon#about to read 5, iclass 25, count 2 2006.211.08:08:40.21#ibcon#read 5, iclass 25, count 2 2006.211.08:08:40.21#ibcon#about to read 6, iclass 25, count 2 2006.211.08:08:40.21#ibcon#read 6, iclass 25, count 2 2006.211.08:08:40.21#ibcon#end of sib2, iclass 25, count 2 2006.211.08:08:40.21#ibcon#*mode == 0, iclass 25, count 2 2006.211.08:08:40.21#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.08:08:40.21#ibcon#[27=AT01-04\r\n] 2006.211.08:08:40.21#ibcon#*before write, iclass 25, count 2 2006.211.08:08:40.21#ibcon#enter sib2, iclass 25, count 2 2006.211.08:08:40.21#ibcon#flushed, iclass 25, count 2 2006.211.08:08:40.21#ibcon#about to write, iclass 25, count 2 2006.211.08:08:40.21#ibcon#wrote, iclass 25, count 2 2006.211.08:08:40.21#ibcon#about to read 3, iclass 25, count 2 2006.211.08:08:40.24#ibcon#read 3, iclass 25, count 2 2006.211.08:08:40.24#ibcon#about to read 4, iclass 25, count 2 2006.211.08:08:40.24#ibcon#read 4, iclass 25, count 2 2006.211.08:08:40.24#ibcon#about to read 5, iclass 25, count 2 2006.211.08:08:40.24#ibcon#read 5, iclass 25, count 2 2006.211.08:08:40.24#ibcon#about to read 6, iclass 25, count 2 2006.211.08:08:40.24#ibcon#read 6, iclass 25, count 2 2006.211.08:08:40.24#ibcon#end of sib2, iclass 25, count 2 2006.211.08:08:40.24#ibcon#*after write, iclass 25, count 2 2006.211.08:08:40.24#ibcon#*before return 0, iclass 25, count 2 2006.211.08:08:40.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:08:40.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:08:40.24#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.08:08:40.24#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:40.24#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:08:40.36#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:08:40.36#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:08:40.36#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:08:40.36#ibcon#first serial, iclass 25, count 0 2006.211.08:08:40.36#ibcon#enter sib2, iclass 25, count 0 2006.211.08:08:40.36#ibcon#flushed, iclass 25, count 0 2006.211.08:08:40.36#ibcon#about to write, iclass 25, count 0 2006.211.08:08:40.36#ibcon#wrote, iclass 25, count 0 2006.211.08:08:40.36#ibcon#about to read 3, iclass 25, count 0 2006.211.08:08:40.38#ibcon#read 3, iclass 25, count 0 2006.211.08:08:40.38#ibcon#about to read 4, iclass 25, count 0 2006.211.08:08:40.38#ibcon#read 4, iclass 25, count 0 2006.211.08:08:40.38#ibcon#about to read 5, iclass 25, count 0 2006.211.08:08:40.38#ibcon#read 5, iclass 25, count 0 2006.211.08:08:40.38#ibcon#about to read 6, iclass 25, count 0 2006.211.08:08:40.38#ibcon#read 6, iclass 25, count 0 2006.211.08:08:40.38#ibcon#end of sib2, iclass 25, count 0 2006.211.08:08:40.38#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:08:40.38#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:08:40.38#ibcon#[27=USB\r\n] 2006.211.08:08:40.38#ibcon#*before write, iclass 25, count 0 2006.211.08:08:40.38#ibcon#enter sib2, iclass 25, count 0 2006.211.08:08:40.38#ibcon#flushed, iclass 25, count 0 2006.211.08:08:40.38#ibcon#about to write, iclass 25, count 0 2006.211.08:08:40.38#ibcon#wrote, iclass 25, count 0 2006.211.08:08:40.38#ibcon#about to read 3, iclass 25, count 0 2006.211.08:08:40.41#ibcon#read 3, iclass 25, count 0 2006.211.08:08:40.41#ibcon#about to read 4, iclass 25, count 0 2006.211.08:08:40.41#ibcon#read 4, iclass 25, count 0 2006.211.08:08:40.41#ibcon#about to read 5, iclass 25, count 0 2006.211.08:08:40.41#ibcon#read 5, iclass 25, count 0 2006.211.08:08:40.41#ibcon#about to read 6, iclass 25, count 0 2006.211.08:08:40.41#ibcon#read 6, iclass 25, count 0 2006.211.08:08:40.41#ibcon#end of sib2, iclass 25, count 0 2006.211.08:08:40.41#ibcon#*after write, iclass 25, count 0 2006.211.08:08:40.41#ibcon#*before return 0, iclass 25, count 0 2006.211.08:08:40.41#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:08:40.41#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:08:40.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:08:40.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:08:40.41$vc4f8/vblo=2,640.99 2006.211.08:08:40.41#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.08:08:40.41#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.08:08:40.41#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:40.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:40.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:40.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:40.41#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:08:40.41#ibcon#first serial, iclass 27, count 0 2006.211.08:08:40.41#ibcon#enter sib2, iclass 27, count 0 2006.211.08:08:40.41#ibcon#flushed, iclass 27, count 0 2006.211.08:08:40.41#ibcon#about to write, iclass 27, count 0 2006.211.08:08:40.41#ibcon#wrote, iclass 27, count 0 2006.211.08:08:40.41#ibcon#about to read 3, iclass 27, count 0 2006.211.08:08:40.43#ibcon#read 3, iclass 27, count 0 2006.211.08:08:40.43#ibcon#about to read 4, iclass 27, count 0 2006.211.08:08:40.43#ibcon#read 4, iclass 27, count 0 2006.211.08:08:40.43#ibcon#about to read 5, iclass 27, count 0 2006.211.08:08:40.43#ibcon#read 5, iclass 27, count 0 2006.211.08:08:40.43#ibcon#about to read 6, iclass 27, count 0 2006.211.08:08:40.43#ibcon#read 6, iclass 27, count 0 2006.211.08:08:40.43#ibcon#end of sib2, iclass 27, count 0 2006.211.08:08:40.43#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:08:40.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:08:40.43#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:08:40.43#ibcon#*before write, iclass 27, count 0 2006.211.08:08:40.43#ibcon#enter sib2, iclass 27, count 0 2006.211.08:08:40.43#ibcon#flushed, iclass 27, count 0 2006.211.08:08:40.43#ibcon#about to write, iclass 27, count 0 2006.211.08:08:40.43#ibcon#wrote, iclass 27, count 0 2006.211.08:08:40.43#ibcon#about to read 3, iclass 27, count 0 2006.211.08:08:40.47#ibcon#read 3, iclass 27, count 0 2006.211.08:08:40.47#ibcon#about to read 4, iclass 27, count 0 2006.211.08:08:40.47#ibcon#read 4, iclass 27, count 0 2006.211.08:08:40.47#ibcon#about to read 5, iclass 27, count 0 2006.211.08:08:40.47#ibcon#read 5, iclass 27, count 0 2006.211.08:08:40.47#ibcon#about to read 6, iclass 27, count 0 2006.211.08:08:40.47#ibcon#read 6, iclass 27, count 0 2006.211.08:08:40.47#ibcon#end of sib2, iclass 27, count 0 2006.211.08:08:40.47#ibcon#*after write, iclass 27, count 0 2006.211.08:08:40.47#ibcon#*before return 0, iclass 27, count 0 2006.211.08:08:40.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:40.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:08:40.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:08:40.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:08:40.47$vc4f8/vb=2,4 2006.211.08:08:40.47#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.08:08:40.47#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.08:08:40.47#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:40.47#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:40.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:40.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:40.53#ibcon#enter wrdev, iclass 29, count 2 2006.211.08:08:40.53#ibcon#first serial, iclass 29, count 2 2006.211.08:08:40.53#ibcon#enter sib2, iclass 29, count 2 2006.211.08:08:40.53#ibcon#flushed, iclass 29, count 2 2006.211.08:08:40.53#ibcon#about to write, iclass 29, count 2 2006.211.08:08:40.53#ibcon#wrote, iclass 29, count 2 2006.211.08:08:40.53#ibcon#about to read 3, iclass 29, count 2 2006.211.08:08:40.55#ibcon#read 3, iclass 29, count 2 2006.211.08:08:40.55#ibcon#about to read 4, iclass 29, count 2 2006.211.08:08:40.55#ibcon#read 4, iclass 29, count 2 2006.211.08:08:40.55#ibcon#about to read 5, iclass 29, count 2 2006.211.08:08:40.55#ibcon#read 5, iclass 29, count 2 2006.211.08:08:40.55#ibcon#about to read 6, iclass 29, count 2 2006.211.08:08:40.55#ibcon#read 6, iclass 29, count 2 2006.211.08:08:40.55#ibcon#end of sib2, iclass 29, count 2 2006.211.08:08:40.55#ibcon#*mode == 0, iclass 29, count 2 2006.211.08:08:40.55#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.08:08:40.55#ibcon#[27=AT02-04\r\n] 2006.211.08:08:40.55#ibcon#*before write, iclass 29, count 2 2006.211.08:08:40.55#ibcon#enter sib2, iclass 29, count 2 2006.211.08:08:40.55#ibcon#flushed, iclass 29, count 2 2006.211.08:08:40.55#ibcon#about to write, iclass 29, count 2 2006.211.08:08:40.55#ibcon#wrote, iclass 29, count 2 2006.211.08:08:40.55#ibcon#about to read 3, iclass 29, count 2 2006.211.08:08:40.58#ibcon#read 3, iclass 29, count 2 2006.211.08:08:40.58#ibcon#about to read 4, iclass 29, count 2 2006.211.08:08:40.58#ibcon#read 4, iclass 29, count 2 2006.211.08:08:40.58#ibcon#about to read 5, iclass 29, count 2 2006.211.08:08:40.58#ibcon#read 5, iclass 29, count 2 2006.211.08:08:40.58#ibcon#about to read 6, iclass 29, count 2 2006.211.08:08:40.58#ibcon#read 6, iclass 29, count 2 2006.211.08:08:40.58#ibcon#end of sib2, iclass 29, count 2 2006.211.08:08:40.58#ibcon#*after write, iclass 29, count 2 2006.211.08:08:40.58#ibcon#*before return 0, iclass 29, count 2 2006.211.08:08:40.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:40.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:08:40.58#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.08:08:40.58#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:40.58#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:40.70#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:40.70#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:40.70#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:08:40.70#ibcon#first serial, iclass 29, count 0 2006.211.08:08:40.70#ibcon#enter sib2, iclass 29, count 0 2006.211.08:08:40.70#ibcon#flushed, iclass 29, count 0 2006.211.08:08:40.70#ibcon#about to write, iclass 29, count 0 2006.211.08:08:40.70#ibcon#wrote, iclass 29, count 0 2006.211.08:08:40.70#ibcon#about to read 3, iclass 29, count 0 2006.211.08:08:40.72#ibcon#read 3, iclass 29, count 0 2006.211.08:08:40.72#ibcon#about to read 4, iclass 29, count 0 2006.211.08:08:40.72#ibcon#read 4, iclass 29, count 0 2006.211.08:08:40.72#ibcon#about to read 5, iclass 29, count 0 2006.211.08:08:40.72#ibcon#read 5, iclass 29, count 0 2006.211.08:08:40.72#ibcon#about to read 6, iclass 29, count 0 2006.211.08:08:40.72#ibcon#read 6, iclass 29, count 0 2006.211.08:08:40.72#ibcon#end of sib2, iclass 29, count 0 2006.211.08:08:40.72#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:08:40.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:08:40.72#ibcon#[27=USB\r\n] 2006.211.08:08:40.72#ibcon#*before write, iclass 29, count 0 2006.211.08:08:40.72#ibcon#enter sib2, iclass 29, count 0 2006.211.08:08:40.72#ibcon#flushed, iclass 29, count 0 2006.211.08:08:40.72#ibcon#about to write, iclass 29, count 0 2006.211.08:08:40.72#ibcon#wrote, iclass 29, count 0 2006.211.08:08:40.72#ibcon#about to read 3, iclass 29, count 0 2006.211.08:08:40.75#ibcon#read 3, iclass 29, count 0 2006.211.08:08:40.75#ibcon#about to read 4, iclass 29, count 0 2006.211.08:08:40.75#ibcon#read 4, iclass 29, count 0 2006.211.08:08:40.75#ibcon#about to read 5, iclass 29, count 0 2006.211.08:08:40.75#ibcon#read 5, iclass 29, count 0 2006.211.08:08:40.75#ibcon#about to read 6, iclass 29, count 0 2006.211.08:08:40.75#ibcon#read 6, iclass 29, count 0 2006.211.08:08:40.75#ibcon#end of sib2, iclass 29, count 0 2006.211.08:08:40.75#ibcon#*after write, iclass 29, count 0 2006.211.08:08:40.75#ibcon#*before return 0, iclass 29, count 0 2006.211.08:08:40.75#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:40.75#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:08:40.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:08:40.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:08:40.75$vc4f8/vblo=3,656.99 2006.211.08:08:40.75#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.08:08:40.75#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.08:08:40.75#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:40.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:40.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:40.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:40.75#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:08:40.75#ibcon#first serial, iclass 31, count 0 2006.211.08:08:40.75#ibcon#enter sib2, iclass 31, count 0 2006.211.08:08:40.75#ibcon#flushed, iclass 31, count 0 2006.211.08:08:40.75#ibcon#about to write, iclass 31, count 0 2006.211.08:08:40.75#ibcon#wrote, iclass 31, count 0 2006.211.08:08:40.75#ibcon#about to read 3, iclass 31, count 0 2006.211.08:08:40.77#ibcon#read 3, iclass 31, count 0 2006.211.08:08:40.77#ibcon#about to read 4, iclass 31, count 0 2006.211.08:08:40.77#ibcon#read 4, iclass 31, count 0 2006.211.08:08:40.77#ibcon#about to read 5, iclass 31, count 0 2006.211.08:08:40.77#ibcon#read 5, iclass 31, count 0 2006.211.08:08:40.77#ibcon#about to read 6, iclass 31, count 0 2006.211.08:08:40.77#ibcon#read 6, iclass 31, count 0 2006.211.08:08:40.77#ibcon#end of sib2, iclass 31, count 0 2006.211.08:08:40.77#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:08:40.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:08:40.77#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:08:40.77#ibcon#*before write, iclass 31, count 0 2006.211.08:08:40.77#ibcon#enter sib2, iclass 31, count 0 2006.211.08:08:40.77#ibcon#flushed, iclass 31, count 0 2006.211.08:08:40.77#ibcon#about to write, iclass 31, count 0 2006.211.08:08:40.77#ibcon#wrote, iclass 31, count 0 2006.211.08:08:40.77#ibcon#about to read 3, iclass 31, count 0 2006.211.08:08:40.81#ibcon#read 3, iclass 31, count 0 2006.211.08:08:40.81#ibcon#about to read 4, iclass 31, count 0 2006.211.08:08:40.81#ibcon#read 4, iclass 31, count 0 2006.211.08:08:40.81#ibcon#about to read 5, iclass 31, count 0 2006.211.08:08:40.81#ibcon#read 5, iclass 31, count 0 2006.211.08:08:40.81#ibcon#about to read 6, iclass 31, count 0 2006.211.08:08:40.81#ibcon#read 6, iclass 31, count 0 2006.211.08:08:40.81#ibcon#end of sib2, iclass 31, count 0 2006.211.08:08:40.81#ibcon#*after write, iclass 31, count 0 2006.211.08:08:40.81#ibcon#*before return 0, iclass 31, count 0 2006.211.08:08:40.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:40.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:08:40.81#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:08:40.81#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:08:40.81$vc4f8/vb=3,3 2006.211.08:08:40.81#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.08:08:40.81#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.08:08:40.81#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:40.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:40.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:40.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:40.87#ibcon#enter wrdev, iclass 33, count 2 2006.211.08:08:40.87#ibcon#first serial, iclass 33, count 2 2006.211.08:08:40.87#ibcon#enter sib2, iclass 33, count 2 2006.211.08:08:40.87#ibcon#flushed, iclass 33, count 2 2006.211.08:08:40.87#ibcon#about to write, iclass 33, count 2 2006.211.08:08:40.87#ibcon#wrote, iclass 33, count 2 2006.211.08:08:40.87#ibcon#about to read 3, iclass 33, count 2 2006.211.08:08:40.89#ibcon#read 3, iclass 33, count 2 2006.211.08:08:40.89#ibcon#about to read 4, iclass 33, count 2 2006.211.08:08:40.89#ibcon#read 4, iclass 33, count 2 2006.211.08:08:40.89#ibcon#about to read 5, iclass 33, count 2 2006.211.08:08:40.89#ibcon#read 5, iclass 33, count 2 2006.211.08:08:40.89#ibcon#about to read 6, iclass 33, count 2 2006.211.08:08:40.89#ibcon#read 6, iclass 33, count 2 2006.211.08:08:40.89#ibcon#end of sib2, iclass 33, count 2 2006.211.08:08:40.89#ibcon#*mode == 0, iclass 33, count 2 2006.211.08:08:40.89#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.08:08:40.89#ibcon#[27=AT03-03\r\n] 2006.211.08:08:40.89#ibcon#*before write, iclass 33, count 2 2006.211.08:08:40.89#ibcon#enter sib2, iclass 33, count 2 2006.211.08:08:40.89#ibcon#flushed, iclass 33, count 2 2006.211.08:08:40.89#ibcon#about to write, iclass 33, count 2 2006.211.08:08:40.89#ibcon#wrote, iclass 33, count 2 2006.211.08:08:40.89#ibcon#about to read 3, iclass 33, count 2 2006.211.08:08:40.92#ibcon#read 3, iclass 33, count 2 2006.211.08:08:40.92#ibcon#about to read 4, iclass 33, count 2 2006.211.08:08:40.92#ibcon#read 4, iclass 33, count 2 2006.211.08:08:40.92#ibcon#about to read 5, iclass 33, count 2 2006.211.08:08:40.92#ibcon#read 5, iclass 33, count 2 2006.211.08:08:40.92#ibcon#about to read 6, iclass 33, count 2 2006.211.08:08:40.92#ibcon#read 6, iclass 33, count 2 2006.211.08:08:40.92#ibcon#end of sib2, iclass 33, count 2 2006.211.08:08:40.92#ibcon#*after write, iclass 33, count 2 2006.211.08:08:40.92#ibcon#*before return 0, iclass 33, count 2 2006.211.08:08:40.92#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:40.92#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:08:40.92#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.08:08:40.92#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:40.92#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:41.04#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:41.04#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:41.04#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:08:41.04#ibcon#first serial, iclass 33, count 0 2006.211.08:08:41.04#ibcon#enter sib2, iclass 33, count 0 2006.211.08:08:41.04#ibcon#flushed, iclass 33, count 0 2006.211.08:08:41.04#ibcon#about to write, iclass 33, count 0 2006.211.08:08:41.04#ibcon#wrote, iclass 33, count 0 2006.211.08:08:41.04#ibcon#about to read 3, iclass 33, count 0 2006.211.08:08:41.06#ibcon#read 3, iclass 33, count 0 2006.211.08:08:41.06#ibcon#about to read 4, iclass 33, count 0 2006.211.08:08:41.06#ibcon#read 4, iclass 33, count 0 2006.211.08:08:41.06#ibcon#about to read 5, iclass 33, count 0 2006.211.08:08:41.06#ibcon#read 5, iclass 33, count 0 2006.211.08:08:41.06#ibcon#about to read 6, iclass 33, count 0 2006.211.08:08:41.06#ibcon#read 6, iclass 33, count 0 2006.211.08:08:41.06#ibcon#end of sib2, iclass 33, count 0 2006.211.08:08:41.06#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:08:41.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:08:41.06#ibcon#[27=USB\r\n] 2006.211.08:08:41.06#ibcon#*before write, iclass 33, count 0 2006.211.08:08:41.06#ibcon#enter sib2, iclass 33, count 0 2006.211.08:08:41.06#ibcon#flushed, iclass 33, count 0 2006.211.08:08:41.06#ibcon#about to write, iclass 33, count 0 2006.211.08:08:41.06#ibcon#wrote, iclass 33, count 0 2006.211.08:08:41.06#ibcon#about to read 3, iclass 33, count 0 2006.211.08:08:41.09#ibcon#read 3, iclass 33, count 0 2006.211.08:08:41.09#ibcon#about to read 4, iclass 33, count 0 2006.211.08:08:41.09#ibcon#read 4, iclass 33, count 0 2006.211.08:08:41.09#ibcon#about to read 5, iclass 33, count 0 2006.211.08:08:41.09#ibcon#read 5, iclass 33, count 0 2006.211.08:08:41.09#ibcon#about to read 6, iclass 33, count 0 2006.211.08:08:41.09#ibcon#read 6, iclass 33, count 0 2006.211.08:08:41.09#ibcon#end of sib2, iclass 33, count 0 2006.211.08:08:41.09#ibcon#*after write, iclass 33, count 0 2006.211.08:08:41.09#ibcon#*before return 0, iclass 33, count 0 2006.211.08:08:41.09#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:41.09#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:08:41.09#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:08:41.09#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:08:41.09$vc4f8/vblo=4,712.99 2006.211.08:08:41.09#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.08:08:41.09#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.08:08:41.09#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:41.09#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:41.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:41.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:41.09#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:08:41.09#ibcon#first serial, iclass 35, count 0 2006.211.08:08:41.09#ibcon#enter sib2, iclass 35, count 0 2006.211.08:08:41.09#ibcon#flushed, iclass 35, count 0 2006.211.08:08:41.09#ibcon#about to write, iclass 35, count 0 2006.211.08:08:41.09#ibcon#wrote, iclass 35, count 0 2006.211.08:08:41.09#ibcon#about to read 3, iclass 35, count 0 2006.211.08:08:41.11#ibcon#read 3, iclass 35, count 0 2006.211.08:08:41.11#ibcon#about to read 4, iclass 35, count 0 2006.211.08:08:41.11#ibcon#read 4, iclass 35, count 0 2006.211.08:08:41.11#ibcon#about to read 5, iclass 35, count 0 2006.211.08:08:41.11#ibcon#read 5, iclass 35, count 0 2006.211.08:08:41.11#ibcon#about to read 6, iclass 35, count 0 2006.211.08:08:41.11#ibcon#read 6, iclass 35, count 0 2006.211.08:08:41.11#ibcon#end of sib2, iclass 35, count 0 2006.211.08:08:41.11#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:08:41.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:08:41.11#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:08:41.11#ibcon#*before write, iclass 35, count 0 2006.211.08:08:41.11#ibcon#enter sib2, iclass 35, count 0 2006.211.08:08:41.11#ibcon#flushed, iclass 35, count 0 2006.211.08:08:41.11#ibcon#about to write, iclass 35, count 0 2006.211.08:08:41.11#ibcon#wrote, iclass 35, count 0 2006.211.08:08:41.11#ibcon#about to read 3, iclass 35, count 0 2006.211.08:08:41.15#ibcon#read 3, iclass 35, count 0 2006.211.08:08:41.15#ibcon#about to read 4, iclass 35, count 0 2006.211.08:08:41.15#ibcon#read 4, iclass 35, count 0 2006.211.08:08:41.15#ibcon#about to read 5, iclass 35, count 0 2006.211.08:08:41.15#ibcon#read 5, iclass 35, count 0 2006.211.08:08:41.15#ibcon#about to read 6, iclass 35, count 0 2006.211.08:08:41.15#ibcon#read 6, iclass 35, count 0 2006.211.08:08:41.15#ibcon#end of sib2, iclass 35, count 0 2006.211.08:08:41.15#ibcon#*after write, iclass 35, count 0 2006.211.08:08:41.15#ibcon#*before return 0, iclass 35, count 0 2006.211.08:08:41.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:41.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:08:41.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:08:41.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:08:41.15$vc4f8/vb=4,3 2006.211.08:08:41.15#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.08:08:41.15#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.08:08:41.15#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:41.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:41.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:41.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:41.21#ibcon#enter wrdev, iclass 37, count 2 2006.211.08:08:41.21#ibcon#first serial, iclass 37, count 2 2006.211.08:08:41.21#ibcon#enter sib2, iclass 37, count 2 2006.211.08:08:41.21#ibcon#flushed, iclass 37, count 2 2006.211.08:08:41.21#ibcon#about to write, iclass 37, count 2 2006.211.08:08:41.21#ibcon#wrote, iclass 37, count 2 2006.211.08:08:41.21#ibcon#about to read 3, iclass 37, count 2 2006.211.08:08:41.23#ibcon#read 3, iclass 37, count 2 2006.211.08:08:41.23#ibcon#about to read 4, iclass 37, count 2 2006.211.08:08:41.23#ibcon#read 4, iclass 37, count 2 2006.211.08:08:41.23#ibcon#about to read 5, iclass 37, count 2 2006.211.08:08:41.23#ibcon#read 5, iclass 37, count 2 2006.211.08:08:41.23#ibcon#about to read 6, iclass 37, count 2 2006.211.08:08:41.23#ibcon#read 6, iclass 37, count 2 2006.211.08:08:41.23#ibcon#end of sib2, iclass 37, count 2 2006.211.08:08:41.23#ibcon#*mode == 0, iclass 37, count 2 2006.211.08:08:41.23#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.08:08:41.23#ibcon#[27=AT04-03\r\n] 2006.211.08:08:41.23#ibcon#*before write, iclass 37, count 2 2006.211.08:08:41.23#ibcon#enter sib2, iclass 37, count 2 2006.211.08:08:41.23#ibcon#flushed, iclass 37, count 2 2006.211.08:08:41.23#ibcon#about to write, iclass 37, count 2 2006.211.08:08:41.23#ibcon#wrote, iclass 37, count 2 2006.211.08:08:41.23#ibcon#about to read 3, iclass 37, count 2 2006.211.08:08:41.26#ibcon#read 3, iclass 37, count 2 2006.211.08:08:41.26#ibcon#about to read 4, iclass 37, count 2 2006.211.08:08:41.26#ibcon#read 4, iclass 37, count 2 2006.211.08:08:41.26#ibcon#about to read 5, iclass 37, count 2 2006.211.08:08:41.26#ibcon#read 5, iclass 37, count 2 2006.211.08:08:41.26#ibcon#about to read 6, iclass 37, count 2 2006.211.08:08:41.26#ibcon#read 6, iclass 37, count 2 2006.211.08:08:41.26#ibcon#end of sib2, iclass 37, count 2 2006.211.08:08:41.26#ibcon#*after write, iclass 37, count 2 2006.211.08:08:41.26#ibcon#*before return 0, iclass 37, count 2 2006.211.08:08:41.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:41.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:08:41.26#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.08:08:41.26#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:41.26#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:41.38#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:41.38#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:41.38#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:08:41.38#ibcon#first serial, iclass 37, count 0 2006.211.08:08:41.38#ibcon#enter sib2, iclass 37, count 0 2006.211.08:08:41.38#ibcon#flushed, iclass 37, count 0 2006.211.08:08:41.38#ibcon#about to write, iclass 37, count 0 2006.211.08:08:41.38#ibcon#wrote, iclass 37, count 0 2006.211.08:08:41.38#ibcon#about to read 3, iclass 37, count 0 2006.211.08:08:41.40#ibcon#read 3, iclass 37, count 0 2006.211.08:08:41.40#ibcon#about to read 4, iclass 37, count 0 2006.211.08:08:41.40#ibcon#read 4, iclass 37, count 0 2006.211.08:08:41.40#ibcon#about to read 5, iclass 37, count 0 2006.211.08:08:41.40#ibcon#read 5, iclass 37, count 0 2006.211.08:08:41.40#ibcon#about to read 6, iclass 37, count 0 2006.211.08:08:41.40#ibcon#read 6, iclass 37, count 0 2006.211.08:08:41.40#ibcon#end of sib2, iclass 37, count 0 2006.211.08:08:41.40#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:08:41.40#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:08:41.40#ibcon#[27=USB\r\n] 2006.211.08:08:41.40#ibcon#*before write, iclass 37, count 0 2006.211.08:08:41.40#ibcon#enter sib2, iclass 37, count 0 2006.211.08:08:41.40#ibcon#flushed, iclass 37, count 0 2006.211.08:08:41.40#ibcon#about to write, iclass 37, count 0 2006.211.08:08:41.40#ibcon#wrote, iclass 37, count 0 2006.211.08:08:41.40#ibcon#about to read 3, iclass 37, count 0 2006.211.08:08:41.43#ibcon#read 3, iclass 37, count 0 2006.211.08:08:41.43#ibcon#about to read 4, iclass 37, count 0 2006.211.08:08:41.43#ibcon#read 4, iclass 37, count 0 2006.211.08:08:41.43#ibcon#about to read 5, iclass 37, count 0 2006.211.08:08:41.43#ibcon#read 5, iclass 37, count 0 2006.211.08:08:41.43#ibcon#about to read 6, iclass 37, count 0 2006.211.08:08:41.43#ibcon#read 6, iclass 37, count 0 2006.211.08:08:41.43#ibcon#end of sib2, iclass 37, count 0 2006.211.08:08:41.43#ibcon#*after write, iclass 37, count 0 2006.211.08:08:41.43#ibcon#*before return 0, iclass 37, count 0 2006.211.08:08:41.43#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:41.43#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:08:41.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:08:41.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:08:41.43$vc4f8/vblo=5,744.99 2006.211.08:08:41.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.08:08:41.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.08:08:41.43#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:41.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:41.43#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:41.43#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:41.43#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:08:41.43#ibcon#first serial, iclass 39, count 0 2006.211.08:08:41.43#ibcon#enter sib2, iclass 39, count 0 2006.211.08:08:41.43#ibcon#flushed, iclass 39, count 0 2006.211.08:08:41.43#ibcon#about to write, iclass 39, count 0 2006.211.08:08:41.43#ibcon#wrote, iclass 39, count 0 2006.211.08:08:41.43#ibcon#about to read 3, iclass 39, count 0 2006.211.08:08:41.45#ibcon#read 3, iclass 39, count 0 2006.211.08:08:41.45#ibcon#about to read 4, iclass 39, count 0 2006.211.08:08:41.45#ibcon#read 4, iclass 39, count 0 2006.211.08:08:41.45#ibcon#about to read 5, iclass 39, count 0 2006.211.08:08:41.45#ibcon#read 5, iclass 39, count 0 2006.211.08:08:41.45#ibcon#about to read 6, iclass 39, count 0 2006.211.08:08:41.45#ibcon#read 6, iclass 39, count 0 2006.211.08:08:41.45#ibcon#end of sib2, iclass 39, count 0 2006.211.08:08:41.45#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:08:41.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:08:41.45#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:08:41.45#ibcon#*before write, iclass 39, count 0 2006.211.08:08:41.45#ibcon#enter sib2, iclass 39, count 0 2006.211.08:08:41.45#ibcon#flushed, iclass 39, count 0 2006.211.08:08:41.45#ibcon#about to write, iclass 39, count 0 2006.211.08:08:41.45#ibcon#wrote, iclass 39, count 0 2006.211.08:08:41.45#ibcon#about to read 3, iclass 39, count 0 2006.211.08:08:41.49#ibcon#read 3, iclass 39, count 0 2006.211.08:08:41.49#ibcon#about to read 4, iclass 39, count 0 2006.211.08:08:41.49#ibcon#read 4, iclass 39, count 0 2006.211.08:08:41.49#ibcon#about to read 5, iclass 39, count 0 2006.211.08:08:41.49#ibcon#read 5, iclass 39, count 0 2006.211.08:08:41.49#ibcon#about to read 6, iclass 39, count 0 2006.211.08:08:41.49#ibcon#read 6, iclass 39, count 0 2006.211.08:08:41.49#ibcon#end of sib2, iclass 39, count 0 2006.211.08:08:41.49#ibcon#*after write, iclass 39, count 0 2006.211.08:08:41.49#ibcon#*before return 0, iclass 39, count 0 2006.211.08:08:41.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:41.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:08:41.49#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:08:41.49#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:08:41.49$vc4f8/vb=5,3 2006.211.08:08:41.49#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.08:08:41.49#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.08:08:41.49#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:41.49#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:41.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:41.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:41.55#ibcon#enter wrdev, iclass 3, count 2 2006.211.08:08:41.55#ibcon#first serial, iclass 3, count 2 2006.211.08:08:41.55#ibcon#enter sib2, iclass 3, count 2 2006.211.08:08:41.55#ibcon#flushed, iclass 3, count 2 2006.211.08:08:41.55#ibcon#about to write, iclass 3, count 2 2006.211.08:08:41.55#ibcon#wrote, iclass 3, count 2 2006.211.08:08:41.55#ibcon#about to read 3, iclass 3, count 2 2006.211.08:08:41.57#ibcon#read 3, iclass 3, count 2 2006.211.08:08:41.57#ibcon#about to read 4, iclass 3, count 2 2006.211.08:08:41.57#ibcon#read 4, iclass 3, count 2 2006.211.08:08:41.57#ibcon#about to read 5, iclass 3, count 2 2006.211.08:08:41.57#ibcon#read 5, iclass 3, count 2 2006.211.08:08:41.57#ibcon#about to read 6, iclass 3, count 2 2006.211.08:08:41.57#ibcon#read 6, iclass 3, count 2 2006.211.08:08:41.57#ibcon#end of sib2, iclass 3, count 2 2006.211.08:08:41.57#ibcon#*mode == 0, iclass 3, count 2 2006.211.08:08:41.57#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.08:08:41.57#ibcon#[27=AT05-03\r\n] 2006.211.08:08:41.57#ibcon#*before write, iclass 3, count 2 2006.211.08:08:41.57#ibcon#enter sib2, iclass 3, count 2 2006.211.08:08:41.57#ibcon#flushed, iclass 3, count 2 2006.211.08:08:41.57#ibcon#about to write, iclass 3, count 2 2006.211.08:08:41.57#ibcon#wrote, iclass 3, count 2 2006.211.08:08:41.57#ibcon#about to read 3, iclass 3, count 2 2006.211.08:08:41.60#ibcon#read 3, iclass 3, count 2 2006.211.08:08:41.60#ibcon#about to read 4, iclass 3, count 2 2006.211.08:08:41.60#ibcon#read 4, iclass 3, count 2 2006.211.08:08:41.60#ibcon#about to read 5, iclass 3, count 2 2006.211.08:08:41.60#ibcon#read 5, iclass 3, count 2 2006.211.08:08:41.60#ibcon#about to read 6, iclass 3, count 2 2006.211.08:08:41.60#ibcon#read 6, iclass 3, count 2 2006.211.08:08:41.60#ibcon#end of sib2, iclass 3, count 2 2006.211.08:08:41.60#ibcon#*after write, iclass 3, count 2 2006.211.08:08:41.60#ibcon#*before return 0, iclass 3, count 2 2006.211.08:08:41.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:41.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:08:41.60#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.08:08:41.60#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:41.60#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:41.72#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:41.72#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:41.72#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:08:41.72#ibcon#first serial, iclass 3, count 0 2006.211.08:08:41.72#ibcon#enter sib2, iclass 3, count 0 2006.211.08:08:41.72#ibcon#flushed, iclass 3, count 0 2006.211.08:08:41.72#ibcon#about to write, iclass 3, count 0 2006.211.08:08:41.72#ibcon#wrote, iclass 3, count 0 2006.211.08:08:41.72#ibcon#about to read 3, iclass 3, count 0 2006.211.08:08:41.74#ibcon#read 3, iclass 3, count 0 2006.211.08:08:41.74#ibcon#about to read 4, iclass 3, count 0 2006.211.08:08:41.74#ibcon#read 4, iclass 3, count 0 2006.211.08:08:41.74#ibcon#about to read 5, iclass 3, count 0 2006.211.08:08:41.74#ibcon#read 5, iclass 3, count 0 2006.211.08:08:41.74#ibcon#about to read 6, iclass 3, count 0 2006.211.08:08:41.74#ibcon#read 6, iclass 3, count 0 2006.211.08:08:41.74#ibcon#end of sib2, iclass 3, count 0 2006.211.08:08:41.74#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:08:41.74#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:08:41.74#ibcon#[27=USB\r\n] 2006.211.08:08:41.74#ibcon#*before write, iclass 3, count 0 2006.211.08:08:41.74#ibcon#enter sib2, iclass 3, count 0 2006.211.08:08:41.74#ibcon#flushed, iclass 3, count 0 2006.211.08:08:41.74#ibcon#about to write, iclass 3, count 0 2006.211.08:08:41.74#ibcon#wrote, iclass 3, count 0 2006.211.08:08:41.74#ibcon#about to read 3, iclass 3, count 0 2006.211.08:08:41.77#ibcon#read 3, iclass 3, count 0 2006.211.08:08:41.77#ibcon#about to read 4, iclass 3, count 0 2006.211.08:08:41.77#ibcon#read 4, iclass 3, count 0 2006.211.08:08:41.77#ibcon#about to read 5, iclass 3, count 0 2006.211.08:08:41.77#ibcon#read 5, iclass 3, count 0 2006.211.08:08:41.77#ibcon#about to read 6, iclass 3, count 0 2006.211.08:08:41.77#ibcon#read 6, iclass 3, count 0 2006.211.08:08:41.77#ibcon#end of sib2, iclass 3, count 0 2006.211.08:08:41.77#ibcon#*after write, iclass 3, count 0 2006.211.08:08:41.77#ibcon#*before return 0, iclass 3, count 0 2006.211.08:08:41.77#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:41.77#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:08:41.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:08:41.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:08:41.77$vc4f8/vblo=6,752.99 2006.211.08:08:41.77#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.08:08:41.77#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.08:08:41.77#ibcon#ireg 17 cls_cnt 0 2006.211.08:08:41.77#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:41.77#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:41.77#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:41.77#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:08:41.77#ibcon#first serial, iclass 5, count 0 2006.211.08:08:41.77#ibcon#enter sib2, iclass 5, count 0 2006.211.08:08:41.77#ibcon#flushed, iclass 5, count 0 2006.211.08:08:41.77#ibcon#about to write, iclass 5, count 0 2006.211.08:08:41.77#ibcon#wrote, iclass 5, count 0 2006.211.08:08:41.77#ibcon#about to read 3, iclass 5, count 0 2006.211.08:08:41.79#ibcon#read 3, iclass 5, count 0 2006.211.08:08:41.79#ibcon#about to read 4, iclass 5, count 0 2006.211.08:08:41.79#ibcon#read 4, iclass 5, count 0 2006.211.08:08:41.79#ibcon#about to read 5, iclass 5, count 0 2006.211.08:08:41.79#ibcon#read 5, iclass 5, count 0 2006.211.08:08:41.79#ibcon#about to read 6, iclass 5, count 0 2006.211.08:08:41.79#ibcon#read 6, iclass 5, count 0 2006.211.08:08:41.79#ibcon#end of sib2, iclass 5, count 0 2006.211.08:08:41.79#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:08:41.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:08:41.79#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:08:41.79#ibcon#*before write, iclass 5, count 0 2006.211.08:08:41.79#ibcon#enter sib2, iclass 5, count 0 2006.211.08:08:41.79#ibcon#flushed, iclass 5, count 0 2006.211.08:08:41.79#ibcon#about to write, iclass 5, count 0 2006.211.08:08:41.79#ibcon#wrote, iclass 5, count 0 2006.211.08:08:41.79#ibcon#about to read 3, iclass 5, count 0 2006.211.08:08:41.83#ibcon#read 3, iclass 5, count 0 2006.211.08:08:41.83#ibcon#about to read 4, iclass 5, count 0 2006.211.08:08:41.83#ibcon#read 4, iclass 5, count 0 2006.211.08:08:41.83#ibcon#about to read 5, iclass 5, count 0 2006.211.08:08:41.83#ibcon#read 5, iclass 5, count 0 2006.211.08:08:41.83#ibcon#about to read 6, iclass 5, count 0 2006.211.08:08:41.83#ibcon#read 6, iclass 5, count 0 2006.211.08:08:41.83#ibcon#end of sib2, iclass 5, count 0 2006.211.08:08:41.83#ibcon#*after write, iclass 5, count 0 2006.211.08:08:41.83#ibcon#*before return 0, iclass 5, count 0 2006.211.08:08:41.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:41.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:08:41.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:08:41.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:08:41.83$vc4f8/vb=6,3 2006.211.08:08:41.83#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.08:08:41.83#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.08:08:41.83#ibcon#ireg 11 cls_cnt 2 2006.211.08:08:41.83#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:41.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:41.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:41.89#ibcon#enter wrdev, iclass 7, count 2 2006.211.08:08:41.89#ibcon#first serial, iclass 7, count 2 2006.211.08:08:41.89#ibcon#enter sib2, iclass 7, count 2 2006.211.08:08:41.89#ibcon#flushed, iclass 7, count 2 2006.211.08:08:41.89#ibcon#about to write, iclass 7, count 2 2006.211.08:08:41.89#ibcon#wrote, iclass 7, count 2 2006.211.08:08:41.89#ibcon#about to read 3, iclass 7, count 2 2006.211.08:08:41.91#ibcon#read 3, iclass 7, count 2 2006.211.08:08:41.91#ibcon#about to read 4, iclass 7, count 2 2006.211.08:08:41.91#ibcon#read 4, iclass 7, count 2 2006.211.08:08:41.91#ibcon#about to read 5, iclass 7, count 2 2006.211.08:08:41.91#ibcon#read 5, iclass 7, count 2 2006.211.08:08:41.91#ibcon#about to read 6, iclass 7, count 2 2006.211.08:08:41.91#ibcon#read 6, iclass 7, count 2 2006.211.08:08:41.91#ibcon#end of sib2, iclass 7, count 2 2006.211.08:08:41.91#ibcon#*mode == 0, iclass 7, count 2 2006.211.08:08:41.91#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.08:08:41.91#ibcon#[27=AT06-03\r\n] 2006.211.08:08:41.91#ibcon#*before write, iclass 7, count 2 2006.211.08:08:41.91#ibcon#enter sib2, iclass 7, count 2 2006.211.08:08:41.91#ibcon#flushed, iclass 7, count 2 2006.211.08:08:41.91#ibcon#about to write, iclass 7, count 2 2006.211.08:08:41.91#ibcon#wrote, iclass 7, count 2 2006.211.08:08:41.91#ibcon#about to read 3, iclass 7, count 2 2006.211.08:08:41.94#ibcon#read 3, iclass 7, count 2 2006.211.08:08:41.94#ibcon#about to read 4, iclass 7, count 2 2006.211.08:08:41.94#ibcon#read 4, iclass 7, count 2 2006.211.08:08:41.94#ibcon#about to read 5, iclass 7, count 2 2006.211.08:08:41.94#ibcon#read 5, iclass 7, count 2 2006.211.08:08:41.94#ibcon#about to read 6, iclass 7, count 2 2006.211.08:08:41.94#ibcon#read 6, iclass 7, count 2 2006.211.08:08:41.94#ibcon#end of sib2, iclass 7, count 2 2006.211.08:08:41.94#ibcon#*after write, iclass 7, count 2 2006.211.08:08:41.94#ibcon#*before return 0, iclass 7, count 2 2006.211.08:08:41.94#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:41.94#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:08:41.94#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.08:08:41.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:08:41.94#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:42.06#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:42.06#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:42.06#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:08:42.06#ibcon#first serial, iclass 7, count 0 2006.211.08:08:42.06#ibcon#enter sib2, iclass 7, count 0 2006.211.08:08:42.06#ibcon#flushed, iclass 7, count 0 2006.211.08:08:42.06#ibcon#about to write, iclass 7, count 0 2006.211.08:08:42.06#ibcon#wrote, iclass 7, count 0 2006.211.08:08:42.06#ibcon#about to read 3, iclass 7, count 0 2006.211.08:08:42.08#ibcon#read 3, iclass 7, count 0 2006.211.08:08:42.08#ibcon#about to read 4, iclass 7, count 0 2006.211.08:08:42.08#ibcon#read 4, iclass 7, count 0 2006.211.08:08:42.08#ibcon#about to read 5, iclass 7, count 0 2006.211.08:08:42.08#ibcon#read 5, iclass 7, count 0 2006.211.08:08:42.08#ibcon#about to read 6, iclass 7, count 0 2006.211.08:08:42.08#ibcon#read 6, iclass 7, count 0 2006.211.08:08:42.08#ibcon#end of sib2, iclass 7, count 0 2006.211.08:08:42.08#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:08:42.08#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:08:42.08#ibcon#[27=USB\r\n] 2006.211.08:08:42.08#ibcon#*before write, iclass 7, count 0 2006.211.08:08:42.08#ibcon#enter sib2, iclass 7, count 0 2006.211.08:08:42.08#ibcon#flushed, iclass 7, count 0 2006.211.08:08:42.08#ibcon#about to write, iclass 7, count 0 2006.211.08:08:42.08#ibcon#wrote, iclass 7, count 0 2006.211.08:08:42.08#ibcon#about to read 3, iclass 7, count 0 2006.211.08:08:42.11#ibcon#read 3, iclass 7, count 0 2006.211.08:08:42.11#ibcon#about to read 4, iclass 7, count 0 2006.211.08:08:42.11#ibcon#read 4, iclass 7, count 0 2006.211.08:08:42.11#ibcon#about to read 5, iclass 7, count 0 2006.211.08:08:42.11#ibcon#read 5, iclass 7, count 0 2006.211.08:08:42.11#ibcon#about to read 6, iclass 7, count 0 2006.211.08:08:42.11#ibcon#read 6, iclass 7, count 0 2006.211.08:08:42.11#ibcon#end of sib2, iclass 7, count 0 2006.211.08:08:42.11#ibcon#*after write, iclass 7, count 0 2006.211.08:08:42.11#ibcon#*before return 0, iclass 7, count 0 2006.211.08:08:42.11#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:42.11#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:08:42.11#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:08:42.11#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:08:42.11$vc4f8/vabw=wide 2006.211.08:08:42.11#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.08:08:42.11#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.08:08:42.11#ibcon#ireg 8 cls_cnt 0 2006.211.08:08:42.11#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:42.11#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:42.11#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:42.11#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:08:42.11#ibcon#first serial, iclass 11, count 0 2006.211.08:08:42.11#ibcon#enter sib2, iclass 11, count 0 2006.211.08:08:42.11#ibcon#flushed, iclass 11, count 0 2006.211.08:08:42.11#ibcon#about to write, iclass 11, count 0 2006.211.08:08:42.11#ibcon#wrote, iclass 11, count 0 2006.211.08:08:42.11#ibcon#about to read 3, iclass 11, count 0 2006.211.08:08:42.13#ibcon#read 3, iclass 11, count 0 2006.211.08:08:42.13#ibcon#about to read 4, iclass 11, count 0 2006.211.08:08:42.13#ibcon#read 4, iclass 11, count 0 2006.211.08:08:42.13#ibcon#about to read 5, iclass 11, count 0 2006.211.08:08:42.13#ibcon#read 5, iclass 11, count 0 2006.211.08:08:42.13#ibcon#about to read 6, iclass 11, count 0 2006.211.08:08:42.13#ibcon#read 6, iclass 11, count 0 2006.211.08:08:42.13#ibcon#end of sib2, iclass 11, count 0 2006.211.08:08:42.13#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:08:42.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:08:42.13#ibcon#[25=BW32\r\n] 2006.211.08:08:42.13#ibcon#*before write, iclass 11, count 0 2006.211.08:08:42.13#ibcon#enter sib2, iclass 11, count 0 2006.211.08:08:42.13#ibcon#flushed, iclass 11, count 0 2006.211.08:08:42.13#ibcon#about to write, iclass 11, count 0 2006.211.08:08:42.13#ibcon#wrote, iclass 11, count 0 2006.211.08:08:42.13#ibcon#about to read 3, iclass 11, count 0 2006.211.08:08:42.16#ibcon#read 3, iclass 11, count 0 2006.211.08:08:42.16#ibcon#about to read 4, iclass 11, count 0 2006.211.08:08:42.16#ibcon#read 4, iclass 11, count 0 2006.211.08:08:42.16#ibcon#about to read 5, iclass 11, count 0 2006.211.08:08:42.16#ibcon#read 5, iclass 11, count 0 2006.211.08:08:42.16#ibcon#about to read 6, iclass 11, count 0 2006.211.08:08:42.16#ibcon#read 6, iclass 11, count 0 2006.211.08:08:42.16#ibcon#end of sib2, iclass 11, count 0 2006.211.08:08:42.16#ibcon#*after write, iclass 11, count 0 2006.211.08:08:42.16#ibcon#*before return 0, iclass 11, count 0 2006.211.08:08:42.16#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:42.16#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:08:42.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:08:42.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:08:42.16$vc4f8/vbbw=wide 2006.211.08:08:42.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:08:42.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:08:42.16#ibcon#ireg 8 cls_cnt 0 2006.211.08:08:42.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:08:42.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:08:42.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:08:42.23#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:08:42.23#ibcon#first serial, iclass 13, count 0 2006.211.08:08:42.23#ibcon#enter sib2, iclass 13, count 0 2006.211.08:08:42.23#ibcon#flushed, iclass 13, count 0 2006.211.08:08:42.23#ibcon#about to write, iclass 13, count 0 2006.211.08:08:42.23#ibcon#wrote, iclass 13, count 0 2006.211.08:08:42.23#ibcon#about to read 3, iclass 13, count 0 2006.211.08:08:42.25#ibcon#read 3, iclass 13, count 0 2006.211.08:08:42.25#ibcon#about to read 4, iclass 13, count 0 2006.211.08:08:42.25#ibcon#read 4, iclass 13, count 0 2006.211.08:08:42.25#ibcon#about to read 5, iclass 13, count 0 2006.211.08:08:42.25#ibcon#read 5, iclass 13, count 0 2006.211.08:08:42.25#ibcon#about to read 6, iclass 13, count 0 2006.211.08:08:42.25#ibcon#read 6, iclass 13, count 0 2006.211.08:08:42.25#ibcon#end of sib2, iclass 13, count 0 2006.211.08:08:42.25#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:08:42.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:08:42.25#ibcon#[27=BW32\r\n] 2006.211.08:08:42.25#ibcon#*before write, iclass 13, count 0 2006.211.08:08:42.25#ibcon#enter sib2, iclass 13, count 0 2006.211.08:08:42.25#ibcon#flushed, iclass 13, count 0 2006.211.08:08:42.25#ibcon#about to write, iclass 13, count 0 2006.211.08:08:42.25#ibcon#wrote, iclass 13, count 0 2006.211.08:08:42.25#ibcon#about to read 3, iclass 13, count 0 2006.211.08:08:42.28#ibcon#read 3, iclass 13, count 0 2006.211.08:08:42.28#ibcon#about to read 4, iclass 13, count 0 2006.211.08:08:42.28#ibcon#read 4, iclass 13, count 0 2006.211.08:08:42.28#ibcon#about to read 5, iclass 13, count 0 2006.211.08:08:42.28#ibcon#read 5, iclass 13, count 0 2006.211.08:08:42.28#ibcon#about to read 6, iclass 13, count 0 2006.211.08:08:42.28#ibcon#read 6, iclass 13, count 0 2006.211.08:08:42.28#ibcon#end of sib2, iclass 13, count 0 2006.211.08:08:42.28#ibcon#*after write, iclass 13, count 0 2006.211.08:08:42.28#ibcon#*before return 0, iclass 13, count 0 2006.211.08:08:42.28#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:08:42.28#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:08:42.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:08:42.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:08:42.28$4f8m12a/ifd4f 2006.211.08:08:42.28$ifd4f/lo= 2006.211.08:08:42.28$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:08:42.28$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:08:42.28$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:08:42.28$ifd4f/patch= 2006.211.08:08:42.28$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:08:42.28$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:08:42.29$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:08:42.29$4f8m12a/"form=m,16.000,1:2 2006.211.08:08:42.29$4f8m12a/"tpicd 2006.211.08:08:42.29$4f8m12a/echo=off 2006.211.08:08:42.29$4f8m12a/xlog=off 2006.211.08:08:42.29:!2006.211.08:09:10 2006.211.08:08:48.14#trakl#Source acquired 2006.211.08:08:49.14#flagr#flagr/antenna,acquired 2006.211.08:09:10.01:preob 2006.211.08:09:11.14/onsource/TRACKING 2006.211.08:09:11.14:!2006.211.08:09:20 2006.211.08:09:20.00:data_valid=on 2006.211.08:09:20.00:midob 2006.211.08:09:20.14/onsource/TRACKING 2006.211.08:09:20.14/wx/24.64,1010.0,78 2006.211.08:09:20.33/cable/+6.4395E-03 2006.211.08:09:21.42/va/01,08,usb,yes,28,29 2006.211.08:09:21.42/va/02,07,usb,yes,28,29 2006.211.08:09:21.42/va/03,06,usb,yes,29,30 2006.211.08:09:21.42/va/04,07,usb,yes,29,31 2006.211.08:09:21.42/va/05,07,usb,yes,31,33 2006.211.08:09:21.42/va/06,06,usb,yes,30,30 2006.211.08:09:21.42/va/07,06,usb,yes,31,30 2006.211.08:09:21.42/va/08,07,usb,yes,29,29 2006.211.08:09:21.65/valo/01,532.99,yes,locked 2006.211.08:09:21.65/valo/02,572.99,yes,locked 2006.211.08:09:21.65/valo/03,672.99,yes,locked 2006.211.08:09:21.65/valo/04,832.99,yes,locked 2006.211.08:09:21.65/valo/05,652.99,yes,locked 2006.211.08:09:21.65/valo/06,772.99,yes,locked 2006.211.08:09:21.65/valo/07,832.99,yes,locked 2006.211.08:09:21.65/valo/08,852.99,yes,locked 2006.211.08:09:22.74/vb/01,04,usb,yes,28,27 2006.211.08:09:22.74/vb/02,04,usb,yes,30,31 2006.211.08:09:22.74/vb/03,03,usb,yes,33,37 2006.211.08:09:22.74/vb/04,03,usb,yes,33,34 2006.211.08:09:22.74/vb/05,03,usb,yes,32,36 2006.211.08:09:22.74/vb/06,03,usb,yes,32,36 2006.211.08:09:22.74/vb/07,04,usb,yes,28,28 2006.211.08:09:22.74/vb/08,03,usb,yes,33,36 2006.211.08:09:22.98/vblo/01,632.99,yes,locked 2006.211.08:09:22.98/vblo/02,640.99,yes,locked 2006.211.08:09:22.98/vblo/03,656.99,yes,locked 2006.211.08:09:22.98/vblo/04,712.99,yes,locked 2006.211.08:09:22.98/vblo/05,744.99,yes,locked 2006.211.08:09:22.98/vblo/06,752.99,yes,locked 2006.211.08:09:22.98/vblo/07,734.99,yes,locked 2006.211.08:09:22.98/vblo/08,744.99,yes,locked 2006.211.08:09:23.13/vabw/8 2006.211.08:09:23.28/vbbw/8 2006.211.08:09:23.37/xfe/off,on,12.0 2006.211.08:09:23.75/ifatt/23,28,28,28 2006.211.08:09:24.07/fmout-gps/S +4.47E-07 2006.211.08:09:24.12:!2006.211.08:10:20 2006.211.08:10:20.01:data_valid=off 2006.211.08:10:20.01:postob 2006.211.08:10:20.14/cable/+6.4418E-03 2006.211.08:10:20.14/wx/24.62,1010.0,79 2006.211.08:10:21.07/fmout-gps/S +4.46E-07 2006.211.08:10:21.07:scan_name=211-0811,k06211,60 2006.211.08:10:21.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.211.08:10:21.14#flagr#flagr/antenna,new-source 2006.211.08:10:22.14:checkk5 2006.211.08:10:22.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:10:22.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:10:23.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:10:23.52/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:10:23.85/chk_obsdata//k5ts1/T2110809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:10:24.18/chk_obsdata//k5ts2/T2110809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:10:24.51/chk_obsdata//k5ts3/T2110809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:10:24.85/chk_obsdata//k5ts4/T2110809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:10:25.51/k5log//k5ts1_log_newline 2006.211.08:10:26.16/k5log//k5ts2_log_newline 2006.211.08:10:26.81/k5log//k5ts3_log_newline 2006.211.08:10:27.48/k5log//k5ts4_log_newline 2006.211.08:10:27.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:10:27.50:4f8m12a=2 2006.211.08:10:27.50$4f8m12a/echo=on 2006.211.08:10:27.50$4f8m12a/pcalon 2006.211.08:10:27.50$pcalon/"no phase cal control is implemented here 2006.211.08:10:27.50$4f8m12a/"tpicd=stop 2006.211.08:10:27.51$4f8m12a/vc4f8 2006.211.08:10:27.51$vc4f8/valo=1,532.99 2006.211.08:10:27.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.08:10:27.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.08:10:27.51#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:27.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:27.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:27.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:27.51#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:10:27.51#ibcon#first serial, iclass 20, count 0 2006.211.08:10:27.51#ibcon#enter sib2, iclass 20, count 0 2006.211.08:10:27.51#ibcon#flushed, iclass 20, count 0 2006.211.08:10:27.51#ibcon#about to write, iclass 20, count 0 2006.211.08:10:27.51#ibcon#wrote, iclass 20, count 0 2006.211.08:10:27.51#ibcon#about to read 3, iclass 20, count 0 2006.211.08:10:27.52#ibcon#read 3, iclass 20, count 0 2006.211.08:10:27.52#ibcon#about to read 4, iclass 20, count 0 2006.211.08:10:27.52#ibcon#read 4, iclass 20, count 0 2006.211.08:10:27.52#ibcon#about to read 5, iclass 20, count 0 2006.211.08:10:27.52#ibcon#read 5, iclass 20, count 0 2006.211.08:10:27.52#ibcon#about to read 6, iclass 20, count 0 2006.211.08:10:27.52#ibcon#read 6, iclass 20, count 0 2006.211.08:10:27.52#ibcon#end of sib2, iclass 20, count 0 2006.211.08:10:27.52#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:10:27.52#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:10:27.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:10:27.52#ibcon#*before write, iclass 20, count 0 2006.211.08:10:27.52#ibcon#enter sib2, iclass 20, count 0 2006.211.08:10:27.52#ibcon#flushed, iclass 20, count 0 2006.211.08:10:27.52#ibcon#about to write, iclass 20, count 0 2006.211.08:10:27.52#ibcon#wrote, iclass 20, count 0 2006.211.08:10:27.52#ibcon#about to read 3, iclass 20, count 0 2006.211.08:10:27.57#ibcon#read 3, iclass 20, count 0 2006.211.08:10:27.57#ibcon#about to read 4, iclass 20, count 0 2006.211.08:10:27.57#ibcon#read 4, iclass 20, count 0 2006.211.08:10:27.57#ibcon#about to read 5, iclass 20, count 0 2006.211.08:10:27.57#ibcon#read 5, iclass 20, count 0 2006.211.08:10:27.57#ibcon#about to read 6, iclass 20, count 0 2006.211.08:10:27.57#ibcon#read 6, iclass 20, count 0 2006.211.08:10:27.57#ibcon#end of sib2, iclass 20, count 0 2006.211.08:10:27.57#ibcon#*after write, iclass 20, count 0 2006.211.08:10:27.57#ibcon#*before return 0, iclass 20, count 0 2006.211.08:10:27.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:27.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:27.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:10:27.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:10:27.57$vc4f8/va=1,8 2006.211.08:10:27.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.08:10:27.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.08:10:27.57#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:27.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:27.57#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:27.57#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:27.57#ibcon#enter wrdev, iclass 22, count 2 2006.211.08:10:27.57#ibcon#first serial, iclass 22, count 2 2006.211.08:10:27.57#ibcon#enter sib2, iclass 22, count 2 2006.211.08:10:27.57#ibcon#flushed, iclass 22, count 2 2006.211.08:10:27.57#ibcon#about to write, iclass 22, count 2 2006.211.08:10:27.57#ibcon#wrote, iclass 22, count 2 2006.211.08:10:27.57#ibcon#about to read 3, iclass 22, count 2 2006.211.08:10:27.59#ibcon#read 3, iclass 22, count 2 2006.211.08:10:27.59#ibcon#about to read 4, iclass 22, count 2 2006.211.08:10:27.59#ibcon#read 4, iclass 22, count 2 2006.211.08:10:27.59#ibcon#about to read 5, iclass 22, count 2 2006.211.08:10:27.59#ibcon#read 5, iclass 22, count 2 2006.211.08:10:27.59#ibcon#about to read 6, iclass 22, count 2 2006.211.08:10:27.59#ibcon#read 6, iclass 22, count 2 2006.211.08:10:27.59#ibcon#end of sib2, iclass 22, count 2 2006.211.08:10:27.59#ibcon#*mode == 0, iclass 22, count 2 2006.211.08:10:27.59#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.08:10:27.59#ibcon#[25=AT01-08\r\n] 2006.211.08:10:27.59#ibcon#*before write, iclass 22, count 2 2006.211.08:10:27.59#ibcon#enter sib2, iclass 22, count 2 2006.211.08:10:27.59#ibcon#flushed, iclass 22, count 2 2006.211.08:10:27.59#ibcon#about to write, iclass 22, count 2 2006.211.08:10:27.59#ibcon#wrote, iclass 22, count 2 2006.211.08:10:27.59#ibcon#about to read 3, iclass 22, count 2 2006.211.08:10:27.62#ibcon#read 3, iclass 22, count 2 2006.211.08:10:27.62#ibcon#about to read 4, iclass 22, count 2 2006.211.08:10:27.62#ibcon#read 4, iclass 22, count 2 2006.211.08:10:27.62#ibcon#about to read 5, iclass 22, count 2 2006.211.08:10:27.62#ibcon#read 5, iclass 22, count 2 2006.211.08:10:27.62#ibcon#about to read 6, iclass 22, count 2 2006.211.08:10:27.62#ibcon#read 6, iclass 22, count 2 2006.211.08:10:27.62#ibcon#end of sib2, iclass 22, count 2 2006.211.08:10:27.62#ibcon#*after write, iclass 22, count 2 2006.211.08:10:27.62#ibcon#*before return 0, iclass 22, count 2 2006.211.08:10:27.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:27.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:27.62#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.08:10:27.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:27.62#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:27.74#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:27.74#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:27.74#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:10:27.74#ibcon#first serial, iclass 22, count 0 2006.211.08:10:27.74#ibcon#enter sib2, iclass 22, count 0 2006.211.08:10:27.74#ibcon#flushed, iclass 22, count 0 2006.211.08:10:27.74#ibcon#about to write, iclass 22, count 0 2006.211.08:10:27.74#ibcon#wrote, iclass 22, count 0 2006.211.08:10:27.74#ibcon#about to read 3, iclass 22, count 0 2006.211.08:10:27.76#ibcon#read 3, iclass 22, count 0 2006.211.08:10:27.76#ibcon#about to read 4, iclass 22, count 0 2006.211.08:10:27.76#ibcon#read 4, iclass 22, count 0 2006.211.08:10:27.76#ibcon#about to read 5, iclass 22, count 0 2006.211.08:10:27.76#ibcon#read 5, iclass 22, count 0 2006.211.08:10:27.76#ibcon#about to read 6, iclass 22, count 0 2006.211.08:10:27.76#ibcon#read 6, iclass 22, count 0 2006.211.08:10:27.76#ibcon#end of sib2, iclass 22, count 0 2006.211.08:10:27.76#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:10:27.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:10:27.76#ibcon#[25=USB\r\n] 2006.211.08:10:27.76#ibcon#*before write, iclass 22, count 0 2006.211.08:10:27.76#ibcon#enter sib2, iclass 22, count 0 2006.211.08:10:27.76#ibcon#flushed, iclass 22, count 0 2006.211.08:10:27.76#ibcon#about to write, iclass 22, count 0 2006.211.08:10:27.76#ibcon#wrote, iclass 22, count 0 2006.211.08:10:27.76#ibcon#about to read 3, iclass 22, count 0 2006.211.08:10:27.79#ibcon#read 3, iclass 22, count 0 2006.211.08:10:27.79#ibcon#about to read 4, iclass 22, count 0 2006.211.08:10:27.79#ibcon#read 4, iclass 22, count 0 2006.211.08:10:27.79#ibcon#about to read 5, iclass 22, count 0 2006.211.08:10:27.79#ibcon#read 5, iclass 22, count 0 2006.211.08:10:27.79#ibcon#about to read 6, iclass 22, count 0 2006.211.08:10:27.79#ibcon#read 6, iclass 22, count 0 2006.211.08:10:27.79#ibcon#end of sib2, iclass 22, count 0 2006.211.08:10:27.79#ibcon#*after write, iclass 22, count 0 2006.211.08:10:27.79#ibcon#*before return 0, iclass 22, count 0 2006.211.08:10:27.79#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:27.79#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:27.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:10:27.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:10:27.79$vc4f8/valo=2,572.99 2006.211.08:10:27.79#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.08:10:27.79#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.08:10:27.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:27.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:27.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:27.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:27.79#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:10:27.79#ibcon#first serial, iclass 24, count 0 2006.211.08:10:27.79#ibcon#enter sib2, iclass 24, count 0 2006.211.08:10:27.79#ibcon#flushed, iclass 24, count 0 2006.211.08:10:27.79#ibcon#about to write, iclass 24, count 0 2006.211.08:10:27.79#ibcon#wrote, iclass 24, count 0 2006.211.08:10:27.79#ibcon#about to read 3, iclass 24, count 0 2006.211.08:10:27.81#ibcon#read 3, iclass 24, count 0 2006.211.08:10:27.81#ibcon#about to read 4, iclass 24, count 0 2006.211.08:10:27.81#ibcon#read 4, iclass 24, count 0 2006.211.08:10:27.81#ibcon#about to read 5, iclass 24, count 0 2006.211.08:10:27.81#ibcon#read 5, iclass 24, count 0 2006.211.08:10:27.81#ibcon#about to read 6, iclass 24, count 0 2006.211.08:10:27.81#ibcon#read 6, iclass 24, count 0 2006.211.08:10:27.81#ibcon#end of sib2, iclass 24, count 0 2006.211.08:10:27.81#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:10:27.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:10:27.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:10:27.81#ibcon#*before write, iclass 24, count 0 2006.211.08:10:27.81#ibcon#enter sib2, iclass 24, count 0 2006.211.08:10:27.81#ibcon#flushed, iclass 24, count 0 2006.211.08:10:27.81#ibcon#about to write, iclass 24, count 0 2006.211.08:10:27.81#ibcon#wrote, iclass 24, count 0 2006.211.08:10:27.81#ibcon#about to read 3, iclass 24, count 0 2006.211.08:10:27.85#ibcon#read 3, iclass 24, count 0 2006.211.08:10:27.85#ibcon#about to read 4, iclass 24, count 0 2006.211.08:10:27.85#ibcon#read 4, iclass 24, count 0 2006.211.08:10:27.85#ibcon#about to read 5, iclass 24, count 0 2006.211.08:10:27.85#ibcon#read 5, iclass 24, count 0 2006.211.08:10:27.85#ibcon#about to read 6, iclass 24, count 0 2006.211.08:10:27.85#ibcon#read 6, iclass 24, count 0 2006.211.08:10:27.85#ibcon#end of sib2, iclass 24, count 0 2006.211.08:10:27.85#ibcon#*after write, iclass 24, count 0 2006.211.08:10:27.85#ibcon#*before return 0, iclass 24, count 0 2006.211.08:10:27.85#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:27.85#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:27.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:10:27.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:10:27.85$vc4f8/va=2,7 2006.211.08:10:27.85#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.08:10:27.85#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.08:10:27.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:27.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:27.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:27.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:27.91#ibcon#enter wrdev, iclass 26, count 2 2006.211.08:10:27.91#ibcon#first serial, iclass 26, count 2 2006.211.08:10:27.91#ibcon#enter sib2, iclass 26, count 2 2006.211.08:10:27.91#ibcon#flushed, iclass 26, count 2 2006.211.08:10:27.91#ibcon#about to write, iclass 26, count 2 2006.211.08:10:27.91#ibcon#wrote, iclass 26, count 2 2006.211.08:10:27.91#ibcon#about to read 3, iclass 26, count 2 2006.211.08:10:27.93#ibcon#read 3, iclass 26, count 2 2006.211.08:10:27.93#ibcon#about to read 4, iclass 26, count 2 2006.211.08:10:27.93#ibcon#read 4, iclass 26, count 2 2006.211.08:10:27.93#ibcon#about to read 5, iclass 26, count 2 2006.211.08:10:27.93#ibcon#read 5, iclass 26, count 2 2006.211.08:10:27.93#ibcon#about to read 6, iclass 26, count 2 2006.211.08:10:27.93#ibcon#read 6, iclass 26, count 2 2006.211.08:10:27.93#ibcon#end of sib2, iclass 26, count 2 2006.211.08:10:27.93#ibcon#*mode == 0, iclass 26, count 2 2006.211.08:10:27.93#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.08:10:27.93#ibcon#[25=AT02-07\r\n] 2006.211.08:10:27.93#ibcon#*before write, iclass 26, count 2 2006.211.08:10:27.93#ibcon#enter sib2, iclass 26, count 2 2006.211.08:10:27.93#ibcon#flushed, iclass 26, count 2 2006.211.08:10:27.93#ibcon#about to write, iclass 26, count 2 2006.211.08:10:27.93#ibcon#wrote, iclass 26, count 2 2006.211.08:10:27.93#ibcon#about to read 3, iclass 26, count 2 2006.211.08:10:27.96#ibcon#read 3, iclass 26, count 2 2006.211.08:10:27.96#ibcon#about to read 4, iclass 26, count 2 2006.211.08:10:27.96#ibcon#read 4, iclass 26, count 2 2006.211.08:10:27.96#ibcon#about to read 5, iclass 26, count 2 2006.211.08:10:27.96#ibcon#read 5, iclass 26, count 2 2006.211.08:10:27.96#ibcon#about to read 6, iclass 26, count 2 2006.211.08:10:27.96#ibcon#read 6, iclass 26, count 2 2006.211.08:10:27.96#ibcon#end of sib2, iclass 26, count 2 2006.211.08:10:27.96#ibcon#*after write, iclass 26, count 2 2006.211.08:10:27.96#ibcon#*before return 0, iclass 26, count 2 2006.211.08:10:27.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:27.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:27.96#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.08:10:27.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:27.96#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:28.08#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:28.08#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:28.08#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:10:28.08#ibcon#first serial, iclass 26, count 0 2006.211.08:10:28.08#ibcon#enter sib2, iclass 26, count 0 2006.211.08:10:28.08#ibcon#flushed, iclass 26, count 0 2006.211.08:10:28.08#ibcon#about to write, iclass 26, count 0 2006.211.08:10:28.08#ibcon#wrote, iclass 26, count 0 2006.211.08:10:28.08#ibcon#about to read 3, iclass 26, count 0 2006.211.08:10:28.10#ibcon#read 3, iclass 26, count 0 2006.211.08:10:28.10#ibcon#about to read 4, iclass 26, count 0 2006.211.08:10:28.10#ibcon#read 4, iclass 26, count 0 2006.211.08:10:28.10#ibcon#about to read 5, iclass 26, count 0 2006.211.08:10:28.10#ibcon#read 5, iclass 26, count 0 2006.211.08:10:28.10#ibcon#about to read 6, iclass 26, count 0 2006.211.08:10:28.10#ibcon#read 6, iclass 26, count 0 2006.211.08:10:28.10#ibcon#end of sib2, iclass 26, count 0 2006.211.08:10:28.10#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:10:28.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:10:28.10#ibcon#[25=USB\r\n] 2006.211.08:10:28.10#ibcon#*before write, iclass 26, count 0 2006.211.08:10:28.10#ibcon#enter sib2, iclass 26, count 0 2006.211.08:10:28.10#ibcon#flushed, iclass 26, count 0 2006.211.08:10:28.10#ibcon#about to write, iclass 26, count 0 2006.211.08:10:28.10#ibcon#wrote, iclass 26, count 0 2006.211.08:10:28.10#ibcon#about to read 3, iclass 26, count 0 2006.211.08:10:28.13#ibcon#read 3, iclass 26, count 0 2006.211.08:10:28.13#ibcon#about to read 4, iclass 26, count 0 2006.211.08:10:28.13#ibcon#read 4, iclass 26, count 0 2006.211.08:10:28.13#ibcon#about to read 5, iclass 26, count 0 2006.211.08:10:28.13#ibcon#read 5, iclass 26, count 0 2006.211.08:10:28.13#ibcon#about to read 6, iclass 26, count 0 2006.211.08:10:28.13#ibcon#read 6, iclass 26, count 0 2006.211.08:10:28.13#ibcon#end of sib2, iclass 26, count 0 2006.211.08:10:28.13#ibcon#*after write, iclass 26, count 0 2006.211.08:10:28.13#ibcon#*before return 0, iclass 26, count 0 2006.211.08:10:28.13#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:28.13#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:28.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:10:28.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:10:28.13$vc4f8/valo=3,672.99 2006.211.08:10:28.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.08:10:28.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.08:10:28.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:28.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:28.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:28.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:28.13#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:10:28.13#ibcon#first serial, iclass 28, count 0 2006.211.08:10:28.13#ibcon#enter sib2, iclass 28, count 0 2006.211.08:10:28.13#ibcon#flushed, iclass 28, count 0 2006.211.08:10:28.13#ibcon#about to write, iclass 28, count 0 2006.211.08:10:28.13#ibcon#wrote, iclass 28, count 0 2006.211.08:10:28.13#ibcon#about to read 3, iclass 28, count 0 2006.211.08:10:28.15#ibcon#read 3, iclass 28, count 0 2006.211.08:10:28.15#ibcon#about to read 4, iclass 28, count 0 2006.211.08:10:28.15#ibcon#read 4, iclass 28, count 0 2006.211.08:10:28.15#ibcon#about to read 5, iclass 28, count 0 2006.211.08:10:28.15#ibcon#read 5, iclass 28, count 0 2006.211.08:10:28.15#ibcon#about to read 6, iclass 28, count 0 2006.211.08:10:28.15#ibcon#read 6, iclass 28, count 0 2006.211.08:10:28.15#ibcon#end of sib2, iclass 28, count 0 2006.211.08:10:28.15#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:10:28.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:10:28.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:10:28.15#ibcon#*before write, iclass 28, count 0 2006.211.08:10:28.15#ibcon#enter sib2, iclass 28, count 0 2006.211.08:10:28.15#ibcon#flushed, iclass 28, count 0 2006.211.08:10:28.15#ibcon#about to write, iclass 28, count 0 2006.211.08:10:28.15#ibcon#wrote, iclass 28, count 0 2006.211.08:10:28.15#ibcon#about to read 3, iclass 28, count 0 2006.211.08:10:28.19#ibcon#read 3, iclass 28, count 0 2006.211.08:10:28.19#ibcon#about to read 4, iclass 28, count 0 2006.211.08:10:28.19#ibcon#read 4, iclass 28, count 0 2006.211.08:10:28.19#ibcon#about to read 5, iclass 28, count 0 2006.211.08:10:28.19#ibcon#read 5, iclass 28, count 0 2006.211.08:10:28.19#ibcon#about to read 6, iclass 28, count 0 2006.211.08:10:28.19#ibcon#read 6, iclass 28, count 0 2006.211.08:10:28.19#ibcon#end of sib2, iclass 28, count 0 2006.211.08:10:28.19#ibcon#*after write, iclass 28, count 0 2006.211.08:10:28.19#ibcon#*before return 0, iclass 28, count 0 2006.211.08:10:28.19#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:28.19#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:28.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:10:28.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:10:28.19$vc4f8/va=3,6 2006.211.08:10:28.19#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.08:10:28.19#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.08:10:28.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:28.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:28.25#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:28.25#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:28.25#ibcon#enter wrdev, iclass 30, count 2 2006.211.08:10:28.25#ibcon#first serial, iclass 30, count 2 2006.211.08:10:28.25#ibcon#enter sib2, iclass 30, count 2 2006.211.08:10:28.25#ibcon#flushed, iclass 30, count 2 2006.211.08:10:28.25#ibcon#about to write, iclass 30, count 2 2006.211.08:10:28.25#ibcon#wrote, iclass 30, count 2 2006.211.08:10:28.25#ibcon#about to read 3, iclass 30, count 2 2006.211.08:10:28.27#ibcon#read 3, iclass 30, count 2 2006.211.08:10:28.27#ibcon#about to read 4, iclass 30, count 2 2006.211.08:10:28.27#ibcon#read 4, iclass 30, count 2 2006.211.08:10:28.27#ibcon#about to read 5, iclass 30, count 2 2006.211.08:10:28.27#ibcon#read 5, iclass 30, count 2 2006.211.08:10:28.27#ibcon#about to read 6, iclass 30, count 2 2006.211.08:10:28.27#ibcon#read 6, iclass 30, count 2 2006.211.08:10:28.27#ibcon#end of sib2, iclass 30, count 2 2006.211.08:10:28.27#ibcon#*mode == 0, iclass 30, count 2 2006.211.08:10:28.27#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.08:10:28.27#ibcon#[25=AT03-06\r\n] 2006.211.08:10:28.27#ibcon#*before write, iclass 30, count 2 2006.211.08:10:28.27#ibcon#enter sib2, iclass 30, count 2 2006.211.08:10:28.27#ibcon#flushed, iclass 30, count 2 2006.211.08:10:28.27#ibcon#about to write, iclass 30, count 2 2006.211.08:10:28.27#ibcon#wrote, iclass 30, count 2 2006.211.08:10:28.27#ibcon#about to read 3, iclass 30, count 2 2006.211.08:10:28.30#ibcon#read 3, iclass 30, count 2 2006.211.08:10:28.30#ibcon#about to read 4, iclass 30, count 2 2006.211.08:10:28.30#ibcon#read 4, iclass 30, count 2 2006.211.08:10:28.30#ibcon#about to read 5, iclass 30, count 2 2006.211.08:10:28.30#ibcon#read 5, iclass 30, count 2 2006.211.08:10:28.30#ibcon#about to read 6, iclass 30, count 2 2006.211.08:10:28.30#ibcon#read 6, iclass 30, count 2 2006.211.08:10:28.30#ibcon#end of sib2, iclass 30, count 2 2006.211.08:10:28.30#ibcon#*after write, iclass 30, count 2 2006.211.08:10:28.30#ibcon#*before return 0, iclass 30, count 2 2006.211.08:10:28.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:28.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:28.30#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.08:10:28.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:28.30#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:28.42#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:28.42#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:28.42#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:10:28.42#ibcon#first serial, iclass 30, count 0 2006.211.08:10:28.42#ibcon#enter sib2, iclass 30, count 0 2006.211.08:10:28.42#ibcon#flushed, iclass 30, count 0 2006.211.08:10:28.42#ibcon#about to write, iclass 30, count 0 2006.211.08:10:28.42#ibcon#wrote, iclass 30, count 0 2006.211.08:10:28.42#ibcon#about to read 3, iclass 30, count 0 2006.211.08:10:28.44#ibcon#read 3, iclass 30, count 0 2006.211.08:10:28.44#ibcon#about to read 4, iclass 30, count 0 2006.211.08:10:28.44#ibcon#read 4, iclass 30, count 0 2006.211.08:10:28.44#ibcon#about to read 5, iclass 30, count 0 2006.211.08:10:28.44#ibcon#read 5, iclass 30, count 0 2006.211.08:10:28.44#ibcon#about to read 6, iclass 30, count 0 2006.211.08:10:28.44#ibcon#read 6, iclass 30, count 0 2006.211.08:10:28.44#ibcon#end of sib2, iclass 30, count 0 2006.211.08:10:28.44#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:10:28.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:10:28.44#ibcon#[25=USB\r\n] 2006.211.08:10:28.44#ibcon#*before write, iclass 30, count 0 2006.211.08:10:28.44#ibcon#enter sib2, iclass 30, count 0 2006.211.08:10:28.44#ibcon#flushed, iclass 30, count 0 2006.211.08:10:28.44#ibcon#about to write, iclass 30, count 0 2006.211.08:10:28.44#ibcon#wrote, iclass 30, count 0 2006.211.08:10:28.44#ibcon#about to read 3, iclass 30, count 0 2006.211.08:10:28.47#ibcon#read 3, iclass 30, count 0 2006.211.08:10:28.47#ibcon#about to read 4, iclass 30, count 0 2006.211.08:10:28.47#ibcon#read 4, iclass 30, count 0 2006.211.08:10:28.47#ibcon#about to read 5, iclass 30, count 0 2006.211.08:10:28.47#ibcon#read 5, iclass 30, count 0 2006.211.08:10:28.47#ibcon#about to read 6, iclass 30, count 0 2006.211.08:10:28.47#ibcon#read 6, iclass 30, count 0 2006.211.08:10:28.47#ibcon#end of sib2, iclass 30, count 0 2006.211.08:10:28.47#ibcon#*after write, iclass 30, count 0 2006.211.08:10:28.47#ibcon#*before return 0, iclass 30, count 0 2006.211.08:10:28.47#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:28.47#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:28.47#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:10:28.47#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:10:28.47$vc4f8/valo=4,832.99 2006.211.08:10:28.47#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.08:10:28.47#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.08:10:28.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:28.47#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:28.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:28.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:28.47#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:10:28.47#ibcon#first serial, iclass 32, count 0 2006.211.08:10:28.47#ibcon#enter sib2, iclass 32, count 0 2006.211.08:10:28.47#ibcon#flushed, iclass 32, count 0 2006.211.08:10:28.47#ibcon#about to write, iclass 32, count 0 2006.211.08:10:28.47#ibcon#wrote, iclass 32, count 0 2006.211.08:10:28.47#ibcon#about to read 3, iclass 32, count 0 2006.211.08:10:28.49#ibcon#read 3, iclass 32, count 0 2006.211.08:10:28.49#ibcon#about to read 4, iclass 32, count 0 2006.211.08:10:28.49#ibcon#read 4, iclass 32, count 0 2006.211.08:10:28.49#ibcon#about to read 5, iclass 32, count 0 2006.211.08:10:28.49#ibcon#read 5, iclass 32, count 0 2006.211.08:10:28.49#ibcon#about to read 6, iclass 32, count 0 2006.211.08:10:28.49#ibcon#read 6, iclass 32, count 0 2006.211.08:10:28.49#ibcon#end of sib2, iclass 32, count 0 2006.211.08:10:28.49#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:10:28.49#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:10:28.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:10:28.49#ibcon#*before write, iclass 32, count 0 2006.211.08:10:28.49#ibcon#enter sib2, iclass 32, count 0 2006.211.08:10:28.49#ibcon#flushed, iclass 32, count 0 2006.211.08:10:28.49#ibcon#about to write, iclass 32, count 0 2006.211.08:10:28.49#ibcon#wrote, iclass 32, count 0 2006.211.08:10:28.49#ibcon#about to read 3, iclass 32, count 0 2006.211.08:10:28.53#ibcon#read 3, iclass 32, count 0 2006.211.08:10:28.53#ibcon#about to read 4, iclass 32, count 0 2006.211.08:10:28.53#ibcon#read 4, iclass 32, count 0 2006.211.08:10:28.53#ibcon#about to read 5, iclass 32, count 0 2006.211.08:10:28.53#ibcon#read 5, iclass 32, count 0 2006.211.08:10:28.53#ibcon#about to read 6, iclass 32, count 0 2006.211.08:10:28.53#ibcon#read 6, iclass 32, count 0 2006.211.08:10:28.53#ibcon#end of sib2, iclass 32, count 0 2006.211.08:10:28.53#ibcon#*after write, iclass 32, count 0 2006.211.08:10:28.53#ibcon#*before return 0, iclass 32, count 0 2006.211.08:10:28.53#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:28.53#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:28.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:10:28.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:10:28.53$vc4f8/va=4,7 2006.211.08:10:28.53#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.08:10:28.53#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.08:10:28.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:28.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:28.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:28.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:28.59#ibcon#enter wrdev, iclass 34, count 2 2006.211.08:10:28.59#ibcon#first serial, iclass 34, count 2 2006.211.08:10:28.59#ibcon#enter sib2, iclass 34, count 2 2006.211.08:10:28.59#ibcon#flushed, iclass 34, count 2 2006.211.08:10:28.59#ibcon#about to write, iclass 34, count 2 2006.211.08:10:28.59#ibcon#wrote, iclass 34, count 2 2006.211.08:10:28.59#ibcon#about to read 3, iclass 34, count 2 2006.211.08:10:28.61#ibcon#read 3, iclass 34, count 2 2006.211.08:10:28.61#ibcon#about to read 4, iclass 34, count 2 2006.211.08:10:28.61#ibcon#read 4, iclass 34, count 2 2006.211.08:10:28.61#ibcon#about to read 5, iclass 34, count 2 2006.211.08:10:28.61#ibcon#read 5, iclass 34, count 2 2006.211.08:10:28.61#ibcon#about to read 6, iclass 34, count 2 2006.211.08:10:28.61#ibcon#read 6, iclass 34, count 2 2006.211.08:10:28.61#ibcon#end of sib2, iclass 34, count 2 2006.211.08:10:28.61#ibcon#*mode == 0, iclass 34, count 2 2006.211.08:10:28.61#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.08:10:28.61#ibcon#[25=AT04-07\r\n] 2006.211.08:10:28.61#ibcon#*before write, iclass 34, count 2 2006.211.08:10:28.61#ibcon#enter sib2, iclass 34, count 2 2006.211.08:10:28.61#ibcon#flushed, iclass 34, count 2 2006.211.08:10:28.61#ibcon#about to write, iclass 34, count 2 2006.211.08:10:28.61#ibcon#wrote, iclass 34, count 2 2006.211.08:10:28.61#ibcon#about to read 3, iclass 34, count 2 2006.211.08:10:28.64#ibcon#read 3, iclass 34, count 2 2006.211.08:10:28.64#ibcon#about to read 4, iclass 34, count 2 2006.211.08:10:28.64#ibcon#read 4, iclass 34, count 2 2006.211.08:10:28.64#ibcon#about to read 5, iclass 34, count 2 2006.211.08:10:28.64#ibcon#read 5, iclass 34, count 2 2006.211.08:10:28.64#ibcon#about to read 6, iclass 34, count 2 2006.211.08:10:28.64#ibcon#read 6, iclass 34, count 2 2006.211.08:10:28.64#ibcon#end of sib2, iclass 34, count 2 2006.211.08:10:28.64#ibcon#*after write, iclass 34, count 2 2006.211.08:10:28.64#ibcon#*before return 0, iclass 34, count 2 2006.211.08:10:28.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:28.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:28.64#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.08:10:28.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:28.64#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:28.76#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:28.76#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:28.76#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:10:28.76#ibcon#first serial, iclass 34, count 0 2006.211.08:10:28.76#ibcon#enter sib2, iclass 34, count 0 2006.211.08:10:28.76#ibcon#flushed, iclass 34, count 0 2006.211.08:10:28.76#ibcon#about to write, iclass 34, count 0 2006.211.08:10:28.76#ibcon#wrote, iclass 34, count 0 2006.211.08:10:28.76#ibcon#about to read 3, iclass 34, count 0 2006.211.08:10:28.78#ibcon#read 3, iclass 34, count 0 2006.211.08:10:28.78#ibcon#about to read 4, iclass 34, count 0 2006.211.08:10:28.78#ibcon#read 4, iclass 34, count 0 2006.211.08:10:28.78#ibcon#about to read 5, iclass 34, count 0 2006.211.08:10:28.78#ibcon#read 5, iclass 34, count 0 2006.211.08:10:28.78#ibcon#about to read 6, iclass 34, count 0 2006.211.08:10:28.78#ibcon#read 6, iclass 34, count 0 2006.211.08:10:28.78#ibcon#end of sib2, iclass 34, count 0 2006.211.08:10:28.78#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:10:28.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:10:28.78#ibcon#[25=USB\r\n] 2006.211.08:10:28.78#ibcon#*before write, iclass 34, count 0 2006.211.08:10:28.78#ibcon#enter sib2, iclass 34, count 0 2006.211.08:10:28.78#ibcon#flushed, iclass 34, count 0 2006.211.08:10:28.78#ibcon#about to write, iclass 34, count 0 2006.211.08:10:28.78#ibcon#wrote, iclass 34, count 0 2006.211.08:10:28.78#ibcon#about to read 3, iclass 34, count 0 2006.211.08:10:28.81#ibcon#read 3, iclass 34, count 0 2006.211.08:10:28.81#ibcon#about to read 4, iclass 34, count 0 2006.211.08:10:28.81#ibcon#read 4, iclass 34, count 0 2006.211.08:10:28.81#ibcon#about to read 5, iclass 34, count 0 2006.211.08:10:28.81#ibcon#read 5, iclass 34, count 0 2006.211.08:10:28.81#ibcon#about to read 6, iclass 34, count 0 2006.211.08:10:28.81#ibcon#read 6, iclass 34, count 0 2006.211.08:10:28.81#ibcon#end of sib2, iclass 34, count 0 2006.211.08:10:28.81#ibcon#*after write, iclass 34, count 0 2006.211.08:10:28.81#ibcon#*before return 0, iclass 34, count 0 2006.211.08:10:28.81#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:28.81#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:28.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:10:28.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:10:28.81$vc4f8/valo=5,652.99 2006.211.08:10:28.81#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.08:10:28.81#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.08:10:28.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:28.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:28.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:28.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:28.81#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:10:28.81#ibcon#first serial, iclass 36, count 0 2006.211.08:10:28.81#ibcon#enter sib2, iclass 36, count 0 2006.211.08:10:28.81#ibcon#flushed, iclass 36, count 0 2006.211.08:10:28.81#ibcon#about to write, iclass 36, count 0 2006.211.08:10:28.81#ibcon#wrote, iclass 36, count 0 2006.211.08:10:28.81#ibcon#about to read 3, iclass 36, count 0 2006.211.08:10:28.83#ibcon#read 3, iclass 36, count 0 2006.211.08:10:28.83#ibcon#about to read 4, iclass 36, count 0 2006.211.08:10:28.83#ibcon#read 4, iclass 36, count 0 2006.211.08:10:28.83#ibcon#about to read 5, iclass 36, count 0 2006.211.08:10:28.83#ibcon#read 5, iclass 36, count 0 2006.211.08:10:28.83#ibcon#about to read 6, iclass 36, count 0 2006.211.08:10:28.83#ibcon#read 6, iclass 36, count 0 2006.211.08:10:28.83#ibcon#end of sib2, iclass 36, count 0 2006.211.08:10:28.83#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:10:28.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:10:28.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:10:28.83#ibcon#*before write, iclass 36, count 0 2006.211.08:10:28.83#ibcon#enter sib2, iclass 36, count 0 2006.211.08:10:28.83#ibcon#flushed, iclass 36, count 0 2006.211.08:10:28.83#ibcon#about to write, iclass 36, count 0 2006.211.08:10:28.83#ibcon#wrote, iclass 36, count 0 2006.211.08:10:28.83#ibcon#about to read 3, iclass 36, count 0 2006.211.08:10:28.87#ibcon#read 3, iclass 36, count 0 2006.211.08:10:28.87#ibcon#about to read 4, iclass 36, count 0 2006.211.08:10:28.87#ibcon#read 4, iclass 36, count 0 2006.211.08:10:28.87#ibcon#about to read 5, iclass 36, count 0 2006.211.08:10:28.87#ibcon#read 5, iclass 36, count 0 2006.211.08:10:28.87#ibcon#about to read 6, iclass 36, count 0 2006.211.08:10:28.87#ibcon#read 6, iclass 36, count 0 2006.211.08:10:28.87#ibcon#end of sib2, iclass 36, count 0 2006.211.08:10:28.87#ibcon#*after write, iclass 36, count 0 2006.211.08:10:28.87#ibcon#*before return 0, iclass 36, count 0 2006.211.08:10:28.87#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:28.87#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:28.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:10:28.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:10:28.87$vc4f8/va=5,7 2006.211.08:10:28.87#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.08:10:28.87#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.08:10:28.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:28.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:28.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:28.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:28.93#ibcon#enter wrdev, iclass 38, count 2 2006.211.08:10:28.93#ibcon#first serial, iclass 38, count 2 2006.211.08:10:28.93#ibcon#enter sib2, iclass 38, count 2 2006.211.08:10:28.93#ibcon#flushed, iclass 38, count 2 2006.211.08:10:28.93#ibcon#about to write, iclass 38, count 2 2006.211.08:10:28.93#ibcon#wrote, iclass 38, count 2 2006.211.08:10:28.93#ibcon#about to read 3, iclass 38, count 2 2006.211.08:10:28.95#ibcon#read 3, iclass 38, count 2 2006.211.08:10:28.95#ibcon#about to read 4, iclass 38, count 2 2006.211.08:10:28.95#ibcon#read 4, iclass 38, count 2 2006.211.08:10:28.95#ibcon#about to read 5, iclass 38, count 2 2006.211.08:10:28.95#ibcon#read 5, iclass 38, count 2 2006.211.08:10:28.95#ibcon#about to read 6, iclass 38, count 2 2006.211.08:10:28.95#ibcon#read 6, iclass 38, count 2 2006.211.08:10:28.95#ibcon#end of sib2, iclass 38, count 2 2006.211.08:10:28.95#ibcon#*mode == 0, iclass 38, count 2 2006.211.08:10:28.95#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.08:10:28.95#ibcon#[25=AT05-07\r\n] 2006.211.08:10:28.95#ibcon#*before write, iclass 38, count 2 2006.211.08:10:28.95#ibcon#enter sib2, iclass 38, count 2 2006.211.08:10:28.95#ibcon#flushed, iclass 38, count 2 2006.211.08:10:28.95#ibcon#about to write, iclass 38, count 2 2006.211.08:10:28.95#ibcon#wrote, iclass 38, count 2 2006.211.08:10:28.95#ibcon#about to read 3, iclass 38, count 2 2006.211.08:10:28.95#abcon#<5=/04 4.4 8.1 24.62 791010.1\r\n> 2006.211.08:10:28.97#abcon#{5=INTERFACE CLEAR} 2006.211.08:10:28.98#ibcon#read 3, iclass 38, count 2 2006.211.08:10:28.98#ibcon#about to read 4, iclass 38, count 2 2006.211.08:10:28.98#ibcon#read 4, iclass 38, count 2 2006.211.08:10:28.98#ibcon#about to read 5, iclass 38, count 2 2006.211.08:10:28.98#ibcon#read 5, iclass 38, count 2 2006.211.08:10:28.98#ibcon#about to read 6, iclass 38, count 2 2006.211.08:10:28.98#ibcon#read 6, iclass 38, count 2 2006.211.08:10:28.98#ibcon#end of sib2, iclass 38, count 2 2006.211.08:10:28.98#ibcon#*after write, iclass 38, count 2 2006.211.08:10:28.98#ibcon#*before return 0, iclass 38, count 2 2006.211.08:10:28.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:28.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:28.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.08:10:28.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:28.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:29.03#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:10:29.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:29.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:29.10#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:10:29.10#ibcon#first serial, iclass 38, count 0 2006.211.08:10:29.10#ibcon#enter sib2, iclass 38, count 0 2006.211.08:10:29.10#ibcon#flushed, iclass 38, count 0 2006.211.08:10:29.10#ibcon#about to write, iclass 38, count 0 2006.211.08:10:29.10#ibcon#wrote, iclass 38, count 0 2006.211.08:10:29.10#ibcon#about to read 3, iclass 38, count 0 2006.211.08:10:29.12#ibcon#read 3, iclass 38, count 0 2006.211.08:10:29.12#ibcon#about to read 4, iclass 38, count 0 2006.211.08:10:29.12#ibcon#read 4, iclass 38, count 0 2006.211.08:10:29.12#ibcon#about to read 5, iclass 38, count 0 2006.211.08:10:29.12#ibcon#read 5, iclass 38, count 0 2006.211.08:10:29.12#ibcon#about to read 6, iclass 38, count 0 2006.211.08:10:29.12#ibcon#read 6, iclass 38, count 0 2006.211.08:10:29.12#ibcon#end of sib2, iclass 38, count 0 2006.211.08:10:29.12#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:10:29.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:10:29.12#ibcon#[25=USB\r\n] 2006.211.08:10:29.12#ibcon#*before write, iclass 38, count 0 2006.211.08:10:29.12#ibcon#enter sib2, iclass 38, count 0 2006.211.08:10:29.12#ibcon#flushed, iclass 38, count 0 2006.211.08:10:29.12#ibcon#about to write, iclass 38, count 0 2006.211.08:10:29.12#ibcon#wrote, iclass 38, count 0 2006.211.08:10:29.12#ibcon#about to read 3, iclass 38, count 0 2006.211.08:10:29.15#ibcon#read 3, iclass 38, count 0 2006.211.08:10:29.15#ibcon#about to read 4, iclass 38, count 0 2006.211.08:10:29.15#ibcon#read 4, iclass 38, count 0 2006.211.08:10:29.15#ibcon#about to read 5, iclass 38, count 0 2006.211.08:10:29.15#ibcon#read 5, iclass 38, count 0 2006.211.08:10:29.15#ibcon#about to read 6, iclass 38, count 0 2006.211.08:10:29.15#ibcon#read 6, iclass 38, count 0 2006.211.08:10:29.15#ibcon#end of sib2, iclass 38, count 0 2006.211.08:10:29.15#ibcon#*after write, iclass 38, count 0 2006.211.08:10:29.15#ibcon#*before return 0, iclass 38, count 0 2006.211.08:10:29.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:29.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:29.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:10:29.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:10:29.15$vc4f8/valo=6,772.99 2006.211.08:10:29.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.08:10:29.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.08:10:29.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:29.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:29.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:29.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:29.15#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:10:29.15#ibcon#first serial, iclass 6, count 0 2006.211.08:10:29.15#ibcon#enter sib2, iclass 6, count 0 2006.211.08:10:29.15#ibcon#flushed, iclass 6, count 0 2006.211.08:10:29.15#ibcon#about to write, iclass 6, count 0 2006.211.08:10:29.15#ibcon#wrote, iclass 6, count 0 2006.211.08:10:29.15#ibcon#about to read 3, iclass 6, count 0 2006.211.08:10:29.17#ibcon#read 3, iclass 6, count 0 2006.211.08:10:29.17#ibcon#about to read 4, iclass 6, count 0 2006.211.08:10:29.17#ibcon#read 4, iclass 6, count 0 2006.211.08:10:29.17#ibcon#about to read 5, iclass 6, count 0 2006.211.08:10:29.17#ibcon#read 5, iclass 6, count 0 2006.211.08:10:29.17#ibcon#about to read 6, iclass 6, count 0 2006.211.08:10:29.17#ibcon#read 6, iclass 6, count 0 2006.211.08:10:29.17#ibcon#end of sib2, iclass 6, count 0 2006.211.08:10:29.17#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:10:29.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:10:29.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:10:29.17#ibcon#*before write, iclass 6, count 0 2006.211.08:10:29.17#ibcon#enter sib2, iclass 6, count 0 2006.211.08:10:29.17#ibcon#flushed, iclass 6, count 0 2006.211.08:10:29.17#ibcon#about to write, iclass 6, count 0 2006.211.08:10:29.17#ibcon#wrote, iclass 6, count 0 2006.211.08:10:29.17#ibcon#about to read 3, iclass 6, count 0 2006.211.08:10:29.21#ibcon#read 3, iclass 6, count 0 2006.211.08:10:29.21#ibcon#about to read 4, iclass 6, count 0 2006.211.08:10:29.21#ibcon#read 4, iclass 6, count 0 2006.211.08:10:29.21#ibcon#about to read 5, iclass 6, count 0 2006.211.08:10:29.21#ibcon#read 5, iclass 6, count 0 2006.211.08:10:29.21#ibcon#about to read 6, iclass 6, count 0 2006.211.08:10:29.21#ibcon#read 6, iclass 6, count 0 2006.211.08:10:29.21#ibcon#end of sib2, iclass 6, count 0 2006.211.08:10:29.21#ibcon#*after write, iclass 6, count 0 2006.211.08:10:29.21#ibcon#*before return 0, iclass 6, count 0 2006.211.08:10:29.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:29.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:29.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:10:29.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:10:29.21$vc4f8/va=6,6 2006.211.08:10:29.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.211.08:10:29.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.211.08:10:29.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:29.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.08:10:29.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.211.08:10:29.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.08:10:29.27#ibcon#enter wrdev, iclass 10, count 2 2006.211.08:10:29.27#ibcon#first serial, iclass 10, count 2 2006.211.08:10:29.27#ibcon#enter sib2, iclass 10, count 2 2006.211.08:10:29.27#ibcon#flushed, iclass 10, count 2 2006.211.08:10:29.27#ibcon#about to write, iclass 10, count 2 2006.211.08:10:29.27#ibcon#wrote, iclass 10, count 2 2006.211.08:10:29.27#ibcon#about to read 3, iclass 10, count 2 2006.211.08:10:29.29#ibcon#read 3, iclass 10, count 2 2006.211.08:10:29.29#ibcon#about to read 4, iclass 10, count 2 2006.211.08:10:29.29#ibcon#read 4, iclass 10, count 2 2006.211.08:10:29.29#ibcon#about to read 5, iclass 10, count 2 2006.211.08:10:29.29#ibcon#read 5, iclass 10, count 2 2006.211.08:10:29.29#ibcon#about to read 6, iclass 10, count 2 2006.211.08:10:29.29#ibcon#read 6, iclass 10, count 2 2006.211.08:10:29.29#ibcon#end of sib2, iclass 10, count 2 2006.211.08:10:29.29#ibcon#*mode == 0, iclass 10, count 2 2006.211.08:10:29.29#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.211.08:10:29.29#ibcon#[25=AT06-06\r\n] 2006.211.08:10:29.29#ibcon#*before write, iclass 10, count 2 2006.211.08:10:29.29#ibcon#enter sib2, iclass 10, count 2 2006.211.08:10:29.29#ibcon#flushed, iclass 10, count 2 2006.211.08:10:29.29#ibcon#about to write, iclass 10, count 2 2006.211.08:10:29.29#ibcon#wrote, iclass 10, count 2 2006.211.08:10:29.29#ibcon#about to read 3, iclass 10, count 2 2006.211.08:10:29.32#ibcon#read 3, iclass 10, count 2 2006.211.08:10:29.32#ibcon#about to read 4, iclass 10, count 2 2006.211.08:10:29.32#ibcon#read 4, iclass 10, count 2 2006.211.08:10:29.32#ibcon#about to read 5, iclass 10, count 2 2006.211.08:10:29.32#ibcon#read 5, iclass 10, count 2 2006.211.08:10:29.32#ibcon#about to read 6, iclass 10, count 2 2006.211.08:10:29.32#ibcon#read 6, iclass 10, count 2 2006.211.08:10:29.32#ibcon#end of sib2, iclass 10, count 2 2006.211.08:10:29.32#ibcon#*after write, iclass 10, count 2 2006.211.08:10:29.32#ibcon#*before return 0, iclass 10, count 2 2006.211.08:10:29.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.211.08:10:29.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.211.08:10:29.32#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.211.08:10:29.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:29.32#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.08:10:29.44#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.211.08:10:29.44#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.08:10:29.44#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:10:29.44#ibcon#first serial, iclass 10, count 0 2006.211.08:10:29.44#ibcon#enter sib2, iclass 10, count 0 2006.211.08:10:29.44#ibcon#flushed, iclass 10, count 0 2006.211.08:10:29.44#ibcon#about to write, iclass 10, count 0 2006.211.08:10:29.44#ibcon#wrote, iclass 10, count 0 2006.211.08:10:29.44#ibcon#about to read 3, iclass 10, count 0 2006.211.08:10:29.46#ibcon#read 3, iclass 10, count 0 2006.211.08:10:29.46#ibcon#about to read 4, iclass 10, count 0 2006.211.08:10:29.46#ibcon#read 4, iclass 10, count 0 2006.211.08:10:29.46#ibcon#about to read 5, iclass 10, count 0 2006.211.08:10:29.46#ibcon#read 5, iclass 10, count 0 2006.211.08:10:29.46#ibcon#about to read 6, iclass 10, count 0 2006.211.08:10:29.46#ibcon#read 6, iclass 10, count 0 2006.211.08:10:29.46#ibcon#end of sib2, iclass 10, count 0 2006.211.08:10:29.46#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:10:29.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:10:29.46#ibcon#[25=USB\r\n] 2006.211.08:10:29.46#ibcon#*before write, iclass 10, count 0 2006.211.08:10:29.46#ibcon#enter sib2, iclass 10, count 0 2006.211.08:10:29.46#ibcon#flushed, iclass 10, count 0 2006.211.08:10:29.46#ibcon#about to write, iclass 10, count 0 2006.211.08:10:29.46#ibcon#wrote, iclass 10, count 0 2006.211.08:10:29.46#ibcon#about to read 3, iclass 10, count 0 2006.211.08:10:29.49#ibcon#read 3, iclass 10, count 0 2006.211.08:10:29.49#ibcon#about to read 4, iclass 10, count 0 2006.211.08:10:29.49#ibcon#read 4, iclass 10, count 0 2006.211.08:10:29.49#ibcon#about to read 5, iclass 10, count 0 2006.211.08:10:29.49#ibcon#read 5, iclass 10, count 0 2006.211.08:10:29.49#ibcon#about to read 6, iclass 10, count 0 2006.211.08:10:29.49#ibcon#read 6, iclass 10, count 0 2006.211.08:10:29.49#ibcon#end of sib2, iclass 10, count 0 2006.211.08:10:29.49#ibcon#*after write, iclass 10, count 0 2006.211.08:10:29.49#ibcon#*before return 0, iclass 10, count 0 2006.211.08:10:29.49#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.211.08:10:29.49#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.211.08:10:29.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:10:29.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:10:29.49$vc4f8/valo=7,832.99 2006.211.08:10:29.49#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.211.08:10:29.49#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.211.08:10:29.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:29.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.08:10:29.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.211.08:10:29.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.08:10:29.49#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:10:29.49#ibcon#first serial, iclass 12, count 0 2006.211.08:10:29.49#ibcon#enter sib2, iclass 12, count 0 2006.211.08:10:29.49#ibcon#flushed, iclass 12, count 0 2006.211.08:10:29.49#ibcon#about to write, iclass 12, count 0 2006.211.08:10:29.49#ibcon#wrote, iclass 12, count 0 2006.211.08:10:29.49#ibcon#about to read 3, iclass 12, count 0 2006.211.08:10:29.51#ibcon#read 3, iclass 12, count 0 2006.211.08:10:29.51#ibcon#about to read 4, iclass 12, count 0 2006.211.08:10:29.51#ibcon#read 4, iclass 12, count 0 2006.211.08:10:29.51#ibcon#about to read 5, iclass 12, count 0 2006.211.08:10:29.51#ibcon#read 5, iclass 12, count 0 2006.211.08:10:29.51#ibcon#about to read 6, iclass 12, count 0 2006.211.08:10:29.51#ibcon#read 6, iclass 12, count 0 2006.211.08:10:29.51#ibcon#end of sib2, iclass 12, count 0 2006.211.08:10:29.51#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:10:29.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:10:29.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:10:29.51#ibcon#*before write, iclass 12, count 0 2006.211.08:10:29.51#ibcon#enter sib2, iclass 12, count 0 2006.211.08:10:29.51#ibcon#flushed, iclass 12, count 0 2006.211.08:10:29.51#ibcon#about to write, iclass 12, count 0 2006.211.08:10:29.51#ibcon#wrote, iclass 12, count 0 2006.211.08:10:29.51#ibcon#about to read 3, iclass 12, count 0 2006.211.08:10:29.55#ibcon#read 3, iclass 12, count 0 2006.211.08:10:29.55#ibcon#about to read 4, iclass 12, count 0 2006.211.08:10:29.55#ibcon#read 4, iclass 12, count 0 2006.211.08:10:29.55#ibcon#about to read 5, iclass 12, count 0 2006.211.08:10:29.55#ibcon#read 5, iclass 12, count 0 2006.211.08:10:29.55#ibcon#about to read 6, iclass 12, count 0 2006.211.08:10:29.55#ibcon#read 6, iclass 12, count 0 2006.211.08:10:29.55#ibcon#end of sib2, iclass 12, count 0 2006.211.08:10:29.55#ibcon#*after write, iclass 12, count 0 2006.211.08:10:29.55#ibcon#*before return 0, iclass 12, count 0 2006.211.08:10:29.55#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.211.08:10:29.55#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.211.08:10:29.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:10:29.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:10:29.55$vc4f8/va=7,6 2006.211.08:10:29.55#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.211.08:10:29.55#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.211.08:10:29.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:29.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.08:10:29.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.211.08:10:29.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.08:10:29.61#ibcon#enter wrdev, iclass 14, count 2 2006.211.08:10:29.61#ibcon#first serial, iclass 14, count 2 2006.211.08:10:29.61#ibcon#enter sib2, iclass 14, count 2 2006.211.08:10:29.61#ibcon#flushed, iclass 14, count 2 2006.211.08:10:29.61#ibcon#about to write, iclass 14, count 2 2006.211.08:10:29.61#ibcon#wrote, iclass 14, count 2 2006.211.08:10:29.61#ibcon#about to read 3, iclass 14, count 2 2006.211.08:10:29.63#ibcon#read 3, iclass 14, count 2 2006.211.08:10:29.63#ibcon#about to read 4, iclass 14, count 2 2006.211.08:10:29.63#ibcon#read 4, iclass 14, count 2 2006.211.08:10:29.63#ibcon#about to read 5, iclass 14, count 2 2006.211.08:10:29.63#ibcon#read 5, iclass 14, count 2 2006.211.08:10:29.63#ibcon#about to read 6, iclass 14, count 2 2006.211.08:10:29.63#ibcon#read 6, iclass 14, count 2 2006.211.08:10:29.63#ibcon#end of sib2, iclass 14, count 2 2006.211.08:10:29.63#ibcon#*mode == 0, iclass 14, count 2 2006.211.08:10:29.63#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.211.08:10:29.63#ibcon#[25=AT07-06\r\n] 2006.211.08:10:29.63#ibcon#*before write, iclass 14, count 2 2006.211.08:10:29.63#ibcon#enter sib2, iclass 14, count 2 2006.211.08:10:29.63#ibcon#flushed, iclass 14, count 2 2006.211.08:10:29.63#ibcon#about to write, iclass 14, count 2 2006.211.08:10:29.63#ibcon#wrote, iclass 14, count 2 2006.211.08:10:29.63#ibcon#about to read 3, iclass 14, count 2 2006.211.08:10:29.66#ibcon#read 3, iclass 14, count 2 2006.211.08:10:29.66#ibcon#about to read 4, iclass 14, count 2 2006.211.08:10:29.66#ibcon#read 4, iclass 14, count 2 2006.211.08:10:29.66#ibcon#about to read 5, iclass 14, count 2 2006.211.08:10:29.66#ibcon#read 5, iclass 14, count 2 2006.211.08:10:29.66#ibcon#about to read 6, iclass 14, count 2 2006.211.08:10:29.66#ibcon#read 6, iclass 14, count 2 2006.211.08:10:29.66#ibcon#end of sib2, iclass 14, count 2 2006.211.08:10:29.66#ibcon#*after write, iclass 14, count 2 2006.211.08:10:29.66#ibcon#*before return 0, iclass 14, count 2 2006.211.08:10:29.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.211.08:10:29.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.211.08:10:29.66#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.211.08:10:29.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:29.66#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.08:10:29.78#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.211.08:10:29.78#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.08:10:29.78#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:10:29.78#ibcon#first serial, iclass 14, count 0 2006.211.08:10:29.78#ibcon#enter sib2, iclass 14, count 0 2006.211.08:10:29.78#ibcon#flushed, iclass 14, count 0 2006.211.08:10:29.78#ibcon#about to write, iclass 14, count 0 2006.211.08:10:29.78#ibcon#wrote, iclass 14, count 0 2006.211.08:10:29.78#ibcon#about to read 3, iclass 14, count 0 2006.211.08:10:29.80#ibcon#read 3, iclass 14, count 0 2006.211.08:10:29.80#ibcon#about to read 4, iclass 14, count 0 2006.211.08:10:29.80#ibcon#read 4, iclass 14, count 0 2006.211.08:10:29.80#ibcon#about to read 5, iclass 14, count 0 2006.211.08:10:29.80#ibcon#read 5, iclass 14, count 0 2006.211.08:10:29.80#ibcon#about to read 6, iclass 14, count 0 2006.211.08:10:29.80#ibcon#read 6, iclass 14, count 0 2006.211.08:10:29.80#ibcon#end of sib2, iclass 14, count 0 2006.211.08:10:29.80#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:10:29.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:10:29.80#ibcon#[25=USB\r\n] 2006.211.08:10:29.80#ibcon#*before write, iclass 14, count 0 2006.211.08:10:29.80#ibcon#enter sib2, iclass 14, count 0 2006.211.08:10:29.80#ibcon#flushed, iclass 14, count 0 2006.211.08:10:29.80#ibcon#about to write, iclass 14, count 0 2006.211.08:10:29.80#ibcon#wrote, iclass 14, count 0 2006.211.08:10:29.80#ibcon#about to read 3, iclass 14, count 0 2006.211.08:10:29.83#ibcon#read 3, iclass 14, count 0 2006.211.08:10:29.83#ibcon#about to read 4, iclass 14, count 0 2006.211.08:10:29.83#ibcon#read 4, iclass 14, count 0 2006.211.08:10:29.83#ibcon#about to read 5, iclass 14, count 0 2006.211.08:10:29.83#ibcon#read 5, iclass 14, count 0 2006.211.08:10:29.83#ibcon#about to read 6, iclass 14, count 0 2006.211.08:10:29.83#ibcon#read 6, iclass 14, count 0 2006.211.08:10:29.83#ibcon#end of sib2, iclass 14, count 0 2006.211.08:10:29.83#ibcon#*after write, iclass 14, count 0 2006.211.08:10:29.83#ibcon#*before return 0, iclass 14, count 0 2006.211.08:10:29.83#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.211.08:10:29.83#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.211.08:10:29.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:10:29.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:10:29.83$vc4f8/valo=8,852.99 2006.211.08:10:29.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.211.08:10:29.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.211.08:10:29.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:29.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:10:29.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:10:29.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:10:29.83#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:10:29.83#ibcon#first serial, iclass 16, count 0 2006.211.08:10:29.83#ibcon#enter sib2, iclass 16, count 0 2006.211.08:10:29.83#ibcon#flushed, iclass 16, count 0 2006.211.08:10:29.83#ibcon#about to write, iclass 16, count 0 2006.211.08:10:29.83#ibcon#wrote, iclass 16, count 0 2006.211.08:10:29.83#ibcon#about to read 3, iclass 16, count 0 2006.211.08:10:29.85#ibcon#read 3, iclass 16, count 0 2006.211.08:10:29.85#ibcon#about to read 4, iclass 16, count 0 2006.211.08:10:29.85#ibcon#read 4, iclass 16, count 0 2006.211.08:10:29.85#ibcon#about to read 5, iclass 16, count 0 2006.211.08:10:29.85#ibcon#read 5, iclass 16, count 0 2006.211.08:10:29.85#ibcon#about to read 6, iclass 16, count 0 2006.211.08:10:29.85#ibcon#read 6, iclass 16, count 0 2006.211.08:10:29.85#ibcon#end of sib2, iclass 16, count 0 2006.211.08:10:29.85#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:10:29.85#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:10:29.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:10:29.85#ibcon#*before write, iclass 16, count 0 2006.211.08:10:29.85#ibcon#enter sib2, iclass 16, count 0 2006.211.08:10:29.85#ibcon#flushed, iclass 16, count 0 2006.211.08:10:29.85#ibcon#about to write, iclass 16, count 0 2006.211.08:10:29.85#ibcon#wrote, iclass 16, count 0 2006.211.08:10:29.85#ibcon#about to read 3, iclass 16, count 0 2006.211.08:10:29.89#ibcon#read 3, iclass 16, count 0 2006.211.08:10:29.89#ibcon#about to read 4, iclass 16, count 0 2006.211.08:10:29.89#ibcon#read 4, iclass 16, count 0 2006.211.08:10:29.89#ibcon#about to read 5, iclass 16, count 0 2006.211.08:10:29.89#ibcon#read 5, iclass 16, count 0 2006.211.08:10:29.89#ibcon#about to read 6, iclass 16, count 0 2006.211.08:10:29.89#ibcon#read 6, iclass 16, count 0 2006.211.08:10:29.89#ibcon#end of sib2, iclass 16, count 0 2006.211.08:10:29.89#ibcon#*after write, iclass 16, count 0 2006.211.08:10:29.89#ibcon#*before return 0, iclass 16, count 0 2006.211.08:10:29.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:10:29.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.211.08:10:29.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:10:29.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:10:29.89$vc4f8/va=8,7 2006.211.08:10:29.89#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.211.08:10:29.89#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.211.08:10:29.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:29.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.08:10:29.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.211.08:10:29.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.08:10:29.95#ibcon#enter wrdev, iclass 18, count 2 2006.211.08:10:29.95#ibcon#first serial, iclass 18, count 2 2006.211.08:10:29.95#ibcon#enter sib2, iclass 18, count 2 2006.211.08:10:29.95#ibcon#flushed, iclass 18, count 2 2006.211.08:10:29.95#ibcon#about to write, iclass 18, count 2 2006.211.08:10:29.95#ibcon#wrote, iclass 18, count 2 2006.211.08:10:29.95#ibcon#about to read 3, iclass 18, count 2 2006.211.08:10:29.97#ibcon#read 3, iclass 18, count 2 2006.211.08:10:29.97#ibcon#about to read 4, iclass 18, count 2 2006.211.08:10:29.97#ibcon#read 4, iclass 18, count 2 2006.211.08:10:29.97#ibcon#about to read 5, iclass 18, count 2 2006.211.08:10:29.97#ibcon#read 5, iclass 18, count 2 2006.211.08:10:29.97#ibcon#about to read 6, iclass 18, count 2 2006.211.08:10:29.97#ibcon#read 6, iclass 18, count 2 2006.211.08:10:29.97#ibcon#end of sib2, iclass 18, count 2 2006.211.08:10:29.97#ibcon#*mode == 0, iclass 18, count 2 2006.211.08:10:29.97#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.211.08:10:29.97#ibcon#[25=AT08-07\r\n] 2006.211.08:10:29.97#ibcon#*before write, iclass 18, count 2 2006.211.08:10:29.97#ibcon#enter sib2, iclass 18, count 2 2006.211.08:10:29.97#ibcon#flushed, iclass 18, count 2 2006.211.08:10:29.97#ibcon#about to write, iclass 18, count 2 2006.211.08:10:29.97#ibcon#wrote, iclass 18, count 2 2006.211.08:10:29.97#ibcon#about to read 3, iclass 18, count 2 2006.211.08:10:30.00#ibcon#read 3, iclass 18, count 2 2006.211.08:10:30.00#ibcon#about to read 4, iclass 18, count 2 2006.211.08:10:30.00#ibcon#read 4, iclass 18, count 2 2006.211.08:10:30.00#ibcon#about to read 5, iclass 18, count 2 2006.211.08:10:30.00#ibcon#read 5, iclass 18, count 2 2006.211.08:10:30.00#ibcon#about to read 6, iclass 18, count 2 2006.211.08:10:30.00#ibcon#read 6, iclass 18, count 2 2006.211.08:10:30.00#ibcon#end of sib2, iclass 18, count 2 2006.211.08:10:30.00#ibcon#*after write, iclass 18, count 2 2006.211.08:10:30.00#ibcon#*before return 0, iclass 18, count 2 2006.211.08:10:30.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.211.08:10:30.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.211.08:10:30.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.211.08:10:30.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:30.00#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.08:10:30.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.211.08:10:30.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.08:10:30.12#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:10:30.12#ibcon#first serial, iclass 18, count 0 2006.211.08:10:30.12#ibcon#enter sib2, iclass 18, count 0 2006.211.08:10:30.12#ibcon#flushed, iclass 18, count 0 2006.211.08:10:30.12#ibcon#about to write, iclass 18, count 0 2006.211.08:10:30.12#ibcon#wrote, iclass 18, count 0 2006.211.08:10:30.12#ibcon#about to read 3, iclass 18, count 0 2006.211.08:10:30.14#ibcon#read 3, iclass 18, count 0 2006.211.08:10:30.14#ibcon#about to read 4, iclass 18, count 0 2006.211.08:10:30.14#ibcon#read 4, iclass 18, count 0 2006.211.08:10:30.14#ibcon#about to read 5, iclass 18, count 0 2006.211.08:10:30.14#ibcon#read 5, iclass 18, count 0 2006.211.08:10:30.14#ibcon#about to read 6, iclass 18, count 0 2006.211.08:10:30.14#ibcon#read 6, iclass 18, count 0 2006.211.08:10:30.14#ibcon#end of sib2, iclass 18, count 0 2006.211.08:10:30.14#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:10:30.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:10:30.14#ibcon#[25=USB\r\n] 2006.211.08:10:30.14#ibcon#*before write, iclass 18, count 0 2006.211.08:10:30.14#ibcon#enter sib2, iclass 18, count 0 2006.211.08:10:30.14#ibcon#flushed, iclass 18, count 0 2006.211.08:10:30.14#ibcon#about to write, iclass 18, count 0 2006.211.08:10:30.14#ibcon#wrote, iclass 18, count 0 2006.211.08:10:30.14#ibcon#about to read 3, iclass 18, count 0 2006.211.08:10:30.17#ibcon#read 3, iclass 18, count 0 2006.211.08:10:30.17#ibcon#about to read 4, iclass 18, count 0 2006.211.08:10:30.17#ibcon#read 4, iclass 18, count 0 2006.211.08:10:30.17#ibcon#about to read 5, iclass 18, count 0 2006.211.08:10:30.17#ibcon#read 5, iclass 18, count 0 2006.211.08:10:30.17#ibcon#about to read 6, iclass 18, count 0 2006.211.08:10:30.17#ibcon#read 6, iclass 18, count 0 2006.211.08:10:30.17#ibcon#end of sib2, iclass 18, count 0 2006.211.08:10:30.17#ibcon#*after write, iclass 18, count 0 2006.211.08:10:30.17#ibcon#*before return 0, iclass 18, count 0 2006.211.08:10:30.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.211.08:10:30.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.211.08:10:30.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:10:30.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:10:30.17$vc4f8/vblo=1,632.99 2006.211.08:10:30.17#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.211.08:10:30.17#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.211.08:10:30.17#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:30.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:30.17#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:30.17#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:30.17#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:10:30.17#ibcon#first serial, iclass 20, count 0 2006.211.08:10:30.17#ibcon#enter sib2, iclass 20, count 0 2006.211.08:10:30.17#ibcon#flushed, iclass 20, count 0 2006.211.08:10:30.17#ibcon#about to write, iclass 20, count 0 2006.211.08:10:30.17#ibcon#wrote, iclass 20, count 0 2006.211.08:10:30.17#ibcon#about to read 3, iclass 20, count 0 2006.211.08:10:30.19#ibcon#read 3, iclass 20, count 0 2006.211.08:10:30.19#ibcon#about to read 4, iclass 20, count 0 2006.211.08:10:30.19#ibcon#read 4, iclass 20, count 0 2006.211.08:10:30.19#ibcon#about to read 5, iclass 20, count 0 2006.211.08:10:30.19#ibcon#read 5, iclass 20, count 0 2006.211.08:10:30.19#ibcon#about to read 6, iclass 20, count 0 2006.211.08:10:30.19#ibcon#read 6, iclass 20, count 0 2006.211.08:10:30.19#ibcon#end of sib2, iclass 20, count 0 2006.211.08:10:30.19#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:10:30.19#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:10:30.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:10:30.19#ibcon#*before write, iclass 20, count 0 2006.211.08:10:30.19#ibcon#enter sib2, iclass 20, count 0 2006.211.08:10:30.19#ibcon#flushed, iclass 20, count 0 2006.211.08:10:30.19#ibcon#about to write, iclass 20, count 0 2006.211.08:10:30.19#ibcon#wrote, iclass 20, count 0 2006.211.08:10:30.19#ibcon#about to read 3, iclass 20, count 0 2006.211.08:10:30.23#ibcon#read 3, iclass 20, count 0 2006.211.08:10:30.23#ibcon#about to read 4, iclass 20, count 0 2006.211.08:10:30.23#ibcon#read 4, iclass 20, count 0 2006.211.08:10:30.23#ibcon#about to read 5, iclass 20, count 0 2006.211.08:10:30.23#ibcon#read 5, iclass 20, count 0 2006.211.08:10:30.23#ibcon#about to read 6, iclass 20, count 0 2006.211.08:10:30.23#ibcon#read 6, iclass 20, count 0 2006.211.08:10:30.23#ibcon#end of sib2, iclass 20, count 0 2006.211.08:10:30.23#ibcon#*after write, iclass 20, count 0 2006.211.08:10:30.23#ibcon#*before return 0, iclass 20, count 0 2006.211.08:10:30.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:30.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.211.08:10:30.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:10:30.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:10:30.23$vc4f8/vb=1,4 2006.211.08:10:30.23#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.211.08:10:30.23#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.211.08:10:30.23#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:30.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:30.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:30.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:30.23#ibcon#enter wrdev, iclass 22, count 2 2006.211.08:10:30.23#ibcon#first serial, iclass 22, count 2 2006.211.08:10:30.23#ibcon#enter sib2, iclass 22, count 2 2006.211.08:10:30.23#ibcon#flushed, iclass 22, count 2 2006.211.08:10:30.23#ibcon#about to write, iclass 22, count 2 2006.211.08:10:30.23#ibcon#wrote, iclass 22, count 2 2006.211.08:10:30.23#ibcon#about to read 3, iclass 22, count 2 2006.211.08:10:30.25#ibcon#read 3, iclass 22, count 2 2006.211.08:10:30.25#ibcon#about to read 4, iclass 22, count 2 2006.211.08:10:30.25#ibcon#read 4, iclass 22, count 2 2006.211.08:10:30.25#ibcon#about to read 5, iclass 22, count 2 2006.211.08:10:30.25#ibcon#read 5, iclass 22, count 2 2006.211.08:10:30.25#ibcon#about to read 6, iclass 22, count 2 2006.211.08:10:30.25#ibcon#read 6, iclass 22, count 2 2006.211.08:10:30.25#ibcon#end of sib2, iclass 22, count 2 2006.211.08:10:30.25#ibcon#*mode == 0, iclass 22, count 2 2006.211.08:10:30.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.211.08:10:30.25#ibcon#[27=AT01-04\r\n] 2006.211.08:10:30.25#ibcon#*before write, iclass 22, count 2 2006.211.08:10:30.25#ibcon#enter sib2, iclass 22, count 2 2006.211.08:10:30.25#ibcon#flushed, iclass 22, count 2 2006.211.08:10:30.25#ibcon#about to write, iclass 22, count 2 2006.211.08:10:30.25#ibcon#wrote, iclass 22, count 2 2006.211.08:10:30.25#ibcon#about to read 3, iclass 22, count 2 2006.211.08:10:30.28#ibcon#read 3, iclass 22, count 2 2006.211.08:10:30.28#ibcon#about to read 4, iclass 22, count 2 2006.211.08:10:30.28#ibcon#read 4, iclass 22, count 2 2006.211.08:10:30.28#ibcon#about to read 5, iclass 22, count 2 2006.211.08:10:30.28#ibcon#read 5, iclass 22, count 2 2006.211.08:10:30.28#ibcon#about to read 6, iclass 22, count 2 2006.211.08:10:30.28#ibcon#read 6, iclass 22, count 2 2006.211.08:10:30.28#ibcon#end of sib2, iclass 22, count 2 2006.211.08:10:30.28#ibcon#*after write, iclass 22, count 2 2006.211.08:10:30.28#ibcon#*before return 0, iclass 22, count 2 2006.211.08:10:30.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:30.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.211.08:10:30.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.211.08:10:30.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:30.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:30.40#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:30.40#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:30.40#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:10:30.40#ibcon#first serial, iclass 22, count 0 2006.211.08:10:30.40#ibcon#enter sib2, iclass 22, count 0 2006.211.08:10:30.40#ibcon#flushed, iclass 22, count 0 2006.211.08:10:30.40#ibcon#about to write, iclass 22, count 0 2006.211.08:10:30.40#ibcon#wrote, iclass 22, count 0 2006.211.08:10:30.40#ibcon#about to read 3, iclass 22, count 0 2006.211.08:10:30.42#ibcon#read 3, iclass 22, count 0 2006.211.08:10:30.42#ibcon#about to read 4, iclass 22, count 0 2006.211.08:10:30.42#ibcon#read 4, iclass 22, count 0 2006.211.08:10:30.42#ibcon#about to read 5, iclass 22, count 0 2006.211.08:10:30.42#ibcon#read 5, iclass 22, count 0 2006.211.08:10:30.42#ibcon#about to read 6, iclass 22, count 0 2006.211.08:10:30.42#ibcon#read 6, iclass 22, count 0 2006.211.08:10:30.42#ibcon#end of sib2, iclass 22, count 0 2006.211.08:10:30.42#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:10:30.42#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:10:30.42#ibcon#[27=USB\r\n] 2006.211.08:10:30.42#ibcon#*before write, iclass 22, count 0 2006.211.08:10:30.42#ibcon#enter sib2, iclass 22, count 0 2006.211.08:10:30.42#ibcon#flushed, iclass 22, count 0 2006.211.08:10:30.42#ibcon#about to write, iclass 22, count 0 2006.211.08:10:30.42#ibcon#wrote, iclass 22, count 0 2006.211.08:10:30.42#ibcon#about to read 3, iclass 22, count 0 2006.211.08:10:30.45#ibcon#read 3, iclass 22, count 0 2006.211.08:10:30.45#ibcon#about to read 4, iclass 22, count 0 2006.211.08:10:30.45#ibcon#read 4, iclass 22, count 0 2006.211.08:10:30.45#ibcon#about to read 5, iclass 22, count 0 2006.211.08:10:30.45#ibcon#read 5, iclass 22, count 0 2006.211.08:10:30.45#ibcon#about to read 6, iclass 22, count 0 2006.211.08:10:30.45#ibcon#read 6, iclass 22, count 0 2006.211.08:10:30.45#ibcon#end of sib2, iclass 22, count 0 2006.211.08:10:30.45#ibcon#*after write, iclass 22, count 0 2006.211.08:10:30.45#ibcon#*before return 0, iclass 22, count 0 2006.211.08:10:30.45#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:30.45#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.211.08:10:30.45#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:10:30.45#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:10:30.45$vc4f8/vblo=2,640.99 2006.211.08:10:30.45#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.211.08:10:30.45#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.211.08:10:30.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:30.45#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:30.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:30.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:30.45#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:10:30.45#ibcon#first serial, iclass 24, count 0 2006.211.08:10:30.45#ibcon#enter sib2, iclass 24, count 0 2006.211.08:10:30.45#ibcon#flushed, iclass 24, count 0 2006.211.08:10:30.45#ibcon#about to write, iclass 24, count 0 2006.211.08:10:30.45#ibcon#wrote, iclass 24, count 0 2006.211.08:10:30.45#ibcon#about to read 3, iclass 24, count 0 2006.211.08:10:30.47#ibcon#read 3, iclass 24, count 0 2006.211.08:10:30.47#ibcon#about to read 4, iclass 24, count 0 2006.211.08:10:30.47#ibcon#read 4, iclass 24, count 0 2006.211.08:10:30.47#ibcon#about to read 5, iclass 24, count 0 2006.211.08:10:30.47#ibcon#read 5, iclass 24, count 0 2006.211.08:10:30.47#ibcon#about to read 6, iclass 24, count 0 2006.211.08:10:30.47#ibcon#read 6, iclass 24, count 0 2006.211.08:10:30.47#ibcon#end of sib2, iclass 24, count 0 2006.211.08:10:30.47#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:10:30.47#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:10:30.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:10:30.47#ibcon#*before write, iclass 24, count 0 2006.211.08:10:30.47#ibcon#enter sib2, iclass 24, count 0 2006.211.08:10:30.47#ibcon#flushed, iclass 24, count 0 2006.211.08:10:30.47#ibcon#about to write, iclass 24, count 0 2006.211.08:10:30.47#ibcon#wrote, iclass 24, count 0 2006.211.08:10:30.47#ibcon#about to read 3, iclass 24, count 0 2006.211.08:10:30.51#ibcon#read 3, iclass 24, count 0 2006.211.08:10:30.51#ibcon#about to read 4, iclass 24, count 0 2006.211.08:10:30.51#ibcon#read 4, iclass 24, count 0 2006.211.08:10:30.51#ibcon#about to read 5, iclass 24, count 0 2006.211.08:10:30.51#ibcon#read 5, iclass 24, count 0 2006.211.08:10:30.51#ibcon#about to read 6, iclass 24, count 0 2006.211.08:10:30.51#ibcon#read 6, iclass 24, count 0 2006.211.08:10:30.51#ibcon#end of sib2, iclass 24, count 0 2006.211.08:10:30.51#ibcon#*after write, iclass 24, count 0 2006.211.08:10:30.51#ibcon#*before return 0, iclass 24, count 0 2006.211.08:10:30.51#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:30.51#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.211.08:10:30.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:10:30.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:10:30.51$vc4f8/vb=2,4 2006.211.08:10:30.51#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.08:10:30.51#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.08:10:30.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:30.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:30.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:30.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:30.57#ibcon#enter wrdev, iclass 26, count 2 2006.211.08:10:30.57#ibcon#first serial, iclass 26, count 2 2006.211.08:10:30.57#ibcon#enter sib2, iclass 26, count 2 2006.211.08:10:30.57#ibcon#flushed, iclass 26, count 2 2006.211.08:10:30.57#ibcon#about to write, iclass 26, count 2 2006.211.08:10:30.57#ibcon#wrote, iclass 26, count 2 2006.211.08:10:30.57#ibcon#about to read 3, iclass 26, count 2 2006.211.08:10:30.59#ibcon#read 3, iclass 26, count 2 2006.211.08:10:30.59#ibcon#about to read 4, iclass 26, count 2 2006.211.08:10:30.59#ibcon#read 4, iclass 26, count 2 2006.211.08:10:30.59#ibcon#about to read 5, iclass 26, count 2 2006.211.08:10:30.59#ibcon#read 5, iclass 26, count 2 2006.211.08:10:30.59#ibcon#about to read 6, iclass 26, count 2 2006.211.08:10:30.59#ibcon#read 6, iclass 26, count 2 2006.211.08:10:30.59#ibcon#end of sib2, iclass 26, count 2 2006.211.08:10:30.59#ibcon#*mode == 0, iclass 26, count 2 2006.211.08:10:30.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.08:10:30.59#ibcon#[27=AT02-04\r\n] 2006.211.08:10:30.59#ibcon#*before write, iclass 26, count 2 2006.211.08:10:30.59#ibcon#enter sib2, iclass 26, count 2 2006.211.08:10:30.59#ibcon#flushed, iclass 26, count 2 2006.211.08:10:30.59#ibcon#about to write, iclass 26, count 2 2006.211.08:10:30.59#ibcon#wrote, iclass 26, count 2 2006.211.08:10:30.59#ibcon#about to read 3, iclass 26, count 2 2006.211.08:10:30.62#ibcon#read 3, iclass 26, count 2 2006.211.08:10:30.62#ibcon#about to read 4, iclass 26, count 2 2006.211.08:10:30.62#ibcon#read 4, iclass 26, count 2 2006.211.08:10:30.62#ibcon#about to read 5, iclass 26, count 2 2006.211.08:10:30.62#ibcon#read 5, iclass 26, count 2 2006.211.08:10:30.62#ibcon#about to read 6, iclass 26, count 2 2006.211.08:10:30.62#ibcon#read 6, iclass 26, count 2 2006.211.08:10:30.62#ibcon#end of sib2, iclass 26, count 2 2006.211.08:10:30.62#ibcon#*after write, iclass 26, count 2 2006.211.08:10:30.62#ibcon#*before return 0, iclass 26, count 2 2006.211.08:10:30.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:30.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:10:30.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.08:10:30.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:30.62#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:30.74#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:30.74#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:30.74#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:10:30.74#ibcon#first serial, iclass 26, count 0 2006.211.08:10:30.74#ibcon#enter sib2, iclass 26, count 0 2006.211.08:10:30.74#ibcon#flushed, iclass 26, count 0 2006.211.08:10:30.74#ibcon#about to write, iclass 26, count 0 2006.211.08:10:30.74#ibcon#wrote, iclass 26, count 0 2006.211.08:10:30.74#ibcon#about to read 3, iclass 26, count 0 2006.211.08:10:30.76#ibcon#read 3, iclass 26, count 0 2006.211.08:10:30.76#ibcon#about to read 4, iclass 26, count 0 2006.211.08:10:30.76#ibcon#read 4, iclass 26, count 0 2006.211.08:10:30.76#ibcon#about to read 5, iclass 26, count 0 2006.211.08:10:30.76#ibcon#read 5, iclass 26, count 0 2006.211.08:10:30.76#ibcon#about to read 6, iclass 26, count 0 2006.211.08:10:30.76#ibcon#read 6, iclass 26, count 0 2006.211.08:10:30.76#ibcon#end of sib2, iclass 26, count 0 2006.211.08:10:30.76#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:10:30.76#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:10:30.76#ibcon#[27=USB\r\n] 2006.211.08:10:30.76#ibcon#*before write, iclass 26, count 0 2006.211.08:10:30.76#ibcon#enter sib2, iclass 26, count 0 2006.211.08:10:30.76#ibcon#flushed, iclass 26, count 0 2006.211.08:10:30.76#ibcon#about to write, iclass 26, count 0 2006.211.08:10:30.76#ibcon#wrote, iclass 26, count 0 2006.211.08:10:30.76#ibcon#about to read 3, iclass 26, count 0 2006.211.08:10:30.79#ibcon#read 3, iclass 26, count 0 2006.211.08:10:30.79#ibcon#about to read 4, iclass 26, count 0 2006.211.08:10:30.79#ibcon#read 4, iclass 26, count 0 2006.211.08:10:30.79#ibcon#about to read 5, iclass 26, count 0 2006.211.08:10:30.79#ibcon#read 5, iclass 26, count 0 2006.211.08:10:30.79#ibcon#about to read 6, iclass 26, count 0 2006.211.08:10:30.79#ibcon#read 6, iclass 26, count 0 2006.211.08:10:30.79#ibcon#end of sib2, iclass 26, count 0 2006.211.08:10:30.79#ibcon#*after write, iclass 26, count 0 2006.211.08:10:30.79#ibcon#*before return 0, iclass 26, count 0 2006.211.08:10:30.79#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:30.79#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:10:30.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:10:30.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:10:30.79$vc4f8/vblo=3,656.99 2006.211.08:10:30.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.211.08:10:30.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.211.08:10:30.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:30.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:30.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:30.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:30.79#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:10:30.79#ibcon#first serial, iclass 28, count 0 2006.211.08:10:30.79#ibcon#enter sib2, iclass 28, count 0 2006.211.08:10:30.79#ibcon#flushed, iclass 28, count 0 2006.211.08:10:30.79#ibcon#about to write, iclass 28, count 0 2006.211.08:10:30.79#ibcon#wrote, iclass 28, count 0 2006.211.08:10:30.79#ibcon#about to read 3, iclass 28, count 0 2006.211.08:10:30.81#ibcon#read 3, iclass 28, count 0 2006.211.08:10:30.81#ibcon#about to read 4, iclass 28, count 0 2006.211.08:10:30.81#ibcon#read 4, iclass 28, count 0 2006.211.08:10:30.81#ibcon#about to read 5, iclass 28, count 0 2006.211.08:10:30.81#ibcon#read 5, iclass 28, count 0 2006.211.08:10:30.81#ibcon#about to read 6, iclass 28, count 0 2006.211.08:10:30.81#ibcon#read 6, iclass 28, count 0 2006.211.08:10:30.81#ibcon#end of sib2, iclass 28, count 0 2006.211.08:10:30.81#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:10:30.81#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:10:30.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:10:30.81#ibcon#*before write, iclass 28, count 0 2006.211.08:10:30.81#ibcon#enter sib2, iclass 28, count 0 2006.211.08:10:30.81#ibcon#flushed, iclass 28, count 0 2006.211.08:10:30.81#ibcon#about to write, iclass 28, count 0 2006.211.08:10:30.81#ibcon#wrote, iclass 28, count 0 2006.211.08:10:30.81#ibcon#about to read 3, iclass 28, count 0 2006.211.08:10:30.85#ibcon#read 3, iclass 28, count 0 2006.211.08:10:30.85#ibcon#about to read 4, iclass 28, count 0 2006.211.08:10:30.85#ibcon#read 4, iclass 28, count 0 2006.211.08:10:30.85#ibcon#about to read 5, iclass 28, count 0 2006.211.08:10:30.85#ibcon#read 5, iclass 28, count 0 2006.211.08:10:30.85#ibcon#about to read 6, iclass 28, count 0 2006.211.08:10:30.85#ibcon#read 6, iclass 28, count 0 2006.211.08:10:30.85#ibcon#end of sib2, iclass 28, count 0 2006.211.08:10:30.85#ibcon#*after write, iclass 28, count 0 2006.211.08:10:30.85#ibcon#*before return 0, iclass 28, count 0 2006.211.08:10:30.85#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:30.85#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.211.08:10:30.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:10:30.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:10:30.85$vc4f8/vb=3,3 2006.211.08:10:30.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.211.08:10:30.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.211.08:10:30.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:30.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:30.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:30.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:30.91#ibcon#enter wrdev, iclass 30, count 2 2006.211.08:10:30.91#ibcon#first serial, iclass 30, count 2 2006.211.08:10:30.91#ibcon#enter sib2, iclass 30, count 2 2006.211.08:10:30.91#ibcon#flushed, iclass 30, count 2 2006.211.08:10:30.91#ibcon#about to write, iclass 30, count 2 2006.211.08:10:30.91#ibcon#wrote, iclass 30, count 2 2006.211.08:10:30.91#ibcon#about to read 3, iclass 30, count 2 2006.211.08:10:30.93#ibcon#read 3, iclass 30, count 2 2006.211.08:10:30.93#ibcon#about to read 4, iclass 30, count 2 2006.211.08:10:30.93#ibcon#read 4, iclass 30, count 2 2006.211.08:10:30.93#ibcon#about to read 5, iclass 30, count 2 2006.211.08:10:30.93#ibcon#read 5, iclass 30, count 2 2006.211.08:10:30.93#ibcon#about to read 6, iclass 30, count 2 2006.211.08:10:30.93#ibcon#read 6, iclass 30, count 2 2006.211.08:10:30.93#ibcon#end of sib2, iclass 30, count 2 2006.211.08:10:30.93#ibcon#*mode == 0, iclass 30, count 2 2006.211.08:10:30.93#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.211.08:10:30.93#ibcon#[27=AT03-03\r\n] 2006.211.08:10:30.93#ibcon#*before write, iclass 30, count 2 2006.211.08:10:30.93#ibcon#enter sib2, iclass 30, count 2 2006.211.08:10:30.93#ibcon#flushed, iclass 30, count 2 2006.211.08:10:30.93#ibcon#about to write, iclass 30, count 2 2006.211.08:10:30.93#ibcon#wrote, iclass 30, count 2 2006.211.08:10:30.93#ibcon#about to read 3, iclass 30, count 2 2006.211.08:10:30.96#ibcon#read 3, iclass 30, count 2 2006.211.08:10:30.96#ibcon#about to read 4, iclass 30, count 2 2006.211.08:10:30.96#ibcon#read 4, iclass 30, count 2 2006.211.08:10:30.96#ibcon#about to read 5, iclass 30, count 2 2006.211.08:10:30.96#ibcon#read 5, iclass 30, count 2 2006.211.08:10:30.96#ibcon#about to read 6, iclass 30, count 2 2006.211.08:10:30.96#ibcon#read 6, iclass 30, count 2 2006.211.08:10:30.96#ibcon#end of sib2, iclass 30, count 2 2006.211.08:10:30.96#ibcon#*after write, iclass 30, count 2 2006.211.08:10:30.96#ibcon#*before return 0, iclass 30, count 2 2006.211.08:10:30.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:30.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.211.08:10:30.96#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.211.08:10:30.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:30.96#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:31.08#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:31.08#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:31.08#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:10:31.08#ibcon#first serial, iclass 30, count 0 2006.211.08:10:31.08#ibcon#enter sib2, iclass 30, count 0 2006.211.08:10:31.08#ibcon#flushed, iclass 30, count 0 2006.211.08:10:31.08#ibcon#about to write, iclass 30, count 0 2006.211.08:10:31.08#ibcon#wrote, iclass 30, count 0 2006.211.08:10:31.08#ibcon#about to read 3, iclass 30, count 0 2006.211.08:10:31.10#ibcon#read 3, iclass 30, count 0 2006.211.08:10:31.10#ibcon#about to read 4, iclass 30, count 0 2006.211.08:10:31.10#ibcon#read 4, iclass 30, count 0 2006.211.08:10:31.10#ibcon#about to read 5, iclass 30, count 0 2006.211.08:10:31.10#ibcon#read 5, iclass 30, count 0 2006.211.08:10:31.10#ibcon#about to read 6, iclass 30, count 0 2006.211.08:10:31.10#ibcon#read 6, iclass 30, count 0 2006.211.08:10:31.10#ibcon#end of sib2, iclass 30, count 0 2006.211.08:10:31.10#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:10:31.10#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:10:31.10#ibcon#[27=USB\r\n] 2006.211.08:10:31.10#ibcon#*before write, iclass 30, count 0 2006.211.08:10:31.10#ibcon#enter sib2, iclass 30, count 0 2006.211.08:10:31.10#ibcon#flushed, iclass 30, count 0 2006.211.08:10:31.10#ibcon#about to write, iclass 30, count 0 2006.211.08:10:31.10#ibcon#wrote, iclass 30, count 0 2006.211.08:10:31.10#ibcon#about to read 3, iclass 30, count 0 2006.211.08:10:31.13#ibcon#read 3, iclass 30, count 0 2006.211.08:10:31.13#ibcon#about to read 4, iclass 30, count 0 2006.211.08:10:31.13#ibcon#read 4, iclass 30, count 0 2006.211.08:10:31.13#ibcon#about to read 5, iclass 30, count 0 2006.211.08:10:31.13#ibcon#read 5, iclass 30, count 0 2006.211.08:10:31.13#ibcon#about to read 6, iclass 30, count 0 2006.211.08:10:31.13#ibcon#read 6, iclass 30, count 0 2006.211.08:10:31.13#ibcon#end of sib2, iclass 30, count 0 2006.211.08:10:31.13#ibcon#*after write, iclass 30, count 0 2006.211.08:10:31.13#ibcon#*before return 0, iclass 30, count 0 2006.211.08:10:31.13#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:31.13#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.211.08:10:31.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:10:31.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:10:31.13$vc4f8/vblo=4,712.99 2006.211.08:10:31.13#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.08:10:31.13#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.08:10:31.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:31.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:31.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:31.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:31.13#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:10:31.13#ibcon#first serial, iclass 32, count 0 2006.211.08:10:31.13#ibcon#enter sib2, iclass 32, count 0 2006.211.08:10:31.13#ibcon#flushed, iclass 32, count 0 2006.211.08:10:31.13#ibcon#about to write, iclass 32, count 0 2006.211.08:10:31.13#ibcon#wrote, iclass 32, count 0 2006.211.08:10:31.13#ibcon#about to read 3, iclass 32, count 0 2006.211.08:10:31.15#ibcon#read 3, iclass 32, count 0 2006.211.08:10:31.15#ibcon#about to read 4, iclass 32, count 0 2006.211.08:10:31.15#ibcon#read 4, iclass 32, count 0 2006.211.08:10:31.15#ibcon#about to read 5, iclass 32, count 0 2006.211.08:10:31.15#ibcon#read 5, iclass 32, count 0 2006.211.08:10:31.15#ibcon#about to read 6, iclass 32, count 0 2006.211.08:10:31.15#ibcon#read 6, iclass 32, count 0 2006.211.08:10:31.15#ibcon#end of sib2, iclass 32, count 0 2006.211.08:10:31.15#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:10:31.15#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:10:31.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:10:31.15#ibcon#*before write, iclass 32, count 0 2006.211.08:10:31.15#ibcon#enter sib2, iclass 32, count 0 2006.211.08:10:31.15#ibcon#flushed, iclass 32, count 0 2006.211.08:10:31.15#ibcon#about to write, iclass 32, count 0 2006.211.08:10:31.15#ibcon#wrote, iclass 32, count 0 2006.211.08:10:31.15#ibcon#about to read 3, iclass 32, count 0 2006.211.08:10:31.19#ibcon#read 3, iclass 32, count 0 2006.211.08:10:31.19#ibcon#about to read 4, iclass 32, count 0 2006.211.08:10:31.19#ibcon#read 4, iclass 32, count 0 2006.211.08:10:31.19#ibcon#about to read 5, iclass 32, count 0 2006.211.08:10:31.19#ibcon#read 5, iclass 32, count 0 2006.211.08:10:31.19#ibcon#about to read 6, iclass 32, count 0 2006.211.08:10:31.19#ibcon#read 6, iclass 32, count 0 2006.211.08:10:31.19#ibcon#end of sib2, iclass 32, count 0 2006.211.08:10:31.19#ibcon#*after write, iclass 32, count 0 2006.211.08:10:31.19#ibcon#*before return 0, iclass 32, count 0 2006.211.08:10:31.19#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:31.19#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:10:31.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:10:31.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:10:31.19$vc4f8/vb=4,3 2006.211.08:10:31.19#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.211.08:10:31.19#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.211.08:10:31.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:31.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:31.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:31.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:31.25#ibcon#enter wrdev, iclass 34, count 2 2006.211.08:10:31.25#ibcon#first serial, iclass 34, count 2 2006.211.08:10:31.25#ibcon#enter sib2, iclass 34, count 2 2006.211.08:10:31.25#ibcon#flushed, iclass 34, count 2 2006.211.08:10:31.25#ibcon#about to write, iclass 34, count 2 2006.211.08:10:31.25#ibcon#wrote, iclass 34, count 2 2006.211.08:10:31.25#ibcon#about to read 3, iclass 34, count 2 2006.211.08:10:31.27#ibcon#read 3, iclass 34, count 2 2006.211.08:10:31.27#ibcon#about to read 4, iclass 34, count 2 2006.211.08:10:31.27#ibcon#read 4, iclass 34, count 2 2006.211.08:10:31.27#ibcon#about to read 5, iclass 34, count 2 2006.211.08:10:31.27#ibcon#read 5, iclass 34, count 2 2006.211.08:10:31.27#ibcon#about to read 6, iclass 34, count 2 2006.211.08:10:31.27#ibcon#read 6, iclass 34, count 2 2006.211.08:10:31.27#ibcon#end of sib2, iclass 34, count 2 2006.211.08:10:31.27#ibcon#*mode == 0, iclass 34, count 2 2006.211.08:10:31.27#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.211.08:10:31.27#ibcon#[27=AT04-03\r\n] 2006.211.08:10:31.27#ibcon#*before write, iclass 34, count 2 2006.211.08:10:31.27#ibcon#enter sib2, iclass 34, count 2 2006.211.08:10:31.27#ibcon#flushed, iclass 34, count 2 2006.211.08:10:31.27#ibcon#about to write, iclass 34, count 2 2006.211.08:10:31.27#ibcon#wrote, iclass 34, count 2 2006.211.08:10:31.27#ibcon#about to read 3, iclass 34, count 2 2006.211.08:10:31.30#ibcon#read 3, iclass 34, count 2 2006.211.08:10:31.30#ibcon#about to read 4, iclass 34, count 2 2006.211.08:10:31.30#ibcon#read 4, iclass 34, count 2 2006.211.08:10:31.30#ibcon#about to read 5, iclass 34, count 2 2006.211.08:10:31.30#ibcon#read 5, iclass 34, count 2 2006.211.08:10:31.30#ibcon#about to read 6, iclass 34, count 2 2006.211.08:10:31.30#ibcon#read 6, iclass 34, count 2 2006.211.08:10:31.30#ibcon#end of sib2, iclass 34, count 2 2006.211.08:10:31.30#ibcon#*after write, iclass 34, count 2 2006.211.08:10:31.30#ibcon#*before return 0, iclass 34, count 2 2006.211.08:10:31.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:31.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.211.08:10:31.30#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.211.08:10:31.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:31.30#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:31.42#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:31.42#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:31.42#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:10:31.42#ibcon#first serial, iclass 34, count 0 2006.211.08:10:31.42#ibcon#enter sib2, iclass 34, count 0 2006.211.08:10:31.42#ibcon#flushed, iclass 34, count 0 2006.211.08:10:31.42#ibcon#about to write, iclass 34, count 0 2006.211.08:10:31.42#ibcon#wrote, iclass 34, count 0 2006.211.08:10:31.42#ibcon#about to read 3, iclass 34, count 0 2006.211.08:10:31.44#ibcon#read 3, iclass 34, count 0 2006.211.08:10:31.44#ibcon#about to read 4, iclass 34, count 0 2006.211.08:10:31.44#ibcon#read 4, iclass 34, count 0 2006.211.08:10:31.44#ibcon#about to read 5, iclass 34, count 0 2006.211.08:10:31.44#ibcon#read 5, iclass 34, count 0 2006.211.08:10:31.44#ibcon#about to read 6, iclass 34, count 0 2006.211.08:10:31.44#ibcon#read 6, iclass 34, count 0 2006.211.08:10:31.44#ibcon#end of sib2, iclass 34, count 0 2006.211.08:10:31.44#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:10:31.44#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:10:31.44#ibcon#[27=USB\r\n] 2006.211.08:10:31.44#ibcon#*before write, iclass 34, count 0 2006.211.08:10:31.44#ibcon#enter sib2, iclass 34, count 0 2006.211.08:10:31.44#ibcon#flushed, iclass 34, count 0 2006.211.08:10:31.44#ibcon#about to write, iclass 34, count 0 2006.211.08:10:31.44#ibcon#wrote, iclass 34, count 0 2006.211.08:10:31.44#ibcon#about to read 3, iclass 34, count 0 2006.211.08:10:31.47#ibcon#read 3, iclass 34, count 0 2006.211.08:10:31.47#ibcon#about to read 4, iclass 34, count 0 2006.211.08:10:31.47#ibcon#read 4, iclass 34, count 0 2006.211.08:10:31.47#ibcon#about to read 5, iclass 34, count 0 2006.211.08:10:31.47#ibcon#read 5, iclass 34, count 0 2006.211.08:10:31.47#ibcon#about to read 6, iclass 34, count 0 2006.211.08:10:31.47#ibcon#read 6, iclass 34, count 0 2006.211.08:10:31.47#ibcon#end of sib2, iclass 34, count 0 2006.211.08:10:31.47#ibcon#*after write, iclass 34, count 0 2006.211.08:10:31.47#ibcon#*before return 0, iclass 34, count 0 2006.211.08:10:31.47#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:31.47#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.211.08:10:31.47#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:10:31.47#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:10:31.47$vc4f8/vblo=5,744.99 2006.211.08:10:31.47#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.08:10:31.47#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.08:10:31.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:31.47#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:31.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:31.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:31.47#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:10:31.47#ibcon#first serial, iclass 36, count 0 2006.211.08:10:31.47#ibcon#enter sib2, iclass 36, count 0 2006.211.08:10:31.47#ibcon#flushed, iclass 36, count 0 2006.211.08:10:31.47#ibcon#about to write, iclass 36, count 0 2006.211.08:10:31.47#ibcon#wrote, iclass 36, count 0 2006.211.08:10:31.47#ibcon#about to read 3, iclass 36, count 0 2006.211.08:10:31.49#ibcon#read 3, iclass 36, count 0 2006.211.08:10:31.49#ibcon#about to read 4, iclass 36, count 0 2006.211.08:10:31.49#ibcon#read 4, iclass 36, count 0 2006.211.08:10:31.49#ibcon#about to read 5, iclass 36, count 0 2006.211.08:10:31.49#ibcon#read 5, iclass 36, count 0 2006.211.08:10:31.49#ibcon#about to read 6, iclass 36, count 0 2006.211.08:10:31.49#ibcon#read 6, iclass 36, count 0 2006.211.08:10:31.49#ibcon#end of sib2, iclass 36, count 0 2006.211.08:10:31.49#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:10:31.49#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:10:31.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:10:31.49#ibcon#*before write, iclass 36, count 0 2006.211.08:10:31.49#ibcon#enter sib2, iclass 36, count 0 2006.211.08:10:31.49#ibcon#flushed, iclass 36, count 0 2006.211.08:10:31.49#ibcon#about to write, iclass 36, count 0 2006.211.08:10:31.49#ibcon#wrote, iclass 36, count 0 2006.211.08:10:31.49#ibcon#about to read 3, iclass 36, count 0 2006.211.08:10:31.53#ibcon#read 3, iclass 36, count 0 2006.211.08:10:31.53#ibcon#about to read 4, iclass 36, count 0 2006.211.08:10:31.53#ibcon#read 4, iclass 36, count 0 2006.211.08:10:31.53#ibcon#about to read 5, iclass 36, count 0 2006.211.08:10:31.53#ibcon#read 5, iclass 36, count 0 2006.211.08:10:31.53#ibcon#about to read 6, iclass 36, count 0 2006.211.08:10:31.53#ibcon#read 6, iclass 36, count 0 2006.211.08:10:31.53#ibcon#end of sib2, iclass 36, count 0 2006.211.08:10:31.53#ibcon#*after write, iclass 36, count 0 2006.211.08:10:31.53#ibcon#*before return 0, iclass 36, count 0 2006.211.08:10:31.53#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:31.53#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:10:31.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:10:31.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:10:31.53$vc4f8/vb=5,3 2006.211.08:10:31.53#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.211.08:10:31.53#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.211.08:10:31.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:31.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:31.59#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:31.59#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:31.59#ibcon#enter wrdev, iclass 38, count 2 2006.211.08:10:31.59#ibcon#first serial, iclass 38, count 2 2006.211.08:10:31.59#ibcon#enter sib2, iclass 38, count 2 2006.211.08:10:31.59#ibcon#flushed, iclass 38, count 2 2006.211.08:10:31.59#ibcon#about to write, iclass 38, count 2 2006.211.08:10:31.59#ibcon#wrote, iclass 38, count 2 2006.211.08:10:31.59#ibcon#about to read 3, iclass 38, count 2 2006.211.08:10:31.61#ibcon#read 3, iclass 38, count 2 2006.211.08:10:31.61#ibcon#about to read 4, iclass 38, count 2 2006.211.08:10:31.61#ibcon#read 4, iclass 38, count 2 2006.211.08:10:31.61#ibcon#about to read 5, iclass 38, count 2 2006.211.08:10:31.61#ibcon#read 5, iclass 38, count 2 2006.211.08:10:31.61#ibcon#about to read 6, iclass 38, count 2 2006.211.08:10:31.61#ibcon#read 6, iclass 38, count 2 2006.211.08:10:31.61#ibcon#end of sib2, iclass 38, count 2 2006.211.08:10:31.61#ibcon#*mode == 0, iclass 38, count 2 2006.211.08:10:31.61#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.211.08:10:31.61#ibcon#[27=AT05-03\r\n] 2006.211.08:10:31.61#ibcon#*before write, iclass 38, count 2 2006.211.08:10:31.61#ibcon#enter sib2, iclass 38, count 2 2006.211.08:10:31.61#ibcon#flushed, iclass 38, count 2 2006.211.08:10:31.61#ibcon#about to write, iclass 38, count 2 2006.211.08:10:31.61#ibcon#wrote, iclass 38, count 2 2006.211.08:10:31.61#ibcon#about to read 3, iclass 38, count 2 2006.211.08:10:31.64#ibcon#read 3, iclass 38, count 2 2006.211.08:10:31.64#ibcon#about to read 4, iclass 38, count 2 2006.211.08:10:31.64#ibcon#read 4, iclass 38, count 2 2006.211.08:10:31.64#ibcon#about to read 5, iclass 38, count 2 2006.211.08:10:31.64#ibcon#read 5, iclass 38, count 2 2006.211.08:10:31.64#ibcon#about to read 6, iclass 38, count 2 2006.211.08:10:31.64#ibcon#read 6, iclass 38, count 2 2006.211.08:10:31.64#ibcon#end of sib2, iclass 38, count 2 2006.211.08:10:31.64#ibcon#*after write, iclass 38, count 2 2006.211.08:10:31.64#ibcon#*before return 0, iclass 38, count 2 2006.211.08:10:31.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:31.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.211.08:10:31.64#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.211.08:10:31.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:31.64#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:31.76#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:31.76#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:31.76#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:10:31.76#ibcon#first serial, iclass 38, count 0 2006.211.08:10:31.76#ibcon#enter sib2, iclass 38, count 0 2006.211.08:10:31.76#ibcon#flushed, iclass 38, count 0 2006.211.08:10:31.76#ibcon#about to write, iclass 38, count 0 2006.211.08:10:31.76#ibcon#wrote, iclass 38, count 0 2006.211.08:10:31.76#ibcon#about to read 3, iclass 38, count 0 2006.211.08:10:31.78#ibcon#read 3, iclass 38, count 0 2006.211.08:10:31.78#ibcon#about to read 4, iclass 38, count 0 2006.211.08:10:31.78#ibcon#read 4, iclass 38, count 0 2006.211.08:10:31.78#ibcon#about to read 5, iclass 38, count 0 2006.211.08:10:31.78#ibcon#read 5, iclass 38, count 0 2006.211.08:10:31.78#ibcon#about to read 6, iclass 38, count 0 2006.211.08:10:31.78#ibcon#read 6, iclass 38, count 0 2006.211.08:10:31.78#ibcon#end of sib2, iclass 38, count 0 2006.211.08:10:31.78#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:10:31.78#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:10:31.78#ibcon#[27=USB\r\n] 2006.211.08:10:31.78#ibcon#*before write, iclass 38, count 0 2006.211.08:10:31.78#ibcon#enter sib2, iclass 38, count 0 2006.211.08:10:31.78#ibcon#flushed, iclass 38, count 0 2006.211.08:10:31.78#ibcon#about to write, iclass 38, count 0 2006.211.08:10:31.78#ibcon#wrote, iclass 38, count 0 2006.211.08:10:31.78#ibcon#about to read 3, iclass 38, count 0 2006.211.08:10:31.81#ibcon#read 3, iclass 38, count 0 2006.211.08:10:31.81#ibcon#about to read 4, iclass 38, count 0 2006.211.08:10:31.81#ibcon#read 4, iclass 38, count 0 2006.211.08:10:31.81#ibcon#about to read 5, iclass 38, count 0 2006.211.08:10:31.81#ibcon#read 5, iclass 38, count 0 2006.211.08:10:31.81#ibcon#about to read 6, iclass 38, count 0 2006.211.08:10:31.81#ibcon#read 6, iclass 38, count 0 2006.211.08:10:31.81#ibcon#end of sib2, iclass 38, count 0 2006.211.08:10:31.81#ibcon#*after write, iclass 38, count 0 2006.211.08:10:31.81#ibcon#*before return 0, iclass 38, count 0 2006.211.08:10:31.81#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:31.81#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.211.08:10:31.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:10:31.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:10:31.81$vc4f8/vblo=6,752.99 2006.211.08:10:31.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.211.08:10:31.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.211.08:10:31.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:10:31.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.08:10:31.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.211.08:10:31.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.08:10:31.81#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:10:31.81#ibcon#first serial, iclass 40, count 0 2006.211.08:10:31.81#ibcon#enter sib2, iclass 40, count 0 2006.211.08:10:31.81#ibcon#flushed, iclass 40, count 0 2006.211.08:10:31.81#ibcon#about to write, iclass 40, count 0 2006.211.08:10:31.81#ibcon#wrote, iclass 40, count 0 2006.211.08:10:31.81#ibcon#about to read 3, iclass 40, count 0 2006.211.08:10:31.83#ibcon#read 3, iclass 40, count 0 2006.211.08:10:31.83#ibcon#about to read 4, iclass 40, count 0 2006.211.08:10:31.83#ibcon#read 4, iclass 40, count 0 2006.211.08:10:31.83#ibcon#about to read 5, iclass 40, count 0 2006.211.08:10:31.83#ibcon#read 5, iclass 40, count 0 2006.211.08:10:31.83#ibcon#about to read 6, iclass 40, count 0 2006.211.08:10:31.83#ibcon#read 6, iclass 40, count 0 2006.211.08:10:31.83#ibcon#end of sib2, iclass 40, count 0 2006.211.08:10:31.83#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:10:31.83#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:10:31.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:10:31.83#ibcon#*before write, iclass 40, count 0 2006.211.08:10:31.83#ibcon#enter sib2, iclass 40, count 0 2006.211.08:10:31.83#ibcon#flushed, iclass 40, count 0 2006.211.08:10:31.83#ibcon#about to write, iclass 40, count 0 2006.211.08:10:31.83#ibcon#wrote, iclass 40, count 0 2006.211.08:10:31.83#ibcon#about to read 3, iclass 40, count 0 2006.211.08:10:31.87#ibcon#read 3, iclass 40, count 0 2006.211.08:10:31.87#ibcon#about to read 4, iclass 40, count 0 2006.211.08:10:31.87#ibcon#read 4, iclass 40, count 0 2006.211.08:10:31.87#ibcon#about to read 5, iclass 40, count 0 2006.211.08:10:31.87#ibcon#read 5, iclass 40, count 0 2006.211.08:10:31.87#ibcon#about to read 6, iclass 40, count 0 2006.211.08:10:31.87#ibcon#read 6, iclass 40, count 0 2006.211.08:10:31.87#ibcon#end of sib2, iclass 40, count 0 2006.211.08:10:31.87#ibcon#*after write, iclass 40, count 0 2006.211.08:10:31.87#ibcon#*before return 0, iclass 40, count 0 2006.211.08:10:31.87#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.211.08:10:31.87#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.211.08:10:31.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:10:31.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:10:31.87$vc4f8/vb=6,3 2006.211.08:10:31.87#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.211.08:10:31.87#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.211.08:10:31.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:10:31.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.08:10:31.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.211.08:10:31.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.08:10:31.93#ibcon#enter wrdev, iclass 4, count 2 2006.211.08:10:31.93#ibcon#first serial, iclass 4, count 2 2006.211.08:10:31.93#ibcon#enter sib2, iclass 4, count 2 2006.211.08:10:31.93#ibcon#flushed, iclass 4, count 2 2006.211.08:10:31.93#ibcon#about to write, iclass 4, count 2 2006.211.08:10:31.93#ibcon#wrote, iclass 4, count 2 2006.211.08:10:31.93#ibcon#about to read 3, iclass 4, count 2 2006.211.08:10:31.95#ibcon#read 3, iclass 4, count 2 2006.211.08:10:31.95#ibcon#about to read 4, iclass 4, count 2 2006.211.08:10:31.95#ibcon#read 4, iclass 4, count 2 2006.211.08:10:31.95#ibcon#about to read 5, iclass 4, count 2 2006.211.08:10:31.95#ibcon#read 5, iclass 4, count 2 2006.211.08:10:31.95#ibcon#about to read 6, iclass 4, count 2 2006.211.08:10:31.95#ibcon#read 6, iclass 4, count 2 2006.211.08:10:31.95#ibcon#end of sib2, iclass 4, count 2 2006.211.08:10:31.95#ibcon#*mode == 0, iclass 4, count 2 2006.211.08:10:31.95#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.211.08:10:31.95#ibcon#[27=AT06-03\r\n] 2006.211.08:10:31.95#ibcon#*before write, iclass 4, count 2 2006.211.08:10:31.95#ibcon#enter sib2, iclass 4, count 2 2006.211.08:10:31.95#ibcon#flushed, iclass 4, count 2 2006.211.08:10:31.95#ibcon#about to write, iclass 4, count 2 2006.211.08:10:31.95#ibcon#wrote, iclass 4, count 2 2006.211.08:10:31.95#ibcon#about to read 3, iclass 4, count 2 2006.211.08:10:31.98#ibcon#read 3, iclass 4, count 2 2006.211.08:10:31.98#ibcon#about to read 4, iclass 4, count 2 2006.211.08:10:31.98#ibcon#read 4, iclass 4, count 2 2006.211.08:10:31.98#ibcon#about to read 5, iclass 4, count 2 2006.211.08:10:31.98#ibcon#read 5, iclass 4, count 2 2006.211.08:10:31.98#ibcon#about to read 6, iclass 4, count 2 2006.211.08:10:31.98#ibcon#read 6, iclass 4, count 2 2006.211.08:10:31.98#ibcon#end of sib2, iclass 4, count 2 2006.211.08:10:31.98#ibcon#*after write, iclass 4, count 2 2006.211.08:10:31.98#ibcon#*before return 0, iclass 4, count 2 2006.211.08:10:31.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.211.08:10:31.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.211.08:10:31.98#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.211.08:10:31.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:10:31.98#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.08:10:32.10#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.211.08:10:32.10#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.08:10:32.10#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:10:32.10#ibcon#first serial, iclass 4, count 0 2006.211.08:10:32.10#ibcon#enter sib2, iclass 4, count 0 2006.211.08:10:32.10#ibcon#flushed, iclass 4, count 0 2006.211.08:10:32.10#ibcon#about to write, iclass 4, count 0 2006.211.08:10:32.10#ibcon#wrote, iclass 4, count 0 2006.211.08:10:32.10#ibcon#about to read 3, iclass 4, count 0 2006.211.08:10:32.12#ibcon#read 3, iclass 4, count 0 2006.211.08:10:32.12#ibcon#about to read 4, iclass 4, count 0 2006.211.08:10:32.12#ibcon#read 4, iclass 4, count 0 2006.211.08:10:32.12#ibcon#about to read 5, iclass 4, count 0 2006.211.08:10:32.12#ibcon#read 5, iclass 4, count 0 2006.211.08:10:32.12#ibcon#about to read 6, iclass 4, count 0 2006.211.08:10:32.12#ibcon#read 6, iclass 4, count 0 2006.211.08:10:32.12#ibcon#end of sib2, iclass 4, count 0 2006.211.08:10:32.12#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:10:32.12#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:10:32.12#ibcon#[27=USB\r\n] 2006.211.08:10:32.12#ibcon#*before write, iclass 4, count 0 2006.211.08:10:32.12#ibcon#enter sib2, iclass 4, count 0 2006.211.08:10:32.12#ibcon#flushed, iclass 4, count 0 2006.211.08:10:32.12#ibcon#about to write, iclass 4, count 0 2006.211.08:10:32.12#ibcon#wrote, iclass 4, count 0 2006.211.08:10:32.12#ibcon#about to read 3, iclass 4, count 0 2006.211.08:10:32.15#ibcon#read 3, iclass 4, count 0 2006.211.08:10:32.15#ibcon#about to read 4, iclass 4, count 0 2006.211.08:10:32.15#ibcon#read 4, iclass 4, count 0 2006.211.08:10:32.15#ibcon#about to read 5, iclass 4, count 0 2006.211.08:10:32.15#ibcon#read 5, iclass 4, count 0 2006.211.08:10:32.15#ibcon#about to read 6, iclass 4, count 0 2006.211.08:10:32.15#ibcon#read 6, iclass 4, count 0 2006.211.08:10:32.15#ibcon#end of sib2, iclass 4, count 0 2006.211.08:10:32.15#ibcon#*after write, iclass 4, count 0 2006.211.08:10:32.15#ibcon#*before return 0, iclass 4, count 0 2006.211.08:10:32.15#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.211.08:10:32.15#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.211.08:10:32.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:10:32.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:10:32.15$vc4f8/vabw=wide 2006.211.08:10:32.15#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.08:10:32.15#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.08:10:32.15#ibcon#ireg 8 cls_cnt 0 2006.211.08:10:32.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:32.15#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:32.15#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:32.15#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:10:32.15#ibcon#first serial, iclass 6, count 0 2006.211.08:10:32.15#ibcon#enter sib2, iclass 6, count 0 2006.211.08:10:32.15#ibcon#flushed, iclass 6, count 0 2006.211.08:10:32.15#ibcon#about to write, iclass 6, count 0 2006.211.08:10:32.15#ibcon#wrote, iclass 6, count 0 2006.211.08:10:32.15#ibcon#about to read 3, iclass 6, count 0 2006.211.08:10:32.17#ibcon#read 3, iclass 6, count 0 2006.211.08:10:32.17#ibcon#about to read 4, iclass 6, count 0 2006.211.08:10:32.17#ibcon#read 4, iclass 6, count 0 2006.211.08:10:32.17#ibcon#about to read 5, iclass 6, count 0 2006.211.08:10:32.17#ibcon#read 5, iclass 6, count 0 2006.211.08:10:32.17#ibcon#about to read 6, iclass 6, count 0 2006.211.08:10:32.17#ibcon#read 6, iclass 6, count 0 2006.211.08:10:32.17#ibcon#end of sib2, iclass 6, count 0 2006.211.08:10:32.17#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:10:32.17#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:10:32.17#ibcon#[25=BW32\r\n] 2006.211.08:10:32.17#ibcon#*before write, iclass 6, count 0 2006.211.08:10:32.17#ibcon#enter sib2, iclass 6, count 0 2006.211.08:10:32.17#ibcon#flushed, iclass 6, count 0 2006.211.08:10:32.17#ibcon#about to write, iclass 6, count 0 2006.211.08:10:32.17#ibcon#wrote, iclass 6, count 0 2006.211.08:10:32.17#ibcon#about to read 3, iclass 6, count 0 2006.211.08:10:32.20#ibcon#read 3, iclass 6, count 0 2006.211.08:10:32.20#ibcon#about to read 4, iclass 6, count 0 2006.211.08:10:32.20#ibcon#read 4, iclass 6, count 0 2006.211.08:10:32.20#ibcon#about to read 5, iclass 6, count 0 2006.211.08:10:32.20#ibcon#read 5, iclass 6, count 0 2006.211.08:10:32.20#ibcon#about to read 6, iclass 6, count 0 2006.211.08:10:32.20#ibcon#read 6, iclass 6, count 0 2006.211.08:10:32.20#ibcon#end of sib2, iclass 6, count 0 2006.211.08:10:32.20#ibcon#*after write, iclass 6, count 0 2006.211.08:10:32.20#ibcon#*before return 0, iclass 6, count 0 2006.211.08:10:32.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:32.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:10:32.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:10:32.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:10:32.20$vc4f8/vbbw=wide 2006.211.08:10:32.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:10:32.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:10:32.20#ibcon#ireg 8 cls_cnt 0 2006.211.08:10:32.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:10:32.27#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:10:32.27#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:10:32.27#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:10:32.27#ibcon#first serial, iclass 10, count 0 2006.211.08:10:32.27#ibcon#enter sib2, iclass 10, count 0 2006.211.08:10:32.27#ibcon#flushed, iclass 10, count 0 2006.211.08:10:32.27#ibcon#about to write, iclass 10, count 0 2006.211.08:10:32.27#ibcon#wrote, iclass 10, count 0 2006.211.08:10:32.27#ibcon#about to read 3, iclass 10, count 0 2006.211.08:10:32.29#ibcon#read 3, iclass 10, count 0 2006.211.08:10:32.29#ibcon#about to read 4, iclass 10, count 0 2006.211.08:10:32.29#ibcon#read 4, iclass 10, count 0 2006.211.08:10:32.29#ibcon#about to read 5, iclass 10, count 0 2006.211.08:10:32.29#ibcon#read 5, iclass 10, count 0 2006.211.08:10:32.29#ibcon#about to read 6, iclass 10, count 0 2006.211.08:10:32.29#ibcon#read 6, iclass 10, count 0 2006.211.08:10:32.29#ibcon#end of sib2, iclass 10, count 0 2006.211.08:10:32.29#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:10:32.29#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:10:32.29#ibcon#[27=BW32\r\n] 2006.211.08:10:32.29#ibcon#*before write, iclass 10, count 0 2006.211.08:10:32.29#ibcon#enter sib2, iclass 10, count 0 2006.211.08:10:32.29#ibcon#flushed, iclass 10, count 0 2006.211.08:10:32.29#ibcon#about to write, iclass 10, count 0 2006.211.08:10:32.29#ibcon#wrote, iclass 10, count 0 2006.211.08:10:32.29#ibcon#about to read 3, iclass 10, count 0 2006.211.08:10:32.32#ibcon#read 3, iclass 10, count 0 2006.211.08:10:32.32#ibcon#about to read 4, iclass 10, count 0 2006.211.08:10:32.32#ibcon#read 4, iclass 10, count 0 2006.211.08:10:32.32#ibcon#about to read 5, iclass 10, count 0 2006.211.08:10:32.32#ibcon#read 5, iclass 10, count 0 2006.211.08:10:32.32#ibcon#about to read 6, iclass 10, count 0 2006.211.08:10:32.32#ibcon#read 6, iclass 10, count 0 2006.211.08:10:32.32#ibcon#end of sib2, iclass 10, count 0 2006.211.08:10:32.32#ibcon#*after write, iclass 10, count 0 2006.211.08:10:32.32#ibcon#*before return 0, iclass 10, count 0 2006.211.08:10:32.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:10:32.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:10:32.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:10:32.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:10:32.32$4f8m12a/ifd4f 2006.211.08:10:32.32$ifd4f/lo= 2006.211.08:10:32.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:10:32.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:10:32.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:10:32.32$ifd4f/patch= 2006.211.08:10:32.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:10:32.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:10:32.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:10:32.32$4f8m12a/"form=m,16.000,1:2 2006.211.08:10:32.32$4f8m12a/"tpicd 2006.211.08:10:32.32$4f8m12a/echo=off 2006.211.08:10:32.33$4f8m12a/xlog=off 2006.211.08:10:32.33:!2006.211.08:11:00 2006.211.08:10:42.14#trakl#Source acquired 2006.211.08:10:42.14#flagr#flagr/antenna,acquired 2006.211.08:11:00.01:preob 2006.211.08:11:01.14/onsource/TRACKING 2006.211.08:11:01.14:!2006.211.08:11:10 2006.211.08:11:10.00:data_valid=on 2006.211.08:11:10.00:midob 2006.211.08:11:10.14/onsource/TRACKING 2006.211.08:11:10.14/wx/24.60,1010.0,80 2006.211.08:11:10.30/cable/+6.4407E-03 2006.211.08:11:11.39/va/01,08,usb,yes,29,31 2006.211.08:11:11.39/va/02,07,usb,yes,29,31 2006.211.08:11:11.39/va/03,06,usb,yes,31,31 2006.211.08:11:11.39/va/04,07,usb,yes,30,32 2006.211.08:11:11.39/va/05,07,usb,yes,33,35 2006.211.08:11:11.39/va/06,06,usb,yes,32,32 2006.211.08:11:11.39/va/07,06,usb,yes,32,32 2006.211.08:11:11.39/va/08,07,usb,yes,31,30 2006.211.08:11:11.62/valo/01,532.99,yes,locked 2006.211.08:11:11.62/valo/02,572.99,yes,locked 2006.211.08:11:11.62/valo/03,672.99,yes,locked 2006.211.08:11:11.62/valo/04,832.99,yes,locked 2006.211.08:11:11.62/valo/05,652.99,yes,locked 2006.211.08:11:11.62/valo/06,772.99,yes,locked 2006.211.08:11:11.62/valo/07,832.99,yes,locked 2006.211.08:11:11.62/valo/08,852.99,yes,locked 2006.211.08:11:12.71/vb/01,04,usb,yes,29,27 2006.211.08:11:12.71/vb/02,04,usb,yes,30,32 2006.211.08:11:12.71/vb/03,03,usb,yes,33,38 2006.211.08:11:12.71/vb/04,03,usb,yes,34,35 2006.211.08:11:12.71/vb/05,03,usb,yes,33,37 2006.211.08:11:12.71/vb/06,03,usb,yes,33,37 2006.211.08:11:12.71/vb/07,04,usb,yes,29,29 2006.211.08:11:12.71/vb/08,03,usb,yes,33,37 2006.211.08:11:12.94/vblo/01,632.99,yes,locked 2006.211.08:11:12.94/vblo/02,640.99,yes,locked 2006.211.08:11:12.94/vblo/03,656.99,yes,locked 2006.211.08:11:12.94/vblo/04,712.99,yes,locked 2006.211.08:11:12.94/vblo/05,744.99,yes,locked 2006.211.08:11:12.94/vblo/06,752.99,yes,locked 2006.211.08:11:12.94/vblo/07,734.99,yes,locked 2006.211.08:11:12.94/vblo/08,744.99,yes,locked 2006.211.08:11:13.09/vabw/8 2006.211.08:11:13.24/vbbw/8 2006.211.08:11:13.33/xfe/off,on,12.0 2006.211.08:11:13.71/ifatt/23,28,28,28 2006.211.08:11:14.07/fmout-gps/S +4.46E-07 2006.211.08:11:14.11:!2006.211.08:12:10 2006.211.08:12:10.01:data_valid=off 2006.211.08:12:10.01:postob 2006.211.08:12:10.25/cable/+6.4408E-03 2006.211.08:12:10.25/wx/24.58,1010.1,81 2006.211.08:12:11.07/fmout-gps/S +4.46E-07 2006.211.08:12:11.07:scan_name=211-0813,k06211,60 2006.211.08:12:11.07:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.211.08:12:11.13#flagr#flagr/antenna,new-source 2006.211.08:12:12.13:checkk5 2006.211.08:12:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:12:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:12:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:12:13.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:12:13.84/chk_obsdata//k5ts1/T2110811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:12:14.17/chk_obsdata//k5ts2/T2110811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:12:14.51/chk_obsdata//k5ts3/T2110811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:12:14.84/chk_obsdata//k5ts4/T2110811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:12:15.50/k5log//k5ts1_log_newline 2006.211.08:12:16.15/k5log//k5ts2_log_newline 2006.211.08:12:16.81/k5log//k5ts3_log_newline 2006.211.08:12:17.47/k5log//k5ts4_log_newline 2006.211.08:12:17.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:12:17.49:4f8m12a=2 2006.211.08:12:17.50$4f8m12a/echo=on 2006.211.08:12:17.50$4f8m12a/pcalon 2006.211.08:12:17.50$pcalon/"no phase cal control is implemented here 2006.211.08:12:17.50$4f8m12a/"tpicd=stop 2006.211.08:12:17.50$4f8m12a/vc4f8 2006.211.08:12:17.50$vc4f8/valo=1,532.99 2006.211.08:12:17.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:12:17.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:12:17.50#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:17.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:17.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:17.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:17.50#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:12:17.50#ibcon#first serial, iclass 17, count 0 2006.211.08:12:17.50#ibcon#enter sib2, iclass 17, count 0 2006.211.08:12:17.50#ibcon#flushed, iclass 17, count 0 2006.211.08:12:17.50#ibcon#about to write, iclass 17, count 0 2006.211.08:12:17.50#ibcon#wrote, iclass 17, count 0 2006.211.08:12:17.50#ibcon#about to read 3, iclass 17, count 0 2006.211.08:12:17.51#ibcon#read 3, iclass 17, count 0 2006.211.08:12:17.51#ibcon#about to read 4, iclass 17, count 0 2006.211.08:12:17.51#ibcon#read 4, iclass 17, count 0 2006.211.08:12:17.51#ibcon#about to read 5, iclass 17, count 0 2006.211.08:12:17.51#ibcon#read 5, iclass 17, count 0 2006.211.08:12:17.51#ibcon#about to read 6, iclass 17, count 0 2006.211.08:12:17.51#ibcon#read 6, iclass 17, count 0 2006.211.08:12:17.51#ibcon#end of sib2, iclass 17, count 0 2006.211.08:12:17.51#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:12:17.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:12:17.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:12:17.51#ibcon#*before write, iclass 17, count 0 2006.211.08:12:17.51#ibcon#enter sib2, iclass 17, count 0 2006.211.08:12:17.51#ibcon#flushed, iclass 17, count 0 2006.211.08:12:17.51#ibcon#about to write, iclass 17, count 0 2006.211.08:12:17.51#ibcon#wrote, iclass 17, count 0 2006.211.08:12:17.51#ibcon#about to read 3, iclass 17, count 0 2006.211.08:12:17.56#ibcon#read 3, iclass 17, count 0 2006.211.08:12:17.56#ibcon#about to read 4, iclass 17, count 0 2006.211.08:12:17.56#ibcon#read 4, iclass 17, count 0 2006.211.08:12:17.56#ibcon#about to read 5, iclass 17, count 0 2006.211.08:12:17.56#ibcon#read 5, iclass 17, count 0 2006.211.08:12:17.56#ibcon#about to read 6, iclass 17, count 0 2006.211.08:12:17.56#ibcon#read 6, iclass 17, count 0 2006.211.08:12:17.56#ibcon#end of sib2, iclass 17, count 0 2006.211.08:12:17.56#ibcon#*after write, iclass 17, count 0 2006.211.08:12:17.56#ibcon#*before return 0, iclass 17, count 0 2006.211.08:12:17.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:17.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:17.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:12:17.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:12:17.56$vc4f8/va=1,8 2006.211.08:12:17.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:12:17.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:12:17.56#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:17.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:17.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:17.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:17.56#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:12:17.56#ibcon#first serial, iclass 19, count 2 2006.211.08:12:17.56#ibcon#enter sib2, iclass 19, count 2 2006.211.08:12:17.56#ibcon#flushed, iclass 19, count 2 2006.211.08:12:17.56#ibcon#about to write, iclass 19, count 2 2006.211.08:12:17.56#ibcon#wrote, iclass 19, count 2 2006.211.08:12:17.56#ibcon#about to read 3, iclass 19, count 2 2006.211.08:12:17.58#ibcon#read 3, iclass 19, count 2 2006.211.08:12:17.58#ibcon#about to read 4, iclass 19, count 2 2006.211.08:12:17.58#ibcon#read 4, iclass 19, count 2 2006.211.08:12:17.58#ibcon#about to read 5, iclass 19, count 2 2006.211.08:12:17.58#ibcon#read 5, iclass 19, count 2 2006.211.08:12:17.58#ibcon#about to read 6, iclass 19, count 2 2006.211.08:12:17.58#ibcon#read 6, iclass 19, count 2 2006.211.08:12:17.58#ibcon#end of sib2, iclass 19, count 2 2006.211.08:12:17.58#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:12:17.58#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:12:17.58#ibcon#[25=AT01-08\r\n] 2006.211.08:12:17.58#ibcon#*before write, iclass 19, count 2 2006.211.08:12:17.58#ibcon#enter sib2, iclass 19, count 2 2006.211.08:12:17.58#ibcon#flushed, iclass 19, count 2 2006.211.08:12:17.58#ibcon#about to write, iclass 19, count 2 2006.211.08:12:17.58#ibcon#wrote, iclass 19, count 2 2006.211.08:12:17.58#ibcon#about to read 3, iclass 19, count 2 2006.211.08:12:17.61#ibcon#read 3, iclass 19, count 2 2006.211.08:12:17.61#ibcon#about to read 4, iclass 19, count 2 2006.211.08:12:17.61#ibcon#read 4, iclass 19, count 2 2006.211.08:12:17.61#ibcon#about to read 5, iclass 19, count 2 2006.211.08:12:17.61#ibcon#read 5, iclass 19, count 2 2006.211.08:12:17.61#ibcon#about to read 6, iclass 19, count 2 2006.211.08:12:17.61#ibcon#read 6, iclass 19, count 2 2006.211.08:12:17.61#ibcon#end of sib2, iclass 19, count 2 2006.211.08:12:17.61#ibcon#*after write, iclass 19, count 2 2006.211.08:12:17.61#ibcon#*before return 0, iclass 19, count 2 2006.211.08:12:17.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:17.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:17.61#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:12:17.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:17.61#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:17.73#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:17.73#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:17.73#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:12:17.73#ibcon#first serial, iclass 19, count 0 2006.211.08:12:17.73#ibcon#enter sib2, iclass 19, count 0 2006.211.08:12:17.73#ibcon#flushed, iclass 19, count 0 2006.211.08:12:17.73#ibcon#about to write, iclass 19, count 0 2006.211.08:12:17.73#ibcon#wrote, iclass 19, count 0 2006.211.08:12:17.73#ibcon#about to read 3, iclass 19, count 0 2006.211.08:12:17.75#ibcon#read 3, iclass 19, count 0 2006.211.08:12:17.75#ibcon#about to read 4, iclass 19, count 0 2006.211.08:12:17.75#ibcon#read 4, iclass 19, count 0 2006.211.08:12:17.75#ibcon#about to read 5, iclass 19, count 0 2006.211.08:12:17.75#ibcon#read 5, iclass 19, count 0 2006.211.08:12:17.75#ibcon#about to read 6, iclass 19, count 0 2006.211.08:12:17.75#ibcon#read 6, iclass 19, count 0 2006.211.08:12:17.75#ibcon#end of sib2, iclass 19, count 0 2006.211.08:12:17.75#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:12:17.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:12:17.75#ibcon#[25=USB\r\n] 2006.211.08:12:17.75#ibcon#*before write, iclass 19, count 0 2006.211.08:12:17.75#ibcon#enter sib2, iclass 19, count 0 2006.211.08:12:17.75#ibcon#flushed, iclass 19, count 0 2006.211.08:12:17.75#ibcon#about to write, iclass 19, count 0 2006.211.08:12:17.75#ibcon#wrote, iclass 19, count 0 2006.211.08:12:17.75#ibcon#about to read 3, iclass 19, count 0 2006.211.08:12:17.78#ibcon#read 3, iclass 19, count 0 2006.211.08:12:17.78#ibcon#about to read 4, iclass 19, count 0 2006.211.08:12:17.78#ibcon#read 4, iclass 19, count 0 2006.211.08:12:17.78#ibcon#about to read 5, iclass 19, count 0 2006.211.08:12:17.78#ibcon#read 5, iclass 19, count 0 2006.211.08:12:17.78#ibcon#about to read 6, iclass 19, count 0 2006.211.08:12:17.78#ibcon#read 6, iclass 19, count 0 2006.211.08:12:17.78#ibcon#end of sib2, iclass 19, count 0 2006.211.08:12:17.78#ibcon#*after write, iclass 19, count 0 2006.211.08:12:17.78#ibcon#*before return 0, iclass 19, count 0 2006.211.08:12:17.78#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:17.78#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:17.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:12:17.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:12:17.78$vc4f8/valo=2,572.99 2006.211.08:12:17.78#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:12:17.78#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:12:17.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:17.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:12:17.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:12:17.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:12:17.78#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:12:17.78#ibcon#first serial, iclass 21, count 0 2006.211.08:12:17.78#ibcon#enter sib2, iclass 21, count 0 2006.211.08:12:17.78#ibcon#flushed, iclass 21, count 0 2006.211.08:12:17.78#ibcon#about to write, iclass 21, count 0 2006.211.08:12:17.78#ibcon#wrote, iclass 21, count 0 2006.211.08:12:17.78#ibcon#about to read 3, iclass 21, count 0 2006.211.08:12:17.80#ibcon#read 3, iclass 21, count 0 2006.211.08:12:17.80#ibcon#about to read 4, iclass 21, count 0 2006.211.08:12:17.80#ibcon#read 4, iclass 21, count 0 2006.211.08:12:17.80#ibcon#about to read 5, iclass 21, count 0 2006.211.08:12:17.80#ibcon#read 5, iclass 21, count 0 2006.211.08:12:17.80#ibcon#about to read 6, iclass 21, count 0 2006.211.08:12:17.80#ibcon#read 6, iclass 21, count 0 2006.211.08:12:17.80#ibcon#end of sib2, iclass 21, count 0 2006.211.08:12:17.80#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:12:17.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:12:17.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:12:17.80#ibcon#*before write, iclass 21, count 0 2006.211.08:12:17.80#ibcon#enter sib2, iclass 21, count 0 2006.211.08:12:17.80#ibcon#flushed, iclass 21, count 0 2006.211.08:12:17.80#ibcon#about to write, iclass 21, count 0 2006.211.08:12:17.80#ibcon#wrote, iclass 21, count 0 2006.211.08:12:17.80#ibcon#about to read 3, iclass 21, count 0 2006.211.08:12:17.84#ibcon#read 3, iclass 21, count 0 2006.211.08:12:17.84#ibcon#about to read 4, iclass 21, count 0 2006.211.08:12:17.84#ibcon#read 4, iclass 21, count 0 2006.211.08:12:17.84#ibcon#about to read 5, iclass 21, count 0 2006.211.08:12:17.84#ibcon#read 5, iclass 21, count 0 2006.211.08:12:17.84#ibcon#about to read 6, iclass 21, count 0 2006.211.08:12:17.84#ibcon#read 6, iclass 21, count 0 2006.211.08:12:17.84#ibcon#end of sib2, iclass 21, count 0 2006.211.08:12:17.84#ibcon#*after write, iclass 21, count 0 2006.211.08:12:17.84#ibcon#*before return 0, iclass 21, count 0 2006.211.08:12:17.84#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:12:17.84#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:12:17.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:12:17.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:12:17.84$vc4f8/va=2,7 2006.211.08:12:17.84#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:12:17.84#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:12:17.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:17.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:12:17.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:12:17.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:12:17.90#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:12:17.90#ibcon#first serial, iclass 23, count 2 2006.211.08:12:17.90#ibcon#enter sib2, iclass 23, count 2 2006.211.08:12:17.90#ibcon#flushed, iclass 23, count 2 2006.211.08:12:17.90#ibcon#about to write, iclass 23, count 2 2006.211.08:12:17.90#ibcon#wrote, iclass 23, count 2 2006.211.08:12:17.90#ibcon#about to read 3, iclass 23, count 2 2006.211.08:12:17.92#ibcon#read 3, iclass 23, count 2 2006.211.08:12:17.92#ibcon#about to read 4, iclass 23, count 2 2006.211.08:12:17.92#ibcon#read 4, iclass 23, count 2 2006.211.08:12:17.92#ibcon#about to read 5, iclass 23, count 2 2006.211.08:12:17.92#ibcon#read 5, iclass 23, count 2 2006.211.08:12:17.92#ibcon#about to read 6, iclass 23, count 2 2006.211.08:12:17.92#ibcon#read 6, iclass 23, count 2 2006.211.08:12:17.92#ibcon#end of sib2, iclass 23, count 2 2006.211.08:12:17.92#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:12:17.92#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:12:17.92#ibcon#[25=AT02-07\r\n] 2006.211.08:12:17.92#ibcon#*before write, iclass 23, count 2 2006.211.08:12:17.92#ibcon#enter sib2, iclass 23, count 2 2006.211.08:12:17.92#ibcon#flushed, iclass 23, count 2 2006.211.08:12:17.92#ibcon#about to write, iclass 23, count 2 2006.211.08:12:17.92#ibcon#wrote, iclass 23, count 2 2006.211.08:12:17.92#ibcon#about to read 3, iclass 23, count 2 2006.211.08:12:17.95#ibcon#read 3, iclass 23, count 2 2006.211.08:12:17.95#ibcon#about to read 4, iclass 23, count 2 2006.211.08:12:17.95#ibcon#read 4, iclass 23, count 2 2006.211.08:12:17.95#ibcon#about to read 5, iclass 23, count 2 2006.211.08:12:17.95#ibcon#read 5, iclass 23, count 2 2006.211.08:12:17.95#ibcon#about to read 6, iclass 23, count 2 2006.211.08:12:17.95#ibcon#read 6, iclass 23, count 2 2006.211.08:12:17.95#ibcon#end of sib2, iclass 23, count 2 2006.211.08:12:17.95#ibcon#*after write, iclass 23, count 2 2006.211.08:12:17.95#ibcon#*before return 0, iclass 23, count 2 2006.211.08:12:17.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:12:17.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:12:17.95#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:12:17.95#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:17.95#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:12:18.07#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:12:18.07#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:12:18.07#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:12:18.07#ibcon#first serial, iclass 23, count 0 2006.211.08:12:18.07#ibcon#enter sib2, iclass 23, count 0 2006.211.08:12:18.07#ibcon#flushed, iclass 23, count 0 2006.211.08:12:18.07#ibcon#about to write, iclass 23, count 0 2006.211.08:12:18.07#ibcon#wrote, iclass 23, count 0 2006.211.08:12:18.07#ibcon#about to read 3, iclass 23, count 0 2006.211.08:12:18.09#ibcon#read 3, iclass 23, count 0 2006.211.08:12:18.09#ibcon#about to read 4, iclass 23, count 0 2006.211.08:12:18.09#ibcon#read 4, iclass 23, count 0 2006.211.08:12:18.09#ibcon#about to read 5, iclass 23, count 0 2006.211.08:12:18.09#ibcon#read 5, iclass 23, count 0 2006.211.08:12:18.09#ibcon#about to read 6, iclass 23, count 0 2006.211.08:12:18.09#ibcon#read 6, iclass 23, count 0 2006.211.08:12:18.09#ibcon#end of sib2, iclass 23, count 0 2006.211.08:12:18.09#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:12:18.09#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:12:18.09#ibcon#[25=USB\r\n] 2006.211.08:12:18.09#ibcon#*before write, iclass 23, count 0 2006.211.08:12:18.09#ibcon#enter sib2, iclass 23, count 0 2006.211.08:12:18.09#ibcon#flushed, iclass 23, count 0 2006.211.08:12:18.09#ibcon#about to write, iclass 23, count 0 2006.211.08:12:18.09#ibcon#wrote, iclass 23, count 0 2006.211.08:12:18.09#ibcon#about to read 3, iclass 23, count 0 2006.211.08:12:18.12#ibcon#read 3, iclass 23, count 0 2006.211.08:12:18.12#ibcon#about to read 4, iclass 23, count 0 2006.211.08:12:18.12#ibcon#read 4, iclass 23, count 0 2006.211.08:12:18.12#ibcon#about to read 5, iclass 23, count 0 2006.211.08:12:18.12#ibcon#read 5, iclass 23, count 0 2006.211.08:12:18.12#ibcon#about to read 6, iclass 23, count 0 2006.211.08:12:18.12#ibcon#read 6, iclass 23, count 0 2006.211.08:12:18.12#ibcon#end of sib2, iclass 23, count 0 2006.211.08:12:18.12#ibcon#*after write, iclass 23, count 0 2006.211.08:12:18.12#ibcon#*before return 0, iclass 23, count 0 2006.211.08:12:18.12#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:12:18.12#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:12:18.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:12:18.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:12:18.12$vc4f8/valo=3,672.99 2006.211.08:12:18.12#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:12:18.12#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:12:18.12#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:18.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:12:18.12#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:12:18.12#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:12:18.12#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:12:18.12#ibcon#first serial, iclass 25, count 0 2006.211.08:12:18.12#ibcon#enter sib2, iclass 25, count 0 2006.211.08:12:18.12#ibcon#flushed, iclass 25, count 0 2006.211.08:12:18.12#ibcon#about to write, iclass 25, count 0 2006.211.08:12:18.12#ibcon#wrote, iclass 25, count 0 2006.211.08:12:18.12#ibcon#about to read 3, iclass 25, count 0 2006.211.08:12:18.14#ibcon#read 3, iclass 25, count 0 2006.211.08:12:18.14#ibcon#about to read 4, iclass 25, count 0 2006.211.08:12:18.14#ibcon#read 4, iclass 25, count 0 2006.211.08:12:18.14#ibcon#about to read 5, iclass 25, count 0 2006.211.08:12:18.14#ibcon#read 5, iclass 25, count 0 2006.211.08:12:18.14#ibcon#about to read 6, iclass 25, count 0 2006.211.08:12:18.14#ibcon#read 6, iclass 25, count 0 2006.211.08:12:18.14#ibcon#end of sib2, iclass 25, count 0 2006.211.08:12:18.14#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:12:18.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:12:18.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:12:18.14#ibcon#*before write, iclass 25, count 0 2006.211.08:12:18.14#ibcon#enter sib2, iclass 25, count 0 2006.211.08:12:18.14#ibcon#flushed, iclass 25, count 0 2006.211.08:12:18.14#ibcon#about to write, iclass 25, count 0 2006.211.08:12:18.14#ibcon#wrote, iclass 25, count 0 2006.211.08:12:18.14#ibcon#about to read 3, iclass 25, count 0 2006.211.08:12:18.18#ibcon#read 3, iclass 25, count 0 2006.211.08:12:18.18#ibcon#about to read 4, iclass 25, count 0 2006.211.08:12:18.18#ibcon#read 4, iclass 25, count 0 2006.211.08:12:18.18#ibcon#about to read 5, iclass 25, count 0 2006.211.08:12:18.18#ibcon#read 5, iclass 25, count 0 2006.211.08:12:18.18#ibcon#about to read 6, iclass 25, count 0 2006.211.08:12:18.18#ibcon#read 6, iclass 25, count 0 2006.211.08:12:18.18#ibcon#end of sib2, iclass 25, count 0 2006.211.08:12:18.18#ibcon#*after write, iclass 25, count 0 2006.211.08:12:18.18#ibcon#*before return 0, iclass 25, count 0 2006.211.08:12:18.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:12:18.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:12:18.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:12:18.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:12:18.18$vc4f8/va=3,6 2006.211.08:12:18.18#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:12:18.18#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:12:18.18#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:18.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:12:18.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:12:18.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:12:18.24#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:12:18.24#ibcon#first serial, iclass 27, count 2 2006.211.08:12:18.24#ibcon#enter sib2, iclass 27, count 2 2006.211.08:12:18.24#ibcon#flushed, iclass 27, count 2 2006.211.08:12:18.24#ibcon#about to write, iclass 27, count 2 2006.211.08:12:18.24#ibcon#wrote, iclass 27, count 2 2006.211.08:12:18.24#ibcon#about to read 3, iclass 27, count 2 2006.211.08:12:18.26#ibcon#read 3, iclass 27, count 2 2006.211.08:12:18.26#ibcon#about to read 4, iclass 27, count 2 2006.211.08:12:18.26#ibcon#read 4, iclass 27, count 2 2006.211.08:12:18.26#ibcon#about to read 5, iclass 27, count 2 2006.211.08:12:18.26#ibcon#read 5, iclass 27, count 2 2006.211.08:12:18.26#ibcon#about to read 6, iclass 27, count 2 2006.211.08:12:18.26#ibcon#read 6, iclass 27, count 2 2006.211.08:12:18.26#ibcon#end of sib2, iclass 27, count 2 2006.211.08:12:18.26#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:12:18.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:12:18.26#ibcon#[25=AT03-06\r\n] 2006.211.08:12:18.26#ibcon#*before write, iclass 27, count 2 2006.211.08:12:18.26#ibcon#enter sib2, iclass 27, count 2 2006.211.08:12:18.26#ibcon#flushed, iclass 27, count 2 2006.211.08:12:18.26#ibcon#about to write, iclass 27, count 2 2006.211.08:12:18.26#ibcon#wrote, iclass 27, count 2 2006.211.08:12:18.26#ibcon#about to read 3, iclass 27, count 2 2006.211.08:12:18.29#ibcon#read 3, iclass 27, count 2 2006.211.08:12:18.29#ibcon#about to read 4, iclass 27, count 2 2006.211.08:12:18.29#ibcon#read 4, iclass 27, count 2 2006.211.08:12:18.29#ibcon#about to read 5, iclass 27, count 2 2006.211.08:12:18.29#ibcon#read 5, iclass 27, count 2 2006.211.08:12:18.29#ibcon#about to read 6, iclass 27, count 2 2006.211.08:12:18.29#ibcon#read 6, iclass 27, count 2 2006.211.08:12:18.29#ibcon#end of sib2, iclass 27, count 2 2006.211.08:12:18.29#ibcon#*after write, iclass 27, count 2 2006.211.08:12:18.29#ibcon#*before return 0, iclass 27, count 2 2006.211.08:12:18.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:12:18.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:12:18.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:12:18.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:18.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:12:18.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:12:18.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:12:18.41#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:12:18.41#ibcon#first serial, iclass 27, count 0 2006.211.08:12:18.41#ibcon#enter sib2, iclass 27, count 0 2006.211.08:12:18.41#ibcon#flushed, iclass 27, count 0 2006.211.08:12:18.41#ibcon#about to write, iclass 27, count 0 2006.211.08:12:18.41#ibcon#wrote, iclass 27, count 0 2006.211.08:12:18.41#ibcon#about to read 3, iclass 27, count 0 2006.211.08:12:18.43#ibcon#read 3, iclass 27, count 0 2006.211.08:12:18.43#ibcon#about to read 4, iclass 27, count 0 2006.211.08:12:18.43#ibcon#read 4, iclass 27, count 0 2006.211.08:12:18.43#ibcon#about to read 5, iclass 27, count 0 2006.211.08:12:18.43#ibcon#read 5, iclass 27, count 0 2006.211.08:12:18.43#ibcon#about to read 6, iclass 27, count 0 2006.211.08:12:18.43#ibcon#read 6, iclass 27, count 0 2006.211.08:12:18.43#ibcon#end of sib2, iclass 27, count 0 2006.211.08:12:18.43#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:12:18.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:12:18.43#ibcon#[25=USB\r\n] 2006.211.08:12:18.43#ibcon#*before write, iclass 27, count 0 2006.211.08:12:18.43#ibcon#enter sib2, iclass 27, count 0 2006.211.08:12:18.43#ibcon#flushed, iclass 27, count 0 2006.211.08:12:18.43#ibcon#about to write, iclass 27, count 0 2006.211.08:12:18.43#ibcon#wrote, iclass 27, count 0 2006.211.08:12:18.43#ibcon#about to read 3, iclass 27, count 0 2006.211.08:12:18.46#ibcon#read 3, iclass 27, count 0 2006.211.08:12:18.46#ibcon#about to read 4, iclass 27, count 0 2006.211.08:12:18.46#ibcon#read 4, iclass 27, count 0 2006.211.08:12:18.46#ibcon#about to read 5, iclass 27, count 0 2006.211.08:12:18.46#ibcon#read 5, iclass 27, count 0 2006.211.08:12:18.46#ibcon#about to read 6, iclass 27, count 0 2006.211.08:12:18.46#ibcon#read 6, iclass 27, count 0 2006.211.08:12:18.46#ibcon#end of sib2, iclass 27, count 0 2006.211.08:12:18.46#ibcon#*after write, iclass 27, count 0 2006.211.08:12:18.46#ibcon#*before return 0, iclass 27, count 0 2006.211.08:12:18.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:12:18.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:12:18.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:12:18.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:12:18.46$vc4f8/valo=4,832.99 2006.211.08:12:18.46#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:12:18.46#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:12:18.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:18.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:18.46#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:18.46#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:18.46#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:12:18.46#ibcon#first serial, iclass 29, count 0 2006.211.08:12:18.46#ibcon#enter sib2, iclass 29, count 0 2006.211.08:12:18.46#ibcon#flushed, iclass 29, count 0 2006.211.08:12:18.46#ibcon#about to write, iclass 29, count 0 2006.211.08:12:18.46#ibcon#wrote, iclass 29, count 0 2006.211.08:12:18.46#ibcon#about to read 3, iclass 29, count 0 2006.211.08:12:18.48#ibcon#read 3, iclass 29, count 0 2006.211.08:12:18.48#ibcon#about to read 4, iclass 29, count 0 2006.211.08:12:18.48#ibcon#read 4, iclass 29, count 0 2006.211.08:12:18.48#ibcon#about to read 5, iclass 29, count 0 2006.211.08:12:18.48#ibcon#read 5, iclass 29, count 0 2006.211.08:12:18.48#ibcon#about to read 6, iclass 29, count 0 2006.211.08:12:18.48#ibcon#read 6, iclass 29, count 0 2006.211.08:12:18.48#ibcon#end of sib2, iclass 29, count 0 2006.211.08:12:18.48#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:12:18.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:12:18.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:12:18.48#ibcon#*before write, iclass 29, count 0 2006.211.08:12:18.48#ibcon#enter sib2, iclass 29, count 0 2006.211.08:12:18.48#ibcon#flushed, iclass 29, count 0 2006.211.08:12:18.48#ibcon#about to write, iclass 29, count 0 2006.211.08:12:18.48#ibcon#wrote, iclass 29, count 0 2006.211.08:12:18.48#ibcon#about to read 3, iclass 29, count 0 2006.211.08:12:18.52#ibcon#read 3, iclass 29, count 0 2006.211.08:12:18.52#ibcon#about to read 4, iclass 29, count 0 2006.211.08:12:18.52#ibcon#read 4, iclass 29, count 0 2006.211.08:12:18.52#ibcon#about to read 5, iclass 29, count 0 2006.211.08:12:18.52#ibcon#read 5, iclass 29, count 0 2006.211.08:12:18.52#ibcon#about to read 6, iclass 29, count 0 2006.211.08:12:18.52#ibcon#read 6, iclass 29, count 0 2006.211.08:12:18.52#ibcon#end of sib2, iclass 29, count 0 2006.211.08:12:18.52#ibcon#*after write, iclass 29, count 0 2006.211.08:12:18.52#ibcon#*before return 0, iclass 29, count 0 2006.211.08:12:18.52#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:18.52#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:18.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:12:18.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:12:18.52$vc4f8/va=4,7 2006.211.08:12:18.52#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.08:12:18.52#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.08:12:18.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:18.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:18.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:18.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:18.58#ibcon#enter wrdev, iclass 31, count 2 2006.211.08:12:18.58#ibcon#first serial, iclass 31, count 2 2006.211.08:12:18.58#ibcon#enter sib2, iclass 31, count 2 2006.211.08:12:18.58#ibcon#flushed, iclass 31, count 2 2006.211.08:12:18.58#ibcon#about to write, iclass 31, count 2 2006.211.08:12:18.58#ibcon#wrote, iclass 31, count 2 2006.211.08:12:18.58#ibcon#about to read 3, iclass 31, count 2 2006.211.08:12:18.60#ibcon#read 3, iclass 31, count 2 2006.211.08:12:18.60#ibcon#about to read 4, iclass 31, count 2 2006.211.08:12:18.60#ibcon#read 4, iclass 31, count 2 2006.211.08:12:18.60#ibcon#about to read 5, iclass 31, count 2 2006.211.08:12:18.60#ibcon#read 5, iclass 31, count 2 2006.211.08:12:18.60#ibcon#about to read 6, iclass 31, count 2 2006.211.08:12:18.60#ibcon#read 6, iclass 31, count 2 2006.211.08:12:18.60#ibcon#end of sib2, iclass 31, count 2 2006.211.08:12:18.60#ibcon#*mode == 0, iclass 31, count 2 2006.211.08:12:18.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.08:12:18.60#ibcon#[25=AT04-07\r\n] 2006.211.08:12:18.60#ibcon#*before write, iclass 31, count 2 2006.211.08:12:18.60#ibcon#enter sib2, iclass 31, count 2 2006.211.08:12:18.60#ibcon#flushed, iclass 31, count 2 2006.211.08:12:18.60#ibcon#about to write, iclass 31, count 2 2006.211.08:12:18.60#ibcon#wrote, iclass 31, count 2 2006.211.08:12:18.60#ibcon#about to read 3, iclass 31, count 2 2006.211.08:12:18.63#ibcon#read 3, iclass 31, count 2 2006.211.08:12:18.63#ibcon#about to read 4, iclass 31, count 2 2006.211.08:12:18.63#ibcon#read 4, iclass 31, count 2 2006.211.08:12:18.63#ibcon#about to read 5, iclass 31, count 2 2006.211.08:12:18.63#ibcon#read 5, iclass 31, count 2 2006.211.08:12:18.63#ibcon#about to read 6, iclass 31, count 2 2006.211.08:12:18.63#ibcon#read 6, iclass 31, count 2 2006.211.08:12:18.63#ibcon#end of sib2, iclass 31, count 2 2006.211.08:12:18.63#ibcon#*after write, iclass 31, count 2 2006.211.08:12:18.63#ibcon#*before return 0, iclass 31, count 2 2006.211.08:12:18.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:18.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:18.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.08:12:18.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:18.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:18.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:18.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:18.75#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:12:18.75#ibcon#first serial, iclass 31, count 0 2006.211.08:12:18.75#ibcon#enter sib2, iclass 31, count 0 2006.211.08:12:18.75#ibcon#flushed, iclass 31, count 0 2006.211.08:12:18.75#ibcon#about to write, iclass 31, count 0 2006.211.08:12:18.75#ibcon#wrote, iclass 31, count 0 2006.211.08:12:18.75#ibcon#about to read 3, iclass 31, count 0 2006.211.08:12:18.77#ibcon#read 3, iclass 31, count 0 2006.211.08:12:18.77#ibcon#about to read 4, iclass 31, count 0 2006.211.08:12:18.77#ibcon#read 4, iclass 31, count 0 2006.211.08:12:18.77#ibcon#about to read 5, iclass 31, count 0 2006.211.08:12:18.77#ibcon#read 5, iclass 31, count 0 2006.211.08:12:18.77#ibcon#about to read 6, iclass 31, count 0 2006.211.08:12:18.77#ibcon#read 6, iclass 31, count 0 2006.211.08:12:18.77#ibcon#end of sib2, iclass 31, count 0 2006.211.08:12:18.77#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:12:18.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:12:18.77#ibcon#[25=USB\r\n] 2006.211.08:12:18.77#ibcon#*before write, iclass 31, count 0 2006.211.08:12:18.77#ibcon#enter sib2, iclass 31, count 0 2006.211.08:12:18.77#ibcon#flushed, iclass 31, count 0 2006.211.08:12:18.77#ibcon#about to write, iclass 31, count 0 2006.211.08:12:18.77#ibcon#wrote, iclass 31, count 0 2006.211.08:12:18.77#ibcon#about to read 3, iclass 31, count 0 2006.211.08:12:18.80#ibcon#read 3, iclass 31, count 0 2006.211.08:12:18.80#ibcon#about to read 4, iclass 31, count 0 2006.211.08:12:18.80#ibcon#read 4, iclass 31, count 0 2006.211.08:12:18.80#ibcon#about to read 5, iclass 31, count 0 2006.211.08:12:18.80#ibcon#read 5, iclass 31, count 0 2006.211.08:12:18.80#ibcon#about to read 6, iclass 31, count 0 2006.211.08:12:18.80#ibcon#read 6, iclass 31, count 0 2006.211.08:12:18.80#ibcon#end of sib2, iclass 31, count 0 2006.211.08:12:18.80#ibcon#*after write, iclass 31, count 0 2006.211.08:12:18.80#ibcon#*before return 0, iclass 31, count 0 2006.211.08:12:18.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:18.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:18.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:12:18.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:12:18.80$vc4f8/valo=5,652.99 2006.211.08:12:18.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.08:12:18.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.08:12:18.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:18.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:18.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:18.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:18.80#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:12:18.80#ibcon#first serial, iclass 33, count 0 2006.211.08:12:18.80#ibcon#enter sib2, iclass 33, count 0 2006.211.08:12:18.80#ibcon#flushed, iclass 33, count 0 2006.211.08:12:18.80#ibcon#about to write, iclass 33, count 0 2006.211.08:12:18.80#ibcon#wrote, iclass 33, count 0 2006.211.08:12:18.80#ibcon#about to read 3, iclass 33, count 0 2006.211.08:12:18.82#ibcon#read 3, iclass 33, count 0 2006.211.08:12:18.82#ibcon#about to read 4, iclass 33, count 0 2006.211.08:12:18.82#ibcon#read 4, iclass 33, count 0 2006.211.08:12:18.82#ibcon#about to read 5, iclass 33, count 0 2006.211.08:12:18.82#ibcon#read 5, iclass 33, count 0 2006.211.08:12:18.82#ibcon#about to read 6, iclass 33, count 0 2006.211.08:12:18.82#ibcon#read 6, iclass 33, count 0 2006.211.08:12:18.82#ibcon#end of sib2, iclass 33, count 0 2006.211.08:12:18.82#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:12:18.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:12:18.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:12:18.82#ibcon#*before write, iclass 33, count 0 2006.211.08:12:18.82#ibcon#enter sib2, iclass 33, count 0 2006.211.08:12:18.82#ibcon#flushed, iclass 33, count 0 2006.211.08:12:18.82#ibcon#about to write, iclass 33, count 0 2006.211.08:12:18.82#ibcon#wrote, iclass 33, count 0 2006.211.08:12:18.82#ibcon#about to read 3, iclass 33, count 0 2006.211.08:12:18.86#ibcon#read 3, iclass 33, count 0 2006.211.08:12:18.86#ibcon#about to read 4, iclass 33, count 0 2006.211.08:12:18.86#ibcon#read 4, iclass 33, count 0 2006.211.08:12:18.86#ibcon#about to read 5, iclass 33, count 0 2006.211.08:12:18.86#ibcon#read 5, iclass 33, count 0 2006.211.08:12:18.86#ibcon#about to read 6, iclass 33, count 0 2006.211.08:12:18.86#ibcon#read 6, iclass 33, count 0 2006.211.08:12:18.86#ibcon#end of sib2, iclass 33, count 0 2006.211.08:12:18.86#ibcon#*after write, iclass 33, count 0 2006.211.08:12:18.86#ibcon#*before return 0, iclass 33, count 0 2006.211.08:12:18.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:18.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:18.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:12:18.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:12:18.86$vc4f8/va=5,7 2006.211.08:12:18.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:12:18.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:12:18.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:18.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:18.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:18.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:18.92#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:12:18.92#ibcon#first serial, iclass 35, count 2 2006.211.08:12:18.92#ibcon#enter sib2, iclass 35, count 2 2006.211.08:12:18.92#ibcon#flushed, iclass 35, count 2 2006.211.08:12:18.92#ibcon#about to write, iclass 35, count 2 2006.211.08:12:18.92#ibcon#wrote, iclass 35, count 2 2006.211.08:12:18.92#ibcon#about to read 3, iclass 35, count 2 2006.211.08:12:18.94#ibcon#read 3, iclass 35, count 2 2006.211.08:12:18.94#ibcon#about to read 4, iclass 35, count 2 2006.211.08:12:18.94#ibcon#read 4, iclass 35, count 2 2006.211.08:12:18.94#ibcon#about to read 5, iclass 35, count 2 2006.211.08:12:18.94#ibcon#read 5, iclass 35, count 2 2006.211.08:12:18.94#ibcon#about to read 6, iclass 35, count 2 2006.211.08:12:18.94#ibcon#read 6, iclass 35, count 2 2006.211.08:12:18.94#ibcon#end of sib2, iclass 35, count 2 2006.211.08:12:18.94#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:12:18.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:12:18.94#ibcon#[25=AT05-07\r\n] 2006.211.08:12:18.94#ibcon#*before write, iclass 35, count 2 2006.211.08:12:18.94#ibcon#enter sib2, iclass 35, count 2 2006.211.08:12:18.94#ibcon#flushed, iclass 35, count 2 2006.211.08:12:18.94#ibcon#about to write, iclass 35, count 2 2006.211.08:12:18.94#ibcon#wrote, iclass 35, count 2 2006.211.08:12:18.94#ibcon#about to read 3, iclass 35, count 2 2006.211.08:12:18.97#ibcon#read 3, iclass 35, count 2 2006.211.08:12:18.97#ibcon#about to read 4, iclass 35, count 2 2006.211.08:12:18.97#ibcon#read 4, iclass 35, count 2 2006.211.08:12:18.97#ibcon#about to read 5, iclass 35, count 2 2006.211.08:12:18.97#ibcon#read 5, iclass 35, count 2 2006.211.08:12:18.97#ibcon#about to read 6, iclass 35, count 2 2006.211.08:12:18.97#ibcon#read 6, iclass 35, count 2 2006.211.08:12:18.97#ibcon#end of sib2, iclass 35, count 2 2006.211.08:12:18.97#ibcon#*after write, iclass 35, count 2 2006.211.08:12:18.97#ibcon#*before return 0, iclass 35, count 2 2006.211.08:12:18.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:18.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:18.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:12:18.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:18.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:19.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:19.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:19.09#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:12:19.09#ibcon#first serial, iclass 35, count 0 2006.211.08:12:19.09#ibcon#enter sib2, iclass 35, count 0 2006.211.08:12:19.09#ibcon#flushed, iclass 35, count 0 2006.211.08:12:19.09#ibcon#about to write, iclass 35, count 0 2006.211.08:12:19.09#ibcon#wrote, iclass 35, count 0 2006.211.08:12:19.09#ibcon#about to read 3, iclass 35, count 0 2006.211.08:12:19.11#ibcon#read 3, iclass 35, count 0 2006.211.08:12:19.11#ibcon#about to read 4, iclass 35, count 0 2006.211.08:12:19.11#ibcon#read 4, iclass 35, count 0 2006.211.08:12:19.11#ibcon#about to read 5, iclass 35, count 0 2006.211.08:12:19.11#ibcon#read 5, iclass 35, count 0 2006.211.08:12:19.11#ibcon#about to read 6, iclass 35, count 0 2006.211.08:12:19.11#ibcon#read 6, iclass 35, count 0 2006.211.08:12:19.11#ibcon#end of sib2, iclass 35, count 0 2006.211.08:12:19.11#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:12:19.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:12:19.11#ibcon#[25=USB\r\n] 2006.211.08:12:19.11#ibcon#*before write, iclass 35, count 0 2006.211.08:12:19.11#ibcon#enter sib2, iclass 35, count 0 2006.211.08:12:19.11#ibcon#flushed, iclass 35, count 0 2006.211.08:12:19.11#ibcon#about to write, iclass 35, count 0 2006.211.08:12:19.11#ibcon#wrote, iclass 35, count 0 2006.211.08:12:19.11#ibcon#about to read 3, iclass 35, count 0 2006.211.08:12:19.14#ibcon#read 3, iclass 35, count 0 2006.211.08:12:19.14#ibcon#about to read 4, iclass 35, count 0 2006.211.08:12:19.14#ibcon#read 4, iclass 35, count 0 2006.211.08:12:19.14#ibcon#about to read 5, iclass 35, count 0 2006.211.08:12:19.14#ibcon#read 5, iclass 35, count 0 2006.211.08:12:19.14#ibcon#about to read 6, iclass 35, count 0 2006.211.08:12:19.14#ibcon#read 6, iclass 35, count 0 2006.211.08:12:19.14#ibcon#end of sib2, iclass 35, count 0 2006.211.08:12:19.14#ibcon#*after write, iclass 35, count 0 2006.211.08:12:19.14#ibcon#*before return 0, iclass 35, count 0 2006.211.08:12:19.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:19.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:19.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:12:19.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:12:19.14$vc4f8/valo=6,772.99 2006.211.08:12:19.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:12:19.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:12:19.14#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:19.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:19.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:19.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:19.14#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:12:19.14#ibcon#first serial, iclass 37, count 0 2006.211.08:12:19.14#ibcon#enter sib2, iclass 37, count 0 2006.211.08:12:19.14#ibcon#flushed, iclass 37, count 0 2006.211.08:12:19.14#ibcon#about to write, iclass 37, count 0 2006.211.08:12:19.14#ibcon#wrote, iclass 37, count 0 2006.211.08:12:19.14#ibcon#about to read 3, iclass 37, count 0 2006.211.08:12:19.16#ibcon#read 3, iclass 37, count 0 2006.211.08:12:19.16#ibcon#about to read 4, iclass 37, count 0 2006.211.08:12:19.16#ibcon#read 4, iclass 37, count 0 2006.211.08:12:19.16#ibcon#about to read 5, iclass 37, count 0 2006.211.08:12:19.16#ibcon#read 5, iclass 37, count 0 2006.211.08:12:19.16#ibcon#about to read 6, iclass 37, count 0 2006.211.08:12:19.16#ibcon#read 6, iclass 37, count 0 2006.211.08:12:19.16#ibcon#end of sib2, iclass 37, count 0 2006.211.08:12:19.16#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:12:19.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:12:19.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:12:19.16#ibcon#*before write, iclass 37, count 0 2006.211.08:12:19.16#ibcon#enter sib2, iclass 37, count 0 2006.211.08:12:19.16#ibcon#flushed, iclass 37, count 0 2006.211.08:12:19.16#ibcon#about to write, iclass 37, count 0 2006.211.08:12:19.16#ibcon#wrote, iclass 37, count 0 2006.211.08:12:19.16#ibcon#about to read 3, iclass 37, count 0 2006.211.08:12:19.20#ibcon#read 3, iclass 37, count 0 2006.211.08:12:19.20#ibcon#about to read 4, iclass 37, count 0 2006.211.08:12:19.20#ibcon#read 4, iclass 37, count 0 2006.211.08:12:19.20#ibcon#about to read 5, iclass 37, count 0 2006.211.08:12:19.20#ibcon#read 5, iclass 37, count 0 2006.211.08:12:19.20#ibcon#about to read 6, iclass 37, count 0 2006.211.08:12:19.20#ibcon#read 6, iclass 37, count 0 2006.211.08:12:19.20#ibcon#end of sib2, iclass 37, count 0 2006.211.08:12:19.20#ibcon#*after write, iclass 37, count 0 2006.211.08:12:19.20#ibcon#*before return 0, iclass 37, count 0 2006.211.08:12:19.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:19.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:19.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:12:19.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:12:19.20$vc4f8/va=6,6 2006.211.08:12:19.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:12:19.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:12:19.20#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:19.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:19.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:19.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:19.26#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:12:19.26#ibcon#first serial, iclass 39, count 2 2006.211.08:12:19.26#ibcon#enter sib2, iclass 39, count 2 2006.211.08:12:19.26#ibcon#flushed, iclass 39, count 2 2006.211.08:12:19.26#ibcon#about to write, iclass 39, count 2 2006.211.08:12:19.26#ibcon#wrote, iclass 39, count 2 2006.211.08:12:19.26#ibcon#about to read 3, iclass 39, count 2 2006.211.08:12:19.28#ibcon#read 3, iclass 39, count 2 2006.211.08:12:19.28#ibcon#about to read 4, iclass 39, count 2 2006.211.08:12:19.28#ibcon#read 4, iclass 39, count 2 2006.211.08:12:19.28#ibcon#about to read 5, iclass 39, count 2 2006.211.08:12:19.28#ibcon#read 5, iclass 39, count 2 2006.211.08:12:19.28#ibcon#about to read 6, iclass 39, count 2 2006.211.08:12:19.28#ibcon#read 6, iclass 39, count 2 2006.211.08:12:19.28#ibcon#end of sib2, iclass 39, count 2 2006.211.08:12:19.28#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:12:19.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:12:19.28#ibcon#[25=AT06-06\r\n] 2006.211.08:12:19.28#ibcon#*before write, iclass 39, count 2 2006.211.08:12:19.28#ibcon#enter sib2, iclass 39, count 2 2006.211.08:12:19.28#ibcon#flushed, iclass 39, count 2 2006.211.08:12:19.28#ibcon#about to write, iclass 39, count 2 2006.211.08:12:19.28#ibcon#wrote, iclass 39, count 2 2006.211.08:12:19.28#ibcon#about to read 3, iclass 39, count 2 2006.211.08:12:19.31#ibcon#read 3, iclass 39, count 2 2006.211.08:12:19.31#ibcon#about to read 4, iclass 39, count 2 2006.211.08:12:19.31#ibcon#read 4, iclass 39, count 2 2006.211.08:12:19.31#ibcon#about to read 5, iclass 39, count 2 2006.211.08:12:19.31#ibcon#read 5, iclass 39, count 2 2006.211.08:12:19.31#ibcon#about to read 6, iclass 39, count 2 2006.211.08:12:19.31#ibcon#read 6, iclass 39, count 2 2006.211.08:12:19.31#ibcon#end of sib2, iclass 39, count 2 2006.211.08:12:19.31#ibcon#*after write, iclass 39, count 2 2006.211.08:12:19.31#ibcon#*before return 0, iclass 39, count 2 2006.211.08:12:19.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:19.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:19.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:12:19.31#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:19.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:19.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:19.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:19.43#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:12:19.43#ibcon#first serial, iclass 39, count 0 2006.211.08:12:19.43#ibcon#enter sib2, iclass 39, count 0 2006.211.08:12:19.43#ibcon#flushed, iclass 39, count 0 2006.211.08:12:19.43#ibcon#about to write, iclass 39, count 0 2006.211.08:12:19.43#ibcon#wrote, iclass 39, count 0 2006.211.08:12:19.43#ibcon#about to read 3, iclass 39, count 0 2006.211.08:12:19.45#ibcon#read 3, iclass 39, count 0 2006.211.08:12:19.45#ibcon#about to read 4, iclass 39, count 0 2006.211.08:12:19.45#ibcon#read 4, iclass 39, count 0 2006.211.08:12:19.45#ibcon#about to read 5, iclass 39, count 0 2006.211.08:12:19.45#ibcon#read 5, iclass 39, count 0 2006.211.08:12:19.45#ibcon#about to read 6, iclass 39, count 0 2006.211.08:12:19.45#ibcon#read 6, iclass 39, count 0 2006.211.08:12:19.45#ibcon#end of sib2, iclass 39, count 0 2006.211.08:12:19.45#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:12:19.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:12:19.45#ibcon#[25=USB\r\n] 2006.211.08:12:19.45#ibcon#*before write, iclass 39, count 0 2006.211.08:12:19.45#ibcon#enter sib2, iclass 39, count 0 2006.211.08:12:19.45#ibcon#flushed, iclass 39, count 0 2006.211.08:12:19.45#ibcon#about to write, iclass 39, count 0 2006.211.08:12:19.45#ibcon#wrote, iclass 39, count 0 2006.211.08:12:19.45#ibcon#about to read 3, iclass 39, count 0 2006.211.08:12:19.48#ibcon#read 3, iclass 39, count 0 2006.211.08:12:19.48#ibcon#about to read 4, iclass 39, count 0 2006.211.08:12:19.48#ibcon#read 4, iclass 39, count 0 2006.211.08:12:19.48#ibcon#about to read 5, iclass 39, count 0 2006.211.08:12:19.48#ibcon#read 5, iclass 39, count 0 2006.211.08:12:19.48#ibcon#about to read 6, iclass 39, count 0 2006.211.08:12:19.48#ibcon#read 6, iclass 39, count 0 2006.211.08:12:19.48#ibcon#end of sib2, iclass 39, count 0 2006.211.08:12:19.48#ibcon#*after write, iclass 39, count 0 2006.211.08:12:19.48#ibcon#*before return 0, iclass 39, count 0 2006.211.08:12:19.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:19.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:19.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:12:19.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:12:19.48$vc4f8/valo=7,832.99 2006.211.08:12:19.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:12:19.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:12:19.48#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:19.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:19.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:19.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:19.48#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:12:19.48#ibcon#first serial, iclass 3, count 0 2006.211.08:12:19.48#ibcon#enter sib2, iclass 3, count 0 2006.211.08:12:19.48#ibcon#flushed, iclass 3, count 0 2006.211.08:12:19.48#ibcon#about to write, iclass 3, count 0 2006.211.08:12:19.48#ibcon#wrote, iclass 3, count 0 2006.211.08:12:19.48#ibcon#about to read 3, iclass 3, count 0 2006.211.08:12:19.50#ibcon#read 3, iclass 3, count 0 2006.211.08:12:19.50#ibcon#about to read 4, iclass 3, count 0 2006.211.08:12:19.50#ibcon#read 4, iclass 3, count 0 2006.211.08:12:19.50#ibcon#about to read 5, iclass 3, count 0 2006.211.08:12:19.50#ibcon#read 5, iclass 3, count 0 2006.211.08:12:19.50#ibcon#about to read 6, iclass 3, count 0 2006.211.08:12:19.50#ibcon#read 6, iclass 3, count 0 2006.211.08:12:19.50#ibcon#end of sib2, iclass 3, count 0 2006.211.08:12:19.50#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:12:19.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:12:19.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:12:19.50#ibcon#*before write, iclass 3, count 0 2006.211.08:12:19.50#ibcon#enter sib2, iclass 3, count 0 2006.211.08:12:19.50#ibcon#flushed, iclass 3, count 0 2006.211.08:12:19.50#ibcon#about to write, iclass 3, count 0 2006.211.08:12:19.50#ibcon#wrote, iclass 3, count 0 2006.211.08:12:19.50#ibcon#about to read 3, iclass 3, count 0 2006.211.08:12:19.54#ibcon#read 3, iclass 3, count 0 2006.211.08:12:19.54#ibcon#about to read 4, iclass 3, count 0 2006.211.08:12:19.54#ibcon#read 4, iclass 3, count 0 2006.211.08:12:19.54#ibcon#about to read 5, iclass 3, count 0 2006.211.08:12:19.54#ibcon#read 5, iclass 3, count 0 2006.211.08:12:19.54#ibcon#about to read 6, iclass 3, count 0 2006.211.08:12:19.54#ibcon#read 6, iclass 3, count 0 2006.211.08:12:19.54#ibcon#end of sib2, iclass 3, count 0 2006.211.08:12:19.54#ibcon#*after write, iclass 3, count 0 2006.211.08:12:19.54#ibcon#*before return 0, iclass 3, count 0 2006.211.08:12:19.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:19.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:19.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:12:19.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:12:19.54$vc4f8/va=7,6 2006.211.08:12:19.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:12:19.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:12:19.54#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:19.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:12:19.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:12:19.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:12:19.60#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:12:19.60#ibcon#first serial, iclass 5, count 2 2006.211.08:12:19.60#ibcon#enter sib2, iclass 5, count 2 2006.211.08:12:19.60#ibcon#flushed, iclass 5, count 2 2006.211.08:12:19.60#ibcon#about to write, iclass 5, count 2 2006.211.08:12:19.60#ibcon#wrote, iclass 5, count 2 2006.211.08:12:19.60#ibcon#about to read 3, iclass 5, count 2 2006.211.08:12:19.62#ibcon#read 3, iclass 5, count 2 2006.211.08:12:19.62#ibcon#about to read 4, iclass 5, count 2 2006.211.08:12:19.62#ibcon#read 4, iclass 5, count 2 2006.211.08:12:19.62#ibcon#about to read 5, iclass 5, count 2 2006.211.08:12:19.62#ibcon#read 5, iclass 5, count 2 2006.211.08:12:19.62#ibcon#about to read 6, iclass 5, count 2 2006.211.08:12:19.62#ibcon#read 6, iclass 5, count 2 2006.211.08:12:19.62#ibcon#end of sib2, iclass 5, count 2 2006.211.08:12:19.62#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:12:19.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:12:19.62#ibcon#[25=AT07-06\r\n] 2006.211.08:12:19.62#ibcon#*before write, iclass 5, count 2 2006.211.08:12:19.62#ibcon#enter sib2, iclass 5, count 2 2006.211.08:12:19.62#ibcon#flushed, iclass 5, count 2 2006.211.08:12:19.62#ibcon#about to write, iclass 5, count 2 2006.211.08:12:19.62#ibcon#wrote, iclass 5, count 2 2006.211.08:12:19.62#ibcon#about to read 3, iclass 5, count 2 2006.211.08:12:19.65#ibcon#read 3, iclass 5, count 2 2006.211.08:12:19.65#ibcon#about to read 4, iclass 5, count 2 2006.211.08:12:19.65#ibcon#read 4, iclass 5, count 2 2006.211.08:12:19.65#ibcon#about to read 5, iclass 5, count 2 2006.211.08:12:19.65#ibcon#read 5, iclass 5, count 2 2006.211.08:12:19.65#ibcon#about to read 6, iclass 5, count 2 2006.211.08:12:19.65#ibcon#read 6, iclass 5, count 2 2006.211.08:12:19.65#ibcon#end of sib2, iclass 5, count 2 2006.211.08:12:19.65#ibcon#*after write, iclass 5, count 2 2006.211.08:12:19.65#ibcon#*before return 0, iclass 5, count 2 2006.211.08:12:19.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:12:19.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:12:19.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:12:19.65#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:19.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:12:19.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:12:19.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:12:19.77#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:12:19.77#ibcon#first serial, iclass 5, count 0 2006.211.08:12:19.77#ibcon#enter sib2, iclass 5, count 0 2006.211.08:12:19.77#ibcon#flushed, iclass 5, count 0 2006.211.08:12:19.77#ibcon#about to write, iclass 5, count 0 2006.211.08:12:19.77#ibcon#wrote, iclass 5, count 0 2006.211.08:12:19.77#ibcon#about to read 3, iclass 5, count 0 2006.211.08:12:19.79#ibcon#read 3, iclass 5, count 0 2006.211.08:12:19.79#ibcon#about to read 4, iclass 5, count 0 2006.211.08:12:19.79#ibcon#read 4, iclass 5, count 0 2006.211.08:12:19.79#ibcon#about to read 5, iclass 5, count 0 2006.211.08:12:19.79#ibcon#read 5, iclass 5, count 0 2006.211.08:12:19.79#ibcon#about to read 6, iclass 5, count 0 2006.211.08:12:19.79#ibcon#read 6, iclass 5, count 0 2006.211.08:12:19.79#ibcon#end of sib2, iclass 5, count 0 2006.211.08:12:19.79#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:12:19.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:12:19.79#ibcon#[25=USB\r\n] 2006.211.08:12:19.79#ibcon#*before write, iclass 5, count 0 2006.211.08:12:19.79#ibcon#enter sib2, iclass 5, count 0 2006.211.08:12:19.79#ibcon#flushed, iclass 5, count 0 2006.211.08:12:19.79#ibcon#about to write, iclass 5, count 0 2006.211.08:12:19.79#ibcon#wrote, iclass 5, count 0 2006.211.08:12:19.79#ibcon#about to read 3, iclass 5, count 0 2006.211.08:12:19.82#ibcon#read 3, iclass 5, count 0 2006.211.08:12:19.82#ibcon#about to read 4, iclass 5, count 0 2006.211.08:12:19.82#ibcon#read 4, iclass 5, count 0 2006.211.08:12:19.82#ibcon#about to read 5, iclass 5, count 0 2006.211.08:12:19.82#ibcon#read 5, iclass 5, count 0 2006.211.08:12:19.82#ibcon#about to read 6, iclass 5, count 0 2006.211.08:12:19.82#ibcon#read 6, iclass 5, count 0 2006.211.08:12:19.82#ibcon#end of sib2, iclass 5, count 0 2006.211.08:12:19.82#ibcon#*after write, iclass 5, count 0 2006.211.08:12:19.82#ibcon#*before return 0, iclass 5, count 0 2006.211.08:12:19.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:12:19.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:12:19.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:12:19.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:12:19.82$vc4f8/valo=8,852.99 2006.211.08:12:19.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:12:19.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:12:19.82#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:19.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:12:19.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:12:19.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:12:19.82#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:12:19.82#ibcon#first serial, iclass 7, count 0 2006.211.08:12:19.82#ibcon#enter sib2, iclass 7, count 0 2006.211.08:12:19.82#ibcon#flushed, iclass 7, count 0 2006.211.08:12:19.82#ibcon#about to write, iclass 7, count 0 2006.211.08:12:19.82#ibcon#wrote, iclass 7, count 0 2006.211.08:12:19.82#ibcon#about to read 3, iclass 7, count 0 2006.211.08:12:19.84#ibcon#read 3, iclass 7, count 0 2006.211.08:12:19.84#ibcon#about to read 4, iclass 7, count 0 2006.211.08:12:19.84#ibcon#read 4, iclass 7, count 0 2006.211.08:12:19.84#ibcon#about to read 5, iclass 7, count 0 2006.211.08:12:19.84#ibcon#read 5, iclass 7, count 0 2006.211.08:12:19.84#ibcon#about to read 6, iclass 7, count 0 2006.211.08:12:19.84#ibcon#read 6, iclass 7, count 0 2006.211.08:12:19.84#ibcon#end of sib2, iclass 7, count 0 2006.211.08:12:19.84#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:12:19.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:12:19.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:12:19.84#ibcon#*before write, iclass 7, count 0 2006.211.08:12:19.84#ibcon#enter sib2, iclass 7, count 0 2006.211.08:12:19.84#ibcon#flushed, iclass 7, count 0 2006.211.08:12:19.84#ibcon#about to write, iclass 7, count 0 2006.211.08:12:19.84#ibcon#wrote, iclass 7, count 0 2006.211.08:12:19.84#ibcon#about to read 3, iclass 7, count 0 2006.211.08:12:19.88#ibcon#read 3, iclass 7, count 0 2006.211.08:12:19.88#ibcon#about to read 4, iclass 7, count 0 2006.211.08:12:19.88#ibcon#read 4, iclass 7, count 0 2006.211.08:12:19.88#ibcon#about to read 5, iclass 7, count 0 2006.211.08:12:19.88#ibcon#read 5, iclass 7, count 0 2006.211.08:12:19.88#ibcon#about to read 6, iclass 7, count 0 2006.211.08:12:19.88#ibcon#read 6, iclass 7, count 0 2006.211.08:12:19.88#ibcon#end of sib2, iclass 7, count 0 2006.211.08:12:19.88#ibcon#*after write, iclass 7, count 0 2006.211.08:12:19.88#ibcon#*before return 0, iclass 7, count 0 2006.211.08:12:19.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:12:19.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:12:19.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:12:19.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:12:19.88$vc4f8/va=8,7 2006.211.08:12:19.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:12:19.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:12:19.88#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:19.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:12:19.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:12:19.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:12:19.94#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:12:19.94#ibcon#first serial, iclass 11, count 2 2006.211.08:12:19.94#ibcon#enter sib2, iclass 11, count 2 2006.211.08:12:19.94#ibcon#flushed, iclass 11, count 2 2006.211.08:12:19.94#ibcon#about to write, iclass 11, count 2 2006.211.08:12:19.94#ibcon#wrote, iclass 11, count 2 2006.211.08:12:19.94#ibcon#about to read 3, iclass 11, count 2 2006.211.08:12:19.96#ibcon#read 3, iclass 11, count 2 2006.211.08:12:19.96#ibcon#about to read 4, iclass 11, count 2 2006.211.08:12:19.96#ibcon#read 4, iclass 11, count 2 2006.211.08:12:19.96#ibcon#about to read 5, iclass 11, count 2 2006.211.08:12:19.96#ibcon#read 5, iclass 11, count 2 2006.211.08:12:19.96#ibcon#about to read 6, iclass 11, count 2 2006.211.08:12:19.96#ibcon#read 6, iclass 11, count 2 2006.211.08:12:19.96#ibcon#end of sib2, iclass 11, count 2 2006.211.08:12:19.96#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:12:19.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:12:19.96#ibcon#[25=AT08-07\r\n] 2006.211.08:12:19.96#ibcon#*before write, iclass 11, count 2 2006.211.08:12:19.96#ibcon#enter sib2, iclass 11, count 2 2006.211.08:12:19.96#ibcon#flushed, iclass 11, count 2 2006.211.08:12:19.96#ibcon#about to write, iclass 11, count 2 2006.211.08:12:19.96#ibcon#wrote, iclass 11, count 2 2006.211.08:12:19.96#ibcon#about to read 3, iclass 11, count 2 2006.211.08:12:19.99#ibcon#read 3, iclass 11, count 2 2006.211.08:12:19.99#ibcon#about to read 4, iclass 11, count 2 2006.211.08:12:19.99#ibcon#read 4, iclass 11, count 2 2006.211.08:12:19.99#ibcon#about to read 5, iclass 11, count 2 2006.211.08:12:19.99#ibcon#read 5, iclass 11, count 2 2006.211.08:12:19.99#ibcon#about to read 6, iclass 11, count 2 2006.211.08:12:19.99#ibcon#read 6, iclass 11, count 2 2006.211.08:12:19.99#ibcon#end of sib2, iclass 11, count 2 2006.211.08:12:19.99#ibcon#*after write, iclass 11, count 2 2006.211.08:12:19.99#ibcon#*before return 0, iclass 11, count 2 2006.211.08:12:19.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:12:19.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:12:19.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:12:19.99#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:19.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:12:20.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:12:20.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:12:20.11#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:12:20.11#ibcon#first serial, iclass 11, count 0 2006.211.08:12:20.11#ibcon#enter sib2, iclass 11, count 0 2006.211.08:12:20.11#ibcon#flushed, iclass 11, count 0 2006.211.08:12:20.11#ibcon#about to write, iclass 11, count 0 2006.211.08:12:20.11#ibcon#wrote, iclass 11, count 0 2006.211.08:12:20.11#ibcon#about to read 3, iclass 11, count 0 2006.211.08:12:20.13#ibcon#read 3, iclass 11, count 0 2006.211.08:12:20.13#ibcon#about to read 4, iclass 11, count 0 2006.211.08:12:20.13#ibcon#read 4, iclass 11, count 0 2006.211.08:12:20.13#ibcon#about to read 5, iclass 11, count 0 2006.211.08:12:20.13#ibcon#read 5, iclass 11, count 0 2006.211.08:12:20.13#ibcon#about to read 6, iclass 11, count 0 2006.211.08:12:20.13#ibcon#read 6, iclass 11, count 0 2006.211.08:12:20.13#ibcon#end of sib2, iclass 11, count 0 2006.211.08:12:20.13#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:12:20.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:12:20.13#ibcon#[25=USB\r\n] 2006.211.08:12:20.13#ibcon#*before write, iclass 11, count 0 2006.211.08:12:20.13#ibcon#enter sib2, iclass 11, count 0 2006.211.08:12:20.13#ibcon#flushed, iclass 11, count 0 2006.211.08:12:20.13#ibcon#about to write, iclass 11, count 0 2006.211.08:12:20.13#ibcon#wrote, iclass 11, count 0 2006.211.08:12:20.13#ibcon#about to read 3, iclass 11, count 0 2006.211.08:12:20.16#ibcon#read 3, iclass 11, count 0 2006.211.08:12:20.16#ibcon#about to read 4, iclass 11, count 0 2006.211.08:12:20.16#ibcon#read 4, iclass 11, count 0 2006.211.08:12:20.16#ibcon#about to read 5, iclass 11, count 0 2006.211.08:12:20.16#ibcon#read 5, iclass 11, count 0 2006.211.08:12:20.16#ibcon#about to read 6, iclass 11, count 0 2006.211.08:12:20.16#ibcon#read 6, iclass 11, count 0 2006.211.08:12:20.16#ibcon#end of sib2, iclass 11, count 0 2006.211.08:12:20.16#ibcon#*after write, iclass 11, count 0 2006.211.08:12:20.16#ibcon#*before return 0, iclass 11, count 0 2006.211.08:12:20.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:12:20.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:12:20.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:12:20.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:12:20.16$vc4f8/vblo=1,632.99 2006.211.08:12:20.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:12:20.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:12:20.16#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:20.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:12:20.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:12:20.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:12:20.16#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:12:20.16#ibcon#first serial, iclass 13, count 0 2006.211.08:12:20.16#ibcon#enter sib2, iclass 13, count 0 2006.211.08:12:20.16#ibcon#flushed, iclass 13, count 0 2006.211.08:12:20.16#ibcon#about to write, iclass 13, count 0 2006.211.08:12:20.16#ibcon#wrote, iclass 13, count 0 2006.211.08:12:20.16#ibcon#about to read 3, iclass 13, count 0 2006.211.08:12:20.18#ibcon#read 3, iclass 13, count 0 2006.211.08:12:20.18#ibcon#about to read 4, iclass 13, count 0 2006.211.08:12:20.18#ibcon#read 4, iclass 13, count 0 2006.211.08:12:20.18#ibcon#about to read 5, iclass 13, count 0 2006.211.08:12:20.18#ibcon#read 5, iclass 13, count 0 2006.211.08:12:20.18#ibcon#about to read 6, iclass 13, count 0 2006.211.08:12:20.18#ibcon#read 6, iclass 13, count 0 2006.211.08:12:20.18#ibcon#end of sib2, iclass 13, count 0 2006.211.08:12:20.18#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:12:20.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:12:20.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:12:20.18#ibcon#*before write, iclass 13, count 0 2006.211.08:12:20.18#ibcon#enter sib2, iclass 13, count 0 2006.211.08:12:20.18#ibcon#flushed, iclass 13, count 0 2006.211.08:12:20.18#ibcon#about to write, iclass 13, count 0 2006.211.08:12:20.18#ibcon#wrote, iclass 13, count 0 2006.211.08:12:20.18#ibcon#about to read 3, iclass 13, count 0 2006.211.08:12:20.22#ibcon#read 3, iclass 13, count 0 2006.211.08:12:20.22#ibcon#about to read 4, iclass 13, count 0 2006.211.08:12:20.22#ibcon#read 4, iclass 13, count 0 2006.211.08:12:20.22#ibcon#about to read 5, iclass 13, count 0 2006.211.08:12:20.22#ibcon#read 5, iclass 13, count 0 2006.211.08:12:20.22#ibcon#about to read 6, iclass 13, count 0 2006.211.08:12:20.22#ibcon#read 6, iclass 13, count 0 2006.211.08:12:20.22#ibcon#end of sib2, iclass 13, count 0 2006.211.08:12:20.22#ibcon#*after write, iclass 13, count 0 2006.211.08:12:20.22#ibcon#*before return 0, iclass 13, count 0 2006.211.08:12:20.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:12:20.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:12:20.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:12:20.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:12:20.22$vc4f8/vb=1,4 2006.211.08:12:20.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:12:20.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:12:20.22#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:20.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:12:20.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:12:20.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:12:20.22#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:12:20.22#ibcon#first serial, iclass 15, count 2 2006.211.08:12:20.22#ibcon#enter sib2, iclass 15, count 2 2006.211.08:12:20.22#ibcon#flushed, iclass 15, count 2 2006.211.08:12:20.22#ibcon#about to write, iclass 15, count 2 2006.211.08:12:20.22#ibcon#wrote, iclass 15, count 2 2006.211.08:12:20.22#ibcon#about to read 3, iclass 15, count 2 2006.211.08:12:20.24#ibcon#read 3, iclass 15, count 2 2006.211.08:12:20.24#ibcon#about to read 4, iclass 15, count 2 2006.211.08:12:20.24#ibcon#read 4, iclass 15, count 2 2006.211.08:12:20.24#ibcon#about to read 5, iclass 15, count 2 2006.211.08:12:20.24#ibcon#read 5, iclass 15, count 2 2006.211.08:12:20.24#ibcon#about to read 6, iclass 15, count 2 2006.211.08:12:20.24#ibcon#read 6, iclass 15, count 2 2006.211.08:12:20.24#ibcon#end of sib2, iclass 15, count 2 2006.211.08:12:20.24#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:12:20.24#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:12:20.24#ibcon#[27=AT01-04\r\n] 2006.211.08:12:20.24#ibcon#*before write, iclass 15, count 2 2006.211.08:12:20.24#ibcon#enter sib2, iclass 15, count 2 2006.211.08:12:20.24#ibcon#flushed, iclass 15, count 2 2006.211.08:12:20.24#ibcon#about to write, iclass 15, count 2 2006.211.08:12:20.24#ibcon#wrote, iclass 15, count 2 2006.211.08:12:20.24#ibcon#about to read 3, iclass 15, count 2 2006.211.08:12:20.27#ibcon#read 3, iclass 15, count 2 2006.211.08:12:20.27#ibcon#about to read 4, iclass 15, count 2 2006.211.08:12:20.27#ibcon#read 4, iclass 15, count 2 2006.211.08:12:20.27#ibcon#about to read 5, iclass 15, count 2 2006.211.08:12:20.27#ibcon#read 5, iclass 15, count 2 2006.211.08:12:20.27#ibcon#about to read 6, iclass 15, count 2 2006.211.08:12:20.27#ibcon#read 6, iclass 15, count 2 2006.211.08:12:20.27#ibcon#end of sib2, iclass 15, count 2 2006.211.08:12:20.27#ibcon#*after write, iclass 15, count 2 2006.211.08:12:20.27#ibcon#*before return 0, iclass 15, count 2 2006.211.08:12:20.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:12:20.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:12:20.27#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:12:20.27#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:20.27#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:12:20.39#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:12:20.39#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:12:20.39#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:12:20.39#ibcon#first serial, iclass 15, count 0 2006.211.08:12:20.39#ibcon#enter sib2, iclass 15, count 0 2006.211.08:12:20.39#ibcon#flushed, iclass 15, count 0 2006.211.08:12:20.39#ibcon#about to write, iclass 15, count 0 2006.211.08:12:20.39#ibcon#wrote, iclass 15, count 0 2006.211.08:12:20.39#ibcon#about to read 3, iclass 15, count 0 2006.211.08:12:20.41#ibcon#read 3, iclass 15, count 0 2006.211.08:12:20.41#ibcon#about to read 4, iclass 15, count 0 2006.211.08:12:20.41#ibcon#read 4, iclass 15, count 0 2006.211.08:12:20.41#ibcon#about to read 5, iclass 15, count 0 2006.211.08:12:20.41#ibcon#read 5, iclass 15, count 0 2006.211.08:12:20.41#ibcon#about to read 6, iclass 15, count 0 2006.211.08:12:20.41#ibcon#read 6, iclass 15, count 0 2006.211.08:12:20.41#ibcon#end of sib2, iclass 15, count 0 2006.211.08:12:20.41#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:12:20.41#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:12:20.41#ibcon#[27=USB\r\n] 2006.211.08:12:20.41#ibcon#*before write, iclass 15, count 0 2006.211.08:12:20.41#ibcon#enter sib2, iclass 15, count 0 2006.211.08:12:20.41#ibcon#flushed, iclass 15, count 0 2006.211.08:12:20.41#ibcon#about to write, iclass 15, count 0 2006.211.08:12:20.41#ibcon#wrote, iclass 15, count 0 2006.211.08:12:20.41#ibcon#about to read 3, iclass 15, count 0 2006.211.08:12:20.44#ibcon#read 3, iclass 15, count 0 2006.211.08:12:20.44#ibcon#about to read 4, iclass 15, count 0 2006.211.08:12:20.44#ibcon#read 4, iclass 15, count 0 2006.211.08:12:20.44#ibcon#about to read 5, iclass 15, count 0 2006.211.08:12:20.44#ibcon#read 5, iclass 15, count 0 2006.211.08:12:20.44#ibcon#about to read 6, iclass 15, count 0 2006.211.08:12:20.44#ibcon#read 6, iclass 15, count 0 2006.211.08:12:20.44#ibcon#end of sib2, iclass 15, count 0 2006.211.08:12:20.44#ibcon#*after write, iclass 15, count 0 2006.211.08:12:20.44#ibcon#*before return 0, iclass 15, count 0 2006.211.08:12:20.44#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:12:20.44#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:12:20.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:12:20.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:12:20.44$vc4f8/vblo=2,640.99 2006.211.08:12:20.44#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:12:20.44#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:12:20.44#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:20.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:20.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:20.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:20.44#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:12:20.44#ibcon#first serial, iclass 17, count 0 2006.211.08:12:20.44#ibcon#enter sib2, iclass 17, count 0 2006.211.08:12:20.44#ibcon#flushed, iclass 17, count 0 2006.211.08:12:20.44#ibcon#about to write, iclass 17, count 0 2006.211.08:12:20.44#ibcon#wrote, iclass 17, count 0 2006.211.08:12:20.44#ibcon#about to read 3, iclass 17, count 0 2006.211.08:12:20.46#ibcon#read 3, iclass 17, count 0 2006.211.08:12:20.46#ibcon#about to read 4, iclass 17, count 0 2006.211.08:12:20.46#ibcon#read 4, iclass 17, count 0 2006.211.08:12:20.46#ibcon#about to read 5, iclass 17, count 0 2006.211.08:12:20.46#ibcon#read 5, iclass 17, count 0 2006.211.08:12:20.46#ibcon#about to read 6, iclass 17, count 0 2006.211.08:12:20.46#ibcon#read 6, iclass 17, count 0 2006.211.08:12:20.46#ibcon#end of sib2, iclass 17, count 0 2006.211.08:12:20.46#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:12:20.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:12:20.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:12:20.46#ibcon#*before write, iclass 17, count 0 2006.211.08:12:20.46#ibcon#enter sib2, iclass 17, count 0 2006.211.08:12:20.46#ibcon#flushed, iclass 17, count 0 2006.211.08:12:20.46#ibcon#about to write, iclass 17, count 0 2006.211.08:12:20.46#ibcon#wrote, iclass 17, count 0 2006.211.08:12:20.46#ibcon#about to read 3, iclass 17, count 0 2006.211.08:12:20.50#ibcon#read 3, iclass 17, count 0 2006.211.08:12:20.50#ibcon#about to read 4, iclass 17, count 0 2006.211.08:12:20.50#ibcon#read 4, iclass 17, count 0 2006.211.08:12:20.50#ibcon#about to read 5, iclass 17, count 0 2006.211.08:12:20.50#ibcon#read 5, iclass 17, count 0 2006.211.08:12:20.50#ibcon#about to read 6, iclass 17, count 0 2006.211.08:12:20.50#ibcon#read 6, iclass 17, count 0 2006.211.08:12:20.50#ibcon#end of sib2, iclass 17, count 0 2006.211.08:12:20.50#ibcon#*after write, iclass 17, count 0 2006.211.08:12:20.50#ibcon#*before return 0, iclass 17, count 0 2006.211.08:12:20.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:20.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:12:20.50#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:12:20.50#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:12:20.50$vc4f8/vb=2,4 2006.211.08:12:20.50#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:12:20.50#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:12:20.50#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:20.50#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:20.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:20.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:20.56#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:12:20.56#ibcon#first serial, iclass 19, count 2 2006.211.08:12:20.56#ibcon#enter sib2, iclass 19, count 2 2006.211.08:12:20.56#ibcon#flushed, iclass 19, count 2 2006.211.08:12:20.56#ibcon#about to write, iclass 19, count 2 2006.211.08:12:20.56#ibcon#wrote, iclass 19, count 2 2006.211.08:12:20.56#ibcon#about to read 3, iclass 19, count 2 2006.211.08:12:20.58#ibcon#read 3, iclass 19, count 2 2006.211.08:12:20.58#ibcon#about to read 4, iclass 19, count 2 2006.211.08:12:20.58#ibcon#read 4, iclass 19, count 2 2006.211.08:12:20.58#ibcon#about to read 5, iclass 19, count 2 2006.211.08:12:20.58#ibcon#read 5, iclass 19, count 2 2006.211.08:12:20.58#ibcon#about to read 6, iclass 19, count 2 2006.211.08:12:20.58#ibcon#read 6, iclass 19, count 2 2006.211.08:12:20.58#ibcon#end of sib2, iclass 19, count 2 2006.211.08:12:20.58#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:12:20.58#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:12:20.58#ibcon#[27=AT02-04\r\n] 2006.211.08:12:20.58#ibcon#*before write, iclass 19, count 2 2006.211.08:12:20.58#ibcon#enter sib2, iclass 19, count 2 2006.211.08:12:20.58#ibcon#flushed, iclass 19, count 2 2006.211.08:12:20.58#ibcon#about to write, iclass 19, count 2 2006.211.08:12:20.58#ibcon#wrote, iclass 19, count 2 2006.211.08:12:20.58#ibcon#about to read 3, iclass 19, count 2 2006.211.08:12:20.61#ibcon#read 3, iclass 19, count 2 2006.211.08:12:20.61#ibcon#about to read 4, iclass 19, count 2 2006.211.08:12:20.61#ibcon#read 4, iclass 19, count 2 2006.211.08:12:20.61#ibcon#about to read 5, iclass 19, count 2 2006.211.08:12:20.61#ibcon#read 5, iclass 19, count 2 2006.211.08:12:20.61#ibcon#about to read 6, iclass 19, count 2 2006.211.08:12:20.61#ibcon#read 6, iclass 19, count 2 2006.211.08:12:20.61#ibcon#end of sib2, iclass 19, count 2 2006.211.08:12:20.61#ibcon#*after write, iclass 19, count 2 2006.211.08:12:20.61#ibcon#*before return 0, iclass 19, count 2 2006.211.08:12:20.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:20.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:12:20.61#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:12:20.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:20.61#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:20.73#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:20.73#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:20.73#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:12:20.73#ibcon#first serial, iclass 19, count 0 2006.211.08:12:20.73#ibcon#enter sib2, iclass 19, count 0 2006.211.08:12:20.73#ibcon#flushed, iclass 19, count 0 2006.211.08:12:20.73#ibcon#about to write, iclass 19, count 0 2006.211.08:12:20.73#ibcon#wrote, iclass 19, count 0 2006.211.08:12:20.73#ibcon#about to read 3, iclass 19, count 0 2006.211.08:12:20.75#ibcon#read 3, iclass 19, count 0 2006.211.08:12:20.75#ibcon#about to read 4, iclass 19, count 0 2006.211.08:12:20.75#ibcon#read 4, iclass 19, count 0 2006.211.08:12:20.75#ibcon#about to read 5, iclass 19, count 0 2006.211.08:12:20.75#ibcon#read 5, iclass 19, count 0 2006.211.08:12:20.75#ibcon#about to read 6, iclass 19, count 0 2006.211.08:12:20.75#ibcon#read 6, iclass 19, count 0 2006.211.08:12:20.75#ibcon#end of sib2, iclass 19, count 0 2006.211.08:12:20.75#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:12:20.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:12:20.75#ibcon#[27=USB\r\n] 2006.211.08:12:20.75#ibcon#*before write, iclass 19, count 0 2006.211.08:12:20.75#ibcon#enter sib2, iclass 19, count 0 2006.211.08:12:20.75#ibcon#flushed, iclass 19, count 0 2006.211.08:12:20.75#ibcon#about to write, iclass 19, count 0 2006.211.08:12:20.75#ibcon#wrote, iclass 19, count 0 2006.211.08:12:20.75#ibcon#about to read 3, iclass 19, count 0 2006.211.08:12:20.78#ibcon#read 3, iclass 19, count 0 2006.211.08:12:20.78#ibcon#about to read 4, iclass 19, count 0 2006.211.08:12:20.78#ibcon#read 4, iclass 19, count 0 2006.211.08:12:20.78#ibcon#about to read 5, iclass 19, count 0 2006.211.08:12:20.78#ibcon#read 5, iclass 19, count 0 2006.211.08:12:20.78#ibcon#about to read 6, iclass 19, count 0 2006.211.08:12:20.78#ibcon#read 6, iclass 19, count 0 2006.211.08:12:20.78#ibcon#end of sib2, iclass 19, count 0 2006.211.08:12:20.78#ibcon#*after write, iclass 19, count 0 2006.211.08:12:20.78#ibcon#*before return 0, iclass 19, count 0 2006.211.08:12:20.78#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:20.78#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:12:20.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:12:20.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:12:20.78$vc4f8/vblo=3,656.99 2006.211.08:12:20.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:12:20.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:12:20.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:20.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:12:20.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:12:20.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:12:20.78#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:12:20.78#ibcon#first serial, iclass 22, count 0 2006.211.08:12:20.78#ibcon#enter sib2, iclass 22, count 0 2006.211.08:12:20.78#ibcon#flushed, iclass 22, count 0 2006.211.08:12:20.78#ibcon#about to write, iclass 22, count 0 2006.211.08:12:20.78#ibcon#wrote, iclass 22, count 0 2006.211.08:12:20.78#ibcon#about to read 3, iclass 22, count 0 2006.211.08:12:20.80#ibcon#read 3, iclass 22, count 0 2006.211.08:12:20.80#ibcon#about to read 4, iclass 22, count 0 2006.211.08:12:20.80#ibcon#read 4, iclass 22, count 0 2006.211.08:12:20.80#ibcon#about to read 5, iclass 22, count 0 2006.211.08:12:20.80#ibcon#read 5, iclass 22, count 0 2006.211.08:12:20.80#ibcon#about to read 6, iclass 22, count 0 2006.211.08:12:20.80#ibcon#read 6, iclass 22, count 0 2006.211.08:12:20.80#ibcon#end of sib2, iclass 22, count 0 2006.211.08:12:20.80#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:12:20.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:12:20.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:12:20.80#ibcon#*before write, iclass 22, count 0 2006.211.08:12:20.80#ibcon#enter sib2, iclass 22, count 0 2006.211.08:12:20.80#ibcon#flushed, iclass 22, count 0 2006.211.08:12:20.80#ibcon#about to write, iclass 22, count 0 2006.211.08:12:20.80#ibcon#wrote, iclass 22, count 0 2006.211.08:12:20.80#ibcon#about to read 3, iclass 22, count 0 2006.211.08:12:20.82#abcon#<5=/04 4.5 8.0 24.57 791010.1\r\n> 2006.211.08:12:20.84#abcon#{5=INTERFACE CLEAR} 2006.211.08:12:20.84#ibcon#read 3, iclass 22, count 0 2006.211.08:12:20.84#ibcon#about to read 4, iclass 22, count 0 2006.211.08:12:20.84#ibcon#read 4, iclass 22, count 0 2006.211.08:12:20.84#ibcon#about to read 5, iclass 22, count 0 2006.211.08:12:20.84#ibcon#read 5, iclass 22, count 0 2006.211.08:12:20.84#ibcon#about to read 6, iclass 22, count 0 2006.211.08:12:20.84#ibcon#read 6, iclass 22, count 0 2006.211.08:12:20.84#ibcon#end of sib2, iclass 22, count 0 2006.211.08:12:20.84#ibcon#*after write, iclass 22, count 0 2006.211.08:12:20.84#ibcon#*before return 0, iclass 22, count 0 2006.211.08:12:20.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:12:20.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:12:20.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:12:20.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:12:20.84$vc4f8/vb=3,3 2006.211.08:12:20.84#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.211.08:12:20.84#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.211.08:12:20.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:20.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:12:20.90#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:12:20.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:12:20.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:12:20.90#ibcon#enter wrdev, iclass 26, count 2 2006.211.08:12:20.90#ibcon#first serial, iclass 26, count 2 2006.211.08:12:20.90#ibcon#enter sib2, iclass 26, count 2 2006.211.08:12:20.90#ibcon#flushed, iclass 26, count 2 2006.211.08:12:20.90#ibcon#about to write, iclass 26, count 2 2006.211.08:12:20.90#ibcon#wrote, iclass 26, count 2 2006.211.08:12:20.90#ibcon#about to read 3, iclass 26, count 2 2006.211.08:12:20.92#ibcon#read 3, iclass 26, count 2 2006.211.08:12:20.92#ibcon#about to read 4, iclass 26, count 2 2006.211.08:12:20.92#ibcon#read 4, iclass 26, count 2 2006.211.08:12:20.92#ibcon#about to read 5, iclass 26, count 2 2006.211.08:12:20.92#ibcon#read 5, iclass 26, count 2 2006.211.08:12:20.92#ibcon#about to read 6, iclass 26, count 2 2006.211.08:12:20.92#ibcon#read 6, iclass 26, count 2 2006.211.08:12:20.92#ibcon#end of sib2, iclass 26, count 2 2006.211.08:12:20.92#ibcon#*mode == 0, iclass 26, count 2 2006.211.08:12:20.92#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.211.08:12:20.92#ibcon#[27=AT03-03\r\n] 2006.211.08:12:20.92#ibcon#*before write, iclass 26, count 2 2006.211.08:12:20.92#ibcon#enter sib2, iclass 26, count 2 2006.211.08:12:20.92#ibcon#flushed, iclass 26, count 2 2006.211.08:12:20.92#ibcon#about to write, iclass 26, count 2 2006.211.08:12:20.92#ibcon#wrote, iclass 26, count 2 2006.211.08:12:20.92#ibcon#about to read 3, iclass 26, count 2 2006.211.08:12:20.95#ibcon#read 3, iclass 26, count 2 2006.211.08:12:20.95#ibcon#about to read 4, iclass 26, count 2 2006.211.08:12:20.95#ibcon#read 4, iclass 26, count 2 2006.211.08:12:20.95#ibcon#about to read 5, iclass 26, count 2 2006.211.08:12:20.95#ibcon#read 5, iclass 26, count 2 2006.211.08:12:20.95#ibcon#about to read 6, iclass 26, count 2 2006.211.08:12:20.95#ibcon#read 6, iclass 26, count 2 2006.211.08:12:20.95#ibcon#end of sib2, iclass 26, count 2 2006.211.08:12:20.95#ibcon#*after write, iclass 26, count 2 2006.211.08:12:20.95#ibcon#*before return 0, iclass 26, count 2 2006.211.08:12:20.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:12:20.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.211.08:12:20.95#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.211.08:12:20.95#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:20.95#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:12:21.07#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:12:21.07#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:12:21.07#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:12:21.07#ibcon#first serial, iclass 26, count 0 2006.211.08:12:21.07#ibcon#enter sib2, iclass 26, count 0 2006.211.08:12:21.07#ibcon#flushed, iclass 26, count 0 2006.211.08:12:21.07#ibcon#about to write, iclass 26, count 0 2006.211.08:12:21.07#ibcon#wrote, iclass 26, count 0 2006.211.08:12:21.07#ibcon#about to read 3, iclass 26, count 0 2006.211.08:12:21.09#ibcon#read 3, iclass 26, count 0 2006.211.08:12:21.09#ibcon#about to read 4, iclass 26, count 0 2006.211.08:12:21.09#ibcon#read 4, iclass 26, count 0 2006.211.08:12:21.09#ibcon#about to read 5, iclass 26, count 0 2006.211.08:12:21.09#ibcon#read 5, iclass 26, count 0 2006.211.08:12:21.09#ibcon#about to read 6, iclass 26, count 0 2006.211.08:12:21.09#ibcon#read 6, iclass 26, count 0 2006.211.08:12:21.09#ibcon#end of sib2, iclass 26, count 0 2006.211.08:12:21.09#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:12:21.09#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:12:21.09#ibcon#[27=USB\r\n] 2006.211.08:12:21.09#ibcon#*before write, iclass 26, count 0 2006.211.08:12:21.09#ibcon#enter sib2, iclass 26, count 0 2006.211.08:12:21.09#ibcon#flushed, iclass 26, count 0 2006.211.08:12:21.09#ibcon#about to write, iclass 26, count 0 2006.211.08:12:21.09#ibcon#wrote, iclass 26, count 0 2006.211.08:12:21.09#ibcon#about to read 3, iclass 26, count 0 2006.211.08:12:21.12#ibcon#read 3, iclass 26, count 0 2006.211.08:12:21.12#ibcon#about to read 4, iclass 26, count 0 2006.211.08:12:21.12#ibcon#read 4, iclass 26, count 0 2006.211.08:12:21.12#ibcon#about to read 5, iclass 26, count 0 2006.211.08:12:21.12#ibcon#read 5, iclass 26, count 0 2006.211.08:12:21.12#ibcon#about to read 6, iclass 26, count 0 2006.211.08:12:21.12#ibcon#read 6, iclass 26, count 0 2006.211.08:12:21.12#ibcon#end of sib2, iclass 26, count 0 2006.211.08:12:21.12#ibcon#*after write, iclass 26, count 0 2006.211.08:12:21.12#ibcon#*before return 0, iclass 26, count 0 2006.211.08:12:21.12#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:12:21.12#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.211.08:12:21.12#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:12:21.12#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:12:21.12$vc4f8/vblo=4,712.99 2006.211.08:12:21.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:12:21.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:12:21.12#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:21.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:21.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:21.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:21.12#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:12:21.12#ibcon#first serial, iclass 29, count 0 2006.211.08:12:21.12#ibcon#enter sib2, iclass 29, count 0 2006.211.08:12:21.12#ibcon#flushed, iclass 29, count 0 2006.211.08:12:21.12#ibcon#about to write, iclass 29, count 0 2006.211.08:12:21.12#ibcon#wrote, iclass 29, count 0 2006.211.08:12:21.12#ibcon#about to read 3, iclass 29, count 0 2006.211.08:12:21.14#ibcon#read 3, iclass 29, count 0 2006.211.08:12:21.14#ibcon#about to read 4, iclass 29, count 0 2006.211.08:12:21.14#ibcon#read 4, iclass 29, count 0 2006.211.08:12:21.14#ibcon#about to read 5, iclass 29, count 0 2006.211.08:12:21.14#ibcon#read 5, iclass 29, count 0 2006.211.08:12:21.14#ibcon#about to read 6, iclass 29, count 0 2006.211.08:12:21.14#ibcon#read 6, iclass 29, count 0 2006.211.08:12:21.14#ibcon#end of sib2, iclass 29, count 0 2006.211.08:12:21.14#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:12:21.14#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:12:21.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:12:21.14#ibcon#*before write, iclass 29, count 0 2006.211.08:12:21.14#ibcon#enter sib2, iclass 29, count 0 2006.211.08:12:21.14#ibcon#flushed, iclass 29, count 0 2006.211.08:12:21.14#ibcon#about to write, iclass 29, count 0 2006.211.08:12:21.14#ibcon#wrote, iclass 29, count 0 2006.211.08:12:21.14#ibcon#about to read 3, iclass 29, count 0 2006.211.08:12:21.18#ibcon#read 3, iclass 29, count 0 2006.211.08:12:21.18#ibcon#about to read 4, iclass 29, count 0 2006.211.08:12:21.18#ibcon#read 4, iclass 29, count 0 2006.211.08:12:21.18#ibcon#about to read 5, iclass 29, count 0 2006.211.08:12:21.18#ibcon#read 5, iclass 29, count 0 2006.211.08:12:21.18#ibcon#about to read 6, iclass 29, count 0 2006.211.08:12:21.18#ibcon#read 6, iclass 29, count 0 2006.211.08:12:21.18#ibcon#end of sib2, iclass 29, count 0 2006.211.08:12:21.18#ibcon#*after write, iclass 29, count 0 2006.211.08:12:21.18#ibcon#*before return 0, iclass 29, count 0 2006.211.08:12:21.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:21.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:12:21.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:12:21.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:12:21.18$vc4f8/vb=4,3 2006.211.08:12:21.18#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.08:12:21.18#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.08:12:21.18#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:21.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:21.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:21.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:21.24#ibcon#enter wrdev, iclass 31, count 2 2006.211.08:12:21.24#ibcon#first serial, iclass 31, count 2 2006.211.08:12:21.24#ibcon#enter sib2, iclass 31, count 2 2006.211.08:12:21.24#ibcon#flushed, iclass 31, count 2 2006.211.08:12:21.24#ibcon#about to write, iclass 31, count 2 2006.211.08:12:21.24#ibcon#wrote, iclass 31, count 2 2006.211.08:12:21.24#ibcon#about to read 3, iclass 31, count 2 2006.211.08:12:21.26#ibcon#read 3, iclass 31, count 2 2006.211.08:12:21.26#ibcon#about to read 4, iclass 31, count 2 2006.211.08:12:21.26#ibcon#read 4, iclass 31, count 2 2006.211.08:12:21.26#ibcon#about to read 5, iclass 31, count 2 2006.211.08:12:21.26#ibcon#read 5, iclass 31, count 2 2006.211.08:12:21.26#ibcon#about to read 6, iclass 31, count 2 2006.211.08:12:21.26#ibcon#read 6, iclass 31, count 2 2006.211.08:12:21.26#ibcon#end of sib2, iclass 31, count 2 2006.211.08:12:21.26#ibcon#*mode == 0, iclass 31, count 2 2006.211.08:12:21.26#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.08:12:21.26#ibcon#[27=AT04-03\r\n] 2006.211.08:12:21.26#ibcon#*before write, iclass 31, count 2 2006.211.08:12:21.26#ibcon#enter sib2, iclass 31, count 2 2006.211.08:12:21.26#ibcon#flushed, iclass 31, count 2 2006.211.08:12:21.26#ibcon#about to write, iclass 31, count 2 2006.211.08:12:21.26#ibcon#wrote, iclass 31, count 2 2006.211.08:12:21.26#ibcon#about to read 3, iclass 31, count 2 2006.211.08:12:21.29#ibcon#read 3, iclass 31, count 2 2006.211.08:12:21.29#ibcon#about to read 4, iclass 31, count 2 2006.211.08:12:21.29#ibcon#read 4, iclass 31, count 2 2006.211.08:12:21.29#ibcon#about to read 5, iclass 31, count 2 2006.211.08:12:21.29#ibcon#read 5, iclass 31, count 2 2006.211.08:12:21.29#ibcon#about to read 6, iclass 31, count 2 2006.211.08:12:21.29#ibcon#read 6, iclass 31, count 2 2006.211.08:12:21.29#ibcon#end of sib2, iclass 31, count 2 2006.211.08:12:21.29#ibcon#*after write, iclass 31, count 2 2006.211.08:12:21.29#ibcon#*before return 0, iclass 31, count 2 2006.211.08:12:21.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:21.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:12:21.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.08:12:21.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:21.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:21.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:21.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:21.41#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:12:21.41#ibcon#first serial, iclass 31, count 0 2006.211.08:12:21.41#ibcon#enter sib2, iclass 31, count 0 2006.211.08:12:21.41#ibcon#flushed, iclass 31, count 0 2006.211.08:12:21.41#ibcon#about to write, iclass 31, count 0 2006.211.08:12:21.41#ibcon#wrote, iclass 31, count 0 2006.211.08:12:21.41#ibcon#about to read 3, iclass 31, count 0 2006.211.08:12:21.43#ibcon#read 3, iclass 31, count 0 2006.211.08:12:21.43#ibcon#about to read 4, iclass 31, count 0 2006.211.08:12:21.43#ibcon#read 4, iclass 31, count 0 2006.211.08:12:21.43#ibcon#about to read 5, iclass 31, count 0 2006.211.08:12:21.43#ibcon#read 5, iclass 31, count 0 2006.211.08:12:21.43#ibcon#about to read 6, iclass 31, count 0 2006.211.08:12:21.43#ibcon#read 6, iclass 31, count 0 2006.211.08:12:21.43#ibcon#end of sib2, iclass 31, count 0 2006.211.08:12:21.43#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:12:21.43#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:12:21.43#ibcon#[27=USB\r\n] 2006.211.08:12:21.43#ibcon#*before write, iclass 31, count 0 2006.211.08:12:21.43#ibcon#enter sib2, iclass 31, count 0 2006.211.08:12:21.43#ibcon#flushed, iclass 31, count 0 2006.211.08:12:21.43#ibcon#about to write, iclass 31, count 0 2006.211.08:12:21.43#ibcon#wrote, iclass 31, count 0 2006.211.08:12:21.43#ibcon#about to read 3, iclass 31, count 0 2006.211.08:12:21.46#ibcon#read 3, iclass 31, count 0 2006.211.08:12:21.46#ibcon#about to read 4, iclass 31, count 0 2006.211.08:12:21.46#ibcon#read 4, iclass 31, count 0 2006.211.08:12:21.46#ibcon#about to read 5, iclass 31, count 0 2006.211.08:12:21.46#ibcon#read 5, iclass 31, count 0 2006.211.08:12:21.46#ibcon#about to read 6, iclass 31, count 0 2006.211.08:12:21.46#ibcon#read 6, iclass 31, count 0 2006.211.08:12:21.46#ibcon#end of sib2, iclass 31, count 0 2006.211.08:12:21.46#ibcon#*after write, iclass 31, count 0 2006.211.08:12:21.46#ibcon#*before return 0, iclass 31, count 0 2006.211.08:12:21.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:21.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:12:21.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:12:21.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:12:21.46$vc4f8/vblo=5,744.99 2006.211.08:12:21.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.08:12:21.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.08:12:21.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:21.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:21.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:21.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:21.46#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:12:21.46#ibcon#first serial, iclass 33, count 0 2006.211.08:12:21.46#ibcon#enter sib2, iclass 33, count 0 2006.211.08:12:21.46#ibcon#flushed, iclass 33, count 0 2006.211.08:12:21.46#ibcon#about to write, iclass 33, count 0 2006.211.08:12:21.46#ibcon#wrote, iclass 33, count 0 2006.211.08:12:21.46#ibcon#about to read 3, iclass 33, count 0 2006.211.08:12:21.48#ibcon#read 3, iclass 33, count 0 2006.211.08:12:21.48#ibcon#about to read 4, iclass 33, count 0 2006.211.08:12:21.48#ibcon#read 4, iclass 33, count 0 2006.211.08:12:21.48#ibcon#about to read 5, iclass 33, count 0 2006.211.08:12:21.48#ibcon#read 5, iclass 33, count 0 2006.211.08:12:21.48#ibcon#about to read 6, iclass 33, count 0 2006.211.08:12:21.48#ibcon#read 6, iclass 33, count 0 2006.211.08:12:21.48#ibcon#end of sib2, iclass 33, count 0 2006.211.08:12:21.48#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:12:21.48#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:12:21.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:12:21.48#ibcon#*before write, iclass 33, count 0 2006.211.08:12:21.48#ibcon#enter sib2, iclass 33, count 0 2006.211.08:12:21.48#ibcon#flushed, iclass 33, count 0 2006.211.08:12:21.48#ibcon#about to write, iclass 33, count 0 2006.211.08:12:21.48#ibcon#wrote, iclass 33, count 0 2006.211.08:12:21.48#ibcon#about to read 3, iclass 33, count 0 2006.211.08:12:21.52#ibcon#read 3, iclass 33, count 0 2006.211.08:12:21.52#ibcon#about to read 4, iclass 33, count 0 2006.211.08:12:21.52#ibcon#read 4, iclass 33, count 0 2006.211.08:12:21.52#ibcon#about to read 5, iclass 33, count 0 2006.211.08:12:21.52#ibcon#read 5, iclass 33, count 0 2006.211.08:12:21.52#ibcon#about to read 6, iclass 33, count 0 2006.211.08:12:21.52#ibcon#read 6, iclass 33, count 0 2006.211.08:12:21.52#ibcon#end of sib2, iclass 33, count 0 2006.211.08:12:21.52#ibcon#*after write, iclass 33, count 0 2006.211.08:12:21.52#ibcon#*before return 0, iclass 33, count 0 2006.211.08:12:21.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:21.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:12:21.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:12:21.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:12:21.52$vc4f8/vb=5,3 2006.211.08:12:21.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:12:21.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:12:21.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:21.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:21.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:21.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:21.58#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:12:21.58#ibcon#first serial, iclass 35, count 2 2006.211.08:12:21.58#ibcon#enter sib2, iclass 35, count 2 2006.211.08:12:21.58#ibcon#flushed, iclass 35, count 2 2006.211.08:12:21.58#ibcon#about to write, iclass 35, count 2 2006.211.08:12:21.58#ibcon#wrote, iclass 35, count 2 2006.211.08:12:21.58#ibcon#about to read 3, iclass 35, count 2 2006.211.08:12:21.60#ibcon#read 3, iclass 35, count 2 2006.211.08:12:21.60#ibcon#about to read 4, iclass 35, count 2 2006.211.08:12:21.60#ibcon#read 4, iclass 35, count 2 2006.211.08:12:21.60#ibcon#about to read 5, iclass 35, count 2 2006.211.08:12:21.60#ibcon#read 5, iclass 35, count 2 2006.211.08:12:21.60#ibcon#about to read 6, iclass 35, count 2 2006.211.08:12:21.60#ibcon#read 6, iclass 35, count 2 2006.211.08:12:21.60#ibcon#end of sib2, iclass 35, count 2 2006.211.08:12:21.60#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:12:21.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:12:21.60#ibcon#[27=AT05-03\r\n] 2006.211.08:12:21.60#ibcon#*before write, iclass 35, count 2 2006.211.08:12:21.60#ibcon#enter sib2, iclass 35, count 2 2006.211.08:12:21.60#ibcon#flushed, iclass 35, count 2 2006.211.08:12:21.60#ibcon#about to write, iclass 35, count 2 2006.211.08:12:21.60#ibcon#wrote, iclass 35, count 2 2006.211.08:12:21.60#ibcon#about to read 3, iclass 35, count 2 2006.211.08:12:21.63#ibcon#read 3, iclass 35, count 2 2006.211.08:12:21.63#ibcon#about to read 4, iclass 35, count 2 2006.211.08:12:21.63#ibcon#read 4, iclass 35, count 2 2006.211.08:12:21.63#ibcon#about to read 5, iclass 35, count 2 2006.211.08:12:21.63#ibcon#read 5, iclass 35, count 2 2006.211.08:12:21.63#ibcon#about to read 6, iclass 35, count 2 2006.211.08:12:21.63#ibcon#read 6, iclass 35, count 2 2006.211.08:12:21.63#ibcon#end of sib2, iclass 35, count 2 2006.211.08:12:21.63#ibcon#*after write, iclass 35, count 2 2006.211.08:12:21.63#ibcon#*before return 0, iclass 35, count 2 2006.211.08:12:21.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:21.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:12:21.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:12:21.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:21.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:21.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:21.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:21.75#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:12:21.75#ibcon#first serial, iclass 35, count 0 2006.211.08:12:21.75#ibcon#enter sib2, iclass 35, count 0 2006.211.08:12:21.75#ibcon#flushed, iclass 35, count 0 2006.211.08:12:21.75#ibcon#about to write, iclass 35, count 0 2006.211.08:12:21.75#ibcon#wrote, iclass 35, count 0 2006.211.08:12:21.75#ibcon#about to read 3, iclass 35, count 0 2006.211.08:12:21.77#ibcon#read 3, iclass 35, count 0 2006.211.08:12:21.77#ibcon#about to read 4, iclass 35, count 0 2006.211.08:12:21.77#ibcon#read 4, iclass 35, count 0 2006.211.08:12:21.77#ibcon#about to read 5, iclass 35, count 0 2006.211.08:12:21.77#ibcon#read 5, iclass 35, count 0 2006.211.08:12:21.77#ibcon#about to read 6, iclass 35, count 0 2006.211.08:12:21.77#ibcon#read 6, iclass 35, count 0 2006.211.08:12:21.77#ibcon#end of sib2, iclass 35, count 0 2006.211.08:12:21.77#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:12:21.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:12:21.77#ibcon#[27=USB\r\n] 2006.211.08:12:21.77#ibcon#*before write, iclass 35, count 0 2006.211.08:12:21.77#ibcon#enter sib2, iclass 35, count 0 2006.211.08:12:21.77#ibcon#flushed, iclass 35, count 0 2006.211.08:12:21.77#ibcon#about to write, iclass 35, count 0 2006.211.08:12:21.77#ibcon#wrote, iclass 35, count 0 2006.211.08:12:21.77#ibcon#about to read 3, iclass 35, count 0 2006.211.08:12:21.80#ibcon#read 3, iclass 35, count 0 2006.211.08:12:21.80#ibcon#about to read 4, iclass 35, count 0 2006.211.08:12:21.80#ibcon#read 4, iclass 35, count 0 2006.211.08:12:21.80#ibcon#about to read 5, iclass 35, count 0 2006.211.08:12:21.80#ibcon#read 5, iclass 35, count 0 2006.211.08:12:21.80#ibcon#about to read 6, iclass 35, count 0 2006.211.08:12:21.80#ibcon#read 6, iclass 35, count 0 2006.211.08:12:21.80#ibcon#end of sib2, iclass 35, count 0 2006.211.08:12:21.80#ibcon#*after write, iclass 35, count 0 2006.211.08:12:21.80#ibcon#*before return 0, iclass 35, count 0 2006.211.08:12:21.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:21.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:12:21.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:12:21.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:12:21.80$vc4f8/vblo=6,752.99 2006.211.08:12:21.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:12:21.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:12:21.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:12:21.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:21.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:21.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:21.80#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:12:21.80#ibcon#first serial, iclass 37, count 0 2006.211.08:12:21.80#ibcon#enter sib2, iclass 37, count 0 2006.211.08:12:21.80#ibcon#flushed, iclass 37, count 0 2006.211.08:12:21.80#ibcon#about to write, iclass 37, count 0 2006.211.08:12:21.80#ibcon#wrote, iclass 37, count 0 2006.211.08:12:21.80#ibcon#about to read 3, iclass 37, count 0 2006.211.08:12:21.82#ibcon#read 3, iclass 37, count 0 2006.211.08:12:21.82#ibcon#about to read 4, iclass 37, count 0 2006.211.08:12:21.82#ibcon#read 4, iclass 37, count 0 2006.211.08:12:21.82#ibcon#about to read 5, iclass 37, count 0 2006.211.08:12:21.82#ibcon#read 5, iclass 37, count 0 2006.211.08:12:21.82#ibcon#about to read 6, iclass 37, count 0 2006.211.08:12:21.82#ibcon#read 6, iclass 37, count 0 2006.211.08:12:21.82#ibcon#end of sib2, iclass 37, count 0 2006.211.08:12:21.82#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:12:21.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:12:21.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:12:21.82#ibcon#*before write, iclass 37, count 0 2006.211.08:12:21.82#ibcon#enter sib2, iclass 37, count 0 2006.211.08:12:21.82#ibcon#flushed, iclass 37, count 0 2006.211.08:12:21.82#ibcon#about to write, iclass 37, count 0 2006.211.08:12:21.82#ibcon#wrote, iclass 37, count 0 2006.211.08:12:21.82#ibcon#about to read 3, iclass 37, count 0 2006.211.08:12:21.86#ibcon#read 3, iclass 37, count 0 2006.211.08:12:21.86#ibcon#about to read 4, iclass 37, count 0 2006.211.08:12:21.86#ibcon#read 4, iclass 37, count 0 2006.211.08:12:21.86#ibcon#about to read 5, iclass 37, count 0 2006.211.08:12:21.86#ibcon#read 5, iclass 37, count 0 2006.211.08:12:21.86#ibcon#about to read 6, iclass 37, count 0 2006.211.08:12:21.86#ibcon#read 6, iclass 37, count 0 2006.211.08:12:21.86#ibcon#end of sib2, iclass 37, count 0 2006.211.08:12:21.86#ibcon#*after write, iclass 37, count 0 2006.211.08:12:21.86#ibcon#*before return 0, iclass 37, count 0 2006.211.08:12:21.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:21.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:12:21.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:12:21.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:12:21.86$vc4f8/vb=6,3 2006.211.08:12:21.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:12:21.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:12:21.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:12:21.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:21.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:21.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:21.92#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:12:21.92#ibcon#first serial, iclass 39, count 2 2006.211.08:12:21.92#ibcon#enter sib2, iclass 39, count 2 2006.211.08:12:21.92#ibcon#flushed, iclass 39, count 2 2006.211.08:12:21.92#ibcon#about to write, iclass 39, count 2 2006.211.08:12:21.92#ibcon#wrote, iclass 39, count 2 2006.211.08:12:21.92#ibcon#about to read 3, iclass 39, count 2 2006.211.08:12:21.94#ibcon#read 3, iclass 39, count 2 2006.211.08:12:21.94#ibcon#about to read 4, iclass 39, count 2 2006.211.08:12:21.94#ibcon#read 4, iclass 39, count 2 2006.211.08:12:21.94#ibcon#about to read 5, iclass 39, count 2 2006.211.08:12:21.94#ibcon#read 5, iclass 39, count 2 2006.211.08:12:21.94#ibcon#about to read 6, iclass 39, count 2 2006.211.08:12:21.94#ibcon#read 6, iclass 39, count 2 2006.211.08:12:21.94#ibcon#end of sib2, iclass 39, count 2 2006.211.08:12:21.94#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:12:21.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:12:21.94#ibcon#[27=AT06-03\r\n] 2006.211.08:12:21.94#ibcon#*before write, iclass 39, count 2 2006.211.08:12:21.94#ibcon#enter sib2, iclass 39, count 2 2006.211.08:12:21.94#ibcon#flushed, iclass 39, count 2 2006.211.08:12:21.94#ibcon#about to write, iclass 39, count 2 2006.211.08:12:21.94#ibcon#wrote, iclass 39, count 2 2006.211.08:12:21.94#ibcon#about to read 3, iclass 39, count 2 2006.211.08:12:21.97#ibcon#read 3, iclass 39, count 2 2006.211.08:12:21.97#ibcon#about to read 4, iclass 39, count 2 2006.211.08:12:21.97#ibcon#read 4, iclass 39, count 2 2006.211.08:12:21.97#ibcon#about to read 5, iclass 39, count 2 2006.211.08:12:21.97#ibcon#read 5, iclass 39, count 2 2006.211.08:12:21.97#ibcon#about to read 6, iclass 39, count 2 2006.211.08:12:21.97#ibcon#read 6, iclass 39, count 2 2006.211.08:12:21.97#ibcon#end of sib2, iclass 39, count 2 2006.211.08:12:21.97#ibcon#*after write, iclass 39, count 2 2006.211.08:12:21.97#ibcon#*before return 0, iclass 39, count 2 2006.211.08:12:21.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:21.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:12:21.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:12:21.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:12:21.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:22.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:22.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:22.09#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:12:22.09#ibcon#first serial, iclass 39, count 0 2006.211.08:12:22.09#ibcon#enter sib2, iclass 39, count 0 2006.211.08:12:22.09#ibcon#flushed, iclass 39, count 0 2006.211.08:12:22.09#ibcon#about to write, iclass 39, count 0 2006.211.08:12:22.09#ibcon#wrote, iclass 39, count 0 2006.211.08:12:22.09#ibcon#about to read 3, iclass 39, count 0 2006.211.08:12:22.11#ibcon#read 3, iclass 39, count 0 2006.211.08:12:22.11#ibcon#about to read 4, iclass 39, count 0 2006.211.08:12:22.11#ibcon#read 4, iclass 39, count 0 2006.211.08:12:22.11#ibcon#about to read 5, iclass 39, count 0 2006.211.08:12:22.11#ibcon#read 5, iclass 39, count 0 2006.211.08:12:22.11#ibcon#about to read 6, iclass 39, count 0 2006.211.08:12:22.11#ibcon#read 6, iclass 39, count 0 2006.211.08:12:22.11#ibcon#end of sib2, iclass 39, count 0 2006.211.08:12:22.11#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:12:22.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:12:22.11#ibcon#[27=USB\r\n] 2006.211.08:12:22.11#ibcon#*before write, iclass 39, count 0 2006.211.08:12:22.11#ibcon#enter sib2, iclass 39, count 0 2006.211.08:12:22.11#ibcon#flushed, iclass 39, count 0 2006.211.08:12:22.11#ibcon#about to write, iclass 39, count 0 2006.211.08:12:22.11#ibcon#wrote, iclass 39, count 0 2006.211.08:12:22.11#ibcon#about to read 3, iclass 39, count 0 2006.211.08:12:22.14#ibcon#read 3, iclass 39, count 0 2006.211.08:12:22.14#ibcon#about to read 4, iclass 39, count 0 2006.211.08:12:22.14#ibcon#read 4, iclass 39, count 0 2006.211.08:12:22.14#ibcon#about to read 5, iclass 39, count 0 2006.211.08:12:22.14#ibcon#read 5, iclass 39, count 0 2006.211.08:12:22.14#ibcon#about to read 6, iclass 39, count 0 2006.211.08:12:22.14#ibcon#read 6, iclass 39, count 0 2006.211.08:12:22.14#ibcon#end of sib2, iclass 39, count 0 2006.211.08:12:22.14#ibcon#*after write, iclass 39, count 0 2006.211.08:12:22.14#ibcon#*before return 0, iclass 39, count 0 2006.211.08:12:22.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:22.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:12:22.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:12:22.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:12:22.14$vc4f8/vabw=wide 2006.211.08:12:22.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:12:22.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:12:22.14#ibcon#ireg 8 cls_cnt 0 2006.211.08:12:22.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:22.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:22.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:22.14#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:12:22.14#ibcon#first serial, iclass 3, count 0 2006.211.08:12:22.14#ibcon#enter sib2, iclass 3, count 0 2006.211.08:12:22.14#ibcon#flushed, iclass 3, count 0 2006.211.08:12:22.14#ibcon#about to write, iclass 3, count 0 2006.211.08:12:22.14#ibcon#wrote, iclass 3, count 0 2006.211.08:12:22.14#ibcon#about to read 3, iclass 3, count 0 2006.211.08:12:22.16#ibcon#read 3, iclass 3, count 0 2006.211.08:12:22.16#ibcon#about to read 4, iclass 3, count 0 2006.211.08:12:22.16#ibcon#read 4, iclass 3, count 0 2006.211.08:12:22.16#ibcon#about to read 5, iclass 3, count 0 2006.211.08:12:22.16#ibcon#read 5, iclass 3, count 0 2006.211.08:12:22.16#ibcon#about to read 6, iclass 3, count 0 2006.211.08:12:22.16#ibcon#read 6, iclass 3, count 0 2006.211.08:12:22.16#ibcon#end of sib2, iclass 3, count 0 2006.211.08:12:22.16#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:12:22.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:12:22.16#ibcon#[25=BW32\r\n] 2006.211.08:12:22.16#ibcon#*before write, iclass 3, count 0 2006.211.08:12:22.16#ibcon#enter sib2, iclass 3, count 0 2006.211.08:12:22.16#ibcon#flushed, iclass 3, count 0 2006.211.08:12:22.16#ibcon#about to write, iclass 3, count 0 2006.211.08:12:22.16#ibcon#wrote, iclass 3, count 0 2006.211.08:12:22.16#ibcon#about to read 3, iclass 3, count 0 2006.211.08:12:22.19#ibcon#read 3, iclass 3, count 0 2006.211.08:12:22.19#ibcon#about to read 4, iclass 3, count 0 2006.211.08:12:22.19#ibcon#read 4, iclass 3, count 0 2006.211.08:12:22.19#ibcon#about to read 5, iclass 3, count 0 2006.211.08:12:22.19#ibcon#read 5, iclass 3, count 0 2006.211.08:12:22.19#ibcon#about to read 6, iclass 3, count 0 2006.211.08:12:22.19#ibcon#read 6, iclass 3, count 0 2006.211.08:12:22.19#ibcon#end of sib2, iclass 3, count 0 2006.211.08:12:22.19#ibcon#*after write, iclass 3, count 0 2006.211.08:12:22.19#ibcon#*before return 0, iclass 3, count 0 2006.211.08:12:22.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:22.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:12:22.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:12:22.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:12:22.19$vc4f8/vbbw=wide 2006.211.08:12:22.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.08:12:22.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.08:12:22.19#ibcon#ireg 8 cls_cnt 0 2006.211.08:12:22.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:12:22.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:12:22.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:12:22.26#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:12:22.26#ibcon#first serial, iclass 5, count 0 2006.211.08:12:22.26#ibcon#enter sib2, iclass 5, count 0 2006.211.08:12:22.26#ibcon#flushed, iclass 5, count 0 2006.211.08:12:22.26#ibcon#about to write, iclass 5, count 0 2006.211.08:12:22.26#ibcon#wrote, iclass 5, count 0 2006.211.08:12:22.26#ibcon#about to read 3, iclass 5, count 0 2006.211.08:12:22.28#ibcon#read 3, iclass 5, count 0 2006.211.08:12:22.28#ibcon#about to read 4, iclass 5, count 0 2006.211.08:12:22.28#ibcon#read 4, iclass 5, count 0 2006.211.08:12:22.28#ibcon#about to read 5, iclass 5, count 0 2006.211.08:12:22.28#ibcon#read 5, iclass 5, count 0 2006.211.08:12:22.28#ibcon#about to read 6, iclass 5, count 0 2006.211.08:12:22.28#ibcon#read 6, iclass 5, count 0 2006.211.08:12:22.28#ibcon#end of sib2, iclass 5, count 0 2006.211.08:12:22.28#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:12:22.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:12:22.28#ibcon#[27=BW32\r\n] 2006.211.08:12:22.28#ibcon#*before write, iclass 5, count 0 2006.211.08:12:22.28#ibcon#enter sib2, iclass 5, count 0 2006.211.08:12:22.28#ibcon#flushed, iclass 5, count 0 2006.211.08:12:22.28#ibcon#about to write, iclass 5, count 0 2006.211.08:12:22.28#ibcon#wrote, iclass 5, count 0 2006.211.08:12:22.28#ibcon#about to read 3, iclass 5, count 0 2006.211.08:12:22.31#ibcon#read 3, iclass 5, count 0 2006.211.08:12:22.31#ibcon#about to read 4, iclass 5, count 0 2006.211.08:12:22.31#ibcon#read 4, iclass 5, count 0 2006.211.08:12:22.31#ibcon#about to read 5, iclass 5, count 0 2006.211.08:12:22.31#ibcon#read 5, iclass 5, count 0 2006.211.08:12:22.31#ibcon#about to read 6, iclass 5, count 0 2006.211.08:12:22.31#ibcon#read 6, iclass 5, count 0 2006.211.08:12:22.31#ibcon#end of sib2, iclass 5, count 0 2006.211.08:12:22.31#ibcon#*after write, iclass 5, count 0 2006.211.08:12:22.31#ibcon#*before return 0, iclass 5, count 0 2006.211.08:12:22.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:12:22.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:12:22.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:12:22.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:12:22.31$4f8m12a/ifd4f 2006.211.08:12:22.31$ifd4f/lo= 2006.211.08:12:22.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:12:22.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:12:22.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:12:22.31$ifd4f/patch= 2006.211.08:12:22.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:12:22.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:12:22.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:12:22.31$4f8m12a/"form=m,16.000,1:2 2006.211.08:12:22.31$4f8m12a/"tpicd 2006.211.08:12:22.31$4f8m12a/echo=off 2006.211.08:12:22.31$4f8m12a/xlog=off 2006.211.08:12:22.31:!2006.211.08:12:50 2006.211.08:12:32.13#trakl#Source acquired 2006.211.08:12:32.13#flagr#flagr/antenna,acquired 2006.211.08:12:50.00:preob 2006.211.08:12:51.13/onsource/TRACKING 2006.211.08:12:51.13:!2006.211.08:13:00 2006.211.08:13:00.00:data_valid=on 2006.211.08:13:00.00:midob 2006.211.08:13:00.13/onsource/TRACKING 2006.211.08:13:00.13/wx/24.56,1010.1,80 2006.211.08:13:00.25/cable/+6.4393E-03 2006.211.08:13:01.34/va/01,08,usb,yes,37,38 2006.211.08:13:01.34/va/02,07,usb,yes,37,38 2006.211.08:13:01.34/va/03,06,usb,yes,39,39 2006.211.08:13:01.34/va/04,07,usb,yes,38,40 2006.211.08:13:01.34/va/05,07,usb,yes,42,44 2006.211.08:13:01.34/va/06,06,usb,yes,41,41 2006.211.08:13:01.34/va/07,06,usb,yes,41,41 2006.211.08:13:01.34/va/08,07,usb,yes,39,39 2006.211.08:13:01.57/valo/01,532.99,yes,locked 2006.211.08:13:01.57/valo/02,572.99,yes,locked 2006.211.08:13:01.57/valo/03,672.99,yes,locked 2006.211.08:13:01.57/valo/04,832.99,yes,locked 2006.211.08:13:01.57/valo/05,652.99,yes,locked 2006.211.08:13:01.57/valo/06,772.99,yes,locked 2006.211.08:13:01.57/valo/07,832.99,yes,locked 2006.211.08:13:01.57/valo/08,852.99,yes,locked 2006.211.08:13:02.66/vb/01,04,usb,yes,33,31 2006.211.08:13:02.66/vb/02,04,usb,yes,35,36 2006.211.08:13:02.66/vb/03,03,usb,yes,38,43 2006.211.08:13:02.66/vb/04,03,usb,yes,40,40 2006.211.08:13:02.66/vb/05,03,usb,yes,38,43 2006.211.08:13:02.66/vb/06,03,usb,yes,39,43 2006.211.08:13:02.66/vb/07,04,usb,yes,34,34 2006.211.08:13:02.66/vb/08,03,usb,yes,39,43 2006.211.08:13:02.89/vblo/01,632.99,yes,locked 2006.211.08:13:02.89/vblo/02,640.99,yes,locked 2006.211.08:13:02.89/vblo/03,656.99,yes,locked 2006.211.08:13:02.89/vblo/04,712.99,yes,locked 2006.211.08:13:02.89/vblo/05,744.99,yes,locked 2006.211.08:13:02.89/vblo/06,752.99,yes,locked 2006.211.08:13:02.89/vblo/07,734.99,yes,locked 2006.211.08:13:02.89/vblo/08,744.99,yes,locked 2006.211.08:13:03.04/vabw/8 2006.211.08:13:03.19/vbbw/8 2006.211.08:13:03.28/xfe/off,on,12.0 2006.211.08:13:03.67/ifatt/23,28,28,28 2006.211.08:13:04.07/fmout-gps/S +4.47E-07 2006.211.08:13:04.11:!2006.211.08:14:00 2006.211.08:14:00.01:data_valid=off 2006.211.08:14:00.01:postob 2006.211.08:14:00.10/cable/+6.4394E-03 2006.211.08:14:00.10/wx/24.53,1010.1,80 2006.211.08:14:01.07/fmout-gps/S +4.45E-07 2006.211.08:14:01.07:scan_name=211-0814,k06211,60 2006.211.08:14:01.07:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.211.08:14:01.14#flagr#flagr/antenna,new-source 2006.211.08:14:02.14:checkk5 2006.211.08:14:02.49/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:14:02.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:14:03.18/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:14:03.52/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:14:03.86/chk_obsdata//k5ts1/T2110813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:14:04.19/chk_obsdata//k5ts2/T2110813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:14:04.53/chk_obsdata//k5ts3/T2110813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:14:04.86/chk_obsdata//k5ts4/T2110813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:14:05.52/k5log//k5ts1_log_newline 2006.211.08:14:06.18/k5log//k5ts2_log_newline 2006.211.08:14:06.84/k5log//k5ts3_log_newline 2006.211.08:14:07.49/k5log//k5ts4_log_newline 2006.211.08:14:07.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:14:07.52:4f8m12a=2 2006.211.08:14:07.52$4f8m12a/echo=on 2006.211.08:14:07.52$4f8m12a/pcalon 2006.211.08:14:07.52$pcalon/"no phase cal control is implemented here 2006.211.08:14:07.52$4f8m12a/"tpicd=stop 2006.211.08:14:07.52$4f8m12a/vc4f8 2006.211.08:14:07.52$vc4f8/valo=1,532.99 2006.211.08:14:07.52#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:14:07.52#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:14:07.52#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:07.52#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:07.52#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:07.52#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:07.52#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:14:07.52#ibcon#first serial, iclass 14, count 0 2006.211.08:14:07.52#ibcon#enter sib2, iclass 14, count 0 2006.211.08:14:07.52#ibcon#flushed, iclass 14, count 0 2006.211.08:14:07.52#ibcon#about to write, iclass 14, count 0 2006.211.08:14:07.52#ibcon#wrote, iclass 14, count 0 2006.211.08:14:07.52#ibcon#about to read 3, iclass 14, count 0 2006.211.08:14:07.54#ibcon#read 3, iclass 14, count 0 2006.211.08:14:07.54#ibcon#about to read 4, iclass 14, count 0 2006.211.08:14:07.54#ibcon#read 4, iclass 14, count 0 2006.211.08:14:07.54#ibcon#about to read 5, iclass 14, count 0 2006.211.08:14:07.54#ibcon#read 5, iclass 14, count 0 2006.211.08:14:07.54#ibcon#about to read 6, iclass 14, count 0 2006.211.08:14:07.54#ibcon#read 6, iclass 14, count 0 2006.211.08:14:07.54#ibcon#end of sib2, iclass 14, count 0 2006.211.08:14:07.54#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:14:07.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:14:07.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:14:07.54#ibcon#*before write, iclass 14, count 0 2006.211.08:14:07.54#ibcon#enter sib2, iclass 14, count 0 2006.211.08:14:07.54#ibcon#flushed, iclass 14, count 0 2006.211.08:14:07.54#ibcon#about to write, iclass 14, count 0 2006.211.08:14:07.54#ibcon#wrote, iclass 14, count 0 2006.211.08:14:07.54#ibcon#about to read 3, iclass 14, count 0 2006.211.08:14:07.59#ibcon#read 3, iclass 14, count 0 2006.211.08:14:07.59#ibcon#about to read 4, iclass 14, count 0 2006.211.08:14:07.59#ibcon#read 4, iclass 14, count 0 2006.211.08:14:07.59#ibcon#about to read 5, iclass 14, count 0 2006.211.08:14:07.59#ibcon#read 5, iclass 14, count 0 2006.211.08:14:07.59#ibcon#about to read 6, iclass 14, count 0 2006.211.08:14:07.59#ibcon#read 6, iclass 14, count 0 2006.211.08:14:07.59#ibcon#end of sib2, iclass 14, count 0 2006.211.08:14:07.59#ibcon#*after write, iclass 14, count 0 2006.211.08:14:07.59#ibcon#*before return 0, iclass 14, count 0 2006.211.08:14:07.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:07.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:07.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:14:07.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:14:07.59$vc4f8/va=1,8 2006.211.08:14:07.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:14:07.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:14:07.59#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:07.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:07.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:07.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:07.59#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:14:07.59#ibcon#first serial, iclass 16, count 2 2006.211.08:14:07.59#ibcon#enter sib2, iclass 16, count 2 2006.211.08:14:07.59#ibcon#flushed, iclass 16, count 2 2006.211.08:14:07.59#ibcon#about to write, iclass 16, count 2 2006.211.08:14:07.59#ibcon#wrote, iclass 16, count 2 2006.211.08:14:07.59#ibcon#about to read 3, iclass 16, count 2 2006.211.08:14:07.61#ibcon#read 3, iclass 16, count 2 2006.211.08:14:07.61#ibcon#about to read 4, iclass 16, count 2 2006.211.08:14:07.61#ibcon#read 4, iclass 16, count 2 2006.211.08:14:07.61#ibcon#about to read 5, iclass 16, count 2 2006.211.08:14:07.61#ibcon#read 5, iclass 16, count 2 2006.211.08:14:07.61#ibcon#about to read 6, iclass 16, count 2 2006.211.08:14:07.61#ibcon#read 6, iclass 16, count 2 2006.211.08:14:07.61#ibcon#end of sib2, iclass 16, count 2 2006.211.08:14:07.61#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:14:07.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:14:07.61#ibcon#[25=AT01-08\r\n] 2006.211.08:14:07.61#ibcon#*before write, iclass 16, count 2 2006.211.08:14:07.61#ibcon#enter sib2, iclass 16, count 2 2006.211.08:14:07.61#ibcon#flushed, iclass 16, count 2 2006.211.08:14:07.61#ibcon#about to write, iclass 16, count 2 2006.211.08:14:07.61#ibcon#wrote, iclass 16, count 2 2006.211.08:14:07.61#ibcon#about to read 3, iclass 16, count 2 2006.211.08:14:07.64#ibcon#read 3, iclass 16, count 2 2006.211.08:14:07.64#ibcon#about to read 4, iclass 16, count 2 2006.211.08:14:07.64#ibcon#read 4, iclass 16, count 2 2006.211.08:14:07.64#ibcon#about to read 5, iclass 16, count 2 2006.211.08:14:07.64#ibcon#read 5, iclass 16, count 2 2006.211.08:14:07.64#ibcon#about to read 6, iclass 16, count 2 2006.211.08:14:07.64#ibcon#read 6, iclass 16, count 2 2006.211.08:14:07.64#ibcon#end of sib2, iclass 16, count 2 2006.211.08:14:07.64#ibcon#*after write, iclass 16, count 2 2006.211.08:14:07.64#ibcon#*before return 0, iclass 16, count 2 2006.211.08:14:07.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:07.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:07.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:14:07.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:07.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:07.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:07.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:07.76#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:14:07.76#ibcon#first serial, iclass 16, count 0 2006.211.08:14:07.76#ibcon#enter sib2, iclass 16, count 0 2006.211.08:14:07.76#ibcon#flushed, iclass 16, count 0 2006.211.08:14:07.76#ibcon#about to write, iclass 16, count 0 2006.211.08:14:07.76#ibcon#wrote, iclass 16, count 0 2006.211.08:14:07.76#ibcon#about to read 3, iclass 16, count 0 2006.211.08:14:07.78#ibcon#read 3, iclass 16, count 0 2006.211.08:14:07.78#ibcon#about to read 4, iclass 16, count 0 2006.211.08:14:07.78#ibcon#read 4, iclass 16, count 0 2006.211.08:14:07.78#ibcon#about to read 5, iclass 16, count 0 2006.211.08:14:07.78#ibcon#read 5, iclass 16, count 0 2006.211.08:14:07.78#ibcon#about to read 6, iclass 16, count 0 2006.211.08:14:07.78#ibcon#read 6, iclass 16, count 0 2006.211.08:14:07.78#ibcon#end of sib2, iclass 16, count 0 2006.211.08:14:07.78#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:14:07.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:14:07.78#ibcon#[25=USB\r\n] 2006.211.08:14:07.78#ibcon#*before write, iclass 16, count 0 2006.211.08:14:07.78#ibcon#enter sib2, iclass 16, count 0 2006.211.08:14:07.78#ibcon#flushed, iclass 16, count 0 2006.211.08:14:07.78#ibcon#about to write, iclass 16, count 0 2006.211.08:14:07.78#ibcon#wrote, iclass 16, count 0 2006.211.08:14:07.78#ibcon#about to read 3, iclass 16, count 0 2006.211.08:14:07.81#ibcon#read 3, iclass 16, count 0 2006.211.08:14:07.81#ibcon#about to read 4, iclass 16, count 0 2006.211.08:14:07.81#ibcon#read 4, iclass 16, count 0 2006.211.08:14:07.81#ibcon#about to read 5, iclass 16, count 0 2006.211.08:14:07.81#ibcon#read 5, iclass 16, count 0 2006.211.08:14:07.81#ibcon#about to read 6, iclass 16, count 0 2006.211.08:14:07.81#ibcon#read 6, iclass 16, count 0 2006.211.08:14:07.81#ibcon#end of sib2, iclass 16, count 0 2006.211.08:14:07.81#ibcon#*after write, iclass 16, count 0 2006.211.08:14:07.81#ibcon#*before return 0, iclass 16, count 0 2006.211.08:14:07.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:07.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:07.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:14:07.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:14:07.81$vc4f8/valo=2,572.99 2006.211.08:14:07.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:14:07.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:14:07.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:07.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:07.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:07.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:07.81#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:14:07.81#ibcon#first serial, iclass 18, count 0 2006.211.08:14:07.81#ibcon#enter sib2, iclass 18, count 0 2006.211.08:14:07.81#ibcon#flushed, iclass 18, count 0 2006.211.08:14:07.81#ibcon#about to write, iclass 18, count 0 2006.211.08:14:07.81#ibcon#wrote, iclass 18, count 0 2006.211.08:14:07.81#ibcon#about to read 3, iclass 18, count 0 2006.211.08:14:07.83#ibcon#read 3, iclass 18, count 0 2006.211.08:14:07.83#ibcon#about to read 4, iclass 18, count 0 2006.211.08:14:07.83#ibcon#read 4, iclass 18, count 0 2006.211.08:14:07.83#ibcon#about to read 5, iclass 18, count 0 2006.211.08:14:07.83#ibcon#read 5, iclass 18, count 0 2006.211.08:14:07.83#ibcon#about to read 6, iclass 18, count 0 2006.211.08:14:07.83#ibcon#read 6, iclass 18, count 0 2006.211.08:14:07.83#ibcon#end of sib2, iclass 18, count 0 2006.211.08:14:07.83#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:14:07.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:14:07.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:14:07.83#ibcon#*before write, iclass 18, count 0 2006.211.08:14:07.83#ibcon#enter sib2, iclass 18, count 0 2006.211.08:14:07.83#ibcon#flushed, iclass 18, count 0 2006.211.08:14:07.83#ibcon#about to write, iclass 18, count 0 2006.211.08:14:07.83#ibcon#wrote, iclass 18, count 0 2006.211.08:14:07.83#ibcon#about to read 3, iclass 18, count 0 2006.211.08:14:07.87#ibcon#read 3, iclass 18, count 0 2006.211.08:14:07.87#ibcon#about to read 4, iclass 18, count 0 2006.211.08:14:07.87#ibcon#read 4, iclass 18, count 0 2006.211.08:14:07.87#ibcon#about to read 5, iclass 18, count 0 2006.211.08:14:07.87#ibcon#read 5, iclass 18, count 0 2006.211.08:14:07.87#ibcon#about to read 6, iclass 18, count 0 2006.211.08:14:07.87#ibcon#read 6, iclass 18, count 0 2006.211.08:14:07.87#ibcon#end of sib2, iclass 18, count 0 2006.211.08:14:07.87#ibcon#*after write, iclass 18, count 0 2006.211.08:14:07.87#ibcon#*before return 0, iclass 18, count 0 2006.211.08:14:07.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:07.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:07.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:14:07.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:14:07.87$vc4f8/va=2,7 2006.211.08:14:07.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:14:07.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:14:07.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:07.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:07.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:07.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:07.93#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:14:07.93#ibcon#first serial, iclass 20, count 2 2006.211.08:14:07.93#ibcon#enter sib2, iclass 20, count 2 2006.211.08:14:07.93#ibcon#flushed, iclass 20, count 2 2006.211.08:14:07.93#ibcon#about to write, iclass 20, count 2 2006.211.08:14:07.93#ibcon#wrote, iclass 20, count 2 2006.211.08:14:07.93#ibcon#about to read 3, iclass 20, count 2 2006.211.08:14:07.95#ibcon#read 3, iclass 20, count 2 2006.211.08:14:07.95#ibcon#about to read 4, iclass 20, count 2 2006.211.08:14:07.95#ibcon#read 4, iclass 20, count 2 2006.211.08:14:07.95#ibcon#about to read 5, iclass 20, count 2 2006.211.08:14:07.95#ibcon#read 5, iclass 20, count 2 2006.211.08:14:07.95#ibcon#about to read 6, iclass 20, count 2 2006.211.08:14:07.95#ibcon#read 6, iclass 20, count 2 2006.211.08:14:07.95#ibcon#end of sib2, iclass 20, count 2 2006.211.08:14:07.95#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:14:07.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:14:07.95#ibcon#[25=AT02-07\r\n] 2006.211.08:14:07.95#ibcon#*before write, iclass 20, count 2 2006.211.08:14:07.95#ibcon#enter sib2, iclass 20, count 2 2006.211.08:14:07.95#ibcon#flushed, iclass 20, count 2 2006.211.08:14:07.95#ibcon#about to write, iclass 20, count 2 2006.211.08:14:07.95#ibcon#wrote, iclass 20, count 2 2006.211.08:14:07.95#ibcon#about to read 3, iclass 20, count 2 2006.211.08:14:07.98#ibcon#read 3, iclass 20, count 2 2006.211.08:14:07.98#ibcon#about to read 4, iclass 20, count 2 2006.211.08:14:07.98#ibcon#read 4, iclass 20, count 2 2006.211.08:14:07.98#ibcon#about to read 5, iclass 20, count 2 2006.211.08:14:07.98#ibcon#read 5, iclass 20, count 2 2006.211.08:14:07.98#ibcon#about to read 6, iclass 20, count 2 2006.211.08:14:07.98#ibcon#read 6, iclass 20, count 2 2006.211.08:14:07.98#ibcon#end of sib2, iclass 20, count 2 2006.211.08:14:07.98#ibcon#*after write, iclass 20, count 2 2006.211.08:14:07.98#ibcon#*before return 0, iclass 20, count 2 2006.211.08:14:07.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:07.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:07.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:14:07.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:07.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:08.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:08.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:08.10#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:14:08.10#ibcon#first serial, iclass 20, count 0 2006.211.08:14:08.10#ibcon#enter sib2, iclass 20, count 0 2006.211.08:14:08.10#ibcon#flushed, iclass 20, count 0 2006.211.08:14:08.10#ibcon#about to write, iclass 20, count 0 2006.211.08:14:08.10#ibcon#wrote, iclass 20, count 0 2006.211.08:14:08.10#ibcon#about to read 3, iclass 20, count 0 2006.211.08:14:08.12#ibcon#read 3, iclass 20, count 0 2006.211.08:14:08.12#ibcon#about to read 4, iclass 20, count 0 2006.211.08:14:08.12#ibcon#read 4, iclass 20, count 0 2006.211.08:14:08.12#ibcon#about to read 5, iclass 20, count 0 2006.211.08:14:08.12#ibcon#read 5, iclass 20, count 0 2006.211.08:14:08.12#ibcon#about to read 6, iclass 20, count 0 2006.211.08:14:08.12#ibcon#read 6, iclass 20, count 0 2006.211.08:14:08.12#ibcon#end of sib2, iclass 20, count 0 2006.211.08:14:08.12#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:14:08.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:14:08.12#ibcon#[25=USB\r\n] 2006.211.08:14:08.12#ibcon#*before write, iclass 20, count 0 2006.211.08:14:08.12#ibcon#enter sib2, iclass 20, count 0 2006.211.08:14:08.12#ibcon#flushed, iclass 20, count 0 2006.211.08:14:08.12#ibcon#about to write, iclass 20, count 0 2006.211.08:14:08.12#ibcon#wrote, iclass 20, count 0 2006.211.08:14:08.12#ibcon#about to read 3, iclass 20, count 0 2006.211.08:14:08.15#ibcon#read 3, iclass 20, count 0 2006.211.08:14:08.15#ibcon#about to read 4, iclass 20, count 0 2006.211.08:14:08.15#ibcon#read 4, iclass 20, count 0 2006.211.08:14:08.15#ibcon#about to read 5, iclass 20, count 0 2006.211.08:14:08.15#ibcon#read 5, iclass 20, count 0 2006.211.08:14:08.15#ibcon#about to read 6, iclass 20, count 0 2006.211.08:14:08.15#ibcon#read 6, iclass 20, count 0 2006.211.08:14:08.15#ibcon#end of sib2, iclass 20, count 0 2006.211.08:14:08.15#ibcon#*after write, iclass 20, count 0 2006.211.08:14:08.15#ibcon#*before return 0, iclass 20, count 0 2006.211.08:14:08.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:08.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:08.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:14:08.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:14:08.15$vc4f8/valo=3,672.99 2006.211.08:14:08.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:14:08.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:14:08.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:08.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:08.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:08.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:08.15#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:14:08.15#ibcon#first serial, iclass 22, count 0 2006.211.08:14:08.15#ibcon#enter sib2, iclass 22, count 0 2006.211.08:14:08.15#ibcon#flushed, iclass 22, count 0 2006.211.08:14:08.15#ibcon#about to write, iclass 22, count 0 2006.211.08:14:08.15#ibcon#wrote, iclass 22, count 0 2006.211.08:14:08.15#ibcon#about to read 3, iclass 22, count 0 2006.211.08:14:08.17#ibcon#read 3, iclass 22, count 0 2006.211.08:14:08.17#ibcon#about to read 4, iclass 22, count 0 2006.211.08:14:08.17#ibcon#read 4, iclass 22, count 0 2006.211.08:14:08.17#ibcon#about to read 5, iclass 22, count 0 2006.211.08:14:08.17#ibcon#read 5, iclass 22, count 0 2006.211.08:14:08.17#ibcon#about to read 6, iclass 22, count 0 2006.211.08:14:08.17#ibcon#read 6, iclass 22, count 0 2006.211.08:14:08.17#ibcon#end of sib2, iclass 22, count 0 2006.211.08:14:08.17#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:14:08.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:14:08.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:14:08.17#ibcon#*before write, iclass 22, count 0 2006.211.08:14:08.17#ibcon#enter sib2, iclass 22, count 0 2006.211.08:14:08.17#ibcon#flushed, iclass 22, count 0 2006.211.08:14:08.17#ibcon#about to write, iclass 22, count 0 2006.211.08:14:08.17#ibcon#wrote, iclass 22, count 0 2006.211.08:14:08.17#ibcon#about to read 3, iclass 22, count 0 2006.211.08:14:08.21#ibcon#read 3, iclass 22, count 0 2006.211.08:14:08.21#ibcon#about to read 4, iclass 22, count 0 2006.211.08:14:08.21#ibcon#read 4, iclass 22, count 0 2006.211.08:14:08.21#ibcon#about to read 5, iclass 22, count 0 2006.211.08:14:08.21#ibcon#read 5, iclass 22, count 0 2006.211.08:14:08.21#ibcon#about to read 6, iclass 22, count 0 2006.211.08:14:08.21#ibcon#read 6, iclass 22, count 0 2006.211.08:14:08.21#ibcon#end of sib2, iclass 22, count 0 2006.211.08:14:08.21#ibcon#*after write, iclass 22, count 0 2006.211.08:14:08.21#ibcon#*before return 0, iclass 22, count 0 2006.211.08:14:08.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:08.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:08.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:14:08.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:14:08.21$vc4f8/va=3,6 2006.211.08:14:08.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:14:08.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:14:08.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:08.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:08.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:08.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:08.27#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:14:08.27#ibcon#first serial, iclass 24, count 2 2006.211.08:14:08.27#ibcon#enter sib2, iclass 24, count 2 2006.211.08:14:08.27#ibcon#flushed, iclass 24, count 2 2006.211.08:14:08.27#ibcon#about to write, iclass 24, count 2 2006.211.08:14:08.27#ibcon#wrote, iclass 24, count 2 2006.211.08:14:08.27#ibcon#about to read 3, iclass 24, count 2 2006.211.08:14:08.29#ibcon#read 3, iclass 24, count 2 2006.211.08:14:08.29#ibcon#about to read 4, iclass 24, count 2 2006.211.08:14:08.29#ibcon#read 4, iclass 24, count 2 2006.211.08:14:08.29#ibcon#about to read 5, iclass 24, count 2 2006.211.08:14:08.29#ibcon#read 5, iclass 24, count 2 2006.211.08:14:08.29#ibcon#about to read 6, iclass 24, count 2 2006.211.08:14:08.29#ibcon#read 6, iclass 24, count 2 2006.211.08:14:08.29#ibcon#end of sib2, iclass 24, count 2 2006.211.08:14:08.29#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:14:08.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:14:08.29#ibcon#[25=AT03-06\r\n] 2006.211.08:14:08.29#ibcon#*before write, iclass 24, count 2 2006.211.08:14:08.29#ibcon#enter sib2, iclass 24, count 2 2006.211.08:14:08.29#ibcon#flushed, iclass 24, count 2 2006.211.08:14:08.29#ibcon#about to write, iclass 24, count 2 2006.211.08:14:08.29#ibcon#wrote, iclass 24, count 2 2006.211.08:14:08.29#ibcon#about to read 3, iclass 24, count 2 2006.211.08:14:08.32#ibcon#read 3, iclass 24, count 2 2006.211.08:14:08.32#ibcon#about to read 4, iclass 24, count 2 2006.211.08:14:08.32#ibcon#read 4, iclass 24, count 2 2006.211.08:14:08.32#ibcon#about to read 5, iclass 24, count 2 2006.211.08:14:08.32#ibcon#read 5, iclass 24, count 2 2006.211.08:14:08.32#ibcon#about to read 6, iclass 24, count 2 2006.211.08:14:08.32#ibcon#read 6, iclass 24, count 2 2006.211.08:14:08.32#ibcon#end of sib2, iclass 24, count 2 2006.211.08:14:08.32#ibcon#*after write, iclass 24, count 2 2006.211.08:14:08.32#ibcon#*before return 0, iclass 24, count 2 2006.211.08:14:08.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:08.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:08.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:14:08.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:08.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:08.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:08.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:08.44#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:14:08.44#ibcon#first serial, iclass 24, count 0 2006.211.08:14:08.44#ibcon#enter sib2, iclass 24, count 0 2006.211.08:14:08.44#ibcon#flushed, iclass 24, count 0 2006.211.08:14:08.44#ibcon#about to write, iclass 24, count 0 2006.211.08:14:08.44#ibcon#wrote, iclass 24, count 0 2006.211.08:14:08.44#ibcon#about to read 3, iclass 24, count 0 2006.211.08:14:08.46#ibcon#read 3, iclass 24, count 0 2006.211.08:14:08.46#ibcon#about to read 4, iclass 24, count 0 2006.211.08:14:08.46#ibcon#read 4, iclass 24, count 0 2006.211.08:14:08.46#ibcon#about to read 5, iclass 24, count 0 2006.211.08:14:08.46#ibcon#read 5, iclass 24, count 0 2006.211.08:14:08.46#ibcon#about to read 6, iclass 24, count 0 2006.211.08:14:08.46#ibcon#read 6, iclass 24, count 0 2006.211.08:14:08.46#ibcon#end of sib2, iclass 24, count 0 2006.211.08:14:08.46#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:14:08.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:14:08.46#ibcon#[25=USB\r\n] 2006.211.08:14:08.46#ibcon#*before write, iclass 24, count 0 2006.211.08:14:08.46#ibcon#enter sib2, iclass 24, count 0 2006.211.08:14:08.46#ibcon#flushed, iclass 24, count 0 2006.211.08:14:08.46#ibcon#about to write, iclass 24, count 0 2006.211.08:14:08.46#ibcon#wrote, iclass 24, count 0 2006.211.08:14:08.46#ibcon#about to read 3, iclass 24, count 0 2006.211.08:14:08.49#ibcon#read 3, iclass 24, count 0 2006.211.08:14:08.49#ibcon#about to read 4, iclass 24, count 0 2006.211.08:14:08.49#ibcon#read 4, iclass 24, count 0 2006.211.08:14:08.49#ibcon#about to read 5, iclass 24, count 0 2006.211.08:14:08.49#ibcon#read 5, iclass 24, count 0 2006.211.08:14:08.49#ibcon#about to read 6, iclass 24, count 0 2006.211.08:14:08.49#ibcon#read 6, iclass 24, count 0 2006.211.08:14:08.49#ibcon#end of sib2, iclass 24, count 0 2006.211.08:14:08.49#ibcon#*after write, iclass 24, count 0 2006.211.08:14:08.49#ibcon#*before return 0, iclass 24, count 0 2006.211.08:14:08.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:08.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:08.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:14:08.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:14:08.49$vc4f8/valo=4,832.99 2006.211.08:14:08.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:14:08.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:14:08.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:08.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:08.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:08.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:08.49#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:14:08.49#ibcon#first serial, iclass 26, count 0 2006.211.08:14:08.49#ibcon#enter sib2, iclass 26, count 0 2006.211.08:14:08.49#ibcon#flushed, iclass 26, count 0 2006.211.08:14:08.49#ibcon#about to write, iclass 26, count 0 2006.211.08:14:08.49#ibcon#wrote, iclass 26, count 0 2006.211.08:14:08.49#ibcon#about to read 3, iclass 26, count 0 2006.211.08:14:08.51#ibcon#read 3, iclass 26, count 0 2006.211.08:14:08.51#ibcon#about to read 4, iclass 26, count 0 2006.211.08:14:08.51#ibcon#read 4, iclass 26, count 0 2006.211.08:14:08.51#ibcon#about to read 5, iclass 26, count 0 2006.211.08:14:08.51#ibcon#read 5, iclass 26, count 0 2006.211.08:14:08.51#ibcon#about to read 6, iclass 26, count 0 2006.211.08:14:08.51#ibcon#read 6, iclass 26, count 0 2006.211.08:14:08.51#ibcon#end of sib2, iclass 26, count 0 2006.211.08:14:08.51#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:14:08.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:14:08.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:14:08.51#ibcon#*before write, iclass 26, count 0 2006.211.08:14:08.51#ibcon#enter sib2, iclass 26, count 0 2006.211.08:14:08.51#ibcon#flushed, iclass 26, count 0 2006.211.08:14:08.51#ibcon#about to write, iclass 26, count 0 2006.211.08:14:08.51#ibcon#wrote, iclass 26, count 0 2006.211.08:14:08.51#ibcon#about to read 3, iclass 26, count 0 2006.211.08:14:08.55#ibcon#read 3, iclass 26, count 0 2006.211.08:14:08.55#ibcon#about to read 4, iclass 26, count 0 2006.211.08:14:08.55#ibcon#read 4, iclass 26, count 0 2006.211.08:14:08.55#ibcon#about to read 5, iclass 26, count 0 2006.211.08:14:08.55#ibcon#read 5, iclass 26, count 0 2006.211.08:14:08.55#ibcon#about to read 6, iclass 26, count 0 2006.211.08:14:08.55#ibcon#read 6, iclass 26, count 0 2006.211.08:14:08.55#ibcon#end of sib2, iclass 26, count 0 2006.211.08:14:08.55#ibcon#*after write, iclass 26, count 0 2006.211.08:14:08.55#ibcon#*before return 0, iclass 26, count 0 2006.211.08:14:08.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:08.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:08.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:14:08.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:14:08.55$vc4f8/va=4,7 2006.211.08:14:08.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:14:08.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:14:08.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:08.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:08.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:08.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:08.61#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:14:08.61#ibcon#first serial, iclass 28, count 2 2006.211.08:14:08.61#ibcon#enter sib2, iclass 28, count 2 2006.211.08:14:08.61#ibcon#flushed, iclass 28, count 2 2006.211.08:14:08.61#ibcon#about to write, iclass 28, count 2 2006.211.08:14:08.61#ibcon#wrote, iclass 28, count 2 2006.211.08:14:08.61#ibcon#about to read 3, iclass 28, count 2 2006.211.08:14:08.63#ibcon#read 3, iclass 28, count 2 2006.211.08:14:08.63#ibcon#about to read 4, iclass 28, count 2 2006.211.08:14:08.63#ibcon#read 4, iclass 28, count 2 2006.211.08:14:08.63#ibcon#about to read 5, iclass 28, count 2 2006.211.08:14:08.63#ibcon#read 5, iclass 28, count 2 2006.211.08:14:08.63#ibcon#about to read 6, iclass 28, count 2 2006.211.08:14:08.63#ibcon#read 6, iclass 28, count 2 2006.211.08:14:08.63#ibcon#end of sib2, iclass 28, count 2 2006.211.08:14:08.63#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:14:08.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:14:08.63#ibcon#[25=AT04-07\r\n] 2006.211.08:14:08.63#ibcon#*before write, iclass 28, count 2 2006.211.08:14:08.63#ibcon#enter sib2, iclass 28, count 2 2006.211.08:14:08.63#ibcon#flushed, iclass 28, count 2 2006.211.08:14:08.63#ibcon#about to write, iclass 28, count 2 2006.211.08:14:08.63#ibcon#wrote, iclass 28, count 2 2006.211.08:14:08.63#ibcon#about to read 3, iclass 28, count 2 2006.211.08:14:08.66#ibcon#read 3, iclass 28, count 2 2006.211.08:14:08.66#ibcon#about to read 4, iclass 28, count 2 2006.211.08:14:08.66#ibcon#read 4, iclass 28, count 2 2006.211.08:14:08.66#ibcon#about to read 5, iclass 28, count 2 2006.211.08:14:08.66#ibcon#read 5, iclass 28, count 2 2006.211.08:14:08.66#ibcon#about to read 6, iclass 28, count 2 2006.211.08:14:08.66#ibcon#read 6, iclass 28, count 2 2006.211.08:14:08.66#ibcon#end of sib2, iclass 28, count 2 2006.211.08:14:08.66#ibcon#*after write, iclass 28, count 2 2006.211.08:14:08.66#ibcon#*before return 0, iclass 28, count 2 2006.211.08:14:08.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:08.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:08.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:14:08.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:08.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:08.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:08.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:08.78#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:14:08.78#ibcon#first serial, iclass 28, count 0 2006.211.08:14:08.78#ibcon#enter sib2, iclass 28, count 0 2006.211.08:14:08.78#ibcon#flushed, iclass 28, count 0 2006.211.08:14:08.78#ibcon#about to write, iclass 28, count 0 2006.211.08:14:08.78#ibcon#wrote, iclass 28, count 0 2006.211.08:14:08.78#ibcon#about to read 3, iclass 28, count 0 2006.211.08:14:08.80#ibcon#read 3, iclass 28, count 0 2006.211.08:14:08.80#ibcon#about to read 4, iclass 28, count 0 2006.211.08:14:08.80#ibcon#read 4, iclass 28, count 0 2006.211.08:14:08.80#ibcon#about to read 5, iclass 28, count 0 2006.211.08:14:08.80#ibcon#read 5, iclass 28, count 0 2006.211.08:14:08.80#ibcon#about to read 6, iclass 28, count 0 2006.211.08:14:08.80#ibcon#read 6, iclass 28, count 0 2006.211.08:14:08.80#ibcon#end of sib2, iclass 28, count 0 2006.211.08:14:08.80#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:14:08.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:14:08.80#ibcon#[25=USB\r\n] 2006.211.08:14:08.80#ibcon#*before write, iclass 28, count 0 2006.211.08:14:08.80#ibcon#enter sib2, iclass 28, count 0 2006.211.08:14:08.80#ibcon#flushed, iclass 28, count 0 2006.211.08:14:08.80#ibcon#about to write, iclass 28, count 0 2006.211.08:14:08.80#ibcon#wrote, iclass 28, count 0 2006.211.08:14:08.80#ibcon#about to read 3, iclass 28, count 0 2006.211.08:14:08.83#ibcon#read 3, iclass 28, count 0 2006.211.08:14:08.83#ibcon#about to read 4, iclass 28, count 0 2006.211.08:14:08.83#ibcon#read 4, iclass 28, count 0 2006.211.08:14:08.83#ibcon#about to read 5, iclass 28, count 0 2006.211.08:14:08.83#ibcon#read 5, iclass 28, count 0 2006.211.08:14:08.83#ibcon#about to read 6, iclass 28, count 0 2006.211.08:14:08.83#ibcon#read 6, iclass 28, count 0 2006.211.08:14:08.83#ibcon#end of sib2, iclass 28, count 0 2006.211.08:14:08.83#ibcon#*after write, iclass 28, count 0 2006.211.08:14:08.83#ibcon#*before return 0, iclass 28, count 0 2006.211.08:14:08.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:08.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:08.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:14:08.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:14:08.83$vc4f8/valo=5,652.99 2006.211.08:14:08.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:14:08.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:14:08.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:08.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:08.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:08.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:08.83#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:14:08.83#ibcon#first serial, iclass 30, count 0 2006.211.08:14:08.83#ibcon#enter sib2, iclass 30, count 0 2006.211.08:14:08.83#ibcon#flushed, iclass 30, count 0 2006.211.08:14:08.83#ibcon#about to write, iclass 30, count 0 2006.211.08:14:08.83#ibcon#wrote, iclass 30, count 0 2006.211.08:14:08.83#ibcon#about to read 3, iclass 30, count 0 2006.211.08:14:08.85#ibcon#read 3, iclass 30, count 0 2006.211.08:14:08.85#ibcon#about to read 4, iclass 30, count 0 2006.211.08:14:08.85#ibcon#read 4, iclass 30, count 0 2006.211.08:14:08.85#ibcon#about to read 5, iclass 30, count 0 2006.211.08:14:08.85#ibcon#read 5, iclass 30, count 0 2006.211.08:14:08.85#ibcon#about to read 6, iclass 30, count 0 2006.211.08:14:08.85#ibcon#read 6, iclass 30, count 0 2006.211.08:14:08.85#ibcon#end of sib2, iclass 30, count 0 2006.211.08:14:08.85#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:14:08.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:14:08.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:14:08.85#ibcon#*before write, iclass 30, count 0 2006.211.08:14:08.85#ibcon#enter sib2, iclass 30, count 0 2006.211.08:14:08.85#ibcon#flushed, iclass 30, count 0 2006.211.08:14:08.85#ibcon#about to write, iclass 30, count 0 2006.211.08:14:08.85#ibcon#wrote, iclass 30, count 0 2006.211.08:14:08.85#ibcon#about to read 3, iclass 30, count 0 2006.211.08:14:08.89#ibcon#read 3, iclass 30, count 0 2006.211.08:14:08.89#ibcon#about to read 4, iclass 30, count 0 2006.211.08:14:08.89#ibcon#read 4, iclass 30, count 0 2006.211.08:14:08.89#ibcon#about to read 5, iclass 30, count 0 2006.211.08:14:08.89#ibcon#read 5, iclass 30, count 0 2006.211.08:14:08.89#ibcon#about to read 6, iclass 30, count 0 2006.211.08:14:08.89#ibcon#read 6, iclass 30, count 0 2006.211.08:14:08.89#ibcon#end of sib2, iclass 30, count 0 2006.211.08:14:08.89#ibcon#*after write, iclass 30, count 0 2006.211.08:14:08.89#ibcon#*before return 0, iclass 30, count 0 2006.211.08:14:08.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:08.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:08.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:14:08.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:14:08.89$vc4f8/va=5,7 2006.211.08:14:08.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:14:08.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:14:08.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:08.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:08.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:08.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:08.95#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:14:08.95#ibcon#first serial, iclass 32, count 2 2006.211.08:14:08.95#ibcon#enter sib2, iclass 32, count 2 2006.211.08:14:08.95#ibcon#flushed, iclass 32, count 2 2006.211.08:14:08.95#ibcon#about to write, iclass 32, count 2 2006.211.08:14:08.95#ibcon#wrote, iclass 32, count 2 2006.211.08:14:08.95#ibcon#about to read 3, iclass 32, count 2 2006.211.08:14:08.97#ibcon#read 3, iclass 32, count 2 2006.211.08:14:08.97#ibcon#about to read 4, iclass 32, count 2 2006.211.08:14:08.97#ibcon#read 4, iclass 32, count 2 2006.211.08:14:08.97#ibcon#about to read 5, iclass 32, count 2 2006.211.08:14:08.97#ibcon#read 5, iclass 32, count 2 2006.211.08:14:08.97#ibcon#about to read 6, iclass 32, count 2 2006.211.08:14:08.97#ibcon#read 6, iclass 32, count 2 2006.211.08:14:08.97#ibcon#end of sib2, iclass 32, count 2 2006.211.08:14:08.97#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:14:08.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:14:08.97#ibcon#[25=AT05-07\r\n] 2006.211.08:14:08.97#ibcon#*before write, iclass 32, count 2 2006.211.08:14:08.97#ibcon#enter sib2, iclass 32, count 2 2006.211.08:14:08.97#ibcon#flushed, iclass 32, count 2 2006.211.08:14:08.97#ibcon#about to write, iclass 32, count 2 2006.211.08:14:08.97#ibcon#wrote, iclass 32, count 2 2006.211.08:14:08.97#ibcon#about to read 3, iclass 32, count 2 2006.211.08:14:09.00#ibcon#read 3, iclass 32, count 2 2006.211.08:14:09.00#ibcon#about to read 4, iclass 32, count 2 2006.211.08:14:09.00#ibcon#read 4, iclass 32, count 2 2006.211.08:14:09.00#ibcon#about to read 5, iclass 32, count 2 2006.211.08:14:09.00#ibcon#read 5, iclass 32, count 2 2006.211.08:14:09.00#ibcon#about to read 6, iclass 32, count 2 2006.211.08:14:09.00#ibcon#read 6, iclass 32, count 2 2006.211.08:14:09.00#ibcon#end of sib2, iclass 32, count 2 2006.211.08:14:09.00#ibcon#*after write, iclass 32, count 2 2006.211.08:14:09.00#ibcon#*before return 0, iclass 32, count 2 2006.211.08:14:09.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:09.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:09.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:14:09.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:09.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:09.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:09.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:09.12#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:14:09.12#ibcon#first serial, iclass 32, count 0 2006.211.08:14:09.12#ibcon#enter sib2, iclass 32, count 0 2006.211.08:14:09.12#ibcon#flushed, iclass 32, count 0 2006.211.08:14:09.12#ibcon#about to write, iclass 32, count 0 2006.211.08:14:09.12#ibcon#wrote, iclass 32, count 0 2006.211.08:14:09.12#ibcon#about to read 3, iclass 32, count 0 2006.211.08:14:09.14#ibcon#read 3, iclass 32, count 0 2006.211.08:14:09.14#ibcon#about to read 4, iclass 32, count 0 2006.211.08:14:09.14#ibcon#read 4, iclass 32, count 0 2006.211.08:14:09.14#ibcon#about to read 5, iclass 32, count 0 2006.211.08:14:09.14#ibcon#read 5, iclass 32, count 0 2006.211.08:14:09.14#ibcon#about to read 6, iclass 32, count 0 2006.211.08:14:09.14#ibcon#read 6, iclass 32, count 0 2006.211.08:14:09.14#ibcon#end of sib2, iclass 32, count 0 2006.211.08:14:09.14#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:14:09.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:14:09.14#ibcon#[25=USB\r\n] 2006.211.08:14:09.14#ibcon#*before write, iclass 32, count 0 2006.211.08:14:09.14#ibcon#enter sib2, iclass 32, count 0 2006.211.08:14:09.14#ibcon#flushed, iclass 32, count 0 2006.211.08:14:09.14#ibcon#about to write, iclass 32, count 0 2006.211.08:14:09.14#ibcon#wrote, iclass 32, count 0 2006.211.08:14:09.14#ibcon#about to read 3, iclass 32, count 0 2006.211.08:14:09.17#ibcon#read 3, iclass 32, count 0 2006.211.08:14:09.17#ibcon#about to read 4, iclass 32, count 0 2006.211.08:14:09.17#ibcon#read 4, iclass 32, count 0 2006.211.08:14:09.17#ibcon#about to read 5, iclass 32, count 0 2006.211.08:14:09.17#ibcon#read 5, iclass 32, count 0 2006.211.08:14:09.17#ibcon#about to read 6, iclass 32, count 0 2006.211.08:14:09.17#ibcon#read 6, iclass 32, count 0 2006.211.08:14:09.17#ibcon#end of sib2, iclass 32, count 0 2006.211.08:14:09.17#ibcon#*after write, iclass 32, count 0 2006.211.08:14:09.17#ibcon#*before return 0, iclass 32, count 0 2006.211.08:14:09.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:09.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:09.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:14:09.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:14:09.17$vc4f8/valo=6,772.99 2006.211.08:14:09.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:14:09.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:14:09.17#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:09.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:09.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:09.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:09.17#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:14:09.17#ibcon#first serial, iclass 34, count 0 2006.211.08:14:09.17#ibcon#enter sib2, iclass 34, count 0 2006.211.08:14:09.17#ibcon#flushed, iclass 34, count 0 2006.211.08:14:09.17#ibcon#about to write, iclass 34, count 0 2006.211.08:14:09.17#ibcon#wrote, iclass 34, count 0 2006.211.08:14:09.17#ibcon#about to read 3, iclass 34, count 0 2006.211.08:14:09.19#ibcon#read 3, iclass 34, count 0 2006.211.08:14:09.19#ibcon#about to read 4, iclass 34, count 0 2006.211.08:14:09.19#ibcon#read 4, iclass 34, count 0 2006.211.08:14:09.19#ibcon#about to read 5, iclass 34, count 0 2006.211.08:14:09.19#ibcon#read 5, iclass 34, count 0 2006.211.08:14:09.19#ibcon#about to read 6, iclass 34, count 0 2006.211.08:14:09.19#ibcon#read 6, iclass 34, count 0 2006.211.08:14:09.19#ibcon#end of sib2, iclass 34, count 0 2006.211.08:14:09.19#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:14:09.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:14:09.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:14:09.19#ibcon#*before write, iclass 34, count 0 2006.211.08:14:09.19#ibcon#enter sib2, iclass 34, count 0 2006.211.08:14:09.19#ibcon#flushed, iclass 34, count 0 2006.211.08:14:09.19#ibcon#about to write, iclass 34, count 0 2006.211.08:14:09.19#ibcon#wrote, iclass 34, count 0 2006.211.08:14:09.19#ibcon#about to read 3, iclass 34, count 0 2006.211.08:14:09.23#ibcon#read 3, iclass 34, count 0 2006.211.08:14:09.23#ibcon#about to read 4, iclass 34, count 0 2006.211.08:14:09.23#ibcon#read 4, iclass 34, count 0 2006.211.08:14:09.23#ibcon#about to read 5, iclass 34, count 0 2006.211.08:14:09.23#ibcon#read 5, iclass 34, count 0 2006.211.08:14:09.23#ibcon#about to read 6, iclass 34, count 0 2006.211.08:14:09.23#ibcon#read 6, iclass 34, count 0 2006.211.08:14:09.23#ibcon#end of sib2, iclass 34, count 0 2006.211.08:14:09.23#ibcon#*after write, iclass 34, count 0 2006.211.08:14:09.23#ibcon#*before return 0, iclass 34, count 0 2006.211.08:14:09.23#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:09.23#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:09.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:14:09.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:14:09.23$vc4f8/va=6,6 2006.211.08:14:09.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:14:09.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:14:09.23#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:09.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:14:09.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:14:09.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:14:09.29#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:14:09.29#ibcon#first serial, iclass 36, count 2 2006.211.08:14:09.29#ibcon#enter sib2, iclass 36, count 2 2006.211.08:14:09.29#ibcon#flushed, iclass 36, count 2 2006.211.08:14:09.29#ibcon#about to write, iclass 36, count 2 2006.211.08:14:09.29#ibcon#wrote, iclass 36, count 2 2006.211.08:14:09.29#ibcon#about to read 3, iclass 36, count 2 2006.211.08:14:09.31#ibcon#read 3, iclass 36, count 2 2006.211.08:14:09.31#ibcon#about to read 4, iclass 36, count 2 2006.211.08:14:09.31#ibcon#read 4, iclass 36, count 2 2006.211.08:14:09.31#ibcon#about to read 5, iclass 36, count 2 2006.211.08:14:09.31#ibcon#read 5, iclass 36, count 2 2006.211.08:14:09.31#ibcon#about to read 6, iclass 36, count 2 2006.211.08:14:09.31#ibcon#read 6, iclass 36, count 2 2006.211.08:14:09.31#ibcon#end of sib2, iclass 36, count 2 2006.211.08:14:09.31#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:14:09.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:14:09.31#ibcon#[25=AT06-06\r\n] 2006.211.08:14:09.31#ibcon#*before write, iclass 36, count 2 2006.211.08:14:09.31#ibcon#enter sib2, iclass 36, count 2 2006.211.08:14:09.31#ibcon#flushed, iclass 36, count 2 2006.211.08:14:09.31#ibcon#about to write, iclass 36, count 2 2006.211.08:14:09.31#ibcon#wrote, iclass 36, count 2 2006.211.08:14:09.31#ibcon#about to read 3, iclass 36, count 2 2006.211.08:14:09.34#ibcon#read 3, iclass 36, count 2 2006.211.08:14:09.34#ibcon#about to read 4, iclass 36, count 2 2006.211.08:14:09.34#ibcon#read 4, iclass 36, count 2 2006.211.08:14:09.34#ibcon#about to read 5, iclass 36, count 2 2006.211.08:14:09.34#ibcon#read 5, iclass 36, count 2 2006.211.08:14:09.34#ibcon#about to read 6, iclass 36, count 2 2006.211.08:14:09.34#ibcon#read 6, iclass 36, count 2 2006.211.08:14:09.34#ibcon#end of sib2, iclass 36, count 2 2006.211.08:14:09.34#ibcon#*after write, iclass 36, count 2 2006.211.08:14:09.34#ibcon#*before return 0, iclass 36, count 2 2006.211.08:14:09.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:14:09.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:14:09.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:14:09.34#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:09.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:14:09.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:14:09.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:14:09.46#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:14:09.46#ibcon#first serial, iclass 36, count 0 2006.211.08:14:09.46#ibcon#enter sib2, iclass 36, count 0 2006.211.08:14:09.46#ibcon#flushed, iclass 36, count 0 2006.211.08:14:09.46#ibcon#about to write, iclass 36, count 0 2006.211.08:14:09.46#ibcon#wrote, iclass 36, count 0 2006.211.08:14:09.46#ibcon#about to read 3, iclass 36, count 0 2006.211.08:14:09.48#ibcon#read 3, iclass 36, count 0 2006.211.08:14:09.48#ibcon#about to read 4, iclass 36, count 0 2006.211.08:14:09.48#ibcon#read 4, iclass 36, count 0 2006.211.08:14:09.48#ibcon#about to read 5, iclass 36, count 0 2006.211.08:14:09.48#ibcon#read 5, iclass 36, count 0 2006.211.08:14:09.48#ibcon#about to read 6, iclass 36, count 0 2006.211.08:14:09.48#ibcon#read 6, iclass 36, count 0 2006.211.08:14:09.48#ibcon#end of sib2, iclass 36, count 0 2006.211.08:14:09.48#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:14:09.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:14:09.48#ibcon#[25=USB\r\n] 2006.211.08:14:09.48#ibcon#*before write, iclass 36, count 0 2006.211.08:14:09.48#ibcon#enter sib2, iclass 36, count 0 2006.211.08:14:09.48#ibcon#flushed, iclass 36, count 0 2006.211.08:14:09.48#ibcon#about to write, iclass 36, count 0 2006.211.08:14:09.48#ibcon#wrote, iclass 36, count 0 2006.211.08:14:09.48#ibcon#about to read 3, iclass 36, count 0 2006.211.08:14:09.51#ibcon#read 3, iclass 36, count 0 2006.211.08:14:09.51#ibcon#about to read 4, iclass 36, count 0 2006.211.08:14:09.51#ibcon#read 4, iclass 36, count 0 2006.211.08:14:09.51#ibcon#about to read 5, iclass 36, count 0 2006.211.08:14:09.51#ibcon#read 5, iclass 36, count 0 2006.211.08:14:09.51#ibcon#about to read 6, iclass 36, count 0 2006.211.08:14:09.51#ibcon#read 6, iclass 36, count 0 2006.211.08:14:09.51#ibcon#end of sib2, iclass 36, count 0 2006.211.08:14:09.51#ibcon#*after write, iclass 36, count 0 2006.211.08:14:09.51#ibcon#*before return 0, iclass 36, count 0 2006.211.08:14:09.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:14:09.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:14:09.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:14:09.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:14:09.51$vc4f8/valo=7,832.99 2006.211.08:14:09.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:14:09.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:14:09.51#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:09.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:14:09.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:14:09.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:14:09.51#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:14:09.51#ibcon#first serial, iclass 38, count 0 2006.211.08:14:09.51#ibcon#enter sib2, iclass 38, count 0 2006.211.08:14:09.51#ibcon#flushed, iclass 38, count 0 2006.211.08:14:09.51#ibcon#about to write, iclass 38, count 0 2006.211.08:14:09.51#ibcon#wrote, iclass 38, count 0 2006.211.08:14:09.51#ibcon#about to read 3, iclass 38, count 0 2006.211.08:14:09.53#ibcon#read 3, iclass 38, count 0 2006.211.08:14:09.53#ibcon#about to read 4, iclass 38, count 0 2006.211.08:14:09.53#ibcon#read 4, iclass 38, count 0 2006.211.08:14:09.53#ibcon#about to read 5, iclass 38, count 0 2006.211.08:14:09.53#ibcon#read 5, iclass 38, count 0 2006.211.08:14:09.53#ibcon#about to read 6, iclass 38, count 0 2006.211.08:14:09.53#ibcon#read 6, iclass 38, count 0 2006.211.08:14:09.53#ibcon#end of sib2, iclass 38, count 0 2006.211.08:14:09.53#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:14:09.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:14:09.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:14:09.53#ibcon#*before write, iclass 38, count 0 2006.211.08:14:09.53#ibcon#enter sib2, iclass 38, count 0 2006.211.08:14:09.53#ibcon#flushed, iclass 38, count 0 2006.211.08:14:09.53#ibcon#about to write, iclass 38, count 0 2006.211.08:14:09.53#ibcon#wrote, iclass 38, count 0 2006.211.08:14:09.53#ibcon#about to read 3, iclass 38, count 0 2006.211.08:14:09.57#ibcon#read 3, iclass 38, count 0 2006.211.08:14:09.57#ibcon#about to read 4, iclass 38, count 0 2006.211.08:14:09.57#ibcon#read 4, iclass 38, count 0 2006.211.08:14:09.57#ibcon#about to read 5, iclass 38, count 0 2006.211.08:14:09.57#ibcon#read 5, iclass 38, count 0 2006.211.08:14:09.57#ibcon#about to read 6, iclass 38, count 0 2006.211.08:14:09.57#ibcon#read 6, iclass 38, count 0 2006.211.08:14:09.57#ibcon#end of sib2, iclass 38, count 0 2006.211.08:14:09.57#ibcon#*after write, iclass 38, count 0 2006.211.08:14:09.57#ibcon#*before return 0, iclass 38, count 0 2006.211.08:14:09.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:14:09.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:14:09.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:14:09.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:14:09.57$vc4f8/va=7,6 2006.211.08:14:09.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:14:09.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:14:09.57#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:09.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:14:09.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:14:09.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:14:09.63#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:14:09.63#ibcon#first serial, iclass 40, count 2 2006.211.08:14:09.63#ibcon#enter sib2, iclass 40, count 2 2006.211.08:14:09.63#ibcon#flushed, iclass 40, count 2 2006.211.08:14:09.63#ibcon#about to write, iclass 40, count 2 2006.211.08:14:09.63#ibcon#wrote, iclass 40, count 2 2006.211.08:14:09.63#ibcon#about to read 3, iclass 40, count 2 2006.211.08:14:09.65#ibcon#read 3, iclass 40, count 2 2006.211.08:14:09.65#ibcon#about to read 4, iclass 40, count 2 2006.211.08:14:09.65#ibcon#read 4, iclass 40, count 2 2006.211.08:14:09.65#ibcon#about to read 5, iclass 40, count 2 2006.211.08:14:09.65#ibcon#read 5, iclass 40, count 2 2006.211.08:14:09.65#ibcon#about to read 6, iclass 40, count 2 2006.211.08:14:09.65#ibcon#read 6, iclass 40, count 2 2006.211.08:14:09.65#ibcon#end of sib2, iclass 40, count 2 2006.211.08:14:09.65#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:14:09.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:14:09.65#ibcon#[25=AT07-06\r\n] 2006.211.08:14:09.65#ibcon#*before write, iclass 40, count 2 2006.211.08:14:09.65#ibcon#enter sib2, iclass 40, count 2 2006.211.08:14:09.65#ibcon#flushed, iclass 40, count 2 2006.211.08:14:09.65#ibcon#about to write, iclass 40, count 2 2006.211.08:14:09.65#ibcon#wrote, iclass 40, count 2 2006.211.08:14:09.65#ibcon#about to read 3, iclass 40, count 2 2006.211.08:14:09.68#ibcon#read 3, iclass 40, count 2 2006.211.08:14:09.68#ibcon#about to read 4, iclass 40, count 2 2006.211.08:14:09.68#ibcon#read 4, iclass 40, count 2 2006.211.08:14:09.68#ibcon#about to read 5, iclass 40, count 2 2006.211.08:14:09.68#ibcon#read 5, iclass 40, count 2 2006.211.08:14:09.68#ibcon#about to read 6, iclass 40, count 2 2006.211.08:14:09.68#ibcon#read 6, iclass 40, count 2 2006.211.08:14:09.68#ibcon#end of sib2, iclass 40, count 2 2006.211.08:14:09.68#ibcon#*after write, iclass 40, count 2 2006.211.08:14:09.68#ibcon#*before return 0, iclass 40, count 2 2006.211.08:14:09.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:14:09.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:14:09.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:14:09.68#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:09.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:14:09.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:14:09.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:14:09.80#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:14:09.80#ibcon#first serial, iclass 40, count 0 2006.211.08:14:09.80#ibcon#enter sib2, iclass 40, count 0 2006.211.08:14:09.80#ibcon#flushed, iclass 40, count 0 2006.211.08:14:09.80#ibcon#about to write, iclass 40, count 0 2006.211.08:14:09.80#ibcon#wrote, iclass 40, count 0 2006.211.08:14:09.80#ibcon#about to read 3, iclass 40, count 0 2006.211.08:14:09.82#ibcon#read 3, iclass 40, count 0 2006.211.08:14:09.82#ibcon#about to read 4, iclass 40, count 0 2006.211.08:14:09.82#ibcon#read 4, iclass 40, count 0 2006.211.08:14:09.82#ibcon#about to read 5, iclass 40, count 0 2006.211.08:14:09.82#ibcon#read 5, iclass 40, count 0 2006.211.08:14:09.82#ibcon#about to read 6, iclass 40, count 0 2006.211.08:14:09.82#ibcon#read 6, iclass 40, count 0 2006.211.08:14:09.82#ibcon#end of sib2, iclass 40, count 0 2006.211.08:14:09.82#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:14:09.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:14:09.82#ibcon#[25=USB\r\n] 2006.211.08:14:09.82#ibcon#*before write, iclass 40, count 0 2006.211.08:14:09.82#ibcon#enter sib2, iclass 40, count 0 2006.211.08:14:09.82#ibcon#flushed, iclass 40, count 0 2006.211.08:14:09.82#ibcon#about to write, iclass 40, count 0 2006.211.08:14:09.82#ibcon#wrote, iclass 40, count 0 2006.211.08:14:09.82#ibcon#about to read 3, iclass 40, count 0 2006.211.08:14:09.85#ibcon#read 3, iclass 40, count 0 2006.211.08:14:09.85#ibcon#about to read 4, iclass 40, count 0 2006.211.08:14:09.85#ibcon#read 4, iclass 40, count 0 2006.211.08:14:09.85#ibcon#about to read 5, iclass 40, count 0 2006.211.08:14:09.85#ibcon#read 5, iclass 40, count 0 2006.211.08:14:09.85#ibcon#about to read 6, iclass 40, count 0 2006.211.08:14:09.85#ibcon#read 6, iclass 40, count 0 2006.211.08:14:09.85#ibcon#end of sib2, iclass 40, count 0 2006.211.08:14:09.85#ibcon#*after write, iclass 40, count 0 2006.211.08:14:09.85#ibcon#*before return 0, iclass 40, count 0 2006.211.08:14:09.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:14:09.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:14:09.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:14:09.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:14:09.85$vc4f8/valo=8,852.99 2006.211.08:14:09.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:14:09.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:14:09.85#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:09.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:14:09.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:14:09.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:14:09.85#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:14:09.85#ibcon#first serial, iclass 4, count 0 2006.211.08:14:09.85#ibcon#enter sib2, iclass 4, count 0 2006.211.08:14:09.85#ibcon#flushed, iclass 4, count 0 2006.211.08:14:09.85#ibcon#about to write, iclass 4, count 0 2006.211.08:14:09.85#ibcon#wrote, iclass 4, count 0 2006.211.08:14:09.85#ibcon#about to read 3, iclass 4, count 0 2006.211.08:14:09.87#ibcon#read 3, iclass 4, count 0 2006.211.08:14:09.87#ibcon#about to read 4, iclass 4, count 0 2006.211.08:14:09.87#ibcon#read 4, iclass 4, count 0 2006.211.08:14:09.87#ibcon#about to read 5, iclass 4, count 0 2006.211.08:14:09.87#ibcon#read 5, iclass 4, count 0 2006.211.08:14:09.87#ibcon#about to read 6, iclass 4, count 0 2006.211.08:14:09.87#ibcon#read 6, iclass 4, count 0 2006.211.08:14:09.87#ibcon#end of sib2, iclass 4, count 0 2006.211.08:14:09.87#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:14:09.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:14:09.87#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:14:09.87#ibcon#*before write, iclass 4, count 0 2006.211.08:14:09.87#ibcon#enter sib2, iclass 4, count 0 2006.211.08:14:09.87#ibcon#flushed, iclass 4, count 0 2006.211.08:14:09.87#ibcon#about to write, iclass 4, count 0 2006.211.08:14:09.87#ibcon#wrote, iclass 4, count 0 2006.211.08:14:09.87#ibcon#about to read 3, iclass 4, count 0 2006.211.08:14:09.91#ibcon#read 3, iclass 4, count 0 2006.211.08:14:09.91#ibcon#about to read 4, iclass 4, count 0 2006.211.08:14:09.91#ibcon#read 4, iclass 4, count 0 2006.211.08:14:09.91#ibcon#about to read 5, iclass 4, count 0 2006.211.08:14:09.91#ibcon#read 5, iclass 4, count 0 2006.211.08:14:09.91#ibcon#about to read 6, iclass 4, count 0 2006.211.08:14:09.91#ibcon#read 6, iclass 4, count 0 2006.211.08:14:09.91#ibcon#end of sib2, iclass 4, count 0 2006.211.08:14:09.91#ibcon#*after write, iclass 4, count 0 2006.211.08:14:09.91#ibcon#*before return 0, iclass 4, count 0 2006.211.08:14:09.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:14:09.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:14:09.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:14:09.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:14:09.91$vc4f8/va=8,7 2006.211.08:14:09.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:14:09.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:14:09.91#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:09.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:14:09.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:14:09.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:14:09.97#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:14:09.97#ibcon#first serial, iclass 6, count 2 2006.211.08:14:09.97#ibcon#enter sib2, iclass 6, count 2 2006.211.08:14:09.97#ibcon#flushed, iclass 6, count 2 2006.211.08:14:09.97#ibcon#about to write, iclass 6, count 2 2006.211.08:14:09.97#ibcon#wrote, iclass 6, count 2 2006.211.08:14:09.97#ibcon#about to read 3, iclass 6, count 2 2006.211.08:14:09.99#ibcon#read 3, iclass 6, count 2 2006.211.08:14:09.99#ibcon#about to read 4, iclass 6, count 2 2006.211.08:14:09.99#ibcon#read 4, iclass 6, count 2 2006.211.08:14:09.99#ibcon#about to read 5, iclass 6, count 2 2006.211.08:14:09.99#ibcon#read 5, iclass 6, count 2 2006.211.08:14:09.99#ibcon#about to read 6, iclass 6, count 2 2006.211.08:14:09.99#ibcon#read 6, iclass 6, count 2 2006.211.08:14:09.99#ibcon#end of sib2, iclass 6, count 2 2006.211.08:14:09.99#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:14:09.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:14:09.99#ibcon#[25=AT08-07\r\n] 2006.211.08:14:09.99#ibcon#*before write, iclass 6, count 2 2006.211.08:14:09.99#ibcon#enter sib2, iclass 6, count 2 2006.211.08:14:09.99#ibcon#flushed, iclass 6, count 2 2006.211.08:14:09.99#ibcon#about to write, iclass 6, count 2 2006.211.08:14:09.99#ibcon#wrote, iclass 6, count 2 2006.211.08:14:09.99#ibcon#about to read 3, iclass 6, count 2 2006.211.08:14:10.02#ibcon#read 3, iclass 6, count 2 2006.211.08:14:10.02#ibcon#about to read 4, iclass 6, count 2 2006.211.08:14:10.02#ibcon#read 4, iclass 6, count 2 2006.211.08:14:10.02#ibcon#about to read 5, iclass 6, count 2 2006.211.08:14:10.02#ibcon#read 5, iclass 6, count 2 2006.211.08:14:10.02#ibcon#about to read 6, iclass 6, count 2 2006.211.08:14:10.02#ibcon#read 6, iclass 6, count 2 2006.211.08:14:10.02#ibcon#end of sib2, iclass 6, count 2 2006.211.08:14:10.02#ibcon#*after write, iclass 6, count 2 2006.211.08:14:10.02#ibcon#*before return 0, iclass 6, count 2 2006.211.08:14:10.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:14:10.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:14:10.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:14:10.02#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:10.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:14:10.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:14:10.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:14:10.14#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:14:10.14#ibcon#first serial, iclass 6, count 0 2006.211.08:14:10.14#ibcon#enter sib2, iclass 6, count 0 2006.211.08:14:10.14#ibcon#flushed, iclass 6, count 0 2006.211.08:14:10.14#ibcon#about to write, iclass 6, count 0 2006.211.08:14:10.14#ibcon#wrote, iclass 6, count 0 2006.211.08:14:10.14#ibcon#about to read 3, iclass 6, count 0 2006.211.08:14:10.16#ibcon#read 3, iclass 6, count 0 2006.211.08:14:10.16#ibcon#about to read 4, iclass 6, count 0 2006.211.08:14:10.16#ibcon#read 4, iclass 6, count 0 2006.211.08:14:10.16#ibcon#about to read 5, iclass 6, count 0 2006.211.08:14:10.16#ibcon#read 5, iclass 6, count 0 2006.211.08:14:10.16#ibcon#about to read 6, iclass 6, count 0 2006.211.08:14:10.16#ibcon#read 6, iclass 6, count 0 2006.211.08:14:10.16#ibcon#end of sib2, iclass 6, count 0 2006.211.08:14:10.16#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:14:10.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:14:10.16#ibcon#[25=USB\r\n] 2006.211.08:14:10.16#ibcon#*before write, iclass 6, count 0 2006.211.08:14:10.16#ibcon#enter sib2, iclass 6, count 0 2006.211.08:14:10.16#ibcon#flushed, iclass 6, count 0 2006.211.08:14:10.16#ibcon#about to write, iclass 6, count 0 2006.211.08:14:10.16#ibcon#wrote, iclass 6, count 0 2006.211.08:14:10.16#ibcon#about to read 3, iclass 6, count 0 2006.211.08:14:10.19#ibcon#read 3, iclass 6, count 0 2006.211.08:14:10.19#ibcon#about to read 4, iclass 6, count 0 2006.211.08:14:10.19#ibcon#read 4, iclass 6, count 0 2006.211.08:14:10.19#ibcon#about to read 5, iclass 6, count 0 2006.211.08:14:10.19#ibcon#read 5, iclass 6, count 0 2006.211.08:14:10.19#ibcon#about to read 6, iclass 6, count 0 2006.211.08:14:10.19#ibcon#read 6, iclass 6, count 0 2006.211.08:14:10.19#ibcon#end of sib2, iclass 6, count 0 2006.211.08:14:10.19#ibcon#*after write, iclass 6, count 0 2006.211.08:14:10.19#ibcon#*before return 0, iclass 6, count 0 2006.211.08:14:10.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:14:10.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:14:10.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:14:10.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:14:10.19$vc4f8/vblo=1,632.99 2006.211.08:14:10.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:14:10.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:14:10.19#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:10.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:14:10.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:14:10.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:14:10.19#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:14:10.19#ibcon#first serial, iclass 10, count 0 2006.211.08:14:10.19#ibcon#enter sib2, iclass 10, count 0 2006.211.08:14:10.19#ibcon#flushed, iclass 10, count 0 2006.211.08:14:10.19#ibcon#about to write, iclass 10, count 0 2006.211.08:14:10.19#ibcon#wrote, iclass 10, count 0 2006.211.08:14:10.19#ibcon#about to read 3, iclass 10, count 0 2006.211.08:14:10.21#ibcon#read 3, iclass 10, count 0 2006.211.08:14:10.21#ibcon#about to read 4, iclass 10, count 0 2006.211.08:14:10.21#ibcon#read 4, iclass 10, count 0 2006.211.08:14:10.21#ibcon#about to read 5, iclass 10, count 0 2006.211.08:14:10.21#ibcon#read 5, iclass 10, count 0 2006.211.08:14:10.21#ibcon#about to read 6, iclass 10, count 0 2006.211.08:14:10.21#ibcon#read 6, iclass 10, count 0 2006.211.08:14:10.21#ibcon#end of sib2, iclass 10, count 0 2006.211.08:14:10.21#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:14:10.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:14:10.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:14:10.21#ibcon#*before write, iclass 10, count 0 2006.211.08:14:10.21#ibcon#enter sib2, iclass 10, count 0 2006.211.08:14:10.21#ibcon#flushed, iclass 10, count 0 2006.211.08:14:10.21#ibcon#about to write, iclass 10, count 0 2006.211.08:14:10.21#ibcon#wrote, iclass 10, count 0 2006.211.08:14:10.21#ibcon#about to read 3, iclass 10, count 0 2006.211.08:14:10.25#ibcon#read 3, iclass 10, count 0 2006.211.08:14:10.25#ibcon#about to read 4, iclass 10, count 0 2006.211.08:14:10.25#ibcon#read 4, iclass 10, count 0 2006.211.08:14:10.25#ibcon#about to read 5, iclass 10, count 0 2006.211.08:14:10.25#ibcon#read 5, iclass 10, count 0 2006.211.08:14:10.25#ibcon#about to read 6, iclass 10, count 0 2006.211.08:14:10.25#ibcon#read 6, iclass 10, count 0 2006.211.08:14:10.25#ibcon#end of sib2, iclass 10, count 0 2006.211.08:14:10.25#ibcon#*after write, iclass 10, count 0 2006.211.08:14:10.25#ibcon#*before return 0, iclass 10, count 0 2006.211.08:14:10.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:14:10.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:14:10.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:14:10.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:14:10.25$vc4f8/vb=1,4 2006.211.08:14:10.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:14:10.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:14:10.25#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:10.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:14:10.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:14:10.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:14:10.25#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:14:10.25#ibcon#first serial, iclass 12, count 2 2006.211.08:14:10.25#ibcon#enter sib2, iclass 12, count 2 2006.211.08:14:10.25#ibcon#flushed, iclass 12, count 2 2006.211.08:14:10.25#ibcon#about to write, iclass 12, count 2 2006.211.08:14:10.25#ibcon#wrote, iclass 12, count 2 2006.211.08:14:10.25#ibcon#about to read 3, iclass 12, count 2 2006.211.08:14:10.27#ibcon#read 3, iclass 12, count 2 2006.211.08:14:10.27#ibcon#about to read 4, iclass 12, count 2 2006.211.08:14:10.27#ibcon#read 4, iclass 12, count 2 2006.211.08:14:10.27#ibcon#about to read 5, iclass 12, count 2 2006.211.08:14:10.27#ibcon#read 5, iclass 12, count 2 2006.211.08:14:10.27#ibcon#about to read 6, iclass 12, count 2 2006.211.08:14:10.27#ibcon#read 6, iclass 12, count 2 2006.211.08:14:10.27#ibcon#end of sib2, iclass 12, count 2 2006.211.08:14:10.27#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:14:10.27#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:14:10.27#ibcon#[27=AT01-04\r\n] 2006.211.08:14:10.27#ibcon#*before write, iclass 12, count 2 2006.211.08:14:10.27#ibcon#enter sib2, iclass 12, count 2 2006.211.08:14:10.27#ibcon#flushed, iclass 12, count 2 2006.211.08:14:10.27#ibcon#about to write, iclass 12, count 2 2006.211.08:14:10.27#ibcon#wrote, iclass 12, count 2 2006.211.08:14:10.27#ibcon#about to read 3, iclass 12, count 2 2006.211.08:14:10.30#ibcon#read 3, iclass 12, count 2 2006.211.08:14:10.30#ibcon#about to read 4, iclass 12, count 2 2006.211.08:14:10.30#ibcon#read 4, iclass 12, count 2 2006.211.08:14:10.30#ibcon#about to read 5, iclass 12, count 2 2006.211.08:14:10.30#ibcon#read 5, iclass 12, count 2 2006.211.08:14:10.30#ibcon#about to read 6, iclass 12, count 2 2006.211.08:14:10.30#ibcon#read 6, iclass 12, count 2 2006.211.08:14:10.30#ibcon#end of sib2, iclass 12, count 2 2006.211.08:14:10.30#ibcon#*after write, iclass 12, count 2 2006.211.08:14:10.30#ibcon#*before return 0, iclass 12, count 2 2006.211.08:14:10.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:14:10.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:14:10.30#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:14:10.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:10.30#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:14:10.42#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:14:10.42#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:14:10.42#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:14:10.42#ibcon#first serial, iclass 12, count 0 2006.211.08:14:10.42#ibcon#enter sib2, iclass 12, count 0 2006.211.08:14:10.42#ibcon#flushed, iclass 12, count 0 2006.211.08:14:10.42#ibcon#about to write, iclass 12, count 0 2006.211.08:14:10.42#ibcon#wrote, iclass 12, count 0 2006.211.08:14:10.42#ibcon#about to read 3, iclass 12, count 0 2006.211.08:14:10.44#ibcon#read 3, iclass 12, count 0 2006.211.08:14:10.44#ibcon#about to read 4, iclass 12, count 0 2006.211.08:14:10.44#ibcon#read 4, iclass 12, count 0 2006.211.08:14:10.44#ibcon#about to read 5, iclass 12, count 0 2006.211.08:14:10.44#ibcon#read 5, iclass 12, count 0 2006.211.08:14:10.44#ibcon#about to read 6, iclass 12, count 0 2006.211.08:14:10.44#ibcon#read 6, iclass 12, count 0 2006.211.08:14:10.44#ibcon#end of sib2, iclass 12, count 0 2006.211.08:14:10.44#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:14:10.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:14:10.44#ibcon#[27=USB\r\n] 2006.211.08:14:10.44#ibcon#*before write, iclass 12, count 0 2006.211.08:14:10.44#ibcon#enter sib2, iclass 12, count 0 2006.211.08:14:10.44#ibcon#flushed, iclass 12, count 0 2006.211.08:14:10.44#ibcon#about to write, iclass 12, count 0 2006.211.08:14:10.44#ibcon#wrote, iclass 12, count 0 2006.211.08:14:10.44#ibcon#about to read 3, iclass 12, count 0 2006.211.08:14:10.47#ibcon#read 3, iclass 12, count 0 2006.211.08:14:10.47#ibcon#about to read 4, iclass 12, count 0 2006.211.08:14:10.47#ibcon#read 4, iclass 12, count 0 2006.211.08:14:10.47#ibcon#about to read 5, iclass 12, count 0 2006.211.08:14:10.47#ibcon#read 5, iclass 12, count 0 2006.211.08:14:10.47#ibcon#about to read 6, iclass 12, count 0 2006.211.08:14:10.47#ibcon#read 6, iclass 12, count 0 2006.211.08:14:10.47#ibcon#end of sib2, iclass 12, count 0 2006.211.08:14:10.47#ibcon#*after write, iclass 12, count 0 2006.211.08:14:10.47#ibcon#*before return 0, iclass 12, count 0 2006.211.08:14:10.47#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:14:10.47#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:14:10.47#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:14:10.47#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:14:10.47$vc4f8/vblo=2,640.99 2006.211.08:14:10.47#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:14:10.47#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:14:10.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:10.47#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:10.47#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:10.47#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:10.47#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:14:10.47#ibcon#first serial, iclass 14, count 0 2006.211.08:14:10.47#ibcon#enter sib2, iclass 14, count 0 2006.211.08:14:10.47#ibcon#flushed, iclass 14, count 0 2006.211.08:14:10.47#ibcon#about to write, iclass 14, count 0 2006.211.08:14:10.47#ibcon#wrote, iclass 14, count 0 2006.211.08:14:10.47#ibcon#about to read 3, iclass 14, count 0 2006.211.08:14:10.49#ibcon#read 3, iclass 14, count 0 2006.211.08:14:10.49#ibcon#about to read 4, iclass 14, count 0 2006.211.08:14:10.49#ibcon#read 4, iclass 14, count 0 2006.211.08:14:10.49#ibcon#about to read 5, iclass 14, count 0 2006.211.08:14:10.49#ibcon#read 5, iclass 14, count 0 2006.211.08:14:10.49#ibcon#about to read 6, iclass 14, count 0 2006.211.08:14:10.49#ibcon#read 6, iclass 14, count 0 2006.211.08:14:10.49#ibcon#end of sib2, iclass 14, count 0 2006.211.08:14:10.49#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:14:10.49#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:14:10.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:14:10.49#ibcon#*before write, iclass 14, count 0 2006.211.08:14:10.49#ibcon#enter sib2, iclass 14, count 0 2006.211.08:14:10.49#ibcon#flushed, iclass 14, count 0 2006.211.08:14:10.49#ibcon#about to write, iclass 14, count 0 2006.211.08:14:10.49#ibcon#wrote, iclass 14, count 0 2006.211.08:14:10.49#ibcon#about to read 3, iclass 14, count 0 2006.211.08:14:10.53#ibcon#read 3, iclass 14, count 0 2006.211.08:14:10.53#ibcon#about to read 4, iclass 14, count 0 2006.211.08:14:10.53#ibcon#read 4, iclass 14, count 0 2006.211.08:14:10.53#ibcon#about to read 5, iclass 14, count 0 2006.211.08:14:10.53#ibcon#read 5, iclass 14, count 0 2006.211.08:14:10.53#ibcon#about to read 6, iclass 14, count 0 2006.211.08:14:10.53#ibcon#read 6, iclass 14, count 0 2006.211.08:14:10.53#ibcon#end of sib2, iclass 14, count 0 2006.211.08:14:10.53#ibcon#*after write, iclass 14, count 0 2006.211.08:14:10.53#ibcon#*before return 0, iclass 14, count 0 2006.211.08:14:10.53#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:10.53#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:14:10.53#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:14:10.53#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:14:10.53$vc4f8/vb=2,4 2006.211.08:14:10.53#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:14:10.53#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:14:10.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:10.53#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:10.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:10.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:10.59#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:14:10.59#ibcon#first serial, iclass 16, count 2 2006.211.08:14:10.59#ibcon#enter sib2, iclass 16, count 2 2006.211.08:14:10.59#ibcon#flushed, iclass 16, count 2 2006.211.08:14:10.59#ibcon#about to write, iclass 16, count 2 2006.211.08:14:10.59#ibcon#wrote, iclass 16, count 2 2006.211.08:14:10.59#ibcon#about to read 3, iclass 16, count 2 2006.211.08:14:10.61#ibcon#read 3, iclass 16, count 2 2006.211.08:14:10.61#ibcon#about to read 4, iclass 16, count 2 2006.211.08:14:10.61#ibcon#read 4, iclass 16, count 2 2006.211.08:14:10.61#ibcon#about to read 5, iclass 16, count 2 2006.211.08:14:10.61#ibcon#read 5, iclass 16, count 2 2006.211.08:14:10.61#ibcon#about to read 6, iclass 16, count 2 2006.211.08:14:10.61#ibcon#read 6, iclass 16, count 2 2006.211.08:14:10.61#ibcon#end of sib2, iclass 16, count 2 2006.211.08:14:10.61#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:14:10.61#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:14:10.61#ibcon#[27=AT02-04\r\n] 2006.211.08:14:10.61#ibcon#*before write, iclass 16, count 2 2006.211.08:14:10.61#ibcon#enter sib2, iclass 16, count 2 2006.211.08:14:10.61#ibcon#flushed, iclass 16, count 2 2006.211.08:14:10.61#ibcon#about to write, iclass 16, count 2 2006.211.08:14:10.61#ibcon#wrote, iclass 16, count 2 2006.211.08:14:10.61#ibcon#about to read 3, iclass 16, count 2 2006.211.08:14:10.64#ibcon#read 3, iclass 16, count 2 2006.211.08:14:10.64#ibcon#about to read 4, iclass 16, count 2 2006.211.08:14:10.64#ibcon#read 4, iclass 16, count 2 2006.211.08:14:10.64#ibcon#about to read 5, iclass 16, count 2 2006.211.08:14:10.64#ibcon#read 5, iclass 16, count 2 2006.211.08:14:10.64#ibcon#about to read 6, iclass 16, count 2 2006.211.08:14:10.64#ibcon#read 6, iclass 16, count 2 2006.211.08:14:10.64#ibcon#end of sib2, iclass 16, count 2 2006.211.08:14:10.64#ibcon#*after write, iclass 16, count 2 2006.211.08:14:10.64#ibcon#*before return 0, iclass 16, count 2 2006.211.08:14:10.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:10.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:14:10.64#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:14:10.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:10.64#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:10.76#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:10.76#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:10.76#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:14:10.76#ibcon#first serial, iclass 16, count 0 2006.211.08:14:10.76#ibcon#enter sib2, iclass 16, count 0 2006.211.08:14:10.76#ibcon#flushed, iclass 16, count 0 2006.211.08:14:10.76#ibcon#about to write, iclass 16, count 0 2006.211.08:14:10.76#ibcon#wrote, iclass 16, count 0 2006.211.08:14:10.76#ibcon#about to read 3, iclass 16, count 0 2006.211.08:14:10.78#ibcon#read 3, iclass 16, count 0 2006.211.08:14:10.78#ibcon#about to read 4, iclass 16, count 0 2006.211.08:14:10.78#ibcon#read 4, iclass 16, count 0 2006.211.08:14:10.78#ibcon#about to read 5, iclass 16, count 0 2006.211.08:14:10.78#ibcon#read 5, iclass 16, count 0 2006.211.08:14:10.78#ibcon#about to read 6, iclass 16, count 0 2006.211.08:14:10.78#ibcon#read 6, iclass 16, count 0 2006.211.08:14:10.78#ibcon#end of sib2, iclass 16, count 0 2006.211.08:14:10.78#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:14:10.78#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:14:10.78#ibcon#[27=USB\r\n] 2006.211.08:14:10.78#ibcon#*before write, iclass 16, count 0 2006.211.08:14:10.78#ibcon#enter sib2, iclass 16, count 0 2006.211.08:14:10.78#ibcon#flushed, iclass 16, count 0 2006.211.08:14:10.78#ibcon#about to write, iclass 16, count 0 2006.211.08:14:10.78#ibcon#wrote, iclass 16, count 0 2006.211.08:14:10.78#ibcon#about to read 3, iclass 16, count 0 2006.211.08:14:10.81#ibcon#read 3, iclass 16, count 0 2006.211.08:14:10.81#ibcon#about to read 4, iclass 16, count 0 2006.211.08:14:10.81#ibcon#read 4, iclass 16, count 0 2006.211.08:14:10.81#ibcon#about to read 5, iclass 16, count 0 2006.211.08:14:10.81#ibcon#read 5, iclass 16, count 0 2006.211.08:14:10.81#ibcon#about to read 6, iclass 16, count 0 2006.211.08:14:10.81#ibcon#read 6, iclass 16, count 0 2006.211.08:14:10.81#ibcon#end of sib2, iclass 16, count 0 2006.211.08:14:10.81#ibcon#*after write, iclass 16, count 0 2006.211.08:14:10.81#ibcon#*before return 0, iclass 16, count 0 2006.211.08:14:10.81#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:10.81#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:14:10.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:14:10.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:14:10.81$vc4f8/vblo=3,656.99 2006.211.08:14:10.81#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:14:10.81#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:14:10.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:10.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:10.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:10.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:10.81#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:14:10.81#ibcon#first serial, iclass 18, count 0 2006.211.08:14:10.81#ibcon#enter sib2, iclass 18, count 0 2006.211.08:14:10.81#ibcon#flushed, iclass 18, count 0 2006.211.08:14:10.81#ibcon#about to write, iclass 18, count 0 2006.211.08:14:10.81#ibcon#wrote, iclass 18, count 0 2006.211.08:14:10.81#ibcon#about to read 3, iclass 18, count 0 2006.211.08:14:10.83#ibcon#read 3, iclass 18, count 0 2006.211.08:14:10.83#ibcon#about to read 4, iclass 18, count 0 2006.211.08:14:10.83#ibcon#read 4, iclass 18, count 0 2006.211.08:14:10.83#ibcon#about to read 5, iclass 18, count 0 2006.211.08:14:10.83#ibcon#read 5, iclass 18, count 0 2006.211.08:14:10.83#ibcon#about to read 6, iclass 18, count 0 2006.211.08:14:10.83#ibcon#read 6, iclass 18, count 0 2006.211.08:14:10.83#ibcon#end of sib2, iclass 18, count 0 2006.211.08:14:10.83#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:14:10.83#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:14:10.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:14:10.83#ibcon#*before write, iclass 18, count 0 2006.211.08:14:10.83#ibcon#enter sib2, iclass 18, count 0 2006.211.08:14:10.83#ibcon#flushed, iclass 18, count 0 2006.211.08:14:10.83#ibcon#about to write, iclass 18, count 0 2006.211.08:14:10.83#ibcon#wrote, iclass 18, count 0 2006.211.08:14:10.83#ibcon#about to read 3, iclass 18, count 0 2006.211.08:14:10.87#ibcon#read 3, iclass 18, count 0 2006.211.08:14:10.87#ibcon#about to read 4, iclass 18, count 0 2006.211.08:14:10.87#ibcon#read 4, iclass 18, count 0 2006.211.08:14:10.87#ibcon#about to read 5, iclass 18, count 0 2006.211.08:14:10.87#ibcon#read 5, iclass 18, count 0 2006.211.08:14:10.87#ibcon#about to read 6, iclass 18, count 0 2006.211.08:14:10.87#ibcon#read 6, iclass 18, count 0 2006.211.08:14:10.87#ibcon#end of sib2, iclass 18, count 0 2006.211.08:14:10.87#ibcon#*after write, iclass 18, count 0 2006.211.08:14:10.87#ibcon#*before return 0, iclass 18, count 0 2006.211.08:14:10.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:10.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:14:10.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:14:10.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:14:10.87$vc4f8/vb=3,3 2006.211.08:14:10.87#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:14:10.87#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:14:10.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:10.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:10.93#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:10.93#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:10.93#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:14:10.93#ibcon#first serial, iclass 20, count 2 2006.211.08:14:10.93#ibcon#enter sib2, iclass 20, count 2 2006.211.08:14:10.93#ibcon#flushed, iclass 20, count 2 2006.211.08:14:10.93#ibcon#about to write, iclass 20, count 2 2006.211.08:14:10.93#ibcon#wrote, iclass 20, count 2 2006.211.08:14:10.93#ibcon#about to read 3, iclass 20, count 2 2006.211.08:14:10.95#ibcon#read 3, iclass 20, count 2 2006.211.08:14:10.95#ibcon#about to read 4, iclass 20, count 2 2006.211.08:14:10.95#ibcon#read 4, iclass 20, count 2 2006.211.08:14:10.95#ibcon#about to read 5, iclass 20, count 2 2006.211.08:14:10.95#ibcon#read 5, iclass 20, count 2 2006.211.08:14:10.95#ibcon#about to read 6, iclass 20, count 2 2006.211.08:14:10.95#ibcon#read 6, iclass 20, count 2 2006.211.08:14:10.95#ibcon#end of sib2, iclass 20, count 2 2006.211.08:14:10.95#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:14:10.95#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:14:10.95#ibcon#[27=AT03-03\r\n] 2006.211.08:14:10.95#ibcon#*before write, iclass 20, count 2 2006.211.08:14:10.95#ibcon#enter sib2, iclass 20, count 2 2006.211.08:14:10.95#ibcon#flushed, iclass 20, count 2 2006.211.08:14:10.95#ibcon#about to write, iclass 20, count 2 2006.211.08:14:10.95#ibcon#wrote, iclass 20, count 2 2006.211.08:14:10.95#ibcon#about to read 3, iclass 20, count 2 2006.211.08:14:10.98#ibcon#read 3, iclass 20, count 2 2006.211.08:14:10.98#ibcon#about to read 4, iclass 20, count 2 2006.211.08:14:10.98#ibcon#read 4, iclass 20, count 2 2006.211.08:14:10.98#ibcon#about to read 5, iclass 20, count 2 2006.211.08:14:10.98#ibcon#read 5, iclass 20, count 2 2006.211.08:14:10.98#ibcon#about to read 6, iclass 20, count 2 2006.211.08:14:10.98#ibcon#read 6, iclass 20, count 2 2006.211.08:14:10.98#ibcon#end of sib2, iclass 20, count 2 2006.211.08:14:10.98#ibcon#*after write, iclass 20, count 2 2006.211.08:14:10.98#ibcon#*before return 0, iclass 20, count 2 2006.211.08:14:10.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:10.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:14:10.98#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:14:10.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:10.98#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:11.10#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:11.10#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:11.10#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:14:11.10#ibcon#first serial, iclass 20, count 0 2006.211.08:14:11.10#ibcon#enter sib2, iclass 20, count 0 2006.211.08:14:11.10#ibcon#flushed, iclass 20, count 0 2006.211.08:14:11.10#ibcon#about to write, iclass 20, count 0 2006.211.08:14:11.10#ibcon#wrote, iclass 20, count 0 2006.211.08:14:11.10#ibcon#about to read 3, iclass 20, count 0 2006.211.08:14:11.12#ibcon#read 3, iclass 20, count 0 2006.211.08:14:11.12#ibcon#about to read 4, iclass 20, count 0 2006.211.08:14:11.12#ibcon#read 4, iclass 20, count 0 2006.211.08:14:11.12#ibcon#about to read 5, iclass 20, count 0 2006.211.08:14:11.12#ibcon#read 5, iclass 20, count 0 2006.211.08:14:11.12#ibcon#about to read 6, iclass 20, count 0 2006.211.08:14:11.12#ibcon#read 6, iclass 20, count 0 2006.211.08:14:11.12#ibcon#end of sib2, iclass 20, count 0 2006.211.08:14:11.12#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:14:11.12#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:14:11.12#ibcon#[27=USB\r\n] 2006.211.08:14:11.12#ibcon#*before write, iclass 20, count 0 2006.211.08:14:11.12#ibcon#enter sib2, iclass 20, count 0 2006.211.08:14:11.12#ibcon#flushed, iclass 20, count 0 2006.211.08:14:11.12#ibcon#about to write, iclass 20, count 0 2006.211.08:14:11.12#ibcon#wrote, iclass 20, count 0 2006.211.08:14:11.12#ibcon#about to read 3, iclass 20, count 0 2006.211.08:14:11.15#ibcon#read 3, iclass 20, count 0 2006.211.08:14:11.15#ibcon#about to read 4, iclass 20, count 0 2006.211.08:14:11.15#ibcon#read 4, iclass 20, count 0 2006.211.08:14:11.15#ibcon#about to read 5, iclass 20, count 0 2006.211.08:14:11.15#ibcon#read 5, iclass 20, count 0 2006.211.08:14:11.15#ibcon#about to read 6, iclass 20, count 0 2006.211.08:14:11.15#ibcon#read 6, iclass 20, count 0 2006.211.08:14:11.15#ibcon#end of sib2, iclass 20, count 0 2006.211.08:14:11.15#ibcon#*after write, iclass 20, count 0 2006.211.08:14:11.15#ibcon#*before return 0, iclass 20, count 0 2006.211.08:14:11.15#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:11.15#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:14:11.15#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:14:11.15#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:14:11.15$vc4f8/vblo=4,712.99 2006.211.08:14:11.15#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:14:11.15#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:14:11.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:11.15#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:11.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:11.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:11.15#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:14:11.15#ibcon#first serial, iclass 22, count 0 2006.211.08:14:11.15#ibcon#enter sib2, iclass 22, count 0 2006.211.08:14:11.15#ibcon#flushed, iclass 22, count 0 2006.211.08:14:11.15#ibcon#about to write, iclass 22, count 0 2006.211.08:14:11.15#ibcon#wrote, iclass 22, count 0 2006.211.08:14:11.15#ibcon#about to read 3, iclass 22, count 0 2006.211.08:14:11.17#ibcon#read 3, iclass 22, count 0 2006.211.08:14:11.17#ibcon#about to read 4, iclass 22, count 0 2006.211.08:14:11.17#ibcon#read 4, iclass 22, count 0 2006.211.08:14:11.17#ibcon#about to read 5, iclass 22, count 0 2006.211.08:14:11.17#ibcon#read 5, iclass 22, count 0 2006.211.08:14:11.17#ibcon#about to read 6, iclass 22, count 0 2006.211.08:14:11.17#ibcon#read 6, iclass 22, count 0 2006.211.08:14:11.17#ibcon#end of sib2, iclass 22, count 0 2006.211.08:14:11.17#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:14:11.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:14:11.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:14:11.17#ibcon#*before write, iclass 22, count 0 2006.211.08:14:11.17#ibcon#enter sib2, iclass 22, count 0 2006.211.08:14:11.17#ibcon#flushed, iclass 22, count 0 2006.211.08:14:11.17#ibcon#about to write, iclass 22, count 0 2006.211.08:14:11.17#ibcon#wrote, iclass 22, count 0 2006.211.08:14:11.17#ibcon#about to read 3, iclass 22, count 0 2006.211.08:14:11.21#ibcon#read 3, iclass 22, count 0 2006.211.08:14:11.21#ibcon#about to read 4, iclass 22, count 0 2006.211.08:14:11.21#ibcon#read 4, iclass 22, count 0 2006.211.08:14:11.21#ibcon#about to read 5, iclass 22, count 0 2006.211.08:14:11.21#ibcon#read 5, iclass 22, count 0 2006.211.08:14:11.21#ibcon#about to read 6, iclass 22, count 0 2006.211.08:14:11.21#ibcon#read 6, iclass 22, count 0 2006.211.08:14:11.21#ibcon#end of sib2, iclass 22, count 0 2006.211.08:14:11.21#ibcon#*after write, iclass 22, count 0 2006.211.08:14:11.21#ibcon#*before return 0, iclass 22, count 0 2006.211.08:14:11.21#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:11.21#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:14:11.21#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:14:11.21#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:14:11.21$vc4f8/vb=4,3 2006.211.08:14:11.21#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:14:11.21#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:14:11.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:11.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:11.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:11.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:11.27#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:14:11.27#ibcon#first serial, iclass 24, count 2 2006.211.08:14:11.27#ibcon#enter sib2, iclass 24, count 2 2006.211.08:14:11.27#ibcon#flushed, iclass 24, count 2 2006.211.08:14:11.27#ibcon#about to write, iclass 24, count 2 2006.211.08:14:11.27#ibcon#wrote, iclass 24, count 2 2006.211.08:14:11.27#ibcon#about to read 3, iclass 24, count 2 2006.211.08:14:11.29#ibcon#read 3, iclass 24, count 2 2006.211.08:14:11.29#ibcon#about to read 4, iclass 24, count 2 2006.211.08:14:11.29#ibcon#read 4, iclass 24, count 2 2006.211.08:14:11.29#ibcon#about to read 5, iclass 24, count 2 2006.211.08:14:11.29#ibcon#read 5, iclass 24, count 2 2006.211.08:14:11.29#ibcon#about to read 6, iclass 24, count 2 2006.211.08:14:11.29#ibcon#read 6, iclass 24, count 2 2006.211.08:14:11.29#ibcon#end of sib2, iclass 24, count 2 2006.211.08:14:11.29#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:14:11.29#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:14:11.29#ibcon#[27=AT04-03\r\n] 2006.211.08:14:11.29#ibcon#*before write, iclass 24, count 2 2006.211.08:14:11.29#ibcon#enter sib2, iclass 24, count 2 2006.211.08:14:11.29#ibcon#flushed, iclass 24, count 2 2006.211.08:14:11.29#ibcon#about to write, iclass 24, count 2 2006.211.08:14:11.29#ibcon#wrote, iclass 24, count 2 2006.211.08:14:11.29#ibcon#about to read 3, iclass 24, count 2 2006.211.08:14:11.32#ibcon#read 3, iclass 24, count 2 2006.211.08:14:11.32#ibcon#about to read 4, iclass 24, count 2 2006.211.08:14:11.32#ibcon#read 4, iclass 24, count 2 2006.211.08:14:11.32#ibcon#about to read 5, iclass 24, count 2 2006.211.08:14:11.32#ibcon#read 5, iclass 24, count 2 2006.211.08:14:11.32#ibcon#about to read 6, iclass 24, count 2 2006.211.08:14:11.32#ibcon#read 6, iclass 24, count 2 2006.211.08:14:11.32#ibcon#end of sib2, iclass 24, count 2 2006.211.08:14:11.32#ibcon#*after write, iclass 24, count 2 2006.211.08:14:11.32#ibcon#*before return 0, iclass 24, count 2 2006.211.08:14:11.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:11.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:14:11.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:14:11.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:11.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:11.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:11.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:11.44#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:14:11.44#ibcon#first serial, iclass 24, count 0 2006.211.08:14:11.44#ibcon#enter sib2, iclass 24, count 0 2006.211.08:14:11.44#ibcon#flushed, iclass 24, count 0 2006.211.08:14:11.44#ibcon#about to write, iclass 24, count 0 2006.211.08:14:11.44#ibcon#wrote, iclass 24, count 0 2006.211.08:14:11.44#ibcon#about to read 3, iclass 24, count 0 2006.211.08:14:11.46#ibcon#read 3, iclass 24, count 0 2006.211.08:14:11.46#ibcon#about to read 4, iclass 24, count 0 2006.211.08:14:11.46#ibcon#read 4, iclass 24, count 0 2006.211.08:14:11.46#ibcon#about to read 5, iclass 24, count 0 2006.211.08:14:11.46#ibcon#read 5, iclass 24, count 0 2006.211.08:14:11.46#ibcon#about to read 6, iclass 24, count 0 2006.211.08:14:11.46#ibcon#read 6, iclass 24, count 0 2006.211.08:14:11.46#ibcon#end of sib2, iclass 24, count 0 2006.211.08:14:11.46#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:14:11.46#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:14:11.46#ibcon#[27=USB\r\n] 2006.211.08:14:11.46#ibcon#*before write, iclass 24, count 0 2006.211.08:14:11.46#ibcon#enter sib2, iclass 24, count 0 2006.211.08:14:11.46#ibcon#flushed, iclass 24, count 0 2006.211.08:14:11.46#ibcon#about to write, iclass 24, count 0 2006.211.08:14:11.46#ibcon#wrote, iclass 24, count 0 2006.211.08:14:11.46#ibcon#about to read 3, iclass 24, count 0 2006.211.08:14:11.49#ibcon#read 3, iclass 24, count 0 2006.211.08:14:11.49#ibcon#about to read 4, iclass 24, count 0 2006.211.08:14:11.49#ibcon#read 4, iclass 24, count 0 2006.211.08:14:11.49#ibcon#about to read 5, iclass 24, count 0 2006.211.08:14:11.49#ibcon#read 5, iclass 24, count 0 2006.211.08:14:11.49#ibcon#about to read 6, iclass 24, count 0 2006.211.08:14:11.49#ibcon#read 6, iclass 24, count 0 2006.211.08:14:11.49#ibcon#end of sib2, iclass 24, count 0 2006.211.08:14:11.49#ibcon#*after write, iclass 24, count 0 2006.211.08:14:11.49#ibcon#*before return 0, iclass 24, count 0 2006.211.08:14:11.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:11.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:14:11.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:14:11.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:14:11.49$vc4f8/vblo=5,744.99 2006.211.08:14:11.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:14:11.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:14:11.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:11.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:11.49#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:11.49#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:11.49#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:14:11.49#ibcon#first serial, iclass 26, count 0 2006.211.08:14:11.49#ibcon#enter sib2, iclass 26, count 0 2006.211.08:14:11.49#ibcon#flushed, iclass 26, count 0 2006.211.08:14:11.49#ibcon#about to write, iclass 26, count 0 2006.211.08:14:11.49#ibcon#wrote, iclass 26, count 0 2006.211.08:14:11.49#ibcon#about to read 3, iclass 26, count 0 2006.211.08:14:11.51#ibcon#read 3, iclass 26, count 0 2006.211.08:14:11.51#ibcon#about to read 4, iclass 26, count 0 2006.211.08:14:11.51#ibcon#read 4, iclass 26, count 0 2006.211.08:14:11.51#ibcon#about to read 5, iclass 26, count 0 2006.211.08:14:11.51#ibcon#read 5, iclass 26, count 0 2006.211.08:14:11.51#ibcon#about to read 6, iclass 26, count 0 2006.211.08:14:11.51#ibcon#read 6, iclass 26, count 0 2006.211.08:14:11.51#ibcon#end of sib2, iclass 26, count 0 2006.211.08:14:11.51#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:14:11.51#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:14:11.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:14:11.51#ibcon#*before write, iclass 26, count 0 2006.211.08:14:11.51#ibcon#enter sib2, iclass 26, count 0 2006.211.08:14:11.51#ibcon#flushed, iclass 26, count 0 2006.211.08:14:11.51#ibcon#about to write, iclass 26, count 0 2006.211.08:14:11.51#ibcon#wrote, iclass 26, count 0 2006.211.08:14:11.51#ibcon#about to read 3, iclass 26, count 0 2006.211.08:14:11.55#ibcon#read 3, iclass 26, count 0 2006.211.08:14:11.55#ibcon#about to read 4, iclass 26, count 0 2006.211.08:14:11.55#ibcon#read 4, iclass 26, count 0 2006.211.08:14:11.55#ibcon#about to read 5, iclass 26, count 0 2006.211.08:14:11.55#ibcon#read 5, iclass 26, count 0 2006.211.08:14:11.55#ibcon#about to read 6, iclass 26, count 0 2006.211.08:14:11.55#ibcon#read 6, iclass 26, count 0 2006.211.08:14:11.55#ibcon#end of sib2, iclass 26, count 0 2006.211.08:14:11.55#ibcon#*after write, iclass 26, count 0 2006.211.08:14:11.55#ibcon#*before return 0, iclass 26, count 0 2006.211.08:14:11.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:11.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:14:11.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:14:11.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:14:11.55$vc4f8/vb=5,3 2006.211.08:14:11.55#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:14:11.55#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:14:11.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:11.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:11.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:11.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:11.61#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:14:11.61#ibcon#first serial, iclass 28, count 2 2006.211.08:14:11.61#ibcon#enter sib2, iclass 28, count 2 2006.211.08:14:11.61#ibcon#flushed, iclass 28, count 2 2006.211.08:14:11.61#ibcon#about to write, iclass 28, count 2 2006.211.08:14:11.61#ibcon#wrote, iclass 28, count 2 2006.211.08:14:11.61#ibcon#about to read 3, iclass 28, count 2 2006.211.08:14:11.63#ibcon#read 3, iclass 28, count 2 2006.211.08:14:11.63#ibcon#about to read 4, iclass 28, count 2 2006.211.08:14:11.63#ibcon#read 4, iclass 28, count 2 2006.211.08:14:11.63#ibcon#about to read 5, iclass 28, count 2 2006.211.08:14:11.63#ibcon#read 5, iclass 28, count 2 2006.211.08:14:11.63#ibcon#about to read 6, iclass 28, count 2 2006.211.08:14:11.63#ibcon#read 6, iclass 28, count 2 2006.211.08:14:11.63#ibcon#end of sib2, iclass 28, count 2 2006.211.08:14:11.63#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:14:11.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:14:11.63#ibcon#[27=AT05-03\r\n] 2006.211.08:14:11.63#ibcon#*before write, iclass 28, count 2 2006.211.08:14:11.63#ibcon#enter sib2, iclass 28, count 2 2006.211.08:14:11.63#ibcon#flushed, iclass 28, count 2 2006.211.08:14:11.63#ibcon#about to write, iclass 28, count 2 2006.211.08:14:11.63#ibcon#wrote, iclass 28, count 2 2006.211.08:14:11.63#ibcon#about to read 3, iclass 28, count 2 2006.211.08:14:11.66#ibcon#read 3, iclass 28, count 2 2006.211.08:14:11.66#ibcon#about to read 4, iclass 28, count 2 2006.211.08:14:11.66#ibcon#read 4, iclass 28, count 2 2006.211.08:14:11.66#ibcon#about to read 5, iclass 28, count 2 2006.211.08:14:11.66#ibcon#read 5, iclass 28, count 2 2006.211.08:14:11.66#ibcon#about to read 6, iclass 28, count 2 2006.211.08:14:11.66#ibcon#read 6, iclass 28, count 2 2006.211.08:14:11.66#ibcon#end of sib2, iclass 28, count 2 2006.211.08:14:11.66#ibcon#*after write, iclass 28, count 2 2006.211.08:14:11.66#ibcon#*before return 0, iclass 28, count 2 2006.211.08:14:11.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:11.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:14:11.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:14:11.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:11.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:11.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:11.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:11.78#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:14:11.78#ibcon#first serial, iclass 28, count 0 2006.211.08:14:11.78#ibcon#enter sib2, iclass 28, count 0 2006.211.08:14:11.78#ibcon#flushed, iclass 28, count 0 2006.211.08:14:11.78#ibcon#about to write, iclass 28, count 0 2006.211.08:14:11.78#ibcon#wrote, iclass 28, count 0 2006.211.08:14:11.78#ibcon#about to read 3, iclass 28, count 0 2006.211.08:14:11.80#ibcon#read 3, iclass 28, count 0 2006.211.08:14:11.80#ibcon#about to read 4, iclass 28, count 0 2006.211.08:14:11.80#ibcon#read 4, iclass 28, count 0 2006.211.08:14:11.80#ibcon#about to read 5, iclass 28, count 0 2006.211.08:14:11.80#ibcon#read 5, iclass 28, count 0 2006.211.08:14:11.80#ibcon#about to read 6, iclass 28, count 0 2006.211.08:14:11.80#ibcon#read 6, iclass 28, count 0 2006.211.08:14:11.80#ibcon#end of sib2, iclass 28, count 0 2006.211.08:14:11.80#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:14:11.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:14:11.80#ibcon#[27=USB\r\n] 2006.211.08:14:11.80#ibcon#*before write, iclass 28, count 0 2006.211.08:14:11.80#ibcon#enter sib2, iclass 28, count 0 2006.211.08:14:11.80#ibcon#flushed, iclass 28, count 0 2006.211.08:14:11.80#ibcon#about to write, iclass 28, count 0 2006.211.08:14:11.80#ibcon#wrote, iclass 28, count 0 2006.211.08:14:11.80#ibcon#about to read 3, iclass 28, count 0 2006.211.08:14:11.83#ibcon#read 3, iclass 28, count 0 2006.211.08:14:11.83#ibcon#about to read 4, iclass 28, count 0 2006.211.08:14:11.83#ibcon#read 4, iclass 28, count 0 2006.211.08:14:11.83#ibcon#about to read 5, iclass 28, count 0 2006.211.08:14:11.83#ibcon#read 5, iclass 28, count 0 2006.211.08:14:11.83#ibcon#about to read 6, iclass 28, count 0 2006.211.08:14:11.83#ibcon#read 6, iclass 28, count 0 2006.211.08:14:11.83#ibcon#end of sib2, iclass 28, count 0 2006.211.08:14:11.83#ibcon#*after write, iclass 28, count 0 2006.211.08:14:11.83#ibcon#*before return 0, iclass 28, count 0 2006.211.08:14:11.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:11.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:14:11.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:14:11.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:14:11.83$vc4f8/vblo=6,752.99 2006.211.08:14:11.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:14:11.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:14:11.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:14:11.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:11.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:11.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:11.83#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:14:11.83#ibcon#first serial, iclass 30, count 0 2006.211.08:14:11.83#ibcon#enter sib2, iclass 30, count 0 2006.211.08:14:11.83#ibcon#flushed, iclass 30, count 0 2006.211.08:14:11.83#ibcon#about to write, iclass 30, count 0 2006.211.08:14:11.83#ibcon#wrote, iclass 30, count 0 2006.211.08:14:11.83#ibcon#about to read 3, iclass 30, count 0 2006.211.08:14:11.85#ibcon#read 3, iclass 30, count 0 2006.211.08:14:11.85#ibcon#about to read 4, iclass 30, count 0 2006.211.08:14:11.85#ibcon#read 4, iclass 30, count 0 2006.211.08:14:11.85#ibcon#about to read 5, iclass 30, count 0 2006.211.08:14:11.85#ibcon#read 5, iclass 30, count 0 2006.211.08:14:11.85#ibcon#about to read 6, iclass 30, count 0 2006.211.08:14:11.85#ibcon#read 6, iclass 30, count 0 2006.211.08:14:11.85#ibcon#end of sib2, iclass 30, count 0 2006.211.08:14:11.85#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:14:11.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:14:11.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:14:11.85#ibcon#*before write, iclass 30, count 0 2006.211.08:14:11.85#ibcon#enter sib2, iclass 30, count 0 2006.211.08:14:11.85#ibcon#flushed, iclass 30, count 0 2006.211.08:14:11.85#ibcon#about to write, iclass 30, count 0 2006.211.08:14:11.85#ibcon#wrote, iclass 30, count 0 2006.211.08:14:11.85#ibcon#about to read 3, iclass 30, count 0 2006.211.08:14:11.89#ibcon#read 3, iclass 30, count 0 2006.211.08:14:11.89#ibcon#about to read 4, iclass 30, count 0 2006.211.08:14:11.89#ibcon#read 4, iclass 30, count 0 2006.211.08:14:11.89#ibcon#about to read 5, iclass 30, count 0 2006.211.08:14:11.89#ibcon#read 5, iclass 30, count 0 2006.211.08:14:11.89#ibcon#about to read 6, iclass 30, count 0 2006.211.08:14:11.89#ibcon#read 6, iclass 30, count 0 2006.211.08:14:11.89#ibcon#end of sib2, iclass 30, count 0 2006.211.08:14:11.89#ibcon#*after write, iclass 30, count 0 2006.211.08:14:11.89#ibcon#*before return 0, iclass 30, count 0 2006.211.08:14:11.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:11.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:14:11.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:14:11.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:14:11.89$vc4f8/vb=6,3 2006.211.08:14:11.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:14:11.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:14:11.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:14:11.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:11.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:11.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:11.95#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:14:11.95#ibcon#first serial, iclass 32, count 2 2006.211.08:14:11.95#ibcon#enter sib2, iclass 32, count 2 2006.211.08:14:11.95#ibcon#flushed, iclass 32, count 2 2006.211.08:14:11.95#ibcon#about to write, iclass 32, count 2 2006.211.08:14:11.95#ibcon#wrote, iclass 32, count 2 2006.211.08:14:11.95#ibcon#about to read 3, iclass 32, count 2 2006.211.08:14:11.97#ibcon#read 3, iclass 32, count 2 2006.211.08:14:11.97#ibcon#about to read 4, iclass 32, count 2 2006.211.08:14:11.97#ibcon#read 4, iclass 32, count 2 2006.211.08:14:11.97#ibcon#about to read 5, iclass 32, count 2 2006.211.08:14:11.97#ibcon#read 5, iclass 32, count 2 2006.211.08:14:11.97#ibcon#about to read 6, iclass 32, count 2 2006.211.08:14:11.97#ibcon#read 6, iclass 32, count 2 2006.211.08:14:11.97#ibcon#end of sib2, iclass 32, count 2 2006.211.08:14:11.97#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:14:11.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:14:11.97#ibcon#[27=AT06-03\r\n] 2006.211.08:14:11.97#ibcon#*before write, iclass 32, count 2 2006.211.08:14:11.97#ibcon#enter sib2, iclass 32, count 2 2006.211.08:14:11.97#ibcon#flushed, iclass 32, count 2 2006.211.08:14:11.97#ibcon#about to write, iclass 32, count 2 2006.211.08:14:11.97#ibcon#wrote, iclass 32, count 2 2006.211.08:14:11.97#ibcon#about to read 3, iclass 32, count 2 2006.211.08:14:12.00#ibcon#read 3, iclass 32, count 2 2006.211.08:14:12.00#ibcon#about to read 4, iclass 32, count 2 2006.211.08:14:12.00#ibcon#read 4, iclass 32, count 2 2006.211.08:14:12.00#ibcon#about to read 5, iclass 32, count 2 2006.211.08:14:12.00#ibcon#read 5, iclass 32, count 2 2006.211.08:14:12.00#ibcon#about to read 6, iclass 32, count 2 2006.211.08:14:12.00#ibcon#read 6, iclass 32, count 2 2006.211.08:14:12.00#ibcon#end of sib2, iclass 32, count 2 2006.211.08:14:12.00#ibcon#*after write, iclass 32, count 2 2006.211.08:14:12.00#ibcon#*before return 0, iclass 32, count 2 2006.211.08:14:12.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:12.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:14:12.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:14:12.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:14:12.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:12.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:12.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:12.12#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:14:12.12#ibcon#first serial, iclass 32, count 0 2006.211.08:14:12.12#ibcon#enter sib2, iclass 32, count 0 2006.211.08:14:12.12#ibcon#flushed, iclass 32, count 0 2006.211.08:14:12.12#ibcon#about to write, iclass 32, count 0 2006.211.08:14:12.12#ibcon#wrote, iclass 32, count 0 2006.211.08:14:12.12#ibcon#about to read 3, iclass 32, count 0 2006.211.08:14:12.14#ibcon#read 3, iclass 32, count 0 2006.211.08:14:12.14#ibcon#about to read 4, iclass 32, count 0 2006.211.08:14:12.14#ibcon#read 4, iclass 32, count 0 2006.211.08:14:12.14#ibcon#about to read 5, iclass 32, count 0 2006.211.08:14:12.14#ibcon#read 5, iclass 32, count 0 2006.211.08:14:12.14#ibcon#about to read 6, iclass 32, count 0 2006.211.08:14:12.14#ibcon#read 6, iclass 32, count 0 2006.211.08:14:12.14#ibcon#end of sib2, iclass 32, count 0 2006.211.08:14:12.14#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:14:12.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:14:12.14#ibcon#[27=USB\r\n] 2006.211.08:14:12.14#ibcon#*before write, iclass 32, count 0 2006.211.08:14:12.14#ibcon#enter sib2, iclass 32, count 0 2006.211.08:14:12.14#ibcon#flushed, iclass 32, count 0 2006.211.08:14:12.14#ibcon#about to write, iclass 32, count 0 2006.211.08:14:12.14#ibcon#wrote, iclass 32, count 0 2006.211.08:14:12.14#ibcon#about to read 3, iclass 32, count 0 2006.211.08:14:12.17#ibcon#read 3, iclass 32, count 0 2006.211.08:14:12.17#ibcon#about to read 4, iclass 32, count 0 2006.211.08:14:12.17#ibcon#read 4, iclass 32, count 0 2006.211.08:14:12.17#ibcon#about to read 5, iclass 32, count 0 2006.211.08:14:12.17#ibcon#read 5, iclass 32, count 0 2006.211.08:14:12.17#ibcon#about to read 6, iclass 32, count 0 2006.211.08:14:12.17#ibcon#read 6, iclass 32, count 0 2006.211.08:14:12.17#ibcon#end of sib2, iclass 32, count 0 2006.211.08:14:12.17#ibcon#*after write, iclass 32, count 0 2006.211.08:14:12.17#ibcon#*before return 0, iclass 32, count 0 2006.211.08:14:12.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:12.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:14:12.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:14:12.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:14:12.17$vc4f8/vabw=wide 2006.211.08:14:12.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:14:12.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:14:12.17#ibcon#ireg 8 cls_cnt 0 2006.211.08:14:12.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:12.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:12.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:12.17#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:14:12.17#ibcon#first serial, iclass 34, count 0 2006.211.08:14:12.17#ibcon#enter sib2, iclass 34, count 0 2006.211.08:14:12.17#ibcon#flushed, iclass 34, count 0 2006.211.08:14:12.17#ibcon#about to write, iclass 34, count 0 2006.211.08:14:12.17#ibcon#wrote, iclass 34, count 0 2006.211.08:14:12.17#ibcon#about to read 3, iclass 34, count 0 2006.211.08:14:12.19#ibcon#read 3, iclass 34, count 0 2006.211.08:14:12.19#ibcon#about to read 4, iclass 34, count 0 2006.211.08:14:12.19#ibcon#read 4, iclass 34, count 0 2006.211.08:14:12.19#ibcon#about to read 5, iclass 34, count 0 2006.211.08:14:12.19#ibcon#read 5, iclass 34, count 0 2006.211.08:14:12.19#ibcon#about to read 6, iclass 34, count 0 2006.211.08:14:12.19#ibcon#read 6, iclass 34, count 0 2006.211.08:14:12.19#ibcon#end of sib2, iclass 34, count 0 2006.211.08:14:12.19#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:14:12.19#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:14:12.19#ibcon#[25=BW32\r\n] 2006.211.08:14:12.19#ibcon#*before write, iclass 34, count 0 2006.211.08:14:12.19#ibcon#enter sib2, iclass 34, count 0 2006.211.08:14:12.19#ibcon#flushed, iclass 34, count 0 2006.211.08:14:12.19#ibcon#about to write, iclass 34, count 0 2006.211.08:14:12.19#ibcon#wrote, iclass 34, count 0 2006.211.08:14:12.19#ibcon#about to read 3, iclass 34, count 0 2006.211.08:14:12.22#ibcon#read 3, iclass 34, count 0 2006.211.08:14:12.22#ibcon#about to read 4, iclass 34, count 0 2006.211.08:14:12.22#ibcon#read 4, iclass 34, count 0 2006.211.08:14:12.22#ibcon#about to read 5, iclass 34, count 0 2006.211.08:14:12.22#ibcon#read 5, iclass 34, count 0 2006.211.08:14:12.22#ibcon#about to read 6, iclass 34, count 0 2006.211.08:14:12.22#ibcon#read 6, iclass 34, count 0 2006.211.08:14:12.22#ibcon#end of sib2, iclass 34, count 0 2006.211.08:14:12.22#ibcon#*after write, iclass 34, count 0 2006.211.08:14:12.22#ibcon#*before return 0, iclass 34, count 0 2006.211.08:14:12.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:12.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:14:12.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:14:12.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:14:12.22$vc4f8/vbbw=wide 2006.211.08:14:12.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.211.08:14:12.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.211.08:14:12.22#ibcon#ireg 8 cls_cnt 0 2006.211.08:14:12.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:14:12.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:14:12.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:14:12.29#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:14:12.29#ibcon#first serial, iclass 36, count 0 2006.211.08:14:12.29#ibcon#enter sib2, iclass 36, count 0 2006.211.08:14:12.29#ibcon#flushed, iclass 36, count 0 2006.211.08:14:12.29#ibcon#about to write, iclass 36, count 0 2006.211.08:14:12.29#ibcon#wrote, iclass 36, count 0 2006.211.08:14:12.29#ibcon#about to read 3, iclass 36, count 0 2006.211.08:14:12.31#ibcon#read 3, iclass 36, count 0 2006.211.08:14:12.31#ibcon#about to read 4, iclass 36, count 0 2006.211.08:14:12.31#ibcon#read 4, iclass 36, count 0 2006.211.08:14:12.31#ibcon#about to read 5, iclass 36, count 0 2006.211.08:14:12.31#ibcon#read 5, iclass 36, count 0 2006.211.08:14:12.31#ibcon#about to read 6, iclass 36, count 0 2006.211.08:14:12.31#ibcon#read 6, iclass 36, count 0 2006.211.08:14:12.31#ibcon#end of sib2, iclass 36, count 0 2006.211.08:14:12.31#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:14:12.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:14:12.31#ibcon#[27=BW32\r\n] 2006.211.08:14:12.31#ibcon#*before write, iclass 36, count 0 2006.211.08:14:12.31#ibcon#enter sib2, iclass 36, count 0 2006.211.08:14:12.31#ibcon#flushed, iclass 36, count 0 2006.211.08:14:12.31#ibcon#about to write, iclass 36, count 0 2006.211.08:14:12.31#ibcon#wrote, iclass 36, count 0 2006.211.08:14:12.31#ibcon#about to read 3, iclass 36, count 0 2006.211.08:14:12.34#ibcon#read 3, iclass 36, count 0 2006.211.08:14:12.34#ibcon#about to read 4, iclass 36, count 0 2006.211.08:14:12.34#ibcon#read 4, iclass 36, count 0 2006.211.08:14:12.34#ibcon#about to read 5, iclass 36, count 0 2006.211.08:14:12.34#ibcon#read 5, iclass 36, count 0 2006.211.08:14:12.34#ibcon#about to read 6, iclass 36, count 0 2006.211.08:14:12.34#ibcon#read 6, iclass 36, count 0 2006.211.08:14:12.34#ibcon#end of sib2, iclass 36, count 0 2006.211.08:14:12.34#ibcon#*after write, iclass 36, count 0 2006.211.08:14:12.34#ibcon#*before return 0, iclass 36, count 0 2006.211.08:14:12.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:14:12.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.211.08:14:12.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:14:12.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:14:12.34$4f8m12a/ifd4f 2006.211.08:14:12.34$ifd4f/lo= 2006.211.08:14:12.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:14:12.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:14:12.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:14:12.34$ifd4f/patch= 2006.211.08:14:12.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:14:12.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:14:12.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:14:12.34$4f8m12a/"form=m,16.000,1:2 2006.211.08:14:12.34$4f8m12a/"tpicd 2006.211.08:14:12.34$4f8m12a/echo=off 2006.211.08:14:12.34$4f8m12a/xlog=off 2006.211.08:14:12.34:!2006.211.08:14:40 2006.211.08:14:24.14#trakl#Source acquired 2006.211.08:14:25.14#flagr#flagr/antenna,acquired 2006.211.08:14:40.00:preob 2006.211.08:14:41.14/onsource/TRACKING 2006.211.08:14:41.14:!2006.211.08:14:50 2006.211.08:14:50.00:data_valid=on 2006.211.08:14:50.00:midob 2006.211.08:14:50.14/onsource/TRACKING 2006.211.08:14:50.14/wx/24.51,1010.1,80 2006.211.08:14:50.25/cable/+6.4399E-03 2006.211.08:14:51.34/va/01,08,usb,yes,28,30 2006.211.08:14:51.34/va/02,07,usb,yes,28,30 2006.211.08:14:51.34/va/03,06,usb,yes,30,30 2006.211.08:14:51.34/va/04,07,usb,yes,29,31 2006.211.08:14:51.34/va/05,07,usb,yes,31,33 2006.211.08:14:51.34/va/06,06,usb,yes,30,30 2006.211.08:14:51.34/va/07,06,usb,yes,31,31 2006.211.08:14:51.34/va/08,07,usb,yes,29,29 2006.211.08:14:51.57/valo/01,532.99,yes,locked 2006.211.08:14:51.57/valo/02,572.99,yes,locked 2006.211.08:14:51.57/valo/03,672.99,yes,locked 2006.211.08:14:51.57/valo/04,832.99,yes,locked 2006.211.08:14:51.57/valo/05,652.99,yes,locked 2006.211.08:14:51.57/valo/06,772.99,yes,locked 2006.211.08:14:51.57/valo/07,832.99,yes,locked 2006.211.08:14:51.57/valo/08,852.99,yes,locked 2006.211.08:14:52.66/vb/01,04,usb,yes,28,27 2006.211.08:14:52.66/vb/02,04,usb,yes,30,31 2006.211.08:14:52.66/vb/03,03,usb,yes,33,37 2006.211.08:14:52.66/vb/04,03,usb,yes,34,34 2006.211.08:14:52.66/vb/05,03,usb,yes,32,37 2006.211.08:14:52.66/vb/06,03,usb,yes,33,36 2006.211.08:14:52.66/vb/07,04,usb,yes,29,29 2006.211.08:14:52.66/vb/08,03,usb,yes,33,37 2006.211.08:14:52.90/vblo/01,632.99,yes,locked 2006.211.08:14:52.90/vblo/02,640.99,yes,locked 2006.211.08:14:52.90/vblo/03,656.99,yes,locked 2006.211.08:14:52.90/vblo/04,712.99,yes,locked 2006.211.08:14:52.90/vblo/05,744.99,yes,locked 2006.211.08:14:52.90/vblo/06,752.99,yes,locked 2006.211.08:14:52.90/vblo/07,734.99,yes,locked 2006.211.08:14:52.90/vblo/08,744.99,yes,locked 2006.211.08:14:53.05/vabw/8 2006.211.08:14:53.20/vbbw/8 2006.211.08:14:53.33/xfe/off,on,12.0 2006.211.08:14:53.75/ifatt/23,28,28,28 2006.211.08:14:54.07/fmout-gps/S +4.45E-07 2006.211.08:14:54.11:!2006.211.08:15:50 2006.211.08:15:22.14#trakl#Off source 2006.211.08:15:22.14?ERROR st -7 Antenna off-source! 2006.211.08:15:22.14#trakl#az 339.714 el 46.374 azerr*cos(el) -0.0199 elerr -0.0038 2006.211.08:15:22.14#flagr#flagr/antenna,off-source 2006.211.08:15:28.14#trakl#Source re-acquired 2006.211.08:15:28.14#flagr#flagr/antenna,re-acquired 2006.211.08:15:29.14#trakl#Off source 2006.211.08:15:29.14?ERROR st -7 Antenna off-source! 2006.211.08:15:29.14#trakl#az 339.708 el 46.366 azerr*cos(el) -0.0005 elerr 0.0254 2006.211.08:15:31.14#flagr#flagr/antenna,off-source 2006.211.08:15:37.14#trakl#Source re-acquired 2006.211.08:15:37.14#flagr#flagr/antenna,re-acquired 2006.211.08:15:50.01:data_valid=off 2006.211.08:15:50.01:postob 2006.211.08:15:50.21/cable/+6.4384E-03 2006.211.08:15:50.21/wx/24.47,1010.1,80 2006.211.08:15:51.07/fmout-gps/S +4.44E-07 2006.211.08:15:51.07:scan_name=211-0816,k06211,60 2006.211.08:15:51.07:source=1803+784,180045.68,782804.0,2000.0,cw 2006.211.08:15:51.14#flagr#flagr/antenna,new-source 2006.211.08:15:52.14:checkk5 2006.211.08:15:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:15:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:15:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:15:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:15:53.84/chk_obsdata//k5ts1/T2110814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:15:54.18/chk_obsdata//k5ts2/T2110814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:15:54.51/chk_obsdata//k5ts3/T2110814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:15:54.84/chk_obsdata//k5ts4/T2110814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:15:55.51/k5log//k5ts1_log_newline 2006.211.08:15:56.18/k5log//k5ts2_log_newline 2006.211.08:15:56.84/k5log//k5ts3_log_newline 2006.211.08:15:57.50/k5log//k5ts4_log_newline 2006.211.08:15:57.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:15:57.52:4f8m12a=2 2006.211.08:15:57.52$4f8m12a/echo=on 2006.211.08:15:57.52$4f8m12a/pcalon 2006.211.08:15:57.52$pcalon/"no phase cal control is implemented here 2006.211.08:15:57.52$4f8m12a/"tpicd=stop 2006.211.08:15:57.52$4f8m12a/vc4f8 2006.211.08:15:57.52$vc4f8/valo=1,532.99 2006.211.08:15:57.53#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.08:15:57.53#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.08:15:57.53#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:57.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:15:57.53#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:15:57.53#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:15:57.53#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:15:57.53#ibcon#first serial, iclass 15, count 0 2006.211.08:15:57.53#ibcon#enter sib2, iclass 15, count 0 2006.211.08:15:57.53#ibcon#flushed, iclass 15, count 0 2006.211.08:15:57.53#ibcon#about to write, iclass 15, count 0 2006.211.08:15:57.53#ibcon#wrote, iclass 15, count 0 2006.211.08:15:57.53#ibcon#about to read 3, iclass 15, count 0 2006.211.08:15:57.54#ibcon#read 3, iclass 15, count 0 2006.211.08:15:57.54#ibcon#about to read 4, iclass 15, count 0 2006.211.08:15:57.54#ibcon#read 4, iclass 15, count 0 2006.211.08:15:57.54#ibcon#about to read 5, iclass 15, count 0 2006.211.08:15:57.54#ibcon#read 5, iclass 15, count 0 2006.211.08:15:57.54#ibcon#about to read 6, iclass 15, count 0 2006.211.08:15:57.54#ibcon#read 6, iclass 15, count 0 2006.211.08:15:57.54#ibcon#end of sib2, iclass 15, count 0 2006.211.08:15:57.54#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:15:57.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:15:57.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:15:57.54#ibcon#*before write, iclass 15, count 0 2006.211.08:15:57.54#ibcon#enter sib2, iclass 15, count 0 2006.211.08:15:57.54#ibcon#flushed, iclass 15, count 0 2006.211.08:15:57.54#ibcon#about to write, iclass 15, count 0 2006.211.08:15:57.54#ibcon#wrote, iclass 15, count 0 2006.211.08:15:57.54#ibcon#about to read 3, iclass 15, count 0 2006.211.08:15:57.59#ibcon#read 3, iclass 15, count 0 2006.211.08:15:57.59#ibcon#about to read 4, iclass 15, count 0 2006.211.08:15:57.59#ibcon#read 4, iclass 15, count 0 2006.211.08:15:57.59#ibcon#about to read 5, iclass 15, count 0 2006.211.08:15:57.59#ibcon#read 5, iclass 15, count 0 2006.211.08:15:57.59#ibcon#about to read 6, iclass 15, count 0 2006.211.08:15:57.59#ibcon#read 6, iclass 15, count 0 2006.211.08:15:57.59#ibcon#end of sib2, iclass 15, count 0 2006.211.08:15:57.59#ibcon#*after write, iclass 15, count 0 2006.211.08:15:57.59#ibcon#*before return 0, iclass 15, count 0 2006.211.08:15:57.59#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:15:57.59#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:15:57.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:15:57.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:15:57.59$vc4f8/va=1,8 2006.211.08:15:57.59#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.08:15:57.59#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.08:15:57.59#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:57.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:15:57.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:15:57.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:15:57.59#ibcon#enter wrdev, iclass 17, count 2 2006.211.08:15:57.59#ibcon#first serial, iclass 17, count 2 2006.211.08:15:57.59#ibcon#enter sib2, iclass 17, count 2 2006.211.08:15:57.59#ibcon#flushed, iclass 17, count 2 2006.211.08:15:57.59#ibcon#about to write, iclass 17, count 2 2006.211.08:15:57.59#ibcon#wrote, iclass 17, count 2 2006.211.08:15:57.59#ibcon#about to read 3, iclass 17, count 2 2006.211.08:15:57.61#ibcon#read 3, iclass 17, count 2 2006.211.08:15:57.61#ibcon#about to read 4, iclass 17, count 2 2006.211.08:15:57.61#ibcon#read 4, iclass 17, count 2 2006.211.08:15:57.61#ibcon#about to read 5, iclass 17, count 2 2006.211.08:15:57.61#ibcon#read 5, iclass 17, count 2 2006.211.08:15:57.61#ibcon#about to read 6, iclass 17, count 2 2006.211.08:15:57.61#ibcon#read 6, iclass 17, count 2 2006.211.08:15:57.61#ibcon#end of sib2, iclass 17, count 2 2006.211.08:15:57.61#ibcon#*mode == 0, iclass 17, count 2 2006.211.08:15:57.61#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.08:15:57.61#ibcon#[25=AT01-08\r\n] 2006.211.08:15:57.61#ibcon#*before write, iclass 17, count 2 2006.211.08:15:57.61#ibcon#enter sib2, iclass 17, count 2 2006.211.08:15:57.61#ibcon#flushed, iclass 17, count 2 2006.211.08:15:57.61#ibcon#about to write, iclass 17, count 2 2006.211.08:15:57.61#ibcon#wrote, iclass 17, count 2 2006.211.08:15:57.61#ibcon#about to read 3, iclass 17, count 2 2006.211.08:15:57.64#ibcon#read 3, iclass 17, count 2 2006.211.08:15:57.64#ibcon#about to read 4, iclass 17, count 2 2006.211.08:15:57.64#ibcon#read 4, iclass 17, count 2 2006.211.08:15:57.64#ibcon#about to read 5, iclass 17, count 2 2006.211.08:15:57.64#ibcon#read 5, iclass 17, count 2 2006.211.08:15:57.64#ibcon#about to read 6, iclass 17, count 2 2006.211.08:15:57.64#ibcon#read 6, iclass 17, count 2 2006.211.08:15:57.64#ibcon#end of sib2, iclass 17, count 2 2006.211.08:15:57.64#ibcon#*after write, iclass 17, count 2 2006.211.08:15:57.64#ibcon#*before return 0, iclass 17, count 2 2006.211.08:15:57.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:15:57.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:15:57.64#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.08:15:57.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:57.64#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:15:57.76#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:15:57.76#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:15:57.76#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:15:57.76#ibcon#first serial, iclass 17, count 0 2006.211.08:15:57.76#ibcon#enter sib2, iclass 17, count 0 2006.211.08:15:57.76#ibcon#flushed, iclass 17, count 0 2006.211.08:15:57.76#ibcon#about to write, iclass 17, count 0 2006.211.08:15:57.76#ibcon#wrote, iclass 17, count 0 2006.211.08:15:57.76#ibcon#about to read 3, iclass 17, count 0 2006.211.08:15:57.78#ibcon#read 3, iclass 17, count 0 2006.211.08:15:57.78#ibcon#about to read 4, iclass 17, count 0 2006.211.08:15:57.78#ibcon#read 4, iclass 17, count 0 2006.211.08:15:57.78#ibcon#about to read 5, iclass 17, count 0 2006.211.08:15:57.78#ibcon#read 5, iclass 17, count 0 2006.211.08:15:57.78#ibcon#about to read 6, iclass 17, count 0 2006.211.08:15:57.78#ibcon#read 6, iclass 17, count 0 2006.211.08:15:57.78#ibcon#end of sib2, iclass 17, count 0 2006.211.08:15:57.78#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:15:57.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:15:57.78#ibcon#[25=USB\r\n] 2006.211.08:15:57.78#ibcon#*before write, iclass 17, count 0 2006.211.08:15:57.78#ibcon#enter sib2, iclass 17, count 0 2006.211.08:15:57.78#ibcon#flushed, iclass 17, count 0 2006.211.08:15:57.78#ibcon#about to write, iclass 17, count 0 2006.211.08:15:57.78#ibcon#wrote, iclass 17, count 0 2006.211.08:15:57.78#ibcon#about to read 3, iclass 17, count 0 2006.211.08:15:57.81#ibcon#read 3, iclass 17, count 0 2006.211.08:15:57.81#ibcon#about to read 4, iclass 17, count 0 2006.211.08:15:57.81#ibcon#read 4, iclass 17, count 0 2006.211.08:15:57.81#ibcon#about to read 5, iclass 17, count 0 2006.211.08:15:57.81#ibcon#read 5, iclass 17, count 0 2006.211.08:15:57.81#ibcon#about to read 6, iclass 17, count 0 2006.211.08:15:57.81#ibcon#read 6, iclass 17, count 0 2006.211.08:15:57.81#ibcon#end of sib2, iclass 17, count 0 2006.211.08:15:57.81#ibcon#*after write, iclass 17, count 0 2006.211.08:15:57.81#ibcon#*before return 0, iclass 17, count 0 2006.211.08:15:57.81#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:15:57.81#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:15:57.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:15:57.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:15:57.81$vc4f8/valo=2,572.99 2006.211.08:15:57.81#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.08:15:57.81#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.08:15:57.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:57.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:15:57.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:15:57.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:15:57.81#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:15:57.81#ibcon#first serial, iclass 19, count 0 2006.211.08:15:57.81#ibcon#enter sib2, iclass 19, count 0 2006.211.08:15:57.81#ibcon#flushed, iclass 19, count 0 2006.211.08:15:57.81#ibcon#about to write, iclass 19, count 0 2006.211.08:15:57.81#ibcon#wrote, iclass 19, count 0 2006.211.08:15:57.81#ibcon#about to read 3, iclass 19, count 0 2006.211.08:15:57.83#ibcon#read 3, iclass 19, count 0 2006.211.08:15:57.83#ibcon#about to read 4, iclass 19, count 0 2006.211.08:15:57.83#ibcon#read 4, iclass 19, count 0 2006.211.08:15:57.83#ibcon#about to read 5, iclass 19, count 0 2006.211.08:15:57.83#ibcon#read 5, iclass 19, count 0 2006.211.08:15:57.83#ibcon#about to read 6, iclass 19, count 0 2006.211.08:15:57.83#ibcon#read 6, iclass 19, count 0 2006.211.08:15:57.83#ibcon#end of sib2, iclass 19, count 0 2006.211.08:15:57.83#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:15:57.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:15:57.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:15:57.83#ibcon#*before write, iclass 19, count 0 2006.211.08:15:57.83#ibcon#enter sib2, iclass 19, count 0 2006.211.08:15:57.83#ibcon#flushed, iclass 19, count 0 2006.211.08:15:57.83#ibcon#about to write, iclass 19, count 0 2006.211.08:15:57.83#ibcon#wrote, iclass 19, count 0 2006.211.08:15:57.83#ibcon#about to read 3, iclass 19, count 0 2006.211.08:15:57.87#ibcon#read 3, iclass 19, count 0 2006.211.08:15:57.87#ibcon#about to read 4, iclass 19, count 0 2006.211.08:15:57.87#ibcon#read 4, iclass 19, count 0 2006.211.08:15:57.87#ibcon#about to read 5, iclass 19, count 0 2006.211.08:15:57.87#ibcon#read 5, iclass 19, count 0 2006.211.08:15:57.87#ibcon#about to read 6, iclass 19, count 0 2006.211.08:15:57.87#ibcon#read 6, iclass 19, count 0 2006.211.08:15:57.87#ibcon#end of sib2, iclass 19, count 0 2006.211.08:15:57.87#ibcon#*after write, iclass 19, count 0 2006.211.08:15:57.87#ibcon#*before return 0, iclass 19, count 0 2006.211.08:15:57.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:15:57.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:15:57.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:15:57.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:15:57.87$vc4f8/va=2,7 2006.211.08:15:57.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.08:15:57.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.08:15:57.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:57.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:15:57.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:15:57.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:15:57.93#ibcon#enter wrdev, iclass 21, count 2 2006.211.08:15:57.93#ibcon#first serial, iclass 21, count 2 2006.211.08:15:57.93#ibcon#enter sib2, iclass 21, count 2 2006.211.08:15:57.93#ibcon#flushed, iclass 21, count 2 2006.211.08:15:57.93#ibcon#about to write, iclass 21, count 2 2006.211.08:15:57.93#ibcon#wrote, iclass 21, count 2 2006.211.08:15:57.93#ibcon#about to read 3, iclass 21, count 2 2006.211.08:15:57.95#ibcon#read 3, iclass 21, count 2 2006.211.08:15:57.95#ibcon#about to read 4, iclass 21, count 2 2006.211.08:15:57.95#ibcon#read 4, iclass 21, count 2 2006.211.08:15:57.95#ibcon#about to read 5, iclass 21, count 2 2006.211.08:15:57.95#ibcon#read 5, iclass 21, count 2 2006.211.08:15:57.95#ibcon#about to read 6, iclass 21, count 2 2006.211.08:15:57.95#ibcon#read 6, iclass 21, count 2 2006.211.08:15:57.95#ibcon#end of sib2, iclass 21, count 2 2006.211.08:15:57.95#ibcon#*mode == 0, iclass 21, count 2 2006.211.08:15:57.95#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.08:15:57.95#ibcon#[25=AT02-07\r\n] 2006.211.08:15:57.95#ibcon#*before write, iclass 21, count 2 2006.211.08:15:57.95#ibcon#enter sib2, iclass 21, count 2 2006.211.08:15:57.95#ibcon#flushed, iclass 21, count 2 2006.211.08:15:57.95#ibcon#about to write, iclass 21, count 2 2006.211.08:15:57.95#ibcon#wrote, iclass 21, count 2 2006.211.08:15:57.95#ibcon#about to read 3, iclass 21, count 2 2006.211.08:15:57.98#ibcon#read 3, iclass 21, count 2 2006.211.08:15:57.98#ibcon#about to read 4, iclass 21, count 2 2006.211.08:15:57.98#ibcon#read 4, iclass 21, count 2 2006.211.08:15:57.98#ibcon#about to read 5, iclass 21, count 2 2006.211.08:15:57.98#ibcon#read 5, iclass 21, count 2 2006.211.08:15:57.98#ibcon#about to read 6, iclass 21, count 2 2006.211.08:15:57.98#ibcon#read 6, iclass 21, count 2 2006.211.08:15:57.98#ibcon#end of sib2, iclass 21, count 2 2006.211.08:15:57.98#ibcon#*after write, iclass 21, count 2 2006.211.08:15:57.98#ibcon#*before return 0, iclass 21, count 2 2006.211.08:15:57.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:15:57.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:15:57.98#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.08:15:57.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:57.98#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:15:58.10#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:15:58.10#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:15:58.10#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:15:58.10#ibcon#first serial, iclass 21, count 0 2006.211.08:15:58.10#ibcon#enter sib2, iclass 21, count 0 2006.211.08:15:58.10#ibcon#flushed, iclass 21, count 0 2006.211.08:15:58.10#ibcon#about to write, iclass 21, count 0 2006.211.08:15:58.10#ibcon#wrote, iclass 21, count 0 2006.211.08:15:58.10#ibcon#about to read 3, iclass 21, count 0 2006.211.08:15:58.12#ibcon#read 3, iclass 21, count 0 2006.211.08:15:58.12#ibcon#about to read 4, iclass 21, count 0 2006.211.08:15:58.12#ibcon#read 4, iclass 21, count 0 2006.211.08:15:58.12#ibcon#about to read 5, iclass 21, count 0 2006.211.08:15:58.12#ibcon#read 5, iclass 21, count 0 2006.211.08:15:58.12#ibcon#about to read 6, iclass 21, count 0 2006.211.08:15:58.12#ibcon#read 6, iclass 21, count 0 2006.211.08:15:58.12#ibcon#end of sib2, iclass 21, count 0 2006.211.08:15:58.12#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:15:58.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:15:58.12#ibcon#[25=USB\r\n] 2006.211.08:15:58.12#ibcon#*before write, iclass 21, count 0 2006.211.08:15:58.12#ibcon#enter sib2, iclass 21, count 0 2006.211.08:15:58.12#ibcon#flushed, iclass 21, count 0 2006.211.08:15:58.12#ibcon#about to write, iclass 21, count 0 2006.211.08:15:58.12#ibcon#wrote, iclass 21, count 0 2006.211.08:15:58.12#ibcon#about to read 3, iclass 21, count 0 2006.211.08:15:58.15#ibcon#read 3, iclass 21, count 0 2006.211.08:15:58.15#ibcon#about to read 4, iclass 21, count 0 2006.211.08:15:58.15#ibcon#read 4, iclass 21, count 0 2006.211.08:15:58.15#ibcon#about to read 5, iclass 21, count 0 2006.211.08:15:58.15#ibcon#read 5, iclass 21, count 0 2006.211.08:15:58.15#ibcon#about to read 6, iclass 21, count 0 2006.211.08:15:58.15#ibcon#read 6, iclass 21, count 0 2006.211.08:15:58.15#ibcon#end of sib2, iclass 21, count 0 2006.211.08:15:58.15#ibcon#*after write, iclass 21, count 0 2006.211.08:15:58.15#ibcon#*before return 0, iclass 21, count 0 2006.211.08:15:58.15#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:15:58.15#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:15:58.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:15:58.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:15:58.15$vc4f8/valo=3,672.99 2006.211.08:15:58.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.08:15:58.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.08:15:58.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:58.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:15:58.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:15:58.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:15:58.15#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:15:58.15#ibcon#first serial, iclass 23, count 0 2006.211.08:15:58.15#ibcon#enter sib2, iclass 23, count 0 2006.211.08:15:58.15#ibcon#flushed, iclass 23, count 0 2006.211.08:15:58.15#ibcon#about to write, iclass 23, count 0 2006.211.08:15:58.15#ibcon#wrote, iclass 23, count 0 2006.211.08:15:58.15#ibcon#about to read 3, iclass 23, count 0 2006.211.08:15:58.17#ibcon#read 3, iclass 23, count 0 2006.211.08:15:58.17#ibcon#about to read 4, iclass 23, count 0 2006.211.08:15:58.17#ibcon#read 4, iclass 23, count 0 2006.211.08:15:58.17#ibcon#about to read 5, iclass 23, count 0 2006.211.08:15:58.17#ibcon#read 5, iclass 23, count 0 2006.211.08:15:58.17#ibcon#about to read 6, iclass 23, count 0 2006.211.08:15:58.17#ibcon#read 6, iclass 23, count 0 2006.211.08:15:58.17#ibcon#end of sib2, iclass 23, count 0 2006.211.08:15:58.17#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:15:58.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:15:58.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:15:58.17#ibcon#*before write, iclass 23, count 0 2006.211.08:15:58.17#ibcon#enter sib2, iclass 23, count 0 2006.211.08:15:58.17#ibcon#flushed, iclass 23, count 0 2006.211.08:15:58.17#ibcon#about to write, iclass 23, count 0 2006.211.08:15:58.17#ibcon#wrote, iclass 23, count 0 2006.211.08:15:58.17#ibcon#about to read 3, iclass 23, count 0 2006.211.08:15:58.21#ibcon#read 3, iclass 23, count 0 2006.211.08:15:58.21#ibcon#about to read 4, iclass 23, count 0 2006.211.08:15:58.21#ibcon#read 4, iclass 23, count 0 2006.211.08:15:58.21#ibcon#about to read 5, iclass 23, count 0 2006.211.08:15:58.21#ibcon#read 5, iclass 23, count 0 2006.211.08:15:58.21#ibcon#about to read 6, iclass 23, count 0 2006.211.08:15:58.21#ibcon#read 6, iclass 23, count 0 2006.211.08:15:58.21#ibcon#end of sib2, iclass 23, count 0 2006.211.08:15:58.21#ibcon#*after write, iclass 23, count 0 2006.211.08:15:58.21#ibcon#*before return 0, iclass 23, count 0 2006.211.08:15:58.21#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:15:58.21#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:15:58.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:15:58.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:15:58.21$vc4f8/va=3,6 2006.211.08:15:58.21#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.08:15:58.21#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.08:15:58.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:58.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:15:58.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:15:58.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:15:58.27#ibcon#enter wrdev, iclass 25, count 2 2006.211.08:15:58.27#ibcon#first serial, iclass 25, count 2 2006.211.08:15:58.27#ibcon#enter sib2, iclass 25, count 2 2006.211.08:15:58.27#ibcon#flushed, iclass 25, count 2 2006.211.08:15:58.27#ibcon#about to write, iclass 25, count 2 2006.211.08:15:58.27#ibcon#wrote, iclass 25, count 2 2006.211.08:15:58.27#ibcon#about to read 3, iclass 25, count 2 2006.211.08:15:58.29#ibcon#read 3, iclass 25, count 2 2006.211.08:15:58.29#ibcon#about to read 4, iclass 25, count 2 2006.211.08:15:58.29#ibcon#read 4, iclass 25, count 2 2006.211.08:15:58.29#ibcon#about to read 5, iclass 25, count 2 2006.211.08:15:58.29#ibcon#read 5, iclass 25, count 2 2006.211.08:15:58.29#ibcon#about to read 6, iclass 25, count 2 2006.211.08:15:58.29#ibcon#read 6, iclass 25, count 2 2006.211.08:15:58.29#ibcon#end of sib2, iclass 25, count 2 2006.211.08:15:58.29#ibcon#*mode == 0, iclass 25, count 2 2006.211.08:15:58.29#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.08:15:58.29#ibcon#[25=AT03-06\r\n] 2006.211.08:15:58.29#ibcon#*before write, iclass 25, count 2 2006.211.08:15:58.29#ibcon#enter sib2, iclass 25, count 2 2006.211.08:15:58.29#ibcon#flushed, iclass 25, count 2 2006.211.08:15:58.29#ibcon#about to write, iclass 25, count 2 2006.211.08:15:58.29#ibcon#wrote, iclass 25, count 2 2006.211.08:15:58.29#ibcon#about to read 3, iclass 25, count 2 2006.211.08:15:58.32#ibcon#read 3, iclass 25, count 2 2006.211.08:15:58.32#ibcon#about to read 4, iclass 25, count 2 2006.211.08:15:58.32#ibcon#read 4, iclass 25, count 2 2006.211.08:15:58.32#ibcon#about to read 5, iclass 25, count 2 2006.211.08:15:58.32#ibcon#read 5, iclass 25, count 2 2006.211.08:15:58.32#ibcon#about to read 6, iclass 25, count 2 2006.211.08:15:58.32#ibcon#read 6, iclass 25, count 2 2006.211.08:15:58.32#ibcon#end of sib2, iclass 25, count 2 2006.211.08:15:58.32#ibcon#*after write, iclass 25, count 2 2006.211.08:15:58.32#ibcon#*before return 0, iclass 25, count 2 2006.211.08:15:58.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:15:58.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:15:58.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.08:15:58.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:58.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:15:58.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:15:58.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:15:58.44#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:15:58.44#ibcon#first serial, iclass 25, count 0 2006.211.08:15:58.44#ibcon#enter sib2, iclass 25, count 0 2006.211.08:15:58.44#ibcon#flushed, iclass 25, count 0 2006.211.08:15:58.44#ibcon#about to write, iclass 25, count 0 2006.211.08:15:58.44#ibcon#wrote, iclass 25, count 0 2006.211.08:15:58.44#ibcon#about to read 3, iclass 25, count 0 2006.211.08:15:58.46#ibcon#read 3, iclass 25, count 0 2006.211.08:15:58.46#ibcon#about to read 4, iclass 25, count 0 2006.211.08:15:58.46#ibcon#read 4, iclass 25, count 0 2006.211.08:15:58.46#ibcon#about to read 5, iclass 25, count 0 2006.211.08:15:58.46#ibcon#read 5, iclass 25, count 0 2006.211.08:15:58.46#ibcon#about to read 6, iclass 25, count 0 2006.211.08:15:58.46#ibcon#read 6, iclass 25, count 0 2006.211.08:15:58.46#ibcon#end of sib2, iclass 25, count 0 2006.211.08:15:58.46#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:15:58.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:15:58.46#ibcon#[25=USB\r\n] 2006.211.08:15:58.46#ibcon#*before write, iclass 25, count 0 2006.211.08:15:58.46#ibcon#enter sib2, iclass 25, count 0 2006.211.08:15:58.46#ibcon#flushed, iclass 25, count 0 2006.211.08:15:58.46#ibcon#about to write, iclass 25, count 0 2006.211.08:15:58.46#ibcon#wrote, iclass 25, count 0 2006.211.08:15:58.46#ibcon#about to read 3, iclass 25, count 0 2006.211.08:15:58.49#ibcon#read 3, iclass 25, count 0 2006.211.08:15:58.49#ibcon#about to read 4, iclass 25, count 0 2006.211.08:15:58.49#ibcon#read 4, iclass 25, count 0 2006.211.08:15:58.49#ibcon#about to read 5, iclass 25, count 0 2006.211.08:15:58.49#ibcon#read 5, iclass 25, count 0 2006.211.08:15:58.49#ibcon#about to read 6, iclass 25, count 0 2006.211.08:15:58.49#ibcon#read 6, iclass 25, count 0 2006.211.08:15:58.49#ibcon#end of sib2, iclass 25, count 0 2006.211.08:15:58.49#ibcon#*after write, iclass 25, count 0 2006.211.08:15:58.49#ibcon#*before return 0, iclass 25, count 0 2006.211.08:15:58.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:15:58.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:15:58.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:15:58.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:15:58.49$vc4f8/valo=4,832.99 2006.211.08:15:58.49#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.08:15:58.49#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.08:15:58.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:58.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:15:58.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:15:58.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:15:58.49#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:15:58.49#ibcon#first serial, iclass 27, count 0 2006.211.08:15:58.49#ibcon#enter sib2, iclass 27, count 0 2006.211.08:15:58.49#ibcon#flushed, iclass 27, count 0 2006.211.08:15:58.49#ibcon#about to write, iclass 27, count 0 2006.211.08:15:58.49#ibcon#wrote, iclass 27, count 0 2006.211.08:15:58.49#ibcon#about to read 3, iclass 27, count 0 2006.211.08:15:58.51#ibcon#read 3, iclass 27, count 0 2006.211.08:15:58.51#ibcon#about to read 4, iclass 27, count 0 2006.211.08:15:58.51#ibcon#read 4, iclass 27, count 0 2006.211.08:15:58.51#ibcon#about to read 5, iclass 27, count 0 2006.211.08:15:58.51#ibcon#read 5, iclass 27, count 0 2006.211.08:15:58.51#ibcon#about to read 6, iclass 27, count 0 2006.211.08:15:58.51#ibcon#read 6, iclass 27, count 0 2006.211.08:15:58.51#ibcon#end of sib2, iclass 27, count 0 2006.211.08:15:58.51#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:15:58.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:15:58.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:15:58.51#ibcon#*before write, iclass 27, count 0 2006.211.08:15:58.51#ibcon#enter sib2, iclass 27, count 0 2006.211.08:15:58.51#ibcon#flushed, iclass 27, count 0 2006.211.08:15:58.51#ibcon#about to write, iclass 27, count 0 2006.211.08:15:58.51#ibcon#wrote, iclass 27, count 0 2006.211.08:15:58.51#ibcon#about to read 3, iclass 27, count 0 2006.211.08:15:58.55#ibcon#read 3, iclass 27, count 0 2006.211.08:15:58.55#ibcon#about to read 4, iclass 27, count 0 2006.211.08:15:58.55#ibcon#read 4, iclass 27, count 0 2006.211.08:15:58.55#ibcon#about to read 5, iclass 27, count 0 2006.211.08:15:58.55#ibcon#read 5, iclass 27, count 0 2006.211.08:15:58.55#ibcon#about to read 6, iclass 27, count 0 2006.211.08:15:58.55#ibcon#read 6, iclass 27, count 0 2006.211.08:15:58.55#ibcon#end of sib2, iclass 27, count 0 2006.211.08:15:58.55#ibcon#*after write, iclass 27, count 0 2006.211.08:15:58.55#ibcon#*before return 0, iclass 27, count 0 2006.211.08:15:58.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:15:58.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:15:58.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:15:58.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:15:58.55$vc4f8/va=4,7 2006.211.08:15:58.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.08:15:58.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.08:15:58.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:58.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:15:58.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:15:58.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:15:58.61#ibcon#enter wrdev, iclass 29, count 2 2006.211.08:15:58.61#ibcon#first serial, iclass 29, count 2 2006.211.08:15:58.61#ibcon#enter sib2, iclass 29, count 2 2006.211.08:15:58.61#ibcon#flushed, iclass 29, count 2 2006.211.08:15:58.61#ibcon#about to write, iclass 29, count 2 2006.211.08:15:58.61#ibcon#wrote, iclass 29, count 2 2006.211.08:15:58.61#ibcon#about to read 3, iclass 29, count 2 2006.211.08:15:58.63#ibcon#read 3, iclass 29, count 2 2006.211.08:15:58.63#ibcon#about to read 4, iclass 29, count 2 2006.211.08:15:58.63#ibcon#read 4, iclass 29, count 2 2006.211.08:15:58.63#ibcon#about to read 5, iclass 29, count 2 2006.211.08:15:58.63#ibcon#read 5, iclass 29, count 2 2006.211.08:15:58.63#ibcon#about to read 6, iclass 29, count 2 2006.211.08:15:58.63#ibcon#read 6, iclass 29, count 2 2006.211.08:15:58.63#ibcon#end of sib2, iclass 29, count 2 2006.211.08:15:58.63#ibcon#*mode == 0, iclass 29, count 2 2006.211.08:15:58.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.08:15:58.63#ibcon#[25=AT04-07\r\n] 2006.211.08:15:58.63#ibcon#*before write, iclass 29, count 2 2006.211.08:15:58.63#ibcon#enter sib2, iclass 29, count 2 2006.211.08:15:58.63#ibcon#flushed, iclass 29, count 2 2006.211.08:15:58.63#ibcon#about to write, iclass 29, count 2 2006.211.08:15:58.63#ibcon#wrote, iclass 29, count 2 2006.211.08:15:58.63#ibcon#about to read 3, iclass 29, count 2 2006.211.08:15:58.66#ibcon#read 3, iclass 29, count 2 2006.211.08:15:58.66#ibcon#about to read 4, iclass 29, count 2 2006.211.08:15:58.66#ibcon#read 4, iclass 29, count 2 2006.211.08:15:58.66#ibcon#about to read 5, iclass 29, count 2 2006.211.08:15:58.66#ibcon#read 5, iclass 29, count 2 2006.211.08:15:58.66#ibcon#about to read 6, iclass 29, count 2 2006.211.08:15:58.66#ibcon#read 6, iclass 29, count 2 2006.211.08:15:58.66#ibcon#end of sib2, iclass 29, count 2 2006.211.08:15:58.66#ibcon#*after write, iclass 29, count 2 2006.211.08:15:58.66#ibcon#*before return 0, iclass 29, count 2 2006.211.08:15:58.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:15:58.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:15:58.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.08:15:58.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:58.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:15:58.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:15:58.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:15:58.78#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:15:58.78#ibcon#first serial, iclass 29, count 0 2006.211.08:15:58.78#ibcon#enter sib2, iclass 29, count 0 2006.211.08:15:58.78#ibcon#flushed, iclass 29, count 0 2006.211.08:15:58.78#ibcon#about to write, iclass 29, count 0 2006.211.08:15:58.78#ibcon#wrote, iclass 29, count 0 2006.211.08:15:58.78#ibcon#about to read 3, iclass 29, count 0 2006.211.08:15:58.80#ibcon#read 3, iclass 29, count 0 2006.211.08:15:58.80#ibcon#about to read 4, iclass 29, count 0 2006.211.08:15:58.80#ibcon#read 4, iclass 29, count 0 2006.211.08:15:58.80#ibcon#about to read 5, iclass 29, count 0 2006.211.08:15:58.80#ibcon#read 5, iclass 29, count 0 2006.211.08:15:58.80#ibcon#about to read 6, iclass 29, count 0 2006.211.08:15:58.80#ibcon#read 6, iclass 29, count 0 2006.211.08:15:58.80#ibcon#end of sib2, iclass 29, count 0 2006.211.08:15:58.80#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:15:58.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:15:58.80#ibcon#[25=USB\r\n] 2006.211.08:15:58.80#ibcon#*before write, iclass 29, count 0 2006.211.08:15:58.80#ibcon#enter sib2, iclass 29, count 0 2006.211.08:15:58.80#ibcon#flushed, iclass 29, count 0 2006.211.08:15:58.80#ibcon#about to write, iclass 29, count 0 2006.211.08:15:58.80#ibcon#wrote, iclass 29, count 0 2006.211.08:15:58.80#ibcon#about to read 3, iclass 29, count 0 2006.211.08:15:58.83#ibcon#read 3, iclass 29, count 0 2006.211.08:15:58.83#ibcon#about to read 4, iclass 29, count 0 2006.211.08:15:58.83#ibcon#read 4, iclass 29, count 0 2006.211.08:15:58.83#ibcon#about to read 5, iclass 29, count 0 2006.211.08:15:58.83#ibcon#read 5, iclass 29, count 0 2006.211.08:15:58.83#ibcon#about to read 6, iclass 29, count 0 2006.211.08:15:58.83#ibcon#read 6, iclass 29, count 0 2006.211.08:15:58.83#ibcon#end of sib2, iclass 29, count 0 2006.211.08:15:58.83#ibcon#*after write, iclass 29, count 0 2006.211.08:15:58.83#ibcon#*before return 0, iclass 29, count 0 2006.211.08:15:58.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:15:58.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:15:58.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:15:58.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:15:58.83$vc4f8/valo=5,652.99 2006.211.08:15:58.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.08:15:58.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.08:15:58.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:58.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:15:58.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:15:58.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:15:58.83#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:15:58.83#ibcon#first serial, iclass 31, count 0 2006.211.08:15:58.83#ibcon#enter sib2, iclass 31, count 0 2006.211.08:15:58.83#ibcon#flushed, iclass 31, count 0 2006.211.08:15:58.83#ibcon#about to write, iclass 31, count 0 2006.211.08:15:58.83#ibcon#wrote, iclass 31, count 0 2006.211.08:15:58.83#ibcon#about to read 3, iclass 31, count 0 2006.211.08:15:58.85#ibcon#read 3, iclass 31, count 0 2006.211.08:15:58.85#ibcon#about to read 4, iclass 31, count 0 2006.211.08:15:58.85#ibcon#read 4, iclass 31, count 0 2006.211.08:15:58.85#ibcon#about to read 5, iclass 31, count 0 2006.211.08:15:58.85#ibcon#read 5, iclass 31, count 0 2006.211.08:15:58.85#ibcon#about to read 6, iclass 31, count 0 2006.211.08:15:58.85#ibcon#read 6, iclass 31, count 0 2006.211.08:15:58.85#ibcon#end of sib2, iclass 31, count 0 2006.211.08:15:58.85#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:15:58.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:15:58.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:15:58.85#ibcon#*before write, iclass 31, count 0 2006.211.08:15:58.85#ibcon#enter sib2, iclass 31, count 0 2006.211.08:15:58.85#ibcon#flushed, iclass 31, count 0 2006.211.08:15:58.85#ibcon#about to write, iclass 31, count 0 2006.211.08:15:58.85#ibcon#wrote, iclass 31, count 0 2006.211.08:15:58.85#ibcon#about to read 3, iclass 31, count 0 2006.211.08:15:58.89#ibcon#read 3, iclass 31, count 0 2006.211.08:15:58.89#ibcon#about to read 4, iclass 31, count 0 2006.211.08:15:58.89#ibcon#read 4, iclass 31, count 0 2006.211.08:15:58.89#ibcon#about to read 5, iclass 31, count 0 2006.211.08:15:58.89#ibcon#read 5, iclass 31, count 0 2006.211.08:15:58.89#ibcon#about to read 6, iclass 31, count 0 2006.211.08:15:58.89#ibcon#read 6, iclass 31, count 0 2006.211.08:15:58.89#ibcon#end of sib2, iclass 31, count 0 2006.211.08:15:58.89#ibcon#*after write, iclass 31, count 0 2006.211.08:15:58.89#ibcon#*before return 0, iclass 31, count 0 2006.211.08:15:58.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:15:58.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:15:58.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:15:58.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:15:58.89$vc4f8/va=5,7 2006.211.08:15:58.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.08:15:58.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.08:15:58.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:58.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:15:58.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:15:58.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:15:58.95#ibcon#enter wrdev, iclass 33, count 2 2006.211.08:15:58.95#ibcon#first serial, iclass 33, count 2 2006.211.08:15:58.95#ibcon#enter sib2, iclass 33, count 2 2006.211.08:15:58.95#ibcon#flushed, iclass 33, count 2 2006.211.08:15:58.95#ibcon#about to write, iclass 33, count 2 2006.211.08:15:58.95#ibcon#wrote, iclass 33, count 2 2006.211.08:15:58.95#ibcon#about to read 3, iclass 33, count 2 2006.211.08:15:58.97#ibcon#read 3, iclass 33, count 2 2006.211.08:15:58.97#ibcon#about to read 4, iclass 33, count 2 2006.211.08:15:58.97#ibcon#read 4, iclass 33, count 2 2006.211.08:15:58.97#ibcon#about to read 5, iclass 33, count 2 2006.211.08:15:58.97#ibcon#read 5, iclass 33, count 2 2006.211.08:15:58.97#ibcon#about to read 6, iclass 33, count 2 2006.211.08:15:58.97#ibcon#read 6, iclass 33, count 2 2006.211.08:15:58.97#ibcon#end of sib2, iclass 33, count 2 2006.211.08:15:58.97#ibcon#*mode == 0, iclass 33, count 2 2006.211.08:15:58.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.08:15:58.97#ibcon#[25=AT05-07\r\n] 2006.211.08:15:58.97#ibcon#*before write, iclass 33, count 2 2006.211.08:15:58.97#ibcon#enter sib2, iclass 33, count 2 2006.211.08:15:58.97#ibcon#flushed, iclass 33, count 2 2006.211.08:15:58.97#ibcon#about to write, iclass 33, count 2 2006.211.08:15:58.97#ibcon#wrote, iclass 33, count 2 2006.211.08:15:58.97#ibcon#about to read 3, iclass 33, count 2 2006.211.08:15:59.00#ibcon#read 3, iclass 33, count 2 2006.211.08:15:59.00#ibcon#about to read 4, iclass 33, count 2 2006.211.08:15:59.00#ibcon#read 4, iclass 33, count 2 2006.211.08:15:59.00#ibcon#about to read 5, iclass 33, count 2 2006.211.08:15:59.00#ibcon#read 5, iclass 33, count 2 2006.211.08:15:59.00#ibcon#about to read 6, iclass 33, count 2 2006.211.08:15:59.00#ibcon#read 6, iclass 33, count 2 2006.211.08:15:59.00#ibcon#end of sib2, iclass 33, count 2 2006.211.08:15:59.00#ibcon#*after write, iclass 33, count 2 2006.211.08:15:59.00#ibcon#*before return 0, iclass 33, count 2 2006.211.08:15:59.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:15:59.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:15:59.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.08:15:59.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:59.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:15:59.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:15:59.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:15:59.12#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:15:59.12#ibcon#first serial, iclass 33, count 0 2006.211.08:15:59.12#ibcon#enter sib2, iclass 33, count 0 2006.211.08:15:59.12#ibcon#flushed, iclass 33, count 0 2006.211.08:15:59.12#ibcon#about to write, iclass 33, count 0 2006.211.08:15:59.12#ibcon#wrote, iclass 33, count 0 2006.211.08:15:59.12#ibcon#about to read 3, iclass 33, count 0 2006.211.08:15:59.14#ibcon#read 3, iclass 33, count 0 2006.211.08:15:59.14#ibcon#about to read 4, iclass 33, count 0 2006.211.08:15:59.14#ibcon#read 4, iclass 33, count 0 2006.211.08:15:59.14#ibcon#about to read 5, iclass 33, count 0 2006.211.08:15:59.14#ibcon#read 5, iclass 33, count 0 2006.211.08:15:59.14#ibcon#about to read 6, iclass 33, count 0 2006.211.08:15:59.14#ibcon#read 6, iclass 33, count 0 2006.211.08:15:59.14#ibcon#end of sib2, iclass 33, count 0 2006.211.08:15:59.14#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:15:59.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:15:59.14#ibcon#[25=USB\r\n] 2006.211.08:15:59.14#ibcon#*before write, iclass 33, count 0 2006.211.08:15:59.14#ibcon#enter sib2, iclass 33, count 0 2006.211.08:15:59.14#ibcon#flushed, iclass 33, count 0 2006.211.08:15:59.14#ibcon#about to write, iclass 33, count 0 2006.211.08:15:59.14#ibcon#wrote, iclass 33, count 0 2006.211.08:15:59.14#ibcon#about to read 3, iclass 33, count 0 2006.211.08:15:59.17#ibcon#read 3, iclass 33, count 0 2006.211.08:15:59.17#ibcon#about to read 4, iclass 33, count 0 2006.211.08:15:59.17#ibcon#read 4, iclass 33, count 0 2006.211.08:15:59.17#ibcon#about to read 5, iclass 33, count 0 2006.211.08:15:59.17#ibcon#read 5, iclass 33, count 0 2006.211.08:15:59.17#ibcon#about to read 6, iclass 33, count 0 2006.211.08:15:59.17#ibcon#read 6, iclass 33, count 0 2006.211.08:15:59.17#ibcon#end of sib2, iclass 33, count 0 2006.211.08:15:59.17#ibcon#*after write, iclass 33, count 0 2006.211.08:15:59.17#ibcon#*before return 0, iclass 33, count 0 2006.211.08:15:59.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:15:59.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:15:59.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:15:59.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:15:59.17$vc4f8/valo=6,772.99 2006.211.08:15:59.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.08:15:59.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.08:15:59.17#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:59.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:15:59.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:15:59.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:15:59.17#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:15:59.17#ibcon#first serial, iclass 35, count 0 2006.211.08:15:59.17#ibcon#enter sib2, iclass 35, count 0 2006.211.08:15:59.17#ibcon#flushed, iclass 35, count 0 2006.211.08:15:59.17#ibcon#about to write, iclass 35, count 0 2006.211.08:15:59.17#ibcon#wrote, iclass 35, count 0 2006.211.08:15:59.17#ibcon#about to read 3, iclass 35, count 0 2006.211.08:15:59.19#ibcon#read 3, iclass 35, count 0 2006.211.08:15:59.19#ibcon#about to read 4, iclass 35, count 0 2006.211.08:15:59.19#ibcon#read 4, iclass 35, count 0 2006.211.08:15:59.19#ibcon#about to read 5, iclass 35, count 0 2006.211.08:15:59.19#ibcon#read 5, iclass 35, count 0 2006.211.08:15:59.19#ibcon#about to read 6, iclass 35, count 0 2006.211.08:15:59.19#ibcon#read 6, iclass 35, count 0 2006.211.08:15:59.19#ibcon#end of sib2, iclass 35, count 0 2006.211.08:15:59.19#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:15:59.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:15:59.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:15:59.19#ibcon#*before write, iclass 35, count 0 2006.211.08:15:59.19#ibcon#enter sib2, iclass 35, count 0 2006.211.08:15:59.19#ibcon#flushed, iclass 35, count 0 2006.211.08:15:59.19#ibcon#about to write, iclass 35, count 0 2006.211.08:15:59.19#ibcon#wrote, iclass 35, count 0 2006.211.08:15:59.19#ibcon#about to read 3, iclass 35, count 0 2006.211.08:15:59.23#ibcon#read 3, iclass 35, count 0 2006.211.08:15:59.23#ibcon#about to read 4, iclass 35, count 0 2006.211.08:15:59.23#ibcon#read 4, iclass 35, count 0 2006.211.08:15:59.23#ibcon#about to read 5, iclass 35, count 0 2006.211.08:15:59.23#ibcon#read 5, iclass 35, count 0 2006.211.08:15:59.23#ibcon#about to read 6, iclass 35, count 0 2006.211.08:15:59.23#ibcon#read 6, iclass 35, count 0 2006.211.08:15:59.23#ibcon#end of sib2, iclass 35, count 0 2006.211.08:15:59.23#ibcon#*after write, iclass 35, count 0 2006.211.08:15:59.23#ibcon#*before return 0, iclass 35, count 0 2006.211.08:15:59.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:15:59.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:15:59.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:15:59.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:15:59.23$vc4f8/va=6,6 2006.211.08:15:59.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.08:15:59.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.08:15:59.23#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:59.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:15:59.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:15:59.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:15:59.29#ibcon#enter wrdev, iclass 37, count 2 2006.211.08:15:59.29#ibcon#first serial, iclass 37, count 2 2006.211.08:15:59.29#ibcon#enter sib2, iclass 37, count 2 2006.211.08:15:59.29#ibcon#flushed, iclass 37, count 2 2006.211.08:15:59.29#ibcon#about to write, iclass 37, count 2 2006.211.08:15:59.29#ibcon#wrote, iclass 37, count 2 2006.211.08:15:59.29#ibcon#about to read 3, iclass 37, count 2 2006.211.08:15:59.31#ibcon#read 3, iclass 37, count 2 2006.211.08:15:59.31#ibcon#about to read 4, iclass 37, count 2 2006.211.08:15:59.31#ibcon#read 4, iclass 37, count 2 2006.211.08:15:59.31#ibcon#about to read 5, iclass 37, count 2 2006.211.08:15:59.31#ibcon#read 5, iclass 37, count 2 2006.211.08:15:59.31#ibcon#about to read 6, iclass 37, count 2 2006.211.08:15:59.31#ibcon#read 6, iclass 37, count 2 2006.211.08:15:59.31#ibcon#end of sib2, iclass 37, count 2 2006.211.08:15:59.31#ibcon#*mode == 0, iclass 37, count 2 2006.211.08:15:59.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.08:15:59.31#ibcon#[25=AT06-06\r\n] 2006.211.08:15:59.31#ibcon#*before write, iclass 37, count 2 2006.211.08:15:59.31#ibcon#enter sib2, iclass 37, count 2 2006.211.08:15:59.31#ibcon#flushed, iclass 37, count 2 2006.211.08:15:59.31#ibcon#about to write, iclass 37, count 2 2006.211.08:15:59.31#ibcon#wrote, iclass 37, count 2 2006.211.08:15:59.31#ibcon#about to read 3, iclass 37, count 2 2006.211.08:15:59.34#ibcon#read 3, iclass 37, count 2 2006.211.08:15:59.34#ibcon#about to read 4, iclass 37, count 2 2006.211.08:15:59.34#ibcon#read 4, iclass 37, count 2 2006.211.08:15:59.34#ibcon#about to read 5, iclass 37, count 2 2006.211.08:15:59.34#ibcon#read 5, iclass 37, count 2 2006.211.08:15:59.34#ibcon#about to read 6, iclass 37, count 2 2006.211.08:15:59.34#ibcon#read 6, iclass 37, count 2 2006.211.08:15:59.34#ibcon#end of sib2, iclass 37, count 2 2006.211.08:15:59.34#ibcon#*after write, iclass 37, count 2 2006.211.08:15:59.34#ibcon#*before return 0, iclass 37, count 2 2006.211.08:15:59.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:15:59.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:15:59.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.08:15:59.34#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:59.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:15:59.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:15:59.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:15:59.46#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:15:59.46#ibcon#first serial, iclass 37, count 0 2006.211.08:15:59.46#ibcon#enter sib2, iclass 37, count 0 2006.211.08:15:59.46#ibcon#flushed, iclass 37, count 0 2006.211.08:15:59.46#ibcon#about to write, iclass 37, count 0 2006.211.08:15:59.46#ibcon#wrote, iclass 37, count 0 2006.211.08:15:59.46#ibcon#about to read 3, iclass 37, count 0 2006.211.08:15:59.48#ibcon#read 3, iclass 37, count 0 2006.211.08:15:59.48#ibcon#about to read 4, iclass 37, count 0 2006.211.08:15:59.48#ibcon#read 4, iclass 37, count 0 2006.211.08:15:59.48#ibcon#about to read 5, iclass 37, count 0 2006.211.08:15:59.48#ibcon#read 5, iclass 37, count 0 2006.211.08:15:59.48#ibcon#about to read 6, iclass 37, count 0 2006.211.08:15:59.48#ibcon#read 6, iclass 37, count 0 2006.211.08:15:59.48#ibcon#end of sib2, iclass 37, count 0 2006.211.08:15:59.48#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:15:59.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:15:59.48#ibcon#[25=USB\r\n] 2006.211.08:15:59.48#ibcon#*before write, iclass 37, count 0 2006.211.08:15:59.48#ibcon#enter sib2, iclass 37, count 0 2006.211.08:15:59.48#ibcon#flushed, iclass 37, count 0 2006.211.08:15:59.48#ibcon#about to write, iclass 37, count 0 2006.211.08:15:59.48#ibcon#wrote, iclass 37, count 0 2006.211.08:15:59.48#ibcon#about to read 3, iclass 37, count 0 2006.211.08:15:59.51#ibcon#read 3, iclass 37, count 0 2006.211.08:15:59.51#ibcon#about to read 4, iclass 37, count 0 2006.211.08:15:59.51#ibcon#read 4, iclass 37, count 0 2006.211.08:15:59.51#ibcon#about to read 5, iclass 37, count 0 2006.211.08:15:59.51#ibcon#read 5, iclass 37, count 0 2006.211.08:15:59.51#ibcon#about to read 6, iclass 37, count 0 2006.211.08:15:59.51#ibcon#read 6, iclass 37, count 0 2006.211.08:15:59.51#ibcon#end of sib2, iclass 37, count 0 2006.211.08:15:59.51#ibcon#*after write, iclass 37, count 0 2006.211.08:15:59.51#ibcon#*before return 0, iclass 37, count 0 2006.211.08:15:59.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:15:59.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:15:59.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:15:59.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:15:59.51$vc4f8/valo=7,832.99 2006.211.08:15:59.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.08:15:59.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.08:15:59.51#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:59.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:15:59.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:15:59.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:15:59.51#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:15:59.51#ibcon#first serial, iclass 39, count 0 2006.211.08:15:59.51#ibcon#enter sib2, iclass 39, count 0 2006.211.08:15:59.51#ibcon#flushed, iclass 39, count 0 2006.211.08:15:59.51#ibcon#about to write, iclass 39, count 0 2006.211.08:15:59.51#ibcon#wrote, iclass 39, count 0 2006.211.08:15:59.51#ibcon#about to read 3, iclass 39, count 0 2006.211.08:15:59.53#ibcon#read 3, iclass 39, count 0 2006.211.08:15:59.53#ibcon#about to read 4, iclass 39, count 0 2006.211.08:15:59.53#ibcon#read 4, iclass 39, count 0 2006.211.08:15:59.53#ibcon#about to read 5, iclass 39, count 0 2006.211.08:15:59.53#ibcon#read 5, iclass 39, count 0 2006.211.08:15:59.53#ibcon#about to read 6, iclass 39, count 0 2006.211.08:15:59.53#ibcon#read 6, iclass 39, count 0 2006.211.08:15:59.53#ibcon#end of sib2, iclass 39, count 0 2006.211.08:15:59.53#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:15:59.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:15:59.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:15:59.53#ibcon#*before write, iclass 39, count 0 2006.211.08:15:59.53#ibcon#enter sib2, iclass 39, count 0 2006.211.08:15:59.53#ibcon#flushed, iclass 39, count 0 2006.211.08:15:59.53#ibcon#about to write, iclass 39, count 0 2006.211.08:15:59.53#ibcon#wrote, iclass 39, count 0 2006.211.08:15:59.53#ibcon#about to read 3, iclass 39, count 0 2006.211.08:15:59.57#ibcon#read 3, iclass 39, count 0 2006.211.08:15:59.57#ibcon#about to read 4, iclass 39, count 0 2006.211.08:15:59.57#ibcon#read 4, iclass 39, count 0 2006.211.08:15:59.57#ibcon#about to read 5, iclass 39, count 0 2006.211.08:15:59.57#ibcon#read 5, iclass 39, count 0 2006.211.08:15:59.57#ibcon#about to read 6, iclass 39, count 0 2006.211.08:15:59.57#ibcon#read 6, iclass 39, count 0 2006.211.08:15:59.57#ibcon#end of sib2, iclass 39, count 0 2006.211.08:15:59.57#ibcon#*after write, iclass 39, count 0 2006.211.08:15:59.57#ibcon#*before return 0, iclass 39, count 0 2006.211.08:15:59.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:15:59.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:15:59.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:15:59.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:15:59.57$vc4f8/va=7,6 2006.211.08:15:59.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.08:15:59.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.08:15:59.57#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:59.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:15:59.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:15:59.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:15:59.63#ibcon#enter wrdev, iclass 3, count 2 2006.211.08:15:59.63#ibcon#first serial, iclass 3, count 2 2006.211.08:15:59.63#ibcon#enter sib2, iclass 3, count 2 2006.211.08:15:59.63#ibcon#flushed, iclass 3, count 2 2006.211.08:15:59.63#ibcon#about to write, iclass 3, count 2 2006.211.08:15:59.63#ibcon#wrote, iclass 3, count 2 2006.211.08:15:59.63#ibcon#about to read 3, iclass 3, count 2 2006.211.08:15:59.65#ibcon#read 3, iclass 3, count 2 2006.211.08:15:59.65#ibcon#about to read 4, iclass 3, count 2 2006.211.08:15:59.65#ibcon#read 4, iclass 3, count 2 2006.211.08:15:59.65#ibcon#about to read 5, iclass 3, count 2 2006.211.08:15:59.65#ibcon#read 5, iclass 3, count 2 2006.211.08:15:59.65#ibcon#about to read 6, iclass 3, count 2 2006.211.08:15:59.65#ibcon#read 6, iclass 3, count 2 2006.211.08:15:59.65#ibcon#end of sib2, iclass 3, count 2 2006.211.08:15:59.65#ibcon#*mode == 0, iclass 3, count 2 2006.211.08:15:59.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.08:15:59.65#ibcon#[25=AT07-06\r\n] 2006.211.08:15:59.65#ibcon#*before write, iclass 3, count 2 2006.211.08:15:59.65#ibcon#enter sib2, iclass 3, count 2 2006.211.08:15:59.65#ibcon#flushed, iclass 3, count 2 2006.211.08:15:59.65#ibcon#about to write, iclass 3, count 2 2006.211.08:15:59.65#ibcon#wrote, iclass 3, count 2 2006.211.08:15:59.65#ibcon#about to read 3, iclass 3, count 2 2006.211.08:15:59.68#ibcon#read 3, iclass 3, count 2 2006.211.08:15:59.68#ibcon#about to read 4, iclass 3, count 2 2006.211.08:15:59.68#ibcon#read 4, iclass 3, count 2 2006.211.08:15:59.68#ibcon#about to read 5, iclass 3, count 2 2006.211.08:15:59.68#ibcon#read 5, iclass 3, count 2 2006.211.08:15:59.68#ibcon#about to read 6, iclass 3, count 2 2006.211.08:15:59.68#ibcon#read 6, iclass 3, count 2 2006.211.08:15:59.68#ibcon#end of sib2, iclass 3, count 2 2006.211.08:15:59.68#ibcon#*after write, iclass 3, count 2 2006.211.08:15:59.68#ibcon#*before return 0, iclass 3, count 2 2006.211.08:15:59.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:15:59.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:15:59.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.08:15:59.68#ibcon#ireg 7 cls_cnt 0 2006.211.08:15:59.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:15:59.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:15:59.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:15:59.80#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:15:59.80#ibcon#first serial, iclass 3, count 0 2006.211.08:15:59.80#ibcon#enter sib2, iclass 3, count 0 2006.211.08:15:59.80#ibcon#flushed, iclass 3, count 0 2006.211.08:15:59.80#ibcon#about to write, iclass 3, count 0 2006.211.08:15:59.80#ibcon#wrote, iclass 3, count 0 2006.211.08:15:59.80#ibcon#about to read 3, iclass 3, count 0 2006.211.08:15:59.82#ibcon#read 3, iclass 3, count 0 2006.211.08:15:59.82#ibcon#about to read 4, iclass 3, count 0 2006.211.08:15:59.82#ibcon#read 4, iclass 3, count 0 2006.211.08:15:59.82#ibcon#about to read 5, iclass 3, count 0 2006.211.08:15:59.82#ibcon#read 5, iclass 3, count 0 2006.211.08:15:59.82#ibcon#about to read 6, iclass 3, count 0 2006.211.08:15:59.82#ibcon#read 6, iclass 3, count 0 2006.211.08:15:59.82#ibcon#end of sib2, iclass 3, count 0 2006.211.08:15:59.82#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:15:59.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:15:59.82#ibcon#[25=USB\r\n] 2006.211.08:15:59.82#ibcon#*before write, iclass 3, count 0 2006.211.08:15:59.82#ibcon#enter sib2, iclass 3, count 0 2006.211.08:15:59.82#ibcon#flushed, iclass 3, count 0 2006.211.08:15:59.82#ibcon#about to write, iclass 3, count 0 2006.211.08:15:59.82#ibcon#wrote, iclass 3, count 0 2006.211.08:15:59.82#ibcon#about to read 3, iclass 3, count 0 2006.211.08:15:59.85#ibcon#read 3, iclass 3, count 0 2006.211.08:15:59.85#ibcon#about to read 4, iclass 3, count 0 2006.211.08:15:59.85#ibcon#read 4, iclass 3, count 0 2006.211.08:15:59.85#ibcon#about to read 5, iclass 3, count 0 2006.211.08:15:59.85#ibcon#read 5, iclass 3, count 0 2006.211.08:15:59.85#ibcon#about to read 6, iclass 3, count 0 2006.211.08:15:59.85#ibcon#read 6, iclass 3, count 0 2006.211.08:15:59.85#ibcon#end of sib2, iclass 3, count 0 2006.211.08:15:59.85#ibcon#*after write, iclass 3, count 0 2006.211.08:15:59.85#ibcon#*before return 0, iclass 3, count 0 2006.211.08:15:59.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:15:59.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:15:59.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:15:59.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:15:59.85$vc4f8/valo=8,852.99 2006.211.08:15:59.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.08:15:59.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.08:15:59.85#ibcon#ireg 17 cls_cnt 0 2006.211.08:15:59.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:15:59.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:15:59.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:15:59.85#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:15:59.85#ibcon#first serial, iclass 5, count 0 2006.211.08:15:59.85#ibcon#enter sib2, iclass 5, count 0 2006.211.08:15:59.85#ibcon#flushed, iclass 5, count 0 2006.211.08:15:59.85#ibcon#about to write, iclass 5, count 0 2006.211.08:15:59.85#ibcon#wrote, iclass 5, count 0 2006.211.08:15:59.85#ibcon#about to read 3, iclass 5, count 0 2006.211.08:15:59.87#ibcon#read 3, iclass 5, count 0 2006.211.08:15:59.87#ibcon#about to read 4, iclass 5, count 0 2006.211.08:15:59.87#ibcon#read 4, iclass 5, count 0 2006.211.08:15:59.87#ibcon#about to read 5, iclass 5, count 0 2006.211.08:15:59.87#ibcon#read 5, iclass 5, count 0 2006.211.08:15:59.87#ibcon#about to read 6, iclass 5, count 0 2006.211.08:15:59.87#ibcon#read 6, iclass 5, count 0 2006.211.08:15:59.87#ibcon#end of sib2, iclass 5, count 0 2006.211.08:15:59.87#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:15:59.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:15:59.87#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:15:59.87#ibcon#*before write, iclass 5, count 0 2006.211.08:15:59.87#ibcon#enter sib2, iclass 5, count 0 2006.211.08:15:59.87#ibcon#flushed, iclass 5, count 0 2006.211.08:15:59.87#ibcon#about to write, iclass 5, count 0 2006.211.08:15:59.87#ibcon#wrote, iclass 5, count 0 2006.211.08:15:59.87#ibcon#about to read 3, iclass 5, count 0 2006.211.08:15:59.91#ibcon#read 3, iclass 5, count 0 2006.211.08:15:59.91#ibcon#about to read 4, iclass 5, count 0 2006.211.08:15:59.91#ibcon#read 4, iclass 5, count 0 2006.211.08:15:59.91#ibcon#about to read 5, iclass 5, count 0 2006.211.08:15:59.91#ibcon#read 5, iclass 5, count 0 2006.211.08:15:59.91#ibcon#about to read 6, iclass 5, count 0 2006.211.08:15:59.91#ibcon#read 6, iclass 5, count 0 2006.211.08:15:59.91#ibcon#end of sib2, iclass 5, count 0 2006.211.08:15:59.91#ibcon#*after write, iclass 5, count 0 2006.211.08:15:59.91#ibcon#*before return 0, iclass 5, count 0 2006.211.08:15:59.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:15:59.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:15:59.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:15:59.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:15:59.91$vc4f8/va=8,7 2006.211.08:15:59.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.08:15:59.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.08:15:59.91#ibcon#ireg 11 cls_cnt 2 2006.211.08:15:59.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:15:59.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:15:59.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:15:59.97#ibcon#enter wrdev, iclass 7, count 2 2006.211.08:15:59.97#ibcon#first serial, iclass 7, count 2 2006.211.08:15:59.97#ibcon#enter sib2, iclass 7, count 2 2006.211.08:15:59.97#ibcon#flushed, iclass 7, count 2 2006.211.08:15:59.97#ibcon#about to write, iclass 7, count 2 2006.211.08:15:59.97#ibcon#wrote, iclass 7, count 2 2006.211.08:15:59.97#ibcon#about to read 3, iclass 7, count 2 2006.211.08:15:59.99#ibcon#read 3, iclass 7, count 2 2006.211.08:15:59.99#ibcon#about to read 4, iclass 7, count 2 2006.211.08:15:59.99#ibcon#read 4, iclass 7, count 2 2006.211.08:15:59.99#ibcon#about to read 5, iclass 7, count 2 2006.211.08:15:59.99#ibcon#read 5, iclass 7, count 2 2006.211.08:15:59.99#ibcon#about to read 6, iclass 7, count 2 2006.211.08:15:59.99#ibcon#read 6, iclass 7, count 2 2006.211.08:15:59.99#ibcon#end of sib2, iclass 7, count 2 2006.211.08:15:59.99#ibcon#*mode == 0, iclass 7, count 2 2006.211.08:15:59.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.08:15:59.99#ibcon#[25=AT08-07\r\n] 2006.211.08:15:59.99#ibcon#*before write, iclass 7, count 2 2006.211.08:15:59.99#ibcon#enter sib2, iclass 7, count 2 2006.211.08:15:59.99#ibcon#flushed, iclass 7, count 2 2006.211.08:15:59.99#ibcon#about to write, iclass 7, count 2 2006.211.08:15:59.99#ibcon#wrote, iclass 7, count 2 2006.211.08:15:59.99#ibcon#about to read 3, iclass 7, count 2 2006.211.08:16:00.02#ibcon#read 3, iclass 7, count 2 2006.211.08:16:00.02#ibcon#about to read 4, iclass 7, count 2 2006.211.08:16:00.02#ibcon#read 4, iclass 7, count 2 2006.211.08:16:00.02#ibcon#about to read 5, iclass 7, count 2 2006.211.08:16:00.02#ibcon#read 5, iclass 7, count 2 2006.211.08:16:00.02#ibcon#about to read 6, iclass 7, count 2 2006.211.08:16:00.02#ibcon#read 6, iclass 7, count 2 2006.211.08:16:00.02#ibcon#end of sib2, iclass 7, count 2 2006.211.08:16:00.02#ibcon#*after write, iclass 7, count 2 2006.211.08:16:00.02#ibcon#*before return 0, iclass 7, count 2 2006.211.08:16:00.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:16:00.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:16:00.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.08:16:00.02#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:00.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:16:00.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:16:00.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:16:00.14#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:16:00.14#ibcon#first serial, iclass 7, count 0 2006.211.08:16:00.14#ibcon#enter sib2, iclass 7, count 0 2006.211.08:16:00.14#ibcon#flushed, iclass 7, count 0 2006.211.08:16:00.14#ibcon#about to write, iclass 7, count 0 2006.211.08:16:00.14#ibcon#wrote, iclass 7, count 0 2006.211.08:16:00.14#ibcon#about to read 3, iclass 7, count 0 2006.211.08:16:00.16#ibcon#read 3, iclass 7, count 0 2006.211.08:16:00.16#ibcon#about to read 4, iclass 7, count 0 2006.211.08:16:00.16#ibcon#read 4, iclass 7, count 0 2006.211.08:16:00.16#ibcon#about to read 5, iclass 7, count 0 2006.211.08:16:00.16#ibcon#read 5, iclass 7, count 0 2006.211.08:16:00.16#ibcon#about to read 6, iclass 7, count 0 2006.211.08:16:00.16#ibcon#read 6, iclass 7, count 0 2006.211.08:16:00.16#ibcon#end of sib2, iclass 7, count 0 2006.211.08:16:00.16#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:16:00.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:16:00.16#ibcon#[25=USB\r\n] 2006.211.08:16:00.16#ibcon#*before write, iclass 7, count 0 2006.211.08:16:00.16#ibcon#enter sib2, iclass 7, count 0 2006.211.08:16:00.16#ibcon#flushed, iclass 7, count 0 2006.211.08:16:00.16#ibcon#about to write, iclass 7, count 0 2006.211.08:16:00.16#ibcon#wrote, iclass 7, count 0 2006.211.08:16:00.16#ibcon#about to read 3, iclass 7, count 0 2006.211.08:16:00.19#ibcon#read 3, iclass 7, count 0 2006.211.08:16:00.19#ibcon#about to read 4, iclass 7, count 0 2006.211.08:16:00.19#ibcon#read 4, iclass 7, count 0 2006.211.08:16:00.19#ibcon#about to read 5, iclass 7, count 0 2006.211.08:16:00.19#ibcon#read 5, iclass 7, count 0 2006.211.08:16:00.19#ibcon#about to read 6, iclass 7, count 0 2006.211.08:16:00.19#ibcon#read 6, iclass 7, count 0 2006.211.08:16:00.19#ibcon#end of sib2, iclass 7, count 0 2006.211.08:16:00.19#ibcon#*after write, iclass 7, count 0 2006.211.08:16:00.19#ibcon#*before return 0, iclass 7, count 0 2006.211.08:16:00.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:16:00.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:16:00.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:16:00.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:16:00.19$vc4f8/vblo=1,632.99 2006.211.08:16:00.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.08:16:00.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.08:16:00.19#ibcon#ireg 17 cls_cnt 0 2006.211.08:16:00.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:16:00.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:16:00.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:16:00.19#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:16:00.19#ibcon#first serial, iclass 11, count 0 2006.211.08:16:00.19#ibcon#enter sib2, iclass 11, count 0 2006.211.08:16:00.19#ibcon#flushed, iclass 11, count 0 2006.211.08:16:00.19#ibcon#about to write, iclass 11, count 0 2006.211.08:16:00.19#ibcon#wrote, iclass 11, count 0 2006.211.08:16:00.19#ibcon#about to read 3, iclass 11, count 0 2006.211.08:16:00.21#ibcon#read 3, iclass 11, count 0 2006.211.08:16:00.21#ibcon#about to read 4, iclass 11, count 0 2006.211.08:16:00.21#ibcon#read 4, iclass 11, count 0 2006.211.08:16:00.21#ibcon#about to read 5, iclass 11, count 0 2006.211.08:16:00.21#ibcon#read 5, iclass 11, count 0 2006.211.08:16:00.21#ibcon#about to read 6, iclass 11, count 0 2006.211.08:16:00.21#ibcon#read 6, iclass 11, count 0 2006.211.08:16:00.21#ibcon#end of sib2, iclass 11, count 0 2006.211.08:16:00.21#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:16:00.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:16:00.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:16:00.21#ibcon#*before write, iclass 11, count 0 2006.211.08:16:00.21#ibcon#enter sib2, iclass 11, count 0 2006.211.08:16:00.21#ibcon#flushed, iclass 11, count 0 2006.211.08:16:00.21#ibcon#about to write, iclass 11, count 0 2006.211.08:16:00.21#ibcon#wrote, iclass 11, count 0 2006.211.08:16:00.21#ibcon#about to read 3, iclass 11, count 0 2006.211.08:16:00.25#ibcon#read 3, iclass 11, count 0 2006.211.08:16:00.25#ibcon#about to read 4, iclass 11, count 0 2006.211.08:16:00.25#ibcon#read 4, iclass 11, count 0 2006.211.08:16:00.25#ibcon#about to read 5, iclass 11, count 0 2006.211.08:16:00.25#ibcon#read 5, iclass 11, count 0 2006.211.08:16:00.25#ibcon#about to read 6, iclass 11, count 0 2006.211.08:16:00.25#ibcon#read 6, iclass 11, count 0 2006.211.08:16:00.25#ibcon#end of sib2, iclass 11, count 0 2006.211.08:16:00.25#ibcon#*after write, iclass 11, count 0 2006.211.08:16:00.25#ibcon#*before return 0, iclass 11, count 0 2006.211.08:16:00.25#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:16:00.25#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.08:16:00.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:16:00.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:16:00.25$vc4f8/vb=1,4 2006.211.08:16:00.25#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.08:16:00.25#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.08:16:00.25#ibcon#ireg 11 cls_cnt 2 2006.211.08:16:00.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:16:00.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:16:00.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:16:00.25#ibcon#enter wrdev, iclass 13, count 2 2006.211.08:16:00.25#ibcon#first serial, iclass 13, count 2 2006.211.08:16:00.25#ibcon#enter sib2, iclass 13, count 2 2006.211.08:16:00.25#ibcon#flushed, iclass 13, count 2 2006.211.08:16:00.25#ibcon#about to write, iclass 13, count 2 2006.211.08:16:00.25#ibcon#wrote, iclass 13, count 2 2006.211.08:16:00.25#ibcon#about to read 3, iclass 13, count 2 2006.211.08:16:00.27#ibcon#read 3, iclass 13, count 2 2006.211.08:16:00.27#ibcon#about to read 4, iclass 13, count 2 2006.211.08:16:00.27#ibcon#read 4, iclass 13, count 2 2006.211.08:16:00.27#ibcon#about to read 5, iclass 13, count 2 2006.211.08:16:00.27#ibcon#read 5, iclass 13, count 2 2006.211.08:16:00.27#ibcon#about to read 6, iclass 13, count 2 2006.211.08:16:00.27#ibcon#read 6, iclass 13, count 2 2006.211.08:16:00.27#ibcon#end of sib2, iclass 13, count 2 2006.211.08:16:00.27#ibcon#*mode == 0, iclass 13, count 2 2006.211.08:16:00.27#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.08:16:00.27#ibcon#[27=AT01-04\r\n] 2006.211.08:16:00.27#ibcon#*before write, iclass 13, count 2 2006.211.08:16:00.27#ibcon#enter sib2, iclass 13, count 2 2006.211.08:16:00.27#ibcon#flushed, iclass 13, count 2 2006.211.08:16:00.27#ibcon#about to write, iclass 13, count 2 2006.211.08:16:00.27#ibcon#wrote, iclass 13, count 2 2006.211.08:16:00.27#ibcon#about to read 3, iclass 13, count 2 2006.211.08:16:00.30#ibcon#read 3, iclass 13, count 2 2006.211.08:16:00.30#ibcon#about to read 4, iclass 13, count 2 2006.211.08:16:00.30#ibcon#read 4, iclass 13, count 2 2006.211.08:16:00.30#ibcon#about to read 5, iclass 13, count 2 2006.211.08:16:00.30#ibcon#read 5, iclass 13, count 2 2006.211.08:16:00.30#ibcon#about to read 6, iclass 13, count 2 2006.211.08:16:00.30#ibcon#read 6, iclass 13, count 2 2006.211.08:16:00.30#ibcon#end of sib2, iclass 13, count 2 2006.211.08:16:00.30#ibcon#*after write, iclass 13, count 2 2006.211.08:16:00.30#ibcon#*before return 0, iclass 13, count 2 2006.211.08:16:00.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:16:00.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.08:16:00.30#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.08:16:00.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:00.30#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:16:00.42#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:16:00.42#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:16:00.42#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:16:00.42#ibcon#first serial, iclass 13, count 0 2006.211.08:16:00.42#ibcon#enter sib2, iclass 13, count 0 2006.211.08:16:00.42#ibcon#flushed, iclass 13, count 0 2006.211.08:16:00.42#ibcon#about to write, iclass 13, count 0 2006.211.08:16:00.42#ibcon#wrote, iclass 13, count 0 2006.211.08:16:00.42#ibcon#about to read 3, iclass 13, count 0 2006.211.08:16:00.44#ibcon#read 3, iclass 13, count 0 2006.211.08:16:00.44#ibcon#about to read 4, iclass 13, count 0 2006.211.08:16:00.44#ibcon#read 4, iclass 13, count 0 2006.211.08:16:00.44#ibcon#about to read 5, iclass 13, count 0 2006.211.08:16:00.44#ibcon#read 5, iclass 13, count 0 2006.211.08:16:00.44#ibcon#about to read 6, iclass 13, count 0 2006.211.08:16:00.44#ibcon#read 6, iclass 13, count 0 2006.211.08:16:00.44#ibcon#end of sib2, iclass 13, count 0 2006.211.08:16:00.44#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:16:00.44#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:16:00.44#ibcon#[27=USB\r\n] 2006.211.08:16:00.44#ibcon#*before write, iclass 13, count 0 2006.211.08:16:00.44#ibcon#enter sib2, iclass 13, count 0 2006.211.08:16:00.44#ibcon#flushed, iclass 13, count 0 2006.211.08:16:00.44#ibcon#about to write, iclass 13, count 0 2006.211.08:16:00.44#ibcon#wrote, iclass 13, count 0 2006.211.08:16:00.44#ibcon#about to read 3, iclass 13, count 0 2006.211.08:16:00.47#ibcon#read 3, iclass 13, count 0 2006.211.08:16:00.47#ibcon#about to read 4, iclass 13, count 0 2006.211.08:16:00.47#ibcon#read 4, iclass 13, count 0 2006.211.08:16:00.47#ibcon#about to read 5, iclass 13, count 0 2006.211.08:16:00.47#ibcon#read 5, iclass 13, count 0 2006.211.08:16:00.47#ibcon#about to read 6, iclass 13, count 0 2006.211.08:16:00.47#ibcon#read 6, iclass 13, count 0 2006.211.08:16:00.47#ibcon#end of sib2, iclass 13, count 0 2006.211.08:16:00.47#ibcon#*after write, iclass 13, count 0 2006.211.08:16:00.47#ibcon#*before return 0, iclass 13, count 0 2006.211.08:16:00.47#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:16:00.47#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.08:16:00.47#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:16:00.47#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:16:00.47$vc4f8/vblo=2,640.99 2006.211.08:16:00.47#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.08:16:00.47#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.08:16:00.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:16:00.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:16:00.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:16:00.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:16:00.47#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:16:00.47#ibcon#first serial, iclass 15, count 0 2006.211.08:16:00.47#ibcon#enter sib2, iclass 15, count 0 2006.211.08:16:00.47#ibcon#flushed, iclass 15, count 0 2006.211.08:16:00.47#ibcon#about to write, iclass 15, count 0 2006.211.08:16:00.47#ibcon#wrote, iclass 15, count 0 2006.211.08:16:00.47#ibcon#about to read 3, iclass 15, count 0 2006.211.08:16:00.49#ibcon#read 3, iclass 15, count 0 2006.211.08:16:00.49#ibcon#about to read 4, iclass 15, count 0 2006.211.08:16:00.49#ibcon#read 4, iclass 15, count 0 2006.211.08:16:00.49#ibcon#about to read 5, iclass 15, count 0 2006.211.08:16:00.49#ibcon#read 5, iclass 15, count 0 2006.211.08:16:00.49#ibcon#about to read 6, iclass 15, count 0 2006.211.08:16:00.49#ibcon#read 6, iclass 15, count 0 2006.211.08:16:00.49#ibcon#end of sib2, iclass 15, count 0 2006.211.08:16:00.49#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:16:00.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:16:00.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:16:00.49#ibcon#*before write, iclass 15, count 0 2006.211.08:16:00.49#ibcon#enter sib2, iclass 15, count 0 2006.211.08:16:00.49#ibcon#flushed, iclass 15, count 0 2006.211.08:16:00.49#ibcon#about to write, iclass 15, count 0 2006.211.08:16:00.49#ibcon#wrote, iclass 15, count 0 2006.211.08:16:00.49#ibcon#about to read 3, iclass 15, count 0 2006.211.08:16:00.53#ibcon#read 3, iclass 15, count 0 2006.211.08:16:00.53#ibcon#about to read 4, iclass 15, count 0 2006.211.08:16:00.53#ibcon#read 4, iclass 15, count 0 2006.211.08:16:00.53#ibcon#about to read 5, iclass 15, count 0 2006.211.08:16:00.53#ibcon#read 5, iclass 15, count 0 2006.211.08:16:00.53#ibcon#about to read 6, iclass 15, count 0 2006.211.08:16:00.53#ibcon#read 6, iclass 15, count 0 2006.211.08:16:00.53#ibcon#end of sib2, iclass 15, count 0 2006.211.08:16:00.53#ibcon#*after write, iclass 15, count 0 2006.211.08:16:00.53#ibcon#*before return 0, iclass 15, count 0 2006.211.08:16:00.53#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:16:00.53#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:16:00.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:16:00.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:16:00.53$vc4f8/vb=2,4 2006.211.08:16:00.53#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.08:16:00.53#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.08:16:00.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:16:00.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:16:00.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:16:00.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:16:00.59#ibcon#enter wrdev, iclass 17, count 2 2006.211.08:16:00.59#ibcon#first serial, iclass 17, count 2 2006.211.08:16:00.59#ibcon#enter sib2, iclass 17, count 2 2006.211.08:16:00.59#ibcon#flushed, iclass 17, count 2 2006.211.08:16:00.59#ibcon#about to write, iclass 17, count 2 2006.211.08:16:00.59#ibcon#wrote, iclass 17, count 2 2006.211.08:16:00.59#ibcon#about to read 3, iclass 17, count 2 2006.211.08:16:00.61#ibcon#read 3, iclass 17, count 2 2006.211.08:16:00.61#ibcon#about to read 4, iclass 17, count 2 2006.211.08:16:00.61#ibcon#read 4, iclass 17, count 2 2006.211.08:16:00.61#ibcon#about to read 5, iclass 17, count 2 2006.211.08:16:00.61#ibcon#read 5, iclass 17, count 2 2006.211.08:16:00.61#ibcon#about to read 6, iclass 17, count 2 2006.211.08:16:00.61#ibcon#read 6, iclass 17, count 2 2006.211.08:16:00.61#ibcon#end of sib2, iclass 17, count 2 2006.211.08:16:00.61#ibcon#*mode == 0, iclass 17, count 2 2006.211.08:16:00.61#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.08:16:00.61#ibcon#[27=AT02-04\r\n] 2006.211.08:16:00.61#ibcon#*before write, iclass 17, count 2 2006.211.08:16:00.61#ibcon#enter sib2, iclass 17, count 2 2006.211.08:16:00.61#ibcon#flushed, iclass 17, count 2 2006.211.08:16:00.61#ibcon#about to write, iclass 17, count 2 2006.211.08:16:00.61#ibcon#wrote, iclass 17, count 2 2006.211.08:16:00.61#ibcon#about to read 3, iclass 17, count 2 2006.211.08:16:00.64#ibcon#read 3, iclass 17, count 2 2006.211.08:16:00.64#ibcon#about to read 4, iclass 17, count 2 2006.211.08:16:00.64#ibcon#read 4, iclass 17, count 2 2006.211.08:16:00.64#ibcon#about to read 5, iclass 17, count 2 2006.211.08:16:00.64#ibcon#read 5, iclass 17, count 2 2006.211.08:16:00.64#ibcon#about to read 6, iclass 17, count 2 2006.211.08:16:00.64#ibcon#read 6, iclass 17, count 2 2006.211.08:16:00.64#ibcon#end of sib2, iclass 17, count 2 2006.211.08:16:00.64#ibcon#*after write, iclass 17, count 2 2006.211.08:16:00.64#ibcon#*before return 0, iclass 17, count 2 2006.211.08:16:00.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:16:00.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:16:00.64#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.08:16:00.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:00.64#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:16:00.76#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:16:00.76#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:16:00.76#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:16:00.76#ibcon#first serial, iclass 17, count 0 2006.211.08:16:00.76#ibcon#enter sib2, iclass 17, count 0 2006.211.08:16:00.76#ibcon#flushed, iclass 17, count 0 2006.211.08:16:00.76#ibcon#about to write, iclass 17, count 0 2006.211.08:16:00.76#ibcon#wrote, iclass 17, count 0 2006.211.08:16:00.76#ibcon#about to read 3, iclass 17, count 0 2006.211.08:16:00.78#ibcon#read 3, iclass 17, count 0 2006.211.08:16:00.78#ibcon#about to read 4, iclass 17, count 0 2006.211.08:16:00.78#ibcon#read 4, iclass 17, count 0 2006.211.08:16:00.78#ibcon#about to read 5, iclass 17, count 0 2006.211.08:16:00.78#ibcon#read 5, iclass 17, count 0 2006.211.08:16:00.78#ibcon#about to read 6, iclass 17, count 0 2006.211.08:16:00.78#ibcon#read 6, iclass 17, count 0 2006.211.08:16:00.78#ibcon#end of sib2, iclass 17, count 0 2006.211.08:16:00.78#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:16:00.78#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:16:00.78#ibcon#[27=USB\r\n] 2006.211.08:16:00.78#ibcon#*before write, iclass 17, count 0 2006.211.08:16:00.78#ibcon#enter sib2, iclass 17, count 0 2006.211.08:16:00.78#ibcon#flushed, iclass 17, count 0 2006.211.08:16:00.78#ibcon#about to write, iclass 17, count 0 2006.211.08:16:00.78#ibcon#wrote, iclass 17, count 0 2006.211.08:16:00.78#ibcon#about to read 3, iclass 17, count 0 2006.211.08:16:00.81#ibcon#read 3, iclass 17, count 0 2006.211.08:16:00.81#ibcon#about to read 4, iclass 17, count 0 2006.211.08:16:00.81#ibcon#read 4, iclass 17, count 0 2006.211.08:16:00.81#ibcon#about to read 5, iclass 17, count 0 2006.211.08:16:00.81#ibcon#read 5, iclass 17, count 0 2006.211.08:16:00.81#ibcon#about to read 6, iclass 17, count 0 2006.211.08:16:00.81#ibcon#read 6, iclass 17, count 0 2006.211.08:16:00.81#ibcon#end of sib2, iclass 17, count 0 2006.211.08:16:00.81#ibcon#*after write, iclass 17, count 0 2006.211.08:16:00.81#ibcon#*before return 0, iclass 17, count 0 2006.211.08:16:00.81#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:16:00.81#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:16:00.81#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:16:00.81#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:16:00.81$vc4f8/vblo=3,656.99 2006.211.08:16:00.81#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.08:16:00.81#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.08:16:00.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:16:00.81#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:16:00.81#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:16:00.81#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:16:00.81#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:16:00.81#ibcon#first serial, iclass 19, count 0 2006.211.08:16:00.81#ibcon#enter sib2, iclass 19, count 0 2006.211.08:16:00.81#ibcon#flushed, iclass 19, count 0 2006.211.08:16:00.81#ibcon#about to write, iclass 19, count 0 2006.211.08:16:00.81#ibcon#wrote, iclass 19, count 0 2006.211.08:16:00.81#ibcon#about to read 3, iclass 19, count 0 2006.211.08:16:00.83#ibcon#read 3, iclass 19, count 0 2006.211.08:16:00.83#ibcon#about to read 4, iclass 19, count 0 2006.211.08:16:00.83#ibcon#read 4, iclass 19, count 0 2006.211.08:16:00.83#ibcon#about to read 5, iclass 19, count 0 2006.211.08:16:00.83#ibcon#read 5, iclass 19, count 0 2006.211.08:16:00.83#ibcon#about to read 6, iclass 19, count 0 2006.211.08:16:00.83#ibcon#read 6, iclass 19, count 0 2006.211.08:16:00.83#ibcon#end of sib2, iclass 19, count 0 2006.211.08:16:00.83#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:16:00.83#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:16:00.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:16:00.83#ibcon#*before write, iclass 19, count 0 2006.211.08:16:00.83#ibcon#enter sib2, iclass 19, count 0 2006.211.08:16:00.83#ibcon#flushed, iclass 19, count 0 2006.211.08:16:00.83#ibcon#about to write, iclass 19, count 0 2006.211.08:16:00.83#ibcon#wrote, iclass 19, count 0 2006.211.08:16:00.83#ibcon#about to read 3, iclass 19, count 0 2006.211.08:16:00.87#ibcon#read 3, iclass 19, count 0 2006.211.08:16:00.87#ibcon#about to read 4, iclass 19, count 0 2006.211.08:16:00.87#ibcon#read 4, iclass 19, count 0 2006.211.08:16:00.87#ibcon#about to read 5, iclass 19, count 0 2006.211.08:16:00.87#ibcon#read 5, iclass 19, count 0 2006.211.08:16:00.87#ibcon#about to read 6, iclass 19, count 0 2006.211.08:16:00.87#ibcon#read 6, iclass 19, count 0 2006.211.08:16:00.87#ibcon#end of sib2, iclass 19, count 0 2006.211.08:16:00.87#ibcon#*after write, iclass 19, count 0 2006.211.08:16:00.87#ibcon#*before return 0, iclass 19, count 0 2006.211.08:16:00.87#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:16:00.87#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:16:00.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:16:00.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:16:00.87$vc4f8/vb=3,3 2006.211.08:16:00.87#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.08:16:00.87#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.08:16:00.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:16:00.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:16:00.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:16:00.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:16:00.93#ibcon#enter wrdev, iclass 21, count 2 2006.211.08:16:00.93#ibcon#first serial, iclass 21, count 2 2006.211.08:16:00.93#ibcon#enter sib2, iclass 21, count 2 2006.211.08:16:00.93#ibcon#flushed, iclass 21, count 2 2006.211.08:16:00.93#ibcon#about to write, iclass 21, count 2 2006.211.08:16:00.93#ibcon#wrote, iclass 21, count 2 2006.211.08:16:00.93#ibcon#about to read 3, iclass 21, count 2 2006.211.08:16:00.95#ibcon#read 3, iclass 21, count 2 2006.211.08:16:00.95#ibcon#about to read 4, iclass 21, count 2 2006.211.08:16:00.95#ibcon#read 4, iclass 21, count 2 2006.211.08:16:00.95#ibcon#about to read 5, iclass 21, count 2 2006.211.08:16:00.95#ibcon#read 5, iclass 21, count 2 2006.211.08:16:00.95#ibcon#about to read 6, iclass 21, count 2 2006.211.08:16:00.95#ibcon#read 6, iclass 21, count 2 2006.211.08:16:00.95#ibcon#end of sib2, iclass 21, count 2 2006.211.08:16:00.95#ibcon#*mode == 0, iclass 21, count 2 2006.211.08:16:00.95#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.08:16:00.95#ibcon#[27=AT03-03\r\n] 2006.211.08:16:00.95#ibcon#*before write, iclass 21, count 2 2006.211.08:16:00.95#ibcon#enter sib2, iclass 21, count 2 2006.211.08:16:00.95#ibcon#flushed, iclass 21, count 2 2006.211.08:16:00.95#ibcon#about to write, iclass 21, count 2 2006.211.08:16:00.95#ibcon#wrote, iclass 21, count 2 2006.211.08:16:00.95#ibcon#about to read 3, iclass 21, count 2 2006.211.08:16:00.98#ibcon#read 3, iclass 21, count 2 2006.211.08:16:00.98#ibcon#about to read 4, iclass 21, count 2 2006.211.08:16:00.98#ibcon#read 4, iclass 21, count 2 2006.211.08:16:00.98#ibcon#about to read 5, iclass 21, count 2 2006.211.08:16:00.98#ibcon#read 5, iclass 21, count 2 2006.211.08:16:00.98#ibcon#about to read 6, iclass 21, count 2 2006.211.08:16:00.98#ibcon#read 6, iclass 21, count 2 2006.211.08:16:00.98#ibcon#end of sib2, iclass 21, count 2 2006.211.08:16:00.98#ibcon#*after write, iclass 21, count 2 2006.211.08:16:00.98#ibcon#*before return 0, iclass 21, count 2 2006.211.08:16:00.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:16:00.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:16:00.98#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.08:16:00.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:00.98#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:16:01.10#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:16:01.10#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:16:01.10#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:16:01.10#ibcon#first serial, iclass 21, count 0 2006.211.08:16:01.10#ibcon#enter sib2, iclass 21, count 0 2006.211.08:16:01.10#ibcon#flushed, iclass 21, count 0 2006.211.08:16:01.10#ibcon#about to write, iclass 21, count 0 2006.211.08:16:01.10#ibcon#wrote, iclass 21, count 0 2006.211.08:16:01.10#ibcon#about to read 3, iclass 21, count 0 2006.211.08:16:01.12#ibcon#read 3, iclass 21, count 0 2006.211.08:16:01.12#ibcon#about to read 4, iclass 21, count 0 2006.211.08:16:01.12#ibcon#read 4, iclass 21, count 0 2006.211.08:16:01.12#ibcon#about to read 5, iclass 21, count 0 2006.211.08:16:01.12#ibcon#read 5, iclass 21, count 0 2006.211.08:16:01.12#ibcon#about to read 6, iclass 21, count 0 2006.211.08:16:01.12#ibcon#read 6, iclass 21, count 0 2006.211.08:16:01.12#ibcon#end of sib2, iclass 21, count 0 2006.211.08:16:01.12#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:16:01.12#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:16:01.12#ibcon#[27=USB\r\n] 2006.211.08:16:01.12#ibcon#*before write, iclass 21, count 0 2006.211.08:16:01.12#ibcon#enter sib2, iclass 21, count 0 2006.211.08:16:01.12#ibcon#flushed, iclass 21, count 0 2006.211.08:16:01.12#ibcon#about to write, iclass 21, count 0 2006.211.08:16:01.12#ibcon#wrote, iclass 21, count 0 2006.211.08:16:01.12#ibcon#about to read 3, iclass 21, count 0 2006.211.08:16:01.15#ibcon#read 3, iclass 21, count 0 2006.211.08:16:01.15#ibcon#about to read 4, iclass 21, count 0 2006.211.08:16:01.15#ibcon#read 4, iclass 21, count 0 2006.211.08:16:01.15#ibcon#about to read 5, iclass 21, count 0 2006.211.08:16:01.15#ibcon#read 5, iclass 21, count 0 2006.211.08:16:01.15#ibcon#about to read 6, iclass 21, count 0 2006.211.08:16:01.15#ibcon#read 6, iclass 21, count 0 2006.211.08:16:01.15#ibcon#end of sib2, iclass 21, count 0 2006.211.08:16:01.15#ibcon#*after write, iclass 21, count 0 2006.211.08:16:01.15#ibcon#*before return 0, iclass 21, count 0 2006.211.08:16:01.15#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:16:01.15#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:16:01.15#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:16:01.15#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:16:01.15$vc4f8/vblo=4,712.99 2006.211.08:16:01.15#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.08:16:01.15#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.08:16:01.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:16:01.15#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:16:01.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:16:01.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:16:01.15#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:16:01.15#ibcon#first serial, iclass 23, count 0 2006.211.08:16:01.15#ibcon#enter sib2, iclass 23, count 0 2006.211.08:16:01.15#ibcon#flushed, iclass 23, count 0 2006.211.08:16:01.15#ibcon#about to write, iclass 23, count 0 2006.211.08:16:01.15#ibcon#wrote, iclass 23, count 0 2006.211.08:16:01.15#ibcon#about to read 3, iclass 23, count 0 2006.211.08:16:01.17#ibcon#read 3, iclass 23, count 0 2006.211.08:16:01.17#ibcon#about to read 4, iclass 23, count 0 2006.211.08:16:01.17#ibcon#read 4, iclass 23, count 0 2006.211.08:16:01.17#ibcon#about to read 5, iclass 23, count 0 2006.211.08:16:01.17#ibcon#read 5, iclass 23, count 0 2006.211.08:16:01.17#ibcon#about to read 6, iclass 23, count 0 2006.211.08:16:01.17#ibcon#read 6, iclass 23, count 0 2006.211.08:16:01.17#ibcon#end of sib2, iclass 23, count 0 2006.211.08:16:01.17#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:16:01.17#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:16:01.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:16:01.17#ibcon#*before write, iclass 23, count 0 2006.211.08:16:01.17#ibcon#enter sib2, iclass 23, count 0 2006.211.08:16:01.17#ibcon#flushed, iclass 23, count 0 2006.211.08:16:01.17#ibcon#about to write, iclass 23, count 0 2006.211.08:16:01.17#ibcon#wrote, iclass 23, count 0 2006.211.08:16:01.17#ibcon#about to read 3, iclass 23, count 0 2006.211.08:16:01.21#ibcon#read 3, iclass 23, count 0 2006.211.08:16:01.21#ibcon#about to read 4, iclass 23, count 0 2006.211.08:16:01.21#ibcon#read 4, iclass 23, count 0 2006.211.08:16:01.21#ibcon#about to read 5, iclass 23, count 0 2006.211.08:16:01.21#ibcon#read 5, iclass 23, count 0 2006.211.08:16:01.21#ibcon#about to read 6, iclass 23, count 0 2006.211.08:16:01.21#ibcon#read 6, iclass 23, count 0 2006.211.08:16:01.21#ibcon#end of sib2, iclass 23, count 0 2006.211.08:16:01.21#ibcon#*after write, iclass 23, count 0 2006.211.08:16:01.21#ibcon#*before return 0, iclass 23, count 0 2006.211.08:16:01.21#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:16:01.21#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:16:01.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:16:01.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:16:01.21$vc4f8/vb=4,3 2006.211.08:16:01.21#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.08:16:01.21#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.08:16:01.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:16:01.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:16:01.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:16:01.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:16:01.27#ibcon#enter wrdev, iclass 25, count 2 2006.211.08:16:01.27#ibcon#first serial, iclass 25, count 2 2006.211.08:16:01.27#ibcon#enter sib2, iclass 25, count 2 2006.211.08:16:01.27#ibcon#flushed, iclass 25, count 2 2006.211.08:16:01.27#ibcon#about to write, iclass 25, count 2 2006.211.08:16:01.27#ibcon#wrote, iclass 25, count 2 2006.211.08:16:01.27#ibcon#about to read 3, iclass 25, count 2 2006.211.08:16:01.29#ibcon#read 3, iclass 25, count 2 2006.211.08:16:01.29#ibcon#about to read 4, iclass 25, count 2 2006.211.08:16:01.29#ibcon#read 4, iclass 25, count 2 2006.211.08:16:01.29#ibcon#about to read 5, iclass 25, count 2 2006.211.08:16:01.29#ibcon#read 5, iclass 25, count 2 2006.211.08:16:01.29#ibcon#about to read 6, iclass 25, count 2 2006.211.08:16:01.29#ibcon#read 6, iclass 25, count 2 2006.211.08:16:01.29#ibcon#end of sib2, iclass 25, count 2 2006.211.08:16:01.29#ibcon#*mode == 0, iclass 25, count 2 2006.211.08:16:01.29#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.08:16:01.29#ibcon#[27=AT04-03\r\n] 2006.211.08:16:01.29#ibcon#*before write, iclass 25, count 2 2006.211.08:16:01.29#ibcon#enter sib2, iclass 25, count 2 2006.211.08:16:01.29#ibcon#flushed, iclass 25, count 2 2006.211.08:16:01.29#ibcon#about to write, iclass 25, count 2 2006.211.08:16:01.29#ibcon#wrote, iclass 25, count 2 2006.211.08:16:01.29#ibcon#about to read 3, iclass 25, count 2 2006.211.08:16:01.32#ibcon#read 3, iclass 25, count 2 2006.211.08:16:01.32#ibcon#about to read 4, iclass 25, count 2 2006.211.08:16:01.32#ibcon#read 4, iclass 25, count 2 2006.211.08:16:01.32#ibcon#about to read 5, iclass 25, count 2 2006.211.08:16:01.32#ibcon#read 5, iclass 25, count 2 2006.211.08:16:01.32#ibcon#about to read 6, iclass 25, count 2 2006.211.08:16:01.32#ibcon#read 6, iclass 25, count 2 2006.211.08:16:01.32#ibcon#end of sib2, iclass 25, count 2 2006.211.08:16:01.32#ibcon#*after write, iclass 25, count 2 2006.211.08:16:01.32#ibcon#*before return 0, iclass 25, count 2 2006.211.08:16:01.32#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:16:01.32#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:16:01.32#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.08:16:01.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:01.32#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:16:01.44#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:16:01.44#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:16:01.44#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:16:01.44#ibcon#first serial, iclass 25, count 0 2006.211.08:16:01.44#ibcon#enter sib2, iclass 25, count 0 2006.211.08:16:01.44#ibcon#flushed, iclass 25, count 0 2006.211.08:16:01.44#ibcon#about to write, iclass 25, count 0 2006.211.08:16:01.44#ibcon#wrote, iclass 25, count 0 2006.211.08:16:01.44#ibcon#about to read 3, iclass 25, count 0 2006.211.08:16:01.46#ibcon#read 3, iclass 25, count 0 2006.211.08:16:01.46#ibcon#about to read 4, iclass 25, count 0 2006.211.08:16:01.46#ibcon#read 4, iclass 25, count 0 2006.211.08:16:01.46#ibcon#about to read 5, iclass 25, count 0 2006.211.08:16:01.46#ibcon#read 5, iclass 25, count 0 2006.211.08:16:01.46#ibcon#about to read 6, iclass 25, count 0 2006.211.08:16:01.46#ibcon#read 6, iclass 25, count 0 2006.211.08:16:01.46#ibcon#end of sib2, iclass 25, count 0 2006.211.08:16:01.46#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:16:01.46#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:16:01.46#ibcon#[27=USB\r\n] 2006.211.08:16:01.46#ibcon#*before write, iclass 25, count 0 2006.211.08:16:01.46#ibcon#enter sib2, iclass 25, count 0 2006.211.08:16:01.46#ibcon#flushed, iclass 25, count 0 2006.211.08:16:01.46#ibcon#about to write, iclass 25, count 0 2006.211.08:16:01.46#ibcon#wrote, iclass 25, count 0 2006.211.08:16:01.46#ibcon#about to read 3, iclass 25, count 0 2006.211.08:16:01.49#ibcon#read 3, iclass 25, count 0 2006.211.08:16:01.49#ibcon#about to read 4, iclass 25, count 0 2006.211.08:16:01.49#ibcon#read 4, iclass 25, count 0 2006.211.08:16:01.49#ibcon#about to read 5, iclass 25, count 0 2006.211.08:16:01.49#ibcon#read 5, iclass 25, count 0 2006.211.08:16:01.49#ibcon#about to read 6, iclass 25, count 0 2006.211.08:16:01.49#ibcon#read 6, iclass 25, count 0 2006.211.08:16:01.49#ibcon#end of sib2, iclass 25, count 0 2006.211.08:16:01.49#ibcon#*after write, iclass 25, count 0 2006.211.08:16:01.49#ibcon#*before return 0, iclass 25, count 0 2006.211.08:16:01.49#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:16:01.49#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:16:01.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:16:01.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:16:01.49$vc4f8/vblo=5,744.99 2006.211.08:16:01.49#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.08:16:01.49#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.08:16:01.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:16:01.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:16:01.49#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:16:01.49#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:16:01.49#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:16:01.49#ibcon#first serial, iclass 27, count 0 2006.211.08:16:01.49#ibcon#enter sib2, iclass 27, count 0 2006.211.08:16:01.49#ibcon#flushed, iclass 27, count 0 2006.211.08:16:01.49#ibcon#about to write, iclass 27, count 0 2006.211.08:16:01.49#ibcon#wrote, iclass 27, count 0 2006.211.08:16:01.49#ibcon#about to read 3, iclass 27, count 0 2006.211.08:16:01.51#ibcon#read 3, iclass 27, count 0 2006.211.08:16:01.51#ibcon#about to read 4, iclass 27, count 0 2006.211.08:16:01.51#ibcon#read 4, iclass 27, count 0 2006.211.08:16:01.51#ibcon#about to read 5, iclass 27, count 0 2006.211.08:16:01.51#ibcon#read 5, iclass 27, count 0 2006.211.08:16:01.51#ibcon#about to read 6, iclass 27, count 0 2006.211.08:16:01.51#ibcon#read 6, iclass 27, count 0 2006.211.08:16:01.51#ibcon#end of sib2, iclass 27, count 0 2006.211.08:16:01.51#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:16:01.51#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:16:01.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:16:01.51#ibcon#*before write, iclass 27, count 0 2006.211.08:16:01.51#ibcon#enter sib2, iclass 27, count 0 2006.211.08:16:01.51#ibcon#flushed, iclass 27, count 0 2006.211.08:16:01.51#ibcon#about to write, iclass 27, count 0 2006.211.08:16:01.51#ibcon#wrote, iclass 27, count 0 2006.211.08:16:01.51#ibcon#about to read 3, iclass 27, count 0 2006.211.08:16:01.55#ibcon#read 3, iclass 27, count 0 2006.211.08:16:01.55#ibcon#about to read 4, iclass 27, count 0 2006.211.08:16:01.55#ibcon#read 4, iclass 27, count 0 2006.211.08:16:01.55#ibcon#about to read 5, iclass 27, count 0 2006.211.08:16:01.55#ibcon#read 5, iclass 27, count 0 2006.211.08:16:01.55#ibcon#about to read 6, iclass 27, count 0 2006.211.08:16:01.55#ibcon#read 6, iclass 27, count 0 2006.211.08:16:01.55#ibcon#end of sib2, iclass 27, count 0 2006.211.08:16:01.55#ibcon#*after write, iclass 27, count 0 2006.211.08:16:01.55#ibcon#*before return 0, iclass 27, count 0 2006.211.08:16:01.55#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:16:01.55#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:16:01.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:16:01.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:16:01.55$vc4f8/vb=5,3 2006.211.08:16:01.55#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.211.08:16:01.55#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.211.08:16:01.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:16:01.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:16:01.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:16:01.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:16:01.61#ibcon#enter wrdev, iclass 29, count 2 2006.211.08:16:01.61#ibcon#first serial, iclass 29, count 2 2006.211.08:16:01.61#ibcon#enter sib2, iclass 29, count 2 2006.211.08:16:01.61#ibcon#flushed, iclass 29, count 2 2006.211.08:16:01.61#ibcon#about to write, iclass 29, count 2 2006.211.08:16:01.61#ibcon#wrote, iclass 29, count 2 2006.211.08:16:01.61#ibcon#about to read 3, iclass 29, count 2 2006.211.08:16:01.63#ibcon#read 3, iclass 29, count 2 2006.211.08:16:01.63#ibcon#about to read 4, iclass 29, count 2 2006.211.08:16:01.63#ibcon#read 4, iclass 29, count 2 2006.211.08:16:01.63#ibcon#about to read 5, iclass 29, count 2 2006.211.08:16:01.63#ibcon#read 5, iclass 29, count 2 2006.211.08:16:01.63#ibcon#about to read 6, iclass 29, count 2 2006.211.08:16:01.63#ibcon#read 6, iclass 29, count 2 2006.211.08:16:01.63#ibcon#end of sib2, iclass 29, count 2 2006.211.08:16:01.63#ibcon#*mode == 0, iclass 29, count 2 2006.211.08:16:01.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.211.08:16:01.63#ibcon#[27=AT05-03\r\n] 2006.211.08:16:01.63#ibcon#*before write, iclass 29, count 2 2006.211.08:16:01.63#ibcon#enter sib2, iclass 29, count 2 2006.211.08:16:01.63#ibcon#flushed, iclass 29, count 2 2006.211.08:16:01.63#ibcon#about to write, iclass 29, count 2 2006.211.08:16:01.63#ibcon#wrote, iclass 29, count 2 2006.211.08:16:01.63#ibcon#about to read 3, iclass 29, count 2 2006.211.08:16:01.66#ibcon#read 3, iclass 29, count 2 2006.211.08:16:01.66#ibcon#about to read 4, iclass 29, count 2 2006.211.08:16:01.66#ibcon#read 4, iclass 29, count 2 2006.211.08:16:01.66#ibcon#about to read 5, iclass 29, count 2 2006.211.08:16:01.66#ibcon#read 5, iclass 29, count 2 2006.211.08:16:01.66#ibcon#about to read 6, iclass 29, count 2 2006.211.08:16:01.66#ibcon#read 6, iclass 29, count 2 2006.211.08:16:01.66#ibcon#end of sib2, iclass 29, count 2 2006.211.08:16:01.66#ibcon#*after write, iclass 29, count 2 2006.211.08:16:01.66#ibcon#*before return 0, iclass 29, count 2 2006.211.08:16:01.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:16:01.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.211.08:16:01.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.211.08:16:01.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:01.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:16:01.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:16:01.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:16:01.78#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:16:01.78#ibcon#first serial, iclass 29, count 0 2006.211.08:16:01.78#ibcon#enter sib2, iclass 29, count 0 2006.211.08:16:01.78#ibcon#flushed, iclass 29, count 0 2006.211.08:16:01.78#ibcon#about to write, iclass 29, count 0 2006.211.08:16:01.78#ibcon#wrote, iclass 29, count 0 2006.211.08:16:01.78#ibcon#about to read 3, iclass 29, count 0 2006.211.08:16:01.80#ibcon#read 3, iclass 29, count 0 2006.211.08:16:01.80#ibcon#about to read 4, iclass 29, count 0 2006.211.08:16:01.80#ibcon#read 4, iclass 29, count 0 2006.211.08:16:01.80#ibcon#about to read 5, iclass 29, count 0 2006.211.08:16:01.80#ibcon#read 5, iclass 29, count 0 2006.211.08:16:01.80#ibcon#about to read 6, iclass 29, count 0 2006.211.08:16:01.80#ibcon#read 6, iclass 29, count 0 2006.211.08:16:01.80#ibcon#end of sib2, iclass 29, count 0 2006.211.08:16:01.80#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:16:01.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:16:01.80#ibcon#[27=USB\r\n] 2006.211.08:16:01.80#ibcon#*before write, iclass 29, count 0 2006.211.08:16:01.80#ibcon#enter sib2, iclass 29, count 0 2006.211.08:16:01.80#ibcon#flushed, iclass 29, count 0 2006.211.08:16:01.80#ibcon#about to write, iclass 29, count 0 2006.211.08:16:01.80#ibcon#wrote, iclass 29, count 0 2006.211.08:16:01.80#ibcon#about to read 3, iclass 29, count 0 2006.211.08:16:01.83#ibcon#read 3, iclass 29, count 0 2006.211.08:16:01.83#ibcon#about to read 4, iclass 29, count 0 2006.211.08:16:01.83#ibcon#read 4, iclass 29, count 0 2006.211.08:16:01.83#ibcon#about to read 5, iclass 29, count 0 2006.211.08:16:01.83#ibcon#read 5, iclass 29, count 0 2006.211.08:16:01.83#ibcon#about to read 6, iclass 29, count 0 2006.211.08:16:01.83#ibcon#read 6, iclass 29, count 0 2006.211.08:16:01.83#ibcon#end of sib2, iclass 29, count 0 2006.211.08:16:01.83#ibcon#*after write, iclass 29, count 0 2006.211.08:16:01.83#ibcon#*before return 0, iclass 29, count 0 2006.211.08:16:01.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:16:01.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.211.08:16:01.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:16:01.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:16:01.83$vc4f8/vblo=6,752.99 2006.211.08:16:01.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.08:16:01.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.08:16:01.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:16:01.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:16:01.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:16:01.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:16:01.83#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:16:01.83#ibcon#first serial, iclass 31, count 0 2006.211.08:16:01.83#ibcon#enter sib2, iclass 31, count 0 2006.211.08:16:01.83#ibcon#flushed, iclass 31, count 0 2006.211.08:16:01.83#ibcon#about to write, iclass 31, count 0 2006.211.08:16:01.83#ibcon#wrote, iclass 31, count 0 2006.211.08:16:01.83#ibcon#about to read 3, iclass 31, count 0 2006.211.08:16:01.85#ibcon#read 3, iclass 31, count 0 2006.211.08:16:01.85#ibcon#about to read 4, iclass 31, count 0 2006.211.08:16:01.85#ibcon#read 4, iclass 31, count 0 2006.211.08:16:01.85#ibcon#about to read 5, iclass 31, count 0 2006.211.08:16:01.85#ibcon#read 5, iclass 31, count 0 2006.211.08:16:01.85#ibcon#about to read 6, iclass 31, count 0 2006.211.08:16:01.85#ibcon#read 6, iclass 31, count 0 2006.211.08:16:01.85#ibcon#end of sib2, iclass 31, count 0 2006.211.08:16:01.85#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:16:01.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:16:01.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:16:01.85#ibcon#*before write, iclass 31, count 0 2006.211.08:16:01.85#ibcon#enter sib2, iclass 31, count 0 2006.211.08:16:01.85#ibcon#flushed, iclass 31, count 0 2006.211.08:16:01.85#ibcon#about to write, iclass 31, count 0 2006.211.08:16:01.85#ibcon#wrote, iclass 31, count 0 2006.211.08:16:01.85#ibcon#about to read 3, iclass 31, count 0 2006.211.08:16:01.89#ibcon#read 3, iclass 31, count 0 2006.211.08:16:01.89#ibcon#about to read 4, iclass 31, count 0 2006.211.08:16:01.89#ibcon#read 4, iclass 31, count 0 2006.211.08:16:01.89#ibcon#about to read 5, iclass 31, count 0 2006.211.08:16:01.89#ibcon#read 5, iclass 31, count 0 2006.211.08:16:01.89#ibcon#about to read 6, iclass 31, count 0 2006.211.08:16:01.89#ibcon#read 6, iclass 31, count 0 2006.211.08:16:01.89#ibcon#end of sib2, iclass 31, count 0 2006.211.08:16:01.89#ibcon#*after write, iclass 31, count 0 2006.211.08:16:01.89#ibcon#*before return 0, iclass 31, count 0 2006.211.08:16:01.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:16:01.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:16:01.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:16:01.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:16:01.89$vc4f8/vb=6,3 2006.211.08:16:01.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.08:16:01.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.08:16:01.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:16:01.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:16:01.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:16:01.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:16:01.95#ibcon#enter wrdev, iclass 33, count 2 2006.211.08:16:01.95#ibcon#first serial, iclass 33, count 2 2006.211.08:16:01.95#ibcon#enter sib2, iclass 33, count 2 2006.211.08:16:01.95#ibcon#flushed, iclass 33, count 2 2006.211.08:16:01.95#ibcon#about to write, iclass 33, count 2 2006.211.08:16:01.95#ibcon#wrote, iclass 33, count 2 2006.211.08:16:01.95#ibcon#about to read 3, iclass 33, count 2 2006.211.08:16:01.97#ibcon#read 3, iclass 33, count 2 2006.211.08:16:01.97#ibcon#about to read 4, iclass 33, count 2 2006.211.08:16:01.97#ibcon#read 4, iclass 33, count 2 2006.211.08:16:01.97#ibcon#about to read 5, iclass 33, count 2 2006.211.08:16:01.97#ibcon#read 5, iclass 33, count 2 2006.211.08:16:01.97#ibcon#about to read 6, iclass 33, count 2 2006.211.08:16:01.97#ibcon#read 6, iclass 33, count 2 2006.211.08:16:01.97#ibcon#end of sib2, iclass 33, count 2 2006.211.08:16:01.97#ibcon#*mode == 0, iclass 33, count 2 2006.211.08:16:01.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.08:16:01.97#ibcon#[27=AT06-03\r\n] 2006.211.08:16:01.97#ibcon#*before write, iclass 33, count 2 2006.211.08:16:01.97#ibcon#enter sib2, iclass 33, count 2 2006.211.08:16:01.97#ibcon#flushed, iclass 33, count 2 2006.211.08:16:01.97#ibcon#about to write, iclass 33, count 2 2006.211.08:16:01.97#ibcon#wrote, iclass 33, count 2 2006.211.08:16:01.97#ibcon#about to read 3, iclass 33, count 2 2006.211.08:16:02.00#ibcon#read 3, iclass 33, count 2 2006.211.08:16:02.00#ibcon#about to read 4, iclass 33, count 2 2006.211.08:16:02.00#ibcon#read 4, iclass 33, count 2 2006.211.08:16:02.00#ibcon#about to read 5, iclass 33, count 2 2006.211.08:16:02.00#ibcon#read 5, iclass 33, count 2 2006.211.08:16:02.00#ibcon#about to read 6, iclass 33, count 2 2006.211.08:16:02.00#ibcon#read 6, iclass 33, count 2 2006.211.08:16:02.00#ibcon#end of sib2, iclass 33, count 2 2006.211.08:16:02.00#ibcon#*after write, iclass 33, count 2 2006.211.08:16:02.00#ibcon#*before return 0, iclass 33, count 2 2006.211.08:16:02.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:16:02.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:16:02.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.08:16:02.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:16:02.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:16:02.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:16:02.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:16:02.12#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:16:02.12#ibcon#first serial, iclass 33, count 0 2006.211.08:16:02.12#ibcon#enter sib2, iclass 33, count 0 2006.211.08:16:02.12#ibcon#flushed, iclass 33, count 0 2006.211.08:16:02.12#ibcon#about to write, iclass 33, count 0 2006.211.08:16:02.12#ibcon#wrote, iclass 33, count 0 2006.211.08:16:02.12#ibcon#about to read 3, iclass 33, count 0 2006.211.08:16:02.14#ibcon#read 3, iclass 33, count 0 2006.211.08:16:02.14#ibcon#about to read 4, iclass 33, count 0 2006.211.08:16:02.14#ibcon#read 4, iclass 33, count 0 2006.211.08:16:02.14#ibcon#about to read 5, iclass 33, count 0 2006.211.08:16:02.14#ibcon#read 5, iclass 33, count 0 2006.211.08:16:02.14#ibcon#about to read 6, iclass 33, count 0 2006.211.08:16:02.14#ibcon#read 6, iclass 33, count 0 2006.211.08:16:02.14#ibcon#end of sib2, iclass 33, count 0 2006.211.08:16:02.14#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:16:02.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:16:02.14#ibcon#[27=USB\r\n] 2006.211.08:16:02.14#ibcon#*before write, iclass 33, count 0 2006.211.08:16:02.14#ibcon#enter sib2, iclass 33, count 0 2006.211.08:16:02.14#ibcon#flushed, iclass 33, count 0 2006.211.08:16:02.14#ibcon#about to write, iclass 33, count 0 2006.211.08:16:02.14#ibcon#wrote, iclass 33, count 0 2006.211.08:16:02.14#ibcon#about to read 3, iclass 33, count 0 2006.211.08:16:02.17#ibcon#read 3, iclass 33, count 0 2006.211.08:16:02.17#ibcon#about to read 4, iclass 33, count 0 2006.211.08:16:02.17#ibcon#read 4, iclass 33, count 0 2006.211.08:16:02.17#ibcon#about to read 5, iclass 33, count 0 2006.211.08:16:02.17#ibcon#read 5, iclass 33, count 0 2006.211.08:16:02.17#ibcon#about to read 6, iclass 33, count 0 2006.211.08:16:02.17#ibcon#read 6, iclass 33, count 0 2006.211.08:16:02.17#ibcon#end of sib2, iclass 33, count 0 2006.211.08:16:02.17#ibcon#*after write, iclass 33, count 0 2006.211.08:16:02.17#ibcon#*before return 0, iclass 33, count 0 2006.211.08:16:02.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:16:02.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:16:02.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:16:02.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:16:02.17$vc4f8/vabw=wide 2006.211.08:16:02.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.08:16:02.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.08:16:02.17#ibcon#ireg 8 cls_cnt 0 2006.211.08:16:02.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:16:02.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:16:02.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:16:02.17#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:16:02.17#ibcon#first serial, iclass 35, count 0 2006.211.08:16:02.17#ibcon#enter sib2, iclass 35, count 0 2006.211.08:16:02.17#ibcon#flushed, iclass 35, count 0 2006.211.08:16:02.17#ibcon#about to write, iclass 35, count 0 2006.211.08:16:02.17#ibcon#wrote, iclass 35, count 0 2006.211.08:16:02.17#ibcon#about to read 3, iclass 35, count 0 2006.211.08:16:02.19#ibcon#read 3, iclass 35, count 0 2006.211.08:16:02.19#ibcon#about to read 4, iclass 35, count 0 2006.211.08:16:02.19#ibcon#read 4, iclass 35, count 0 2006.211.08:16:02.19#ibcon#about to read 5, iclass 35, count 0 2006.211.08:16:02.19#ibcon#read 5, iclass 35, count 0 2006.211.08:16:02.19#ibcon#about to read 6, iclass 35, count 0 2006.211.08:16:02.19#ibcon#read 6, iclass 35, count 0 2006.211.08:16:02.19#ibcon#end of sib2, iclass 35, count 0 2006.211.08:16:02.19#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:16:02.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:16:02.19#ibcon#[25=BW32\r\n] 2006.211.08:16:02.19#ibcon#*before write, iclass 35, count 0 2006.211.08:16:02.19#ibcon#enter sib2, iclass 35, count 0 2006.211.08:16:02.19#ibcon#flushed, iclass 35, count 0 2006.211.08:16:02.19#ibcon#about to write, iclass 35, count 0 2006.211.08:16:02.19#ibcon#wrote, iclass 35, count 0 2006.211.08:16:02.19#ibcon#about to read 3, iclass 35, count 0 2006.211.08:16:02.22#ibcon#read 3, iclass 35, count 0 2006.211.08:16:02.22#ibcon#about to read 4, iclass 35, count 0 2006.211.08:16:02.22#ibcon#read 4, iclass 35, count 0 2006.211.08:16:02.22#ibcon#about to read 5, iclass 35, count 0 2006.211.08:16:02.22#ibcon#read 5, iclass 35, count 0 2006.211.08:16:02.22#ibcon#about to read 6, iclass 35, count 0 2006.211.08:16:02.22#ibcon#read 6, iclass 35, count 0 2006.211.08:16:02.22#ibcon#end of sib2, iclass 35, count 0 2006.211.08:16:02.22#ibcon#*after write, iclass 35, count 0 2006.211.08:16:02.22#ibcon#*before return 0, iclass 35, count 0 2006.211.08:16:02.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:16:02.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:16:02.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:16:02.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:16:02.22$vc4f8/vbbw=wide 2006.211.08:16:02.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:16:02.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:16:02.22#ibcon#ireg 8 cls_cnt 0 2006.211.08:16:02.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:16:02.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:16:02.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:16:02.29#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:16:02.29#ibcon#first serial, iclass 37, count 0 2006.211.08:16:02.29#ibcon#enter sib2, iclass 37, count 0 2006.211.08:16:02.29#ibcon#flushed, iclass 37, count 0 2006.211.08:16:02.29#ibcon#about to write, iclass 37, count 0 2006.211.08:16:02.29#ibcon#wrote, iclass 37, count 0 2006.211.08:16:02.29#ibcon#about to read 3, iclass 37, count 0 2006.211.08:16:02.31#ibcon#read 3, iclass 37, count 0 2006.211.08:16:02.31#ibcon#about to read 4, iclass 37, count 0 2006.211.08:16:02.31#ibcon#read 4, iclass 37, count 0 2006.211.08:16:02.31#ibcon#about to read 5, iclass 37, count 0 2006.211.08:16:02.31#ibcon#read 5, iclass 37, count 0 2006.211.08:16:02.31#ibcon#about to read 6, iclass 37, count 0 2006.211.08:16:02.31#ibcon#read 6, iclass 37, count 0 2006.211.08:16:02.31#ibcon#end of sib2, iclass 37, count 0 2006.211.08:16:02.31#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:16:02.31#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:16:02.31#ibcon#[27=BW32\r\n] 2006.211.08:16:02.31#ibcon#*before write, iclass 37, count 0 2006.211.08:16:02.31#ibcon#enter sib2, iclass 37, count 0 2006.211.08:16:02.31#ibcon#flushed, iclass 37, count 0 2006.211.08:16:02.31#ibcon#about to write, iclass 37, count 0 2006.211.08:16:02.31#ibcon#wrote, iclass 37, count 0 2006.211.08:16:02.31#ibcon#about to read 3, iclass 37, count 0 2006.211.08:16:02.34#ibcon#read 3, iclass 37, count 0 2006.211.08:16:02.34#ibcon#about to read 4, iclass 37, count 0 2006.211.08:16:02.34#ibcon#read 4, iclass 37, count 0 2006.211.08:16:02.34#ibcon#about to read 5, iclass 37, count 0 2006.211.08:16:02.34#ibcon#read 5, iclass 37, count 0 2006.211.08:16:02.34#ibcon#about to read 6, iclass 37, count 0 2006.211.08:16:02.34#ibcon#read 6, iclass 37, count 0 2006.211.08:16:02.34#ibcon#end of sib2, iclass 37, count 0 2006.211.08:16:02.34#ibcon#*after write, iclass 37, count 0 2006.211.08:16:02.34#ibcon#*before return 0, iclass 37, count 0 2006.211.08:16:02.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:16:02.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:16:02.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:16:02.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:16:02.34$4f8m12a/ifd4f 2006.211.08:16:02.34$ifd4f/lo= 2006.211.08:16:02.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:16:02.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:16:02.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:16:02.34$ifd4f/patch= 2006.211.08:16:02.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:16:02.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:16:02.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:16:02.34$4f8m12a/"form=m,16.000,1:2 2006.211.08:16:02.34$4f8m12a/"tpicd 2006.211.08:16:02.34$4f8m12a/echo=off 2006.211.08:16:02.34$4f8m12a/xlog=off 2006.211.08:16:02.34:!2006.211.08:16:30 2006.211.08:16:12.14#trakl#Source acquired 2006.211.08:16:12.14#flagr#flagr/antenna,acquired 2006.211.08:16:30.00:preob 2006.211.08:16:31.14/onsource/TRACKING 2006.211.08:16:31.14:!2006.211.08:16:40 2006.211.08:16:40.00:data_valid=on 2006.211.08:16:40.00:midob 2006.211.08:16:40.14/onsource/TRACKING 2006.211.08:16:40.14/wx/24.44,1010.1,80 2006.211.08:16:40.35/cable/+6.4386E-03 2006.211.08:16:41.44/va/01,08,usb,yes,28,30 2006.211.08:16:41.44/va/02,07,usb,yes,29,30 2006.211.08:16:41.44/va/03,06,usb,yes,30,30 2006.211.08:16:41.44/va/04,07,usb,yes,29,32 2006.211.08:16:41.44/va/05,07,usb,yes,32,33 2006.211.08:16:41.44/va/06,06,usb,yes,31,30 2006.211.08:16:41.44/va/07,06,usb,yes,31,31 2006.211.08:16:41.44/va/08,07,usb,yes,30,29 2006.211.08:16:41.67/valo/01,532.99,yes,locked 2006.211.08:16:41.67/valo/02,572.99,yes,locked 2006.211.08:16:41.67/valo/03,672.99,yes,locked 2006.211.08:16:41.67/valo/04,832.99,yes,locked 2006.211.08:16:41.67/valo/05,652.99,yes,locked 2006.211.08:16:41.67/valo/06,772.99,yes,locked 2006.211.08:16:41.67/valo/07,832.99,yes,locked 2006.211.08:16:41.67/valo/08,852.99,yes,locked 2006.211.08:16:42.76/vb/01,04,usb,yes,28,27 2006.211.08:16:42.76/vb/02,04,usb,yes,30,31 2006.211.08:16:42.76/vb/03,03,usb,yes,33,37 2006.211.08:16:42.76/vb/04,03,usb,yes,34,34 2006.211.08:16:42.76/vb/05,03,usb,yes,32,36 2006.211.08:16:42.76/vb/06,03,usb,yes,33,36 2006.211.08:16:42.76/vb/07,04,usb,yes,29,28 2006.211.08:16:42.76/vb/08,03,usb,yes,33,36 2006.211.08:16:42.99/vblo/01,632.99,yes,locked 2006.211.08:16:42.99/vblo/02,640.99,yes,locked 2006.211.08:16:42.99/vblo/03,656.99,yes,locked 2006.211.08:16:42.99/vblo/04,712.99,yes,locked 2006.211.08:16:42.99/vblo/05,744.99,yes,locked 2006.211.08:16:42.99/vblo/06,752.99,yes,locked 2006.211.08:16:42.99/vblo/07,734.99,yes,locked 2006.211.08:16:42.99/vblo/08,744.99,yes,locked 2006.211.08:16:43.14/vabw/8 2006.211.08:16:43.29/vbbw/8 2006.211.08:16:43.38/xfe/off,on,12.0 2006.211.08:16:43.75/ifatt/23,28,28,28 2006.211.08:16:44.08/fmout-gps/S +4.43E-07 2006.211.08:16:44.12:!2006.211.08:17:40 2006.211.08:17:01.14#trakl#Off source 2006.211.08:17:01.14?ERROR st -7 Antenna off-source! 2006.211.08:17:01.14#trakl#az 13.065 el 41.511 azerr*cos(el) 0.0020 elerr 0.0192 2006.211.08:17:03.14#flagr#flagr/antenna,off-source 2006.211.08:17:14.14#trakl#Source re-acquired 2006.211.08:17:15.14#flagr#flagr/antenna,re-acquired 2006.211.08:17:40.01:data_valid=off 2006.211.08:17:40.01:postob 2006.211.08:17:40.13/cable/+6.4401E-03 2006.211.08:17:40.13/wx/24.41,1010.1,80 2006.211.08:17:41.08/fmout-gps/S +4.42E-07 2006.211.08:17:41.08:scan_name=211-0819,k06211,70 2006.211.08:17:41.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.211.08:17:41.14#flagr#flagr/antenna,new-source 2006.211.08:17:42.14:checkk5 2006.211.08:17:42.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:17:42.83/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:17:43.17/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:17:43.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:17:43.84/chk_obsdata//k5ts1/T2110816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:17:44.18/chk_obsdata//k5ts2/T2110816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:17:44.51/chk_obsdata//k5ts3/T2110816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:17:44.84/chk_obsdata//k5ts4/T2110816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:17:45.49/k5log//k5ts1_log_newline 2006.211.08:17:46.16/k5log//k5ts2_log_newline 2006.211.08:17:46.82/k5log//k5ts3_log_newline 2006.211.08:17:47.48/k5log//k5ts4_log_newline 2006.211.08:17:47.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:17:47.51:4f8m12a=2 2006.211.08:17:47.51$4f8m12a/echo=on 2006.211.08:17:47.51$4f8m12a/pcalon 2006.211.08:17:47.51$pcalon/"no phase cal control is implemented here 2006.211.08:17:47.51$4f8m12a/"tpicd=stop 2006.211.08:17:47.51$4f8m12a/vc4f8 2006.211.08:17:47.51$vc4f8/valo=1,532.99 2006.211.08:17:47.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:17:47.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:17:47.51#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:47.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:47.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:47.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:47.51#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:17:47.51#ibcon#first serial, iclass 3, count 0 2006.211.08:17:47.51#ibcon#enter sib2, iclass 3, count 0 2006.211.08:17:47.51#ibcon#flushed, iclass 3, count 0 2006.211.08:17:47.51#ibcon#about to write, iclass 3, count 0 2006.211.08:17:47.51#ibcon#wrote, iclass 3, count 0 2006.211.08:17:47.51#ibcon#about to read 3, iclass 3, count 0 2006.211.08:17:47.53#ibcon#read 3, iclass 3, count 0 2006.211.08:17:47.53#ibcon#about to read 4, iclass 3, count 0 2006.211.08:17:47.53#ibcon#read 4, iclass 3, count 0 2006.211.08:17:47.53#ibcon#about to read 5, iclass 3, count 0 2006.211.08:17:47.53#ibcon#read 5, iclass 3, count 0 2006.211.08:17:47.53#ibcon#about to read 6, iclass 3, count 0 2006.211.08:17:47.53#ibcon#read 6, iclass 3, count 0 2006.211.08:17:47.53#ibcon#end of sib2, iclass 3, count 0 2006.211.08:17:47.53#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:17:47.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:17:47.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:17:47.53#ibcon#*before write, iclass 3, count 0 2006.211.08:17:47.53#ibcon#enter sib2, iclass 3, count 0 2006.211.08:17:47.53#ibcon#flushed, iclass 3, count 0 2006.211.08:17:47.53#ibcon#about to write, iclass 3, count 0 2006.211.08:17:47.53#ibcon#wrote, iclass 3, count 0 2006.211.08:17:47.53#ibcon#about to read 3, iclass 3, count 0 2006.211.08:17:47.58#ibcon#read 3, iclass 3, count 0 2006.211.08:17:47.58#ibcon#about to read 4, iclass 3, count 0 2006.211.08:17:47.58#ibcon#read 4, iclass 3, count 0 2006.211.08:17:47.58#ibcon#about to read 5, iclass 3, count 0 2006.211.08:17:47.58#ibcon#read 5, iclass 3, count 0 2006.211.08:17:47.58#ibcon#about to read 6, iclass 3, count 0 2006.211.08:17:47.58#ibcon#read 6, iclass 3, count 0 2006.211.08:17:47.58#ibcon#end of sib2, iclass 3, count 0 2006.211.08:17:47.58#ibcon#*after write, iclass 3, count 0 2006.211.08:17:47.58#ibcon#*before return 0, iclass 3, count 0 2006.211.08:17:47.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:47.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:47.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:17:47.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:17:47.58$vc4f8/va=1,8 2006.211.08:17:47.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:17:47.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:17:47.58#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:47.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:47.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:47.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:47.58#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:17:47.58#ibcon#first serial, iclass 5, count 2 2006.211.08:17:47.58#ibcon#enter sib2, iclass 5, count 2 2006.211.08:17:47.58#ibcon#flushed, iclass 5, count 2 2006.211.08:17:47.58#ibcon#about to write, iclass 5, count 2 2006.211.08:17:47.58#ibcon#wrote, iclass 5, count 2 2006.211.08:17:47.58#ibcon#about to read 3, iclass 5, count 2 2006.211.08:17:47.60#ibcon#read 3, iclass 5, count 2 2006.211.08:17:47.60#ibcon#about to read 4, iclass 5, count 2 2006.211.08:17:47.60#ibcon#read 4, iclass 5, count 2 2006.211.08:17:47.60#ibcon#about to read 5, iclass 5, count 2 2006.211.08:17:47.60#ibcon#read 5, iclass 5, count 2 2006.211.08:17:47.60#ibcon#about to read 6, iclass 5, count 2 2006.211.08:17:47.60#ibcon#read 6, iclass 5, count 2 2006.211.08:17:47.60#ibcon#end of sib2, iclass 5, count 2 2006.211.08:17:47.60#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:17:47.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:17:47.60#ibcon#[25=AT01-08\r\n] 2006.211.08:17:47.60#ibcon#*before write, iclass 5, count 2 2006.211.08:17:47.60#ibcon#enter sib2, iclass 5, count 2 2006.211.08:17:47.60#ibcon#flushed, iclass 5, count 2 2006.211.08:17:47.60#ibcon#about to write, iclass 5, count 2 2006.211.08:17:47.60#ibcon#wrote, iclass 5, count 2 2006.211.08:17:47.60#ibcon#about to read 3, iclass 5, count 2 2006.211.08:17:47.63#ibcon#read 3, iclass 5, count 2 2006.211.08:17:47.63#ibcon#about to read 4, iclass 5, count 2 2006.211.08:17:47.63#ibcon#read 4, iclass 5, count 2 2006.211.08:17:47.63#ibcon#about to read 5, iclass 5, count 2 2006.211.08:17:47.63#ibcon#read 5, iclass 5, count 2 2006.211.08:17:47.63#ibcon#about to read 6, iclass 5, count 2 2006.211.08:17:47.63#ibcon#read 6, iclass 5, count 2 2006.211.08:17:47.63#ibcon#end of sib2, iclass 5, count 2 2006.211.08:17:47.63#ibcon#*after write, iclass 5, count 2 2006.211.08:17:47.63#ibcon#*before return 0, iclass 5, count 2 2006.211.08:17:47.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:47.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:47.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:17:47.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:47.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:47.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:47.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:47.75#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:17:47.75#ibcon#first serial, iclass 5, count 0 2006.211.08:17:47.75#ibcon#enter sib2, iclass 5, count 0 2006.211.08:17:47.75#ibcon#flushed, iclass 5, count 0 2006.211.08:17:47.75#ibcon#about to write, iclass 5, count 0 2006.211.08:17:47.75#ibcon#wrote, iclass 5, count 0 2006.211.08:17:47.75#ibcon#about to read 3, iclass 5, count 0 2006.211.08:17:47.77#ibcon#read 3, iclass 5, count 0 2006.211.08:17:47.77#ibcon#about to read 4, iclass 5, count 0 2006.211.08:17:47.77#ibcon#read 4, iclass 5, count 0 2006.211.08:17:47.77#ibcon#about to read 5, iclass 5, count 0 2006.211.08:17:47.77#ibcon#read 5, iclass 5, count 0 2006.211.08:17:47.77#ibcon#about to read 6, iclass 5, count 0 2006.211.08:17:47.77#ibcon#read 6, iclass 5, count 0 2006.211.08:17:47.77#ibcon#end of sib2, iclass 5, count 0 2006.211.08:17:47.77#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:17:47.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:17:47.77#ibcon#[25=USB\r\n] 2006.211.08:17:47.77#ibcon#*before write, iclass 5, count 0 2006.211.08:17:47.77#ibcon#enter sib2, iclass 5, count 0 2006.211.08:17:47.77#ibcon#flushed, iclass 5, count 0 2006.211.08:17:47.77#ibcon#about to write, iclass 5, count 0 2006.211.08:17:47.77#ibcon#wrote, iclass 5, count 0 2006.211.08:17:47.77#ibcon#about to read 3, iclass 5, count 0 2006.211.08:17:47.80#ibcon#read 3, iclass 5, count 0 2006.211.08:17:47.80#ibcon#about to read 4, iclass 5, count 0 2006.211.08:17:47.80#ibcon#read 4, iclass 5, count 0 2006.211.08:17:47.80#ibcon#about to read 5, iclass 5, count 0 2006.211.08:17:47.80#ibcon#read 5, iclass 5, count 0 2006.211.08:17:47.80#ibcon#about to read 6, iclass 5, count 0 2006.211.08:17:47.80#ibcon#read 6, iclass 5, count 0 2006.211.08:17:47.80#ibcon#end of sib2, iclass 5, count 0 2006.211.08:17:47.80#ibcon#*after write, iclass 5, count 0 2006.211.08:17:47.80#ibcon#*before return 0, iclass 5, count 0 2006.211.08:17:47.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:47.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:47.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:17:47.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:17:47.80$vc4f8/valo=2,572.99 2006.211.08:17:47.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:17:47.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:17:47.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:47.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:47.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:47.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:47.80#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:17:47.80#ibcon#first serial, iclass 7, count 0 2006.211.08:17:47.80#ibcon#enter sib2, iclass 7, count 0 2006.211.08:17:47.80#ibcon#flushed, iclass 7, count 0 2006.211.08:17:47.80#ibcon#about to write, iclass 7, count 0 2006.211.08:17:47.80#ibcon#wrote, iclass 7, count 0 2006.211.08:17:47.80#ibcon#about to read 3, iclass 7, count 0 2006.211.08:17:47.82#ibcon#read 3, iclass 7, count 0 2006.211.08:17:47.82#ibcon#about to read 4, iclass 7, count 0 2006.211.08:17:47.82#ibcon#read 4, iclass 7, count 0 2006.211.08:17:47.82#ibcon#about to read 5, iclass 7, count 0 2006.211.08:17:47.82#ibcon#read 5, iclass 7, count 0 2006.211.08:17:47.82#ibcon#about to read 6, iclass 7, count 0 2006.211.08:17:47.82#ibcon#read 6, iclass 7, count 0 2006.211.08:17:47.82#ibcon#end of sib2, iclass 7, count 0 2006.211.08:17:47.82#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:17:47.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:17:47.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:17:47.82#ibcon#*before write, iclass 7, count 0 2006.211.08:17:47.82#ibcon#enter sib2, iclass 7, count 0 2006.211.08:17:47.82#ibcon#flushed, iclass 7, count 0 2006.211.08:17:47.82#ibcon#about to write, iclass 7, count 0 2006.211.08:17:47.82#ibcon#wrote, iclass 7, count 0 2006.211.08:17:47.82#ibcon#about to read 3, iclass 7, count 0 2006.211.08:17:47.86#ibcon#read 3, iclass 7, count 0 2006.211.08:17:47.86#ibcon#about to read 4, iclass 7, count 0 2006.211.08:17:47.86#ibcon#read 4, iclass 7, count 0 2006.211.08:17:47.86#ibcon#about to read 5, iclass 7, count 0 2006.211.08:17:47.86#ibcon#read 5, iclass 7, count 0 2006.211.08:17:47.86#ibcon#about to read 6, iclass 7, count 0 2006.211.08:17:47.86#ibcon#read 6, iclass 7, count 0 2006.211.08:17:47.86#ibcon#end of sib2, iclass 7, count 0 2006.211.08:17:47.86#ibcon#*after write, iclass 7, count 0 2006.211.08:17:47.86#ibcon#*before return 0, iclass 7, count 0 2006.211.08:17:47.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:47.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:47.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:17:47.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:17:47.86$vc4f8/va=2,7 2006.211.08:17:47.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:17:47.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:17:47.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:47.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:47.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:47.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:47.92#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:17:47.92#ibcon#first serial, iclass 11, count 2 2006.211.08:17:47.92#ibcon#enter sib2, iclass 11, count 2 2006.211.08:17:47.92#ibcon#flushed, iclass 11, count 2 2006.211.08:17:47.92#ibcon#about to write, iclass 11, count 2 2006.211.08:17:47.92#ibcon#wrote, iclass 11, count 2 2006.211.08:17:47.92#ibcon#about to read 3, iclass 11, count 2 2006.211.08:17:47.94#ibcon#read 3, iclass 11, count 2 2006.211.08:17:47.94#ibcon#about to read 4, iclass 11, count 2 2006.211.08:17:47.94#ibcon#read 4, iclass 11, count 2 2006.211.08:17:47.94#ibcon#about to read 5, iclass 11, count 2 2006.211.08:17:47.94#ibcon#read 5, iclass 11, count 2 2006.211.08:17:47.94#ibcon#about to read 6, iclass 11, count 2 2006.211.08:17:47.94#ibcon#read 6, iclass 11, count 2 2006.211.08:17:47.94#ibcon#end of sib2, iclass 11, count 2 2006.211.08:17:47.94#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:17:47.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:17:47.94#ibcon#[25=AT02-07\r\n] 2006.211.08:17:47.94#ibcon#*before write, iclass 11, count 2 2006.211.08:17:47.94#ibcon#enter sib2, iclass 11, count 2 2006.211.08:17:47.94#ibcon#flushed, iclass 11, count 2 2006.211.08:17:47.94#ibcon#about to write, iclass 11, count 2 2006.211.08:17:47.94#ibcon#wrote, iclass 11, count 2 2006.211.08:17:47.94#ibcon#about to read 3, iclass 11, count 2 2006.211.08:17:47.97#ibcon#read 3, iclass 11, count 2 2006.211.08:17:47.97#ibcon#about to read 4, iclass 11, count 2 2006.211.08:17:47.97#ibcon#read 4, iclass 11, count 2 2006.211.08:17:47.97#ibcon#about to read 5, iclass 11, count 2 2006.211.08:17:47.97#ibcon#read 5, iclass 11, count 2 2006.211.08:17:47.97#ibcon#about to read 6, iclass 11, count 2 2006.211.08:17:47.97#ibcon#read 6, iclass 11, count 2 2006.211.08:17:47.97#ibcon#end of sib2, iclass 11, count 2 2006.211.08:17:47.97#ibcon#*after write, iclass 11, count 2 2006.211.08:17:47.97#ibcon#*before return 0, iclass 11, count 2 2006.211.08:17:47.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:47.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:47.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:17:47.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:47.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:48.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:48.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:48.09#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:17:48.09#ibcon#first serial, iclass 11, count 0 2006.211.08:17:48.09#ibcon#enter sib2, iclass 11, count 0 2006.211.08:17:48.09#ibcon#flushed, iclass 11, count 0 2006.211.08:17:48.09#ibcon#about to write, iclass 11, count 0 2006.211.08:17:48.09#ibcon#wrote, iclass 11, count 0 2006.211.08:17:48.09#ibcon#about to read 3, iclass 11, count 0 2006.211.08:17:48.11#ibcon#read 3, iclass 11, count 0 2006.211.08:17:48.11#ibcon#about to read 4, iclass 11, count 0 2006.211.08:17:48.11#ibcon#read 4, iclass 11, count 0 2006.211.08:17:48.11#ibcon#about to read 5, iclass 11, count 0 2006.211.08:17:48.11#ibcon#read 5, iclass 11, count 0 2006.211.08:17:48.11#ibcon#about to read 6, iclass 11, count 0 2006.211.08:17:48.11#ibcon#read 6, iclass 11, count 0 2006.211.08:17:48.11#ibcon#end of sib2, iclass 11, count 0 2006.211.08:17:48.11#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:17:48.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:17:48.11#ibcon#[25=USB\r\n] 2006.211.08:17:48.11#ibcon#*before write, iclass 11, count 0 2006.211.08:17:48.11#ibcon#enter sib2, iclass 11, count 0 2006.211.08:17:48.11#ibcon#flushed, iclass 11, count 0 2006.211.08:17:48.11#ibcon#about to write, iclass 11, count 0 2006.211.08:17:48.11#ibcon#wrote, iclass 11, count 0 2006.211.08:17:48.11#ibcon#about to read 3, iclass 11, count 0 2006.211.08:17:48.14#ibcon#read 3, iclass 11, count 0 2006.211.08:17:48.14#ibcon#about to read 4, iclass 11, count 0 2006.211.08:17:48.14#ibcon#read 4, iclass 11, count 0 2006.211.08:17:48.14#ibcon#about to read 5, iclass 11, count 0 2006.211.08:17:48.14#ibcon#read 5, iclass 11, count 0 2006.211.08:17:48.14#ibcon#about to read 6, iclass 11, count 0 2006.211.08:17:48.14#ibcon#read 6, iclass 11, count 0 2006.211.08:17:48.14#ibcon#end of sib2, iclass 11, count 0 2006.211.08:17:48.14#ibcon#*after write, iclass 11, count 0 2006.211.08:17:48.14#ibcon#*before return 0, iclass 11, count 0 2006.211.08:17:48.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:48.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:48.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:17:48.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:17:48.14$vc4f8/valo=3,672.99 2006.211.08:17:48.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:17:48.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:17:48.14#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:48.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:48.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:48.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:48.14#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:17:48.14#ibcon#first serial, iclass 13, count 0 2006.211.08:17:48.14#ibcon#enter sib2, iclass 13, count 0 2006.211.08:17:48.14#ibcon#flushed, iclass 13, count 0 2006.211.08:17:48.14#ibcon#about to write, iclass 13, count 0 2006.211.08:17:48.14#ibcon#wrote, iclass 13, count 0 2006.211.08:17:48.14#ibcon#about to read 3, iclass 13, count 0 2006.211.08:17:48.16#ibcon#read 3, iclass 13, count 0 2006.211.08:17:48.16#ibcon#about to read 4, iclass 13, count 0 2006.211.08:17:48.16#ibcon#read 4, iclass 13, count 0 2006.211.08:17:48.16#ibcon#about to read 5, iclass 13, count 0 2006.211.08:17:48.16#ibcon#read 5, iclass 13, count 0 2006.211.08:17:48.16#ibcon#about to read 6, iclass 13, count 0 2006.211.08:17:48.16#ibcon#read 6, iclass 13, count 0 2006.211.08:17:48.16#ibcon#end of sib2, iclass 13, count 0 2006.211.08:17:48.16#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:17:48.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:17:48.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:17:48.16#ibcon#*before write, iclass 13, count 0 2006.211.08:17:48.16#ibcon#enter sib2, iclass 13, count 0 2006.211.08:17:48.16#ibcon#flushed, iclass 13, count 0 2006.211.08:17:48.16#ibcon#about to write, iclass 13, count 0 2006.211.08:17:48.16#ibcon#wrote, iclass 13, count 0 2006.211.08:17:48.16#ibcon#about to read 3, iclass 13, count 0 2006.211.08:17:48.20#ibcon#read 3, iclass 13, count 0 2006.211.08:17:48.20#ibcon#about to read 4, iclass 13, count 0 2006.211.08:17:48.20#ibcon#read 4, iclass 13, count 0 2006.211.08:17:48.20#ibcon#about to read 5, iclass 13, count 0 2006.211.08:17:48.20#ibcon#read 5, iclass 13, count 0 2006.211.08:17:48.20#ibcon#about to read 6, iclass 13, count 0 2006.211.08:17:48.20#ibcon#read 6, iclass 13, count 0 2006.211.08:17:48.20#ibcon#end of sib2, iclass 13, count 0 2006.211.08:17:48.20#ibcon#*after write, iclass 13, count 0 2006.211.08:17:48.20#ibcon#*before return 0, iclass 13, count 0 2006.211.08:17:48.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:48.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:48.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:17:48.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:17:48.20$vc4f8/va=3,6 2006.211.08:17:48.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:17:48.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:17:48.20#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:48.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:48.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:48.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:48.26#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:17:48.26#ibcon#first serial, iclass 15, count 2 2006.211.08:17:48.26#ibcon#enter sib2, iclass 15, count 2 2006.211.08:17:48.26#ibcon#flushed, iclass 15, count 2 2006.211.08:17:48.26#ibcon#about to write, iclass 15, count 2 2006.211.08:17:48.26#ibcon#wrote, iclass 15, count 2 2006.211.08:17:48.26#ibcon#about to read 3, iclass 15, count 2 2006.211.08:17:48.28#ibcon#read 3, iclass 15, count 2 2006.211.08:17:48.28#ibcon#about to read 4, iclass 15, count 2 2006.211.08:17:48.28#ibcon#read 4, iclass 15, count 2 2006.211.08:17:48.28#ibcon#about to read 5, iclass 15, count 2 2006.211.08:17:48.28#ibcon#read 5, iclass 15, count 2 2006.211.08:17:48.28#ibcon#about to read 6, iclass 15, count 2 2006.211.08:17:48.28#ibcon#read 6, iclass 15, count 2 2006.211.08:17:48.28#ibcon#end of sib2, iclass 15, count 2 2006.211.08:17:48.28#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:17:48.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:17:48.28#ibcon#[25=AT03-06\r\n] 2006.211.08:17:48.28#ibcon#*before write, iclass 15, count 2 2006.211.08:17:48.28#ibcon#enter sib2, iclass 15, count 2 2006.211.08:17:48.28#ibcon#flushed, iclass 15, count 2 2006.211.08:17:48.28#ibcon#about to write, iclass 15, count 2 2006.211.08:17:48.28#ibcon#wrote, iclass 15, count 2 2006.211.08:17:48.28#ibcon#about to read 3, iclass 15, count 2 2006.211.08:17:48.31#ibcon#read 3, iclass 15, count 2 2006.211.08:17:48.31#ibcon#about to read 4, iclass 15, count 2 2006.211.08:17:48.31#ibcon#read 4, iclass 15, count 2 2006.211.08:17:48.31#ibcon#about to read 5, iclass 15, count 2 2006.211.08:17:48.31#ibcon#read 5, iclass 15, count 2 2006.211.08:17:48.31#ibcon#about to read 6, iclass 15, count 2 2006.211.08:17:48.31#ibcon#read 6, iclass 15, count 2 2006.211.08:17:48.31#ibcon#end of sib2, iclass 15, count 2 2006.211.08:17:48.31#ibcon#*after write, iclass 15, count 2 2006.211.08:17:48.31#ibcon#*before return 0, iclass 15, count 2 2006.211.08:17:48.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:48.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:48.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:17:48.31#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:48.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:48.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:48.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:48.43#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:17:48.43#ibcon#first serial, iclass 15, count 0 2006.211.08:17:48.43#ibcon#enter sib2, iclass 15, count 0 2006.211.08:17:48.43#ibcon#flushed, iclass 15, count 0 2006.211.08:17:48.43#ibcon#about to write, iclass 15, count 0 2006.211.08:17:48.43#ibcon#wrote, iclass 15, count 0 2006.211.08:17:48.43#ibcon#about to read 3, iclass 15, count 0 2006.211.08:17:48.45#ibcon#read 3, iclass 15, count 0 2006.211.08:17:48.45#ibcon#about to read 4, iclass 15, count 0 2006.211.08:17:48.45#ibcon#read 4, iclass 15, count 0 2006.211.08:17:48.45#ibcon#about to read 5, iclass 15, count 0 2006.211.08:17:48.45#ibcon#read 5, iclass 15, count 0 2006.211.08:17:48.45#ibcon#about to read 6, iclass 15, count 0 2006.211.08:17:48.45#ibcon#read 6, iclass 15, count 0 2006.211.08:17:48.45#ibcon#end of sib2, iclass 15, count 0 2006.211.08:17:48.45#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:17:48.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:17:48.45#ibcon#[25=USB\r\n] 2006.211.08:17:48.45#ibcon#*before write, iclass 15, count 0 2006.211.08:17:48.45#ibcon#enter sib2, iclass 15, count 0 2006.211.08:17:48.45#ibcon#flushed, iclass 15, count 0 2006.211.08:17:48.45#ibcon#about to write, iclass 15, count 0 2006.211.08:17:48.45#ibcon#wrote, iclass 15, count 0 2006.211.08:17:48.45#ibcon#about to read 3, iclass 15, count 0 2006.211.08:17:48.48#ibcon#read 3, iclass 15, count 0 2006.211.08:17:48.48#ibcon#about to read 4, iclass 15, count 0 2006.211.08:17:48.48#ibcon#read 4, iclass 15, count 0 2006.211.08:17:48.48#ibcon#about to read 5, iclass 15, count 0 2006.211.08:17:48.48#ibcon#read 5, iclass 15, count 0 2006.211.08:17:48.48#ibcon#about to read 6, iclass 15, count 0 2006.211.08:17:48.48#ibcon#read 6, iclass 15, count 0 2006.211.08:17:48.48#ibcon#end of sib2, iclass 15, count 0 2006.211.08:17:48.48#ibcon#*after write, iclass 15, count 0 2006.211.08:17:48.48#ibcon#*before return 0, iclass 15, count 0 2006.211.08:17:48.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:48.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:48.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:17:48.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:17:48.48$vc4f8/valo=4,832.99 2006.211.08:17:48.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:17:48.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:17:48.48#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:48.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:48.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:48.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:48.48#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:17:48.48#ibcon#first serial, iclass 17, count 0 2006.211.08:17:48.48#ibcon#enter sib2, iclass 17, count 0 2006.211.08:17:48.48#ibcon#flushed, iclass 17, count 0 2006.211.08:17:48.48#ibcon#about to write, iclass 17, count 0 2006.211.08:17:48.48#ibcon#wrote, iclass 17, count 0 2006.211.08:17:48.48#ibcon#about to read 3, iclass 17, count 0 2006.211.08:17:48.50#ibcon#read 3, iclass 17, count 0 2006.211.08:17:48.50#ibcon#about to read 4, iclass 17, count 0 2006.211.08:17:48.50#ibcon#read 4, iclass 17, count 0 2006.211.08:17:48.50#ibcon#about to read 5, iclass 17, count 0 2006.211.08:17:48.50#ibcon#read 5, iclass 17, count 0 2006.211.08:17:48.50#ibcon#about to read 6, iclass 17, count 0 2006.211.08:17:48.50#ibcon#read 6, iclass 17, count 0 2006.211.08:17:48.50#ibcon#end of sib2, iclass 17, count 0 2006.211.08:17:48.50#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:17:48.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:17:48.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:17:48.50#ibcon#*before write, iclass 17, count 0 2006.211.08:17:48.50#ibcon#enter sib2, iclass 17, count 0 2006.211.08:17:48.50#ibcon#flushed, iclass 17, count 0 2006.211.08:17:48.50#ibcon#about to write, iclass 17, count 0 2006.211.08:17:48.50#ibcon#wrote, iclass 17, count 0 2006.211.08:17:48.50#ibcon#about to read 3, iclass 17, count 0 2006.211.08:17:48.54#ibcon#read 3, iclass 17, count 0 2006.211.08:17:48.54#ibcon#about to read 4, iclass 17, count 0 2006.211.08:17:48.54#ibcon#read 4, iclass 17, count 0 2006.211.08:17:48.54#ibcon#about to read 5, iclass 17, count 0 2006.211.08:17:48.54#ibcon#read 5, iclass 17, count 0 2006.211.08:17:48.54#ibcon#about to read 6, iclass 17, count 0 2006.211.08:17:48.54#ibcon#read 6, iclass 17, count 0 2006.211.08:17:48.54#ibcon#end of sib2, iclass 17, count 0 2006.211.08:17:48.54#ibcon#*after write, iclass 17, count 0 2006.211.08:17:48.54#ibcon#*before return 0, iclass 17, count 0 2006.211.08:17:48.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:48.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:48.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:17:48.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:17:48.54$vc4f8/va=4,7 2006.211.08:17:48.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:17:48.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:17:48.54#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:48.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:48.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:48.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:48.60#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:17:48.60#ibcon#first serial, iclass 19, count 2 2006.211.08:17:48.60#ibcon#enter sib2, iclass 19, count 2 2006.211.08:17:48.60#ibcon#flushed, iclass 19, count 2 2006.211.08:17:48.60#ibcon#about to write, iclass 19, count 2 2006.211.08:17:48.60#ibcon#wrote, iclass 19, count 2 2006.211.08:17:48.60#ibcon#about to read 3, iclass 19, count 2 2006.211.08:17:48.62#ibcon#read 3, iclass 19, count 2 2006.211.08:17:48.62#ibcon#about to read 4, iclass 19, count 2 2006.211.08:17:48.62#ibcon#read 4, iclass 19, count 2 2006.211.08:17:48.62#ibcon#about to read 5, iclass 19, count 2 2006.211.08:17:48.62#ibcon#read 5, iclass 19, count 2 2006.211.08:17:48.62#ibcon#about to read 6, iclass 19, count 2 2006.211.08:17:48.62#ibcon#read 6, iclass 19, count 2 2006.211.08:17:48.62#ibcon#end of sib2, iclass 19, count 2 2006.211.08:17:48.62#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:17:48.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:17:48.62#ibcon#[25=AT04-07\r\n] 2006.211.08:17:48.62#ibcon#*before write, iclass 19, count 2 2006.211.08:17:48.62#ibcon#enter sib2, iclass 19, count 2 2006.211.08:17:48.62#ibcon#flushed, iclass 19, count 2 2006.211.08:17:48.62#ibcon#about to write, iclass 19, count 2 2006.211.08:17:48.62#ibcon#wrote, iclass 19, count 2 2006.211.08:17:48.62#ibcon#about to read 3, iclass 19, count 2 2006.211.08:17:48.65#ibcon#read 3, iclass 19, count 2 2006.211.08:17:48.65#ibcon#about to read 4, iclass 19, count 2 2006.211.08:17:48.65#ibcon#read 4, iclass 19, count 2 2006.211.08:17:48.65#ibcon#about to read 5, iclass 19, count 2 2006.211.08:17:48.65#ibcon#read 5, iclass 19, count 2 2006.211.08:17:48.65#ibcon#about to read 6, iclass 19, count 2 2006.211.08:17:48.65#ibcon#read 6, iclass 19, count 2 2006.211.08:17:48.65#ibcon#end of sib2, iclass 19, count 2 2006.211.08:17:48.65#ibcon#*after write, iclass 19, count 2 2006.211.08:17:48.65#ibcon#*before return 0, iclass 19, count 2 2006.211.08:17:48.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:48.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:48.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:17:48.65#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:48.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:48.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:48.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:48.77#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:17:48.77#ibcon#first serial, iclass 19, count 0 2006.211.08:17:48.77#ibcon#enter sib2, iclass 19, count 0 2006.211.08:17:48.77#ibcon#flushed, iclass 19, count 0 2006.211.08:17:48.77#ibcon#about to write, iclass 19, count 0 2006.211.08:17:48.77#ibcon#wrote, iclass 19, count 0 2006.211.08:17:48.77#ibcon#about to read 3, iclass 19, count 0 2006.211.08:17:48.79#ibcon#read 3, iclass 19, count 0 2006.211.08:17:48.79#ibcon#about to read 4, iclass 19, count 0 2006.211.08:17:48.79#ibcon#read 4, iclass 19, count 0 2006.211.08:17:48.79#ibcon#about to read 5, iclass 19, count 0 2006.211.08:17:48.79#ibcon#read 5, iclass 19, count 0 2006.211.08:17:48.79#ibcon#about to read 6, iclass 19, count 0 2006.211.08:17:48.79#ibcon#read 6, iclass 19, count 0 2006.211.08:17:48.79#ibcon#end of sib2, iclass 19, count 0 2006.211.08:17:48.79#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:17:48.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:17:48.79#ibcon#[25=USB\r\n] 2006.211.08:17:48.79#ibcon#*before write, iclass 19, count 0 2006.211.08:17:48.79#ibcon#enter sib2, iclass 19, count 0 2006.211.08:17:48.79#ibcon#flushed, iclass 19, count 0 2006.211.08:17:48.79#ibcon#about to write, iclass 19, count 0 2006.211.08:17:48.79#ibcon#wrote, iclass 19, count 0 2006.211.08:17:48.79#ibcon#about to read 3, iclass 19, count 0 2006.211.08:17:48.82#ibcon#read 3, iclass 19, count 0 2006.211.08:17:48.82#ibcon#about to read 4, iclass 19, count 0 2006.211.08:17:48.82#ibcon#read 4, iclass 19, count 0 2006.211.08:17:48.82#ibcon#about to read 5, iclass 19, count 0 2006.211.08:17:48.82#ibcon#read 5, iclass 19, count 0 2006.211.08:17:48.82#ibcon#about to read 6, iclass 19, count 0 2006.211.08:17:48.82#ibcon#read 6, iclass 19, count 0 2006.211.08:17:48.82#ibcon#end of sib2, iclass 19, count 0 2006.211.08:17:48.82#ibcon#*after write, iclass 19, count 0 2006.211.08:17:48.82#ibcon#*before return 0, iclass 19, count 0 2006.211.08:17:48.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:48.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:48.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:17:48.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:17:48.82$vc4f8/valo=5,652.99 2006.211.08:17:48.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:17:48.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:17:48.82#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:48.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:48.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:48.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:48.82#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:17:48.82#ibcon#first serial, iclass 21, count 0 2006.211.08:17:48.82#ibcon#enter sib2, iclass 21, count 0 2006.211.08:17:48.82#ibcon#flushed, iclass 21, count 0 2006.211.08:17:48.82#ibcon#about to write, iclass 21, count 0 2006.211.08:17:48.82#ibcon#wrote, iclass 21, count 0 2006.211.08:17:48.82#ibcon#about to read 3, iclass 21, count 0 2006.211.08:17:48.84#ibcon#read 3, iclass 21, count 0 2006.211.08:17:48.84#ibcon#about to read 4, iclass 21, count 0 2006.211.08:17:48.84#ibcon#read 4, iclass 21, count 0 2006.211.08:17:48.84#ibcon#about to read 5, iclass 21, count 0 2006.211.08:17:48.84#ibcon#read 5, iclass 21, count 0 2006.211.08:17:48.84#ibcon#about to read 6, iclass 21, count 0 2006.211.08:17:48.84#ibcon#read 6, iclass 21, count 0 2006.211.08:17:48.84#ibcon#end of sib2, iclass 21, count 0 2006.211.08:17:48.84#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:17:48.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:17:48.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:17:48.84#ibcon#*before write, iclass 21, count 0 2006.211.08:17:48.84#ibcon#enter sib2, iclass 21, count 0 2006.211.08:17:48.84#ibcon#flushed, iclass 21, count 0 2006.211.08:17:48.84#ibcon#about to write, iclass 21, count 0 2006.211.08:17:48.84#ibcon#wrote, iclass 21, count 0 2006.211.08:17:48.84#ibcon#about to read 3, iclass 21, count 0 2006.211.08:17:48.88#ibcon#read 3, iclass 21, count 0 2006.211.08:17:48.88#ibcon#about to read 4, iclass 21, count 0 2006.211.08:17:48.88#ibcon#read 4, iclass 21, count 0 2006.211.08:17:48.88#ibcon#about to read 5, iclass 21, count 0 2006.211.08:17:48.88#ibcon#read 5, iclass 21, count 0 2006.211.08:17:48.88#ibcon#about to read 6, iclass 21, count 0 2006.211.08:17:48.88#ibcon#read 6, iclass 21, count 0 2006.211.08:17:48.88#ibcon#end of sib2, iclass 21, count 0 2006.211.08:17:48.88#ibcon#*after write, iclass 21, count 0 2006.211.08:17:48.88#ibcon#*before return 0, iclass 21, count 0 2006.211.08:17:48.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:48.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:48.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:17:48.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:17:48.88$vc4f8/va=5,7 2006.211.08:17:48.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:17:48.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:17:48.88#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:48.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:48.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:48.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:48.94#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:17:48.94#ibcon#first serial, iclass 23, count 2 2006.211.08:17:48.94#ibcon#enter sib2, iclass 23, count 2 2006.211.08:17:48.94#ibcon#flushed, iclass 23, count 2 2006.211.08:17:48.94#ibcon#about to write, iclass 23, count 2 2006.211.08:17:48.94#ibcon#wrote, iclass 23, count 2 2006.211.08:17:48.94#ibcon#about to read 3, iclass 23, count 2 2006.211.08:17:48.96#ibcon#read 3, iclass 23, count 2 2006.211.08:17:48.96#ibcon#about to read 4, iclass 23, count 2 2006.211.08:17:48.96#ibcon#read 4, iclass 23, count 2 2006.211.08:17:48.96#ibcon#about to read 5, iclass 23, count 2 2006.211.08:17:48.96#ibcon#read 5, iclass 23, count 2 2006.211.08:17:48.96#ibcon#about to read 6, iclass 23, count 2 2006.211.08:17:48.96#ibcon#read 6, iclass 23, count 2 2006.211.08:17:48.96#ibcon#end of sib2, iclass 23, count 2 2006.211.08:17:48.96#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:17:48.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:17:48.96#ibcon#[25=AT05-07\r\n] 2006.211.08:17:48.96#ibcon#*before write, iclass 23, count 2 2006.211.08:17:48.96#ibcon#enter sib2, iclass 23, count 2 2006.211.08:17:48.96#ibcon#flushed, iclass 23, count 2 2006.211.08:17:48.96#ibcon#about to write, iclass 23, count 2 2006.211.08:17:48.96#ibcon#wrote, iclass 23, count 2 2006.211.08:17:48.96#ibcon#about to read 3, iclass 23, count 2 2006.211.08:17:48.99#ibcon#read 3, iclass 23, count 2 2006.211.08:17:48.99#ibcon#about to read 4, iclass 23, count 2 2006.211.08:17:48.99#ibcon#read 4, iclass 23, count 2 2006.211.08:17:48.99#ibcon#about to read 5, iclass 23, count 2 2006.211.08:17:48.99#ibcon#read 5, iclass 23, count 2 2006.211.08:17:48.99#ibcon#about to read 6, iclass 23, count 2 2006.211.08:17:48.99#ibcon#read 6, iclass 23, count 2 2006.211.08:17:48.99#ibcon#end of sib2, iclass 23, count 2 2006.211.08:17:48.99#ibcon#*after write, iclass 23, count 2 2006.211.08:17:48.99#ibcon#*before return 0, iclass 23, count 2 2006.211.08:17:48.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:48.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:48.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:17:48.99#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:48.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:49.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:49.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:49.11#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:17:49.11#ibcon#first serial, iclass 23, count 0 2006.211.08:17:49.11#ibcon#enter sib2, iclass 23, count 0 2006.211.08:17:49.11#ibcon#flushed, iclass 23, count 0 2006.211.08:17:49.11#ibcon#about to write, iclass 23, count 0 2006.211.08:17:49.11#ibcon#wrote, iclass 23, count 0 2006.211.08:17:49.11#ibcon#about to read 3, iclass 23, count 0 2006.211.08:17:49.13#ibcon#read 3, iclass 23, count 0 2006.211.08:17:49.13#ibcon#about to read 4, iclass 23, count 0 2006.211.08:17:49.13#ibcon#read 4, iclass 23, count 0 2006.211.08:17:49.13#ibcon#about to read 5, iclass 23, count 0 2006.211.08:17:49.13#ibcon#read 5, iclass 23, count 0 2006.211.08:17:49.13#ibcon#about to read 6, iclass 23, count 0 2006.211.08:17:49.13#ibcon#read 6, iclass 23, count 0 2006.211.08:17:49.13#ibcon#end of sib2, iclass 23, count 0 2006.211.08:17:49.13#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:17:49.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:17:49.13#ibcon#[25=USB\r\n] 2006.211.08:17:49.13#ibcon#*before write, iclass 23, count 0 2006.211.08:17:49.13#ibcon#enter sib2, iclass 23, count 0 2006.211.08:17:49.13#ibcon#flushed, iclass 23, count 0 2006.211.08:17:49.13#ibcon#about to write, iclass 23, count 0 2006.211.08:17:49.13#ibcon#wrote, iclass 23, count 0 2006.211.08:17:49.13#ibcon#about to read 3, iclass 23, count 0 2006.211.08:17:49.16#ibcon#read 3, iclass 23, count 0 2006.211.08:17:49.16#ibcon#about to read 4, iclass 23, count 0 2006.211.08:17:49.16#ibcon#read 4, iclass 23, count 0 2006.211.08:17:49.16#ibcon#about to read 5, iclass 23, count 0 2006.211.08:17:49.16#ibcon#read 5, iclass 23, count 0 2006.211.08:17:49.16#ibcon#about to read 6, iclass 23, count 0 2006.211.08:17:49.16#ibcon#read 6, iclass 23, count 0 2006.211.08:17:49.16#ibcon#end of sib2, iclass 23, count 0 2006.211.08:17:49.16#ibcon#*after write, iclass 23, count 0 2006.211.08:17:49.16#ibcon#*before return 0, iclass 23, count 0 2006.211.08:17:49.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:49.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:49.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:17:49.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:17:49.16$vc4f8/valo=6,772.99 2006.211.08:17:49.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:17:49.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:17:49.16#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:49.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:49.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:49.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:49.16#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:17:49.16#ibcon#first serial, iclass 25, count 0 2006.211.08:17:49.16#ibcon#enter sib2, iclass 25, count 0 2006.211.08:17:49.16#ibcon#flushed, iclass 25, count 0 2006.211.08:17:49.16#ibcon#about to write, iclass 25, count 0 2006.211.08:17:49.16#ibcon#wrote, iclass 25, count 0 2006.211.08:17:49.16#ibcon#about to read 3, iclass 25, count 0 2006.211.08:17:49.18#ibcon#read 3, iclass 25, count 0 2006.211.08:17:49.18#ibcon#about to read 4, iclass 25, count 0 2006.211.08:17:49.18#ibcon#read 4, iclass 25, count 0 2006.211.08:17:49.18#ibcon#about to read 5, iclass 25, count 0 2006.211.08:17:49.18#ibcon#read 5, iclass 25, count 0 2006.211.08:17:49.18#ibcon#about to read 6, iclass 25, count 0 2006.211.08:17:49.18#ibcon#read 6, iclass 25, count 0 2006.211.08:17:49.18#ibcon#end of sib2, iclass 25, count 0 2006.211.08:17:49.18#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:17:49.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:17:49.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:17:49.18#ibcon#*before write, iclass 25, count 0 2006.211.08:17:49.18#ibcon#enter sib2, iclass 25, count 0 2006.211.08:17:49.18#ibcon#flushed, iclass 25, count 0 2006.211.08:17:49.18#ibcon#about to write, iclass 25, count 0 2006.211.08:17:49.18#ibcon#wrote, iclass 25, count 0 2006.211.08:17:49.18#ibcon#about to read 3, iclass 25, count 0 2006.211.08:17:49.22#ibcon#read 3, iclass 25, count 0 2006.211.08:17:49.22#ibcon#about to read 4, iclass 25, count 0 2006.211.08:17:49.22#ibcon#read 4, iclass 25, count 0 2006.211.08:17:49.22#ibcon#about to read 5, iclass 25, count 0 2006.211.08:17:49.22#ibcon#read 5, iclass 25, count 0 2006.211.08:17:49.22#ibcon#about to read 6, iclass 25, count 0 2006.211.08:17:49.22#ibcon#read 6, iclass 25, count 0 2006.211.08:17:49.22#ibcon#end of sib2, iclass 25, count 0 2006.211.08:17:49.22#ibcon#*after write, iclass 25, count 0 2006.211.08:17:49.22#ibcon#*before return 0, iclass 25, count 0 2006.211.08:17:49.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:49.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:49.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:17:49.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:17:49.22$vc4f8/va=6,6 2006.211.08:17:49.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:17:49.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:17:49.22#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:49.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:49.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:49.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:49.28#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:17:49.28#ibcon#first serial, iclass 27, count 2 2006.211.08:17:49.28#ibcon#enter sib2, iclass 27, count 2 2006.211.08:17:49.28#ibcon#flushed, iclass 27, count 2 2006.211.08:17:49.28#ibcon#about to write, iclass 27, count 2 2006.211.08:17:49.28#ibcon#wrote, iclass 27, count 2 2006.211.08:17:49.28#ibcon#about to read 3, iclass 27, count 2 2006.211.08:17:49.30#ibcon#read 3, iclass 27, count 2 2006.211.08:17:49.30#ibcon#about to read 4, iclass 27, count 2 2006.211.08:17:49.30#ibcon#read 4, iclass 27, count 2 2006.211.08:17:49.30#ibcon#about to read 5, iclass 27, count 2 2006.211.08:17:49.30#ibcon#read 5, iclass 27, count 2 2006.211.08:17:49.30#ibcon#about to read 6, iclass 27, count 2 2006.211.08:17:49.30#ibcon#read 6, iclass 27, count 2 2006.211.08:17:49.30#ibcon#end of sib2, iclass 27, count 2 2006.211.08:17:49.30#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:17:49.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:17:49.30#ibcon#[25=AT06-06\r\n] 2006.211.08:17:49.30#ibcon#*before write, iclass 27, count 2 2006.211.08:17:49.30#ibcon#enter sib2, iclass 27, count 2 2006.211.08:17:49.30#ibcon#flushed, iclass 27, count 2 2006.211.08:17:49.30#ibcon#about to write, iclass 27, count 2 2006.211.08:17:49.30#ibcon#wrote, iclass 27, count 2 2006.211.08:17:49.30#ibcon#about to read 3, iclass 27, count 2 2006.211.08:17:49.33#ibcon#read 3, iclass 27, count 2 2006.211.08:17:49.33#ibcon#about to read 4, iclass 27, count 2 2006.211.08:17:49.33#ibcon#read 4, iclass 27, count 2 2006.211.08:17:49.33#ibcon#about to read 5, iclass 27, count 2 2006.211.08:17:49.33#ibcon#read 5, iclass 27, count 2 2006.211.08:17:49.33#ibcon#about to read 6, iclass 27, count 2 2006.211.08:17:49.33#ibcon#read 6, iclass 27, count 2 2006.211.08:17:49.33#ibcon#end of sib2, iclass 27, count 2 2006.211.08:17:49.33#ibcon#*after write, iclass 27, count 2 2006.211.08:17:49.33#ibcon#*before return 0, iclass 27, count 2 2006.211.08:17:49.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:49.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:49.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:17:49.33#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:49.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:49.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:49.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:49.45#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:17:49.45#ibcon#first serial, iclass 27, count 0 2006.211.08:17:49.45#ibcon#enter sib2, iclass 27, count 0 2006.211.08:17:49.45#ibcon#flushed, iclass 27, count 0 2006.211.08:17:49.45#ibcon#about to write, iclass 27, count 0 2006.211.08:17:49.45#ibcon#wrote, iclass 27, count 0 2006.211.08:17:49.45#ibcon#about to read 3, iclass 27, count 0 2006.211.08:17:49.47#ibcon#read 3, iclass 27, count 0 2006.211.08:17:49.47#ibcon#about to read 4, iclass 27, count 0 2006.211.08:17:49.47#ibcon#read 4, iclass 27, count 0 2006.211.08:17:49.47#ibcon#about to read 5, iclass 27, count 0 2006.211.08:17:49.47#ibcon#read 5, iclass 27, count 0 2006.211.08:17:49.47#ibcon#about to read 6, iclass 27, count 0 2006.211.08:17:49.47#ibcon#read 6, iclass 27, count 0 2006.211.08:17:49.47#ibcon#end of sib2, iclass 27, count 0 2006.211.08:17:49.47#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:17:49.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:17:49.47#ibcon#[25=USB\r\n] 2006.211.08:17:49.47#ibcon#*before write, iclass 27, count 0 2006.211.08:17:49.47#ibcon#enter sib2, iclass 27, count 0 2006.211.08:17:49.47#ibcon#flushed, iclass 27, count 0 2006.211.08:17:49.47#ibcon#about to write, iclass 27, count 0 2006.211.08:17:49.47#ibcon#wrote, iclass 27, count 0 2006.211.08:17:49.47#ibcon#about to read 3, iclass 27, count 0 2006.211.08:17:49.49#abcon#<5=/04 4.8 9.0 24.40 811010.1\r\n> 2006.211.08:17:49.50#ibcon#read 3, iclass 27, count 0 2006.211.08:17:49.50#ibcon#about to read 4, iclass 27, count 0 2006.211.08:17:49.50#ibcon#read 4, iclass 27, count 0 2006.211.08:17:49.50#ibcon#about to read 5, iclass 27, count 0 2006.211.08:17:49.50#ibcon#read 5, iclass 27, count 0 2006.211.08:17:49.50#ibcon#about to read 6, iclass 27, count 0 2006.211.08:17:49.50#ibcon#read 6, iclass 27, count 0 2006.211.08:17:49.50#ibcon#end of sib2, iclass 27, count 0 2006.211.08:17:49.50#ibcon#*after write, iclass 27, count 0 2006.211.08:17:49.50#ibcon#*before return 0, iclass 27, count 0 2006.211.08:17:49.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:49.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:49.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:17:49.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:17:49.50$vc4f8/valo=7,832.99 2006.211.08:17:49.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.08:17:49.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.08:17:49.50#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:49.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:17:49.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:17:49.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:17:49.50#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:17:49.50#ibcon#first serial, iclass 32, count 0 2006.211.08:17:49.50#ibcon#enter sib2, iclass 32, count 0 2006.211.08:17:49.50#ibcon#flushed, iclass 32, count 0 2006.211.08:17:49.50#ibcon#about to write, iclass 32, count 0 2006.211.08:17:49.50#ibcon#wrote, iclass 32, count 0 2006.211.08:17:49.50#ibcon#about to read 3, iclass 32, count 0 2006.211.08:17:49.51#abcon#{5=INTERFACE CLEAR} 2006.211.08:17:49.52#ibcon#read 3, iclass 32, count 0 2006.211.08:17:49.52#ibcon#about to read 4, iclass 32, count 0 2006.211.08:17:49.52#ibcon#read 4, iclass 32, count 0 2006.211.08:17:49.52#ibcon#about to read 5, iclass 32, count 0 2006.211.08:17:49.52#ibcon#read 5, iclass 32, count 0 2006.211.08:17:49.52#ibcon#about to read 6, iclass 32, count 0 2006.211.08:17:49.52#ibcon#read 6, iclass 32, count 0 2006.211.08:17:49.52#ibcon#end of sib2, iclass 32, count 0 2006.211.08:17:49.52#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:17:49.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:17:49.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:17:49.52#ibcon#*before write, iclass 32, count 0 2006.211.08:17:49.52#ibcon#enter sib2, iclass 32, count 0 2006.211.08:17:49.52#ibcon#flushed, iclass 32, count 0 2006.211.08:17:49.52#ibcon#about to write, iclass 32, count 0 2006.211.08:17:49.52#ibcon#wrote, iclass 32, count 0 2006.211.08:17:49.52#ibcon#about to read 3, iclass 32, count 0 2006.211.08:17:49.56#ibcon#read 3, iclass 32, count 0 2006.211.08:17:49.56#ibcon#about to read 4, iclass 32, count 0 2006.211.08:17:49.56#ibcon#read 4, iclass 32, count 0 2006.211.08:17:49.56#ibcon#about to read 5, iclass 32, count 0 2006.211.08:17:49.56#ibcon#read 5, iclass 32, count 0 2006.211.08:17:49.56#ibcon#about to read 6, iclass 32, count 0 2006.211.08:17:49.56#ibcon#read 6, iclass 32, count 0 2006.211.08:17:49.56#ibcon#end of sib2, iclass 32, count 0 2006.211.08:17:49.56#ibcon#*after write, iclass 32, count 0 2006.211.08:17:49.56#ibcon#*before return 0, iclass 32, count 0 2006.211.08:17:49.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:17:49.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:17:49.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:17:49.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:17:49.56$vc4f8/va=7,6 2006.211.08:17:49.56#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:17:49.56#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:17:49.56#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:49.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:17:49.57#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:17:49.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:17:49.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:17:49.62#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:17:49.62#ibcon#first serial, iclass 35, count 2 2006.211.08:17:49.62#ibcon#enter sib2, iclass 35, count 2 2006.211.08:17:49.62#ibcon#flushed, iclass 35, count 2 2006.211.08:17:49.62#ibcon#about to write, iclass 35, count 2 2006.211.08:17:49.62#ibcon#wrote, iclass 35, count 2 2006.211.08:17:49.62#ibcon#about to read 3, iclass 35, count 2 2006.211.08:17:49.64#ibcon#read 3, iclass 35, count 2 2006.211.08:17:49.64#ibcon#about to read 4, iclass 35, count 2 2006.211.08:17:49.64#ibcon#read 4, iclass 35, count 2 2006.211.08:17:49.64#ibcon#about to read 5, iclass 35, count 2 2006.211.08:17:49.64#ibcon#read 5, iclass 35, count 2 2006.211.08:17:49.64#ibcon#about to read 6, iclass 35, count 2 2006.211.08:17:49.64#ibcon#read 6, iclass 35, count 2 2006.211.08:17:49.64#ibcon#end of sib2, iclass 35, count 2 2006.211.08:17:49.64#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:17:49.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:17:49.64#ibcon#[25=AT07-06\r\n] 2006.211.08:17:49.64#ibcon#*before write, iclass 35, count 2 2006.211.08:17:49.64#ibcon#enter sib2, iclass 35, count 2 2006.211.08:17:49.64#ibcon#flushed, iclass 35, count 2 2006.211.08:17:49.64#ibcon#about to write, iclass 35, count 2 2006.211.08:17:49.64#ibcon#wrote, iclass 35, count 2 2006.211.08:17:49.64#ibcon#about to read 3, iclass 35, count 2 2006.211.08:17:49.67#ibcon#read 3, iclass 35, count 2 2006.211.08:17:49.67#ibcon#about to read 4, iclass 35, count 2 2006.211.08:17:49.67#ibcon#read 4, iclass 35, count 2 2006.211.08:17:49.67#ibcon#about to read 5, iclass 35, count 2 2006.211.08:17:49.67#ibcon#read 5, iclass 35, count 2 2006.211.08:17:49.67#ibcon#about to read 6, iclass 35, count 2 2006.211.08:17:49.67#ibcon#read 6, iclass 35, count 2 2006.211.08:17:49.67#ibcon#end of sib2, iclass 35, count 2 2006.211.08:17:49.67#ibcon#*after write, iclass 35, count 2 2006.211.08:17:49.67#ibcon#*before return 0, iclass 35, count 2 2006.211.08:17:49.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:17:49.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:17:49.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:17:49.67#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:49.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:17:49.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:17:49.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:17:49.79#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:17:49.79#ibcon#first serial, iclass 35, count 0 2006.211.08:17:49.79#ibcon#enter sib2, iclass 35, count 0 2006.211.08:17:49.79#ibcon#flushed, iclass 35, count 0 2006.211.08:17:49.79#ibcon#about to write, iclass 35, count 0 2006.211.08:17:49.79#ibcon#wrote, iclass 35, count 0 2006.211.08:17:49.79#ibcon#about to read 3, iclass 35, count 0 2006.211.08:17:49.81#ibcon#read 3, iclass 35, count 0 2006.211.08:17:49.81#ibcon#about to read 4, iclass 35, count 0 2006.211.08:17:49.81#ibcon#read 4, iclass 35, count 0 2006.211.08:17:49.81#ibcon#about to read 5, iclass 35, count 0 2006.211.08:17:49.81#ibcon#read 5, iclass 35, count 0 2006.211.08:17:49.81#ibcon#about to read 6, iclass 35, count 0 2006.211.08:17:49.81#ibcon#read 6, iclass 35, count 0 2006.211.08:17:49.81#ibcon#end of sib2, iclass 35, count 0 2006.211.08:17:49.81#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:17:49.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:17:49.81#ibcon#[25=USB\r\n] 2006.211.08:17:49.81#ibcon#*before write, iclass 35, count 0 2006.211.08:17:49.81#ibcon#enter sib2, iclass 35, count 0 2006.211.08:17:49.81#ibcon#flushed, iclass 35, count 0 2006.211.08:17:49.81#ibcon#about to write, iclass 35, count 0 2006.211.08:17:49.81#ibcon#wrote, iclass 35, count 0 2006.211.08:17:49.81#ibcon#about to read 3, iclass 35, count 0 2006.211.08:17:49.84#ibcon#read 3, iclass 35, count 0 2006.211.08:17:49.84#ibcon#about to read 4, iclass 35, count 0 2006.211.08:17:49.84#ibcon#read 4, iclass 35, count 0 2006.211.08:17:49.84#ibcon#about to read 5, iclass 35, count 0 2006.211.08:17:49.84#ibcon#read 5, iclass 35, count 0 2006.211.08:17:49.84#ibcon#about to read 6, iclass 35, count 0 2006.211.08:17:49.84#ibcon#read 6, iclass 35, count 0 2006.211.08:17:49.84#ibcon#end of sib2, iclass 35, count 0 2006.211.08:17:49.84#ibcon#*after write, iclass 35, count 0 2006.211.08:17:49.84#ibcon#*before return 0, iclass 35, count 0 2006.211.08:17:49.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:17:49.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:17:49.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:17:49.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:17:49.84$vc4f8/valo=8,852.99 2006.211.08:17:49.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:17:49.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:17:49.84#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:49.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:17:49.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:17:49.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:17:49.84#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:17:49.84#ibcon#first serial, iclass 37, count 0 2006.211.08:17:49.84#ibcon#enter sib2, iclass 37, count 0 2006.211.08:17:49.84#ibcon#flushed, iclass 37, count 0 2006.211.08:17:49.84#ibcon#about to write, iclass 37, count 0 2006.211.08:17:49.84#ibcon#wrote, iclass 37, count 0 2006.211.08:17:49.84#ibcon#about to read 3, iclass 37, count 0 2006.211.08:17:49.86#ibcon#read 3, iclass 37, count 0 2006.211.08:17:49.86#ibcon#about to read 4, iclass 37, count 0 2006.211.08:17:49.86#ibcon#read 4, iclass 37, count 0 2006.211.08:17:49.86#ibcon#about to read 5, iclass 37, count 0 2006.211.08:17:49.86#ibcon#read 5, iclass 37, count 0 2006.211.08:17:49.86#ibcon#about to read 6, iclass 37, count 0 2006.211.08:17:49.86#ibcon#read 6, iclass 37, count 0 2006.211.08:17:49.86#ibcon#end of sib2, iclass 37, count 0 2006.211.08:17:49.86#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:17:49.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:17:49.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:17:49.86#ibcon#*before write, iclass 37, count 0 2006.211.08:17:49.86#ibcon#enter sib2, iclass 37, count 0 2006.211.08:17:49.86#ibcon#flushed, iclass 37, count 0 2006.211.08:17:49.86#ibcon#about to write, iclass 37, count 0 2006.211.08:17:49.86#ibcon#wrote, iclass 37, count 0 2006.211.08:17:49.86#ibcon#about to read 3, iclass 37, count 0 2006.211.08:17:49.90#ibcon#read 3, iclass 37, count 0 2006.211.08:17:49.90#ibcon#about to read 4, iclass 37, count 0 2006.211.08:17:49.90#ibcon#read 4, iclass 37, count 0 2006.211.08:17:49.90#ibcon#about to read 5, iclass 37, count 0 2006.211.08:17:49.90#ibcon#read 5, iclass 37, count 0 2006.211.08:17:49.90#ibcon#about to read 6, iclass 37, count 0 2006.211.08:17:49.90#ibcon#read 6, iclass 37, count 0 2006.211.08:17:49.90#ibcon#end of sib2, iclass 37, count 0 2006.211.08:17:49.90#ibcon#*after write, iclass 37, count 0 2006.211.08:17:49.90#ibcon#*before return 0, iclass 37, count 0 2006.211.08:17:49.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:17:49.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:17:49.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:17:49.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:17:49.90$vc4f8/va=8,7 2006.211.08:17:49.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:17:49.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:17:49.90#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:49.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:17:49.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:17:49.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:17:49.96#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:17:49.96#ibcon#first serial, iclass 39, count 2 2006.211.08:17:49.96#ibcon#enter sib2, iclass 39, count 2 2006.211.08:17:49.96#ibcon#flushed, iclass 39, count 2 2006.211.08:17:49.96#ibcon#about to write, iclass 39, count 2 2006.211.08:17:49.96#ibcon#wrote, iclass 39, count 2 2006.211.08:17:49.96#ibcon#about to read 3, iclass 39, count 2 2006.211.08:17:49.98#ibcon#read 3, iclass 39, count 2 2006.211.08:17:49.98#ibcon#about to read 4, iclass 39, count 2 2006.211.08:17:49.98#ibcon#read 4, iclass 39, count 2 2006.211.08:17:49.98#ibcon#about to read 5, iclass 39, count 2 2006.211.08:17:49.98#ibcon#read 5, iclass 39, count 2 2006.211.08:17:49.98#ibcon#about to read 6, iclass 39, count 2 2006.211.08:17:49.98#ibcon#read 6, iclass 39, count 2 2006.211.08:17:49.98#ibcon#end of sib2, iclass 39, count 2 2006.211.08:17:49.98#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:17:49.98#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:17:49.98#ibcon#[25=AT08-07\r\n] 2006.211.08:17:49.98#ibcon#*before write, iclass 39, count 2 2006.211.08:17:49.98#ibcon#enter sib2, iclass 39, count 2 2006.211.08:17:49.98#ibcon#flushed, iclass 39, count 2 2006.211.08:17:49.98#ibcon#about to write, iclass 39, count 2 2006.211.08:17:49.98#ibcon#wrote, iclass 39, count 2 2006.211.08:17:49.98#ibcon#about to read 3, iclass 39, count 2 2006.211.08:17:50.01#ibcon#read 3, iclass 39, count 2 2006.211.08:17:50.01#ibcon#about to read 4, iclass 39, count 2 2006.211.08:17:50.01#ibcon#read 4, iclass 39, count 2 2006.211.08:17:50.01#ibcon#about to read 5, iclass 39, count 2 2006.211.08:17:50.01#ibcon#read 5, iclass 39, count 2 2006.211.08:17:50.01#ibcon#about to read 6, iclass 39, count 2 2006.211.08:17:50.01#ibcon#read 6, iclass 39, count 2 2006.211.08:17:50.01#ibcon#end of sib2, iclass 39, count 2 2006.211.08:17:50.01#ibcon#*after write, iclass 39, count 2 2006.211.08:17:50.01#ibcon#*before return 0, iclass 39, count 2 2006.211.08:17:50.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:17:50.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:17:50.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:17:50.01#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:50.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:17:50.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:17:50.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:17:50.13#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:17:50.13#ibcon#first serial, iclass 39, count 0 2006.211.08:17:50.13#ibcon#enter sib2, iclass 39, count 0 2006.211.08:17:50.13#ibcon#flushed, iclass 39, count 0 2006.211.08:17:50.13#ibcon#about to write, iclass 39, count 0 2006.211.08:17:50.13#ibcon#wrote, iclass 39, count 0 2006.211.08:17:50.13#ibcon#about to read 3, iclass 39, count 0 2006.211.08:17:50.15#ibcon#read 3, iclass 39, count 0 2006.211.08:17:50.15#ibcon#about to read 4, iclass 39, count 0 2006.211.08:17:50.15#ibcon#read 4, iclass 39, count 0 2006.211.08:17:50.15#ibcon#about to read 5, iclass 39, count 0 2006.211.08:17:50.15#ibcon#read 5, iclass 39, count 0 2006.211.08:17:50.15#ibcon#about to read 6, iclass 39, count 0 2006.211.08:17:50.15#ibcon#read 6, iclass 39, count 0 2006.211.08:17:50.15#ibcon#end of sib2, iclass 39, count 0 2006.211.08:17:50.15#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:17:50.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:17:50.15#ibcon#[25=USB\r\n] 2006.211.08:17:50.15#ibcon#*before write, iclass 39, count 0 2006.211.08:17:50.15#ibcon#enter sib2, iclass 39, count 0 2006.211.08:17:50.15#ibcon#flushed, iclass 39, count 0 2006.211.08:17:50.15#ibcon#about to write, iclass 39, count 0 2006.211.08:17:50.15#ibcon#wrote, iclass 39, count 0 2006.211.08:17:50.15#ibcon#about to read 3, iclass 39, count 0 2006.211.08:17:50.18#ibcon#read 3, iclass 39, count 0 2006.211.08:17:50.18#ibcon#about to read 4, iclass 39, count 0 2006.211.08:17:50.18#ibcon#read 4, iclass 39, count 0 2006.211.08:17:50.18#ibcon#about to read 5, iclass 39, count 0 2006.211.08:17:50.18#ibcon#read 5, iclass 39, count 0 2006.211.08:17:50.18#ibcon#about to read 6, iclass 39, count 0 2006.211.08:17:50.18#ibcon#read 6, iclass 39, count 0 2006.211.08:17:50.18#ibcon#end of sib2, iclass 39, count 0 2006.211.08:17:50.18#ibcon#*after write, iclass 39, count 0 2006.211.08:17:50.18#ibcon#*before return 0, iclass 39, count 0 2006.211.08:17:50.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:17:50.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:17:50.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:17:50.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:17:50.18$vc4f8/vblo=1,632.99 2006.211.08:17:50.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:17:50.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:17:50.18#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:50.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:50.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:50.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:50.18#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:17:50.18#ibcon#first serial, iclass 3, count 0 2006.211.08:17:50.18#ibcon#enter sib2, iclass 3, count 0 2006.211.08:17:50.18#ibcon#flushed, iclass 3, count 0 2006.211.08:17:50.18#ibcon#about to write, iclass 3, count 0 2006.211.08:17:50.18#ibcon#wrote, iclass 3, count 0 2006.211.08:17:50.18#ibcon#about to read 3, iclass 3, count 0 2006.211.08:17:50.20#ibcon#read 3, iclass 3, count 0 2006.211.08:17:50.20#ibcon#about to read 4, iclass 3, count 0 2006.211.08:17:50.20#ibcon#read 4, iclass 3, count 0 2006.211.08:17:50.20#ibcon#about to read 5, iclass 3, count 0 2006.211.08:17:50.20#ibcon#read 5, iclass 3, count 0 2006.211.08:17:50.20#ibcon#about to read 6, iclass 3, count 0 2006.211.08:17:50.20#ibcon#read 6, iclass 3, count 0 2006.211.08:17:50.20#ibcon#end of sib2, iclass 3, count 0 2006.211.08:17:50.20#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:17:50.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:17:50.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:17:50.20#ibcon#*before write, iclass 3, count 0 2006.211.08:17:50.20#ibcon#enter sib2, iclass 3, count 0 2006.211.08:17:50.20#ibcon#flushed, iclass 3, count 0 2006.211.08:17:50.20#ibcon#about to write, iclass 3, count 0 2006.211.08:17:50.20#ibcon#wrote, iclass 3, count 0 2006.211.08:17:50.20#ibcon#about to read 3, iclass 3, count 0 2006.211.08:17:50.24#ibcon#read 3, iclass 3, count 0 2006.211.08:17:50.24#ibcon#about to read 4, iclass 3, count 0 2006.211.08:17:50.24#ibcon#read 4, iclass 3, count 0 2006.211.08:17:50.24#ibcon#about to read 5, iclass 3, count 0 2006.211.08:17:50.24#ibcon#read 5, iclass 3, count 0 2006.211.08:17:50.24#ibcon#about to read 6, iclass 3, count 0 2006.211.08:17:50.24#ibcon#read 6, iclass 3, count 0 2006.211.08:17:50.24#ibcon#end of sib2, iclass 3, count 0 2006.211.08:17:50.24#ibcon#*after write, iclass 3, count 0 2006.211.08:17:50.24#ibcon#*before return 0, iclass 3, count 0 2006.211.08:17:50.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:50.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:17:50.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:17:50.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:17:50.24$vc4f8/vb=1,4 2006.211.08:17:50.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:17:50.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:17:50.24#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:50.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:50.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:50.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:50.24#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:17:50.24#ibcon#first serial, iclass 5, count 2 2006.211.08:17:50.24#ibcon#enter sib2, iclass 5, count 2 2006.211.08:17:50.24#ibcon#flushed, iclass 5, count 2 2006.211.08:17:50.24#ibcon#about to write, iclass 5, count 2 2006.211.08:17:50.24#ibcon#wrote, iclass 5, count 2 2006.211.08:17:50.24#ibcon#about to read 3, iclass 5, count 2 2006.211.08:17:50.26#ibcon#read 3, iclass 5, count 2 2006.211.08:17:50.26#ibcon#about to read 4, iclass 5, count 2 2006.211.08:17:50.26#ibcon#read 4, iclass 5, count 2 2006.211.08:17:50.26#ibcon#about to read 5, iclass 5, count 2 2006.211.08:17:50.26#ibcon#read 5, iclass 5, count 2 2006.211.08:17:50.26#ibcon#about to read 6, iclass 5, count 2 2006.211.08:17:50.26#ibcon#read 6, iclass 5, count 2 2006.211.08:17:50.26#ibcon#end of sib2, iclass 5, count 2 2006.211.08:17:50.26#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:17:50.26#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:17:50.26#ibcon#[27=AT01-04\r\n] 2006.211.08:17:50.26#ibcon#*before write, iclass 5, count 2 2006.211.08:17:50.26#ibcon#enter sib2, iclass 5, count 2 2006.211.08:17:50.26#ibcon#flushed, iclass 5, count 2 2006.211.08:17:50.26#ibcon#about to write, iclass 5, count 2 2006.211.08:17:50.26#ibcon#wrote, iclass 5, count 2 2006.211.08:17:50.26#ibcon#about to read 3, iclass 5, count 2 2006.211.08:17:50.29#ibcon#read 3, iclass 5, count 2 2006.211.08:17:50.29#ibcon#about to read 4, iclass 5, count 2 2006.211.08:17:50.29#ibcon#read 4, iclass 5, count 2 2006.211.08:17:50.29#ibcon#about to read 5, iclass 5, count 2 2006.211.08:17:50.29#ibcon#read 5, iclass 5, count 2 2006.211.08:17:50.29#ibcon#about to read 6, iclass 5, count 2 2006.211.08:17:50.29#ibcon#read 6, iclass 5, count 2 2006.211.08:17:50.29#ibcon#end of sib2, iclass 5, count 2 2006.211.08:17:50.29#ibcon#*after write, iclass 5, count 2 2006.211.08:17:50.29#ibcon#*before return 0, iclass 5, count 2 2006.211.08:17:50.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:50.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:17:50.29#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:17:50.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:50.29#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:50.41#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:50.41#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:50.41#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:17:50.41#ibcon#first serial, iclass 5, count 0 2006.211.08:17:50.41#ibcon#enter sib2, iclass 5, count 0 2006.211.08:17:50.41#ibcon#flushed, iclass 5, count 0 2006.211.08:17:50.41#ibcon#about to write, iclass 5, count 0 2006.211.08:17:50.41#ibcon#wrote, iclass 5, count 0 2006.211.08:17:50.41#ibcon#about to read 3, iclass 5, count 0 2006.211.08:17:50.43#ibcon#read 3, iclass 5, count 0 2006.211.08:17:50.43#ibcon#about to read 4, iclass 5, count 0 2006.211.08:17:50.43#ibcon#read 4, iclass 5, count 0 2006.211.08:17:50.43#ibcon#about to read 5, iclass 5, count 0 2006.211.08:17:50.43#ibcon#read 5, iclass 5, count 0 2006.211.08:17:50.43#ibcon#about to read 6, iclass 5, count 0 2006.211.08:17:50.43#ibcon#read 6, iclass 5, count 0 2006.211.08:17:50.43#ibcon#end of sib2, iclass 5, count 0 2006.211.08:17:50.43#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:17:50.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:17:50.43#ibcon#[27=USB\r\n] 2006.211.08:17:50.43#ibcon#*before write, iclass 5, count 0 2006.211.08:17:50.43#ibcon#enter sib2, iclass 5, count 0 2006.211.08:17:50.43#ibcon#flushed, iclass 5, count 0 2006.211.08:17:50.43#ibcon#about to write, iclass 5, count 0 2006.211.08:17:50.43#ibcon#wrote, iclass 5, count 0 2006.211.08:17:50.43#ibcon#about to read 3, iclass 5, count 0 2006.211.08:17:50.46#ibcon#read 3, iclass 5, count 0 2006.211.08:17:50.46#ibcon#about to read 4, iclass 5, count 0 2006.211.08:17:50.46#ibcon#read 4, iclass 5, count 0 2006.211.08:17:50.46#ibcon#about to read 5, iclass 5, count 0 2006.211.08:17:50.46#ibcon#read 5, iclass 5, count 0 2006.211.08:17:50.46#ibcon#about to read 6, iclass 5, count 0 2006.211.08:17:50.46#ibcon#read 6, iclass 5, count 0 2006.211.08:17:50.46#ibcon#end of sib2, iclass 5, count 0 2006.211.08:17:50.46#ibcon#*after write, iclass 5, count 0 2006.211.08:17:50.46#ibcon#*before return 0, iclass 5, count 0 2006.211.08:17:50.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:50.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:17:50.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:17:50.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:17:50.46$vc4f8/vblo=2,640.99 2006.211.08:17:50.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:17:50.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:17:50.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:50.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:50.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:50.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:50.46#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:17:50.46#ibcon#first serial, iclass 7, count 0 2006.211.08:17:50.46#ibcon#enter sib2, iclass 7, count 0 2006.211.08:17:50.46#ibcon#flushed, iclass 7, count 0 2006.211.08:17:50.46#ibcon#about to write, iclass 7, count 0 2006.211.08:17:50.46#ibcon#wrote, iclass 7, count 0 2006.211.08:17:50.46#ibcon#about to read 3, iclass 7, count 0 2006.211.08:17:50.48#ibcon#read 3, iclass 7, count 0 2006.211.08:17:50.48#ibcon#about to read 4, iclass 7, count 0 2006.211.08:17:50.48#ibcon#read 4, iclass 7, count 0 2006.211.08:17:50.48#ibcon#about to read 5, iclass 7, count 0 2006.211.08:17:50.48#ibcon#read 5, iclass 7, count 0 2006.211.08:17:50.48#ibcon#about to read 6, iclass 7, count 0 2006.211.08:17:50.48#ibcon#read 6, iclass 7, count 0 2006.211.08:17:50.48#ibcon#end of sib2, iclass 7, count 0 2006.211.08:17:50.48#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:17:50.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:17:50.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:17:50.48#ibcon#*before write, iclass 7, count 0 2006.211.08:17:50.48#ibcon#enter sib2, iclass 7, count 0 2006.211.08:17:50.48#ibcon#flushed, iclass 7, count 0 2006.211.08:17:50.48#ibcon#about to write, iclass 7, count 0 2006.211.08:17:50.48#ibcon#wrote, iclass 7, count 0 2006.211.08:17:50.48#ibcon#about to read 3, iclass 7, count 0 2006.211.08:17:50.52#ibcon#read 3, iclass 7, count 0 2006.211.08:17:50.52#ibcon#about to read 4, iclass 7, count 0 2006.211.08:17:50.52#ibcon#read 4, iclass 7, count 0 2006.211.08:17:50.52#ibcon#about to read 5, iclass 7, count 0 2006.211.08:17:50.52#ibcon#read 5, iclass 7, count 0 2006.211.08:17:50.52#ibcon#about to read 6, iclass 7, count 0 2006.211.08:17:50.52#ibcon#read 6, iclass 7, count 0 2006.211.08:17:50.52#ibcon#end of sib2, iclass 7, count 0 2006.211.08:17:50.52#ibcon#*after write, iclass 7, count 0 2006.211.08:17:50.52#ibcon#*before return 0, iclass 7, count 0 2006.211.08:17:50.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:50.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:17:50.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:17:50.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:17:50.52$vc4f8/vb=2,4 2006.211.08:17:50.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:17:50.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:17:50.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:50.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:50.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:50.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:50.58#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:17:50.58#ibcon#first serial, iclass 11, count 2 2006.211.08:17:50.58#ibcon#enter sib2, iclass 11, count 2 2006.211.08:17:50.58#ibcon#flushed, iclass 11, count 2 2006.211.08:17:50.58#ibcon#about to write, iclass 11, count 2 2006.211.08:17:50.58#ibcon#wrote, iclass 11, count 2 2006.211.08:17:50.58#ibcon#about to read 3, iclass 11, count 2 2006.211.08:17:50.60#ibcon#read 3, iclass 11, count 2 2006.211.08:17:50.60#ibcon#about to read 4, iclass 11, count 2 2006.211.08:17:50.60#ibcon#read 4, iclass 11, count 2 2006.211.08:17:50.60#ibcon#about to read 5, iclass 11, count 2 2006.211.08:17:50.60#ibcon#read 5, iclass 11, count 2 2006.211.08:17:50.60#ibcon#about to read 6, iclass 11, count 2 2006.211.08:17:50.60#ibcon#read 6, iclass 11, count 2 2006.211.08:17:50.60#ibcon#end of sib2, iclass 11, count 2 2006.211.08:17:50.60#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:17:50.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:17:50.60#ibcon#[27=AT02-04\r\n] 2006.211.08:17:50.60#ibcon#*before write, iclass 11, count 2 2006.211.08:17:50.60#ibcon#enter sib2, iclass 11, count 2 2006.211.08:17:50.60#ibcon#flushed, iclass 11, count 2 2006.211.08:17:50.60#ibcon#about to write, iclass 11, count 2 2006.211.08:17:50.60#ibcon#wrote, iclass 11, count 2 2006.211.08:17:50.60#ibcon#about to read 3, iclass 11, count 2 2006.211.08:17:50.63#ibcon#read 3, iclass 11, count 2 2006.211.08:17:50.63#ibcon#about to read 4, iclass 11, count 2 2006.211.08:17:50.63#ibcon#read 4, iclass 11, count 2 2006.211.08:17:50.63#ibcon#about to read 5, iclass 11, count 2 2006.211.08:17:50.63#ibcon#read 5, iclass 11, count 2 2006.211.08:17:50.63#ibcon#about to read 6, iclass 11, count 2 2006.211.08:17:50.63#ibcon#read 6, iclass 11, count 2 2006.211.08:17:50.63#ibcon#end of sib2, iclass 11, count 2 2006.211.08:17:50.63#ibcon#*after write, iclass 11, count 2 2006.211.08:17:50.63#ibcon#*before return 0, iclass 11, count 2 2006.211.08:17:50.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:50.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:17:50.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:17:50.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:50.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:50.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:50.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:50.75#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:17:50.75#ibcon#first serial, iclass 11, count 0 2006.211.08:17:50.75#ibcon#enter sib2, iclass 11, count 0 2006.211.08:17:50.75#ibcon#flushed, iclass 11, count 0 2006.211.08:17:50.75#ibcon#about to write, iclass 11, count 0 2006.211.08:17:50.75#ibcon#wrote, iclass 11, count 0 2006.211.08:17:50.75#ibcon#about to read 3, iclass 11, count 0 2006.211.08:17:50.77#ibcon#read 3, iclass 11, count 0 2006.211.08:17:50.77#ibcon#about to read 4, iclass 11, count 0 2006.211.08:17:50.77#ibcon#read 4, iclass 11, count 0 2006.211.08:17:50.77#ibcon#about to read 5, iclass 11, count 0 2006.211.08:17:50.77#ibcon#read 5, iclass 11, count 0 2006.211.08:17:50.77#ibcon#about to read 6, iclass 11, count 0 2006.211.08:17:50.77#ibcon#read 6, iclass 11, count 0 2006.211.08:17:50.77#ibcon#end of sib2, iclass 11, count 0 2006.211.08:17:50.77#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:17:50.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:17:50.77#ibcon#[27=USB\r\n] 2006.211.08:17:50.77#ibcon#*before write, iclass 11, count 0 2006.211.08:17:50.77#ibcon#enter sib2, iclass 11, count 0 2006.211.08:17:50.77#ibcon#flushed, iclass 11, count 0 2006.211.08:17:50.77#ibcon#about to write, iclass 11, count 0 2006.211.08:17:50.77#ibcon#wrote, iclass 11, count 0 2006.211.08:17:50.77#ibcon#about to read 3, iclass 11, count 0 2006.211.08:17:50.80#ibcon#read 3, iclass 11, count 0 2006.211.08:17:50.80#ibcon#about to read 4, iclass 11, count 0 2006.211.08:17:50.80#ibcon#read 4, iclass 11, count 0 2006.211.08:17:50.80#ibcon#about to read 5, iclass 11, count 0 2006.211.08:17:50.80#ibcon#read 5, iclass 11, count 0 2006.211.08:17:50.80#ibcon#about to read 6, iclass 11, count 0 2006.211.08:17:50.80#ibcon#read 6, iclass 11, count 0 2006.211.08:17:50.80#ibcon#end of sib2, iclass 11, count 0 2006.211.08:17:50.80#ibcon#*after write, iclass 11, count 0 2006.211.08:17:50.80#ibcon#*before return 0, iclass 11, count 0 2006.211.08:17:50.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:50.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:17:50.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:17:50.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:17:50.80$vc4f8/vblo=3,656.99 2006.211.08:17:50.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:17:50.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:17:50.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:50.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:50.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:50.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:50.80#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:17:50.80#ibcon#first serial, iclass 13, count 0 2006.211.08:17:50.80#ibcon#enter sib2, iclass 13, count 0 2006.211.08:17:50.80#ibcon#flushed, iclass 13, count 0 2006.211.08:17:50.80#ibcon#about to write, iclass 13, count 0 2006.211.08:17:50.80#ibcon#wrote, iclass 13, count 0 2006.211.08:17:50.80#ibcon#about to read 3, iclass 13, count 0 2006.211.08:17:50.82#ibcon#read 3, iclass 13, count 0 2006.211.08:17:50.82#ibcon#about to read 4, iclass 13, count 0 2006.211.08:17:50.82#ibcon#read 4, iclass 13, count 0 2006.211.08:17:50.82#ibcon#about to read 5, iclass 13, count 0 2006.211.08:17:50.82#ibcon#read 5, iclass 13, count 0 2006.211.08:17:50.82#ibcon#about to read 6, iclass 13, count 0 2006.211.08:17:50.82#ibcon#read 6, iclass 13, count 0 2006.211.08:17:50.82#ibcon#end of sib2, iclass 13, count 0 2006.211.08:17:50.82#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:17:50.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:17:50.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:17:50.82#ibcon#*before write, iclass 13, count 0 2006.211.08:17:50.82#ibcon#enter sib2, iclass 13, count 0 2006.211.08:17:50.82#ibcon#flushed, iclass 13, count 0 2006.211.08:17:50.82#ibcon#about to write, iclass 13, count 0 2006.211.08:17:50.82#ibcon#wrote, iclass 13, count 0 2006.211.08:17:50.82#ibcon#about to read 3, iclass 13, count 0 2006.211.08:17:50.86#ibcon#read 3, iclass 13, count 0 2006.211.08:17:50.86#ibcon#about to read 4, iclass 13, count 0 2006.211.08:17:50.86#ibcon#read 4, iclass 13, count 0 2006.211.08:17:50.86#ibcon#about to read 5, iclass 13, count 0 2006.211.08:17:50.86#ibcon#read 5, iclass 13, count 0 2006.211.08:17:50.86#ibcon#about to read 6, iclass 13, count 0 2006.211.08:17:50.86#ibcon#read 6, iclass 13, count 0 2006.211.08:17:50.86#ibcon#end of sib2, iclass 13, count 0 2006.211.08:17:50.86#ibcon#*after write, iclass 13, count 0 2006.211.08:17:50.86#ibcon#*before return 0, iclass 13, count 0 2006.211.08:17:50.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:50.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:17:50.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:17:50.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:17:50.86$vc4f8/vb=3,3 2006.211.08:17:50.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:17:50.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:17:50.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:50.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:50.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:50.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:50.92#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:17:50.92#ibcon#first serial, iclass 15, count 2 2006.211.08:17:50.92#ibcon#enter sib2, iclass 15, count 2 2006.211.08:17:50.92#ibcon#flushed, iclass 15, count 2 2006.211.08:17:50.92#ibcon#about to write, iclass 15, count 2 2006.211.08:17:50.92#ibcon#wrote, iclass 15, count 2 2006.211.08:17:50.92#ibcon#about to read 3, iclass 15, count 2 2006.211.08:17:50.94#ibcon#read 3, iclass 15, count 2 2006.211.08:17:50.94#ibcon#about to read 4, iclass 15, count 2 2006.211.08:17:50.94#ibcon#read 4, iclass 15, count 2 2006.211.08:17:50.94#ibcon#about to read 5, iclass 15, count 2 2006.211.08:17:50.94#ibcon#read 5, iclass 15, count 2 2006.211.08:17:50.94#ibcon#about to read 6, iclass 15, count 2 2006.211.08:17:50.94#ibcon#read 6, iclass 15, count 2 2006.211.08:17:50.94#ibcon#end of sib2, iclass 15, count 2 2006.211.08:17:50.94#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:17:50.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:17:50.94#ibcon#[27=AT03-03\r\n] 2006.211.08:17:50.94#ibcon#*before write, iclass 15, count 2 2006.211.08:17:50.94#ibcon#enter sib2, iclass 15, count 2 2006.211.08:17:50.94#ibcon#flushed, iclass 15, count 2 2006.211.08:17:50.94#ibcon#about to write, iclass 15, count 2 2006.211.08:17:50.94#ibcon#wrote, iclass 15, count 2 2006.211.08:17:50.94#ibcon#about to read 3, iclass 15, count 2 2006.211.08:17:50.97#ibcon#read 3, iclass 15, count 2 2006.211.08:17:50.97#ibcon#about to read 4, iclass 15, count 2 2006.211.08:17:50.97#ibcon#read 4, iclass 15, count 2 2006.211.08:17:50.97#ibcon#about to read 5, iclass 15, count 2 2006.211.08:17:50.97#ibcon#read 5, iclass 15, count 2 2006.211.08:17:50.97#ibcon#about to read 6, iclass 15, count 2 2006.211.08:17:50.97#ibcon#read 6, iclass 15, count 2 2006.211.08:17:50.97#ibcon#end of sib2, iclass 15, count 2 2006.211.08:17:50.97#ibcon#*after write, iclass 15, count 2 2006.211.08:17:50.97#ibcon#*before return 0, iclass 15, count 2 2006.211.08:17:50.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:50.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:17:50.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:17:50.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:50.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:51.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:51.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:51.09#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:17:51.09#ibcon#first serial, iclass 15, count 0 2006.211.08:17:51.09#ibcon#enter sib2, iclass 15, count 0 2006.211.08:17:51.09#ibcon#flushed, iclass 15, count 0 2006.211.08:17:51.09#ibcon#about to write, iclass 15, count 0 2006.211.08:17:51.09#ibcon#wrote, iclass 15, count 0 2006.211.08:17:51.09#ibcon#about to read 3, iclass 15, count 0 2006.211.08:17:51.11#ibcon#read 3, iclass 15, count 0 2006.211.08:17:51.11#ibcon#about to read 4, iclass 15, count 0 2006.211.08:17:51.11#ibcon#read 4, iclass 15, count 0 2006.211.08:17:51.11#ibcon#about to read 5, iclass 15, count 0 2006.211.08:17:51.11#ibcon#read 5, iclass 15, count 0 2006.211.08:17:51.11#ibcon#about to read 6, iclass 15, count 0 2006.211.08:17:51.11#ibcon#read 6, iclass 15, count 0 2006.211.08:17:51.11#ibcon#end of sib2, iclass 15, count 0 2006.211.08:17:51.11#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:17:51.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:17:51.11#ibcon#[27=USB\r\n] 2006.211.08:17:51.11#ibcon#*before write, iclass 15, count 0 2006.211.08:17:51.11#ibcon#enter sib2, iclass 15, count 0 2006.211.08:17:51.11#ibcon#flushed, iclass 15, count 0 2006.211.08:17:51.11#ibcon#about to write, iclass 15, count 0 2006.211.08:17:51.11#ibcon#wrote, iclass 15, count 0 2006.211.08:17:51.11#ibcon#about to read 3, iclass 15, count 0 2006.211.08:17:51.14#ibcon#read 3, iclass 15, count 0 2006.211.08:17:51.14#ibcon#about to read 4, iclass 15, count 0 2006.211.08:17:51.14#ibcon#read 4, iclass 15, count 0 2006.211.08:17:51.14#ibcon#about to read 5, iclass 15, count 0 2006.211.08:17:51.14#ibcon#read 5, iclass 15, count 0 2006.211.08:17:51.14#ibcon#about to read 6, iclass 15, count 0 2006.211.08:17:51.14#ibcon#read 6, iclass 15, count 0 2006.211.08:17:51.14#ibcon#end of sib2, iclass 15, count 0 2006.211.08:17:51.14#ibcon#*after write, iclass 15, count 0 2006.211.08:17:51.14#ibcon#*before return 0, iclass 15, count 0 2006.211.08:17:51.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:51.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:17:51.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:17:51.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:17:51.14$vc4f8/vblo=4,712.99 2006.211.08:17:51.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:17:51.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:17:51.14#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:51.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:51.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:51.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:51.14#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:17:51.14#ibcon#first serial, iclass 17, count 0 2006.211.08:17:51.14#ibcon#enter sib2, iclass 17, count 0 2006.211.08:17:51.14#ibcon#flushed, iclass 17, count 0 2006.211.08:17:51.14#ibcon#about to write, iclass 17, count 0 2006.211.08:17:51.14#ibcon#wrote, iclass 17, count 0 2006.211.08:17:51.14#ibcon#about to read 3, iclass 17, count 0 2006.211.08:17:51.16#ibcon#read 3, iclass 17, count 0 2006.211.08:17:51.16#ibcon#about to read 4, iclass 17, count 0 2006.211.08:17:51.16#ibcon#read 4, iclass 17, count 0 2006.211.08:17:51.16#ibcon#about to read 5, iclass 17, count 0 2006.211.08:17:51.16#ibcon#read 5, iclass 17, count 0 2006.211.08:17:51.16#ibcon#about to read 6, iclass 17, count 0 2006.211.08:17:51.16#ibcon#read 6, iclass 17, count 0 2006.211.08:17:51.16#ibcon#end of sib2, iclass 17, count 0 2006.211.08:17:51.16#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:17:51.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:17:51.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:17:51.16#ibcon#*before write, iclass 17, count 0 2006.211.08:17:51.16#ibcon#enter sib2, iclass 17, count 0 2006.211.08:17:51.16#ibcon#flushed, iclass 17, count 0 2006.211.08:17:51.16#ibcon#about to write, iclass 17, count 0 2006.211.08:17:51.16#ibcon#wrote, iclass 17, count 0 2006.211.08:17:51.16#ibcon#about to read 3, iclass 17, count 0 2006.211.08:17:51.20#ibcon#read 3, iclass 17, count 0 2006.211.08:17:51.20#ibcon#about to read 4, iclass 17, count 0 2006.211.08:17:51.20#ibcon#read 4, iclass 17, count 0 2006.211.08:17:51.20#ibcon#about to read 5, iclass 17, count 0 2006.211.08:17:51.20#ibcon#read 5, iclass 17, count 0 2006.211.08:17:51.20#ibcon#about to read 6, iclass 17, count 0 2006.211.08:17:51.20#ibcon#read 6, iclass 17, count 0 2006.211.08:17:51.20#ibcon#end of sib2, iclass 17, count 0 2006.211.08:17:51.20#ibcon#*after write, iclass 17, count 0 2006.211.08:17:51.20#ibcon#*before return 0, iclass 17, count 0 2006.211.08:17:51.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:51.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:17:51.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:17:51.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:17:51.20$vc4f8/vb=4,3 2006.211.08:17:51.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:17:51.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:17:51.20#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:51.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:51.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:51.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:51.26#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:17:51.26#ibcon#first serial, iclass 19, count 2 2006.211.08:17:51.26#ibcon#enter sib2, iclass 19, count 2 2006.211.08:17:51.26#ibcon#flushed, iclass 19, count 2 2006.211.08:17:51.26#ibcon#about to write, iclass 19, count 2 2006.211.08:17:51.26#ibcon#wrote, iclass 19, count 2 2006.211.08:17:51.26#ibcon#about to read 3, iclass 19, count 2 2006.211.08:17:51.28#ibcon#read 3, iclass 19, count 2 2006.211.08:17:51.28#ibcon#about to read 4, iclass 19, count 2 2006.211.08:17:51.28#ibcon#read 4, iclass 19, count 2 2006.211.08:17:51.28#ibcon#about to read 5, iclass 19, count 2 2006.211.08:17:51.28#ibcon#read 5, iclass 19, count 2 2006.211.08:17:51.28#ibcon#about to read 6, iclass 19, count 2 2006.211.08:17:51.28#ibcon#read 6, iclass 19, count 2 2006.211.08:17:51.28#ibcon#end of sib2, iclass 19, count 2 2006.211.08:17:51.28#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:17:51.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:17:51.28#ibcon#[27=AT04-03\r\n] 2006.211.08:17:51.28#ibcon#*before write, iclass 19, count 2 2006.211.08:17:51.28#ibcon#enter sib2, iclass 19, count 2 2006.211.08:17:51.28#ibcon#flushed, iclass 19, count 2 2006.211.08:17:51.28#ibcon#about to write, iclass 19, count 2 2006.211.08:17:51.28#ibcon#wrote, iclass 19, count 2 2006.211.08:17:51.28#ibcon#about to read 3, iclass 19, count 2 2006.211.08:17:51.31#ibcon#read 3, iclass 19, count 2 2006.211.08:17:51.31#ibcon#about to read 4, iclass 19, count 2 2006.211.08:17:51.31#ibcon#read 4, iclass 19, count 2 2006.211.08:17:51.31#ibcon#about to read 5, iclass 19, count 2 2006.211.08:17:51.31#ibcon#read 5, iclass 19, count 2 2006.211.08:17:51.31#ibcon#about to read 6, iclass 19, count 2 2006.211.08:17:51.31#ibcon#read 6, iclass 19, count 2 2006.211.08:17:51.31#ibcon#end of sib2, iclass 19, count 2 2006.211.08:17:51.31#ibcon#*after write, iclass 19, count 2 2006.211.08:17:51.31#ibcon#*before return 0, iclass 19, count 2 2006.211.08:17:51.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:51.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:17:51.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:17:51.31#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:51.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:51.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:51.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:51.43#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:17:51.43#ibcon#first serial, iclass 19, count 0 2006.211.08:17:51.43#ibcon#enter sib2, iclass 19, count 0 2006.211.08:17:51.43#ibcon#flushed, iclass 19, count 0 2006.211.08:17:51.43#ibcon#about to write, iclass 19, count 0 2006.211.08:17:51.43#ibcon#wrote, iclass 19, count 0 2006.211.08:17:51.43#ibcon#about to read 3, iclass 19, count 0 2006.211.08:17:51.45#ibcon#read 3, iclass 19, count 0 2006.211.08:17:51.45#ibcon#about to read 4, iclass 19, count 0 2006.211.08:17:51.45#ibcon#read 4, iclass 19, count 0 2006.211.08:17:51.45#ibcon#about to read 5, iclass 19, count 0 2006.211.08:17:51.45#ibcon#read 5, iclass 19, count 0 2006.211.08:17:51.45#ibcon#about to read 6, iclass 19, count 0 2006.211.08:17:51.45#ibcon#read 6, iclass 19, count 0 2006.211.08:17:51.45#ibcon#end of sib2, iclass 19, count 0 2006.211.08:17:51.45#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:17:51.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:17:51.45#ibcon#[27=USB\r\n] 2006.211.08:17:51.45#ibcon#*before write, iclass 19, count 0 2006.211.08:17:51.45#ibcon#enter sib2, iclass 19, count 0 2006.211.08:17:51.45#ibcon#flushed, iclass 19, count 0 2006.211.08:17:51.45#ibcon#about to write, iclass 19, count 0 2006.211.08:17:51.45#ibcon#wrote, iclass 19, count 0 2006.211.08:17:51.45#ibcon#about to read 3, iclass 19, count 0 2006.211.08:17:51.48#ibcon#read 3, iclass 19, count 0 2006.211.08:17:51.48#ibcon#about to read 4, iclass 19, count 0 2006.211.08:17:51.48#ibcon#read 4, iclass 19, count 0 2006.211.08:17:51.48#ibcon#about to read 5, iclass 19, count 0 2006.211.08:17:51.48#ibcon#read 5, iclass 19, count 0 2006.211.08:17:51.48#ibcon#about to read 6, iclass 19, count 0 2006.211.08:17:51.48#ibcon#read 6, iclass 19, count 0 2006.211.08:17:51.48#ibcon#end of sib2, iclass 19, count 0 2006.211.08:17:51.48#ibcon#*after write, iclass 19, count 0 2006.211.08:17:51.48#ibcon#*before return 0, iclass 19, count 0 2006.211.08:17:51.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:51.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:17:51.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:17:51.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:17:51.48$vc4f8/vblo=5,744.99 2006.211.08:17:51.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:17:51.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:17:51.48#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:51.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:51.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:51.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:51.48#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:17:51.48#ibcon#first serial, iclass 21, count 0 2006.211.08:17:51.48#ibcon#enter sib2, iclass 21, count 0 2006.211.08:17:51.48#ibcon#flushed, iclass 21, count 0 2006.211.08:17:51.48#ibcon#about to write, iclass 21, count 0 2006.211.08:17:51.48#ibcon#wrote, iclass 21, count 0 2006.211.08:17:51.48#ibcon#about to read 3, iclass 21, count 0 2006.211.08:17:51.50#ibcon#read 3, iclass 21, count 0 2006.211.08:17:51.50#ibcon#about to read 4, iclass 21, count 0 2006.211.08:17:51.50#ibcon#read 4, iclass 21, count 0 2006.211.08:17:51.50#ibcon#about to read 5, iclass 21, count 0 2006.211.08:17:51.50#ibcon#read 5, iclass 21, count 0 2006.211.08:17:51.50#ibcon#about to read 6, iclass 21, count 0 2006.211.08:17:51.50#ibcon#read 6, iclass 21, count 0 2006.211.08:17:51.50#ibcon#end of sib2, iclass 21, count 0 2006.211.08:17:51.50#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:17:51.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:17:51.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:17:51.50#ibcon#*before write, iclass 21, count 0 2006.211.08:17:51.50#ibcon#enter sib2, iclass 21, count 0 2006.211.08:17:51.50#ibcon#flushed, iclass 21, count 0 2006.211.08:17:51.50#ibcon#about to write, iclass 21, count 0 2006.211.08:17:51.50#ibcon#wrote, iclass 21, count 0 2006.211.08:17:51.50#ibcon#about to read 3, iclass 21, count 0 2006.211.08:17:51.54#ibcon#read 3, iclass 21, count 0 2006.211.08:17:51.54#ibcon#about to read 4, iclass 21, count 0 2006.211.08:17:51.54#ibcon#read 4, iclass 21, count 0 2006.211.08:17:51.54#ibcon#about to read 5, iclass 21, count 0 2006.211.08:17:51.54#ibcon#read 5, iclass 21, count 0 2006.211.08:17:51.54#ibcon#about to read 6, iclass 21, count 0 2006.211.08:17:51.54#ibcon#read 6, iclass 21, count 0 2006.211.08:17:51.54#ibcon#end of sib2, iclass 21, count 0 2006.211.08:17:51.54#ibcon#*after write, iclass 21, count 0 2006.211.08:17:51.54#ibcon#*before return 0, iclass 21, count 0 2006.211.08:17:51.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:51.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:17:51.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:17:51.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:17:51.54$vc4f8/vb=5,3 2006.211.08:17:51.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:17:51.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:17:51.54#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:51.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:51.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:51.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:51.60#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:17:51.60#ibcon#first serial, iclass 23, count 2 2006.211.08:17:51.60#ibcon#enter sib2, iclass 23, count 2 2006.211.08:17:51.60#ibcon#flushed, iclass 23, count 2 2006.211.08:17:51.60#ibcon#about to write, iclass 23, count 2 2006.211.08:17:51.60#ibcon#wrote, iclass 23, count 2 2006.211.08:17:51.60#ibcon#about to read 3, iclass 23, count 2 2006.211.08:17:51.62#ibcon#read 3, iclass 23, count 2 2006.211.08:17:51.62#ibcon#about to read 4, iclass 23, count 2 2006.211.08:17:51.62#ibcon#read 4, iclass 23, count 2 2006.211.08:17:51.62#ibcon#about to read 5, iclass 23, count 2 2006.211.08:17:51.62#ibcon#read 5, iclass 23, count 2 2006.211.08:17:51.62#ibcon#about to read 6, iclass 23, count 2 2006.211.08:17:51.62#ibcon#read 6, iclass 23, count 2 2006.211.08:17:51.62#ibcon#end of sib2, iclass 23, count 2 2006.211.08:17:51.62#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:17:51.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:17:51.62#ibcon#[27=AT05-03\r\n] 2006.211.08:17:51.62#ibcon#*before write, iclass 23, count 2 2006.211.08:17:51.62#ibcon#enter sib2, iclass 23, count 2 2006.211.08:17:51.62#ibcon#flushed, iclass 23, count 2 2006.211.08:17:51.62#ibcon#about to write, iclass 23, count 2 2006.211.08:17:51.62#ibcon#wrote, iclass 23, count 2 2006.211.08:17:51.62#ibcon#about to read 3, iclass 23, count 2 2006.211.08:17:51.65#ibcon#read 3, iclass 23, count 2 2006.211.08:17:51.65#ibcon#about to read 4, iclass 23, count 2 2006.211.08:17:51.65#ibcon#read 4, iclass 23, count 2 2006.211.08:17:51.65#ibcon#about to read 5, iclass 23, count 2 2006.211.08:17:51.65#ibcon#read 5, iclass 23, count 2 2006.211.08:17:51.65#ibcon#about to read 6, iclass 23, count 2 2006.211.08:17:51.65#ibcon#read 6, iclass 23, count 2 2006.211.08:17:51.65#ibcon#end of sib2, iclass 23, count 2 2006.211.08:17:51.65#ibcon#*after write, iclass 23, count 2 2006.211.08:17:51.65#ibcon#*before return 0, iclass 23, count 2 2006.211.08:17:51.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:51.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:17:51.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:17:51.65#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:51.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:51.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:51.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:51.77#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:17:51.77#ibcon#first serial, iclass 23, count 0 2006.211.08:17:51.77#ibcon#enter sib2, iclass 23, count 0 2006.211.08:17:51.77#ibcon#flushed, iclass 23, count 0 2006.211.08:17:51.77#ibcon#about to write, iclass 23, count 0 2006.211.08:17:51.77#ibcon#wrote, iclass 23, count 0 2006.211.08:17:51.77#ibcon#about to read 3, iclass 23, count 0 2006.211.08:17:51.79#ibcon#read 3, iclass 23, count 0 2006.211.08:17:51.79#ibcon#about to read 4, iclass 23, count 0 2006.211.08:17:51.79#ibcon#read 4, iclass 23, count 0 2006.211.08:17:51.79#ibcon#about to read 5, iclass 23, count 0 2006.211.08:17:51.79#ibcon#read 5, iclass 23, count 0 2006.211.08:17:51.79#ibcon#about to read 6, iclass 23, count 0 2006.211.08:17:51.79#ibcon#read 6, iclass 23, count 0 2006.211.08:17:51.79#ibcon#end of sib2, iclass 23, count 0 2006.211.08:17:51.79#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:17:51.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:17:51.79#ibcon#[27=USB\r\n] 2006.211.08:17:51.79#ibcon#*before write, iclass 23, count 0 2006.211.08:17:51.79#ibcon#enter sib2, iclass 23, count 0 2006.211.08:17:51.79#ibcon#flushed, iclass 23, count 0 2006.211.08:17:51.79#ibcon#about to write, iclass 23, count 0 2006.211.08:17:51.79#ibcon#wrote, iclass 23, count 0 2006.211.08:17:51.79#ibcon#about to read 3, iclass 23, count 0 2006.211.08:17:51.82#ibcon#read 3, iclass 23, count 0 2006.211.08:17:51.82#ibcon#about to read 4, iclass 23, count 0 2006.211.08:17:51.82#ibcon#read 4, iclass 23, count 0 2006.211.08:17:51.82#ibcon#about to read 5, iclass 23, count 0 2006.211.08:17:51.82#ibcon#read 5, iclass 23, count 0 2006.211.08:17:51.82#ibcon#about to read 6, iclass 23, count 0 2006.211.08:17:51.82#ibcon#read 6, iclass 23, count 0 2006.211.08:17:51.82#ibcon#end of sib2, iclass 23, count 0 2006.211.08:17:51.82#ibcon#*after write, iclass 23, count 0 2006.211.08:17:51.82#ibcon#*before return 0, iclass 23, count 0 2006.211.08:17:51.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:51.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:17:51.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:17:51.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:17:51.82$vc4f8/vblo=6,752.99 2006.211.08:17:51.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:17:51.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:17:51.82#ibcon#ireg 17 cls_cnt 0 2006.211.08:17:51.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:51.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:51.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:51.82#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:17:51.82#ibcon#first serial, iclass 25, count 0 2006.211.08:17:51.82#ibcon#enter sib2, iclass 25, count 0 2006.211.08:17:51.82#ibcon#flushed, iclass 25, count 0 2006.211.08:17:51.82#ibcon#about to write, iclass 25, count 0 2006.211.08:17:51.82#ibcon#wrote, iclass 25, count 0 2006.211.08:17:51.82#ibcon#about to read 3, iclass 25, count 0 2006.211.08:17:51.84#ibcon#read 3, iclass 25, count 0 2006.211.08:17:51.84#ibcon#about to read 4, iclass 25, count 0 2006.211.08:17:51.84#ibcon#read 4, iclass 25, count 0 2006.211.08:17:51.84#ibcon#about to read 5, iclass 25, count 0 2006.211.08:17:51.84#ibcon#read 5, iclass 25, count 0 2006.211.08:17:51.84#ibcon#about to read 6, iclass 25, count 0 2006.211.08:17:51.84#ibcon#read 6, iclass 25, count 0 2006.211.08:17:51.84#ibcon#end of sib2, iclass 25, count 0 2006.211.08:17:51.84#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:17:51.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:17:51.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:17:51.84#ibcon#*before write, iclass 25, count 0 2006.211.08:17:51.84#ibcon#enter sib2, iclass 25, count 0 2006.211.08:17:51.84#ibcon#flushed, iclass 25, count 0 2006.211.08:17:51.84#ibcon#about to write, iclass 25, count 0 2006.211.08:17:51.84#ibcon#wrote, iclass 25, count 0 2006.211.08:17:51.84#ibcon#about to read 3, iclass 25, count 0 2006.211.08:17:51.88#ibcon#read 3, iclass 25, count 0 2006.211.08:17:51.88#ibcon#about to read 4, iclass 25, count 0 2006.211.08:17:51.88#ibcon#read 4, iclass 25, count 0 2006.211.08:17:51.88#ibcon#about to read 5, iclass 25, count 0 2006.211.08:17:51.88#ibcon#read 5, iclass 25, count 0 2006.211.08:17:51.88#ibcon#about to read 6, iclass 25, count 0 2006.211.08:17:51.88#ibcon#read 6, iclass 25, count 0 2006.211.08:17:51.88#ibcon#end of sib2, iclass 25, count 0 2006.211.08:17:51.88#ibcon#*after write, iclass 25, count 0 2006.211.08:17:51.88#ibcon#*before return 0, iclass 25, count 0 2006.211.08:17:51.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:51.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:17:51.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:17:51.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:17:51.88$vc4f8/vb=6,3 2006.211.08:17:51.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:17:51.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:17:51.88#ibcon#ireg 11 cls_cnt 2 2006.211.08:17:51.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:51.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:51.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:51.94#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:17:51.94#ibcon#first serial, iclass 27, count 2 2006.211.08:17:51.94#ibcon#enter sib2, iclass 27, count 2 2006.211.08:17:51.94#ibcon#flushed, iclass 27, count 2 2006.211.08:17:51.94#ibcon#about to write, iclass 27, count 2 2006.211.08:17:51.94#ibcon#wrote, iclass 27, count 2 2006.211.08:17:51.94#ibcon#about to read 3, iclass 27, count 2 2006.211.08:17:51.96#ibcon#read 3, iclass 27, count 2 2006.211.08:17:51.96#ibcon#about to read 4, iclass 27, count 2 2006.211.08:17:51.96#ibcon#read 4, iclass 27, count 2 2006.211.08:17:51.96#ibcon#about to read 5, iclass 27, count 2 2006.211.08:17:51.96#ibcon#read 5, iclass 27, count 2 2006.211.08:17:51.96#ibcon#about to read 6, iclass 27, count 2 2006.211.08:17:51.96#ibcon#read 6, iclass 27, count 2 2006.211.08:17:51.96#ibcon#end of sib2, iclass 27, count 2 2006.211.08:17:51.96#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:17:51.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:17:51.96#ibcon#[27=AT06-03\r\n] 2006.211.08:17:51.96#ibcon#*before write, iclass 27, count 2 2006.211.08:17:51.96#ibcon#enter sib2, iclass 27, count 2 2006.211.08:17:51.96#ibcon#flushed, iclass 27, count 2 2006.211.08:17:51.96#ibcon#about to write, iclass 27, count 2 2006.211.08:17:51.96#ibcon#wrote, iclass 27, count 2 2006.211.08:17:51.96#ibcon#about to read 3, iclass 27, count 2 2006.211.08:17:51.99#ibcon#read 3, iclass 27, count 2 2006.211.08:17:51.99#ibcon#about to read 4, iclass 27, count 2 2006.211.08:17:51.99#ibcon#read 4, iclass 27, count 2 2006.211.08:17:51.99#ibcon#about to read 5, iclass 27, count 2 2006.211.08:17:51.99#ibcon#read 5, iclass 27, count 2 2006.211.08:17:51.99#ibcon#about to read 6, iclass 27, count 2 2006.211.08:17:51.99#ibcon#read 6, iclass 27, count 2 2006.211.08:17:51.99#ibcon#end of sib2, iclass 27, count 2 2006.211.08:17:51.99#ibcon#*after write, iclass 27, count 2 2006.211.08:17:51.99#ibcon#*before return 0, iclass 27, count 2 2006.211.08:17:51.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:51.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:17:51.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:17:51.99#ibcon#ireg 7 cls_cnt 0 2006.211.08:17:51.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:52.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:52.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:52.11#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:17:52.11#ibcon#first serial, iclass 27, count 0 2006.211.08:17:52.11#ibcon#enter sib2, iclass 27, count 0 2006.211.08:17:52.11#ibcon#flushed, iclass 27, count 0 2006.211.08:17:52.11#ibcon#about to write, iclass 27, count 0 2006.211.08:17:52.11#ibcon#wrote, iclass 27, count 0 2006.211.08:17:52.11#ibcon#about to read 3, iclass 27, count 0 2006.211.08:17:52.13#ibcon#read 3, iclass 27, count 0 2006.211.08:17:52.13#ibcon#about to read 4, iclass 27, count 0 2006.211.08:17:52.13#ibcon#read 4, iclass 27, count 0 2006.211.08:17:52.13#ibcon#about to read 5, iclass 27, count 0 2006.211.08:17:52.13#ibcon#read 5, iclass 27, count 0 2006.211.08:17:52.13#ibcon#about to read 6, iclass 27, count 0 2006.211.08:17:52.13#ibcon#read 6, iclass 27, count 0 2006.211.08:17:52.13#ibcon#end of sib2, iclass 27, count 0 2006.211.08:17:52.13#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:17:52.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:17:52.13#ibcon#[27=USB\r\n] 2006.211.08:17:52.13#ibcon#*before write, iclass 27, count 0 2006.211.08:17:52.13#ibcon#enter sib2, iclass 27, count 0 2006.211.08:17:52.13#ibcon#flushed, iclass 27, count 0 2006.211.08:17:52.13#ibcon#about to write, iclass 27, count 0 2006.211.08:17:52.13#ibcon#wrote, iclass 27, count 0 2006.211.08:17:52.13#ibcon#about to read 3, iclass 27, count 0 2006.211.08:17:52.16#ibcon#read 3, iclass 27, count 0 2006.211.08:17:52.16#ibcon#about to read 4, iclass 27, count 0 2006.211.08:17:52.16#ibcon#read 4, iclass 27, count 0 2006.211.08:17:52.16#ibcon#about to read 5, iclass 27, count 0 2006.211.08:17:52.16#ibcon#read 5, iclass 27, count 0 2006.211.08:17:52.16#ibcon#about to read 6, iclass 27, count 0 2006.211.08:17:52.16#ibcon#read 6, iclass 27, count 0 2006.211.08:17:52.16#ibcon#end of sib2, iclass 27, count 0 2006.211.08:17:52.16#ibcon#*after write, iclass 27, count 0 2006.211.08:17:52.16#ibcon#*before return 0, iclass 27, count 0 2006.211.08:17:52.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:52.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:17:52.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:17:52.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:17:52.16$vc4f8/vabw=wide 2006.211.08:17:52.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:17:52.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:17:52.16#ibcon#ireg 8 cls_cnt 0 2006.211.08:17:52.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:17:52.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:17:52.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:17:52.16#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:17:52.16#ibcon#first serial, iclass 29, count 0 2006.211.08:17:52.16#ibcon#enter sib2, iclass 29, count 0 2006.211.08:17:52.16#ibcon#flushed, iclass 29, count 0 2006.211.08:17:52.16#ibcon#about to write, iclass 29, count 0 2006.211.08:17:52.16#ibcon#wrote, iclass 29, count 0 2006.211.08:17:52.16#ibcon#about to read 3, iclass 29, count 0 2006.211.08:17:52.18#ibcon#read 3, iclass 29, count 0 2006.211.08:17:52.18#ibcon#about to read 4, iclass 29, count 0 2006.211.08:17:52.18#ibcon#read 4, iclass 29, count 0 2006.211.08:17:52.18#ibcon#about to read 5, iclass 29, count 0 2006.211.08:17:52.18#ibcon#read 5, iclass 29, count 0 2006.211.08:17:52.18#ibcon#about to read 6, iclass 29, count 0 2006.211.08:17:52.18#ibcon#read 6, iclass 29, count 0 2006.211.08:17:52.18#ibcon#end of sib2, iclass 29, count 0 2006.211.08:17:52.18#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:17:52.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:17:52.18#ibcon#[25=BW32\r\n] 2006.211.08:17:52.18#ibcon#*before write, iclass 29, count 0 2006.211.08:17:52.18#ibcon#enter sib2, iclass 29, count 0 2006.211.08:17:52.18#ibcon#flushed, iclass 29, count 0 2006.211.08:17:52.18#ibcon#about to write, iclass 29, count 0 2006.211.08:17:52.18#ibcon#wrote, iclass 29, count 0 2006.211.08:17:52.18#ibcon#about to read 3, iclass 29, count 0 2006.211.08:17:52.21#ibcon#read 3, iclass 29, count 0 2006.211.08:17:52.21#ibcon#about to read 4, iclass 29, count 0 2006.211.08:17:52.21#ibcon#read 4, iclass 29, count 0 2006.211.08:17:52.21#ibcon#about to read 5, iclass 29, count 0 2006.211.08:17:52.21#ibcon#read 5, iclass 29, count 0 2006.211.08:17:52.21#ibcon#about to read 6, iclass 29, count 0 2006.211.08:17:52.21#ibcon#read 6, iclass 29, count 0 2006.211.08:17:52.21#ibcon#end of sib2, iclass 29, count 0 2006.211.08:17:52.21#ibcon#*after write, iclass 29, count 0 2006.211.08:17:52.21#ibcon#*before return 0, iclass 29, count 0 2006.211.08:17:52.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:17:52.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:17:52.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:17:52.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:17:52.21$vc4f8/vbbw=wide 2006.211.08:17:52.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.211.08:17:52.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.211.08:17:52.21#ibcon#ireg 8 cls_cnt 0 2006.211.08:17:52.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:17:52.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:17:52.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:17:52.28#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:17:52.28#ibcon#first serial, iclass 31, count 0 2006.211.08:17:52.28#ibcon#enter sib2, iclass 31, count 0 2006.211.08:17:52.28#ibcon#flushed, iclass 31, count 0 2006.211.08:17:52.28#ibcon#about to write, iclass 31, count 0 2006.211.08:17:52.28#ibcon#wrote, iclass 31, count 0 2006.211.08:17:52.28#ibcon#about to read 3, iclass 31, count 0 2006.211.08:17:52.30#ibcon#read 3, iclass 31, count 0 2006.211.08:17:52.30#ibcon#about to read 4, iclass 31, count 0 2006.211.08:17:52.30#ibcon#read 4, iclass 31, count 0 2006.211.08:17:52.30#ibcon#about to read 5, iclass 31, count 0 2006.211.08:17:52.30#ibcon#read 5, iclass 31, count 0 2006.211.08:17:52.30#ibcon#about to read 6, iclass 31, count 0 2006.211.08:17:52.30#ibcon#read 6, iclass 31, count 0 2006.211.08:17:52.30#ibcon#end of sib2, iclass 31, count 0 2006.211.08:17:52.30#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:17:52.30#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:17:52.30#ibcon#[27=BW32\r\n] 2006.211.08:17:52.30#ibcon#*before write, iclass 31, count 0 2006.211.08:17:52.30#ibcon#enter sib2, iclass 31, count 0 2006.211.08:17:52.30#ibcon#flushed, iclass 31, count 0 2006.211.08:17:52.30#ibcon#about to write, iclass 31, count 0 2006.211.08:17:52.30#ibcon#wrote, iclass 31, count 0 2006.211.08:17:52.30#ibcon#about to read 3, iclass 31, count 0 2006.211.08:17:52.33#ibcon#read 3, iclass 31, count 0 2006.211.08:17:52.33#ibcon#about to read 4, iclass 31, count 0 2006.211.08:17:52.33#ibcon#read 4, iclass 31, count 0 2006.211.08:17:52.33#ibcon#about to read 5, iclass 31, count 0 2006.211.08:17:52.33#ibcon#read 5, iclass 31, count 0 2006.211.08:17:52.33#ibcon#about to read 6, iclass 31, count 0 2006.211.08:17:52.33#ibcon#read 6, iclass 31, count 0 2006.211.08:17:52.33#ibcon#end of sib2, iclass 31, count 0 2006.211.08:17:52.33#ibcon#*after write, iclass 31, count 0 2006.211.08:17:52.33#ibcon#*before return 0, iclass 31, count 0 2006.211.08:17:52.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:17:52.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.211.08:17:52.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:17:52.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:17:52.33$4f8m12a/ifd4f 2006.211.08:17:52.33$ifd4f/lo= 2006.211.08:17:52.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:17:52.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:17:52.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:17:52.33$ifd4f/patch= 2006.211.08:17:52.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:17:52.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:17:52.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:17:52.33$4f8m12a/"form=m,16.000,1:2 2006.211.08:17:52.33$4f8m12a/"tpicd 2006.211.08:17:52.33$4f8m12a/echo=off 2006.211.08:17:52.33$4f8m12a/xlog=off 2006.211.08:17:52.33:!2006.211.08:18:50 2006.211.08:18:30.14#trakl#Source acquired 2006.211.08:18:32.14#flagr#flagr/antenna,acquired 2006.211.08:18:50.00:preob 2006.211.08:18:51.14/onsource/TRACKING 2006.211.08:18:51.14:!2006.211.08:19:00 2006.211.08:19:00.00:data_valid=on 2006.211.08:19:00.00:midob 2006.211.08:19:00.14/onsource/TRACKING 2006.211.08:19:00.14/wx/24.37,1010.1,81 2006.211.08:19:00.21/cable/+6.4398E-03 2006.211.08:19:01.30/va/01,08,usb,yes,28,30 2006.211.08:19:01.30/va/02,07,usb,yes,28,30 2006.211.08:19:01.30/va/03,06,usb,yes,30,30 2006.211.08:19:01.30/va/04,07,usb,yes,29,31 2006.211.08:19:01.30/va/05,07,usb,yes,31,33 2006.211.08:19:01.30/va/06,06,usb,yes,30,30 2006.211.08:19:01.30/va/07,06,usb,yes,31,31 2006.211.08:19:01.30/va/08,07,usb,yes,29,29 2006.211.08:19:01.53/valo/01,532.99,yes,locked 2006.211.08:19:01.53/valo/02,572.99,yes,locked 2006.211.08:19:01.53/valo/03,672.99,yes,locked 2006.211.08:19:01.53/valo/04,832.99,yes,locked 2006.211.08:19:01.53/valo/05,652.99,yes,locked 2006.211.08:19:01.53/valo/06,772.99,yes,locked 2006.211.08:19:01.53/valo/07,832.99,yes,locked 2006.211.08:19:01.53/valo/08,852.99,yes,locked 2006.211.08:19:02.62/vb/01,04,usb,yes,28,27 2006.211.08:19:02.62/vb/02,04,usb,yes,30,31 2006.211.08:19:02.62/vb/03,03,usb,yes,33,37 2006.211.08:19:02.62/vb/04,03,usb,yes,34,34 2006.211.08:19:02.62/vb/05,03,usb,yes,32,36 2006.211.08:19:02.62/vb/06,03,usb,yes,33,36 2006.211.08:19:02.62/vb/07,04,usb,yes,29,28 2006.211.08:19:02.62/vb/08,03,usb,yes,33,36 2006.211.08:19:02.85/vblo/01,632.99,yes,locked 2006.211.08:19:02.85/vblo/02,640.99,yes,locked 2006.211.08:19:02.85/vblo/03,656.99,yes,locked 2006.211.08:19:02.85/vblo/04,712.99,yes,locked 2006.211.08:19:02.85/vblo/05,744.99,yes,locked 2006.211.08:19:02.85/vblo/06,752.99,yes,locked 2006.211.08:19:02.85/vblo/07,734.99,yes,locked 2006.211.08:19:02.85/vblo/08,744.99,yes,locked 2006.211.08:19:03.00/vabw/8 2006.211.08:19:03.15/vbbw/8 2006.211.08:19:03.24/xfe/off,on,12.0 2006.211.08:19:03.62/ifatt/23,28,28,28 2006.211.08:19:04.08/fmout-gps/S +4.41E-07 2006.211.08:19:04.12:!2006.211.08:20:10 2006.211.08:20:10.01:data_valid=off 2006.211.08:20:10.01:postob 2006.211.08:20:10.22/cable/+6.4390E-03 2006.211.08:20:10.22/wx/24.33,1010.2,81 2006.211.08:20:11.07/fmout-gps/S +4.41E-07 2006.211.08:20:11.07:scan_name=211-0822,k06211,60 2006.211.08:20:11.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.211.08:20:12.13#flagr#flagr/antenna,new-source 2006.211.08:20:12.13:checkk5 2006.211.08:20:12.47/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:20:12.81/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:20:13.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:20:13.51/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:20:13.84/chk_obsdata//k5ts1/T2110819??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.211.08:20:14.17/chk_obsdata//k5ts2/T2110819??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.211.08:20:14.51/chk_obsdata//k5ts3/T2110819??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.211.08:20:14.84/chk_obsdata//k5ts4/T2110819??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.211.08:20:15.51/k5log//k5ts1_log_newline 2006.211.08:20:16.17/k5log//k5ts2_log_newline 2006.211.08:20:16.82/k5log//k5ts3_log_newline 2006.211.08:20:17.47/k5log//k5ts4_log_newline 2006.211.08:20:17.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:20:17.50:4f8m12a=3 2006.211.08:20:17.50$4f8m12a/echo=on 2006.211.08:20:17.50$4f8m12a/pcalon 2006.211.08:20:17.50$pcalon/"no phase cal control is implemented here 2006.211.08:20:17.50$4f8m12a/"tpicd=stop 2006.211.08:20:17.50$4f8m12a/vc4f8 2006.211.08:20:17.50$vc4f8/valo=1,532.99 2006.211.08:20:17.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:20:17.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:20:17.50#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:17.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:17.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:17.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:17.50#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:20:17.50#ibcon#first serial, iclass 18, count 0 2006.211.08:20:17.50#ibcon#enter sib2, iclass 18, count 0 2006.211.08:20:17.50#ibcon#flushed, iclass 18, count 0 2006.211.08:20:17.50#ibcon#about to write, iclass 18, count 0 2006.211.08:20:17.50#ibcon#wrote, iclass 18, count 0 2006.211.08:20:17.50#ibcon#about to read 3, iclass 18, count 0 2006.211.08:20:17.52#ibcon#read 3, iclass 18, count 0 2006.211.08:20:17.52#ibcon#about to read 4, iclass 18, count 0 2006.211.08:20:17.52#ibcon#read 4, iclass 18, count 0 2006.211.08:20:17.52#ibcon#about to read 5, iclass 18, count 0 2006.211.08:20:17.52#ibcon#read 5, iclass 18, count 0 2006.211.08:20:17.52#ibcon#about to read 6, iclass 18, count 0 2006.211.08:20:17.52#ibcon#read 6, iclass 18, count 0 2006.211.08:20:17.52#ibcon#end of sib2, iclass 18, count 0 2006.211.08:20:17.52#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:20:17.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:20:17.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:20:17.52#ibcon#*before write, iclass 18, count 0 2006.211.08:20:17.52#ibcon#enter sib2, iclass 18, count 0 2006.211.08:20:17.52#ibcon#flushed, iclass 18, count 0 2006.211.08:20:17.52#ibcon#about to write, iclass 18, count 0 2006.211.08:20:17.52#ibcon#wrote, iclass 18, count 0 2006.211.08:20:17.52#ibcon#about to read 3, iclass 18, count 0 2006.211.08:20:17.57#ibcon#read 3, iclass 18, count 0 2006.211.08:20:17.57#ibcon#about to read 4, iclass 18, count 0 2006.211.08:20:17.57#ibcon#read 4, iclass 18, count 0 2006.211.08:20:17.57#ibcon#about to read 5, iclass 18, count 0 2006.211.08:20:17.57#ibcon#read 5, iclass 18, count 0 2006.211.08:20:17.57#ibcon#about to read 6, iclass 18, count 0 2006.211.08:20:17.57#ibcon#read 6, iclass 18, count 0 2006.211.08:20:17.57#ibcon#end of sib2, iclass 18, count 0 2006.211.08:20:17.57#ibcon#*after write, iclass 18, count 0 2006.211.08:20:17.57#ibcon#*before return 0, iclass 18, count 0 2006.211.08:20:17.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:17.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:17.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:20:17.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:20:17.57$vc4f8/va=1,8 2006.211.08:20:17.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:20:17.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:20:17.57#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:17.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:17.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:17.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:17.57#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:20:17.57#ibcon#first serial, iclass 20, count 2 2006.211.08:20:17.57#ibcon#enter sib2, iclass 20, count 2 2006.211.08:20:17.57#ibcon#flushed, iclass 20, count 2 2006.211.08:20:17.57#ibcon#about to write, iclass 20, count 2 2006.211.08:20:17.57#ibcon#wrote, iclass 20, count 2 2006.211.08:20:17.57#ibcon#about to read 3, iclass 20, count 2 2006.211.08:20:17.59#ibcon#read 3, iclass 20, count 2 2006.211.08:20:17.59#ibcon#about to read 4, iclass 20, count 2 2006.211.08:20:17.59#ibcon#read 4, iclass 20, count 2 2006.211.08:20:17.59#ibcon#about to read 5, iclass 20, count 2 2006.211.08:20:17.59#ibcon#read 5, iclass 20, count 2 2006.211.08:20:17.59#ibcon#about to read 6, iclass 20, count 2 2006.211.08:20:17.59#ibcon#read 6, iclass 20, count 2 2006.211.08:20:17.59#ibcon#end of sib2, iclass 20, count 2 2006.211.08:20:17.59#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:20:17.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:20:17.59#ibcon#[25=AT01-08\r\n] 2006.211.08:20:17.59#ibcon#*before write, iclass 20, count 2 2006.211.08:20:17.59#ibcon#enter sib2, iclass 20, count 2 2006.211.08:20:17.59#ibcon#flushed, iclass 20, count 2 2006.211.08:20:17.59#ibcon#about to write, iclass 20, count 2 2006.211.08:20:17.59#ibcon#wrote, iclass 20, count 2 2006.211.08:20:17.59#ibcon#about to read 3, iclass 20, count 2 2006.211.08:20:17.62#ibcon#read 3, iclass 20, count 2 2006.211.08:20:17.62#ibcon#about to read 4, iclass 20, count 2 2006.211.08:20:17.62#ibcon#read 4, iclass 20, count 2 2006.211.08:20:17.62#ibcon#about to read 5, iclass 20, count 2 2006.211.08:20:17.62#ibcon#read 5, iclass 20, count 2 2006.211.08:20:17.62#ibcon#about to read 6, iclass 20, count 2 2006.211.08:20:17.62#ibcon#read 6, iclass 20, count 2 2006.211.08:20:17.62#ibcon#end of sib2, iclass 20, count 2 2006.211.08:20:17.62#ibcon#*after write, iclass 20, count 2 2006.211.08:20:17.62#ibcon#*before return 0, iclass 20, count 2 2006.211.08:20:17.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:17.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:17.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:20:17.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:17.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:17.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:17.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:17.74#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:20:17.74#ibcon#first serial, iclass 20, count 0 2006.211.08:20:17.74#ibcon#enter sib2, iclass 20, count 0 2006.211.08:20:17.74#ibcon#flushed, iclass 20, count 0 2006.211.08:20:17.74#ibcon#about to write, iclass 20, count 0 2006.211.08:20:17.74#ibcon#wrote, iclass 20, count 0 2006.211.08:20:17.74#ibcon#about to read 3, iclass 20, count 0 2006.211.08:20:17.76#ibcon#read 3, iclass 20, count 0 2006.211.08:20:17.76#ibcon#about to read 4, iclass 20, count 0 2006.211.08:20:17.76#ibcon#read 4, iclass 20, count 0 2006.211.08:20:17.76#ibcon#about to read 5, iclass 20, count 0 2006.211.08:20:17.76#ibcon#read 5, iclass 20, count 0 2006.211.08:20:17.76#ibcon#about to read 6, iclass 20, count 0 2006.211.08:20:17.76#ibcon#read 6, iclass 20, count 0 2006.211.08:20:17.76#ibcon#end of sib2, iclass 20, count 0 2006.211.08:20:17.76#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:20:17.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:20:17.76#ibcon#[25=USB\r\n] 2006.211.08:20:17.76#ibcon#*before write, iclass 20, count 0 2006.211.08:20:17.76#ibcon#enter sib2, iclass 20, count 0 2006.211.08:20:17.76#ibcon#flushed, iclass 20, count 0 2006.211.08:20:17.76#ibcon#about to write, iclass 20, count 0 2006.211.08:20:17.76#ibcon#wrote, iclass 20, count 0 2006.211.08:20:17.76#ibcon#about to read 3, iclass 20, count 0 2006.211.08:20:17.79#ibcon#read 3, iclass 20, count 0 2006.211.08:20:17.79#ibcon#about to read 4, iclass 20, count 0 2006.211.08:20:17.79#ibcon#read 4, iclass 20, count 0 2006.211.08:20:17.79#ibcon#about to read 5, iclass 20, count 0 2006.211.08:20:17.79#ibcon#read 5, iclass 20, count 0 2006.211.08:20:17.79#ibcon#about to read 6, iclass 20, count 0 2006.211.08:20:17.79#ibcon#read 6, iclass 20, count 0 2006.211.08:20:17.79#ibcon#end of sib2, iclass 20, count 0 2006.211.08:20:17.79#ibcon#*after write, iclass 20, count 0 2006.211.08:20:17.79#ibcon#*before return 0, iclass 20, count 0 2006.211.08:20:17.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:17.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:17.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:20:17.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:20:17.79$vc4f8/valo=2,572.99 2006.211.08:20:17.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:20:17.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:20:17.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:17.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:17.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:17.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:17.79#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:20:17.79#ibcon#first serial, iclass 22, count 0 2006.211.08:20:17.79#ibcon#enter sib2, iclass 22, count 0 2006.211.08:20:17.79#ibcon#flushed, iclass 22, count 0 2006.211.08:20:17.79#ibcon#about to write, iclass 22, count 0 2006.211.08:20:17.79#ibcon#wrote, iclass 22, count 0 2006.211.08:20:17.79#ibcon#about to read 3, iclass 22, count 0 2006.211.08:20:17.81#ibcon#read 3, iclass 22, count 0 2006.211.08:20:17.81#ibcon#about to read 4, iclass 22, count 0 2006.211.08:20:17.81#ibcon#read 4, iclass 22, count 0 2006.211.08:20:17.81#ibcon#about to read 5, iclass 22, count 0 2006.211.08:20:17.81#ibcon#read 5, iclass 22, count 0 2006.211.08:20:17.81#ibcon#about to read 6, iclass 22, count 0 2006.211.08:20:17.81#ibcon#read 6, iclass 22, count 0 2006.211.08:20:17.81#ibcon#end of sib2, iclass 22, count 0 2006.211.08:20:17.81#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:20:17.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:20:17.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:20:17.81#ibcon#*before write, iclass 22, count 0 2006.211.08:20:17.81#ibcon#enter sib2, iclass 22, count 0 2006.211.08:20:17.81#ibcon#flushed, iclass 22, count 0 2006.211.08:20:17.81#ibcon#about to write, iclass 22, count 0 2006.211.08:20:17.81#ibcon#wrote, iclass 22, count 0 2006.211.08:20:17.81#ibcon#about to read 3, iclass 22, count 0 2006.211.08:20:17.85#ibcon#read 3, iclass 22, count 0 2006.211.08:20:17.85#ibcon#about to read 4, iclass 22, count 0 2006.211.08:20:17.85#ibcon#read 4, iclass 22, count 0 2006.211.08:20:17.85#ibcon#about to read 5, iclass 22, count 0 2006.211.08:20:17.85#ibcon#read 5, iclass 22, count 0 2006.211.08:20:17.85#ibcon#about to read 6, iclass 22, count 0 2006.211.08:20:17.85#ibcon#read 6, iclass 22, count 0 2006.211.08:20:17.85#ibcon#end of sib2, iclass 22, count 0 2006.211.08:20:17.85#ibcon#*after write, iclass 22, count 0 2006.211.08:20:17.85#ibcon#*before return 0, iclass 22, count 0 2006.211.08:20:17.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:17.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:17.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:20:17.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:20:17.85$vc4f8/va=2,7 2006.211.08:20:17.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:20:17.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:20:17.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:17.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:17.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:17.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:17.91#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:20:17.91#ibcon#first serial, iclass 24, count 2 2006.211.08:20:17.91#ibcon#enter sib2, iclass 24, count 2 2006.211.08:20:17.91#ibcon#flushed, iclass 24, count 2 2006.211.08:20:17.91#ibcon#about to write, iclass 24, count 2 2006.211.08:20:17.91#ibcon#wrote, iclass 24, count 2 2006.211.08:20:17.91#ibcon#about to read 3, iclass 24, count 2 2006.211.08:20:17.93#ibcon#read 3, iclass 24, count 2 2006.211.08:20:17.93#ibcon#about to read 4, iclass 24, count 2 2006.211.08:20:17.93#ibcon#read 4, iclass 24, count 2 2006.211.08:20:17.93#ibcon#about to read 5, iclass 24, count 2 2006.211.08:20:17.93#ibcon#read 5, iclass 24, count 2 2006.211.08:20:17.93#ibcon#about to read 6, iclass 24, count 2 2006.211.08:20:17.93#ibcon#read 6, iclass 24, count 2 2006.211.08:20:17.93#ibcon#end of sib2, iclass 24, count 2 2006.211.08:20:17.93#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:20:17.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:20:17.93#ibcon#[25=AT02-07\r\n] 2006.211.08:20:17.93#ibcon#*before write, iclass 24, count 2 2006.211.08:20:17.93#ibcon#enter sib2, iclass 24, count 2 2006.211.08:20:17.93#ibcon#flushed, iclass 24, count 2 2006.211.08:20:17.93#ibcon#about to write, iclass 24, count 2 2006.211.08:20:17.93#ibcon#wrote, iclass 24, count 2 2006.211.08:20:17.93#ibcon#about to read 3, iclass 24, count 2 2006.211.08:20:17.96#ibcon#read 3, iclass 24, count 2 2006.211.08:20:17.96#ibcon#about to read 4, iclass 24, count 2 2006.211.08:20:17.96#ibcon#read 4, iclass 24, count 2 2006.211.08:20:17.96#ibcon#about to read 5, iclass 24, count 2 2006.211.08:20:17.96#ibcon#read 5, iclass 24, count 2 2006.211.08:20:17.96#ibcon#about to read 6, iclass 24, count 2 2006.211.08:20:17.96#ibcon#read 6, iclass 24, count 2 2006.211.08:20:17.96#ibcon#end of sib2, iclass 24, count 2 2006.211.08:20:17.96#ibcon#*after write, iclass 24, count 2 2006.211.08:20:17.96#ibcon#*before return 0, iclass 24, count 2 2006.211.08:20:17.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:17.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:17.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:20:17.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:17.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:18.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:18.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:18.08#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:20:18.08#ibcon#first serial, iclass 24, count 0 2006.211.08:20:18.08#ibcon#enter sib2, iclass 24, count 0 2006.211.08:20:18.08#ibcon#flushed, iclass 24, count 0 2006.211.08:20:18.08#ibcon#about to write, iclass 24, count 0 2006.211.08:20:18.08#ibcon#wrote, iclass 24, count 0 2006.211.08:20:18.08#ibcon#about to read 3, iclass 24, count 0 2006.211.08:20:18.10#ibcon#read 3, iclass 24, count 0 2006.211.08:20:18.10#ibcon#about to read 4, iclass 24, count 0 2006.211.08:20:18.10#ibcon#read 4, iclass 24, count 0 2006.211.08:20:18.10#ibcon#about to read 5, iclass 24, count 0 2006.211.08:20:18.10#ibcon#read 5, iclass 24, count 0 2006.211.08:20:18.10#ibcon#about to read 6, iclass 24, count 0 2006.211.08:20:18.10#ibcon#read 6, iclass 24, count 0 2006.211.08:20:18.10#ibcon#end of sib2, iclass 24, count 0 2006.211.08:20:18.10#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:20:18.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:20:18.10#ibcon#[25=USB\r\n] 2006.211.08:20:18.10#ibcon#*before write, iclass 24, count 0 2006.211.08:20:18.10#ibcon#enter sib2, iclass 24, count 0 2006.211.08:20:18.10#ibcon#flushed, iclass 24, count 0 2006.211.08:20:18.10#ibcon#about to write, iclass 24, count 0 2006.211.08:20:18.10#ibcon#wrote, iclass 24, count 0 2006.211.08:20:18.10#ibcon#about to read 3, iclass 24, count 0 2006.211.08:20:18.13#ibcon#read 3, iclass 24, count 0 2006.211.08:20:18.13#ibcon#about to read 4, iclass 24, count 0 2006.211.08:20:18.13#ibcon#read 4, iclass 24, count 0 2006.211.08:20:18.13#ibcon#about to read 5, iclass 24, count 0 2006.211.08:20:18.13#ibcon#read 5, iclass 24, count 0 2006.211.08:20:18.13#ibcon#about to read 6, iclass 24, count 0 2006.211.08:20:18.13#ibcon#read 6, iclass 24, count 0 2006.211.08:20:18.13#ibcon#end of sib2, iclass 24, count 0 2006.211.08:20:18.13#ibcon#*after write, iclass 24, count 0 2006.211.08:20:18.13#ibcon#*before return 0, iclass 24, count 0 2006.211.08:20:18.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:18.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:18.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:20:18.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:20:18.13$vc4f8/valo=3,672.99 2006.211.08:20:18.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:20:18.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:20:18.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:18.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:18.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:18.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:18.13#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:20:18.13#ibcon#first serial, iclass 26, count 0 2006.211.08:20:18.13#ibcon#enter sib2, iclass 26, count 0 2006.211.08:20:18.13#ibcon#flushed, iclass 26, count 0 2006.211.08:20:18.13#ibcon#about to write, iclass 26, count 0 2006.211.08:20:18.13#ibcon#wrote, iclass 26, count 0 2006.211.08:20:18.13#ibcon#about to read 3, iclass 26, count 0 2006.211.08:20:18.15#ibcon#read 3, iclass 26, count 0 2006.211.08:20:18.15#ibcon#about to read 4, iclass 26, count 0 2006.211.08:20:18.15#ibcon#read 4, iclass 26, count 0 2006.211.08:20:18.15#ibcon#about to read 5, iclass 26, count 0 2006.211.08:20:18.15#ibcon#read 5, iclass 26, count 0 2006.211.08:20:18.15#ibcon#about to read 6, iclass 26, count 0 2006.211.08:20:18.15#ibcon#read 6, iclass 26, count 0 2006.211.08:20:18.15#ibcon#end of sib2, iclass 26, count 0 2006.211.08:20:18.15#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:20:18.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:20:18.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:20:18.15#ibcon#*before write, iclass 26, count 0 2006.211.08:20:18.15#ibcon#enter sib2, iclass 26, count 0 2006.211.08:20:18.15#ibcon#flushed, iclass 26, count 0 2006.211.08:20:18.15#ibcon#about to write, iclass 26, count 0 2006.211.08:20:18.15#ibcon#wrote, iclass 26, count 0 2006.211.08:20:18.15#ibcon#about to read 3, iclass 26, count 0 2006.211.08:20:18.19#ibcon#read 3, iclass 26, count 0 2006.211.08:20:18.19#ibcon#about to read 4, iclass 26, count 0 2006.211.08:20:18.19#ibcon#read 4, iclass 26, count 0 2006.211.08:20:18.19#ibcon#about to read 5, iclass 26, count 0 2006.211.08:20:18.19#ibcon#read 5, iclass 26, count 0 2006.211.08:20:18.19#ibcon#about to read 6, iclass 26, count 0 2006.211.08:20:18.19#ibcon#read 6, iclass 26, count 0 2006.211.08:20:18.19#ibcon#end of sib2, iclass 26, count 0 2006.211.08:20:18.19#ibcon#*after write, iclass 26, count 0 2006.211.08:20:18.19#ibcon#*before return 0, iclass 26, count 0 2006.211.08:20:18.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:18.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:18.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:20:18.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:20:18.19$vc4f8/va=3,6 2006.211.08:20:18.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:20:18.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:20:18.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:18.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:18.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:18.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:18.25#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:20:18.25#ibcon#first serial, iclass 28, count 2 2006.211.08:20:18.25#ibcon#enter sib2, iclass 28, count 2 2006.211.08:20:18.25#ibcon#flushed, iclass 28, count 2 2006.211.08:20:18.25#ibcon#about to write, iclass 28, count 2 2006.211.08:20:18.25#ibcon#wrote, iclass 28, count 2 2006.211.08:20:18.25#ibcon#about to read 3, iclass 28, count 2 2006.211.08:20:18.27#ibcon#read 3, iclass 28, count 2 2006.211.08:20:18.27#ibcon#about to read 4, iclass 28, count 2 2006.211.08:20:18.27#ibcon#read 4, iclass 28, count 2 2006.211.08:20:18.27#ibcon#about to read 5, iclass 28, count 2 2006.211.08:20:18.27#ibcon#read 5, iclass 28, count 2 2006.211.08:20:18.27#ibcon#about to read 6, iclass 28, count 2 2006.211.08:20:18.27#ibcon#read 6, iclass 28, count 2 2006.211.08:20:18.27#ibcon#end of sib2, iclass 28, count 2 2006.211.08:20:18.27#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:20:18.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:20:18.27#ibcon#[25=AT03-06\r\n] 2006.211.08:20:18.27#ibcon#*before write, iclass 28, count 2 2006.211.08:20:18.27#ibcon#enter sib2, iclass 28, count 2 2006.211.08:20:18.27#ibcon#flushed, iclass 28, count 2 2006.211.08:20:18.27#ibcon#about to write, iclass 28, count 2 2006.211.08:20:18.27#ibcon#wrote, iclass 28, count 2 2006.211.08:20:18.27#ibcon#about to read 3, iclass 28, count 2 2006.211.08:20:18.30#ibcon#read 3, iclass 28, count 2 2006.211.08:20:18.30#ibcon#about to read 4, iclass 28, count 2 2006.211.08:20:18.30#ibcon#read 4, iclass 28, count 2 2006.211.08:20:18.30#ibcon#about to read 5, iclass 28, count 2 2006.211.08:20:18.30#ibcon#read 5, iclass 28, count 2 2006.211.08:20:18.30#ibcon#about to read 6, iclass 28, count 2 2006.211.08:20:18.30#ibcon#read 6, iclass 28, count 2 2006.211.08:20:18.30#ibcon#end of sib2, iclass 28, count 2 2006.211.08:20:18.30#ibcon#*after write, iclass 28, count 2 2006.211.08:20:18.30#ibcon#*before return 0, iclass 28, count 2 2006.211.08:20:18.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:18.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:18.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:20:18.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:18.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:18.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:18.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:18.42#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:20:18.42#ibcon#first serial, iclass 28, count 0 2006.211.08:20:18.42#ibcon#enter sib2, iclass 28, count 0 2006.211.08:20:18.42#ibcon#flushed, iclass 28, count 0 2006.211.08:20:18.42#ibcon#about to write, iclass 28, count 0 2006.211.08:20:18.42#ibcon#wrote, iclass 28, count 0 2006.211.08:20:18.42#ibcon#about to read 3, iclass 28, count 0 2006.211.08:20:18.44#ibcon#read 3, iclass 28, count 0 2006.211.08:20:18.44#ibcon#about to read 4, iclass 28, count 0 2006.211.08:20:18.44#ibcon#read 4, iclass 28, count 0 2006.211.08:20:18.44#ibcon#about to read 5, iclass 28, count 0 2006.211.08:20:18.44#ibcon#read 5, iclass 28, count 0 2006.211.08:20:18.44#ibcon#about to read 6, iclass 28, count 0 2006.211.08:20:18.44#ibcon#read 6, iclass 28, count 0 2006.211.08:20:18.44#ibcon#end of sib2, iclass 28, count 0 2006.211.08:20:18.44#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:20:18.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:20:18.44#ibcon#[25=USB\r\n] 2006.211.08:20:18.44#ibcon#*before write, iclass 28, count 0 2006.211.08:20:18.44#ibcon#enter sib2, iclass 28, count 0 2006.211.08:20:18.44#ibcon#flushed, iclass 28, count 0 2006.211.08:20:18.44#ibcon#about to write, iclass 28, count 0 2006.211.08:20:18.44#ibcon#wrote, iclass 28, count 0 2006.211.08:20:18.44#ibcon#about to read 3, iclass 28, count 0 2006.211.08:20:18.47#ibcon#read 3, iclass 28, count 0 2006.211.08:20:18.47#ibcon#about to read 4, iclass 28, count 0 2006.211.08:20:18.47#ibcon#read 4, iclass 28, count 0 2006.211.08:20:18.47#ibcon#about to read 5, iclass 28, count 0 2006.211.08:20:18.47#ibcon#read 5, iclass 28, count 0 2006.211.08:20:18.47#ibcon#about to read 6, iclass 28, count 0 2006.211.08:20:18.47#ibcon#read 6, iclass 28, count 0 2006.211.08:20:18.47#ibcon#end of sib2, iclass 28, count 0 2006.211.08:20:18.47#ibcon#*after write, iclass 28, count 0 2006.211.08:20:18.47#ibcon#*before return 0, iclass 28, count 0 2006.211.08:20:18.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:18.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:18.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:20:18.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:20:18.47$vc4f8/valo=4,832.99 2006.211.08:20:18.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:20:18.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:20:18.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:18.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:18.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:18.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:18.47#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:20:18.47#ibcon#first serial, iclass 30, count 0 2006.211.08:20:18.47#ibcon#enter sib2, iclass 30, count 0 2006.211.08:20:18.47#ibcon#flushed, iclass 30, count 0 2006.211.08:20:18.47#ibcon#about to write, iclass 30, count 0 2006.211.08:20:18.47#ibcon#wrote, iclass 30, count 0 2006.211.08:20:18.47#ibcon#about to read 3, iclass 30, count 0 2006.211.08:20:18.49#ibcon#read 3, iclass 30, count 0 2006.211.08:20:18.49#ibcon#about to read 4, iclass 30, count 0 2006.211.08:20:18.49#ibcon#read 4, iclass 30, count 0 2006.211.08:20:18.49#ibcon#about to read 5, iclass 30, count 0 2006.211.08:20:18.49#ibcon#read 5, iclass 30, count 0 2006.211.08:20:18.49#ibcon#about to read 6, iclass 30, count 0 2006.211.08:20:18.49#ibcon#read 6, iclass 30, count 0 2006.211.08:20:18.49#ibcon#end of sib2, iclass 30, count 0 2006.211.08:20:18.49#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:20:18.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:20:18.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:20:18.49#ibcon#*before write, iclass 30, count 0 2006.211.08:20:18.49#ibcon#enter sib2, iclass 30, count 0 2006.211.08:20:18.49#ibcon#flushed, iclass 30, count 0 2006.211.08:20:18.49#ibcon#about to write, iclass 30, count 0 2006.211.08:20:18.49#ibcon#wrote, iclass 30, count 0 2006.211.08:20:18.49#ibcon#about to read 3, iclass 30, count 0 2006.211.08:20:18.53#ibcon#read 3, iclass 30, count 0 2006.211.08:20:18.53#ibcon#about to read 4, iclass 30, count 0 2006.211.08:20:18.53#ibcon#read 4, iclass 30, count 0 2006.211.08:20:18.53#ibcon#about to read 5, iclass 30, count 0 2006.211.08:20:18.53#ibcon#read 5, iclass 30, count 0 2006.211.08:20:18.53#ibcon#about to read 6, iclass 30, count 0 2006.211.08:20:18.53#ibcon#read 6, iclass 30, count 0 2006.211.08:20:18.53#ibcon#end of sib2, iclass 30, count 0 2006.211.08:20:18.53#ibcon#*after write, iclass 30, count 0 2006.211.08:20:18.53#ibcon#*before return 0, iclass 30, count 0 2006.211.08:20:18.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:18.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:18.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:20:18.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:20:18.53$vc4f8/va=4,7 2006.211.08:20:18.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:20:18.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:20:18.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:18.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:18.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:18.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:18.59#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:20:18.59#ibcon#first serial, iclass 32, count 2 2006.211.08:20:18.59#ibcon#enter sib2, iclass 32, count 2 2006.211.08:20:18.59#ibcon#flushed, iclass 32, count 2 2006.211.08:20:18.59#ibcon#about to write, iclass 32, count 2 2006.211.08:20:18.59#ibcon#wrote, iclass 32, count 2 2006.211.08:20:18.59#ibcon#about to read 3, iclass 32, count 2 2006.211.08:20:18.61#ibcon#read 3, iclass 32, count 2 2006.211.08:20:18.61#ibcon#about to read 4, iclass 32, count 2 2006.211.08:20:18.61#ibcon#read 4, iclass 32, count 2 2006.211.08:20:18.61#ibcon#about to read 5, iclass 32, count 2 2006.211.08:20:18.61#ibcon#read 5, iclass 32, count 2 2006.211.08:20:18.61#ibcon#about to read 6, iclass 32, count 2 2006.211.08:20:18.61#ibcon#read 6, iclass 32, count 2 2006.211.08:20:18.61#ibcon#end of sib2, iclass 32, count 2 2006.211.08:20:18.61#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:20:18.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:20:18.61#ibcon#[25=AT04-07\r\n] 2006.211.08:20:18.61#ibcon#*before write, iclass 32, count 2 2006.211.08:20:18.61#ibcon#enter sib2, iclass 32, count 2 2006.211.08:20:18.61#ibcon#flushed, iclass 32, count 2 2006.211.08:20:18.61#ibcon#about to write, iclass 32, count 2 2006.211.08:20:18.61#ibcon#wrote, iclass 32, count 2 2006.211.08:20:18.61#ibcon#about to read 3, iclass 32, count 2 2006.211.08:20:18.64#ibcon#read 3, iclass 32, count 2 2006.211.08:20:18.64#ibcon#about to read 4, iclass 32, count 2 2006.211.08:20:18.64#ibcon#read 4, iclass 32, count 2 2006.211.08:20:18.64#ibcon#about to read 5, iclass 32, count 2 2006.211.08:20:18.64#ibcon#read 5, iclass 32, count 2 2006.211.08:20:18.64#ibcon#about to read 6, iclass 32, count 2 2006.211.08:20:18.64#ibcon#read 6, iclass 32, count 2 2006.211.08:20:18.64#ibcon#end of sib2, iclass 32, count 2 2006.211.08:20:18.64#ibcon#*after write, iclass 32, count 2 2006.211.08:20:18.64#ibcon#*before return 0, iclass 32, count 2 2006.211.08:20:18.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:18.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:18.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:20:18.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:18.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:18.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:18.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:18.76#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:20:18.76#ibcon#first serial, iclass 32, count 0 2006.211.08:20:18.76#ibcon#enter sib2, iclass 32, count 0 2006.211.08:20:18.76#ibcon#flushed, iclass 32, count 0 2006.211.08:20:18.76#ibcon#about to write, iclass 32, count 0 2006.211.08:20:18.76#ibcon#wrote, iclass 32, count 0 2006.211.08:20:18.76#ibcon#about to read 3, iclass 32, count 0 2006.211.08:20:18.78#ibcon#read 3, iclass 32, count 0 2006.211.08:20:18.78#ibcon#about to read 4, iclass 32, count 0 2006.211.08:20:18.78#ibcon#read 4, iclass 32, count 0 2006.211.08:20:18.78#ibcon#about to read 5, iclass 32, count 0 2006.211.08:20:18.78#ibcon#read 5, iclass 32, count 0 2006.211.08:20:18.78#ibcon#about to read 6, iclass 32, count 0 2006.211.08:20:18.78#ibcon#read 6, iclass 32, count 0 2006.211.08:20:18.78#ibcon#end of sib2, iclass 32, count 0 2006.211.08:20:18.78#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:20:18.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:20:18.78#ibcon#[25=USB\r\n] 2006.211.08:20:18.78#ibcon#*before write, iclass 32, count 0 2006.211.08:20:18.78#ibcon#enter sib2, iclass 32, count 0 2006.211.08:20:18.78#ibcon#flushed, iclass 32, count 0 2006.211.08:20:18.78#ibcon#about to write, iclass 32, count 0 2006.211.08:20:18.78#ibcon#wrote, iclass 32, count 0 2006.211.08:20:18.78#ibcon#about to read 3, iclass 32, count 0 2006.211.08:20:18.81#ibcon#read 3, iclass 32, count 0 2006.211.08:20:18.81#ibcon#about to read 4, iclass 32, count 0 2006.211.08:20:18.81#ibcon#read 4, iclass 32, count 0 2006.211.08:20:18.81#ibcon#about to read 5, iclass 32, count 0 2006.211.08:20:18.81#ibcon#read 5, iclass 32, count 0 2006.211.08:20:18.81#ibcon#about to read 6, iclass 32, count 0 2006.211.08:20:18.81#ibcon#read 6, iclass 32, count 0 2006.211.08:20:18.81#ibcon#end of sib2, iclass 32, count 0 2006.211.08:20:18.81#ibcon#*after write, iclass 32, count 0 2006.211.08:20:18.81#ibcon#*before return 0, iclass 32, count 0 2006.211.08:20:18.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:18.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:18.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:20:18.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:20:18.81$vc4f8/valo=5,652.99 2006.211.08:20:18.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:20:18.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:20:18.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:18.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:18.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:18.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:18.81#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:20:18.81#ibcon#first serial, iclass 34, count 0 2006.211.08:20:18.81#ibcon#enter sib2, iclass 34, count 0 2006.211.08:20:18.81#ibcon#flushed, iclass 34, count 0 2006.211.08:20:18.81#ibcon#about to write, iclass 34, count 0 2006.211.08:20:18.81#ibcon#wrote, iclass 34, count 0 2006.211.08:20:18.81#ibcon#about to read 3, iclass 34, count 0 2006.211.08:20:18.83#ibcon#read 3, iclass 34, count 0 2006.211.08:20:18.83#ibcon#about to read 4, iclass 34, count 0 2006.211.08:20:18.83#ibcon#read 4, iclass 34, count 0 2006.211.08:20:18.83#ibcon#about to read 5, iclass 34, count 0 2006.211.08:20:18.83#ibcon#read 5, iclass 34, count 0 2006.211.08:20:18.83#ibcon#about to read 6, iclass 34, count 0 2006.211.08:20:18.83#ibcon#read 6, iclass 34, count 0 2006.211.08:20:18.83#ibcon#end of sib2, iclass 34, count 0 2006.211.08:20:18.83#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:20:18.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:20:18.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:20:18.83#ibcon#*before write, iclass 34, count 0 2006.211.08:20:18.83#ibcon#enter sib2, iclass 34, count 0 2006.211.08:20:18.83#ibcon#flushed, iclass 34, count 0 2006.211.08:20:18.83#ibcon#about to write, iclass 34, count 0 2006.211.08:20:18.83#ibcon#wrote, iclass 34, count 0 2006.211.08:20:18.83#ibcon#about to read 3, iclass 34, count 0 2006.211.08:20:18.87#ibcon#read 3, iclass 34, count 0 2006.211.08:20:18.87#ibcon#about to read 4, iclass 34, count 0 2006.211.08:20:18.87#ibcon#read 4, iclass 34, count 0 2006.211.08:20:18.87#ibcon#about to read 5, iclass 34, count 0 2006.211.08:20:18.87#ibcon#read 5, iclass 34, count 0 2006.211.08:20:18.87#ibcon#about to read 6, iclass 34, count 0 2006.211.08:20:18.87#ibcon#read 6, iclass 34, count 0 2006.211.08:20:18.87#ibcon#end of sib2, iclass 34, count 0 2006.211.08:20:18.87#ibcon#*after write, iclass 34, count 0 2006.211.08:20:18.87#ibcon#*before return 0, iclass 34, count 0 2006.211.08:20:18.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:18.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:18.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:20:18.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:20:18.87$vc4f8/va=5,7 2006.211.08:20:18.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:20:18.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:20:18.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:18.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:18.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:18.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:18.93#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:20:18.93#ibcon#first serial, iclass 36, count 2 2006.211.08:20:18.93#ibcon#enter sib2, iclass 36, count 2 2006.211.08:20:18.93#ibcon#flushed, iclass 36, count 2 2006.211.08:20:18.93#ibcon#about to write, iclass 36, count 2 2006.211.08:20:18.93#ibcon#wrote, iclass 36, count 2 2006.211.08:20:18.93#ibcon#about to read 3, iclass 36, count 2 2006.211.08:20:18.95#ibcon#read 3, iclass 36, count 2 2006.211.08:20:18.95#ibcon#about to read 4, iclass 36, count 2 2006.211.08:20:18.95#ibcon#read 4, iclass 36, count 2 2006.211.08:20:18.95#ibcon#about to read 5, iclass 36, count 2 2006.211.08:20:18.95#ibcon#read 5, iclass 36, count 2 2006.211.08:20:18.95#ibcon#about to read 6, iclass 36, count 2 2006.211.08:20:18.95#ibcon#read 6, iclass 36, count 2 2006.211.08:20:18.95#ibcon#end of sib2, iclass 36, count 2 2006.211.08:20:18.95#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:20:18.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:20:18.95#ibcon#[25=AT05-07\r\n] 2006.211.08:20:18.95#ibcon#*before write, iclass 36, count 2 2006.211.08:20:18.95#ibcon#enter sib2, iclass 36, count 2 2006.211.08:20:18.95#ibcon#flushed, iclass 36, count 2 2006.211.08:20:18.95#ibcon#about to write, iclass 36, count 2 2006.211.08:20:18.95#ibcon#wrote, iclass 36, count 2 2006.211.08:20:18.95#ibcon#about to read 3, iclass 36, count 2 2006.211.08:20:18.98#ibcon#read 3, iclass 36, count 2 2006.211.08:20:18.98#ibcon#about to read 4, iclass 36, count 2 2006.211.08:20:18.98#ibcon#read 4, iclass 36, count 2 2006.211.08:20:18.98#ibcon#about to read 5, iclass 36, count 2 2006.211.08:20:18.98#ibcon#read 5, iclass 36, count 2 2006.211.08:20:18.98#ibcon#about to read 6, iclass 36, count 2 2006.211.08:20:18.98#ibcon#read 6, iclass 36, count 2 2006.211.08:20:18.98#ibcon#end of sib2, iclass 36, count 2 2006.211.08:20:18.98#ibcon#*after write, iclass 36, count 2 2006.211.08:20:18.98#ibcon#*before return 0, iclass 36, count 2 2006.211.08:20:18.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:18.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:18.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:20:18.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:18.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:19.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:19.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:19.10#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:20:19.10#ibcon#first serial, iclass 36, count 0 2006.211.08:20:19.10#ibcon#enter sib2, iclass 36, count 0 2006.211.08:20:19.10#ibcon#flushed, iclass 36, count 0 2006.211.08:20:19.10#ibcon#about to write, iclass 36, count 0 2006.211.08:20:19.10#ibcon#wrote, iclass 36, count 0 2006.211.08:20:19.10#ibcon#about to read 3, iclass 36, count 0 2006.211.08:20:19.12#ibcon#read 3, iclass 36, count 0 2006.211.08:20:19.12#ibcon#about to read 4, iclass 36, count 0 2006.211.08:20:19.12#ibcon#read 4, iclass 36, count 0 2006.211.08:20:19.12#ibcon#about to read 5, iclass 36, count 0 2006.211.08:20:19.12#ibcon#read 5, iclass 36, count 0 2006.211.08:20:19.12#ibcon#about to read 6, iclass 36, count 0 2006.211.08:20:19.12#ibcon#read 6, iclass 36, count 0 2006.211.08:20:19.12#ibcon#end of sib2, iclass 36, count 0 2006.211.08:20:19.12#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:20:19.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:20:19.12#ibcon#[25=USB\r\n] 2006.211.08:20:19.12#ibcon#*before write, iclass 36, count 0 2006.211.08:20:19.12#ibcon#enter sib2, iclass 36, count 0 2006.211.08:20:19.12#ibcon#flushed, iclass 36, count 0 2006.211.08:20:19.12#ibcon#about to write, iclass 36, count 0 2006.211.08:20:19.12#ibcon#wrote, iclass 36, count 0 2006.211.08:20:19.12#ibcon#about to read 3, iclass 36, count 0 2006.211.08:20:19.15#ibcon#read 3, iclass 36, count 0 2006.211.08:20:19.15#ibcon#about to read 4, iclass 36, count 0 2006.211.08:20:19.15#ibcon#read 4, iclass 36, count 0 2006.211.08:20:19.15#ibcon#about to read 5, iclass 36, count 0 2006.211.08:20:19.15#ibcon#read 5, iclass 36, count 0 2006.211.08:20:19.15#ibcon#about to read 6, iclass 36, count 0 2006.211.08:20:19.15#ibcon#read 6, iclass 36, count 0 2006.211.08:20:19.15#ibcon#end of sib2, iclass 36, count 0 2006.211.08:20:19.15#ibcon#*after write, iclass 36, count 0 2006.211.08:20:19.15#ibcon#*before return 0, iclass 36, count 0 2006.211.08:20:19.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:19.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:19.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:20:19.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:20:19.15$vc4f8/valo=6,772.99 2006.211.08:20:19.15#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:20:19.15#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:20:19.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:19.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:20:19.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:20:19.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:20:19.15#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:20:19.15#ibcon#first serial, iclass 38, count 0 2006.211.08:20:19.15#ibcon#enter sib2, iclass 38, count 0 2006.211.08:20:19.15#ibcon#flushed, iclass 38, count 0 2006.211.08:20:19.15#ibcon#about to write, iclass 38, count 0 2006.211.08:20:19.15#ibcon#wrote, iclass 38, count 0 2006.211.08:20:19.15#ibcon#about to read 3, iclass 38, count 0 2006.211.08:20:19.17#ibcon#read 3, iclass 38, count 0 2006.211.08:20:19.17#ibcon#about to read 4, iclass 38, count 0 2006.211.08:20:19.17#ibcon#read 4, iclass 38, count 0 2006.211.08:20:19.17#ibcon#about to read 5, iclass 38, count 0 2006.211.08:20:19.17#ibcon#read 5, iclass 38, count 0 2006.211.08:20:19.17#ibcon#about to read 6, iclass 38, count 0 2006.211.08:20:19.17#ibcon#read 6, iclass 38, count 0 2006.211.08:20:19.17#ibcon#end of sib2, iclass 38, count 0 2006.211.08:20:19.17#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:20:19.17#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:20:19.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:20:19.17#ibcon#*before write, iclass 38, count 0 2006.211.08:20:19.17#ibcon#enter sib2, iclass 38, count 0 2006.211.08:20:19.17#ibcon#flushed, iclass 38, count 0 2006.211.08:20:19.17#ibcon#about to write, iclass 38, count 0 2006.211.08:20:19.17#ibcon#wrote, iclass 38, count 0 2006.211.08:20:19.17#ibcon#about to read 3, iclass 38, count 0 2006.211.08:20:19.21#ibcon#read 3, iclass 38, count 0 2006.211.08:20:19.21#ibcon#about to read 4, iclass 38, count 0 2006.211.08:20:19.21#ibcon#read 4, iclass 38, count 0 2006.211.08:20:19.21#ibcon#about to read 5, iclass 38, count 0 2006.211.08:20:19.21#ibcon#read 5, iclass 38, count 0 2006.211.08:20:19.21#ibcon#about to read 6, iclass 38, count 0 2006.211.08:20:19.21#ibcon#read 6, iclass 38, count 0 2006.211.08:20:19.21#ibcon#end of sib2, iclass 38, count 0 2006.211.08:20:19.21#ibcon#*after write, iclass 38, count 0 2006.211.08:20:19.21#ibcon#*before return 0, iclass 38, count 0 2006.211.08:20:19.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:20:19.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:20:19.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:20:19.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:20:19.21$vc4f8/va=6,6 2006.211.08:20:19.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:20:19.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:20:19.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:19.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:20:19.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:20:19.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:20:19.27#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:20:19.27#ibcon#first serial, iclass 40, count 2 2006.211.08:20:19.27#ibcon#enter sib2, iclass 40, count 2 2006.211.08:20:19.27#ibcon#flushed, iclass 40, count 2 2006.211.08:20:19.27#ibcon#about to write, iclass 40, count 2 2006.211.08:20:19.27#ibcon#wrote, iclass 40, count 2 2006.211.08:20:19.27#ibcon#about to read 3, iclass 40, count 2 2006.211.08:20:19.29#ibcon#read 3, iclass 40, count 2 2006.211.08:20:19.29#ibcon#about to read 4, iclass 40, count 2 2006.211.08:20:19.29#ibcon#read 4, iclass 40, count 2 2006.211.08:20:19.29#ibcon#about to read 5, iclass 40, count 2 2006.211.08:20:19.29#ibcon#read 5, iclass 40, count 2 2006.211.08:20:19.29#ibcon#about to read 6, iclass 40, count 2 2006.211.08:20:19.29#ibcon#read 6, iclass 40, count 2 2006.211.08:20:19.29#ibcon#end of sib2, iclass 40, count 2 2006.211.08:20:19.29#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:20:19.29#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:20:19.29#ibcon#[25=AT06-06\r\n] 2006.211.08:20:19.29#ibcon#*before write, iclass 40, count 2 2006.211.08:20:19.29#ibcon#enter sib2, iclass 40, count 2 2006.211.08:20:19.29#ibcon#flushed, iclass 40, count 2 2006.211.08:20:19.29#ibcon#about to write, iclass 40, count 2 2006.211.08:20:19.29#ibcon#wrote, iclass 40, count 2 2006.211.08:20:19.29#ibcon#about to read 3, iclass 40, count 2 2006.211.08:20:19.32#ibcon#read 3, iclass 40, count 2 2006.211.08:20:19.32#ibcon#about to read 4, iclass 40, count 2 2006.211.08:20:19.32#ibcon#read 4, iclass 40, count 2 2006.211.08:20:19.32#ibcon#about to read 5, iclass 40, count 2 2006.211.08:20:19.32#ibcon#read 5, iclass 40, count 2 2006.211.08:20:19.32#ibcon#about to read 6, iclass 40, count 2 2006.211.08:20:19.32#ibcon#read 6, iclass 40, count 2 2006.211.08:20:19.32#ibcon#end of sib2, iclass 40, count 2 2006.211.08:20:19.32#ibcon#*after write, iclass 40, count 2 2006.211.08:20:19.32#ibcon#*before return 0, iclass 40, count 2 2006.211.08:20:19.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:20:19.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:20:19.32#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:20:19.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:19.32#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:20:19.44#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:20:19.44#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:20:19.44#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:20:19.44#ibcon#first serial, iclass 40, count 0 2006.211.08:20:19.44#ibcon#enter sib2, iclass 40, count 0 2006.211.08:20:19.44#ibcon#flushed, iclass 40, count 0 2006.211.08:20:19.44#ibcon#about to write, iclass 40, count 0 2006.211.08:20:19.44#ibcon#wrote, iclass 40, count 0 2006.211.08:20:19.44#ibcon#about to read 3, iclass 40, count 0 2006.211.08:20:19.46#ibcon#read 3, iclass 40, count 0 2006.211.08:20:19.46#ibcon#about to read 4, iclass 40, count 0 2006.211.08:20:19.46#ibcon#read 4, iclass 40, count 0 2006.211.08:20:19.46#ibcon#about to read 5, iclass 40, count 0 2006.211.08:20:19.46#ibcon#read 5, iclass 40, count 0 2006.211.08:20:19.46#ibcon#about to read 6, iclass 40, count 0 2006.211.08:20:19.46#ibcon#read 6, iclass 40, count 0 2006.211.08:20:19.46#ibcon#end of sib2, iclass 40, count 0 2006.211.08:20:19.46#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:20:19.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:20:19.46#ibcon#[25=USB\r\n] 2006.211.08:20:19.46#ibcon#*before write, iclass 40, count 0 2006.211.08:20:19.46#ibcon#enter sib2, iclass 40, count 0 2006.211.08:20:19.46#ibcon#flushed, iclass 40, count 0 2006.211.08:20:19.46#ibcon#about to write, iclass 40, count 0 2006.211.08:20:19.46#ibcon#wrote, iclass 40, count 0 2006.211.08:20:19.46#ibcon#about to read 3, iclass 40, count 0 2006.211.08:20:19.49#ibcon#read 3, iclass 40, count 0 2006.211.08:20:19.49#ibcon#about to read 4, iclass 40, count 0 2006.211.08:20:19.49#ibcon#read 4, iclass 40, count 0 2006.211.08:20:19.49#ibcon#about to read 5, iclass 40, count 0 2006.211.08:20:19.49#ibcon#read 5, iclass 40, count 0 2006.211.08:20:19.49#ibcon#about to read 6, iclass 40, count 0 2006.211.08:20:19.49#ibcon#read 6, iclass 40, count 0 2006.211.08:20:19.49#ibcon#end of sib2, iclass 40, count 0 2006.211.08:20:19.49#ibcon#*after write, iclass 40, count 0 2006.211.08:20:19.49#ibcon#*before return 0, iclass 40, count 0 2006.211.08:20:19.49#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:20:19.49#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:20:19.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:20:19.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:20:19.49$vc4f8/valo=7,832.99 2006.211.08:20:19.49#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:20:19.49#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:20:19.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:19.49#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:19.49#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:19.49#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:19.49#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:20:19.49#ibcon#first serial, iclass 4, count 0 2006.211.08:20:19.49#ibcon#enter sib2, iclass 4, count 0 2006.211.08:20:19.49#ibcon#flushed, iclass 4, count 0 2006.211.08:20:19.49#ibcon#about to write, iclass 4, count 0 2006.211.08:20:19.49#ibcon#wrote, iclass 4, count 0 2006.211.08:20:19.49#ibcon#about to read 3, iclass 4, count 0 2006.211.08:20:19.51#ibcon#read 3, iclass 4, count 0 2006.211.08:20:19.51#ibcon#about to read 4, iclass 4, count 0 2006.211.08:20:19.51#ibcon#read 4, iclass 4, count 0 2006.211.08:20:19.51#ibcon#about to read 5, iclass 4, count 0 2006.211.08:20:19.51#ibcon#read 5, iclass 4, count 0 2006.211.08:20:19.51#ibcon#about to read 6, iclass 4, count 0 2006.211.08:20:19.51#ibcon#read 6, iclass 4, count 0 2006.211.08:20:19.51#ibcon#end of sib2, iclass 4, count 0 2006.211.08:20:19.51#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:20:19.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:20:19.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:20:19.51#ibcon#*before write, iclass 4, count 0 2006.211.08:20:19.51#ibcon#enter sib2, iclass 4, count 0 2006.211.08:20:19.51#ibcon#flushed, iclass 4, count 0 2006.211.08:20:19.51#ibcon#about to write, iclass 4, count 0 2006.211.08:20:19.51#ibcon#wrote, iclass 4, count 0 2006.211.08:20:19.51#ibcon#about to read 3, iclass 4, count 0 2006.211.08:20:19.55#ibcon#read 3, iclass 4, count 0 2006.211.08:20:19.55#ibcon#about to read 4, iclass 4, count 0 2006.211.08:20:19.55#ibcon#read 4, iclass 4, count 0 2006.211.08:20:19.55#ibcon#about to read 5, iclass 4, count 0 2006.211.08:20:19.55#ibcon#read 5, iclass 4, count 0 2006.211.08:20:19.55#ibcon#about to read 6, iclass 4, count 0 2006.211.08:20:19.55#ibcon#read 6, iclass 4, count 0 2006.211.08:20:19.55#ibcon#end of sib2, iclass 4, count 0 2006.211.08:20:19.55#ibcon#*after write, iclass 4, count 0 2006.211.08:20:19.55#ibcon#*before return 0, iclass 4, count 0 2006.211.08:20:19.55#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:19.55#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:19.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:20:19.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:20:19.55$vc4f8/va=7,6 2006.211.08:20:19.55#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:20:19.55#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:20:19.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:19.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:20:19.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:20:19.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:20:19.61#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:20:19.61#ibcon#first serial, iclass 6, count 2 2006.211.08:20:19.61#ibcon#enter sib2, iclass 6, count 2 2006.211.08:20:19.61#ibcon#flushed, iclass 6, count 2 2006.211.08:20:19.61#ibcon#about to write, iclass 6, count 2 2006.211.08:20:19.61#ibcon#wrote, iclass 6, count 2 2006.211.08:20:19.61#ibcon#about to read 3, iclass 6, count 2 2006.211.08:20:19.63#ibcon#read 3, iclass 6, count 2 2006.211.08:20:19.63#ibcon#about to read 4, iclass 6, count 2 2006.211.08:20:19.63#ibcon#read 4, iclass 6, count 2 2006.211.08:20:19.63#ibcon#about to read 5, iclass 6, count 2 2006.211.08:20:19.63#ibcon#read 5, iclass 6, count 2 2006.211.08:20:19.63#ibcon#about to read 6, iclass 6, count 2 2006.211.08:20:19.63#ibcon#read 6, iclass 6, count 2 2006.211.08:20:19.63#ibcon#end of sib2, iclass 6, count 2 2006.211.08:20:19.63#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:20:19.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:20:19.63#ibcon#[25=AT07-06\r\n] 2006.211.08:20:19.63#ibcon#*before write, iclass 6, count 2 2006.211.08:20:19.63#ibcon#enter sib2, iclass 6, count 2 2006.211.08:20:19.63#ibcon#flushed, iclass 6, count 2 2006.211.08:20:19.63#ibcon#about to write, iclass 6, count 2 2006.211.08:20:19.63#ibcon#wrote, iclass 6, count 2 2006.211.08:20:19.63#ibcon#about to read 3, iclass 6, count 2 2006.211.08:20:19.66#ibcon#read 3, iclass 6, count 2 2006.211.08:20:19.66#ibcon#about to read 4, iclass 6, count 2 2006.211.08:20:19.66#ibcon#read 4, iclass 6, count 2 2006.211.08:20:19.66#ibcon#about to read 5, iclass 6, count 2 2006.211.08:20:19.66#ibcon#read 5, iclass 6, count 2 2006.211.08:20:19.66#ibcon#about to read 6, iclass 6, count 2 2006.211.08:20:19.66#ibcon#read 6, iclass 6, count 2 2006.211.08:20:19.66#ibcon#end of sib2, iclass 6, count 2 2006.211.08:20:19.66#ibcon#*after write, iclass 6, count 2 2006.211.08:20:19.66#ibcon#*before return 0, iclass 6, count 2 2006.211.08:20:19.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:20:19.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:20:19.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:20:19.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:19.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:20:19.78#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:20:19.78#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:20:19.78#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:20:19.78#ibcon#first serial, iclass 6, count 0 2006.211.08:20:19.78#ibcon#enter sib2, iclass 6, count 0 2006.211.08:20:19.78#ibcon#flushed, iclass 6, count 0 2006.211.08:20:19.78#ibcon#about to write, iclass 6, count 0 2006.211.08:20:19.78#ibcon#wrote, iclass 6, count 0 2006.211.08:20:19.78#ibcon#about to read 3, iclass 6, count 0 2006.211.08:20:19.80#ibcon#read 3, iclass 6, count 0 2006.211.08:20:19.80#ibcon#about to read 4, iclass 6, count 0 2006.211.08:20:19.80#ibcon#read 4, iclass 6, count 0 2006.211.08:20:19.80#ibcon#about to read 5, iclass 6, count 0 2006.211.08:20:19.80#ibcon#read 5, iclass 6, count 0 2006.211.08:20:19.80#ibcon#about to read 6, iclass 6, count 0 2006.211.08:20:19.80#ibcon#read 6, iclass 6, count 0 2006.211.08:20:19.80#ibcon#end of sib2, iclass 6, count 0 2006.211.08:20:19.80#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:20:19.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:20:19.80#ibcon#[25=USB\r\n] 2006.211.08:20:19.80#ibcon#*before write, iclass 6, count 0 2006.211.08:20:19.80#ibcon#enter sib2, iclass 6, count 0 2006.211.08:20:19.80#ibcon#flushed, iclass 6, count 0 2006.211.08:20:19.80#ibcon#about to write, iclass 6, count 0 2006.211.08:20:19.80#ibcon#wrote, iclass 6, count 0 2006.211.08:20:19.80#ibcon#about to read 3, iclass 6, count 0 2006.211.08:20:19.83#ibcon#read 3, iclass 6, count 0 2006.211.08:20:19.83#ibcon#about to read 4, iclass 6, count 0 2006.211.08:20:19.83#ibcon#read 4, iclass 6, count 0 2006.211.08:20:19.83#ibcon#about to read 5, iclass 6, count 0 2006.211.08:20:19.83#ibcon#read 5, iclass 6, count 0 2006.211.08:20:19.83#ibcon#about to read 6, iclass 6, count 0 2006.211.08:20:19.83#ibcon#read 6, iclass 6, count 0 2006.211.08:20:19.83#ibcon#end of sib2, iclass 6, count 0 2006.211.08:20:19.83#ibcon#*after write, iclass 6, count 0 2006.211.08:20:19.83#ibcon#*before return 0, iclass 6, count 0 2006.211.08:20:19.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:20:19.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:20:19.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:20:19.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:20:19.83$vc4f8/valo=8,852.99 2006.211.08:20:19.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:20:19.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:20:19.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:19.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:20:19.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:20:19.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:20:19.83#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:20:19.83#ibcon#first serial, iclass 10, count 0 2006.211.08:20:19.83#ibcon#enter sib2, iclass 10, count 0 2006.211.08:20:19.83#ibcon#flushed, iclass 10, count 0 2006.211.08:20:19.83#ibcon#about to write, iclass 10, count 0 2006.211.08:20:19.83#ibcon#wrote, iclass 10, count 0 2006.211.08:20:19.83#ibcon#about to read 3, iclass 10, count 0 2006.211.08:20:19.85#ibcon#read 3, iclass 10, count 0 2006.211.08:20:19.85#ibcon#about to read 4, iclass 10, count 0 2006.211.08:20:19.85#ibcon#read 4, iclass 10, count 0 2006.211.08:20:19.85#ibcon#about to read 5, iclass 10, count 0 2006.211.08:20:19.85#ibcon#read 5, iclass 10, count 0 2006.211.08:20:19.85#ibcon#about to read 6, iclass 10, count 0 2006.211.08:20:19.85#ibcon#read 6, iclass 10, count 0 2006.211.08:20:19.85#ibcon#end of sib2, iclass 10, count 0 2006.211.08:20:19.85#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:20:19.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:20:19.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:20:19.85#ibcon#*before write, iclass 10, count 0 2006.211.08:20:19.85#ibcon#enter sib2, iclass 10, count 0 2006.211.08:20:19.85#ibcon#flushed, iclass 10, count 0 2006.211.08:20:19.85#ibcon#about to write, iclass 10, count 0 2006.211.08:20:19.85#ibcon#wrote, iclass 10, count 0 2006.211.08:20:19.85#ibcon#about to read 3, iclass 10, count 0 2006.211.08:20:19.89#ibcon#read 3, iclass 10, count 0 2006.211.08:20:19.89#ibcon#about to read 4, iclass 10, count 0 2006.211.08:20:19.89#ibcon#read 4, iclass 10, count 0 2006.211.08:20:19.89#ibcon#about to read 5, iclass 10, count 0 2006.211.08:20:19.89#ibcon#read 5, iclass 10, count 0 2006.211.08:20:19.89#ibcon#about to read 6, iclass 10, count 0 2006.211.08:20:19.89#ibcon#read 6, iclass 10, count 0 2006.211.08:20:19.89#ibcon#end of sib2, iclass 10, count 0 2006.211.08:20:19.89#ibcon#*after write, iclass 10, count 0 2006.211.08:20:19.89#ibcon#*before return 0, iclass 10, count 0 2006.211.08:20:19.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:20:19.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:20:19.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:20:19.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:20:19.89$vc4f8/va=8,7 2006.211.08:20:19.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:20:19.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:20:19.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:19.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:20:19.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:20:19.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:20:19.95#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:20:19.95#ibcon#first serial, iclass 12, count 2 2006.211.08:20:19.95#ibcon#enter sib2, iclass 12, count 2 2006.211.08:20:19.95#ibcon#flushed, iclass 12, count 2 2006.211.08:20:19.95#ibcon#about to write, iclass 12, count 2 2006.211.08:20:19.95#ibcon#wrote, iclass 12, count 2 2006.211.08:20:19.95#ibcon#about to read 3, iclass 12, count 2 2006.211.08:20:19.97#ibcon#read 3, iclass 12, count 2 2006.211.08:20:19.97#ibcon#about to read 4, iclass 12, count 2 2006.211.08:20:19.97#ibcon#read 4, iclass 12, count 2 2006.211.08:20:19.97#ibcon#about to read 5, iclass 12, count 2 2006.211.08:20:19.97#ibcon#read 5, iclass 12, count 2 2006.211.08:20:19.97#ibcon#about to read 6, iclass 12, count 2 2006.211.08:20:19.97#ibcon#read 6, iclass 12, count 2 2006.211.08:20:19.97#ibcon#end of sib2, iclass 12, count 2 2006.211.08:20:19.97#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:20:19.97#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:20:19.97#ibcon#[25=AT08-07\r\n] 2006.211.08:20:19.97#ibcon#*before write, iclass 12, count 2 2006.211.08:20:19.97#ibcon#enter sib2, iclass 12, count 2 2006.211.08:20:19.97#ibcon#flushed, iclass 12, count 2 2006.211.08:20:19.97#ibcon#about to write, iclass 12, count 2 2006.211.08:20:19.97#ibcon#wrote, iclass 12, count 2 2006.211.08:20:19.97#ibcon#about to read 3, iclass 12, count 2 2006.211.08:20:20.00#ibcon#read 3, iclass 12, count 2 2006.211.08:20:20.00#ibcon#about to read 4, iclass 12, count 2 2006.211.08:20:20.00#ibcon#read 4, iclass 12, count 2 2006.211.08:20:20.00#ibcon#about to read 5, iclass 12, count 2 2006.211.08:20:20.00#ibcon#read 5, iclass 12, count 2 2006.211.08:20:20.00#ibcon#about to read 6, iclass 12, count 2 2006.211.08:20:20.00#ibcon#read 6, iclass 12, count 2 2006.211.08:20:20.00#ibcon#end of sib2, iclass 12, count 2 2006.211.08:20:20.00#ibcon#*after write, iclass 12, count 2 2006.211.08:20:20.00#ibcon#*before return 0, iclass 12, count 2 2006.211.08:20:20.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:20:20.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:20:20.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:20:20.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:20.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:20:20.12#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:20:20.12#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:20:20.12#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:20:20.12#ibcon#first serial, iclass 12, count 0 2006.211.08:20:20.12#ibcon#enter sib2, iclass 12, count 0 2006.211.08:20:20.12#ibcon#flushed, iclass 12, count 0 2006.211.08:20:20.12#ibcon#about to write, iclass 12, count 0 2006.211.08:20:20.12#ibcon#wrote, iclass 12, count 0 2006.211.08:20:20.12#ibcon#about to read 3, iclass 12, count 0 2006.211.08:20:20.14#ibcon#read 3, iclass 12, count 0 2006.211.08:20:20.14#ibcon#about to read 4, iclass 12, count 0 2006.211.08:20:20.14#ibcon#read 4, iclass 12, count 0 2006.211.08:20:20.14#ibcon#about to read 5, iclass 12, count 0 2006.211.08:20:20.14#ibcon#read 5, iclass 12, count 0 2006.211.08:20:20.14#ibcon#about to read 6, iclass 12, count 0 2006.211.08:20:20.14#ibcon#read 6, iclass 12, count 0 2006.211.08:20:20.14#ibcon#end of sib2, iclass 12, count 0 2006.211.08:20:20.14#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:20:20.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:20:20.14#ibcon#[25=USB\r\n] 2006.211.08:20:20.14#ibcon#*before write, iclass 12, count 0 2006.211.08:20:20.14#ibcon#enter sib2, iclass 12, count 0 2006.211.08:20:20.14#ibcon#flushed, iclass 12, count 0 2006.211.08:20:20.14#ibcon#about to write, iclass 12, count 0 2006.211.08:20:20.14#ibcon#wrote, iclass 12, count 0 2006.211.08:20:20.14#ibcon#about to read 3, iclass 12, count 0 2006.211.08:20:20.17#ibcon#read 3, iclass 12, count 0 2006.211.08:20:20.17#ibcon#about to read 4, iclass 12, count 0 2006.211.08:20:20.17#ibcon#read 4, iclass 12, count 0 2006.211.08:20:20.17#ibcon#about to read 5, iclass 12, count 0 2006.211.08:20:20.17#ibcon#read 5, iclass 12, count 0 2006.211.08:20:20.17#ibcon#about to read 6, iclass 12, count 0 2006.211.08:20:20.17#ibcon#read 6, iclass 12, count 0 2006.211.08:20:20.17#ibcon#end of sib2, iclass 12, count 0 2006.211.08:20:20.17#ibcon#*after write, iclass 12, count 0 2006.211.08:20:20.17#ibcon#*before return 0, iclass 12, count 0 2006.211.08:20:20.17#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:20:20.17#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:20:20.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:20:20.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:20:20.17$vc4f8/vblo=1,632.99 2006.211.08:20:20.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:20:20.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:20:20.17#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:20.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:20:20.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:20:20.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:20:20.17#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:20:20.17#ibcon#first serial, iclass 14, count 0 2006.211.08:20:20.17#ibcon#enter sib2, iclass 14, count 0 2006.211.08:20:20.17#ibcon#flushed, iclass 14, count 0 2006.211.08:20:20.17#ibcon#about to write, iclass 14, count 0 2006.211.08:20:20.17#ibcon#wrote, iclass 14, count 0 2006.211.08:20:20.17#ibcon#about to read 3, iclass 14, count 0 2006.211.08:20:20.19#ibcon#read 3, iclass 14, count 0 2006.211.08:20:20.19#ibcon#about to read 4, iclass 14, count 0 2006.211.08:20:20.19#ibcon#read 4, iclass 14, count 0 2006.211.08:20:20.19#ibcon#about to read 5, iclass 14, count 0 2006.211.08:20:20.19#ibcon#read 5, iclass 14, count 0 2006.211.08:20:20.19#ibcon#about to read 6, iclass 14, count 0 2006.211.08:20:20.19#ibcon#read 6, iclass 14, count 0 2006.211.08:20:20.19#ibcon#end of sib2, iclass 14, count 0 2006.211.08:20:20.19#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:20:20.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:20:20.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:20:20.19#ibcon#*before write, iclass 14, count 0 2006.211.08:20:20.19#ibcon#enter sib2, iclass 14, count 0 2006.211.08:20:20.19#ibcon#flushed, iclass 14, count 0 2006.211.08:20:20.19#ibcon#about to write, iclass 14, count 0 2006.211.08:20:20.19#ibcon#wrote, iclass 14, count 0 2006.211.08:20:20.19#ibcon#about to read 3, iclass 14, count 0 2006.211.08:20:20.23#ibcon#read 3, iclass 14, count 0 2006.211.08:20:20.23#ibcon#about to read 4, iclass 14, count 0 2006.211.08:20:20.23#ibcon#read 4, iclass 14, count 0 2006.211.08:20:20.23#ibcon#about to read 5, iclass 14, count 0 2006.211.08:20:20.23#ibcon#read 5, iclass 14, count 0 2006.211.08:20:20.23#ibcon#about to read 6, iclass 14, count 0 2006.211.08:20:20.23#ibcon#read 6, iclass 14, count 0 2006.211.08:20:20.23#ibcon#end of sib2, iclass 14, count 0 2006.211.08:20:20.23#ibcon#*after write, iclass 14, count 0 2006.211.08:20:20.23#ibcon#*before return 0, iclass 14, count 0 2006.211.08:20:20.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:20:20.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:20:20.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:20:20.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:20:20.23$vc4f8/vb=1,4 2006.211.08:20:20.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:20:20.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:20:20.23#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:20.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:20:20.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:20:20.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:20:20.23#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:20:20.23#ibcon#first serial, iclass 16, count 2 2006.211.08:20:20.23#ibcon#enter sib2, iclass 16, count 2 2006.211.08:20:20.23#ibcon#flushed, iclass 16, count 2 2006.211.08:20:20.23#ibcon#about to write, iclass 16, count 2 2006.211.08:20:20.23#ibcon#wrote, iclass 16, count 2 2006.211.08:20:20.23#ibcon#about to read 3, iclass 16, count 2 2006.211.08:20:20.25#ibcon#read 3, iclass 16, count 2 2006.211.08:20:20.25#ibcon#about to read 4, iclass 16, count 2 2006.211.08:20:20.25#ibcon#read 4, iclass 16, count 2 2006.211.08:20:20.25#ibcon#about to read 5, iclass 16, count 2 2006.211.08:20:20.25#ibcon#read 5, iclass 16, count 2 2006.211.08:20:20.25#ibcon#about to read 6, iclass 16, count 2 2006.211.08:20:20.25#ibcon#read 6, iclass 16, count 2 2006.211.08:20:20.25#ibcon#end of sib2, iclass 16, count 2 2006.211.08:20:20.25#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:20:20.25#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:20:20.25#ibcon#[27=AT01-04\r\n] 2006.211.08:20:20.25#ibcon#*before write, iclass 16, count 2 2006.211.08:20:20.25#ibcon#enter sib2, iclass 16, count 2 2006.211.08:20:20.25#ibcon#flushed, iclass 16, count 2 2006.211.08:20:20.25#ibcon#about to write, iclass 16, count 2 2006.211.08:20:20.25#ibcon#wrote, iclass 16, count 2 2006.211.08:20:20.25#ibcon#about to read 3, iclass 16, count 2 2006.211.08:20:20.28#ibcon#read 3, iclass 16, count 2 2006.211.08:20:20.28#ibcon#about to read 4, iclass 16, count 2 2006.211.08:20:20.28#ibcon#read 4, iclass 16, count 2 2006.211.08:20:20.28#ibcon#about to read 5, iclass 16, count 2 2006.211.08:20:20.28#ibcon#read 5, iclass 16, count 2 2006.211.08:20:20.28#ibcon#about to read 6, iclass 16, count 2 2006.211.08:20:20.28#ibcon#read 6, iclass 16, count 2 2006.211.08:20:20.28#ibcon#end of sib2, iclass 16, count 2 2006.211.08:20:20.28#ibcon#*after write, iclass 16, count 2 2006.211.08:20:20.28#ibcon#*before return 0, iclass 16, count 2 2006.211.08:20:20.28#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:20:20.28#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:20:20.28#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:20:20.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:20.28#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:20:20.40#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:20:20.40#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:20:20.40#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:20:20.40#ibcon#first serial, iclass 16, count 0 2006.211.08:20:20.40#ibcon#enter sib2, iclass 16, count 0 2006.211.08:20:20.40#ibcon#flushed, iclass 16, count 0 2006.211.08:20:20.40#ibcon#about to write, iclass 16, count 0 2006.211.08:20:20.40#ibcon#wrote, iclass 16, count 0 2006.211.08:20:20.40#ibcon#about to read 3, iclass 16, count 0 2006.211.08:20:20.42#ibcon#read 3, iclass 16, count 0 2006.211.08:20:20.42#ibcon#about to read 4, iclass 16, count 0 2006.211.08:20:20.42#ibcon#read 4, iclass 16, count 0 2006.211.08:20:20.42#ibcon#about to read 5, iclass 16, count 0 2006.211.08:20:20.42#ibcon#read 5, iclass 16, count 0 2006.211.08:20:20.42#ibcon#about to read 6, iclass 16, count 0 2006.211.08:20:20.42#ibcon#read 6, iclass 16, count 0 2006.211.08:20:20.42#ibcon#end of sib2, iclass 16, count 0 2006.211.08:20:20.42#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:20:20.42#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:20:20.42#ibcon#[27=USB\r\n] 2006.211.08:20:20.42#ibcon#*before write, iclass 16, count 0 2006.211.08:20:20.42#ibcon#enter sib2, iclass 16, count 0 2006.211.08:20:20.42#ibcon#flushed, iclass 16, count 0 2006.211.08:20:20.42#ibcon#about to write, iclass 16, count 0 2006.211.08:20:20.42#ibcon#wrote, iclass 16, count 0 2006.211.08:20:20.42#ibcon#about to read 3, iclass 16, count 0 2006.211.08:20:20.45#ibcon#read 3, iclass 16, count 0 2006.211.08:20:20.45#ibcon#about to read 4, iclass 16, count 0 2006.211.08:20:20.45#ibcon#read 4, iclass 16, count 0 2006.211.08:20:20.45#ibcon#about to read 5, iclass 16, count 0 2006.211.08:20:20.45#ibcon#read 5, iclass 16, count 0 2006.211.08:20:20.45#ibcon#about to read 6, iclass 16, count 0 2006.211.08:20:20.45#ibcon#read 6, iclass 16, count 0 2006.211.08:20:20.45#ibcon#end of sib2, iclass 16, count 0 2006.211.08:20:20.45#ibcon#*after write, iclass 16, count 0 2006.211.08:20:20.45#ibcon#*before return 0, iclass 16, count 0 2006.211.08:20:20.45#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:20:20.45#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:20:20.45#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:20:20.45#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:20:20.45$vc4f8/vblo=2,640.99 2006.211.08:20:20.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:20:20.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:20:20.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:20.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:20.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:20.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:20.45#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:20:20.45#ibcon#first serial, iclass 18, count 0 2006.211.08:20:20.45#ibcon#enter sib2, iclass 18, count 0 2006.211.08:20:20.45#ibcon#flushed, iclass 18, count 0 2006.211.08:20:20.45#ibcon#about to write, iclass 18, count 0 2006.211.08:20:20.45#ibcon#wrote, iclass 18, count 0 2006.211.08:20:20.45#ibcon#about to read 3, iclass 18, count 0 2006.211.08:20:20.47#ibcon#read 3, iclass 18, count 0 2006.211.08:20:20.47#ibcon#about to read 4, iclass 18, count 0 2006.211.08:20:20.47#ibcon#read 4, iclass 18, count 0 2006.211.08:20:20.47#ibcon#about to read 5, iclass 18, count 0 2006.211.08:20:20.47#ibcon#read 5, iclass 18, count 0 2006.211.08:20:20.47#ibcon#about to read 6, iclass 18, count 0 2006.211.08:20:20.47#ibcon#read 6, iclass 18, count 0 2006.211.08:20:20.47#ibcon#end of sib2, iclass 18, count 0 2006.211.08:20:20.47#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:20:20.47#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:20:20.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:20:20.47#ibcon#*before write, iclass 18, count 0 2006.211.08:20:20.47#ibcon#enter sib2, iclass 18, count 0 2006.211.08:20:20.47#ibcon#flushed, iclass 18, count 0 2006.211.08:20:20.47#ibcon#about to write, iclass 18, count 0 2006.211.08:20:20.47#ibcon#wrote, iclass 18, count 0 2006.211.08:20:20.47#ibcon#about to read 3, iclass 18, count 0 2006.211.08:20:20.51#ibcon#read 3, iclass 18, count 0 2006.211.08:20:20.51#ibcon#about to read 4, iclass 18, count 0 2006.211.08:20:20.51#ibcon#read 4, iclass 18, count 0 2006.211.08:20:20.51#ibcon#about to read 5, iclass 18, count 0 2006.211.08:20:20.51#ibcon#read 5, iclass 18, count 0 2006.211.08:20:20.51#ibcon#about to read 6, iclass 18, count 0 2006.211.08:20:20.51#ibcon#read 6, iclass 18, count 0 2006.211.08:20:20.51#ibcon#end of sib2, iclass 18, count 0 2006.211.08:20:20.51#ibcon#*after write, iclass 18, count 0 2006.211.08:20:20.51#ibcon#*before return 0, iclass 18, count 0 2006.211.08:20:20.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:20.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:20:20.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:20:20.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:20:20.51$vc4f8/vb=2,4 2006.211.08:20:20.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:20:20.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:20:20.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:20.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:20.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:20.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:20.57#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:20:20.57#ibcon#first serial, iclass 20, count 2 2006.211.08:20:20.57#ibcon#enter sib2, iclass 20, count 2 2006.211.08:20:20.57#ibcon#flushed, iclass 20, count 2 2006.211.08:20:20.57#ibcon#about to write, iclass 20, count 2 2006.211.08:20:20.57#ibcon#wrote, iclass 20, count 2 2006.211.08:20:20.57#ibcon#about to read 3, iclass 20, count 2 2006.211.08:20:20.59#ibcon#read 3, iclass 20, count 2 2006.211.08:20:20.59#ibcon#about to read 4, iclass 20, count 2 2006.211.08:20:20.59#ibcon#read 4, iclass 20, count 2 2006.211.08:20:20.59#ibcon#about to read 5, iclass 20, count 2 2006.211.08:20:20.59#ibcon#read 5, iclass 20, count 2 2006.211.08:20:20.59#ibcon#about to read 6, iclass 20, count 2 2006.211.08:20:20.59#ibcon#read 6, iclass 20, count 2 2006.211.08:20:20.59#ibcon#end of sib2, iclass 20, count 2 2006.211.08:20:20.59#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:20:20.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:20:20.59#ibcon#[27=AT02-04\r\n] 2006.211.08:20:20.59#ibcon#*before write, iclass 20, count 2 2006.211.08:20:20.59#ibcon#enter sib2, iclass 20, count 2 2006.211.08:20:20.59#ibcon#flushed, iclass 20, count 2 2006.211.08:20:20.59#ibcon#about to write, iclass 20, count 2 2006.211.08:20:20.59#ibcon#wrote, iclass 20, count 2 2006.211.08:20:20.59#ibcon#about to read 3, iclass 20, count 2 2006.211.08:20:20.62#ibcon#read 3, iclass 20, count 2 2006.211.08:20:20.62#ibcon#about to read 4, iclass 20, count 2 2006.211.08:20:20.62#ibcon#read 4, iclass 20, count 2 2006.211.08:20:20.62#ibcon#about to read 5, iclass 20, count 2 2006.211.08:20:20.62#ibcon#read 5, iclass 20, count 2 2006.211.08:20:20.62#ibcon#about to read 6, iclass 20, count 2 2006.211.08:20:20.62#ibcon#read 6, iclass 20, count 2 2006.211.08:20:20.62#ibcon#end of sib2, iclass 20, count 2 2006.211.08:20:20.62#ibcon#*after write, iclass 20, count 2 2006.211.08:20:20.62#ibcon#*before return 0, iclass 20, count 2 2006.211.08:20:20.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:20.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:20:20.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:20:20.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:20.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:20.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:20.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:20.74#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:20:20.74#ibcon#first serial, iclass 20, count 0 2006.211.08:20:20.74#ibcon#enter sib2, iclass 20, count 0 2006.211.08:20:20.74#ibcon#flushed, iclass 20, count 0 2006.211.08:20:20.74#ibcon#about to write, iclass 20, count 0 2006.211.08:20:20.74#ibcon#wrote, iclass 20, count 0 2006.211.08:20:20.74#ibcon#about to read 3, iclass 20, count 0 2006.211.08:20:20.76#ibcon#read 3, iclass 20, count 0 2006.211.08:20:20.76#ibcon#about to read 4, iclass 20, count 0 2006.211.08:20:20.76#ibcon#read 4, iclass 20, count 0 2006.211.08:20:20.76#ibcon#about to read 5, iclass 20, count 0 2006.211.08:20:20.76#ibcon#read 5, iclass 20, count 0 2006.211.08:20:20.76#ibcon#about to read 6, iclass 20, count 0 2006.211.08:20:20.76#ibcon#read 6, iclass 20, count 0 2006.211.08:20:20.76#ibcon#end of sib2, iclass 20, count 0 2006.211.08:20:20.76#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:20:20.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:20:20.76#ibcon#[27=USB\r\n] 2006.211.08:20:20.76#ibcon#*before write, iclass 20, count 0 2006.211.08:20:20.76#ibcon#enter sib2, iclass 20, count 0 2006.211.08:20:20.76#ibcon#flushed, iclass 20, count 0 2006.211.08:20:20.76#ibcon#about to write, iclass 20, count 0 2006.211.08:20:20.76#ibcon#wrote, iclass 20, count 0 2006.211.08:20:20.76#ibcon#about to read 3, iclass 20, count 0 2006.211.08:20:20.79#ibcon#read 3, iclass 20, count 0 2006.211.08:20:20.79#ibcon#about to read 4, iclass 20, count 0 2006.211.08:20:20.79#ibcon#read 4, iclass 20, count 0 2006.211.08:20:20.79#ibcon#about to read 5, iclass 20, count 0 2006.211.08:20:20.79#ibcon#read 5, iclass 20, count 0 2006.211.08:20:20.79#ibcon#about to read 6, iclass 20, count 0 2006.211.08:20:20.79#ibcon#read 6, iclass 20, count 0 2006.211.08:20:20.79#ibcon#end of sib2, iclass 20, count 0 2006.211.08:20:20.79#ibcon#*after write, iclass 20, count 0 2006.211.08:20:20.79#ibcon#*before return 0, iclass 20, count 0 2006.211.08:20:20.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:20.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:20:20.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:20:20.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:20:20.79$vc4f8/vblo=3,656.99 2006.211.08:20:20.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:20:20.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:20:20.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:20.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:20.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:20.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:20.79#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:20:20.79#ibcon#first serial, iclass 22, count 0 2006.211.08:20:20.79#ibcon#enter sib2, iclass 22, count 0 2006.211.08:20:20.79#ibcon#flushed, iclass 22, count 0 2006.211.08:20:20.79#ibcon#about to write, iclass 22, count 0 2006.211.08:20:20.79#ibcon#wrote, iclass 22, count 0 2006.211.08:20:20.79#ibcon#about to read 3, iclass 22, count 0 2006.211.08:20:20.81#ibcon#read 3, iclass 22, count 0 2006.211.08:20:20.81#ibcon#about to read 4, iclass 22, count 0 2006.211.08:20:20.81#ibcon#read 4, iclass 22, count 0 2006.211.08:20:20.81#ibcon#about to read 5, iclass 22, count 0 2006.211.08:20:20.81#ibcon#read 5, iclass 22, count 0 2006.211.08:20:20.81#ibcon#about to read 6, iclass 22, count 0 2006.211.08:20:20.81#ibcon#read 6, iclass 22, count 0 2006.211.08:20:20.81#ibcon#end of sib2, iclass 22, count 0 2006.211.08:20:20.81#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:20:20.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:20:20.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:20:20.81#ibcon#*before write, iclass 22, count 0 2006.211.08:20:20.81#ibcon#enter sib2, iclass 22, count 0 2006.211.08:20:20.81#ibcon#flushed, iclass 22, count 0 2006.211.08:20:20.81#ibcon#about to write, iclass 22, count 0 2006.211.08:20:20.81#ibcon#wrote, iclass 22, count 0 2006.211.08:20:20.81#ibcon#about to read 3, iclass 22, count 0 2006.211.08:20:20.85#ibcon#read 3, iclass 22, count 0 2006.211.08:20:20.85#ibcon#about to read 4, iclass 22, count 0 2006.211.08:20:20.85#ibcon#read 4, iclass 22, count 0 2006.211.08:20:20.85#ibcon#about to read 5, iclass 22, count 0 2006.211.08:20:20.85#ibcon#read 5, iclass 22, count 0 2006.211.08:20:20.85#ibcon#about to read 6, iclass 22, count 0 2006.211.08:20:20.85#ibcon#read 6, iclass 22, count 0 2006.211.08:20:20.85#ibcon#end of sib2, iclass 22, count 0 2006.211.08:20:20.85#ibcon#*after write, iclass 22, count 0 2006.211.08:20:20.85#ibcon#*before return 0, iclass 22, count 0 2006.211.08:20:20.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:20.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:20:20.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:20:20.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:20:20.85$vc4f8/vb=3,3 2006.211.08:20:20.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:20:20.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:20:20.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:20.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:20.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:20.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:20.91#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:20:20.91#ibcon#first serial, iclass 24, count 2 2006.211.08:20:20.91#ibcon#enter sib2, iclass 24, count 2 2006.211.08:20:20.91#ibcon#flushed, iclass 24, count 2 2006.211.08:20:20.91#ibcon#about to write, iclass 24, count 2 2006.211.08:20:20.91#ibcon#wrote, iclass 24, count 2 2006.211.08:20:20.91#ibcon#about to read 3, iclass 24, count 2 2006.211.08:20:20.93#ibcon#read 3, iclass 24, count 2 2006.211.08:20:20.93#ibcon#about to read 4, iclass 24, count 2 2006.211.08:20:20.93#ibcon#read 4, iclass 24, count 2 2006.211.08:20:20.93#ibcon#about to read 5, iclass 24, count 2 2006.211.08:20:20.93#ibcon#read 5, iclass 24, count 2 2006.211.08:20:20.93#ibcon#about to read 6, iclass 24, count 2 2006.211.08:20:20.93#ibcon#read 6, iclass 24, count 2 2006.211.08:20:20.93#ibcon#end of sib2, iclass 24, count 2 2006.211.08:20:20.93#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:20:20.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:20:20.93#ibcon#[27=AT03-03\r\n] 2006.211.08:20:20.93#ibcon#*before write, iclass 24, count 2 2006.211.08:20:20.93#ibcon#enter sib2, iclass 24, count 2 2006.211.08:20:20.93#ibcon#flushed, iclass 24, count 2 2006.211.08:20:20.93#ibcon#about to write, iclass 24, count 2 2006.211.08:20:20.93#ibcon#wrote, iclass 24, count 2 2006.211.08:20:20.93#ibcon#about to read 3, iclass 24, count 2 2006.211.08:20:20.96#ibcon#read 3, iclass 24, count 2 2006.211.08:20:20.96#ibcon#about to read 4, iclass 24, count 2 2006.211.08:20:20.96#ibcon#read 4, iclass 24, count 2 2006.211.08:20:20.96#ibcon#about to read 5, iclass 24, count 2 2006.211.08:20:20.96#ibcon#read 5, iclass 24, count 2 2006.211.08:20:20.96#ibcon#about to read 6, iclass 24, count 2 2006.211.08:20:20.96#ibcon#read 6, iclass 24, count 2 2006.211.08:20:20.96#ibcon#end of sib2, iclass 24, count 2 2006.211.08:20:20.96#ibcon#*after write, iclass 24, count 2 2006.211.08:20:20.96#ibcon#*before return 0, iclass 24, count 2 2006.211.08:20:20.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:20.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:20:20.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:20:20.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:20.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:21.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:21.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:21.08#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:20:21.08#ibcon#first serial, iclass 24, count 0 2006.211.08:20:21.08#ibcon#enter sib2, iclass 24, count 0 2006.211.08:20:21.08#ibcon#flushed, iclass 24, count 0 2006.211.08:20:21.08#ibcon#about to write, iclass 24, count 0 2006.211.08:20:21.08#ibcon#wrote, iclass 24, count 0 2006.211.08:20:21.08#ibcon#about to read 3, iclass 24, count 0 2006.211.08:20:21.10#ibcon#read 3, iclass 24, count 0 2006.211.08:20:21.10#ibcon#about to read 4, iclass 24, count 0 2006.211.08:20:21.10#ibcon#read 4, iclass 24, count 0 2006.211.08:20:21.10#ibcon#about to read 5, iclass 24, count 0 2006.211.08:20:21.10#ibcon#read 5, iclass 24, count 0 2006.211.08:20:21.10#ibcon#about to read 6, iclass 24, count 0 2006.211.08:20:21.10#ibcon#read 6, iclass 24, count 0 2006.211.08:20:21.10#ibcon#end of sib2, iclass 24, count 0 2006.211.08:20:21.10#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:20:21.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:20:21.10#ibcon#[27=USB\r\n] 2006.211.08:20:21.10#ibcon#*before write, iclass 24, count 0 2006.211.08:20:21.10#ibcon#enter sib2, iclass 24, count 0 2006.211.08:20:21.10#ibcon#flushed, iclass 24, count 0 2006.211.08:20:21.10#ibcon#about to write, iclass 24, count 0 2006.211.08:20:21.10#ibcon#wrote, iclass 24, count 0 2006.211.08:20:21.10#ibcon#about to read 3, iclass 24, count 0 2006.211.08:20:21.13#ibcon#read 3, iclass 24, count 0 2006.211.08:20:21.13#ibcon#about to read 4, iclass 24, count 0 2006.211.08:20:21.13#ibcon#read 4, iclass 24, count 0 2006.211.08:20:21.13#ibcon#about to read 5, iclass 24, count 0 2006.211.08:20:21.13#ibcon#read 5, iclass 24, count 0 2006.211.08:20:21.13#ibcon#about to read 6, iclass 24, count 0 2006.211.08:20:21.13#ibcon#read 6, iclass 24, count 0 2006.211.08:20:21.13#ibcon#end of sib2, iclass 24, count 0 2006.211.08:20:21.13#ibcon#*after write, iclass 24, count 0 2006.211.08:20:21.13#ibcon#*before return 0, iclass 24, count 0 2006.211.08:20:21.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:21.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:20:21.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:20:21.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:20:21.13$vc4f8/vblo=4,712.99 2006.211.08:20:21.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:20:21.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:20:21.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:21.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:21.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:21.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:21.13#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:20:21.13#ibcon#first serial, iclass 26, count 0 2006.211.08:20:21.13#ibcon#enter sib2, iclass 26, count 0 2006.211.08:20:21.13#ibcon#flushed, iclass 26, count 0 2006.211.08:20:21.13#ibcon#about to write, iclass 26, count 0 2006.211.08:20:21.13#ibcon#wrote, iclass 26, count 0 2006.211.08:20:21.13#ibcon#about to read 3, iclass 26, count 0 2006.211.08:20:21.15#ibcon#read 3, iclass 26, count 0 2006.211.08:20:21.15#ibcon#about to read 4, iclass 26, count 0 2006.211.08:20:21.15#ibcon#read 4, iclass 26, count 0 2006.211.08:20:21.15#ibcon#about to read 5, iclass 26, count 0 2006.211.08:20:21.15#ibcon#read 5, iclass 26, count 0 2006.211.08:20:21.15#ibcon#about to read 6, iclass 26, count 0 2006.211.08:20:21.15#ibcon#read 6, iclass 26, count 0 2006.211.08:20:21.15#ibcon#end of sib2, iclass 26, count 0 2006.211.08:20:21.15#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:20:21.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:20:21.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:20:21.15#ibcon#*before write, iclass 26, count 0 2006.211.08:20:21.15#ibcon#enter sib2, iclass 26, count 0 2006.211.08:20:21.15#ibcon#flushed, iclass 26, count 0 2006.211.08:20:21.15#ibcon#about to write, iclass 26, count 0 2006.211.08:20:21.15#ibcon#wrote, iclass 26, count 0 2006.211.08:20:21.15#ibcon#about to read 3, iclass 26, count 0 2006.211.08:20:21.19#ibcon#read 3, iclass 26, count 0 2006.211.08:20:21.19#ibcon#about to read 4, iclass 26, count 0 2006.211.08:20:21.19#ibcon#read 4, iclass 26, count 0 2006.211.08:20:21.19#ibcon#about to read 5, iclass 26, count 0 2006.211.08:20:21.19#ibcon#read 5, iclass 26, count 0 2006.211.08:20:21.19#ibcon#about to read 6, iclass 26, count 0 2006.211.08:20:21.19#ibcon#read 6, iclass 26, count 0 2006.211.08:20:21.19#ibcon#end of sib2, iclass 26, count 0 2006.211.08:20:21.19#ibcon#*after write, iclass 26, count 0 2006.211.08:20:21.19#ibcon#*before return 0, iclass 26, count 0 2006.211.08:20:21.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:21.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:20:21.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:20:21.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:20:21.19$vc4f8/vb=4,3 2006.211.08:20:21.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:20:21.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:20:21.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:21.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:21.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:21.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:21.25#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:20:21.25#ibcon#first serial, iclass 28, count 2 2006.211.08:20:21.25#ibcon#enter sib2, iclass 28, count 2 2006.211.08:20:21.25#ibcon#flushed, iclass 28, count 2 2006.211.08:20:21.25#ibcon#about to write, iclass 28, count 2 2006.211.08:20:21.25#ibcon#wrote, iclass 28, count 2 2006.211.08:20:21.25#ibcon#about to read 3, iclass 28, count 2 2006.211.08:20:21.27#ibcon#read 3, iclass 28, count 2 2006.211.08:20:21.27#ibcon#about to read 4, iclass 28, count 2 2006.211.08:20:21.27#ibcon#read 4, iclass 28, count 2 2006.211.08:20:21.27#ibcon#about to read 5, iclass 28, count 2 2006.211.08:20:21.27#ibcon#read 5, iclass 28, count 2 2006.211.08:20:21.27#ibcon#about to read 6, iclass 28, count 2 2006.211.08:20:21.27#ibcon#read 6, iclass 28, count 2 2006.211.08:20:21.27#ibcon#end of sib2, iclass 28, count 2 2006.211.08:20:21.27#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:20:21.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:20:21.27#ibcon#[27=AT04-03\r\n] 2006.211.08:20:21.27#ibcon#*before write, iclass 28, count 2 2006.211.08:20:21.27#ibcon#enter sib2, iclass 28, count 2 2006.211.08:20:21.27#ibcon#flushed, iclass 28, count 2 2006.211.08:20:21.27#ibcon#about to write, iclass 28, count 2 2006.211.08:20:21.27#ibcon#wrote, iclass 28, count 2 2006.211.08:20:21.27#ibcon#about to read 3, iclass 28, count 2 2006.211.08:20:21.30#ibcon#read 3, iclass 28, count 2 2006.211.08:20:21.30#ibcon#about to read 4, iclass 28, count 2 2006.211.08:20:21.30#ibcon#read 4, iclass 28, count 2 2006.211.08:20:21.30#ibcon#about to read 5, iclass 28, count 2 2006.211.08:20:21.30#ibcon#read 5, iclass 28, count 2 2006.211.08:20:21.30#ibcon#about to read 6, iclass 28, count 2 2006.211.08:20:21.30#ibcon#read 6, iclass 28, count 2 2006.211.08:20:21.30#ibcon#end of sib2, iclass 28, count 2 2006.211.08:20:21.30#ibcon#*after write, iclass 28, count 2 2006.211.08:20:21.30#ibcon#*before return 0, iclass 28, count 2 2006.211.08:20:21.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:21.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:20:21.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:20:21.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:21.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:21.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:21.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:21.42#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:20:21.42#ibcon#first serial, iclass 28, count 0 2006.211.08:20:21.42#ibcon#enter sib2, iclass 28, count 0 2006.211.08:20:21.42#ibcon#flushed, iclass 28, count 0 2006.211.08:20:21.42#ibcon#about to write, iclass 28, count 0 2006.211.08:20:21.42#ibcon#wrote, iclass 28, count 0 2006.211.08:20:21.42#ibcon#about to read 3, iclass 28, count 0 2006.211.08:20:21.44#ibcon#read 3, iclass 28, count 0 2006.211.08:20:21.44#ibcon#about to read 4, iclass 28, count 0 2006.211.08:20:21.44#ibcon#read 4, iclass 28, count 0 2006.211.08:20:21.44#ibcon#about to read 5, iclass 28, count 0 2006.211.08:20:21.44#ibcon#read 5, iclass 28, count 0 2006.211.08:20:21.44#ibcon#about to read 6, iclass 28, count 0 2006.211.08:20:21.44#ibcon#read 6, iclass 28, count 0 2006.211.08:20:21.44#ibcon#end of sib2, iclass 28, count 0 2006.211.08:20:21.44#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:20:21.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:20:21.44#ibcon#[27=USB\r\n] 2006.211.08:20:21.44#ibcon#*before write, iclass 28, count 0 2006.211.08:20:21.44#ibcon#enter sib2, iclass 28, count 0 2006.211.08:20:21.44#ibcon#flushed, iclass 28, count 0 2006.211.08:20:21.44#ibcon#about to write, iclass 28, count 0 2006.211.08:20:21.44#ibcon#wrote, iclass 28, count 0 2006.211.08:20:21.44#ibcon#about to read 3, iclass 28, count 0 2006.211.08:20:21.47#ibcon#read 3, iclass 28, count 0 2006.211.08:20:21.47#ibcon#about to read 4, iclass 28, count 0 2006.211.08:20:21.47#ibcon#read 4, iclass 28, count 0 2006.211.08:20:21.47#ibcon#about to read 5, iclass 28, count 0 2006.211.08:20:21.47#ibcon#read 5, iclass 28, count 0 2006.211.08:20:21.47#ibcon#about to read 6, iclass 28, count 0 2006.211.08:20:21.47#ibcon#read 6, iclass 28, count 0 2006.211.08:20:21.47#ibcon#end of sib2, iclass 28, count 0 2006.211.08:20:21.47#ibcon#*after write, iclass 28, count 0 2006.211.08:20:21.47#ibcon#*before return 0, iclass 28, count 0 2006.211.08:20:21.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:21.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:20:21.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:20:21.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:20:21.47$vc4f8/vblo=5,744.99 2006.211.08:20:21.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:20:21.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:20:21.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:21.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:21.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:21.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:21.47#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:20:21.47#ibcon#first serial, iclass 30, count 0 2006.211.08:20:21.47#ibcon#enter sib2, iclass 30, count 0 2006.211.08:20:21.47#ibcon#flushed, iclass 30, count 0 2006.211.08:20:21.47#ibcon#about to write, iclass 30, count 0 2006.211.08:20:21.47#ibcon#wrote, iclass 30, count 0 2006.211.08:20:21.47#ibcon#about to read 3, iclass 30, count 0 2006.211.08:20:21.49#ibcon#read 3, iclass 30, count 0 2006.211.08:20:21.49#ibcon#about to read 4, iclass 30, count 0 2006.211.08:20:21.49#ibcon#read 4, iclass 30, count 0 2006.211.08:20:21.49#ibcon#about to read 5, iclass 30, count 0 2006.211.08:20:21.49#ibcon#read 5, iclass 30, count 0 2006.211.08:20:21.49#ibcon#about to read 6, iclass 30, count 0 2006.211.08:20:21.49#ibcon#read 6, iclass 30, count 0 2006.211.08:20:21.49#ibcon#end of sib2, iclass 30, count 0 2006.211.08:20:21.49#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:20:21.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:20:21.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:20:21.49#ibcon#*before write, iclass 30, count 0 2006.211.08:20:21.49#ibcon#enter sib2, iclass 30, count 0 2006.211.08:20:21.49#ibcon#flushed, iclass 30, count 0 2006.211.08:20:21.49#ibcon#about to write, iclass 30, count 0 2006.211.08:20:21.49#ibcon#wrote, iclass 30, count 0 2006.211.08:20:21.49#ibcon#about to read 3, iclass 30, count 0 2006.211.08:20:21.53#ibcon#read 3, iclass 30, count 0 2006.211.08:20:21.53#ibcon#about to read 4, iclass 30, count 0 2006.211.08:20:21.53#ibcon#read 4, iclass 30, count 0 2006.211.08:20:21.53#ibcon#about to read 5, iclass 30, count 0 2006.211.08:20:21.53#ibcon#read 5, iclass 30, count 0 2006.211.08:20:21.53#ibcon#about to read 6, iclass 30, count 0 2006.211.08:20:21.53#ibcon#read 6, iclass 30, count 0 2006.211.08:20:21.53#ibcon#end of sib2, iclass 30, count 0 2006.211.08:20:21.53#ibcon#*after write, iclass 30, count 0 2006.211.08:20:21.53#ibcon#*before return 0, iclass 30, count 0 2006.211.08:20:21.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:21.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:20:21.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:20:21.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:20:21.53$vc4f8/vb=5,3 2006.211.08:20:21.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:20:21.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:20:21.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:21.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:21.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:21.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:21.59#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:20:21.59#ibcon#first serial, iclass 32, count 2 2006.211.08:20:21.59#ibcon#enter sib2, iclass 32, count 2 2006.211.08:20:21.59#ibcon#flushed, iclass 32, count 2 2006.211.08:20:21.59#ibcon#about to write, iclass 32, count 2 2006.211.08:20:21.59#ibcon#wrote, iclass 32, count 2 2006.211.08:20:21.59#ibcon#about to read 3, iclass 32, count 2 2006.211.08:20:21.61#ibcon#read 3, iclass 32, count 2 2006.211.08:20:21.61#ibcon#about to read 4, iclass 32, count 2 2006.211.08:20:21.61#ibcon#read 4, iclass 32, count 2 2006.211.08:20:21.61#ibcon#about to read 5, iclass 32, count 2 2006.211.08:20:21.61#ibcon#read 5, iclass 32, count 2 2006.211.08:20:21.61#ibcon#about to read 6, iclass 32, count 2 2006.211.08:20:21.61#ibcon#read 6, iclass 32, count 2 2006.211.08:20:21.61#ibcon#end of sib2, iclass 32, count 2 2006.211.08:20:21.61#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:20:21.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:20:21.61#ibcon#[27=AT05-03\r\n] 2006.211.08:20:21.61#ibcon#*before write, iclass 32, count 2 2006.211.08:20:21.61#ibcon#enter sib2, iclass 32, count 2 2006.211.08:20:21.61#ibcon#flushed, iclass 32, count 2 2006.211.08:20:21.61#ibcon#about to write, iclass 32, count 2 2006.211.08:20:21.61#ibcon#wrote, iclass 32, count 2 2006.211.08:20:21.61#ibcon#about to read 3, iclass 32, count 2 2006.211.08:20:21.64#ibcon#read 3, iclass 32, count 2 2006.211.08:20:21.64#ibcon#about to read 4, iclass 32, count 2 2006.211.08:20:21.64#ibcon#read 4, iclass 32, count 2 2006.211.08:20:21.64#ibcon#about to read 5, iclass 32, count 2 2006.211.08:20:21.64#ibcon#read 5, iclass 32, count 2 2006.211.08:20:21.64#ibcon#about to read 6, iclass 32, count 2 2006.211.08:20:21.64#ibcon#read 6, iclass 32, count 2 2006.211.08:20:21.64#ibcon#end of sib2, iclass 32, count 2 2006.211.08:20:21.64#ibcon#*after write, iclass 32, count 2 2006.211.08:20:21.64#ibcon#*before return 0, iclass 32, count 2 2006.211.08:20:21.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:21.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:20:21.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:20:21.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:21.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:21.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:21.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:21.76#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:20:21.76#ibcon#first serial, iclass 32, count 0 2006.211.08:20:21.76#ibcon#enter sib2, iclass 32, count 0 2006.211.08:20:21.76#ibcon#flushed, iclass 32, count 0 2006.211.08:20:21.76#ibcon#about to write, iclass 32, count 0 2006.211.08:20:21.76#ibcon#wrote, iclass 32, count 0 2006.211.08:20:21.76#ibcon#about to read 3, iclass 32, count 0 2006.211.08:20:21.78#ibcon#read 3, iclass 32, count 0 2006.211.08:20:21.78#ibcon#about to read 4, iclass 32, count 0 2006.211.08:20:21.78#ibcon#read 4, iclass 32, count 0 2006.211.08:20:21.78#ibcon#about to read 5, iclass 32, count 0 2006.211.08:20:21.78#ibcon#read 5, iclass 32, count 0 2006.211.08:20:21.78#ibcon#about to read 6, iclass 32, count 0 2006.211.08:20:21.78#ibcon#read 6, iclass 32, count 0 2006.211.08:20:21.78#ibcon#end of sib2, iclass 32, count 0 2006.211.08:20:21.78#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:20:21.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:20:21.78#ibcon#[27=USB\r\n] 2006.211.08:20:21.78#ibcon#*before write, iclass 32, count 0 2006.211.08:20:21.78#ibcon#enter sib2, iclass 32, count 0 2006.211.08:20:21.78#ibcon#flushed, iclass 32, count 0 2006.211.08:20:21.78#ibcon#about to write, iclass 32, count 0 2006.211.08:20:21.78#ibcon#wrote, iclass 32, count 0 2006.211.08:20:21.78#ibcon#about to read 3, iclass 32, count 0 2006.211.08:20:21.81#ibcon#read 3, iclass 32, count 0 2006.211.08:20:21.81#ibcon#about to read 4, iclass 32, count 0 2006.211.08:20:21.81#ibcon#read 4, iclass 32, count 0 2006.211.08:20:21.81#ibcon#about to read 5, iclass 32, count 0 2006.211.08:20:21.81#ibcon#read 5, iclass 32, count 0 2006.211.08:20:21.81#ibcon#about to read 6, iclass 32, count 0 2006.211.08:20:21.81#ibcon#read 6, iclass 32, count 0 2006.211.08:20:21.81#ibcon#end of sib2, iclass 32, count 0 2006.211.08:20:21.81#ibcon#*after write, iclass 32, count 0 2006.211.08:20:21.81#ibcon#*before return 0, iclass 32, count 0 2006.211.08:20:21.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:21.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:20:21.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:20:21.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:20:21.81$vc4f8/vblo=6,752.99 2006.211.08:20:21.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:20:21.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:20:21.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:20:21.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:21.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:21.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:21.81#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:20:21.81#ibcon#first serial, iclass 34, count 0 2006.211.08:20:21.81#ibcon#enter sib2, iclass 34, count 0 2006.211.08:20:21.81#ibcon#flushed, iclass 34, count 0 2006.211.08:20:21.81#ibcon#about to write, iclass 34, count 0 2006.211.08:20:21.81#ibcon#wrote, iclass 34, count 0 2006.211.08:20:21.81#ibcon#about to read 3, iclass 34, count 0 2006.211.08:20:21.83#ibcon#read 3, iclass 34, count 0 2006.211.08:20:21.83#ibcon#about to read 4, iclass 34, count 0 2006.211.08:20:21.83#ibcon#read 4, iclass 34, count 0 2006.211.08:20:21.83#ibcon#about to read 5, iclass 34, count 0 2006.211.08:20:21.83#ibcon#read 5, iclass 34, count 0 2006.211.08:20:21.83#ibcon#about to read 6, iclass 34, count 0 2006.211.08:20:21.83#ibcon#read 6, iclass 34, count 0 2006.211.08:20:21.83#ibcon#end of sib2, iclass 34, count 0 2006.211.08:20:21.83#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:20:21.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:20:21.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:20:21.83#ibcon#*before write, iclass 34, count 0 2006.211.08:20:21.83#ibcon#enter sib2, iclass 34, count 0 2006.211.08:20:21.83#ibcon#flushed, iclass 34, count 0 2006.211.08:20:21.83#ibcon#about to write, iclass 34, count 0 2006.211.08:20:21.83#ibcon#wrote, iclass 34, count 0 2006.211.08:20:21.83#ibcon#about to read 3, iclass 34, count 0 2006.211.08:20:21.87#ibcon#read 3, iclass 34, count 0 2006.211.08:20:21.87#ibcon#about to read 4, iclass 34, count 0 2006.211.08:20:21.87#ibcon#read 4, iclass 34, count 0 2006.211.08:20:21.87#ibcon#about to read 5, iclass 34, count 0 2006.211.08:20:21.87#ibcon#read 5, iclass 34, count 0 2006.211.08:20:21.87#ibcon#about to read 6, iclass 34, count 0 2006.211.08:20:21.87#ibcon#read 6, iclass 34, count 0 2006.211.08:20:21.87#ibcon#end of sib2, iclass 34, count 0 2006.211.08:20:21.87#ibcon#*after write, iclass 34, count 0 2006.211.08:20:21.87#ibcon#*before return 0, iclass 34, count 0 2006.211.08:20:21.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:21.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:20:21.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:20:21.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:20:21.87$vc4f8/vb=6,3 2006.211.08:20:21.87#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:20:21.87#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:20:21.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:20:21.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:21.93#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:21.93#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:21.93#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:20:21.93#ibcon#first serial, iclass 36, count 2 2006.211.08:20:21.93#ibcon#enter sib2, iclass 36, count 2 2006.211.08:20:21.93#ibcon#flushed, iclass 36, count 2 2006.211.08:20:21.93#ibcon#about to write, iclass 36, count 2 2006.211.08:20:21.93#ibcon#wrote, iclass 36, count 2 2006.211.08:20:21.93#ibcon#about to read 3, iclass 36, count 2 2006.211.08:20:21.95#ibcon#read 3, iclass 36, count 2 2006.211.08:20:21.95#ibcon#about to read 4, iclass 36, count 2 2006.211.08:20:21.95#ibcon#read 4, iclass 36, count 2 2006.211.08:20:21.95#ibcon#about to read 5, iclass 36, count 2 2006.211.08:20:21.95#ibcon#read 5, iclass 36, count 2 2006.211.08:20:21.95#ibcon#about to read 6, iclass 36, count 2 2006.211.08:20:21.95#ibcon#read 6, iclass 36, count 2 2006.211.08:20:21.95#ibcon#end of sib2, iclass 36, count 2 2006.211.08:20:21.95#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:20:21.95#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:20:21.95#ibcon#[27=AT06-03\r\n] 2006.211.08:20:21.95#ibcon#*before write, iclass 36, count 2 2006.211.08:20:21.95#ibcon#enter sib2, iclass 36, count 2 2006.211.08:20:21.95#ibcon#flushed, iclass 36, count 2 2006.211.08:20:21.95#ibcon#about to write, iclass 36, count 2 2006.211.08:20:21.95#ibcon#wrote, iclass 36, count 2 2006.211.08:20:21.95#ibcon#about to read 3, iclass 36, count 2 2006.211.08:20:21.98#ibcon#read 3, iclass 36, count 2 2006.211.08:20:21.98#ibcon#about to read 4, iclass 36, count 2 2006.211.08:20:21.98#ibcon#read 4, iclass 36, count 2 2006.211.08:20:21.98#ibcon#about to read 5, iclass 36, count 2 2006.211.08:20:21.98#ibcon#read 5, iclass 36, count 2 2006.211.08:20:21.98#ibcon#about to read 6, iclass 36, count 2 2006.211.08:20:21.98#ibcon#read 6, iclass 36, count 2 2006.211.08:20:21.98#ibcon#end of sib2, iclass 36, count 2 2006.211.08:20:21.98#ibcon#*after write, iclass 36, count 2 2006.211.08:20:21.98#ibcon#*before return 0, iclass 36, count 2 2006.211.08:20:21.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:21.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:20:21.98#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:20:21.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:20:21.98#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:22.04#abcon#<5=/04 4.7 9.0 24.32 801010.1\r\n> 2006.211.08:20:22.06#abcon#{5=INTERFACE CLEAR} 2006.211.08:20:22.10#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:22.10#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:22.10#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:20:22.10#ibcon#first serial, iclass 36, count 0 2006.211.08:20:22.10#ibcon#enter sib2, iclass 36, count 0 2006.211.08:20:22.10#ibcon#flushed, iclass 36, count 0 2006.211.08:20:22.10#ibcon#about to write, iclass 36, count 0 2006.211.08:20:22.10#ibcon#wrote, iclass 36, count 0 2006.211.08:20:22.10#ibcon#about to read 3, iclass 36, count 0 2006.211.08:20:22.12#ibcon#read 3, iclass 36, count 0 2006.211.08:20:22.12#ibcon#about to read 4, iclass 36, count 0 2006.211.08:20:22.12#ibcon#read 4, iclass 36, count 0 2006.211.08:20:22.12#ibcon#about to read 5, iclass 36, count 0 2006.211.08:20:22.12#ibcon#read 5, iclass 36, count 0 2006.211.08:20:22.12#ibcon#about to read 6, iclass 36, count 0 2006.211.08:20:22.12#ibcon#read 6, iclass 36, count 0 2006.211.08:20:22.12#ibcon#end of sib2, iclass 36, count 0 2006.211.08:20:22.12#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:20:22.12#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:20:22.12#ibcon#[27=USB\r\n] 2006.211.08:20:22.12#ibcon#*before write, iclass 36, count 0 2006.211.08:20:22.12#ibcon#enter sib2, iclass 36, count 0 2006.211.08:20:22.12#ibcon#flushed, iclass 36, count 0 2006.211.08:20:22.12#ibcon#about to write, iclass 36, count 0 2006.211.08:20:22.12#ibcon#wrote, iclass 36, count 0 2006.211.08:20:22.12#ibcon#about to read 3, iclass 36, count 0 2006.211.08:20:22.12#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:20:22.15#ibcon#read 3, iclass 36, count 0 2006.211.08:20:22.15#ibcon#about to read 4, iclass 36, count 0 2006.211.08:20:22.15#ibcon#read 4, iclass 36, count 0 2006.211.08:20:22.15#ibcon#about to read 5, iclass 36, count 0 2006.211.08:20:22.15#ibcon#read 5, iclass 36, count 0 2006.211.08:20:22.15#ibcon#about to read 6, iclass 36, count 0 2006.211.08:20:22.15#ibcon#read 6, iclass 36, count 0 2006.211.08:20:22.15#ibcon#end of sib2, iclass 36, count 0 2006.211.08:20:22.15#ibcon#*after write, iclass 36, count 0 2006.211.08:20:22.15#ibcon#*before return 0, iclass 36, count 0 2006.211.08:20:22.15#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:22.15#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:20:22.15#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:20:22.15#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:20:22.15$vc4f8/vabw=wide 2006.211.08:20:22.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:20:22.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:20:22.15#ibcon#ireg 8 cls_cnt 0 2006.211.08:20:22.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:22.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:22.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:22.15#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:20:22.15#ibcon#first serial, iclass 4, count 0 2006.211.08:20:22.15#ibcon#enter sib2, iclass 4, count 0 2006.211.08:20:22.15#ibcon#flushed, iclass 4, count 0 2006.211.08:20:22.15#ibcon#about to write, iclass 4, count 0 2006.211.08:20:22.15#ibcon#wrote, iclass 4, count 0 2006.211.08:20:22.15#ibcon#about to read 3, iclass 4, count 0 2006.211.08:20:22.17#ibcon#read 3, iclass 4, count 0 2006.211.08:20:22.17#ibcon#about to read 4, iclass 4, count 0 2006.211.08:20:22.17#ibcon#read 4, iclass 4, count 0 2006.211.08:20:22.17#ibcon#about to read 5, iclass 4, count 0 2006.211.08:20:22.17#ibcon#read 5, iclass 4, count 0 2006.211.08:20:22.17#ibcon#about to read 6, iclass 4, count 0 2006.211.08:20:22.17#ibcon#read 6, iclass 4, count 0 2006.211.08:20:22.17#ibcon#end of sib2, iclass 4, count 0 2006.211.08:20:22.17#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:20:22.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:20:22.17#ibcon#[25=BW32\r\n] 2006.211.08:20:22.17#ibcon#*before write, iclass 4, count 0 2006.211.08:20:22.17#ibcon#enter sib2, iclass 4, count 0 2006.211.08:20:22.17#ibcon#flushed, iclass 4, count 0 2006.211.08:20:22.17#ibcon#about to write, iclass 4, count 0 2006.211.08:20:22.17#ibcon#wrote, iclass 4, count 0 2006.211.08:20:22.17#ibcon#about to read 3, iclass 4, count 0 2006.211.08:20:22.20#ibcon#read 3, iclass 4, count 0 2006.211.08:20:22.20#ibcon#about to read 4, iclass 4, count 0 2006.211.08:20:22.20#ibcon#read 4, iclass 4, count 0 2006.211.08:20:22.20#ibcon#about to read 5, iclass 4, count 0 2006.211.08:20:22.20#ibcon#read 5, iclass 4, count 0 2006.211.08:20:22.20#ibcon#about to read 6, iclass 4, count 0 2006.211.08:20:22.20#ibcon#read 6, iclass 4, count 0 2006.211.08:20:22.20#ibcon#end of sib2, iclass 4, count 0 2006.211.08:20:22.20#ibcon#*after write, iclass 4, count 0 2006.211.08:20:22.20#ibcon#*before return 0, iclass 4, count 0 2006.211.08:20:22.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:22.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:20:22.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:20:22.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:20:22.20$vc4f8/vbbw=wide 2006.211.08:20:22.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.211.08:20:22.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.211.08:20:22.20#ibcon#ireg 8 cls_cnt 0 2006.211.08:20:22.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:20:22.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:20:22.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:20:22.27#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:20:22.27#ibcon#first serial, iclass 6, count 0 2006.211.08:20:22.27#ibcon#enter sib2, iclass 6, count 0 2006.211.08:20:22.27#ibcon#flushed, iclass 6, count 0 2006.211.08:20:22.27#ibcon#about to write, iclass 6, count 0 2006.211.08:20:22.27#ibcon#wrote, iclass 6, count 0 2006.211.08:20:22.27#ibcon#about to read 3, iclass 6, count 0 2006.211.08:20:22.29#ibcon#read 3, iclass 6, count 0 2006.211.08:20:22.29#ibcon#about to read 4, iclass 6, count 0 2006.211.08:20:22.29#ibcon#read 4, iclass 6, count 0 2006.211.08:20:22.29#ibcon#about to read 5, iclass 6, count 0 2006.211.08:20:22.29#ibcon#read 5, iclass 6, count 0 2006.211.08:20:22.29#ibcon#about to read 6, iclass 6, count 0 2006.211.08:20:22.29#ibcon#read 6, iclass 6, count 0 2006.211.08:20:22.29#ibcon#end of sib2, iclass 6, count 0 2006.211.08:20:22.29#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:20:22.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:20:22.29#ibcon#[27=BW32\r\n] 2006.211.08:20:22.29#ibcon#*before write, iclass 6, count 0 2006.211.08:20:22.29#ibcon#enter sib2, iclass 6, count 0 2006.211.08:20:22.29#ibcon#flushed, iclass 6, count 0 2006.211.08:20:22.29#ibcon#about to write, iclass 6, count 0 2006.211.08:20:22.29#ibcon#wrote, iclass 6, count 0 2006.211.08:20:22.29#ibcon#about to read 3, iclass 6, count 0 2006.211.08:20:22.32#ibcon#read 3, iclass 6, count 0 2006.211.08:20:22.32#ibcon#about to read 4, iclass 6, count 0 2006.211.08:20:22.32#ibcon#read 4, iclass 6, count 0 2006.211.08:20:22.32#ibcon#about to read 5, iclass 6, count 0 2006.211.08:20:22.32#ibcon#read 5, iclass 6, count 0 2006.211.08:20:22.32#ibcon#about to read 6, iclass 6, count 0 2006.211.08:20:22.32#ibcon#read 6, iclass 6, count 0 2006.211.08:20:22.32#ibcon#end of sib2, iclass 6, count 0 2006.211.08:20:22.32#ibcon#*after write, iclass 6, count 0 2006.211.08:20:22.32#ibcon#*before return 0, iclass 6, count 0 2006.211.08:20:22.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:20:22.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.211.08:20:22.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:20:22.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:20:22.32$4f8m12a/ifd4f 2006.211.08:20:22.32$ifd4f/lo= 2006.211.08:20:22.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:20:22.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:20:22.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:20:22.32$ifd4f/patch= 2006.211.08:20:22.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:20:22.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:20:22.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:20:22.32$4f8m12a/"form=m,16.000,1:2 2006.211.08:20:22.32$4f8m12a/"tpicd 2006.211.08:20:22.32$4f8m12a/echo=off 2006.211.08:20:22.32$4f8m12a/xlog=off 2006.211.08:20:22.32:!2006.211.08:21:50 2006.211.08:20:33.13#trakl#Source acquired 2006.211.08:20:34.13#flagr#flagr/antenna,acquired 2006.211.08:21:50.00:preob 2006.211.08:21:50.13/onsource/TRACKING 2006.211.08:21:50.13:!2006.211.08:22:00 2006.211.08:22:00.00:data_valid=on 2006.211.08:22:00.00:midob 2006.211.08:22:01.13/onsource/TRACKING 2006.211.08:22:01.13/wx/24.28,1010.2,80 2006.211.08:22:01.30/cable/+6.4409E-03 2006.211.08:22:02.39/va/01,08,usb,yes,28,29 2006.211.08:22:02.39/va/02,07,usb,yes,28,29 2006.211.08:22:02.39/va/03,06,usb,yes,29,30 2006.211.08:22:02.39/va/04,07,usb,yes,29,31 2006.211.08:22:02.39/va/05,07,usb,yes,31,33 2006.211.08:22:02.39/va/06,06,usb,yes,30,30 2006.211.08:22:02.39/va/07,06,usb,yes,31,30 2006.211.08:22:02.39/va/08,07,usb,yes,29,29 2006.211.08:22:02.62/valo/01,532.99,yes,locked 2006.211.08:22:02.62/valo/02,572.99,yes,locked 2006.211.08:22:02.62/valo/03,672.99,yes,locked 2006.211.08:22:02.62/valo/04,832.99,yes,locked 2006.211.08:22:02.62/valo/05,652.99,yes,locked 2006.211.08:22:02.62/valo/06,772.99,yes,locked 2006.211.08:22:02.62/valo/07,832.99,yes,locked 2006.211.08:22:02.62/valo/08,852.99,yes,locked 2006.211.08:22:03.71/vb/01,04,usb,yes,28,27 2006.211.08:22:03.71/vb/02,04,usb,yes,30,31 2006.211.08:22:03.71/vb/03,03,usb,yes,33,37 2006.211.08:22:03.71/vb/04,03,usb,yes,33,34 2006.211.08:22:03.71/vb/05,03,usb,yes,32,36 2006.211.08:22:03.71/vb/06,03,usb,yes,33,36 2006.211.08:22:03.71/vb/07,04,usb,yes,28,28 2006.211.08:22:03.71/vb/08,03,usb,yes,33,36 2006.211.08:22:03.95/vblo/01,632.99,yes,locked 2006.211.08:22:03.95/vblo/02,640.99,yes,locked 2006.211.08:22:03.95/vblo/03,656.99,yes,locked 2006.211.08:22:03.95/vblo/04,712.99,yes,locked 2006.211.08:22:03.95/vblo/05,744.99,yes,locked 2006.211.08:22:03.95/vblo/06,752.99,yes,locked 2006.211.08:22:03.95/vblo/07,734.99,yes,locked 2006.211.08:22:03.95/vblo/08,744.99,yes,locked 2006.211.08:22:04.10/vabw/8 2006.211.08:22:04.25/vbbw/8 2006.211.08:22:04.35/xfe/off,on,11.7 2006.211.08:22:04.73/ifatt/23,28,28,28 2006.211.08:22:05.07/fmout-gps/S +4.41E-07 2006.211.08:22:05.11:!2006.211.08:23:00 2006.211.08:22:21.14#trakl#Off source 2006.211.08:22:21.14?ERROR st -7 Antenna off-source! 2006.211.08:22:21.14#trakl#az 286.189 el 57.740 azerr*cos(el) -0.0007 elerr -0.0182 2006.211.08:22:23.14#flagr#flagr/antenna,off-source 2006.211.08:22:28.14#trakl#Source re-acquired 2006.211.08:22:29.14#flagr#flagr/antenna,re-acquired 2006.211.08:23:00.01:data_valid=off 2006.211.08:23:00.01:postob 2006.211.08:23:00.11/cable/+6.4410E-03 2006.211.08:23:00.11/wx/24.24,1010.2,81 2006.211.08:23:01.07/fmout-gps/S +4.41E-07 2006.211.08:23:01.07:scan_name=211-0825,k06211,60 2006.211.08:23:01.07:source=1417+385,141946.61,382148.5,2000.0,cw 2006.211.08:23:01.14#flagr#flagr/antenna,new-source 2006.211.08:23:02.14:checkk5 2006.211.08:23:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:23:02.81/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:23:03.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:23:03.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:23:03.84/chk_obsdata//k5ts1/T2110822??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:23:04.18/chk_obsdata//k5ts2/T2110822??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:23:04.51/chk_obsdata//k5ts3/T2110822??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:23:04.84/chk_obsdata//k5ts4/T2110822??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.211.08:23:05.50/k5log//k5ts1_log_newline 2006.211.08:23:06.16/k5log//k5ts2_log_newline 2006.211.08:23:06.81/k5log//k5ts3_log_newline 2006.211.08:23:07.47/k5log//k5ts4_log_newline 2006.211.08:23:07.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:23:07.50:4f8m12a=3 2006.211.08:23:07.50$4f8m12a/echo=on 2006.211.08:23:07.50$4f8m12a/pcalon 2006.211.08:23:07.50$pcalon/"no phase cal control is implemented here 2006.211.08:23:07.50$4f8m12a/"tpicd=stop 2006.211.08:23:07.50$4f8m12a/vc4f8 2006.211.08:23:07.50$vc4f8/valo=1,532.99 2006.211.08:23:07.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:23:07.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:23:07.50#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:07.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:07.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:07.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:07.50#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:23:07.50#ibcon#first serial, iclass 3, count 0 2006.211.08:23:07.50#ibcon#enter sib2, iclass 3, count 0 2006.211.08:23:07.50#ibcon#flushed, iclass 3, count 0 2006.211.08:23:07.50#ibcon#about to write, iclass 3, count 0 2006.211.08:23:07.50#ibcon#wrote, iclass 3, count 0 2006.211.08:23:07.50#ibcon#about to read 3, iclass 3, count 0 2006.211.08:23:07.52#ibcon#read 3, iclass 3, count 0 2006.211.08:23:07.52#ibcon#about to read 4, iclass 3, count 0 2006.211.08:23:07.52#ibcon#read 4, iclass 3, count 0 2006.211.08:23:07.52#ibcon#about to read 5, iclass 3, count 0 2006.211.08:23:07.52#ibcon#read 5, iclass 3, count 0 2006.211.08:23:07.52#ibcon#about to read 6, iclass 3, count 0 2006.211.08:23:07.52#ibcon#read 6, iclass 3, count 0 2006.211.08:23:07.52#ibcon#end of sib2, iclass 3, count 0 2006.211.08:23:07.52#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:23:07.52#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:23:07.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:23:07.52#ibcon#*before write, iclass 3, count 0 2006.211.08:23:07.52#ibcon#enter sib2, iclass 3, count 0 2006.211.08:23:07.52#ibcon#flushed, iclass 3, count 0 2006.211.08:23:07.52#ibcon#about to write, iclass 3, count 0 2006.211.08:23:07.52#ibcon#wrote, iclass 3, count 0 2006.211.08:23:07.52#ibcon#about to read 3, iclass 3, count 0 2006.211.08:23:07.57#ibcon#read 3, iclass 3, count 0 2006.211.08:23:07.57#ibcon#about to read 4, iclass 3, count 0 2006.211.08:23:07.57#ibcon#read 4, iclass 3, count 0 2006.211.08:23:07.57#ibcon#about to read 5, iclass 3, count 0 2006.211.08:23:07.57#ibcon#read 5, iclass 3, count 0 2006.211.08:23:07.57#ibcon#about to read 6, iclass 3, count 0 2006.211.08:23:07.57#ibcon#read 6, iclass 3, count 0 2006.211.08:23:07.57#ibcon#end of sib2, iclass 3, count 0 2006.211.08:23:07.57#ibcon#*after write, iclass 3, count 0 2006.211.08:23:07.57#ibcon#*before return 0, iclass 3, count 0 2006.211.08:23:07.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:07.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:07.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:23:07.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:23:07.57$vc4f8/va=1,8 2006.211.08:23:07.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:23:07.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:23:07.57#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:07.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:07.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:07.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:07.57#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:23:07.57#ibcon#first serial, iclass 5, count 2 2006.211.08:23:07.57#ibcon#enter sib2, iclass 5, count 2 2006.211.08:23:07.57#ibcon#flushed, iclass 5, count 2 2006.211.08:23:07.57#ibcon#about to write, iclass 5, count 2 2006.211.08:23:07.57#ibcon#wrote, iclass 5, count 2 2006.211.08:23:07.57#ibcon#about to read 3, iclass 5, count 2 2006.211.08:23:07.59#ibcon#read 3, iclass 5, count 2 2006.211.08:23:07.59#ibcon#about to read 4, iclass 5, count 2 2006.211.08:23:07.59#ibcon#read 4, iclass 5, count 2 2006.211.08:23:07.59#ibcon#about to read 5, iclass 5, count 2 2006.211.08:23:07.59#ibcon#read 5, iclass 5, count 2 2006.211.08:23:07.59#ibcon#about to read 6, iclass 5, count 2 2006.211.08:23:07.59#ibcon#read 6, iclass 5, count 2 2006.211.08:23:07.59#ibcon#end of sib2, iclass 5, count 2 2006.211.08:23:07.59#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:23:07.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:23:07.59#ibcon#[25=AT01-08\r\n] 2006.211.08:23:07.59#ibcon#*before write, iclass 5, count 2 2006.211.08:23:07.59#ibcon#enter sib2, iclass 5, count 2 2006.211.08:23:07.59#ibcon#flushed, iclass 5, count 2 2006.211.08:23:07.59#ibcon#about to write, iclass 5, count 2 2006.211.08:23:07.59#ibcon#wrote, iclass 5, count 2 2006.211.08:23:07.59#ibcon#about to read 3, iclass 5, count 2 2006.211.08:23:07.62#ibcon#read 3, iclass 5, count 2 2006.211.08:23:07.62#ibcon#about to read 4, iclass 5, count 2 2006.211.08:23:07.62#ibcon#read 4, iclass 5, count 2 2006.211.08:23:07.62#ibcon#about to read 5, iclass 5, count 2 2006.211.08:23:07.62#ibcon#read 5, iclass 5, count 2 2006.211.08:23:07.62#ibcon#about to read 6, iclass 5, count 2 2006.211.08:23:07.62#ibcon#read 6, iclass 5, count 2 2006.211.08:23:07.62#ibcon#end of sib2, iclass 5, count 2 2006.211.08:23:07.62#ibcon#*after write, iclass 5, count 2 2006.211.08:23:07.62#ibcon#*before return 0, iclass 5, count 2 2006.211.08:23:07.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:07.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:07.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:23:07.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:07.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:07.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:07.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:07.74#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:23:07.74#ibcon#first serial, iclass 5, count 0 2006.211.08:23:07.74#ibcon#enter sib2, iclass 5, count 0 2006.211.08:23:07.74#ibcon#flushed, iclass 5, count 0 2006.211.08:23:07.74#ibcon#about to write, iclass 5, count 0 2006.211.08:23:07.74#ibcon#wrote, iclass 5, count 0 2006.211.08:23:07.74#ibcon#about to read 3, iclass 5, count 0 2006.211.08:23:07.76#ibcon#read 3, iclass 5, count 0 2006.211.08:23:07.76#ibcon#about to read 4, iclass 5, count 0 2006.211.08:23:07.76#ibcon#read 4, iclass 5, count 0 2006.211.08:23:07.76#ibcon#about to read 5, iclass 5, count 0 2006.211.08:23:07.76#ibcon#read 5, iclass 5, count 0 2006.211.08:23:07.76#ibcon#about to read 6, iclass 5, count 0 2006.211.08:23:07.76#ibcon#read 6, iclass 5, count 0 2006.211.08:23:07.76#ibcon#end of sib2, iclass 5, count 0 2006.211.08:23:07.76#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:23:07.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:23:07.76#ibcon#[25=USB\r\n] 2006.211.08:23:07.76#ibcon#*before write, iclass 5, count 0 2006.211.08:23:07.76#ibcon#enter sib2, iclass 5, count 0 2006.211.08:23:07.76#ibcon#flushed, iclass 5, count 0 2006.211.08:23:07.76#ibcon#about to write, iclass 5, count 0 2006.211.08:23:07.76#ibcon#wrote, iclass 5, count 0 2006.211.08:23:07.76#ibcon#about to read 3, iclass 5, count 0 2006.211.08:23:07.79#ibcon#read 3, iclass 5, count 0 2006.211.08:23:07.79#ibcon#about to read 4, iclass 5, count 0 2006.211.08:23:07.79#ibcon#read 4, iclass 5, count 0 2006.211.08:23:07.79#ibcon#about to read 5, iclass 5, count 0 2006.211.08:23:07.79#ibcon#read 5, iclass 5, count 0 2006.211.08:23:07.79#ibcon#about to read 6, iclass 5, count 0 2006.211.08:23:07.79#ibcon#read 6, iclass 5, count 0 2006.211.08:23:07.79#ibcon#end of sib2, iclass 5, count 0 2006.211.08:23:07.79#ibcon#*after write, iclass 5, count 0 2006.211.08:23:07.79#ibcon#*before return 0, iclass 5, count 0 2006.211.08:23:07.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:07.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:07.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:23:07.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:23:07.79$vc4f8/valo=2,572.99 2006.211.08:23:07.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:23:07.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:23:07.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:07.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:07.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:07.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:07.79#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:23:07.79#ibcon#first serial, iclass 7, count 0 2006.211.08:23:07.79#ibcon#enter sib2, iclass 7, count 0 2006.211.08:23:07.79#ibcon#flushed, iclass 7, count 0 2006.211.08:23:07.79#ibcon#about to write, iclass 7, count 0 2006.211.08:23:07.79#ibcon#wrote, iclass 7, count 0 2006.211.08:23:07.79#ibcon#about to read 3, iclass 7, count 0 2006.211.08:23:07.81#ibcon#read 3, iclass 7, count 0 2006.211.08:23:07.81#ibcon#about to read 4, iclass 7, count 0 2006.211.08:23:07.81#ibcon#read 4, iclass 7, count 0 2006.211.08:23:07.81#ibcon#about to read 5, iclass 7, count 0 2006.211.08:23:07.81#ibcon#read 5, iclass 7, count 0 2006.211.08:23:07.81#ibcon#about to read 6, iclass 7, count 0 2006.211.08:23:07.81#ibcon#read 6, iclass 7, count 0 2006.211.08:23:07.81#ibcon#end of sib2, iclass 7, count 0 2006.211.08:23:07.81#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:23:07.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:23:07.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:23:07.81#ibcon#*before write, iclass 7, count 0 2006.211.08:23:07.81#ibcon#enter sib2, iclass 7, count 0 2006.211.08:23:07.81#ibcon#flushed, iclass 7, count 0 2006.211.08:23:07.81#ibcon#about to write, iclass 7, count 0 2006.211.08:23:07.81#ibcon#wrote, iclass 7, count 0 2006.211.08:23:07.81#ibcon#about to read 3, iclass 7, count 0 2006.211.08:23:07.85#ibcon#read 3, iclass 7, count 0 2006.211.08:23:07.85#ibcon#about to read 4, iclass 7, count 0 2006.211.08:23:07.85#ibcon#read 4, iclass 7, count 0 2006.211.08:23:07.85#ibcon#about to read 5, iclass 7, count 0 2006.211.08:23:07.85#ibcon#read 5, iclass 7, count 0 2006.211.08:23:07.85#ibcon#about to read 6, iclass 7, count 0 2006.211.08:23:07.85#ibcon#read 6, iclass 7, count 0 2006.211.08:23:07.85#ibcon#end of sib2, iclass 7, count 0 2006.211.08:23:07.85#ibcon#*after write, iclass 7, count 0 2006.211.08:23:07.85#ibcon#*before return 0, iclass 7, count 0 2006.211.08:23:07.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:07.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:07.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:23:07.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:23:07.85$vc4f8/va=2,7 2006.211.08:23:07.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:23:07.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:23:07.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:07.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:07.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:07.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:07.91#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:23:07.91#ibcon#first serial, iclass 11, count 2 2006.211.08:23:07.91#ibcon#enter sib2, iclass 11, count 2 2006.211.08:23:07.91#ibcon#flushed, iclass 11, count 2 2006.211.08:23:07.91#ibcon#about to write, iclass 11, count 2 2006.211.08:23:07.91#ibcon#wrote, iclass 11, count 2 2006.211.08:23:07.91#ibcon#about to read 3, iclass 11, count 2 2006.211.08:23:07.93#ibcon#read 3, iclass 11, count 2 2006.211.08:23:07.93#ibcon#about to read 4, iclass 11, count 2 2006.211.08:23:07.93#ibcon#read 4, iclass 11, count 2 2006.211.08:23:07.93#ibcon#about to read 5, iclass 11, count 2 2006.211.08:23:07.93#ibcon#read 5, iclass 11, count 2 2006.211.08:23:07.93#ibcon#about to read 6, iclass 11, count 2 2006.211.08:23:07.93#ibcon#read 6, iclass 11, count 2 2006.211.08:23:07.93#ibcon#end of sib2, iclass 11, count 2 2006.211.08:23:07.93#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:23:07.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:23:07.93#ibcon#[25=AT02-07\r\n] 2006.211.08:23:07.93#ibcon#*before write, iclass 11, count 2 2006.211.08:23:07.93#ibcon#enter sib2, iclass 11, count 2 2006.211.08:23:07.93#ibcon#flushed, iclass 11, count 2 2006.211.08:23:07.93#ibcon#about to write, iclass 11, count 2 2006.211.08:23:07.93#ibcon#wrote, iclass 11, count 2 2006.211.08:23:07.93#ibcon#about to read 3, iclass 11, count 2 2006.211.08:23:07.96#ibcon#read 3, iclass 11, count 2 2006.211.08:23:07.96#ibcon#about to read 4, iclass 11, count 2 2006.211.08:23:07.96#ibcon#read 4, iclass 11, count 2 2006.211.08:23:07.96#ibcon#about to read 5, iclass 11, count 2 2006.211.08:23:07.96#ibcon#read 5, iclass 11, count 2 2006.211.08:23:07.96#ibcon#about to read 6, iclass 11, count 2 2006.211.08:23:07.96#ibcon#read 6, iclass 11, count 2 2006.211.08:23:07.96#ibcon#end of sib2, iclass 11, count 2 2006.211.08:23:07.96#ibcon#*after write, iclass 11, count 2 2006.211.08:23:07.96#ibcon#*before return 0, iclass 11, count 2 2006.211.08:23:07.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:07.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:07.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:23:07.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:07.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:08.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:08.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:08.08#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:23:08.08#ibcon#first serial, iclass 11, count 0 2006.211.08:23:08.08#ibcon#enter sib2, iclass 11, count 0 2006.211.08:23:08.08#ibcon#flushed, iclass 11, count 0 2006.211.08:23:08.08#ibcon#about to write, iclass 11, count 0 2006.211.08:23:08.08#ibcon#wrote, iclass 11, count 0 2006.211.08:23:08.08#ibcon#about to read 3, iclass 11, count 0 2006.211.08:23:08.10#ibcon#read 3, iclass 11, count 0 2006.211.08:23:08.10#ibcon#about to read 4, iclass 11, count 0 2006.211.08:23:08.10#ibcon#read 4, iclass 11, count 0 2006.211.08:23:08.10#ibcon#about to read 5, iclass 11, count 0 2006.211.08:23:08.10#ibcon#read 5, iclass 11, count 0 2006.211.08:23:08.10#ibcon#about to read 6, iclass 11, count 0 2006.211.08:23:08.10#ibcon#read 6, iclass 11, count 0 2006.211.08:23:08.10#ibcon#end of sib2, iclass 11, count 0 2006.211.08:23:08.10#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:23:08.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:23:08.10#ibcon#[25=USB\r\n] 2006.211.08:23:08.10#ibcon#*before write, iclass 11, count 0 2006.211.08:23:08.10#ibcon#enter sib2, iclass 11, count 0 2006.211.08:23:08.10#ibcon#flushed, iclass 11, count 0 2006.211.08:23:08.10#ibcon#about to write, iclass 11, count 0 2006.211.08:23:08.10#ibcon#wrote, iclass 11, count 0 2006.211.08:23:08.10#ibcon#about to read 3, iclass 11, count 0 2006.211.08:23:08.13#ibcon#read 3, iclass 11, count 0 2006.211.08:23:08.13#ibcon#about to read 4, iclass 11, count 0 2006.211.08:23:08.13#ibcon#read 4, iclass 11, count 0 2006.211.08:23:08.13#ibcon#about to read 5, iclass 11, count 0 2006.211.08:23:08.13#ibcon#read 5, iclass 11, count 0 2006.211.08:23:08.13#ibcon#about to read 6, iclass 11, count 0 2006.211.08:23:08.13#ibcon#read 6, iclass 11, count 0 2006.211.08:23:08.13#ibcon#end of sib2, iclass 11, count 0 2006.211.08:23:08.13#ibcon#*after write, iclass 11, count 0 2006.211.08:23:08.13#ibcon#*before return 0, iclass 11, count 0 2006.211.08:23:08.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:08.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:08.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:23:08.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:23:08.13$vc4f8/valo=3,672.99 2006.211.08:23:08.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:23:08.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:23:08.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:08.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:08.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:08.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:08.13#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:23:08.13#ibcon#first serial, iclass 13, count 0 2006.211.08:23:08.13#ibcon#enter sib2, iclass 13, count 0 2006.211.08:23:08.13#ibcon#flushed, iclass 13, count 0 2006.211.08:23:08.13#ibcon#about to write, iclass 13, count 0 2006.211.08:23:08.13#ibcon#wrote, iclass 13, count 0 2006.211.08:23:08.13#ibcon#about to read 3, iclass 13, count 0 2006.211.08:23:08.15#ibcon#read 3, iclass 13, count 0 2006.211.08:23:08.15#ibcon#about to read 4, iclass 13, count 0 2006.211.08:23:08.15#ibcon#read 4, iclass 13, count 0 2006.211.08:23:08.15#ibcon#about to read 5, iclass 13, count 0 2006.211.08:23:08.15#ibcon#read 5, iclass 13, count 0 2006.211.08:23:08.15#ibcon#about to read 6, iclass 13, count 0 2006.211.08:23:08.15#ibcon#read 6, iclass 13, count 0 2006.211.08:23:08.15#ibcon#end of sib2, iclass 13, count 0 2006.211.08:23:08.15#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:23:08.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:23:08.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:23:08.15#ibcon#*before write, iclass 13, count 0 2006.211.08:23:08.15#ibcon#enter sib2, iclass 13, count 0 2006.211.08:23:08.15#ibcon#flushed, iclass 13, count 0 2006.211.08:23:08.15#ibcon#about to write, iclass 13, count 0 2006.211.08:23:08.15#ibcon#wrote, iclass 13, count 0 2006.211.08:23:08.15#ibcon#about to read 3, iclass 13, count 0 2006.211.08:23:08.19#ibcon#read 3, iclass 13, count 0 2006.211.08:23:08.19#ibcon#about to read 4, iclass 13, count 0 2006.211.08:23:08.19#ibcon#read 4, iclass 13, count 0 2006.211.08:23:08.19#ibcon#about to read 5, iclass 13, count 0 2006.211.08:23:08.19#ibcon#read 5, iclass 13, count 0 2006.211.08:23:08.19#ibcon#about to read 6, iclass 13, count 0 2006.211.08:23:08.19#ibcon#read 6, iclass 13, count 0 2006.211.08:23:08.19#ibcon#end of sib2, iclass 13, count 0 2006.211.08:23:08.19#ibcon#*after write, iclass 13, count 0 2006.211.08:23:08.19#ibcon#*before return 0, iclass 13, count 0 2006.211.08:23:08.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:08.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:08.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:23:08.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:23:08.19$vc4f8/va=3,6 2006.211.08:23:08.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:23:08.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:23:08.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:08.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:08.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:08.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:08.25#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:23:08.25#ibcon#first serial, iclass 15, count 2 2006.211.08:23:08.25#ibcon#enter sib2, iclass 15, count 2 2006.211.08:23:08.25#ibcon#flushed, iclass 15, count 2 2006.211.08:23:08.25#ibcon#about to write, iclass 15, count 2 2006.211.08:23:08.25#ibcon#wrote, iclass 15, count 2 2006.211.08:23:08.25#ibcon#about to read 3, iclass 15, count 2 2006.211.08:23:08.27#ibcon#read 3, iclass 15, count 2 2006.211.08:23:08.27#ibcon#about to read 4, iclass 15, count 2 2006.211.08:23:08.27#ibcon#read 4, iclass 15, count 2 2006.211.08:23:08.27#ibcon#about to read 5, iclass 15, count 2 2006.211.08:23:08.27#ibcon#read 5, iclass 15, count 2 2006.211.08:23:08.27#ibcon#about to read 6, iclass 15, count 2 2006.211.08:23:08.27#ibcon#read 6, iclass 15, count 2 2006.211.08:23:08.27#ibcon#end of sib2, iclass 15, count 2 2006.211.08:23:08.27#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:23:08.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:23:08.27#ibcon#[25=AT03-06\r\n] 2006.211.08:23:08.27#ibcon#*before write, iclass 15, count 2 2006.211.08:23:08.27#ibcon#enter sib2, iclass 15, count 2 2006.211.08:23:08.27#ibcon#flushed, iclass 15, count 2 2006.211.08:23:08.27#ibcon#about to write, iclass 15, count 2 2006.211.08:23:08.27#ibcon#wrote, iclass 15, count 2 2006.211.08:23:08.27#ibcon#about to read 3, iclass 15, count 2 2006.211.08:23:08.30#ibcon#read 3, iclass 15, count 2 2006.211.08:23:08.30#ibcon#about to read 4, iclass 15, count 2 2006.211.08:23:08.30#ibcon#read 4, iclass 15, count 2 2006.211.08:23:08.30#ibcon#about to read 5, iclass 15, count 2 2006.211.08:23:08.30#ibcon#read 5, iclass 15, count 2 2006.211.08:23:08.30#ibcon#about to read 6, iclass 15, count 2 2006.211.08:23:08.30#ibcon#read 6, iclass 15, count 2 2006.211.08:23:08.30#ibcon#end of sib2, iclass 15, count 2 2006.211.08:23:08.30#ibcon#*after write, iclass 15, count 2 2006.211.08:23:08.30#ibcon#*before return 0, iclass 15, count 2 2006.211.08:23:08.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:08.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:08.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:23:08.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:08.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:08.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:08.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:08.42#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:23:08.42#ibcon#first serial, iclass 15, count 0 2006.211.08:23:08.42#ibcon#enter sib2, iclass 15, count 0 2006.211.08:23:08.42#ibcon#flushed, iclass 15, count 0 2006.211.08:23:08.42#ibcon#about to write, iclass 15, count 0 2006.211.08:23:08.42#ibcon#wrote, iclass 15, count 0 2006.211.08:23:08.42#ibcon#about to read 3, iclass 15, count 0 2006.211.08:23:08.44#ibcon#read 3, iclass 15, count 0 2006.211.08:23:08.44#ibcon#about to read 4, iclass 15, count 0 2006.211.08:23:08.44#ibcon#read 4, iclass 15, count 0 2006.211.08:23:08.44#ibcon#about to read 5, iclass 15, count 0 2006.211.08:23:08.44#ibcon#read 5, iclass 15, count 0 2006.211.08:23:08.44#ibcon#about to read 6, iclass 15, count 0 2006.211.08:23:08.44#ibcon#read 6, iclass 15, count 0 2006.211.08:23:08.44#ibcon#end of sib2, iclass 15, count 0 2006.211.08:23:08.44#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:23:08.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:23:08.44#ibcon#[25=USB\r\n] 2006.211.08:23:08.44#ibcon#*before write, iclass 15, count 0 2006.211.08:23:08.44#ibcon#enter sib2, iclass 15, count 0 2006.211.08:23:08.44#ibcon#flushed, iclass 15, count 0 2006.211.08:23:08.44#ibcon#about to write, iclass 15, count 0 2006.211.08:23:08.44#ibcon#wrote, iclass 15, count 0 2006.211.08:23:08.44#ibcon#about to read 3, iclass 15, count 0 2006.211.08:23:08.47#ibcon#read 3, iclass 15, count 0 2006.211.08:23:08.47#ibcon#about to read 4, iclass 15, count 0 2006.211.08:23:08.47#ibcon#read 4, iclass 15, count 0 2006.211.08:23:08.47#ibcon#about to read 5, iclass 15, count 0 2006.211.08:23:08.47#ibcon#read 5, iclass 15, count 0 2006.211.08:23:08.47#ibcon#about to read 6, iclass 15, count 0 2006.211.08:23:08.47#ibcon#read 6, iclass 15, count 0 2006.211.08:23:08.47#ibcon#end of sib2, iclass 15, count 0 2006.211.08:23:08.47#ibcon#*after write, iclass 15, count 0 2006.211.08:23:08.47#ibcon#*before return 0, iclass 15, count 0 2006.211.08:23:08.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:08.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:08.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:23:08.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:23:08.47$vc4f8/valo=4,832.99 2006.211.08:23:08.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:23:08.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:23:08.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:08.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:08.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:08.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:08.47#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:23:08.47#ibcon#first serial, iclass 17, count 0 2006.211.08:23:08.47#ibcon#enter sib2, iclass 17, count 0 2006.211.08:23:08.47#ibcon#flushed, iclass 17, count 0 2006.211.08:23:08.47#ibcon#about to write, iclass 17, count 0 2006.211.08:23:08.47#ibcon#wrote, iclass 17, count 0 2006.211.08:23:08.47#ibcon#about to read 3, iclass 17, count 0 2006.211.08:23:08.49#ibcon#read 3, iclass 17, count 0 2006.211.08:23:08.49#ibcon#about to read 4, iclass 17, count 0 2006.211.08:23:08.49#ibcon#read 4, iclass 17, count 0 2006.211.08:23:08.49#ibcon#about to read 5, iclass 17, count 0 2006.211.08:23:08.49#ibcon#read 5, iclass 17, count 0 2006.211.08:23:08.49#ibcon#about to read 6, iclass 17, count 0 2006.211.08:23:08.49#ibcon#read 6, iclass 17, count 0 2006.211.08:23:08.49#ibcon#end of sib2, iclass 17, count 0 2006.211.08:23:08.49#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:23:08.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:23:08.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:23:08.49#ibcon#*before write, iclass 17, count 0 2006.211.08:23:08.49#ibcon#enter sib2, iclass 17, count 0 2006.211.08:23:08.49#ibcon#flushed, iclass 17, count 0 2006.211.08:23:08.49#ibcon#about to write, iclass 17, count 0 2006.211.08:23:08.49#ibcon#wrote, iclass 17, count 0 2006.211.08:23:08.49#ibcon#about to read 3, iclass 17, count 0 2006.211.08:23:08.53#ibcon#read 3, iclass 17, count 0 2006.211.08:23:08.53#ibcon#about to read 4, iclass 17, count 0 2006.211.08:23:08.53#ibcon#read 4, iclass 17, count 0 2006.211.08:23:08.53#ibcon#about to read 5, iclass 17, count 0 2006.211.08:23:08.53#ibcon#read 5, iclass 17, count 0 2006.211.08:23:08.53#ibcon#about to read 6, iclass 17, count 0 2006.211.08:23:08.53#ibcon#read 6, iclass 17, count 0 2006.211.08:23:08.53#ibcon#end of sib2, iclass 17, count 0 2006.211.08:23:08.53#ibcon#*after write, iclass 17, count 0 2006.211.08:23:08.53#ibcon#*before return 0, iclass 17, count 0 2006.211.08:23:08.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:08.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:08.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:23:08.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:23:08.53$vc4f8/va=4,7 2006.211.08:23:08.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:23:08.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:23:08.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:08.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:08.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:08.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:08.59#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:23:08.59#ibcon#first serial, iclass 19, count 2 2006.211.08:23:08.59#ibcon#enter sib2, iclass 19, count 2 2006.211.08:23:08.59#ibcon#flushed, iclass 19, count 2 2006.211.08:23:08.59#ibcon#about to write, iclass 19, count 2 2006.211.08:23:08.59#ibcon#wrote, iclass 19, count 2 2006.211.08:23:08.59#ibcon#about to read 3, iclass 19, count 2 2006.211.08:23:08.61#ibcon#read 3, iclass 19, count 2 2006.211.08:23:08.61#ibcon#about to read 4, iclass 19, count 2 2006.211.08:23:08.61#ibcon#read 4, iclass 19, count 2 2006.211.08:23:08.61#ibcon#about to read 5, iclass 19, count 2 2006.211.08:23:08.61#ibcon#read 5, iclass 19, count 2 2006.211.08:23:08.61#ibcon#about to read 6, iclass 19, count 2 2006.211.08:23:08.61#ibcon#read 6, iclass 19, count 2 2006.211.08:23:08.61#ibcon#end of sib2, iclass 19, count 2 2006.211.08:23:08.61#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:23:08.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:23:08.61#ibcon#[25=AT04-07\r\n] 2006.211.08:23:08.61#ibcon#*before write, iclass 19, count 2 2006.211.08:23:08.61#ibcon#enter sib2, iclass 19, count 2 2006.211.08:23:08.61#ibcon#flushed, iclass 19, count 2 2006.211.08:23:08.61#ibcon#about to write, iclass 19, count 2 2006.211.08:23:08.61#ibcon#wrote, iclass 19, count 2 2006.211.08:23:08.61#ibcon#about to read 3, iclass 19, count 2 2006.211.08:23:08.64#ibcon#read 3, iclass 19, count 2 2006.211.08:23:08.64#ibcon#about to read 4, iclass 19, count 2 2006.211.08:23:08.64#ibcon#read 4, iclass 19, count 2 2006.211.08:23:08.64#ibcon#about to read 5, iclass 19, count 2 2006.211.08:23:08.64#ibcon#read 5, iclass 19, count 2 2006.211.08:23:08.64#ibcon#about to read 6, iclass 19, count 2 2006.211.08:23:08.64#ibcon#read 6, iclass 19, count 2 2006.211.08:23:08.64#ibcon#end of sib2, iclass 19, count 2 2006.211.08:23:08.64#ibcon#*after write, iclass 19, count 2 2006.211.08:23:08.64#ibcon#*before return 0, iclass 19, count 2 2006.211.08:23:08.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:08.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:08.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:23:08.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:08.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:08.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:08.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:08.76#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:23:08.76#ibcon#first serial, iclass 19, count 0 2006.211.08:23:08.76#ibcon#enter sib2, iclass 19, count 0 2006.211.08:23:08.76#ibcon#flushed, iclass 19, count 0 2006.211.08:23:08.76#ibcon#about to write, iclass 19, count 0 2006.211.08:23:08.76#ibcon#wrote, iclass 19, count 0 2006.211.08:23:08.76#ibcon#about to read 3, iclass 19, count 0 2006.211.08:23:08.78#ibcon#read 3, iclass 19, count 0 2006.211.08:23:08.78#ibcon#about to read 4, iclass 19, count 0 2006.211.08:23:08.78#ibcon#read 4, iclass 19, count 0 2006.211.08:23:08.78#ibcon#about to read 5, iclass 19, count 0 2006.211.08:23:08.78#ibcon#read 5, iclass 19, count 0 2006.211.08:23:08.78#ibcon#about to read 6, iclass 19, count 0 2006.211.08:23:08.78#ibcon#read 6, iclass 19, count 0 2006.211.08:23:08.78#ibcon#end of sib2, iclass 19, count 0 2006.211.08:23:08.78#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:23:08.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:23:08.78#ibcon#[25=USB\r\n] 2006.211.08:23:08.78#ibcon#*before write, iclass 19, count 0 2006.211.08:23:08.78#ibcon#enter sib2, iclass 19, count 0 2006.211.08:23:08.78#ibcon#flushed, iclass 19, count 0 2006.211.08:23:08.78#ibcon#about to write, iclass 19, count 0 2006.211.08:23:08.78#ibcon#wrote, iclass 19, count 0 2006.211.08:23:08.78#ibcon#about to read 3, iclass 19, count 0 2006.211.08:23:08.81#ibcon#read 3, iclass 19, count 0 2006.211.08:23:08.81#ibcon#about to read 4, iclass 19, count 0 2006.211.08:23:08.81#ibcon#read 4, iclass 19, count 0 2006.211.08:23:08.81#ibcon#about to read 5, iclass 19, count 0 2006.211.08:23:08.81#ibcon#read 5, iclass 19, count 0 2006.211.08:23:08.81#ibcon#about to read 6, iclass 19, count 0 2006.211.08:23:08.81#ibcon#read 6, iclass 19, count 0 2006.211.08:23:08.81#ibcon#end of sib2, iclass 19, count 0 2006.211.08:23:08.81#ibcon#*after write, iclass 19, count 0 2006.211.08:23:08.81#ibcon#*before return 0, iclass 19, count 0 2006.211.08:23:08.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:08.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:08.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:23:08.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:23:08.81$vc4f8/valo=5,652.99 2006.211.08:23:08.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:23:08.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:23:08.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:08.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:08.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:08.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:08.81#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:23:08.81#ibcon#first serial, iclass 21, count 0 2006.211.08:23:08.81#ibcon#enter sib2, iclass 21, count 0 2006.211.08:23:08.81#ibcon#flushed, iclass 21, count 0 2006.211.08:23:08.81#ibcon#about to write, iclass 21, count 0 2006.211.08:23:08.81#ibcon#wrote, iclass 21, count 0 2006.211.08:23:08.81#ibcon#about to read 3, iclass 21, count 0 2006.211.08:23:08.83#ibcon#read 3, iclass 21, count 0 2006.211.08:23:08.83#ibcon#about to read 4, iclass 21, count 0 2006.211.08:23:08.83#ibcon#read 4, iclass 21, count 0 2006.211.08:23:08.83#ibcon#about to read 5, iclass 21, count 0 2006.211.08:23:08.83#ibcon#read 5, iclass 21, count 0 2006.211.08:23:08.83#ibcon#about to read 6, iclass 21, count 0 2006.211.08:23:08.83#ibcon#read 6, iclass 21, count 0 2006.211.08:23:08.83#ibcon#end of sib2, iclass 21, count 0 2006.211.08:23:08.83#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:23:08.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:23:08.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:23:08.83#ibcon#*before write, iclass 21, count 0 2006.211.08:23:08.83#ibcon#enter sib2, iclass 21, count 0 2006.211.08:23:08.83#ibcon#flushed, iclass 21, count 0 2006.211.08:23:08.83#ibcon#about to write, iclass 21, count 0 2006.211.08:23:08.83#ibcon#wrote, iclass 21, count 0 2006.211.08:23:08.83#ibcon#about to read 3, iclass 21, count 0 2006.211.08:23:08.87#ibcon#read 3, iclass 21, count 0 2006.211.08:23:08.87#ibcon#about to read 4, iclass 21, count 0 2006.211.08:23:08.87#ibcon#read 4, iclass 21, count 0 2006.211.08:23:08.87#ibcon#about to read 5, iclass 21, count 0 2006.211.08:23:08.87#ibcon#read 5, iclass 21, count 0 2006.211.08:23:08.87#ibcon#about to read 6, iclass 21, count 0 2006.211.08:23:08.87#ibcon#read 6, iclass 21, count 0 2006.211.08:23:08.87#ibcon#end of sib2, iclass 21, count 0 2006.211.08:23:08.87#ibcon#*after write, iclass 21, count 0 2006.211.08:23:08.87#ibcon#*before return 0, iclass 21, count 0 2006.211.08:23:08.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:08.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:08.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:23:08.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:23:08.87$vc4f8/va=5,7 2006.211.08:23:08.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:23:08.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:23:08.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:08.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:08.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:08.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:08.93#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:23:08.93#ibcon#first serial, iclass 23, count 2 2006.211.08:23:08.93#ibcon#enter sib2, iclass 23, count 2 2006.211.08:23:08.93#ibcon#flushed, iclass 23, count 2 2006.211.08:23:08.93#ibcon#about to write, iclass 23, count 2 2006.211.08:23:08.93#ibcon#wrote, iclass 23, count 2 2006.211.08:23:08.93#ibcon#about to read 3, iclass 23, count 2 2006.211.08:23:08.95#ibcon#read 3, iclass 23, count 2 2006.211.08:23:08.95#ibcon#about to read 4, iclass 23, count 2 2006.211.08:23:08.95#ibcon#read 4, iclass 23, count 2 2006.211.08:23:08.95#ibcon#about to read 5, iclass 23, count 2 2006.211.08:23:08.95#ibcon#read 5, iclass 23, count 2 2006.211.08:23:08.95#ibcon#about to read 6, iclass 23, count 2 2006.211.08:23:08.95#ibcon#read 6, iclass 23, count 2 2006.211.08:23:08.95#ibcon#end of sib2, iclass 23, count 2 2006.211.08:23:08.95#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:23:08.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:23:08.95#ibcon#[25=AT05-07\r\n] 2006.211.08:23:08.95#ibcon#*before write, iclass 23, count 2 2006.211.08:23:08.95#ibcon#enter sib2, iclass 23, count 2 2006.211.08:23:08.95#ibcon#flushed, iclass 23, count 2 2006.211.08:23:08.95#ibcon#about to write, iclass 23, count 2 2006.211.08:23:08.95#ibcon#wrote, iclass 23, count 2 2006.211.08:23:08.95#ibcon#about to read 3, iclass 23, count 2 2006.211.08:23:08.98#ibcon#read 3, iclass 23, count 2 2006.211.08:23:08.98#ibcon#about to read 4, iclass 23, count 2 2006.211.08:23:08.98#ibcon#read 4, iclass 23, count 2 2006.211.08:23:08.98#ibcon#about to read 5, iclass 23, count 2 2006.211.08:23:08.98#ibcon#read 5, iclass 23, count 2 2006.211.08:23:08.98#ibcon#about to read 6, iclass 23, count 2 2006.211.08:23:08.98#ibcon#read 6, iclass 23, count 2 2006.211.08:23:08.98#ibcon#end of sib2, iclass 23, count 2 2006.211.08:23:08.98#ibcon#*after write, iclass 23, count 2 2006.211.08:23:08.98#ibcon#*before return 0, iclass 23, count 2 2006.211.08:23:08.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:08.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:08.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:23:08.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:08.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:09.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:09.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:09.10#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:23:09.10#ibcon#first serial, iclass 23, count 0 2006.211.08:23:09.10#ibcon#enter sib2, iclass 23, count 0 2006.211.08:23:09.10#ibcon#flushed, iclass 23, count 0 2006.211.08:23:09.10#ibcon#about to write, iclass 23, count 0 2006.211.08:23:09.10#ibcon#wrote, iclass 23, count 0 2006.211.08:23:09.10#ibcon#about to read 3, iclass 23, count 0 2006.211.08:23:09.12#ibcon#read 3, iclass 23, count 0 2006.211.08:23:09.12#ibcon#about to read 4, iclass 23, count 0 2006.211.08:23:09.12#ibcon#read 4, iclass 23, count 0 2006.211.08:23:09.12#ibcon#about to read 5, iclass 23, count 0 2006.211.08:23:09.12#ibcon#read 5, iclass 23, count 0 2006.211.08:23:09.12#ibcon#about to read 6, iclass 23, count 0 2006.211.08:23:09.12#ibcon#read 6, iclass 23, count 0 2006.211.08:23:09.12#ibcon#end of sib2, iclass 23, count 0 2006.211.08:23:09.12#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:23:09.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:23:09.12#ibcon#[25=USB\r\n] 2006.211.08:23:09.12#ibcon#*before write, iclass 23, count 0 2006.211.08:23:09.12#ibcon#enter sib2, iclass 23, count 0 2006.211.08:23:09.12#ibcon#flushed, iclass 23, count 0 2006.211.08:23:09.12#ibcon#about to write, iclass 23, count 0 2006.211.08:23:09.12#ibcon#wrote, iclass 23, count 0 2006.211.08:23:09.12#ibcon#about to read 3, iclass 23, count 0 2006.211.08:23:09.15#ibcon#read 3, iclass 23, count 0 2006.211.08:23:09.15#ibcon#about to read 4, iclass 23, count 0 2006.211.08:23:09.15#ibcon#read 4, iclass 23, count 0 2006.211.08:23:09.15#ibcon#about to read 5, iclass 23, count 0 2006.211.08:23:09.15#ibcon#read 5, iclass 23, count 0 2006.211.08:23:09.15#ibcon#about to read 6, iclass 23, count 0 2006.211.08:23:09.15#ibcon#read 6, iclass 23, count 0 2006.211.08:23:09.15#ibcon#end of sib2, iclass 23, count 0 2006.211.08:23:09.15#ibcon#*after write, iclass 23, count 0 2006.211.08:23:09.15#ibcon#*before return 0, iclass 23, count 0 2006.211.08:23:09.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:09.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:09.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:23:09.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:23:09.15$vc4f8/valo=6,772.99 2006.211.08:23:09.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:23:09.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:23:09.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:09.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:09.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:09.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:09.15#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:23:09.15#ibcon#first serial, iclass 25, count 0 2006.211.08:23:09.15#ibcon#enter sib2, iclass 25, count 0 2006.211.08:23:09.15#ibcon#flushed, iclass 25, count 0 2006.211.08:23:09.15#ibcon#about to write, iclass 25, count 0 2006.211.08:23:09.15#ibcon#wrote, iclass 25, count 0 2006.211.08:23:09.15#ibcon#about to read 3, iclass 25, count 0 2006.211.08:23:09.17#ibcon#read 3, iclass 25, count 0 2006.211.08:23:09.17#ibcon#about to read 4, iclass 25, count 0 2006.211.08:23:09.17#ibcon#read 4, iclass 25, count 0 2006.211.08:23:09.17#ibcon#about to read 5, iclass 25, count 0 2006.211.08:23:09.17#ibcon#read 5, iclass 25, count 0 2006.211.08:23:09.17#ibcon#about to read 6, iclass 25, count 0 2006.211.08:23:09.17#ibcon#read 6, iclass 25, count 0 2006.211.08:23:09.17#ibcon#end of sib2, iclass 25, count 0 2006.211.08:23:09.17#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:23:09.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:23:09.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:23:09.17#ibcon#*before write, iclass 25, count 0 2006.211.08:23:09.17#ibcon#enter sib2, iclass 25, count 0 2006.211.08:23:09.17#ibcon#flushed, iclass 25, count 0 2006.211.08:23:09.17#ibcon#about to write, iclass 25, count 0 2006.211.08:23:09.17#ibcon#wrote, iclass 25, count 0 2006.211.08:23:09.17#ibcon#about to read 3, iclass 25, count 0 2006.211.08:23:09.21#ibcon#read 3, iclass 25, count 0 2006.211.08:23:09.21#ibcon#about to read 4, iclass 25, count 0 2006.211.08:23:09.21#ibcon#read 4, iclass 25, count 0 2006.211.08:23:09.21#ibcon#about to read 5, iclass 25, count 0 2006.211.08:23:09.21#ibcon#read 5, iclass 25, count 0 2006.211.08:23:09.21#ibcon#about to read 6, iclass 25, count 0 2006.211.08:23:09.21#ibcon#read 6, iclass 25, count 0 2006.211.08:23:09.21#ibcon#end of sib2, iclass 25, count 0 2006.211.08:23:09.21#ibcon#*after write, iclass 25, count 0 2006.211.08:23:09.21#ibcon#*before return 0, iclass 25, count 0 2006.211.08:23:09.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:09.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:09.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:23:09.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:23:09.21$vc4f8/va=6,6 2006.211.08:23:09.21#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.211.08:23:09.21#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.211.08:23:09.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:09.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:23:09.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:23:09.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:23:09.27#ibcon#enter wrdev, iclass 27, count 2 2006.211.08:23:09.27#ibcon#first serial, iclass 27, count 2 2006.211.08:23:09.27#ibcon#enter sib2, iclass 27, count 2 2006.211.08:23:09.27#ibcon#flushed, iclass 27, count 2 2006.211.08:23:09.27#ibcon#about to write, iclass 27, count 2 2006.211.08:23:09.27#ibcon#wrote, iclass 27, count 2 2006.211.08:23:09.27#ibcon#about to read 3, iclass 27, count 2 2006.211.08:23:09.29#ibcon#read 3, iclass 27, count 2 2006.211.08:23:09.29#ibcon#about to read 4, iclass 27, count 2 2006.211.08:23:09.29#ibcon#read 4, iclass 27, count 2 2006.211.08:23:09.29#ibcon#about to read 5, iclass 27, count 2 2006.211.08:23:09.29#ibcon#read 5, iclass 27, count 2 2006.211.08:23:09.29#ibcon#about to read 6, iclass 27, count 2 2006.211.08:23:09.29#ibcon#read 6, iclass 27, count 2 2006.211.08:23:09.29#ibcon#end of sib2, iclass 27, count 2 2006.211.08:23:09.29#ibcon#*mode == 0, iclass 27, count 2 2006.211.08:23:09.29#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.211.08:23:09.29#ibcon#[25=AT06-06\r\n] 2006.211.08:23:09.29#ibcon#*before write, iclass 27, count 2 2006.211.08:23:09.29#ibcon#enter sib2, iclass 27, count 2 2006.211.08:23:09.29#ibcon#flushed, iclass 27, count 2 2006.211.08:23:09.29#ibcon#about to write, iclass 27, count 2 2006.211.08:23:09.29#ibcon#wrote, iclass 27, count 2 2006.211.08:23:09.29#ibcon#about to read 3, iclass 27, count 2 2006.211.08:23:09.32#ibcon#read 3, iclass 27, count 2 2006.211.08:23:09.32#ibcon#about to read 4, iclass 27, count 2 2006.211.08:23:09.32#ibcon#read 4, iclass 27, count 2 2006.211.08:23:09.32#ibcon#about to read 5, iclass 27, count 2 2006.211.08:23:09.32#ibcon#read 5, iclass 27, count 2 2006.211.08:23:09.32#ibcon#about to read 6, iclass 27, count 2 2006.211.08:23:09.32#ibcon#read 6, iclass 27, count 2 2006.211.08:23:09.32#ibcon#end of sib2, iclass 27, count 2 2006.211.08:23:09.32#ibcon#*after write, iclass 27, count 2 2006.211.08:23:09.32#ibcon#*before return 0, iclass 27, count 2 2006.211.08:23:09.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:23:09.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.211.08:23:09.32#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.211.08:23:09.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:09.32#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:23:09.44#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:23:09.44#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:23:09.44#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:23:09.44#ibcon#first serial, iclass 27, count 0 2006.211.08:23:09.44#ibcon#enter sib2, iclass 27, count 0 2006.211.08:23:09.44#ibcon#flushed, iclass 27, count 0 2006.211.08:23:09.44#ibcon#about to write, iclass 27, count 0 2006.211.08:23:09.44#ibcon#wrote, iclass 27, count 0 2006.211.08:23:09.44#ibcon#about to read 3, iclass 27, count 0 2006.211.08:23:09.46#ibcon#read 3, iclass 27, count 0 2006.211.08:23:09.46#ibcon#about to read 4, iclass 27, count 0 2006.211.08:23:09.46#ibcon#read 4, iclass 27, count 0 2006.211.08:23:09.46#ibcon#about to read 5, iclass 27, count 0 2006.211.08:23:09.46#ibcon#read 5, iclass 27, count 0 2006.211.08:23:09.46#ibcon#about to read 6, iclass 27, count 0 2006.211.08:23:09.46#ibcon#read 6, iclass 27, count 0 2006.211.08:23:09.46#ibcon#end of sib2, iclass 27, count 0 2006.211.08:23:09.46#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:23:09.46#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:23:09.46#ibcon#[25=USB\r\n] 2006.211.08:23:09.46#ibcon#*before write, iclass 27, count 0 2006.211.08:23:09.46#ibcon#enter sib2, iclass 27, count 0 2006.211.08:23:09.46#ibcon#flushed, iclass 27, count 0 2006.211.08:23:09.46#ibcon#about to write, iclass 27, count 0 2006.211.08:23:09.46#ibcon#wrote, iclass 27, count 0 2006.211.08:23:09.46#ibcon#about to read 3, iclass 27, count 0 2006.211.08:23:09.49#ibcon#read 3, iclass 27, count 0 2006.211.08:23:09.49#ibcon#about to read 4, iclass 27, count 0 2006.211.08:23:09.49#ibcon#read 4, iclass 27, count 0 2006.211.08:23:09.49#ibcon#about to read 5, iclass 27, count 0 2006.211.08:23:09.49#ibcon#read 5, iclass 27, count 0 2006.211.08:23:09.49#ibcon#about to read 6, iclass 27, count 0 2006.211.08:23:09.49#ibcon#read 6, iclass 27, count 0 2006.211.08:23:09.49#ibcon#end of sib2, iclass 27, count 0 2006.211.08:23:09.49#ibcon#*after write, iclass 27, count 0 2006.211.08:23:09.49#ibcon#*before return 0, iclass 27, count 0 2006.211.08:23:09.49#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:23:09.49#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.211.08:23:09.49#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:23:09.49#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:23:09.49$vc4f8/valo=7,832.99 2006.211.08:23:09.49#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:23:09.49#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:23:09.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:09.49#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:23:09.49#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:23:09.49#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:23:09.49#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:23:09.49#ibcon#first serial, iclass 29, count 0 2006.211.08:23:09.49#ibcon#enter sib2, iclass 29, count 0 2006.211.08:23:09.49#ibcon#flushed, iclass 29, count 0 2006.211.08:23:09.49#ibcon#about to write, iclass 29, count 0 2006.211.08:23:09.49#ibcon#wrote, iclass 29, count 0 2006.211.08:23:09.49#ibcon#about to read 3, iclass 29, count 0 2006.211.08:23:09.51#ibcon#read 3, iclass 29, count 0 2006.211.08:23:09.51#ibcon#about to read 4, iclass 29, count 0 2006.211.08:23:09.51#ibcon#read 4, iclass 29, count 0 2006.211.08:23:09.51#ibcon#about to read 5, iclass 29, count 0 2006.211.08:23:09.51#ibcon#read 5, iclass 29, count 0 2006.211.08:23:09.51#ibcon#about to read 6, iclass 29, count 0 2006.211.08:23:09.51#ibcon#read 6, iclass 29, count 0 2006.211.08:23:09.51#ibcon#end of sib2, iclass 29, count 0 2006.211.08:23:09.51#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:23:09.51#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:23:09.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:23:09.51#ibcon#*before write, iclass 29, count 0 2006.211.08:23:09.51#ibcon#enter sib2, iclass 29, count 0 2006.211.08:23:09.51#ibcon#flushed, iclass 29, count 0 2006.211.08:23:09.51#ibcon#about to write, iclass 29, count 0 2006.211.08:23:09.51#ibcon#wrote, iclass 29, count 0 2006.211.08:23:09.51#ibcon#about to read 3, iclass 29, count 0 2006.211.08:23:09.55#ibcon#read 3, iclass 29, count 0 2006.211.08:23:09.55#ibcon#about to read 4, iclass 29, count 0 2006.211.08:23:09.55#ibcon#read 4, iclass 29, count 0 2006.211.08:23:09.55#ibcon#about to read 5, iclass 29, count 0 2006.211.08:23:09.55#ibcon#read 5, iclass 29, count 0 2006.211.08:23:09.55#ibcon#about to read 6, iclass 29, count 0 2006.211.08:23:09.55#ibcon#read 6, iclass 29, count 0 2006.211.08:23:09.55#ibcon#end of sib2, iclass 29, count 0 2006.211.08:23:09.55#ibcon#*after write, iclass 29, count 0 2006.211.08:23:09.55#ibcon#*before return 0, iclass 29, count 0 2006.211.08:23:09.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:23:09.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:23:09.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:23:09.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:23:09.55$vc4f8/va=7,6 2006.211.08:23:09.55#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.211.08:23:09.55#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.211.08:23:09.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:09.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:23:09.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:23:09.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:23:09.61#ibcon#enter wrdev, iclass 31, count 2 2006.211.08:23:09.61#ibcon#first serial, iclass 31, count 2 2006.211.08:23:09.61#ibcon#enter sib2, iclass 31, count 2 2006.211.08:23:09.61#ibcon#flushed, iclass 31, count 2 2006.211.08:23:09.61#ibcon#about to write, iclass 31, count 2 2006.211.08:23:09.61#ibcon#wrote, iclass 31, count 2 2006.211.08:23:09.61#ibcon#about to read 3, iclass 31, count 2 2006.211.08:23:09.63#ibcon#read 3, iclass 31, count 2 2006.211.08:23:09.63#ibcon#about to read 4, iclass 31, count 2 2006.211.08:23:09.63#ibcon#read 4, iclass 31, count 2 2006.211.08:23:09.63#ibcon#about to read 5, iclass 31, count 2 2006.211.08:23:09.63#ibcon#read 5, iclass 31, count 2 2006.211.08:23:09.63#ibcon#about to read 6, iclass 31, count 2 2006.211.08:23:09.63#ibcon#read 6, iclass 31, count 2 2006.211.08:23:09.63#ibcon#end of sib2, iclass 31, count 2 2006.211.08:23:09.63#ibcon#*mode == 0, iclass 31, count 2 2006.211.08:23:09.63#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.211.08:23:09.63#ibcon#[25=AT07-06\r\n] 2006.211.08:23:09.63#ibcon#*before write, iclass 31, count 2 2006.211.08:23:09.63#ibcon#enter sib2, iclass 31, count 2 2006.211.08:23:09.63#ibcon#flushed, iclass 31, count 2 2006.211.08:23:09.63#ibcon#about to write, iclass 31, count 2 2006.211.08:23:09.63#ibcon#wrote, iclass 31, count 2 2006.211.08:23:09.63#ibcon#about to read 3, iclass 31, count 2 2006.211.08:23:09.66#ibcon#read 3, iclass 31, count 2 2006.211.08:23:09.66#ibcon#about to read 4, iclass 31, count 2 2006.211.08:23:09.66#ibcon#read 4, iclass 31, count 2 2006.211.08:23:09.66#ibcon#about to read 5, iclass 31, count 2 2006.211.08:23:09.66#ibcon#read 5, iclass 31, count 2 2006.211.08:23:09.66#ibcon#about to read 6, iclass 31, count 2 2006.211.08:23:09.66#ibcon#read 6, iclass 31, count 2 2006.211.08:23:09.66#ibcon#end of sib2, iclass 31, count 2 2006.211.08:23:09.66#ibcon#*after write, iclass 31, count 2 2006.211.08:23:09.66#ibcon#*before return 0, iclass 31, count 2 2006.211.08:23:09.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:23:09.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.211.08:23:09.66#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.211.08:23:09.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:09.66#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:23:09.78#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:23:09.78#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:23:09.78#ibcon#enter wrdev, iclass 31, count 0 2006.211.08:23:09.78#ibcon#first serial, iclass 31, count 0 2006.211.08:23:09.78#ibcon#enter sib2, iclass 31, count 0 2006.211.08:23:09.78#ibcon#flushed, iclass 31, count 0 2006.211.08:23:09.78#ibcon#about to write, iclass 31, count 0 2006.211.08:23:09.78#ibcon#wrote, iclass 31, count 0 2006.211.08:23:09.78#ibcon#about to read 3, iclass 31, count 0 2006.211.08:23:09.80#ibcon#read 3, iclass 31, count 0 2006.211.08:23:09.80#ibcon#about to read 4, iclass 31, count 0 2006.211.08:23:09.80#ibcon#read 4, iclass 31, count 0 2006.211.08:23:09.80#ibcon#about to read 5, iclass 31, count 0 2006.211.08:23:09.80#ibcon#read 5, iclass 31, count 0 2006.211.08:23:09.80#ibcon#about to read 6, iclass 31, count 0 2006.211.08:23:09.80#ibcon#read 6, iclass 31, count 0 2006.211.08:23:09.80#ibcon#end of sib2, iclass 31, count 0 2006.211.08:23:09.80#ibcon#*mode == 0, iclass 31, count 0 2006.211.08:23:09.80#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.211.08:23:09.80#ibcon#[25=USB\r\n] 2006.211.08:23:09.80#ibcon#*before write, iclass 31, count 0 2006.211.08:23:09.80#ibcon#enter sib2, iclass 31, count 0 2006.211.08:23:09.80#ibcon#flushed, iclass 31, count 0 2006.211.08:23:09.80#ibcon#about to write, iclass 31, count 0 2006.211.08:23:09.80#ibcon#wrote, iclass 31, count 0 2006.211.08:23:09.80#ibcon#about to read 3, iclass 31, count 0 2006.211.08:23:09.83#ibcon#read 3, iclass 31, count 0 2006.211.08:23:09.83#ibcon#about to read 4, iclass 31, count 0 2006.211.08:23:09.83#ibcon#read 4, iclass 31, count 0 2006.211.08:23:09.83#ibcon#about to read 5, iclass 31, count 0 2006.211.08:23:09.83#ibcon#read 5, iclass 31, count 0 2006.211.08:23:09.83#ibcon#about to read 6, iclass 31, count 0 2006.211.08:23:09.83#ibcon#read 6, iclass 31, count 0 2006.211.08:23:09.83#ibcon#end of sib2, iclass 31, count 0 2006.211.08:23:09.83#ibcon#*after write, iclass 31, count 0 2006.211.08:23:09.83#ibcon#*before return 0, iclass 31, count 0 2006.211.08:23:09.83#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:23:09.83#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.211.08:23:09.83#ibcon#about to clear, iclass 31 cls_cnt 0 2006.211.08:23:09.83#ibcon#cleared, iclass 31 cls_cnt 0 2006.211.08:23:09.83$vc4f8/valo=8,852.99 2006.211.08:23:09.83#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.211.08:23:09.83#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.211.08:23:09.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:09.83#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:23:09.83#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:23:09.83#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:23:09.83#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:23:09.83#ibcon#first serial, iclass 33, count 0 2006.211.08:23:09.83#ibcon#enter sib2, iclass 33, count 0 2006.211.08:23:09.83#ibcon#flushed, iclass 33, count 0 2006.211.08:23:09.83#ibcon#about to write, iclass 33, count 0 2006.211.08:23:09.83#ibcon#wrote, iclass 33, count 0 2006.211.08:23:09.83#ibcon#about to read 3, iclass 33, count 0 2006.211.08:23:09.85#ibcon#read 3, iclass 33, count 0 2006.211.08:23:09.85#ibcon#about to read 4, iclass 33, count 0 2006.211.08:23:09.85#ibcon#read 4, iclass 33, count 0 2006.211.08:23:09.85#ibcon#about to read 5, iclass 33, count 0 2006.211.08:23:09.85#ibcon#read 5, iclass 33, count 0 2006.211.08:23:09.85#ibcon#about to read 6, iclass 33, count 0 2006.211.08:23:09.85#ibcon#read 6, iclass 33, count 0 2006.211.08:23:09.85#ibcon#end of sib2, iclass 33, count 0 2006.211.08:23:09.85#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:23:09.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:23:09.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:23:09.85#ibcon#*before write, iclass 33, count 0 2006.211.08:23:09.85#ibcon#enter sib2, iclass 33, count 0 2006.211.08:23:09.85#ibcon#flushed, iclass 33, count 0 2006.211.08:23:09.85#ibcon#about to write, iclass 33, count 0 2006.211.08:23:09.85#ibcon#wrote, iclass 33, count 0 2006.211.08:23:09.85#ibcon#about to read 3, iclass 33, count 0 2006.211.08:23:09.89#ibcon#read 3, iclass 33, count 0 2006.211.08:23:09.89#ibcon#about to read 4, iclass 33, count 0 2006.211.08:23:09.89#ibcon#read 4, iclass 33, count 0 2006.211.08:23:09.89#ibcon#about to read 5, iclass 33, count 0 2006.211.08:23:09.89#ibcon#read 5, iclass 33, count 0 2006.211.08:23:09.89#ibcon#about to read 6, iclass 33, count 0 2006.211.08:23:09.89#ibcon#read 6, iclass 33, count 0 2006.211.08:23:09.89#ibcon#end of sib2, iclass 33, count 0 2006.211.08:23:09.89#ibcon#*after write, iclass 33, count 0 2006.211.08:23:09.89#ibcon#*before return 0, iclass 33, count 0 2006.211.08:23:09.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:23:09.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.211.08:23:09.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:23:09.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:23:09.89$vc4f8/va=8,7 2006.211.08:23:09.89#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.211.08:23:09.89#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.211.08:23:09.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:09.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:23:09.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:23:09.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:23:09.95#ibcon#enter wrdev, iclass 35, count 2 2006.211.08:23:09.95#ibcon#first serial, iclass 35, count 2 2006.211.08:23:09.95#ibcon#enter sib2, iclass 35, count 2 2006.211.08:23:09.95#ibcon#flushed, iclass 35, count 2 2006.211.08:23:09.95#ibcon#about to write, iclass 35, count 2 2006.211.08:23:09.95#ibcon#wrote, iclass 35, count 2 2006.211.08:23:09.95#ibcon#about to read 3, iclass 35, count 2 2006.211.08:23:09.97#ibcon#read 3, iclass 35, count 2 2006.211.08:23:09.97#ibcon#about to read 4, iclass 35, count 2 2006.211.08:23:09.97#ibcon#read 4, iclass 35, count 2 2006.211.08:23:09.97#ibcon#about to read 5, iclass 35, count 2 2006.211.08:23:09.97#ibcon#read 5, iclass 35, count 2 2006.211.08:23:09.97#ibcon#about to read 6, iclass 35, count 2 2006.211.08:23:09.97#ibcon#read 6, iclass 35, count 2 2006.211.08:23:09.97#ibcon#end of sib2, iclass 35, count 2 2006.211.08:23:09.97#ibcon#*mode == 0, iclass 35, count 2 2006.211.08:23:09.97#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.211.08:23:09.97#ibcon#[25=AT08-07\r\n] 2006.211.08:23:09.97#ibcon#*before write, iclass 35, count 2 2006.211.08:23:09.97#ibcon#enter sib2, iclass 35, count 2 2006.211.08:23:09.97#ibcon#flushed, iclass 35, count 2 2006.211.08:23:09.97#ibcon#about to write, iclass 35, count 2 2006.211.08:23:09.97#ibcon#wrote, iclass 35, count 2 2006.211.08:23:09.97#ibcon#about to read 3, iclass 35, count 2 2006.211.08:23:10.00#ibcon#read 3, iclass 35, count 2 2006.211.08:23:10.00#ibcon#about to read 4, iclass 35, count 2 2006.211.08:23:10.00#ibcon#read 4, iclass 35, count 2 2006.211.08:23:10.00#ibcon#about to read 5, iclass 35, count 2 2006.211.08:23:10.00#ibcon#read 5, iclass 35, count 2 2006.211.08:23:10.00#ibcon#about to read 6, iclass 35, count 2 2006.211.08:23:10.00#ibcon#read 6, iclass 35, count 2 2006.211.08:23:10.00#ibcon#end of sib2, iclass 35, count 2 2006.211.08:23:10.00#ibcon#*after write, iclass 35, count 2 2006.211.08:23:10.00#ibcon#*before return 0, iclass 35, count 2 2006.211.08:23:10.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:23:10.00#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.211.08:23:10.00#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.211.08:23:10.00#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:10.00#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:23:10.12#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:23:10.12#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:23:10.12#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:23:10.12#ibcon#first serial, iclass 35, count 0 2006.211.08:23:10.12#ibcon#enter sib2, iclass 35, count 0 2006.211.08:23:10.12#ibcon#flushed, iclass 35, count 0 2006.211.08:23:10.12#ibcon#about to write, iclass 35, count 0 2006.211.08:23:10.12#ibcon#wrote, iclass 35, count 0 2006.211.08:23:10.12#ibcon#about to read 3, iclass 35, count 0 2006.211.08:23:10.14#ibcon#read 3, iclass 35, count 0 2006.211.08:23:10.14#ibcon#about to read 4, iclass 35, count 0 2006.211.08:23:10.14#ibcon#read 4, iclass 35, count 0 2006.211.08:23:10.14#ibcon#about to read 5, iclass 35, count 0 2006.211.08:23:10.14#ibcon#read 5, iclass 35, count 0 2006.211.08:23:10.14#ibcon#about to read 6, iclass 35, count 0 2006.211.08:23:10.14#ibcon#read 6, iclass 35, count 0 2006.211.08:23:10.14#ibcon#end of sib2, iclass 35, count 0 2006.211.08:23:10.14#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:23:10.14#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:23:10.14#ibcon#[25=USB\r\n] 2006.211.08:23:10.14#ibcon#*before write, iclass 35, count 0 2006.211.08:23:10.14#ibcon#enter sib2, iclass 35, count 0 2006.211.08:23:10.14#ibcon#flushed, iclass 35, count 0 2006.211.08:23:10.14#ibcon#about to write, iclass 35, count 0 2006.211.08:23:10.14#ibcon#wrote, iclass 35, count 0 2006.211.08:23:10.14#ibcon#about to read 3, iclass 35, count 0 2006.211.08:23:10.17#ibcon#read 3, iclass 35, count 0 2006.211.08:23:10.17#ibcon#about to read 4, iclass 35, count 0 2006.211.08:23:10.17#ibcon#read 4, iclass 35, count 0 2006.211.08:23:10.17#ibcon#about to read 5, iclass 35, count 0 2006.211.08:23:10.17#ibcon#read 5, iclass 35, count 0 2006.211.08:23:10.17#ibcon#about to read 6, iclass 35, count 0 2006.211.08:23:10.17#ibcon#read 6, iclass 35, count 0 2006.211.08:23:10.17#ibcon#end of sib2, iclass 35, count 0 2006.211.08:23:10.17#ibcon#*after write, iclass 35, count 0 2006.211.08:23:10.17#ibcon#*before return 0, iclass 35, count 0 2006.211.08:23:10.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:23:10.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.211.08:23:10.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:23:10.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:23:10.17$vc4f8/vblo=1,632.99 2006.211.08:23:10.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.211.08:23:10.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.211.08:23:10.17#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:10.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:23:10.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:23:10.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:23:10.17#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:23:10.17#ibcon#first serial, iclass 37, count 0 2006.211.08:23:10.17#ibcon#enter sib2, iclass 37, count 0 2006.211.08:23:10.17#ibcon#flushed, iclass 37, count 0 2006.211.08:23:10.17#ibcon#about to write, iclass 37, count 0 2006.211.08:23:10.17#ibcon#wrote, iclass 37, count 0 2006.211.08:23:10.17#ibcon#about to read 3, iclass 37, count 0 2006.211.08:23:10.19#ibcon#read 3, iclass 37, count 0 2006.211.08:23:10.19#ibcon#about to read 4, iclass 37, count 0 2006.211.08:23:10.19#ibcon#read 4, iclass 37, count 0 2006.211.08:23:10.19#ibcon#about to read 5, iclass 37, count 0 2006.211.08:23:10.19#ibcon#read 5, iclass 37, count 0 2006.211.08:23:10.19#ibcon#about to read 6, iclass 37, count 0 2006.211.08:23:10.19#ibcon#read 6, iclass 37, count 0 2006.211.08:23:10.19#ibcon#end of sib2, iclass 37, count 0 2006.211.08:23:10.19#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:23:10.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:23:10.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:23:10.19#ibcon#*before write, iclass 37, count 0 2006.211.08:23:10.19#ibcon#enter sib2, iclass 37, count 0 2006.211.08:23:10.19#ibcon#flushed, iclass 37, count 0 2006.211.08:23:10.19#ibcon#about to write, iclass 37, count 0 2006.211.08:23:10.19#ibcon#wrote, iclass 37, count 0 2006.211.08:23:10.19#ibcon#about to read 3, iclass 37, count 0 2006.211.08:23:10.23#ibcon#read 3, iclass 37, count 0 2006.211.08:23:10.23#ibcon#about to read 4, iclass 37, count 0 2006.211.08:23:10.23#ibcon#read 4, iclass 37, count 0 2006.211.08:23:10.23#ibcon#about to read 5, iclass 37, count 0 2006.211.08:23:10.23#ibcon#read 5, iclass 37, count 0 2006.211.08:23:10.23#ibcon#about to read 6, iclass 37, count 0 2006.211.08:23:10.23#ibcon#read 6, iclass 37, count 0 2006.211.08:23:10.23#ibcon#end of sib2, iclass 37, count 0 2006.211.08:23:10.23#ibcon#*after write, iclass 37, count 0 2006.211.08:23:10.23#ibcon#*before return 0, iclass 37, count 0 2006.211.08:23:10.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:23:10.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.211.08:23:10.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:23:10.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:23:10.23$vc4f8/vb=1,4 2006.211.08:23:10.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.211.08:23:10.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.211.08:23:10.23#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:10.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:23:10.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:23:10.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:23:10.23#ibcon#enter wrdev, iclass 39, count 2 2006.211.08:23:10.23#ibcon#first serial, iclass 39, count 2 2006.211.08:23:10.23#ibcon#enter sib2, iclass 39, count 2 2006.211.08:23:10.23#ibcon#flushed, iclass 39, count 2 2006.211.08:23:10.23#ibcon#about to write, iclass 39, count 2 2006.211.08:23:10.23#ibcon#wrote, iclass 39, count 2 2006.211.08:23:10.23#ibcon#about to read 3, iclass 39, count 2 2006.211.08:23:10.25#ibcon#read 3, iclass 39, count 2 2006.211.08:23:10.25#ibcon#about to read 4, iclass 39, count 2 2006.211.08:23:10.25#ibcon#read 4, iclass 39, count 2 2006.211.08:23:10.25#ibcon#about to read 5, iclass 39, count 2 2006.211.08:23:10.25#ibcon#read 5, iclass 39, count 2 2006.211.08:23:10.25#ibcon#about to read 6, iclass 39, count 2 2006.211.08:23:10.25#ibcon#read 6, iclass 39, count 2 2006.211.08:23:10.25#ibcon#end of sib2, iclass 39, count 2 2006.211.08:23:10.25#ibcon#*mode == 0, iclass 39, count 2 2006.211.08:23:10.25#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.211.08:23:10.25#ibcon#[27=AT01-04\r\n] 2006.211.08:23:10.25#ibcon#*before write, iclass 39, count 2 2006.211.08:23:10.25#ibcon#enter sib2, iclass 39, count 2 2006.211.08:23:10.25#ibcon#flushed, iclass 39, count 2 2006.211.08:23:10.25#ibcon#about to write, iclass 39, count 2 2006.211.08:23:10.25#ibcon#wrote, iclass 39, count 2 2006.211.08:23:10.25#ibcon#about to read 3, iclass 39, count 2 2006.211.08:23:10.28#ibcon#read 3, iclass 39, count 2 2006.211.08:23:10.28#ibcon#about to read 4, iclass 39, count 2 2006.211.08:23:10.28#ibcon#read 4, iclass 39, count 2 2006.211.08:23:10.28#ibcon#about to read 5, iclass 39, count 2 2006.211.08:23:10.28#ibcon#read 5, iclass 39, count 2 2006.211.08:23:10.28#ibcon#about to read 6, iclass 39, count 2 2006.211.08:23:10.28#ibcon#read 6, iclass 39, count 2 2006.211.08:23:10.28#ibcon#end of sib2, iclass 39, count 2 2006.211.08:23:10.28#ibcon#*after write, iclass 39, count 2 2006.211.08:23:10.28#ibcon#*before return 0, iclass 39, count 2 2006.211.08:23:10.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:23:10.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.211.08:23:10.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.211.08:23:10.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:10.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:23:10.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:23:10.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:23:10.40#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:23:10.40#ibcon#first serial, iclass 39, count 0 2006.211.08:23:10.40#ibcon#enter sib2, iclass 39, count 0 2006.211.08:23:10.40#ibcon#flushed, iclass 39, count 0 2006.211.08:23:10.40#ibcon#about to write, iclass 39, count 0 2006.211.08:23:10.40#ibcon#wrote, iclass 39, count 0 2006.211.08:23:10.40#ibcon#about to read 3, iclass 39, count 0 2006.211.08:23:10.42#ibcon#read 3, iclass 39, count 0 2006.211.08:23:10.42#ibcon#about to read 4, iclass 39, count 0 2006.211.08:23:10.42#ibcon#read 4, iclass 39, count 0 2006.211.08:23:10.42#ibcon#about to read 5, iclass 39, count 0 2006.211.08:23:10.42#ibcon#read 5, iclass 39, count 0 2006.211.08:23:10.42#ibcon#about to read 6, iclass 39, count 0 2006.211.08:23:10.42#ibcon#read 6, iclass 39, count 0 2006.211.08:23:10.42#ibcon#end of sib2, iclass 39, count 0 2006.211.08:23:10.42#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:23:10.42#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:23:10.42#ibcon#[27=USB\r\n] 2006.211.08:23:10.42#ibcon#*before write, iclass 39, count 0 2006.211.08:23:10.42#ibcon#enter sib2, iclass 39, count 0 2006.211.08:23:10.42#ibcon#flushed, iclass 39, count 0 2006.211.08:23:10.42#ibcon#about to write, iclass 39, count 0 2006.211.08:23:10.42#ibcon#wrote, iclass 39, count 0 2006.211.08:23:10.42#ibcon#about to read 3, iclass 39, count 0 2006.211.08:23:10.45#ibcon#read 3, iclass 39, count 0 2006.211.08:23:10.45#ibcon#about to read 4, iclass 39, count 0 2006.211.08:23:10.45#ibcon#read 4, iclass 39, count 0 2006.211.08:23:10.45#ibcon#about to read 5, iclass 39, count 0 2006.211.08:23:10.45#ibcon#read 5, iclass 39, count 0 2006.211.08:23:10.45#ibcon#about to read 6, iclass 39, count 0 2006.211.08:23:10.45#ibcon#read 6, iclass 39, count 0 2006.211.08:23:10.45#ibcon#end of sib2, iclass 39, count 0 2006.211.08:23:10.45#ibcon#*after write, iclass 39, count 0 2006.211.08:23:10.45#ibcon#*before return 0, iclass 39, count 0 2006.211.08:23:10.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:23:10.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.211.08:23:10.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:23:10.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:23:10.45$vc4f8/vblo=2,640.99 2006.211.08:23:10.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.211.08:23:10.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.211.08:23:10.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:10.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:10.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:10.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:10.45#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:23:10.45#ibcon#first serial, iclass 3, count 0 2006.211.08:23:10.45#ibcon#enter sib2, iclass 3, count 0 2006.211.08:23:10.45#ibcon#flushed, iclass 3, count 0 2006.211.08:23:10.45#ibcon#about to write, iclass 3, count 0 2006.211.08:23:10.45#ibcon#wrote, iclass 3, count 0 2006.211.08:23:10.45#ibcon#about to read 3, iclass 3, count 0 2006.211.08:23:10.47#ibcon#read 3, iclass 3, count 0 2006.211.08:23:10.47#ibcon#about to read 4, iclass 3, count 0 2006.211.08:23:10.47#ibcon#read 4, iclass 3, count 0 2006.211.08:23:10.47#ibcon#about to read 5, iclass 3, count 0 2006.211.08:23:10.47#ibcon#read 5, iclass 3, count 0 2006.211.08:23:10.47#ibcon#about to read 6, iclass 3, count 0 2006.211.08:23:10.47#ibcon#read 6, iclass 3, count 0 2006.211.08:23:10.47#ibcon#end of sib2, iclass 3, count 0 2006.211.08:23:10.47#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:23:10.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:23:10.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:23:10.47#ibcon#*before write, iclass 3, count 0 2006.211.08:23:10.47#ibcon#enter sib2, iclass 3, count 0 2006.211.08:23:10.47#ibcon#flushed, iclass 3, count 0 2006.211.08:23:10.47#ibcon#about to write, iclass 3, count 0 2006.211.08:23:10.47#ibcon#wrote, iclass 3, count 0 2006.211.08:23:10.47#ibcon#about to read 3, iclass 3, count 0 2006.211.08:23:10.51#ibcon#read 3, iclass 3, count 0 2006.211.08:23:10.51#ibcon#about to read 4, iclass 3, count 0 2006.211.08:23:10.51#ibcon#read 4, iclass 3, count 0 2006.211.08:23:10.51#ibcon#about to read 5, iclass 3, count 0 2006.211.08:23:10.51#ibcon#read 5, iclass 3, count 0 2006.211.08:23:10.51#ibcon#about to read 6, iclass 3, count 0 2006.211.08:23:10.51#ibcon#read 6, iclass 3, count 0 2006.211.08:23:10.51#ibcon#end of sib2, iclass 3, count 0 2006.211.08:23:10.51#ibcon#*after write, iclass 3, count 0 2006.211.08:23:10.51#ibcon#*before return 0, iclass 3, count 0 2006.211.08:23:10.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:10.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.211.08:23:10.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:23:10.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:23:10.51$vc4f8/vb=2,4 2006.211.08:23:10.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.211.08:23:10.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.211.08:23:10.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:10.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:10.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:10.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:10.57#ibcon#enter wrdev, iclass 5, count 2 2006.211.08:23:10.57#ibcon#first serial, iclass 5, count 2 2006.211.08:23:10.57#ibcon#enter sib2, iclass 5, count 2 2006.211.08:23:10.57#ibcon#flushed, iclass 5, count 2 2006.211.08:23:10.57#ibcon#about to write, iclass 5, count 2 2006.211.08:23:10.57#ibcon#wrote, iclass 5, count 2 2006.211.08:23:10.57#ibcon#about to read 3, iclass 5, count 2 2006.211.08:23:10.59#ibcon#read 3, iclass 5, count 2 2006.211.08:23:10.59#ibcon#about to read 4, iclass 5, count 2 2006.211.08:23:10.59#ibcon#read 4, iclass 5, count 2 2006.211.08:23:10.59#ibcon#about to read 5, iclass 5, count 2 2006.211.08:23:10.59#ibcon#read 5, iclass 5, count 2 2006.211.08:23:10.59#ibcon#about to read 6, iclass 5, count 2 2006.211.08:23:10.59#ibcon#read 6, iclass 5, count 2 2006.211.08:23:10.59#ibcon#end of sib2, iclass 5, count 2 2006.211.08:23:10.59#ibcon#*mode == 0, iclass 5, count 2 2006.211.08:23:10.59#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.211.08:23:10.59#ibcon#[27=AT02-04\r\n] 2006.211.08:23:10.59#ibcon#*before write, iclass 5, count 2 2006.211.08:23:10.59#ibcon#enter sib2, iclass 5, count 2 2006.211.08:23:10.59#ibcon#flushed, iclass 5, count 2 2006.211.08:23:10.59#ibcon#about to write, iclass 5, count 2 2006.211.08:23:10.59#ibcon#wrote, iclass 5, count 2 2006.211.08:23:10.59#ibcon#about to read 3, iclass 5, count 2 2006.211.08:23:10.62#ibcon#read 3, iclass 5, count 2 2006.211.08:23:10.62#ibcon#about to read 4, iclass 5, count 2 2006.211.08:23:10.62#ibcon#read 4, iclass 5, count 2 2006.211.08:23:10.62#ibcon#about to read 5, iclass 5, count 2 2006.211.08:23:10.62#ibcon#read 5, iclass 5, count 2 2006.211.08:23:10.62#ibcon#about to read 6, iclass 5, count 2 2006.211.08:23:10.62#ibcon#read 6, iclass 5, count 2 2006.211.08:23:10.62#ibcon#end of sib2, iclass 5, count 2 2006.211.08:23:10.62#ibcon#*after write, iclass 5, count 2 2006.211.08:23:10.62#ibcon#*before return 0, iclass 5, count 2 2006.211.08:23:10.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:10.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.211.08:23:10.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.211.08:23:10.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:10.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:10.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:10.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:10.74#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:23:10.74#ibcon#first serial, iclass 5, count 0 2006.211.08:23:10.74#ibcon#enter sib2, iclass 5, count 0 2006.211.08:23:10.74#ibcon#flushed, iclass 5, count 0 2006.211.08:23:10.74#ibcon#about to write, iclass 5, count 0 2006.211.08:23:10.74#ibcon#wrote, iclass 5, count 0 2006.211.08:23:10.74#ibcon#about to read 3, iclass 5, count 0 2006.211.08:23:10.76#ibcon#read 3, iclass 5, count 0 2006.211.08:23:10.76#ibcon#about to read 4, iclass 5, count 0 2006.211.08:23:10.76#ibcon#read 4, iclass 5, count 0 2006.211.08:23:10.76#ibcon#about to read 5, iclass 5, count 0 2006.211.08:23:10.76#ibcon#read 5, iclass 5, count 0 2006.211.08:23:10.76#ibcon#about to read 6, iclass 5, count 0 2006.211.08:23:10.76#ibcon#read 6, iclass 5, count 0 2006.211.08:23:10.76#ibcon#end of sib2, iclass 5, count 0 2006.211.08:23:10.76#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:23:10.76#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:23:10.76#ibcon#[27=USB\r\n] 2006.211.08:23:10.76#ibcon#*before write, iclass 5, count 0 2006.211.08:23:10.76#ibcon#enter sib2, iclass 5, count 0 2006.211.08:23:10.76#ibcon#flushed, iclass 5, count 0 2006.211.08:23:10.76#ibcon#about to write, iclass 5, count 0 2006.211.08:23:10.76#ibcon#wrote, iclass 5, count 0 2006.211.08:23:10.76#ibcon#about to read 3, iclass 5, count 0 2006.211.08:23:10.79#ibcon#read 3, iclass 5, count 0 2006.211.08:23:10.79#ibcon#about to read 4, iclass 5, count 0 2006.211.08:23:10.79#ibcon#read 4, iclass 5, count 0 2006.211.08:23:10.79#ibcon#about to read 5, iclass 5, count 0 2006.211.08:23:10.79#ibcon#read 5, iclass 5, count 0 2006.211.08:23:10.79#ibcon#about to read 6, iclass 5, count 0 2006.211.08:23:10.79#ibcon#read 6, iclass 5, count 0 2006.211.08:23:10.79#ibcon#end of sib2, iclass 5, count 0 2006.211.08:23:10.79#ibcon#*after write, iclass 5, count 0 2006.211.08:23:10.79#ibcon#*before return 0, iclass 5, count 0 2006.211.08:23:10.79#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:10.79#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.211.08:23:10.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:23:10.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:23:10.79$vc4f8/vblo=3,656.99 2006.211.08:23:10.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.211.08:23:10.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.211.08:23:10.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:10.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:10.79#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:10.79#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:10.79#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:23:10.79#ibcon#first serial, iclass 7, count 0 2006.211.08:23:10.79#ibcon#enter sib2, iclass 7, count 0 2006.211.08:23:10.79#ibcon#flushed, iclass 7, count 0 2006.211.08:23:10.79#ibcon#about to write, iclass 7, count 0 2006.211.08:23:10.79#ibcon#wrote, iclass 7, count 0 2006.211.08:23:10.79#ibcon#about to read 3, iclass 7, count 0 2006.211.08:23:10.81#ibcon#read 3, iclass 7, count 0 2006.211.08:23:10.81#ibcon#about to read 4, iclass 7, count 0 2006.211.08:23:10.81#ibcon#read 4, iclass 7, count 0 2006.211.08:23:10.81#ibcon#about to read 5, iclass 7, count 0 2006.211.08:23:10.81#ibcon#read 5, iclass 7, count 0 2006.211.08:23:10.81#ibcon#about to read 6, iclass 7, count 0 2006.211.08:23:10.81#ibcon#read 6, iclass 7, count 0 2006.211.08:23:10.81#ibcon#end of sib2, iclass 7, count 0 2006.211.08:23:10.81#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:23:10.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:23:10.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:23:10.81#ibcon#*before write, iclass 7, count 0 2006.211.08:23:10.81#ibcon#enter sib2, iclass 7, count 0 2006.211.08:23:10.81#ibcon#flushed, iclass 7, count 0 2006.211.08:23:10.81#ibcon#about to write, iclass 7, count 0 2006.211.08:23:10.81#ibcon#wrote, iclass 7, count 0 2006.211.08:23:10.81#ibcon#about to read 3, iclass 7, count 0 2006.211.08:23:10.85#ibcon#read 3, iclass 7, count 0 2006.211.08:23:10.85#ibcon#about to read 4, iclass 7, count 0 2006.211.08:23:10.85#ibcon#read 4, iclass 7, count 0 2006.211.08:23:10.85#ibcon#about to read 5, iclass 7, count 0 2006.211.08:23:10.85#ibcon#read 5, iclass 7, count 0 2006.211.08:23:10.85#ibcon#about to read 6, iclass 7, count 0 2006.211.08:23:10.85#ibcon#read 6, iclass 7, count 0 2006.211.08:23:10.85#ibcon#end of sib2, iclass 7, count 0 2006.211.08:23:10.85#ibcon#*after write, iclass 7, count 0 2006.211.08:23:10.85#ibcon#*before return 0, iclass 7, count 0 2006.211.08:23:10.85#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:10.85#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.211.08:23:10.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:23:10.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:23:10.85$vc4f8/vb=3,3 2006.211.08:23:10.85#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.211.08:23:10.85#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.211.08:23:10.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:10.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:10.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:10.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:10.91#ibcon#enter wrdev, iclass 11, count 2 2006.211.08:23:10.91#ibcon#first serial, iclass 11, count 2 2006.211.08:23:10.91#ibcon#enter sib2, iclass 11, count 2 2006.211.08:23:10.91#ibcon#flushed, iclass 11, count 2 2006.211.08:23:10.91#ibcon#about to write, iclass 11, count 2 2006.211.08:23:10.91#ibcon#wrote, iclass 11, count 2 2006.211.08:23:10.91#ibcon#about to read 3, iclass 11, count 2 2006.211.08:23:10.93#ibcon#read 3, iclass 11, count 2 2006.211.08:23:10.93#ibcon#about to read 4, iclass 11, count 2 2006.211.08:23:10.93#ibcon#read 4, iclass 11, count 2 2006.211.08:23:10.93#ibcon#about to read 5, iclass 11, count 2 2006.211.08:23:10.93#ibcon#read 5, iclass 11, count 2 2006.211.08:23:10.93#ibcon#about to read 6, iclass 11, count 2 2006.211.08:23:10.93#ibcon#read 6, iclass 11, count 2 2006.211.08:23:10.93#ibcon#end of sib2, iclass 11, count 2 2006.211.08:23:10.93#ibcon#*mode == 0, iclass 11, count 2 2006.211.08:23:10.93#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.211.08:23:10.93#ibcon#[27=AT03-03\r\n] 2006.211.08:23:10.93#ibcon#*before write, iclass 11, count 2 2006.211.08:23:10.93#ibcon#enter sib2, iclass 11, count 2 2006.211.08:23:10.93#ibcon#flushed, iclass 11, count 2 2006.211.08:23:10.93#ibcon#about to write, iclass 11, count 2 2006.211.08:23:10.93#ibcon#wrote, iclass 11, count 2 2006.211.08:23:10.93#ibcon#about to read 3, iclass 11, count 2 2006.211.08:23:10.96#ibcon#read 3, iclass 11, count 2 2006.211.08:23:10.96#ibcon#about to read 4, iclass 11, count 2 2006.211.08:23:10.96#ibcon#read 4, iclass 11, count 2 2006.211.08:23:10.96#ibcon#about to read 5, iclass 11, count 2 2006.211.08:23:10.96#ibcon#read 5, iclass 11, count 2 2006.211.08:23:10.96#ibcon#about to read 6, iclass 11, count 2 2006.211.08:23:10.96#ibcon#read 6, iclass 11, count 2 2006.211.08:23:10.96#ibcon#end of sib2, iclass 11, count 2 2006.211.08:23:10.96#ibcon#*after write, iclass 11, count 2 2006.211.08:23:10.96#ibcon#*before return 0, iclass 11, count 2 2006.211.08:23:10.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:10.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.211.08:23:10.96#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.211.08:23:10.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:10.96#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:11.08#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:11.08#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:11.08#ibcon#enter wrdev, iclass 11, count 0 2006.211.08:23:11.08#ibcon#first serial, iclass 11, count 0 2006.211.08:23:11.08#ibcon#enter sib2, iclass 11, count 0 2006.211.08:23:11.08#ibcon#flushed, iclass 11, count 0 2006.211.08:23:11.08#ibcon#about to write, iclass 11, count 0 2006.211.08:23:11.08#ibcon#wrote, iclass 11, count 0 2006.211.08:23:11.08#ibcon#about to read 3, iclass 11, count 0 2006.211.08:23:11.10#ibcon#read 3, iclass 11, count 0 2006.211.08:23:11.10#ibcon#about to read 4, iclass 11, count 0 2006.211.08:23:11.10#ibcon#read 4, iclass 11, count 0 2006.211.08:23:11.10#ibcon#about to read 5, iclass 11, count 0 2006.211.08:23:11.10#ibcon#read 5, iclass 11, count 0 2006.211.08:23:11.10#ibcon#about to read 6, iclass 11, count 0 2006.211.08:23:11.10#ibcon#read 6, iclass 11, count 0 2006.211.08:23:11.10#ibcon#end of sib2, iclass 11, count 0 2006.211.08:23:11.10#ibcon#*mode == 0, iclass 11, count 0 2006.211.08:23:11.10#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.08:23:11.10#ibcon#[27=USB\r\n] 2006.211.08:23:11.10#ibcon#*before write, iclass 11, count 0 2006.211.08:23:11.10#ibcon#enter sib2, iclass 11, count 0 2006.211.08:23:11.10#ibcon#flushed, iclass 11, count 0 2006.211.08:23:11.10#ibcon#about to write, iclass 11, count 0 2006.211.08:23:11.10#ibcon#wrote, iclass 11, count 0 2006.211.08:23:11.10#ibcon#about to read 3, iclass 11, count 0 2006.211.08:23:11.13#ibcon#read 3, iclass 11, count 0 2006.211.08:23:11.13#ibcon#about to read 4, iclass 11, count 0 2006.211.08:23:11.13#ibcon#read 4, iclass 11, count 0 2006.211.08:23:11.13#ibcon#about to read 5, iclass 11, count 0 2006.211.08:23:11.13#ibcon#read 5, iclass 11, count 0 2006.211.08:23:11.13#ibcon#about to read 6, iclass 11, count 0 2006.211.08:23:11.13#ibcon#read 6, iclass 11, count 0 2006.211.08:23:11.13#ibcon#end of sib2, iclass 11, count 0 2006.211.08:23:11.13#ibcon#*after write, iclass 11, count 0 2006.211.08:23:11.13#ibcon#*before return 0, iclass 11, count 0 2006.211.08:23:11.13#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:11.13#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.211.08:23:11.13#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.08:23:11.13#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.08:23:11.13$vc4f8/vblo=4,712.99 2006.211.08:23:11.13#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.211.08:23:11.13#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.211.08:23:11.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:11.13#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:11.13#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:11.13#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:11.13#ibcon#enter wrdev, iclass 13, count 0 2006.211.08:23:11.13#ibcon#first serial, iclass 13, count 0 2006.211.08:23:11.13#ibcon#enter sib2, iclass 13, count 0 2006.211.08:23:11.13#ibcon#flushed, iclass 13, count 0 2006.211.08:23:11.13#ibcon#about to write, iclass 13, count 0 2006.211.08:23:11.13#ibcon#wrote, iclass 13, count 0 2006.211.08:23:11.13#ibcon#about to read 3, iclass 13, count 0 2006.211.08:23:11.15#ibcon#read 3, iclass 13, count 0 2006.211.08:23:11.15#ibcon#about to read 4, iclass 13, count 0 2006.211.08:23:11.15#ibcon#read 4, iclass 13, count 0 2006.211.08:23:11.15#ibcon#about to read 5, iclass 13, count 0 2006.211.08:23:11.15#ibcon#read 5, iclass 13, count 0 2006.211.08:23:11.15#ibcon#about to read 6, iclass 13, count 0 2006.211.08:23:11.15#ibcon#read 6, iclass 13, count 0 2006.211.08:23:11.15#ibcon#end of sib2, iclass 13, count 0 2006.211.08:23:11.15#ibcon#*mode == 0, iclass 13, count 0 2006.211.08:23:11.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.08:23:11.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:23:11.15#ibcon#*before write, iclass 13, count 0 2006.211.08:23:11.15#ibcon#enter sib2, iclass 13, count 0 2006.211.08:23:11.15#ibcon#flushed, iclass 13, count 0 2006.211.08:23:11.15#ibcon#about to write, iclass 13, count 0 2006.211.08:23:11.15#ibcon#wrote, iclass 13, count 0 2006.211.08:23:11.15#ibcon#about to read 3, iclass 13, count 0 2006.211.08:23:11.19#ibcon#read 3, iclass 13, count 0 2006.211.08:23:11.19#ibcon#about to read 4, iclass 13, count 0 2006.211.08:23:11.19#ibcon#read 4, iclass 13, count 0 2006.211.08:23:11.19#ibcon#about to read 5, iclass 13, count 0 2006.211.08:23:11.19#ibcon#read 5, iclass 13, count 0 2006.211.08:23:11.19#ibcon#about to read 6, iclass 13, count 0 2006.211.08:23:11.19#ibcon#read 6, iclass 13, count 0 2006.211.08:23:11.19#ibcon#end of sib2, iclass 13, count 0 2006.211.08:23:11.19#ibcon#*after write, iclass 13, count 0 2006.211.08:23:11.19#ibcon#*before return 0, iclass 13, count 0 2006.211.08:23:11.19#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:11.19#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.211.08:23:11.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.08:23:11.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.08:23:11.19$vc4f8/vb=4,3 2006.211.08:23:11.19#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.211.08:23:11.19#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.211.08:23:11.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:11.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:11.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:11.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:11.25#ibcon#enter wrdev, iclass 15, count 2 2006.211.08:23:11.25#ibcon#first serial, iclass 15, count 2 2006.211.08:23:11.25#ibcon#enter sib2, iclass 15, count 2 2006.211.08:23:11.25#ibcon#flushed, iclass 15, count 2 2006.211.08:23:11.25#ibcon#about to write, iclass 15, count 2 2006.211.08:23:11.25#ibcon#wrote, iclass 15, count 2 2006.211.08:23:11.25#ibcon#about to read 3, iclass 15, count 2 2006.211.08:23:11.27#ibcon#read 3, iclass 15, count 2 2006.211.08:23:11.27#ibcon#about to read 4, iclass 15, count 2 2006.211.08:23:11.27#ibcon#read 4, iclass 15, count 2 2006.211.08:23:11.27#ibcon#about to read 5, iclass 15, count 2 2006.211.08:23:11.27#ibcon#read 5, iclass 15, count 2 2006.211.08:23:11.27#ibcon#about to read 6, iclass 15, count 2 2006.211.08:23:11.27#ibcon#read 6, iclass 15, count 2 2006.211.08:23:11.27#ibcon#end of sib2, iclass 15, count 2 2006.211.08:23:11.27#ibcon#*mode == 0, iclass 15, count 2 2006.211.08:23:11.27#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.211.08:23:11.27#ibcon#[27=AT04-03\r\n] 2006.211.08:23:11.27#ibcon#*before write, iclass 15, count 2 2006.211.08:23:11.27#ibcon#enter sib2, iclass 15, count 2 2006.211.08:23:11.27#ibcon#flushed, iclass 15, count 2 2006.211.08:23:11.27#ibcon#about to write, iclass 15, count 2 2006.211.08:23:11.27#ibcon#wrote, iclass 15, count 2 2006.211.08:23:11.27#ibcon#about to read 3, iclass 15, count 2 2006.211.08:23:11.30#ibcon#read 3, iclass 15, count 2 2006.211.08:23:11.30#ibcon#about to read 4, iclass 15, count 2 2006.211.08:23:11.30#ibcon#read 4, iclass 15, count 2 2006.211.08:23:11.30#ibcon#about to read 5, iclass 15, count 2 2006.211.08:23:11.30#ibcon#read 5, iclass 15, count 2 2006.211.08:23:11.30#ibcon#about to read 6, iclass 15, count 2 2006.211.08:23:11.30#ibcon#read 6, iclass 15, count 2 2006.211.08:23:11.30#ibcon#end of sib2, iclass 15, count 2 2006.211.08:23:11.30#ibcon#*after write, iclass 15, count 2 2006.211.08:23:11.30#ibcon#*before return 0, iclass 15, count 2 2006.211.08:23:11.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:11.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.211.08:23:11.30#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.211.08:23:11.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:11.30#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:11.42#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:11.42#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:11.42#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:23:11.42#ibcon#first serial, iclass 15, count 0 2006.211.08:23:11.42#ibcon#enter sib2, iclass 15, count 0 2006.211.08:23:11.42#ibcon#flushed, iclass 15, count 0 2006.211.08:23:11.42#ibcon#about to write, iclass 15, count 0 2006.211.08:23:11.42#ibcon#wrote, iclass 15, count 0 2006.211.08:23:11.42#ibcon#about to read 3, iclass 15, count 0 2006.211.08:23:11.44#ibcon#read 3, iclass 15, count 0 2006.211.08:23:11.44#ibcon#about to read 4, iclass 15, count 0 2006.211.08:23:11.44#ibcon#read 4, iclass 15, count 0 2006.211.08:23:11.44#ibcon#about to read 5, iclass 15, count 0 2006.211.08:23:11.44#ibcon#read 5, iclass 15, count 0 2006.211.08:23:11.44#ibcon#about to read 6, iclass 15, count 0 2006.211.08:23:11.44#ibcon#read 6, iclass 15, count 0 2006.211.08:23:11.44#ibcon#end of sib2, iclass 15, count 0 2006.211.08:23:11.44#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:23:11.44#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:23:11.44#ibcon#[27=USB\r\n] 2006.211.08:23:11.44#ibcon#*before write, iclass 15, count 0 2006.211.08:23:11.44#ibcon#enter sib2, iclass 15, count 0 2006.211.08:23:11.44#ibcon#flushed, iclass 15, count 0 2006.211.08:23:11.44#ibcon#about to write, iclass 15, count 0 2006.211.08:23:11.44#ibcon#wrote, iclass 15, count 0 2006.211.08:23:11.44#ibcon#about to read 3, iclass 15, count 0 2006.211.08:23:11.47#ibcon#read 3, iclass 15, count 0 2006.211.08:23:11.47#ibcon#about to read 4, iclass 15, count 0 2006.211.08:23:11.47#ibcon#read 4, iclass 15, count 0 2006.211.08:23:11.47#ibcon#about to read 5, iclass 15, count 0 2006.211.08:23:11.47#ibcon#read 5, iclass 15, count 0 2006.211.08:23:11.47#ibcon#about to read 6, iclass 15, count 0 2006.211.08:23:11.47#ibcon#read 6, iclass 15, count 0 2006.211.08:23:11.47#ibcon#end of sib2, iclass 15, count 0 2006.211.08:23:11.47#ibcon#*after write, iclass 15, count 0 2006.211.08:23:11.47#ibcon#*before return 0, iclass 15, count 0 2006.211.08:23:11.47#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:11.47#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.211.08:23:11.47#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:23:11.47#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:23:11.47$vc4f8/vblo=5,744.99 2006.211.08:23:11.47#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.211.08:23:11.47#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.211.08:23:11.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:11.47#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:11.47#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:11.47#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:11.47#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:23:11.47#ibcon#first serial, iclass 17, count 0 2006.211.08:23:11.47#ibcon#enter sib2, iclass 17, count 0 2006.211.08:23:11.47#ibcon#flushed, iclass 17, count 0 2006.211.08:23:11.47#ibcon#about to write, iclass 17, count 0 2006.211.08:23:11.47#ibcon#wrote, iclass 17, count 0 2006.211.08:23:11.47#ibcon#about to read 3, iclass 17, count 0 2006.211.08:23:11.49#ibcon#read 3, iclass 17, count 0 2006.211.08:23:11.49#ibcon#about to read 4, iclass 17, count 0 2006.211.08:23:11.49#ibcon#read 4, iclass 17, count 0 2006.211.08:23:11.49#ibcon#about to read 5, iclass 17, count 0 2006.211.08:23:11.49#ibcon#read 5, iclass 17, count 0 2006.211.08:23:11.49#ibcon#about to read 6, iclass 17, count 0 2006.211.08:23:11.49#ibcon#read 6, iclass 17, count 0 2006.211.08:23:11.49#ibcon#end of sib2, iclass 17, count 0 2006.211.08:23:11.49#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:23:11.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:23:11.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:23:11.49#ibcon#*before write, iclass 17, count 0 2006.211.08:23:11.49#ibcon#enter sib2, iclass 17, count 0 2006.211.08:23:11.49#ibcon#flushed, iclass 17, count 0 2006.211.08:23:11.49#ibcon#about to write, iclass 17, count 0 2006.211.08:23:11.49#ibcon#wrote, iclass 17, count 0 2006.211.08:23:11.49#ibcon#about to read 3, iclass 17, count 0 2006.211.08:23:11.53#ibcon#read 3, iclass 17, count 0 2006.211.08:23:11.53#ibcon#about to read 4, iclass 17, count 0 2006.211.08:23:11.53#ibcon#read 4, iclass 17, count 0 2006.211.08:23:11.53#ibcon#about to read 5, iclass 17, count 0 2006.211.08:23:11.53#ibcon#read 5, iclass 17, count 0 2006.211.08:23:11.53#ibcon#about to read 6, iclass 17, count 0 2006.211.08:23:11.53#ibcon#read 6, iclass 17, count 0 2006.211.08:23:11.53#ibcon#end of sib2, iclass 17, count 0 2006.211.08:23:11.53#ibcon#*after write, iclass 17, count 0 2006.211.08:23:11.53#ibcon#*before return 0, iclass 17, count 0 2006.211.08:23:11.53#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:11.53#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.211.08:23:11.53#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:23:11.53#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:23:11.53$vc4f8/vb=5,3 2006.211.08:23:11.53#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.211.08:23:11.53#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.211.08:23:11.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:11.53#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:11.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:11.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:11.59#ibcon#enter wrdev, iclass 19, count 2 2006.211.08:23:11.59#ibcon#first serial, iclass 19, count 2 2006.211.08:23:11.59#ibcon#enter sib2, iclass 19, count 2 2006.211.08:23:11.59#ibcon#flushed, iclass 19, count 2 2006.211.08:23:11.59#ibcon#about to write, iclass 19, count 2 2006.211.08:23:11.59#ibcon#wrote, iclass 19, count 2 2006.211.08:23:11.59#ibcon#about to read 3, iclass 19, count 2 2006.211.08:23:11.61#ibcon#read 3, iclass 19, count 2 2006.211.08:23:11.61#ibcon#about to read 4, iclass 19, count 2 2006.211.08:23:11.61#ibcon#read 4, iclass 19, count 2 2006.211.08:23:11.61#ibcon#about to read 5, iclass 19, count 2 2006.211.08:23:11.61#ibcon#read 5, iclass 19, count 2 2006.211.08:23:11.61#ibcon#about to read 6, iclass 19, count 2 2006.211.08:23:11.61#ibcon#read 6, iclass 19, count 2 2006.211.08:23:11.61#ibcon#end of sib2, iclass 19, count 2 2006.211.08:23:11.61#ibcon#*mode == 0, iclass 19, count 2 2006.211.08:23:11.61#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.211.08:23:11.61#ibcon#[27=AT05-03\r\n] 2006.211.08:23:11.61#ibcon#*before write, iclass 19, count 2 2006.211.08:23:11.61#ibcon#enter sib2, iclass 19, count 2 2006.211.08:23:11.61#ibcon#flushed, iclass 19, count 2 2006.211.08:23:11.61#ibcon#about to write, iclass 19, count 2 2006.211.08:23:11.61#ibcon#wrote, iclass 19, count 2 2006.211.08:23:11.61#ibcon#about to read 3, iclass 19, count 2 2006.211.08:23:11.64#ibcon#read 3, iclass 19, count 2 2006.211.08:23:11.64#ibcon#about to read 4, iclass 19, count 2 2006.211.08:23:11.64#ibcon#read 4, iclass 19, count 2 2006.211.08:23:11.64#ibcon#about to read 5, iclass 19, count 2 2006.211.08:23:11.64#ibcon#read 5, iclass 19, count 2 2006.211.08:23:11.64#ibcon#about to read 6, iclass 19, count 2 2006.211.08:23:11.64#ibcon#read 6, iclass 19, count 2 2006.211.08:23:11.64#ibcon#end of sib2, iclass 19, count 2 2006.211.08:23:11.64#ibcon#*after write, iclass 19, count 2 2006.211.08:23:11.64#ibcon#*before return 0, iclass 19, count 2 2006.211.08:23:11.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:11.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.211.08:23:11.64#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.211.08:23:11.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:11.64#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:11.76#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:11.76#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:11.76#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:23:11.76#ibcon#first serial, iclass 19, count 0 2006.211.08:23:11.76#ibcon#enter sib2, iclass 19, count 0 2006.211.08:23:11.76#ibcon#flushed, iclass 19, count 0 2006.211.08:23:11.76#ibcon#about to write, iclass 19, count 0 2006.211.08:23:11.76#ibcon#wrote, iclass 19, count 0 2006.211.08:23:11.76#ibcon#about to read 3, iclass 19, count 0 2006.211.08:23:11.78#ibcon#read 3, iclass 19, count 0 2006.211.08:23:11.78#ibcon#about to read 4, iclass 19, count 0 2006.211.08:23:11.78#ibcon#read 4, iclass 19, count 0 2006.211.08:23:11.78#ibcon#about to read 5, iclass 19, count 0 2006.211.08:23:11.78#ibcon#read 5, iclass 19, count 0 2006.211.08:23:11.78#ibcon#about to read 6, iclass 19, count 0 2006.211.08:23:11.78#ibcon#read 6, iclass 19, count 0 2006.211.08:23:11.78#ibcon#end of sib2, iclass 19, count 0 2006.211.08:23:11.78#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:23:11.78#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:23:11.78#ibcon#[27=USB\r\n] 2006.211.08:23:11.78#ibcon#*before write, iclass 19, count 0 2006.211.08:23:11.78#ibcon#enter sib2, iclass 19, count 0 2006.211.08:23:11.78#ibcon#flushed, iclass 19, count 0 2006.211.08:23:11.78#ibcon#about to write, iclass 19, count 0 2006.211.08:23:11.78#ibcon#wrote, iclass 19, count 0 2006.211.08:23:11.78#ibcon#about to read 3, iclass 19, count 0 2006.211.08:23:11.81#ibcon#read 3, iclass 19, count 0 2006.211.08:23:11.81#ibcon#about to read 4, iclass 19, count 0 2006.211.08:23:11.81#ibcon#read 4, iclass 19, count 0 2006.211.08:23:11.81#ibcon#about to read 5, iclass 19, count 0 2006.211.08:23:11.81#ibcon#read 5, iclass 19, count 0 2006.211.08:23:11.81#ibcon#about to read 6, iclass 19, count 0 2006.211.08:23:11.81#ibcon#read 6, iclass 19, count 0 2006.211.08:23:11.81#ibcon#end of sib2, iclass 19, count 0 2006.211.08:23:11.81#ibcon#*after write, iclass 19, count 0 2006.211.08:23:11.81#ibcon#*before return 0, iclass 19, count 0 2006.211.08:23:11.81#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:11.81#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.211.08:23:11.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:23:11.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:23:11.81$vc4f8/vblo=6,752.99 2006.211.08:23:11.81#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.211.08:23:11.81#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.211.08:23:11.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:23:11.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:11.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:11.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:11.81#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:23:11.81#ibcon#first serial, iclass 21, count 0 2006.211.08:23:11.81#ibcon#enter sib2, iclass 21, count 0 2006.211.08:23:11.81#ibcon#flushed, iclass 21, count 0 2006.211.08:23:11.81#ibcon#about to write, iclass 21, count 0 2006.211.08:23:11.81#ibcon#wrote, iclass 21, count 0 2006.211.08:23:11.81#ibcon#about to read 3, iclass 21, count 0 2006.211.08:23:11.83#ibcon#read 3, iclass 21, count 0 2006.211.08:23:11.83#ibcon#about to read 4, iclass 21, count 0 2006.211.08:23:11.83#ibcon#read 4, iclass 21, count 0 2006.211.08:23:11.83#ibcon#about to read 5, iclass 21, count 0 2006.211.08:23:11.83#ibcon#read 5, iclass 21, count 0 2006.211.08:23:11.83#ibcon#about to read 6, iclass 21, count 0 2006.211.08:23:11.83#ibcon#read 6, iclass 21, count 0 2006.211.08:23:11.83#ibcon#end of sib2, iclass 21, count 0 2006.211.08:23:11.83#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:23:11.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:23:11.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:23:11.83#ibcon#*before write, iclass 21, count 0 2006.211.08:23:11.83#ibcon#enter sib2, iclass 21, count 0 2006.211.08:23:11.83#ibcon#flushed, iclass 21, count 0 2006.211.08:23:11.83#ibcon#about to write, iclass 21, count 0 2006.211.08:23:11.83#ibcon#wrote, iclass 21, count 0 2006.211.08:23:11.83#ibcon#about to read 3, iclass 21, count 0 2006.211.08:23:11.87#ibcon#read 3, iclass 21, count 0 2006.211.08:23:11.87#ibcon#about to read 4, iclass 21, count 0 2006.211.08:23:11.87#ibcon#read 4, iclass 21, count 0 2006.211.08:23:11.87#ibcon#about to read 5, iclass 21, count 0 2006.211.08:23:11.87#ibcon#read 5, iclass 21, count 0 2006.211.08:23:11.87#ibcon#about to read 6, iclass 21, count 0 2006.211.08:23:11.87#ibcon#read 6, iclass 21, count 0 2006.211.08:23:11.87#ibcon#end of sib2, iclass 21, count 0 2006.211.08:23:11.87#ibcon#*after write, iclass 21, count 0 2006.211.08:23:11.87#ibcon#*before return 0, iclass 21, count 0 2006.211.08:23:11.87#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:11.87#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.211.08:23:11.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:23:11.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:23:11.87$vc4f8/vb=6,3 2006.211.08:23:11.87#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.211.08:23:11.87#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.211.08:23:11.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:23:11.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:11.93#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:11.93#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:11.93#ibcon#enter wrdev, iclass 23, count 2 2006.211.08:23:11.93#ibcon#first serial, iclass 23, count 2 2006.211.08:23:11.93#ibcon#enter sib2, iclass 23, count 2 2006.211.08:23:11.93#ibcon#flushed, iclass 23, count 2 2006.211.08:23:11.93#ibcon#about to write, iclass 23, count 2 2006.211.08:23:11.93#ibcon#wrote, iclass 23, count 2 2006.211.08:23:11.93#ibcon#about to read 3, iclass 23, count 2 2006.211.08:23:11.95#ibcon#read 3, iclass 23, count 2 2006.211.08:23:11.95#ibcon#about to read 4, iclass 23, count 2 2006.211.08:23:11.95#ibcon#read 4, iclass 23, count 2 2006.211.08:23:11.95#ibcon#about to read 5, iclass 23, count 2 2006.211.08:23:11.95#ibcon#read 5, iclass 23, count 2 2006.211.08:23:11.95#ibcon#about to read 6, iclass 23, count 2 2006.211.08:23:11.95#ibcon#read 6, iclass 23, count 2 2006.211.08:23:11.95#ibcon#end of sib2, iclass 23, count 2 2006.211.08:23:11.95#ibcon#*mode == 0, iclass 23, count 2 2006.211.08:23:11.95#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.211.08:23:11.95#ibcon#[27=AT06-03\r\n] 2006.211.08:23:11.95#ibcon#*before write, iclass 23, count 2 2006.211.08:23:11.95#ibcon#enter sib2, iclass 23, count 2 2006.211.08:23:11.95#ibcon#flushed, iclass 23, count 2 2006.211.08:23:11.95#ibcon#about to write, iclass 23, count 2 2006.211.08:23:11.95#ibcon#wrote, iclass 23, count 2 2006.211.08:23:11.95#ibcon#about to read 3, iclass 23, count 2 2006.211.08:23:11.98#ibcon#read 3, iclass 23, count 2 2006.211.08:23:11.98#ibcon#about to read 4, iclass 23, count 2 2006.211.08:23:11.98#ibcon#read 4, iclass 23, count 2 2006.211.08:23:11.98#ibcon#about to read 5, iclass 23, count 2 2006.211.08:23:11.98#ibcon#read 5, iclass 23, count 2 2006.211.08:23:11.98#ibcon#about to read 6, iclass 23, count 2 2006.211.08:23:11.98#ibcon#read 6, iclass 23, count 2 2006.211.08:23:11.98#ibcon#end of sib2, iclass 23, count 2 2006.211.08:23:11.98#ibcon#*after write, iclass 23, count 2 2006.211.08:23:11.98#ibcon#*before return 0, iclass 23, count 2 2006.211.08:23:11.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:11.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.211.08:23:11.98#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.211.08:23:11.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:23:11.98#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:12.10#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:12.10#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:12.10#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:23:12.10#ibcon#first serial, iclass 23, count 0 2006.211.08:23:12.10#ibcon#enter sib2, iclass 23, count 0 2006.211.08:23:12.10#ibcon#flushed, iclass 23, count 0 2006.211.08:23:12.10#ibcon#about to write, iclass 23, count 0 2006.211.08:23:12.10#ibcon#wrote, iclass 23, count 0 2006.211.08:23:12.10#ibcon#about to read 3, iclass 23, count 0 2006.211.08:23:12.12#ibcon#read 3, iclass 23, count 0 2006.211.08:23:12.12#ibcon#about to read 4, iclass 23, count 0 2006.211.08:23:12.12#ibcon#read 4, iclass 23, count 0 2006.211.08:23:12.12#ibcon#about to read 5, iclass 23, count 0 2006.211.08:23:12.12#ibcon#read 5, iclass 23, count 0 2006.211.08:23:12.12#ibcon#about to read 6, iclass 23, count 0 2006.211.08:23:12.12#ibcon#read 6, iclass 23, count 0 2006.211.08:23:12.12#ibcon#end of sib2, iclass 23, count 0 2006.211.08:23:12.12#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:23:12.12#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:23:12.12#ibcon#[27=USB\r\n] 2006.211.08:23:12.12#ibcon#*before write, iclass 23, count 0 2006.211.08:23:12.12#ibcon#enter sib2, iclass 23, count 0 2006.211.08:23:12.12#ibcon#flushed, iclass 23, count 0 2006.211.08:23:12.12#ibcon#about to write, iclass 23, count 0 2006.211.08:23:12.12#ibcon#wrote, iclass 23, count 0 2006.211.08:23:12.12#ibcon#about to read 3, iclass 23, count 0 2006.211.08:23:12.15#ibcon#read 3, iclass 23, count 0 2006.211.08:23:12.15#ibcon#about to read 4, iclass 23, count 0 2006.211.08:23:12.15#ibcon#read 4, iclass 23, count 0 2006.211.08:23:12.15#ibcon#about to read 5, iclass 23, count 0 2006.211.08:23:12.15#ibcon#read 5, iclass 23, count 0 2006.211.08:23:12.15#ibcon#about to read 6, iclass 23, count 0 2006.211.08:23:12.15#ibcon#read 6, iclass 23, count 0 2006.211.08:23:12.15#ibcon#end of sib2, iclass 23, count 0 2006.211.08:23:12.15#ibcon#*after write, iclass 23, count 0 2006.211.08:23:12.15#ibcon#*before return 0, iclass 23, count 0 2006.211.08:23:12.15#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:12.15#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.211.08:23:12.15#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:23:12.15#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:23:12.15$vc4f8/vabw=wide 2006.211.08:23:12.15#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.211.08:23:12.15#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.211.08:23:12.15#ibcon#ireg 8 cls_cnt 0 2006.211.08:23:12.15#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:12.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:12.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:12.15#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:23:12.15#ibcon#first serial, iclass 25, count 0 2006.211.08:23:12.15#ibcon#enter sib2, iclass 25, count 0 2006.211.08:23:12.15#ibcon#flushed, iclass 25, count 0 2006.211.08:23:12.15#ibcon#about to write, iclass 25, count 0 2006.211.08:23:12.15#ibcon#wrote, iclass 25, count 0 2006.211.08:23:12.15#ibcon#about to read 3, iclass 25, count 0 2006.211.08:23:12.17#ibcon#read 3, iclass 25, count 0 2006.211.08:23:12.17#ibcon#about to read 4, iclass 25, count 0 2006.211.08:23:12.17#ibcon#read 4, iclass 25, count 0 2006.211.08:23:12.17#ibcon#about to read 5, iclass 25, count 0 2006.211.08:23:12.17#ibcon#read 5, iclass 25, count 0 2006.211.08:23:12.17#ibcon#about to read 6, iclass 25, count 0 2006.211.08:23:12.17#ibcon#read 6, iclass 25, count 0 2006.211.08:23:12.17#ibcon#end of sib2, iclass 25, count 0 2006.211.08:23:12.17#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:23:12.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:23:12.17#ibcon#[25=BW32\r\n] 2006.211.08:23:12.17#ibcon#*before write, iclass 25, count 0 2006.211.08:23:12.17#ibcon#enter sib2, iclass 25, count 0 2006.211.08:23:12.17#ibcon#flushed, iclass 25, count 0 2006.211.08:23:12.17#ibcon#about to write, iclass 25, count 0 2006.211.08:23:12.17#ibcon#wrote, iclass 25, count 0 2006.211.08:23:12.17#ibcon#about to read 3, iclass 25, count 0 2006.211.08:23:12.20#ibcon#read 3, iclass 25, count 0 2006.211.08:23:12.20#ibcon#about to read 4, iclass 25, count 0 2006.211.08:23:12.20#ibcon#read 4, iclass 25, count 0 2006.211.08:23:12.20#ibcon#about to read 5, iclass 25, count 0 2006.211.08:23:12.20#ibcon#read 5, iclass 25, count 0 2006.211.08:23:12.20#ibcon#about to read 6, iclass 25, count 0 2006.211.08:23:12.20#ibcon#read 6, iclass 25, count 0 2006.211.08:23:12.20#ibcon#end of sib2, iclass 25, count 0 2006.211.08:23:12.20#ibcon#*after write, iclass 25, count 0 2006.211.08:23:12.20#ibcon#*before return 0, iclass 25, count 0 2006.211.08:23:12.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:12.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.211.08:23:12.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:23:12.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:23:12.20$vc4f8/vbbw=wide 2006.211.08:23:12.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.08:23:12.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.08:23:12.20#ibcon#ireg 8 cls_cnt 0 2006.211.08:23:12.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:23:12.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:23:12.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:23:12.27#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:23:12.27#ibcon#first serial, iclass 27, count 0 2006.211.08:23:12.27#ibcon#enter sib2, iclass 27, count 0 2006.211.08:23:12.27#ibcon#flushed, iclass 27, count 0 2006.211.08:23:12.27#ibcon#about to write, iclass 27, count 0 2006.211.08:23:12.27#ibcon#wrote, iclass 27, count 0 2006.211.08:23:12.27#ibcon#about to read 3, iclass 27, count 0 2006.211.08:23:12.29#ibcon#read 3, iclass 27, count 0 2006.211.08:23:12.29#ibcon#about to read 4, iclass 27, count 0 2006.211.08:23:12.29#ibcon#read 4, iclass 27, count 0 2006.211.08:23:12.29#ibcon#about to read 5, iclass 27, count 0 2006.211.08:23:12.29#ibcon#read 5, iclass 27, count 0 2006.211.08:23:12.29#ibcon#about to read 6, iclass 27, count 0 2006.211.08:23:12.29#ibcon#read 6, iclass 27, count 0 2006.211.08:23:12.29#ibcon#end of sib2, iclass 27, count 0 2006.211.08:23:12.29#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:23:12.29#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:23:12.29#ibcon#[27=BW32\r\n] 2006.211.08:23:12.29#ibcon#*before write, iclass 27, count 0 2006.211.08:23:12.29#ibcon#enter sib2, iclass 27, count 0 2006.211.08:23:12.29#ibcon#flushed, iclass 27, count 0 2006.211.08:23:12.29#ibcon#about to write, iclass 27, count 0 2006.211.08:23:12.29#ibcon#wrote, iclass 27, count 0 2006.211.08:23:12.29#ibcon#about to read 3, iclass 27, count 0 2006.211.08:23:12.32#ibcon#read 3, iclass 27, count 0 2006.211.08:23:12.32#ibcon#about to read 4, iclass 27, count 0 2006.211.08:23:12.32#ibcon#read 4, iclass 27, count 0 2006.211.08:23:12.32#ibcon#about to read 5, iclass 27, count 0 2006.211.08:23:12.32#ibcon#read 5, iclass 27, count 0 2006.211.08:23:12.32#ibcon#about to read 6, iclass 27, count 0 2006.211.08:23:12.32#ibcon#read 6, iclass 27, count 0 2006.211.08:23:12.32#ibcon#end of sib2, iclass 27, count 0 2006.211.08:23:12.32#ibcon#*after write, iclass 27, count 0 2006.211.08:23:12.32#ibcon#*before return 0, iclass 27, count 0 2006.211.08:23:12.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:23:12.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:23:12.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:23:12.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:23:12.32$4f8m12a/ifd4f 2006.211.08:23:12.32$ifd4f/lo= 2006.211.08:23:12.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:23:12.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:23:12.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:23:12.32$ifd4f/patch= 2006.211.08:23:12.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:23:12.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:23:12.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:23:12.32$4f8m12a/"form=m,16.000,1:2 2006.211.08:23:12.32$4f8m12a/"tpicd 2006.211.08:23:12.32$4f8m12a/echo=off 2006.211.08:23:12.32$4f8m12a/xlog=off 2006.211.08:23:12.32:!2006.211.08:25:20 2006.211.08:23:41.14#trakl#Source acquired 2006.211.08:23:43.14#flagr#flagr/antenna,acquired 2006.211.08:24:38.14#trakl#Off source 2006.211.08:24:38.14?ERROR st -7 Antenna off-source! 2006.211.08:24:38.14#trakl#az 18.035 el 87.647 azerr*cos(el) 0.0028 elerr -0.0164 2006.211.08:24:40.14#flagr#flagr/antenna,off-source 2006.211.08:24:44.14#trakl#Source re-acquired 2006.211.08:24:46.14#flagr#flagr/antenna,re-acquired 2006.211.08:24:57.14#trakl#Off source 2006.211.08:24:57.14?ERROR st -7 Antenna off-source! 2006.211.08:24:57.14#trakl#az 16.587 el 87.667 azerr*cos(el) 0.0030 elerr -0.0197 2006.211.08:24:58.14#flagr#flagr/antenna,off-source 2006.211.08:25:04.14#trakl#Source re-acquired 2006.211.08:25:04.14#flagr#flagr/antenna,re-acquired 2006.211.08:25:20.00:preob 2006.211.08:25:20.14/onsource/TRACKING 2006.211.08:25:20.14:!2006.211.08:25:30 2006.211.08:25:30.00:data_valid=on 2006.211.08:25:30.00:midob 2006.211.08:25:31.14/onsource/TRACKING 2006.211.08:25:31.14/wx/24.17,1010.2,81 2006.211.08:25:31.26/cable/+6.4391E-03 2006.211.08:25:32.35/va/01,08,usb,yes,28,29 2006.211.08:25:32.35/va/02,07,usb,yes,28,29 2006.211.08:25:32.35/va/03,06,usb,yes,29,30 2006.211.08:25:32.35/va/04,07,usb,yes,29,31 2006.211.08:25:32.35/va/05,07,usb,yes,31,33 2006.211.08:25:32.35/va/06,06,usb,yes,30,30 2006.211.08:25:32.35/va/07,06,usb,yes,31,30 2006.211.08:25:32.35/va/08,07,usb,yes,29,28 2006.211.08:25:32.58/valo/01,532.99,yes,locked 2006.211.08:25:32.58/valo/02,572.99,yes,locked 2006.211.08:25:32.58/valo/03,672.99,yes,locked 2006.211.08:25:32.58/valo/04,832.99,yes,locked 2006.211.08:25:32.58/valo/05,652.99,yes,locked 2006.211.08:25:32.58/valo/06,772.99,yes,locked 2006.211.08:25:32.58/valo/07,832.99,yes,locked 2006.211.08:25:32.58/valo/08,852.99,yes,locked 2006.211.08:25:33.67/vb/01,04,usb,yes,28,27 2006.211.08:25:33.67/vb/02,04,usb,yes,30,31 2006.211.08:25:33.67/vb/03,03,usb,yes,33,37 2006.211.08:25:33.67/vb/04,03,usb,yes,34,34 2006.211.08:25:33.67/vb/05,03,usb,yes,32,36 2006.211.08:25:33.67/vb/06,03,usb,yes,33,36 2006.211.08:25:33.67/vb/07,04,usb,yes,28,28 2006.211.08:25:33.67/vb/08,03,usb,yes,33,36 2006.211.08:25:33.91/vblo/01,632.99,yes,locked 2006.211.08:25:33.91/vblo/02,640.99,yes,locked 2006.211.08:25:33.91/vblo/03,656.99,yes,locked 2006.211.08:25:33.91/vblo/04,712.99,yes,locked 2006.211.08:25:33.91/vblo/05,744.99,yes,locked 2006.211.08:25:33.91/vblo/06,752.99,yes,locked 2006.211.08:25:33.91/vblo/07,734.99,yes,locked 2006.211.08:25:33.91/vblo/08,744.99,yes,locked 2006.211.08:25:34.06/vabw/8 2006.211.08:25:34.21/vbbw/8 2006.211.08:25:34.30/xfe/off,on,11.7 2006.211.08:25:34.67/ifatt/23,28,28,28 2006.211.08:25:35.08/fmout-gps/S +4.41E-07 2006.211.08:25:35.12:!2006.211.08:26:30 2006.211.08:26:30.01:data_valid=off 2006.211.08:26:30.01:postob 2006.211.08:26:30.14/cable/+6.4408E-03 2006.211.08:26:30.14/wx/24.14,1010.3,82 2006.211.08:26:31.08/fmout-gps/S +4.42E-07 2006.211.08:26:31.08:scan_name=211-0829,k06211,60 2006.211.08:26:31.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.211.08:26:31.14#flagr#flagr/antenna,new-source 2006.211.08:26:32.14:checkk5 2006.211.08:26:32.47/chk_autoobs//k5ts1/ autoobs is running! 2006.211.08:26:32.81/chk_autoobs//k5ts2/ autoobs is running! 2006.211.08:26:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.211.08:26:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.211.08:26:33.84/chk_obsdata//k5ts1/T2110825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:26:34.17/chk_obsdata//k5ts2/T2110825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:26:34.50/chk_obsdata//k5ts3/T2110825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:26:34.83/chk_obsdata//k5ts4/T2110825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:26:35.49/k5log//k5ts1_log_newline 2006.211.08:26:36.15/k5log//k5ts2_log_newline 2006.211.08:26:36.80/k5log//k5ts3_log_newline 2006.211.08:26:37.46/k5log//k5ts4_log_newline 2006.211.08:26:37.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:26:37.49:4f8m12a=3 2006.211.08:26:37.49$4f8m12a/echo=on 2006.211.08:26:37.49$4f8m12a/pcalon 2006.211.08:26:37.49$pcalon/"no phase cal control is implemented here 2006.211.08:26:37.49$4f8m12a/"tpicd=stop 2006.211.08:26:37.49$4f8m12a/vc4f8 2006.211.08:26:37.49$vc4f8/valo=1,532.99 2006.211.08:26:37.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:26:37.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:26:37.50#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:37.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:37.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:37.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:37.50#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:26:37.50#ibcon#first serial, iclass 4, count 0 2006.211.08:26:37.50#ibcon#enter sib2, iclass 4, count 0 2006.211.08:26:37.50#ibcon#flushed, iclass 4, count 0 2006.211.08:26:37.50#ibcon#about to write, iclass 4, count 0 2006.211.08:26:37.50#ibcon#wrote, iclass 4, count 0 2006.211.08:26:37.50#ibcon#about to read 3, iclass 4, count 0 2006.211.08:26:37.51#ibcon#read 3, iclass 4, count 0 2006.211.08:26:37.51#ibcon#about to read 4, iclass 4, count 0 2006.211.08:26:37.51#ibcon#read 4, iclass 4, count 0 2006.211.08:26:37.51#ibcon#about to read 5, iclass 4, count 0 2006.211.08:26:37.51#ibcon#read 5, iclass 4, count 0 2006.211.08:26:37.51#ibcon#about to read 6, iclass 4, count 0 2006.211.08:26:37.51#ibcon#read 6, iclass 4, count 0 2006.211.08:26:37.51#ibcon#end of sib2, iclass 4, count 0 2006.211.08:26:37.51#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:26:37.51#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:26:37.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:26:37.51#ibcon#*before write, iclass 4, count 0 2006.211.08:26:37.51#ibcon#enter sib2, iclass 4, count 0 2006.211.08:26:37.51#ibcon#flushed, iclass 4, count 0 2006.211.08:26:37.51#ibcon#about to write, iclass 4, count 0 2006.211.08:26:37.51#ibcon#wrote, iclass 4, count 0 2006.211.08:26:37.51#ibcon#about to read 3, iclass 4, count 0 2006.211.08:26:37.56#ibcon#read 3, iclass 4, count 0 2006.211.08:26:37.56#ibcon#about to read 4, iclass 4, count 0 2006.211.08:26:37.56#ibcon#read 4, iclass 4, count 0 2006.211.08:26:37.56#ibcon#about to read 5, iclass 4, count 0 2006.211.08:26:37.56#ibcon#read 5, iclass 4, count 0 2006.211.08:26:37.56#ibcon#about to read 6, iclass 4, count 0 2006.211.08:26:37.56#ibcon#read 6, iclass 4, count 0 2006.211.08:26:37.56#ibcon#end of sib2, iclass 4, count 0 2006.211.08:26:37.56#ibcon#*after write, iclass 4, count 0 2006.211.08:26:37.56#ibcon#*before return 0, iclass 4, count 0 2006.211.08:26:37.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:37.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:37.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:26:37.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:26:37.56$vc4f8/va=1,8 2006.211.08:26:37.56#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:26:37.56#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:26:37.56#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:37.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:37.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:37.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:37.56#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:26:37.56#ibcon#first serial, iclass 6, count 2 2006.211.08:26:37.56#ibcon#enter sib2, iclass 6, count 2 2006.211.08:26:37.56#ibcon#flushed, iclass 6, count 2 2006.211.08:26:37.56#ibcon#about to write, iclass 6, count 2 2006.211.08:26:37.56#ibcon#wrote, iclass 6, count 2 2006.211.08:26:37.56#ibcon#about to read 3, iclass 6, count 2 2006.211.08:26:37.58#ibcon#read 3, iclass 6, count 2 2006.211.08:26:37.58#ibcon#about to read 4, iclass 6, count 2 2006.211.08:26:37.58#ibcon#read 4, iclass 6, count 2 2006.211.08:26:37.58#ibcon#about to read 5, iclass 6, count 2 2006.211.08:26:37.58#ibcon#read 5, iclass 6, count 2 2006.211.08:26:37.58#ibcon#about to read 6, iclass 6, count 2 2006.211.08:26:37.58#ibcon#read 6, iclass 6, count 2 2006.211.08:26:37.58#ibcon#end of sib2, iclass 6, count 2 2006.211.08:26:37.58#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:26:37.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:26:37.58#ibcon#[25=AT01-08\r\n] 2006.211.08:26:37.58#ibcon#*before write, iclass 6, count 2 2006.211.08:26:37.58#ibcon#enter sib2, iclass 6, count 2 2006.211.08:26:37.58#ibcon#flushed, iclass 6, count 2 2006.211.08:26:37.58#ibcon#about to write, iclass 6, count 2 2006.211.08:26:37.58#ibcon#wrote, iclass 6, count 2 2006.211.08:26:37.58#ibcon#about to read 3, iclass 6, count 2 2006.211.08:26:37.61#ibcon#read 3, iclass 6, count 2 2006.211.08:26:37.61#ibcon#about to read 4, iclass 6, count 2 2006.211.08:26:37.61#ibcon#read 4, iclass 6, count 2 2006.211.08:26:37.61#ibcon#about to read 5, iclass 6, count 2 2006.211.08:26:37.61#ibcon#read 5, iclass 6, count 2 2006.211.08:26:37.61#ibcon#about to read 6, iclass 6, count 2 2006.211.08:26:37.61#ibcon#read 6, iclass 6, count 2 2006.211.08:26:37.61#ibcon#end of sib2, iclass 6, count 2 2006.211.08:26:37.61#ibcon#*after write, iclass 6, count 2 2006.211.08:26:37.61#ibcon#*before return 0, iclass 6, count 2 2006.211.08:26:37.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:37.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:37.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:26:37.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:37.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:37.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:37.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:37.73#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:26:37.73#ibcon#first serial, iclass 6, count 0 2006.211.08:26:37.73#ibcon#enter sib2, iclass 6, count 0 2006.211.08:26:37.73#ibcon#flushed, iclass 6, count 0 2006.211.08:26:37.73#ibcon#about to write, iclass 6, count 0 2006.211.08:26:37.73#ibcon#wrote, iclass 6, count 0 2006.211.08:26:37.73#ibcon#about to read 3, iclass 6, count 0 2006.211.08:26:37.75#ibcon#read 3, iclass 6, count 0 2006.211.08:26:37.75#ibcon#about to read 4, iclass 6, count 0 2006.211.08:26:37.75#ibcon#read 4, iclass 6, count 0 2006.211.08:26:37.75#ibcon#about to read 5, iclass 6, count 0 2006.211.08:26:37.75#ibcon#read 5, iclass 6, count 0 2006.211.08:26:37.75#ibcon#about to read 6, iclass 6, count 0 2006.211.08:26:37.75#ibcon#read 6, iclass 6, count 0 2006.211.08:26:37.75#ibcon#end of sib2, iclass 6, count 0 2006.211.08:26:37.75#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:26:37.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:26:37.75#ibcon#[25=USB\r\n] 2006.211.08:26:37.75#ibcon#*before write, iclass 6, count 0 2006.211.08:26:37.75#ibcon#enter sib2, iclass 6, count 0 2006.211.08:26:37.75#ibcon#flushed, iclass 6, count 0 2006.211.08:26:37.75#ibcon#about to write, iclass 6, count 0 2006.211.08:26:37.75#ibcon#wrote, iclass 6, count 0 2006.211.08:26:37.75#ibcon#about to read 3, iclass 6, count 0 2006.211.08:26:37.78#ibcon#read 3, iclass 6, count 0 2006.211.08:26:37.78#ibcon#about to read 4, iclass 6, count 0 2006.211.08:26:37.78#ibcon#read 4, iclass 6, count 0 2006.211.08:26:37.78#ibcon#about to read 5, iclass 6, count 0 2006.211.08:26:37.78#ibcon#read 5, iclass 6, count 0 2006.211.08:26:37.78#ibcon#about to read 6, iclass 6, count 0 2006.211.08:26:37.78#ibcon#read 6, iclass 6, count 0 2006.211.08:26:37.78#ibcon#end of sib2, iclass 6, count 0 2006.211.08:26:37.78#ibcon#*after write, iclass 6, count 0 2006.211.08:26:37.78#ibcon#*before return 0, iclass 6, count 0 2006.211.08:26:37.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:37.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:37.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:26:37.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:26:37.78$vc4f8/valo=2,572.99 2006.211.08:26:37.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:26:37.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:26:37.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:37.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:37.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:37.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:37.78#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:26:37.78#ibcon#first serial, iclass 10, count 0 2006.211.08:26:37.78#ibcon#enter sib2, iclass 10, count 0 2006.211.08:26:37.78#ibcon#flushed, iclass 10, count 0 2006.211.08:26:37.78#ibcon#about to write, iclass 10, count 0 2006.211.08:26:37.78#ibcon#wrote, iclass 10, count 0 2006.211.08:26:37.78#ibcon#about to read 3, iclass 10, count 0 2006.211.08:26:37.80#ibcon#read 3, iclass 10, count 0 2006.211.08:26:37.80#ibcon#about to read 4, iclass 10, count 0 2006.211.08:26:37.80#ibcon#read 4, iclass 10, count 0 2006.211.08:26:37.80#ibcon#about to read 5, iclass 10, count 0 2006.211.08:26:37.80#ibcon#read 5, iclass 10, count 0 2006.211.08:26:37.80#ibcon#about to read 6, iclass 10, count 0 2006.211.08:26:37.80#ibcon#read 6, iclass 10, count 0 2006.211.08:26:37.80#ibcon#end of sib2, iclass 10, count 0 2006.211.08:26:37.80#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:26:37.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:26:37.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:26:37.80#ibcon#*before write, iclass 10, count 0 2006.211.08:26:37.80#ibcon#enter sib2, iclass 10, count 0 2006.211.08:26:37.80#ibcon#flushed, iclass 10, count 0 2006.211.08:26:37.80#ibcon#about to write, iclass 10, count 0 2006.211.08:26:37.80#ibcon#wrote, iclass 10, count 0 2006.211.08:26:37.80#ibcon#about to read 3, iclass 10, count 0 2006.211.08:26:37.84#ibcon#read 3, iclass 10, count 0 2006.211.08:26:37.84#ibcon#about to read 4, iclass 10, count 0 2006.211.08:26:37.84#ibcon#read 4, iclass 10, count 0 2006.211.08:26:37.84#ibcon#about to read 5, iclass 10, count 0 2006.211.08:26:37.84#ibcon#read 5, iclass 10, count 0 2006.211.08:26:37.84#ibcon#about to read 6, iclass 10, count 0 2006.211.08:26:37.84#ibcon#read 6, iclass 10, count 0 2006.211.08:26:37.84#ibcon#end of sib2, iclass 10, count 0 2006.211.08:26:37.84#ibcon#*after write, iclass 10, count 0 2006.211.08:26:37.84#ibcon#*before return 0, iclass 10, count 0 2006.211.08:26:37.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:37.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:37.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:26:37.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:26:37.84$vc4f8/va=2,7 2006.211.08:26:37.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:26:37.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:26:37.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:37.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:37.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:37.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:37.90#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:26:37.90#ibcon#first serial, iclass 12, count 2 2006.211.08:26:37.90#ibcon#enter sib2, iclass 12, count 2 2006.211.08:26:37.90#ibcon#flushed, iclass 12, count 2 2006.211.08:26:37.90#ibcon#about to write, iclass 12, count 2 2006.211.08:26:37.90#ibcon#wrote, iclass 12, count 2 2006.211.08:26:37.90#ibcon#about to read 3, iclass 12, count 2 2006.211.08:26:37.92#ibcon#read 3, iclass 12, count 2 2006.211.08:26:37.92#ibcon#about to read 4, iclass 12, count 2 2006.211.08:26:37.92#ibcon#read 4, iclass 12, count 2 2006.211.08:26:37.92#ibcon#about to read 5, iclass 12, count 2 2006.211.08:26:37.92#ibcon#read 5, iclass 12, count 2 2006.211.08:26:37.92#ibcon#about to read 6, iclass 12, count 2 2006.211.08:26:37.92#ibcon#read 6, iclass 12, count 2 2006.211.08:26:37.92#ibcon#end of sib2, iclass 12, count 2 2006.211.08:26:37.92#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:26:37.92#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:26:37.92#ibcon#[25=AT02-07\r\n] 2006.211.08:26:37.92#ibcon#*before write, iclass 12, count 2 2006.211.08:26:37.92#ibcon#enter sib2, iclass 12, count 2 2006.211.08:26:37.92#ibcon#flushed, iclass 12, count 2 2006.211.08:26:37.92#ibcon#about to write, iclass 12, count 2 2006.211.08:26:37.92#ibcon#wrote, iclass 12, count 2 2006.211.08:26:37.92#ibcon#about to read 3, iclass 12, count 2 2006.211.08:26:37.95#ibcon#read 3, iclass 12, count 2 2006.211.08:26:37.95#ibcon#about to read 4, iclass 12, count 2 2006.211.08:26:37.95#ibcon#read 4, iclass 12, count 2 2006.211.08:26:37.95#ibcon#about to read 5, iclass 12, count 2 2006.211.08:26:37.95#ibcon#read 5, iclass 12, count 2 2006.211.08:26:37.95#ibcon#about to read 6, iclass 12, count 2 2006.211.08:26:37.95#ibcon#read 6, iclass 12, count 2 2006.211.08:26:37.95#ibcon#end of sib2, iclass 12, count 2 2006.211.08:26:37.95#ibcon#*after write, iclass 12, count 2 2006.211.08:26:37.95#ibcon#*before return 0, iclass 12, count 2 2006.211.08:26:37.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:37.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:37.95#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:26:37.95#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:37.95#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:38.07#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:38.07#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:38.07#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:26:38.07#ibcon#first serial, iclass 12, count 0 2006.211.08:26:38.07#ibcon#enter sib2, iclass 12, count 0 2006.211.08:26:38.07#ibcon#flushed, iclass 12, count 0 2006.211.08:26:38.07#ibcon#about to write, iclass 12, count 0 2006.211.08:26:38.07#ibcon#wrote, iclass 12, count 0 2006.211.08:26:38.07#ibcon#about to read 3, iclass 12, count 0 2006.211.08:26:38.09#ibcon#read 3, iclass 12, count 0 2006.211.08:26:38.09#ibcon#about to read 4, iclass 12, count 0 2006.211.08:26:38.09#ibcon#read 4, iclass 12, count 0 2006.211.08:26:38.09#ibcon#about to read 5, iclass 12, count 0 2006.211.08:26:38.09#ibcon#read 5, iclass 12, count 0 2006.211.08:26:38.09#ibcon#about to read 6, iclass 12, count 0 2006.211.08:26:38.09#ibcon#read 6, iclass 12, count 0 2006.211.08:26:38.09#ibcon#end of sib2, iclass 12, count 0 2006.211.08:26:38.09#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:26:38.09#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:26:38.09#ibcon#[25=USB\r\n] 2006.211.08:26:38.09#ibcon#*before write, iclass 12, count 0 2006.211.08:26:38.09#ibcon#enter sib2, iclass 12, count 0 2006.211.08:26:38.09#ibcon#flushed, iclass 12, count 0 2006.211.08:26:38.09#ibcon#about to write, iclass 12, count 0 2006.211.08:26:38.09#ibcon#wrote, iclass 12, count 0 2006.211.08:26:38.09#ibcon#about to read 3, iclass 12, count 0 2006.211.08:26:38.12#ibcon#read 3, iclass 12, count 0 2006.211.08:26:38.12#ibcon#about to read 4, iclass 12, count 0 2006.211.08:26:38.12#ibcon#read 4, iclass 12, count 0 2006.211.08:26:38.12#ibcon#about to read 5, iclass 12, count 0 2006.211.08:26:38.12#ibcon#read 5, iclass 12, count 0 2006.211.08:26:38.12#ibcon#about to read 6, iclass 12, count 0 2006.211.08:26:38.12#ibcon#read 6, iclass 12, count 0 2006.211.08:26:38.12#ibcon#end of sib2, iclass 12, count 0 2006.211.08:26:38.12#ibcon#*after write, iclass 12, count 0 2006.211.08:26:38.12#ibcon#*before return 0, iclass 12, count 0 2006.211.08:26:38.12#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:38.12#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:38.12#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:26:38.12#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:26:38.12$vc4f8/valo=3,672.99 2006.211.08:26:38.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:26:38.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:26:38.12#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:38.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:38.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:38.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:38.12#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:26:38.12#ibcon#first serial, iclass 14, count 0 2006.211.08:26:38.12#ibcon#enter sib2, iclass 14, count 0 2006.211.08:26:38.12#ibcon#flushed, iclass 14, count 0 2006.211.08:26:38.12#ibcon#about to write, iclass 14, count 0 2006.211.08:26:38.12#ibcon#wrote, iclass 14, count 0 2006.211.08:26:38.12#ibcon#about to read 3, iclass 14, count 0 2006.211.08:26:38.14#ibcon#read 3, iclass 14, count 0 2006.211.08:26:38.14#ibcon#about to read 4, iclass 14, count 0 2006.211.08:26:38.14#ibcon#read 4, iclass 14, count 0 2006.211.08:26:38.14#ibcon#about to read 5, iclass 14, count 0 2006.211.08:26:38.14#ibcon#read 5, iclass 14, count 0 2006.211.08:26:38.14#ibcon#about to read 6, iclass 14, count 0 2006.211.08:26:38.14#ibcon#read 6, iclass 14, count 0 2006.211.08:26:38.14#ibcon#end of sib2, iclass 14, count 0 2006.211.08:26:38.14#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:26:38.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:26:38.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:26:38.14#ibcon#*before write, iclass 14, count 0 2006.211.08:26:38.14#ibcon#enter sib2, iclass 14, count 0 2006.211.08:26:38.14#ibcon#flushed, iclass 14, count 0 2006.211.08:26:38.14#ibcon#about to write, iclass 14, count 0 2006.211.08:26:38.14#ibcon#wrote, iclass 14, count 0 2006.211.08:26:38.14#ibcon#about to read 3, iclass 14, count 0 2006.211.08:26:38.18#ibcon#read 3, iclass 14, count 0 2006.211.08:26:38.18#ibcon#about to read 4, iclass 14, count 0 2006.211.08:26:38.18#ibcon#read 4, iclass 14, count 0 2006.211.08:26:38.18#ibcon#about to read 5, iclass 14, count 0 2006.211.08:26:38.18#ibcon#read 5, iclass 14, count 0 2006.211.08:26:38.18#ibcon#about to read 6, iclass 14, count 0 2006.211.08:26:38.18#ibcon#read 6, iclass 14, count 0 2006.211.08:26:38.18#ibcon#end of sib2, iclass 14, count 0 2006.211.08:26:38.18#ibcon#*after write, iclass 14, count 0 2006.211.08:26:38.18#ibcon#*before return 0, iclass 14, count 0 2006.211.08:26:38.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:38.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:38.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:26:38.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:26:38.18$vc4f8/va=3,6 2006.211.08:26:38.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:26:38.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:26:38.18#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:38.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:38.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:38.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:38.24#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:26:38.24#ibcon#first serial, iclass 16, count 2 2006.211.08:26:38.24#ibcon#enter sib2, iclass 16, count 2 2006.211.08:26:38.24#ibcon#flushed, iclass 16, count 2 2006.211.08:26:38.24#ibcon#about to write, iclass 16, count 2 2006.211.08:26:38.24#ibcon#wrote, iclass 16, count 2 2006.211.08:26:38.24#ibcon#about to read 3, iclass 16, count 2 2006.211.08:26:38.26#ibcon#read 3, iclass 16, count 2 2006.211.08:26:38.26#ibcon#about to read 4, iclass 16, count 2 2006.211.08:26:38.26#ibcon#read 4, iclass 16, count 2 2006.211.08:26:38.26#ibcon#about to read 5, iclass 16, count 2 2006.211.08:26:38.26#ibcon#read 5, iclass 16, count 2 2006.211.08:26:38.26#ibcon#about to read 6, iclass 16, count 2 2006.211.08:26:38.26#ibcon#read 6, iclass 16, count 2 2006.211.08:26:38.26#ibcon#end of sib2, iclass 16, count 2 2006.211.08:26:38.26#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:26:38.26#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:26:38.26#ibcon#[25=AT03-06\r\n] 2006.211.08:26:38.26#ibcon#*before write, iclass 16, count 2 2006.211.08:26:38.26#ibcon#enter sib2, iclass 16, count 2 2006.211.08:26:38.26#ibcon#flushed, iclass 16, count 2 2006.211.08:26:38.26#ibcon#about to write, iclass 16, count 2 2006.211.08:26:38.26#ibcon#wrote, iclass 16, count 2 2006.211.08:26:38.26#ibcon#about to read 3, iclass 16, count 2 2006.211.08:26:38.29#ibcon#read 3, iclass 16, count 2 2006.211.08:26:38.29#ibcon#about to read 4, iclass 16, count 2 2006.211.08:26:38.29#ibcon#read 4, iclass 16, count 2 2006.211.08:26:38.29#ibcon#about to read 5, iclass 16, count 2 2006.211.08:26:38.29#ibcon#read 5, iclass 16, count 2 2006.211.08:26:38.29#ibcon#about to read 6, iclass 16, count 2 2006.211.08:26:38.29#ibcon#read 6, iclass 16, count 2 2006.211.08:26:38.29#ibcon#end of sib2, iclass 16, count 2 2006.211.08:26:38.29#ibcon#*after write, iclass 16, count 2 2006.211.08:26:38.29#ibcon#*before return 0, iclass 16, count 2 2006.211.08:26:38.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:38.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:38.29#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:26:38.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:38.29#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:38.41#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:38.41#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:38.41#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:26:38.41#ibcon#first serial, iclass 16, count 0 2006.211.08:26:38.41#ibcon#enter sib2, iclass 16, count 0 2006.211.08:26:38.41#ibcon#flushed, iclass 16, count 0 2006.211.08:26:38.41#ibcon#about to write, iclass 16, count 0 2006.211.08:26:38.41#ibcon#wrote, iclass 16, count 0 2006.211.08:26:38.41#ibcon#about to read 3, iclass 16, count 0 2006.211.08:26:38.43#ibcon#read 3, iclass 16, count 0 2006.211.08:26:38.43#ibcon#about to read 4, iclass 16, count 0 2006.211.08:26:38.43#ibcon#read 4, iclass 16, count 0 2006.211.08:26:38.43#ibcon#about to read 5, iclass 16, count 0 2006.211.08:26:38.43#ibcon#read 5, iclass 16, count 0 2006.211.08:26:38.43#ibcon#about to read 6, iclass 16, count 0 2006.211.08:26:38.43#ibcon#read 6, iclass 16, count 0 2006.211.08:26:38.43#ibcon#end of sib2, iclass 16, count 0 2006.211.08:26:38.43#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:26:38.43#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:26:38.43#ibcon#[25=USB\r\n] 2006.211.08:26:38.43#ibcon#*before write, iclass 16, count 0 2006.211.08:26:38.43#ibcon#enter sib2, iclass 16, count 0 2006.211.08:26:38.43#ibcon#flushed, iclass 16, count 0 2006.211.08:26:38.43#ibcon#about to write, iclass 16, count 0 2006.211.08:26:38.43#ibcon#wrote, iclass 16, count 0 2006.211.08:26:38.43#ibcon#about to read 3, iclass 16, count 0 2006.211.08:26:38.46#ibcon#read 3, iclass 16, count 0 2006.211.08:26:38.46#ibcon#about to read 4, iclass 16, count 0 2006.211.08:26:38.46#ibcon#read 4, iclass 16, count 0 2006.211.08:26:38.46#ibcon#about to read 5, iclass 16, count 0 2006.211.08:26:38.46#ibcon#read 5, iclass 16, count 0 2006.211.08:26:38.46#ibcon#about to read 6, iclass 16, count 0 2006.211.08:26:38.46#ibcon#read 6, iclass 16, count 0 2006.211.08:26:38.46#ibcon#end of sib2, iclass 16, count 0 2006.211.08:26:38.46#ibcon#*after write, iclass 16, count 0 2006.211.08:26:38.46#ibcon#*before return 0, iclass 16, count 0 2006.211.08:26:38.46#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:38.46#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:38.46#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:26:38.46#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:26:38.46$vc4f8/valo=4,832.99 2006.211.08:26:38.46#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:26:38.46#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:26:38.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:38.46#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:38.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:38.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:38.46#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:26:38.46#ibcon#first serial, iclass 18, count 0 2006.211.08:26:38.46#ibcon#enter sib2, iclass 18, count 0 2006.211.08:26:38.46#ibcon#flushed, iclass 18, count 0 2006.211.08:26:38.46#ibcon#about to write, iclass 18, count 0 2006.211.08:26:38.46#ibcon#wrote, iclass 18, count 0 2006.211.08:26:38.46#ibcon#about to read 3, iclass 18, count 0 2006.211.08:26:38.48#ibcon#read 3, iclass 18, count 0 2006.211.08:26:38.48#ibcon#about to read 4, iclass 18, count 0 2006.211.08:26:38.48#ibcon#read 4, iclass 18, count 0 2006.211.08:26:38.48#ibcon#about to read 5, iclass 18, count 0 2006.211.08:26:38.48#ibcon#read 5, iclass 18, count 0 2006.211.08:26:38.48#ibcon#about to read 6, iclass 18, count 0 2006.211.08:26:38.48#ibcon#read 6, iclass 18, count 0 2006.211.08:26:38.48#ibcon#end of sib2, iclass 18, count 0 2006.211.08:26:38.48#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:26:38.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:26:38.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:26:38.48#ibcon#*before write, iclass 18, count 0 2006.211.08:26:38.48#ibcon#enter sib2, iclass 18, count 0 2006.211.08:26:38.48#ibcon#flushed, iclass 18, count 0 2006.211.08:26:38.48#ibcon#about to write, iclass 18, count 0 2006.211.08:26:38.48#ibcon#wrote, iclass 18, count 0 2006.211.08:26:38.48#ibcon#about to read 3, iclass 18, count 0 2006.211.08:26:38.52#ibcon#read 3, iclass 18, count 0 2006.211.08:26:38.52#ibcon#about to read 4, iclass 18, count 0 2006.211.08:26:38.52#ibcon#read 4, iclass 18, count 0 2006.211.08:26:38.52#ibcon#about to read 5, iclass 18, count 0 2006.211.08:26:38.52#ibcon#read 5, iclass 18, count 0 2006.211.08:26:38.52#ibcon#about to read 6, iclass 18, count 0 2006.211.08:26:38.52#ibcon#read 6, iclass 18, count 0 2006.211.08:26:38.52#ibcon#end of sib2, iclass 18, count 0 2006.211.08:26:38.52#ibcon#*after write, iclass 18, count 0 2006.211.08:26:38.52#ibcon#*before return 0, iclass 18, count 0 2006.211.08:26:38.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:38.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:38.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:26:38.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:26:38.52$vc4f8/va=4,7 2006.211.08:26:38.52#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:26:38.52#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:26:38.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:38.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:38.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:38.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:38.58#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:26:38.58#ibcon#first serial, iclass 20, count 2 2006.211.08:26:38.58#ibcon#enter sib2, iclass 20, count 2 2006.211.08:26:38.58#ibcon#flushed, iclass 20, count 2 2006.211.08:26:38.58#ibcon#about to write, iclass 20, count 2 2006.211.08:26:38.58#ibcon#wrote, iclass 20, count 2 2006.211.08:26:38.58#ibcon#about to read 3, iclass 20, count 2 2006.211.08:26:38.60#ibcon#read 3, iclass 20, count 2 2006.211.08:26:38.60#ibcon#about to read 4, iclass 20, count 2 2006.211.08:26:38.60#ibcon#read 4, iclass 20, count 2 2006.211.08:26:38.60#ibcon#about to read 5, iclass 20, count 2 2006.211.08:26:38.60#ibcon#read 5, iclass 20, count 2 2006.211.08:26:38.60#ibcon#about to read 6, iclass 20, count 2 2006.211.08:26:38.60#ibcon#read 6, iclass 20, count 2 2006.211.08:26:38.60#ibcon#end of sib2, iclass 20, count 2 2006.211.08:26:38.60#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:26:38.60#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:26:38.60#ibcon#[25=AT04-07\r\n] 2006.211.08:26:38.60#ibcon#*before write, iclass 20, count 2 2006.211.08:26:38.60#ibcon#enter sib2, iclass 20, count 2 2006.211.08:26:38.60#ibcon#flushed, iclass 20, count 2 2006.211.08:26:38.60#ibcon#about to write, iclass 20, count 2 2006.211.08:26:38.60#ibcon#wrote, iclass 20, count 2 2006.211.08:26:38.60#ibcon#about to read 3, iclass 20, count 2 2006.211.08:26:38.62#abcon#<5=/04 4.310.3 24.13 821010.2\r\n> 2006.211.08:26:38.63#ibcon#read 3, iclass 20, count 2 2006.211.08:26:38.63#ibcon#about to read 4, iclass 20, count 2 2006.211.08:26:38.63#ibcon#read 4, iclass 20, count 2 2006.211.08:26:38.63#ibcon#about to read 5, iclass 20, count 2 2006.211.08:26:38.63#ibcon#read 5, iclass 20, count 2 2006.211.08:26:38.63#ibcon#about to read 6, iclass 20, count 2 2006.211.08:26:38.63#ibcon#read 6, iclass 20, count 2 2006.211.08:26:38.63#ibcon#end of sib2, iclass 20, count 2 2006.211.08:26:38.63#ibcon#*after write, iclass 20, count 2 2006.211.08:26:38.63#ibcon#*before return 0, iclass 20, count 2 2006.211.08:26:38.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:38.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:38.63#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:26:38.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:38.63#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:38.64#abcon#{5=INTERFACE CLEAR} 2006.211.08:26:38.70#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:26:38.75#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:38.75#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:38.75#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:26:38.75#ibcon#first serial, iclass 20, count 0 2006.211.08:26:38.75#ibcon#enter sib2, iclass 20, count 0 2006.211.08:26:38.75#ibcon#flushed, iclass 20, count 0 2006.211.08:26:38.75#ibcon#about to write, iclass 20, count 0 2006.211.08:26:38.75#ibcon#wrote, iclass 20, count 0 2006.211.08:26:38.75#ibcon#about to read 3, iclass 20, count 0 2006.211.08:26:38.77#ibcon#read 3, iclass 20, count 0 2006.211.08:26:38.77#ibcon#about to read 4, iclass 20, count 0 2006.211.08:26:38.77#ibcon#read 4, iclass 20, count 0 2006.211.08:26:38.77#ibcon#about to read 5, iclass 20, count 0 2006.211.08:26:38.77#ibcon#read 5, iclass 20, count 0 2006.211.08:26:38.77#ibcon#about to read 6, iclass 20, count 0 2006.211.08:26:38.77#ibcon#read 6, iclass 20, count 0 2006.211.08:26:38.77#ibcon#end of sib2, iclass 20, count 0 2006.211.08:26:38.77#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:26:38.77#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:26:38.77#ibcon#[25=USB\r\n] 2006.211.08:26:38.77#ibcon#*before write, iclass 20, count 0 2006.211.08:26:38.77#ibcon#enter sib2, iclass 20, count 0 2006.211.08:26:38.77#ibcon#flushed, iclass 20, count 0 2006.211.08:26:38.77#ibcon#about to write, iclass 20, count 0 2006.211.08:26:38.77#ibcon#wrote, iclass 20, count 0 2006.211.08:26:38.77#ibcon#about to read 3, iclass 20, count 0 2006.211.08:26:38.80#ibcon#read 3, iclass 20, count 0 2006.211.08:26:38.80#ibcon#about to read 4, iclass 20, count 0 2006.211.08:26:38.80#ibcon#read 4, iclass 20, count 0 2006.211.08:26:38.80#ibcon#about to read 5, iclass 20, count 0 2006.211.08:26:38.80#ibcon#read 5, iclass 20, count 0 2006.211.08:26:38.80#ibcon#about to read 6, iclass 20, count 0 2006.211.08:26:38.80#ibcon#read 6, iclass 20, count 0 2006.211.08:26:38.80#ibcon#end of sib2, iclass 20, count 0 2006.211.08:26:38.80#ibcon#*after write, iclass 20, count 0 2006.211.08:26:38.80#ibcon#*before return 0, iclass 20, count 0 2006.211.08:26:38.80#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:38.80#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:38.80#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:26:38.80#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:26:38.80$vc4f8/valo=5,652.99 2006.211.08:26:38.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:26:38.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:26:38.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:38.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:38.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:38.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:38.80#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:26:38.80#ibcon#first serial, iclass 26, count 0 2006.211.08:26:38.80#ibcon#enter sib2, iclass 26, count 0 2006.211.08:26:38.80#ibcon#flushed, iclass 26, count 0 2006.211.08:26:38.80#ibcon#about to write, iclass 26, count 0 2006.211.08:26:38.80#ibcon#wrote, iclass 26, count 0 2006.211.08:26:38.80#ibcon#about to read 3, iclass 26, count 0 2006.211.08:26:38.82#ibcon#read 3, iclass 26, count 0 2006.211.08:26:38.82#ibcon#about to read 4, iclass 26, count 0 2006.211.08:26:38.82#ibcon#read 4, iclass 26, count 0 2006.211.08:26:38.82#ibcon#about to read 5, iclass 26, count 0 2006.211.08:26:38.82#ibcon#read 5, iclass 26, count 0 2006.211.08:26:38.82#ibcon#about to read 6, iclass 26, count 0 2006.211.08:26:38.82#ibcon#read 6, iclass 26, count 0 2006.211.08:26:38.82#ibcon#end of sib2, iclass 26, count 0 2006.211.08:26:38.82#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:26:38.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:26:38.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:26:38.82#ibcon#*before write, iclass 26, count 0 2006.211.08:26:38.82#ibcon#enter sib2, iclass 26, count 0 2006.211.08:26:38.82#ibcon#flushed, iclass 26, count 0 2006.211.08:26:38.82#ibcon#about to write, iclass 26, count 0 2006.211.08:26:38.82#ibcon#wrote, iclass 26, count 0 2006.211.08:26:38.82#ibcon#about to read 3, iclass 26, count 0 2006.211.08:26:38.86#ibcon#read 3, iclass 26, count 0 2006.211.08:26:38.86#ibcon#about to read 4, iclass 26, count 0 2006.211.08:26:38.86#ibcon#read 4, iclass 26, count 0 2006.211.08:26:38.86#ibcon#about to read 5, iclass 26, count 0 2006.211.08:26:38.86#ibcon#read 5, iclass 26, count 0 2006.211.08:26:38.86#ibcon#about to read 6, iclass 26, count 0 2006.211.08:26:38.86#ibcon#read 6, iclass 26, count 0 2006.211.08:26:38.86#ibcon#end of sib2, iclass 26, count 0 2006.211.08:26:38.86#ibcon#*after write, iclass 26, count 0 2006.211.08:26:38.86#ibcon#*before return 0, iclass 26, count 0 2006.211.08:26:38.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:38.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:38.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:26:38.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:26:38.86$vc4f8/va=5,7 2006.211.08:26:38.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:26:38.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:26:38.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:38.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:38.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:38.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:38.92#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:26:38.92#ibcon#first serial, iclass 28, count 2 2006.211.08:26:38.92#ibcon#enter sib2, iclass 28, count 2 2006.211.08:26:38.92#ibcon#flushed, iclass 28, count 2 2006.211.08:26:38.92#ibcon#about to write, iclass 28, count 2 2006.211.08:26:38.92#ibcon#wrote, iclass 28, count 2 2006.211.08:26:38.92#ibcon#about to read 3, iclass 28, count 2 2006.211.08:26:38.94#ibcon#read 3, iclass 28, count 2 2006.211.08:26:38.94#ibcon#about to read 4, iclass 28, count 2 2006.211.08:26:38.94#ibcon#read 4, iclass 28, count 2 2006.211.08:26:38.94#ibcon#about to read 5, iclass 28, count 2 2006.211.08:26:38.94#ibcon#read 5, iclass 28, count 2 2006.211.08:26:38.94#ibcon#about to read 6, iclass 28, count 2 2006.211.08:26:38.94#ibcon#read 6, iclass 28, count 2 2006.211.08:26:38.94#ibcon#end of sib2, iclass 28, count 2 2006.211.08:26:38.94#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:26:38.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:26:38.94#ibcon#[25=AT05-07\r\n] 2006.211.08:26:38.94#ibcon#*before write, iclass 28, count 2 2006.211.08:26:38.94#ibcon#enter sib2, iclass 28, count 2 2006.211.08:26:38.94#ibcon#flushed, iclass 28, count 2 2006.211.08:26:38.94#ibcon#about to write, iclass 28, count 2 2006.211.08:26:38.94#ibcon#wrote, iclass 28, count 2 2006.211.08:26:38.94#ibcon#about to read 3, iclass 28, count 2 2006.211.08:26:38.97#ibcon#read 3, iclass 28, count 2 2006.211.08:26:38.97#ibcon#about to read 4, iclass 28, count 2 2006.211.08:26:38.97#ibcon#read 4, iclass 28, count 2 2006.211.08:26:38.97#ibcon#about to read 5, iclass 28, count 2 2006.211.08:26:38.97#ibcon#read 5, iclass 28, count 2 2006.211.08:26:38.97#ibcon#about to read 6, iclass 28, count 2 2006.211.08:26:38.97#ibcon#read 6, iclass 28, count 2 2006.211.08:26:38.97#ibcon#end of sib2, iclass 28, count 2 2006.211.08:26:38.97#ibcon#*after write, iclass 28, count 2 2006.211.08:26:38.97#ibcon#*before return 0, iclass 28, count 2 2006.211.08:26:38.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:38.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:38.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:26:38.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:38.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:39.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:39.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:39.09#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:26:39.09#ibcon#first serial, iclass 28, count 0 2006.211.08:26:39.09#ibcon#enter sib2, iclass 28, count 0 2006.211.08:26:39.09#ibcon#flushed, iclass 28, count 0 2006.211.08:26:39.09#ibcon#about to write, iclass 28, count 0 2006.211.08:26:39.09#ibcon#wrote, iclass 28, count 0 2006.211.08:26:39.09#ibcon#about to read 3, iclass 28, count 0 2006.211.08:26:39.11#ibcon#read 3, iclass 28, count 0 2006.211.08:26:39.11#ibcon#about to read 4, iclass 28, count 0 2006.211.08:26:39.11#ibcon#read 4, iclass 28, count 0 2006.211.08:26:39.11#ibcon#about to read 5, iclass 28, count 0 2006.211.08:26:39.11#ibcon#read 5, iclass 28, count 0 2006.211.08:26:39.11#ibcon#about to read 6, iclass 28, count 0 2006.211.08:26:39.11#ibcon#read 6, iclass 28, count 0 2006.211.08:26:39.11#ibcon#end of sib2, iclass 28, count 0 2006.211.08:26:39.11#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:26:39.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:26:39.11#ibcon#[25=USB\r\n] 2006.211.08:26:39.11#ibcon#*before write, iclass 28, count 0 2006.211.08:26:39.11#ibcon#enter sib2, iclass 28, count 0 2006.211.08:26:39.11#ibcon#flushed, iclass 28, count 0 2006.211.08:26:39.11#ibcon#about to write, iclass 28, count 0 2006.211.08:26:39.11#ibcon#wrote, iclass 28, count 0 2006.211.08:26:39.11#ibcon#about to read 3, iclass 28, count 0 2006.211.08:26:39.14#ibcon#read 3, iclass 28, count 0 2006.211.08:26:39.14#ibcon#about to read 4, iclass 28, count 0 2006.211.08:26:39.14#ibcon#read 4, iclass 28, count 0 2006.211.08:26:39.14#ibcon#about to read 5, iclass 28, count 0 2006.211.08:26:39.14#ibcon#read 5, iclass 28, count 0 2006.211.08:26:39.14#ibcon#about to read 6, iclass 28, count 0 2006.211.08:26:39.14#ibcon#read 6, iclass 28, count 0 2006.211.08:26:39.14#ibcon#end of sib2, iclass 28, count 0 2006.211.08:26:39.14#ibcon#*after write, iclass 28, count 0 2006.211.08:26:39.14#ibcon#*before return 0, iclass 28, count 0 2006.211.08:26:39.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:39.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:39.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:26:39.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:26:39.14$vc4f8/valo=6,772.99 2006.211.08:26:39.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:26:39.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:26:39.14#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:39.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:39.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:39.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:39.14#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:26:39.14#ibcon#first serial, iclass 30, count 0 2006.211.08:26:39.14#ibcon#enter sib2, iclass 30, count 0 2006.211.08:26:39.14#ibcon#flushed, iclass 30, count 0 2006.211.08:26:39.14#ibcon#about to write, iclass 30, count 0 2006.211.08:26:39.14#ibcon#wrote, iclass 30, count 0 2006.211.08:26:39.14#ibcon#about to read 3, iclass 30, count 0 2006.211.08:26:39.16#ibcon#read 3, iclass 30, count 0 2006.211.08:26:39.16#ibcon#about to read 4, iclass 30, count 0 2006.211.08:26:39.16#ibcon#read 4, iclass 30, count 0 2006.211.08:26:39.16#ibcon#about to read 5, iclass 30, count 0 2006.211.08:26:39.16#ibcon#read 5, iclass 30, count 0 2006.211.08:26:39.16#ibcon#about to read 6, iclass 30, count 0 2006.211.08:26:39.16#ibcon#read 6, iclass 30, count 0 2006.211.08:26:39.16#ibcon#end of sib2, iclass 30, count 0 2006.211.08:26:39.16#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:26:39.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:26:39.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:26:39.16#ibcon#*before write, iclass 30, count 0 2006.211.08:26:39.16#ibcon#enter sib2, iclass 30, count 0 2006.211.08:26:39.16#ibcon#flushed, iclass 30, count 0 2006.211.08:26:39.16#ibcon#about to write, iclass 30, count 0 2006.211.08:26:39.16#ibcon#wrote, iclass 30, count 0 2006.211.08:26:39.16#ibcon#about to read 3, iclass 30, count 0 2006.211.08:26:39.20#ibcon#read 3, iclass 30, count 0 2006.211.08:26:39.20#ibcon#about to read 4, iclass 30, count 0 2006.211.08:26:39.20#ibcon#read 4, iclass 30, count 0 2006.211.08:26:39.20#ibcon#about to read 5, iclass 30, count 0 2006.211.08:26:39.20#ibcon#read 5, iclass 30, count 0 2006.211.08:26:39.20#ibcon#about to read 6, iclass 30, count 0 2006.211.08:26:39.20#ibcon#read 6, iclass 30, count 0 2006.211.08:26:39.20#ibcon#end of sib2, iclass 30, count 0 2006.211.08:26:39.20#ibcon#*after write, iclass 30, count 0 2006.211.08:26:39.20#ibcon#*before return 0, iclass 30, count 0 2006.211.08:26:39.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:39.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:39.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:26:39.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:26:39.20$vc4f8/va=6,6 2006.211.08:26:39.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.08:26:39.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.08:26:39.20#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:39.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:26:39.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:26:39.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:26:39.26#ibcon#enter wrdev, iclass 32, count 2 2006.211.08:26:39.26#ibcon#first serial, iclass 32, count 2 2006.211.08:26:39.26#ibcon#enter sib2, iclass 32, count 2 2006.211.08:26:39.26#ibcon#flushed, iclass 32, count 2 2006.211.08:26:39.26#ibcon#about to write, iclass 32, count 2 2006.211.08:26:39.26#ibcon#wrote, iclass 32, count 2 2006.211.08:26:39.26#ibcon#about to read 3, iclass 32, count 2 2006.211.08:26:39.28#ibcon#read 3, iclass 32, count 2 2006.211.08:26:39.28#ibcon#about to read 4, iclass 32, count 2 2006.211.08:26:39.28#ibcon#read 4, iclass 32, count 2 2006.211.08:26:39.28#ibcon#about to read 5, iclass 32, count 2 2006.211.08:26:39.28#ibcon#read 5, iclass 32, count 2 2006.211.08:26:39.28#ibcon#about to read 6, iclass 32, count 2 2006.211.08:26:39.28#ibcon#read 6, iclass 32, count 2 2006.211.08:26:39.28#ibcon#end of sib2, iclass 32, count 2 2006.211.08:26:39.28#ibcon#*mode == 0, iclass 32, count 2 2006.211.08:26:39.28#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.08:26:39.28#ibcon#[25=AT06-06\r\n] 2006.211.08:26:39.28#ibcon#*before write, iclass 32, count 2 2006.211.08:26:39.28#ibcon#enter sib2, iclass 32, count 2 2006.211.08:26:39.28#ibcon#flushed, iclass 32, count 2 2006.211.08:26:39.28#ibcon#about to write, iclass 32, count 2 2006.211.08:26:39.28#ibcon#wrote, iclass 32, count 2 2006.211.08:26:39.28#ibcon#about to read 3, iclass 32, count 2 2006.211.08:26:39.31#ibcon#read 3, iclass 32, count 2 2006.211.08:26:39.31#ibcon#about to read 4, iclass 32, count 2 2006.211.08:26:39.31#ibcon#read 4, iclass 32, count 2 2006.211.08:26:39.31#ibcon#about to read 5, iclass 32, count 2 2006.211.08:26:39.31#ibcon#read 5, iclass 32, count 2 2006.211.08:26:39.31#ibcon#about to read 6, iclass 32, count 2 2006.211.08:26:39.31#ibcon#read 6, iclass 32, count 2 2006.211.08:26:39.31#ibcon#end of sib2, iclass 32, count 2 2006.211.08:26:39.31#ibcon#*after write, iclass 32, count 2 2006.211.08:26:39.31#ibcon#*before return 0, iclass 32, count 2 2006.211.08:26:39.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:26:39.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.08:26:39.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.08:26:39.31#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:39.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:26:39.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:26:39.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:26:39.43#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:26:39.43#ibcon#first serial, iclass 32, count 0 2006.211.08:26:39.43#ibcon#enter sib2, iclass 32, count 0 2006.211.08:26:39.43#ibcon#flushed, iclass 32, count 0 2006.211.08:26:39.43#ibcon#about to write, iclass 32, count 0 2006.211.08:26:39.43#ibcon#wrote, iclass 32, count 0 2006.211.08:26:39.43#ibcon#about to read 3, iclass 32, count 0 2006.211.08:26:39.45#ibcon#read 3, iclass 32, count 0 2006.211.08:26:39.45#ibcon#about to read 4, iclass 32, count 0 2006.211.08:26:39.45#ibcon#read 4, iclass 32, count 0 2006.211.08:26:39.45#ibcon#about to read 5, iclass 32, count 0 2006.211.08:26:39.45#ibcon#read 5, iclass 32, count 0 2006.211.08:26:39.45#ibcon#about to read 6, iclass 32, count 0 2006.211.08:26:39.45#ibcon#read 6, iclass 32, count 0 2006.211.08:26:39.45#ibcon#end of sib2, iclass 32, count 0 2006.211.08:26:39.45#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:26:39.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:26:39.45#ibcon#[25=USB\r\n] 2006.211.08:26:39.45#ibcon#*before write, iclass 32, count 0 2006.211.08:26:39.45#ibcon#enter sib2, iclass 32, count 0 2006.211.08:26:39.45#ibcon#flushed, iclass 32, count 0 2006.211.08:26:39.45#ibcon#about to write, iclass 32, count 0 2006.211.08:26:39.45#ibcon#wrote, iclass 32, count 0 2006.211.08:26:39.45#ibcon#about to read 3, iclass 32, count 0 2006.211.08:26:39.48#ibcon#read 3, iclass 32, count 0 2006.211.08:26:39.48#ibcon#about to read 4, iclass 32, count 0 2006.211.08:26:39.48#ibcon#read 4, iclass 32, count 0 2006.211.08:26:39.48#ibcon#about to read 5, iclass 32, count 0 2006.211.08:26:39.48#ibcon#read 5, iclass 32, count 0 2006.211.08:26:39.48#ibcon#about to read 6, iclass 32, count 0 2006.211.08:26:39.48#ibcon#read 6, iclass 32, count 0 2006.211.08:26:39.48#ibcon#end of sib2, iclass 32, count 0 2006.211.08:26:39.48#ibcon#*after write, iclass 32, count 0 2006.211.08:26:39.48#ibcon#*before return 0, iclass 32, count 0 2006.211.08:26:39.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:26:39.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.08:26:39.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:26:39.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:26:39.48$vc4f8/valo=7,832.99 2006.211.08:26:39.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.08:26:39.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.08:26:39.48#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:39.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:26:39.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:26:39.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:26:39.48#ibcon#enter wrdev, iclass 34, count 0 2006.211.08:26:39.48#ibcon#first serial, iclass 34, count 0 2006.211.08:26:39.48#ibcon#enter sib2, iclass 34, count 0 2006.211.08:26:39.48#ibcon#flushed, iclass 34, count 0 2006.211.08:26:39.48#ibcon#about to write, iclass 34, count 0 2006.211.08:26:39.48#ibcon#wrote, iclass 34, count 0 2006.211.08:26:39.48#ibcon#about to read 3, iclass 34, count 0 2006.211.08:26:39.50#ibcon#read 3, iclass 34, count 0 2006.211.08:26:39.50#ibcon#about to read 4, iclass 34, count 0 2006.211.08:26:39.50#ibcon#read 4, iclass 34, count 0 2006.211.08:26:39.50#ibcon#about to read 5, iclass 34, count 0 2006.211.08:26:39.50#ibcon#read 5, iclass 34, count 0 2006.211.08:26:39.50#ibcon#about to read 6, iclass 34, count 0 2006.211.08:26:39.50#ibcon#read 6, iclass 34, count 0 2006.211.08:26:39.50#ibcon#end of sib2, iclass 34, count 0 2006.211.08:26:39.50#ibcon#*mode == 0, iclass 34, count 0 2006.211.08:26:39.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.08:26:39.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:26:39.50#ibcon#*before write, iclass 34, count 0 2006.211.08:26:39.50#ibcon#enter sib2, iclass 34, count 0 2006.211.08:26:39.50#ibcon#flushed, iclass 34, count 0 2006.211.08:26:39.50#ibcon#about to write, iclass 34, count 0 2006.211.08:26:39.50#ibcon#wrote, iclass 34, count 0 2006.211.08:26:39.50#ibcon#about to read 3, iclass 34, count 0 2006.211.08:26:39.54#ibcon#read 3, iclass 34, count 0 2006.211.08:26:39.54#ibcon#about to read 4, iclass 34, count 0 2006.211.08:26:39.54#ibcon#read 4, iclass 34, count 0 2006.211.08:26:39.54#ibcon#about to read 5, iclass 34, count 0 2006.211.08:26:39.54#ibcon#read 5, iclass 34, count 0 2006.211.08:26:39.54#ibcon#about to read 6, iclass 34, count 0 2006.211.08:26:39.54#ibcon#read 6, iclass 34, count 0 2006.211.08:26:39.54#ibcon#end of sib2, iclass 34, count 0 2006.211.08:26:39.54#ibcon#*after write, iclass 34, count 0 2006.211.08:26:39.54#ibcon#*before return 0, iclass 34, count 0 2006.211.08:26:39.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:26:39.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.08:26:39.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.08:26:39.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.08:26:39.54$vc4f8/va=7,6 2006.211.08:26:39.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.211.08:26:39.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.211.08:26:39.54#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:39.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:26:39.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:26:39.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:26:39.60#ibcon#enter wrdev, iclass 36, count 2 2006.211.08:26:39.60#ibcon#first serial, iclass 36, count 2 2006.211.08:26:39.60#ibcon#enter sib2, iclass 36, count 2 2006.211.08:26:39.60#ibcon#flushed, iclass 36, count 2 2006.211.08:26:39.60#ibcon#about to write, iclass 36, count 2 2006.211.08:26:39.60#ibcon#wrote, iclass 36, count 2 2006.211.08:26:39.60#ibcon#about to read 3, iclass 36, count 2 2006.211.08:26:39.62#ibcon#read 3, iclass 36, count 2 2006.211.08:26:39.62#ibcon#about to read 4, iclass 36, count 2 2006.211.08:26:39.62#ibcon#read 4, iclass 36, count 2 2006.211.08:26:39.62#ibcon#about to read 5, iclass 36, count 2 2006.211.08:26:39.62#ibcon#read 5, iclass 36, count 2 2006.211.08:26:39.62#ibcon#about to read 6, iclass 36, count 2 2006.211.08:26:39.62#ibcon#read 6, iclass 36, count 2 2006.211.08:26:39.62#ibcon#end of sib2, iclass 36, count 2 2006.211.08:26:39.62#ibcon#*mode == 0, iclass 36, count 2 2006.211.08:26:39.62#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.211.08:26:39.62#ibcon#[25=AT07-06\r\n] 2006.211.08:26:39.62#ibcon#*before write, iclass 36, count 2 2006.211.08:26:39.62#ibcon#enter sib2, iclass 36, count 2 2006.211.08:26:39.62#ibcon#flushed, iclass 36, count 2 2006.211.08:26:39.62#ibcon#about to write, iclass 36, count 2 2006.211.08:26:39.62#ibcon#wrote, iclass 36, count 2 2006.211.08:26:39.62#ibcon#about to read 3, iclass 36, count 2 2006.211.08:26:39.65#ibcon#read 3, iclass 36, count 2 2006.211.08:26:39.65#ibcon#about to read 4, iclass 36, count 2 2006.211.08:26:39.65#ibcon#read 4, iclass 36, count 2 2006.211.08:26:39.65#ibcon#about to read 5, iclass 36, count 2 2006.211.08:26:39.65#ibcon#read 5, iclass 36, count 2 2006.211.08:26:39.65#ibcon#about to read 6, iclass 36, count 2 2006.211.08:26:39.65#ibcon#read 6, iclass 36, count 2 2006.211.08:26:39.65#ibcon#end of sib2, iclass 36, count 2 2006.211.08:26:39.65#ibcon#*after write, iclass 36, count 2 2006.211.08:26:39.65#ibcon#*before return 0, iclass 36, count 2 2006.211.08:26:39.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:26:39.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.211.08:26:39.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.211.08:26:39.65#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:39.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:26:39.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:26:39.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:26:39.77#ibcon#enter wrdev, iclass 36, count 0 2006.211.08:26:39.77#ibcon#first serial, iclass 36, count 0 2006.211.08:26:39.77#ibcon#enter sib2, iclass 36, count 0 2006.211.08:26:39.77#ibcon#flushed, iclass 36, count 0 2006.211.08:26:39.77#ibcon#about to write, iclass 36, count 0 2006.211.08:26:39.77#ibcon#wrote, iclass 36, count 0 2006.211.08:26:39.77#ibcon#about to read 3, iclass 36, count 0 2006.211.08:26:39.79#ibcon#read 3, iclass 36, count 0 2006.211.08:26:39.79#ibcon#about to read 4, iclass 36, count 0 2006.211.08:26:39.79#ibcon#read 4, iclass 36, count 0 2006.211.08:26:39.79#ibcon#about to read 5, iclass 36, count 0 2006.211.08:26:39.79#ibcon#read 5, iclass 36, count 0 2006.211.08:26:39.79#ibcon#about to read 6, iclass 36, count 0 2006.211.08:26:39.79#ibcon#read 6, iclass 36, count 0 2006.211.08:26:39.79#ibcon#end of sib2, iclass 36, count 0 2006.211.08:26:39.79#ibcon#*mode == 0, iclass 36, count 0 2006.211.08:26:39.79#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.211.08:26:39.79#ibcon#[25=USB\r\n] 2006.211.08:26:39.79#ibcon#*before write, iclass 36, count 0 2006.211.08:26:39.79#ibcon#enter sib2, iclass 36, count 0 2006.211.08:26:39.79#ibcon#flushed, iclass 36, count 0 2006.211.08:26:39.79#ibcon#about to write, iclass 36, count 0 2006.211.08:26:39.79#ibcon#wrote, iclass 36, count 0 2006.211.08:26:39.79#ibcon#about to read 3, iclass 36, count 0 2006.211.08:26:39.82#ibcon#read 3, iclass 36, count 0 2006.211.08:26:39.82#ibcon#about to read 4, iclass 36, count 0 2006.211.08:26:39.82#ibcon#read 4, iclass 36, count 0 2006.211.08:26:39.82#ibcon#about to read 5, iclass 36, count 0 2006.211.08:26:39.82#ibcon#read 5, iclass 36, count 0 2006.211.08:26:39.82#ibcon#about to read 6, iclass 36, count 0 2006.211.08:26:39.82#ibcon#read 6, iclass 36, count 0 2006.211.08:26:39.82#ibcon#end of sib2, iclass 36, count 0 2006.211.08:26:39.82#ibcon#*after write, iclass 36, count 0 2006.211.08:26:39.82#ibcon#*before return 0, iclass 36, count 0 2006.211.08:26:39.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:26:39.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.211.08:26:39.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.211.08:26:39.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.211.08:26:39.82$vc4f8/valo=8,852.99 2006.211.08:26:39.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:26:39.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:26:39.82#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:39.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:26:39.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:26:39.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:26:39.82#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:26:39.82#ibcon#first serial, iclass 38, count 0 2006.211.08:26:39.82#ibcon#enter sib2, iclass 38, count 0 2006.211.08:26:39.82#ibcon#flushed, iclass 38, count 0 2006.211.08:26:39.82#ibcon#about to write, iclass 38, count 0 2006.211.08:26:39.82#ibcon#wrote, iclass 38, count 0 2006.211.08:26:39.82#ibcon#about to read 3, iclass 38, count 0 2006.211.08:26:39.84#ibcon#read 3, iclass 38, count 0 2006.211.08:26:39.84#ibcon#about to read 4, iclass 38, count 0 2006.211.08:26:39.84#ibcon#read 4, iclass 38, count 0 2006.211.08:26:39.84#ibcon#about to read 5, iclass 38, count 0 2006.211.08:26:39.84#ibcon#read 5, iclass 38, count 0 2006.211.08:26:39.84#ibcon#about to read 6, iclass 38, count 0 2006.211.08:26:39.84#ibcon#read 6, iclass 38, count 0 2006.211.08:26:39.84#ibcon#end of sib2, iclass 38, count 0 2006.211.08:26:39.84#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:26:39.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:26:39.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:26:39.84#ibcon#*before write, iclass 38, count 0 2006.211.08:26:39.84#ibcon#enter sib2, iclass 38, count 0 2006.211.08:26:39.84#ibcon#flushed, iclass 38, count 0 2006.211.08:26:39.84#ibcon#about to write, iclass 38, count 0 2006.211.08:26:39.84#ibcon#wrote, iclass 38, count 0 2006.211.08:26:39.84#ibcon#about to read 3, iclass 38, count 0 2006.211.08:26:39.88#ibcon#read 3, iclass 38, count 0 2006.211.08:26:39.88#ibcon#about to read 4, iclass 38, count 0 2006.211.08:26:39.88#ibcon#read 4, iclass 38, count 0 2006.211.08:26:39.88#ibcon#about to read 5, iclass 38, count 0 2006.211.08:26:39.88#ibcon#read 5, iclass 38, count 0 2006.211.08:26:39.88#ibcon#about to read 6, iclass 38, count 0 2006.211.08:26:39.88#ibcon#read 6, iclass 38, count 0 2006.211.08:26:39.88#ibcon#end of sib2, iclass 38, count 0 2006.211.08:26:39.88#ibcon#*after write, iclass 38, count 0 2006.211.08:26:39.88#ibcon#*before return 0, iclass 38, count 0 2006.211.08:26:39.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:26:39.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:26:39.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:26:39.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:26:39.88$vc4f8/va=8,7 2006.211.08:26:39.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:26:39.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:26:39.88#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:39.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:26:39.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:26:39.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:26:39.94#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:26:39.94#ibcon#first serial, iclass 40, count 2 2006.211.08:26:39.94#ibcon#enter sib2, iclass 40, count 2 2006.211.08:26:39.94#ibcon#flushed, iclass 40, count 2 2006.211.08:26:39.94#ibcon#about to write, iclass 40, count 2 2006.211.08:26:39.94#ibcon#wrote, iclass 40, count 2 2006.211.08:26:39.94#ibcon#about to read 3, iclass 40, count 2 2006.211.08:26:39.96#ibcon#read 3, iclass 40, count 2 2006.211.08:26:39.96#ibcon#about to read 4, iclass 40, count 2 2006.211.08:26:39.96#ibcon#read 4, iclass 40, count 2 2006.211.08:26:39.96#ibcon#about to read 5, iclass 40, count 2 2006.211.08:26:39.96#ibcon#read 5, iclass 40, count 2 2006.211.08:26:39.96#ibcon#about to read 6, iclass 40, count 2 2006.211.08:26:39.96#ibcon#read 6, iclass 40, count 2 2006.211.08:26:39.96#ibcon#end of sib2, iclass 40, count 2 2006.211.08:26:39.96#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:26:39.96#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:26:39.96#ibcon#[25=AT08-07\r\n] 2006.211.08:26:39.96#ibcon#*before write, iclass 40, count 2 2006.211.08:26:39.96#ibcon#enter sib2, iclass 40, count 2 2006.211.08:26:39.96#ibcon#flushed, iclass 40, count 2 2006.211.08:26:39.96#ibcon#about to write, iclass 40, count 2 2006.211.08:26:39.96#ibcon#wrote, iclass 40, count 2 2006.211.08:26:39.96#ibcon#about to read 3, iclass 40, count 2 2006.211.08:26:39.99#ibcon#read 3, iclass 40, count 2 2006.211.08:26:39.99#ibcon#about to read 4, iclass 40, count 2 2006.211.08:26:39.99#ibcon#read 4, iclass 40, count 2 2006.211.08:26:39.99#ibcon#about to read 5, iclass 40, count 2 2006.211.08:26:39.99#ibcon#read 5, iclass 40, count 2 2006.211.08:26:39.99#ibcon#about to read 6, iclass 40, count 2 2006.211.08:26:39.99#ibcon#read 6, iclass 40, count 2 2006.211.08:26:39.99#ibcon#end of sib2, iclass 40, count 2 2006.211.08:26:39.99#ibcon#*after write, iclass 40, count 2 2006.211.08:26:39.99#ibcon#*before return 0, iclass 40, count 2 2006.211.08:26:39.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:26:39.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:26:39.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:26:39.99#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:39.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:26:40.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:26:40.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:26:40.11#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:26:40.11#ibcon#first serial, iclass 40, count 0 2006.211.08:26:40.11#ibcon#enter sib2, iclass 40, count 0 2006.211.08:26:40.11#ibcon#flushed, iclass 40, count 0 2006.211.08:26:40.11#ibcon#about to write, iclass 40, count 0 2006.211.08:26:40.11#ibcon#wrote, iclass 40, count 0 2006.211.08:26:40.11#ibcon#about to read 3, iclass 40, count 0 2006.211.08:26:40.13#ibcon#read 3, iclass 40, count 0 2006.211.08:26:40.13#ibcon#about to read 4, iclass 40, count 0 2006.211.08:26:40.13#ibcon#read 4, iclass 40, count 0 2006.211.08:26:40.13#ibcon#about to read 5, iclass 40, count 0 2006.211.08:26:40.13#ibcon#read 5, iclass 40, count 0 2006.211.08:26:40.13#ibcon#about to read 6, iclass 40, count 0 2006.211.08:26:40.13#ibcon#read 6, iclass 40, count 0 2006.211.08:26:40.13#ibcon#end of sib2, iclass 40, count 0 2006.211.08:26:40.13#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:26:40.13#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:26:40.13#ibcon#[25=USB\r\n] 2006.211.08:26:40.13#ibcon#*before write, iclass 40, count 0 2006.211.08:26:40.13#ibcon#enter sib2, iclass 40, count 0 2006.211.08:26:40.13#ibcon#flushed, iclass 40, count 0 2006.211.08:26:40.13#ibcon#about to write, iclass 40, count 0 2006.211.08:26:40.13#ibcon#wrote, iclass 40, count 0 2006.211.08:26:40.13#ibcon#about to read 3, iclass 40, count 0 2006.211.08:26:40.16#ibcon#read 3, iclass 40, count 0 2006.211.08:26:40.16#ibcon#about to read 4, iclass 40, count 0 2006.211.08:26:40.16#ibcon#read 4, iclass 40, count 0 2006.211.08:26:40.16#ibcon#about to read 5, iclass 40, count 0 2006.211.08:26:40.16#ibcon#read 5, iclass 40, count 0 2006.211.08:26:40.16#ibcon#about to read 6, iclass 40, count 0 2006.211.08:26:40.16#ibcon#read 6, iclass 40, count 0 2006.211.08:26:40.16#ibcon#end of sib2, iclass 40, count 0 2006.211.08:26:40.16#ibcon#*after write, iclass 40, count 0 2006.211.08:26:40.16#ibcon#*before return 0, iclass 40, count 0 2006.211.08:26:40.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:26:40.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:26:40.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:26:40.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:26:40.16$vc4f8/vblo=1,632.99 2006.211.08:26:40.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:26:40.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:26:40.16#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:40.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:40.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:40.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:40.16#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:26:40.16#ibcon#first serial, iclass 4, count 0 2006.211.08:26:40.16#ibcon#enter sib2, iclass 4, count 0 2006.211.08:26:40.16#ibcon#flushed, iclass 4, count 0 2006.211.08:26:40.16#ibcon#about to write, iclass 4, count 0 2006.211.08:26:40.16#ibcon#wrote, iclass 4, count 0 2006.211.08:26:40.16#ibcon#about to read 3, iclass 4, count 0 2006.211.08:26:40.18#ibcon#read 3, iclass 4, count 0 2006.211.08:26:40.18#ibcon#about to read 4, iclass 4, count 0 2006.211.08:26:40.18#ibcon#read 4, iclass 4, count 0 2006.211.08:26:40.18#ibcon#about to read 5, iclass 4, count 0 2006.211.08:26:40.18#ibcon#read 5, iclass 4, count 0 2006.211.08:26:40.18#ibcon#about to read 6, iclass 4, count 0 2006.211.08:26:40.18#ibcon#read 6, iclass 4, count 0 2006.211.08:26:40.18#ibcon#end of sib2, iclass 4, count 0 2006.211.08:26:40.18#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:26:40.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:26:40.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:26:40.18#ibcon#*before write, iclass 4, count 0 2006.211.08:26:40.18#ibcon#enter sib2, iclass 4, count 0 2006.211.08:26:40.18#ibcon#flushed, iclass 4, count 0 2006.211.08:26:40.18#ibcon#about to write, iclass 4, count 0 2006.211.08:26:40.18#ibcon#wrote, iclass 4, count 0 2006.211.08:26:40.18#ibcon#about to read 3, iclass 4, count 0 2006.211.08:26:40.22#ibcon#read 3, iclass 4, count 0 2006.211.08:26:40.22#ibcon#about to read 4, iclass 4, count 0 2006.211.08:26:40.22#ibcon#read 4, iclass 4, count 0 2006.211.08:26:40.22#ibcon#about to read 5, iclass 4, count 0 2006.211.08:26:40.22#ibcon#read 5, iclass 4, count 0 2006.211.08:26:40.22#ibcon#about to read 6, iclass 4, count 0 2006.211.08:26:40.22#ibcon#read 6, iclass 4, count 0 2006.211.08:26:40.22#ibcon#end of sib2, iclass 4, count 0 2006.211.08:26:40.22#ibcon#*after write, iclass 4, count 0 2006.211.08:26:40.22#ibcon#*before return 0, iclass 4, count 0 2006.211.08:26:40.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:40.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:26:40.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:26:40.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:26:40.22$vc4f8/vb=1,4 2006.211.08:26:40.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:26:40.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:26:40.22#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:40.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:40.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:40.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:40.22#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:26:40.22#ibcon#first serial, iclass 6, count 2 2006.211.08:26:40.22#ibcon#enter sib2, iclass 6, count 2 2006.211.08:26:40.22#ibcon#flushed, iclass 6, count 2 2006.211.08:26:40.22#ibcon#about to write, iclass 6, count 2 2006.211.08:26:40.22#ibcon#wrote, iclass 6, count 2 2006.211.08:26:40.22#ibcon#about to read 3, iclass 6, count 2 2006.211.08:26:40.24#ibcon#read 3, iclass 6, count 2 2006.211.08:26:40.24#ibcon#about to read 4, iclass 6, count 2 2006.211.08:26:40.24#ibcon#read 4, iclass 6, count 2 2006.211.08:26:40.24#ibcon#about to read 5, iclass 6, count 2 2006.211.08:26:40.24#ibcon#read 5, iclass 6, count 2 2006.211.08:26:40.24#ibcon#about to read 6, iclass 6, count 2 2006.211.08:26:40.24#ibcon#read 6, iclass 6, count 2 2006.211.08:26:40.24#ibcon#end of sib2, iclass 6, count 2 2006.211.08:26:40.24#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:26:40.24#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:26:40.24#ibcon#[27=AT01-04\r\n] 2006.211.08:26:40.24#ibcon#*before write, iclass 6, count 2 2006.211.08:26:40.24#ibcon#enter sib2, iclass 6, count 2 2006.211.08:26:40.24#ibcon#flushed, iclass 6, count 2 2006.211.08:26:40.24#ibcon#about to write, iclass 6, count 2 2006.211.08:26:40.24#ibcon#wrote, iclass 6, count 2 2006.211.08:26:40.24#ibcon#about to read 3, iclass 6, count 2 2006.211.08:26:40.27#ibcon#read 3, iclass 6, count 2 2006.211.08:26:40.27#ibcon#about to read 4, iclass 6, count 2 2006.211.08:26:40.27#ibcon#read 4, iclass 6, count 2 2006.211.08:26:40.27#ibcon#about to read 5, iclass 6, count 2 2006.211.08:26:40.27#ibcon#read 5, iclass 6, count 2 2006.211.08:26:40.27#ibcon#about to read 6, iclass 6, count 2 2006.211.08:26:40.27#ibcon#read 6, iclass 6, count 2 2006.211.08:26:40.27#ibcon#end of sib2, iclass 6, count 2 2006.211.08:26:40.27#ibcon#*after write, iclass 6, count 2 2006.211.08:26:40.27#ibcon#*before return 0, iclass 6, count 2 2006.211.08:26:40.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:40.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:26:40.27#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:26:40.27#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:40.27#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:40.39#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:40.39#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:40.39#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:26:40.39#ibcon#first serial, iclass 6, count 0 2006.211.08:26:40.39#ibcon#enter sib2, iclass 6, count 0 2006.211.08:26:40.39#ibcon#flushed, iclass 6, count 0 2006.211.08:26:40.39#ibcon#about to write, iclass 6, count 0 2006.211.08:26:40.39#ibcon#wrote, iclass 6, count 0 2006.211.08:26:40.39#ibcon#about to read 3, iclass 6, count 0 2006.211.08:26:40.41#ibcon#read 3, iclass 6, count 0 2006.211.08:26:40.41#ibcon#about to read 4, iclass 6, count 0 2006.211.08:26:40.41#ibcon#read 4, iclass 6, count 0 2006.211.08:26:40.41#ibcon#about to read 5, iclass 6, count 0 2006.211.08:26:40.41#ibcon#read 5, iclass 6, count 0 2006.211.08:26:40.41#ibcon#about to read 6, iclass 6, count 0 2006.211.08:26:40.41#ibcon#read 6, iclass 6, count 0 2006.211.08:26:40.41#ibcon#end of sib2, iclass 6, count 0 2006.211.08:26:40.41#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:26:40.41#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:26:40.41#ibcon#[27=USB\r\n] 2006.211.08:26:40.41#ibcon#*before write, iclass 6, count 0 2006.211.08:26:40.41#ibcon#enter sib2, iclass 6, count 0 2006.211.08:26:40.41#ibcon#flushed, iclass 6, count 0 2006.211.08:26:40.41#ibcon#about to write, iclass 6, count 0 2006.211.08:26:40.41#ibcon#wrote, iclass 6, count 0 2006.211.08:26:40.41#ibcon#about to read 3, iclass 6, count 0 2006.211.08:26:40.44#ibcon#read 3, iclass 6, count 0 2006.211.08:26:40.44#ibcon#about to read 4, iclass 6, count 0 2006.211.08:26:40.44#ibcon#read 4, iclass 6, count 0 2006.211.08:26:40.44#ibcon#about to read 5, iclass 6, count 0 2006.211.08:26:40.44#ibcon#read 5, iclass 6, count 0 2006.211.08:26:40.44#ibcon#about to read 6, iclass 6, count 0 2006.211.08:26:40.44#ibcon#read 6, iclass 6, count 0 2006.211.08:26:40.44#ibcon#end of sib2, iclass 6, count 0 2006.211.08:26:40.44#ibcon#*after write, iclass 6, count 0 2006.211.08:26:40.44#ibcon#*before return 0, iclass 6, count 0 2006.211.08:26:40.44#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:40.44#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:26:40.44#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:26:40.44#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:26:40.44$vc4f8/vblo=2,640.99 2006.211.08:26:40.44#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:26:40.44#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:26:40.44#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:40.44#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:40.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:40.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:40.44#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:26:40.44#ibcon#first serial, iclass 10, count 0 2006.211.08:26:40.44#ibcon#enter sib2, iclass 10, count 0 2006.211.08:26:40.44#ibcon#flushed, iclass 10, count 0 2006.211.08:26:40.44#ibcon#about to write, iclass 10, count 0 2006.211.08:26:40.44#ibcon#wrote, iclass 10, count 0 2006.211.08:26:40.44#ibcon#about to read 3, iclass 10, count 0 2006.211.08:26:40.46#ibcon#read 3, iclass 10, count 0 2006.211.08:26:40.46#ibcon#about to read 4, iclass 10, count 0 2006.211.08:26:40.46#ibcon#read 4, iclass 10, count 0 2006.211.08:26:40.46#ibcon#about to read 5, iclass 10, count 0 2006.211.08:26:40.46#ibcon#read 5, iclass 10, count 0 2006.211.08:26:40.46#ibcon#about to read 6, iclass 10, count 0 2006.211.08:26:40.46#ibcon#read 6, iclass 10, count 0 2006.211.08:26:40.46#ibcon#end of sib2, iclass 10, count 0 2006.211.08:26:40.46#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:26:40.46#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:26:40.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:26:40.46#ibcon#*before write, iclass 10, count 0 2006.211.08:26:40.46#ibcon#enter sib2, iclass 10, count 0 2006.211.08:26:40.46#ibcon#flushed, iclass 10, count 0 2006.211.08:26:40.46#ibcon#about to write, iclass 10, count 0 2006.211.08:26:40.46#ibcon#wrote, iclass 10, count 0 2006.211.08:26:40.46#ibcon#about to read 3, iclass 10, count 0 2006.211.08:26:40.50#ibcon#read 3, iclass 10, count 0 2006.211.08:26:40.50#ibcon#about to read 4, iclass 10, count 0 2006.211.08:26:40.50#ibcon#read 4, iclass 10, count 0 2006.211.08:26:40.50#ibcon#about to read 5, iclass 10, count 0 2006.211.08:26:40.50#ibcon#read 5, iclass 10, count 0 2006.211.08:26:40.50#ibcon#about to read 6, iclass 10, count 0 2006.211.08:26:40.50#ibcon#read 6, iclass 10, count 0 2006.211.08:26:40.50#ibcon#end of sib2, iclass 10, count 0 2006.211.08:26:40.50#ibcon#*after write, iclass 10, count 0 2006.211.08:26:40.50#ibcon#*before return 0, iclass 10, count 0 2006.211.08:26:40.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:40.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:26:40.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:26:40.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:26:40.50$vc4f8/vb=2,4 2006.211.08:26:40.50#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:26:40.50#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:26:40.50#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:40.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:40.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:40.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:40.56#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:26:40.56#ibcon#first serial, iclass 12, count 2 2006.211.08:26:40.56#ibcon#enter sib2, iclass 12, count 2 2006.211.08:26:40.56#ibcon#flushed, iclass 12, count 2 2006.211.08:26:40.56#ibcon#about to write, iclass 12, count 2 2006.211.08:26:40.56#ibcon#wrote, iclass 12, count 2 2006.211.08:26:40.56#ibcon#about to read 3, iclass 12, count 2 2006.211.08:26:40.58#ibcon#read 3, iclass 12, count 2 2006.211.08:26:40.58#ibcon#about to read 4, iclass 12, count 2 2006.211.08:26:40.58#ibcon#read 4, iclass 12, count 2 2006.211.08:26:40.58#ibcon#about to read 5, iclass 12, count 2 2006.211.08:26:40.58#ibcon#read 5, iclass 12, count 2 2006.211.08:26:40.58#ibcon#about to read 6, iclass 12, count 2 2006.211.08:26:40.58#ibcon#read 6, iclass 12, count 2 2006.211.08:26:40.58#ibcon#end of sib2, iclass 12, count 2 2006.211.08:26:40.58#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:26:40.58#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:26:40.58#ibcon#[27=AT02-04\r\n] 2006.211.08:26:40.58#ibcon#*before write, iclass 12, count 2 2006.211.08:26:40.58#ibcon#enter sib2, iclass 12, count 2 2006.211.08:26:40.58#ibcon#flushed, iclass 12, count 2 2006.211.08:26:40.58#ibcon#about to write, iclass 12, count 2 2006.211.08:26:40.58#ibcon#wrote, iclass 12, count 2 2006.211.08:26:40.58#ibcon#about to read 3, iclass 12, count 2 2006.211.08:26:40.61#ibcon#read 3, iclass 12, count 2 2006.211.08:26:40.61#ibcon#about to read 4, iclass 12, count 2 2006.211.08:26:40.61#ibcon#read 4, iclass 12, count 2 2006.211.08:26:40.61#ibcon#about to read 5, iclass 12, count 2 2006.211.08:26:40.61#ibcon#read 5, iclass 12, count 2 2006.211.08:26:40.61#ibcon#about to read 6, iclass 12, count 2 2006.211.08:26:40.61#ibcon#read 6, iclass 12, count 2 2006.211.08:26:40.61#ibcon#end of sib2, iclass 12, count 2 2006.211.08:26:40.61#ibcon#*after write, iclass 12, count 2 2006.211.08:26:40.61#ibcon#*before return 0, iclass 12, count 2 2006.211.08:26:40.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:40.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:26:40.61#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:26:40.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:40.61#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:40.73#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:40.73#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:40.73#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:26:40.73#ibcon#first serial, iclass 12, count 0 2006.211.08:26:40.73#ibcon#enter sib2, iclass 12, count 0 2006.211.08:26:40.73#ibcon#flushed, iclass 12, count 0 2006.211.08:26:40.73#ibcon#about to write, iclass 12, count 0 2006.211.08:26:40.73#ibcon#wrote, iclass 12, count 0 2006.211.08:26:40.73#ibcon#about to read 3, iclass 12, count 0 2006.211.08:26:40.75#ibcon#read 3, iclass 12, count 0 2006.211.08:26:40.75#ibcon#about to read 4, iclass 12, count 0 2006.211.08:26:40.75#ibcon#read 4, iclass 12, count 0 2006.211.08:26:40.75#ibcon#about to read 5, iclass 12, count 0 2006.211.08:26:40.75#ibcon#read 5, iclass 12, count 0 2006.211.08:26:40.75#ibcon#about to read 6, iclass 12, count 0 2006.211.08:26:40.75#ibcon#read 6, iclass 12, count 0 2006.211.08:26:40.75#ibcon#end of sib2, iclass 12, count 0 2006.211.08:26:40.75#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:26:40.75#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:26:40.75#ibcon#[27=USB\r\n] 2006.211.08:26:40.75#ibcon#*before write, iclass 12, count 0 2006.211.08:26:40.75#ibcon#enter sib2, iclass 12, count 0 2006.211.08:26:40.75#ibcon#flushed, iclass 12, count 0 2006.211.08:26:40.75#ibcon#about to write, iclass 12, count 0 2006.211.08:26:40.75#ibcon#wrote, iclass 12, count 0 2006.211.08:26:40.75#ibcon#about to read 3, iclass 12, count 0 2006.211.08:26:40.78#ibcon#read 3, iclass 12, count 0 2006.211.08:26:40.78#ibcon#about to read 4, iclass 12, count 0 2006.211.08:26:40.78#ibcon#read 4, iclass 12, count 0 2006.211.08:26:40.78#ibcon#about to read 5, iclass 12, count 0 2006.211.08:26:40.78#ibcon#read 5, iclass 12, count 0 2006.211.08:26:40.78#ibcon#about to read 6, iclass 12, count 0 2006.211.08:26:40.78#ibcon#read 6, iclass 12, count 0 2006.211.08:26:40.78#ibcon#end of sib2, iclass 12, count 0 2006.211.08:26:40.78#ibcon#*after write, iclass 12, count 0 2006.211.08:26:40.78#ibcon#*before return 0, iclass 12, count 0 2006.211.08:26:40.78#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:40.78#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:26:40.78#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:26:40.78#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:26:40.78$vc4f8/vblo=3,656.99 2006.211.08:26:40.78#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:26:40.78#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:26:40.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:40.78#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:40.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:40.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:40.78#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:26:40.78#ibcon#first serial, iclass 14, count 0 2006.211.08:26:40.78#ibcon#enter sib2, iclass 14, count 0 2006.211.08:26:40.78#ibcon#flushed, iclass 14, count 0 2006.211.08:26:40.78#ibcon#about to write, iclass 14, count 0 2006.211.08:26:40.78#ibcon#wrote, iclass 14, count 0 2006.211.08:26:40.78#ibcon#about to read 3, iclass 14, count 0 2006.211.08:26:40.80#ibcon#read 3, iclass 14, count 0 2006.211.08:26:40.80#ibcon#about to read 4, iclass 14, count 0 2006.211.08:26:40.80#ibcon#read 4, iclass 14, count 0 2006.211.08:26:40.80#ibcon#about to read 5, iclass 14, count 0 2006.211.08:26:40.80#ibcon#read 5, iclass 14, count 0 2006.211.08:26:40.80#ibcon#about to read 6, iclass 14, count 0 2006.211.08:26:40.80#ibcon#read 6, iclass 14, count 0 2006.211.08:26:40.80#ibcon#end of sib2, iclass 14, count 0 2006.211.08:26:40.80#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:26:40.80#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:26:40.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:26:40.80#ibcon#*before write, iclass 14, count 0 2006.211.08:26:40.80#ibcon#enter sib2, iclass 14, count 0 2006.211.08:26:40.80#ibcon#flushed, iclass 14, count 0 2006.211.08:26:40.80#ibcon#about to write, iclass 14, count 0 2006.211.08:26:40.80#ibcon#wrote, iclass 14, count 0 2006.211.08:26:40.80#ibcon#about to read 3, iclass 14, count 0 2006.211.08:26:40.84#ibcon#read 3, iclass 14, count 0 2006.211.08:26:40.84#ibcon#about to read 4, iclass 14, count 0 2006.211.08:26:40.84#ibcon#read 4, iclass 14, count 0 2006.211.08:26:40.84#ibcon#about to read 5, iclass 14, count 0 2006.211.08:26:40.84#ibcon#read 5, iclass 14, count 0 2006.211.08:26:40.84#ibcon#about to read 6, iclass 14, count 0 2006.211.08:26:40.84#ibcon#read 6, iclass 14, count 0 2006.211.08:26:40.84#ibcon#end of sib2, iclass 14, count 0 2006.211.08:26:40.84#ibcon#*after write, iclass 14, count 0 2006.211.08:26:40.84#ibcon#*before return 0, iclass 14, count 0 2006.211.08:26:40.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:40.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:26:40.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:26:40.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:26:40.84$vc4f8/vb=3,3 2006.211.08:26:40.84#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:26:40.84#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:26:40.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:40.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:40.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:40.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:40.90#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:26:40.90#ibcon#first serial, iclass 16, count 2 2006.211.08:26:40.90#ibcon#enter sib2, iclass 16, count 2 2006.211.08:26:40.90#ibcon#flushed, iclass 16, count 2 2006.211.08:26:40.90#ibcon#about to write, iclass 16, count 2 2006.211.08:26:40.90#ibcon#wrote, iclass 16, count 2 2006.211.08:26:40.90#ibcon#about to read 3, iclass 16, count 2 2006.211.08:26:40.92#ibcon#read 3, iclass 16, count 2 2006.211.08:26:40.92#ibcon#about to read 4, iclass 16, count 2 2006.211.08:26:40.92#ibcon#read 4, iclass 16, count 2 2006.211.08:26:40.92#ibcon#about to read 5, iclass 16, count 2 2006.211.08:26:40.92#ibcon#read 5, iclass 16, count 2 2006.211.08:26:40.92#ibcon#about to read 6, iclass 16, count 2 2006.211.08:26:40.92#ibcon#read 6, iclass 16, count 2 2006.211.08:26:40.92#ibcon#end of sib2, iclass 16, count 2 2006.211.08:26:40.92#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:26:40.92#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:26:40.92#ibcon#[27=AT03-03\r\n] 2006.211.08:26:40.92#ibcon#*before write, iclass 16, count 2 2006.211.08:26:40.92#ibcon#enter sib2, iclass 16, count 2 2006.211.08:26:40.92#ibcon#flushed, iclass 16, count 2 2006.211.08:26:40.92#ibcon#about to write, iclass 16, count 2 2006.211.08:26:40.92#ibcon#wrote, iclass 16, count 2 2006.211.08:26:40.92#ibcon#about to read 3, iclass 16, count 2 2006.211.08:26:40.95#ibcon#read 3, iclass 16, count 2 2006.211.08:26:40.95#ibcon#about to read 4, iclass 16, count 2 2006.211.08:26:40.95#ibcon#read 4, iclass 16, count 2 2006.211.08:26:40.95#ibcon#about to read 5, iclass 16, count 2 2006.211.08:26:40.95#ibcon#read 5, iclass 16, count 2 2006.211.08:26:40.95#ibcon#about to read 6, iclass 16, count 2 2006.211.08:26:40.95#ibcon#read 6, iclass 16, count 2 2006.211.08:26:40.95#ibcon#end of sib2, iclass 16, count 2 2006.211.08:26:40.95#ibcon#*after write, iclass 16, count 2 2006.211.08:26:40.95#ibcon#*before return 0, iclass 16, count 2 2006.211.08:26:40.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:40.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:26:40.95#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:26:40.95#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:40.95#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:41.07#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:41.07#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:41.07#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:26:41.07#ibcon#first serial, iclass 16, count 0 2006.211.08:26:41.07#ibcon#enter sib2, iclass 16, count 0 2006.211.08:26:41.07#ibcon#flushed, iclass 16, count 0 2006.211.08:26:41.07#ibcon#about to write, iclass 16, count 0 2006.211.08:26:41.07#ibcon#wrote, iclass 16, count 0 2006.211.08:26:41.07#ibcon#about to read 3, iclass 16, count 0 2006.211.08:26:41.09#ibcon#read 3, iclass 16, count 0 2006.211.08:26:41.09#ibcon#about to read 4, iclass 16, count 0 2006.211.08:26:41.09#ibcon#read 4, iclass 16, count 0 2006.211.08:26:41.09#ibcon#about to read 5, iclass 16, count 0 2006.211.08:26:41.09#ibcon#read 5, iclass 16, count 0 2006.211.08:26:41.09#ibcon#about to read 6, iclass 16, count 0 2006.211.08:26:41.09#ibcon#read 6, iclass 16, count 0 2006.211.08:26:41.09#ibcon#end of sib2, iclass 16, count 0 2006.211.08:26:41.09#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:26:41.09#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:26:41.09#ibcon#[27=USB\r\n] 2006.211.08:26:41.09#ibcon#*before write, iclass 16, count 0 2006.211.08:26:41.09#ibcon#enter sib2, iclass 16, count 0 2006.211.08:26:41.09#ibcon#flushed, iclass 16, count 0 2006.211.08:26:41.09#ibcon#about to write, iclass 16, count 0 2006.211.08:26:41.09#ibcon#wrote, iclass 16, count 0 2006.211.08:26:41.09#ibcon#about to read 3, iclass 16, count 0 2006.211.08:26:41.12#ibcon#read 3, iclass 16, count 0 2006.211.08:26:41.12#ibcon#about to read 4, iclass 16, count 0 2006.211.08:26:41.12#ibcon#read 4, iclass 16, count 0 2006.211.08:26:41.12#ibcon#about to read 5, iclass 16, count 0 2006.211.08:26:41.12#ibcon#read 5, iclass 16, count 0 2006.211.08:26:41.12#ibcon#about to read 6, iclass 16, count 0 2006.211.08:26:41.12#ibcon#read 6, iclass 16, count 0 2006.211.08:26:41.12#ibcon#end of sib2, iclass 16, count 0 2006.211.08:26:41.12#ibcon#*after write, iclass 16, count 0 2006.211.08:26:41.12#ibcon#*before return 0, iclass 16, count 0 2006.211.08:26:41.12#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:41.12#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:26:41.12#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:26:41.12#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:26:41.12$vc4f8/vblo=4,712.99 2006.211.08:26:41.12#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:26:41.12#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:26:41.12#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:41.12#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:41.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:41.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:41.12#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:26:41.12#ibcon#first serial, iclass 18, count 0 2006.211.08:26:41.12#ibcon#enter sib2, iclass 18, count 0 2006.211.08:26:41.12#ibcon#flushed, iclass 18, count 0 2006.211.08:26:41.12#ibcon#about to write, iclass 18, count 0 2006.211.08:26:41.12#ibcon#wrote, iclass 18, count 0 2006.211.08:26:41.12#ibcon#about to read 3, iclass 18, count 0 2006.211.08:26:41.14#ibcon#read 3, iclass 18, count 0 2006.211.08:26:41.14#ibcon#about to read 4, iclass 18, count 0 2006.211.08:26:41.14#ibcon#read 4, iclass 18, count 0 2006.211.08:26:41.14#ibcon#about to read 5, iclass 18, count 0 2006.211.08:26:41.14#ibcon#read 5, iclass 18, count 0 2006.211.08:26:41.14#ibcon#about to read 6, iclass 18, count 0 2006.211.08:26:41.14#ibcon#read 6, iclass 18, count 0 2006.211.08:26:41.14#ibcon#end of sib2, iclass 18, count 0 2006.211.08:26:41.14#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:26:41.14#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:26:41.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:26:41.14#ibcon#*before write, iclass 18, count 0 2006.211.08:26:41.14#ibcon#enter sib2, iclass 18, count 0 2006.211.08:26:41.14#ibcon#flushed, iclass 18, count 0 2006.211.08:26:41.14#ibcon#about to write, iclass 18, count 0 2006.211.08:26:41.14#ibcon#wrote, iclass 18, count 0 2006.211.08:26:41.14#ibcon#about to read 3, iclass 18, count 0 2006.211.08:26:41.18#ibcon#read 3, iclass 18, count 0 2006.211.08:26:41.18#ibcon#about to read 4, iclass 18, count 0 2006.211.08:26:41.18#ibcon#read 4, iclass 18, count 0 2006.211.08:26:41.18#ibcon#about to read 5, iclass 18, count 0 2006.211.08:26:41.18#ibcon#read 5, iclass 18, count 0 2006.211.08:26:41.18#ibcon#about to read 6, iclass 18, count 0 2006.211.08:26:41.18#ibcon#read 6, iclass 18, count 0 2006.211.08:26:41.18#ibcon#end of sib2, iclass 18, count 0 2006.211.08:26:41.18#ibcon#*after write, iclass 18, count 0 2006.211.08:26:41.18#ibcon#*before return 0, iclass 18, count 0 2006.211.08:26:41.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:41.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:26:41.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:26:41.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:26:41.18$vc4f8/vb=4,3 2006.211.08:26:41.18#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:26:41.18#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:26:41.18#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:41.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:41.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:41.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:41.24#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:26:41.24#ibcon#first serial, iclass 20, count 2 2006.211.08:26:41.24#ibcon#enter sib2, iclass 20, count 2 2006.211.08:26:41.24#ibcon#flushed, iclass 20, count 2 2006.211.08:26:41.24#ibcon#about to write, iclass 20, count 2 2006.211.08:26:41.24#ibcon#wrote, iclass 20, count 2 2006.211.08:26:41.24#ibcon#about to read 3, iclass 20, count 2 2006.211.08:26:41.26#ibcon#read 3, iclass 20, count 2 2006.211.08:26:41.26#ibcon#about to read 4, iclass 20, count 2 2006.211.08:26:41.26#ibcon#read 4, iclass 20, count 2 2006.211.08:26:41.26#ibcon#about to read 5, iclass 20, count 2 2006.211.08:26:41.26#ibcon#read 5, iclass 20, count 2 2006.211.08:26:41.26#ibcon#about to read 6, iclass 20, count 2 2006.211.08:26:41.26#ibcon#read 6, iclass 20, count 2 2006.211.08:26:41.26#ibcon#end of sib2, iclass 20, count 2 2006.211.08:26:41.26#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:26:41.26#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:26:41.26#ibcon#[27=AT04-03\r\n] 2006.211.08:26:41.26#ibcon#*before write, iclass 20, count 2 2006.211.08:26:41.26#ibcon#enter sib2, iclass 20, count 2 2006.211.08:26:41.26#ibcon#flushed, iclass 20, count 2 2006.211.08:26:41.26#ibcon#about to write, iclass 20, count 2 2006.211.08:26:41.26#ibcon#wrote, iclass 20, count 2 2006.211.08:26:41.26#ibcon#about to read 3, iclass 20, count 2 2006.211.08:26:41.29#ibcon#read 3, iclass 20, count 2 2006.211.08:26:41.29#ibcon#about to read 4, iclass 20, count 2 2006.211.08:26:41.29#ibcon#read 4, iclass 20, count 2 2006.211.08:26:41.29#ibcon#about to read 5, iclass 20, count 2 2006.211.08:26:41.29#ibcon#read 5, iclass 20, count 2 2006.211.08:26:41.29#ibcon#about to read 6, iclass 20, count 2 2006.211.08:26:41.29#ibcon#read 6, iclass 20, count 2 2006.211.08:26:41.29#ibcon#end of sib2, iclass 20, count 2 2006.211.08:26:41.29#ibcon#*after write, iclass 20, count 2 2006.211.08:26:41.29#ibcon#*before return 0, iclass 20, count 2 2006.211.08:26:41.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:41.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:26:41.29#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:26:41.29#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:41.29#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:41.41#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:41.41#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:41.41#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:26:41.41#ibcon#first serial, iclass 20, count 0 2006.211.08:26:41.41#ibcon#enter sib2, iclass 20, count 0 2006.211.08:26:41.41#ibcon#flushed, iclass 20, count 0 2006.211.08:26:41.41#ibcon#about to write, iclass 20, count 0 2006.211.08:26:41.41#ibcon#wrote, iclass 20, count 0 2006.211.08:26:41.41#ibcon#about to read 3, iclass 20, count 0 2006.211.08:26:41.43#ibcon#read 3, iclass 20, count 0 2006.211.08:26:41.43#ibcon#about to read 4, iclass 20, count 0 2006.211.08:26:41.43#ibcon#read 4, iclass 20, count 0 2006.211.08:26:41.43#ibcon#about to read 5, iclass 20, count 0 2006.211.08:26:41.43#ibcon#read 5, iclass 20, count 0 2006.211.08:26:41.43#ibcon#about to read 6, iclass 20, count 0 2006.211.08:26:41.43#ibcon#read 6, iclass 20, count 0 2006.211.08:26:41.43#ibcon#end of sib2, iclass 20, count 0 2006.211.08:26:41.43#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:26:41.43#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:26:41.43#ibcon#[27=USB\r\n] 2006.211.08:26:41.43#ibcon#*before write, iclass 20, count 0 2006.211.08:26:41.43#ibcon#enter sib2, iclass 20, count 0 2006.211.08:26:41.43#ibcon#flushed, iclass 20, count 0 2006.211.08:26:41.43#ibcon#about to write, iclass 20, count 0 2006.211.08:26:41.43#ibcon#wrote, iclass 20, count 0 2006.211.08:26:41.43#ibcon#about to read 3, iclass 20, count 0 2006.211.08:26:41.46#ibcon#read 3, iclass 20, count 0 2006.211.08:26:41.46#ibcon#about to read 4, iclass 20, count 0 2006.211.08:26:41.46#ibcon#read 4, iclass 20, count 0 2006.211.08:26:41.46#ibcon#about to read 5, iclass 20, count 0 2006.211.08:26:41.46#ibcon#read 5, iclass 20, count 0 2006.211.08:26:41.46#ibcon#about to read 6, iclass 20, count 0 2006.211.08:26:41.46#ibcon#read 6, iclass 20, count 0 2006.211.08:26:41.46#ibcon#end of sib2, iclass 20, count 0 2006.211.08:26:41.46#ibcon#*after write, iclass 20, count 0 2006.211.08:26:41.46#ibcon#*before return 0, iclass 20, count 0 2006.211.08:26:41.46#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:41.46#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:26:41.46#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:26:41.46#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:26:41.46$vc4f8/vblo=5,744.99 2006.211.08:26:41.46#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:26:41.46#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:26:41.46#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:41.46#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:26:41.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:26:41.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:26:41.46#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:26:41.46#ibcon#first serial, iclass 22, count 0 2006.211.08:26:41.46#ibcon#enter sib2, iclass 22, count 0 2006.211.08:26:41.46#ibcon#flushed, iclass 22, count 0 2006.211.08:26:41.46#ibcon#about to write, iclass 22, count 0 2006.211.08:26:41.46#ibcon#wrote, iclass 22, count 0 2006.211.08:26:41.46#ibcon#about to read 3, iclass 22, count 0 2006.211.08:26:41.48#ibcon#read 3, iclass 22, count 0 2006.211.08:26:41.48#ibcon#about to read 4, iclass 22, count 0 2006.211.08:26:41.48#ibcon#read 4, iclass 22, count 0 2006.211.08:26:41.48#ibcon#about to read 5, iclass 22, count 0 2006.211.08:26:41.48#ibcon#read 5, iclass 22, count 0 2006.211.08:26:41.48#ibcon#about to read 6, iclass 22, count 0 2006.211.08:26:41.48#ibcon#read 6, iclass 22, count 0 2006.211.08:26:41.48#ibcon#end of sib2, iclass 22, count 0 2006.211.08:26:41.48#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:26:41.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:26:41.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:26:41.48#ibcon#*before write, iclass 22, count 0 2006.211.08:26:41.48#ibcon#enter sib2, iclass 22, count 0 2006.211.08:26:41.48#ibcon#flushed, iclass 22, count 0 2006.211.08:26:41.48#ibcon#about to write, iclass 22, count 0 2006.211.08:26:41.48#ibcon#wrote, iclass 22, count 0 2006.211.08:26:41.48#ibcon#about to read 3, iclass 22, count 0 2006.211.08:26:41.52#ibcon#read 3, iclass 22, count 0 2006.211.08:26:41.52#ibcon#about to read 4, iclass 22, count 0 2006.211.08:26:41.52#ibcon#read 4, iclass 22, count 0 2006.211.08:26:41.52#ibcon#about to read 5, iclass 22, count 0 2006.211.08:26:41.52#ibcon#read 5, iclass 22, count 0 2006.211.08:26:41.52#ibcon#about to read 6, iclass 22, count 0 2006.211.08:26:41.52#ibcon#read 6, iclass 22, count 0 2006.211.08:26:41.52#ibcon#end of sib2, iclass 22, count 0 2006.211.08:26:41.52#ibcon#*after write, iclass 22, count 0 2006.211.08:26:41.52#ibcon#*before return 0, iclass 22, count 0 2006.211.08:26:41.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:26:41.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:26:41.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:26:41.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:26:41.52$vc4f8/vb=5,3 2006.211.08:26:41.52#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:26:41.52#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:26:41.52#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:41.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:26:41.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:26:41.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:26:41.58#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:26:41.58#ibcon#first serial, iclass 24, count 2 2006.211.08:26:41.58#ibcon#enter sib2, iclass 24, count 2 2006.211.08:26:41.58#ibcon#flushed, iclass 24, count 2 2006.211.08:26:41.58#ibcon#about to write, iclass 24, count 2 2006.211.08:26:41.58#ibcon#wrote, iclass 24, count 2 2006.211.08:26:41.58#ibcon#about to read 3, iclass 24, count 2 2006.211.08:26:41.60#ibcon#read 3, iclass 24, count 2 2006.211.08:26:41.60#ibcon#about to read 4, iclass 24, count 2 2006.211.08:26:41.60#ibcon#read 4, iclass 24, count 2 2006.211.08:26:41.60#ibcon#about to read 5, iclass 24, count 2 2006.211.08:26:41.60#ibcon#read 5, iclass 24, count 2 2006.211.08:26:41.60#ibcon#about to read 6, iclass 24, count 2 2006.211.08:26:41.60#ibcon#read 6, iclass 24, count 2 2006.211.08:26:41.60#ibcon#end of sib2, iclass 24, count 2 2006.211.08:26:41.60#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:26:41.60#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:26:41.60#ibcon#[27=AT05-03\r\n] 2006.211.08:26:41.60#ibcon#*before write, iclass 24, count 2 2006.211.08:26:41.60#ibcon#enter sib2, iclass 24, count 2 2006.211.08:26:41.60#ibcon#flushed, iclass 24, count 2 2006.211.08:26:41.60#ibcon#about to write, iclass 24, count 2 2006.211.08:26:41.60#ibcon#wrote, iclass 24, count 2 2006.211.08:26:41.60#ibcon#about to read 3, iclass 24, count 2 2006.211.08:26:41.63#ibcon#read 3, iclass 24, count 2 2006.211.08:26:41.63#ibcon#about to read 4, iclass 24, count 2 2006.211.08:26:41.63#ibcon#read 4, iclass 24, count 2 2006.211.08:26:41.63#ibcon#about to read 5, iclass 24, count 2 2006.211.08:26:41.63#ibcon#read 5, iclass 24, count 2 2006.211.08:26:41.63#ibcon#about to read 6, iclass 24, count 2 2006.211.08:26:41.63#ibcon#read 6, iclass 24, count 2 2006.211.08:26:41.63#ibcon#end of sib2, iclass 24, count 2 2006.211.08:26:41.63#ibcon#*after write, iclass 24, count 2 2006.211.08:26:41.63#ibcon#*before return 0, iclass 24, count 2 2006.211.08:26:41.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:26:41.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:26:41.63#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:26:41.63#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:41.63#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:26:41.75#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:26:41.75#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:26:41.75#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:26:41.75#ibcon#first serial, iclass 24, count 0 2006.211.08:26:41.75#ibcon#enter sib2, iclass 24, count 0 2006.211.08:26:41.75#ibcon#flushed, iclass 24, count 0 2006.211.08:26:41.75#ibcon#about to write, iclass 24, count 0 2006.211.08:26:41.75#ibcon#wrote, iclass 24, count 0 2006.211.08:26:41.75#ibcon#about to read 3, iclass 24, count 0 2006.211.08:26:41.77#ibcon#read 3, iclass 24, count 0 2006.211.08:26:41.77#ibcon#about to read 4, iclass 24, count 0 2006.211.08:26:41.77#ibcon#read 4, iclass 24, count 0 2006.211.08:26:41.77#ibcon#about to read 5, iclass 24, count 0 2006.211.08:26:41.77#ibcon#read 5, iclass 24, count 0 2006.211.08:26:41.77#ibcon#about to read 6, iclass 24, count 0 2006.211.08:26:41.77#ibcon#read 6, iclass 24, count 0 2006.211.08:26:41.77#ibcon#end of sib2, iclass 24, count 0 2006.211.08:26:41.77#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:26:41.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:26:41.77#ibcon#[27=USB\r\n] 2006.211.08:26:41.77#ibcon#*before write, iclass 24, count 0 2006.211.08:26:41.77#ibcon#enter sib2, iclass 24, count 0 2006.211.08:26:41.77#ibcon#flushed, iclass 24, count 0 2006.211.08:26:41.77#ibcon#about to write, iclass 24, count 0 2006.211.08:26:41.77#ibcon#wrote, iclass 24, count 0 2006.211.08:26:41.77#ibcon#about to read 3, iclass 24, count 0 2006.211.08:26:41.80#ibcon#read 3, iclass 24, count 0 2006.211.08:26:41.80#ibcon#about to read 4, iclass 24, count 0 2006.211.08:26:41.80#ibcon#read 4, iclass 24, count 0 2006.211.08:26:41.80#ibcon#about to read 5, iclass 24, count 0 2006.211.08:26:41.80#ibcon#read 5, iclass 24, count 0 2006.211.08:26:41.80#ibcon#about to read 6, iclass 24, count 0 2006.211.08:26:41.80#ibcon#read 6, iclass 24, count 0 2006.211.08:26:41.80#ibcon#end of sib2, iclass 24, count 0 2006.211.08:26:41.80#ibcon#*after write, iclass 24, count 0 2006.211.08:26:41.80#ibcon#*before return 0, iclass 24, count 0 2006.211.08:26:41.80#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:26:41.80#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:26:41.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:26:41.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:26:41.80$vc4f8/vblo=6,752.99 2006.211.08:26:41.80#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:26:41.80#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:26:41.80#ibcon#ireg 17 cls_cnt 0 2006.211.08:26:41.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:41.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:41.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:41.80#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:26:41.80#ibcon#first serial, iclass 26, count 0 2006.211.08:26:41.80#ibcon#enter sib2, iclass 26, count 0 2006.211.08:26:41.80#ibcon#flushed, iclass 26, count 0 2006.211.08:26:41.80#ibcon#about to write, iclass 26, count 0 2006.211.08:26:41.80#ibcon#wrote, iclass 26, count 0 2006.211.08:26:41.80#ibcon#about to read 3, iclass 26, count 0 2006.211.08:26:41.82#ibcon#read 3, iclass 26, count 0 2006.211.08:26:41.82#ibcon#about to read 4, iclass 26, count 0 2006.211.08:26:41.82#ibcon#read 4, iclass 26, count 0 2006.211.08:26:41.82#ibcon#about to read 5, iclass 26, count 0 2006.211.08:26:41.82#ibcon#read 5, iclass 26, count 0 2006.211.08:26:41.82#ibcon#about to read 6, iclass 26, count 0 2006.211.08:26:41.82#ibcon#read 6, iclass 26, count 0 2006.211.08:26:41.82#ibcon#end of sib2, iclass 26, count 0 2006.211.08:26:41.82#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:26:41.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:26:41.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:26:41.82#ibcon#*before write, iclass 26, count 0 2006.211.08:26:41.82#ibcon#enter sib2, iclass 26, count 0 2006.211.08:26:41.82#ibcon#flushed, iclass 26, count 0 2006.211.08:26:41.82#ibcon#about to write, iclass 26, count 0 2006.211.08:26:41.82#ibcon#wrote, iclass 26, count 0 2006.211.08:26:41.82#ibcon#about to read 3, iclass 26, count 0 2006.211.08:26:41.86#ibcon#read 3, iclass 26, count 0 2006.211.08:26:41.86#ibcon#about to read 4, iclass 26, count 0 2006.211.08:26:41.86#ibcon#read 4, iclass 26, count 0 2006.211.08:26:41.86#ibcon#about to read 5, iclass 26, count 0 2006.211.08:26:41.86#ibcon#read 5, iclass 26, count 0 2006.211.08:26:41.86#ibcon#about to read 6, iclass 26, count 0 2006.211.08:26:41.86#ibcon#read 6, iclass 26, count 0 2006.211.08:26:41.86#ibcon#end of sib2, iclass 26, count 0 2006.211.08:26:41.86#ibcon#*after write, iclass 26, count 0 2006.211.08:26:41.86#ibcon#*before return 0, iclass 26, count 0 2006.211.08:26:41.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:41.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:26:41.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:26:41.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:26:41.86$vc4f8/vb=6,3 2006.211.08:26:41.86#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:26:41.86#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:26:41.86#ibcon#ireg 11 cls_cnt 2 2006.211.08:26:41.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:41.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:41.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:41.92#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:26:41.92#ibcon#first serial, iclass 28, count 2 2006.211.08:26:41.92#ibcon#enter sib2, iclass 28, count 2 2006.211.08:26:41.92#ibcon#flushed, iclass 28, count 2 2006.211.08:26:41.92#ibcon#about to write, iclass 28, count 2 2006.211.08:26:41.92#ibcon#wrote, iclass 28, count 2 2006.211.08:26:41.92#ibcon#about to read 3, iclass 28, count 2 2006.211.08:26:41.94#ibcon#read 3, iclass 28, count 2 2006.211.08:26:41.94#ibcon#about to read 4, iclass 28, count 2 2006.211.08:26:41.94#ibcon#read 4, iclass 28, count 2 2006.211.08:26:41.94#ibcon#about to read 5, iclass 28, count 2 2006.211.08:26:41.94#ibcon#read 5, iclass 28, count 2 2006.211.08:26:41.94#ibcon#about to read 6, iclass 28, count 2 2006.211.08:26:41.94#ibcon#read 6, iclass 28, count 2 2006.211.08:26:41.94#ibcon#end of sib2, iclass 28, count 2 2006.211.08:26:41.94#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:26:41.94#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:26:41.94#ibcon#[27=AT06-03\r\n] 2006.211.08:26:41.94#ibcon#*before write, iclass 28, count 2 2006.211.08:26:41.94#ibcon#enter sib2, iclass 28, count 2 2006.211.08:26:41.94#ibcon#flushed, iclass 28, count 2 2006.211.08:26:41.94#ibcon#about to write, iclass 28, count 2 2006.211.08:26:41.94#ibcon#wrote, iclass 28, count 2 2006.211.08:26:41.94#ibcon#about to read 3, iclass 28, count 2 2006.211.08:26:41.97#ibcon#read 3, iclass 28, count 2 2006.211.08:26:41.97#ibcon#about to read 4, iclass 28, count 2 2006.211.08:26:41.97#ibcon#read 4, iclass 28, count 2 2006.211.08:26:41.97#ibcon#about to read 5, iclass 28, count 2 2006.211.08:26:41.97#ibcon#read 5, iclass 28, count 2 2006.211.08:26:41.97#ibcon#about to read 6, iclass 28, count 2 2006.211.08:26:41.97#ibcon#read 6, iclass 28, count 2 2006.211.08:26:41.97#ibcon#end of sib2, iclass 28, count 2 2006.211.08:26:41.97#ibcon#*after write, iclass 28, count 2 2006.211.08:26:41.97#ibcon#*before return 0, iclass 28, count 2 2006.211.08:26:41.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:41.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:26:41.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:26:41.97#ibcon#ireg 7 cls_cnt 0 2006.211.08:26:41.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:42.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:42.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:42.09#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:26:42.09#ibcon#first serial, iclass 28, count 0 2006.211.08:26:42.09#ibcon#enter sib2, iclass 28, count 0 2006.211.08:26:42.09#ibcon#flushed, iclass 28, count 0 2006.211.08:26:42.09#ibcon#about to write, iclass 28, count 0 2006.211.08:26:42.09#ibcon#wrote, iclass 28, count 0 2006.211.08:26:42.09#ibcon#about to read 3, iclass 28, count 0 2006.211.08:26:42.11#ibcon#read 3, iclass 28, count 0 2006.211.08:26:42.11#ibcon#about to read 4, iclass 28, count 0 2006.211.08:26:42.11#ibcon#read 4, iclass 28, count 0 2006.211.08:26:42.11#ibcon#about to read 5, iclass 28, count 0 2006.211.08:26:42.11#ibcon#read 5, iclass 28, count 0 2006.211.08:26:42.11#ibcon#about to read 6, iclass 28, count 0 2006.211.08:26:42.11#ibcon#read 6, iclass 28, count 0 2006.211.08:26:42.11#ibcon#end of sib2, iclass 28, count 0 2006.211.08:26:42.11#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:26:42.11#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:26:42.11#ibcon#[27=USB\r\n] 2006.211.08:26:42.11#ibcon#*before write, iclass 28, count 0 2006.211.08:26:42.11#ibcon#enter sib2, iclass 28, count 0 2006.211.08:26:42.11#ibcon#flushed, iclass 28, count 0 2006.211.08:26:42.11#ibcon#about to write, iclass 28, count 0 2006.211.08:26:42.11#ibcon#wrote, iclass 28, count 0 2006.211.08:26:42.11#ibcon#about to read 3, iclass 28, count 0 2006.211.08:26:42.14#ibcon#read 3, iclass 28, count 0 2006.211.08:26:42.14#ibcon#about to read 4, iclass 28, count 0 2006.211.08:26:42.14#ibcon#read 4, iclass 28, count 0 2006.211.08:26:42.14#ibcon#about to read 5, iclass 28, count 0 2006.211.08:26:42.14#ibcon#read 5, iclass 28, count 0 2006.211.08:26:42.14#ibcon#about to read 6, iclass 28, count 0 2006.211.08:26:42.14#ibcon#read 6, iclass 28, count 0 2006.211.08:26:42.14#ibcon#end of sib2, iclass 28, count 0 2006.211.08:26:42.14#ibcon#*after write, iclass 28, count 0 2006.211.08:26:42.14#ibcon#*before return 0, iclass 28, count 0 2006.211.08:26:42.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:42.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:26:42.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:26:42.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:26:42.14$vc4f8/vabw=wide 2006.211.08:26:42.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:26:42.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:26:42.14#ibcon#ireg 8 cls_cnt 0 2006.211.08:26:42.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:42.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:42.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:42.14#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:26:42.14#ibcon#first serial, iclass 30, count 0 2006.211.08:26:42.14#ibcon#enter sib2, iclass 30, count 0 2006.211.08:26:42.14#ibcon#flushed, iclass 30, count 0 2006.211.08:26:42.14#ibcon#about to write, iclass 30, count 0 2006.211.08:26:42.14#ibcon#wrote, iclass 30, count 0 2006.211.08:26:42.14#ibcon#about to read 3, iclass 30, count 0 2006.211.08:26:42.16#ibcon#read 3, iclass 30, count 0 2006.211.08:26:42.16#ibcon#about to read 4, iclass 30, count 0 2006.211.08:26:42.16#ibcon#read 4, iclass 30, count 0 2006.211.08:26:42.16#ibcon#about to read 5, iclass 30, count 0 2006.211.08:26:42.16#ibcon#read 5, iclass 30, count 0 2006.211.08:26:42.16#ibcon#about to read 6, iclass 30, count 0 2006.211.08:26:42.16#ibcon#read 6, iclass 30, count 0 2006.211.08:26:42.16#ibcon#end of sib2, iclass 30, count 0 2006.211.08:26:42.16#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:26:42.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:26:42.16#ibcon#[25=BW32\r\n] 2006.211.08:26:42.16#ibcon#*before write, iclass 30, count 0 2006.211.08:26:42.16#ibcon#enter sib2, iclass 30, count 0 2006.211.08:26:42.16#ibcon#flushed, iclass 30, count 0 2006.211.08:26:42.16#ibcon#about to write, iclass 30, count 0 2006.211.08:26:42.16#ibcon#wrote, iclass 30, count 0 2006.211.08:26:42.16#ibcon#about to read 3, iclass 30, count 0 2006.211.08:26:42.19#ibcon#read 3, iclass 30, count 0 2006.211.08:26:42.19#ibcon#about to read 4, iclass 30, count 0 2006.211.08:26:42.19#ibcon#read 4, iclass 30, count 0 2006.211.08:26:42.19#ibcon#about to read 5, iclass 30, count 0 2006.211.08:26:42.19#ibcon#read 5, iclass 30, count 0 2006.211.08:26:42.19#ibcon#about to read 6, iclass 30, count 0 2006.211.08:26:42.19#ibcon#read 6, iclass 30, count 0 2006.211.08:26:42.19#ibcon#end of sib2, iclass 30, count 0 2006.211.08:26:42.19#ibcon#*after write, iclass 30, count 0 2006.211.08:26:42.19#ibcon#*before return 0, iclass 30, count 0 2006.211.08:26:42.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:42.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:26:42.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:26:42.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:26:42.19$vc4f8/vbbw=wide 2006.211.08:26:42.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.211.08:26:42.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.211.08:26:42.19#ibcon#ireg 8 cls_cnt 0 2006.211.08:26:42.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:26:42.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:26:42.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:26:42.26#ibcon#enter wrdev, iclass 32, count 0 2006.211.08:26:42.26#ibcon#first serial, iclass 32, count 0 2006.211.08:26:42.26#ibcon#enter sib2, iclass 32, count 0 2006.211.08:26:42.26#ibcon#flushed, iclass 32, count 0 2006.211.08:26:42.26#ibcon#about to write, iclass 32, count 0 2006.211.08:26:42.26#ibcon#wrote, iclass 32, count 0 2006.211.08:26:42.26#ibcon#about to read 3, iclass 32, count 0 2006.211.08:26:42.28#ibcon#read 3, iclass 32, count 0 2006.211.08:26:42.28#ibcon#about to read 4, iclass 32, count 0 2006.211.08:26:42.28#ibcon#read 4, iclass 32, count 0 2006.211.08:26:42.28#ibcon#about to read 5, iclass 32, count 0 2006.211.08:26:42.28#ibcon#read 5, iclass 32, count 0 2006.211.08:26:42.28#ibcon#about to read 6, iclass 32, count 0 2006.211.08:26:42.28#ibcon#read 6, iclass 32, count 0 2006.211.08:26:42.28#ibcon#end of sib2, iclass 32, count 0 2006.211.08:26:42.28#ibcon#*mode == 0, iclass 32, count 0 2006.211.08:26:42.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.08:26:42.28#ibcon#[27=BW32\r\n] 2006.211.08:26:42.28#ibcon#*before write, iclass 32, count 0 2006.211.08:26:42.28#ibcon#enter sib2, iclass 32, count 0 2006.211.08:26:42.28#ibcon#flushed, iclass 32, count 0 2006.211.08:26:42.28#ibcon#about to write, iclass 32, count 0 2006.211.08:26:42.28#ibcon#wrote, iclass 32, count 0 2006.211.08:26:42.28#ibcon#about to read 3, iclass 32, count 0 2006.211.08:26:42.31#ibcon#read 3, iclass 32, count 0 2006.211.08:26:42.31#ibcon#about to read 4, iclass 32, count 0 2006.211.08:26:42.31#ibcon#read 4, iclass 32, count 0 2006.211.08:26:42.31#ibcon#about to read 5, iclass 32, count 0 2006.211.08:26:42.31#ibcon#read 5, iclass 32, count 0 2006.211.08:26:42.31#ibcon#about to read 6, iclass 32, count 0 2006.211.08:26:42.31#ibcon#read 6, iclass 32, count 0 2006.211.08:26:42.31#ibcon#end of sib2, iclass 32, count 0 2006.211.08:26:42.31#ibcon#*after write, iclass 32, count 0 2006.211.08:26:42.31#ibcon#*before return 0, iclass 32, count 0 2006.211.08:26:42.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:26:42.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.211.08:26:42.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.08:26:42.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.08:26:42.31$4f8m12a/ifd4f 2006.211.08:26:42.31$ifd4f/lo= 2006.211.08:26:42.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:26:42.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:26:42.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:26:42.31$ifd4f/patch= 2006.211.08:26:42.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:26:42.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:26:42.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:26:42.31$4f8m12a/"form=m,16.000,1:2 2006.211.08:26:42.31$4f8m12a/"tpicd 2006.211.08:26:42.31$4f8m12a/echo=off 2006.211.08:26:42.31$4f8m12a/xlog=off 2006.211.08:26:42.31:!2006.211.08:29:00 2006.211.08:26:56.14#trakl#Source acquired 2006.211.08:26:58.14#flagr#flagr/antenna,acquired 2006.211.08:29:00.00:preob 2006.211.08:29:00.13/onsource/TRACKING 2006.211.08:29:00.13:!2006.211.08:29:10 2006.211.08:29:10.00:data_valid=on 2006.211.08:29:10.00:midob 2006.211.08:29:10.13/onsource/TRACKING 2006.211.08:29:10.13/wx/24.07,1010.3,82 2006.211.08:29:10.25/cable/+6.4411E-03 2006.211.08:29:11.34/va/01,08,usb,yes,28,30 2006.211.08:29:11.34/va/02,07,usb,yes,28,30 2006.211.08:29:11.34/va/03,06,usb,yes,30,30 2006.211.08:29:11.34/va/04,07,usb,yes,29,31 2006.211.08:29:11.34/va/05,07,usb,yes,31,33 2006.211.08:29:11.34/va/06,06,usb,yes,30,30 2006.211.08:29:11.34/va/07,06,usb,yes,31,31 2006.211.08:29:11.34/va/08,07,usb,yes,29,29 2006.211.08:29:11.57/valo/01,532.99,yes,locked 2006.211.08:29:11.57/valo/02,572.99,yes,locked 2006.211.08:29:11.57/valo/03,672.99,yes,locked 2006.211.08:29:11.57/valo/04,832.99,yes,locked 2006.211.08:29:11.57/valo/05,652.99,yes,locked 2006.211.08:29:11.57/valo/06,772.99,yes,locked 2006.211.08:29:11.57/valo/07,832.99,yes,locked 2006.211.08:29:11.57/valo/08,852.99,yes,locked 2006.211.08:29:12.66/vb/01,04,usb,yes,28,27 2006.211.08:29:12.66/vb/02,04,usb,yes,30,31 2006.211.08:29:12.66/vb/03,03,usb,yes,33,37 2006.211.08:29:12.66/vb/04,03,usb,yes,34,34 2006.211.08:29:12.66/vb/05,03,usb,yes,32,36 2006.211.08:29:12.66/vb/06,03,usb,yes,33,36 2006.211.08:29:12.66/vb/07,04,usb,yes,29,28 2006.211.08:29:12.66/vb/08,03,usb,yes,33,36 2006.211.08:29:12.89/vblo/01,632.99,yes,locked 2006.211.08:29:12.89/vblo/02,640.99,yes,locked 2006.211.08:29:12.89/vblo/03,656.99,yes,locked 2006.211.08:29:12.89/vblo/04,712.99,yes,locked 2006.211.08:29:12.89/vblo/05,744.99,yes,locked 2006.211.08:29:12.89/vblo/06,752.99,yes,locked 2006.211.08:29:12.89/vblo/07,734.99,yes,locked 2006.211.08:29:12.89/vblo/08,744.99,yes,locked 2006.211.08:29:13.04/vabw/8 2006.211.08:29:13.19/vbbw/8 2006.211.08:29:13.33/xfe/off,on,12.0 2006.211.08:29:13.71/ifatt/23,28,28,28 2006.211.08:29:14.08/fmout-gps/S +4.43E-07 2006.211.08:29:14.12:!2006.211.08:30:10 2006.211.08:30:10.01:data_valid=off 2006.211.08:30:10.01:postob 2006.211.08:30:10.14/cable/+6.4392E-03 2006.211.08:30:10.14/wx/24.04,1010.3,82 2006.211.08:30:11.08/fmout-gps/S +4.44E-07 2006.211.08:30:11.08:checkk5last 2006.211.08:30:11.08&checkk5last/chk_obsdata=1 2006.211.08:30:11.08&checkk5last/chk_obsdata=2 2006.211.08:30:11.08&checkk5last/chk_obsdata=3 2006.211.08:30:11.08&checkk5last/chk_obsdata=4 2006.211.08:30:11.08&checkk5last/k5log=1 2006.211.08:30:11.08&checkk5last/k5log=2 2006.211.08:30:11.08&checkk5last/k5log=3 2006.211.08:30:11.08&checkk5last/k5log=4 2006.211.08:30:11.08&checkk5last/obsinfo 2006.211.08:30:11.42/chk_obsdata//k5ts1/T2110829??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:30:11.75/chk_obsdata//k5ts2/T2110829??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:30:12.09/chk_obsdata//k5ts3/T2110829??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:30:12.44/chk_obsdata//k5ts4/T2110829??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.211.08:30:13.09/k5log//k5ts1_log_newline 2006.211.08:30:13.75/k5log//k5ts2_log_newline 2006.211.08:30:14.41/k5log//k5ts3_log_newline 2006.211.08:30:15.06/k5log//k5ts4_log_newline 2006.211.08:30:15.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:30:15.09:"sched_end 2006.211.08:30:15.09:checkk5hdd 2006.211.08:30:15.09&checkk5hdd/chk_hdd=1 2006.211.08:30:15.09&checkk5hdd/chk_hdd=2 2006.211.08:30:15.09&checkk5hdd/chk_hdd=3 2006.211.08:30:15.09&checkk5hdd/chk_hdd=4 2006.211.08:30:17.89/chk_hdd//k5ts1/GSI00275:T211073000a.dat~T211082910a.dat[13177389056Byte] 2006.211.08:30:20.66/chk_hdd//k5ts2/GSI00163:T211073000b.dat~T211082910b.dat[13177389056Byte] 2006.211.08:30:23.42/chk_hdd//k5ts3/GSI00278:T211073000c.dat~T211082910c.dat[13177389056Byte] 2006.211.08:30:26.18/chk_hdd//k5ts4/GSI00220:T211073000d.dat~T211082910d.dat[13177389056Byte] 2006.211.08:30:26.18:sy=cp /usr2/log/k06211ts.log /usr2/log_backup/ 2006.211.08:30:26.23:log=u06211ts