2006.210.07:26:39.54;Log Opened: Mark IV Field System Version 9.7.7 2006.210.07:26:39.54;location,TSUKUB32,-140.09,36.10,61.0 2006.210.07:26:39.54;horizon1,0.,5.,360. 2006.210.07:26:39.54;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.210.07:26:39.54;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.210.07:26:39.54;drivev11,330,270,no 2006.210.07:26:39.54;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.210.07:26:39.54;drivev13,15.000,268,10.000,10.000,10.000 2006.210.07:26:39.54;drivev21,330,270,no 2006.210.07:26:39.54;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.210.07:26:39.54;drivev23,15.000,268,10.000,10.000,10.000 2006.210.07:26:39.54;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.210.07:26:39.54;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.210.07:26:39.54;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.210.07:26:39.54;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.210.07:26:39.54;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.210.07:26:39.54;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.210.07:26:39.54;time,-0.364,101.533,rate 2006.210.07:26:39.54;flagr,200 2006.210.07:26:39.54:" K06210 2006 TSUKUB32 T Ts 2006.210.07:26:39.54:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.210.07:26:39.54:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.210.07:26:39.54:" 108 TSUKUB32 14 17400 2006.210.07:26:39.54:" drudg version 050216 compiled under FS 9.7.07 2006.210.07:26:39.54:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.210.07:26:39.54:exper_initi 2006.210.07:26:39.54&exper_initi/proc_library 2006.210.07:26:39.54&exper_initi/sched_initi 2006.210.07:26:39.54:!2006.210.06:29:50 2006.210.07:26:39.54:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.210.07:26:39.58:!2006.210.07:19:50 2006.210.07:26:39.66:unstow 2006.210.07:26:39.66&unstow/antenna=e 2006.210.07:26:39.66&unstow/!+10s 2006.210.07:26:39.67&unstow/antenna=m2 2006.210.07:26:41.01&proc_library/" k06210 tsukub32 ts 2006.210.07:26:41.01&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.210.07:26:41.01&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.210.07:26:41.02&sched_initi/startcheck 2006.210.07:26:41.02&startcheck/sy=check_fsrun.pl & 2006.210.07:26:41.03&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.210.07:26:52.01:scan_name=210-0730,k06210,60 2006.210.07:26:52.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.210.07:26:53.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.210.07:26:53.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.210.07:26:53.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.210.07:26:53.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.210.07:26:53.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.210.07:26:53.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.210.07:26:54.14#flagr#flagr/antenna,new-source 2006.210.07:26:54.14:ready_k5 2006.210.07:26:54.14&ready_k5/obsinfo=st 2006.210.07:26:54.15&ready_k5/autoobs=1 2006.210.07:26:54.15&ready_k5/autoobs=2 2006.210.07:26:54.15&ready_k5/autoobs=3 2006.210.07:26:54.16&ready_k5/autoobs=4 2006.210.07:26:54.16&ready_k5/obsinfo 2006.210.07:26:54.17/obsinfo=st/error_log.tmp was removed. 2006.210.07:26:58.03/autoobs//k5ts1/ autoobs started! 2006.210.07:27:01.48/autoobs//k5ts2/ autoobs started! 2006.210.07:27:04.91/autoobs//k5ts3/ autoobs started! 2006.210.07:27:08.34/autoobs//k5ts4/ autoobs started! 2006.210.07:27:08.37/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:27:08.37:4f8m12a=1 2006.210.07:27:08.37&4f8m12a/xlog=on 2006.210.07:27:08.37&4f8m12a/echo=on 2006.210.07:27:08.37&4f8m12a/pcalon 2006.210.07:27:08.37&4f8m12a/"tpicd=stop 2006.210.07:27:08.37&4f8m12a/vc4f8 2006.210.07:27:08.37&4f8m12a/ifd4f 2006.210.07:27:08.37&4f8m12a/"form=m,16.000,1:2 2006.210.07:27:08.37&4f8m12a/"tpicd 2006.210.07:27:08.37&4f8m12a/echo=off 2006.210.07:27:08.37&4f8m12a/xlog=off 2006.210.07:27:08.37$4f8m12a/echo=on 2006.210.07:27:08.37$4f8m12a/pcalon 2006.210.07:27:08.37&pcalon/"no phase cal control is implemented here 2006.210.07:27:08.37$pcalon/"no phase cal control is implemented here 2006.210.07:27:08.37$4f8m12a/"tpicd=stop 2006.210.07:27:08.37$4f8m12a/vc4f8 2006.210.07:27:08.37&vc4f8/valo=1,532.99 2006.210.07:27:08.37&vc4f8/va=1,8 2006.210.07:27:08.37&vc4f8/valo=2,572.99 2006.210.07:27:08.37&vc4f8/va=2,7 2006.210.07:27:08.37&vc4f8/valo=3,672.99 2006.210.07:27:08.37&vc4f8/va=3,6 2006.210.07:27:08.37&vc4f8/valo=4,832.99 2006.210.07:27:08.37&vc4f8/va=4,7 2006.210.07:27:08.37&vc4f8/valo=5,652.99 2006.210.07:27:08.37&vc4f8/va=5,7 2006.210.07:27:08.37&vc4f8/valo=6,772.99 2006.210.07:27:08.37&vc4f8/va=6,6 2006.210.07:27:08.37&vc4f8/valo=7,832.99 2006.210.07:27:08.37&vc4f8/va=7,6 2006.210.07:27:08.37&vc4f8/valo=8,852.99 2006.210.07:27:08.37&vc4f8/va=8,7 2006.210.07:27:08.37&vc4f8/vblo=1,632.99 2006.210.07:27:08.37&vc4f8/vb=1,4 2006.210.07:27:08.37&vc4f8/vblo=2,640.99 2006.210.07:27:08.37&vc4f8/vb=2,4 2006.210.07:27:08.37&vc4f8/vblo=3,656.99 2006.210.07:27:08.37&vc4f8/vb=3,3 2006.210.07:27:08.37&vc4f8/vblo=4,712.99 2006.210.07:27:08.37&vc4f8/vb=4,3 2006.210.07:27:08.37&vc4f8/vblo=5,744.99 2006.210.07:27:08.37&vc4f8/vb=5,3 2006.210.07:27:08.37&vc4f8/vblo=6,752.99 2006.210.07:27:08.37&vc4f8/vb=6,3 2006.210.07:27:08.37&vc4f8/vabw=wide 2006.210.07:27:08.37&vc4f8/vbbw=wide 2006.210.07:27:08.37$vc4f8/valo=1,532.99 2006.210.07:27:08.37#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:27:08.37#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:27:08.37#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:08.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:08.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:08.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:08.37#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:27:08.37#ibcon#first serial, iclass 24, count 0 2006.210.07:27:08.37#ibcon#enter sib2, iclass 24, count 0 2006.210.07:27:08.37#ibcon#flushed, iclass 24, count 0 2006.210.07:27:08.37#ibcon#about to write, iclass 24, count 0 2006.210.07:27:08.37#ibcon#wrote, iclass 24, count 0 2006.210.07:27:08.37#ibcon#about to read 3, iclass 24, count 0 2006.210.07:27:08.39#ibcon#read 3, iclass 24, count 0 2006.210.07:27:08.39#ibcon#about to read 4, iclass 24, count 0 2006.210.07:27:08.39#ibcon#read 4, iclass 24, count 0 2006.210.07:27:08.39#ibcon#about to read 5, iclass 24, count 0 2006.210.07:27:08.39#ibcon#read 5, iclass 24, count 0 2006.210.07:27:08.39#ibcon#about to read 6, iclass 24, count 0 2006.210.07:27:08.39#ibcon#read 6, iclass 24, count 0 2006.210.07:27:08.39#ibcon#end of sib2, iclass 24, count 0 2006.210.07:27:08.39#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:27:08.39#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:27:08.39#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:27:08.39#ibcon#*before write, iclass 24, count 0 2006.210.07:27:08.39#ibcon#enter sib2, iclass 24, count 0 2006.210.07:27:08.39#ibcon#flushed, iclass 24, count 0 2006.210.07:27:08.39#ibcon#about to write, iclass 24, count 0 2006.210.07:27:08.39#ibcon#wrote, iclass 24, count 0 2006.210.07:27:08.39#ibcon#about to read 3, iclass 24, count 0 2006.210.07:27:08.45#ibcon#read 3, iclass 24, count 0 2006.210.07:27:08.45#ibcon#about to read 4, iclass 24, count 0 2006.210.07:27:08.45#ibcon#read 4, iclass 24, count 0 2006.210.07:27:08.45#ibcon#about to read 5, iclass 24, count 0 2006.210.07:27:08.45#ibcon#read 5, iclass 24, count 0 2006.210.07:27:08.45#ibcon#about to read 6, iclass 24, count 0 2006.210.07:27:08.45#ibcon#read 6, iclass 24, count 0 2006.210.07:27:08.45#ibcon#end of sib2, iclass 24, count 0 2006.210.07:27:08.45#ibcon#*after write, iclass 24, count 0 2006.210.07:27:08.45#ibcon#*before return 0, iclass 24, count 0 2006.210.07:27:08.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:08.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:08.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:27:08.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:27:08.45$vc4f8/va=1,8 2006.210.07:27:08.45#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:27:08.45#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:27:08.45#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:08.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:08.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:08.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:08.45#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:27:08.45#ibcon#first serial, iclass 26, count 2 2006.210.07:27:08.45#ibcon#enter sib2, iclass 26, count 2 2006.210.07:27:08.45#ibcon#flushed, iclass 26, count 2 2006.210.07:27:08.45#ibcon#about to write, iclass 26, count 2 2006.210.07:27:08.45#ibcon#wrote, iclass 26, count 2 2006.210.07:27:08.45#ibcon#about to read 3, iclass 26, count 2 2006.210.07:27:08.47#ibcon#read 3, iclass 26, count 2 2006.210.07:27:08.47#ibcon#about to read 4, iclass 26, count 2 2006.210.07:27:08.47#ibcon#read 4, iclass 26, count 2 2006.210.07:27:08.47#ibcon#about to read 5, iclass 26, count 2 2006.210.07:27:08.47#ibcon#read 5, iclass 26, count 2 2006.210.07:27:08.47#ibcon#about to read 6, iclass 26, count 2 2006.210.07:27:08.47#ibcon#read 6, iclass 26, count 2 2006.210.07:27:08.47#ibcon#end of sib2, iclass 26, count 2 2006.210.07:27:08.47#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:27:08.47#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:27:08.47#ibcon#[25=AT01-08\r\n] 2006.210.07:27:08.47#ibcon#*before write, iclass 26, count 2 2006.210.07:27:08.47#ibcon#enter sib2, iclass 26, count 2 2006.210.07:27:08.47#ibcon#flushed, iclass 26, count 2 2006.210.07:27:08.47#ibcon#about to write, iclass 26, count 2 2006.210.07:27:08.47#ibcon#wrote, iclass 26, count 2 2006.210.07:27:08.47#ibcon#about to read 3, iclass 26, count 2 2006.210.07:27:08.51#ibcon#read 3, iclass 26, count 2 2006.210.07:27:08.51#ibcon#about to read 4, iclass 26, count 2 2006.210.07:27:08.51#ibcon#read 4, iclass 26, count 2 2006.210.07:27:08.51#ibcon#about to read 5, iclass 26, count 2 2006.210.07:27:08.51#ibcon#read 5, iclass 26, count 2 2006.210.07:27:08.51#ibcon#about to read 6, iclass 26, count 2 2006.210.07:27:08.51#ibcon#read 6, iclass 26, count 2 2006.210.07:27:08.51#ibcon#end of sib2, iclass 26, count 2 2006.210.07:27:08.51#ibcon#*after write, iclass 26, count 2 2006.210.07:27:08.51#ibcon#*before return 0, iclass 26, count 2 2006.210.07:27:08.51#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:08.51#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:08.51#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:27:08.51#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:08.51#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:08.64#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:08.64#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:08.64#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:27:08.64#ibcon#first serial, iclass 26, count 0 2006.210.07:27:08.64#ibcon#enter sib2, iclass 26, count 0 2006.210.07:27:08.64#ibcon#flushed, iclass 26, count 0 2006.210.07:27:08.64#ibcon#about to write, iclass 26, count 0 2006.210.07:27:08.64#ibcon#wrote, iclass 26, count 0 2006.210.07:27:08.64#ibcon#about to read 3, iclass 26, count 0 2006.210.07:27:08.66#ibcon#read 3, iclass 26, count 0 2006.210.07:27:08.66#ibcon#about to read 4, iclass 26, count 0 2006.210.07:27:08.66#ibcon#read 4, iclass 26, count 0 2006.210.07:27:08.66#ibcon#about to read 5, iclass 26, count 0 2006.210.07:27:08.66#ibcon#read 5, iclass 26, count 0 2006.210.07:27:08.66#ibcon#about to read 6, iclass 26, count 0 2006.210.07:27:08.66#ibcon#read 6, iclass 26, count 0 2006.210.07:27:08.66#ibcon#end of sib2, iclass 26, count 0 2006.210.07:27:08.66#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:27:08.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:27:08.66#ibcon#[25=USB\r\n] 2006.210.07:27:08.66#ibcon#*before write, iclass 26, count 0 2006.210.07:27:08.66#ibcon#enter sib2, iclass 26, count 0 2006.210.07:27:08.66#ibcon#flushed, iclass 26, count 0 2006.210.07:27:08.66#ibcon#about to write, iclass 26, count 0 2006.210.07:27:08.66#ibcon#wrote, iclass 26, count 0 2006.210.07:27:08.66#ibcon#about to read 3, iclass 26, count 0 2006.210.07:27:08.69#ibcon#read 3, iclass 26, count 0 2006.210.07:27:08.69#ibcon#about to read 4, iclass 26, count 0 2006.210.07:27:08.69#ibcon#read 4, iclass 26, count 0 2006.210.07:27:08.69#ibcon#about to read 5, iclass 26, count 0 2006.210.07:27:08.69#ibcon#read 5, iclass 26, count 0 2006.210.07:27:08.69#ibcon#about to read 6, iclass 26, count 0 2006.210.07:27:08.69#ibcon#read 6, iclass 26, count 0 2006.210.07:27:08.69#ibcon#end of sib2, iclass 26, count 0 2006.210.07:27:08.69#ibcon#*after write, iclass 26, count 0 2006.210.07:27:08.69#ibcon#*before return 0, iclass 26, count 0 2006.210.07:27:08.69#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:08.69#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:08.69#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:27:08.69#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:27:08.69$vc4f8/valo=2,572.99 2006.210.07:27:08.69#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:27:08.69#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:27:08.69#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:08.69#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:08.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:08.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:08.69#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:27:08.69#ibcon#first serial, iclass 28, count 0 2006.210.07:27:08.69#ibcon#enter sib2, iclass 28, count 0 2006.210.07:27:08.69#ibcon#flushed, iclass 28, count 0 2006.210.07:27:08.69#ibcon#about to write, iclass 28, count 0 2006.210.07:27:08.69#ibcon#wrote, iclass 28, count 0 2006.210.07:27:08.69#ibcon#about to read 3, iclass 28, count 0 2006.210.07:27:08.71#ibcon#read 3, iclass 28, count 0 2006.210.07:27:08.71#ibcon#about to read 4, iclass 28, count 0 2006.210.07:27:08.71#ibcon#read 4, iclass 28, count 0 2006.210.07:27:08.71#ibcon#about to read 5, iclass 28, count 0 2006.210.07:27:08.71#ibcon#read 5, iclass 28, count 0 2006.210.07:27:08.71#ibcon#about to read 6, iclass 28, count 0 2006.210.07:27:08.71#ibcon#read 6, iclass 28, count 0 2006.210.07:27:08.71#ibcon#end of sib2, iclass 28, count 0 2006.210.07:27:08.71#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:27:08.71#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:27:08.71#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:27:08.71#ibcon#*before write, iclass 28, count 0 2006.210.07:27:08.71#ibcon#enter sib2, iclass 28, count 0 2006.210.07:27:08.71#ibcon#flushed, iclass 28, count 0 2006.210.07:27:08.71#ibcon#about to write, iclass 28, count 0 2006.210.07:27:08.71#ibcon#wrote, iclass 28, count 0 2006.210.07:27:08.71#ibcon#about to read 3, iclass 28, count 0 2006.210.07:27:08.75#ibcon#read 3, iclass 28, count 0 2006.210.07:27:08.75#ibcon#about to read 4, iclass 28, count 0 2006.210.07:27:08.75#ibcon#read 4, iclass 28, count 0 2006.210.07:27:08.75#ibcon#about to read 5, iclass 28, count 0 2006.210.07:27:08.75#ibcon#read 5, iclass 28, count 0 2006.210.07:27:08.75#ibcon#about to read 6, iclass 28, count 0 2006.210.07:27:08.75#ibcon#read 6, iclass 28, count 0 2006.210.07:27:08.75#ibcon#end of sib2, iclass 28, count 0 2006.210.07:27:08.75#ibcon#*after write, iclass 28, count 0 2006.210.07:27:08.75#ibcon#*before return 0, iclass 28, count 0 2006.210.07:27:08.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:08.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:08.75#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:27:08.75#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:27:08.80$vc4f8/va=2,7 2006.210.07:27:08.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:27:08.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:27:08.80#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:08.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:08.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:08.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:08.80#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:27:08.80#ibcon#first serial, iclass 30, count 2 2006.210.07:27:08.80#ibcon#enter sib2, iclass 30, count 2 2006.210.07:27:08.80#ibcon#flushed, iclass 30, count 2 2006.210.07:27:08.80#ibcon#about to write, iclass 30, count 2 2006.210.07:27:08.80#ibcon#wrote, iclass 30, count 2 2006.210.07:27:08.80#ibcon#about to read 3, iclass 30, count 2 2006.210.07:27:08.82#ibcon#read 3, iclass 30, count 2 2006.210.07:27:08.82#ibcon#about to read 4, iclass 30, count 2 2006.210.07:27:08.82#ibcon#read 4, iclass 30, count 2 2006.210.07:27:08.82#ibcon#about to read 5, iclass 30, count 2 2006.210.07:27:08.82#ibcon#read 5, iclass 30, count 2 2006.210.07:27:08.82#ibcon#about to read 6, iclass 30, count 2 2006.210.07:27:08.82#ibcon#read 6, iclass 30, count 2 2006.210.07:27:08.82#ibcon#end of sib2, iclass 30, count 2 2006.210.07:27:08.82#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:27:08.82#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:27:08.82#ibcon#[25=AT02-07\r\n] 2006.210.07:27:08.82#ibcon#*before write, iclass 30, count 2 2006.210.07:27:08.82#ibcon#enter sib2, iclass 30, count 2 2006.210.07:27:08.82#ibcon#flushed, iclass 30, count 2 2006.210.07:27:08.82#ibcon#about to write, iclass 30, count 2 2006.210.07:27:08.82#ibcon#wrote, iclass 30, count 2 2006.210.07:27:08.82#ibcon#about to read 3, iclass 30, count 2 2006.210.07:27:08.85#ibcon#read 3, iclass 30, count 2 2006.210.07:27:08.85#ibcon#about to read 4, iclass 30, count 2 2006.210.07:27:08.85#ibcon#read 4, iclass 30, count 2 2006.210.07:27:08.85#ibcon#about to read 5, iclass 30, count 2 2006.210.07:27:08.85#ibcon#read 5, iclass 30, count 2 2006.210.07:27:08.85#ibcon#about to read 6, iclass 30, count 2 2006.210.07:27:08.85#ibcon#read 6, iclass 30, count 2 2006.210.07:27:08.85#ibcon#end of sib2, iclass 30, count 2 2006.210.07:27:08.85#ibcon#*after write, iclass 30, count 2 2006.210.07:27:08.85#ibcon#*before return 0, iclass 30, count 2 2006.210.07:27:08.85#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:08.85#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:08.85#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:27:08.85#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:08.85#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:08.97#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:08.97#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:08.97#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:27:08.97#ibcon#first serial, iclass 30, count 0 2006.210.07:27:08.97#ibcon#enter sib2, iclass 30, count 0 2006.210.07:27:08.97#ibcon#flushed, iclass 30, count 0 2006.210.07:27:08.97#ibcon#about to write, iclass 30, count 0 2006.210.07:27:08.97#ibcon#wrote, iclass 30, count 0 2006.210.07:27:08.97#ibcon#about to read 3, iclass 30, count 0 2006.210.07:27:08.99#ibcon#read 3, iclass 30, count 0 2006.210.07:27:08.99#ibcon#about to read 4, iclass 30, count 0 2006.210.07:27:08.99#ibcon#read 4, iclass 30, count 0 2006.210.07:27:08.99#ibcon#about to read 5, iclass 30, count 0 2006.210.07:27:08.99#ibcon#read 5, iclass 30, count 0 2006.210.07:27:08.99#ibcon#about to read 6, iclass 30, count 0 2006.210.07:27:08.99#ibcon#read 6, iclass 30, count 0 2006.210.07:27:08.99#ibcon#end of sib2, iclass 30, count 0 2006.210.07:27:08.99#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:27:08.99#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:27:08.99#ibcon#[25=USB\r\n] 2006.210.07:27:08.99#ibcon#*before write, iclass 30, count 0 2006.210.07:27:08.99#ibcon#enter sib2, iclass 30, count 0 2006.210.07:27:08.99#ibcon#flushed, iclass 30, count 0 2006.210.07:27:08.99#ibcon#about to write, iclass 30, count 0 2006.210.07:27:08.99#ibcon#wrote, iclass 30, count 0 2006.210.07:27:08.99#ibcon#about to read 3, iclass 30, count 0 2006.210.07:27:09.02#ibcon#read 3, iclass 30, count 0 2006.210.07:27:09.02#ibcon#about to read 4, iclass 30, count 0 2006.210.07:27:09.02#ibcon#read 4, iclass 30, count 0 2006.210.07:27:09.02#ibcon#about to read 5, iclass 30, count 0 2006.210.07:27:09.02#ibcon#read 5, iclass 30, count 0 2006.210.07:27:09.02#ibcon#about to read 6, iclass 30, count 0 2006.210.07:27:09.02#ibcon#read 6, iclass 30, count 0 2006.210.07:27:09.02#ibcon#end of sib2, iclass 30, count 0 2006.210.07:27:09.02#ibcon#*after write, iclass 30, count 0 2006.210.07:27:09.02#ibcon#*before return 0, iclass 30, count 0 2006.210.07:27:09.02#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:09.02#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:09.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:27:09.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:27:09.02$vc4f8/valo=3,672.99 2006.210.07:27:09.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:27:09.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:27:09.02#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:09.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:09.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:09.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:09.02#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:27:09.02#ibcon#first serial, iclass 32, count 0 2006.210.07:27:09.02#ibcon#enter sib2, iclass 32, count 0 2006.210.07:27:09.02#ibcon#flushed, iclass 32, count 0 2006.210.07:27:09.02#ibcon#about to write, iclass 32, count 0 2006.210.07:27:09.02#ibcon#wrote, iclass 32, count 0 2006.210.07:27:09.02#ibcon#about to read 3, iclass 32, count 0 2006.210.07:27:09.04#ibcon#read 3, iclass 32, count 0 2006.210.07:27:09.04#ibcon#about to read 4, iclass 32, count 0 2006.210.07:27:09.04#ibcon#read 4, iclass 32, count 0 2006.210.07:27:09.04#ibcon#about to read 5, iclass 32, count 0 2006.210.07:27:09.04#ibcon#read 5, iclass 32, count 0 2006.210.07:27:09.04#ibcon#about to read 6, iclass 32, count 0 2006.210.07:27:09.04#ibcon#read 6, iclass 32, count 0 2006.210.07:27:09.04#ibcon#end of sib2, iclass 32, count 0 2006.210.07:27:09.04#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:27:09.04#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:27:09.04#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:27:09.04#ibcon#*before write, iclass 32, count 0 2006.210.07:27:09.04#ibcon#enter sib2, iclass 32, count 0 2006.210.07:27:09.04#ibcon#flushed, iclass 32, count 0 2006.210.07:27:09.04#ibcon#about to write, iclass 32, count 0 2006.210.07:27:09.04#ibcon#wrote, iclass 32, count 0 2006.210.07:27:09.04#ibcon#about to read 3, iclass 32, count 0 2006.210.07:27:09.08#ibcon#read 3, iclass 32, count 0 2006.210.07:27:09.08#ibcon#about to read 4, iclass 32, count 0 2006.210.07:27:09.08#ibcon#read 4, iclass 32, count 0 2006.210.07:27:09.08#ibcon#about to read 5, iclass 32, count 0 2006.210.07:27:09.08#ibcon#read 5, iclass 32, count 0 2006.210.07:27:09.08#ibcon#about to read 6, iclass 32, count 0 2006.210.07:27:09.08#ibcon#read 6, iclass 32, count 0 2006.210.07:27:09.08#ibcon#end of sib2, iclass 32, count 0 2006.210.07:27:09.08#ibcon#*after write, iclass 32, count 0 2006.210.07:27:09.08#ibcon#*before return 0, iclass 32, count 0 2006.210.07:27:09.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:09.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:09.08#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:27:09.08#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:27:09.08$vc4f8/va=3,6 2006.210.07:27:09.08#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:27:09.08#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:27:09.08#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:09.08#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:09.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:09.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:09.14#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:27:09.14#ibcon#first serial, iclass 34, count 2 2006.210.07:27:09.14#ibcon#enter sib2, iclass 34, count 2 2006.210.07:27:09.14#ibcon#flushed, iclass 34, count 2 2006.210.07:27:09.14#ibcon#about to write, iclass 34, count 2 2006.210.07:27:09.14#ibcon#wrote, iclass 34, count 2 2006.210.07:27:09.14#ibcon#about to read 3, iclass 34, count 2 2006.210.07:27:09.16#ibcon#read 3, iclass 34, count 2 2006.210.07:27:09.16#ibcon#about to read 4, iclass 34, count 2 2006.210.07:27:09.16#ibcon#read 4, iclass 34, count 2 2006.210.07:27:09.16#ibcon#about to read 5, iclass 34, count 2 2006.210.07:27:09.16#ibcon#read 5, iclass 34, count 2 2006.210.07:27:09.16#ibcon#about to read 6, iclass 34, count 2 2006.210.07:27:09.16#ibcon#read 6, iclass 34, count 2 2006.210.07:27:09.16#ibcon#end of sib2, iclass 34, count 2 2006.210.07:27:09.16#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:27:09.16#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:27:09.16#ibcon#[25=AT03-06\r\n] 2006.210.07:27:09.16#ibcon#*before write, iclass 34, count 2 2006.210.07:27:09.16#ibcon#enter sib2, iclass 34, count 2 2006.210.07:27:09.16#ibcon#flushed, iclass 34, count 2 2006.210.07:27:09.16#ibcon#about to write, iclass 34, count 2 2006.210.07:27:09.16#ibcon#wrote, iclass 34, count 2 2006.210.07:27:09.16#ibcon#about to read 3, iclass 34, count 2 2006.210.07:27:09.19#ibcon#read 3, iclass 34, count 2 2006.210.07:27:09.19#ibcon#about to read 4, iclass 34, count 2 2006.210.07:27:09.19#ibcon#read 4, iclass 34, count 2 2006.210.07:27:09.19#ibcon#about to read 5, iclass 34, count 2 2006.210.07:27:09.19#ibcon#read 5, iclass 34, count 2 2006.210.07:27:09.19#ibcon#about to read 6, iclass 34, count 2 2006.210.07:27:09.19#ibcon#read 6, iclass 34, count 2 2006.210.07:27:09.19#ibcon#end of sib2, iclass 34, count 2 2006.210.07:27:09.19#ibcon#*after write, iclass 34, count 2 2006.210.07:27:09.19#ibcon#*before return 0, iclass 34, count 2 2006.210.07:27:09.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:09.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:09.19#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:27:09.19#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:09.19#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:09.31#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:09.31#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:09.31#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:27:09.31#ibcon#first serial, iclass 34, count 0 2006.210.07:27:09.31#ibcon#enter sib2, iclass 34, count 0 2006.210.07:27:09.31#ibcon#flushed, iclass 34, count 0 2006.210.07:27:09.31#ibcon#about to write, iclass 34, count 0 2006.210.07:27:09.31#ibcon#wrote, iclass 34, count 0 2006.210.07:27:09.31#ibcon#about to read 3, iclass 34, count 0 2006.210.07:27:09.33#ibcon#read 3, iclass 34, count 0 2006.210.07:27:09.33#ibcon#about to read 4, iclass 34, count 0 2006.210.07:27:09.33#ibcon#read 4, iclass 34, count 0 2006.210.07:27:09.33#ibcon#about to read 5, iclass 34, count 0 2006.210.07:27:09.33#ibcon#read 5, iclass 34, count 0 2006.210.07:27:09.33#ibcon#about to read 6, iclass 34, count 0 2006.210.07:27:09.33#ibcon#read 6, iclass 34, count 0 2006.210.07:27:09.33#ibcon#end of sib2, iclass 34, count 0 2006.210.07:27:09.33#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:27:09.33#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:27:09.33#ibcon#[25=USB\r\n] 2006.210.07:27:09.33#ibcon#*before write, iclass 34, count 0 2006.210.07:27:09.33#ibcon#enter sib2, iclass 34, count 0 2006.210.07:27:09.33#ibcon#flushed, iclass 34, count 0 2006.210.07:27:09.33#ibcon#about to write, iclass 34, count 0 2006.210.07:27:09.33#ibcon#wrote, iclass 34, count 0 2006.210.07:27:09.33#ibcon#about to read 3, iclass 34, count 0 2006.210.07:27:09.36#ibcon#read 3, iclass 34, count 0 2006.210.07:27:09.36#ibcon#about to read 4, iclass 34, count 0 2006.210.07:27:09.36#ibcon#read 4, iclass 34, count 0 2006.210.07:27:09.36#ibcon#about to read 5, iclass 34, count 0 2006.210.07:27:09.36#ibcon#read 5, iclass 34, count 0 2006.210.07:27:09.36#ibcon#about to read 6, iclass 34, count 0 2006.210.07:27:09.36#ibcon#read 6, iclass 34, count 0 2006.210.07:27:09.36#ibcon#end of sib2, iclass 34, count 0 2006.210.07:27:09.36#ibcon#*after write, iclass 34, count 0 2006.210.07:27:09.36#ibcon#*before return 0, iclass 34, count 0 2006.210.07:27:09.36#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:09.36#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:09.36#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:27:09.36#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:27:09.36$vc4f8/valo=4,832.99 2006.210.07:27:09.36#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:27:09.36#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:27:09.36#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:09.36#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:09.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:09.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:09.36#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:27:09.36#ibcon#first serial, iclass 36, count 0 2006.210.07:27:09.36#ibcon#enter sib2, iclass 36, count 0 2006.210.07:27:09.36#ibcon#flushed, iclass 36, count 0 2006.210.07:27:09.36#ibcon#about to write, iclass 36, count 0 2006.210.07:27:09.36#ibcon#wrote, iclass 36, count 0 2006.210.07:27:09.36#ibcon#about to read 3, iclass 36, count 0 2006.210.07:27:09.38#ibcon#read 3, iclass 36, count 0 2006.210.07:27:09.38#ibcon#about to read 4, iclass 36, count 0 2006.210.07:27:09.38#ibcon#read 4, iclass 36, count 0 2006.210.07:27:09.38#ibcon#about to read 5, iclass 36, count 0 2006.210.07:27:09.38#ibcon#read 5, iclass 36, count 0 2006.210.07:27:09.38#ibcon#about to read 6, iclass 36, count 0 2006.210.07:27:09.38#ibcon#read 6, iclass 36, count 0 2006.210.07:27:09.38#ibcon#end of sib2, iclass 36, count 0 2006.210.07:27:09.38#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:27:09.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:27:09.38#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:27:09.38#ibcon#*before write, iclass 36, count 0 2006.210.07:27:09.38#ibcon#enter sib2, iclass 36, count 0 2006.210.07:27:09.38#ibcon#flushed, iclass 36, count 0 2006.210.07:27:09.38#ibcon#about to write, iclass 36, count 0 2006.210.07:27:09.38#ibcon#wrote, iclass 36, count 0 2006.210.07:27:09.38#ibcon#about to read 3, iclass 36, count 0 2006.210.07:27:09.42#ibcon#read 3, iclass 36, count 0 2006.210.07:27:09.42#ibcon#about to read 4, iclass 36, count 0 2006.210.07:27:09.42#ibcon#read 4, iclass 36, count 0 2006.210.07:27:09.42#ibcon#about to read 5, iclass 36, count 0 2006.210.07:27:09.42#ibcon#read 5, iclass 36, count 0 2006.210.07:27:09.42#ibcon#about to read 6, iclass 36, count 0 2006.210.07:27:09.42#ibcon#read 6, iclass 36, count 0 2006.210.07:27:09.42#ibcon#end of sib2, iclass 36, count 0 2006.210.07:27:09.42#ibcon#*after write, iclass 36, count 0 2006.210.07:27:09.42#ibcon#*before return 0, iclass 36, count 0 2006.210.07:27:09.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:09.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:09.42#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:27:09.42#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:27:09.42$vc4f8/va=4,7 2006.210.07:27:09.42#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:27:09.42#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:27:09.42#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:09.42#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:09.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:09.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:09.48#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:27:09.48#ibcon#first serial, iclass 38, count 2 2006.210.07:27:09.48#ibcon#enter sib2, iclass 38, count 2 2006.210.07:27:09.48#ibcon#flushed, iclass 38, count 2 2006.210.07:27:09.48#ibcon#about to write, iclass 38, count 2 2006.210.07:27:09.48#ibcon#wrote, iclass 38, count 2 2006.210.07:27:09.48#ibcon#about to read 3, iclass 38, count 2 2006.210.07:27:09.50#ibcon#read 3, iclass 38, count 2 2006.210.07:27:09.50#ibcon#about to read 4, iclass 38, count 2 2006.210.07:27:09.50#ibcon#read 4, iclass 38, count 2 2006.210.07:27:09.50#ibcon#about to read 5, iclass 38, count 2 2006.210.07:27:09.50#ibcon#read 5, iclass 38, count 2 2006.210.07:27:09.50#ibcon#about to read 6, iclass 38, count 2 2006.210.07:27:09.50#ibcon#read 6, iclass 38, count 2 2006.210.07:27:09.50#ibcon#end of sib2, iclass 38, count 2 2006.210.07:27:09.50#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:27:09.50#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:27:09.50#ibcon#[25=AT04-07\r\n] 2006.210.07:27:09.50#ibcon#*before write, iclass 38, count 2 2006.210.07:27:09.50#ibcon#enter sib2, iclass 38, count 2 2006.210.07:27:09.50#ibcon#flushed, iclass 38, count 2 2006.210.07:27:09.50#ibcon#about to write, iclass 38, count 2 2006.210.07:27:09.50#ibcon#wrote, iclass 38, count 2 2006.210.07:27:09.50#ibcon#about to read 3, iclass 38, count 2 2006.210.07:27:09.53#ibcon#read 3, iclass 38, count 2 2006.210.07:27:09.53#ibcon#about to read 4, iclass 38, count 2 2006.210.07:27:09.53#ibcon#read 4, iclass 38, count 2 2006.210.07:27:09.53#ibcon#about to read 5, iclass 38, count 2 2006.210.07:27:09.53#ibcon#read 5, iclass 38, count 2 2006.210.07:27:09.53#ibcon#about to read 6, iclass 38, count 2 2006.210.07:27:09.53#ibcon#read 6, iclass 38, count 2 2006.210.07:27:09.53#ibcon#end of sib2, iclass 38, count 2 2006.210.07:27:09.53#ibcon#*after write, iclass 38, count 2 2006.210.07:27:09.53#ibcon#*before return 0, iclass 38, count 2 2006.210.07:27:09.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:09.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:09.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:27:09.53#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:09.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:09.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:09.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:09.65#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:27:09.65#ibcon#first serial, iclass 38, count 0 2006.210.07:27:09.65#ibcon#enter sib2, iclass 38, count 0 2006.210.07:27:09.65#ibcon#flushed, iclass 38, count 0 2006.210.07:27:09.65#ibcon#about to write, iclass 38, count 0 2006.210.07:27:09.65#ibcon#wrote, iclass 38, count 0 2006.210.07:27:09.65#ibcon#about to read 3, iclass 38, count 0 2006.210.07:27:09.67#ibcon#read 3, iclass 38, count 0 2006.210.07:27:09.67#ibcon#about to read 4, iclass 38, count 0 2006.210.07:27:09.67#ibcon#read 4, iclass 38, count 0 2006.210.07:27:09.67#ibcon#about to read 5, iclass 38, count 0 2006.210.07:27:09.67#ibcon#read 5, iclass 38, count 0 2006.210.07:27:09.67#ibcon#about to read 6, iclass 38, count 0 2006.210.07:27:09.67#ibcon#read 6, iclass 38, count 0 2006.210.07:27:09.67#ibcon#end of sib2, iclass 38, count 0 2006.210.07:27:09.67#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:27:09.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:27:09.67#ibcon#[25=USB\r\n] 2006.210.07:27:09.67#ibcon#*before write, iclass 38, count 0 2006.210.07:27:09.67#ibcon#enter sib2, iclass 38, count 0 2006.210.07:27:09.67#ibcon#flushed, iclass 38, count 0 2006.210.07:27:09.67#ibcon#about to write, iclass 38, count 0 2006.210.07:27:09.67#ibcon#wrote, iclass 38, count 0 2006.210.07:27:09.67#ibcon#about to read 3, iclass 38, count 0 2006.210.07:27:09.70#ibcon#read 3, iclass 38, count 0 2006.210.07:27:09.70#ibcon#about to read 4, iclass 38, count 0 2006.210.07:27:09.70#ibcon#read 4, iclass 38, count 0 2006.210.07:27:09.70#ibcon#about to read 5, iclass 38, count 0 2006.210.07:27:09.70#ibcon#read 5, iclass 38, count 0 2006.210.07:27:09.70#ibcon#about to read 6, iclass 38, count 0 2006.210.07:27:09.70#ibcon#read 6, iclass 38, count 0 2006.210.07:27:09.70#ibcon#end of sib2, iclass 38, count 0 2006.210.07:27:09.70#ibcon#*after write, iclass 38, count 0 2006.210.07:27:09.70#ibcon#*before return 0, iclass 38, count 0 2006.210.07:27:09.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:09.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:09.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:27:09.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:27:09.70$vc4f8/valo=5,652.99 2006.210.07:27:09.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:27:09.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:27:09.70#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:09.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:09.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:09.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:09.70#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:27:09.70#ibcon#first serial, iclass 40, count 0 2006.210.07:27:09.70#ibcon#enter sib2, iclass 40, count 0 2006.210.07:27:09.70#ibcon#flushed, iclass 40, count 0 2006.210.07:27:09.70#ibcon#about to write, iclass 40, count 0 2006.210.07:27:09.70#ibcon#wrote, iclass 40, count 0 2006.210.07:27:09.70#ibcon#about to read 3, iclass 40, count 0 2006.210.07:27:09.72#ibcon#read 3, iclass 40, count 0 2006.210.07:27:09.72#ibcon#about to read 4, iclass 40, count 0 2006.210.07:27:09.72#ibcon#read 4, iclass 40, count 0 2006.210.07:27:09.72#ibcon#about to read 5, iclass 40, count 0 2006.210.07:27:09.72#ibcon#read 5, iclass 40, count 0 2006.210.07:27:09.72#ibcon#about to read 6, iclass 40, count 0 2006.210.07:27:09.72#ibcon#read 6, iclass 40, count 0 2006.210.07:27:09.72#ibcon#end of sib2, iclass 40, count 0 2006.210.07:27:09.72#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:27:09.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:27:09.72#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:27:09.72#ibcon#*before write, iclass 40, count 0 2006.210.07:27:09.72#ibcon#enter sib2, iclass 40, count 0 2006.210.07:27:09.72#ibcon#flushed, iclass 40, count 0 2006.210.07:27:09.72#ibcon#about to write, iclass 40, count 0 2006.210.07:27:09.72#ibcon#wrote, iclass 40, count 0 2006.210.07:27:09.72#ibcon#about to read 3, iclass 40, count 0 2006.210.07:27:09.76#ibcon#read 3, iclass 40, count 0 2006.210.07:27:09.76#ibcon#about to read 4, iclass 40, count 0 2006.210.07:27:09.76#ibcon#read 4, iclass 40, count 0 2006.210.07:27:09.76#ibcon#about to read 5, iclass 40, count 0 2006.210.07:27:09.76#ibcon#read 5, iclass 40, count 0 2006.210.07:27:09.76#ibcon#about to read 6, iclass 40, count 0 2006.210.07:27:09.76#ibcon#read 6, iclass 40, count 0 2006.210.07:27:09.76#ibcon#end of sib2, iclass 40, count 0 2006.210.07:27:09.76#ibcon#*after write, iclass 40, count 0 2006.210.07:27:09.76#ibcon#*before return 0, iclass 40, count 0 2006.210.07:27:09.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:09.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:09.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:27:09.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:27:09.76$vc4f8/va=5,7 2006.210.07:27:09.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:27:09.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:27:09.76#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:09.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:09.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:09.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:09.82#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:27:09.82#ibcon#first serial, iclass 4, count 2 2006.210.07:27:09.82#ibcon#enter sib2, iclass 4, count 2 2006.210.07:27:09.82#ibcon#flushed, iclass 4, count 2 2006.210.07:27:09.82#ibcon#about to write, iclass 4, count 2 2006.210.07:27:09.82#ibcon#wrote, iclass 4, count 2 2006.210.07:27:09.82#ibcon#about to read 3, iclass 4, count 2 2006.210.07:27:09.84#ibcon#read 3, iclass 4, count 2 2006.210.07:27:09.84#ibcon#about to read 4, iclass 4, count 2 2006.210.07:27:09.84#ibcon#read 4, iclass 4, count 2 2006.210.07:27:09.84#ibcon#about to read 5, iclass 4, count 2 2006.210.07:27:09.84#ibcon#read 5, iclass 4, count 2 2006.210.07:27:09.84#ibcon#about to read 6, iclass 4, count 2 2006.210.07:27:09.84#ibcon#read 6, iclass 4, count 2 2006.210.07:27:09.84#ibcon#end of sib2, iclass 4, count 2 2006.210.07:27:09.84#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:27:09.84#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:27:09.84#ibcon#[25=AT05-07\r\n] 2006.210.07:27:09.84#ibcon#*before write, iclass 4, count 2 2006.210.07:27:09.84#ibcon#enter sib2, iclass 4, count 2 2006.210.07:27:09.84#ibcon#flushed, iclass 4, count 2 2006.210.07:27:09.84#ibcon#about to write, iclass 4, count 2 2006.210.07:27:09.84#ibcon#wrote, iclass 4, count 2 2006.210.07:27:09.84#ibcon#about to read 3, iclass 4, count 2 2006.210.07:27:09.87#ibcon#read 3, iclass 4, count 2 2006.210.07:27:09.87#ibcon#about to read 4, iclass 4, count 2 2006.210.07:27:09.87#ibcon#read 4, iclass 4, count 2 2006.210.07:27:09.87#ibcon#about to read 5, iclass 4, count 2 2006.210.07:27:09.87#ibcon#read 5, iclass 4, count 2 2006.210.07:27:09.87#ibcon#about to read 6, iclass 4, count 2 2006.210.07:27:09.87#ibcon#read 6, iclass 4, count 2 2006.210.07:27:09.87#ibcon#end of sib2, iclass 4, count 2 2006.210.07:27:09.87#ibcon#*after write, iclass 4, count 2 2006.210.07:27:09.87#ibcon#*before return 0, iclass 4, count 2 2006.210.07:27:09.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:09.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:09.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:27:09.87#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:09.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:09.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:09.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:09.99#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:27:09.99#ibcon#first serial, iclass 4, count 0 2006.210.07:27:09.99#ibcon#enter sib2, iclass 4, count 0 2006.210.07:27:09.99#ibcon#flushed, iclass 4, count 0 2006.210.07:27:09.99#ibcon#about to write, iclass 4, count 0 2006.210.07:27:09.99#ibcon#wrote, iclass 4, count 0 2006.210.07:27:09.99#ibcon#about to read 3, iclass 4, count 0 2006.210.07:27:10.01#ibcon#read 3, iclass 4, count 0 2006.210.07:27:10.01#ibcon#about to read 4, iclass 4, count 0 2006.210.07:27:10.01#ibcon#read 4, iclass 4, count 0 2006.210.07:27:10.01#ibcon#about to read 5, iclass 4, count 0 2006.210.07:27:10.01#ibcon#read 5, iclass 4, count 0 2006.210.07:27:10.01#ibcon#about to read 6, iclass 4, count 0 2006.210.07:27:10.01#ibcon#read 6, iclass 4, count 0 2006.210.07:27:10.01#ibcon#end of sib2, iclass 4, count 0 2006.210.07:27:10.01#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:27:10.01#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:27:10.01#ibcon#[25=USB\r\n] 2006.210.07:27:10.01#ibcon#*before write, iclass 4, count 0 2006.210.07:27:10.01#ibcon#enter sib2, iclass 4, count 0 2006.210.07:27:10.01#ibcon#flushed, iclass 4, count 0 2006.210.07:27:10.01#ibcon#about to write, iclass 4, count 0 2006.210.07:27:10.01#ibcon#wrote, iclass 4, count 0 2006.210.07:27:10.01#ibcon#about to read 3, iclass 4, count 0 2006.210.07:27:10.05#ibcon#read 3, iclass 4, count 0 2006.210.07:27:10.05#ibcon#about to read 4, iclass 4, count 0 2006.210.07:27:10.05#ibcon#read 4, iclass 4, count 0 2006.210.07:27:10.05#ibcon#about to read 5, iclass 4, count 0 2006.210.07:27:10.05#ibcon#read 5, iclass 4, count 0 2006.210.07:27:10.05#ibcon#about to read 6, iclass 4, count 0 2006.210.07:27:10.05#ibcon#read 6, iclass 4, count 0 2006.210.07:27:10.05#ibcon#end of sib2, iclass 4, count 0 2006.210.07:27:10.05#ibcon#*after write, iclass 4, count 0 2006.210.07:27:10.05#ibcon#*before return 0, iclass 4, count 0 2006.210.07:27:10.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:10.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:10.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:27:10.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:27:10.05$vc4f8/valo=6,772.99 2006.210.07:27:10.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:27:10.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:27:10.05#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:10.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:10.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:10.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:10.05#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:27:10.05#ibcon#first serial, iclass 6, count 0 2006.210.07:27:10.05#ibcon#enter sib2, iclass 6, count 0 2006.210.07:27:10.05#ibcon#flushed, iclass 6, count 0 2006.210.07:27:10.05#ibcon#about to write, iclass 6, count 0 2006.210.07:27:10.05#ibcon#wrote, iclass 6, count 0 2006.210.07:27:10.05#ibcon#about to read 3, iclass 6, count 0 2006.210.07:27:10.07#ibcon#read 3, iclass 6, count 0 2006.210.07:27:10.07#ibcon#about to read 4, iclass 6, count 0 2006.210.07:27:10.07#ibcon#read 4, iclass 6, count 0 2006.210.07:27:10.07#ibcon#about to read 5, iclass 6, count 0 2006.210.07:27:10.07#ibcon#read 5, iclass 6, count 0 2006.210.07:27:10.07#ibcon#about to read 6, iclass 6, count 0 2006.210.07:27:10.07#ibcon#read 6, iclass 6, count 0 2006.210.07:27:10.07#ibcon#end of sib2, iclass 6, count 0 2006.210.07:27:10.07#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:27:10.07#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:27:10.07#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:27:10.07#ibcon#*before write, iclass 6, count 0 2006.210.07:27:10.07#ibcon#enter sib2, iclass 6, count 0 2006.210.07:27:10.07#ibcon#flushed, iclass 6, count 0 2006.210.07:27:10.07#ibcon#about to write, iclass 6, count 0 2006.210.07:27:10.07#ibcon#wrote, iclass 6, count 0 2006.210.07:27:10.07#ibcon#about to read 3, iclass 6, count 0 2006.210.07:27:10.11#ibcon#read 3, iclass 6, count 0 2006.210.07:27:10.11#ibcon#about to read 4, iclass 6, count 0 2006.210.07:27:10.11#ibcon#read 4, iclass 6, count 0 2006.210.07:27:10.11#ibcon#about to read 5, iclass 6, count 0 2006.210.07:27:10.11#ibcon#read 5, iclass 6, count 0 2006.210.07:27:10.11#ibcon#about to read 6, iclass 6, count 0 2006.210.07:27:10.11#ibcon#read 6, iclass 6, count 0 2006.210.07:27:10.11#ibcon#end of sib2, iclass 6, count 0 2006.210.07:27:10.11#ibcon#*after write, iclass 6, count 0 2006.210.07:27:10.11#ibcon#*before return 0, iclass 6, count 0 2006.210.07:27:10.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:10.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:10.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:27:10.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:27:10.11$vc4f8/va=6,6 2006.210.07:27:10.11#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:27:10.11#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:27:10.11#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:10.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:27:10.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:27:10.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:27:10.17#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:27:10.17#ibcon#first serial, iclass 10, count 2 2006.210.07:27:10.17#ibcon#enter sib2, iclass 10, count 2 2006.210.07:27:10.17#ibcon#flushed, iclass 10, count 2 2006.210.07:27:10.17#ibcon#about to write, iclass 10, count 2 2006.210.07:27:10.17#ibcon#wrote, iclass 10, count 2 2006.210.07:27:10.17#ibcon#about to read 3, iclass 10, count 2 2006.210.07:27:10.19#ibcon#read 3, iclass 10, count 2 2006.210.07:27:10.19#ibcon#about to read 4, iclass 10, count 2 2006.210.07:27:10.19#ibcon#read 4, iclass 10, count 2 2006.210.07:27:10.19#ibcon#about to read 5, iclass 10, count 2 2006.210.07:27:10.19#ibcon#read 5, iclass 10, count 2 2006.210.07:27:10.19#ibcon#about to read 6, iclass 10, count 2 2006.210.07:27:10.19#ibcon#read 6, iclass 10, count 2 2006.210.07:27:10.19#ibcon#end of sib2, iclass 10, count 2 2006.210.07:27:10.19#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:27:10.19#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:27:10.19#ibcon#[25=AT06-06\r\n] 2006.210.07:27:10.19#ibcon#*before write, iclass 10, count 2 2006.210.07:27:10.19#ibcon#enter sib2, iclass 10, count 2 2006.210.07:27:10.19#ibcon#flushed, iclass 10, count 2 2006.210.07:27:10.19#ibcon#about to write, iclass 10, count 2 2006.210.07:27:10.19#ibcon#wrote, iclass 10, count 2 2006.210.07:27:10.19#ibcon#about to read 3, iclass 10, count 2 2006.210.07:27:10.22#ibcon#read 3, iclass 10, count 2 2006.210.07:27:10.22#ibcon#about to read 4, iclass 10, count 2 2006.210.07:27:10.22#ibcon#read 4, iclass 10, count 2 2006.210.07:27:10.22#ibcon#about to read 5, iclass 10, count 2 2006.210.07:27:10.22#ibcon#read 5, iclass 10, count 2 2006.210.07:27:10.22#ibcon#about to read 6, iclass 10, count 2 2006.210.07:27:10.22#ibcon#read 6, iclass 10, count 2 2006.210.07:27:10.22#ibcon#end of sib2, iclass 10, count 2 2006.210.07:27:10.22#ibcon#*after write, iclass 10, count 2 2006.210.07:27:10.22#ibcon#*before return 0, iclass 10, count 2 2006.210.07:27:10.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:27:10.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:27:10.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:27:10.22#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:10.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:27:10.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:27:10.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:27:10.34#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:27:10.34#ibcon#first serial, iclass 10, count 0 2006.210.07:27:10.34#ibcon#enter sib2, iclass 10, count 0 2006.210.07:27:10.34#ibcon#flushed, iclass 10, count 0 2006.210.07:27:10.34#ibcon#about to write, iclass 10, count 0 2006.210.07:27:10.34#ibcon#wrote, iclass 10, count 0 2006.210.07:27:10.34#ibcon#about to read 3, iclass 10, count 0 2006.210.07:27:10.36#ibcon#read 3, iclass 10, count 0 2006.210.07:27:10.36#ibcon#about to read 4, iclass 10, count 0 2006.210.07:27:10.36#ibcon#read 4, iclass 10, count 0 2006.210.07:27:10.36#ibcon#about to read 5, iclass 10, count 0 2006.210.07:27:10.36#ibcon#read 5, iclass 10, count 0 2006.210.07:27:10.36#ibcon#about to read 6, iclass 10, count 0 2006.210.07:27:10.36#ibcon#read 6, iclass 10, count 0 2006.210.07:27:10.36#ibcon#end of sib2, iclass 10, count 0 2006.210.07:27:10.36#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:27:10.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:27:10.36#ibcon#[25=USB\r\n] 2006.210.07:27:10.36#ibcon#*before write, iclass 10, count 0 2006.210.07:27:10.36#ibcon#enter sib2, iclass 10, count 0 2006.210.07:27:10.36#ibcon#flushed, iclass 10, count 0 2006.210.07:27:10.36#ibcon#about to write, iclass 10, count 0 2006.210.07:27:10.36#ibcon#wrote, iclass 10, count 0 2006.210.07:27:10.36#ibcon#about to read 3, iclass 10, count 0 2006.210.07:27:10.39#ibcon#read 3, iclass 10, count 0 2006.210.07:27:10.39#ibcon#about to read 4, iclass 10, count 0 2006.210.07:27:10.39#ibcon#read 4, iclass 10, count 0 2006.210.07:27:10.39#ibcon#about to read 5, iclass 10, count 0 2006.210.07:27:10.39#ibcon#read 5, iclass 10, count 0 2006.210.07:27:10.39#ibcon#about to read 6, iclass 10, count 0 2006.210.07:27:10.39#ibcon#read 6, iclass 10, count 0 2006.210.07:27:10.39#ibcon#end of sib2, iclass 10, count 0 2006.210.07:27:10.39#ibcon#*after write, iclass 10, count 0 2006.210.07:27:10.39#ibcon#*before return 0, iclass 10, count 0 2006.210.07:27:10.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:27:10.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:27:10.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:27:10.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:27:10.39$vc4f8/valo=7,832.99 2006.210.07:27:10.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:27:10.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:27:10.39#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:10.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:27:10.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:27:10.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:27:10.39#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:27:10.39#ibcon#first serial, iclass 12, count 0 2006.210.07:27:10.39#ibcon#enter sib2, iclass 12, count 0 2006.210.07:27:10.39#ibcon#flushed, iclass 12, count 0 2006.210.07:27:10.39#ibcon#about to write, iclass 12, count 0 2006.210.07:27:10.39#ibcon#wrote, iclass 12, count 0 2006.210.07:27:10.39#ibcon#about to read 3, iclass 12, count 0 2006.210.07:27:10.41#ibcon#read 3, iclass 12, count 0 2006.210.07:27:10.41#ibcon#about to read 4, iclass 12, count 0 2006.210.07:27:10.41#ibcon#read 4, iclass 12, count 0 2006.210.07:27:10.41#ibcon#about to read 5, iclass 12, count 0 2006.210.07:27:10.41#ibcon#read 5, iclass 12, count 0 2006.210.07:27:10.41#ibcon#about to read 6, iclass 12, count 0 2006.210.07:27:10.41#ibcon#read 6, iclass 12, count 0 2006.210.07:27:10.41#ibcon#end of sib2, iclass 12, count 0 2006.210.07:27:10.41#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:27:10.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:27:10.41#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:27:10.41#ibcon#*before write, iclass 12, count 0 2006.210.07:27:10.41#ibcon#enter sib2, iclass 12, count 0 2006.210.07:27:10.41#ibcon#flushed, iclass 12, count 0 2006.210.07:27:10.41#ibcon#about to write, iclass 12, count 0 2006.210.07:27:10.41#ibcon#wrote, iclass 12, count 0 2006.210.07:27:10.41#ibcon#about to read 3, iclass 12, count 0 2006.210.07:27:10.45#ibcon#read 3, iclass 12, count 0 2006.210.07:27:10.45#ibcon#about to read 4, iclass 12, count 0 2006.210.07:27:10.45#ibcon#read 4, iclass 12, count 0 2006.210.07:27:10.45#ibcon#about to read 5, iclass 12, count 0 2006.210.07:27:10.45#ibcon#read 5, iclass 12, count 0 2006.210.07:27:10.45#ibcon#about to read 6, iclass 12, count 0 2006.210.07:27:10.45#ibcon#read 6, iclass 12, count 0 2006.210.07:27:10.45#ibcon#end of sib2, iclass 12, count 0 2006.210.07:27:10.45#ibcon#*after write, iclass 12, count 0 2006.210.07:27:10.45#ibcon#*before return 0, iclass 12, count 0 2006.210.07:27:10.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:27:10.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:27:10.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:27:10.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:27:10.45$vc4f8/va=7,6 2006.210.07:27:10.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:27:10.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:27:10.45#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:10.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:27:10.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:27:10.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:27:10.51#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:27:10.51#ibcon#first serial, iclass 14, count 2 2006.210.07:27:10.51#ibcon#enter sib2, iclass 14, count 2 2006.210.07:27:10.51#ibcon#flushed, iclass 14, count 2 2006.210.07:27:10.51#ibcon#about to write, iclass 14, count 2 2006.210.07:27:10.51#ibcon#wrote, iclass 14, count 2 2006.210.07:27:10.51#ibcon#about to read 3, iclass 14, count 2 2006.210.07:27:10.53#ibcon#read 3, iclass 14, count 2 2006.210.07:27:10.53#ibcon#about to read 4, iclass 14, count 2 2006.210.07:27:10.53#ibcon#read 4, iclass 14, count 2 2006.210.07:27:10.53#ibcon#about to read 5, iclass 14, count 2 2006.210.07:27:10.53#ibcon#read 5, iclass 14, count 2 2006.210.07:27:10.53#ibcon#about to read 6, iclass 14, count 2 2006.210.07:27:10.53#ibcon#read 6, iclass 14, count 2 2006.210.07:27:10.53#ibcon#end of sib2, iclass 14, count 2 2006.210.07:27:10.53#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:27:10.53#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:27:10.53#ibcon#[25=AT07-06\r\n] 2006.210.07:27:10.53#ibcon#*before write, iclass 14, count 2 2006.210.07:27:10.53#ibcon#enter sib2, iclass 14, count 2 2006.210.07:27:10.53#ibcon#flushed, iclass 14, count 2 2006.210.07:27:10.53#ibcon#about to write, iclass 14, count 2 2006.210.07:27:10.53#ibcon#wrote, iclass 14, count 2 2006.210.07:27:10.53#ibcon#about to read 3, iclass 14, count 2 2006.210.07:27:10.57#ibcon#read 3, iclass 14, count 2 2006.210.07:27:10.57#ibcon#about to read 4, iclass 14, count 2 2006.210.07:27:10.57#ibcon#read 4, iclass 14, count 2 2006.210.07:27:10.57#ibcon#about to read 5, iclass 14, count 2 2006.210.07:27:10.57#ibcon#read 5, iclass 14, count 2 2006.210.07:27:10.57#ibcon#about to read 6, iclass 14, count 2 2006.210.07:27:10.57#ibcon#read 6, iclass 14, count 2 2006.210.07:27:10.57#ibcon#end of sib2, iclass 14, count 2 2006.210.07:27:10.57#ibcon#*after write, iclass 14, count 2 2006.210.07:27:10.57#ibcon#*before return 0, iclass 14, count 2 2006.210.07:27:10.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:27:10.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:27:10.57#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:27:10.57#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:10.57#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:27:10.69#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:27:10.69#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:27:10.69#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:27:10.69#ibcon#first serial, iclass 14, count 0 2006.210.07:27:10.69#ibcon#enter sib2, iclass 14, count 0 2006.210.07:27:10.69#ibcon#flushed, iclass 14, count 0 2006.210.07:27:10.69#ibcon#about to write, iclass 14, count 0 2006.210.07:27:10.69#ibcon#wrote, iclass 14, count 0 2006.210.07:27:10.69#ibcon#about to read 3, iclass 14, count 0 2006.210.07:27:10.71#ibcon#read 3, iclass 14, count 0 2006.210.07:27:10.71#ibcon#about to read 4, iclass 14, count 0 2006.210.07:27:10.71#ibcon#read 4, iclass 14, count 0 2006.210.07:27:10.71#ibcon#about to read 5, iclass 14, count 0 2006.210.07:27:10.71#ibcon#read 5, iclass 14, count 0 2006.210.07:27:10.71#ibcon#about to read 6, iclass 14, count 0 2006.210.07:27:10.71#ibcon#read 6, iclass 14, count 0 2006.210.07:27:10.71#ibcon#end of sib2, iclass 14, count 0 2006.210.07:27:10.71#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:27:10.71#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:27:10.71#ibcon#[25=USB\r\n] 2006.210.07:27:10.71#ibcon#*before write, iclass 14, count 0 2006.210.07:27:10.71#ibcon#enter sib2, iclass 14, count 0 2006.210.07:27:10.71#ibcon#flushed, iclass 14, count 0 2006.210.07:27:10.71#ibcon#about to write, iclass 14, count 0 2006.210.07:27:10.71#ibcon#wrote, iclass 14, count 0 2006.210.07:27:10.71#ibcon#about to read 3, iclass 14, count 0 2006.210.07:27:10.74#ibcon#read 3, iclass 14, count 0 2006.210.07:27:10.74#ibcon#about to read 4, iclass 14, count 0 2006.210.07:27:10.74#ibcon#read 4, iclass 14, count 0 2006.210.07:27:10.74#ibcon#about to read 5, iclass 14, count 0 2006.210.07:27:10.74#ibcon#read 5, iclass 14, count 0 2006.210.07:27:10.74#ibcon#about to read 6, iclass 14, count 0 2006.210.07:27:10.74#ibcon#read 6, iclass 14, count 0 2006.210.07:27:10.74#ibcon#end of sib2, iclass 14, count 0 2006.210.07:27:10.74#ibcon#*after write, iclass 14, count 0 2006.210.07:27:10.74#ibcon#*before return 0, iclass 14, count 0 2006.210.07:27:10.74#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:27:10.74#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:27:10.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:27:10.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:27:10.74$vc4f8/valo=8,852.99 2006.210.07:27:10.74#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:27:10.74#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:27:10.74#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:10.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:27:10.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:27:10.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:27:10.74#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:27:10.74#ibcon#first serial, iclass 16, count 0 2006.210.07:27:10.74#ibcon#enter sib2, iclass 16, count 0 2006.210.07:27:10.74#ibcon#flushed, iclass 16, count 0 2006.210.07:27:10.74#ibcon#about to write, iclass 16, count 0 2006.210.07:27:10.74#ibcon#wrote, iclass 16, count 0 2006.210.07:27:10.74#ibcon#about to read 3, iclass 16, count 0 2006.210.07:27:10.76#ibcon#read 3, iclass 16, count 0 2006.210.07:27:10.76#ibcon#about to read 4, iclass 16, count 0 2006.210.07:27:10.76#ibcon#read 4, iclass 16, count 0 2006.210.07:27:10.76#ibcon#about to read 5, iclass 16, count 0 2006.210.07:27:10.76#ibcon#read 5, iclass 16, count 0 2006.210.07:27:10.76#ibcon#about to read 6, iclass 16, count 0 2006.210.07:27:10.76#ibcon#read 6, iclass 16, count 0 2006.210.07:27:10.76#ibcon#end of sib2, iclass 16, count 0 2006.210.07:27:10.76#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:27:10.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:27:10.76#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:27:10.76#ibcon#*before write, iclass 16, count 0 2006.210.07:27:10.76#ibcon#enter sib2, iclass 16, count 0 2006.210.07:27:10.76#ibcon#flushed, iclass 16, count 0 2006.210.07:27:10.76#ibcon#about to write, iclass 16, count 0 2006.210.07:27:10.76#ibcon#wrote, iclass 16, count 0 2006.210.07:27:10.76#ibcon#about to read 3, iclass 16, count 0 2006.210.07:27:10.80#ibcon#read 3, iclass 16, count 0 2006.210.07:27:10.80#ibcon#about to read 4, iclass 16, count 0 2006.210.07:27:10.80#ibcon#read 4, iclass 16, count 0 2006.210.07:27:10.80#ibcon#about to read 5, iclass 16, count 0 2006.210.07:27:10.80#ibcon#read 5, iclass 16, count 0 2006.210.07:27:10.80#ibcon#about to read 6, iclass 16, count 0 2006.210.07:27:10.80#ibcon#read 6, iclass 16, count 0 2006.210.07:27:10.80#ibcon#end of sib2, iclass 16, count 0 2006.210.07:27:10.80#ibcon#*after write, iclass 16, count 0 2006.210.07:27:10.80#ibcon#*before return 0, iclass 16, count 0 2006.210.07:27:10.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:27:10.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:27:10.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:27:10.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:27:10.80$vc4f8/va=8,7 2006.210.07:27:10.80#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:27:10.80#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:27:10.80#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:10.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:27:10.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:27:10.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:27:10.86#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:27:10.86#ibcon#first serial, iclass 18, count 2 2006.210.07:27:10.86#ibcon#enter sib2, iclass 18, count 2 2006.210.07:27:10.86#ibcon#flushed, iclass 18, count 2 2006.210.07:27:10.86#ibcon#about to write, iclass 18, count 2 2006.210.07:27:10.86#ibcon#wrote, iclass 18, count 2 2006.210.07:27:10.86#ibcon#about to read 3, iclass 18, count 2 2006.210.07:27:10.88#ibcon#read 3, iclass 18, count 2 2006.210.07:27:10.88#ibcon#about to read 4, iclass 18, count 2 2006.210.07:27:10.88#ibcon#read 4, iclass 18, count 2 2006.210.07:27:10.88#ibcon#about to read 5, iclass 18, count 2 2006.210.07:27:10.88#ibcon#read 5, iclass 18, count 2 2006.210.07:27:10.88#ibcon#about to read 6, iclass 18, count 2 2006.210.07:27:10.88#ibcon#read 6, iclass 18, count 2 2006.210.07:27:10.88#ibcon#end of sib2, iclass 18, count 2 2006.210.07:27:10.88#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:27:10.88#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:27:10.88#ibcon#[25=AT08-07\r\n] 2006.210.07:27:10.88#ibcon#*before write, iclass 18, count 2 2006.210.07:27:10.88#ibcon#enter sib2, iclass 18, count 2 2006.210.07:27:10.88#ibcon#flushed, iclass 18, count 2 2006.210.07:27:10.88#ibcon#about to write, iclass 18, count 2 2006.210.07:27:10.88#ibcon#wrote, iclass 18, count 2 2006.210.07:27:10.88#ibcon#about to read 3, iclass 18, count 2 2006.210.07:27:10.91#ibcon#read 3, iclass 18, count 2 2006.210.07:27:10.91#ibcon#about to read 4, iclass 18, count 2 2006.210.07:27:10.91#ibcon#read 4, iclass 18, count 2 2006.210.07:27:10.91#ibcon#about to read 5, iclass 18, count 2 2006.210.07:27:10.91#ibcon#read 5, iclass 18, count 2 2006.210.07:27:10.91#ibcon#about to read 6, iclass 18, count 2 2006.210.07:27:10.91#ibcon#read 6, iclass 18, count 2 2006.210.07:27:10.91#ibcon#end of sib2, iclass 18, count 2 2006.210.07:27:10.91#ibcon#*after write, iclass 18, count 2 2006.210.07:27:10.91#ibcon#*before return 0, iclass 18, count 2 2006.210.07:27:10.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:27:10.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:27:10.91#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:27:10.91#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:10.91#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:27:11.03#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:27:11.03#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:27:11.03#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:27:11.03#ibcon#first serial, iclass 18, count 0 2006.210.07:27:11.03#ibcon#enter sib2, iclass 18, count 0 2006.210.07:27:11.03#ibcon#flushed, iclass 18, count 0 2006.210.07:27:11.03#ibcon#about to write, iclass 18, count 0 2006.210.07:27:11.03#ibcon#wrote, iclass 18, count 0 2006.210.07:27:11.03#ibcon#about to read 3, iclass 18, count 0 2006.210.07:27:11.05#ibcon#read 3, iclass 18, count 0 2006.210.07:27:11.05#ibcon#about to read 4, iclass 18, count 0 2006.210.07:27:11.05#ibcon#read 4, iclass 18, count 0 2006.210.07:27:11.05#ibcon#about to read 5, iclass 18, count 0 2006.210.07:27:11.05#ibcon#read 5, iclass 18, count 0 2006.210.07:27:11.05#ibcon#about to read 6, iclass 18, count 0 2006.210.07:27:11.05#ibcon#read 6, iclass 18, count 0 2006.210.07:27:11.05#ibcon#end of sib2, iclass 18, count 0 2006.210.07:27:11.05#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:27:11.05#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:27:11.05#ibcon#[25=USB\r\n] 2006.210.07:27:11.05#ibcon#*before write, iclass 18, count 0 2006.210.07:27:11.05#ibcon#enter sib2, iclass 18, count 0 2006.210.07:27:11.05#ibcon#flushed, iclass 18, count 0 2006.210.07:27:11.05#ibcon#about to write, iclass 18, count 0 2006.210.07:27:11.05#ibcon#wrote, iclass 18, count 0 2006.210.07:27:11.05#ibcon#about to read 3, iclass 18, count 0 2006.210.07:27:11.08#ibcon#read 3, iclass 18, count 0 2006.210.07:27:11.08#ibcon#about to read 4, iclass 18, count 0 2006.210.07:27:11.08#ibcon#read 4, iclass 18, count 0 2006.210.07:27:11.08#ibcon#about to read 5, iclass 18, count 0 2006.210.07:27:11.08#ibcon#read 5, iclass 18, count 0 2006.210.07:27:11.08#ibcon#about to read 6, iclass 18, count 0 2006.210.07:27:11.08#ibcon#read 6, iclass 18, count 0 2006.210.07:27:11.08#ibcon#end of sib2, iclass 18, count 0 2006.210.07:27:11.08#ibcon#*after write, iclass 18, count 0 2006.210.07:27:11.08#ibcon#*before return 0, iclass 18, count 0 2006.210.07:27:11.08#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:27:11.08#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:27:11.08#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:27:11.08#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:27:11.08$vc4f8/vblo=1,632.99 2006.210.07:27:11.08#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:27:11.08#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:27:11.08#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:11.08#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:27:11.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:27:11.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:27:11.08#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:27:11.08#ibcon#first serial, iclass 20, count 0 2006.210.07:27:11.08#ibcon#enter sib2, iclass 20, count 0 2006.210.07:27:11.08#ibcon#flushed, iclass 20, count 0 2006.210.07:27:11.08#ibcon#about to write, iclass 20, count 0 2006.210.07:27:11.08#ibcon#wrote, iclass 20, count 0 2006.210.07:27:11.08#ibcon#about to read 3, iclass 20, count 0 2006.210.07:27:11.10#ibcon#read 3, iclass 20, count 0 2006.210.07:27:11.10#ibcon#about to read 4, iclass 20, count 0 2006.210.07:27:11.10#ibcon#read 4, iclass 20, count 0 2006.210.07:27:11.10#ibcon#about to read 5, iclass 20, count 0 2006.210.07:27:11.10#ibcon#read 5, iclass 20, count 0 2006.210.07:27:11.10#ibcon#about to read 6, iclass 20, count 0 2006.210.07:27:11.10#ibcon#read 6, iclass 20, count 0 2006.210.07:27:11.10#ibcon#end of sib2, iclass 20, count 0 2006.210.07:27:11.10#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:27:11.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:27:11.10#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:27:11.10#ibcon#*before write, iclass 20, count 0 2006.210.07:27:11.10#ibcon#enter sib2, iclass 20, count 0 2006.210.07:27:11.10#ibcon#flushed, iclass 20, count 0 2006.210.07:27:11.10#ibcon#about to write, iclass 20, count 0 2006.210.07:27:11.10#ibcon#wrote, iclass 20, count 0 2006.210.07:27:11.10#ibcon#about to read 3, iclass 20, count 0 2006.210.07:27:11.16#ibcon#read 3, iclass 20, count 0 2006.210.07:27:11.16#ibcon#about to read 4, iclass 20, count 0 2006.210.07:27:11.16#ibcon#read 4, iclass 20, count 0 2006.210.07:27:11.16#ibcon#about to read 5, iclass 20, count 0 2006.210.07:27:11.16#ibcon#read 5, iclass 20, count 0 2006.210.07:27:11.16#ibcon#about to read 6, iclass 20, count 0 2006.210.07:27:11.16#ibcon#read 6, iclass 20, count 0 2006.210.07:27:11.16#ibcon#end of sib2, iclass 20, count 0 2006.210.07:27:11.16#ibcon#*after write, iclass 20, count 0 2006.210.07:27:11.16#ibcon#*before return 0, iclass 20, count 0 2006.210.07:27:11.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:27:11.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:27:11.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:27:11.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:27:11.16$vc4f8/vb=1,4 2006.210.07:27:11.16#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:27:11.16#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:27:11.16#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:11.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:27:11.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:27:11.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:27:11.16#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:27:11.16#ibcon#first serial, iclass 22, count 2 2006.210.07:27:11.16#ibcon#enter sib2, iclass 22, count 2 2006.210.07:27:11.16#ibcon#flushed, iclass 22, count 2 2006.210.07:27:11.16#ibcon#about to write, iclass 22, count 2 2006.210.07:27:11.16#ibcon#wrote, iclass 22, count 2 2006.210.07:27:11.16#ibcon#about to read 3, iclass 22, count 2 2006.210.07:27:11.18#ibcon#read 3, iclass 22, count 2 2006.210.07:27:11.18#ibcon#about to read 4, iclass 22, count 2 2006.210.07:27:11.18#ibcon#read 4, iclass 22, count 2 2006.210.07:27:11.18#ibcon#about to read 5, iclass 22, count 2 2006.210.07:27:11.18#ibcon#read 5, iclass 22, count 2 2006.210.07:27:11.18#ibcon#about to read 6, iclass 22, count 2 2006.210.07:27:11.18#ibcon#read 6, iclass 22, count 2 2006.210.07:27:11.18#ibcon#end of sib2, iclass 22, count 2 2006.210.07:27:11.18#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:27:11.18#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:27:11.18#ibcon#[27=AT01-04\r\n] 2006.210.07:27:11.18#ibcon#*before write, iclass 22, count 2 2006.210.07:27:11.18#ibcon#enter sib2, iclass 22, count 2 2006.210.07:27:11.18#ibcon#flushed, iclass 22, count 2 2006.210.07:27:11.18#ibcon#about to write, iclass 22, count 2 2006.210.07:27:11.18#ibcon#wrote, iclass 22, count 2 2006.210.07:27:11.18#ibcon#about to read 3, iclass 22, count 2 2006.210.07:27:11.22#ibcon#read 3, iclass 22, count 2 2006.210.07:27:11.22#ibcon#about to read 4, iclass 22, count 2 2006.210.07:27:11.22#ibcon#read 4, iclass 22, count 2 2006.210.07:27:11.22#ibcon#about to read 5, iclass 22, count 2 2006.210.07:27:11.22#ibcon#read 5, iclass 22, count 2 2006.210.07:27:11.22#ibcon#about to read 6, iclass 22, count 2 2006.210.07:27:11.22#ibcon#read 6, iclass 22, count 2 2006.210.07:27:11.22#ibcon#end of sib2, iclass 22, count 2 2006.210.07:27:11.22#ibcon#*after write, iclass 22, count 2 2006.210.07:27:11.22#ibcon#*before return 0, iclass 22, count 2 2006.210.07:27:11.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:27:11.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:27:11.22#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:27:11.22#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:11.22#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:27:11.34#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:27:11.34#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:27:11.34#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:27:11.34#ibcon#first serial, iclass 22, count 0 2006.210.07:27:11.34#ibcon#enter sib2, iclass 22, count 0 2006.210.07:27:11.34#ibcon#flushed, iclass 22, count 0 2006.210.07:27:11.34#ibcon#about to write, iclass 22, count 0 2006.210.07:27:11.34#ibcon#wrote, iclass 22, count 0 2006.210.07:27:11.34#ibcon#about to read 3, iclass 22, count 0 2006.210.07:27:11.36#ibcon#read 3, iclass 22, count 0 2006.210.07:27:11.36#ibcon#about to read 4, iclass 22, count 0 2006.210.07:27:11.36#ibcon#read 4, iclass 22, count 0 2006.210.07:27:11.36#ibcon#about to read 5, iclass 22, count 0 2006.210.07:27:11.36#ibcon#read 5, iclass 22, count 0 2006.210.07:27:11.36#ibcon#about to read 6, iclass 22, count 0 2006.210.07:27:11.36#ibcon#read 6, iclass 22, count 0 2006.210.07:27:11.36#ibcon#end of sib2, iclass 22, count 0 2006.210.07:27:11.36#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:27:11.36#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:27:11.36#ibcon#[27=USB\r\n] 2006.210.07:27:11.36#ibcon#*before write, iclass 22, count 0 2006.210.07:27:11.36#ibcon#enter sib2, iclass 22, count 0 2006.210.07:27:11.36#ibcon#flushed, iclass 22, count 0 2006.210.07:27:11.36#ibcon#about to write, iclass 22, count 0 2006.210.07:27:11.36#ibcon#wrote, iclass 22, count 0 2006.210.07:27:11.36#ibcon#about to read 3, iclass 22, count 0 2006.210.07:27:11.39#ibcon#read 3, iclass 22, count 0 2006.210.07:27:11.39#ibcon#about to read 4, iclass 22, count 0 2006.210.07:27:11.39#ibcon#read 4, iclass 22, count 0 2006.210.07:27:11.39#ibcon#about to read 5, iclass 22, count 0 2006.210.07:27:11.39#ibcon#read 5, iclass 22, count 0 2006.210.07:27:11.39#ibcon#about to read 6, iclass 22, count 0 2006.210.07:27:11.39#ibcon#read 6, iclass 22, count 0 2006.210.07:27:11.39#ibcon#end of sib2, iclass 22, count 0 2006.210.07:27:11.39#ibcon#*after write, iclass 22, count 0 2006.210.07:27:11.39#ibcon#*before return 0, iclass 22, count 0 2006.210.07:27:11.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:27:11.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:27:11.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:27:11.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:27:11.39$vc4f8/vblo=2,640.99 2006.210.07:27:11.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:27:11.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:27:11.39#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:11.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:11.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:11.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:11.39#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:27:11.39#ibcon#first serial, iclass 24, count 0 2006.210.07:27:11.39#ibcon#enter sib2, iclass 24, count 0 2006.210.07:27:11.39#ibcon#flushed, iclass 24, count 0 2006.210.07:27:11.39#ibcon#about to write, iclass 24, count 0 2006.210.07:27:11.39#ibcon#wrote, iclass 24, count 0 2006.210.07:27:11.39#ibcon#about to read 3, iclass 24, count 0 2006.210.07:27:11.41#ibcon#read 3, iclass 24, count 0 2006.210.07:27:11.41#ibcon#about to read 4, iclass 24, count 0 2006.210.07:27:11.41#ibcon#read 4, iclass 24, count 0 2006.210.07:27:11.41#ibcon#about to read 5, iclass 24, count 0 2006.210.07:27:11.41#ibcon#read 5, iclass 24, count 0 2006.210.07:27:11.41#ibcon#about to read 6, iclass 24, count 0 2006.210.07:27:11.41#ibcon#read 6, iclass 24, count 0 2006.210.07:27:11.41#ibcon#end of sib2, iclass 24, count 0 2006.210.07:27:11.41#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:27:11.41#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:27:11.41#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:27:11.41#ibcon#*before write, iclass 24, count 0 2006.210.07:27:11.41#ibcon#enter sib2, iclass 24, count 0 2006.210.07:27:11.41#ibcon#flushed, iclass 24, count 0 2006.210.07:27:11.41#ibcon#about to write, iclass 24, count 0 2006.210.07:27:11.41#ibcon#wrote, iclass 24, count 0 2006.210.07:27:11.41#ibcon#about to read 3, iclass 24, count 0 2006.210.07:27:11.45#ibcon#read 3, iclass 24, count 0 2006.210.07:27:11.45#ibcon#about to read 4, iclass 24, count 0 2006.210.07:27:11.45#ibcon#read 4, iclass 24, count 0 2006.210.07:27:11.45#ibcon#about to read 5, iclass 24, count 0 2006.210.07:27:11.45#ibcon#read 5, iclass 24, count 0 2006.210.07:27:11.45#ibcon#about to read 6, iclass 24, count 0 2006.210.07:27:11.45#ibcon#read 6, iclass 24, count 0 2006.210.07:27:11.45#ibcon#end of sib2, iclass 24, count 0 2006.210.07:27:11.45#ibcon#*after write, iclass 24, count 0 2006.210.07:27:11.45#ibcon#*before return 0, iclass 24, count 0 2006.210.07:27:11.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:11.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:27:11.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:27:11.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:27:11.45$vc4f8/vb=2,4 2006.210.07:27:11.45#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:27:11.45#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:27:11.45#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:11.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:11.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:11.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:11.51#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:27:11.51#ibcon#first serial, iclass 26, count 2 2006.210.07:27:11.51#ibcon#enter sib2, iclass 26, count 2 2006.210.07:27:11.51#ibcon#flushed, iclass 26, count 2 2006.210.07:27:11.51#ibcon#about to write, iclass 26, count 2 2006.210.07:27:11.51#ibcon#wrote, iclass 26, count 2 2006.210.07:27:11.51#ibcon#about to read 3, iclass 26, count 2 2006.210.07:27:11.53#ibcon#read 3, iclass 26, count 2 2006.210.07:27:11.53#ibcon#about to read 4, iclass 26, count 2 2006.210.07:27:11.53#ibcon#read 4, iclass 26, count 2 2006.210.07:27:11.53#ibcon#about to read 5, iclass 26, count 2 2006.210.07:27:11.53#ibcon#read 5, iclass 26, count 2 2006.210.07:27:11.53#ibcon#about to read 6, iclass 26, count 2 2006.210.07:27:11.53#ibcon#read 6, iclass 26, count 2 2006.210.07:27:11.53#ibcon#end of sib2, iclass 26, count 2 2006.210.07:27:11.53#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:27:11.53#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:27:11.53#ibcon#[27=AT02-04\r\n] 2006.210.07:27:11.53#ibcon#*before write, iclass 26, count 2 2006.210.07:27:11.53#ibcon#enter sib2, iclass 26, count 2 2006.210.07:27:11.53#ibcon#flushed, iclass 26, count 2 2006.210.07:27:11.53#ibcon#about to write, iclass 26, count 2 2006.210.07:27:11.53#ibcon#wrote, iclass 26, count 2 2006.210.07:27:11.53#ibcon#about to read 3, iclass 26, count 2 2006.210.07:27:11.56#ibcon#read 3, iclass 26, count 2 2006.210.07:27:11.56#ibcon#about to read 4, iclass 26, count 2 2006.210.07:27:11.56#ibcon#read 4, iclass 26, count 2 2006.210.07:27:11.56#ibcon#about to read 5, iclass 26, count 2 2006.210.07:27:11.56#ibcon#read 5, iclass 26, count 2 2006.210.07:27:11.56#ibcon#about to read 6, iclass 26, count 2 2006.210.07:27:11.56#ibcon#read 6, iclass 26, count 2 2006.210.07:27:11.56#ibcon#end of sib2, iclass 26, count 2 2006.210.07:27:11.56#ibcon#*after write, iclass 26, count 2 2006.210.07:27:11.56#ibcon#*before return 0, iclass 26, count 2 2006.210.07:27:11.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:11.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:27:11.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:27:11.56#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:11.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:11.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:11.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:11.68#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:27:11.68#ibcon#first serial, iclass 26, count 0 2006.210.07:27:11.68#ibcon#enter sib2, iclass 26, count 0 2006.210.07:27:11.68#ibcon#flushed, iclass 26, count 0 2006.210.07:27:11.68#ibcon#about to write, iclass 26, count 0 2006.210.07:27:11.68#ibcon#wrote, iclass 26, count 0 2006.210.07:27:11.68#ibcon#about to read 3, iclass 26, count 0 2006.210.07:27:11.70#ibcon#read 3, iclass 26, count 0 2006.210.07:27:11.70#ibcon#about to read 4, iclass 26, count 0 2006.210.07:27:11.70#ibcon#read 4, iclass 26, count 0 2006.210.07:27:11.70#ibcon#about to read 5, iclass 26, count 0 2006.210.07:27:11.70#ibcon#read 5, iclass 26, count 0 2006.210.07:27:11.70#ibcon#about to read 6, iclass 26, count 0 2006.210.07:27:11.70#ibcon#read 6, iclass 26, count 0 2006.210.07:27:11.70#ibcon#end of sib2, iclass 26, count 0 2006.210.07:27:11.70#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:27:11.70#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:27:11.70#ibcon#[27=USB\r\n] 2006.210.07:27:11.70#ibcon#*before write, iclass 26, count 0 2006.210.07:27:11.70#ibcon#enter sib2, iclass 26, count 0 2006.210.07:27:11.70#ibcon#flushed, iclass 26, count 0 2006.210.07:27:11.70#ibcon#about to write, iclass 26, count 0 2006.210.07:27:11.70#ibcon#wrote, iclass 26, count 0 2006.210.07:27:11.70#ibcon#about to read 3, iclass 26, count 0 2006.210.07:27:11.73#ibcon#read 3, iclass 26, count 0 2006.210.07:27:11.73#ibcon#about to read 4, iclass 26, count 0 2006.210.07:27:11.73#ibcon#read 4, iclass 26, count 0 2006.210.07:27:11.73#ibcon#about to read 5, iclass 26, count 0 2006.210.07:27:11.73#ibcon#read 5, iclass 26, count 0 2006.210.07:27:11.73#ibcon#about to read 6, iclass 26, count 0 2006.210.07:27:11.73#ibcon#read 6, iclass 26, count 0 2006.210.07:27:11.73#ibcon#end of sib2, iclass 26, count 0 2006.210.07:27:11.73#ibcon#*after write, iclass 26, count 0 2006.210.07:27:11.73#ibcon#*before return 0, iclass 26, count 0 2006.210.07:27:11.73#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:11.73#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:27:11.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:27:11.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:27:11.73$vc4f8/vblo=3,656.99 2006.210.07:27:11.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:27:11.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:27:11.73#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:11.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:11.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:11.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:11.73#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:27:11.73#ibcon#first serial, iclass 28, count 0 2006.210.07:27:11.73#ibcon#enter sib2, iclass 28, count 0 2006.210.07:27:11.73#ibcon#flushed, iclass 28, count 0 2006.210.07:27:11.73#ibcon#about to write, iclass 28, count 0 2006.210.07:27:11.73#ibcon#wrote, iclass 28, count 0 2006.210.07:27:11.73#ibcon#about to read 3, iclass 28, count 0 2006.210.07:27:11.75#ibcon#read 3, iclass 28, count 0 2006.210.07:27:11.75#ibcon#about to read 4, iclass 28, count 0 2006.210.07:27:11.75#ibcon#read 4, iclass 28, count 0 2006.210.07:27:11.75#ibcon#about to read 5, iclass 28, count 0 2006.210.07:27:11.75#ibcon#read 5, iclass 28, count 0 2006.210.07:27:11.75#ibcon#about to read 6, iclass 28, count 0 2006.210.07:27:11.75#ibcon#read 6, iclass 28, count 0 2006.210.07:27:11.75#ibcon#end of sib2, iclass 28, count 0 2006.210.07:27:11.75#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:27:11.75#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:27:11.75#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:27:11.75#ibcon#*before write, iclass 28, count 0 2006.210.07:27:11.75#ibcon#enter sib2, iclass 28, count 0 2006.210.07:27:11.75#ibcon#flushed, iclass 28, count 0 2006.210.07:27:11.75#ibcon#about to write, iclass 28, count 0 2006.210.07:27:11.75#ibcon#wrote, iclass 28, count 0 2006.210.07:27:11.75#ibcon#about to read 3, iclass 28, count 0 2006.210.07:27:11.79#ibcon#read 3, iclass 28, count 0 2006.210.07:27:11.79#ibcon#about to read 4, iclass 28, count 0 2006.210.07:27:11.79#ibcon#read 4, iclass 28, count 0 2006.210.07:27:11.79#ibcon#about to read 5, iclass 28, count 0 2006.210.07:27:11.79#ibcon#read 5, iclass 28, count 0 2006.210.07:27:11.79#ibcon#about to read 6, iclass 28, count 0 2006.210.07:27:11.79#ibcon#read 6, iclass 28, count 0 2006.210.07:27:11.79#ibcon#end of sib2, iclass 28, count 0 2006.210.07:27:11.79#ibcon#*after write, iclass 28, count 0 2006.210.07:27:11.79#ibcon#*before return 0, iclass 28, count 0 2006.210.07:27:11.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:11.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:27:11.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:27:11.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:27:11.79$vc4f8/vb=3,3 2006.210.07:27:11.79#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:27:11.79#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:27:11.79#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:11.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:11.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:11.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:11.85#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:27:11.85#ibcon#first serial, iclass 30, count 2 2006.210.07:27:11.85#ibcon#enter sib2, iclass 30, count 2 2006.210.07:27:11.85#ibcon#flushed, iclass 30, count 2 2006.210.07:27:11.85#ibcon#about to write, iclass 30, count 2 2006.210.07:27:11.85#ibcon#wrote, iclass 30, count 2 2006.210.07:27:11.85#ibcon#about to read 3, iclass 30, count 2 2006.210.07:27:11.87#ibcon#read 3, iclass 30, count 2 2006.210.07:27:11.87#ibcon#about to read 4, iclass 30, count 2 2006.210.07:27:11.87#ibcon#read 4, iclass 30, count 2 2006.210.07:27:11.87#ibcon#about to read 5, iclass 30, count 2 2006.210.07:27:11.87#ibcon#read 5, iclass 30, count 2 2006.210.07:27:11.87#ibcon#about to read 6, iclass 30, count 2 2006.210.07:27:11.87#ibcon#read 6, iclass 30, count 2 2006.210.07:27:11.87#ibcon#end of sib2, iclass 30, count 2 2006.210.07:27:11.87#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:27:11.87#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:27:11.87#ibcon#[27=AT03-03\r\n] 2006.210.07:27:11.87#ibcon#*before write, iclass 30, count 2 2006.210.07:27:11.87#ibcon#enter sib2, iclass 30, count 2 2006.210.07:27:11.87#ibcon#flushed, iclass 30, count 2 2006.210.07:27:11.87#ibcon#about to write, iclass 30, count 2 2006.210.07:27:11.87#ibcon#wrote, iclass 30, count 2 2006.210.07:27:11.87#ibcon#about to read 3, iclass 30, count 2 2006.210.07:27:11.90#ibcon#read 3, iclass 30, count 2 2006.210.07:27:11.90#ibcon#about to read 4, iclass 30, count 2 2006.210.07:27:11.90#ibcon#read 4, iclass 30, count 2 2006.210.07:27:11.90#ibcon#about to read 5, iclass 30, count 2 2006.210.07:27:11.90#ibcon#read 5, iclass 30, count 2 2006.210.07:27:11.90#ibcon#about to read 6, iclass 30, count 2 2006.210.07:27:11.90#ibcon#read 6, iclass 30, count 2 2006.210.07:27:11.90#ibcon#end of sib2, iclass 30, count 2 2006.210.07:27:11.90#ibcon#*after write, iclass 30, count 2 2006.210.07:27:11.90#ibcon#*before return 0, iclass 30, count 2 2006.210.07:27:11.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:11.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:27:11.90#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:27:11.90#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:11.90#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:12.02#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:12.02#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:12.02#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:27:12.02#ibcon#first serial, iclass 30, count 0 2006.210.07:27:12.02#ibcon#enter sib2, iclass 30, count 0 2006.210.07:27:12.02#ibcon#flushed, iclass 30, count 0 2006.210.07:27:12.02#ibcon#about to write, iclass 30, count 0 2006.210.07:27:12.02#ibcon#wrote, iclass 30, count 0 2006.210.07:27:12.02#ibcon#about to read 3, iclass 30, count 0 2006.210.07:27:12.04#ibcon#read 3, iclass 30, count 0 2006.210.07:27:12.04#ibcon#about to read 4, iclass 30, count 0 2006.210.07:27:12.04#ibcon#read 4, iclass 30, count 0 2006.210.07:27:12.04#ibcon#about to read 5, iclass 30, count 0 2006.210.07:27:12.04#ibcon#read 5, iclass 30, count 0 2006.210.07:27:12.04#ibcon#about to read 6, iclass 30, count 0 2006.210.07:27:12.04#ibcon#read 6, iclass 30, count 0 2006.210.07:27:12.04#ibcon#end of sib2, iclass 30, count 0 2006.210.07:27:12.04#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:27:12.04#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:27:12.04#ibcon#[27=USB\r\n] 2006.210.07:27:12.04#ibcon#*before write, iclass 30, count 0 2006.210.07:27:12.04#ibcon#enter sib2, iclass 30, count 0 2006.210.07:27:12.04#ibcon#flushed, iclass 30, count 0 2006.210.07:27:12.04#ibcon#about to write, iclass 30, count 0 2006.210.07:27:12.04#ibcon#wrote, iclass 30, count 0 2006.210.07:27:12.04#ibcon#about to read 3, iclass 30, count 0 2006.210.07:27:12.07#ibcon#read 3, iclass 30, count 0 2006.210.07:27:12.07#ibcon#about to read 4, iclass 30, count 0 2006.210.07:27:12.07#ibcon#read 4, iclass 30, count 0 2006.210.07:27:12.07#ibcon#about to read 5, iclass 30, count 0 2006.210.07:27:12.07#ibcon#read 5, iclass 30, count 0 2006.210.07:27:12.07#ibcon#about to read 6, iclass 30, count 0 2006.210.07:27:12.07#ibcon#read 6, iclass 30, count 0 2006.210.07:27:12.07#ibcon#end of sib2, iclass 30, count 0 2006.210.07:27:12.07#ibcon#*after write, iclass 30, count 0 2006.210.07:27:12.07#ibcon#*before return 0, iclass 30, count 0 2006.210.07:27:12.07#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:12.07#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:27:12.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:27:12.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:27:12.07$vc4f8/vblo=4,712.99 2006.210.07:27:12.07#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:27:12.07#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:27:12.07#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:12.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:12.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:12.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:12.07#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:27:12.07#ibcon#first serial, iclass 32, count 0 2006.210.07:27:12.07#ibcon#enter sib2, iclass 32, count 0 2006.210.07:27:12.07#ibcon#flushed, iclass 32, count 0 2006.210.07:27:12.07#ibcon#about to write, iclass 32, count 0 2006.210.07:27:12.07#ibcon#wrote, iclass 32, count 0 2006.210.07:27:12.07#ibcon#about to read 3, iclass 32, count 0 2006.210.07:27:12.09#ibcon#read 3, iclass 32, count 0 2006.210.07:27:12.09#ibcon#about to read 4, iclass 32, count 0 2006.210.07:27:12.09#ibcon#read 4, iclass 32, count 0 2006.210.07:27:12.09#ibcon#about to read 5, iclass 32, count 0 2006.210.07:27:12.09#ibcon#read 5, iclass 32, count 0 2006.210.07:27:12.09#ibcon#about to read 6, iclass 32, count 0 2006.210.07:27:12.09#ibcon#read 6, iclass 32, count 0 2006.210.07:27:12.09#ibcon#end of sib2, iclass 32, count 0 2006.210.07:27:12.09#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:27:12.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:27:12.09#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:27:12.09#ibcon#*before write, iclass 32, count 0 2006.210.07:27:12.09#ibcon#enter sib2, iclass 32, count 0 2006.210.07:27:12.09#ibcon#flushed, iclass 32, count 0 2006.210.07:27:12.09#ibcon#about to write, iclass 32, count 0 2006.210.07:27:12.09#ibcon#wrote, iclass 32, count 0 2006.210.07:27:12.09#ibcon#about to read 3, iclass 32, count 0 2006.210.07:27:12.13#ibcon#read 3, iclass 32, count 0 2006.210.07:27:12.13#ibcon#about to read 4, iclass 32, count 0 2006.210.07:27:12.13#ibcon#read 4, iclass 32, count 0 2006.210.07:27:12.13#ibcon#about to read 5, iclass 32, count 0 2006.210.07:27:12.13#ibcon#read 5, iclass 32, count 0 2006.210.07:27:12.13#ibcon#about to read 6, iclass 32, count 0 2006.210.07:27:12.13#ibcon#read 6, iclass 32, count 0 2006.210.07:27:12.13#ibcon#end of sib2, iclass 32, count 0 2006.210.07:27:12.13#ibcon#*after write, iclass 32, count 0 2006.210.07:27:12.13#ibcon#*before return 0, iclass 32, count 0 2006.210.07:27:12.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:12.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:27:12.13#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:27:12.13#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:27:12.13$vc4f8/vb=4,3 2006.210.07:27:12.13#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:27:12.13#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:27:12.13#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:12.13#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:12.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:12.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:12.19#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:27:12.19#ibcon#first serial, iclass 34, count 2 2006.210.07:27:12.19#ibcon#enter sib2, iclass 34, count 2 2006.210.07:27:12.19#ibcon#flushed, iclass 34, count 2 2006.210.07:27:12.19#ibcon#about to write, iclass 34, count 2 2006.210.07:27:12.19#ibcon#wrote, iclass 34, count 2 2006.210.07:27:12.19#ibcon#about to read 3, iclass 34, count 2 2006.210.07:27:12.21#ibcon#read 3, iclass 34, count 2 2006.210.07:27:12.21#ibcon#about to read 4, iclass 34, count 2 2006.210.07:27:12.21#ibcon#read 4, iclass 34, count 2 2006.210.07:27:12.21#ibcon#about to read 5, iclass 34, count 2 2006.210.07:27:12.21#ibcon#read 5, iclass 34, count 2 2006.210.07:27:12.21#ibcon#about to read 6, iclass 34, count 2 2006.210.07:27:12.21#ibcon#read 6, iclass 34, count 2 2006.210.07:27:12.21#ibcon#end of sib2, iclass 34, count 2 2006.210.07:27:12.21#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:27:12.21#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:27:12.21#ibcon#[27=AT04-03\r\n] 2006.210.07:27:12.21#ibcon#*before write, iclass 34, count 2 2006.210.07:27:12.21#ibcon#enter sib2, iclass 34, count 2 2006.210.07:27:12.21#ibcon#flushed, iclass 34, count 2 2006.210.07:27:12.21#ibcon#about to write, iclass 34, count 2 2006.210.07:27:12.21#ibcon#wrote, iclass 34, count 2 2006.210.07:27:12.21#ibcon#about to read 3, iclass 34, count 2 2006.210.07:27:12.24#ibcon#read 3, iclass 34, count 2 2006.210.07:27:12.24#ibcon#about to read 4, iclass 34, count 2 2006.210.07:27:12.24#ibcon#read 4, iclass 34, count 2 2006.210.07:27:12.24#ibcon#about to read 5, iclass 34, count 2 2006.210.07:27:12.24#ibcon#read 5, iclass 34, count 2 2006.210.07:27:12.24#ibcon#about to read 6, iclass 34, count 2 2006.210.07:27:12.24#ibcon#read 6, iclass 34, count 2 2006.210.07:27:12.24#ibcon#end of sib2, iclass 34, count 2 2006.210.07:27:12.24#ibcon#*after write, iclass 34, count 2 2006.210.07:27:12.24#ibcon#*before return 0, iclass 34, count 2 2006.210.07:27:12.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:12.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:27:12.24#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:27:12.24#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:12.24#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:12.36#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:12.36#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:12.36#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:27:12.36#ibcon#first serial, iclass 34, count 0 2006.210.07:27:12.36#ibcon#enter sib2, iclass 34, count 0 2006.210.07:27:12.36#ibcon#flushed, iclass 34, count 0 2006.210.07:27:12.36#ibcon#about to write, iclass 34, count 0 2006.210.07:27:12.36#ibcon#wrote, iclass 34, count 0 2006.210.07:27:12.36#ibcon#about to read 3, iclass 34, count 0 2006.210.07:27:12.38#ibcon#read 3, iclass 34, count 0 2006.210.07:27:12.38#ibcon#about to read 4, iclass 34, count 0 2006.210.07:27:12.38#ibcon#read 4, iclass 34, count 0 2006.210.07:27:12.38#ibcon#about to read 5, iclass 34, count 0 2006.210.07:27:12.38#ibcon#read 5, iclass 34, count 0 2006.210.07:27:12.38#ibcon#about to read 6, iclass 34, count 0 2006.210.07:27:12.38#ibcon#read 6, iclass 34, count 0 2006.210.07:27:12.38#ibcon#end of sib2, iclass 34, count 0 2006.210.07:27:12.38#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:27:12.38#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:27:12.38#ibcon#[27=USB\r\n] 2006.210.07:27:12.38#ibcon#*before write, iclass 34, count 0 2006.210.07:27:12.38#ibcon#enter sib2, iclass 34, count 0 2006.210.07:27:12.38#ibcon#flushed, iclass 34, count 0 2006.210.07:27:12.38#ibcon#about to write, iclass 34, count 0 2006.210.07:27:12.38#ibcon#wrote, iclass 34, count 0 2006.210.07:27:12.38#ibcon#about to read 3, iclass 34, count 0 2006.210.07:27:12.41#ibcon#read 3, iclass 34, count 0 2006.210.07:27:12.41#ibcon#about to read 4, iclass 34, count 0 2006.210.07:27:12.41#ibcon#read 4, iclass 34, count 0 2006.210.07:27:12.41#ibcon#about to read 5, iclass 34, count 0 2006.210.07:27:12.41#ibcon#read 5, iclass 34, count 0 2006.210.07:27:12.41#ibcon#about to read 6, iclass 34, count 0 2006.210.07:27:12.41#ibcon#read 6, iclass 34, count 0 2006.210.07:27:12.41#ibcon#end of sib2, iclass 34, count 0 2006.210.07:27:12.41#ibcon#*after write, iclass 34, count 0 2006.210.07:27:12.41#ibcon#*before return 0, iclass 34, count 0 2006.210.07:27:12.41#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:12.41#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:27:12.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:27:12.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:27:12.41$vc4f8/vblo=5,744.99 2006.210.07:27:12.41#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:27:12.41#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:27:12.41#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:12.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:12.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:12.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:12.41#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:27:12.41#ibcon#first serial, iclass 36, count 0 2006.210.07:27:12.41#ibcon#enter sib2, iclass 36, count 0 2006.210.07:27:12.41#ibcon#flushed, iclass 36, count 0 2006.210.07:27:12.41#ibcon#about to write, iclass 36, count 0 2006.210.07:27:12.41#ibcon#wrote, iclass 36, count 0 2006.210.07:27:12.41#ibcon#about to read 3, iclass 36, count 0 2006.210.07:27:12.43#ibcon#read 3, iclass 36, count 0 2006.210.07:27:12.43#ibcon#about to read 4, iclass 36, count 0 2006.210.07:27:12.43#ibcon#read 4, iclass 36, count 0 2006.210.07:27:12.43#ibcon#about to read 5, iclass 36, count 0 2006.210.07:27:12.43#ibcon#read 5, iclass 36, count 0 2006.210.07:27:12.43#ibcon#about to read 6, iclass 36, count 0 2006.210.07:27:12.43#ibcon#read 6, iclass 36, count 0 2006.210.07:27:12.43#ibcon#end of sib2, iclass 36, count 0 2006.210.07:27:12.43#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:27:12.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:27:12.43#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:27:12.43#ibcon#*before write, iclass 36, count 0 2006.210.07:27:12.43#ibcon#enter sib2, iclass 36, count 0 2006.210.07:27:12.43#ibcon#flushed, iclass 36, count 0 2006.210.07:27:12.43#ibcon#about to write, iclass 36, count 0 2006.210.07:27:12.43#ibcon#wrote, iclass 36, count 0 2006.210.07:27:12.43#ibcon#about to read 3, iclass 36, count 0 2006.210.07:27:12.47#ibcon#read 3, iclass 36, count 0 2006.210.07:27:12.47#ibcon#about to read 4, iclass 36, count 0 2006.210.07:27:12.47#ibcon#read 4, iclass 36, count 0 2006.210.07:27:12.47#ibcon#about to read 5, iclass 36, count 0 2006.210.07:27:12.47#ibcon#read 5, iclass 36, count 0 2006.210.07:27:12.47#ibcon#about to read 6, iclass 36, count 0 2006.210.07:27:12.47#ibcon#read 6, iclass 36, count 0 2006.210.07:27:12.47#ibcon#end of sib2, iclass 36, count 0 2006.210.07:27:12.47#ibcon#*after write, iclass 36, count 0 2006.210.07:27:12.47#ibcon#*before return 0, iclass 36, count 0 2006.210.07:27:12.47#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:12.47#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:27:12.47#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:27:12.47#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:27:12.47$vc4f8/vb=5,3 2006.210.07:27:12.47#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:27:12.47#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:27:12.47#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:12.47#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:12.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:12.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:12.53#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:27:12.53#ibcon#first serial, iclass 38, count 2 2006.210.07:27:12.53#ibcon#enter sib2, iclass 38, count 2 2006.210.07:27:12.53#ibcon#flushed, iclass 38, count 2 2006.210.07:27:12.53#ibcon#about to write, iclass 38, count 2 2006.210.07:27:12.53#ibcon#wrote, iclass 38, count 2 2006.210.07:27:12.53#ibcon#about to read 3, iclass 38, count 2 2006.210.07:27:12.55#ibcon#read 3, iclass 38, count 2 2006.210.07:27:12.55#ibcon#about to read 4, iclass 38, count 2 2006.210.07:27:12.55#ibcon#read 4, iclass 38, count 2 2006.210.07:27:12.55#ibcon#about to read 5, iclass 38, count 2 2006.210.07:27:12.55#ibcon#read 5, iclass 38, count 2 2006.210.07:27:12.55#ibcon#about to read 6, iclass 38, count 2 2006.210.07:27:12.55#ibcon#read 6, iclass 38, count 2 2006.210.07:27:12.55#ibcon#end of sib2, iclass 38, count 2 2006.210.07:27:12.55#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:27:12.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:27:12.55#ibcon#[27=AT05-03\r\n] 2006.210.07:27:12.55#ibcon#*before write, iclass 38, count 2 2006.210.07:27:12.55#ibcon#enter sib2, iclass 38, count 2 2006.210.07:27:12.55#ibcon#flushed, iclass 38, count 2 2006.210.07:27:12.55#ibcon#about to write, iclass 38, count 2 2006.210.07:27:12.55#ibcon#wrote, iclass 38, count 2 2006.210.07:27:12.55#ibcon#about to read 3, iclass 38, count 2 2006.210.07:27:12.58#ibcon#read 3, iclass 38, count 2 2006.210.07:27:12.58#ibcon#about to read 4, iclass 38, count 2 2006.210.07:27:12.58#ibcon#read 4, iclass 38, count 2 2006.210.07:27:12.58#ibcon#about to read 5, iclass 38, count 2 2006.210.07:27:12.58#ibcon#read 5, iclass 38, count 2 2006.210.07:27:12.58#ibcon#about to read 6, iclass 38, count 2 2006.210.07:27:12.58#ibcon#read 6, iclass 38, count 2 2006.210.07:27:12.58#ibcon#end of sib2, iclass 38, count 2 2006.210.07:27:12.58#ibcon#*after write, iclass 38, count 2 2006.210.07:27:12.58#ibcon#*before return 0, iclass 38, count 2 2006.210.07:27:12.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:12.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:27:12.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:27:12.58#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:12.58#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:12.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:12.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:12.70#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:27:12.70#ibcon#first serial, iclass 38, count 0 2006.210.07:27:12.70#ibcon#enter sib2, iclass 38, count 0 2006.210.07:27:12.70#ibcon#flushed, iclass 38, count 0 2006.210.07:27:12.70#ibcon#about to write, iclass 38, count 0 2006.210.07:27:12.70#ibcon#wrote, iclass 38, count 0 2006.210.07:27:12.70#ibcon#about to read 3, iclass 38, count 0 2006.210.07:27:12.72#ibcon#read 3, iclass 38, count 0 2006.210.07:27:12.72#ibcon#about to read 4, iclass 38, count 0 2006.210.07:27:12.72#ibcon#read 4, iclass 38, count 0 2006.210.07:27:12.72#ibcon#about to read 5, iclass 38, count 0 2006.210.07:27:12.72#ibcon#read 5, iclass 38, count 0 2006.210.07:27:12.72#ibcon#about to read 6, iclass 38, count 0 2006.210.07:27:12.72#ibcon#read 6, iclass 38, count 0 2006.210.07:27:12.72#ibcon#end of sib2, iclass 38, count 0 2006.210.07:27:12.72#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:27:12.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:27:12.72#ibcon#[27=USB\r\n] 2006.210.07:27:12.72#ibcon#*before write, iclass 38, count 0 2006.210.07:27:12.72#ibcon#enter sib2, iclass 38, count 0 2006.210.07:27:12.72#ibcon#flushed, iclass 38, count 0 2006.210.07:27:12.72#ibcon#about to write, iclass 38, count 0 2006.210.07:27:12.72#ibcon#wrote, iclass 38, count 0 2006.210.07:27:12.72#ibcon#about to read 3, iclass 38, count 0 2006.210.07:27:12.75#ibcon#read 3, iclass 38, count 0 2006.210.07:27:12.75#ibcon#about to read 4, iclass 38, count 0 2006.210.07:27:12.75#ibcon#read 4, iclass 38, count 0 2006.210.07:27:12.75#ibcon#about to read 5, iclass 38, count 0 2006.210.07:27:12.75#ibcon#read 5, iclass 38, count 0 2006.210.07:27:12.75#ibcon#about to read 6, iclass 38, count 0 2006.210.07:27:12.75#ibcon#read 6, iclass 38, count 0 2006.210.07:27:12.75#ibcon#end of sib2, iclass 38, count 0 2006.210.07:27:12.75#ibcon#*after write, iclass 38, count 0 2006.210.07:27:12.75#ibcon#*before return 0, iclass 38, count 0 2006.210.07:27:12.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:12.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:27:12.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:27:12.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:27:12.75$vc4f8/vblo=6,752.99 2006.210.07:27:12.75#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:27:12.75#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:27:12.75#ibcon#ireg 17 cls_cnt 0 2006.210.07:27:12.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:12.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:12.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:12.75#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:27:12.75#ibcon#first serial, iclass 40, count 0 2006.210.07:27:12.75#ibcon#enter sib2, iclass 40, count 0 2006.210.07:27:12.75#ibcon#flushed, iclass 40, count 0 2006.210.07:27:12.75#ibcon#about to write, iclass 40, count 0 2006.210.07:27:12.75#ibcon#wrote, iclass 40, count 0 2006.210.07:27:12.75#ibcon#about to read 3, iclass 40, count 0 2006.210.07:27:12.77#ibcon#read 3, iclass 40, count 0 2006.210.07:27:12.77#ibcon#about to read 4, iclass 40, count 0 2006.210.07:27:12.77#ibcon#read 4, iclass 40, count 0 2006.210.07:27:12.77#ibcon#about to read 5, iclass 40, count 0 2006.210.07:27:12.77#ibcon#read 5, iclass 40, count 0 2006.210.07:27:12.77#ibcon#about to read 6, iclass 40, count 0 2006.210.07:27:12.77#ibcon#read 6, iclass 40, count 0 2006.210.07:27:12.77#ibcon#end of sib2, iclass 40, count 0 2006.210.07:27:12.77#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:27:12.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:27:12.77#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:27:12.77#ibcon#*before write, iclass 40, count 0 2006.210.07:27:12.77#ibcon#enter sib2, iclass 40, count 0 2006.210.07:27:12.77#ibcon#flushed, iclass 40, count 0 2006.210.07:27:12.77#ibcon#about to write, iclass 40, count 0 2006.210.07:27:12.77#ibcon#wrote, iclass 40, count 0 2006.210.07:27:12.77#ibcon#about to read 3, iclass 40, count 0 2006.210.07:27:12.81#ibcon#read 3, iclass 40, count 0 2006.210.07:27:12.81#ibcon#about to read 4, iclass 40, count 0 2006.210.07:27:12.81#ibcon#read 4, iclass 40, count 0 2006.210.07:27:12.81#ibcon#about to read 5, iclass 40, count 0 2006.210.07:27:12.81#ibcon#read 5, iclass 40, count 0 2006.210.07:27:12.81#ibcon#about to read 6, iclass 40, count 0 2006.210.07:27:12.81#ibcon#read 6, iclass 40, count 0 2006.210.07:27:12.81#ibcon#end of sib2, iclass 40, count 0 2006.210.07:27:12.81#ibcon#*after write, iclass 40, count 0 2006.210.07:27:12.81#ibcon#*before return 0, iclass 40, count 0 2006.210.07:27:12.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:12.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:27:12.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:27:12.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:27:12.81$vc4f8/vb=6,3 2006.210.07:27:12.81#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:27:12.81#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:27:12.81#ibcon#ireg 11 cls_cnt 2 2006.210.07:27:12.81#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:12.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:12.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:12.87#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:27:12.87#ibcon#first serial, iclass 4, count 2 2006.210.07:27:12.87#ibcon#enter sib2, iclass 4, count 2 2006.210.07:27:12.87#ibcon#flushed, iclass 4, count 2 2006.210.07:27:12.87#ibcon#about to write, iclass 4, count 2 2006.210.07:27:12.87#ibcon#wrote, iclass 4, count 2 2006.210.07:27:12.87#ibcon#about to read 3, iclass 4, count 2 2006.210.07:27:12.89#ibcon#read 3, iclass 4, count 2 2006.210.07:27:12.89#ibcon#about to read 4, iclass 4, count 2 2006.210.07:27:12.89#ibcon#read 4, iclass 4, count 2 2006.210.07:27:12.89#ibcon#about to read 5, iclass 4, count 2 2006.210.07:27:12.89#ibcon#read 5, iclass 4, count 2 2006.210.07:27:12.89#ibcon#about to read 6, iclass 4, count 2 2006.210.07:27:12.89#ibcon#read 6, iclass 4, count 2 2006.210.07:27:12.89#ibcon#end of sib2, iclass 4, count 2 2006.210.07:27:12.89#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:27:12.89#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:27:12.89#ibcon#[27=AT06-03\r\n] 2006.210.07:27:12.89#ibcon#*before write, iclass 4, count 2 2006.210.07:27:12.89#ibcon#enter sib2, iclass 4, count 2 2006.210.07:27:12.89#ibcon#flushed, iclass 4, count 2 2006.210.07:27:12.89#ibcon#about to write, iclass 4, count 2 2006.210.07:27:12.89#ibcon#wrote, iclass 4, count 2 2006.210.07:27:12.89#ibcon#about to read 3, iclass 4, count 2 2006.210.07:27:12.92#ibcon#read 3, iclass 4, count 2 2006.210.07:27:12.92#ibcon#about to read 4, iclass 4, count 2 2006.210.07:27:12.92#ibcon#read 4, iclass 4, count 2 2006.210.07:27:12.92#ibcon#about to read 5, iclass 4, count 2 2006.210.07:27:12.92#ibcon#read 5, iclass 4, count 2 2006.210.07:27:12.92#ibcon#about to read 6, iclass 4, count 2 2006.210.07:27:12.92#ibcon#read 6, iclass 4, count 2 2006.210.07:27:12.92#ibcon#end of sib2, iclass 4, count 2 2006.210.07:27:12.92#ibcon#*after write, iclass 4, count 2 2006.210.07:27:12.92#ibcon#*before return 0, iclass 4, count 2 2006.210.07:27:12.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:12.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:27:12.92#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:27:12.92#ibcon#ireg 7 cls_cnt 0 2006.210.07:27:12.92#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:13.04#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:13.04#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:13.04#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:27:13.04#ibcon#first serial, iclass 4, count 0 2006.210.07:27:13.04#ibcon#enter sib2, iclass 4, count 0 2006.210.07:27:13.04#ibcon#flushed, iclass 4, count 0 2006.210.07:27:13.04#ibcon#about to write, iclass 4, count 0 2006.210.07:27:13.04#ibcon#wrote, iclass 4, count 0 2006.210.07:27:13.04#ibcon#about to read 3, iclass 4, count 0 2006.210.07:27:13.06#ibcon#read 3, iclass 4, count 0 2006.210.07:27:13.06#ibcon#about to read 4, iclass 4, count 0 2006.210.07:27:13.06#ibcon#read 4, iclass 4, count 0 2006.210.07:27:13.06#ibcon#about to read 5, iclass 4, count 0 2006.210.07:27:13.06#ibcon#read 5, iclass 4, count 0 2006.210.07:27:13.06#ibcon#about to read 6, iclass 4, count 0 2006.210.07:27:13.06#ibcon#read 6, iclass 4, count 0 2006.210.07:27:13.06#ibcon#end of sib2, iclass 4, count 0 2006.210.07:27:13.06#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:27:13.06#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:27:13.06#ibcon#[27=USB\r\n] 2006.210.07:27:13.06#ibcon#*before write, iclass 4, count 0 2006.210.07:27:13.06#ibcon#enter sib2, iclass 4, count 0 2006.210.07:27:13.06#ibcon#flushed, iclass 4, count 0 2006.210.07:27:13.06#ibcon#about to write, iclass 4, count 0 2006.210.07:27:13.06#ibcon#wrote, iclass 4, count 0 2006.210.07:27:13.06#ibcon#about to read 3, iclass 4, count 0 2006.210.07:27:13.09#ibcon#read 3, iclass 4, count 0 2006.210.07:27:13.09#ibcon#about to read 4, iclass 4, count 0 2006.210.07:27:13.09#ibcon#read 4, iclass 4, count 0 2006.210.07:27:13.09#ibcon#about to read 5, iclass 4, count 0 2006.210.07:27:13.09#ibcon#read 5, iclass 4, count 0 2006.210.07:27:13.09#ibcon#about to read 6, iclass 4, count 0 2006.210.07:27:13.09#ibcon#read 6, iclass 4, count 0 2006.210.07:27:13.09#ibcon#end of sib2, iclass 4, count 0 2006.210.07:27:13.09#ibcon#*after write, iclass 4, count 0 2006.210.07:27:13.09#ibcon#*before return 0, iclass 4, count 0 2006.210.07:27:13.09#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:13.09#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:27:13.09#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:27:13.09#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:27:13.09$vc4f8/vabw=wide 2006.210.07:27:13.09#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:27:13.09#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:27:13.09#ibcon#ireg 8 cls_cnt 0 2006.210.07:27:13.09#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:13.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:13.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:13.09#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:27:13.09#ibcon#first serial, iclass 6, count 0 2006.210.07:27:13.09#ibcon#enter sib2, iclass 6, count 0 2006.210.07:27:13.09#ibcon#flushed, iclass 6, count 0 2006.210.07:27:13.09#ibcon#about to write, iclass 6, count 0 2006.210.07:27:13.09#ibcon#wrote, iclass 6, count 0 2006.210.07:27:13.09#ibcon#about to read 3, iclass 6, count 0 2006.210.07:27:13.11#ibcon#read 3, iclass 6, count 0 2006.210.07:27:13.11#ibcon#about to read 4, iclass 6, count 0 2006.210.07:27:13.11#ibcon#read 4, iclass 6, count 0 2006.210.07:27:13.11#ibcon#about to read 5, iclass 6, count 0 2006.210.07:27:13.11#ibcon#read 5, iclass 6, count 0 2006.210.07:27:13.11#ibcon#about to read 6, iclass 6, count 0 2006.210.07:27:13.11#ibcon#read 6, iclass 6, count 0 2006.210.07:27:13.11#ibcon#end of sib2, iclass 6, count 0 2006.210.07:27:13.11#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:27:13.11#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:27:13.11#ibcon#[25=BW32\r\n] 2006.210.07:27:13.11#ibcon#*before write, iclass 6, count 0 2006.210.07:27:13.11#ibcon#enter sib2, iclass 6, count 0 2006.210.07:27:13.11#ibcon#flushed, iclass 6, count 0 2006.210.07:27:13.11#ibcon#about to write, iclass 6, count 0 2006.210.07:27:13.11#ibcon#wrote, iclass 6, count 0 2006.210.07:27:13.11#ibcon#about to read 3, iclass 6, count 0 2006.210.07:27:13.14#ibcon#read 3, iclass 6, count 0 2006.210.07:27:13.14#ibcon#about to read 4, iclass 6, count 0 2006.210.07:27:13.14#ibcon#read 4, iclass 6, count 0 2006.210.07:27:13.14#ibcon#about to read 5, iclass 6, count 0 2006.210.07:27:13.14#ibcon#read 5, iclass 6, count 0 2006.210.07:27:13.14#ibcon#about to read 6, iclass 6, count 0 2006.210.07:27:13.14#ibcon#read 6, iclass 6, count 0 2006.210.07:27:13.14#ibcon#end of sib2, iclass 6, count 0 2006.210.07:27:13.14#ibcon#*after write, iclass 6, count 0 2006.210.07:27:13.14#ibcon#*before return 0, iclass 6, count 0 2006.210.07:27:13.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:13.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:27:13.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:27:13.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:27:13.14$vc4f8/vbbw=wide 2006.210.07:27:13.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.07:27:13.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.07:27:13.14#ibcon#ireg 8 cls_cnt 0 2006.210.07:27:13.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:27:13.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:27:13.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:27:13.21#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:27:13.21#ibcon#first serial, iclass 10, count 0 2006.210.07:27:13.21#ibcon#enter sib2, iclass 10, count 0 2006.210.07:27:13.21#ibcon#flushed, iclass 10, count 0 2006.210.07:27:13.21#ibcon#about to write, iclass 10, count 0 2006.210.07:27:13.21#ibcon#wrote, iclass 10, count 0 2006.210.07:27:13.21#ibcon#about to read 3, iclass 10, count 0 2006.210.07:27:13.23#ibcon#read 3, iclass 10, count 0 2006.210.07:27:13.23#ibcon#about to read 4, iclass 10, count 0 2006.210.07:27:13.23#ibcon#read 4, iclass 10, count 0 2006.210.07:27:13.23#ibcon#about to read 5, iclass 10, count 0 2006.210.07:27:13.23#ibcon#read 5, iclass 10, count 0 2006.210.07:27:13.23#ibcon#about to read 6, iclass 10, count 0 2006.210.07:27:13.23#ibcon#read 6, iclass 10, count 0 2006.210.07:27:13.23#ibcon#end of sib2, iclass 10, count 0 2006.210.07:27:13.23#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:27:13.23#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:27:13.23#ibcon#[27=BW32\r\n] 2006.210.07:27:13.23#ibcon#*before write, iclass 10, count 0 2006.210.07:27:13.23#ibcon#enter sib2, iclass 10, count 0 2006.210.07:27:13.23#ibcon#flushed, iclass 10, count 0 2006.210.07:27:13.23#ibcon#about to write, iclass 10, count 0 2006.210.07:27:13.23#ibcon#wrote, iclass 10, count 0 2006.210.07:27:13.23#ibcon#about to read 3, iclass 10, count 0 2006.210.07:27:13.26#ibcon#read 3, iclass 10, count 0 2006.210.07:27:13.26#ibcon#about to read 4, iclass 10, count 0 2006.210.07:27:13.26#ibcon#read 4, iclass 10, count 0 2006.210.07:27:13.26#ibcon#about to read 5, iclass 10, count 0 2006.210.07:27:13.26#ibcon#read 5, iclass 10, count 0 2006.210.07:27:13.26#ibcon#about to read 6, iclass 10, count 0 2006.210.07:27:13.26#ibcon#read 6, iclass 10, count 0 2006.210.07:27:13.26#ibcon#end of sib2, iclass 10, count 0 2006.210.07:27:13.26#ibcon#*after write, iclass 10, count 0 2006.210.07:27:13.26#ibcon#*before return 0, iclass 10, count 0 2006.210.07:27:13.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:27:13.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:27:13.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:27:13.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:27:13.26$4f8m12a/ifd4f 2006.210.07:27:13.26&ifd4f/lo= 2006.210.07:27:13.26&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:27:13.26&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:27:13.26&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:27:13.26&ifd4f/patch= 2006.210.07:27:13.26&ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:27:13.26&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:27:13.26&ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:27:13.26$ifd4f/lo= 2006.210.07:27:13.26$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:27:13.26$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:27:13.26$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:27:13.26$ifd4f/patch= 2006.210.07:27:13.26$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:27:13.26$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:27:13.26$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:27:13.26$4f8m12a/"form=m,16.000,1:2 2006.210.07:27:13.26$4f8m12a/"tpicd 2006.210.07:27:13.26$4f8m12a/echo=off 2006.210.07:27:13.26$4f8m12a/xlog=off 2006.210.07:27:13.26:!2006.210.07:29:50 2006.210.07:27:31.13#trakl#Source acquired 2006.210.07:27:31.13#flagr#flagr/antenna,acquired 2006.210.07:29:50.00:preob 2006.210.07:29:50.00&preob/onsource 2006.210.07:29:50.14/onsource/TRACKING 2006.210.07:29:50.14:!2006.210.07:30:00 2006.210.07:30:00.00:data_valid=on 2006.210.07:30:00.00:midob 2006.210.07:30:00.00&midob/onsource 2006.210.07:30:00.00&midob/wx 2006.210.07:30:00.00&midob/cable 2006.210.07:30:00.00&midob/va 2006.210.07:30:00.00&midob/valo 2006.210.07:30:00.00&midob/vb 2006.210.07:30:00.00&midob/vblo 2006.210.07:30:00.00&midob/vabw 2006.210.07:30:00.00&midob/vbbw 2006.210.07:30:00.00&midob/"form 2006.210.07:30:00.00&midob/xfe 2006.210.07:30:00.00&midob/ifatt 2006.210.07:30:00.00&midob/clockoff 2006.210.07:30:00.00&midob/sy=logmail 2006.210.07:30:00.00&midob/"sy=run setcl adapt & 2006.210.07:30:01.14/onsource/TRACKING 2006.210.07:30:01.14/wx/27.74,1006.2,90 2006.210.07:30:01.34/cable/+6.4229E-03 2006.210.07:30:02.43/va/01,08,usb,yes,32,34 2006.210.07:30:02.43/va/02,07,usb,yes,32,33 2006.210.07:30:02.43/va/03,06,usb,yes,34,34 2006.210.07:30:02.43/va/04,07,usb,yes,33,35 2006.210.07:30:02.43/va/05,07,usb,yes,36,38 2006.210.07:30:02.43/va/06,06,usb,yes,35,35 2006.210.07:30:02.43/va/07,06,usb,yes,36,35 2006.210.07:30:02.43/va/08,07,usb,yes,34,33 2006.210.07:30:02.66/valo/01,532.99,yes,locked 2006.210.07:30:02.66/valo/02,572.99,yes,locked 2006.210.07:30:02.66/valo/03,672.99,yes,locked 2006.210.07:30:02.66/valo/04,832.99,yes,locked 2006.210.07:30:02.66/valo/05,652.99,yes,locked 2006.210.07:30:02.66/valo/06,772.99,yes,locked 2006.210.07:30:02.66/valo/07,832.99,yes,locked 2006.210.07:30:02.66/valo/08,852.99,yes,locked 2006.210.07:30:03.75/vb/01,04,usb,yes,30,29 2006.210.07:30:03.75/vb/02,04,usb,yes,32,33 2006.210.07:30:03.75/vb/03,03,usb,yes,35,39 2006.210.07:30:03.75/vb/04,03,usb,yes,36,36 2006.210.07:30:03.75/vb/05,03,usb,yes,35,39 2006.210.07:30:03.75/vb/06,03,usb,yes,35,39 2006.210.07:30:03.75/vb/07,04,usb,yes,31,31 2006.210.07:30:03.75/vb/08,03,usb,yes,35,39 2006.210.07:30:03.99/vblo/01,632.99,yes,locked 2006.210.07:30:03.99/vblo/02,640.99,yes,locked 2006.210.07:30:03.99/vblo/03,656.99,yes,locked 2006.210.07:30:03.99/vblo/04,712.99,yes,locked 2006.210.07:30:03.99/vblo/05,744.99,yes,locked 2006.210.07:30:03.99/vblo/06,752.99,yes,locked 2006.210.07:30:03.99/vblo/07,734.99,yes,locked 2006.210.07:30:03.99/vblo/08,744.99,yes,locked 2006.210.07:30:04.14/vabw/8 2006.210.07:30:04.29/vbbw/8 2006.210.07:30:04.39/xfe/off,on,12.0 2006.210.07:30:04.78/ifatt/23,28,28,28 2006.210.07:30:04.78&clockoff/"gps-fmout=1p 2006.210.07:30:04.78&clockoff/fmout-gps=1p 2006.210.07:30:05.04/fmout-gps/S +4.61E-07 2006.210.07:30:05.12:!2006.210.07:31:00 2006.210.07:31:00.00:data_valid=off 2006.210.07:31:00.00:postob 2006.210.07:31:00.00&postob/cable 2006.210.07:31:00.01&postob/wx 2006.210.07:31:00.01&postob/clockoff 2006.210.07:31:00.21/cable/+6.4223E-03 2006.210.07:31:00.21/wx/27.72,1006.2,90 2006.210.07:31:00.28/fmout-gps/S +4.62E-07 2006.210.07:31:00.29:scan_name=210-0733,k06210,60 2006.210.07:31:00.29:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.210.07:31:01.14#flagr#flagr/antenna,new-source 2006.210.07:31:01.14:checkk5 2006.210.07:31:01.14&checkk5/chk_autoobs=1 2006.210.07:31:01.15&checkk5/chk_autoobs=2 2006.210.07:31:01.15&checkk5/chk_autoobs=3 2006.210.07:31:01.15&checkk5/chk_autoobs=4 2006.210.07:31:01.16&checkk5/chk_obsdata=1 2006.210.07:31:01.16&checkk5/chk_obsdata=2 2006.210.07:31:01.16&checkk5/chk_obsdata=3 2006.210.07:31:01.17&checkk5/chk_obsdata=4 2006.210.07:31:01.17&checkk5/k5log=1 2006.210.07:31:01.17&checkk5/k5log=2 2006.210.07:31:01.18&checkk5/k5log=3 2006.210.07:31:01.21&checkk5/k5log=4 2006.210.07:31:01.21&checkk5/obsinfo 2006.210.07:31:01.62/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:31:02.24/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:31:02.66/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:31:03.08/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:31:03.49/chk_obsdata//k5ts1/T2100730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:03.89/chk_obsdata//k5ts2/T2100730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:04.32/chk_obsdata//k5ts3/T2100730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:04.72/chk_obsdata//k5ts4/T2100730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:05.95/k5log//k5ts1_log_newline 2006.210.07:31:06.82/k5log//k5ts2_log_newline 2006.210.07:31:07.57/k5log//k5ts3_log_newline 2006.210.07:31:08.32/k5log//k5ts4_log_newline 2006.210.07:31:08.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:31:08.34:4f8m12a=1 2006.210.07:31:08.34$4f8m12a/echo=on 2006.210.07:31:08.34$4f8m12a/pcalon 2006.210.07:31:08.34$pcalon/"no phase cal control is implemented here 2006.210.07:31:08.34$4f8m12a/"tpicd=stop 2006.210.07:31:08.34$4f8m12a/vc4f8 2006.210.07:31:08.34$vc4f8/valo=1,532.99 2006.210.07:31:08.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.07:31:08.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.07:31:08.35#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:08.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:08.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:08.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:08.35#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:31:08.35#ibcon#first serial, iclass 33, count 0 2006.210.07:31:08.35#ibcon#enter sib2, iclass 33, count 0 2006.210.07:31:08.35#ibcon#flushed, iclass 33, count 0 2006.210.07:31:08.35#ibcon#about to write, iclass 33, count 0 2006.210.07:31:08.35#ibcon#wrote, iclass 33, count 0 2006.210.07:31:08.35#ibcon#about to read 3, iclass 33, count 0 2006.210.07:31:08.39#ibcon#read 3, iclass 33, count 0 2006.210.07:31:08.39#ibcon#about to read 4, iclass 33, count 0 2006.210.07:31:08.39#ibcon#read 4, iclass 33, count 0 2006.210.07:31:08.39#ibcon#about to read 5, iclass 33, count 0 2006.210.07:31:08.39#ibcon#read 5, iclass 33, count 0 2006.210.07:31:08.39#ibcon#about to read 6, iclass 33, count 0 2006.210.07:31:08.39#ibcon#read 6, iclass 33, count 0 2006.210.07:31:08.39#ibcon#end of sib2, iclass 33, count 0 2006.210.07:31:08.39#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:31:08.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:31:08.39#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:31:08.39#ibcon#*before write, iclass 33, count 0 2006.210.07:31:08.39#ibcon#enter sib2, iclass 33, count 0 2006.210.07:31:08.39#ibcon#flushed, iclass 33, count 0 2006.210.07:31:08.39#ibcon#about to write, iclass 33, count 0 2006.210.07:31:08.39#ibcon#wrote, iclass 33, count 0 2006.210.07:31:08.39#ibcon#about to read 3, iclass 33, count 0 2006.210.07:31:08.44#ibcon#read 3, iclass 33, count 0 2006.210.07:31:08.44#ibcon#about to read 4, iclass 33, count 0 2006.210.07:31:08.44#ibcon#read 4, iclass 33, count 0 2006.210.07:31:08.44#ibcon#about to read 5, iclass 33, count 0 2006.210.07:31:08.44#ibcon#read 5, iclass 33, count 0 2006.210.07:31:08.44#ibcon#about to read 6, iclass 33, count 0 2006.210.07:31:08.44#ibcon#read 6, iclass 33, count 0 2006.210.07:31:08.44#ibcon#end of sib2, iclass 33, count 0 2006.210.07:31:08.44#ibcon#*after write, iclass 33, count 0 2006.210.07:31:08.44#ibcon#*before return 0, iclass 33, count 0 2006.210.07:31:08.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:08.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:08.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:31:08.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:31:08.44$vc4f8/va=1,8 2006.210.07:31:08.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.07:31:08.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.07:31:08.44#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:08.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:08.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:08.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:08.44#ibcon#enter wrdev, iclass 35, count 2 2006.210.07:31:08.44#ibcon#first serial, iclass 35, count 2 2006.210.07:31:08.44#ibcon#enter sib2, iclass 35, count 2 2006.210.07:31:08.44#ibcon#flushed, iclass 35, count 2 2006.210.07:31:08.44#ibcon#about to write, iclass 35, count 2 2006.210.07:31:08.44#ibcon#wrote, iclass 35, count 2 2006.210.07:31:08.44#ibcon#about to read 3, iclass 35, count 2 2006.210.07:31:08.46#ibcon#read 3, iclass 35, count 2 2006.210.07:31:08.46#ibcon#about to read 4, iclass 35, count 2 2006.210.07:31:08.46#ibcon#read 4, iclass 35, count 2 2006.210.07:31:08.46#ibcon#about to read 5, iclass 35, count 2 2006.210.07:31:08.46#ibcon#read 5, iclass 35, count 2 2006.210.07:31:08.46#ibcon#about to read 6, iclass 35, count 2 2006.210.07:31:08.46#ibcon#read 6, iclass 35, count 2 2006.210.07:31:08.46#ibcon#end of sib2, iclass 35, count 2 2006.210.07:31:08.46#ibcon#*mode == 0, iclass 35, count 2 2006.210.07:31:08.46#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.07:31:08.46#ibcon#[25=AT01-08\r\n] 2006.210.07:31:08.46#ibcon#*before write, iclass 35, count 2 2006.210.07:31:08.46#ibcon#enter sib2, iclass 35, count 2 2006.210.07:31:08.46#ibcon#flushed, iclass 35, count 2 2006.210.07:31:08.46#ibcon#about to write, iclass 35, count 2 2006.210.07:31:08.46#ibcon#wrote, iclass 35, count 2 2006.210.07:31:08.46#ibcon#about to read 3, iclass 35, count 2 2006.210.07:31:08.49#ibcon#read 3, iclass 35, count 2 2006.210.07:31:08.49#ibcon#about to read 4, iclass 35, count 2 2006.210.07:31:08.49#ibcon#read 4, iclass 35, count 2 2006.210.07:31:08.49#ibcon#about to read 5, iclass 35, count 2 2006.210.07:31:08.49#ibcon#read 5, iclass 35, count 2 2006.210.07:31:08.49#ibcon#about to read 6, iclass 35, count 2 2006.210.07:31:08.49#ibcon#read 6, iclass 35, count 2 2006.210.07:31:08.49#ibcon#end of sib2, iclass 35, count 2 2006.210.07:31:08.49#ibcon#*after write, iclass 35, count 2 2006.210.07:31:08.49#ibcon#*before return 0, iclass 35, count 2 2006.210.07:31:08.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:08.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:08.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.07:31:08.49#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:08.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:08.61#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:08.61#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:08.61#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:31:08.61#ibcon#first serial, iclass 35, count 0 2006.210.07:31:08.61#ibcon#enter sib2, iclass 35, count 0 2006.210.07:31:08.61#ibcon#flushed, iclass 35, count 0 2006.210.07:31:08.61#ibcon#about to write, iclass 35, count 0 2006.210.07:31:08.61#ibcon#wrote, iclass 35, count 0 2006.210.07:31:08.61#ibcon#about to read 3, iclass 35, count 0 2006.210.07:31:08.63#ibcon#read 3, iclass 35, count 0 2006.210.07:31:08.63#ibcon#about to read 4, iclass 35, count 0 2006.210.07:31:08.63#ibcon#read 4, iclass 35, count 0 2006.210.07:31:08.63#ibcon#about to read 5, iclass 35, count 0 2006.210.07:31:08.63#ibcon#read 5, iclass 35, count 0 2006.210.07:31:08.63#ibcon#about to read 6, iclass 35, count 0 2006.210.07:31:08.63#ibcon#read 6, iclass 35, count 0 2006.210.07:31:08.63#ibcon#end of sib2, iclass 35, count 0 2006.210.07:31:08.63#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:31:08.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:31:08.63#ibcon#[25=USB\r\n] 2006.210.07:31:08.63#ibcon#*before write, iclass 35, count 0 2006.210.07:31:08.63#ibcon#enter sib2, iclass 35, count 0 2006.210.07:31:08.63#ibcon#flushed, iclass 35, count 0 2006.210.07:31:08.63#ibcon#about to write, iclass 35, count 0 2006.210.07:31:08.63#ibcon#wrote, iclass 35, count 0 2006.210.07:31:08.63#ibcon#about to read 3, iclass 35, count 0 2006.210.07:31:08.66#ibcon#read 3, iclass 35, count 0 2006.210.07:31:08.66#ibcon#about to read 4, iclass 35, count 0 2006.210.07:31:08.66#ibcon#read 4, iclass 35, count 0 2006.210.07:31:08.66#ibcon#about to read 5, iclass 35, count 0 2006.210.07:31:08.66#ibcon#read 5, iclass 35, count 0 2006.210.07:31:08.66#ibcon#about to read 6, iclass 35, count 0 2006.210.07:31:08.66#ibcon#read 6, iclass 35, count 0 2006.210.07:31:08.66#ibcon#end of sib2, iclass 35, count 0 2006.210.07:31:08.66#ibcon#*after write, iclass 35, count 0 2006.210.07:31:08.66#ibcon#*before return 0, iclass 35, count 0 2006.210.07:31:08.66#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:08.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:08.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:31:08.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:31:08.66$vc4f8/valo=2,572.99 2006.210.07:31:08.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:31:08.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:31:08.66#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:08.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:08.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:08.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:08.66#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:31:08.66#ibcon#first serial, iclass 37, count 0 2006.210.07:31:08.66#ibcon#enter sib2, iclass 37, count 0 2006.210.07:31:08.66#ibcon#flushed, iclass 37, count 0 2006.210.07:31:08.66#ibcon#about to write, iclass 37, count 0 2006.210.07:31:08.66#ibcon#wrote, iclass 37, count 0 2006.210.07:31:08.66#ibcon#about to read 3, iclass 37, count 0 2006.210.07:31:08.68#ibcon#read 3, iclass 37, count 0 2006.210.07:31:08.68#ibcon#about to read 4, iclass 37, count 0 2006.210.07:31:08.68#ibcon#read 4, iclass 37, count 0 2006.210.07:31:08.68#ibcon#about to read 5, iclass 37, count 0 2006.210.07:31:08.68#ibcon#read 5, iclass 37, count 0 2006.210.07:31:08.68#ibcon#about to read 6, iclass 37, count 0 2006.210.07:31:08.68#ibcon#read 6, iclass 37, count 0 2006.210.07:31:08.68#ibcon#end of sib2, iclass 37, count 0 2006.210.07:31:08.68#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:31:08.68#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:31:08.68#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:31:08.68#ibcon#*before write, iclass 37, count 0 2006.210.07:31:08.68#ibcon#enter sib2, iclass 37, count 0 2006.210.07:31:08.68#ibcon#flushed, iclass 37, count 0 2006.210.07:31:08.68#ibcon#about to write, iclass 37, count 0 2006.210.07:31:08.68#ibcon#wrote, iclass 37, count 0 2006.210.07:31:08.68#ibcon#about to read 3, iclass 37, count 0 2006.210.07:31:08.72#ibcon#read 3, iclass 37, count 0 2006.210.07:31:08.72#ibcon#about to read 4, iclass 37, count 0 2006.210.07:31:08.72#ibcon#read 4, iclass 37, count 0 2006.210.07:31:08.72#ibcon#about to read 5, iclass 37, count 0 2006.210.07:31:08.72#ibcon#read 5, iclass 37, count 0 2006.210.07:31:08.72#ibcon#about to read 6, iclass 37, count 0 2006.210.07:31:08.72#ibcon#read 6, iclass 37, count 0 2006.210.07:31:08.72#ibcon#end of sib2, iclass 37, count 0 2006.210.07:31:08.72#ibcon#*after write, iclass 37, count 0 2006.210.07:31:08.72#ibcon#*before return 0, iclass 37, count 0 2006.210.07:31:08.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:08.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:08.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:31:08.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:31:08.72$vc4f8/va=2,7 2006.210.07:31:08.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:31:08.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:31:08.72#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:08.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:08.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:08.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:08.78#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:31:08.78#ibcon#first serial, iclass 39, count 2 2006.210.07:31:08.78#ibcon#enter sib2, iclass 39, count 2 2006.210.07:31:08.78#ibcon#flushed, iclass 39, count 2 2006.210.07:31:08.78#ibcon#about to write, iclass 39, count 2 2006.210.07:31:08.78#ibcon#wrote, iclass 39, count 2 2006.210.07:31:08.78#ibcon#about to read 3, iclass 39, count 2 2006.210.07:31:08.80#ibcon#read 3, iclass 39, count 2 2006.210.07:31:08.80#ibcon#about to read 4, iclass 39, count 2 2006.210.07:31:08.80#ibcon#read 4, iclass 39, count 2 2006.210.07:31:08.80#ibcon#about to read 5, iclass 39, count 2 2006.210.07:31:08.80#ibcon#read 5, iclass 39, count 2 2006.210.07:31:08.80#ibcon#about to read 6, iclass 39, count 2 2006.210.07:31:08.80#ibcon#read 6, iclass 39, count 2 2006.210.07:31:08.80#ibcon#end of sib2, iclass 39, count 2 2006.210.07:31:08.80#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:31:08.80#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:31:08.80#ibcon#[25=AT02-07\r\n] 2006.210.07:31:08.80#ibcon#*before write, iclass 39, count 2 2006.210.07:31:08.80#ibcon#enter sib2, iclass 39, count 2 2006.210.07:31:08.80#ibcon#flushed, iclass 39, count 2 2006.210.07:31:08.80#ibcon#about to write, iclass 39, count 2 2006.210.07:31:08.80#ibcon#wrote, iclass 39, count 2 2006.210.07:31:08.80#ibcon#about to read 3, iclass 39, count 2 2006.210.07:31:08.83#ibcon#read 3, iclass 39, count 2 2006.210.07:31:08.83#ibcon#about to read 4, iclass 39, count 2 2006.210.07:31:08.83#ibcon#read 4, iclass 39, count 2 2006.210.07:31:08.83#ibcon#about to read 5, iclass 39, count 2 2006.210.07:31:08.83#ibcon#read 5, iclass 39, count 2 2006.210.07:31:08.83#ibcon#about to read 6, iclass 39, count 2 2006.210.07:31:08.83#ibcon#read 6, iclass 39, count 2 2006.210.07:31:08.83#ibcon#end of sib2, iclass 39, count 2 2006.210.07:31:08.83#ibcon#*after write, iclass 39, count 2 2006.210.07:31:08.83#ibcon#*before return 0, iclass 39, count 2 2006.210.07:31:08.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:08.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:08.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:31:08.83#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:08.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:08.95#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:08.95#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:08.95#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:31:08.95#ibcon#first serial, iclass 39, count 0 2006.210.07:31:08.95#ibcon#enter sib2, iclass 39, count 0 2006.210.07:31:08.95#ibcon#flushed, iclass 39, count 0 2006.210.07:31:08.95#ibcon#about to write, iclass 39, count 0 2006.210.07:31:08.95#ibcon#wrote, iclass 39, count 0 2006.210.07:31:08.95#ibcon#about to read 3, iclass 39, count 0 2006.210.07:31:08.97#ibcon#read 3, iclass 39, count 0 2006.210.07:31:08.97#ibcon#about to read 4, iclass 39, count 0 2006.210.07:31:08.97#ibcon#read 4, iclass 39, count 0 2006.210.07:31:08.97#ibcon#about to read 5, iclass 39, count 0 2006.210.07:31:08.97#ibcon#read 5, iclass 39, count 0 2006.210.07:31:08.97#ibcon#about to read 6, iclass 39, count 0 2006.210.07:31:08.97#ibcon#read 6, iclass 39, count 0 2006.210.07:31:08.97#ibcon#end of sib2, iclass 39, count 0 2006.210.07:31:08.97#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:31:08.97#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:31:08.97#ibcon#[25=USB\r\n] 2006.210.07:31:08.97#ibcon#*before write, iclass 39, count 0 2006.210.07:31:08.97#ibcon#enter sib2, iclass 39, count 0 2006.210.07:31:08.97#ibcon#flushed, iclass 39, count 0 2006.210.07:31:08.97#ibcon#about to write, iclass 39, count 0 2006.210.07:31:08.97#ibcon#wrote, iclass 39, count 0 2006.210.07:31:08.97#ibcon#about to read 3, iclass 39, count 0 2006.210.07:31:09.00#ibcon#read 3, iclass 39, count 0 2006.210.07:31:09.00#ibcon#about to read 4, iclass 39, count 0 2006.210.07:31:09.00#ibcon#read 4, iclass 39, count 0 2006.210.07:31:09.00#ibcon#about to read 5, iclass 39, count 0 2006.210.07:31:09.00#ibcon#read 5, iclass 39, count 0 2006.210.07:31:09.00#ibcon#about to read 6, iclass 39, count 0 2006.210.07:31:09.00#ibcon#read 6, iclass 39, count 0 2006.210.07:31:09.00#ibcon#end of sib2, iclass 39, count 0 2006.210.07:31:09.00#ibcon#*after write, iclass 39, count 0 2006.210.07:31:09.00#ibcon#*before return 0, iclass 39, count 0 2006.210.07:31:09.00#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:09.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:09.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:31:09.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:31:09.00$vc4f8/valo=3,672.99 2006.210.07:31:09.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:31:09.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:31:09.00#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:09.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:09.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:09.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:09.00#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:31:09.00#ibcon#first serial, iclass 3, count 0 2006.210.07:31:09.00#ibcon#enter sib2, iclass 3, count 0 2006.210.07:31:09.00#ibcon#flushed, iclass 3, count 0 2006.210.07:31:09.00#ibcon#about to write, iclass 3, count 0 2006.210.07:31:09.00#ibcon#wrote, iclass 3, count 0 2006.210.07:31:09.00#ibcon#about to read 3, iclass 3, count 0 2006.210.07:31:09.02#ibcon#read 3, iclass 3, count 0 2006.210.07:31:09.02#ibcon#about to read 4, iclass 3, count 0 2006.210.07:31:09.02#ibcon#read 4, iclass 3, count 0 2006.210.07:31:09.02#ibcon#about to read 5, iclass 3, count 0 2006.210.07:31:09.02#ibcon#read 5, iclass 3, count 0 2006.210.07:31:09.02#ibcon#about to read 6, iclass 3, count 0 2006.210.07:31:09.02#ibcon#read 6, iclass 3, count 0 2006.210.07:31:09.02#ibcon#end of sib2, iclass 3, count 0 2006.210.07:31:09.02#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:31:09.02#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:31:09.02#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:31:09.02#ibcon#*before write, iclass 3, count 0 2006.210.07:31:09.02#ibcon#enter sib2, iclass 3, count 0 2006.210.07:31:09.02#ibcon#flushed, iclass 3, count 0 2006.210.07:31:09.02#ibcon#about to write, iclass 3, count 0 2006.210.07:31:09.02#ibcon#wrote, iclass 3, count 0 2006.210.07:31:09.02#ibcon#about to read 3, iclass 3, count 0 2006.210.07:31:09.06#ibcon#read 3, iclass 3, count 0 2006.210.07:31:09.06#ibcon#about to read 4, iclass 3, count 0 2006.210.07:31:09.06#ibcon#read 4, iclass 3, count 0 2006.210.07:31:09.06#ibcon#about to read 5, iclass 3, count 0 2006.210.07:31:09.06#ibcon#read 5, iclass 3, count 0 2006.210.07:31:09.06#ibcon#about to read 6, iclass 3, count 0 2006.210.07:31:09.06#ibcon#read 6, iclass 3, count 0 2006.210.07:31:09.06#ibcon#end of sib2, iclass 3, count 0 2006.210.07:31:09.06#ibcon#*after write, iclass 3, count 0 2006.210.07:31:09.06#ibcon#*before return 0, iclass 3, count 0 2006.210.07:31:09.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:09.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:09.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:31:09.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:31:09.06$vc4f8/va=3,6 2006.210.07:31:09.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:31:09.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:31:09.06#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:09.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:09.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:09.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:09.12#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:31:09.12#ibcon#first serial, iclass 5, count 2 2006.210.07:31:09.12#ibcon#enter sib2, iclass 5, count 2 2006.210.07:31:09.12#ibcon#flushed, iclass 5, count 2 2006.210.07:31:09.12#ibcon#about to write, iclass 5, count 2 2006.210.07:31:09.12#ibcon#wrote, iclass 5, count 2 2006.210.07:31:09.12#ibcon#about to read 3, iclass 5, count 2 2006.210.07:31:09.14#ibcon#read 3, iclass 5, count 2 2006.210.07:31:09.14#ibcon#about to read 4, iclass 5, count 2 2006.210.07:31:09.14#ibcon#read 4, iclass 5, count 2 2006.210.07:31:09.14#ibcon#about to read 5, iclass 5, count 2 2006.210.07:31:09.14#ibcon#read 5, iclass 5, count 2 2006.210.07:31:09.14#ibcon#about to read 6, iclass 5, count 2 2006.210.07:31:09.14#ibcon#read 6, iclass 5, count 2 2006.210.07:31:09.14#ibcon#end of sib2, iclass 5, count 2 2006.210.07:31:09.14#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:31:09.14#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:31:09.14#ibcon#[25=AT03-06\r\n] 2006.210.07:31:09.14#ibcon#*before write, iclass 5, count 2 2006.210.07:31:09.14#ibcon#enter sib2, iclass 5, count 2 2006.210.07:31:09.14#ibcon#flushed, iclass 5, count 2 2006.210.07:31:09.14#ibcon#about to write, iclass 5, count 2 2006.210.07:31:09.14#ibcon#wrote, iclass 5, count 2 2006.210.07:31:09.14#ibcon#about to read 3, iclass 5, count 2 2006.210.07:31:09.17#ibcon#read 3, iclass 5, count 2 2006.210.07:31:09.17#ibcon#about to read 4, iclass 5, count 2 2006.210.07:31:09.17#ibcon#read 4, iclass 5, count 2 2006.210.07:31:09.17#ibcon#about to read 5, iclass 5, count 2 2006.210.07:31:09.17#ibcon#read 5, iclass 5, count 2 2006.210.07:31:09.17#ibcon#about to read 6, iclass 5, count 2 2006.210.07:31:09.17#ibcon#read 6, iclass 5, count 2 2006.210.07:31:09.17#ibcon#end of sib2, iclass 5, count 2 2006.210.07:31:09.17#ibcon#*after write, iclass 5, count 2 2006.210.07:31:09.17#ibcon#*before return 0, iclass 5, count 2 2006.210.07:31:09.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:09.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:09.17#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:31:09.17#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:09.17#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:09.29#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:09.29#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:09.29#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:31:09.29#ibcon#first serial, iclass 5, count 0 2006.210.07:31:09.29#ibcon#enter sib2, iclass 5, count 0 2006.210.07:31:09.29#ibcon#flushed, iclass 5, count 0 2006.210.07:31:09.29#ibcon#about to write, iclass 5, count 0 2006.210.07:31:09.29#ibcon#wrote, iclass 5, count 0 2006.210.07:31:09.29#ibcon#about to read 3, iclass 5, count 0 2006.210.07:31:09.31#ibcon#read 3, iclass 5, count 0 2006.210.07:31:09.31#ibcon#about to read 4, iclass 5, count 0 2006.210.07:31:09.31#ibcon#read 4, iclass 5, count 0 2006.210.07:31:09.31#ibcon#about to read 5, iclass 5, count 0 2006.210.07:31:09.31#ibcon#read 5, iclass 5, count 0 2006.210.07:31:09.31#ibcon#about to read 6, iclass 5, count 0 2006.210.07:31:09.31#ibcon#read 6, iclass 5, count 0 2006.210.07:31:09.31#ibcon#end of sib2, iclass 5, count 0 2006.210.07:31:09.31#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:31:09.31#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:31:09.31#ibcon#[25=USB\r\n] 2006.210.07:31:09.31#ibcon#*before write, iclass 5, count 0 2006.210.07:31:09.31#ibcon#enter sib2, iclass 5, count 0 2006.210.07:31:09.31#ibcon#flushed, iclass 5, count 0 2006.210.07:31:09.31#ibcon#about to write, iclass 5, count 0 2006.210.07:31:09.31#ibcon#wrote, iclass 5, count 0 2006.210.07:31:09.31#ibcon#about to read 3, iclass 5, count 0 2006.210.07:31:09.34#ibcon#read 3, iclass 5, count 0 2006.210.07:31:09.34#ibcon#about to read 4, iclass 5, count 0 2006.210.07:31:09.34#ibcon#read 4, iclass 5, count 0 2006.210.07:31:09.34#ibcon#about to read 5, iclass 5, count 0 2006.210.07:31:09.34#ibcon#read 5, iclass 5, count 0 2006.210.07:31:09.34#ibcon#about to read 6, iclass 5, count 0 2006.210.07:31:09.34#ibcon#read 6, iclass 5, count 0 2006.210.07:31:09.34#ibcon#end of sib2, iclass 5, count 0 2006.210.07:31:09.34#ibcon#*after write, iclass 5, count 0 2006.210.07:31:09.34#ibcon#*before return 0, iclass 5, count 0 2006.210.07:31:09.34#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:09.34#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:09.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:31:09.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:31:09.34$vc4f8/valo=4,832.99 2006.210.07:31:09.34#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:31:09.34#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:31:09.34#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:09.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:09.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:09.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:09.34#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:31:09.34#ibcon#first serial, iclass 7, count 0 2006.210.07:31:09.34#ibcon#enter sib2, iclass 7, count 0 2006.210.07:31:09.34#ibcon#flushed, iclass 7, count 0 2006.210.07:31:09.34#ibcon#about to write, iclass 7, count 0 2006.210.07:31:09.34#ibcon#wrote, iclass 7, count 0 2006.210.07:31:09.34#ibcon#about to read 3, iclass 7, count 0 2006.210.07:31:09.36#ibcon#read 3, iclass 7, count 0 2006.210.07:31:09.36#ibcon#about to read 4, iclass 7, count 0 2006.210.07:31:09.36#ibcon#read 4, iclass 7, count 0 2006.210.07:31:09.36#ibcon#about to read 5, iclass 7, count 0 2006.210.07:31:09.36#ibcon#read 5, iclass 7, count 0 2006.210.07:31:09.36#ibcon#about to read 6, iclass 7, count 0 2006.210.07:31:09.36#ibcon#read 6, iclass 7, count 0 2006.210.07:31:09.36#ibcon#end of sib2, iclass 7, count 0 2006.210.07:31:09.36#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:31:09.36#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:31:09.36#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:31:09.36#ibcon#*before write, iclass 7, count 0 2006.210.07:31:09.36#ibcon#enter sib2, iclass 7, count 0 2006.210.07:31:09.36#ibcon#flushed, iclass 7, count 0 2006.210.07:31:09.36#ibcon#about to write, iclass 7, count 0 2006.210.07:31:09.36#ibcon#wrote, iclass 7, count 0 2006.210.07:31:09.36#ibcon#about to read 3, iclass 7, count 0 2006.210.07:31:09.40#ibcon#read 3, iclass 7, count 0 2006.210.07:31:09.40#ibcon#about to read 4, iclass 7, count 0 2006.210.07:31:09.40#ibcon#read 4, iclass 7, count 0 2006.210.07:31:09.40#ibcon#about to read 5, iclass 7, count 0 2006.210.07:31:09.40#ibcon#read 5, iclass 7, count 0 2006.210.07:31:09.40#ibcon#about to read 6, iclass 7, count 0 2006.210.07:31:09.40#ibcon#read 6, iclass 7, count 0 2006.210.07:31:09.40#ibcon#end of sib2, iclass 7, count 0 2006.210.07:31:09.40#ibcon#*after write, iclass 7, count 0 2006.210.07:31:09.40#ibcon#*before return 0, iclass 7, count 0 2006.210.07:31:09.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:09.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:09.40#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:31:09.40#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:31:09.40$vc4f8/va=4,7 2006.210.07:31:09.40#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:31:09.40#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:31:09.40#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:09.40#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:09.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:09.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:09.46#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:31:09.46#ibcon#first serial, iclass 11, count 2 2006.210.07:31:09.46#ibcon#enter sib2, iclass 11, count 2 2006.210.07:31:09.46#ibcon#flushed, iclass 11, count 2 2006.210.07:31:09.46#ibcon#about to write, iclass 11, count 2 2006.210.07:31:09.46#ibcon#wrote, iclass 11, count 2 2006.210.07:31:09.46#ibcon#about to read 3, iclass 11, count 2 2006.210.07:31:09.48#ibcon#read 3, iclass 11, count 2 2006.210.07:31:09.48#ibcon#about to read 4, iclass 11, count 2 2006.210.07:31:09.48#ibcon#read 4, iclass 11, count 2 2006.210.07:31:09.48#ibcon#about to read 5, iclass 11, count 2 2006.210.07:31:09.48#ibcon#read 5, iclass 11, count 2 2006.210.07:31:09.48#ibcon#about to read 6, iclass 11, count 2 2006.210.07:31:09.48#ibcon#read 6, iclass 11, count 2 2006.210.07:31:09.48#ibcon#end of sib2, iclass 11, count 2 2006.210.07:31:09.48#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:31:09.48#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:31:09.48#ibcon#[25=AT04-07\r\n] 2006.210.07:31:09.48#ibcon#*before write, iclass 11, count 2 2006.210.07:31:09.48#ibcon#enter sib2, iclass 11, count 2 2006.210.07:31:09.48#ibcon#flushed, iclass 11, count 2 2006.210.07:31:09.48#ibcon#about to write, iclass 11, count 2 2006.210.07:31:09.48#ibcon#wrote, iclass 11, count 2 2006.210.07:31:09.48#ibcon#about to read 3, iclass 11, count 2 2006.210.07:31:09.51#ibcon#read 3, iclass 11, count 2 2006.210.07:31:09.51#ibcon#about to read 4, iclass 11, count 2 2006.210.07:31:09.51#ibcon#read 4, iclass 11, count 2 2006.210.07:31:09.51#ibcon#about to read 5, iclass 11, count 2 2006.210.07:31:09.51#ibcon#read 5, iclass 11, count 2 2006.210.07:31:09.51#ibcon#about to read 6, iclass 11, count 2 2006.210.07:31:09.51#ibcon#read 6, iclass 11, count 2 2006.210.07:31:09.51#ibcon#end of sib2, iclass 11, count 2 2006.210.07:31:09.51#ibcon#*after write, iclass 11, count 2 2006.210.07:31:09.51#ibcon#*before return 0, iclass 11, count 2 2006.210.07:31:09.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:09.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:09.51#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:31:09.51#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:09.51#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:09.63#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:09.63#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:09.63#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:31:09.63#ibcon#first serial, iclass 11, count 0 2006.210.07:31:09.63#ibcon#enter sib2, iclass 11, count 0 2006.210.07:31:09.63#ibcon#flushed, iclass 11, count 0 2006.210.07:31:09.63#ibcon#about to write, iclass 11, count 0 2006.210.07:31:09.63#ibcon#wrote, iclass 11, count 0 2006.210.07:31:09.63#ibcon#about to read 3, iclass 11, count 0 2006.210.07:31:09.65#ibcon#read 3, iclass 11, count 0 2006.210.07:31:09.65#ibcon#about to read 4, iclass 11, count 0 2006.210.07:31:09.65#ibcon#read 4, iclass 11, count 0 2006.210.07:31:09.65#ibcon#about to read 5, iclass 11, count 0 2006.210.07:31:09.65#ibcon#read 5, iclass 11, count 0 2006.210.07:31:09.65#ibcon#about to read 6, iclass 11, count 0 2006.210.07:31:09.65#ibcon#read 6, iclass 11, count 0 2006.210.07:31:09.65#ibcon#end of sib2, iclass 11, count 0 2006.210.07:31:09.65#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:31:09.65#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:31:09.65#ibcon#[25=USB\r\n] 2006.210.07:31:09.65#ibcon#*before write, iclass 11, count 0 2006.210.07:31:09.65#ibcon#enter sib2, iclass 11, count 0 2006.210.07:31:09.65#ibcon#flushed, iclass 11, count 0 2006.210.07:31:09.65#ibcon#about to write, iclass 11, count 0 2006.210.07:31:09.65#ibcon#wrote, iclass 11, count 0 2006.210.07:31:09.65#ibcon#about to read 3, iclass 11, count 0 2006.210.07:31:09.68#ibcon#read 3, iclass 11, count 0 2006.210.07:31:09.68#ibcon#about to read 4, iclass 11, count 0 2006.210.07:31:09.68#ibcon#read 4, iclass 11, count 0 2006.210.07:31:09.68#ibcon#about to read 5, iclass 11, count 0 2006.210.07:31:09.68#ibcon#read 5, iclass 11, count 0 2006.210.07:31:09.68#ibcon#about to read 6, iclass 11, count 0 2006.210.07:31:09.68#ibcon#read 6, iclass 11, count 0 2006.210.07:31:09.68#ibcon#end of sib2, iclass 11, count 0 2006.210.07:31:09.68#ibcon#*after write, iclass 11, count 0 2006.210.07:31:09.68#ibcon#*before return 0, iclass 11, count 0 2006.210.07:31:09.68#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:09.68#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:09.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:31:09.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:31:09.68$vc4f8/valo=5,652.99 2006.210.07:31:09.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:31:09.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:31:09.68#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:09.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:09.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:09.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:09.68#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:31:09.68#ibcon#first serial, iclass 13, count 0 2006.210.07:31:09.68#ibcon#enter sib2, iclass 13, count 0 2006.210.07:31:09.68#ibcon#flushed, iclass 13, count 0 2006.210.07:31:09.68#ibcon#about to write, iclass 13, count 0 2006.210.07:31:09.68#ibcon#wrote, iclass 13, count 0 2006.210.07:31:09.68#ibcon#about to read 3, iclass 13, count 0 2006.210.07:31:09.70#ibcon#read 3, iclass 13, count 0 2006.210.07:31:09.70#ibcon#about to read 4, iclass 13, count 0 2006.210.07:31:09.70#ibcon#read 4, iclass 13, count 0 2006.210.07:31:09.70#ibcon#about to read 5, iclass 13, count 0 2006.210.07:31:09.70#ibcon#read 5, iclass 13, count 0 2006.210.07:31:09.70#ibcon#about to read 6, iclass 13, count 0 2006.210.07:31:09.70#ibcon#read 6, iclass 13, count 0 2006.210.07:31:09.70#ibcon#end of sib2, iclass 13, count 0 2006.210.07:31:09.70#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:31:09.70#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:31:09.70#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:31:09.70#ibcon#*before write, iclass 13, count 0 2006.210.07:31:09.70#ibcon#enter sib2, iclass 13, count 0 2006.210.07:31:09.70#ibcon#flushed, iclass 13, count 0 2006.210.07:31:09.70#ibcon#about to write, iclass 13, count 0 2006.210.07:31:09.70#ibcon#wrote, iclass 13, count 0 2006.210.07:31:09.70#ibcon#about to read 3, iclass 13, count 0 2006.210.07:31:09.75#ibcon#read 3, iclass 13, count 0 2006.210.07:31:09.75#ibcon#about to read 4, iclass 13, count 0 2006.210.07:31:09.75#ibcon#read 4, iclass 13, count 0 2006.210.07:31:09.75#ibcon#about to read 5, iclass 13, count 0 2006.210.07:31:09.75#ibcon#read 5, iclass 13, count 0 2006.210.07:31:09.75#ibcon#about to read 6, iclass 13, count 0 2006.210.07:31:09.75#ibcon#read 6, iclass 13, count 0 2006.210.07:31:09.75#ibcon#end of sib2, iclass 13, count 0 2006.210.07:31:09.75#ibcon#*after write, iclass 13, count 0 2006.210.07:31:09.75#ibcon#*before return 0, iclass 13, count 0 2006.210.07:31:09.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:09.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:09.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:31:09.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:31:09.75$vc4f8/va=5,7 2006.210.07:31:09.75#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:31:09.75#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:31:09.75#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:09.75#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:09.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:09.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:09.80#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:31:09.80#ibcon#first serial, iclass 15, count 2 2006.210.07:31:09.80#ibcon#enter sib2, iclass 15, count 2 2006.210.07:31:09.80#ibcon#flushed, iclass 15, count 2 2006.210.07:31:09.80#ibcon#about to write, iclass 15, count 2 2006.210.07:31:09.80#ibcon#wrote, iclass 15, count 2 2006.210.07:31:09.80#ibcon#about to read 3, iclass 15, count 2 2006.210.07:31:09.82#ibcon#read 3, iclass 15, count 2 2006.210.07:31:09.82#ibcon#about to read 4, iclass 15, count 2 2006.210.07:31:09.82#ibcon#read 4, iclass 15, count 2 2006.210.07:31:09.82#ibcon#about to read 5, iclass 15, count 2 2006.210.07:31:09.82#ibcon#read 5, iclass 15, count 2 2006.210.07:31:09.82#ibcon#about to read 6, iclass 15, count 2 2006.210.07:31:09.82#ibcon#read 6, iclass 15, count 2 2006.210.07:31:09.82#ibcon#end of sib2, iclass 15, count 2 2006.210.07:31:09.82#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:31:09.82#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:31:09.82#ibcon#[25=AT05-07\r\n] 2006.210.07:31:09.82#ibcon#*before write, iclass 15, count 2 2006.210.07:31:09.82#ibcon#enter sib2, iclass 15, count 2 2006.210.07:31:09.82#ibcon#flushed, iclass 15, count 2 2006.210.07:31:09.82#ibcon#about to write, iclass 15, count 2 2006.210.07:31:09.82#ibcon#wrote, iclass 15, count 2 2006.210.07:31:09.82#ibcon#about to read 3, iclass 15, count 2 2006.210.07:31:09.85#ibcon#read 3, iclass 15, count 2 2006.210.07:31:09.85#ibcon#about to read 4, iclass 15, count 2 2006.210.07:31:09.85#ibcon#read 4, iclass 15, count 2 2006.210.07:31:09.85#ibcon#about to read 5, iclass 15, count 2 2006.210.07:31:09.85#ibcon#read 5, iclass 15, count 2 2006.210.07:31:09.85#ibcon#about to read 6, iclass 15, count 2 2006.210.07:31:09.85#ibcon#read 6, iclass 15, count 2 2006.210.07:31:09.85#ibcon#end of sib2, iclass 15, count 2 2006.210.07:31:09.85#ibcon#*after write, iclass 15, count 2 2006.210.07:31:09.85#ibcon#*before return 0, iclass 15, count 2 2006.210.07:31:09.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:09.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:09.85#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:31:09.85#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:09.85#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:09.97#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:09.97#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:09.97#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:31:09.97#ibcon#first serial, iclass 15, count 0 2006.210.07:31:09.97#ibcon#enter sib2, iclass 15, count 0 2006.210.07:31:09.97#ibcon#flushed, iclass 15, count 0 2006.210.07:31:09.97#ibcon#about to write, iclass 15, count 0 2006.210.07:31:09.97#ibcon#wrote, iclass 15, count 0 2006.210.07:31:09.97#ibcon#about to read 3, iclass 15, count 0 2006.210.07:31:09.99#ibcon#read 3, iclass 15, count 0 2006.210.07:31:09.99#ibcon#about to read 4, iclass 15, count 0 2006.210.07:31:09.99#ibcon#read 4, iclass 15, count 0 2006.210.07:31:09.99#ibcon#about to read 5, iclass 15, count 0 2006.210.07:31:09.99#ibcon#read 5, iclass 15, count 0 2006.210.07:31:09.99#ibcon#about to read 6, iclass 15, count 0 2006.210.07:31:09.99#ibcon#read 6, iclass 15, count 0 2006.210.07:31:09.99#ibcon#end of sib2, iclass 15, count 0 2006.210.07:31:09.99#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:31:09.99#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:31:09.99#ibcon#[25=USB\r\n] 2006.210.07:31:09.99#ibcon#*before write, iclass 15, count 0 2006.210.07:31:09.99#ibcon#enter sib2, iclass 15, count 0 2006.210.07:31:09.99#ibcon#flushed, iclass 15, count 0 2006.210.07:31:09.99#ibcon#about to write, iclass 15, count 0 2006.210.07:31:09.99#ibcon#wrote, iclass 15, count 0 2006.210.07:31:09.99#ibcon#about to read 3, iclass 15, count 0 2006.210.07:31:10.02#ibcon#read 3, iclass 15, count 0 2006.210.07:31:10.02#ibcon#about to read 4, iclass 15, count 0 2006.210.07:31:10.02#ibcon#read 4, iclass 15, count 0 2006.210.07:31:10.02#ibcon#about to read 5, iclass 15, count 0 2006.210.07:31:10.02#ibcon#read 5, iclass 15, count 0 2006.210.07:31:10.02#ibcon#about to read 6, iclass 15, count 0 2006.210.07:31:10.02#ibcon#read 6, iclass 15, count 0 2006.210.07:31:10.02#ibcon#end of sib2, iclass 15, count 0 2006.210.07:31:10.02#ibcon#*after write, iclass 15, count 0 2006.210.07:31:10.02#ibcon#*before return 0, iclass 15, count 0 2006.210.07:31:10.02#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:10.02#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:10.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:31:10.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:31:10.02$vc4f8/valo=6,772.99 2006.210.07:31:10.02#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:31:10.02#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:31:10.02#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:10.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:10.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:10.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:10.02#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:31:10.02#ibcon#first serial, iclass 17, count 0 2006.210.07:31:10.02#ibcon#enter sib2, iclass 17, count 0 2006.210.07:31:10.02#ibcon#flushed, iclass 17, count 0 2006.210.07:31:10.02#ibcon#about to write, iclass 17, count 0 2006.210.07:31:10.02#ibcon#wrote, iclass 17, count 0 2006.210.07:31:10.02#ibcon#about to read 3, iclass 17, count 0 2006.210.07:31:10.04#ibcon#read 3, iclass 17, count 0 2006.210.07:31:10.04#ibcon#about to read 4, iclass 17, count 0 2006.210.07:31:10.04#ibcon#read 4, iclass 17, count 0 2006.210.07:31:10.04#ibcon#about to read 5, iclass 17, count 0 2006.210.07:31:10.04#ibcon#read 5, iclass 17, count 0 2006.210.07:31:10.04#ibcon#about to read 6, iclass 17, count 0 2006.210.07:31:10.04#ibcon#read 6, iclass 17, count 0 2006.210.07:31:10.04#ibcon#end of sib2, iclass 17, count 0 2006.210.07:31:10.04#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:31:10.04#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:31:10.04#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:31:10.04#ibcon#*before write, iclass 17, count 0 2006.210.07:31:10.04#ibcon#enter sib2, iclass 17, count 0 2006.210.07:31:10.04#ibcon#flushed, iclass 17, count 0 2006.210.07:31:10.04#ibcon#about to write, iclass 17, count 0 2006.210.07:31:10.04#ibcon#wrote, iclass 17, count 0 2006.210.07:31:10.04#ibcon#about to read 3, iclass 17, count 0 2006.210.07:31:10.08#ibcon#read 3, iclass 17, count 0 2006.210.07:31:10.08#ibcon#about to read 4, iclass 17, count 0 2006.210.07:31:10.08#ibcon#read 4, iclass 17, count 0 2006.210.07:31:10.08#ibcon#about to read 5, iclass 17, count 0 2006.210.07:31:10.08#ibcon#read 5, iclass 17, count 0 2006.210.07:31:10.08#ibcon#about to read 6, iclass 17, count 0 2006.210.07:31:10.08#ibcon#read 6, iclass 17, count 0 2006.210.07:31:10.08#ibcon#end of sib2, iclass 17, count 0 2006.210.07:31:10.08#ibcon#*after write, iclass 17, count 0 2006.210.07:31:10.08#ibcon#*before return 0, iclass 17, count 0 2006.210.07:31:10.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:10.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:10.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:31:10.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:31:10.08$vc4f8/va=6,6 2006.210.07:31:10.08#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:31:10.08#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:31:10.08#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:10.08#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:10.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:10.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:10.14#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:31:10.14#ibcon#first serial, iclass 19, count 2 2006.210.07:31:10.14#ibcon#enter sib2, iclass 19, count 2 2006.210.07:31:10.14#ibcon#flushed, iclass 19, count 2 2006.210.07:31:10.14#ibcon#about to write, iclass 19, count 2 2006.210.07:31:10.14#ibcon#wrote, iclass 19, count 2 2006.210.07:31:10.14#ibcon#about to read 3, iclass 19, count 2 2006.210.07:31:10.16#ibcon#read 3, iclass 19, count 2 2006.210.07:31:10.16#ibcon#about to read 4, iclass 19, count 2 2006.210.07:31:10.16#ibcon#read 4, iclass 19, count 2 2006.210.07:31:10.16#ibcon#about to read 5, iclass 19, count 2 2006.210.07:31:10.16#ibcon#read 5, iclass 19, count 2 2006.210.07:31:10.16#ibcon#about to read 6, iclass 19, count 2 2006.210.07:31:10.16#ibcon#read 6, iclass 19, count 2 2006.210.07:31:10.16#ibcon#end of sib2, iclass 19, count 2 2006.210.07:31:10.16#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:31:10.16#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:31:10.16#ibcon#[25=AT06-06\r\n] 2006.210.07:31:10.16#ibcon#*before write, iclass 19, count 2 2006.210.07:31:10.16#ibcon#enter sib2, iclass 19, count 2 2006.210.07:31:10.16#ibcon#flushed, iclass 19, count 2 2006.210.07:31:10.16#ibcon#about to write, iclass 19, count 2 2006.210.07:31:10.16#ibcon#wrote, iclass 19, count 2 2006.210.07:31:10.16#ibcon#about to read 3, iclass 19, count 2 2006.210.07:31:10.19#ibcon#read 3, iclass 19, count 2 2006.210.07:31:10.19#ibcon#about to read 4, iclass 19, count 2 2006.210.07:31:10.19#ibcon#read 4, iclass 19, count 2 2006.210.07:31:10.19#ibcon#about to read 5, iclass 19, count 2 2006.210.07:31:10.19#ibcon#read 5, iclass 19, count 2 2006.210.07:31:10.19#ibcon#about to read 6, iclass 19, count 2 2006.210.07:31:10.19#ibcon#read 6, iclass 19, count 2 2006.210.07:31:10.19#ibcon#end of sib2, iclass 19, count 2 2006.210.07:31:10.19#ibcon#*after write, iclass 19, count 2 2006.210.07:31:10.19#ibcon#*before return 0, iclass 19, count 2 2006.210.07:31:10.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:10.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:10.19#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:31:10.19#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.19#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:10.31#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:10.31#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:10.31#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:31:10.31#ibcon#first serial, iclass 19, count 0 2006.210.07:31:10.31#ibcon#enter sib2, iclass 19, count 0 2006.210.07:31:10.31#ibcon#flushed, iclass 19, count 0 2006.210.07:31:10.31#ibcon#about to write, iclass 19, count 0 2006.210.07:31:10.31#ibcon#wrote, iclass 19, count 0 2006.210.07:31:10.31#ibcon#about to read 3, iclass 19, count 0 2006.210.07:31:10.33#ibcon#read 3, iclass 19, count 0 2006.210.07:31:10.33#ibcon#about to read 4, iclass 19, count 0 2006.210.07:31:10.33#ibcon#read 4, iclass 19, count 0 2006.210.07:31:10.33#ibcon#about to read 5, iclass 19, count 0 2006.210.07:31:10.33#ibcon#read 5, iclass 19, count 0 2006.210.07:31:10.33#ibcon#about to read 6, iclass 19, count 0 2006.210.07:31:10.33#ibcon#read 6, iclass 19, count 0 2006.210.07:31:10.33#ibcon#end of sib2, iclass 19, count 0 2006.210.07:31:10.33#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:31:10.33#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:31:10.33#ibcon#[25=USB\r\n] 2006.210.07:31:10.33#ibcon#*before write, iclass 19, count 0 2006.210.07:31:10.33#ibcon#enter sib2, iclass 19, count 0 2006.210.07:31:10.33#ibcon#flushed, iclass 19, count 0 2006.210.07:31:10.33#ibcon#about to write, iclass 19, count 0 2006.210.07:31:10.33#ibcon#wrote, iclass 19, count 0 2006.210.07:31:10.33#ibcon#about to read 3, iclass 19, count 0 2006.210.07:31:10.36#ibcon#read 3, iclass 19, count 0 2006.210.07:31:10.36#ibcon#about to read 4, iclass 19, count 0 2006.210.07:31:10.36#ibcon#read 4, iclass 19, count 0 2006.210.07:31:10.36#ibcon#about to read 5, iclass 19, count 0 2006.210.07:31:10.36#ibcon#read 5, iclass 19, count 0 2006.210.07:31:10.36#ibcon#about to read 6, iclass 19, count 0 2006.210.07:31:10.36#ibcon#read 6, iclass 19, count 0 2006.210.07:31:10.36#ibcon#end of sib2, iclass 19, count 0 2006.210.07:31:10.36#ibcon#*after write, iclass 19, count 0 2006.210.07:31:10.36#ibcon#*before return 0, iclass 19, count 0 2006.210.07:31:10.36#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:10.36#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:10.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:31:10.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:31:10.36$vc4f8/valo=7,832.99 2006.210.07:31:10.36#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:31:10.36#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:31:10.36#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:10.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:10.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:10.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:10.36#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:31:10.36#ibcon#first serial, iclass 21, count 0 2006.210.07:31:10.36#ibcon#enter sib2, iclass 21, count 0 2006.210.07:31:10.36#ibcon#flushed, iclass 21, count 0 2006.210.07:31:10.36#ibcon#about to write, iclass 21, count 0 2006.210.07:31:10.36#ibcon#wrote, iclass 21, count 0 2006.210.07:31:10.36#ibcon#about to read 3, iclass 21, count 0 2006.210.07:31:10.38#ibcon#read 3, iclass 21, count 0 2006.210.07:31:10.38#ibcon#about to read 4, iclass 21, count 0 2006.210.07:31:10.38#ibcon#read 4, iclass 21, count 0 2006.210.07:31:10.38#ibcon#about to read 5, iclass 21, count 0 2006.210.07:31:10.38#ibcon#read 5, iclass 21, count 0 2006.210.07:31:10.38#ibcon#about to read 6, iclass 21, count 0 2006.210.07:31:10.38#ibcon#read 6, iclass 21, count 0 2006.210.07:31:10.38#ibcon#end of sib2, iclass 21, count 0 2006.210.07:31:10.38#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:31:10.38#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:31:10.38#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:31:10.38#ibcon#*before write, iclass 21, count 0 2006.210.07:31:10.38#ibcon#enter sib2, iclass 21, count 0 2006.210.07:31:10.38#ibcon#flushed, iclass 21, count 0 2006.210.07:31:10.38#ibcon#about to write, iclass 21, count 0 2006.210.07:31:10.38#ibcon#wrote, iclass 21, count 0 2006.210.07:31:10.38#ibcon#about to read 3, iclass 21, count 0 2006.210.07:31:10.42#ibcon#read 3, iclass 21, count 0 2006.210.07:31:10.42#ibcon#about to read 4, iclass 21, count 0 2006.210.07:31:10.42#ibcon#read 4, iclass 21, count 0 2006.210.07:31:10.42#ibcon#about to read 5, iclass 21, count 0 2006.210.07:31:10.42#ibcon#read 5, iclass 21, count 0 2006.210.07:31:10.42#ibcon#about to read 6, iclass 21, count 0 2006.210.07:31:10.42#ibcon#read 6, iclass 21, count 0 2006.210.07:31:10.42#ibcon#end of sib2, iclass 21, count 0 2006.210.07:31:10.42#ibcon#*after write, iclass 21, count 0 2006.210.07:31:10.42#ibcon#*before return 0, iclass 21, count 0 2006.210.07:31:10.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:10.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:10.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:31:10.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:31:10.42$vc4f8/va=7,6 2006.210.07:31:10.42#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.07:31:10.42#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.07:31:10.42#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:10.42#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:31:10.48#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:31:10.48#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:31:10.48#ibcon#enter wrdev, iclass 23, count 2 2006.210.07:31:10.48#ibcon#first serial, iclass 23, count 2 2006.210.07:31:10.48#ibcon#enter sib2, iclass 23, count 2 2006.210.07:31:10.48#ibcon#flushed, iclass 23, count 2 2006.210.07:31:10.48#ibcon#about to write, iclass 23, count 2 2006.210.07:31:10.48#ibcon#wrote, iclass 23, count 2 2006.210.07:31:10.48#ibcon#about to read 3, iclass 23, count 2 2006.210.07:31:10.50#ibcon#read 3, iclass 23, count 2 2006.210.07:31:10.50#ibcon#about to read 4, iclass 23, count 2 2006.210.07:31:10.50#ibcon#read 4, iclass 23, count 2 2006.210.07:31:10.50#ibcon#about to read 5, iclass 23, count 2 2006.210.07:31:10.50#ibcon#read 5, iclass 23, count 2 2006.210.07:31:10.50#ibcon#about to read 6, iclass 23, count 2 2006.210.07:31:10.50#ibcon#read 6, iclass 23, count 2 2006.210.07:31:10.50#ibcon#end of sib2, iclass 23, count 2 2006.210.07:31:10.50#ibcon#*mode == 0, iclass 23, count 2 2006.210.07:31:10.50#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.07:31:10.50#ibcon#[25=AT07-06\r\n] 2006.210.07:31:10.50#ibcon#*before write, iclass 23, count 2 2006.210.07:31:10.50#ibcon#enter sib2, iclass 23, count 2 2006.210.07:31:10.50#ibcon#flushed, iclass 23, count 2 2006.210.07:31:10.50#ibcon#about to write, iclass 23, count 2 2006.210.07:31:10.50#ibcon#wrote, iclass 23, count 2 2006.210.07:31:10.50#ibcon#about to read 3, iclass 23, count 2 2006.210.07:31:10.53#ibcon#read 3, iclass 23, count 2 2006.210.07:31:10.53#ibcon#about to read 4, iclass 23, count 2 2006.210.07:31:10.53#ibcon#read 4, iclass 23, count 2 2006.210.07:31:10.53#ibcon#about to read 5, iclass 23, count 2 2006.210.07:31:10.53#ibcon#read 5, iclass 23, count 2 2006.210.07:31:10.53#ibcon#about to read 6, iclass 23, count 2 2006.210.07:31:10.53#ibcon#read 6, iclass 23, count 2 2006.210.07:31:10.53#ibcon#end of sib2, iclass 23, count 2 2006.210.07:31:10.53#ibcon#*after write, iclass 23, count 2 2006.210.07:31:10.53#ibcon#*before return 0, iclass 23, count 2 2006.210.07:31:10.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:31:10.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:31:10.53#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.07:31:10.53#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.53#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:31:10.61#abcon#<5=/05 3.9 6.5 27.72 901006.2\r\n> 2006.210.07:31:10.63#abcon#{5=INTERFACE CLEAR} 2006.210.07:31:10.65#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:31:10.65#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:31:10.65#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:31:10.65#ibcon#first serial, iclass 23, count 0 2006.210.07:31:10.65#ibcon#enter sib2, iclass 23, count 0 2006.210.07:31:10.65#ibcon#flushed, iclass 23, count 0 2006.210.07:31:10.65#ibcon#about to write, iclass 23, count 0 2006.210.07:31:10.65#ibcon#wrote, iclass 23, count 0 2006.210.07:31:10.65#ibcon#about to read 3, iclass 23, count 0 2006.210.07:31:10.67#ibcon#read 3, iclass 23, count 0 2006.210.07:31:10.67#ibcon#about to read 4, iclass 23, count 0 2006.210.07:31:10.67#ibcon#read 4, iclass 23, count 0 2006.210.07:31:10.67#ibcon#about to read 5, iclass 23, count 0 2006.210.07:31:10.67#ibcon#read 5, iclass 23, count 0 2006.210.07:31:10.67#ibcon#about to read 6, iclass 23, count 0 2006.210.07:31:10.67#ibcon#read 6, iclass 23, count 0 2006.210.07:31:10.67#ibcon#end of sib2, iclass 23, count 0 2006.210.07:31:10.67#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:31:10.67#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:31:10.67#ibcon#[25=USB\r\n] 2006.210.07:31:10.67#ibcon#*before write, iclass 23, count 0 2006.210.07:31:10.67#ibcon#enter sib2, iclass 23, count 0 2006.210.07:31:10.67#ibcon#flushed, iclass 23, count 0 2006.210.07:31:10.67#ibcon#about to write, iclass 23, count 0 2006.210.07:31:10.67#ibcon#wrote, iclass 23, count 0 2006.210.07:31:10.67#ibcon#about to read 3, iclass 23, count 0 2006.210.07:31:10.69#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:31:10.70#ibcon#read 3, iclass 23, count 0 2006.210.07:31:10.70#ibcon#about to read 4, iclass 23, count 0 2006.210.07:31:10.70#ibcon#read 4, iclass 23, count 0 2006.210.07:31:10.70#ibcon#about to read 5, iclass 23, count 0 2006.210.07:31:10.70#ibcon#read 5, iclass 23, count 0 2006.210.07:31:10.70#ibcon#about to read 6, iclass 23, count 0 2006.210.07:31:10.70#ibcon#read 6, iclass 23, count 0 2006.210.07:31:10.70#ibcon#end of sib2, iclass 23, count 0 2006.210.07:31:10.70#ibcon#*after write, iclass 23, count 0 2006.210.07:31:10.70#ibcon#*before return 0, iclass 23, count 0 2006.210.07:31:10.70#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:31:10.70#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:31:10.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:31:10.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:31:10.70$vc4f8/valo=8,852.99 2006.210.07:31:10.70#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.07:31:10.70#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.07:31:10.70#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:10.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:31:10.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:31:10.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:31:10.70#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:31:10.70#ibcon#first serial, iclass 29, count 0 2006.210.07:31:10.70#ibcon#enter sib2, iclass 29, count 0 2006.210.07:31:10.70#ibcon#flushed, iclass 29, count 0 2006.210.07:31:10.70#ibcon#about to write, iclass 29, count 0 2006.210.07:31:10.70#ibcon#wrote, iclass 29, count 0 2006.210.07:31:10.70#ibcon#about to read 3, iclass 29, count 0 2006.210.07:31:10.72#ibcon#read 3, iclass 29, count 0 2006.210.07:31:10.72#ibcon#about to read 4, iclass 29, count 0 2006.210.07:31:10.72#ibcon#read 4, iclass 29, count 0 2006.210.07:31:10.72#ibcon#about to read 5, iclass 29, count 0 2006.210.07:31:10.72#ibcon#read 5, iclass 29, count 0 2006.210.07:31:10.72#ibcon#about to read 6, iclass 29, count 0 2006.210.07:31:10.72#ibcon#read 6, iclass 29, count 0 2006.210.07:31:10.72#ibcon#end of sib2, iclass 29, count 0 2006.210.07:31:10.72#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:31:10.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:31:10.72#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:31:10.72#ibcon#*before write, iclass 29, count 0 2006.210.07:31:10.72#ibcon#enter sib2, iclass 29, count 0 2006.210.07:31:10.72#ibcon#flushed, iclass 29, count 0 2006.210.07:31:10.72#ibcon#about to write, iclass 29, count 0 2006.210.07:31:10.72#ibcon#wrote, iclass 29, count 0 2006.210.07:31:10.72#ibcon#about to read 3, iclass 29, count 0 2006.210.07:31:10.76#ibcon#read 3, iclass 29, count 0 2006.210.07:31:10.76#ibcon#about to read 4, iclass 29, count 0 2006.210.07:31:10.76#ibcon#read 4, iclass 29, count 0 2006.210.07:31:10.76#ibcon#about to read 5, iclass 29, count 0 2006.210.07:31:10.76#ibcon#read 5, iclass 29, count 0 2006.210.07:31:10.76#ibcon#about to read 6, iclass 29, count 0 2006.210.07:31:10.76#ibcon#read 6, iclass 29, count 0 2006.210.07:31:10.76#ibcon#end of sib2, iclass 29, count 0 2006.210.07:31:10.76#ibcon#*after write, iclass 29, count 0 2006.210.07:31:10.76#ibcon#*before return 0, iclass 29, count 0 2006.210.07:31:10.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:31:10.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:31:10.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:31:10.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:31:10.76$vc4f8/va=8,7 2006.210.07:31:10.76#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.07:31:10.76#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.07:31:10.76#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:10.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:31:10.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:31:10.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:31:10.82#ibcon#enter wrdev, iclass 31, count 2 2006.210.07:31:10.82#ibcon#first serial, iclass 31, count 2 2006.210.07:31:10.82#ibcon#enter sib2, iclass 31, count 2 2006.210.07:31:10.82#ibcon#flushed, iclass 31, count 2 2006.210.07:31:10.82#ibcon#about to write, iclass 31, count 2 2006.210.07:31:10.82#ibcon#wrote, iclass 31, count 2 2006.210.07:31:10.82#ibcon#about to read 3, iclass 31, count 2 2006.210.07:31:10.84#ibcon#read 3, iclass 31, count 2 2006.210.07:31:10.84#ibcon#about to read 4, iclass 31, count 2 2006.210.07:31:10.84#ibcon#read 4, iclass 31, count 2 2006.210.07:31:10.84#ibcon#about to read 5, iclass 31, count 2 2006.210.07:31:10.84#ibcon#read 5, iclass 31, count 2 2006.210.07:31:10.84#ibcon#about to read 6, iclass 31, count 2 2006.210.07:31:10.84#ibcon#read 6, iclass 31, count 2 2006.210.07:31:10.84#ibcon#end of sib2, iclass 31, count 2 2006.210.07:31:10.84#ibcon#*mode == 0, iclass 31, count 2 2006.210.07:31:10.84#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.07:31:10.84#ibcon#[25=AT08-07\r\n] 2006.210.07:31:10.84#ibcon#*before write, iclass 31, count 2 2006.210.07:31:10.84#ibcon#enter sib2, iclass 31, count 2 2006.210.07:31:10.84#ibcon#flushed, iclass 31, count 2 2006.210.07:31:10.84#ibcon#about to write, iclass 31, count 2 2006.210.07:31:10.84#ibcon#wrote, iclass 31, count 2 2006.210.07:31:10.84#ibcon#about to read 3, iclass 31, count 2 2006.210.07:31:10.87#ibcon#read 3, iclass 31, count 2 2006.210.07:31:10.87#ibcon#about to read 4, iclass 31, count 2 2006.210.07:31:10.87#ibcon#read 4, iclass 31, count 2 2006.210.07:31:10.87#ibcon#about to read 5, iclass 31, count 2 2006.210.07:31:10.87#ibcon#read 5, iclass 31, count 2 2006.210.07:31:10.87#ibcon#about to read 6, iclass 31, count 2 2006.210.07:31:10.87#ibcon#read 6, iclass 31, count 2 2006.210.07:31:10.87#ibcon#end of sib2, iclass 31, count 2 2006.210.07:31:10.87#ibcon#*after write, iclass 31, count 2 2006.210.07:31:10.87#ibcon#*before return 0, iclass 31, count 2 2006.210.07:31:10.87#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:31:10.87#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:31:10.87#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.07:31:10.87#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.87#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:31:10.99#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:31:10.99#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:31:10.99#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:31:10.99#ibcon#first serial, iclass 31, count 0 2006.210.07:31:10.99#ibcon#enter sib2, iclass 31, count 0 2006.210.07:31:10.99#ibcon#flushed, iclass 31, count 0 2006.210.07:31:10.99#ibcon#about to write, iclass 31, count 0 2006.210.07:31:10.99#ibcon#wrote, iclass 31, count 0 2006.210.07:31:10.99#ibcon#about to read 3, iclass 31, count 0 2006.210.07:31:11.01#ibcon#read 3, iclass 31, count 0 2006.210.07:31:11.01#ibcon#about to read 4, iclass 31, count 0 2006.210.07:31:11.01#ibcon#read 4, iclass 31, count 0 2006.210.07:31:11.01#ibcon#about to read 5, iclass 31, count 0 2006.210.07:31:11.01#ibcon#read 5, iclass 31, count 0 2006.210.07:31:11.01#ibcon#about to read 6, iclass 31, count 0 2006.210.07:31:11.01#ibcon#read 6, iclass 31, count 0 2006.210.07:31:11.01#ibcon#end of sib2, iclass 31, count 0 2006.210.07:31:11.01#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:31:11.01#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:31:11.01#ibcon#[25=USB\r\n] 2006.210.07:31:11.01#ibcon#*before write, iclass 31, count 0 2006.210.07:31:11.01#ibcon#enter sib2, iclass 31, count 0 2006.210.07:31:11.01#ibcon#flushed, iclass 31, count 0 2006.210.07:31:11.01#ibcon#about to write, iclass 31, count 0 2006.210.07:31:11.01#ibcon#wrote, iclass 31, count 0 2006.210.07:31:11.01#ibcon#about to read 3, iclass 31, count 0 2006.210.07:31:11.04#ibcon#read 3, iclass 31, count 0 2006.210.07:31:11.04#ibcon#about to read 4, iclass 31, count 0 2006.210.07:31:11.04#ibcon#read 4, iclass 31, count 0 2006.210.07:31:11.04#ibcon#about to read 5, iclass 31, count 0 2006.210.07:31:11.04#ibcon#read 5, iclass 31, count 0 2006.210.07:31:11.04#ibcon#about to read 6, iclass 31, count 0 2006.210.07:31:11.04#ibcon#read 6, iclass 31, count 0 2006.210.07:31:11.04#ibcon#end of sib2, iclass 31, count 0 2006.210.07:31:11.04#ibcon#*after write, iclass 31, count 0 2006.210.07:31:11.04#ibcon#*before return 0, iclass 31, count 0 2006.210.07:31:11.04#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:31:11.04#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:31:11.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:31:11.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:31:11.04$vc4f8/vblo=1,632.99 2006.210.07:31:11.04#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.07:31:11.04#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.07:31:11.04#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:11.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:11.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:11.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:11.04#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:31:11.04#ibcon#first serial, iclass 33, count 0 2006.210.07:31:11.04#ibcon#enter sib2, iclass 33, count 0 2006.210.07:31:11.04#ibcon#flushed, iclass 33, count 0 2006.210.07:31:11.04#ibcon#about to write, iclass 33, count 0 2006.210.07:31:11.04#ibcon#wrote, iclass 33, count 0 2006.210.07:31:11.04#ibcon#about to read 3, iclass 33, count 0 2006.210.07:31:11.06#ibcon#read 3, iclass 33, count 0 2006.210.07:31:11.06#ibcon#about to read 4, iclass 33, count 0 2006.210.07:31:11.06#ibcon#read 4, iclass 33, count 0 2006.210.07:31:11.06#ibcon#about to read 5, iclass 33, count 0 2006.210.07:31:11.06#ibcon#read 5, iclass 33, count 0 2006.210.07:31:11.06#ibcon#about to read 6, iclass 33, count 0 2006.210.07:31:11.06#ibcon#read 6, iclass 33, count 0 2006.210.07:31:11.06#ibcon#end of sib2, iclass 33, count 0 2006.210.07:31:11.06#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:31:11.06#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:31:11.06#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:31:11.06#ibcon#*before write, iclass 33, count 0 2006.210.07:31:11.06#ibcon#enter sib2, iclass 33, count 0 2006.210.07:31:11.06#ibcon#flushed, iclass 33, count 0 2006.210.07:31:11.06#ibcon#about to write, iclass 33, count 0 2006.210.07:31:11.06#ibcon#wrote, iclass 33, count 0 2006.210.07:31:11.06#ibcon#about to read 3, iclass 33, count 0 2006.210.07:31:11.10#ibcon#read 3, iclass 33, count 0 2006.210.07:31:11.10#ibcon#about to read 4, iclass 33, count 0 2006.210.07:31:11.10#ibcon#read 4, iclass 33, count 0 2006.210.07:31:11.10#ibcon#about to read 5, iclass 33, count 0 2006.210.07:31:11.10#ibcon#read 5, iclass 33, count 0 2006.210.07:31:11.10#ibcon#about to read 6, iclass 33, count 0 2006.210.07:31:11.10#ibcon#read 6, iclass 33, count 0 2006.210.07:31:11.10#ibcon#end of sib2, iclass 33, count 0 2006.210.07:31:11.10#ibcon#*after write, iclass 33, count 0 2006.210.07:31:11.10#ibcon#*before return 0, iclass 33, count 0 2006.210.07:31:11.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:11.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:31:11.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:31:11.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:31:11.10$vc4f8/vb=1,4 2006.210.07:31:11.10#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.07:31:11.10#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.07:31:11.10#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:11.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:11.10#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:11.10#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:11.10#ibcon#enter wrdev, iclass 35, count 2 2006.210.07:31:11.10#ibcon#first serial, iclass 35, count 2 2006.210.07:31:11.10#ibcon#enter sib2, iclass 35, count 2 2006.210.07:31:11.10#ibcon#flushed, iclass 35, count 2 2006.210.07:31:11.10#ibcon#about to write, iclass 35, count 2 2006.210.07:31:11.10#ibcon#wrote, iclass 35, count 2 2006.210.07:31:11.10#ibcon#about to read 3, iclass 35, count 2 2006.210.07:31:11.12#ibcon#read 3, iclass 35, count 2 2006.210.07:31:11.12#ibcon#about to read 4, iclass 35, count 2 2006.210.07:31:11.12#ibcon#read 4, iclass 35, count 2 2006.210.07:31:11.12#ibcon#about to read 5, iclass 35, count 2 2006.210.07:31:11.12#ibcon#read 5, iclass 35, count 2 2006.210.07:31:11.12#ibcon#about to read 6, iclass 35, count 2 2006.210.07:31:11.12#ibcon#read 6, iclass 35, count 2 2006.210.07:31:11.12#ibcon#end of sib2, iclass 35, count 2 2006.210.07:31:11.12#ibcon#*mode == 0, iclass 35, count 2 2006.210.07:31:11.12#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.07:31:11.12#ibcon#[27=AT01-04\r\n] 2006.210.07:31:11.12#ibcon#*before write, iclass 35, count 2 2006.210.07:31:11.12#ibcon#enter sib2, iclass 35, count 2 2006.210.07:31:11.12#ibcon#flushed, iclass 35, count 2 2006.210.07:31:11.12#ibcon#about to write, iclass 35, count 2 2006.210.07:31:11.12#ibcon#wrote, iclass 35, count 2 2006.210.07:31:11.12#ibcon#about to read 3, iclass 35, count 2 2006.210.07:31:11.15#ibcon#read 3, iclass 35, count 2 2006.210.07:31:11.15#ibcon#about to read 4, iclass 35, count 2 2006.210.07:31:11.15#ibcon#read 4, iclass 35, count 2 2006.210.07:31:11.15#ibcon#about to read 5, iclass 35, count 2 2006.210.07:31:11.15#ibcon#read 5, iclass 35, count 2 2006.210.07:31:11.15#ibcon#about to read 6, iclass 35, count 2 2006.210.07:31:11.15#ibcon#read 6, iclass 35, count 2 2006.210.07:31:11.15#ibcon#end of sib2, iclass 35, count 2 2006.210.07:31:11.15#ibcon#*after write, iclass 35, count 2 2006.210.07:31:11.15#ibcon#*before return 0, iclass 35, count 2 2006.210.07:31:11.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:11.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:31:11.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.07:31:11.15#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:11.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:11.27#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:11.27#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:11.27#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:31:11.27#ibcon#first serial, iclass 35, count 0 2006.210.07:31:11.27#ibcon#enter sib2, iclass 35, count 0 2006.210.07:31:11.27#ibcon#flushed, iclass 35, count 0 2006.210.07:31:11.27#ibcon#about to write, iclass 35, count 0 2006.210.07:31:11.27#ibcon#wrote, iclass 35, count 0 2006.210.07:31:11.27#ibcon#about to read 3, iclass 35, count 0 2006.210.07:31:11.29#ibcon#read 3, iclass 35, count 0 2006.210.07:31:11.29#ibcon#about to read 4, iclass 35, count 0 2006.210.07:31:11.29#ibcon#read 4, iclass 35, count 0 2006.210.07:31:11.29#ibcon#about to read 5, iclass 35, count 0 2006.210.07:31:11.29#ibcon#read 5, iclass 35, count 0 2006.210.07:31:11.29#ibcon#about to read 6, iclass 35, count 0 2006.210.07:31:11.29#ibcon#read 6, iclass 35, count 0 2006.210.07:31:11.29#ibcon#end of sib2, iclass 35, count 0 2006.210.07:31:11.29#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:31:11.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:31:11.29#ibcon#[27=USB\r\n] 2006.210.07:31:11.29#ibcon#*before write, iclass 35, count 0 2006.210.07:31:11.29#ibcon#enter sib2, iclass 35, count 0 2006.210.07:31:11.29#ibcon#flushed, iclass 35, count 0 2006.210.07:31:11.29#ibcon#about to write, iclass 35, count 0 2006.210.07:31:11.29#ibcon#wrote, iclass 35, count 0 2006.210.07:31:11.29#ibcon#about to read 3, iclass 35, count 0 2006.210.07:31:11.32#ibcon#read 3, iclass 35, count 0 2006.210.07:31:11.32#ibcon#about to read 4, iclass 35, count 0 2006.210.07:31:11.32#ibcon#read 4, iclass 35, count 0 2006.210.07:31:11.32#ibcon#about to read 5, iclass 35, count 0 2006.210.07:31:11.32#ibcon#read 5, iclass 35, count 0 2006.210.07:31:11.32#ibcon#about to read 6, iclass 35, count 0 2006.210.07:31:11.32#ibcon#read 6, iclass 35, count 0 2006.210.07:31:11.32#ibcon#end of sib2, iclass 35, count 0 2006.210.07:31:11.32#ibcon#*after write, iclass 35, count 0 2006.210.07:31:11.32#ibcon#*before return 0, iclass 35, count 0 2006.210.07:31:11.32#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:11.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:31:11.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:31:11.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:31:11.32$vc4f8/vblo=2,640.99 2006.210.07:31:11.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:31:11.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:31:11.32#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:11.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:11.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:11.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:11.32#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:31:11.32#ibcon#first serial, iclass 37, count 0 2006.210.07:31:11.32#ibcon#enter sib2, iclass 37, count 0 2006.210.07:31:11.32#ibcon#flushed, iclass 37, count 0 2006.210.07:31:11.32#ibcon#about to write, iclass 37, count 0 2006.210.07:31:11.32#ibcon#wrote, iclass 37, count 0 2006.210.07:31:11.32#ibcon#about to read 3, iclass 37, count 0 2006.210.07:31:11.34#ibcon#read 3, iclass 37, count 0 2006.210.07:31:11.34#ibcon#about to read 4, iclass 37, count 0 2006.210.07:31:11.34#ibcon#read 4, iclass 37, count 0 2006.210.07:31:11.34#ibcon#about to read 5, iclass 37, count 0 2006.210.07:31:11.34#ibcon#read 5, iclass 37, count 0 2006.210.07:31:11.34#ibcon#about to read 6, iclass 37, count 0 2006.210.07:31:11.34#ibcon#read 6, iclass 37, count 0 2006.210.07:31:11.34#ibcon#end of sib2, iclass 37, count 0 2006.210.07:31:11.34#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:31:11.34#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:31:11.34#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:31:11.34#ibcon#*before write, iclass 37, count 0 2006.210.07:31:11.34#ibcon#enter sib2, iclass 37, count 0 2006.210.07:31:11.34#ibcon#flushed, iclass 37, count 0 2006.210.07:31:11.34#ibcon#about to write, iclass 37, count 0 2006.210.07:31:11.34#ibcon#wrote, iclass 37, count 0 2006.210.07:31:11.34#ibcon#about to read 3, iclass 37, count 0 2006.210.07:31:11.38#ibcon#read 3, iclass 37, count 0 2006.210.07:31:11.38#ibcon#about to read 4, iclass 37, count 0 2006.210.07:31:11.38#ibcon#read 4, iclass 37, count 0 2006.210.07:31:11.38#ibcon#about to read 5, iclass 37, count 0 2006.210.07:31:11.38#ibcon#read 5, iclass 37, count 0 2006.210.07:31:11.38#ibcon#about to read 6, iclass 37, count 0 2006.210.07:31:11.38#ibcon#read 6, iclass 37, count 0 2006.210.07:31:11.38#ibcon#end of sib2, iclass 37, count 0 2006.210.07:31:11.38#ibcon#*after write, iclass 37, count 0 2006.210.07:31:11.38#ibcon#*before return 0, iclass 37, count 0 2006.210.07:31:11.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:11.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:31:11.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:31:11.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:31:11.38$vc4f8/vb=2,4 2006.210.07:31:11.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:31:11.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:31:11.38#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:11.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:11.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:11.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:11.44#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:31:11.44#ibcon#first serial, iclass 39, count 2 2006.210.07:31:11.44#ibcon#enter sib2, iclass 39, count 2 2006.210.07:31:11.44#ibcon#flushed, iclass 39, count 2 2006.210.07:31:11.44#ibcon#about to write, iclass 39, count 2 2006.210.07:31:11.44#ibcon#wrote, iclass 39, count 2 2006.210.07:31:11.44#ibcon#about to read 3, iclass 39, count 2 2006.210.07:31:11.46#ibcon#read 3, iclass 39, count 2 2006.210.07:31:11.46#ibcon#about to read 4, iclass 39, count 2 2006.210.07:31:11.46#ibcon#read 4, iclass 39, count 2 2006.210.07:31:11.46#ibcon#about to read 5, iclass 39, count 2 2006.210.07:31:11.46#ibcon#read 5, iclass 39, count 2 2006.210.07:31:11.46#ibcon#about to read 6, iclass 39, count 2 2006.210.07:31:11.46#ibcon#read 6, iclass 39, count 2 2006.210.07:31:11.46#ibcon#end of sib2, iclass 39, count 2 2006.210.07:31:11.46#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:31:11.46#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:31:11.46#ibcon#[27=AT02-04\r\n] 2006.210.07:31:11.46#ibcon#*before write, iclass 39, count 2 2006.210.07:31:11.46#ibcon#enter sib2, iclass 39, count 2 2006.210.07:31:11.46#ibcon#flushed, iclass 39, count 2 2006.210.07:31:11.46#ibcon#about to write, iclass 39, count 2 2006.210.07:31:11.46#ibcon#wrote, iclass 39, count 2 2006.210.07:31:11.46#ibcon#about to read 3, iclass 39, count 2 2006.210.07:31:11.49#ibcon#read 3, iclass 39, count 2 2006.210.07:31:11.49#ibcon#about to read 4, iclass 39, count 2 2006.210.07:31:11.49#ibcon#read 4, iclass 39, count 2 2006.210.07:31:11.49#ibcon#about to read 5, iclass 39, count 2 2006.210.07:31:11.49#ibcon#read 5, iclass 39, count 2 2006.210.07:31:11.49#ibcon#about to read 6, iclass 39, count 2 2006.210.07:31:11.49#ibcon#read 6, iclass 39, count 2 2006.210.07:31:11.49#ibcon#end of sib2, iclass 39, count 2 2006.210.07:31:11.49#ibcon#*after write, iclass 39, count 2 2006.210.07:31:11.49#ibcon#*before return 0, iclass 39, count 2 2006.210.07:31:11.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:11.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:31:11.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:31:11.49#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:11.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:11.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:11.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:11.61#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:31:11.61#ibcon#first serial, iclass 39, count 0 2006.210.07:31:11.61#ibcon#enter sib2, iclass 39, count 0 2006.210.07:31:11.61#ibcon#flushed, iclass 39, count 0 2006.210.07:31:11.61#ibcon#about to write, iclass 39, count 0 2006.210.07:31:11.61#ibcon#wrote, iclass 39, count 0 2006.210.07:31:11.61#ibcon#about to read 3, iclass 39, count 0 2006.210.07:31:11.63#ibcon#read 3, iclass 39, count 0 2006.210.07:31:11.63#ibcon#about to read 4, iclass 39, count 0 2006.210.07:31:11.63#ibcon#read 4, iclass 39, count 0 2006.210.07:31:11.63#ibcon#about to read 5, iclass 39, count 0 2006.210.07:31:11.63#ibcon#read 5, iclass 39, count 0 2006.210.07:31:11.63#ibcon#about to read 6, iclass 39, count 0 2006.210.07:31:11.63#ibcon#read 6, iclass 39, count 0 2006.210.07:31:11.63#ibcon#end of sib2, iclass 39, count 0 2006.210.07:31:11.63#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:31:11.63#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:31:11.63#ibcon#[27=USB\r\n] 2006.210.07:31:11.63#ibcon#*before write, iclass 39, count 0 2006.210.07:31:11.63#ibcon#enter sib2, iclass 39, count 0 2006.210.07:31:11.63#ibcon#flushed, iclass 39, count 0 2006.210.07:31:11.63#ibcon#about to write, iclass 39, count 0 2006.210.07:31:11.63#ibcon#wrote, iclass 39, count 0 2006.210.07:31:11.63#ibcon#about to read 3, iclass 39, count 0 2006.210.07:31:11.66#ibcon#read 3, iclass 39, count 0 2006.210.07:31:11.66#ibcon#about to read 4, iclass 39, count 0 2006.210.07:31:11.66#ibcon#read 4, iclass 39, count 0 2006.210.07:31:11.66#ibcon#about to read 5, iclass 39, count 0 2006.210.07:31:11.66#ibcon#read 5, iclass 39, count 0 2006.210.07:31:11.66#ibcon#about to read 6, iclass 39, count 0 2006.210.07:31:11.66#ibcon#read 6, iclass 39, count 0 2006.210.07:31:11.66#ibcon#end of sib2, iclass 39, count 0 2006.210.07:31:11.66#ibcon#*after write, iclass 39, count 0 2006.210.07:31:11.66#ibcon#*before return 0, iclass 39, count 0 2006.210.07:31:11.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:11.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:31:11.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:31:11.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:31:11.66$vc4f8/vblo=3,656.99 2006.210.07:31:11.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:31:11.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:31:11.66#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:11.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:11.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:11.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:11.66#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:31:11.66#ibcon#first serial, iclass 3, count 0 2006.210.07:31:11.66#ibcon#enter sib2, iclass 3, count 0 2006.210.07:31:11.66#ibcon#flushed, iclass 3, count 0 2006.210.07:31:11.66#ibcon#about to write, iclass 3, count 0 2006.210.07:31:11.66#ibcon#wrote, iclass 3, count 0 2006.210.07:31:11.66#ibcon#about to read 3, iclass 3, count 0 2006.210.07:31:11.68#ibcon#read 3, iclass 3, count 0 2006.210.07:31:11.68#ibcon#about to read 4, iclass 3, count 0 2006.210.07:31:11.68#ibcon#read 4, iclass 3, count 0 2006.210.07:31:11.68#ibcon#about to read 5, iclass 3, count 0 2006.210.07:31:11.68#ibcon#read 5, iclass 3, count 0 2006.210.07:31:11.68#ibcon#about to read 6, iclass 3, count 0 2006.210.07:31:11.68#ibcon#read 6, iclass 3, count 0 2006.210.07:31:11.68#ibcon#end of sib2, iclass 3, count 0 2006.210.07:31:11.68#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:31:11.68#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:31:11.68#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:31:11.68#ibcon#*before write, iclass 3, count 0 2006.210.07:31:11.68#ibcon#enter sib2, iclass 3, count 0 2006.210.07:31:11.68#ibcon#flushed, iclass 3, count 0 2006.210.07:31:11.68#ibcon#about to write, iclass 3, count 0 2006.210.07:31:11.68#ibcon#wrote, iclass 3, count 0 2006.210.07:31:11.68#ibcon#about to read 3, iclass 3, count 0 2006.210.07:31:11.72#ibcon#read 3, iclass 3, count 0 2006.210.07:31:11.72#ibcon#about to read 4, iclass 3, count 0 2006.210.07:31:11.72#ibcon#read 4, iclass 3, count 0 2006.210.07:31:11.72#ibcon#about to read 5, iclass 3, count 0 2006.210.07:31:11.72#ibcon#read 5, iclass 3, count 0 2006.210.07:31:11.72#ibcon#about to read 6, iclass 3, count 0 2006.210.07:31:11.72#ibcon#read 6, iclass 3, count 0 2006.210.07:31:11.72#ibcon#end of sib2, iclass 3, count 0 2006.210.07:31:11.72#ibcon#*after write, iclass 3, count 0 2006.210.07:31:11.72#ibcon#*before return 0, iclass 3, count 0 2006.210.07:31:11.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:11.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:31:11.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:31:11.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:31:11.72$vc4f8/vb=3,3 2006.210.07:31:11.72#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:31:11.72#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:31:11.72#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:11.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:11.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:11.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:11.78#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:31:11.78#ibcon#first serial, iclass 5, count 2 2006.210.07:31:11.78#ibcon#enter sib2, iclass 5, count 2 2006.210.07:31:11.78#ibcon#flushed, iclass 5, count 2 2006.210.07:31:11.78#ibcon#about to write, iclass 5, count 2 2006.210.07:31:11.78#ibcon#wrote, iclass 5, count 2 2006.210.07:31:11.78#ibcon#about to read 3, iclass 5, count 2 2006.210.07:31:11.80#ibcon#read 3, iclass 5, count 2 2006.210.07:31:11.80#ibcon#about to read 4, iclass 5, count 2 2006.210.07:31:11.80#ibcon#read 4, iclass 5, count 2 2006.210.07:31:11.80#ibcon#about to read 5, iclass 5, count 2 2006.210.07:31:11.80#ibcon#read 5, iclass 5, count 2 2006.210.07:31:11.80#ibcon#about to read 6, iclass 5, count 2 2006.210.07:31:11.80#ibcon#read 6, iclass 5, count 2 2006.210.07:31:11.80#ibcon#end of sib2, iclass 5, count 2 2006.210.07:31:11.80#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:31:11.80#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:31:11.80#ibcon#[27=AT03-03\r\n] 2006.210.07:31:11.80#ibcon#*before write, iclass 5, count 2 2006.210.07:31:11.80#ibcon#enter sib2, iclass 5, count 2 2006.210.07:31:11.80#ibcon#flushed, iclass 5, count 2 2006.210.07:31:11.80#ibcon#about to write, iclass 5, count 2 2006.210.07:31:11.80#ibcon#wrote, iclass 5, count 2 2006.210.07:31:11.80#ibcon#about to read 3, iclass 5, count 2 2006.210.07:31:11.83#ibcon#read 3, iclass 5, count 2 2006.210.07:31:11.83#ibcon#about to read 4, iclass 5, count 2 2006.210.07:31:11.83#ibcon#read 4, iclass 5, count 2 2006.210.07:31:11.83#ibcon#about to read 5, iclass 5, count 2 2006.210.07:31:11.83#ibcon#read 5, iclass 5, count 2 2006.210.07:31:11.83#ibcon#about to read 6, iclass 5, count 2 2006.210.07:31:11.83#ibcon#read 6, iclass 5, count 2 2006.210.07:31:11.83#ibcon#end of sib2, iclass 5, count 2 2006.210.07:31:11.83#ibcon#*after write, iclass 5, count 2 2006.210.07:31:11.83#ibcon#*before return 0, iclass 5, count 2 2006.210.07:31:11.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:11.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:31:11.83#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:31:11.83#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:11.83#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:11.95#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:11.95#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:11.95#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:31:11.95#ibcon#first serial, iclass 5, count 0 2006.210.07:31:11.95#ibcon#enter sib2, iclass 5, count 0 2006.210.07:31:11.95#ibcon#flushed, iclass 5, count 0 2006.210.07:31:11.95#ibcon#about to write, iclass 5, count 0 2006.210.07:31:11.95#ibcon#wrote, iclass 5, count 0 2006.210.07:31:11.95#ibcon#about to read 3, iclass 5, count 0 2006.210.07:31:11.97#ibcon#read 3, iclass 5, count 0 2006.210.07:31:11.97#ibcon#about to read 4, iclass 5, count 0 2006.210.07:31:11.97#ibcon#read 4, iclass 5, count 0 2006.210.07:31:11.97#ibcon#about to read 5, iclass 5, count 0 2006.210.07:31:11.97#ibcon#read 5, iclass 5, count 0 2006.210.07:31:11.97#ibcon#about to read 6, iclass 5, count 0 2006.210.07:31:11.97#ibcon#read 6, iclass 5, count 0 2006.210.07:31:11.97#ibcon#end of sib2, iclass 5, count 0 2006.210.07:31:11.97#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:31:11.97#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:31:11.97#ibcon#[27=USB\r\n] 2006.210.07:31:11.97#ibcon#*before write, iclass 5, count 0 2006.210.07:31:11.97#ibcon#enter sib2, iclass 5, count 0 2006.210.07:31:11.97#ibcon#flushed, iclass 5, count 0 2006.210.07:31:11.97#ibcon#about to write, iclass 5, count 0 2006.210.07:31:11.97#ibcon#wrote, iclass 5, count 0 2006.210.07:31:11.97#ibcon#about to read 3, iclass 5, count 0 2006.210.07:31:12.00#ibcon#read 3, iclass 5, count 0 2006.210.07:31:12.00#ibcon#about to read 4, iclass 5, count 0 2006.210.07:31:12.00#ibcon#read 4, iclass 5, count 0 2006.210.07:31:12.00#ibcon#about to read 5, iclass 5, count 0 2006.210.07:31:12.00#ibcon#read 5, iclass 5, count 0 2006.210.07:31:12.00#ibcon#about to read 6, iclass 5, count 0 2006.210.07:31:12.00#ibcon#read 6, iclass 5, count 0 2006.210.07:31:12.00#ibcon#end of sib2, iclass 5, count 0 2006.210.07:31:12.00#ibcon#*after write, iclass 5, count 0 2006.210.07:31:12.00#ibcon#*before return 0, iclass 5, count 0 2006.210.07:31:12.00#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:12.00#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:31:12.00#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:31:12.00#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:31:12.00$vc4f8/vblo=4,712.99 2006.210.07:31:12.00#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:31:12.00#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:31:12.00#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:12.00#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:12.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:12.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:12.00#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:31:12.00#ibcon#first serial, iclass 7, count 0 2006.210.07:31:12.00#ibcon#enter sib2, iclass 7, count 0 2006.210.07:31:12.00#ibcon#flushed, iclass 7, count 0 2006.210.07:31:12.00#ibcon#about to write, iclass 7, count 0 2006.210.07:31:12.00#ibcon#wrote, iclass 7, count 0 2006.210.07:31:12.00#ibcon#about to read 3, iclass 7, count 0 2006.210.07:31:12.02#ibcon#read 3, iclass 7, count 0 2006.210.07:31:12.02#ibcon#about to read 4, iclass 7, count 0 2006.210.07:31:12.02#ibcon#read 4, iclass 7, count 0 2006.210.07:31:12.02#ibcon#about to read 5, iclass 7, count 0 2006.210.07:31:12.02#ibcon#read 5, iclass 7, count 0 2006.210.07:31:12.02#ibcon#about to read 6, iclass 7, count 0 2006.210.07:31:12.02#ibcon#read 6, iclass 7, count 0 2006.210.07:31:12.02#ibcon#end of sib2, iclass 7, count 0 2006.210.07:31:12.02#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:31:12.02#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:31:12.02#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:31:12.02#ibcon#*before write, iclass 7, count 0 2006.210.07:31:12.02#ibcon#enter sib2, iclass 7, count 0 2006.210.07:31:12.02#ibcon#flushed, iclass 7, count 0 2006.210.07:31:12.02#ibcon#about to write, iclass 7, count 0 2006.210.07:31:12.02#ibcon#wrote, iclass 7, count 0 2006.210.07:31:12.02#ibcon#about to read 3, iclass 7, count 0 2006.210.07:31:12.06#ibcon#read 3, iclass 7, count 0 2006.210.07:31:12.06#ibcon#about to read 4, iclass 7, count 0 2006.210.07:31:12.06#ibcon#read 4, iclass 7, count 0 2006.210.07:31:12.06#ibcon#about to read 5, iclass 7, count 0 2006.210.07:31:12.06#ibcon#read 5, iclass 7, count 0 2006.210.07:31:12.06#ibcon#about to read 6, iclass 7, count 0 2006.210.07:31:12.06#ibcon#read 6, iclass 7, count 0 2006.210.07:31:12.06#ibcon#end of sib2, iclass 7, count 0 2006.210.07:31:12.06#ibcon#*after write, iclass 7, count 0 2006.210.07:31:12.06#ibcon#*before return 0, iclass 7, count 0 2006.210.07:31:12.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:12.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:31:12.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:31:12.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:31:12.06$vc4f8/vb=4,3 2006.210.07:31:12.06#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:31:12.06#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:31:12.06#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:12.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:12.12#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:12.12#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:12.12#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:31:12.12#ibcon#first serial, iclass 11, count 2 2006.210.07:31:12.12#ibcon#enter sib2, iclass 11, count 2 2006.210.07:31:12.12#ibcon#flushed, iclass 11, count 2 2006.210.07:31:12.12#ibcon#about to write, iclass 11, count 2 2006.210.07:31:12.12#ibcon#wrote, iclass 11, count 2 2006.210.07:31:12.12#ibcon#about to read 3, iclass 11, count 2 2006.210.07:31:12.14#ibcon#read 3, iclass 11, count 2 2006.210.07:31:12.14#ibcon#about to read 4, iclass 11, count 2 2006.210.07:31:12.14#ibcon#read 4, iclass 11, count 2 2006.210.07:31:12.14#ibcon#about to read 5, iclass 11, count 2 2006.210.07:31:12.14#ibcon#read 5, iclass 11, count 2 2006.210.07:31:12.14#ibcon#about to read 6, iclass 11, count 2 2006.210.07:31:12.14#ibcon#read 6, iclass 11, count 2 2006.210.07:31:12.14#ibcon#end of sib2, iclass 11, count 2 2006.210.07:31:12.14#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:31:12.14#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:31:12.14#ibcon#[27=AT04-03\r\n] 2006.210.07:31:12.14#ibcon#*before write, iclass 11, count 2 2006.210.07:31:12.14#ibcon#enter sib2, iclass 11, count 2 2006.210.07:31:12.14#ibcon#flushed, iclass 11, count 2 2006.210.07:31:12.14#ibcon#about to write, iclass 11, count 2 2006.210.07:31:12.14#ibcon#wrote, iclass 11, count 2 2006.210.07:31:12.14#ibcon#about to read 3, iclass 11, count 2 2006.210.07:31:12.17#ibcon#read 3, iclass 11, count 2 2006.210.07:31:12.17#ibcon#about to read 4, iclass 11, count 2 2006.210.07:31:12.17#ibcon#read 4, iclass 11, count 2 2006.210.07:31:12.17#ibcon#about to read 5, iclass 11, count 2 2006.210.07:31:12.17#ibcon#read 5, iclass 11, count 2 2006.210.07:31:12.17#ibcon#about to read 6, iclass 11, count 2 2006.210.07:31:12.17#ibcon#read 6, iclass 11, count 2 2006.210.07:31:12.17#ibcon#end of sib2, iclass 11, count 2 2006.210.07:31:12.17#ibcon#*after write, iclass 11, count 2 2006.210.07:31:12.17#ibcon#*before return 0, iclass 11, count 2 2006.210.07:31:12.17#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:12.17#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:31:12.17#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:31:12.17#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:12.17#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:12.29#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:12.29#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:12.29#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:31:12.29#ibcon#first serial, iclass 11, count 0 2006.210.07:31:12.29#ibcon#enter sib2, iclass 11, count 0 2006.210.07:31:12.29#ibcon#flushed, iclass 11, count 0 2006.210.07:31:12.29#ibcon#about to write, iclass 11, count 0 2006.210.07:31:12.29#ibcon#wrote, iclass 11, count 0 2006.210.07:31:12.29#ibcon#about to read 3, iclass 11, count 0 2006.210.07:31:12.31#ibcon#read 3, iclass 11, count 0 2006.210.07:31:12.31#ibcon#about to read 4, iclass 11, count 0 2006.210.07:31:12.31#ibcon#read 4, iclass 11, count 0 2006.210.07:31:12.31#ibcon#about to read 5, iclass 11, count 0 2006.210.07:31:12.31#ibcon#read 5, iclass 11, count 0 2006.210.07:31:12.31#ibcon#about to read 6, iclass 11, count 0 2006.210.07:31:12.31#ibcon#read 6, iclass 11, count 0 2006.210.07:31:12.31#ibcon#end of sib2, iclass 11, count 0 2006.210.07:31:12.31#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:31:12.31#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:31:12.31#ibcon#[27=USB\r\n] 2006.210.07:31:12.31#ibcon#*before write, iclass 11, count 0 2006.210.07:31:12.31#ibcon#enter sib2, iclass 11, count 0 2006.210.07:31:12.31#ibcon#flushed, iclass 11, count 0 2006.210.07:31:12.31#ibcon#about to write, iclass 11, count 0 2006.210.07:31:12.31#ibcon#wrote, iclass 11, count 0 2006.210.07:31:12.31#ibcon#about to read 3, iclass 11, count 0 2006.210.07:31:12.34#ibcon#read 3, iclass 11, count 0 2006.210.07:31:12.34#ibcon#about to read 4, iclass 11, count 0 2006.210.07:31:12.34#ibcon#read 4, iclass 11, count 0 2006.210.07:31:12.34#ibcon#about to read 5, iclass 11, count 0 2006.210.07:31:12.34#ibcon#read 5, iclass 11, count 0 2006.210.07:31:12.34#ibcon#about to read 6, iclass 11, count 0 2006.210.07:31:12.34#ibcon#read 6, iclass 11, count 0 2006.210.07:31:12.34#ibcon#end of sib2, iclass 11, count 0 2006.210.07:31:12.34#ibcon#*after write, iclass 11, count 0 2006.210.07:31:12.34#ibcon#*before return 0, iclass 11, count 0 2006.210.07:31:12.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:12.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:31:12.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:31:12.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:31:12.34$vc4f8/vblo=5,744.99 2006.210.07:31:12.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:31:12.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:31:12.34#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:12.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:12.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:12.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:12.34#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:31:12.34#ibcon#first serial, iclass 13, count 0 2006.210.07:31:12.34#ibcon#enter sib2, iclass 13, count 0 2006.210.07:31:12.34#ibcon#flushed, iclass 13, count 0 2006.210.07:31:12.34#ibcon#about to write, iclass 13, count 0 2006.210.07:31:12.34#ibcon#wrote, iclass 13, count 0 2006.210.07:31:12.34#ibcon#about to read 3, iclass 13, count 0 2006.210.07:31:12.36#ibcon#read 3, iclass 13, count 0 2006.210.07:31:12.36#ibcon#about to read 4, iclass 13, count 0 2006.210.07:31:12.36#ibcon#read 4, iclass 13, count 0 2006.210.07:31:12.36#ibcon#about to read 5, iclass 13, count 0 2006.210.07:31:12.36#ibcon#read 5, iclass 13, count 0 2006.210.07:31:12.36#ibcon#about to read 6, iclass 13, count 0 2006.210.07:31:12.36#ibcon#read 6, iclass 13, count 0 2006.210.07:31:12.36#ibcon#end of sib2, iclass 13, count 0 2006.210.07:31:12.36#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:31:12.36#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:31:12.36#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:31:12.36#ibcon#*before write, iclass 13, count 0 2006.210.07:31:12.36#ibcon#enter sib2, iclass 13, count 0 2006.210.07:31:12.36#ibcon#flushed, iclass 13, count 0 2006.210.07:31:12.36#ibcon#about to write, iclass 13, count 0 2006.210.07:31:12.36#ibcon#wrote, iclass 13, count 0 2006.210.07:31:12.36#ibcon#about to read 3, iclass 13, count 0 2006.210.07:31:12.40#ibcon#read 3, iclass 13, count 0 2006.210.07:31:12.40#ibcon#about to read 4, iclass 13, count 0 2006.210.07:31:12.40#ibcon#read 4, iclass 13, count 0 2006.210.07:31:12.40#ibcon#about to read 5, iclass 13, count 0 2006.210.07:31:12.40#ibcon#read 5, iclass 13, count 0 2006.210.07:31:12.40#ibcon#about to read 6, iclass 13, count 0 2006.210.07:31:12.40#ibcon#read 6, iclass 13, count 0 2006.210.07:31:12.40#ibcon#end of sib2, iclass 13, count 0 2006.210.07:31:12.40#ibcon#*after write, iclass 13, count 0 2006.210.07:31:12.40#ibcon#*before return 0, iclass 13, count 0 2006.210.07:31:12.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:12.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:31:12.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:31:12.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:31:12.40$vc4f8/vb=5,3 2006.210.07:31:12.40#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:31:12.40#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:31:12.40#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:12.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:12.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:12.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:12.46#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:31:12.46#ibcon#first serial, iclass 15, count 2 2006.210.07:31:12.46#ibcon#enter sib2, iclass 15, count 2 2006.210.07:31:12.46#ibcon#flushed, iclass 15, count 2 2006.210.07:31:12.46#ibcon#about to write, iclass 15, count 2 2006.210.07:31:12.46#ibcon#wrote, iclass 15, count 2 2006.210.07:31:12.46#ibcon#about to read 3, iclass 15, count 2 2006.210.07:31:12.48#ibcon#read 3, iclass 15, count 2 2006.210.07:31:12.48#ibcon#about to read 4, iclass 15, count 2 2006.210.07:31:12.48#ibcon#read 4, iclass 15, count 2 2006.210.07:31:12.48#ibcon#about to read 5, iclass 15, count 2 2006.210.07:31:12.48#ibcon#read 5, iclass 15, count 2 2006.210.07:31:12.48#ibcon#about to read 6, iclass 15, count 2 2006.210.07:31:12.48#ibcon#read 6, iclass 15, count 2 2006.210.07:31:12.48#ibcon#end of sib2, iclass 15, count 2 2006.210.07:31:12.48#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:31:12.48#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:31:12.48#ibcon#[27=AT05-03\r\n] 2006.210.07:31:12.48#ibcon#*before write, iclass 15, count 2 2006.210.07:31:12.48#ibcon#enter sib2, iclass 15, count 2 2006.210.07:31:12.48#ibcon#flushed, iclass 15, count 2 2006.210.07:31:12.48#ibcon#about to write, iclass 15, count 2 2006.210.07:31:12.48#ibcon#wrote, iclass 15, count 2 2006.210.07:31:12.48#ibcon#about to read 3, iclass 15, count 2 2006.210.07:31:12.51#ibcon#read 3, iclass 15, count 2 2006.210.07:31:12.51#ibcon#about to read 4, iclass 15, count 2 2006.210.07:31:12.51#ibcon#read 4, iclass 15, count 2 2006.210.07:31:12.51#ibcon#about to read 5, iclass 15, count 2 2006.210.07:31:12.51#ibcon#read 5, iclass 15, count 2 2006.210.07:31:12.51#ibcon#about to read 6, iclass 15, count 2 2006.210.07:31:12.51#ibcon#read 6, iclass 15, count 2 2006.210.07:31:12.51#ibcon#end of sib2, iclass 15, count 2 2006.210.07:31:12.51#ibcon#*after write, iclass 15, count 2 2006.210.07:31:12.51#ibcon#*before return 0, iclass 15, count 2 2006.210.07:31:12.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:12.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:31:12.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:31:12.51#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:12.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:12.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:12.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:12.63#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:31:12.63#ibcon#first serial, iclass 15, count 0 2006.210.07:31:12.63#ibcon#enter sib2, iclass 15, count 0 2006.210.07:31:12.63#ibcon#flushed, iclass 15, count 0 2006.210.07:31:12.63#ibcon#about to write, iclass 15, count 0 2006.210.07:31:12.63#ibcon#wrote, iclass 15, count 0 2006.210.07:31:12.63#ibcon#about to read 3, iclass 15, count 0 2006.210.07:31:12.65#ibcon#read 3, iclass 15, count 0 2006.210.07:31:12.65#ibcon#about to read 4, iclass 15, count 0 2006.210.07:31:12.65#ibcon#read 4, iclass 15, count 0 2006.210.07:31:12.65#ibcon#about to read 5, iclass 15, count 0 2006.210.07:31:12.65#ibcon#read 5, iclass 15, count 0 2006.210.07:31:12.65#ibcon#about to read 6, iclass 15, count 0 2006.210.07:31:12.65#ibcon#read 6, iclass 15, count 0 2006.210.07:31:12.65#ibcon#end of sib2, iclass 15, count 0 2006.210.07:31:12.65#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:31:12.65#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:31:12.65#ibcon#[27=USB\r\n] 2006.210.07:31:12.65#ibcon#*before write, iclass 15, count 0 2006.210.07:31:12.65#ibcon#enter sib2, iclass 15, count 0 2006.210.07:31:12.65#ibcon#flushed, iclass 15, count 0 2006.210.07:31:12.65#ibcon#about to write, iclass 15, count 0 2006.210.07:31:12.65#ibcon#wrote, iclass 15, count 0 2006.210.07:31:12.65#ibcon#about to read 3, iclass 15, count 0 2006.210.07:31:12.68#ibcon#read 3, iclass 15, count 0 2006.210.07:31:12.68#ibcon#about to read 4, iclass 15, count 0 2006.210.07:31:12.68#ibcon#read 4, iclass 15, count 0 2006.210.07:31:12.68#ibcon#about to read 5, iclass 15, count 0 2006.210.07:31:12.68#ibcon#read 5, iclass 15, count 0 2006.210.07:31:12.68#ibcon#about to read 6, iclass 15, count 0 2006.210.07:31:12.68#ibcon#read 6, iclass 15, count 0 2006.210.07:31:12.68#ibcon#end of sib2, iclass 15, count 0 2006.210.07:31:12.68#ibcon#*after write, iclass 15, count 0 2006.210.07:31:12.68#ibcon#*before return 0, iclass 15, count 0 2006.210.07:31:12.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:12.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:31:12.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:31:12.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:31:12.68$vc4f8/vblo=6,752.99 2006.210.07:31:12.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:31:12.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:31:12.68#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:12.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:12.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:12.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:12.68#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:31:12.68#ibcon#first serial, iclass 17, count 0 2006.210.07:31:12.68#ibcon#enter sib2, iclass 17, count 0 2006.210.07:31:12.68#ibcon#flushed, iclass 17, count 0 2006.210.07:31:12.68#ibcon#about to write, iclass 17, count 0 2006.210.07:31:12.68#ibcon#wrote, iclass 17, count 0 2006.210.07:31:12.68#ibcon#about to read 3, iclass 17, count 0 2006.210.07:31:12.70#ibcon#read 3, iclass 17, count 0 2006.210.07:31:12.70#ibcon#about to read 4, iclass 17, count 0 2006.210.07:31:12.70#ibcon#read 4, iclass 17, count 0 2006.210.07:31:12.70#ibcon#about to read 5, iclass 17, count 0 2006.210.07:31:12.70#ibcon#read 5, iclass 17, count 0 2006.210.07:31:12.70#ibcon#about to read 6, iclass 17, count 0 2006.210.07:31:12.70#ibcon#read 6, iclass 17, count 0 2006.210.07:31:12.70#ibcon#end of sib2, iclass 17, count 0 2006.210.07:31:12.70#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:31:12.70#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:31:12.70#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:31:12.70#ibcon#*before write, iclass 17, count 0 2006.210.07:31:12.70#ibcon#enter sib2, iclass 17, count 0 2006.210.07:31:12.70#ibcon#flushed, iclass 17, count 0 2006.210.07:31:12.70#ibcon#about to write, iclass 17, count 0 2006.210.07:31:12.70#ibcon#wrote, iclass 17, count 0 2006.210.07:31:12.70#ibcon#about to read 3, iclass 17, count 0 2006.210.07:31:12.74#ibcon#read 3, iclass 17, count 0 2006.210.07:31:12.74#ibcon#about to read 4, iclass 17, count 0 2006.210.07:31:12.74#ibcon#read 4, iclass 17, count 0 2006.210.07:31:12.74#ibcon#about to read 5, iclass 17, count 0 2006.210.07:31:12.74#ibcon#read 5, iclass 17, count 0 2006.210.07:31:12.74#ibcon#about to read 6, iclass 17, count 0 2006.210.07:31:12.74#ibcon#read 6, iclass 17, count 0 2006.210.07:31:12.74#ibcon#end of sib2, iclass 17, count 0 2006.210.07:31:12.74#ibcon#*after write, iclass 17, count 0 2006.210.07:31:12.74#ibcon#*before return 0, iclass 17, count 0 2006.210.07:31:12.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:12.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:31:12.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:31:12.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:31:12.74$vc4f8/vb=6,3 2006.210.07:31:12.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:31:12.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:31:12.74#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:12.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:12.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:12.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:12.80#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:31:12.80#ibcon#first serial, iclass 19, count 2 2006.210.07:31:12.80#ibcon#enter sib2, iclass 19, count 2 2006.210.07:31:12.80#ibcon#flushed, iclass 19, count 2 2006.210.07:31:12.80#ibcon#about to write, iclass 19, count 2 2006.210.07:31:12.80#ibcon#wrote, iclass 19, count 2 2006.210.07:31:12.80#ibcon#about to read 3, iclass 19, count 2 2006.210.07:31:12.82#ibcon#read 3, iclass 19, count 2 2006.210.07:31:12.82#ibcon#about to read 4, iclass 19, count 2 2006.210.07:31:12.82#ibcon#read 4, iclass 19, count 2 2006.210.07:31:12.82#ibcon#about to read 5, iclass 19, count 2 2006.210.07:31:12.82#ibcon#read 5, iclass 19, count 2 2006.210.07:31:12.82#ibcon#about to read 6, iclass 19, count 2 2006.210.07:31:12.82#ibcon#read 6, iclass 19, count 2 2006.210.07:31:12.82#ibcon#end of sib2, iclass 19, count 2 2006.210.07:31:12.82#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:31:12.82#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:31:12.82#ibcon#[27=AT06-03\r\n] 2006.210.07:31:12.82#ibcon#*before write, iclass 19, count 2 2006.210.07:31:12.82#ibcon#enter sib2, iclass 19, count 2 2006.210.07:31:12.82#ibcon#flushed, iclass 19, count 2 2006.210.07:31:12.82#ibcon#about to write, iclass 19, count 2 2006.210.07:31:12.82#ibcon#wrote, iclass 19, count 2 2006.210.07:31:12.82#ibcon#about to read 3, iclass 19, count 2 2006.210.07:31:12.85#ibcon#read 3, iclass 19, count 2 2006.210.07:31:12.85#ibcon#about to read 4, iclass 19, count 2 2006.210.07:31:12.85#ibcon#read 4, iclass 19, count 2 2006.210.07:31:12.85#ibcon#about to read 5, iclass 19, count 2 2006.210.07:31:12.85#ibcon#read 5, iclass 19, count 2 2006.210.07:31:12.85#ibcon#about to read 6, iclass 19, count 2 2006.210.07:31:12.85#ibcon#read 6, iclass 19, count 2 2006.210.07:31:12.85#ibcon#end of sib2, iclass 19, count 2 2006.210.07:31:12.85#ibcon#*after write, iclass 19, count 2 2006.210.07:31:12.85#ibcon#*before return 0, iclass 19, count 2 2006.210.07:31:12.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:12.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:31:12.85#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:31:12.85#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:12.85#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:12.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:12.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:12.97#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:31:12.97#ibcon#first serial, iclass 19, count 0 2006.210.07:31:12.97#ibcon#enter sib2, iclass 19, count 0 2006.210.07:31:12.97#ibcon#flushed, iclass 19, count 0 2006.210.07:31:12.97#ibcon#about to write, iclass 19, count 0 2006.210.07:31:12.97#ibcon#wrote, iclass 19, count 0 2006.210.07:31:12.97#ibcon#about to read 3, iclass 19, count 0 2006.210.07:31:12.99#ibcon#read 3, iclass 19, count 0 2006.210.07:31:12.99#ibcon#about to read 4, iclass 19, count 0 2006.210.07:31:12.99#ibcon#read 4, iclass 19, count 0 2006.210.07:31:12.99#ibcon#about to read 5, iclass 19, count 0 2006.210.07:31:12.99#ibcon#read 5, iclass 19, count 0 2006.210.07:31:12.99#ibcon#about to read 6, iclass 19, count 0 2006.210.07:31:12.99#ibcon#read 6, iclass 19, count 0 2006.210.07:31:12.99#ibcon#end of sib2, iclass 19, count 0 2006.210.07:31:12.99#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:31:12.99#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:31:12.99#ibcon#[27=USB\r\n] 2006.210.07:31:12.99#ibcon#*before write, iclass 19, count 0 2006.210.07:31:12.99#ibcon#enter sib2, iclass 19, count 0 2006.210.07:31:12.99#ibcon#flushed, iclass 19, count 0 2006.210.07:31:12.99#ibcon#about to write, iclass 19, count 0 2006.210.07:31:12.99#ibcon#wrote, iclass 19, count 0 2006.210.07:31:12.99#ibcon#about to read 3, iclass 19, count 0 2006.210.07:31:13.02#ibcon#read 3, iclass 19, count 0 2006.210.07:31:13.02#ibcon#about to read 4, iclass 19, count 0 2006.210.07:31:13.02#ibcon#read 4, iclass 19, count 0 2006.210.07:31:13.02#ibcon#about to read 5, iclass 19, count 0 2006.210.07:31:13.02#ibcon#read 5, iclass 19, count 0 2006.210.07:31:13.02#ibcon#about to read 6, iclass 19, count 0 2006.210.07:31:13.02#ibcon#read 6, iclass 19, count 0 2006.210.07:31:13.02#ibcon#end of sib2, iclass 19, count 0 2006.210.07:31:13.02#ibcon#*after write, iclass 19, count 0 2006.210.07:31:13.02#ibcon#*before return 0, iclass 19, count 0 2006.210.07:31:13.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:13.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:31:13.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:31:13.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:31:13.02$vc4f8/vabw=wide 2006.210.07:31:13.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:31:13.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:31:13.02#ibcon#ireg 8 cls_cnt 0 2006.210.07:31:13.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:13.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:13.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:13.02#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:31:13.02#ibcon#first serial, iclass 21, count 0 2006.210.07:31:13.02#ibcon#enter sib2, iclass 21, count 0 2006.210.07:31:13.02#ibcon#flushed, iclass 21, count 0 2006.210.07:31:13.02#ibcon#about to write, iclass 21, count 0 2006.210.07:31:13.02#ibcon#wrote, iclass 21, count 0 2006.210.07:31:13.02#ibcon#about to read 3, iclass 21, count 0 2006.210.07:31:13.04#ibcon#read 3, iclass 21, count 0 2006.210.07:31:13.04#ibcon#about to read 4, iclass 21, count 0 2006.210.07:31:13.04#ibcon#read 4, iclass 21, count 0 2006.210.07:31:13.04#ibcon#about to read 5, iclass 21, count 0 2006.210.07:31:13.04#ibcon#read 5, iclass 21, count 0 2006.210.07:31:13.04#ibcon#about to read 6, iclass 21, count 0 2006.210.07:31:13.04#ibcon#read 6, iclass 21, count 0 2006.210.07:31:13.04#ibcon#end of sib2, iclass 21, count 0 2006.210.07:31:13.04#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:31:13.04#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:31:13.04#ibcon#[25=BW32\r\n] 2006.210.07:31:13.04#ibcon#*before write, iclass 21, count 0 2006.210.07:31:13.04#ibcon#enter sib2, iclass 21, count 0 2006.210.07:31:13.04#ibcon#flushed, iclass 21, count 0 2006.210.07:31:13.04#ibcon#about to write, iclass 21, count 0 2006.210.07:31:13.04#ibcon#wrote, iclass 21, count 0 2006.210.07:31:13.04#ibcon#about to read 3, iclass 21, count 0 2006.210.07:31:13.07#ibcon#read 3, iclass 21, count 0 2006.210.07:31:13.07#ibcon#about to read 4, iclass 21, count 0 2006.210.07:31:13.07#ibcon#read 4, iclass 21, count 0 2006.210.07:31:13.07#ibcon#about to read 5, iclass 21, count 0 2006.210.07:31:13.07#ibcon#read 5, iclass 21, count 0 2006.210.07:31:13.07#ibcon#about to read 6, iclass 21, count 0 2006.210.07:31:13.07#ibcon#read 6, iclass 21, count 0 2006.210.07:31:13.07#ibcon#end of sib2, iclass 21, count 0 2006.210.07:31:13.07#ibcon#*after write, iclass 21, count 0 2006.210.07:31:13.07#ibcon#*before return 0, iclass 21, count 0 2006.210.07:31:13.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:13.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:31:13.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:31:13.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:31:13.07$vc4f8/vbbw=wide 2006.210.07:31:13.07#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.07:31:13.07#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.07:31:13.07#ibcon#ireg 8 cls_cnt 0 2006.210.07:31:13.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:31:13.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:31:13.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:31:13.14#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:31:13.14#ibcon#first serial, iclass 23, count 0 2006.210.07:31:13.14#ibcon#enter sib2, iclass 23, count 0 2006.210.07:31:13.14#ibcon#flushed, iclass 23, count 0 2006.210.07:31:13.14#ibcon#about to write, iclass 23, count 0 2006.210.07:31:13.14#ibcon#wrote, iclass 23, count 0 2006.210.07:31:13.14#ibcon#about to read 3, iclass 23, count 0 2006.210.07:31:13.16#ibcon#read 3, iclass 23, count 0 2006.210.07:31:13.16#ibcon#about to read 4, iclass 23, count 0 2006.210.07:31:13.16#ibcon#read 4, iclass 23, count 0 2006.210.07:31:13.16#ibcon#about to read 5, iclass 23, count 0 2006.210.07:31:13.16#ibcon#read 5, iclass 23, count 0 2006.210.07:31:13.16#ibcon#about to read 6, iclass 23, count 0 2006.210.07:31:13.16#ibcon#read 6, iclass 23, count 0 2006.210.07:31:13.16#ibcon#end of sib2, iclass 23, count 0 2006.210.07:31:13.16#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:31:13.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:31:13.16#ibcon#[27=BW32\r\n] 2006.210.07:31:13.16#ibcon#*before write, iclass 23, count 0 2006.210.07:31:13.16#ibcon#enter sib2, iclass 23, count 0 2006.210.07:31:13.16#ibcon#flushed, iclass 23, count 0 2006.210.07:31:13.16#ibcon#about to write, iclass 23, count 0 2006.210.07:31:13.16#ibcon#wrote, iclass 23, count 0 2006.210.07:31:13.16#ibcon#about to read 3, iclass 23, count 0 2006.210.07:31:13.19#ibcon#read 3, iclass 23, count 0 2006.210.07:31:13.19#ibcon#about to read 4, iclass 23, count 0 2006.210.07:31:13.19#ibcon#read 4, iclass 23, count 0 2006.210.07:31:13.19#ibcon#about to read 5, iclass 23, count 0 2006.210.07:31:13.19#ibcon#read 5, iclass 23, count 0 2006.210.07:31:13.19#ibcon#about to read 6, iclass 23, count 0 2006.210.07:31:13.19#ibcon#read 6, iclass 23, count 0 2006.210.07:31:13.19#ibcon#end of sib2, iclass 23, count 0 2006.210.07:31:13.19#ibcon#*after write, iclass 23, count 0 2006.210.07:31:13.19#ibcon#*before return 0, iclass 23, count 0 2006.210.07:31:13.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:31:13.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:31:13.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:31:13.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:31:13.19$4f8m12a/ifd4f 2006.210.07:31:13.19$ifd4f/lo= 2006.210.07:31:13.19$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:31:13.19$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:31:13.19$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:31:13.19$ifd4f/patch= 2006.210.07:31:13.19$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:31:13.19$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:31:13.19$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:31:13.19$4f8m12a/"form=m,16.000,1:2 2006.210.07:31:13.19$4f8m12a/"tpicd 2006.210.07:31:13.19$4f8m12a/echo=off 2006.210.07:31:13.19$4f8m12a/xlog=off 2006.210.07:31:13.19:!2006.210.07:33:20 2006.210.07:31:53.14#trakl#Source acquired 2006.210.07:31:54.14#flagr#flagr/antenna,acquired 2006.210.07:32:06.05;halt 2006.210.07:32:14.55;killautoobs 2006.210.07:32:18.59/killautoobs//k5ts1/ autoobs was killed! //k5ts2/ autoobs was killed! //k5ts3/ autoobs was killed! //k5ts4/ autoobs was killed! 2006.210.07:32:22.95;source=idle 2006.210.07:32:23.14#flagr#flagr/antenna,new-source 2006.210.07:32:31.23;schedule=k06210ts,#332 2006.210.07:32:31.23:" K06210 2006 TSUKUB32 T Ts 2006.210.07:32:31.23:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.210.07:32:31.23:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.210.07:32:31.23:" 108 TSUKUB32 14 17400 2006.210.07:32:31.23:" drudg version 050216 compiled under FS 9.7.07 2006.210.07:32:31.23:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.210.07:32:31.23:exper_initi 2006.210.07:32:31.23&exper_initi/proc_library 2006.210.07:32:31.23&exper_initi/sched_initi 2006.210.07:32:31.23:!2006.210.08:27:20 2006.210.07:32:31.23&proc_library/" k06210 tsukub32 ts 2006.210.07:32:31.23&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.210.07:32:31.23&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.210.07:32:31.23&startcheck/sy=check_fsrun.pl & 2006.210.07:32:31.23&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.210.07:33:10.10;sy=run setcl offset & 2006.210.07:33:10.19#setcl#time/60668302,0,2006,210,08,27,13.13,511333.094,0.152,324300 2006.210.07:33:10.20#setcl#model/old,1153459626,9208111,60613505,-0.364,101.533,rate,0,sync,9208395,9532695 2006.210.08:27:13.20#setcl#model/new,1153459626,9532411,60668302,-0.364,101.533,rate,0 2006.210.08:27:19.55;wx 2006.210.08:27:19.55/wx/27.69,1006.2,90 2006.210.08:27:20.00:data_valid=off 2006.210.08:27:20.00:postob 2006.210.08:27:20.09/cable/+6.4246E-03 2006.210.08:27:20.09?ERROR st -94 No new wx data since last report 2006.210.08:27:21.03/fmout-gps/S +4.62E-07 2006.210.08:27:21.03:checkk5last 2006.210.08:27:21.03&checkk5last/chk_obsdata=1 2006.210.08:27:21.03&checkk5last/chk_obsdata=2 2006.210.08:27:21.03&checkk5last/chk_obsdata=3 2006.210.08:27:21.03&checkk5last/chk_obsdata=4 2006.210.08:27:21.03&checkk5last/k5log=1 2006.210.08:27:21.03&checkk5last/k5log=2 2006.210.08:27:21.03&checkk5last/k5log=3 2006.210.08:27:21.03&checkk5last/k5log=4 2006.210.08:27:21.03&checkk5last/obsinfo 2006.210.08:27:21.40/chk_obsdata//k5ts1?ERROR: no T2100733??a.dat file! 2006.210.08:27:21.78/chk_obsdata//k5ts2?ERROR: no T2100733??b.dat file! 2006.210.08:27:22.14/chk_obsdata//k5ts3?ERROR: no T2100733??c.dat file! 2006.210.08:27:22.57/chk_obsdata//k5ts4?ERROR: no T2100733??d.dat file! 2006.210.08:27:23.30/k5log//k5ts1_log_newline 2006.210.08:27:24.02/k5log//k5ts2_log_newline 2006.210.08:27:24.89/k5log//k5ts3_log_newline 2006.210.08:27:25.64/k5log//k5ts4_log_newline 2006.210.08:27:25.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:27:25.84:"sched_end 2006.210.08:27:25.84:source=idle 2006.210.08:27:26.14:stow 2006.210.08:27:26.14&stow/source=idle 2006.210.08:27:26.14&stow/"this is stow command. 2006.210.08:27:26.14&stow/antenna=m3 2006.210.08:27:29.01:!+10m 2006.210.08:29:38.60;sy=run setcl offset & 2006.210.08:29:38.68#setcl#time/60682851,0,2006,210,08,37,23.62,276142.687,0.040,46500 2006.210.08:29:38.68#setcl#model/old,1153459626,9532411,60668302,-0.364,101.533,rate,0,sync,9532695,9579195 2006.210.08:37:23.68#setcl#model/new,1153459626,9578911,60682851,-0.364,101.533,rate,0 2006.210.08:37:24.65;wx 2006.210.08:37:24.65/wx/27.67,1006.3,90 2006.210.08:37:29.02:standby 2006.210.08:37:29.02&standby/"this is standby command. 2006.210.08:37:29.02&standby/antenna=m0 2006.210.08:37:30.01:checkk5hdd 2006.210.08:37:30.01&checkk5hdd/chk_hdd=1 2006.210.08:37:30.01&checkk5hdd/chk_hdd=2 2006.210.08:37:30.01&checkk5hdd/chk_hdd=3 2006.210.08:37:30.01&checkk5hdd/chk_hdd=4 2006.210.08:37:33.50/chk_hdd//k5ts1/GSI00275:T210073000a.dat~[472055808Byte] 2006.210.08:37:37.20/chk_hdd//k5ts2/GSI00163:T210073000b.dat~[472055808Byte] 2006.210.08:37:40.58/chk_hdd//k5ts3/GSI00278:T210073000c.dat~[472055808Byte] 2006.210.08:37:44.10/chk_hdd//k5ts4/GSI00220:T210073000d.dat~[472055808Byte] 2006.210.08:37:44.10:sy=cp /usr2/log/k06210ts.log /usr2/log_backup/ 2006.210.08:37:44.19:log=u06211ts 2006.211.03:46:35.09;Log Opened: Mark IV Field System Version 9.7.7 2006.211.03:46:35.09;location,TSUKUB32,-140.09,36.10,61.0 2006.211.03:46:35.09;horizon1,0.,5.,360. 2006.211.03:46:35.09;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.211.03:46:35.09;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.211.03:46:35.09;drivev11,330,270,no 2006.211.03:46:35.09;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.211.03:46:35.09;drivev13,15.000,268,10.000,10.000,10.000 2006.211.03:46:35.09;drivev21,330,270,no 2006.211.03:46:35.09;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.211.03:46:35.09;drivev23,15.000,268,10.000,10.000,10.000 2006.211.03:46:35.09;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.211.03:46:35.09;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.211.03:46:35.09;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.211.03:46:35.09;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.211.03:46:35.09;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.211.03:46:35.09;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.211.03:46:35.09;time,-0.364,101.533,rate 2006.211.03:46:35.09;flagr,200 2006.211.03:46:35.09:" K06210 2006 TSUKUB32 T Ts 2006.211.03:46:35.09:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.211.03:46:35.09:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.211.03:46:35.09:" 108 TSUKUB32 14 17400 2006.211.03:46:35.09:" drudg version 050216 compiled under FS 9.7.07 2006.211.03:46:35.09:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.211.03:46:35.09:exper_initi 2006.211.03:46:35.09&exper_initi/proc_library 2006.211.03:46:35.09&exper_initi/sched_initi 2006.211.03:46:35.09:!2006.211.06:57:00 2006.211.03:46:35.09&proc_library/" k06210 tsukub32 ts 2006.211.03:46:35.09&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.211.03:46:35.09&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.211.03:46:35.09&sched_initi/startcheck 2006.211.03:46:35.09&startcheck/sy=check_fsrun.pl & 2006.211.03:46:35.09&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.211.03:46:51.86;source=idle 2006.211.03:46:51.86#antcn#PM 1 00019 2005 228 00 22 31 00 2006.211.03:46:51.86#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.211.03:46:51.86#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.211.03:46:51.86#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.211.03:46:51.86#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.211.03:46:51.86#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.211.03:46:52.14#flagr#flagr/antenna,new-source 2006.211.03:47:27.71;sy=run setcl offset & 2006.211.03:47:27.79#setcl#time/60750763,0,2006,211,07,23,07.74,$$$$$$$$$$,0.073,1294001 2006.211.03:47:27.79#setcl#model/old,1153459626,16411410,60724312,-0.364,101.533,rate,0,sync,16411694,17705695 2006.211.07:23:07.81#setcl#model/new,1153459626,17705411,60750763,-0.364,101.533,rate,0 2006.211.07:23:09.42:data_valid=off 2006.211.07:23:09.42:postob 2006.211.07:23:09.42&postob/cable 2006.211.07:23:09.42&postob/wx 2006.211.07:23:09.42&postob/clockoff 2006.211.07:23:09.50/cable/+6.4241E-03 2006.211.07:23:09.50/wx/27.54,1006.2,89 2006.211.07:23:09.50&clockoff/"gps-fmout=1p 2006.211.07:23:09.50&clockoff/fmout-gps=1p 2006.211.07:23:09.56/fmout-gps/S +4.56E-07 2006.211.07:23:09.56:scan_name=211-0700,u06211,2580 2006.211.07:23:09.56:source=m87,123049.42,122328.0,2000.0,neutral 2006.211.07:23:11.14:4f8m12a=1 2006.211.07:23:11.14&4f8m12a/xlog=on 2006.211.07:23:11.14&4f8m12a/echo=on 2006.211.07:23:11.14&4f8m12a/pcalon 2006.211.07:23:11.14&4f8m12a/"tpicd=stop 2006.211.07:23:11.14&4f8m12a/vc4f8 2006.211.07:23:11.14&4f8m12a/ifd4f 2006.211.07:23:11.14&4f8m12a/"form=m,16.000,1:2 2006.211.07:23:11.14&4f8m12a/"tpicd 2006.211.07:23:11.14&4f8m12a/echo=off 2006.211.07:23:11.14&4f8m12a/xlog=off 2006.211.07:23:11.14$4f8m12a/echo=on 2006.211.07:23:11.14$4f8m12a/pcalon 2006.211.07:23:11.14&pcalon/"no phase cal control is implemented here 2006.211.07:23:11.14$pcalon/"no phase cal control is implemented here 2006.211.07:23:11.14$4f8m12a/"tpicd=stop 2006.211.07:23:11.14$4f8m12a/vc4f8 2006.211.07:23:11.14&vc4f8/valo=1,532.99 2006.211.07:23:11.14&vc4f8/va=1,8 2006.211.07:23:11.14&vc4f8/valo=2,572.99 2006.211.07:23:11.14&vc4f8/va=2,7 2006.211.07:23:11.14&vc4f8/valo=3,672.99 2006.211.07:23:11.14&vc4f8/va=3,6 2006.211.07:23:11.14&vc4f8/valo=4,832.99 2006.211.07:23:11.14&vc4f8/va=4,7 2006.211.07:23:11.14&vc4f8/valo=5,652.99 2006.211.07:23:11.14&vc4f8/va=5,7 2006.211.07:23:11.14&vc4f8/valo=6,772.99 2006.211.07:23:11.14&vc4f8/va=6,6 2006.211.07:23:11.14&vc4f8/valo=7,832.99 2006.211.07:23:11.14&vc4f8/va=7,6 2006.211.07:23:11.14&vc4f8/valo=8,852.99 2006.211.07:23:11.14&vc4f8/va=8,7 2006.211.07:23:11.14&vc4f8/vblo=1,632.99 2006.211.07:23:11.14&vc4f8/vb=1,4 2006.211.07:23:11.14&vc4f8/vblo=2,640.99 2006.211.07:23:11.14&vc4f8/vb=2,4 2006.211.07:23:11.14&vc4f8/vblo=3,656.99 2006.211.07:23:11.14&vc4f8/vb=3,3 2006.211.07:23:11.14&vc4f8/vblo=4,712.99 2006.211.07:23:11.14&vc4f8/vb=4,3 2006.211.07:23:11.14&vc4f8/vblo=5,744.99 2006.211.07:23:11.14&vc4f8/vb=5,3 2006.211.07:23:11.14&vc4f8/vblo=6,752.99 2006.211.07:23:11.14&vc4f8/vb=6,3 2006.211.07:23:11.14&vc4f8/vabw=wide 2006.211.07:23:11.14&vc4f8/vbbw=wide 2006.211.07:23:11.14$vc4f8/valo=1,532.99 2006.211.07:23:11.14#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.07:23:11.14#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.07:23:11.14#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:11.14#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:23:11.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:23:11.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:23:11.14#ibcon#enter wrdev, iclass 4, count 0 2006.211.07:23:11.14#ibcon#first serial, iclass 4, count 0 2006.211.07:23:11.14#ibcon#enter sib2, iclass 4, count 0 2006.211.07:23:11.14#ibcon#flushed, iclass 4, count 0 2006.211.07:23:11.14#ibcon#about to write, iclass 4, count 0 2006.211.07:23:11.14#ibcon#wrote, iclass 4, count 0 2006.211.07:23:11.14#ibcon#about to read 3, iclass 4, count 0 2006.211.07:23:11.14#flagr#flagr/antenna,new-source 2006.211.07:23:11.16#ibcon#read 3, iclass 4, count 0 2006.211.07:23:11.16#ibcon#about to read 4, iclass 4, count 0 2006.211.07:23:11.16#ibcon#read 4, iclass 4, count 0 2006.211.07:23:11.16#ibcon#about to read 5, iclass 4, count 0 2006.211.07:23:11.16#ibcon#read 5, iclass 4, count 0 2006.211.07:23:11.16#ibcon#about to read 6, iclass 4, count 0 2006.211.07:23:11.16#ibcon#read 6, iclass 4, count 0 2006.211.07:23:11.16#ibcon#end of sib2, iclass 4, count 0 2006.211.07:23:11.16#ibcon#*mode == 0, iclass 4, count 0 2006.211.07:23:11.16#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.07:23:11.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.07:23:11.16#ibcon#*before write, iclass 4, count 0 2006.211.07:23:11.16#ibcon#enter sib2, iclass 4, count 0 2006.211.07:23:11.16#ibcon#flushed, iclass 4, count 0 2006.211.07:23:11.16#ibcon#about to write, iclass 4, count 0 2006.211.07:23:11.16#ibcon#wrote, iclass 4, count 0 2006.211.07:23:11.16#ibcon#about to read 3, iclass 4, count 0 2006.211.07:23:11.21#ibcon#read 3, iclass 4, count 0 2006.211.07:23:11.21#ibcon#about to read 4, iclass 4, count 0 2006.211.07:23:11.21#ibcon#read 4, iclass 4, count 0 2006.211.07:23:11.21#ibcon#about to read 5, iclass 4, count 0 2006.211.07:23:11.21#ibcon#read 5, iclass 4, count 0 2006.211.07:23:11.21#ibcon#about to read 6, iclass 4, count 0 2006.211.07:23:11.21#ibcon#read 6, iclass 4, count 0 2006.211.07:23:11.21#ibcon#end of sib2, iclass 4, count 0 2006.211.07:23:11.21#ibcon#*after write, iclass 4, count 0 2006.211.07:23:11.21#ibcon#*before return 0, iclass 4, count 0 2006.211.07:23:11.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:23:11.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.07:23:11.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.07:23:11.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.07:23:11.21$vc4f8/va=1,8 2006.211.07:23:11.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.07:23:11.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.07:23:11.21#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:11.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:23:11.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:23:11.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:23:11.21#ibcon#enter wrdev, iclass 6, count 2 2006.211.07:23:11.21#ibcon#first serial, iclass 6, count 2 2006.211.07:23:11.21#ibcon#enter sib2, iclass 6, count 2 2006.211.07:23:11.21#ibcon#flushed, iclass 6, count 2 2006.211.07:23:11.21#ibcon#about to write, iclass 6, count 2 2006.211.07:23:11.21#ibcon#wrote, iclass 6, count 2 2006.211.07:23:11.21#ibcon#about to read 3, iclass 6, count 2 2006.211.07:23:11.23#ibcon#read 3, iclass 6, count 2 2006.211.07:23:11.23#ibcon#about to read 4, iclass 6, count 2 2006.211.07:23:11.23#ibcon#read 4, iclass 6, count 2 2006.211.07:23:11.23#ibcon#about to read 5, iclass 6, count 2 2006.211.07:23:11.23#ibcon#read 5, iclass 6, count 2 2006.211.07:23:11.23#ibcon#about to read 6, iclass 6, count 2 2006.211.07:23:11.23#ibcon#read 6, iclass 6, count 2 2006.211.07:23:11.23#ibcon#end of sib2, iclass 6, count 2 2006.211.07:23:11.23#ibcon#*mode == 0, iclass 6, count 2 2006.211.07:23:11.23#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.07:23:11.23#ibcon#[25=AT01-08\r\n] 2006.211.07:23:11.23#ibcon#*before write, iclass 6, count 2 2006.211.07:23:11.23#ibcon#enter sib2, iclass 6, count 2 2006.211.07:23:11.23#ibcon#flushed, iclass 6, count 2 2006.211.07:23:11.23#ibcon#about to write, iclass 6, count 2 2006.211.07:23:11.23#ibcon#wrote, iclass 6, count 2 2006.211.07:23:11.23#ibcon#about to read 3, iclass 6, count 2 2006.211.07:23:11.26#ibcon#read 3, iclass 6, count 2 2006.211.07:23:11.26#ibcon#about to read 4, iclass 6, count 2 2006.211.07:23:11.26#ibcon#read 4, iclass 6, count 2 2006.211.07:23:11.26#ibcon#about to read 5, iclass 6, count 2 2006.211.07:23:11.26#ibcon#read 5, iclass 6, count 2 2006.211.07:23:11.26#ibcon#about to read 6, iclass 6, count 2 2006.211.07:23:11.26#ibcon#read 6, iclass 6, count 2 2006.211.07:23:11.26#ibcon#end of sib2, iclass 6, count 2 2006.211.07:23:11.26#ibcon#*after write, iclass 6, count 2 2006.211.07:23:11.26#ibcon#*before return 0, iclass 6, count 2 2006.211.07:23:11.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:23:11.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.07:23:11.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.07:23:11.26#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:11.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:23:11.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:23:11.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:23:11.38#ibcon#enter wrdev, iclass 6, count 0 2006.211.07:23:11.38#ibcon#first serial, iclass 6, count 0 2006.211.07:23:11.38#ibcon#enter sib2, iclass 6, count 0 2006.211.07:23:11.38#ibcon#flushed, iclass 6, count 0 2006.211.07:23:11.38#ibcon#about to write, iclass 6, count 0 2006.211.07:23:11.38#ibcon#wrote, iclass 6, count 0 2006.211.07:23:11.38#ibcon#about to read 3, iclass 6, count 0 2006.211.07:23:11.40#ibcon#read 3, iclass 6, count 0 2006.211.07:23:11.40#ibcon#about to read 4, iclass 6, count 0 2006.211.07:23:11.40#ibcon#read 4, iclass 6, count 0 2006.211.07:23:11.40#ibcon#about to read 5, iclass 6, count 0 2006.211.07:23:11.40#ibcon#read 5, iclass 6, count 0 2006.211.07:23:11.40#ibcon#about to read 6, iclass 6, count 0 2006.211.07:23:11.40#ibcon#read 6, iclass 6, count 0 2006.211.07:23:11.40#ibcon#end of sib2, iclass 6, count 0 2006.211.07:23:11.40#ibcon#*mode == 0, iclass 6, count 0 2006.211.07:23:11.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.07:23:11.40#ibcon#[25=USB\r\n] 2006.211.07:23:11.40#ibcon#*before write, iclass 6, count 0 2006.211.07:23:11.40#ibcon#enter sib2, iclass 6, count 0 2006.211.07:23:11.40#ibcon#flushed, iclass 6, count 0 2006.211.07:23:11.40#ibcon#about to write, iclass 6, count 0 2006.211.07:23:11.40#ibcon#wrote, iclass 6, count 0 2006.211.07:23:11.40#ibcon#about to read 3, iclass 6, count 0 2006.211.07:23:11.43#ibcon#read 3, iclass 6, count 0 2006.211.07:23:11.43#ibcon#about to read 4, iclass 6, count 0 2006.211.07:23:11.43#ibcon#read 4, iclass 6, count 0 2006.211.07:23:11.43#ibcon#about to read 5, iclass 6, count 0 2006.211.07:23:11.43#ibcon#read 5, iclass 6, count 0 2006.211.07:23:11.43#ibcon#about to read 6, iclass 6, count 0 2006.211.07:23:11.43#ibcon#read 6, iclass 6, count 0 2006.211.07:23:11.43#ibcon#end of sib2, iclass 6, count 0 2006.211.07:23:11.43#ibcon#*after write, iclass 6, count 0 2006.211.07:23:11.43#ibcon#*before return 0, iclass 6, count 0 2006.211.07:23:11.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:23:11.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.07:23:11.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.07:23:11.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.07:23:11.43$vc4f8/valo=2,572.99 2006.211.07:23:11.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.07:23:11.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.07:23:11.43#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:11.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:23:11.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:23:11.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:23:11.43#ibcon#enter wrdev, iclass 10, count 0 2006.211.07:23:11.43#ibcon#first serial, iclass 10, count 0 2006.211.07:23:11.43#ibcon#enter sib2, iclass 10, count 0 2006.211.07:23:11.43#ibcon#flushed, iclass 10, count 0 2006.211.07:23:11.43#ibcon#about to write, iclass 10, count 0 2006.211.07:23:11.43#ibcon#wrote, iclass 10, count 0 2006.211.07:23:11.43#ibcon#about to read 3, iclass 10, count 0 2006.211.07:23:11.45#ibcon#read 3, iclass 10, count 0 2006.211.07:23:11.45#ibcon#about to read 4, iclass 10, count 0 2006.211.07:23:11.45#ibcon#read 4, iclass 10, count 0 2006.211.07:23:11.45#ibcon#about to read 5, iclass 10, count 0 2006.211.07:23:11.45#ibcon#read 5, iclass 10, count 0 2006.211.07:23:11.45#ibcon#about to read 6, iclass 10, count 0 2006.211.07:23:11.45#ibcon#read 6, iclass 10, count 0 2006.211.07:23:11.45#ibcon#end of sib2, iclass 10, count 0 2006.211.07:23:11.45#ibcon#*mode == 0, iclass 10, count 0 2006.211.07:23:11.45#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.07:23:11.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.07:23:11.45#ibcon#*before write, iclass 10, count 0 2006.211.07:23:11.45#ibcon#enter sib2, iclass 10, count 0 2006.211.07:23:11.45#ibcon#flushed, iclass 10, count 0 2006.211.07:23:11.45#ibcon#about to write, iclass 10, count 0 2006.211.07:23:11.45#ibcon#wrote, iclass 10, count 0 2006.211.07:23:11.45#ibcon#about to read 3, iclass 10, count 0 2006.211.07:23:11.49#ibcon#read 3, iclass 10, count 0 2006.211.07:23:11.49#ibcon#about to read 4, iclass 10, count 0 2006.211.07:23:11.49#ibcon#read 4, iclass 10, count 0 2006.211.07:23:11.49#ibcon#about to read 5, iclass 10, count 0 2006.211.07:23:11.49#ibcon#read 5, iclass 10, count 0 2006.211.07:23:11.49#ibcon#about to read 6, iclass 10, count 0 2006.211.07:23:11.49#ibcon#read 6, iclass 10, count 0 2006.211.07:23:11.49#ibcon#end of sib2, iclass 10, count 0 2006.211.07:23:11.49#ibcon#*after write, iclass 10, count 0 2006.211.07:23:11.49#ibcon#*before return 0, iclass 10, count 0 2006.211.07:23:11.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:23:11.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.07:23:11.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.07:23:11.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.07:23:11.49$vc4f8/va=2,7 2006.211.07:23:11.49#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.07:23:11.49#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.07:23:11.49#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:11.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:23:11.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:23:11.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:23:11.55#ibcon#enter wrdev, iclass 12, count 2 2006.211.07:23:11.55#ibcon#first serial, iclass 12, count 2 2006.211.07:23:11.55#ibcon#enter sib2, iclass 12, count 2 2006.211.07:23:11.55#ibcon#flushed, iclass 12, count 2 2006.211.07:23:11.55#ibcon#about to write, iclass 12, count 2 2006.211.07:23:11.55#ibcon#wrote, iclass 12, count 2 2006.211.07:23:11.55#ibcon#about to read 3, iclass 12, count 2 2006.211.07:23:11.57#ibcon#read 3, iclass 12, count 2 2006.211.07:23:11.57#ibcon#about to read 4, iclass 12, count 2 2006.211.07:23:11.57#ibcon#read 4, iclass 12, count 2 2006.211.07:23:11.57#ibcon#about to read 5, iclass 12, count 2 2006.211.07:23:11.57#ibcon#read 5, iclass 12, count 2 2006.211.07:23:11.57#ibcon#about to read 6, iclass 12, count 2 2006.211.07:23:11.57#ibcon#read 6, iclass 12, count 2 2006.211.07:23:11.57#ibcon#end of sib2, iclass 12, count 2 2006.211.07:23:11.57#ibcon#*mode == 0, iclass 12, count 2 2006.211.07:23:11.57#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.07:23:11.57#ibcon#[25=AT02-07\r\n] 2006.211.07:23:11.57#ibcon#*before write, iclass 12, count 2 2006.211.07:23:11.57#ibcon#enter sib2, iclass 12, count 2 2006.211.07:23:11.57#ibcon#flushed, iclass 12, count 2 2006.211.07:23:11.57#ibcon#about to write, iclass 12, count 2 2006.211.07:23:11.57#ibcon#wrote, iclass 12, count 2 2006.211.07:23:11.57#ibcon#about to read 3, iclass 12, count 2 2006.211.07:23:11.60#ibcon#read 3, iclass 12, count 2 2006.211.07:23:11.60#ibcon#about to read 4, iclass 12, count 2 2006.211.07:23:11.60#ibcon#read 4, iclass 12, count 2 2006.211.07:23:11.60#ibcon#about to read 5, iclass 12, count 2 2006.211.07:23:11.60#ibcon#read 5, iclass 12, count 2 2006.211.07:23:11.60#ibcon#about to read 6, iclass 12, count 2 2006.211.07:23:11.60#ibcon#read 6, iclass 12, count 2 2006.211.07:23:11.60#ibcon#end of sib2, iclass 12, count 2 2006.211.07:23:11.60#ibcon#*after write, iclass 12, count 2 2006.211.07:23:11.60#ibcon#*before return 0, iclass 12, count 2 2006.211.07:23:11.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:23:11.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.07:23:11.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.07:23:11.60#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:11.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:23:11.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:23:11.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:23:11.72#ibcon#enter wrdev, iclass 12, count 0 2006.211.07:23:11.72#ibcon#first serial, iclass 12, count 0 2006.211.07:23:11.72#ibcon#enter sib2, iclass 12, count 0 2006.211.07:23:11.72#ibcon#flushed, iclass 12, count 0 2006.211.07:23:11.72#ibcon#about to write, iclass 12, count 0 2006.211.07:23:11.72#ibcon#wrote, iclass 12, count 0 2006.211.07:23:11.72#ibcon#about to read 3, iclass 12, count 0 2006.211.07:23:11.74#ibcon#read 3, iclass 12, count 0 2006.211.07:23:11.74#ibcon#about to read 4, iclass 12, count 0 2006.211.07:23:11.74#ibcon#read 4, iclass 12, count 0 2006.211.07:23:11.74#ibcon#about to read 5, iclass 12, count 0 2006.211.07:23:11.74#ibcon#read 5, iclass 12, count 0 2006.211.07:23:11.74#ibcon#about to read 6, iclass 12, count 0 2006.211.07:23:11.74#ibcon#read 6, iclass 12, count 0 2006.211.07:23:11.74#ibcon#end of sib2, iclass 12, count 0 2006.211.07:23:11.74#ibcon#*mode == 0, iclass 12, count 0 2006.211.07:23:11.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.07:23:11.74#ibcon#[25=USB\r\n] 2006.211.07:23:11.74#ibcon#*before write, iclass 12, count 0 2006.211.07:23:11.74#ibcon#enter sib2, iclass 12, count 0 2006.211.07:23:11.74#ibcon#flushed, iclass 12, count 0 2006.211.07:23:11.74#ibcon#about to write, iclass 12, count 0 2006.211.07:23:11.74#ibcon#wrote, iclass 12, count 0 2006.211.07:23:11.74#ibcon#about to read 3, iclass 12, count 0 2006.211.07:23:11.77#ibcon#read 3, iclass 12, count 0 2006.211.07:23:11.77#ibcon#about to read 4, iclass 12, count 0 2006.211.07:23:11.77#ibcon#read 4, iclass 12, count 0 2006.211.07:23:11.77#ibcon#about to read 5, iclass 12, count 0 2006.211.07:23:11.77#ibcon#read 5, iclass 12, count 0 2006.211.07:23:11.77#ibcon#about to read 6, iclass 12, count 0 2006.211.07:23:11.77#ibcon#read 6, iclass 12, count 0 2006.211.07:23:11.77#ibcon#end of sib2, iclass 12, count 0 2006.211.07:23:11.77#ibcon#*after write, iclass 12, count 0 2006.211.07:23:11.77#ibcon#*before return 0, iclass 12, count 0 2006.211.07:23:11.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:23:11.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.07:23:11.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.07:23:11.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.07:23:11.77$vc4f8/valo=3,672.99 2006.211.07:23:11.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.07:23:11.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.07:23:11.77#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:11.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:23:11.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:23:11.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:23:11.77#ibcon#enter wrdev, iclass 14, count 0 2006.211.07:23:11.77#ibcon#first serial, iclass 14, count 0 2006.211.07:23:11.77#ibcon#enter sib2, iclass 14, count 0 2006.211.07:23:11.77#ibcon#flushed, iclass 14, count 0 2006.211.07:23:11.77#ibcon#about to write, iclass 14, count 0 2006.211.07:23:11.77#ibcon#wrote, iclass 14, count 0 2006.211.07:23:11.77#ibcon#about to read 3, iclass 14, count 0 2006.211.07:23:11.79#ibcon#read 3, iclass 14, count 0 2006.211.07:23:11.79#ibcon#about to read 4, iclass 14, count 0 2006.211.07:23:11.79#ibcon#read 4, iclass 14, count 0 2006.211.07:23:11.79#ibcon#about to read 5, iclass 14, count 0 2006.211.07:23:11.79#ibcon#read 5, iclass 14, count 0 2006.211.07:23:11.79#ibcon#about to read 6, iclass 14, count 0 2006.211.07:23:11.79#ibcon#read 6, iclass 14, count 0 2006.211.07:23:11.79#ibcon#end of sib2, iclass 14, count 0 2006.211.07:23:11.79#ibcon#*mode == 0, iclass 14, count 0 2006.211.07:23:11.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.07:23:11.79#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.07:23:11.79#ibcon#*before write, iclass 14, count 0 2006.211.07:23:11.79#ibcon#enter sib2, iclass 14, count 0 2006.211.07:23:11.79#ibcon#flushed, iclass 14, count 0 2006.211.07:23:11.79#ibcon#about to write, iclass 14, count 0 2006.211.07:23:11.79#ibcon#wrote, iclass 14, count 0 2006.211.07:23:11.79#ibcon#about to read 3, iclass 14, count 0 2006.211.07:23:11.83#ibcon#read 3, iclass 14, count 0 2006.211.07:23:11.83#ibcon#about to read 4, iclass 14, count 0 2006.211.07:23:11.83#ibcon#read 4, iclass 14, count 0 2006.211.07:23:11.83#ibcon#about to read 5, iclass 14, count 0 2006.211.07:23:11.83#ibcon#read 5, iclass 14, count 0 2006.211.07:23:11.83#ibcon#about to read 6, iclass 14, count 0 2006.211.07:23:11.83#ibcon#read 6, iclass 14, count 0 2006.211.07:23:11.83#ibcon#end of sib2, iclass 14, count 0 2006.211.07:23:11.83#ibcon#*after write, iclass 14, count 0 2006.211.07:23:11.83#ibcon#*before return 0, iclass 14, count 0 2006.211.07:23:11.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:23:11.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.07:23:11.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.07:23:11.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.07:23:11.83$vc4f8/va=3,6 2006.211.07:23:11.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.07:23:11.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.07:23:11.83#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:11.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:23:11.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:23:11.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:23:11.89#ibcon#enter wrdev, iclass 16, count 2 2006.211.07:23:11.89#ibcon#first serial, iclass 16, count 2 2006.211.07:23:11.89#ibcon#enter sib2, iclass 16, count 2 2006.211.07:23:11.89#ibcon#flushed, iclass 16, count 2 2006.211.07:23:11.89#ibcon#about to write, iclass 16, count 2 2006.211.07:23:11.89#ibcon#wrote, iclass 16, count 2 2006.211.07:23:11.89#ibcon#about to read 3, iclass 16, count 2 2006.211.07:23:11.91#ibcon#read 3, iclass 16, count 2 2006.211.07:23:11.91#ibcon#about to read 4, iclass 16, count 2 2006.211.07:23:11.91#ibcon#read 4, iclass 16, count 2 2006.211.07:23:11.91#ibcon#about to read 5, iclass 16, count 2 2006.211.07:23:11.91#ibcon#read 5, iclass 16, count 2 2006.211.07:23:11.91#ibcon#about to read 6, iclass 16, count 2 2006.211.07:23:11.91#ibcon#read 6, iclass 16, count 2 2006.211.07:23:11.91#ibcon#end of sib2, iclass 16, count 2 2006.211.07:23:11.91#ibcon#*mode == 0, iclass 16, count 2 2006.211.07:23:11.91#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.07:23:11.91#ibcon#[25=AT03-06\r\n] 2006.211.07:23:11.91#ibcon#*before write, iclass 16, count 2 2006.211.07:23:11.91#ibcon#enter sib2, iclass 16, count 2 2006.211.07:23:11.91#ibcon#flushed, iclass 16, count 2 2006.211.07:23:11.91#ibcon#about to write, iclass 16, count 2 2006.211.07:23:11.91#ibcon#wrote, iclass 16, count 2 2006.211.07:23:11.91#ibcon#about to read 3, iclass 16, count 2 2006.211.07:23:11.94#ibcon#read 3, iclass 16, count 2 2006.211.07:23:11.94#ibcon#about to read 4, iclass 16, count 2 2006.211.07:23:11.94#ibcon#read 4, iclass 16, count 2 2006.211.07:23:11.94#ibcon#about to read 5, iclass 16, count 2 2006.211.07:23:11.94#ibcon#read 5, iclass 16, count 2 2006.211.07:23:11.94#ibcon#about to read 6, iclass 16, count 2 2006.211.07:23:11.94#ibcon#read 6, iclass 16, count 2 2006.211.07:23:11.94#ibcon#end of sib2, iclass 16, count 2 2006.211.07:23:11.94#ibcon#*after write, iclass 16, count 2 2006.211.07:23:11.94#ibcon#*before return 0, iclass 16, count 2 2006.211.07:23:11.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:23:11.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.07:23:11.94#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.07:23:11.94#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:11.94#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:23:12.06#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:23:12.06#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:23:12.06#ibcon#enter wrdev, iclass 16, count 0 2006.211.07:23:12.06#ibcon#first serial, iclass 16, count 0 2006.211.07:23:12.06#ibcon#enter sib2, iclass 16, count 0 2006.211.07:23:12.06#ibcon#flushed, iclass 16, count 0 2006.211.07:23:12.06#ibcon#about to write, iclass 16, count 0 2006.211.07:23:12.06#ibcon#wrote, iclass 16, count 0 2006.211.07:23:12.06#ibcon#about to read 3, iclass 16, count 0 2006.211.07:23:12.08#ibcon#read 3, iclass 16, count 0 2006.211.07:23:12.08#ibcon#about to read 4, iclass 16, count 0 2006.211.07:23:12.08#ibcon#read 4, iclass 16, count 0 2006.211.07:23:12.08#ibcon#about to read 5, iclass 16, count 0 2006.211.07:23:12.08#ibcon#read 5, iclass 16, count 0 2006.211.07:23:12.08#ibcon#about to read 6, iclass 16, count 0 2006.211.07:23:12.08#ibcon#read 6, iclass 16, count 0 2006.211.07:23:12.08#ibcon#end of sib2, iclass 16, count 0 2006.211.07:23:12.08#ibcon#*mode == 0, iclass 16, count 0 2006.211.07:23:12.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.07:23:12.08#ibcon#[25=USB\r\n] 2006.211.07:23:12.08#ibcon#*before write, iclass 16, count 0 2006.211.07:23:12.08#ibcon#enter sib2, iclass 16, count 0 2006.211.07:23:12.08#ibcon#flushed, iclass 16, count 0 2006.211.07:23:12.08#ibcon#about to write, iclass 16, count 0 2006.211.07:23:12.08#ibcon#wrote, iclass 16, count 0 2006.211.07:23:12.08#ibcon#about to read 3, iclass 16, count 0 2006.211.07:23:12.11#ibcon#read 3, iclass 16, count 0 2006.211.07:23:12.11#ibcon#about to read 4, iclass 16, count 0 2006.211.07:23:12.11#ibcon#read 4, iclass 16, count 0 2006.211.07:23:12.11#ibcon#about to read 5, iclass 16, count 0 2006.211.07:23:12.11#ibcon#read 5, iclass 16, count 0 2006.211.07:23:12.11#ibcon#about to read 6, iclass 16, count 0 2006.211.07:23:12.11#ibcon#read 6, iclass 16, count 0 2006.211.07:23:12.11#ibcon#end of sib2, iclass 16, count 0 2006.211.07:23:12.11#ibcon#*after write, iclass 16, count 0 2006.211.07:23:12.11#ibcon#*before return 0, iclass 16, count 0 2006.211.07:23:12.11#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:23:12.11#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.07:23:12.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.07:23:12.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.07:23:12.11$vc4f8/valo=4,832.99 2006.211.07:23:12.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.07:23:12.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.07:23:12.11#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:12.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:23:12.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:23:12.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:23:12.11#ibcon#enter wrdev, iclass 18, count 0 2006.211.07:23:12.11#ibcon#first serial, iclass 18, count 0 2006.211.07:23:12.11#ibcon#enter sib2, iclass 18, count 0 2006.211.07:23:12.11#ibcon#flushed, iclass 18, count 0 2006.211.07:23:12.11#ibcon#about to write, iclass 18, count 0 2006.211.07:23:12.11#ibcon#wrote, iclass 18, count 0 2006.211.07:23:12.11#ibcon#about to read 3, iclass 18, count 0 2006.211.07:23:12.13#ibcon#read 3, iclass 18, count 0 2006.211.07:23:12.13#ibcon#about to read 4, iclass 18, count 0 2006.211.07:23:12.13#ibcon#read 4, iclass 18, count 0 2006.211.07:23:12.13#ibcon#about to read 5, iclass 18, count 0 2006.211.07:23:12.13#ibcon#read 5, iclass 18, count 0 2006.211.07:23:12.13#ibcon#about to read 6, iclass 18, count 0 2006.211.07:23:12.13#ibcon#read 6, iclass 18, count 0 2006.211.07:23:12.13#ibcon#end of sib2, iclass 18, count 0 2006.211.07:23:12.13#ibcon#*mode == 0, iclass 18, count 0 2006.211.07:23:12.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.07:23:12.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.07:23:12.13#ibcon#*before write, iclass 18, count 0 2006.211.07:23:12.13#ibcon#enter sib2, iclass 18, count 0 2006.211.07:23:12.13#ibcon#flushed, iclass 18, count 0 2006.211.07:23:12.13#ibcon#about to write, iclass 18, count 0 2006.211.07:23:12.13#ibcon#wrote, iclass 18, count 0 2006.211.07:23:12.13#ibcon#about to read 3, iclass 18, count 0 2006.211.07:23:12.17#ibcon#read 3, iclass 18, count 0 2006.211.07:23:12.17#ibcon#about to read 4, iclass 18, count 0 2006.211.07:23:12.17#ibcon#read 4, iclass 18, count 0 2006.211.07:23:12.17#ibcon#about to read 5, iclass 18, count 0 2006.211.07:23:12.17#ibcon#read 5, iclass 18, count 0 2006.211.07:23:12.17#ibcon#about to read 6, iclass 18, count 0 2006.211.07:23:12.17#ibcon#read 6, iclass 18, count 0 2006.211.07:23:12.17#ibcon#end of sib2, iclass 18, count 0 2006.211.07:23:12.17#ibcon#*after write, iclass 18, count 0 2006.211.07:23:12.17#ibcon#*before return 0, iclass 18, count 0 2006.211.07:23:12.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:23:12.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.07:23:12.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.07:23:12.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.07:23:12.17$vc4f8/va=4,7 2006.211.07:23:12.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.07:23:12.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.07:23:12.17#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:12.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:23:12.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:23:12.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:23:12.23#ibcon#enter wrdev, iclass 20, count 2 2006.211.07:23:12.23#ibcon#first serial, iclass 20, count 2 2006.211.07:23:12.23#ibcon#enter sib2, iclass 20, count 2 2006.211.07:23:12.23#ibcon#flushed, iclass 20, count 2 2006.211.07:23:12.23#ibcon#about to write, iclass 20, count 2 2006.211.07:23:12.23#ibcon#wrote, iclass 20, count 2 2006.211.07:23:12.23#ibcon#about to read 3, iclass 20, count 2 2006.211.07:23:12.25#ibcon#read 3, iclass 20, count 2 2006.211.07:23:12.25#ibcon#about to read 4, iclass 20, count 2 2006.211.07:23:12.25#ibcon#read 4, iclass 20, count 2 2006.211.07:23:12.25#ibcon#about to read 5, iclass 20, count 2 2006.211.07:23:12.25#ibcon#read 5, iclass 20, count 2 2006.211.07:23:12.25#ibcon#about to read 6, iclass 20, count 2 2006.211.07:23:12.25#ibcon#read 6, iclass 20, count 2 2006.211.07:23:12.25#ibcon#end of sib2, iclass 20, count 2 2006.211.07:23:12.25#ibcon#*mode == 0, iclass 20, count 2 2006.211.07:23:12.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.07:23:12.25#ibcon#[25=AT04-07\r\n] 2006.211.07:23:12.25#ibcon#*before write, iclass 20, count 2 2006.211.07:23:12.25#ibcon#enter sib2, iclass 20, count 2 2006.211.07:23:12.25#ibcon#flushed, iclass 20, count 2 2006.211.07:23:12.25#ibcon#about to write, iclass 20, count 2 2006.211.07:23:12.25#ibcon#wrote, iclass 20, count 2 2006.211.07:23:12.25#ibcon#about to read 3, iclass 20, count 2 2006.211.07:23:12.28#ibcon#read 3, iclass 20, count 2 2006.211.07:23:12.28#ibcon#about to read 4, iclass 20, count 2 2006.211.07:23:12.28#ibcon#read 4, iclass 20, count 2 2006.211.07:23:12.28#ibcon#about to read 5, iclass 20, count 2 2006.211.07:23:12.28#ibcon#read 5, iclass 20, count 2 2006.211.07:23:12.28#ibcon#about to read 6, iclass 20, count 2 2006.211.07:23:12.28#ibcon#read 6, iclass 20, count 2 2006.211.07:23:12.28#ibcon#end of sib2, iclass 20, count 2 2006.211.07:23:12.28#ibcon#*after write, iclass 20, count 2 2006.211.07:23:12.28#ibcon#*before return 0, iclass 20, count 2 2006.211.07:23:12.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:23:12.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.07:23:12.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.07:23:12.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:12.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:23:12.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:23:12.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:23:12.40#ibcon#enter wrdev, iclass 20, count 0 2006.211.07:23:12.40#ibcon#first serial, iclass 20, count 0 2006.211.07:23:12.40#ibcon#enter sib2, iclass 20, count 0 2006.211.07:23:12.40#ibcon#flushed, iclass 20, count 0 2006.211.07:23:12.40#ibcon#about to write, iclass 20, count 0 2006.211.07:23:12.40#ibcon#wrote, iclass 20, count 0 2006.211.07:23:12.40#ibcon#about to read 3, iclass 20, count 0 2006.211.07:23:12.42#ibcon#read 3, iclass 20, count 0 2006.211.07:23:12.42#ibcon#about to read 4, iclass 20, count 0 2006.211.07:23:12.42#ibcon#read 4, iclass 20, count 0 2006.211.07:23:12.42#ibcon#about to read 5, iclass 20, count 0 2006.211.07:23:12.42#ibcon#read 5, iclass 20, count 0 2006.211.07:23:12.42#ibcon#about to read 6, iclass 20, count 0 2006.211.07:23:12.42#ibcon#read 6, iclass 20, count 0 2006.211.07:23:12.42#ibcon#end of sib2, iclass 20, count 0 2006.211.07:23:12.42#ibcon#*mode == 0, iclass 20, count 0 2006.211.07:23:12.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.07:23:12.42#ibcon#[25=USB\r\n] 2006.211.07:23:12.42#ibcon#*before write, iclass 20, count 0 2006.211.07:23:12.42#ibcon#enter sib2, iclass 20, count 0 2006.211.07:23:12.42#ibcon#flushed, iclass 20, count 0 2006.211.07:23:12.42#ibcon#about to write, iclass 20, count 0 2006.211.07:23:12.42#ibcon#wrote, iclass 20, count 0 2006.211.07:23:12.42#ibcon#about to read 3, iclass 20, count 0 2006.211.07:23:12.45#ibcon#read 3, iclass 20, count 0 2006.211.07:23:12.45#ibcon#about to read 4, iclass 20, count 0 2006.211.07:23:12.45#ibcon#read 4, iclass 20, count 0 2006.211.07:23:12.45#ibcon#about to read 5, iclass 20, count 0 2006.211.07:23:12.45#ibcon#read 5, iclass 20, count 0 2006.211.07:23:12.45#ibcon#about to read 6, iclass 20, count 0 2006.211.07:23:12.45#ibcon#read 6, iclass 20, count 0 2006.211.07:23:12.45#ibcon#end of sib2, iclass 20, count 0 2006.211.07:23:12.45#ibcon#*after write, iclass 20, count 0 2006.211.07:23:12.45#ibcon#*before return 0, iclass 20, count 0 2006.211.07:23:12.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:23:12.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.07:23:12.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.07:23:12.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.07:23:12.45$vc4f8/valo=5,652.99 2006.211.07:23:12.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.07:23:12.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.07:23:12.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:12.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:23:12.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:23:12.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:23:12.45#ibcon#enter wrdev, iclass 22, count 0 2006.211.07:23:12.45#ibcon#first serial, iclass 22, count 0 2006.211.07:23:12.45#ibcon#enter sib2, iclass 22, count 0 2006.211.07:23:12.45#ibcon#flushed, iclass 22, count 0 2006.211.07:23:12.45#ibcon#about to write, iclass 22, count 0 2006.211.07:23:12.45#ibcon#wrote, iclass 22, count 0 2006.211.07:23:12.45#ibcon#about to read 3, iclass 22, count 0 2006.211.07:23:12.47#ibcon#read 3, iclass 22, count 0 2006.211.07:23:12.47#ibcon#about to read 4, iclass 22, count 0 2006.211.07:23:12.47#ibcon#read 4, iclass 22, count 0 2006.211.07:23:12.47#ibcon#about to read 5, iclass 22, count 0 2006.211.07:23:12.47#ibcon#read 5, iclass 22, count 0 2006.211.07:23:12.47#ibcon#about to read 6, iclass 22, count 0 2006.211.07:23:12.47#ibcon#read 6, iclass 22, count 0 2006.211.07:23:12.47#ibcon#end of sib2, iclass 22, count 0 2006.211.07:23:12.47#ibcon#*mode == 0, iclass 22, count 0 2006.211.07:23:12.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.07:23:12.47#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.07:23:12.47#ibcon#*before write, iclass 22, count 0 2006.211.07:23:12.47#ibcon#enter sib2, iclass 22, count 0 2006.211.07:23:12.47#ibcon#flushed, iclass 22, count 0 2006.211.07:23:12.47#ibcon#about to write, iclass 22, count 0 2006.211.07:23:12.47#ibcon#wrote, iclass 22, count 0 2006.211.07:23:12.47#ibcon#about to read 3, iclass 22, count 0 2006.211.07:23:12.51#ibcon#read 3, iclass 22, count 0 2006.211.07:23:12.51#ibcon#about to read 4, iclass 22, count 0 2006.211.07:23:12.51#ibcon#read 4, iclass 22, count 0 2006.211.07:23:12.51#ibcon#about to read 5, iclass 22, count 0 2006.211.07:23:12.51#ibcon#read 5, iclass 22, count 0 2006.211.07:23:12.51#ibcon#about to read 6, iclass 22, count 0 2006.211.07:23:12.51#ibcon#read 6, iclass 22, count 0 2006.211.07:23:12.51#ibcon#end of sib2, iclass 22, count 0 2006.211.07:23:12.51#ibcon#*after write, iclass 22, count 0 2006.211.07:23:12.51#ibcon#*before return 0, iclass 22, count 0 2006.211.07:23:12.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:23:12.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.07:23:12.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.07:23:12.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.07:23:12.51$vc4f8/va=5,7 2006.211.07:23:12.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.07:23:12.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.07:23:12.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:12.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:23:12.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:23:12.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:23:12.57#ibcon#enter wrdev, iclass 24, count 2 2006.211.07:23:12.57#ibcon#first serial, iclass 24, count 2 2006.211.07:23:12.57#ibcon#enter sib2, iclass 24, count 2 2006.211.07:23:12.57#ibcon#flushed, iclass 24, count 2 2006.211.07:23:12.57#ibcon#about to write, iclass 24, count 2 2006.211.07:23:12.57#ibcon#wrote, iclass 24, count 2 2006.211.07:23:12.57#ibcon#about to read 3, iclass 24, count 2 2006.211.07:23:12.59#ibcon#read 3, iclass 24, count 2 2006.211.07:23:12.59#ibcon#about to read 4, iclass 24, count 2 2006.211.07:23:12.59#ibcon#read 4, iclass 24, count 2 2006.211.07:23:12.59#ibcon#about to read 5, iclass 24, count 2 2006.211.07:23:12.59#ibcon#read 5, iclass 24, count 2 2006.211.07:23:12.59#ibcon#about to read 6, iclass 24, count 2 2006.211.07:23:12.59#ibcon#read 6, iclass 24, count 2 2006.211.07:23:12.59#ibcon#end of sib2, iclass 24, count 2 2006.211.07:23:12.59#ibcon#*mode == 0, iclass 24, count 2 2006.211.07:23:12.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.07:23:12.59#ibcon#[25=AT05-07\r\n] 2006.211.07:23:12.59#ibcon#*before write, iclass 24, count 2 2006.211.07:23:12.59#ibcon#enter sib2, iclass 24, count 2 2006.211.07:23:12.59#ibcon#flushed, iclass 24, count 2 2006.211.07:23:12.59#ibcon#about to write, iclass 24, count 2 2006.211.07:23:12.59#ibcon#wrote, iclass 24, count 2 2006.211.07:23:12.59#ibcon#about to read 3, iclass 24, count 2 2006.211.07:23:12.62#ibcon#read 3, iclass 24, count 2 2006.211.07:23:12.62#ibcon#about to read 4, iclass 24, count 2 2006.211.07:23:12.62#ibcon#read 4, iclass 24, count 2 2006.211.07:23:12.62#ibcon#about to read 5, iclass 24, count 2 2006.211.07:23:12.62#ibcon#read 5, iclass 24, count 2 2006.211.07:23:12.62#ibcon#about to read 6, iclass 24, count 2 2006.211.07:23:12.62#ibcon#read 6, iclass 24, count 2 2006.211.07:23:12.62#ibcon#end of sib2, iclass 24, count 2 2006.211.07:23:12.62#ibcon#*after write, iclass 24, count 2 2006.211.07:23:12.62#ibcon#*before return 0, iclass 24, count 2 2006.211.07:23:12.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:23:12.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.07:23:12.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.07:23:12.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:12.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:23:12.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:23:12.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:23:12.74#ibcon#enter wrdev, iclass 24, count 0 2006.211.07:23:12.74#ibcon#first serial, iclass 24, count 0 2006.211.07:23:12.74#ibcon#enter sib2, iclass 24, count 0 2006.211.07:23:12.74#ibcon#flushed, iclass 24, count 0 2006.211.07:23:12.74#ibcon#about to write, iclass 24, count 0 2006.211.07:23:12.74#ibcon#wrote, iclass 24, count 0 2006.211.07:23:12.74#ibcon#about to read 3, iclass 24, count 0 2006.211.07:23:12.76#ibcon#read 3, iclass 24, count 0 2006.211.07:23:12.76#ibcon#about to read 4, iclass 24, count 0 2006.211.07:23:12.76#ibcon#read 4, iclass 24, count 0 2006.211.07:23:12.76#ibcon#about to read 5, iclass 24, count 0 2006.211.07:23:12.76#ibcon#read 5, iclass 24, count 0 2006.211.07:23:12.76#ibcon#about to read 6, iclass 24, count 0 2006.211.07:23:12.76#ibcon#read 6, iclass 24, count 0 2006.211.07:23:12.76#ibcon#end of sib2, iclass 24, count 0 2006.211.07:23:12.76#ibcon#*mode == 0, iclass 24, count 0 2006.211.07:23:12.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.07:23:12.76#ibcon#[25=USB\r\n] 2006.211.07:23:12.76#ibcon#*before write, iclass 24, count 0 2006.211.07:23:12.76#ibcon#enter sib2, iclass 24, count 0 2006.211.07:23:12.76#ibcon#flushed, iclass 24, count 0 2006.211.07:23:12.76#ibcon#about to write, iclass 24, count 0 2006.211.07:23:12.76#ibcon#wrote, iclass 24, count 0 2006.211.07:23:12.76#ibcon#about to read 3, iclass 24, count 0 2006.211.07:23:12.79#ibcon#read 3, iclass 24, count 0 2006.211.07:23:12.79#ibcon#about to read 4, iclass 24, count 0 2006.211.07:23:12.79#ibcon#read 4, iclass 24, count 0 2006.211.07:23:12.79#ibcon#about to read 5, iclass 24, count 0 2006.211.07:23:12.79#ibcon#read 5, iclass 24, count 0 2006.211.07:23:12.79#ibcon#about to read 6, iclass 24, count 0 2006.211.07:23:12.79#ibcon#read 6, iclass 24, count 0 2006.211.07:23:12.79#ibcon#end of sib2, iclass 24, count 0 2006.211.07:23:12.79#ibcon#*after write, iclass 24, count 0 2006.211.07:23:12.79#ibcon#*before return 0, iclass 24, count 0 2006.211.07:23:12.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:23:12.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.07:23:12.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.07:23:12.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.07:23:12.79$vc4f8/valo=6,772.99 2006.211.07:23:12.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.07:23:12.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.07:23:12.79#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:12.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:23:12.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:23:12.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:23:12.79#ibcon#enter wrdev, iclass 26, count 0 2006.211.07:23:12.79#ibcon#first serial, iclass 26, count 0 2006.211.07:23:12.79#ibcon#enter sib2, iclass 26, count 0 2006.211.07:23:12.79#ibcon#flushed, iclass 26, count 0 2006.211.07:23:12.79#ibcon#about to write, iclass 26, count 0 2006.211.07:23:12.79#ibcon#wrote, iclass 26, count 0 2006.211.07:23:12.79#ibcon#about to read 3, iclass 26, count 0 2006.211.07:23:12.81#ibcon#read 3, iclass 26, count 0 2006.211.07:23:12.81#ibcon#about to read 4, iclass 26, count 0 2006.211.07:23:12.81#ibcon#read 4, iclass 26, count 0 2006.211.07:23:12.81#ibcon#about to read 5, iclass 26, count 0 2006.211.07:23:12.81#ibcon#read 5, iclass 26, count 0 2006.211.07:23:12.81#ibcon#about to read 6, iclass 26, count 0 2006.211.07:23:12.81#ibcon#read 6, iclass 26, count 0 2006.211.07:23:12.81#ibcon#end of sib2, iclass 26, count 0 2006.211.07:23:12.81#ibcon#*mode == 0, iclass 26, count 0 2006.211.07:23:12.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.07:23:12.81#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.07:23:12.81#ibcon#*before write, iclass 26, count 0 2006.211.07:23:12.81#ibcon#enter sib2, iclass 26, count 0 2006.211.07:23:12.81#ibcon#flushed, iclass 26, count 0 2006.211.07:23:12.81#ibcon#about to write, iclass 26, count 0 2006.211.07:23:12.81#ibcon#wrote, iclass 26, count 0 2006.211.07:23:12.81#ibcon#about to read 3, iclass 26, count 0 2006.211.07:23:12.85#ibcon#read 3, iclass 26, count 0 2006.211.07:23:12.85#ibcon#about to read 4, iclass 26, count 0 2006.211.07:23:12.85#ibcon#read 4, iclass 26, count 0 2006.211.07:23:12.85#ibcon#about to read 5, iclass 26, count 0 2006.211.07:23:12.85#ibcon#read 5, iclass 26, count 0 2006.211.07:23:12.85#ibcon#about to read 6, iclass 26, count 0 2006.211.07:23:12.85#ibcon#read 6, iclass 26, count 0 2006.211.07:23:12.85#ibcon#end of sib2, iclass 26, count 0 2006.211.07:23:12.85#ibcon#*after write, iclass 26, count 0 2006.211.07:23:12.85#ibcon#*before return 0, iclass 26, count 0 2006.211.07:23:12.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:23:12.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.07:23:12.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.07:23:12.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.07:23:12.85$vc4f8/va=6,6 2006.211.07:23:12.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.07:23:12.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.07:23:12.85#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:12.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:23:12.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:23:12.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:23:12.91#ibcon#enter wrdev, iclass 28, count 2 2006.211.07:23:12.91#ibcon#first serial, iclass 28, count 2 2006.211.07:23:12.91#ibcon#enter sib2, iclass 28, count 2 2006.211.07:23:12.91#ibcon#flushed, iclass 28, count 2 2006.211.07:23:12.91#ibcon#about to write, iclass 28, count 2 2006.211.07:23:12.91#ibcon#wrote, iclass 28, count 2 2006.211.07:23:12.91#ibcon#about to read 3, iclass 28, count 2 2006.211.07:23:12.93#ibcon#read 3, iclass 28, count 2 2006.211.07:23:12.93#ibcon#about to read 4, iclass 28, count 2 2006.211.07:23:12.93#ibcon#read 4, iclass 28, count 2 2006.211.07:23:12.93#ibcon#about to read 5, iclass 28, count 2 2006.211.07:23:12.93#ibcon#read 5, iclass 28, count 2 2006.211.07:23:12.93#ibcon#about to read 6, iclass 28, count 2 2006.211.07:23:12.93#ibcon#read 6, iclass 28, count 2 2006.211.07:23:12.93#ibcon#end of sib2, iclass 28, count 2 2006.211.07:23:12.93#ibcon#*mode == 0, iclass 28, count 2 2006.211.07:23:12.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.07:23:12.93#ibcon#[25=AT06-06\r\n] 2006.211.07:23:12.93#ibcon#*before write, iclass 28, count 2 2006.211.07:23:12.93#ibcon#enter sib2, iclass 28, count 2 2006.211.07:23:12.93#ibcon#flushed, iclass 28, count 2 2006.211.07:23:12.93#ibcon#about to write, iclass 28, count 2 2006.211.07:23:12.93#ibcon#wrote, iclass 28, count 2 2006.211.07:23:12.93#ibcon#about to read 3, iclass 28, count 2 2006.211.07:23:12.96#ibcon#read 3, iclass 28, count 2 2006.211.07:23:12.96#ibcon#about to read 4, iclass 28, count 2 2006.211.07:23:12.96#ibcon#read 4, iclass 28, count 2 2006.211.07:23:12.96#ibcon#about to read 5, iclass 28, count 2 2006.211.07:23:12.96#ibcon#read 5, iclass 28, count 2 2006.211.07:23:12.96#ibcon#about to read 6, iclass 28, count 2 2006.211.07:23:12.96#ibcon#read 6, iclass 28, count 2 2006.211.07:23:12.96#ibcon#end of sib2, iclass 28, count 2 2006.211.07:23:12.96#ibcon#*after write, iclass 28, count 2 2006.211.07:23:12.96#ibcon#*before return 0, iclass 28, count 2 2006.211.07:23:12.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:23:12.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.07:23:12.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.07:23:12.96#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:12.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:23:13.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:23:13.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:23:13.08#ibcon#enter wrdev, iclass 28, count 0 2006.211.07:23:13.08#ibcon#first serial, iclass 28, count 0 2006.211.07:23:13.08#ibcon#enter sib2, iclass 28, count 0 2006.211.07:23:13.08#ibcon#flushed, iclass 28, count 0 2006.211.07:23:13.08#ibcon#about to write, iclass 28, count 0 2006.211.07:23:13.08#ibcon#wrote, iclass 28, count 0 2006.211.07:23:13.08#ibcon#about to read 3, iclass 28, count 0 2006.211.07:23:13.10#ibcon#read 3, iclass 28, count 0 2006.211.07:23:13.10#ibcon#about to read 4, iclass 28, count 0 2006.211.07:23:13.10#ibcon#read 4, iclass 28, count 0 2006.211.07:23:13.10#ibcon#about to read 5, iclass 28, count 0 2006.211.07:23:13.10#ibcon#read 5, iclass 28, count 0 2006.211.07:23:13.10#ibcon#about to read 6, iclass 28, count 0 2006.211.07:23:13.10#ibcon#read 6, iclass 28, count 0 2006.211.07:23:13.10#ibcon#end of sib2, iclass 28, count 0 2006.211.07:23:13.10#ibcon#*mode == 0, iclass 28, count 0 2006.211.07:23:13.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.07:23:13.10#ibcon#[25=USB\r\n] 2006.211.07:23:13.10#ibcon#*before write, iclass 28, count 0 2006.211.07:23:13.10#ibcon#enter sib2, iclass 28, count 0 2006.211.07:23:13.10#ibcon#flushed, iclass 28, count 0 2006.211.07:23:13.10#ibcon#about to write, iclass 28, count 0 2006.211.07:23:13.10#ibcon#wrote, iclass 28, count 0 2006.211.07:23:13.10#ibcon#about to read 3, iclass 28, count 0 2006.211.07:23:13.13#ibcon#read 3, iclass 28, count 0 2006.211.07:23:13.13#ibcon#about to read 4, iclass 28, count 0 2006.211.07:23:13.13#ibcon#read 4, iclass 28, count 0 2006.211.07:23:13.13#ibcon#about to read 5, iclass 28, count 0 2006.211.07:23:13.13#ibcon#read 5, iclass 28, count 0 2006.211.07:23:13.13#ibcon#about to read 6, iclass 28, count 0 2006.211.07:23:13.13#ibcon#read 6, iclass 28, count 0 2006.211.07:23:13.13#ibcon#end of sib2, iclass 28, count 0 2006.211.07:23:13.13#ibcon#*after write, iclass 28, count 0 2006.211.07:23:13.13#ibcon#*before return 0, iclass 28, count 0 2006.211.07:23:13.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:23:13.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.07:23:13.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.07:23:13.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.07:23:13.13$vc4f8/valo=7,832.99 2006.211.07:23:13.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.07:23:13.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.07:23:13.13#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:13.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:23:13.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:23:13.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:23:13.13#ibcon#enter wrdev, iclass 30, count 0 2006.211.07:23:13.13#ibcon#first serial, iclass 30, count 0 2006.211.07:23:13.13#ibcon#enter sib2, iclass 30, count 0 2006.211.07:23:13.13#ibcon#flushed, iclass 30, count 0 2006.211.07:23:13.13#ibcon#about to write, iclass 30, count 0 2006.211.07:23:13.13#ibcon#wrote, iclass 30, count 0 2006.211.07:23:13.13#ibcon#about to read 3, iclass 30, count 0 2006.211.07:23:13.15#ibcon#read 3, iclass 30, count 0 2006.211.07:23:13.15#ibcon#about to read 4, iclass 30, count 0 2006.211.07:23:13.15#ibcon#read 4, iclass 30, count 0 2006.211.07:23:13.15#ibcon#about to read 5, iclass 30, count 0 2006.211.07:23:13.15#ibcon#read 5, iclass 30, count 0 2006.211.07:23:13.15#ibcon#about to read 6, iclass 30, count 0 2006.211.07:23:13.15#ibcon#read 6, iclass 30, count 0 2006.211.07:23:13.15#ibcon#end of sib2, iclass 30, count 0 2006.211.07:23:13.15#ibcon#*mode == 0, iclass 30, count 0 2006.211.07:23:13.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.07:23:13.15#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.07:23:13.15#ibcon#*before write, iclass 30, count 0 2006.211.07:23:13.15#ibcon#enter sib2, iclass 30, count 0 2006.211.07:23:13.15#ibcon#flushed, iclass 30, count 0 2006.211.07:23:13.15#ibcon#about to write, iclass 30, count 0 2006.211.07:23:13.15#ibcon#wrote, iclass 30, count 0 2006.211.07:23:13.15#ibcon#about to read 3, iclass 30, count 0 2006.211.07:23:13.19#ibcon#read 3, iclass 30, count 0 2006.211.07:23:13.19#ibcon#about to read 4, iclass 30, count 0 2006.211.07:23:13.19#ibcon#read 4, iclass 30, count 0 2006.211.07:23:13.19#ibcon#about to read 5, iclass 30, count 0 2006.211.07:23:13.19#ibcon#read 5, iclass 30, count 0 2006.211.07:23:13.19#ibcon#about to read 6, iclass 30, count 0 2006.211.07:23:13.19#ibcon#read 6, iclass 30, count 0 2006.211.07:23:13.19#ibcon#end of sib2, iclass 30, count 0 2006.211.07:23:13.19#ibcon#*after write, iclass 30, count 0 2006.211.07:23:13.19#ibcon#*before return 0, iclass 30, count 0 2006.211.07:23:13.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:23:13.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.07:23:13.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.07:23:13.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.07:23:13.19$vc4f8/va=7,6 2006.211.07:23:13.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.211.07:23:13.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.211.07:23:13.19#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:13.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:23:13.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:23:13.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:23:13.25#ibcon#enter wrdev, iclass 32, count 2 2006.211.07:23:13.25#ibcon#first serial, iclass 32, count 2 2006.211.07:23:13.25#ibcon#enter sib2, iclass 32, count 2 2006.211.07:23:13.25#ibcon#flushed, iclass 32, count 2 2006.211.07:23:13.25#ibcon#about to write, iclass 32, count 2 2006.211.07:23:13.25#ibcon#wrote, iclass 32, count 2 2006.211.07:23:13.25#ibcon#about to read 3, iclass 32, count 2 2006.211.07:23:13.27#ibcon#read 3, iclass 32, count 2 2006.211.07:23:13.27#ibcon#about to read 4, iclass 32, count 2 2006.211.07:23:13.27#ibcon#read 4, iclass 32, count 2 2006.211.07:23:13.27#ibcon#about to read 5, iclass 32, count 2 2006.211.07:23:13.27#ibcon#read 5, iclass 32, count 2 2006.211.07:23:13.27#ibcon#about to read 6, iclass 32, count 2 2006.211.07:23:13.27#ibcon#read 6, iclass 32, count 2 2006.211.07:23:13.27#ibcon#end of sib2, iclass 32, count 2 2006.211.07:23:13.27#ibcon#*mode == 0, iclass 32, count 2 2006.211.07:23:13.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.211.07:23:13.27#ibcon#[25=AT07-06\r\n] 2006.211.07:23:13.27#ibcon#*before write, iclass 32, count 2 2006.211.07:23:13.27#ibcon#enter sib2, iclass 32, count 2 2006.211.07:23:13.27#ibcon#flushed, iclass 32, count 2 2006.211.07:23:13.27#ibcon#about to write, iclass 32, count 2 2006.211.07:23:13.27#ibcon#wrote, iclass 32, count 2 2006.211.07:23:13.27#ibcon#about to read 3, iclass 32, count 2 2006.211.07:23:13.30#ibcon#read 3, iclass 32, count 2 2006.211.07:23:13.30#ibcon#about to read 4, iclass 32, count 2 2006.211.07:23:13.30#ibcon#read 4, iclass 32, count 2 2006.211.07:23:13.30#ibcon#about to read 5, iclass 32, count 2 2006.211.07:23:13.30#ibcon#read 5, iclass 32, count 2 2006.211.07:23:13.30#ibcon#about to read 6, iclass 32, count 2 2006.211.07:23:13.30#ibcon#read 6, iclass 32, count 2 2006.211.07:23:13.30#ibcon#end of sib2, iclass 32, count 2 2006.211.07:23:13.30#ibcon#*after write, iclass 32, count 2 2006.211.07:23:13.30#ibcon#*before return 0, iclass 32, count 2 2006.211.07:23:13.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:23:13.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.211.07:23:13.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.211.07:23:13.30#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:13.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:23:13.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:23:13.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:23:13.42#ibcon#enter wrdev, iclass 32, count 0 2006.211.07:23:13.42#ibcon#first serial, iclass 32, count 0 2006.211.07:23:13.42#ibcon#enter sib2, iclass 32, count 0 2006.211.07:23:13.42#ibcon#flushed, iclass 32, count 0 2006.211.07:23:13.42#ibcon#about to write, iclass 32, count 0 2006.211.07:23:13.42#ibcon#wrote, iclass 32, count 0 2006.211.07:23:13.42#ibcon#about to read 3, iclass 32, count 0 2006.211.07:23:13.44#ibcon#read 3, iclass 32, count 0 2006.211.07:23:13.44#ibcon#about to read 4, iclass 32, count 0 2006.211.07:23:13.44#ibcon#read 4, iclass 32, count 0 2006.211.07:23:13.44#ibcon#about to read 5, iclass 32, count 0 2006.211.07:23:13.44#ibcon#read 5, iclass 32, count 0 2006.211.07:23:13.44#ibcon#about to read 6, iclass 32, count 0 2006.211.07:23:13.44#ibcon#read 6, iclass 32, count 0 2006.211.07:23:13.44#ibcon#end of sib2, iclass 32, count 0 2006.211.07:23:13.44#ibcon#*mode == 0, iclass 32, count 0 2006.211.07:23:13.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.211.07:23:13.44#ibcon#[25=USB\r\n] 2006.211.07:23:13.44#ibcon#*before write, iclass 32, count 0 2006.211.07:23:13.44#ibcon#enter sib2, iclass 32, count 0 2006.211.07:23:13.44#ibcon#flushed, iclass 32, count 0 2006.211.07:23:13.44#ibcon#about to write, iclass 32, count 0 2006.211.07:23:13.44#ibcon#wrote, iclass 32, count 0 2006.211.07:23:13.44#ibcon#about to read 3, iclass 32, count 0 2006.211.07:23:13.47#ibcon#read 3, iclass 32, count 0 2006.211.07:23:13.47#ibcon#about to read 4, iclass 32, count 0 2006.211.07:23:13.47#ibcon#read 4, iclass 32, count 0 2006.211.07:23:13.47#ibcon#about to read 5, iclass 32, count 0 2006.211.07:23:13.47#ibcon#read 5, iclass 32, count 0 2006.211.07:23:13.47#ibcon#about to read 6, iclass 32, count 0 2006.211.07:23:13.47#ibcon#read 6, iclass 32, count 0 2006.211.07:23:13.47#ibcon#end of sib2, iclass 32, count 0 2006.211.07:23:13.47#ibcon#*after write, iclass 32, count 0 2006.211.07:23:13.47#ibcon#*before return 0, iclass 32, count 0 2006.211.07:23:13.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:23:13.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.211.07:23:13.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.211.07:23:13.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.211.07:23:13.47$vc4f8/valo=8,852.99 2006.211.07:23:13.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.211.07:23:13.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.211.07:23:13.47#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:13.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:23:13.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:23:13.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:23:13.47#ibcon#enter wrdev, iclass 34, count 0 2006.211.07:23:13.47#ibcon#first serial, iclass 34, count 0 2006.211.07:23:13.47#ibcon#enter sib2, iclass 34, count 0 2006.211.07:23:13.47#ibcon#flushed, iclass 34, count 0 2006.211.07:23:13.47#ibcon#about to write, iclass 34, count 0 2006.211.07:23:13.47#ibcon#wrote, iclass 34, count 0 2006.211.07:23:13.47#ibcon#about to read 3, iclass 34, count 0 2006.211.07:23:13.49#ibcon#read 3, iclass 34, count 0 2006.211.07:23:13.49#ibcon#about to read 4, iclass 34, count 0 2006.211.07:23:13.49#ibcon#read 4, iclass 34, count 0 2006.211.07:23:13.49#ibcon#about to read 5, iclass 34, count 0 2006.211.07:23:13.49#ibcon#read 5, iclass 34, count 0 2006.211.07:23:13.49#ibcon#about to read 6, iclass 34, count 0 2006.211.07:23:13.49#ibcon#read 6, iclass 34, count 0 2006.211.07:23:13.49#ibcon#end of sib2, iclass 34, count 0 2006.211.07:23:13.49#ibcon#*mode == 0, iclass 34, count 0 2006.211.07:23:13.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.211.07:23:13.49#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.07:23:13.49#ibcon#*before write, iclass 34, count 0 2006.211.07:23:13.49#ibcon#enter sib2, iclass 34, count 0 2006.211.07:23:13.49#ibcon#flushed, iclass 34, count 0 2006.211.07:23:13.49#ibcon#about to write, iclass 34, count 0 2006.211.07:23:13.49#ibcon#wrote, iclass 34, count 0 2006.211.07:23:13.49#ibcon#about to read 3, iclass 34, count 0 2006.211.07:23:13.53#ibcon#read 3, iclass 34, count 0 2006.211.07:23:13.53#ibcon#about to read 4, iclass 34, count 0 2006.211.07:23:13.53#ibcon#read 4, iclass 34, count 0 2006.211.07:23:13.53#ibcon#about to read 5, iclass 34, count 0 2006.211.07:23:13.53#ibcon#read 5, iclass 34, count 0 2006.211.07:23:13.53#ibcon#about to read 6, iclass 34, count 0 2006.211.07:23:13.53#ibcon#read 6, iclass 34, count 0 2006.211.07:23:13.53#ibcon#end of sib2, iclass 34, count 0 2006.211.07:23:13.53#ibcon#*after write, iclass 34, count 0 2006.211.07:23:13.53#ibcon#*before return 0, iclass 34, count 0 2006.211.07:23:13.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:23:13.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.211.07:23:13.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.211.07:23:13.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.211.07:23:13.53$vc4f8/va=8,7 2006.211.07:23:13.53#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.07:23:13.53#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.07:23:13.53#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:13.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:23:13.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:23:13.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:23:13.59#ibcon#enter wrdev, iclass 37, count 2 2006.211.07:23:13.59#ibcon#first serial, iclass 37, count 2 2006.211.07:23:13.59#ibcon#enter sib2, iclass 37, count 2 2006.211.07:23:13.59#ibcon#flushed, iclass 37, count 2 2006.211.07:23:13.59#ibcon#about to write, iclass 37, count 2 2006.211.07:23:13.59#ibcon#wrote, iclass 37, count 2 2006.211.07:23:13.59#ibcon#about to read 3, iclass 37, count 2 2006.211.07:23:13.61#ibcon#read 3, iclass 37, count 2 2006.211.07:23:13.61#ibcon#about to read 4, iclass 37, count 2 2006.211.07:23:13.61#ibcon#read 4, iclass 37, count 2 2006.211.07:23:13.61#ibcon#about to read 5, iclass 37, count 2 2006.211.07:23:13.61#ibcon#read 5, iclass 37, count 2 2006.211.07:23:13.61#ibcon#about to read 6, iclass 37, count 2 2006.211.07:23:13.61#ibcon#read 6, iclass 37, count 2 2006.211.07:23:13.61#ibcon#end of sib2, iclass 37, count 2 2006.211.07:23:13.61#ibcon#*mode == 0, iclass 37, count 2 2006.211.07:23:13.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.07:23:13.61#ibcon#[25=AT08-07\r\n] 2006.211.07:23:13.61#ibcon#*before write, iclass 37, count 2 2006.211.07:23:13.61#ibcon#enter sib2, iclass 37, count 2 2006.211.07:23:13.61#ibcon#flushed, iclass 37, count 2 2006.211.07:23:13.61#ibcon#about to write, iclass 37, count 2 2006.211.07:23:13.61#ibcon#wrote, iclass 37, count 2 2006.211.07:23:13.61#ibcon#about to read 3, iclass 37, count 2 2006.211.07:23:13.64#ibcon#read 3, iclass 37, count 2 2006.211.07:23:13.64#ibcon#about to read 4, iclass 37, count 2 2006.211.07:23:13.64#ibcon#read 4, iclass 37, count 2 2006.211.07:23:13.64#ibcon#about to read 5, iclass 37, count 2 2006.211.07:23:13.64#ibcon#read 5, iclass 37, count 2 2006.211.07:23:13.64#ibcon#about to read 6, iclass 37, count 2 2006.211.07:23:13.64#ibcon#read 6, iclass 37, count 2 2006.211.07:23:13.64#ibcon#end of sib2, iclass 37, count 2 2006.211.07:23:13.64#ibcon#*after write, iclass 37, count 2 2006.211.07:23:13.64#ibcon#*before return 0, iclass 37, count 2 2006.211.07:23:13.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:23:13.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.07:23:13.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.07:23:13.64#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:13.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:23:13.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:23:13.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:23:13.76#ibcon#enter wrdev, iclass 37, count 0 2006.211.07:23:13.76#ibcon#first serial, iclass 37, count 0 2006.211.07:23:13.76#ibcon#enter sib2, iclass 37, count 0 2006.211.07:23:13.76#ibcon#flushed, iclass 37, count 0 2006.211.07:23:13.76#ibcon#about to write, iclass 37, count 0 2006.211.07:23:13.76#ibcon#wrote, iclass 37, count 0 2006.211.07:23:13.76#ibcon#about to read 3, iclass 37, count 0 2006.211.07:23:13.78#ibcon#read 3, iclass 37, count 0 2006.211.07:23:13.78#ibcon#about to read 4, iclass 37, count 0 2006.211.07:23:13.78#ibcon#read 4, iclass 37, count 0 2006.211.07:23:13.78#ibcon#about to read 5, iclass 37, count 0 2006.211.07:23:13.78#ibcon#read 5, iclass 37, count 0 2006.211.07:23:13.78#ibcon#about to read 6, iclass 37, count 0 2006.211.07:23:13.78#ibcon#read 6, iclass 37, count 0 2006.211.07:23:13.78#ibcon#end of sib2, iclass 37, count 0 2006.211.07:23:13.78#ibcon#*mode == 0, iclass 37, count 0 2006.211.07:23:13.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.07:23:13.78#ibcon#[25=USB\r\n] 2006.211.07:23:13.78#ibcon#*before write, iclass 37, count 0 2006.211.07:23:13.78#ibcon#enter sib2, iclass 37, count 0 2006.211.07:23:13.78#ibcon#flushed, iclass 37, count 0 2006.211.07:23:13.78#ibcon#about to write, iclass 37, count 0 2006.211.07:23:13.78#ibcon#wrote, iclass 37, count 0 2006.211.07:23:13.78#ibcon#about to read 3, iclass 37, count 0 2006.211.07:23:13.81#ibcon#read 3, iclass 37, count 0 2006.211.07:23:13.81#ibcon#about to read 4, iclass 37, count 0 2006.211.07:23:13.81#ibcon#read 4, iclass 37, count 0 2006.211.07:23:13.81#ibcon#about to read 5, iclass 37, count 0 2006.211.07:23:13.81#ibcon#read 5, iclass 37, count 0 2006.211.07:23:13.81#ibcon#about to read 6, iclass 37, count 0 2006.211.07:23:13.81#ibcon#read 6, iclass 37, count 0 2006.211.07:23:13.81#ibcon#end of sib2, iclass 37, count 0 2006.211.07:23:13.81#ibcon#*after write, iclass 37, count 0 2006.211.07:23:13.81#ibcon#*before return 0, iclass 37, count 0 2006.211.07:23:13.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:23:13.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.07:23:13.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.07:23:13.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.07:23:13.81$vc4f8/vblo=1,632.99 2006.211.07:23:13.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.07:23:13.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.07:23:13.81#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:13.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:23:13.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:23:13.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:23:13.81#ibcon#enter wrdev, iclass 39, count 0 2006.211.07:23:13.81#ibcon#first serial, iclass 39, count 0 2006.211.07:23:13.81#ibcon#enter sib2, iclass 39, count 0 2006.211.07:23:13.81#ibcon#flushed, iclass 39, count 0 2006.211.07:23:13.81#ibcon#about to write, iclass 39, count 0 2006.211.07:23:13.81#ibcon#wrote, iclass 39, count 0 2006.211.07:23:13.81#ibcon#about to read 3, iclass 39, count 0 2006.211.07:23:13.83#ibcon#read 3, iclass 39, count 0 2006.211.07:23:13.83#ibcon#about to read 4, iclass 39, count 0 2006.211.07:23:13.83#ibcon#read 4, iclass 39, count 0 2006.211.07:23:13.83#ibcon#about to read 5, iclass 39, count 0 2006.211.07:23:13.83#ibcon#read 5, iclass 39, count 0 2006.211.07:23:13.83#ibcon#about to read 6, iclass 39, count 0 2006.211.07:23:13.83#ibcon#read 6, iclass 39, count 0 2006.211.07:23:13.83#ibcon#end of sib2, iclass 39, count 0 2006.211.07:23:13.83#ibcon#*mode == 0, iclass 39, count 0 2006.211.07:23:13.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.07:23:13.83#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.07:23:13.83#ibcon#*before write, iclass 39, count 0 2006.211.07:23:13.83#ibcon#enter sib2, iclass 39, count 0 2006.211.07:23:13.83#ibcon#flushed, iclass 39, count 0 2006.211.07:23:13.83#ibcon#about to write, iclass 39, count 0 2006.211.07:23:13.83#ibcon#wrote, iclass 39, count 0 2006.211.07:23:13.83#ibcon#about to read 3, iclass 39, count 0 2006.211.07:23:13.87#ibcon#read 3, iclass 39, count 0 2006.211.07:23:13.87#ibcon#about to read 4, iclass 39, count 0 2006.211.07:23:13.87#ibcon#read 4, iclass 39, count 0 2006.211.07:23:13.87#ibcon#about to read 5, iclass 39, count 0 2006.211.07:23:13.87#ibcon#read 5, iclass 39, count 0 2006.211.07:23:13.87#ibcon#about to read 6, iclass 39, count 0 2006.211.07:23:13.87#ibcon#read 6, iclass 39, count 0 2006.211.07:23:13.87#ibcon#end of sib2, iclass 39, count 0 2006.211.07:23:13.87#ibcon#*after write, iclass 39, count 0 2006.211.07:23:13.87#ibcon#*before return 0, iclass 39, count 0 2006.211.07:23:13.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:23:13.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.07:23:13.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.07:23:13.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.07:23:13.87$vc4f8/vb=1,4 2006.211.07:23:13.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.07:23:13.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.07:23:13.87#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:13.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:23:13.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:23:13.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:23:13.87#ibcon#enter wrdev, iclass 3, count 2 2006.211.07:23:13.87#ibcon#first serial, iclass 3, count 2 2006.211.07:23:13.87#ibcon#enter sib2, iclass 3, count 2 2006.211.07:23:13.87#ibcon#flushed, iclass 3, count 2 2006.211.07:23:13.87#ibcon#about to write, iclass 3, count 2 2006.211.07:23:13.87#ibcon#wrote, iclass 3, count 2 2006.211.07:23:13.87#ibcon#about to read 3, iclass 3, count 2 2006.211.07:23:13.89#ibcon#read 3, iclass 3, count 2 2006.211.07:23:13.89#ibcon#about to read 4, iclass 3, count 2 2006.211.07:23:13.89#ibcon#read 4, iclass 3, count 2 2006.211.07:23:13.89#ibcon#about to read 5, iclass 3, count 2 2006.211.07:23:13.89#ibcon#read 5, iclass 3, count 2 2006.211.07:23:13.89#ibcon#about to read 6, iclass 3, count 2 2006.211.07:23:13.89#ibcon#read 6, iclass 3, count 2 2006.211.07:23:13.89#ibcon#end of sib2, iclass 3, count 2 2006.211.07:23:13.89#ibcon#*mode == 0, iclass 3, count 2 2006.211.07:23:13.89#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.07:23:13.89#ibcon#[27=AT01-04\r\n] 2006.211.07:23:13.89#ibcon#*before write, iclass 3, count 2 2006.211.07:23:13.89#ibcon#enter sib2, iclass 3, count 2 2006.211.07:23:13.89#ibcon#flushed, iclass 3, count 2 2006.211.07:23:13.89#ibcon#about to write, iclass 3, count 2 2006.211.07:23:13.89#ibcon#wrote, iclass 3, count 2 2006.211.07:23:13.89#ibcon#about to read 3, iclass 3, count 2 2006.211.07:23:13.92#ibcon#read 3, iclass 3, count 2 2006.211.07:23:13.92#ibcon#about to read 4, iclass 3, count 2 2006.211.07:23:13.92#ibcon#read 4, iclass 3, count 2 2006.211.07:23:13.92#ibcon#about to read 5, iclass 3, count 2 2006.211.07:23:13.92#ibcon#read 5, iclass 3, count 2 2006.211.07:23:13.92#ibcon#about to read 6, iclass 3, count 2 2006.211.07:23:13.92#ibcon#read 6, iclass 3, count 2 2006.211.07:23:13.92#ibcon#end of sib2, iclass 3, count 2 2006.211.07:23:13.92#ibcon#*after write, iclass 3, count 2 2006.211.07:23:13.92#ibcon#*before return 0, iclass 3, count 2 2006.211.07:23:13.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:23:13.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.07:23:13.92#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.07:23:13.92#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:13.92#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:23:14.04#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:23:14.04#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:23:14.04#ibcon#enter wrdev, iclass 3, count 0 2006.211.07:23:14.04#ibcon#first serial, iclass 3, count 0 2006.211.07:23:14.04#ibcon#enter sib2, iclass 3, count 0 2006.211.07:23:14.04#ibcon#flushed, iclass 3, count 0 2006.211.07:23:14.04#ibcon#about to write, iclass 3, count 0 2006.211.07:23:14.04#ibcon#wrote, iclass 3, count 0 2006.211.07:23:14.04#ibcon#about to read 3, iclass 3, count 0 2006.211.07:23:14.06#ibcon#read 3, iclass 3, count 0 2006.211.07:23:14.06#ibcon#about to read 4, iclass 3, count 0 2006.211.07:23:14.06#ibcon#read 4, iclass 3, count 0 2006.211.07:23:14.06#ibcon#about to read 5, iclass 3, count 0 2006.211.07:23:14.06#ibcon#read 5, iclass 3, count 0 2006.211.07:23:14.06#ibcon#about to read 6, iclass 3, count 0 2006.211.07:23:14.06#ibcon#read 6, iclass 3, count 0 2006.211.07:23:14.06#ibcon#end of sib2, iclass 3, count 0 2006.211.07:23:14.06#ibcon#*mode == 0, iclass 3, count 0 2006.211.07:23:14.06#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.07:23:14.06#ibcon#[27=USB\r\n] 2006.211.07:23:14.06#ibcon#*before write, iclass 3, count 0 2006.211.07:23:14.06#ibcon#enter sib2, iclass 3, count 0 2006.211.07:23:14.06#ibcon#flushed, iclass 3, count 0 2006.211.07:23:14.06#ibcon#about to write, iclass 3, count 0 2006.211.07:23:14.06#ibcon#wrote, iclass 3, count 0 2006.211.07:23:14.06#ibcon#about to read 3, iclass 3, count 0 2006.211.07:23:14.09#ibcon#read 3, iclass 3, count 0 2006.211.07:23:14.09#ibcon#about to read 4, iclass 3, count 0 2006.211.07:23:14.09#ibcon#read 4, iclass 3, count 0 2006.211.07:23:14.09#ibcon#about to read 5, iclass 3, count 0 2006.211.07:23:14.09#ibcon#read 5, iclass 3, count 0 2006.211.07:23:14.09#ibcon#about to read 6, iclass 3, count 0 2006.211.07:23:14.09#ibcon#read 6, iclass 3, count 0 2006.211.07:23:14.09#ibcon#end of sib2, iclass 3, count 0 2006.211.07:23:14.09#ibcon#*after write, iclass 3, count 0 2006.211.07:23:14.09#ibcon#*before return 0, iclass 3, count 0 2006.211.07:23:14.09#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:23:14.09#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.07:23:14.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.07:23:14.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.07:23:14.09$vc4f8/vblo=2,640.99 2006.211.07:23:14.09#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.07:23:14.09#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.07:23:14.09#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:14.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:23:14.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:23:14.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:23:14.09#ibcon#enter wrdev, iclass 5, count 0 2006.211.07:23:14.09#ibcon#first serial, iclass 5, count 0 2006.211.07:23:14.09#ibcon#enter sib2, iclass 5, count 0 2006.211.07:23:14.09#ibcon#flushed, iclass 5, count 0 2006.211.07:23:14.09#ibcon#about to write, iclass 5, count 0 2006.211.07:23:14.09#ibcon#wrote, iclass 5, count 0 2006.211.07:23:14.09#ibcon#about to read 3, iclass 5, count 0 2006.211.07:23:14.11#ibcon#read 3, iclass 5, count 0 2006.211.07:23:14.11#ibcon#about to read 4, iclass 5, count 0 2006.211.07:23:14.11#ibcon#read 4, iclass 5, count 0 2006.211.07:23:14.11#ibcon#about to read 5, iclass 5, count 0 2006.211.07:23:14.11#ibcon#read 5, iclass 5, count 0 2006.211.07:23:14.11#ibcon#about to read 6, iclass 5, count 0 2006.211.07:23:14.11#ibcon#read 6, iclass 5, count 0 2006.211.07:23:14.11#ibcon#end of sib2, iclass 5, count 0 2006.211.07:23:14.11#ibcon#*mode == 0, iclass 5, count 0 2006.211.07:23:14.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.07:23:14.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.07:23:14.11#ibcon#*before write, iclass 5, count 0 2006.211.07:23:14.11#ibcon#enter sib2, iclass 5, count 0 2006.211.07:23:14.11#ibcon#flushed, iclass 5, count 0 2006.211.07:23:14.11#ibcon#about to write, iclass 5, count 0 2006.211.07:23:14.11#ibcon#wrote, iclass 5, count 0 2006.211.07:23:14.11#ibcon#about to read 3, iclass 5, count 0 2006.211.07:23:14.15#ibcon#read 3, iclass 5, count 0 2006.211.07:23:14.15#ibcon#about to read 4, iclass 5, count 0 2006.211.07:23:14.15#ibcon#read 4, iclass 5, count 0 2006.211.07:23:14.15#ibcon#about to read 5, iclass 5, count 0 2006.211.07:23:14.15#ibcon#read 5, iclass 5, count 0 2006.211.07:23:14.15#ibcon#about to read 6, iclass 5, count 0 2006.211.07:23:14.15#ibcon#read 6, iclass 5, count 0 2006.211.07:23:14.15#ibcon#end of sib2, iclass 5, count 0 2006.211.07:23:14.15#ibcon#*after write, iclass 5, count 0 2006.211.07:23:14.15#ibcon#*before return 0, iclass 5, count 0 2006.211.07:23:14.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:23:14.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.07:23:14.15#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.07:23:14.15#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.07:23:14.15$vc4f8/vb=2,4 2006.211.07:23:14.15#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.07:23:14.15#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.07:23:14.15#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:14.15#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:23:14.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:23:14.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:23:14.21#ibcon#enter wrdev, iclass 7, count 2 2006.211.07:23:14.21#ibcon#first serial, iclass 7, count 2 2006.211.07:23:14.21#ibcon#enter sib2, iclass 7, count 2 2006.211.07:23:14.21#ibcon#flushed, iclass 7, count 2 2006.211.07:23:14.21#ibcon#about to write, iclass 7, count 2 2006.211.07:23:14.21#ibcon#wrote, iclass 7, count 2 2006.211.07:23:14.21#ibcon#about to read 3, iclass 7, count 2 2006.211.07:23:14.23#ibcon#read 3, iclass 7, count 2 2006.211.07:23:14.23#ibcon#about to read 4, iclass 7, count 2 2006.211.07:23:14.23#ibcon#read 4, iclass 7, count 2 2006.211.07:23:14.23#ibcon#about to read 5, iclass 7, count 2 2006.211.07:23:14.23#ibcon#read 5, iclass 7, count 2 2006.211.07:23:14.23#ibcon#about to read 6, iclass 7, count 2 2006.211.07:23:14.23#ibcon#read 6, iclass 7, count 2 2006.211.07:23:14.23#ibcon#end of sib2, iclass 7, count 2 2006.211.07:23:14.23#ibcon#*mode == 0, iclass 7, count 2 2006.211.07:23:14.23#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.07:23:14.23#ibcon#[27=AT02-04\r\n] 2006.211.07:23:14.23#ibcon#*before write, iclass 7, count 2 2006.211.07:23:14.23#ibcon#enter sib2, iclass 7, count 2 2006.211.07:23:14.23#ibcon#flushed, iclass 7, count 2 2006.211.07:23:14.23#ibcon#about to write, iclass 7, count 2 2006.211.07:23:14.23#ibcon#wrote, iclass 7, count 2 2006.211.07:23:14.23#ibcon#about to read 3, iclass 7, count 2 2006.211.07:23:14.26#ibcon#read 3, iclass 7, count 2 2006.211.07:23:14.26#ibcon#about to read 4, iclass 7, count 2 2006.211.07:23:14.26#ibcon#read 4, iclass 7, count 2 2006.211.07:23:14.26#ibcon#about to read 5, iclass 7, count 2 2006.211.07:23:14.26#ibcon#read 5, iclass 7, count 2 2006.211.07:23:14.26#ibcon#about to read 6, iclass 7, count 2 2006.211.07:23:14.26#ibcon#read 6, iclass 7, count 2 2006.211.07:23:14.26#ibcon#end of sib2, iclass 7, count 2 2006.211.07:23:14.26#ibcon#*after write, iclass 7, count 2 2006.211.07:23:14.26#ibcon#*before return 0, iclass 7, count 2 2006.211.07:23:14.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:23:14.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.07:23:14.26#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.07:23:14.26#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:14.26#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:23:14.38#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:23:14.38#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:23:14.38#ibcon#enter wrdev, iclass 7, count 0 2006.211.07:23:14.38#ibcon#first serial, iclass 7, count 0 2006.211.07:23:14.38#ibcon#enter sib2, iclass 7, count 0 2006.211.07:23:14.38#ibcon#flushed, iclass 7, count 0 2006.211.07:23:14.38#ibcon#about to write, iclass 7, count 0 2006.211.07:23:14.38#ibcon#wrote, iclass 7, count 0 2006.211.07:23:14.38#ibcon#about to read 3, iclass 7, count 0 2006.211.07:23:14.40#ibcon#read 3, iclass 7, count 0 2006.211.07:23:14.40#ibcon#about to read 4, iclass 7, count 0 2006.211.07:23:14.40#ibcon#read 4, iclass 7, count 0 2006.211.07:23:14.40#ibcon#about to read 5, iclass 7, count 0 2006.211.07:23:14.40#ibcon#read 5, iclass 7, count 0 2006.211.07:23:14.40#ibcon#about to read 6, iclass 7, count 0 2006.211.07:23:14.40#ibcon#read 6, iclass 7, count 0 2006.211.07:23:14.40#ibcon#end of sib2, iclass 7, count 0 2006.211.07:23:14.40#ibcon#*mode == 0, iclass 7, count 0 2006.211.07:23:14.40#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.07:23:14.40#ibcon#[27=USB\r\n] 2006.211.07:23:14.40#ibcon#*before write, iclass 7, count 0 2006.211.07:23:14.40#ibcon#enter sib2, iclass 7, count 0 2006.211.07:23:14.40#ibcon#flushed, iclass 7, count 0 2006.211.07:23:14.40#ibcon#about to write, iclass 7, count 0 2006.211.07:23:14.40#ibcon#wrote, iclass 7, count 0 2006.211.07:23:14.40#ibcon#about to read 3, iclass 7, count 0 2006.211.07:23:14.43#ibcon#read 3, iclass 7, count 0 2006.211.07:23:14.43#ibcon#about to read 4, iclass 7, count 0 2006.211.07:23:14.43#ibcon#read 4, iclass 7, count 0 2006.211.07:23:14.43#ibcon#about to read 5, iclass 7, count 0 2006.211.07:23:14.43#ibcon#read 5, iclass 7, count 0 2006.211.07:23:14.43#ibcon#about to read 6, iclass 7, count 0 2006.211.07:23:14.43#ibcon#read 6, iclass 7, count 0 2006.211.07:23:14.43#ibcon#end of sib2, iclass 7, count 0 2006.211.07:23:14.43#ibcon#*after write, iclass 7, count 0 2006.211.07:23:14.43#ibcon#*before return 0, iclass 7, count 0 2006.211.07:23:14.43#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:23:14.43#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.07:23:14.43#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.07:23:14.43#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.07:23:14.43$vc4f8/vblo=3,656.99 2006.211.07:23:14.43#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.211.07:23:14.43#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.211.07:23:14.43#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:14.43#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:23:14.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:23:14.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:23:14.43#ibcon#enter wrdev, iclass 11, count 0 2006.211.07:23:14.43#ibcon#first serial, iclass 11, count 0 2006.211.07:23:14.43#ibcon#enter sib2, iclass 11, count 0 2006.211.07:23:14.43#ibcon#flushed, iclass 11, count 0 2006.211.07:23:14.43#ibcon#about to write, iclass 11, count 0 2006.211.07:23:14.43#ibcon#wrote, iclass 11, count 0 2006.211.07:23:14.43#ibcon#about to read 3, iclass 11, count 0 2006.211.07:23:14.45#ibcon#read 3, iclass 11, count 0 2006.211.07:23:14.45#ibcon#about to read 4, iclass 11, count 0 2006.211.07:23:14.45#ibcon#read 4, iclass 11, count 0 2006.211.07:23:14.45#ibcon#about to read 5, iclass 11, count 0 2006.211.07:23:14.45#ibcon#read 5, iclass 11, count 0 2006.211.07:23:14.45#ibcon#about to read 6, iclass 11, count 0 2006.211.07:23:14.45#ibcon#read 6, iclass 11, count 0 2006.211.07:23:14.45#ibcon#end of sib2, iclass 11, count 0 2006.211.07:23:14.45#ibcon#*mode == 0, iclass 11, count 0 2006.211.07:23:14.45#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.211.07:23:14.45#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.07:23:14.45#ibcon#*before write, iclass 11, count 0 2006.211.07:23:14.45#ibcon#enter sib2, iclass 11, count 0 2006.211.07:23:14.45#ibcon#flushed, iclass 11, count 0 2006.211.07:23:14.45#ibcon#about to write, iclass 11, count 0 2006.211.07:23:14.45#ibcon#wrote, iclass 11, count 0 2006.211.07:23:14.45#ibcon#about to read 3, iclass 11, count 0 2006.211.07:23:14.49#ibcon#read 3, iclass 11, count 0 2006.211.07:23:14.49#ibcon#about to read 4, iclass 11, count 0 2006.211.07:23:14.49#ibcon#read 4, iclass 11, count 0 2006.211.07:23:14.49#ibcon#about to read 5, iclass 11, count 0 2006.211.07:23:14.49#ibcon#read 5, iclass 11, count 0 2006.211.07:23:14.49#ibcon#about to read 6, iclass 11, count 0 2006.211.07:23:14.49#ibcon#read 6, iclass 11, count 0 2006.211.07:23:14.49#ibcon#end of sib2, iclass 11, count 0 2006.211.07:23:14.49#ibcon#*after write, iclass 11, count 0 2006.211.07:23:14.49#ibcon#*before return 0, iclass 11, count 0 2006.211.07:23:14.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:23:14.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.211.07:23:14.49#ibcon#about to clear, iclass 11 cls_cnt 0 2006.211.07:23:14.49#ibcon#cleared, iclass 11 cls_cnt 0 2006.211.07:23:14.49$vc4f8/vb=3,3 2006.211.07:23:14.49#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.211.07:23:14.49#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.211.07:23:14.49#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:14.49#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:23:14.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:23:14.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:23:14.55#ibcon#enter wrdev, iclass 13, count 2 2006.211.07:23:14.55#ibcon#first serial, iclass 13, count 2 2006.211.07:23:14.55#ibcon#enter sib2, iclass 13, count 2 2006.211.07:23:14.55#ibcon#flushed, iclass 13, count 2 2006.211.07:23:14.55#ibcon#about to write, iclass 13, count 2 2006.211.07:23:14.55#ibcon#wrote, iclass 13, count 2 2006.211.07:23:14.55#ibcon#about to read 3, iclass 13, count 2 2006.211.07:23:14.57#ibcon#read 3, iclass 13, count 2 2006.211.07:23:14.57#ibcon#about to read 4, iclass 13, count 2 2006.211.07:23:14.57#ibcon#read 4, iclass 13, count 2 2006.211.07:23:14.57#ibcon#about to read 5, iclass 13, count 2 2006.211.07:23:14.57#ibcon#read 5, iclass 13, count 2 2006.211.07:23:14.57#ibcon#about to read 6, iclass 13, count 2 2006.211.07:23:14.57#ibcon#read 6, iclass 13, count 2 2006.211.07:23:14.57#ibcon#end of sib2, iclass 13, count 2 2006.211.07:23:14.57#ibcon#*mode == 0, iclass 13, count 2 2006.211.07:23:14.57#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.211.07:23:14.57#ibcon#[27=AT03-03\r\n] 2006.211.07:23:14.57#ibcon#*before write, iclass 13, count 2 2006.211.07:23:14.57#ibcon#enter sib2, iclass 13, count 2 2006.211.07:23:14.57#ibcon#flushed, iclass 13, count 2 2006.211.07:23:14.57#ibcon#about to write, iclass 13, count 2 2006.211.07:23:14.57#ibcon#wrote, iclass 13, count 2 2006.211.07:23:14.57#ibcon#about to read 3, iclass 13, count 2 2006.211.07:23:14.60#ibcon#read 3, iclass 13, count 2 2006.211.07:23:14.60#ibcon#about to read 4, iclass 13, count 2 2006.211.07:23:14.60#ibcon#read 4, iclass 13, count 2 2006.211.07:23:14.60#ibcon#about to read 5, iclass 13, count 2 2006.211.07:23:14.60#ibcon#read 5, iclass 13, count 2 2006.211.07:23:14.60#ibcon#about to read 6, iclass 13, count 2 2006.211.07:23:14.60#ibcon#read 6, iclass 13, count 2 2006.211.07:23:14.60#ibcon#end of sib2, iclass 13, count 2 2006.211.07:23:14.60#ibcon#*after write, iclass 13, count 2 2006.211.07:23:14.60#ibcon#*before return 0, iclass 13, count 2 2006.211.07:23:14.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:23:14.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.211.07:23:14.60#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.211.07:23:14.60#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:14.60#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:23:14.72#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:23:14.72#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:23:14.72#ibcon#enter wrdev, iclass 13, count 0 2006.211.07:23:14.72#ibcon#first serial, iclass 13, count 0 2006.211.07:23:14.72#ibcon#enter sib2, iclass 13, count 0 2006.211.07:23:14.72#ibcon#flushed, iclass 13, count 0 2006.211.07:23:14.72#ibcon#about to write, iclass 13, count 0 2006.211.07:23:14.72#ibcon#wrote, iclass 13, count 0 2006.211.07:23:14.72#ibcon#about to read 3, iclass 13, count 0 2006.211.07:23:14.74#ibcon#read 3, iclass 13, count 0 2006.211.07:23:14.74#ibcon#about to read 4, iclass 13, count 0 2006.211.07:23:14.74#ibcon#read 4, iclass 13, count 0 2006.211.07:23:14.74#ibcon#about to read 5, iclass 13, count 0 2006.211.07:23:14.74#ibcon#read 5, iclass 13, count 0 2006.211.07:23:14.74#ibcon#about to read 6, iclass 13, count 0 2006.211.07:23:14.74#ibcon#read 6, iclass 13, count 0 2006.211.07:23:14.74#ibcon#end of sib2, iclass 13, count 0 2006.211.07:23:14.74#ibcon#*mode == 0, iclass 13, count 0 2006.211.07:23:14.74#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.211.07:23:14.74#ibcon#[27=USB\r\n] 2006.211.07:23:14.74#ibcon#*before write, iclass 13, count 0 2006.211.07:23:14.74#ibcon#enter sib2, iclass 13, count 0 2006.211.07:23:14.74#ibcon#flushed, iclass 13, count 0 2006.211.07:23:14.74#ibcon#about to write, iclass 13, count 0 2006.211.07:23:14.74#ibcon#wrote, iclass 13, count 0 2006.211.07:23:14.74#ibcon#about to read 3, iclass 13, count 0 2006.211.07:23:14.77#ibcon#read 3, iclass 13, count 0 2006.211.07:23:14.77#ibcon#about to read 4, iclass 13, count 0 2006.211.07:23:14.77#ibcon#read 4, iclass 13, count 0 2006.211.07:23:14.77#ibcon#about to read 5, iclass 13, count 0 2006.211.07:23:14.77#ibcon#read 5, iclass 13, count 0 2006.211.07:23:14.77#ibcon#about to read 6, iclass 13, count 0 2006.211.07:23:14.77#ibcon#read 6, iclass 13, count 0 2006.211.07:23:14.77#ibcon#end of sib2, iclass 13, count 0 2006.211.07:23:14.77#ibcon#*after write, iclass 13, count 0 2006.211.07:23:14.77#ibcon#*before return 0, iclass 13, count 0 2006.211.07:23:14.77#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:23:14.77#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.211.07:23:14.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.211.07:23:14.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.211.07:23:14.77$vc4f8/vblo=4,712.99 2006.211.07:23:14.77#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.07:23:14.77#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.07:23:14.77#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:14.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:23:14.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:23:14.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:23:14.77#ibcon#enter wrdev, iclass 15, count 0 2006.211.07:23:14.77#ibcon#first serial, iclass 15, count 0 2006.211.07:23:14.77#ibcon#enter sib2, iclass 15, count 0 2006.211.07:23:14.77#ibcon#flushed, iclass 15, count 0 2006.211.07:23:14.77#ibcon#about to write, iclass 15, count 0 2006.211.07:23:14.77#ibcon#wrote, iclass 15, count 0 2006.211.07:23:14.77#ibcon#about to read 3, iclass 15, count 0 2006.211.07:23:14.79#ibcon#read 3, iclass 15, count 0 2006.211.07:23:14.79#ibcon#about to read 4, iclass 15, count 0 2006.211.07:23:14.79#ibcon#read 4, iclass 15, count 0 2006.211.07:23:14.79#ibcon#about to read 5, iclass 15, count 0 2006.211.07:23:14.79#ibcon#read 5, iclass 15, count 0 2006.211.07:23:14.79#ibcon#about to read 6, iclass 15, count 0 2006.211.07:23:14.79#ibcon#read 6, iclass 15, count 0 2006.211.07:23:14.79#ibcon#end of sib2, iclass 15, count 0 2006.211.07:23:14.79#ibcon#*mode == 0, iclass 15, count 0 2006.211.07:23:14.79#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.07:23:14.79#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.07:23:14.79#ibcon#*before write, iclass 15, count 0 2006.211.07:23:14.79#ibcon#enter sib2, iclass 15, count 0 2006.211.07:23:14.79#ibcon#flushed, iclass 15, count 0 2006.211.07:23:14.79#ibcon#about to write, iclass 15, count 0 2006.211.07:23:14.79#ibcon#wrote, iclass 15, count 0 2006.211.07:23:14.79#ibcon#about to read 3, iclass 15, count 0 2006.211.07:23:14.83#ibcon#read 3, iclass 15, count 0 2006.211.07:23:14.83#ibcon#about to read 4, iclass 15, count 0 2006.211.07:23:14.83#ibcon#read 4, iclass 15, count 0 2006.211.07:23:14.83#ibcon#about to read 5, iclass 15, count 0 2006.211.07:23:14.83#ibcon#read 5, iclass 15, count 0 2006.211.07:23:14.83#ibcon#about to read 6, iclass 15, count 0 2006.211.07:23:14.83#ibcon#read 6, iclass 15, count 0 2006.211.07:23:14.83#ibcon#end of sib2, iclass 15, count 0 2006.211.07:23:14.83#ibcon#*after write, iclass 15, count 0 2006.211.07:23:14.83#ibcon#*before return 0, iclass 15, count 0 2006.211.07:23:14.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:23:14.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.07:23:14.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.07:23:14.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.07:23:14.83$vc4f8/vb=4,3 2006.211.07:23:14.83#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.07:23:14.83#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.07:23:14.83#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:14.83#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:23:14.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:23:14.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:23:14.89#ibcon#enter wrdev, iclass 17, count 2 2006.211.07:23:14.89#ibcon#first serial, iclass 17, count 2 2006.211.07:23:14.89#ibcon#enter sib2, iclass 17, count 2 2006.211.07:23:14.89#ibcon#flushed, iclass 17, count 2 2006.211.07:23:14.89#ibcon#about to write, iclass 17, count 2 2006.211.07:23:14.89#ibcon#wrote, iclass 17, count 2 2006.211.07:23:14.89#ibcon#about to read 3, iclass 17, count 2 2006.211.07:23:14.91#ibcon#read 3, iclass 17, count 2 2006.211.07:23:14.91#ibcon#about to read 4, iclass 17, count 2 2006.211.07:23:14.91#ibcon#read 4, iclass 17, count 2 2006.211.07:23:14.91#ibcon#about to read 5, iclass 17, count 2 2006.211.07:23:14.91#ibcon#read 5, iclass 17, count 2 2006.211.07:23:14.91#ibcon#about to read 6, iclass 17, count 2 2006.211.07:23:14.91#ibcon#read 6, iclass 17, count 2 2006.211.07:23:14.91#ibcon#end of sib2, iclass 17, count 2 2006.211.07:23:14.91#ibcon#*mode == 0, iclass 17, count 2 2006.211.07:23:14.91#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.07:23:14.91#ibcon#[27=AT04-03\r\n] 2006.211.07:23:14.91#ibcon#*before write, iclass 17, count 2 2006.211.07:23:14.91#ibcon#enter sib2, iclass 17, count 2 2006.211.07:23:14.91#ibcon#flushed, iclass 17, count 2 2006.211.07:23:14.91#ibcon#about to write, iclass 17, count 2 2006.211.07:23:14.91#ibcon#wrote, iclass 17, count 2 2006.211.07:23:14.91#ibcon#about to read 3, iclass 17, count 2 2006.211.07:23:14.94#ibcon#read 3, iclass 17, count 2 2006.211.07:23:14.94#ibcon#about to read 4, iclass 17, count 2 2006.211.07:23:14.94#ibcon#read 4, iclass 17, count 2 2006.211.07:23:14.94#ibcon#about to read 5, iclass 17, count 2 2006.211.07:23:14.94#ibcon#read 5, iclass 17, count 2 2006.211.07:23:14.94#ibcon#about to read 6, iclass 17, count 2 2006.211.07:23:14.94#ibcon#read 6, iclass 17, count 2 2006.211.07:23:14.94#ibcon#end of sib2, iclass 17, count 2 2006.211.07:23:14.94#ibcon#*after write, iclass 17, count 2 2006.211.07:23:14.94#ibcon#*before return 0, iclass 17, count 2 2006.211.07:23:14.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:23:14.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.07:23:14.94#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.07:23:14.94#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:14.94#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:23:15.06#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:23:15.06#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:23:15.06#ibcon#enter wrdev, iclass 17, count 0 2006.211.07:23:15.06#ibcon#first serial, iclass 17, count 0 2006.211.07:23:15.06#ibcon#enter sib2, iclass 17, count 0 2006.211.07:23:15.06#ibcon#flushed, iclass 17, count 0 2006.211.07:23:15.06#ibcon#about to write, iclass 17, count 0 2006.211.07:23:15.06#ibcon#wrote, iclass 17, count 0 2006.211.07:23:15.06#ibcon#about to read 3, iclass 17, count 0 2006.211.07:23:15.08#ibcon#read 3, iclass 17, count 0 2006.211.07:23:15.08#ibcon#about to read 4, iclass 17, count 0 2006.211.07:23:15.08#ibcon#read 4, iclass 17, count 0 2006.211.07:23:15.08#ibcon#about to read 5, iclass 17, count 0 2006.211.07:23:15.08#ibcon#read 5, iclass 17, count 0 2006.211.07:23:15.08#ibcon#about to read 6, iclass 17, count 0 2006.211.07:23:15.08#ibcon#read 6, iclass 17, count 0 2006.211.07:23:15.08#ibcon#end of sib2, iclass 17, count 0 2006.211.07:23:15.08#ibcon#*mode == 0, iclass 17, count 0 2006.211.07:23:15.08#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.07:23:15.08#ibcon#[27=USB\r\n] 2006.211.07:23:15.08#ibcon#*before write, iclass 17, count 0 2006.211.07:23:15.08#ibcon#enter sib2, iclass 17, count 0 2006.211.07:23:15.08#ibcon#flushed, iclass 17, count 0 2006.211.07:23:15.08#ibcon#about to write, iclass 17, count 0 2006.211.07:23:15.08#ibcon#wrote, iclass 17, count 0 2006.211.07:23:15.08#ibcon#about to read 3, iclass 17, count 0 2006.211.07:23:15.11#ibcon#read 3, iclass 17, count 0 2006.211.07:23:15.11#ibcon#about to read 4, iclass 17, count 0 2006.211.07:23:15.11#ibcon#read 4, iclass 17, count 0 2006.211.07:23:15.11#ibcon#about to read 5, iclass 17, count 0 2006.211.07:23:15.11#ibcon#read 5, iclass 17, count 0 2006.211.07:23:15.11#ibcon#about to read 6, iclass 17, count 0 2006.211.07:23:15.11#ibcon#read 6, iclass 17, count 0 2006.211.07:23:15.11#ibcon#end of sib2, iclass 17, count 0 2006.211.07:23:15.11#ibcon#*after write, iclass 17, count 0 2006.211.07:23:15.11#ibcon#*before return 0, iclass 17, count 0 2006.211.07:23:15.11#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:23:15.11#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.07:23:15.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.07:23:15.11#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.07:23:15.11$vc4f8/vblo=5,744.99 2006.211.07:23:15.11#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.07:23:15.11#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.07:23:15.11#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:15.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:23:15.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:23:15.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:23:15.11#ibcon#enter wrdev, iclass 19, count 0 2006.211.07:23:15.11#ibcon#first serial, iclass 19, count 0 2006.211.07:23:15.11#ibcon#enter sib2, iclass 19, count 0 2006.211.07:23:15.11#ibcon#flushed, iclass 19, count 0 2006.211.07:23:15.11#ibcon#about to write, iclass 19, count 0 2006.211.07:23:15.11#ibcon#wrote, iclass 19, count 0 2006.211.07:23:15.11#ibcon#about to read 3, iclass 19, count 0 2006.211.07:23:15.13#ibcon#read 3, iclass 19, count 0 2006.211.07:23:15.13#ibcon#about to read 4, iclass 19, count 0 2006.211.07:23:15.13#ibcon#read 4, iclass 19, count 0 2006.211.07:23:15.13#ibcon#about to read 5, iclass 19, count 0 2006.211.07:23:15.13#ibcon#read 5, iclass 19, count 0 2006.211.07:23:15.13#ibcon#about to read 6, iclass 19, count 0 2006.211.07:23:15.13#ibcon#read 6, iclass 19, count 0 2006.211.07:23:15.13#ibcon#end of sib2, iclass 19, count 0 2006.211.07:23:15.13#ibcon#*mode == 0, iclass 19, count 0 2006.211.07:23:15.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.07:23:15.13#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.07:23:15.13#ibcon#*before write, iclass 19, count 0 2006.211.07:23:15.13#ibcon#enter sib2, iclass 19, count 0 2006.211.07:23:15.13#ibcon#flushed, iclass 19, count 0 2006.211.07:23:15.13#ibcon#about to write, iclass 19, count 0 2006.211.07:23:15.13#ibcon#wrote, iclass 19, count 0 2006.211.07:23:15.13#ibcon#about to read 3, iclass 19, count 0 2006.211.07:23:15.17#ibcon#read 3, iclass 19, count 0 2006.211.07:23:15.17#ibcon#about to read 4, iclass 19, count 0 2006.211.07:23:15.17#ibcon#read 4, iclass 19, count 0 2006.211.07:23:15.17#ibcon#about to read 5, iclass 19, count 0 2006.211.07:23:15.17#ibcon#read 5, iclass 19, count 0 2006.211.07:23:15.17#ibcon#about to read 6, iclass 19, count 0 2006.211.07:23:15.17#ibcon#read 6, iclass 19, count 0 2006.211.07:23:15.17#ibcon#end of sib2, iclass 19, count 0 2006.211.07:23:15.17#ibcon#*after write, iclass 19, count 0 2006.211.07:23:15.17#ibcon#*before return 0, iclass 19, count 0 2006.211.07:23:15.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:23:15.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.07:23:15.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.07:23:15.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.07:23:15.17$vc4f8/vb=5,3 2006.211.07:23:15.17#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.07:23:15.17#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.07:23:15.17#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:15.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:23:15.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:23:15.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:23:15.23#ibcon#enter wrdev, iclass 21, count 2 2006.211.07:23:15.23#ibcon#first serial, iclass 21, count 2 2006.211.07:23:15.23#ibcon#enter sib2, iclass 21, count 2 2006.211.07:23:15.23#ibcon#flushed, iclass 21, count 2 2006.211.07:23:15.23#ibcon#about to write, iclass 21, count 2 2006.211.07:23:15.23#ibcon#wrote, iclass 21, count 2 2006.211.07:23:15.23#ibcon#about to read 3, iclass 21, count 2 2006.211.07:23:15.25#ibcon#read 3, iclass 21, count 2 2006.211.07:23:15.25#ibcon#about to read 4, iclass 21, count 2 2006.211.07:23:15.25#ibcon#read 4, iclass 21, count 2 2006.211.07:23:15.25#ibcon#about to read 5, iclass 21, count 2 2006.211.07:23:15.25#ibcon#read 5, iclass 21, count 2 2006.211.07:23:15.25#ibcon#about to read 6, iclass 21, count 2 2006.211.07:23:15.25#ibcon#read 6, iclass 21, count 2 2006.211.07:23:15.25#ibcon#end of sib2, iclass 21, count 2 2006.211.07:23:15.25#ibcon#*mode == 0, iclass 21, count 2 2006.211.07:23:15.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.07:23:15.25#ibcon#[27=AT05-03\r\n] 2006.211.07:23:15.25#ibcon#*before write, iclass 21, count 2 2006.211.07:23:15.25#ibcon#enter sib2, iclass 21, count 2 2006.211.07:23:15.25#ibcon#flushed, iclass 21, count 2 2006.211.07:23:15.25#ibcon#about to write, iclass 21, count 2 2006.211.07:23:15.25#ibcon#wrote, iclass 21, count 2 2006.211.07:23:15.25#ibcon#about to read 3, iclass 21, count 2 2006.211.07:23:15.28#ibcon#read 3, iclass 21, count 2 2006.211.07:23:15.28#ibcon#about to read 4, iclass 21, count 2 2006.211.07:23:15.28#ibcon#read 4, iclass 21, count 2 2006.211.07:23:15.28#ibcon#about to read 5, iclass 21, count 2 2006.211.07:23:15.28#ibcon#read 5, iclass 21, count 2 2006.211.07:23:15.28#ibcon#about to read 6, iclass 21, count 2 2006.211.07:23:15.28#ibcon#read 6, iclass 21, count 2 2006.211.07:23:15.28#ibcon#end of sib2, iclass 21, count 2 2006.211.07:23:15.28#ibcon#*after write, iclass 21, count 2 2006.211.07:23:15.28#ibcon#*before return 0, iclass 21, count 2 2006.211.07:23:15.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:23:15.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.07:23:15.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.07:23:15.28#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:15.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:23:15.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:23:15.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:23:15.40#ibcon#enter wrdev, iclass 21, count 0 2006.211.07:23:15.40#ibcon#first serial, iclass 21, count 0 2006.211.07:23:15.40#ibcon#enter sib2, iclass 21, count 0 2006.211.07:23:15.40#ibcon#flushed, iclass 21, count 0 2006.211.07:23:15.40#ibcon#about to write, iclass 21, count 0 2006.211.07:23:15.40#ibcon#wrote, iclass 21, count 0 2006.211.07:23:15.40#ibcon#about to read 3, iclass 21, count 0 2006.211.07:23:15.42#ibcon#read 3, iclass 21, count 0 2006.211.07:23:15.42#ibcon#about to read 4, iclass 21, count 0 2006.211.07:23:15.42#ibcon#read 4, iclass 21, count 0 2006.211.07:23:15.42#ibcon#about to read 5, iclass 21, count 0 2006.211.07:23:15.42#ibcon#read 5, iclass 21, count 0 2006.211.07:23:15.42#ibcon#about to read 6, iclass 21, count 0 2006.211.07:23:15.42#ibcon#read 6, iclass 21, count 0 2006.211.07:23:15.42#ibcon#end of sib2, iclass 21, count 0 2006.211.07:23:15.42#ibcon#*mode == 0, iclass 21, count 0 2006.211.07:23:15.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.07:23:15.42#ibcon#[27=USB\r\n] 2006.211.07:23:15.42#ibcon#*before write, iclass 21, count 0 2006.211.07:23:15.42#ibcon#enter sib2, iclass 21, count 0 2006.211.07:23:15.42#ibcon#flushed, iclass 21, count 0 2006.211.07:23:15.42#ibcon#about to write, iclass 21, count 0 2006.211.07:23:15.42#ibcon#wrote, iclass 21, count 0 2006.211.07:23:15.42#ibcon#about to read 3, iclass 21, count 0 2006.211.07:23:15.45#ibcon#read 3, iclass 21, count 0 2006.211.07:23:15.45#ibcon#about to read 4, iclass 21, count 0 2006.211.07:23:15.45#ibcon#read 4, iclass 21, count 0 2006.211.07:23:15.45#ibcon#about to read 5, iclass 21, count 0 2006.211.07:23:15.45#ibcon#read 5, iclass 21, count 0 2006.211.07:23:15.45#ibcon#about to read 6, iclass 21, count 0 2006.211.07:23:15.45#ibcon#read 6, iclass 21, count 0 2006.211.07:23:15.45#ibcon#end of sib2, iclass 21, count 0 2006.211.07:23:15.45#ibcon#*after write, iclass 21, count 0 2006.211.07:23:15.45#ibcon#*before return 0, iclass 21, count 0 2006.211.07:23:15.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:23:15.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.07:23:15.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.07:23:15.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.07:23:15.45$vc4f8/vblo=6,752.99 2006.211.07:23:15.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.07:23:15.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.07:23:15.45#ibcon#ireg 17 cls_cnt 0 2006.211.07:23:15.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:23:15.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:23:15.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:23:15.45#ibcon#enter wrdev, iclass 23, count 0 2006.211.07:23:15.45#ibcon#first serial, iclass 23, count 0 2006.211.07:23:15.45#ibcon#enter sib2, iclass 23, count 0 2006.211.07:23:15.45#ibcon#flushed, iclass 23, count 0 2006.211.07:23:15.45#ibcon#about to write, iclass 23, count 0 2006.211.07:23:15.45#ibcon#wrote, iclass 23, count 0 2006.211.07:23:15.45#ibcon#about to read 3, iclass 23, count 0 2006.211.07:23:15.47#ibcon#read 3, iclass 23, count 0 2006.211.07:23:15.47#ibcon#about to read 4, iclass 23, count 0 2006.211.07:23:15.47#ibcon#read 4, iclass 23, count 0 2006.211.07:23:15.47#ibcon#about to read 5, iclass 23, count 0 2006.211.07:23:15.47#ibcon#read 5, iclass 23, count 0 2006.211.07:23:15.47#ibcon#about to read 6, iclass 23, count 0 2006.211.07:23:15.47#ibcon#read 6, iclass 23, count 0 2006.211.07:23:15.47#ibcon#end of sib2, iclass 23, count 0 2006.211.07:23:15.47#ibcon#*mode == 0, iclass 23, count 0 2006.211.07:23:15.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.07:23:15.47#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.07:23:15.47#ibcon#*before write, iclass 23, count 0 2006.211.07:23:15.47#ibcon#enter sib2, iclass 23, count 0 2006.211.07:23:15.47#ibcon#flushed, iclass 23, count 0 2006.211.07:23:15.47#ibcon#about to write, iclass 23, count 0 2006.211.07:23:15.47#ibcon#wrote, iclass 23, count 0 2006.211.07:23:15.47#ibcon#about to read 3, iclass 23, count 0 2006.211.07:23:15.51#ibcon#read 3, iclass 23, count 0 2006.211.07:23:15.51#ibcon#about to read 4, iclass 23, count 0 2006.211.07:23:15.51#ibcon#read 4, iclass 23, count 0 2006.211.07:23:15.51#ibcon#about to read 5, iclass 23, count 0 2006.211.07:23:15.51#ibcon#read 5, iclass 23, count 0 2006.211.07:23:15.51#ibcon#about to read 6, iclass 23, count 0 2006.211.07:23:15.51#ibcon#read 6, iclass 23, count 0 2006.211.07:23:15.51#ibcon#end of sib2, iclass 23, count 0 2006.211.07:23:15.51#ibcon#*after write, iclass 23, count 0 2006.211.07:23:15.51#ibcon#*before return 0, iclass 23, count 0 2006.211.07:23:15.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:23:15.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.07:23:15.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.07:23:15.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.07:23:15.51$vc4f8/vb=6,3 2006.211.07:23:15.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.07:23:15.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.07:23:15.51#ibcon#ireg 11 cls_cnt 2 2006.211.07:23:15.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:23:15.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:23:15.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:23:15.57#ibcon#enter wrdev, iclass 25, count 2 2006.211.07:23:15.57#ibcon#first serial, iclass 25, count 2 2006.211.07:23:15.57#ibcon#enter sib2, iclass 25, count 2 2006.211.07:23:15.57#ibcon#flushed, iclass 25, count 2 2006.211.07:23:15.57#ibcon#about to write, iclass 25, count 2 2006.211.07:23:15.57#ibcon#wrote, iclass 25, count 2 2006.211.07:23:15.57#ibcon#about to read 3, iclass 25, count 2 2006.211.07:23:15.59#ibcon#read 3, iclass 25, count 2 2006.211.07:23:15.59#ibcon#about to read 4, iclass 25, count 2 2006.211.07:23:15.59#ibcon#read 4, iclass 25, count 2 2006.211.07:23:15.59#ibcon#about to read 5, iclass 25, count 2 2006.211.07:23:15.59#ibcon#read 5, iclass 25, count 2 2006.211.07:23:15.59#ibcon#about to read 6, iclass 25, count 2 2006.211.07:23:15.59#ibcon#read 6, iclass 25, count 2 2006.211.07:23:15.59#ibcon#end of sib2, iclass 25, count 2 2006.211.07:23:15.59#ibcon#*mode == 0, iclass 25, count 2 2006.211.07:23:15.59#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.07:23:15.59#ibcon#[27=AT06-03\r\n] 2006.211.07:23:15.59#ibcon#*before write, iclass 25, count 2 2006.211.07:23:15.59#ibcon#enter sib2, iclass 25, count 2 2006.211.07:23:15.59#ibcon#flushed, iclass 25, count 2 2006.211.07:23:15.59#ibcon#about to write, iclass 25, count 2 2006.211.07:23:15.59#ibcon#wrote, iclass 25, count 2 2006.211.07:23:15.59#ibcon#about to read 3, iclass 25, count 2 2006.211.07:23:15.62#ibcon#read 3, iclass 25, count 2 2006.211.07:23:15.62#ibcon#about to read 4, iclass 25, count 2 2006.211.07:23:15.62#ibcon#read 4, iclass 25, count 2 2006.211.07:23:15.62#ibcon#about to read 5, iclass 25, count 2 2006.211.07:23:15.62#ibcon#read 5, iclass 25, count 2 2006.211.07:23:15.62#ibcon#about to read 6, iclass 25, count 2 2006.211.07:23:15.62#ibcon#read 6, iclass 25, count 2 2006.211.07:23:15.62#ibcon#end of sib2, iclass 25, count 2 2006.211.07:23:15.62#ibcon#*after write, iclass 25, count 2 2006.211.07:23:15.62#ibcon#*before return 0, iclass 25, count 2 2006.211.07:23:15.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:23:15.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.07:23:15.62#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.07:23:15.62#ibcon#ireg 7 cls_cnt 0 2006.211.07:23:15.62#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:23:15.74#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:23:15.74#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:23:15.74#ibcon#enter wrdev, iclass 25, count 0 2006.211.07:23:15.74#ibcon#first serial, iclass 25, count 0 2006.211.07:23:15.74#ibcon#enter sib2, iclass 25, count 0 2006.211.07:23:15.74#ibcon#flushed, iclass 25, count 0 2006.211.07:23:15.74#ibcon#about to write, iclass 25, count 0 2006.211.07:23:15.74#ibcon#wrote, iclass 25, count 0 2006.211.07:23:15.74#ibcon#about to read 3, iclass 25, count 0 2006.211.07:23:15.76#ibcon#read 3, iclass 25, count 0 2006.211.07:23:15.76#ibcon#about to read 4, iclass 25, count 0 2006.211.07:23:15.76#ibcon#read 4, iclass 25, count 0 2006.211.07:23:15.76#ibcon#about to read 5, iclass 25, count 0 2006.211.07:23:15.76#ibcon#read 5, iclass 25, count 0 2006.211.07:23:15.76#ibcon#about to read 6, iclass 25, count 0 2006.211.07:23:15.76#ibcon#read 6, iclass 25, count 0 2006.211.07:23:15.76#ibcon#end of sib2, iclass 25, count 0 2006.211.07:23:15.76#ibcon#*mode == 0, iclass 25, count 0 2006.211.07:23:15.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.07:23:15.76#ibcon#[27=USB\r\n] 2006.211.07:23:15.76#ibcon#*before write, iclass 25, count 0 2006.211.07:23:15.76#ibcon#enter sib2, iclass 25, count 0 2006.211.07:23:15.76#ibcon#flushed, iclass 25, count 0 2006.211.07:23:15.76#ibcon#about to write, iclass 25, count 0 2006.211.07:23:15.76#ibcon#wrote, iclass 25, count 0 2006.211.07:23:15.76#ibcon#about to read 3, iclass 25, count 0 2006.211.07:23:15.79#ibcon#read 3, iclass 25, count 0 2006.211.07:23:15.79#ibcon#about to read 4, iclass 25, count 0 2006.211.07:23:15.79#ibcon#read 4, iclass 25, count 0 2006.211.07:23:15.79#ibcon#about to read 5, iclass 25, count 0 2006.211.07:23:15.79#ibcon#read 5, iclass 25, count 0 2006.211.07:23:15.79#ibcon#about to read 6, iclass 25, count 0 2006.211.07:23:15.79#ibcon#read 6, iclass 25, count 0 2006.211.07:23:15.79#ibcon#end of sib2, iclass 25, count 0 2006.211.07:23:15.79#ibcon#*after write, iclass 25, count 0 2006.211.07:23:15.79#ibcon#*before return 0, iclass 25, count 0 2006.211.07:23:15.79#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:23:15.79#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.07:23:15.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.07:23:15.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.07:23:15.79$vc4f8/vabw=wide 2006.211.07:23:15.79#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.07:23:15.79#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.07:23:15.79#ibcon#ireg 8 cls_cnt 0 2006.211.07:23:15.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:23:15.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:23:15.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:23:15.79#ibcon#enter wrdev, iclass 27, count 0 2006.211.07:23:15.79#ibcon#first serial, iclass 27, count 0 2006.211.07:23:15.79#ibcon#enter sib2, iclass 27, count 0 2006.211.07:23:15.79#ibcon#flushed, iclass 27, count 0 2006.211.07:23:15.79#ibcon#about to write, iclass 27, count 0 2006.211.07:23:15.79#ibcon#wrote, iclass 27, count 0 2006.211.07:23:15.79#ibcon#about to read 3, iclass 27, count 0 2006.211.07:23:15.81#ibcon#read 3, iclass 27, count 0 2006.211.07:23:15.81#ibcon#about to read 4, iclass 27, count 0 2006.211.07:23:15.81#ibcon#read 4, iclass 27, count 0 2006.211.07:23:15.81#ibcon#about to read 5, iclass 27, count 0 2006.211.07:23:15.81#ibcon#read 5, iclass 27, count 0 2006.211.07:23:15.81#ibcon#about to read 6, iclass 27, count 0 2006.211.07:23:15.81#ibcon#read 6, iclass 27, count 0 2006.211.07:23:15.81#ibcon#end of sib2, iclass 27, count 0 2006.211.07:23:15.81#ibcon#*mode == 0, iclass 27, count 0 2006.211.07:23:15.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.07:23:15.81#ibcon#[25=BW32\r\n] 2006.211.07:23:15.81#ibcon#*before write, iclass 27, count 0 2006.211.07:23:15.81#ibcon#enter sib2, iclass 27, count 0 2006.211.07:23:15.81#ibcon#flushed, iclass 27, count 0 2006.211.07:23:15.81#ibcon#about to write, iclass 27, count 0 2006.211.07:23:15.81#ibcon#wrote, iclass 27, count 0 2006.211.07:23:15.81#ibcon#about to read 3, iclass 27, count 0 2006.211.07:23:15.84#ibcon#read 3, iclass 27, count 0 2006.211.07:23:15.84#ibcon#about to read 4, iclass 27, count 0 2006.211.07:23:15.84#ibcon#read 4, iclass 27, count 0 2006.211.07:23:15.84#ibcon#about to read 5, iclass 27, count 0 2006.211.07:23:15.84#ibcon#read 5, iclass 27, count 0 2006.211.07:23:15.84#ibcon#about to read 6, iclass 27, count 0 2006.211.07:23:15.84#ibcon#read 6, iclass 27, count 0 2006.211.07:23:15.84#ibcon#end of sib2, iclass 27, count 0 2006.211.07:23:15.84#ibcon#*after write, iclass 27, count 0 2006.211.07:23:15.84#ibcon#*before return 0, iclass 27, count 0 2006.211.07:23:15.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:23:15.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.07:23:15.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.07:23:15.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.07:23:15.84$vc4f8/vbbw=wide 2006.211.07:23:15.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.07:23:15.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.07:23:15.84#ibcon#ireg 8 cls_cnt 0 2006.211.07:23:15.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:23:15.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:23:15.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:23:15.91#ibcon#enter wrdev, iclass 29, count 0 2006.211.07:23:15.91#ibcon#first serial, iclass 29, count 0 2006.211.07:23:15.91#ibcon#enter sib2, iclass 29, count 0 2006.211.07:23:15.91#ibcon#flushed, iclass 29, count 0 2006.211.07:23:15.91#ibcon#about to write, iclass 29, count 0 2006.211.07:23:15.91#ibcon#wrote, iclass 29, count 0 2006.211.07:23:15.91#ibcon#about to read 3, iclass 29, count 0 2006.211.07:23:15.93#ibcon#read 3, iclass 29, count 0 2006.211.07:23:15.93#ibcon#about to read 4, iclass 29, count 0 2006.211.07:23:15.93#ibcon#read 4, iclass 29, count 0 2006.211.07:23:15.93#ibcon#about to read 5, iclass 29, count 0 2006.211.07:23:15.93#ibcon#read 5, iclass 29, count 0 2006.211.07:23:15.93#ibcon#about to read 6, iclass 29, count 0 2006.211.07:23:15.93#ibcon#read 6, iclass 29, count 0 2006.211.07:23:15.93#ibcon#end of sib2, iclass 29, count 0 2006.211.07:23:15.93#ibcon#*mode == 0, iclass 29, count 0 2006.211.07:23:15.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.07:23:15.93#ibcon#[27=BW32\r\n] 2006.211.07:23:15.93#ibcon#*before write, iclass 29, count 0 2006.211.07:23:15.93#ibcon#enter sib2, iclass 29, count 0 2006.211.07:23:15.93#ibcon#flushed, iclass 29, count 0 2006.211.07:23:15.93#ibcon#about to write, iclass 29, count 0 2006.211.07:23:15.93#ibcon#wrote, iclass 29, count 0 2006.211.07:23:15.93#ibcon#about to read 3, iclass 29, count 0 2006.211.07:23:15.96#ibcon#read 3, iclass 29, count 0 2006.211.07:23:15.96#ibcon#about to read 4, iclass 29, count 0 2006.211.07:23:15.96#ibcon#read 4, iclass 29, count 0 2006.211.07:23:15.96#ibcon#about to read 5, iclass 29, count 0 2006.211.07:23:15.96#ibcon#read 5, iclass 29, count 0 2006.211.07:23:15.96#ibcon#about to read 6, iclass 29, count 0 2006.211.07:23:15.96#ibcon#read 6, iclass 29, count 0 2006.211.07:23:15.96#ibcon#end of sib2, iclass 29, count 0 2006.211.07:23:15.96#ibcon#*after write, iclass 29, count 0 2006.211.07:23:15.96#ibcon#*before return 0, iclass 29, count 0 2006.211.07:23:15.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:23:15.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.07:23:15.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.07:23:15.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.07:23:15.96$4f8m12a/ifd4f 2006.211.07:23:15.96&ifd4f/lo= 2006.211.07:23:15.96&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:23:15.96&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:23:15.96&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:23:15.96&ifd4f/patch= 2006.211.07:23:15.96&ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:23:15.96&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:23:15.96&ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:23:15.96$ifd4f/lo= 2006.211.07:23:15.96$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.07:23:15.96$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.07:23:15.96$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.07:23:15.96$ifd4f/patch= 2006.211.07:23:15.96$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.07:23:15.96$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.07:23:15.96$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.07:23:15.96$4f8m12a/"form=m,16.000,1:2 2006.211.07:23:15.96$4f8m12a/"tpicd 2006.211.07:23:15.96$4f8m12a/echo=off 2006.211.07:23:15.96$4f8m12a/xlog=off 2006.211.07:23:15.96:!2006.211.06:59:50 2006.211.07:23:15.96:preob 2006.211.07:23:15.96&preob/onsource 2006.211.07:23:16.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.211.07:23:16.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.211.07:23:16.14/onsource/SLEWING 2006.211.07:23:16.14:!2006.211.07:00:00 2006.211.07:23:16.14:data_valid=on 2006.211.07:23:16.14:midob 2006.211.07:23:16.14&midob/onsource 2006.211.07:23:16.14&midob/wx 2006.211.07:23:16.14&midob/cable 2006.211.07:23:16.14&midob/va 2006.211.07:23:16.14&midob/valo 2006.211.07:23:16.14&midob/vb 2006.211.07:23:16.14&midob/vblo 2006.211.07:23:16.14&midob/vabw 2006.211.07:23:16.14&midob/vbbw 2006.211.07:23:16.14&midob/"form 2006.211.07:23:16.14&midob/xfe 2006.211.07:23:16.14&midob/ifatt 2006.211.07:23:16.14&midob/clockoff 2006.211.07:23:16.14&midob/sy=logmail 2006.211.07:23:16.14&midob/"sy=run setcl adapt & 2006.211.07:23:18.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.211.07:23:18.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.211.07:23:18.14/onsource/SLEWING 2006.211.07:23:18.14/wx/27.54,1006.2,89 2006.211.07:23:18.34/cable/+6.4251E-03 2006.211.07:23:19.43/va/01,08,usb,yes,28,30 2006.211.07:23:19.43/va/02,07,usb,yes,28,30 2006.211.07:23:19.43/va/03,06,usb,yes,30,30 2006.211.07:23:19.43/va/04,07,usb,yes,29,31 2006.211.07:23:19.43/va/05,07,usb,yes,32,34 2006.211.07:23:19.43/va/06,06,usb,yes,31,31 2006.211.07:23:19.43/va/07,06,usb,yes,31,31 2006.211.07:23:19.43/va/08,07,usb,yes,30,29 2006.211.07:23:19.66/valo/01,532.99,yes,locked 2006.211.07:23:19.66/valo/02,572.99,yes,locked 2006.211.07:23:19.66/valo/03,672.99,yes,locked 2006.211.07:23:19.66/valo/04,832.99,yes,locked 2006.211.07:23:19.66/valo/05,652.99,yes,locked 2006.211.07:23:19.66/valo/06,772.99,yes,locked 2006.211.07:23:19.66/valo/07,832.99,yes,locked 2006.211.07:23:19.66/valo/08,852.99,yes,locked 2006.211.07:23:20.75/vb/01,04,usb,yes,28,27 2006.211.07:23:20.75/vb/02,04,usb,yes,30,31 2006.211.07:23:20.75/vb/03,03,usb,yes,33,37 2006.211.07:23:20.75/vb/04,03,usb,yes,34,34 2006.211.07:23:20.75/vb/05,03,usb,yes,32,36 2006.211.07:23:20.75/vb/06,03,usb,yes,33,36 2006.211.07:23:20.75/vb/07,04,usb,yes,28,28 2006.211.07:23:20.75/vb/08,03,usb,yes,33,36 2006.211.07:23:20.98/vblo/01,632.99,yes,locked 2006.211.07:23:20.98/vblo/02,640.99,yes,locked 2006.211.07:23:20.98/vblo/03,656.99,yes,locked 2006.211.07:23:20.98/vblo/04,712.99,yes,locked 2006.211.07:23:20.98/vblo/05,744.99,yes,locked 2006.211.07:23:20.98/vblo/06,752.99,yes,locked 2006.211.07:23:20.98/vblo/07,734.99,yes,locked 2006.211.07:23:20.98/vblo/08,744.99,yes,locked 2006.211.07:23:21.13/vabw/8 2006.211.07:23:21.28/vbbw/8 2006.211.07:23:21.37/xfe/off,on,13.0 2006.211.07:23:21.75/ifatt/23,28,28,28 2006.211.07:23:22.04/fmout-gps/S +4.58E-07 2006.211.07:23:22.12:!2006.211.07:24:50 2006.211.07:23:22.12;wx 2006.211.07:23:22.12/wx/27.54,1006.2,89 2006.211.07:23:49.14#trakl#Source acquired 2006.211.07:23:49.14#flagr#flagr/antenna,acquired 2006.211.07:24:50.00:"checkk5hdd 2006.211.07:24:50.00:sy=cp /usr2/log/u06211ts.log /usr2/log_backup/ 2006.211.07:24:50.08:log=k06211ts 2006.211.07:39:03.21;Log Opened: Mark IV Field System Version 9.7.7 2006.211.07:39:03.21;location,TSUKUB32,-140.09,36.10,61.0 2006.211.07:39:03.21;horizon1,0.,5.,360. 2006.211.07:39:03.21;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.211.07:39:03.21;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.211.07:39:03.21;drivev11,330,270,no 2006.211.07:39:03.21;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.211.07:39:03.21;drivev13,15.000,268,10.000,10.000,10.000 2006.211.07:39:03.21;drivev21,330,270,no 2006.211.07:39:03.21;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.211.07:39:03.21;drivev23,15.000,268,10.000,10.000,10.000 2006.211.07:39:03.21;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.211.07:39:03.21;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.211.07:39:03.21;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.211.07:39:03.21;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.211.07:39:03.21;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.211.07:39:03.21;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.211.07:39:03.21;time,-0.364,101.533,rate 2006.211.07:39:03.21;flagr,200 2006.211.07:39:03.21:" K06210 2006 TSUKUB32 T Ts 2006.211.07:39:03.21:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.211.07:39:03.21:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.211.07:39:03.21:" 108 TSUKUB32 14 17400 2006.211.07:39:03.21:" drudg version 050216 compiled under FS 9.7.07 2006.211.07:39:03.21:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.211.07:39:03.21:exper_initi 2006.211.07:39:03.21&exper_initi/proc_library 2006.211.07:39:03.21&exper_initi/sched_initi 2006.211.07:39:03.21:!2006.211.08:30:10 2006.211.07:39:03.21&proc_library/" k06210 tsukub32 ts 2006.211.07:39:03.21&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.211.07:39:03.21&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.211.07:39:03.21&sched_initi/startcheck 2006.211.07:39:03.21&startcheck/sy=check_fsrun.pl & 2006.211.07:39:03.21&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.211.07:39:33.28;sy=run setcl offset & 2006.211.07:39:33.37#setcl#time/60849320,0,2006,211,08,30,06.30,265887.094,0.274,303299 2006.211.07:39:33.41#setcl#model/old,1153459626,17705411,60750763,-0.364,101.533,rate,0,sync,17705696,18008995 2006.211.08:30:06.42#setcl#model/new,1153459626,18008710,60849320,-0.364,101.533,rate,0 2006.211.08:30:07.53;wx 2006.211.08:30:07.53/wx/27.37,1006.1,92 2006.211.08:30:10.00:data_valid=off 2006.211.08:30:10.00:postob 2006.211.08:30:10.00&postob/cable 2006.211.08:30:10.00&postob/wx 2006.211.08:30:10.00&postob/clockoff 2006.211.08:30:10.10/cable/+6.4252E-03 2006.211.08:30:10.10?ERROR st -94 No new wx data since last report 2006.211.08:30:10.10&clockoff/"gps-fmout=1p 2006.211.08:30:10.10&clockoff/fmout-gps=1p 2006.211.08:30:11.03/fmout-gps/S +4.58E-07 2006.211.08:30:11.03:checkk5last 2006.211.08:30:11.03&checkk5last/chk_obsdata=1 2006.211.08:30:11.03&checkk5last/chk_obsdata=2 2006.211.08:30:11.03&checkk5last/chk_obsdata=3 2006.211.08:30:11.03&checkk5last/chk_obsdata=4 2006.211.08:30:11.03&checkk5last/k5log=1 2006.211.08:30:11.03&checkk5last/k5log=2 2006.211.08:30:11.03&checkk5last/k5log=3 2006.211.08:30:11.03&checkk5last/k5log=4 2006.211.08:30:11.03&checkk5last/obsinfo 2006.211.08:30:11.41/chk_obsdata//k5ts1?ERROR: no T2110739??a.dat file! 2006.211.08:30:11.80/chk_obsdata//k5ts2?ERROR: no T2110739??b.dat file! 2006.211.08:30:12.17/chk_obsdata//k5ts3?ERROR: no T2110739??c.dat file! 2006.211.08:30:12.56/chk_obsdata//k5ts4?ERROR: no T2110739??d.dat file! 2006.211.08:30:13.35/k5log//k5ts1_log_newline 2006.211.08:30:14.21/k5log//k5ts2_log_newline 2006.211.08:30:15.06/k5log//k5ts3_log_newline 2006.211.08:30:15.82/k5log//k5ts4_log_newline 2006.211.08:30:16.05/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.211.08:30:16.05:"sched_end 2006.211.08:30:16.05:checkk5hdd 2006.211.08:30:16.05&checkk5hdd/chk_hdd=1 2006.211.08:30:16.05&checkk5hdd/chk_hdd=2 2006.211.08:30:16.05&checkk5hdd/chk_hdd=3 2006.211.08:30:16.05&checkk5hdd/chk_hdd=4 2006.211.08:30:19.20/chk_hdd//k5ts1/GSI00275:T211073000a.dat~T211073710a.dat[1888223232Byte] 2006.211.08:30:22.59/chk_hdd//k5ts2/GSI00163:T211073000b.dat~T211073710b.dat[1888223232Byte] 2006.211.08:30:25.85/chk_hdd//k5ts3/GSI00278:T211073000c.dat~T211073710c.dat[1888223232Byte] 2006.211.08:30:29.19/chk_hdd//k5ts4/GSI00220:T211073000d.dat~T211073710d.dat[1864171520Byte] 2006.211.08:30:29.19:sy=cp /usr2/log/k06211ts.log /usr2/log_backup/ 2006.211.08:30:29.27:log=u06211ts 2006.211.08:45:24.60;Log Opened: Mark IV Field System Version 9.7.7 2006.211.08:45:24.60;location,TSUKUB32,-140.09,36.10,61.0 2006.211.08:45:24.60;horizon1,0.,5.,360. 2006.211.08:45:24.60;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.211.08:45:24.60;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.211.08:45:24.60;drivev11,330,270,no 2006.211.08:45:24.60;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.211.08:45:24.60;drivev13,15.000,268,10.000,10.000,10.000 2006.211.08:45:24.60;drivev21,330,270,no 2006.211.08:45:24.60;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.211.08:45:24.60;drivev23,15.000,268,10.000,10.000,10.000 2006.211.08:45:24.60;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.211.08:45:24.60;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.211.08:45:24.60;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.211.08:45:24.60;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.211.08:45:24.60;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.211.08:45:24.60;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.211.08:45:24.60;time,-0.364,101.533,rate 2006.211.08:45:24.60;flagr,200 2006.211.08:45:24.60:" K06210 2006 TSUKUB32 T Ts 2006.211.08:45:24.60:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.211.08:45:24.60:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.211.08:45:24.60:" 108 TSUKUB32 14 17400 2006.211.08:45:24.60:" drudg version 050216 compiled under FS 9.7.07 2006.211.08:45:24.60:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.211.08:45:24.60:exper_initi 2006.211.08:45:24.60&exper_initi/proc_library 2006.211.08:45:24.60&exper_initi/sched_initi 2006.211.08:45:24.60:scan_name=211-2027,u06211,1800 2006.211.08:45:24.60:source=2201+044,220417.63,044002.0,2000.0,neutral 2006.211.08:45:24.60#antcn#PM 1 00019 2005 228 00 22 31 00 2006.211.08:45:24.60#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.211.08:45:24.60#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.211.08:45:24.60#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.211.08:45:24.60#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.211.08:45:24.60#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.211.08:45:25.14:4f8m12a=1 2006.211.08:45:25.14&4f8m12a/xlog=on 2006.211.08:45:25.14&4f8m12a/echo=on 2006.211.08:45:25.14&4f8m12a/pcalon 2006.211.08:45:25.14&4f8m12a/"tpicd=stop 2006.211.08:45:25.14&4f8m12a/vc4f8 2006.211.08:45:25.14&4f8m12a/ifd4f 2006.211.08:45:25.14&4f8m12a/"form=m,16.000,1:2 2006.211.08:45:25.14&4f8m12a/"tpicd 2006.211.08:45:25.14&4f8m12a/echo=off 2006.211.08:45:25.14&4f8m12a/xlog=off 2006.211.08:45:25.14$4f8m12a/echo=on 2006.211.08:45:25.14$4f8m12a/pcalon 2006.211.08:45:25.14&pcalon/"no phase cal control is implemented here 2006.211.08:45:25.14$pcalon/"no phase cal control is implemented here 2006.211.08:45:25.14$4f8m12a/"tpicd=stop 2006.211.08:45:25.14$4f8m12a/vc4f8 2006.211.08:45:25.14&vc4f8/valo=1,532.99 2006.211.08:45:25.14&vc4f8/va=1,8 2006.211.08:45:25.14&vc4f8/valo=2,572.99 2006.211.08:45:25.14&vc4f8/va=2,7 2006.211.08:45:25.14&vc4f8/valo=3,672.99 2006.211.08:45:25.14&vc4f8/va=3,6 2006.211.08:45:25.14&vc4f8/valo=4,832.99 2006.211.08:45:25.14&vc4f8/va=4,7 2006.211.08:45:25.14&vc4f8/valo=5,652.99 2006.211.08:45:25.14&vc4f8/va=5,7 2006.211.08:45:25.14&vc4f8/valo=6,772.99 2006.211.08:45:25.14&vc4f8/va=6,6 2006.211.08:45:25.14&vc4f8/valo=7,832.99 2006.211.08:45:25.14&vc4f8/va=7,6 2006.211.08:45:25.14&vc4f8/valo=8,852.99 2006.211.08:45:25.14&vc4f8/va=8,7 2006.211.08:45:25.14&vc4f8/vblo=1,632.99 2006.211.08:45:25.14&vc4f8/vb=1,4 2006.211.08:45:25.14&vc4f8/vblo=2,640.99 2006.211.08:45:25.14&vc4f8/vb=2,4 2006.211.08:45:25.14&vc4f8/vblo=3,656.99 2006.211.08:45:25.14&vc4f8/vb=3,3 2006.211.08:45:25.14&vc4f8/vblo=4,712.99 2006.211.08:45:25.14&vc4f8/vb=4,3 2006.211.08:45:25.14&vc4f8/vblo=5,744.99 2006.211.08:45:25.14&vc4f8/vb=5,3 2006.211.08:45:25.14&vc4f8/vblo=6,752.99 2006.211.08:45:25.14&vc4f8/vb=6,3 2006.211.08:45:25.14&vc4f8/vabw=wide 2006.211.08:45:25.14&vc4f8/vbbw=wide 2006.211.08:45:25.14$vc4f8/valo=1,532.99 2006.211.08:45:25.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.211.08:45:25.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.211.08:45:25.14#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:25.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:45:25.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:45:25.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:45:25.14#ibcon#enter wrdev, iclass 38, count 0 2006.211.08:45:25.14#ibcon#first serial, iclass 38, count 0 2006.211.08:45:25.14#ibcon#enter sib2, iclass 38, count 0 2006.211.08:45:25.14#ibcon#flushed, iclass 38, count 0 2006.211.08:45:25.14#ibcon#about to write, iclass 38, count 0 2006.211.08:45:25.14#ibcon#wrote, iclass 38, count 0 2006.211.08:45:25.14#ibcon#about to read 3, iclass 38, count 0 2006.211.08:45:25.14#flagr#flagr/antenna,new-source 2006.211.08:45:25.16#ibcon#read 3, iclass 38, count 0 2006.211.08:45:25.16#ibcon#about to read 4, iclass 38, count 0 2006.211.08:45:25.16#ibcon#read 4, iclass 38, count 0 2006.211.08:45:25.16#ibcon#about to read 5, iclass 38, count 0 2006.211.08:45:25.16#ibcon#read 5, iclass 38, count 0 2006.211.08:45:25.16#ibcon#about to read 6, iclass 38, count 0 2006.211.08:45:25.16#ibcon#read 6, iclass 38, count 0 2006.211.08:45:25.16#ibcon#end of sib2, iclass 38, count 0 2006.211.08:45:25.16#ibcon#*mode == 0, iclass 38, count 0 2006.211.08:45:25.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.211.08:45:25.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.211.08:45:25.16#ibcon#*before write, iclass 38, count 0 2006.211.08:45:25.16#ibcon#enter sib2, iclass 38, count 0 2006.211.08:45:25.16#ibcon#flushed, iclass 38, count 0 2006.211.08:45:25.16#ibcon#about to write, iclass 38, count 0 2006.211.08:45:25.16#ibcon#wrote, iclass 38, count 0 2006.211.08:45:25.16#ibcon#about to read 3, iclass 38, count 0 2006.211.08:45:25.21#ibcon#read 3, iclass 38, count 0 2006.211.08:45:25.21#ibcon#about to read 4, iclass 38, count 0 2006.211.08:45:25.21#ibcon#read 4, iclass 38, count 0 2006.211.08:45:25.21#ibcon#about to read 5, iclass 38, count 0 2006.211.08:45:25.21#ibcon#read 5, iclass 38, count 0 2006.211.08:45:25.21#ibcon#about to read 6, iclass 38, count 0 2006.211.08:45:25.21#ibcon#read 6, iclass 38, count 0 2006.211.08:45:25.21#ibcon#end of sib2, iclass 38, count 0 2006.211.08:45:25.21#ibcon#*after write, iclass 38, count 0 2006.211.08:45:25.21#ibcon#*before return 0, iclass 38, count 0 2006.211.08:45:25.21#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:45:25.21#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.211.08:45:25.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.211.08:45:25.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.211.08:45:25.21$vc4f8/va=1,8 2006.211.08:45:25.21#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.211.08:45:25.21#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.211.08:45:25.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:25.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:45:25.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:45:25.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:45:25.21#ibcon#enter wrdev, iclass 40, count 2 2006.211.08:45:25.21#ibcon#first serial, iclass 40, count 2 2006.211.08:45:25.21#ibcon#enter sib2, iclass 40, count 2 2006.211.08:45:25.21#ibcon#flushed, iclass 40, count 2 2006.211.08:45:25.21#ibcon#about to write, iclass 40, count 2 2006.211.08:45:25.21#ibcon#wrote, iclass 40, count 2 2006.211.08:45:25.21#ibcon#about to read 3, iclass 40, count 2 2006.211.08:45:25.23#ibcon#read 3, iclass 40, count 2 2006.211.08:45:25.23#ibcon#about to read 4, iclass 40, count 2 2006.211.08:45:25.23#ibcon#read 4, iclass 40, count 2 2006.211.08:45:25.23#ibcon#about to read 5, iclass 40, count 2 2006.211.08:45:25.23#ibcon#read 5, iclass 40, count 2 2006.211.08:45:25.23#ibcon#about to read 6, iclass 40, count 2 2006.211.08:45:25.23#ibcon#read 6, iclass 40, count 2 2006.211.08:45:25.23#ibcon#end of sib2, iclass 40, count 2 2006.211.08:45:25.23#ibcon#*mode == 0, iclass 40, count 2 2006.211.08:45:25.23#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.211.08:45:25.23#ibcon#[25=AT01-08\r\n] 2006.211.08:45:25.23#ibcon#*before write, iclass 40, count 2 2006.211.08:45:25.23#ibcon#enter sib2, iclass 40, count 2 2006.211.08:45:25.23#ibcon#flushed, iclass 40, count 2 2006.211.08:45:25.23#ibcon#about to write, iclass 40, count 2 2006.211.08:45:25.23#ibcon#wrote, iclass 40, count 2 2006.211.08:45:25.23#ibcon#about to read 3, iclass 40, count 2 2006.211.08:45:25.26#ibcon#read 3, iclass 40, count 2 2006.211.08:45:25.26#ibcon#about to read 4, iclass 40, count 2 2006.211.08:45:25.26#ibcon#read 4, iclass 40, count 2 2006.211.08:45:25.26#ibcon#about to read 5, iclass 40, count 2 2006.211.08:45:25.26#ibcon#read 5, iclass 40, count 2 2006.211.08:45:25.26#ibcon#about to read 6, iclass 40, count 2 2006.211.08:45:25.26#ibcon#read 6, iclass 40, count 2 2006.211.08:45:25.26#ibcon#end of sib2, iclass 40, count 2 2006.211.08:45:25.26#ibcon#*after write, iclass 40, count 2 2006.211.08:45:25.26#ibcon#*before return 0, iclass 40, count 2 2006.211.08:45:25.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:45:25.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.211.08:45:25.26#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.211.08:45:25.26#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:25.26#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:45:25.38#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:45:25.38#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:45:25.38#ibcon#enter wrdev, iclass 40, count 0 2006.211.08:45:25.38#ibcon#first serial, iclass 40, count 0 2006.211.08:45:25.38#ibcon#enter sib2, iclass 40, count 0 2006.211.08:45:25.38#ibcon#flushed, iclass 40, count 0 2006.211.08:45:25.38#ibcon#about to write, iclass 40, count 0 2006.211.08:45:25.38#ibcon#wrote, iclass 40, count 0 2006.211.08:45:25.38#ibcon#about to read 3, iclass 40, count 0 2006.211.08:45:25.40#ibcon#read 3, iclass 40, count 0 2006.211.08:45:25.40#ibcon#about to read 4, iclass 40, count 0 2006.211.08:45:25.40#ibcon#read 4, iclass 40, count 0 2006.211.08:45:25.40#ibcon#about to read 5, iclass 40, count 0 2006.211.08:45:25.40#ibcon#read 5, iclass 40, count 0 2006.211.08:45:25.40#ibcon#about to read 6, iclass 40, count 0 2006.211.08:45:25.40#ibcon#read 6, iclass 40, count 0 2006.211.08:45:25.40#ibcon#end of sib2, iclass 40, count 0 2006.211.08:45:25.40#ibcon#*mode == 0, iclass 40, count 0 2006.211.08:45:25.40#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.211.08:45:25.40#ibcon#[25=USB\r\n] 2006.211.08:45:25.40#ibcon#*before write, iclass 40, count 0 2006.211.08:45:25.40#ibcon#enter sib2, iclass 40, count 0 2006.211.08:45:25.40#ibcon#flushed, iclass 40, count 0 2006.211.08:45:25.40#ibcon#about to write, iclass 40, count 0 2006.211.08:45:25.40#ibcon#wrote, iclass 40, count 0 2006.211.08:45:25.40#ibcon#about to read 3, iclass 40, count 0 2006.211.08:45:25.43#ibcon#read 3, iclass 40, count 0 2006.211.08:45:25.43#ibcon#about to read 4, iclass 40, count 0 2006.211.08:45:25.43#ibcon#read 4, iclass 40, count 0 2006.211.08:45:25.43#ibcon#about to read 5, iclass 40, count 0 2006.211.08:45:25.43#ibcon#read 5, iclass 40, count 0 2006.211.08:45:25.43#ibcon#about to read 6, iclass 40, count 0 2006.211.08:45:25.43#ibcon#read 6, iclass 40, count 0 2006.211.08:45:25.43#ibcon#end of sib2, iclass 40, count 0 2006.211.08:45:25.43#ibcon#*after write, iclass 40, count 0 2006.211.08:45:25.43#ibcon#*before return 0, iclass 40, count 0 2006.211.08:45:25.43#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:45:25.43#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.211.08:45:25.43#ibcon#about to clear, iclass 40 cls_cnt 0 2006.211.08:45:25.43#ibcon#cleared, iclass 40 cls_cnt 0 2006.211.08:45:25.43$vc4f8/valo=2,572.99 2006.211.08:45:25.43#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.211.08:45:25.43#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.211.08:45:25.43#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:25.43#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:45:25.43#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:45:25.43#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:45:25.43#ibcon#enter wrdev, iclass 4, count 0 2006.211.08:45:25.43#ibcon#first serial, iclass 4, count 0 2006.211.08:45:25.43#ibcon#enter sib2, iclass 4, count 0 2006.211.08:45:25.43#ibcon#flushed, iclass 4, count 0 2006.211.08:45:25.43#ibcon#about to write, iclass 4, count 0 2006.211.08:45:25.43#ibcon#wrote, iclass 4, count 0 2006.211.08:45:25.43#ibcon#about to read 3, iclass 4, count 0 2006.211.08:45:25.45#ibcon#read 3, iclass 4, count 0 2006.211.08:45:25.45#ibcon#about to read 4, iclass 4, count 0 2006.211.08:45:25.45#ibcon#read 4, iclass 4, count 0 2006.211.08:45:25.45#ibcon#about to read 5, iclass 4, count 0 2006.211.08:45:25.45#ibcon#read 5, iclass 4, count 0 2006.211.08:45:25.45#ibcon#about to read 6, iclass 4, count 0 2006.211.08:45:25.45#ibcon#read 6, iclass 4, count 0 2006.211.08:45:25.45#ibcon#end of sib2, iclass 4, count 0 2006.211.08:45:25.45#ibcon#*mode == 0, iclass 4, count 0 2006.211.08:45:25.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.211.08:45:25.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.211.08:45:25.45#ibcon#*before write, iclass 4, count 0 2006.211.08:45:25.45#ibcon#enter sib2, iclass 4, count 0 2006.211.08:45:25.45#ibcon#flushed, iclass 4, count 0 2006.211.08:45:25.45#ibcon#about to write, iclass 4, count 0 2006.211.08:45:25.45#ibcon#wrote, iclass 4, count 0 2006.211.08:45:25.45#ibcon#about to read 3, iclass 4, count 0 2006.211.08:45:25.49#ibcon#read 3, iclass 4, count 0 2006.211.08:45:25.49#ibcon#about to read 4, iclass 4, count 0 2006.211.08:45:25.49#ibcon#read 4, iclass 4, count 0 2006.211.08:45:25.49#ibcon#about to read 5, iclass 4, count 0 2006.211.08:45:25.49#ibcon#read 5, iclass 4, count 0 2006.211.08:45:25.49#ibcon#about to read 6, iclass 4, count 0 2006.211.08:45:25.49#ibcon#read 6, iclass 4, count 0 2006.211.08:45:25.49#ibcon#end of sib2, iclass 4, count 0 2006.211.08:45:25.49#ibcon#*after write, iclass 4, count 0 2006.211.08:45:25.49#ibcon#*before return 0, iclass 4, count 0 2006.211.08:45:25.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:45:25.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.211.08:45:25.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.211.08:45:25.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.211.08:45:25.49$vc4f8/va=2,7 2006.211.08:45:25.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.211.08:45:25.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.211.08:45:25.49#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:25.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:45:25.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:45:25.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:45:25.55#ibcon#enter wrdev, iclass 6, count 2 2006.211.08:45:25.55#ibcon#first serial, iclass 6, count 2 2006.211.08:45:25.55#ibcon#enter sib2, iclass 6, count 2 2006.211.08:45:25.55#ibcon#flushed, iclass 6, count 2 2006.211.08:45:25.55#ibcon#about to write, iclass 6, count 2 2006.211.08:45:25.55#ibcon#wrote, iclass 6, count 2 2006.211.08:45:25.55#ibcon#about to read 3, iclass 6, count 2 2006.211.08:45:25.57#ibcon#read 3, iclass 6, count 2 2006.211.08:45:25.57#ibcon#about to read 4, iclass 6, count 2 2006.211.08:45:25.57#ibcon#read 4, iclass 6, count 2 2006.211.08:45:25.57#ibcon#about to read 5, iclass 6, count 2 2006.211.08:45:25.57#ibcon#read 5, iclass 6, count 2 2006.211.08:45:25.57#ibcon#about to read 6, iclass 6, count 2 2006.211.08:45:25.57#ibcon#read 6, iclass 6, count 2 2006.211.08:45:25.57#ibcon#end of sib2, iclass 6, count 2 2006.211.08:45:25.57#ibcon#*mode == 0, iclass 6, count 2 2006.211.08:45:25.57#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.211.08:45:25.57#ibcon#[25=AT02-07\r\n] 2006.211.08:45:25.57#ibcon#*before write, iclass 6, count 2 2006.211.08:45:25.57#ibcon#enter sib2, iclass 6, count 2 2006.211.08:45:25.57#ibcon#flushed, iclass 6, count 2 2006.211.08:45:25.57#ibcon#about to write, iclass 6, count 2 2006.211.08:45:25.57#ibcon#wrote, iclass 6, count 2 2006.211.08:45:25.57#ibcon#about to read 3, iclass 6, count 2 2006.211.08:45:25.61#ibcon#read 3, iclass 6, count 2 2006.211.08:45:25.61#ibcon#about to read 4, iclass 6, count 2 2006.211.08:45:25.61#ibcon#read 4, iclass 6, count 2 2006.211.08:45:25.61#ibcon#about to read 5, iclass 6, count 2 2006.211.08:45:25.61#ibcon#read 5, iclass 6, count 2 2006.211.08:45:25.61#ibcon#about to read 6, iclass 6, count 2 2006.211.08:45:25.61#ibcon#read 6, iclass 6, count 2 2006.211.08:45:25.61#ibcon#end of sib2, iclass 6, count 2 2006.211.08:45:25.61#ibcon#*after write, iclass 6, count 2 2006.211.08:45:25.61#ibcon#*before return 0, iclass 6, count 2 2006.211.08:45:25.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:45:25.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.211.08:45:25.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.211.08:45:25.61#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:25.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:45:25.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:45:25.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:45:25.73#ibcon#enter wrdev, iclass 6, count 0 2006.211.08:45:25.73#ibcon#first serial, iclass 6, count 0 2006.211.08:45:25.73#ibcon#enter sib2, iclass 6, count 0 2006.211.08:45:25.73#ibcon#flushed, iclass 6, count 0 2006.211.08:45:25.73#ibcon#about to write, iclass 6, count 0 2006.211.08:45:25.73#ibcon#wrote, iclass 6, count 0 2006.211.08:45:25.73#ibcon#about to read 3, iclass 6, count 0 2006.211.08:45:25.75#ibcon#read 3, iclass 6, count 0 2006.211.08:45:25.75#ibcon#about to read 4, iclass 6, count 0 2006.211.08:45:25.75#ibcon#read 4, iclass 6, count 0 2006.211.08:45:25.75#ibcon#about to read 5, iclass 6, count 0 2006.211.08:45:25.75#ibcon#read 5, iclass 6, count 0 2006.211.08:45:25.75#ibcon#about to read 6, iclass 6, count 0 2006.211.08:45:25.75#ibcon#read 6, iclass 6, count 0 2006.211.08:45:25.75#ibcon#end of sib2, iclass 6, count 0 2006.211.08:45:25.75#ibcon#*mode == 0, iclass 6, count 0 2006.211.08:45:25.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.211.08:45:25.75#ibcon#[25=USB\r\n] 2006.211.08:45:25.75#ibcon#*before write, iclass 6, count 0 2006.211.08:45:25.75#ibcon#enter sib2, iclass 6, count 0 2006.211.08:45:25.75#ibcon#flushed, iclass 6, count 0 2006.211.08:45:25.75#ibcon#about to write, iclass 6, count 0 2006.211.08:45:25.75#ibcon#wrote, iclass 6, count 0 2006.211.08:45:25.75#ibcon#about to read 3, iclass 6, count 0 2006.211.08:45:25.78#ibcon#read 3, iclass 6, count 0 2006.211.08:45:25.78#ibcon#about to read 4, iclass 6, count 0 2006.211.08:45:25.78#ibcon#read 4, iclass 6, count 0 2006.211.08:45:25.78#ibcon#about to read 5, iclass 6, count 0 2006.211.08:45:25.78#ibcon#read 5, iclass 6, count 0 2006.211.08:45:25.78#ibcon#about to read 6, iclass 6, count 0 2006.211.08:45:25.78#ibcon#read 6, iclass 6, count 0 2006.211.08:45:25.78#ibcon#end of sib2, iclass 6, count 0 2006.211.08:45:25.78#ibcon#*after write, iclass 6, count 0 2006.211.08:45:25.78#ibcon#*before return 0, iclass 6, count 0 2006.211.08:45:25.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:45:25.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.211.08:45:25.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.211.08:45:25.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.211.08:45:25.78$vc4f8/valo=3,672.99 2006.211.08:45:25.78#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.211.08:45:25.78#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.211.08:45:25.78#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:25.78#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:45:25.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:45:25.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:45:25.78#ibcon#enter wrdev, iclass 10, count 0 2006.211.08:45:25.78#ibcon#first serial, iclass 10, count 0 2006.211.08:45:25.78#ibcon#enter sib2, iclass 10, count 0 2006.211.08:45:25.78#ibcon#flushed, iclass 10, count 0 2006.211.08:45:25.78#ibcon#about to write, iclass 10, count 0 2006.211.08:45:25.78#ibcon#wrote, iclass 10, count 0 2006.211.08:45:25.78#ibcon#about to read 3, iclass 10, count 0 2006.211.08:45:25.80#ibcon#read 3, iclass 10, count 0 2006.211.08:45:25.80#ibcon#about to read 4, iclass 10, count 0 2006.211.08:45:25.80#ibcon#read 4, iclass 10, count 0 2006.211.08:45:25.80#ibcon#about to read 5, iclass 10, count 0 2006.211.08:45:25.80#ibcon#read 5, iclass 10, count 0 2006.211.08:45:25.80#ibcon#about to read 6, iclass 10, count 0 2006.211.08:45:25.80#ibcon#read 6, iclass 10, count 0 2006.211.08:45:25.80#ibcon#end of sib2, iclass 10, count 0 2006.211.08:45:25.80#ibcon#*mode == 0, iclass 10, count 0 2006.211.08:45:25.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.211.08:45:25.80#ibcon#[26=FRQ=03,672.99\r\n] 2006.211.08:45:25.80#ibcon#*before write, iclass 10, count 0 2006.211.08:45:25.80#ibcon#enter sib2, iclass 10, count 0 2006.211.08:45:25.80#ibcon#flushed, iclass 10, count 0 2006.211.08:45:25.80#ibcon#about to write, iclass 10, count 0 2006.211.08:45:25.80#ibcon#wrote, iclass 10, count 0 2006.211.08:45:25.80#ibcon#about to read 3, iclass 10, count 0 2006.211.08:45:25.84#ibcon#read 3, iclass 10, count 0 2006.211.08:45:25.84#ibcon#about to read 4, iclass 10, count 0 2006.211.08:45:25.84#ibcon#read 4, iclass 10, count 0 2006.211.08:45:25.84#ibcon#about to read 5, iclass 10, count 0 2006.211.08:45:25.84#ibcon#read 5, iclass 10, count 0 2006.211.08:45:25.84#ibcon#about to read 6, iclass 10, count 0 2006.211.08:45:25.84#ibcon#read 6, iclass 10, count 0 2006.211.08:45:25.84#ibcon#end of sib2, iclass 10, count 0 2006.211.08:45:25.84#ibcon#*after write, iclass 10, count 0 2006.211.08:45:25.84#ibcon#*before return 0, iclass 10, count 0 2006.211.08:45:25.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:45:25.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.211.08:45:25.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.211.08:45:25.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.211.08:45:25.84$vc4f8/va=3,6 2006.211.08:45:25.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.211.08:45:25.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.211.08:45:25.84#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:25.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:45:25.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:45:25.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:45:25.90#ibcon#enter wrdev, iclass 12, count 2 2006.211.08:45:25.90#ibcon#first serial, iclass 12, count 2 2006.211.08:45:25.90#ibcon#enter sib2, iclass 12, count 2 2006.211.08:45:25.90#ibcon#flushed, iclass 12, count 2 2006.211.08:45:25.90#ibcon#about to write, iclass 12, count 2 2006.211.08:45:25.90#ibcon#wrote, iclass 12, count 2 2006.211.08:45:25.90#ibcon#about to read 3, iclass 12, count 2 2006.211.08:45:25.92#ibcon#read 3, iclass 12, count 2 2006.211.08:45:25.92#ibcon#about to read 4, iclass 12, count 2 2006.211.08:45:25.92#ibcon#read 4, iclass 12, count 2 2006.211.08:45:25.92#ibcon#about to read 5, iclass 12, count 2 2006.211.08:45:25.92#ibcon#read 5, iclass 12, count 2 2006.211.08:45:25.92#ibcon#about to read 6, iclass 12, count 2 2006.211.08:45:25.92#ibcon#read 6, iclass 12, count 2 2006.211.08:45:25.92#ibcon#end of sib2, iclass 12, count 2 2006.211.08:45:25.92#ibcon#*mode == 0, iclass 12, count 2 2006.211.08:45:25.92#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.211.08:45:25.92#ibcon#[25=AT03-06\r\n] 2006.211.08:45:25.92#ibcon#*before write, iclass 12, count 2 2006.211.08:45:25.92#ibcon#enter sib2, iclass 12, count 2 2006.211.08:45:25.92#ibcon#flushed, iclass 12, count 2 2006.211.08:45:25.92#ibcon#about to write, iclass 12, count 2 2006.211.08:45:25.92#ibcon#wrote, iclass 12, count 2 2006.211.08:45:25.92#ibcon#about to read 3, iclass 12, count 2 2006.211.08:45:25.96#ibcon#read 3, iclass 12, count 2 2006.211.08:45:25.96#ibcon#about to read 4, iclass 12, count 2 2006.211.08:45:25.96#ibcon#read 4, iclass 12, count 2 2006.211.08:45:25.96#ibcon#about to read 5, iclass 12, count 2 2006.211.08:45:25.96#ibcon#read 5, iclass 12, count 2 2006.211.08:45:25.96#ibcon#about to read 6, iclass 12, count 2 2006.211.08:45:25.96#ibcon#read 6, iclass 12, count 2 2006.211.08:45:25.96#ibcon#end of sib2, iclass 12, count 2 2006.211.08:45:25.96#ibcon#*after write, iclass 12, count 2 2006.211.08:45:25.96#ibcon#*before return 0, iclass 12, count 2 2006.211.08:45:25.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:45:25.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.211.08:45:25.96#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.211.08:45:25.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:25.96#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:45:26.08#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:45:26.08#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:45:26.08#ibcon#enter wrdev, iclass 12, count 0 2006.211.08:45:26.08#ibcon#first serial, iclass 12, count 0 2006.211.08:45:26.08#ibcon#enter sib2, iclass 12, count 0 2006.211.08:45:26.08#ibcon#flushed, iclass 12, count 0 2006.211.08:45:26.08#ibcon#about to write, iclass 12, count 0 2006.211.08:45:26.08#ibcon#wrote, iclass 12, count 0 2006.211.08:45:26.08#ibcon#about to read 3, iclass 12, count 0 2006.211.08:45:26.10#ibcon#read 3, iclass 12, count 0 2006.211.08:45:26.10#ibcon#about to read 4, iclass 12, count 0 2006.211.08:45:26.10#ibcon#read 4, iclass 12, count 0 2006.211.08:45:26.10#ibcon#about to read 5, iclass 12, count 0 2006.211.08:45:26.10#ibcon#read 5, iclass 12, count 0 2006.211.08:45:26.10#ibcon#about to read 6, iclass 12, count 0 2006.211.08:45:26.10#ibcon#read 6, iclass 12, count 0 2006.211.08:45:26.10#ibcon#end of sib2, iclass 12, count 0 2006.211.08:45:26.10#ibcon#*mode == 0, iclass 12, count 0 2006.211.08:45:26.10#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.211.08:45:26.10#ibcon#[25=USB\r\n] 2006.211.08:45:26.10#ibcon#*before write, iclass 12, count 0 2006.211.08:45:26.10#ibcon#enter sib2, iclass 12, count 0 2006.211.08:45:26.10#ibcon#flushed, iclass 12, count 0 2006.211.08:45:26.10#ibcon#about to write, iclass 12, count 0 2006.211.08:45:26.10#ibcon#wrote, iclass 12, count 0 2006.211.08:45:26.10#ibcon#about to read 3, iclass 12, count 0 2006.211.08:45:26.13#ibcon#read 3, iclass 12, count 0 2006.211.08:45:26.13#ibcon#about to read 4, iclass 12, count 0 2006.211.08:45:26.13#ibcon#read 4, iclass 12, count 0 2006.211.08:45:26.13#ibcon#about to read 5, iclass 12, count 0 2006.211.08:45:26.13#ibcon#read 5, iclass 12, count 0 2006.211.08:45:26.13#ibcon#about to read 6, iclass 12, count 0 2006.211.08:45:26.13#ibcon#read 6, iclass 12, count 0 2006.211.08:45:26.13#ibcon#end of sib2, iclass 12, count 0 2006.211.08:45:26.13#ibcon#*after write, iclass 12, count 0 2006.211.08:45:26.13#ibcon#*before return 0, iclass 12, count 0 2006.211.08:45:26.13#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:45:26.13#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.211.08:45:26.13#ibcon#about to clear, iclass 12 cls_cnt 0 2006.211.08:45:26.13#ibcon#cleared, iclass 12 cls_cnt 0 2006.211.08:45:26.13$vc4f8/valo=4,832.99 2006.211.08:45:26.13#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.211.08:45:26.13#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.211.08:45:26.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:26.13#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:45:26.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:45:26.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:45:26.13#ibcon#enter wrdev, iclass 14, count 0 2006.211.08:45:26.13#ibcon#first serial, iclass 14, count 0 2006.211.08:45:26.13#ibcon#enter sib2, iclass 14, count 0 2006.211.08:45:26.13#ibcon#flushed, iclass 14, count 0 2006.211.08:45:26.13#ibcon#about to write, iclass 14, count 0 2006.211.08:45:26.13#ibcon#wrote, iclass 14, count 0 2006.211.08:45:26.13#ibcon#about to read 3, iclass 14, count 0 2006.211.08:45:26.15#ibcon#read 3, iclass 14, count 0 2006.211.08:45:26.15#ibcon#about to read 4, iclass 14, count 0 2006.211.08:45:26.15#ibcon#read 4, iclass 14, count 0 2006.211.08:45:26.15#ibcon#about to read 5, iclass 14, count 0 2006.211.08:45:26.15#ibcon#read 5, iclass 14, count 0 2006.211.08:45:26.15#ibcon#about to read 6, iclass 14, count 0 2006.211.08:45:26.15#ibcon#read 6, iclass 14, count 0 2006.211.08:45:26.15#ibcon#end of sib2, iclass 14, count 0 2006.211.08:45:26.15#ibcon#*mode == 0, iclass 14, count 0 2006.211.08:45:26.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.211.08:45:26.15#ibcon#[26=FRQ=04,832.99\r\n] 2006.211.08:45:26.15#ibcon#*before write, iclass 14, count 0 2006.211.08:45:26.15#ibcon#enter sib2, iclass 14, count 0 2006.211.08:45:26.15#ibcon#flushed, iclass 14, count 0 2006.211.08:45:26.15#ibcon#about to write, iclass 14, count 0 2006.211.08:45:26.15#ibcon#wrote, iclass 14, count 0 2006.211.08:45:26.15#ibcon#about to read 3, iclass 14, count 0 2006.211.08:45:26.19#ibcon#read 3, iclass 14, count 0 2006.211.08:45:26.19#ibcon#about to read 4, iclass 14, count 0 2006.211.08:45:26.19#ibcon#read 4, iclass 14, count 0 2006.211.08:45:26.19#ibcon#about to read 5, iclass 14, count 0 2006.211.08:45:26.19#ibcon#read 5, iclass 14, count 0 2006.211.08:45:26.19#ibcon#about to read 6, iclass 14, count 0 2006.211.08:45:26.19#ibcon#read 6, iclass 14, count 0 2006.211.08:45:26.19#ibcon#end of sib2, iclass 14, count 0 2006.211.08:45:26.19#ibcon#*after write, iclass 14, count 0 2006.211.08:45:26.19#ibcon#*before return 0, iclass 14, count 0 2006.211.08:45:26.19#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:45:26.19#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.211.08:45:26.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.211.08:45:26.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.211.08:45:26.19$vc4f8/va=4,7 2006.211.08:45:26.19#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.211.08:45:26.19#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.211.08:45:26.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:26.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:45:26.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:45:26.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:45:26.25#ibcon#enter wrdev, iclass 16, count 2 2006.211.08:45:26.25#ibcon#first serial, iclass 16, count 2 2006.211.08:45:26.25#ibcon#enter sib2, iclass 16, count 2 2006.211.08:45:26.25#ibcon#flushed, iclass 16, count 2 2006.211.08:45:26.25#ibcon#about to write, iclass 16, count 2 2006.211.08:45:26.25#ibcon#wrote, iclass 16, count 2 2006.211.08:45:26.25#ibcon#about to read 3, iclass 16, count 2 2006.211.08:45:26.27#ibcon#read 3, iclass 16, count 2 2006.211.08:45:26.27#ibcon#about to read 4, iclass 16, count 2 2006.211.08:45:26.27#ibcon#read 4, iclass 16, count 2 2006.211.08:45:26.27#ibcon#about to read 5, iclass 16, count 2 2006.211.08:45:26.27#ibcon#read 5, iclass 16, count 2 2006.211.08:45:26.27#ibcon#about to read 6, iclass 16, count 2 2006.211.08:45:26.27#ibcon#read 6, iclass 16, count 2 2006.211.08:45:26.27#ibcon#end of sib2, iclass 16, count 2 2006.211.08:45:26.27#ibcon#*mode == 0, iclass 16, count 2 2006.211.08:45:26.27#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.211.08:45:26.27#ibcon#[25=AT04-07\r\n] 2006.211.08:45:26.27#ibcon#*before write, iclass 16, count 2 2006.211.08:45:26.27#ibcon#enter sib2, iclass 16, count 2 2006.211.08:45:26.27#ibcon#flushed, iclass 16, count 2 2006.211.08:45:26.27#ibcon#about to write, iclass 16, count 2 2006.211.08:45:26.27#ibcon#wrote, iclass 16, count 2 2006.211.08:45:26.27#ibcon#about to read 3, iclass 16, count 2 2006.211.08:45:26.30#ibcon#read 3, iclass 16, count 2 2006.211.08:45:26.30#ibcon#about to read 4, iclass 16, count 2 2006.211.08:45:26.30#ibcon#read 4, iclass 16, count 2 2006.211.08:45:26.30#ibcon#about to read 5, iclass 16, count 2 2006.211.08:45:26.30#ibcon#read 5, iclass 16, count 2 2006.211.08:45:26.30#ibcon#about to read 6, iclass 16, count 2 2006.211.08:45:26.30#ibcon#read 6, iclass 16, count 2 2006.211.08:45:26.30#ibcon#end of sib2, iclass 16, count 2 2006.211.08:45:26.30#ibcon#*after write, iclass 16, count 2 2006.211.08:45:26.30#ibcon#*before return 0, iclass 16, count 2 2006.211.08:45:26.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:45:26.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.211.08:45:26.30#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.211.08:45:26.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:26.30#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:45:26.42#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:45:26.42#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:45:26.42#ibcon#enter wrdev, iclass 16, count 0 2006.211.08:45:26.42#ibcon#first serial, iclass 16, count 0 2006.211.08:45:26.42#ibcon#enter sib2, iclass 16, count 0 2006.211.08:45:26.42#ibcon#flushed, iclass 16, count 0 2006.211.08:45:26.42#ibcon#about to write, iclass 16, count 0 2006.211.08:45:26.42#ibcon#wrote, iclass 16, count 0 2006.211.08:45:26.42#ibcon#about to read 3, iclass 16, count 0 2006.211.08:45:26.44#ibcon#read 3, iclass 16, count 0 2006.211.08:45:26.44#ibcon#about to read 4, iclass 16, count 0 2006.211.08:45:26.44#ibcon#read 4, iclass 16, count 0 2006.211.08:45:26.44#ibcon#about to read 5, iclass 16, count 0 2006.211.08:45:26.44#ibcon#read 5, iclass 16, count 0 2006.211.08:45:26.44#ibcon#about to read 6, iclass 16, count 0 2006.211.08:45:26.44#ibcon#read 6, iclass 16, count 0 2006.211.08:45:26.44#ibcon#end of sib2, iclass 16, count 0 2006.211.08:45:26.44#ibcon#*mode == 0, iclass 16, count 0 2006.211.08:45:26.44#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.211.08:45:26.44#ibcon#[25=USB\r\n] 2006.211.08:45:26.44#ibcon#*before write, iclass 16, count 0 2006.211.08:45:26.44#ibcon#enter sib2, iclass 16, count 0 2006.211.08:45:26.44#ibcon#flushed, iclass 16, count 0 2006.211.08:45:26.44#ibcon#about to write, iclass 16, count 0 2006.211.08:45:26.44#ibcon#wrote, iclass 16, count 0 2006.211.08:45:26.44#ibcon#about to read 3, iclass 16, count 0 2006.211.08:45:26.47#ibcon#read 3, iclass 16, count 0 2006.211.08:45:26.47#ibcon#about to read 4, iclass 16, count 0 2006.211.08:45:26.47#ibcon#read 4, iclass 16, count 0 2006.211.08:45:26.47#ibcon#about to read 5, iclass 16, count 0 2006.211.08:45:26.47#ibcon#read 5, iclass 16, count 0 2006.211.08:45:26.47#ibcon#about to read 6, iclass 16, count 0 2006.211.08:45:26.47#ibcon#read 6, iclass 16, count 0 2006.211.08:45:26.47#ibcon#end of sib2, iclass 16, count 0 2006.211.08:45:26.47#ibcon#*after write, iclass 16, count 0 2006.211.08:45:26.47#ibcon#*before return 0, iclass 16, count 0 2006.211.08:45:26.47#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:45:26.47#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.211.08:45:26.47#ibcon#about to clear, iclass 16 cls_cnt 0 2006.211.08:45:26.47#ibcon#cleared, iclass 16 cls_cnt 0 2006.211.08:45:26.47$vc4f8/valo=5,652.99 2006.211.08:45:26.47#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.211.08:45:26.47#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.211.08:45:26.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:26.47#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:45:26.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:45:26.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:45:26.47#ibcon#enter wrdev, iclass 18, count 0 2006.211.08:45:26.47#ibcon#first serial, iclass 18, count 0 2006.211.08:45:26.47#ibcon#enter sib2, iclass 18, count 0 2006.211.08:45:26.47#ibcon#flushed, iclass 18, count 0 2006.211.08:45:26.47#ibcon#about to write, iclass 18, count 0 2006.211.08:45:26.47#ibcon#wrote, iclass 18, count 0 2006.211.08:45:26.47#ibcon#about to read 3, iclass 18, count 0 2006.211.08:45:26.49#ibcon#read 3, iclass 18, count 0 2006.211.08:45:26.49#ibcon#about to read 4, iclass 18, count 0 2006.211.08:45:26.49#ibcon#read 4, iclass 18, count 0 2006.211.08:45:26.49#ibcon#about to read 5, iclass 18, count 0 2006.211.08:45:26.49#ibcon#read 5, iclass 18, count 0 2006.211.08:45:26.49#ibcon#about to read 6, iclass 18, count 0 2006.211.08:45:26.49#ibcon#read 6, iclass 18, count 0 2006.211.08:45:26.49#ibcon#end of sib2, iclass 18, count 0 2006.211.08:45:26.49#ibcon#*mode == 0, iclass 18, count 0 2006.211.08:45:26.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.211.08:45:26.49#ibcon#[26=FRQ=05,652.99\r\n] 2006.211.08:45:26.49#ibcon#*before write, iclass 18, count 0 2006.211.08:45:26.49#ibcon#enter sib2, iclass 18, count 0 2006.211.08:45:26.49#ibcon#flushed, iclass 18, count 0 2006.211.08:45:26.49#ibcon#about to write, iclass 18, count 0 2006.211.08:45:26.49#ibcon#wrote, iclass 18, count 0 2006.211.08:45:26.49#ibcon#about to read 3, iclass 18, count 0 2006.211.08:45:26.53#ibcon#read 3, iclass 18, count 0 2006.211.08:45:26.53#ibcon#about to read 4, iclass 18, count 0 2006.211.08:45:26.53#ibcon#read 4, iclass 18, count 0 2006.211.08:45:26.53#ibcon#about to read 5, iclass 18, count 0 2006.211.08:45:26.53#ibcon#read 5, iclass 18, count 0 2006.211.08:45:26.53#ibcon#about to read 6, iclass 18, count 0 2006.211.08:45:26.53#ibcon#read 6, iclass 18, count 0 2006.211.08:45:26.53#ibcon#end of sib2, iclass 18, count 0 2006.211.08:45:26.53#ibcon#*after write, iclass 18, count 0 2006.211.08:45:26.53#ibcon#*before return 0, iclass 18, count 0 2006.211.08:45:26.53#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:45:26.53#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.211.08:45:26.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.211.08:45:26.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.211.08:45:26.53$vc4f8/va=5,7 2006.211.08:45:26.53#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.211.08:45:26.53#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.211.08:45:26.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:26.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:45:26.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:45:26.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:45:26.59#ibcon#enter wrdev, iclass 20, count 2 2006.211.08:45:26.59#ibcon#first serial, iclass 20, count 2 2006.211.08:45:26.59#ibcon#enter sib2, iclass 20, count 2 2006.211.08:45:26.59#ibcon#flushed, iclass 20, count 2 2006.211.08:45:26.59#ibcon#about to write, iclass 20, count 2 2006.211.08:45:26.59#ibcon#wrote, iclass 20, count 2 2006.211.08:45:26.59#ibcon#about to read 3, iclass 20, count 2 2006.211.08:45:26.61#ibcon#read 3, iclass 20, count 2 2006.211.08:45:26.61#ibcon#about to read 4, iclass 20, count 2 2006.211.08:45:26.61#ibcon#read 4, iclass 20, count 2 2006.211.08:45:26.61#ibcon#about to read 5, iclass 20, count 2 2006.211.08:45:26.61#ibcon#read 5, iclass 20, count 2 2006.211.08:45:26.61#ibcon#about to read 6, iclass 20, count 2 2006.211.08:45:26.61#ibcon#read 6, iclass 20, count 2 2006.211.08:45:26.61#ibcon#end of sib2, iclass 20, count 2 2006.211.08:45:26.61#ibcon#*mode == 0, iclass 20, count 2 2006.211.08:45:26.61#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.211.08:45:26.61#ibcon#[25=AT05-07\r\n] 2006.211.08:45:26.61#ibcon#*before write, iclass 20, count 2 2006.211.08:45:26.61#ibcon#enter sib2, iclass 20, count 2 2006.211.08:45:26.61#ibcon#flushed, iclass 20, count 2 2006.211.08:45:26.61#ibcon#about to write, iclass 20, count 2 2006.211.08:45:26.61#ibcon#wrote, iclass 20, count 2 2006.211.08:45:26.61#ibcon#about to read 3, iclass 20, count 2 2006.211.08:45:26.64#ibcon#read 3, iclass 20, count 2 2006.211.08:45:26.64#ibcon#about to read 4, iclass 20, count 2 2006.211.08:45:26.64#ibcon#read 4, iclass 20, count 2 2006.211.08:45:26.64#ibcon#about to read 5, iclass 20, count 2 2006.211.08:45:26.64#ibcon#read 5, iclass 20, count 2 2006.211.08:45:26.64#ibcon#about to read 6, iclass 20, count 2 2006.211.08:45:26.64#ibcon#read 6, iclass 20, count 2 2006.211.08:45:26.64#ibcon#end of sib2, iclass 20, count 2 2006.211.08:45:26.64#ibcon#*after write, iclass 20, count 2 2006.211.08:45:26.64#ibcon#*before return 0, iclass 20, count 2 2006.211.08:45:26.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:45:26.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.211.08:45:26.64#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.211.08:45:26.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:26.64#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:45:26.76#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:45:26.76#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:45:26.76#ibcon#enter wrdev, iclass 20, count 0 2006.211.08:45:26.76#ibcon#first serial, iclass 20, count 0 2006.211.08:45:26.76#ibcon#enter sib2, iclass 20, count 0 2006.211.08:45:26.76#ibcon#flushed, iclass 20, count 0 2006.211.08:45:26.76#ibcon#about to write, iclass 20, count 0 2006.211.08:45:26.76#ibcon#wrote, iclass 20, count 0 2006.211.08:45:26.76#ibcon#about to read 3, iclass 20, count 0 2006.211.08:45:26.78#ibcon#read 3, iclass 20, count 0 2006.211.08:45:26.78#ibcon#about to read 4, iclass 20, count 0 2006.211.08:45:26.78#ibcon#read 4, iclass 20, count 0 2006.211.08:45:26.78#ibcon#about to read 5, iclass 20, count 0 2006.211.08:45:26.78#ibcon#read 5, iclass 20, count 0 2006.211.08:45:26.78#ibcon#about to read 6, iclass 20, count 0 2006.211.08:45:26.78#ibcon#read 6, iclass 20, count 0 2006.211.08:45:26.78#ibcon#end of sib2, iclass 20, count 0 2006.211.08:45:26.78#ibcon#*mode == 0, iclass 20, count 0 2006.211.08:45:26.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.211.08:45:26.78#ibcon#[25=USB\r\n] 2006.211.08:45:26.78#ibcon#*before write, iclass 20, count 0 2006.211.08:45:26.78#ibcon#enter sib2, iclass 20, count 0 2006.211.08:45:26.78#ibcon#flushed, iclass 20, count 0 2006.211.08:45:26.78#ibcon#about to write, iclass 20, count 0 2006.211.08:45:26.78#ibcon#wrote, iclass 20, count 0 2006.211.08:45:26.78#ibcon#about to read 3, iclass 20, count 0 2006.211.08:45:26.81#ibcon#read 3, iclass 20, count 0 2006.211.08:45:26.81#ibcon#about to read 4, iclass 20, count 0 2006.211.08:45:26.81#ibcon#read 4, iclass 20, count 0 2006.211.08:45:26.81#ibcon#about to read 5, iclass 20, count 0 2006.211.08:45:26.81#ibcon#read 5, iclass 20, count 0 2006.211.08:45:26.81#ibcon#about to read 6, iclass 20, count 0 2006.211.08:45:26.81#ibcon#read 6, iclass 20, count 0 2006.211.08:45:26.81#ibcon#end of sib2, iclass 20, count 0 2006.211.08:45:26.81#ibcon#*after write, iclass 20, count 0 2006.211.08:45:26.81#ibcon#*before return 0, iclass 20, count 0 2006.211.08:45:26.81#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:45:26.81#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.211.08:45:26.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.211.08:45:26.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.211.08:45:26.81$vc4f8/valo=6,772.99 2006.211.08:45:26.81#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.211.08:45:26.81#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.211.08:45:26.81#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:26.81#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:45:26.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:45:26.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:45:26.81#ibcon#enter wrdev, iclass 22, count 0 2006.211.08:45:26.81#ibcon#first serial, iclass 22, count 0 2006.211.08:45:26.81#ibcon#enter sib2, iclass 22, count 0 2006.211.08:45:26.81#ibcon#flushed, iclass 22, count 0 2006.211.08:45:26.81#ibcon#about to write, iclass 22, count 0 2006.211.08:45:26.81#ibcon#wrote, iclass 22, count 0 2006.211.08:45:26.81#ibcon#about to read 3, iclass 22, count 0 2006.211.08:45:26.83#ibcon#read 3, iclass 22, count 0 2006.211.08:45:26.83#ibcon#about to read 4, iclass 22, count 0 2006.211.08:45:26.83#ibcon#read 4, iclass 22, count 0 2006.211.08:45:26.83#ibcon#about to read 5, iclass 22, count 0 2006.211.08:45:26.83#ibcon#read 5, iclass 22, count 0 2006.211.08:45:26.83#ibcon#about to read 6, iclass 22, count 0 2006.211.08:45:26.83#ibcon#read 6, iclass 22, count 0 2006.211.08:45:26.83#ibcon#end of sib2, iclass 22, count 0 2006.211.08:45:26.83#ibcon#*mode == 0, iclass 22, count 0 2006.211.08:45:26.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.211.08:45:26.83#ibcon#[26=FRQ=06,772.99\r\n] 2006.211.08:45:26.83#ibcon#*before write, iclass 22, count 0 2006.211.08:45:26.83#ibcon#enter sib2, iclass 22, count 0 2006.211.08:45:26.83#ibcon#flushed, iclass 22, count 0 2006.211.08:45:26.83#ibcon#about to write, iclass 22, count 0 2006.211.08:45:26.83#ibcon#wrote, iclass 22, count 0 2006.211.08:45:26.83#ibcon#about to read 3, iclass 22, count 0 2006.211.08:45:26.87#ibcon#read 3, iclass 22, count 0 2006.211.08:45:26.87#ibcon#about to read 4, iclass 22, count 0 2006.211.08:45:26.87#ibcon#read 4, iclass 22, count 0 2006.211.08:45:26.87#ibcon#about to read 5, iclass 22, count 0 2006.211.08:45:26.87#ibcon#read 5, iclass 22, count 0 2006.211.08:45:26.87#ibcon#about to read 6, iclass 22, count 0 2006.211.08:45:26.87#ibcon#read 6, iclass 22, count 0 2006.211.08:45:26.87#ibcon#end of sib2, iclass 22, count 0 2006.211.08:45:26.87#ibcon#*after write, iclass 22, count 0 2006.211.08:45:26.87#ibcon#*before return 0, iclass 22, count 0 2006.211.08:45:26.87#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:45:26.87#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.211.08:45:26.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.211.08:45:26.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.211.08:45:26.87$vc4f8/va=6,6 2006.211.08:45:26.87#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.211.08:45:26.87#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.211.08:45:26.87#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:26.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:45:26.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:45:26.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:45:26.93#ibcon#enter wrdev, iclass 24, count 2 2006.211.08:45:26.93#ibcon#first serial, iclass 24, count 2 2006.211.08:45:26.93#ibcon#enter sib2, iclass 24, count 2 2006.211.08:45:26.93#ibcon#flushed, iclass 24, count 2 2006.211.08:45:26.93#ibcon#about to write, iclass 24, count 2 2006.211.08:45:26.93#ibcon#wrote, iclass 24, count 2 2006.211.08:45:26.93#ibcon#about to read 3, iclass 24, count 2 2006.211.08:45:26.95#ibcon#read 3, iclass 24, count 2 2006.211.08:45:26.95#ibcon#about to read 4, iclass 24, count 2 2006.211.08:45:26.95#ibcon#read 4, iclass 24, count 2 2006.211.08:45:26.95#ibcon#about to read 5, iclass 24, count 2 2006.211.08:45:26.95#ibcon#read 5, iclass 24, count 2 2006.211.08:45:26.95#ibcon#about to read 6, iclass 24, count 2 2006.211.08:45:26.95#ibcon#read 6, iclass 24, count 2 2006.211.08:45:26.95#ibcon#end of sib2, iclass 24, count 2 2006.211.08:45:26.95#ibcon#*mode == 0, iclass 24, count 2 2006.211.08:45:26.95#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.211.08:45:26.95#ibcon#[25=AT06-06\r\n] 2006.211.08:45:26.95#ibcon#*before write, iclass 24, count 2 2006.211.08:45:26.95#ibcon#enter sib2, iclass 24, count 2 2006.211.08:45:26.95#ibcon#flushed, iclass 24, count 2 2006.211.08:45:26.95#ibcon#about to write, iclass 24, count 2 2006.211.08:45:26.95#ibcon#wrote, iclass 24, count 2 2006.211.08:45:26.95#ibcon#about to read 3, iclass 24, count 2 2006.211.08:45:26.98#ibcon#read 3, iclass 24, count 2 2006.211.08:45:26.98#ibcon#about to read 4, iclass 24, count 2 2006.211.08:45:26.98#ibcon#read 4, iclass 24, count 2 2006.211.08:45:26.98#ibcon#about to read 5, iclass 24, count 2 2006.211.08:45:26.98#ibcon#read 5, iclass 24, count 2 2006.211.08:45:26.98#ibcon#about to read 6, iclass 24, count 2 2006.211.08:45:26.98#ibcon#read 6, iclass 24, count 2 2006.211.08:45:26.98#ibcon#end of sib2, iclass 24, count 2 2006.211.08:45:26.98#ibcon#*after write, iclass 24, count 2 2006.211.08:45:26.98#ibcon#*before return 0, iclass 24, count 2 2006.211.08:45:26.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:45:26.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.211.08:45:26.98#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.211.08:45:26.98#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:26.98#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:45:27.10#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:45:27.10#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:45:27.10#ibcon#enter wrdev, iclass 24, count 0 2006.211.08:45:27.10#ibcon#first serial, iclass 24, count 0 2006.211.08:45:27.10#ibcon#enter sib2, iclass 24, count 0 2006.211.08:45:27.10#ibcon#flushed, iclass 24, count 0 2006.211.08:45:27.10#ibcon#about to write, iclass 24, count 0 2006.211.08:45:27.10#ibcon#wrote, iclass 24, count 0 2006.211.08:45:27.10#ibcon#about to read 3, iclass 24, count 0 2006.211.08:45:27.12#ibcon#read 3, iclass 24, count 0 2006.211.08:45:27.12#ibcon#about to read 4, iclass 24, count 0 2006.211.08:45:27.12#ibcon#read 4, iclass 24, count 0 2006.211.08:45:27.12#ibcon#about to read 5, iclass 24, count 0 2006.211.08:45:27.12#ibcon#read 5, iclass 24, count 0 2006.211.08:45:27.12#ibcon#about to read 6, iclass 24, count 0 2006.211.08:45:27.12#ibcon#read 6, iclass 24, count 0 2006.211.08:45:27.12#ibcon#end of sib2, iclass 24, count 0 2006.211.08:45:27.12#ibcon#*mode == 0, iclass 24, count 0 2006.211.08:45:27.12#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.211.08:45:27.12#ibcon#[25=USB\r\n] 2006.211.08:45:27.12#ibcon#*before write, iclass 24, count 0 2006.211.08:45:27.12#ibcon#enter sib2, iclass 24, count 0 2006.211.08:45:27.12#ibcon#flushed, iclass 24, count 0 2006.211.08:45:27.12#ibcon#about to write, iclass 24, count 0 2006.211.08:45:27.12#ibcon#wrote, iclass 24, count 0 2006.211.08:45:27.12#ibcon#about to read 3, iclass 24, count 0 2006.211.08:45:27.15#ibcon#read 3, iclass 24, count 0 2006.211.08:45:27.15#ibcon#about to read 4, iclass 24, count 0 2006.211.08:45:27.15#ibcon#read 4, iclass 24, count 0 2006.211.08:45:27.15#ibcon#about to read 5, iclass 24, count 0 2006.211.08:45:27.15#ibcon#read 5, iclass 24, count 0 2006.211.08:45:27.15#ibcon#about to read 6, iclass 24, count 0 2006.211.08:45:27.15#ibcon#read 6, iclass 24, count 0 2006.211.08:45:27.15#ibcon#end of sib2, iclass 24, count 0 2006.211.08:45:27.15#ibcon#*after write, iclass 24, count 0 2006.211.08:45:27.15#ibcon#*before return 0, iclass 24, count 0 2006.211.08:45:27.15#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:45:27.15#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.211.08:45:27.15#ibcon#about to clear, iclass 24 cls_cnt 0 2006.211.08:45:27.15#ibcon#cleared, iclass 24 cls_cnt 0 2006.211.08:45:27.15$vc4f8/valo=7,832.99 2006.211.08:45:27.15#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.211.08:45:27.15#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.211.08:45:27.15#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:27.15#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:45:27.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:45:27.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:45:27.15#ibcon#enter wrdev, iclass 26, count 0 2006.211.08:45:27.15#ibcon#first serial, iclass 26, count 0 2006.211.08:45:27.15#ibcon#enter sib2, iclass 26, count 0 2006.211.08:45:27.15#ibcon#flushed, iclass 26, count 0 2006.211.08:45:27.15#ibcon#about to write, iclass 26, count 0 2006.211.08:45:27.15#ibcon#wrote, iclass 26, count 0 2006.211.08:45:27.15#ibcon#about to read 3, iclass 26, count 0 2006.211.08:45:27.17#ibcon#read 3, iclass 26, count 0 2006.211.08:45:27.17#ibcon#about to read 4, iclass 26, count 0 2006.211.08:45:27.17#ibcon#read 4, iclass 26, count 0 2006.211.08:45:27.17#ibcon#about to read 5, iclass 26, count 0 2006.211.08:45:27.17#ibcon#read 5, iclass 26, count 0 2006.211.08:45:27.17#ibcon#about to read 6, iclass 26, count 0 2006.211.08:45:27.17#ibcon#read 6, iclass 26, count 0 2006.211.08:45:27.17#ibcon#end of sib2, iclass 26, count 0 2006.211.08:45:27.17#ibcon#*mode == 0, iclass 26, count 0 2006.211.08:45:27.17#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.211.08:45:27.17#ibcon#[26=FRQ=07,832.99\r\n] 2006.211.08:45:27.17#ibcon#*before write, iclass 26, count 0 2006.211.08:45:27.17#ibcon#enter sib2, iclass 26, count 0 2006.211.08:45:27.17#ibcon#flushed, iclass 26, count 0 2006.211.08:45:27.17#ibcon#about to write, iclass 26, count 0 2006.211.08:45:27.17#ibcon#wrote, iclass 26, count 0 2006.211.08:45:27.17#ibcon#about to read 3, iclass 26, count 0 2006.211.08:45:27.21#ibcon#read 3, iclass 26, count 0 2006.211.08:45:27.21#ibcon#about to read 4, iclass 26, count 0 2006.211.08:45:27.21#ibcon#read 4, iclass 26, count 0 2006.211.08:45:27.21#ibcon#about to read 5, iclass 26, count 0 2006.211.08:45:27.21#ibcon#read 5, iclass 26, count 0 2006.211.08:45:27.21#ibcon#about to read 6, iclass 26, count 0 2006.211.08:45:27.21#ibcon#read 6, iclass 26, count 0 2006.211.08:45:27.21#ibcon#end of sib2, iclass 26, count 0 2006.211.08:45:27.21#ibcon#*after write, iclass 26, count 0 2006.211.08:45:27.21#ibcon#*before return 0, iclass 26, count 0 2006.211.08:45:27.21#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:45:27.21#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.211.08:45:27.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.211.08:45:27.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.211.08:45:27.21$vc4f8/va=7,6 2006.211.08:45:27.21#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.211.08:45:27.21#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.211.08:45:27.21#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:27.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:45:27.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:45:27.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:45:27.27#ibcon#enter wrdev, iclass 28, count 2 2006.211.08:45:27.27#ibcon#first serial, iclass 28, count 2 2006.211.08:45:27.27#ibcon#enter sib2, iclass 28, count 2 2006.211.08:45:27.27#ibcon#flushed, iclass 28, count 2 2006.211.08:45:27.27#ibcon#about to write, iclass 28, count 2 2006.211.08:45:27.27#ibcon#wrote, iclass 28, count 2 2006.211.08:45:27.27#ibcon#about to read 3, iclass 28, count 2 2006.211.08:45:27.29#ibcon#read 3, iclass 28, count 2 2006.211.08:45:27.29#ibcon#about to read 4, iclass 28, count 2 2006.211.08:45:27.29#ibcon#read 4, iclass 28, count 2 2006.211.08:45:27.29#ibcon#about to read 5, iclass 28, count 2 2006.211.08:45:27.29#ibcon#read 5, iclass 28, count 2 2006.211.08:45:27.29#ibcon#about to read 6, iclass 28, count 2 2006.211.08:45:27.29#ibcon#read 6, iclass 28, count 2 2006.211.08:45:27.29#ibcon#end of sib2, iclass 28, count 2 2006.211.08:45:27.29#ibcon#*mode == 0, iclass 28, count 2 2006.211.08:45:27.29#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.211.08:45:27.29#ibcon#[25=AT07-06\r\n] 2006.211.08:45:27.29#ibcon#*before write, iclass 28, count 2 2006.211.08:45:27.29#ibcon#enter sib2, iclass 28, count 2 2006.211.08:45:27.29#ibcon#flushed, iclass 28, count 2 2006.211.08:45:27.29#ibcon#about to write, iclass 28, count 2 2006.211.08:45:27.29#ibcon#wrote, iclass 28, count 2 2006.211.08:45:27.29#ibcon#about to read 3, iclass 28, count 2 2006.211.08:45:27.32#ibcon#read 3, iclass 28, count 2 2006.211.08:45:27.32#ibcon#about to read 4, iclass 28, count 2 2006.211.08:45:27.32#ibcon#read 4, iclass 28, count 2 2006.211.08:45:27.32#ibcon#about to read 5, iclass 28, count 2 2006.211.08:45:27.32#ibcon#read 5, iclass 28, count 2 2006.211.08:45:27.32#ibcon#about to read 6, iclass 28, count 2 2006.211.08:45:27.32#ibcon#read 6, iclass 28, count 2 2006.211.08:45:27.32#ibcon#end of sib2, iclass 28, count 2 2006.211.08:45:27.32#ibcon#*after write, iclass 28, count 2 2006.211.08:45:27.32#ibcon#*before return 0, iclass 28, count 2 2006.211.08:45:27.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:45:27.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.211.08:45:27.32#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.211.08:45:27.32#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:27.32#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:45:27.44#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:45:27.44#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:45:27.44#ibcon#enter wrdev, iclass 28, count 0 2006.211.08:45:27.44#ibcon#first serial, iclass 28, count 0 2006.211.08:45:27.44#ibcon#enter sib2, iclass 28, count 0 2006.211.08:45:27.44#ibcon#flushed, iclass 28, count 0 2006.211.08:45:27.44#ibcon#about to write, iclass 28, count 0 2006.211.08:45:27.44#ibcon#wrote, iclass 28, count 0 2006.211.08:45:27.44#ibcon#about to read 3, iclass 28, count 0 2006.211.08:45:27.46#ibcon#read 3, iclass 28, count 0 2006.211.08:45:27.46#ibcon#about to read 4, iclass 28, count 0 2006.211.08:45:27.46#ibcon#read 4, iclass 28, count 0 2006.211.08:45:27.46#ibcon#about to read 5, iclass 28, count 0 2006.211.08:45:27.46#ibcon#read 5, iclass 28, count 0 2006.211.08:45:27.46#ibcon#about to read 6, iclass 28, count 0 2006.211.08:45:27.46#ibcon#read 6, iclass 28, count 0 2006.211.08:45:27.46#ibcon#end of sib2, iclass 28, count 0 2006.211.08:45:27.46#ibcon#*mode == 0, iclass 28, count 0 2006.211.08:45:27.46#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.211.08:45:27.46#ibcon#[25=USB\r\n] 2006.211.08:45:27.46#ibcon#*before write, iclass 28, count 0 2006.211.08:45:27.46#ibcon#enter sib2, iclass 28, count 0 2006.211.08:45:27.46#ibcon#flushed, iclass 28, count 0 2006.211.08:45:27.46#ibcon#about to write, iclass 28, count 0 2006.211.08:45:27.46#ibcon#wrote, iclass 28, count 0 2006.211.08:45:27.46#ibcon#about to read 3, iclass 28, count 0 2006.211.08:45:27.49#ibcon#read 3, iclass 28, count 0 2006.211.08:45:27.49#ibcon#about to read 4, iclass 28, count 0 2006.211.08:45:27.49#ibcon#read 4, iclass 28, count 0 2006.211.08:45:27.49#ibcon#about to read 5, iclass 28, count 0 2006.211.08:45:27.49#ibcon#read 5, iclass 28, count 0 2006.211.08:45:27.49#ibcon#about to read 6, iclass 28, count 0 2006.211.08:45:27.49#ibcon#read 6, iclass 28, count 0 2006.211.08:45:27.49#ibcon#end of sib2, iclass 28, count 0 2006.211.08:45:27.49#ibcon#*after write, iclass 28, count 0 2006.211.08:45:27.49#ibcon#*before return 0, iclass 28, count 0 2006.211.08:45:27.49#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:45:27.49#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.211.08:45:27.49#ibcon#about to clear, iclass 28 cls_cnt 0 2006.211.08:45:27.49#ibcon#cleared, iclass 28 cls_cnt 0 2006.211.08:45:27.49$vc4f8/valo=8,852.99 2006.211.08:45:27.49#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.211.08:45:27.49#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.211.08:45:27.49#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:27.49#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:45:27.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:45:27.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:45:27.49#ibcon#enter wrdev, iclass 30, count 0 2006.211.08:45:27.49#ibcon#first serial, iclass 30, count 0 2006.211.08:45:27.49#ibcon#enter sib2, iclass 30, count 0 2006.211.08:45:27.49#ibcon#flushed, iclass 30, count 0 2006.211.08:45:27.49#ibcon#about to write, iclass 30, count 0 2006.211.08:45:27.49#ibcon#wrote, iclass 30, count 0 2006.211.08:45:27.49#ibcon#about to read 3, iclass 30, count 0 2006.211.08:45:27.51#ibcon#read 3, iclass 30, count 0 2006.211.08:45:27.51#ibcon#about to read 4, iclass 30, count 0 2006.211.08:45:27.51#ibcon#read 4, iclass 30, count 0 2006.211.08:45:27.51#ibcon#about to read 5, iclass 30, count 0 2006.211.08:45:27.51#ibcon#read 5, iclass 30, count 0 2006.211.08:45:27.51#ibcon#about to read 6, iclass 30, count 0 2006.211.08:45:27.51#ibcon#read 6, iclass 30, count 0 2006.211.08:45:27.51#ibcon#end of sib2, iclass 30, count 0 2006.211.08:45:27.51#ibcon#*mode == 0, iclass 30, count 0 2006.211.08:45:27.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.211.08:45:27.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.211.08:45:27.51#ibcon#*before write, iclass 30, count 0 2006.211.08:45:27.51#ibcon#enter sib2, iclass 30, count 0 2006.211.08:45:27.51#ibcon#flushed, iclass 30, count 0 2006.211.08:45:27.51#ibcon#about to write, iclass 30, count 0 2006.211.08:45:27.51#ibcon#wrote, iclass 30, count 0 2006.211.08:45:27.51#ibcon#about to read 3, iclass 30, count 0 2006.211.08:45:27.55#ibcon#read 3, iclass 30, count 0 2006.211.08:45:27.55#ibcon#about to read 4, iclass 30, count 0 2006.211.08:45:27.55#ibcon#read 4, iclass 30, count 0 2006.211.08:45:27.55#ibcon#about to read 5, iclass 30, count 0 2006.211.08:45:27.55#ibcon#read 5, iclass 30, count 0 2006.211.08:45:27.55#ibcon#about to read 6, iclass 30, count 0 2006.211.08:45:27.55#ibcon#read 6, iclass 30, count 0 2006.211.08:45:27.55#ibcon#end of sib2, iclass 30, count 0 2006.211.08:45:27.55#ibcon#*after write, iclass 30, count 0 2006.211.08:45:27.55#ibcon#*before return 0, iclass 30, count 0 2006.211.08:45:27.55#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:45:27.55#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.211.08:45:27.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.211.08:45:27.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.211.08:45:27.55$vc4f8/va=8,7 2006.211.08:45:27.55#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.211.08:45:27.55#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.211.08:45:27.55#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:27.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:45:27.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:45:27.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:45:27.61#ibcon#enter wrdev, iclass 33, count 2 2006.211.08:45:27.61#ibcon#first serial, iclass 33, count 2 2006.211.08:45:27.61#ibcon#enter sib2, iclass 33, count 2 2006.211.08:45:27.61#ibcon#flushed, iclass 33, count 2 2006.211.08:45:27.61#ibcon#about to write, iclass 33, count 2 2006.211.08:45:27.61#ibcon#wrote, iclass 33, count 2 2006.211.08:45:27.61#ibcon#about to read 3, iclass 33, count 2 2006.211.08:45:27.63#ibcon#read 3, iclass 33, count 2 2006.211.08:45:27.63#ibcon#about to read 4, iclass 33, count 2 2006.211.08:45:27.63#ibcon#read 4, iclass 33, count 2 2006.211.08:45:27.63#ibcon#about to read 5, iclass 33, count 2 2006.211.08:45:27.63#ibcon#read 5, iclass 33, count 2 2006.211.08:45:27.63#ibcon#about to read 6, iclass 33, count 2 2006.211.08:45:27.63#ibcon#read 6, iclass 33, count 2 2006.211.08:45:27.63#ibcon#end of sib2, iclass 33, count 2 2006.211.08:45:27.63#ibcon#*mode == 0, iclass 33, count 2 2006.211.08:45:27.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.211.08:45:27.63#ibcon#[25=AT08-07\r\n] 2006.211.08:45:27.63#ibcon#*before write, iclass 33, count 2 2006.211.08:45:27.63#ibcon#enter sib2, iclass 33, count 2 2006.211.08:45:27.63#ibcon#flushed, iclass 33, count 2 2006.211.08:45:27.63#ibcon#about to write, iclass 33, count 2 2006.211.08:45:27.63#ibcon#wrote, iclass 33, count 2 2006.211.08:45:27.63#ibcon#about to read 3, iclass 33, count 2 2006.211.08:45:27.66#ibcon#read 3, iclass 33, count 2 2006.211.08:45:27.66#ibcon#about to read 4, iclass 33, count 2 2006.211.08:45:27.66#ibcon#read 4, iclass 33, count 2 2006.211.08:45:27.66#ibcon#about to read 5, iclass 33, count 2 2006.211.08:45:27.66#ibcon#read 5, iclass 33, count 2 2006.211.08:45:27.66#ibcon#about to read 6, iclass 33, count 2 2006.211.08:45:27.66#ibcon#read 6, iclass 33, count 2 2006.211.08:45:27.66#ibcon#end of sib2, iclass 33, count 2 2006.211.08:45:27.66#ibcon#*after write, iclass 33, count 2 2006.211.08:45:27.66#ibcon#*before return 0, iclass 33, count 2 2006.211.08:45:27.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:45:27.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.211.08:45:27.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.211.08:45:27.66#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:27.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:45:27.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:45:27.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:45:27.78#ibcon#enter wrdev, iclass 33, count 0 2006.211.08:45:27.78#ibcon#first serial, iclass 33, count 0 2006.211.08:45:27.78#ibcon#enter sib2, iclass 33, count 0 2006.211.08:45:27.78#ibcon#flushed, iclass 33, count 0 2006.211.08:45:27.78#ibcon#about to write, iclass 33, count 0 2006.211.08:45:27.78#ibcon#wrote, iclass 33, count 0 2006.211.08:45:27.78#ibcon#about to read 3, iclass 33, count 0 2006.211.08:45:27.80#ibcon#read 3, iclass 33, count 0 2006.211.08:45:27.80#ibcon#about to read 4, iclass 33, count 0 2006.211.08:45:27.80#ibcon#read 4, iclass 33, count 0 2006.211.08:45:27.80#ibcon#about to read 5, iclass 33, count 0 2006.211.08:45:27.80#ibcon#read 5, iclass 33, count 0 2006.211.08:45:27.80#ibcon#about to read 6, iclass 33, count 0 2006.211.08:45:27.80#ibcon#read 6, iclass 33, count 0 2006.211.08:45:27.80#ibcon#end of sib2, iclass 33, count 0 2006.211.08:45:27.80#ibcon#*mode == 0, iclass 33, count 0 2006.211.08:45:27.80#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.211.08:45:27.80#ibcon#[25=USB\r\n] 2006.211.08:45:27.80#ibcon#*before write, iclass 33, count 0 2006.211.08:45:27.80#ibcon#enter sib2, iclass 33, count 0 2006.211.08:45:27.80#ibcon#flushed, iclass 33, count 0 2006.211.08:45:27.80#ibcon#about to write, iclass 33, count 0 2006.211.08:45:27.80#ibcon#wrote, iclass 33, count 0 2006.211.08:45:27.80#ibcon#about to read 3, iclass 33, count 0 2006.211.08:45:27.83#ibcon#read 3, iclass 33, count 0 2006.211.08:45:27.83#ibcon#about to read 4, iclass 33, count 0 2006.211.08:45:27.83#ibcon#read 4, iclass 33, count 0 2006.211.08:45:27.83#ibcon#about to read 5, iclass 33, count 0 2006.211.08:45:27.83#ibcon#read 5, iclass 33, count 0 2006.211.08:45:27.83#ibcon#about to read 6, iclass 33, count 0 2006.211.08:45:27.83#ibcon#read 6, iclass 33, count 0 2006.211.08:45:27.83#ibcon#end of sib2, iclass 33, count 0 2006.211.08:45:27.83#ibcon#*after write, iclass 33, count 0 2006.211.08:45:27.83#ibcon#*before return 0, iclass 33, count 0 2006.211.08:45:27.83#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:45:27.83#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.211.08:45:27.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.211.08:45:27.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.211.08:45:27.83$vc4f8/vblo=1,632.99 2006.211.08:45:27.83#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.211.08:45:27.83#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.211.08:45:27.83#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:27.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:45:27.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:45:27.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:45:27.83#ibcon#enter wrdev, iclass 35, count 0 2006.211.08:45:27.83#ibcon#first serial, iclass 35, count 0 2006.211.08:45:27.83#ibcon#enter sib2, iclass 35, count 0 2006.211.08:45:27.83#ibcon#flushed, iclass 35, count 0 2006.211.08:45:27.83#ibcon#about to write, iclass 35, count 0 2006.211.08:45:27.83#ibcon#wrote, iclass 35, count 0 2006.211.08:45:27.83#ibcon#about to read 3, iclass 35, count 0 2006.211.08:45:27.85#ibcon#read 3, iclass 35, count 0 2006.211.08:45:27.85#ibcon#about to read 4, iclass 35, count 0 2006.211.08:45:27.85#ibcon#read 4, iclass 35, count 0 2006.211.08:45:27.85#ibcon#about to read 5, iclass 35, count 0 2006.211.08:45:27.85#ibcon#read 5, iclass 35, count 0 2006.211.08:45:27.85#ibcon#about to read 6, iclass 35, count 0 2006.211.08:45:27.85#ibcon#read 6, iclass 35, count 0 2006.211.08:45:27.85#ibcon#end of sib2, iclass 35, count 0 2006.211.08:45:27.85#ibcon#*mode == 0, iclass 35, count 0 2006.211.08:45:27.85#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.211.08:45:27.85#ibcon#[28=FRQ=01,632.99\r\n] 2006.211.08:45:27.85#ibcon#*before write, iclass 35, count 0 2006.211.08:45:27.85#ibcon#enter sib2, iclass 35, count 0 2006.211.08:45:27.85#ibcon#flushed, iclass 35, count 0 2006.211.08:45:27.85#ibcon#about to write, iclass 35, count 0 2006.211.08:45:27.85#ibcon#wrote, iclass 35, count 0 2006.211.08:45:27.85#ibcon#about to read 3, iclass 35, count 0 2006.211.08:45:27.89#ibcon#read 3, iclass 35, count 0 2006.211.08:45:27.89#ibcon#about to read 4, iclass 35, count 0 2006.211.08:45:27.89#ibcon#read 4, iclass 35, count 0 2006.211.08:45:27.89#ibcon#about to read 5, iclass 35, count 0 2006.211.08:45:27.89#ibcon#read 5, iclass 35, count 0 2006.211.08:45:27.89#ibcon#about to read 6, iclass 35, count 0 2006.211.08:45:27.89#ibcon#read 6, iclass 35, count 0 2006.211.08:45:27.89#ibcon#end of sib2, iclass 35, count 0 2006.211.08:45:27.89#ibcon#*after write, iclass 35, count 0 2006.211.08:45:27.89#ibcon#*before return 0, iclass 35, count 0 2006.211.08:45:27.89#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:45:27.89#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.211.08:45:27.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.211.08:45:27.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.211.08:45:27.89$vc4f8/vb=1,4 2006.211.08:45:27.89#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.211.08:45:27.89#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.211.08:45:27.89#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:27.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:45:27.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:45:27.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:45:27.89#ibcon#enter wrdev, iclass 37, count 2 2006.211.08:45:27.89#ibcon#first serial, iclass 37, count 2 2006.211.08:45:27.89#ibcon#enter sib2, iclass 37, count 2 2006.211.08:45:27.89#ibcon#flushed, iclass 37, count 2 2006.211.08:45:27.89#ibcon#about to write, iclass 37, count 2 2006.211.08:45:27.89#ibcon#wrote, iclass 37, count 2 2006.211.08:45:27.89#ibcon#about to read 3, iclass 37, count 2 2006.211.08:45:27.91#ibcon#read 3, iclass 37, count 2 2006.211.08:45:27.91#ibcon#about to read 4, iclass 37, count 2 2006.211.08:45:27.91#ibcon#read 4, iclass 37, count 2 2006.211.08:45:27.91#ibcon#about to read 5, iclass 37, count 2 2006.211.08:45:27.91#ibcon#read 5, iclass 37, count 2 2006.211.08:45:27.91#ibcon#about to read 6, iclass 37, count 2 2006.211.08:45:27.91#ibcon#read 6, iclass 37, count 2 2006.211.08:45:27.91#ibcon#end of sib2, iclass 37, count 2 2006.211.08:45:27.91#ibcon#*mode == 0, iclass 37, count 2 2006.211.08:45:27.91#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.211.08:45:27.91#ibcon#[27=AT01-04\r\n] 2006.211.08:45:27.91#ibcon#*before write, iclass 37, count 2 2006.211.08:45:27.91#ibcon#enter sib2, iclass 37, count 2 2006.211.08:45:27.91#ibcon#flushed, iclass 37, count 2 2006.211.08:45:27.91#ibcon#about to write, iclass 37, count 2 2006.211.08:45:27.91#ibcon#wrote, iclass 37, count 2 2006.211.08:45:27.91#ibcon#about to read 3, iclass 37, count 2 2006.211.08:45:27.94#ibcon#read 3, iclass 37, count 2 2006.211.08:45:27.94#ibcon#about to read 4, iclass 37, count 2 2006.211.08:45:27.94#ibcon#read 4, iclass 37, count 2 2006.211.08:45:27.94#ibcon#about to read 5, iclass 37, count 2 2006.211.08:45:27.94#ibcon#read 5, iclass 37, count 2 2006.211.08:45:27.94#ibcon#about to read 6, iclass 37, count 2 2006.211.08:45:27.94#ibcon#read 6, iclass 37, count 2 2006.211.08:45:27.94#ibcon#end of sib2, iclass 37, count 2 2006.211.08:45:27.94#ibcon#*after write, iclass 37, count 2 2006.211.08:45:27.94#ibcon#*before return 0, iclass 37, count 2 2006.211.08:45:27.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:45:27.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.211.08:45:27.94#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.211.08:45:27.94#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:27.94#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:45:28.06#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:45:28.06#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:45:28.06#ibcon#enter wrdev, iclass 37, count 0 2006.211.08:45:28.06#ibcon#first serial, iclass 37, count 0 2006.211.08:45:28.06#ibcon#enter sib2, iclass 37, count 0 2006.211.08:45:28.06#ibcon#flushed, iclass 37, count 0 2006.211.08:45:28.06#ibcon#about to write, iclass 37, count 0 2006.211.08:45:28.06#ibcon#wrote, iclass 37, count 0 2006.211.08:45:28.06#ibcon#about to read 3, iclass 37, count 0 2006.211.08:45:28.08#ibcon#read 3, iclass 37, count 0 2006.211.08:45:28.08#ibcon#about to read 4, iclass 37, count 0 2006.211.08:45:28.08#ibcon#read 4, iclass 37, count 0 2006.211.08:45:28.08#ibcon#about to read 5, iclass 37, count 0 2006.211.08:45:28.08#ibcon#read 5, iclass 37, count 0 2006.211.08:45:28.08#ibcon#about to read 6, iclass 37, count 0 2006.211.08:45:28.08#ibcon#read 6, iclass 37, count 0 2006.211.08:45:28.08#ibcon#end of sib2, iclass 37, count 0 2006.211.08:45:28.08#ibcon#*mode == 0, iclass 37, count 0 2006.211.08:45:28.08#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.211.08:45:28.08#ibcon#[27=USB\r\n] 2006.211.08:45:28.08#ibcon#*before write, iclass 37, count 0 2006.211.08:45:28.08#ibcon#enter sib2, iclass 37, count 0 2006.211.08:45:28.08#ibcon#flushed, iclass 37, count 0 2006.211.08:45:28.08#ibcon#about to write, iclass 37, count 0 2006.211.08:45:28.08#ibcon#wrote, iclass 37, count 0 2006.211.08:45:28.08#ibcon#about to read 3, iclass 37, count 0 2006.211.08:45:28.11#ibcon#read 3, iclass 37, count 0 2006.211.08:45:28.11#ibcon#about to read 4, iclass 37, count 0 2006.211.08:45:28.11#ibcon#read 4, iclass 37, count 0 2006.211.08:45:28.11#ibcon#about to read 5, iclass 37, count 0 2006.211.08:45:28.11#ibcon#read 5, iclass 37, count 0 2006.211.08:45:28.11#ibcon#about to read 6, iclass 37, count 0 2006.211.08:45:28.11#ibcon#read 6, iclass 37, count 0 2006.211.08:45:28.11#ibcon#end of sib2, iclass 37, count 0 2006.211.08:45:28.11#ibcon#*after write, iclass 37, count 0 2006.211.08:45:28.11#ibcon#*before return 0, iclass 37, count 0 2006.211.08:45:28.11#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:45:28.11#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.211.08:45:28.11#ibcon#about to clear, iclass 37 cls_cnt 0 2006.211.08:45:28.11#ibcon#cleared, iclass 37 cls_cnt 0 2006.211.08:45:28.11$vc4f8/vblo=2,640.99 2006.211.08:45:28.11#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.211.08:45:28.11#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.211.08:45:28.11#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:28.11#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:45:28.11#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:45:28.11#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:45:28.11#ibcon#enter wrdev, iclass 39, count 0 2006.211.08:45:28.11#ibcon#first serial, iclass 39, count 0 2006.211.08:45:28.11#ibcon#enter sib2, iclass 39, count 0 2006.211.08:45:28.11#ibcon#flushed, iclass 39, count 0 2006.211.08:45:28.11#ibcon#about to write, iclass 39, count 0 2006.211.08:45:28.11#ibcon#wrote, iclass 39, count 0 2006.211.08:45:28.11#ibcon#about to read 3, iclass 39, count 0 2006.211.08:45:28.13#ibcon#read 3, iclass 39, count 0 2006.211.08:45:28.13#ibcon#about to read 4, iclass 39, count 0 2006.211.08:45:28.13#ibcon#read 4, iclass 39, count 0 2006.211.08:45:28.13#ibcon#about to read 5, iclass 39, count 0 2006.211.08:45:28.13#ibcon#read 5, iclass 39, count 0 2006.211.08:45:28.13#ibcon#about to read 6, iclass 39, count 0 2006.211.08:45:28.13#ibcon#read 6, iclass 39, count 0 2006.211.08:45:28.13#ibcon#end of sib2, iclass 39, count 0 2006.211.08:45:28.13#ibcon#*mode == 0, iclass 39, count 0 2006.211.08:45:28.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.211.08:45:28.13#ibcon#[28=FRQ=02,640.99\r\n] 2006.211.08:45:28.13#ibcon#*before write, iclass 39, count 0 2006.211.08:45:28.13#ibcon#enter sib2, iclass 39, count 0 2006.211.08:45:28.13#ibcon#flushed, iclass 39, count 0 2006.211.08:45:28.13#ibcon#about to write, iclass 39, count 0 2006.211.08:45:28.13#ibcon#wrote, iclass 39, count 0 2006.211.08:45:28.13#ibcon#about to read 3, iclass 39, count 0 2006.211.08:45:28.17#ibcon#read 3, iclass 39, count 0 2006.211.08:45:28.17#ibcon#about to read 4, iclass 39, count 0 2006.211.08:45:28.17#ibcon#read 4, iclass 39, count 0 2006.211.08:45:28.17#ibcon#about to read 5, iclass 39, count 0 2006.211.08:45:28.17#ibcon#read 5, iclass 39, count 0 2006.211.08:45:28.17#ibcon#about to read 6, iclass 39, count 0 2006.211.08:45:28.17#ibcon#read 6, iclass 39, count 0 2006.211.08:45:28.17#ibcon#end of sib2, iclass 39, count 0 2006.211.08:45:28.17#ibcon#*after write, iclass 39, count 0 2006.211.08:45:28.17#ibcon#*before return 0, iclass 39, count 0 2006.211.08:45:28.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:45:28.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.211.08:45:28.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.211.08:45:28.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.211.08:45:28.17$vc4f8/vb=2,4 2006.211.08:45:28.17#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.211.08:45:28.17#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.211.08:45:28.17#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:28.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:45:28.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:45:28.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:45:28.23#ibcon#enter wrdev, iclass 3, count 2 2006.211.08:45:28.23#ibcon#first serial, iclass 3, count 2 2006.211.08:45:28.23#ibcon#enter sib2, iclass 3, count 2 2006.211.08:45:28.23#ibcon#flushed, iclass 3, count 2 2006.211.08:45:28.23#ibcon#about to write, iclass 3, count 2 2006.211.08:45:28.23#ibcon#wrote, iclass 3, count 2 2006.211.08:45:28.23#ibcon#about to read 3, iclass 3, count 2 2006.211.08:45:28.25#ibcon#read 3, iclass 3, count 2 2006.211.08:45:28.25#ibcon#about to read 4, iclass 3, count 2 2006.211.08:45:28.25#ibcon#read 4, iclass 3, count 2 2006.211.08:45:28.25#ibcon#about to read 5, iclass 3, count 2 2006.211.08:45:28.25#ibcon#read 5, iclass 3, count 2 2006.211.08:45:28.25#ibcon#about to read 6, iclass 3, count 2 2006.211.08:45:28.25#ibcon#read 6, iclass 3, count 2 2006.211.08:45:28.25#ibcon#end of sib2, iclass 3, count 2 2006.211.08:45:28.25#ibcon#*mode == 0, iclass 3, count 2 2006.211.08:45:28.25#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.211.08:45:28.25#ibcon#[27=AT02-04\r\n] 2006.211.08:45:28.25#ibcon#*before write, iclass 3, count 2 2006.211.08:45:28.25#ibcon#enter sib2, iclass 3, count 2 2006.211.08:45:28.25#ibcon#flushed, iclass 3, count 2 2006.211.08:45:28.25#ibcon#about to write, iclass 3, count 2 2006.211.08:45:28.25#ibcon#wrote, iclass 3, count 2 2006.211.08:45:28.25#ibcon#about to read 3, iclass 3, count 2 2006.211.08:45:28.28#ibcon#read 3, iclass 3, count 2 2006.211.08:45:28.28#ibcon#about to read 4, iclass 3, count 2 2006.211.08:45:28.28#ibcon#read 4, iclass 3, count 2 2006.211.08:45:28.28#ibcon#about to read 5, iclass 3, count 2 2006.211.08:45:28.28#ibcon#read 5, iclass 3, count 2 2006.211.08:45:28.28#ibcon#about to read 6, iclass 3, count 2 2006.211.08:45:28.28#ibcon#read 6, iclass 3, count 2 2006.211.08:45:28.28#ibcon#end of sib2, iclass 3, count 2 2006.211.08:45:28.28#ibcon#*after write, iclass 3, count 2 2006.211.08:45:28.28#ibcon#*before return 0, iclass 3, count 2 2006.211.08:45:28.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:45:28.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.211.08:45:28.28#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.211.08:45:28.28#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:28.28#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:45:28.40#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:45:28.40#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:45:28.40#ibcon#enter wrdev, iclass 3, count 0 2006.211.08:45:28.40#ibcon#first serial, iclass 3, count 0 2006.211.08:45:28.40#ibcon#enter sib2, iclass 3, count 0 2006.211.08:45:28.40#ibcon#flushed, iclass 3, count 0 2006.211.08:45:28.40#ibcon#about to write, iclass 3, count 0 2006.211.08:45:28.40#ibcon#wrote, iclass 3, count 0 2006.211.08:45:28.40#ibcon#about to read 3, iclass 3, count 0 2006.211.08:45:28.42#ibcon#read 3, iclass 3, count 0 2006.211.08:45:28.42#ibcon#about to read 4, iclass 3, count 0 2006.211.08:45:28.42#ibcon#read 4, iclass 3, count 0 2006.211.08:45:28.42#ibcon#about to read 5, iclass 3, count 0 2006.211.08:45:28.42#ibcon#read 5, iclass 3, count 0 2006.211.08:45:28.42#ibcon#about to read 6, iclass 3, count 0 2006.211.08:45:28.42#ibcon#read 6, iclass 3, count 0 2006.211.08:45:28.42#ibcon#end of sib2, iclass 3, count 0 2006.211.08:45:28.42#ibcon#*mode == 0, iclass 3, count 0 2006.211.08:45:28.42#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.211.08:45:28.42#ibcon#[27=USB\r\n] 2006.211.08:45:28.42#ibcon#*before write, iclass 3, count 0 2006.211.08:45:28.42#ibcon#enter sib2, iclass 3, count 0 2006.211.08:45:28.42#ibcon#flushed, iclass 3, count 0 2006.211.08:45:28.42#ibcon#about to write, iclass 3, count 0 2006.211.08:45:28.42#ibcon#wrote, iclass 3, count 0 2006.211.08:45:28.42#ibcon#about to read 3, iclass 3, count 0 2006.211.08:45:28.45#ibcon#read 3, iclass 3, count 0 2006.211.08:45:28.45#ibcon#about to read 4, iclass 3, count 0 2006.211.08:45:28.45#ibcon#read 4, iclass 3, count 0 2006.211.08:45:28.45#ibcon#about to read 5, iclass 3, count 0 2006.211.08:45:28.45#ibcon#read 5, iclass 3, count 0 2006.211.08:45:28.45#ibcon#about to read 6, iclass 3, count 0 2006.211.08:45:28.45#ibcon#read 6, iclass 3, count 0 2006.211.08:45:28.45#ibcon#end of sib2, iclass 3, count 0 2006.211.08:45:28.45#ibcon#*after write, iclass 3, count 0 2006.211.08:45:28.45#ibcon#*before return 0, iclass 3, count 0 2006.211.08:45:28.45#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:45:28.45#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.211.08:45:28.45#ibcon#about to clear, iclass 3 cls_cnt 0 2006.211.08:45:28.45#ibcon#cleared, iclass 3 cls_cnt 0 2006.211.08:45:28.45$vc4f8/vblo=3,656.99 2006.211.08:45:28.45#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.211.08:45:28.45#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.211.08:45:28.45#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:28.45#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:45:28.45#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:45:28.45#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:45:28.45#ibcon#enter wrdev, iclass 5, count 0 2006.211.08:45:28.45#ibcon#first serial, iclass 5, count 0 2006.211.08:45:28.45#ibcon#enter sib2, iclass 5, count 0 2006.211.08:45:28.45#ibcon#flushed, iclass 5, count 0 2006.211.08:45:28.45#ibcon#about to write, iclass 5, count 0 2006.211.08:45:28.45#ibcon#wrote, iclass 5, count 0 2006.211.08:45:28.45#ibcon#about to read 3, iclass 5, count 0 2006.211.08:45:28.47#ibcon#read 3, iclass 5, count 0 2006.211.08:45:28.47#ibcon#about to read 4, iclass 5, count 0 2006.211.08:45:28.47#ibcon#read 4, iclass 5, count 0 2006.211.08:45:28.47#ibcon#about to read 5, iclass 5, count 0 2006.211.08:45:28.47#ibcon#read 5, iclass 5, count 0 2006.211.08:45:28.47#ibcon#about to read 6, iclass 5, count 0 2006.211.08:45:28.47#ibcon#read 6, iclass 5, count 0 2006.211.08:45:28.47#ibcon#end of sib2, iclass 5, count 0 2006.211.08:45:28.47#ibcon#*mode == 0, iclass 5, count 0 2006.211.08:45:28.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.211.08:45:28.47#ibcon#[28=FRQ=03,656.99\r\n] 2006.211.08:45:28.47#ibcon#*before write, iclass 5, count 0 2006.211.08:45:28.47#ibcon#enter sib2, iclass 5, count 0 2006.211.08:45:28.47#ibcon#flushed, iclass 5, count 0 2006.211.08:45:28.47#ibcon#about to write, iclass 5, count 0 2006.211.08:45:28.47#ibcon#wrote, iclass 5, count 0 2006.211.08:45:28.47#ibcon#about to read 3, iclass 5, count 0 2006.211.08:45:28.51#ibcon#read 3, iclass 5, count 0 2006.211.08:45:28.51#ibcon#about to read 4, iclass 5, count 0 2006.211.08:45:28.51#ibcon#read 4, iclass 5, count 0 2006.211.08:45:28.51#ibcon#about to read 5, iclass 5, count 0 2006.211.08:45:28.51#ibcon#read 5, iclass 5, count 0 2006.211.08:45:28.51#ibcon#about to read 6, iclass 5, count 0 2006.211.08:45:28.51#ibcon#read 6, iclass 5, count 0 2006.211.08:45:28.51#ibcon#end of sib2, iclass 5, count 0 2006.211.08:45:28.51#ibcon#*after write, iclass 5, count 0 2006.211.08:45:28.51#ibcon#*before return 0, iclass 5, count 0 2006.211.08:45:28.51#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:45:28.51#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.211.08:45:28.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.211.08:45:28.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.211.08:45:28.51$vc4f8/vb=3,3 2006.211.08:45:28.51#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.211.08:45:28.51#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.211.08:45:28.51#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:28.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:45:28.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:45:28.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:45:28.57#ibcon#enter wrdev, iclass 7, count 2 2006.211.08:45:28.57#ibcon#first serial, iclass 7, count 2 2006.211.08:45:28.57#ibcon#enter sib2, iclass 7, count 2 2006.211.08:45:28.57#ibcon#flushed, iclass 7, count 2 2006.211.08:45:28.57#ibcon#about to write, iclass 7, count 2 2006.211.08:45:28.57#ibcon#wrote, iclass 7, count 2 2006.211.08:45:28.57#ibcon#about to read 3, iclass 7, count 2 2006.211.08:45:28.59#ibcon#read 3, iclass 7, count 2 2006.211.08:45:28.59#ibcon#about to read 4, iclass 7, count 2 2006.211.08:45:28.59#ibcon#read 4, iclass 7, count 2 2006.211.08:45:28.59#ibcon#about to read 5, iclass 7, count 2 2006.211.08:45:28.59#ibcon#read 5, iclass 7, count 2 2006.211.08:45:28.59#ibcon#about to read 6, iclass 7, count 2 2006.211.08:45:28.59#ibcon#read 6, iclass 7, count 2 2006.211.08:45:28.59#ibcon#end of sib2, iclass 7, count 2 2006.211.08:45:28.59#ibcon#*mode == 0, iclass 7, count 2 2006.211.08:45:28.59#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.211.08:45:28.59#ibcon#[27=AT03-03\r\n] 2006.211.08:45:28.59#ibcon#*before write, iclass 7, count 2 2006.211.08:45:28.59#ibcon#enter sib2, iclass 7, count 2 2006.211.08:45:28.59#ibcon#flushed, iclass 7, count 2 2006.211.08:45:28.59#ibcon#about to write, iclass 7, count 2 2006.211.08:45:28.59#ibcon#wrote, iclass 7, count 2 2006.211.08:45:28.59#ibcon#about to read 3, iclass 7, count 2 2006.211.08:45:28.62#ibcon#read 3, iclass 7, count 2 2006.211.08:45:28.62#ibcon#about to read 4, iclass 7, count 2 2006.211.08:45:28.62#ibcon#read 4, iclass 7, count 2 2006.211.08:45:28.62#ibcon#about to read 5, iclass 7, count 2 2006.211.08:45:28.62#ibcon#read 5, iclass 7, count 2 2006.211.08:45:28.62#ibcon#about to read 6, iclass 7, count 2 2006.211.08:45:28.62#ibcon#read 6, iclass 7, count 2 2006.211.08:45:28.62#ibcon#end of sib2, iclass 7, count 2 2006.211.08:45:28.62#ibcon#*after write, iclass 7, count 2 2006.211.08:45:28.62#ibcon#*before return 0, iclass 7, count 2 2006.211.08:45:28.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:45:28.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.211.08:45:28.62#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.211.08:45:28.62#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:28.62#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:45:28.66#abcon#<5=/04 3.5 6.4 27.35 921005.9\r\n> 2006.211.08:45:28.68#abcon#{5=INTERFACE CLEAR} 2006.211.08:45:28.74#abcon#[5=S1D000X0/0*\r\n] 2006.211.08:45:28.74#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:45:28.74#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:45:28.74#ibcon#enter wrdev, iclass 7, count 0 2006.211.08:45:28.74#ibcon#first serial, iclass 7, count 0 2006.211.08:45:28.74#ibcon#enter sib2, iclass 7, count 0 2006.211.08:45:28.74#ibcon#flushed, iclass 7, count 0 2006.211.08:45:28.74#ibcon#about to write, iclass 7, count 0 2006.211.08:45:28.74#ibcon#wrote, iclass 7, count 0 2006.211.08:45:28.74#ibcon#about to read 3, iclass 7, count 0 2006.211.08:45:28.76#ibcon#read 3, iclass 7, count 0 2006.211.08:45:28.76#ibcon#about to read 4, iclass 7, count 0 2006.211.08:45:28.76#ibcon#read 4, iclass 7, count 0 2006.211.08:45:28.76#ibcon#about to read 5, iclass 7, count 0 2006.211.08:45:28.76#ibcon#read 5, iclass 7, count 0 2006.211.08:45:28.76#ibcon#about to read 6, iclass 7, count 0 2006.211.08:45:28.76#ibcon#read 6, iclass 7, count 0 2006.211.08:45:28.76#ibcon#end of sib2, iclass 7, count 0 2006.211.08:45:28.76#ibcon#*mode == 0, iclass 7, count 0 2006.211.08:45:28.76#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.211.08:45:28.76#ibcon#[27=USB\r\n] 2006.211.08:45:28.76#ibcon#*before write, iclass 7, count 0 2006.211.08:45:28.76#ibcon#enter sib2, iclass 7, count 0 2006.211.08:45:28.76#ibcon#flushed, iclass 7, count 0 2006.211.08:45:28.76#ibcon#about to write, iclass 7, count 0 2006.211.08:45:28.76#ibcon#wrote, iclass 7, count 0 2006.211.08:45:28.76#ibcon#about to read 3, iclass 7, count 0 2006.211.08:45:28.79#ibcon#read 3, iclass 7, count 0 2006.211.08:45:28.79#ibcon#about to read 4, iclass 7, count 0 2006.211.08:45:28.79#ibcon#read 4, iclass 7, count 0 2006.211.08:45:28.79#ibcon#about to read 5, iclass 7, count 0 2006.211.08:45:28.79#ibcon#read 5, iclass 7, count 0 2006.211.08:45:28.79#ibcon#about to read 6, iclass 7, count 0 2006.211.08:45:28.79#ibcon#read 6, iclass 7, count 0 2006.211.08:45:28.79#ibcon#end of sib2, iclass 7, count 0 2006.211.08:45:28.79#ibcon#*after write, iclass 7, count 0 2006.211.08:45:28.79#ibcon#*before return 0, iclass 7, count 0 2006.211.08:45:28.79#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:45:28.79#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.211.08:45:28.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.211.08:45:28.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.211.08:45:28.79$vc4f8/vblo=4,712.99 2006.211.08:45:28.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.211.08:45:28.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.211.08:45:28.79#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:28.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:45:28.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:45:28.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:45:28.79#ibcon#enter wrdev, iclass 15, count 0 2006.211.08:45:28.79#ibcon#first serial, iclass 15, count 0 2006.211.08:45:28.79#ibcon#enter sib2, iclass 15, count 0 2006.211.08:45:28.79#ibcon#flushed, iclass 15, count 0 2006.211.08:45:28.79#ibcon#about to write, iclass 15, count 0 2006.211.08:45:28.79#ibcon#wrote, iclass 15, count 0 2006.211.08:45:28.79#ibcon#about to read 3, iclass 15, count 0 2006.211.08:45:28.81#ibcon#read 3, iclass 15, count 0 2006.211.08:45:28.81#ibcon#about to read 4, iclass 15, count 0 2006.211.08:45:28.81#ibcon#read 4, iclass 15, count 0 2006.211.08:45:28.81#ibcon#about to read 5, iclass 15, count 0 2006.211.08:45:28.81#ibcon#read 5, iclass 15, count 0 2006.211.08:45:28.81#ibcon#about to read 6, iclass 15, count 0 2006.211.08:45:28.81#ibcon#read 6, iclass 15, count 0 2006.211.08:45:28.81#ibcon#end of sib2, iclass 15, count 0 2006.211.08:45:28.81#ibcon#*mode == 0, iclass 15, count 0 2006.211.08:45:28.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.211.08:45:28.81#ibcon#[28=FRQ=04,712.99\r\n] 2006.211.08:45:28.81#ibcon#*before write, iclass 15, count 0 2006.211.08:45:28.81#ibcon#enter sib2, iclass 15, count 0 2006.211.08:45:28.81#ibcon#flushed, iclass 15, count 0 2006.211.08:45:28.81#ibcon#about to write, iclass 15, count 0 2006.211.08:45:28.81#ibcon#wrote, iclass 15, count 0 2006.211.08:45:28.81#ibcon#about to read 3, iclass 15, count 0 2006.211.08:45:28.85#ibcon#read 3, iclass 15, count 0 2006.211.08:45:28.85#ibcon#about to read 4, iclass 15, count 0 2006.211.08:45:28.85#ibcon#read 4, iclass 15, count 0 2006.211.08:45:28.85#ibcon#about to read 5, iclass 15, count 0 2006.211.08:45:28.85#ibcon#read 5, iclass 15, count 0 2006.211.08:45:28.85#ibcon#about to read 6, iclass 15, count 0 2006.211.08:45:28.85#ibcon#read 6, iclass 15, count 0 2006.211.08:45:28.85#ibcon#end of sib2, iclass 15, count 0 2006.211.08:45:28.85#ibcon#*after write, iclass 15, count 0 2006.211.08:45:28.85#ibcon#*before return 0, iclass 15, count 0 2006.211.08:45:28.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:45:28.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.211.08:45:28.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.211.08:45:28.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.211.08:45:28.85$vc4f8/vb=4,3 2006.211.08:45:28.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.211.08:45:28.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.211.08:45:28.85#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:28.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:45:28.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:45:28.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:45:28.91#ibcon#enter wrdev, iclass 17, count 2 2006.211.08:45:28.91#ibcon#first serial, iclass 17, count 2 2006.211.08:45:28.91#ibcon#enter sib2, iclass 17, count 2 2006.211.08:45:28.91#ibcon#flushed, iclass 17, count 2 2006.211.08:45:28.91#ibcon#about to write, iclass 17, count 2 2006.211.08:45:28.91#ibcon#wrote, iclass 17, count 2 2006.211.08:45:28.91#ibcon#about to read 3, iclass 17, count 2 2006.211.08:45:28.93#ibcon#read 3, iclass 17, count 2 2006.211.08:45:28.93#ibcon#about to read 4, iclass 17, count 2 2006.211.08:45:28.93#ibcon#read 4, iclass 17, count 2 2006.211.08:45:28.93#ibcon#about to read 5, iclass 17, count 2 2006.211.08:45:28.93#ibcon#read 5, iclass 17, count 2 2006.211.08:45:28.93#ibcon#about to read 6, iclass 17, count 2 2006.211.08:45:28.93#ibcon#read 6, iclass 17, count 2 2006.211.08:45:28.93#ibcon#end of sib2, iclass 17, count 2 2006.211.08:45:28.93#ibcon#*mode == 0, iclass 17, count 2 2006.211.08:45:28.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.211.08:45:28.93#ibcon#[27=AT04-03\r\n] 2006.211.08:45:28.93#ibcon#*before write, iclass 17, count 2 2006.211.08:45:28.93#ibcon#enter sib2, iclass 17, count 2 2006.211.08:45:28.93#ibcon#flushed, iclass 17, count 2 2006.211.08:45:28.93#ibcon#about to write, iclass 17, count 2 2006.211.08:45:28.93#ibcon#wrote, iclass 17, count 2 2006.211.08:45:28.93#ibcon#about to read 3, iclass 17, count 2 2006.211.08:45:28.96#ibcon#read 3, iclass 17, count 2 2006.211.08:45:28.96#ibcon#about to read 4, iclass 17, count 2 2006.211.08:45:28.96#ibcon#read 4, iclass 17, count 2 2006.211.08:45:28.96#ibcon#about to read 5, iclass 17, count 2 2006.211.08:45:28.96#ibcon#read 5, iclass 17, count 2 2006.211.08:45:28.96#ibcon#about to read 6, iclass 17, count 2 2006.211.08:45:28.96#ibcon#read 6, iclass 17, count 2 2006.211.08:45:28.96#ibcon#end of sib2, iclass 17, count 2 2006.211.08:45:28.96#ibcon#*after write, iclass 17, count 2 2006.211.08:45:28.96#ibcon#*before return 0, iclass 17, count 2 2006.211.08:45:28.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:45:28.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.211.08:45:28.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.211.08:45:28.96#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:28.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:45:29.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:45:29.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:45:29.08#ibcon#enter wrdev, iclass 17, count 0 2006.211.08:45:29.08#ibcon#first serial, iclass 17, count 0 2006.211.08:45:29.08#ibcon#enter sib2, iclass 17, count 0 2006.211.08:45:29.08#ibcon#flushed, iclass 17, count 0 2006.211.08:45:29.08#ibcon#about to write, iclass 17, count 0 2006.211.08:45:29.08#ibcon#wrote, iclass 17, count 0 2006.211.08:45:29.08#ibcon#about to read 3, iclass 17, count 0 2006.211.08:45:29.10#ibcon#read 3, iclass 17, count 0 2006.211.08:45:29.10#ibcon#about to read 4, iclass 17, count 0 2006.211.08:45:29.10#ibcon#read 4, iclass 17, count 0 2006.211.08:45:29.10#ibcon#about to read 5, iclass 17, count 0 2006.211.08:45:29.10#ibcon#read 5, iclass 17, count 0 2006.211.08:45:29.10#ibcon#about to read 6, iclass 17, count 0 2006.211.08:45:29.10#ibcon#read 6, iclass 17, count 0 2006.211.08:45:29.10#ibcon#end of sib2, iclass 17, count 0 2006.211.08:45:29.10#ibcon#*mode == 0, iclass 17, count 0 2006.211.08:45:29.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.211.08:45:29.10#ibcon#[27=USB\r\n] 2006.211.08:45:29.10#ibcon#*before write, iclass 17, count 0 2006.211.08:45:29.10#ibcon#enter sib2, iclass 17, count 0 2006.211.08:45:29.10#ibcon#flushed, iclass 17, count 0 2006.211.08:45:29.10#ibcon#about to write, iclass 17, count 0 2006.211.08:45:29.10#ibcon#wrote, iclass 17, count 0 2006.211.08:45:29.10#ibcon#about to read 3, iclass 17, count 0 2006.211.08:45:29.13#ibcon#read 3, iclass 17, count 0 2006.211.08:45:29.13#ibcon#about to read 4, iclass 17, count 0 2006.211.08:45:29.13#ibcon#read 4, iclass 17, count 0 2006.211.08:45:29.13#ibcon#about to read 5, iclass 17, count 0 2006.211.08:45:29.13#ibcon#read 5, iclass 17, count 0 2006.211.08:45:29.13#ibcon#about to read 6, iclass 17, count 0 2006.211.08:45:29.13#ibcon#read 6, iclass 17, count 0 2006.211.08:45:29.13#ibcon#end of sib2, iclass 17, count 0 2006.211.08:45:29.13#ibcon#*after write, iclass 17, count 0 2006.211.08:45:29.13#ibcon#*before return 0, iclass 17, count 0 2006.211.08:45:29.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:45:29.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.211.08:45:29.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.211.08:45:29.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.211.08:45:29.13$vc4f8/vblo=5,744.99 2006.211.08:45:29.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.211.08:45:29.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.211.08:45:29.13#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:29.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:45:29.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:45:29.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:45:29.13#ibcon#enter wrdev, iclass 19, count 0 2006.211.08:45:29.13#ibcon#first serial, iclass 19, count 0 2006.211.08:45:29.13#ibcon#enter sib2, iclass 19, count 0 2006.211.08:45:29.13#ibcon#flushed, iclass 19, count 0 2006.211.08:45:29.13#ibcon#about to write, iclass 19, count 0 2006.211.08:45:29.13#ibcon#wrote, iclass 19, count 0 2006.211.08:45:29.13#ibcon#about to read 3, iclass 19, count 0 2006.211.08:45:29.15#ibcon#read 3, iclass 19, count 0 2006.211.08:45:29.15#ibcon#about to read 4, iclass 19, count 0 2006.211.08:45:29.15#ibcon#read 4, iclass 19, count 0 2006.211.08:45:29.15#ibcon#about to read 5, iclass 19, count 0 2006.211.08:45:29.15#ibcon#read 5, iclass 19, count 0 2006.211.08:45:29.15#ibcon#about to read 6, iclass 19, count 0 2006.211.08:45:29.15#ibcon#read 6, iclass 19, count 0 2006.211.08:45:29.15#ibcon#end of sib2, iclass 19, count 0 2006.211.08:45:29.15#ibcon#*mode == 0, iclass 19, count 0 2006.211.08:45:29.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.211.08:45:29.15#ibcon#[28=FRQ=05,744.99\r\n] 2006.211.08:45:29.15#ibcon#*before write, iclass 19, count 0 2006.211.08:45:29.15#ibcon#enter sib2, iclass 19, count 0 2006.211.08:45:29.15#ibcon#flushed, iclass 19, count 0 2006.211.08:45:29.15#ibcon#about to write, iclass 19, count 0 2006.211.08:45:29.15#ibcon#wrote, iclass 19, count 0 2006.211.08:45:29.15#ibcon#about to read 3, iclass 19, count 0 2006.211.08:45:29.19#ibcon#read 3, iclass 19, count 0 2006.211.08:45:29.19#ibcon#about to read 4, iclass 19, count 0 2006.211.08:45:29.19#ibcon#read 4, iclass 19, count 0 2006.211.08:45:29.19#ibcon#about to read 5, iclass 19, count 0 2006.211.08:45:29.19#ibcon#read 5, iclass 19, count 0 2006.211.08:45:29.19#ibcon#about to read 6, iclass 19, count 0 2006.211.08:45:29.19#ibcon#read 6, iclass 19, count 0 2006.211.08:45:29.19#ibcon#end of sib2, iclass 19, count 0 2006.211.08:45:29.19#ibcon#*after write, iclass 19, count 0 2006.211.08:45:29.19#ibcon#*before return 0, iclass 19, count 0 2006.211.08:45:29.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:45:29.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.211.08:45:29.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.211.08:45:29.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.211.08:45:29.19$vc4f8/vb=5,3 2006.211.08:45:29.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.211.08:45:29.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.211.08:45:29.19#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:29.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:45:29.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:45:29.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:45:29.25#ibcon#enter wrdev, iclass 21, count 2 2006.211.08:45:29.25#ibcon#first serial, iclass 21, count 2 2006.211.08:45:29.25#ibcon#enter sib2, iclass 21, count 2 2006.211.08:45:29.25#ibcon#flushed, iclass 21, count 2 2006.211.08:45:29.25#ibcon#about to write, iclass 21, count 2 2006.211.08:45:29.25#ibcon#wrote, iclass 21, count 2 2006.211.08:45:29.25#ibcon#about to read 3, iclass 21, count 2 2006.211.08:45:29.27#ibcon#read 3, iclass 21, count 2 2006.211.08:45:29.27#ibcon#about to read 4, iclass 21, count 2 2006.211.08:45:29.27#ibcon#read 4, iclass 21, count 2 2006.211.08:45:29.27#ibcon#about to read 5, iclass 21, count 2 2006.211.08:45:29.27#ibcon#read 5, iclass 21, count 2 2006.211.08:45:29.27#ibcon#about to read 6, iclass 21, count 2 2006.211.08:45:29.27#ibcon#read 6, iclass 21, count 2 2006.211.08:45:29.27#ibcon#end of sib2, iclass 21, count 2 2006.211.08:45:29.27#ibcon#*mode == 0, iclass 21, count 2 2006.211.08:45:29.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.211.08:45:29.27#ibcon#[27=AT05-03\r\n] 2006.211.08:45:29.27#ibcon#*before write, iclass 21, count 2 2006.211.08:45:29.27#ibcon#enter sib2, iclass 21, count 2 2006.211.08:45:29.27#ibcon#flushed, iclass 21, count 2 2006.211.08:45:29.27#ibcon#about to write, iclass 21, count 2 2006.211.08:45:29.27#ibcon#wrote, iclass 21, count 2 2006.211.08:45:29.27#ibcon#about to read 3, iclass 21, count 2 2006.211.08:45:29.30#ibcon#read 3, iclass 21, count 2 2006.211.08:45:29.30#ibcon#about to read 4, iclass 21, count 2 2006.211.08:45:29.30#ibcon#read 4, iclass 21, count 2 2006.211.08:45:29.30#ibcon#about to read 5, iclass 21, count 2 2006.211.08:45:29.30#ibcon#read 5, iclass 21, count 2 2006.211.08:45:29.30#ibcon#about to read 6, iclass 21, count 2 2006.211.08:45:29.30#ibcon#read 6, iclass 21, count 2 2006.211.08:45:29.30#ibcon#end of sib2, iclass 21, count 2 2006.211.08:45:29.30#ibcon#*after write, iclass 21, count 2 2006.211.08:45:29.30#ibcon#*before return 0, iclass 21, count 2 2006.211.08:45:29.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:45:29.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.211.08:45:29.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.211.08:45:29.30#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:29.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:45:29.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:45:29.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:45:29.42#ibcon#enter wrdev, iclass 21, count 0 2006.211.08:45:29.42#ibcon#first serial, iclass 21, count 0 2006.211.08:45:29.42#ibcon#enter sib2, iclass 21, count 0 2006.211.08:45:29.42#ibcon#flushed, iclass 21, count 0 2006.211.08:45:29.42#ibcon#about to write, iclass 21, count 0 2006.211.08:45:29.42#ibcon#wrote, iclass 21, count 0 2006.211.08:45:29.42#ibcon#about to read 3, iclass 21, count 0 2006.211.08:45:29.44#ibcon#read 3, iclass 21, count 0 2006.211.08:45:29.44#ibcon#about to read 4, iclass 21, count 0 2006.211.08:45:29.44#ibcon#read 4, iclass 21, count 0 2006.211.08:45:29.44#ibcon#about to read 5, iclass 21, count 0 2006.211.08:45:29.44#ibcon#read 5, iclass 21, count 0 2006.211.08:45:29.44#ibcon#about to read 6, iclass 21, count 0 2006.211.08:45:29.44#ibcon#read 6, iclass 21, count 0 2006.211.08:45:29.44#ibcon#end of sib2, iclass 21, count 0 2006.211.08:45:29.44#ibcon#*mode == 0, iclass 21, count 0 2006.211.08:45:29.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.211.08:45:29.44#ibcon#[27=USB\r\n] 2006.211.08:45:29.44#ibcon#*before write, iclass 21, count 0 2006.211.08:45:29.44#ibcon#enter sib2, iclass 21, count 0 2006.211.08:45:29.44#ibcon#flushed, iclass 21, count 0 2006.211.08:45:29.44#ibcon#about to write, iclass 21, count 0 2006.211.08:45:29.44#ibcon#wrote, iclass 21, count 0 2006.211.08:45:29.44#ibcon#about to read 3, iclass 21, count 0 2006.211.08:45:29.47#ibcon#read 3, iclass 21, count 0 2006.211.08:45:29.47#ibcon#about to read 4, iclass 21, count 0 2006.211.08:45:29.47#ibcon#read 4, iclass 21, count 0 2006.211.08:45:29.47#ibcon#about to read 5, iclass 21, count 0 2006.211.08:45:29.47#ibcon#read 5, iclass 21, count 0 2006.211.08:45:29.47#ibcon#about to read 6, iclass 21, count 0 2006.211.08:45:29.47#ibcon#read 6, iclass 21, count 0 2006.211.08:45:29.47#ibcon#end of sib2, iclass 21, count 0 2006.211.08:45:29.47#ibcon#*after write, iclass 21, count 0 2006.211.08:45:29.47#ibcon#*before return 0, iclass 21, count 0 2006.211.08:45:29.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:45:29.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.211.08:45:29.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.211.08:45:29.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.211.08:45:29.47$vc4f8/vblo=6,752.99 2006.211.08:45:29.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.211.08:45:29.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.211.08:45:29.47#ibcon#ireg 17 cls_cnt 0 2006.211.08:45:29.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:45:29.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:45:29.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:45:29.47#ibcon#enter wrdev, iclass 23, count 0 2006.211.08:45:29.47#ibcon#first serial, iclass 23, count 0 2006.211.08:45:29.47#ibcon#enter sib2, iclass 23, count 0 2006.211.08:45:29.47#ibcon#flushed, iclass 23, count 0 2006.211.08:45:29.47#ibcon#about to write, iclass 23, count 0 2006.211.08:45:29.47#ibcon#wrote, iclass 23, count 0 2006.211.08:45:29.47#ibcon#about to read 3, iclass 23, count 0 2006.211.08:45:29.49#ibcon#read 3, iclass 23, count 0 2006.211.08:45:29.49#ibcon#about to read 4, iclass 23, count 0 2006.211.08:45:29.49#ibcon#read 4, iclass 23, count 0 2006.211.08:45:29.49#ibcon#about to read 5, iclass 23, count 0 2006.211.08:45:29.49#ibcon#read 5, iclass 23, count 0 2006.211.08:45:29.49#ibcon#about to read 6, iclass 23, count 0 2006.211.08:45:29.49#ibcon#read 6, iclass 23, count 0 2006.211.08:45:29.49#ibcon#end of sib2, iclass 23, count 0 2006.211.08:45:29.49#ibcon#*mode == 0, iclass 23, count 0 2006.211.08:45:29.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.211.08:45:29.49#ibcon#[28=FRQ=06,752.99\r\n] 2006.211.08:45:29.49#ibcon#*before write, iclass 23, count 0 2006.211.08:45:29.49#ibcon#enter sib2, iclass 23, count 0 2006.211.08:45:29.49#ibcon#flushed, iclass 23, count 0 2006.211.08:45:29.49#ibcon#about to write, iclass 23, count 0 2006.211.08:45:29.49#ibcon#wrote, iclass 23, count 0 2006.211.08:45:29.49#ibcon#about to read 3, iclass 23, count 0 2006.211.08:45:29.53#ibcon#read 3, iclass 23, count 0 2006.211.08:45:29.53#ibcon#about to read 4, iclass 23, count 0 2006.211.08:45:29.53#ibcon#read 4, iclass 23, count 0 2006.211.08:45:29.53#ibcon#about to read 5, iclass 23, count 0 2006.211.08:45:29.53#ibcon#read 5, iclass 23, count 0 2006.211.08:45:29.53#ibcon#about to read 6, iclass 23, count 0 2006.211.08:45:29.53#ibcon#read 6, iclass 23, count 0 2006.211.08:45:29.53#ibcon#end of sib2, iclass 23, count 0 2006.211.08:45:29.53#ibcon#*after write, iclass 23, count 0 2006.211.08:45:29.53#ibcon#*before return 0, iclass 23, count 0 2006.211.08:45:29.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:45:29.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.211.08:45:29.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.211.08:45:29.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.211.08:45:29.53$vc4f8/vb=6,3 2006.211.08:45:29.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.211.08:45:29.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.211.08:45:29.53#ibcon#ireg 11 cls_cnt 2 2006.211.08:45:29.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:45:29.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:45:29.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:45:29.59#ibcon#enter wrdev, iclass 25, count 2 2006.211.08:45:29.59#ibcon#first serial, iclass 25, count 2 2006.211.08:45:29.59#ibcon#enter sib2, iclass 25, count 2 2006.211.08:45:29.59#ibcon#flushed, iclass 25, count 2 2006.211.08:45:29.59#ibcon#about to write, iclass 25, count 2 2006.211.08:45:29.59#ibcon#wrote, iclass 25, count 2 2006.211.08:45:29.59#ibcon#about to read 3, iclass 25, count 2 2006.211.08:45:29.61#ibcon#read 3, iclass 25, count 2 2006.211.08:45:29.61#ibcon#about to read 4, iclass 25, count 2 2006.211.08:45:29.61#ibcon#read 4, iclass 25, count 2 2006.211.08:45:29.61#ibcon#about to read 5, iclass 25, count 2 2006.211.08:45:29.61#ibcon#read 5, iclass 25, count 2 2006.211.08:45:29.61#ibcon#about to read 6, iclass 25, count 2 2006.211.08:45:29.61#ibcon#read 6, iclass 25, count 2 2006.211.08:45:29.61#ibcon#end of sib2, iclass 25, count 2 2006.211.08:45:29.61#ibcon#*mode == 0, iclass 25, count 2 2006.211.08:45:29.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.211.08:45:29.61#ibcon#[27=AT06-03\r\n] 2006.211.08:45:29.61#ibcon#*before write, iclass 25, count 2 2006.211.08:45:29.61#ibcon#enter sib2, iclass 25, count 2 2006.211.08:45:29.61#ibcon#flushed, iclass 25, count 2 2006.211.08:45:29.61#ibcon#about to write, iclass 25, count 2 2006.211.08:45:29.61#ibcon#wrote, iclass 25, count 2 2006.211.08:45:29.61#ibcon#about to read 3, iclass 25, count 2 2006.211.08:45:29.64#ibcon#read 3, iclass 25, count 2 2006.211.08:45:29.64#ibcon#about to read 4, iclass 25, count 2 2006.211.08:45:29.64#ibcon#read 4, iclass 25, count 2 2006.211.08:45:29.64#ibcon#about to read 5, iclass 25, count 2 2006.211.08:45:29.64#ibcon#read 5, iclass 25, count 2 2006.211.08:45:29.64#ibcon#about to read 6, iclass 25, count 2 2006.211.08:45:29.64#ibcon#read 6, iclass 25, count 2 2006.211.08:45:29.64#ibcon#end of sib2, iclass 25, count 2 2006.211.08:45:29.64#ibcon#*after write, iclass 25, count 2 2006.211.08:45:29.64#ibcon#*before return 0, iclass 25, count 2 2006.211.08:45:29.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:45:29.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.211.08:45:29.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.211.08:45:29.64#ibcon#ireg 7 cls_cnt 0 2006.211.08:45:29.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:45:29.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:45:29.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:45:29.76#ibcon#enter wrdev, iclass 25, count 0 2006.211.08:45:29.76#ibcon#first serial, iclass 25, count 0 2006.211.08:45:29.76#ibcon#enter sib2, iclass 25, count 0 2006.211.08:45:29.76#ibcon#flushed, iclass 25, count 0 2006.211.08:45:29.76#ibcon#about to write, iclass 25, count 0 2006.211.08:45:29.76#ibcon#wrote, iclass 25, count 0 2006.211.08:45:29.76#ibcon#about to read 3, iclass 25, count 0 2006.211.08:45:29.78#ibcon#read 3, iclass 25, count 0 2006.211.08:45:29.78#ibcon#about to read 4, iclass 25, count 0 2006.211.08:45:29.78#ibcon#read 4, iclass 25, count 0 2006.211.08:45:29.78#ibcon#about to read 5, iclass 25, count 0 2006.211.08:45:29.78#ibcon#read 5, iclass 25, count 0 2006.211.08:45:29.78#ibcon#about to read 6, iclass 25, count 0 2006.211.08:45:29.78#ibcon#read 6, iclass 25, count 0 2006.211.08:45:29.78#ibcon#end of sib2, iclass 25, count 0 2006.211.08:45:29.78#ibcon#*mode == 0, iclass 25, count 0 2006.211.08:45:29.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.211.08:45:29.78#ibcon#[27=USB\r\n] 2006.211.08:45:29.78#ibcon#*before write, iclass 25, count 0 2006.211.08:45:29.78#ibcon#enter sib2, iclass 25, count 0 2006.211.08:45:29.78#ibcon#flushed, iclass 25, count 0 2006.211.08:45:29.78#ibcon#about to write, iclass 25, count 0 2006.211.08:45:29.78#ibcon#wrote, iclass 25, count 0 2006.211.08:45:29.78#ibcon#about to read 3, iclass 25, count 0 2006.211.08:45:29.81#ibcon#read 3, iclass 25, count 0 2006.211.08:45:29.81#ibcon#about to read 4, iclass 25, count 0 2006.211.08:45:29.81#ibcon#read 4, iclass 25, count 0 2006.211.08:45:29.81#ibcon#about to read 5, iclass 25, count 0 2006.211.08:45:29.81#ibcon#read 5, iclass 25, count 0 2006.211.08:45:29.81#ibcon#about to read 6, iclass 25, count 0 2006.211.08:45:29.81#ibcon#read 6, iclass 25, count 0 2006.211.08:45:29.81#ibcon#end of sib2, iclass 25, count 0 2006.211.08:45:29.81#ibcon#*after write, iclass 25, count 0 2006.211.08:45:29.81#ibcon#*before return 0, iclass 25, count 0 2006.211.08:45:29.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:45:29.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.211.08:45:29.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.211.08:45:29.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.211.08:45:29.81$vc4f8/vabw=wide 2006.211.08:45:29.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.211.08:45:29.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.211.08:45:29.81#ibcon#ireg 8 cls_cnt 0 2006.211.08:45:29.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:45:29.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:45:29.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:45:29.81#ibcon#enter wrdev, iclass 27, count 0 2006.211.08:45:29.81#ibcon#first serial, iclass 27, count 0 2006.211.08:45:29.81#ibcon#enter sib2, iclass 27, count 0 2006.211.08:45:29.81#ibcon#flushed, iclass 27, count 0 2006.211.08:45:29.81#ibcon#about to write, iclass 27, count 0 2006.211.08:45:29.81#ibcon#wrote, iclass 27, count 0 2006.211.08:45:29.81#ibcon#about to read 3, iclass 27, count 0 2006.211.08:45:29.83#ibcon#read 3, iclass 27, count 0 2006.211.08:45:29.83#ibcon#about to read 4, iclass 27, count 0 2006.211.08:45:29.83#ibcon#read 4, iclass 27, count 0 2006.211.08:45:29.83#ibcon#about to read 5, iclass 27, count 0 2006.211.08:45:29.83#ibcon#read 5, iclass 27, count 0 2006.211.08:45:29.83#ibcon#about to read 6, iclass 27, count 0 2006.211.08:45:29.83#ibcon#read 6, iclass 27, count 0 2006.211.08:45:29.83#ibcon#end of sib2, iclass 27, count 0 2006.211.08:45:29.83#ibcon#*mode == 0, iclass 27, count 0 2006.211.08:45:29.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.211.08:45:29.83#ibcon#[25=BW32\r\n] 2006.211.08:45:29.83#ibcon#*before write, iclass 27, count 0 2006.211.08:45:29.83#ibcon#enter sib2, iclass 27, count 0 2006.211.08:45:29.83#ibcon#flushed, iclass 27, count 0 2006.211.08:45:29.83#ibcon#about to write, iclass 27, count 0 2006.211.08:45:29.83#ibcon#wrote, iclass 27, count 0 2006.211.08:45:29.83#ibcon#about to read 3, iclass 27, count 0 2006.211.08:45:29.86#ibcon#read 3, iclass 27, count 0 2006.211.08:45:29.86#ibcon#about to read 4, iclass 27, count 0 2006.211.08:45:29.86#ibcon#read 4, iclass 27, count 0 2006.211.08:45:29.86#ibcon#about to read 5, iclass 27, count 0 2006.211.08:45:29.86#ibcon#read 5, iclass 27, count 0 2006.211.08:45:29.86#ibcon#about to read 6, iclass 27, count 0 2006.211.08:45:29.86#ibcon#read 6, iclass 27, count 0 2006.211.08:45:29.86#ibcon#end of sib2, iclass 27, count 0 2006.211.08:45:29.86#ibcon#*after write, iclass 27, count 0 2006.211.08:45:29.86#ibcon#*before return 0, iclass 27, count 0 2006.211.08:45:29.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:45:29.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.211.08:45:29.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.211.08:45:29.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.211.08:45:29.86$vc4f8/vbbw=wide 2006.211.08:45:29.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.211.08:45:29.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.211.08:45:29.86#ibcon#ireg 8 cls_cnt 0 2006.211.08:45:29.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:45:29.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:45:29.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:45:29.93#ibcon#enter wrdev, iclass 29, count 0 2006.211.08:45:29.93#ibcon#first serial, iclass 29, count 0 2006.211.08:45:29.93#ibcon#enter sib2, iclass 29, count 0 2006.211.08:45:29.93#ibcon#flushed, iclass 29, count 0 2006.211.08:45:29.93#ibcon#about to write, iclass 29, count 0 2006.211.08:45:29.93#ibcon#wrote, iclass 29, count 0 2006.211.08:45:29.93#ibcon#about to read 3, iclass 29, count 0 2006.211.08:45:29.95#ibcon#read 3, iclass 29, count 0 2006.211.08:45:29.95#ibcon#about to read 4, iclass 29, count 0 2006.211.08:45:29.95#ibcon#read 4, iclass 29, count 0 2006.211.08:45:29.95#ibcon#about to read 5, iclass 29, count 0 2006.211.08:45:29.95#ibcon#read 5, iclass 29, count 0 2006.211.08:45:29.95#ibcon#about to read 6, iclass 29, count 0 2006.211.08:45:29.95#ibcon#read 6, iclass 29, count 0 2006.211.08:45:29.95#ibcon#end of sib2, iclass 29, count 0 2006.211.08:45:29.95#ibcon#*mode == 0, iclass 29, count 0 2006.211.08:45:29.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.211.08:45:29.95#ibcon#[27=BW32\r\n] 2006.211.08:45:29.95#ibcon#*before write, iclass 29, count 0 2006.211.08:45:29.95#ibcon#enter sib2, iclass 29, count 0 2006.211.08:45:29.95#ibcon#flushed, iclass 29, count 0 2006.211.08:45:29.95#ibcon#about to write, iclass 29, count 0 2006.211.08:45:29.95#ibcon#wrote, iclass 29, count 0 2006.211.08:45:29.95#ibcon#about to read 3, iclass 29, count 0 2006.211.08:45:29.98#ibcon#read 3, iclass 29, count 0 2006.211.08:45:29.98#ibcon#about to read 4, iclass 29, count 0 2006.211.08:45:29.98#ibcon#read 4, iclass 29, count 0 2006.211.08:45:29.98#ibcon#about to read 5, iclass 29, count 0 2006.211.08:45:29.98#ibcon#read 5, iclass 29, count 0 2006.211.08:45:29.98#ibcon#about to read 6, iclass 29, count 0 2006.211.08:45:29.98#ibcon#read 6, iclass 29, count 0 2006.211.08:45:29.98#ibcon#end of sib2, iclass 29, count 0 2006.211.08:45:29.98#ibcon#*after write, iclass 29, count 0 2006.211.08:45:29.98#ibcon#*before return 0, iclass 29, count 0 2006.211.08:45:29.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:45:29.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.211.08:45:29.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.211.08:45:29.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.211.08:45:29.98$4f8m12a/ifd4f 2006.211.08:45:29.98&ifd4f/lo= 2006.211.08:45:29.98&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:45:29.98&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:45:29.98&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:45:29.98&ifd4f/patch= 2006.211.08:45:29.98&ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:45:29.98&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:45:29.98&ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:45:29.98$ifd4f/lo= 2006.211.08:45:29.98$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.211.08:45:29.98$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.211.08:45:29.98$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.211.08:45:29.98$ifd4f/patch= 2006.211.08:45:29.98$ifd4f/patch=lo1,a1,a2,a3,a4 2006.211.08:45:29.98$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.211.08:45:29.98$ifd4f/patch=lo3,a5,a6,a7,a8 2006.211.08:45:29.98$4f8m12a/"form=m,16.000,1:2 2006.211.08:45:29.98$4f8m12a/"tpicd 2006.211.08:45:29.98$4f8m12a/echo=off 2006.211.08:45:29.98$4f8m12a/xlog=off 2006.211.08:45:29.98:!2006.211.20:26:50 2006.211.08:45:29.98&proc_library/" k06210 tsukub32 ts 2006.211.08:45:29.98&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.211.08:45:29.98&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.211.08:45:29.98&sched_initi/startcheck 2006.211.08:45:29.98&startcheck/sy=check_fsrun.pl & 2006.211.08:45:29.98&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.211.08:46:21.49;sy=run setcl offset & 2006.211.08:46:21.58#setcl#time/60881442,0,2006,211,20,26,33.52,$$$$$$$$$$,0.063,4201200 2006.211.08:46:21.60#setcl#model/old,1153459626,18074110,60858692,-0.364,101.533,rate,0,sync,18074395,22275595 2006.211.20:26:33.60#setcl#model/new,1153459626,22275310,60881442,-0.364,101.533,rate,0 2006.211.20:26:36.78;wx 2006.211.20:26:36.78/wx/27.35,1005.9,92 2006.211.20:26:50.00:preob 2006.211.20:26:50.00&preob/onsource 2006.211.20:26:50.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.211.20:26:50.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.211.20:26:50.14/onsource/SLEWING 2006.211.20:26:50.14:!2006.211.20:27:00 2006.211.20:27:00.00:data_valid=on 2006.211.20:27:00.00:midob 2006.211.20:27:00.00&midob/onsource 2006.211.20:27:00.00&midob/wx 2006.211.20:27:00.00&midob/cable 2006.211.20:27:00.00&midob/va 2006.211.20:27:00.00&midob/valo 2006.211.20:27:00.00&midob/vb 2006.211.20:27:00.00&midob/vblo 2006.211.20:27:00.00&midob/vabw 2006.211.20:27:00.00&midob/vbbw 2006.211.20:27:00.00&midob/"form 2006.211.20:27:00.00&midob/xfe 2006.211.20:27:00.00&midob/ifatt 2006.211.20:27:00.00&midob/clockoff 2006.211.20:27:00.00&midob/sy=logmail 2006.211.20:27:00.00&midob/"sy=run setcl adapt & 2006.211.20:27:01.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.211.20:27:01.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.211.20:27:01.14/onsource/SLEWING 2006.211.20:27:01.14/wx/27.35,1005.9,92 2006.211.20:27:01.33/cable/+6.4279E-03 2006.211.20:27:02.42/va/01,08,usb,yes,30,32 2006.211.20:27:02.42/va/02,07,usb,yes,30,32 2006.211.20:27:02.42/va/03,06,usb,yes,32,32 2006.211.20:27:02.42/va/04,07,usb,yes,31,34 2006.211.20:27:02.42/va/05,07,usb,yes,34,36 2006.211.20:27:02.42/va/06,06,usb,yes,33,33 2006.211.20:27:02.42/va/07,06,usb,yes,34,33 2006.211.20:27:02.42/va/08,07,usb,yes,32,31 2006.211.20:27:02.65/valo/01,532.99,yes,locked 2006.211.20:27:02.65/valo/02,572.99,yes,locked 2006.211.20:27:02.65/valo/03,672.99,yes,locked 2006.211.20:27:02.65/valo/04,832.99,yes,locked 2006.211.20:27:02.65/valo/05,652.99,yes,locked 2006.211.20:27:02.65/valo/06,772.99,yes,locked 2006.211.20:27:02.65/valo/07,832.99,yes,locked 2006.211.20:27:02.65/valo/08,852.99,yes,locked 2006.211.20:27:03.74/vb/01,04,usb,yes,29,28 2006.211.20:27:03.74/vb/02,04,usb,yes,31,32 2006.211.20:27:03.74/vb/03,03,usb,yes,34,39 2006.211.20:27:03.74/vb/04,03,usb,yes,35,35 2006.211.20:27:03.74/vb/05,03,usb,yes,34,38 2006.211.20:27:03.74/vb/06,03,usb,yes,34,37 2006.211.20:27:03.74/vb/07,04,usb,yes,30,30 2006.211.20:27:03.74/vb/08,03,usb,yes,34,38 2006.211.20:27:03.98/vblo/01,632.99,yes,locked 2006.211.20:27:03.98/vblo/02,640.99,yes,locked 2006.211.20:27:03.98/vblo/03,656.99,yes,locked 2006.211.20:27:03.98/vblo/04,712.99,yes,locked 2006.211.20:27:03.98/vblo/05,744.99,yes,locked 2006.211.20:27:03.98/vblo/06,752.99,yes,locked 2006.211.20:27:03.98/vblo/07,734.99,yes,locked 2006.211.20:27:03.98/vblo/08,744.99,yes,locked 2006.211.20:27:04.13/vabw/8 2006.211.20:27:04.28/vbbw/8 2006.211.20:27:04.37/xfe/off,on,13.2 2006.211.20:27:04.74/ifatt/23,28,28,28 2006.211.20:27:04.74&clockoff/"gps-fmout=1p 2006.211.20:27:04.74&clockoff/fmout-gps=1p 2006.211.20:27:05.03/fmout-gps/S +4.60E-07 2006.211.20:27:05.09:!2006.211.20:57:00 2006.211.20:27:39.86;sy=run setcl offset & 2006.211.20:27:39.94#setcl#time/60888078,0,2006,211,20,56,23.88,$$$$$$$$$$,0.018,172400 2006.211.20:27:39.94#setcl#model/old,1153459626,22275310,60881442,-0.364,101.533,rate,0,sync,22275595,22447995 2006.211.20:56:23.94#setcl#model/new,1153459626,22447710,60888078,-0.364,101.533,rate,0 2006.211.20:56:25.50;wx 2006.211.20:56:25.50/wx/27.34,1005.9,93 2006.211.20:56:38.13#trakl#Source acquired 2006.211.20:56:38.13#flagr#flagr/antenna,acquired 2006.211.20:57:00.00:data_valid=off 2006.211.20:57:00.00:postob 2006.211.20:57:00.00&postob/cable 2006.211.20:57:00.00&postob/wx 2006.211.20:57:00.00&postob/clockoff 2006.211.20:57:00.23/cable/+6.4284E-03 2006.211.20:57:00.23/wx/27.34,1005.8,92 2006.211.20:57:00.29/fmout-gps/S +4.61E-07 2006.211.20:57:00.29:sched_end 2006.211.20:57:00.29&sched_end/stopcheck 2006.211.20:57:00.29&stopcheck/sy=killall check_fsrun.pl 2006.211.20:57:00.29&stopcheck/" sy=killall chmem.sh 2006.211.20:57:00.36:source=idle 2006.211.20:57:01.13#flagr#flagr/antenna,new-source 2006.211.20:57:01.13:stow 2006.211.20:57:01.13&stow/source=idle 2006.211.20:57:01.13&stow/"this is stow command. 2006.211.20:57:01.13&stow/antenna=m3 2006.211.20:57:05.01:!+10m 2006.211.20:59:46.41;sy=run setcl offset & 2006.211.20:59:46.50#setcl#time/60908334,0,2006,211,21,07,03.43,186393.844,0.056,43699 2006.211.20:59:46.51#setcl#model/old,1153459626,22447710,60888078,-0.364,101.533,rate,0,sync,22447995,22491694 2006.211.21:07:03.50#setcl#model/new,1153459626,22491409,60908334,-0.364,101.533,rate,0 2006.211.21:07:04.24;wx 2006.211.21:07:04.24/wx/27.34,1005.8,93 2006.211.21:07:05.02:standby 2006.211.21:07:05.02&standby/"this is standby command. 2006.211.21:07:05.02&standby/antenna=m0 2006.211.21:07:06.01:"checkk5hdd 2006.211.21:07:06.01:sy=cp /usr2/log/u06211ts.log /usr2/log_backup/ 2006.211.21:07:06.07:*end of schedule 2006.211.21:08:06.09#fmset#Formatter time reset. 2006.211.21:08:06.28#setcl#time/60914605,0,2006,209,06,39,29.15,$$$$$$$$$$,0.017,-22491699 2006.211.21:08:06.28#setcl#model/old,1153459626,22491409,60908334,-0.364,101.533,rate,0,sync,22491694,-5 2006.209.06:39:29.30#setcl#model/new,1153459626,-290,60914605,-0.364,101.533,rate,0 2006.209.06:40:26.39;sy=run setcl computer & 2006.209.06:40:26.47#setcl#time/60920331,0,2006,209,06,40,26.41,0.000,0.016,0 2006.209.06:40:26.48#setcl#model/old,1153459626,-290,60914605,-0.364,101.533,rate,0,sync,-5,-5 2006.209.06:40:26.53#setcl#model/new,1153459626,-290,0,-0.364,101.533,computer,0 2006.209.06:40:29.55;terminate 2006.209.06:40:29.55:*boss terminated 2006.209.07:15:20.20;Log Opened: Mark IV Field System Version 9.7.7 2006.209.07:15:20.20;location,TSUKUB32,-140.09,36.10,61.0 2006.209.07:15:20.20;horizon1,0.,5.,360. 2006.209.07:15:20.20;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.209.07:15:20.20;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.209.07:15:20.20;drivev11,330,270,no 2006.209.07:15:20.20;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.209.07:15:20.20;drivev13,15.000,268,10.000,10.000,10.000 2006.209.07:15:20.20;drivev21,330,270,no 2006.209.07:15:20.21;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.209.07:15:20.21;drivev23,15.000,268,10.000,10.000,10.000 2006.209.07:15:20.21;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.209.07:15:20.21;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.209.07:15:20.21;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.209.07:15:20.21;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.209.07:15:20.21;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.209.07:15:20.21;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.209.07:15:20.21;time,-0.364,101.533,rate 2006.209.07:15:20.21;flagr,200 2006.209.07:15:20.21:" K06210 2006 TSUKUB32 T Ts 2006.209.07:15:20.21:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.209.07:15:20.21:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.209.07:15:20.21:" 108 TSUKUB32 14 17400 2006.209.07:15:20.21:" drudg version 050216 compiled under FS 9.7.07 2006.209.07:15:20.21:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.209.07:15:20.21:exper_initi 2006.209.07:15:20.21&exper_initi/proc_library 2006.209.07:15:20.21&exper_initi/sched_initi 2006.209.07:15:20.21:!2006.210.06:29:50 2006.209.07:15:20.21&proc_library/" k06210 tsukub32 ts 2006.209.07:15:20.21&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.209.07:15:20.21&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.209.07:15:20.21&sched_initi/startcheck 2006.209.07:15:20.21&startcheck/sy=check_fsrun.pl & 2006.209.07:15:20.21&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.209.07:15:39.60;cable 2006.209.07:15:39.77/cable/+6.4271E-03 2006.209.07:16:33.27;cablelong 2006.209.07:16:33.50/cablelong/+6.9941E-03 2006.209.07:16:36.39;cablediff 2006.209.07:16:36.39/cablediff/567.0e-6,+ 2006.209.07:17:26.45;cable 2006.209.07:17:26.67/cable/+6.4279E-03 2006.209.07:18:11.82;wx 2006.209.07:18:11.82/wx/27.32,1005.5,93 2006.209.07:18:19.36;"Sky is cloudy. 2006.209.07:18:29.32;clockoff 2006.209.07:18:29.32&clockoff/"gps-fmout=1p 2006.209.07:18:29.32&clockoff/fmout-gps=1p 2006.209.07:18:30.07/fmout-gps/S +4.58E-07 2006.209.07:18:31.55;xfe 2006.209.07:18:31.64/xfe/off,on,12.5 2006.210.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.210.06:29:50.02:!2006.210.07:19:50 2006.210.07:16:59.16?ERROR st -97 Trouble decoding pressure data 2006.210.07:16:59.16#wxget#09 1.1 3.9 30.61 731006.2 2006.210.07:19:50.00:unstow 2006.210.07:19:50.00&unstow/antenna=e 2006.210.07:19:50.00&unstow/!+10s 2006.210.07:19:50.00&unstow/antenna=m2 2006.210.07:20:02.01:scan_name=210-0730,k06210,60 2006.210.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.210.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.210.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.210.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.210.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.210.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.210.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.210.07:20:04.14:ready_k5 2006.210.07:20:04.14&ready_k5/obsinfo=st 2006.210.07:20:04.14&ready_k5/autoobs=1 2006.210.07:20:04.14&ready_k5/autoobs=2 2006.210.07:20:04.14&ready_k5/autoobs=3 2006.210.07:20:04.14&ready_k5/autoobs=4 2006.210.07:20:04.14&ready_k5/obsinfo 2006.210.07:20:04.14#flagr#flagr/antenna,new-source 2006.210.07:20:04.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.210.07:20:07.33/autoobs//k5ts1/ autoobs started! 2006.210.07:20:10.43/autoobs//k5ts2/ autoobs started! 2006.210.07:20:13.54/autoobs//k5ts3/ autoobs started! 2006.210.07:20:16.63/autoobs//k5ts4/ autoobs started! 2006.210.07:20:16.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:20:16.66:4f8m12a=1 2006.210.07:20:16.66&4f8m12a/xlog=on 2006.210.07:20:16.66&4f8m12a/echo=on 2006.210.07:20:16.66&4f8m12a/pcalon 2006.210.07:20:16.66&4f8m12a/"tpicd=stop 2006.210.07:20:16.66&4f8m12a/vc4f8 2006.210.07:20:16.66&4f8m12a/ifd4f 2006.210.07:20:16.66&4f8m12a/"form=m,16.000,1:2 2006.210.07:20:16.66&4f8m12a/"tpicd 2006.210.07:20:16.66&4f8m12a/echo=off 2006.210.07:20:16.66&4f8m12a/xlog=off 2006.210.07:20:16.66$4f8m12a/echo=on 2006.210.07:20:16.66$4f8m12a/pcalon 2006.210.07:20:16.66&pcalon/"no phase cal control is implemented here 2006.210.07:20:16.66$pcalon/"no phase cal control is implemented here 2006.210.07:20:16.66$4f8m12a/"tpicd=stop 2006.210.07:20:16.66$4f8m12a/vc4f8 2006.210.07:20:16.66&vc4f8/valo=1,532.99 2006.210.07:20:16.67&vc4f8/va=1,8 2006.210.07:20:16.67&vc4f8/valo=2,572.99 2006.210.07:20:16.67&vc4f8/va=2,7 2006.210.07:20:16.67&vc4f8/valo=3,672.99 2006.210.07:20:16.67&vc4f8/va=3,6 2006.210.07:20:16.67&vc4f8/valo=4,832.99 2006.210.07:20:16.67&vc4f8/va=4,7 2006.210.07:20:16.67&vc4f8/valo=5,652.99 2006.210.07:20:16.67&vc4f8/va=5,7 2006.210.07:20:16.67&vc4f8/valo=6,772.99 2006.210.07:20:16.67&vc4f8/va=6,6 2006.210.07:20:16.67&vc4f8/valo=7,832.99 2006.210.07:20:16.67&vc4f8/va=7,6 2006.210.07:20:16.67&vc4f8/valo=8,852.99 2006.210.07:20:16.67&vc4f8/va=8,7 2006.210.07:20:16.67&vc4f8/vblo=1,632.99 2006.210.07:20:16.67&vc4f8/vb=1,4 2006.210.07:20:16.67&vc4f8/vblo=2,640.99 2006.210.07:20:16.67&vc4f8/vb=2,4 2006.210.07:20:16.67&vc4f8/vblo=3,656.99 2006.210.07:20:16.67&vc4f8/vb=3,3 2006.210.07:20:16.67&vc4f8/vblo=4,712.99 2006.210.07:20:16.67&vc4f8/vb=4,3 2006.210.07:20:16.67&vc4f8/vblo=5,744.99 2006.210.07:20:16.67&vc4f8/vb=5,3 2006.210.07:20:16.67&vc4f8/vblo=6,752.99 2006.210.07:20:16.67&vc4f8/vb=6,3 2006.210.07:20:16.67&vc4f8/vabw=wide 2006.210.07:20:16.67&vc4f8/vbbw=wide 2006.210.07:20:16.67$vc4f8/valo=1,532.99 2006.210.07:20:16.67#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:20:16.67#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:20:16.67#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:16.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:16.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:16.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:16.67#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:20:16.67#ibcon#first serial, iclass 16, count 0 2006.210.07:20:16.67#ibcon#enter sib2, iclass 16, count 0 2006.210.07:20:16.67#ibcon#flushed, iclass 16, count 0 2006.210.07:20:16.67#ibcon#about to write, iclass 16, count 0 2006.210.07:20:16.67#ibcon#wrote, iclass 16, count 0 2006.210.07:20:16.67#ibcon#about to read 3, iclass 16, count 0 2006.210.07:20:16.68#ibcon#read 3, iclass 16, count 0 2006.210.07:20:16.68#ibcon#about to read 4, iclass 16, count 0 2006.210.07:20:16.68#ibcon#read 4, iclass 16, count 0 2006.210.07:20:16.68#ibcon#about to read 5, iclass 16, count 0 2006.210.07:20:16.68#ibcon#read 5, iclass 16, count 0 2006.210.07:20:16.68#ibcon#about to read 6, iclass 16, count 0 2006.210.07:20:16.68#ibcon#read 6, iclass 16, count 0 2006.210.07:20:16.68#ibcon#end of sib2, iclass 16, count 0 2006.210.07:20:16.68#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:20:16.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:20:16.68#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:20:16.68#ibcon#*before write, iclass 16, count 0 2006.210.07:20:16.68#ibcon#enter sib2, iclass 16, count 0 2006.210.07:20:16.68#ibcon#flushed, iclass 16, count 0 2006.210.07:20:16.68#ibcon#about to write, iclass 16, count 0 2006.210.07:20:16.68#ibcon#wrote, iclass 16, count 0 2006.210.07:20:16.68#ibcon#about to read 3, iclass 16, count 0 2006.210.07:20:16.74#ibcon#read 3, iclass 16, count 0 2006.210.07:20:16.74#ibcon#about to read 4, iclass 16, count 0 2006.210.07:20:16.74#ibcon#read 4, iclass 16, count 0 2006.210.07:20:16.74#ibcon#about to read 5, iclass 16, count 0 2006.210.07:20:16.74#ibcon#read 5, iclass 16, count 0 2006.210.07:20:16.74#ibcon#about to read 6, iclass 16, count 0 2006.210.07:20:16.74#ibcon#read 6, iclass 16, count 0 2006.210.07:20:16.74#ibcon#end of sib2, iclass 16, count 0 2006.210.07:20:16.74#ibcon#*after write, iclass 16, count 0 2006.210.07:20:16.74#ibcon#*before return 0, iclass 16, count 0 2006.210.07:20:16.74#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:16.74#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:16.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:20:16.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:20:16.74$vc4f8/va=1,8 2006.210.07:20:16.74#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:20:16.74#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:20:16.74#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:16.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:16.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:16.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:16.74#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:20:16.74#ibcon#first serial, iclass 18, count 2 2006.210.07:20:16.74#ibcon#enter sib2, iclass 18, count 2 2006.210.07:20:16.74#ibcon#flushed, iclass 18, count 2 2006.210.07:20:16.74#ibcon#about to write, iclass 18, count 2 2006.210.07:20:16.74#ibcon#wrote, iclass 18, count 2 2006.210.07:20:16.74#ibcon#about to read 3, iclass 18, count 2 2006.210.07:20:16.76#ibcon#read 3, iclass 18, count 2 2006.210.07:20:16.76#ibcon#about to read 4, iclass 18, count 2 2006.210.07:20:16.76#ibcon#read 4, iclass 18, count 2 2006.210.07:20:16.76#ibcon#about to read 5, iclass 18, count 2 2006.210.07:20:16.76#ibcon#read 5, iclass 18, count 2 2006.210.07:20:16.76#ibcon#about to read 6, iclass 18, count 2 2006.210.07:20:16.76#ibcon#read 6, iclass 18, count 2 2006.210.07:20:16.76#ibcon#end of sib2, iclass 18, count 2 2006.210.07:20:16.76#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:20:16.76#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:20:16.76#ibcon#[25=AT01-08\r\n] 2006.210.07:20:16.76#ibcon#*before write, iclass 18, count 2 2006.210.07:20:16.76#ibcon#enter sib2, iclass 18, count 2 2006.210.07:20:16.76#ibcon#flushed, iclass 18, count 2 2006.210.07:20:16.76#ibcon#about to write, iclass 18, count 2 2006.210.07:20:16.76#ibcon#wrote, iclass 18, count 2 2006.210.07:20:16.76#ibcon#about to read 3, iclass 18, count 2 2006.210.07:20:16.79#ibcon#read 3, iclass 18, count 2 2006.210.07:20:16.79#ibcon#about to read 4, iclass 18, count 2 2006.210.07:20:16.79#ibcon#read 4, iclass 18, count 2 2006.210.07:20:16.79#ibcon#about to read 5, iclass 18, count 2 2006.210.07:20:16.79#ibcon#read 5, iclass 18, count 2 2006.210.07:20:16.79#ibcon#about to read 6, iclass 18, count 2 2006.210.07:20:16.79#ibcon#read 6, iclass 18, count 2 2006.210.07:20:16.79#ibcon#end of sib2, iclass 18, count 2 2006.210.07:20:16.79#ibcon#*after write, iclass 18, count 2 2006.210.07:20:16.79#ibcon#*before return 0, iclass 18, count 2 2006.210.07:20:16.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:16.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:16.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:20:16.79#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:16.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:16.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:16.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:16.91#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:20:16.91#ibcon#first serial, iclass 18, count 0 2006.210.07:20:16.91#ibcon#enter sib2, iclass 18, count 0 2006.210.07:20:16.91#ibcon#flushed, iclass 18, count 0 2006.210.07:20:16.91#ibcon#about to write, iclass 18, count 0 2006.210.07:20:16.91#ibcon#wrote, iclass 18, count 0 2006.210.07:20:16.91#ibcon#about to read 3, iclass 18, count 0 2006.210.07:20:16.93#ibcon#read 3, iclass 18, count 0 2006.210.07:20:16.93#ibcon#about to read 4, iclass 18, count 0 2006.210.07:20:16.93#ibcon#read 4, iclass 18, count 0 2006.210.07:20:16.93#ibcon#about to read 5, iclass 18, count 0 2006.210.07:20:16.93#ibcon#read 5, iclass 18, count 0 2006.210.07:20:16.93#ibcon#about to read 6, iclass 18, count 0 2006.210.07:20:16.93#ibcon#read 6, iclass 18, count 0 2006.210.07:20:16.93#ibcon#end of sib2, iclass 18, count 0 2006.210.07:20:16.93#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:20:16.93#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:20:16.93#ibcon#[25=USB\r\n] 2006.210.07:20:16.93#ibcon#*before write, iclass 18, count 0 2006.210.07:20:16.93#ibcon#enter sib2, iclass 18, count 0 2006.210.07:20:16.93#ibcon#flushed, iclass 18, count 0 2006.210.07:20:16.93#ibcon#about to write, iclass 18, count 0 2006.210.07:20:16.93#ibcon#wrote, iclass 18, count 0 2006.210.07:20:16.93#ibcon#about to read 3, iclass 18, count 0 2006.210.07:20:16.96#ibcon#read 3, iclass 18, count 0 2006.210.07:20:16.96#ibcon#about to read 4, iclass 18, count 0 2006.210.07:20:16.96#ibcon#read 4, iclass 18, count 0 2006.210.07:20:16.96#ibcon#about to read 5, iclass 18, count 0 2006.210.07:20:16.96#ibcon#read 5, iclass 18, count 0 2006.210.07:20:16.96#ibcon#about to read 6, iclass 18, count 0 2006.210.07:20:16.96#ibcon#read 6, iclass 18, count 0 2006.210.07:20:16.96#ibcon#end of sib2, iclass 18, count 0 2006.210.07:20:16.96#ibcon#*after write, iclass 18, count 0 2006.210.07:20:16.96#ibcon#*before return 0, iclass 18, count 0 2006.210.07:20:16.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:16.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:16.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:20:16.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:20:16.96$vc4f8/valo=2,572.99 2006.210.07:20:16.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:20:16.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:20:16.96#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:16.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:16.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:16.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:16.96#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:20:16.96#ibcon#first serial, iclass 20, count 0 2006.210.07:20:16.96#ibcon#enter sib2, iclass 20, count 0 2006.210.07:20:16.96#ibcon#flushed, iclass 20, count 0 2006.210.07:20:16.96#ibcon#about to write, iclass 20, count 0 2006.210.07:20:16.96#ibcon#wrote, iclass 20, count 0 2006.210.07:20:16.96#ibcon#about to read 3, iclass 20, count 0 2006.210.07:20:16.98#ibcon#read 3, iclass 20, count 0 2006.210.07:20:16.98#ibcon#about to read 4, iclass 20, count 0 2006.210.07:20:16.98#ibcon#read 4, iclass 20, count 0 2006.210.07:20:16.98#ibcon#about to read 5, iclass 20, count 0 2006.210.07:20:16.98#ibcon#read 5, iclass 20, count 0 2006.210.07:20:16.98#ibcon#about to read 6, iclass 20, count 0 2006.210.07:20:16.98#ibcon#read 6, iclass 20, count 0 2006.210.07:20:16.98#ibcon#end of sib2, iclass 20, count 0 2006.210.07:20:16.98#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:20:16.98#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:20:16.98#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:20:16.98#ibcon#*before write, iclass 20, count 0 2006.210.07:20:16.98#ibcon#enter sib2, iclass 20, count 0 2006.210.07:20:16.98#ibcon#flushed, iclass 20, count 0 2006.210.07:20:16.98#ibcon#about to write, iclass 20, count 0 2006.210.07:20:16.98#ibcon#wrote, iclass 20, count 0 2006.210.07:20:16.98#ibcon#about to read 3, iclass 20, count 0 2006.210.07:20:17.02#ibcon#read 3, iclass 20, count 0 2006.210.07:20:17.02#ibcon#about to read 4, iclass 20, count 0 2006.210.07:20:17.02#ibcon#read 4, iclass 20, count 0 2006.210.07:20:17.02#ibcon#about to read 5, iclass 20, count 0 2006.210.07:20:17.02#ibcon#read 5, iclass 20, count 0 2006.210.07:20:17.02#ibcon#about to read 6, iclass 20, count 0 2006.210.07:20:17.02#ibcon#read 6, iclass 20, count 0 2006.210.07:20:17.02#ibcon#end of sib2, iclass 20, count 0 2006.210.07:20:17.02#ibcon#*after write, iclass 20, count 0 2006.210.07:20:17.02#ibcon#*before return 0, iclass 20, count 0 2006.210.07:20:17.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:17.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:17.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:20:17.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:20:17.02$vc4f8/va=2,7 2006.210.07:20:17.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:20:17.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:20:17.02#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:17.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:17.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:17.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:17.08#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:20:17.08#ibcon#first serial, iclass 22, count 2 2006.210.07:20:17.08#ibcon#enter sib2, iclass 22, count 2 2006.210.07:20:17.08#ibcon#flushed, iclass 22, count 2 2006.210.07:20:17.08#ibcon#about to write, iclass 22, count 2 2006.210.07:20:17.08#ibcon#wrote, iclass 22, count 2 2006.210.07:20:17.08#ibcon#about to read 3, iclass 22, count 2 2006.210.07:20:17.10#ibcon#read 3, iclass 22, count 2 2006.210.07:20:17.10#ibcon#about to read 4, iclass 22, count 2 2006.210.07:20:17.10#ibcon#read 4, iclass 22, count 2 2006.210.07:20:17.10#ibcon#about to read 5, iclass 22, count 2 2006.210.07:20:17.10#ibcon#read 5, iclass 22, count 2 2006.210.07:20:17.10#ibcon#about to read 6, iclass 22, count 2 2006.210.07:20:17.10#ibcon#read 6, iclass 22, count 2 2006.210.07:20:17.10#ibcon#end of sib2, iclass 22, count 2 2006.210.07:20:17.10#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:20:17.10#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:20:17.10#ibcon#[25=AT02-07\r\n] 2006.210.07:20:17.10#ibcon#*before write, iclass 22, count 2 2006.210.07:20:17.10#ibcon#enter sib2, iclass 22, count 2 2006.210.07:20:17.10#ibcon#flushed, iclass 22, count 2 2006.210.07:20:17.10#ibcon#about to write, iclass 22, count 2 2006.210.07:20:17.10#ibcon#wrote, iclass 22, count 2 2006.210.07:20:17.10#ibcon#about to read 3, iclass 22, count 2 2006.210.07:20:17.13#ibcon#read 3, iclass 22, count 2 2006.210.07:20:17.13#ibcon#about to read 4, iclass 22, count 2 2006.210.07:20:17.13#ibcon#read 4, iclass 22, count 2 2006.210.07:20:17.13#ibcon#about to read 5, iclass 22, count 2 2006.210.07:20:17.13#ibcon#read 5, iclass 22, count 2 2006.210.07:20:17.13#ibcon#about to read 6, iclass 22, count 2 2006.210.07:20:17.13#ibcon#read 6, iclass 22, count 2 2006.210.07:20:17.13#ibcon#end of sib2, iclass 22, count 2 2006.210.07:20:17.13#ibcon#*after write, iclass 22, count 2 2006.210.07:20:17.13#ibcon#*before return 0, iclass 22, count 2 2006.210.07:20:17.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:17.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:17.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:20:17.13#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:17.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:17.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:17.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:17.25#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:20:17.25#ibcon#first serial, iclass 22, count 0 2006.210.07:20:17.25#ibcon#enter sib2, iclass 22, count 0 2006.210.07:20:17.25#ibcon#flushed, iclass 22, count 0 2006.210.07:20:17.25#ibcon#about to write, iclass 22, count 0 2006.210.07:20:17.25#ibcon#wrote, iclass 22, count 0 2006.210.07:20:17.25#ibcon#about to read 3, iclass 22, count 0 2006.210.07:20:17.27#ibcon#read 3, iclass 22, count 0 2006.210.07:20:17.27#ibcon#about to read 4, iclass 22, count 0 2006.210.07:20:17.27#ibcon#read 4, iclass 22, count 0 2006.210.07:20:17.27#ibcon#about to read 5, iclass 22, count 0 2006.210.07:20:17.27#ibcon#read 5, iclass 22, count 0 2006.210.07:20:17.27#ibcon#about to read 6, iclass 22, count 0 2006.210.07:20:17.27#ibcon#read 6, iclass 22, count 0 2006.210.07:20:17.27#ibcon#end of sib2, iclass 22, count 0 2006.210.07:20:17.27#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:20:17.27#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:20:17.27#ibcon#[25=USB\r\n] 2006.210.07:20:17.27#ibcon#*before write, iclass 22, count 0 2006.210.07:20:17.27#ibcon#enter sib2, iclass 22, count 0 2006.210.07:20:17.27#ibcon#flushed, iclass 22, count 0 2006.210.07:20:17.27#ibcon#about to write, iclass 22, count 0 2006.210.07:20:17.27#ibcon#wrote, iclass 22, count 0 2006.210.07:20:17.27#ibcon#about to read 3, iclass 22, count 0 2006.210.07:20:17.30#ibcon#read 3, iclass 22, count 0 2006.210.07:20:17.30#ibcon#about to read 4, iclass 22, count 0 2006.210.07:20:17.30#ibcon#read 4, iclass 22, count 0 2006.210.07:20:17.30#ibcon#about to read 5, iclass 22, count 0 2006.210.07:20:17.30#ibcon#read 5, iclass 22, count 0 2006.210.07:20:17.30#ibcon#about to read 6, iclass 22, count 0 2006.210.07:20:17.30#ibcon#read 6, iclass 22, count 0 2006.210.07:20:17.30#ibcon#end of sib2, iclass 22, count 0 2006.210.07:20:17.30#ibcon#*after write, iclass 22, count 0 2006.210.07:20:17.30#ibcon#*before return 0, iclass 22, count 0 2006.210.07:20:17.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:17.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:17.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:20:17.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:20:17.30$vc4f8/valo=3,672.99 2006.210.07:20:17.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:20:17.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:20:17.30#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:17.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:17.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:17.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:17.30#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:20:17.30#ibcon#first serial, iclass 24, count 0 2006.210.07:20:17.30#ibcon#enter sib2, iclass 24, count 0 2006.210.07:20:17.30#ibcon#flushed, iclass 24, count 0 2006.210.07:20:17.30#ibcon#about to write, iclass 24, count 0 2006.210.07:20:17.30#ibcon#wrote, iclass 24, count 0 2006.210.07:20:17.30#ibcon#about to read 3, iclass 24, count 0 2006.210.07:20:17.32#ibcon#read 3, iclass 24, count 0 2006.210.07:20:17.32#ibcon#about to read 4, iclass 24, count 0 2006.210.07:20:17.32#ibcon#read 4, iclass 24, count 0 2006.210.07:20:17.32#ibcon#about to read 5, iclass 24, count 0 2006.210.07:20:17.32#ibcon#read 5, iclass 24, count 0 2006.210.07:20:17.32#ibcon#about to read 6, iclass 24, count 0 2006.210.07:20:17.32#ibcon#read 6, iclass 24, count 0 2006.210.07:20:17.32#ibcon#end of sib2, iclass 24, count 0 2006.210.07:20:17.32#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:20:17.32#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:20:17.32#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:20:17.32#ibcon#*before write, iclass 24, count 0 2006.210.07:20:17.32#ibcon#enter sib2, iclass 24, count 0 2006.210.07:20:17.32#ibcon#flushed, iclass 24, count 0 2006.210.07:20:17.32#ibcon#about to write, iclass 24, count 0 2006.210.07:20:17.32#ibcon#wrote, iclass 24, count 0 2006.210.07:20:17.32#ibcon#about to read 3, iclass 24, count 0 2006.210.07:20:17.36#ibcon#read 3, iclass 24, count 0 2006.210.07:20:17.36#ibcon#about to read 4, iclass 24, count 0 2006.210.07:20:17.36#ibcon#read 4, iclass 24, count 0 2006.210.07:20:17.36#ibcon#about to read 5, iclass 24, count 0 2006.210.07:20:17.36#ibcon#read 5, iclass 24, count 0 2006.210.07:20:17.36#ibcon#about to read 6, iclass 24, count 0 2006.210.07:20:17.36#ibcon#read 6, iclass 24, count 0 2006.210.07:20:17.36#ibcon#end of sib2, iclass 24, count 0 2006.210.07:20:17.36#ibcon#*after write, iclass 24, count 0 2006.210.07:20:17.36#ibcon#*before return 0, iclass 24, count 0 2006.210.07:20:17.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:17.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:17.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:20:17.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:20:17.36$vc4f8/va=3,6 2006.210.07:20:17.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:20:17.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:20:17.36#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:17.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:17.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:17.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:17.42#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:20:17.42#ibcon#first serial, iclass 26, count 2 2006.210.07:20:17.42#ibcon#enter sib2, iclass 26, count 2 2006.210.07:20:17.42#ibcon#flushed, iclass 26, count 2 2006.210.07:20:17.42#ibcon#about to write, iclass 26, count 2 2006.210.07:20:17.42#ibcon#wrote, iclass 26, count 2 2006.210.07:20:17.42#ibcon#about to read 3, iclass 26, count 2 2006.210.07:20:17.44#ibcon#read 3, iclass 26, count 2 2006.210.07:20:17.44#ibcon#about to read 4, iclass 26, count 2 2006.210.07:20:17.44#ibcon#read 4, iclass 26, count 2 2006.210.07:20:17.44#ibcon#about to read 5, iclass 26, count 2 2006.210.07:20:17.44#ibcon#read 5, iclass 26, count 2 2006.210.07:20:17.44#ibcon#about to read 6, iclass 26, count 2 2006.210.07:20:17.44#ibcon#read 6, iclass 26, count 2 2006.210.07:20:17.44#ibcon#end of sib2, iclass 26, count 2 2006.210.07:20:17.44#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:20:17.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:20:17.44#ibcon#[25=AT03-06\r\n] 2006.210.07:20:17.44#ibcon#*before write, iclass 26, count 2 2006.210.07:20:17.44#ibcon#enter sib2, iclass 26, count 2 2006.210.07:20:17.44#ibcon#flushed, iclass 26, count 2 2006.210.07:20:17.44#ibcon#about to write, iclass 26, count 2 2006.210.07:20:17.44#ibcon#wrote, iclass 26, count 2 2006.210.07:20:17.44#ibcon#about to read 3, iclass 26, count 2 2006.210.07:20:17.47#ibcon#read 3, iclass 26, count 2 2006.210.07:20:17.47#ibcon#about to read 4, iclass 26, count 2 2006.210.07:20:17.47#ibcon#read 4, iclass 26, count 2 2006.210.07:20:17.47#ibcon#about to read 5, iclass 26, count 2 2006.210.07:20:17.47#ibcon#read 5, iclass 26, count 2 2006.210.07:20:17.47#ibcon#about to read 6, iclass 26, count 2 2006.210.07:20:17.47#ibcon#read 6, iclass 26, count 2 2006.210.07:20:17.47#ibcon#end of sib2, iclass 26, count 2 2006.210.07:20:17.47#ibcon#*after write, iclass 26, count 2 2006.210.07:20:17.47#ibcon#*before return 0, iclass 26, count 2 2006.210.07:20:17.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:17.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:17.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:20:17.47#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:17.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:17.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:17.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:17.59#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:20:17.59#ibcon#first serial, iclass 26, count 0 2006.210.07:20:17.59#ibcon#enter sib2, iclass 26, count 0 2006.210.07:20:17.59#ibcon#flushed, iclass 26, count 0 2006.210.07:20:17.59#ibcon#about to write, iclass 26, count 0 2006.210.07:20:17.59#ibcon#wrote, iclass 26, count 0 2006.210.07:20:17.59#ibcon#about to read 3, iclass 26, count 0 2006.210.07:20:17.61#ibcon#read 3, iclass 26, count 0 2006.210.07:20:17.61#ibcon#about to read 4, iclass 26, count 0 2006.210.07:20:17.61#ibcon#read 4, iclass 26, count 0 2006.210.07:20:17.61#ibcon#about to read 5, iclass 26, count 0 2006.210.07:20:17.61#ibcon#read 5, iclass 26, count 0 2006.210.07:20:17.61#ibcon#about to read 6, iclass 26, count 0 2006.210.07:20:17.61#ibcon#read 6, iclass 26, count 0 2006.210.07:20:17.61#ibcon#end of sib2, iclass 26, count 0 2006.210.07:20:17.61#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:20:17.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:20:17.61#ibcon#[25=USB\r\n] 2006.210.07:20:17.61#ibcon#*before write, iclass 26, count 0 2006.210.07:20:17.61#ibcon#enter sib2, iclass 26, count 0 2006.210.07:20:17.61#ibcon#flushed, iclass 26, count 0 2006.210.07:20:17.61#ibcon#about to write, iclass 26, count 0 2006.210.07:20:17.61#ibcon#wrote, iclass 26, count 0 2006.210.07:20:17.61#ibcon#about to read 3, iclass 26, count 0 2006.210.07:20:17.64#ibcon#read 3, iclass 26, count 0 2006.210.07:20:17.64#ibcon#about to read 4, iclass 26, count 0 2006.210.07:20:17.64#ibcon#read 4, iclass 26, count 0 2006.210.07:20:17.64#ibcon#about to read 5, iclass 26, count 0 2006.210.07:20:17.64#ibcon#read 5, iclass 26, count 0 2006.210.07:20:17.64#ibcon#about to read 6, iclass 26, count 0 2006.210.07:20:17.64#ibcon#read 6, iclass 26, count 0 2006.210.07:20:17.64#ibcon#end of sib2, iclass 26, count 0 2006.210.07:20:17.64#ibcon#*after write, iclass 26, count 0 2006.210.07:20:17.64#ibcon#*before return 0, iclass 26, count 0 2006.210.07:20:17.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:17.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:17.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:20:17.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:20:17.64$vc4f8/valo=4,832.99 2006.210.07:20:17.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:20:17.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:20:17.64#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:17.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:17.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:17.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:17.64#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:20:17.64#ibcon#first serial, iclass 28, count 0 2006.210.07:20:17.64#ibcon#enter sib2, iclass 28, count 0 2006.210.07:20:17.64#ibcon#flushed, iclass 28, count 0 2006.210.07:20:17.64#ibcon#about to write, iclass 28, count 0 2006.210.07:20:17.64#ibcon#wrote, iclass 28, count 0 2006.210.07:20:17.64#ibcon#about to read 3, iclass 28, count 0 2006.210.07:20:17.66#ibcon#read 3, iclass 28, count 0 2006.210.07:20:17.66#ibcon#about to read 4, iclass 28, count 0 2006.210.07:20:17.66#ibcon#read 4, iclass 28, count 0 2006.210.07:20:17.66#ibcon#about to read 5, iclass 28, count 0 2006.210.07:20:17.66#ibcon#read 5, iclass 28, count 0 2006.210.07:20:17.66#ibcon#about to read 6, iclass 28, count 0 2006.210.07:20:17.66#ibcon#read 6, iclass 28, count 0 2006.210.07:20:17.66#ibcon#end of sib2, iclass 28, count 0 2006.210.07:20:17.66#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:20:17.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:20:17.66#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:20:17.66#ibcon#*before write, iclass 28, count 0 2006.210.07:20:17.66#ibcon#enter sib2, iclass 28, count 0 2006.210.07:20:17.66#ibcon#flushed, iclass 28, count 0 2006.210.07:20:17.66#ibcon#about to write, iclass 28, count 0 2006.210.07:20:17.66#ibcon#wrote, iclass 28, count 0 2006.210.07:20:17.66#ibcon#about to read 3, iclass 28, count 0 2006.210.07:20:17.70#ibcon#read 3, iclass 28, count 0 2006.210.07:20:17.70#ibcon#about to read 4, iclass 28, count 0 2006.210.07:20:17.70#ibcon#read 4, iclass 28, count 0 2006.210.07:20:17.70#ibcon#about to read 5, iclass 28, count 0 2006.210.07:20:17.70#ibcon#read 5, iclass 28, count 0 2006.210.07:20:17.70#ibcon#about to read 6, iclass 28, count 0 2006.210.07:20:17.70#ibcon#read 6, iclass 28, count 0 2006.210.07:20:17.70#ibcon#end of sib2, iclass 28, count 0 2006.210.07:20:17.70#ibcon#*after write, iclass 28, count 0 2006.210.07:20:17.70#ibcon#*before return 0, iclass 28, count 0 2006.210.07:20:17.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:17.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:17.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:20:17.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:20:17.70$vc4f8/va=4,7 2006.210.07:20:17.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:20:17.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:20:17.70#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:17.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:17.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:17.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:17.76#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:20:17.76#ibcon#first serial, iclass 30, count 2 2006.210.07:20:17.76#ibcon#enter sib2, iclass 30, count 2 2006.210.07:20:17.76#ibcon#flushed, iclass 30, count 2 2006.210.07:20:17.76#ibcon#about to write, iclass 30, count 2 2006.210.07:20:17.76#ibcon#wrote, iclass 30, count 2 2006.210.07:20:17.76#ibcon#about to read 3, iclass 30, count 2 2006.210.07:20:17.78#ibcon#read 3, iclass 30, count 2 2006.210.07:20:17.78#ibcon#about to read 4, iclass 30, count 2 2006.210.07:20:17.78#ibcon#read 4, iclass 30, count 2 2006.210.07:20:17.78#ibcon#about to read 5, iclass 30, count 2 2006.210.07:20:17.78#ibcon#read 5, iclass 30, count 2 2006.210.07:20:17.78#ibcon#about to read 6, iclass 30, count 2 2006.210.07:20:17.78#ibcon#read 6, iclass 30, count 2 2006.210.07:20:17.78#ibcon#end of sib2, iclass 30, count 2 2006.210.07:20:17.78#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:20:17.78#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:20:17.78#ibcon#[25=AT04-07\r\n] 2006.210.07:20:17.78#ibcon#*before write, iclass 30, count 2 2006.210.07:20:17.78#ibcon#enter sib2, iclass 30, count 2 2006.210.07:20:17.78#ibcon#flushed, iclass 30, count 2 2006.210.07:20:17.78#ibcon#about to write, iclass 30, count 2 2006.210.07:20:17.78#ibcon#wrote, iclass 30, count 2 2006.210.07:20:17.78#ibcon#about to read 3, iclass 30, count 2 2006.210.07:20:17.81#ibcon#read 3, iclass 30, count 2 2006.210.07:20:17.81#ibcon#about to read 4, iclass 30, count 2 2006.210.07:20:17.81#ibcon#read 4, iclass 30, count 2 2006.210.07:20:17.81#ibcon#about to read 5, iclass 30, count 2 2006.210.07:20:17.81#ibcon#read 5, iclass 30, count 2 2006.210.07:20:17.81#ibcon#about to read 6, iclass 30, count 2 2006.210.07:20:17.81#ibcon#read 6, iclass 30, count 2 2006.210.07:20:17.81#ibcon#end of sib2, iclass 30, count 2 2006.210.07:20:17.81#ibcon#*after write, iclass 30, count 2 2006.210.07:20:17.81#ibcon#*before return 0, iclass 30, count 2 2006.210.07:20:17.81#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:17.81#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:17.81#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:20:17.81#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:17.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:17.93#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:17.93#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:17.93#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:20:17.93#ibcon#first serial, iclass 30, count 0 2006.210.07:20:17.93#ibcon#enter sib2, iclass 30, count 0 2006.210.07:20:17.93#ibcon#flushed, iclass 30, count 0 2006.210.07:20:17.93#ibcon#about to write, iclass 30, count 0 2006.210.07:20:17.93#ibcon#wrote, iclass 30, count 0 2006.210.07:20:17.93#ibcon#about to read 3, iclass 30, count 0 2006.210.07:20:17.95#ibcon#read 3, iclass 30, count 0 2006.210.07:20:17.95#ibcon#about to read 4, iclass 30, count 0 2006.210.07:20:17.95#ibcon#read 4, iclass 30, count 0 2006.210.07:20:17.95#ibcon#about to read 5, iclass 30, count 0 2006.210.07:20:17.95#ibcon#read 5, iclass 30, count 0 2006.210.07:20:17.95#ibcon#about to read 6, iclass 30, count 0 2006.210.07:20:17.95#ibcon#read 6, iclass 30, count 0 2006.210.07:20:17.95#ibcon#end of sib2, iclass 30, count 0 2006.210.07:20:17.95#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:20:17.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:20:17.95#ibcon#[25=USB\r\n] 2006.210.07:20:17.95#ibcon#*before write, iclass 30, count 0 2006.210.07:20:17.95#ibcon#enter sib2, iclass 30, count 0 2006.210.07:20:17.95#ibcon#flushed, iclass 30, count 0 2006.210.07:20:17.95#ibcon#about to write, iclass 30, count 0 2006.210.07:20:17.95#ibcon#wrote, iclass 30, count 0 2006.210.07:20:17.95#ibcon#about to read 3, iclass 30, count 0 2006.210.07:20:17.98#ibcon#read 3, iclass 30, count 0 2006.210.07:20:17.98#ibcon#about to read 4, iclass 30, count 0 2006.210.07:20:17.98#ibcon#read 4, iclass 30, count 0 2006.210.07:20:17.98#ibcon#about to read 5, iclass 30, count 0 2006.210.07:20:17.98#ibcon#read 5, iclass 30, count 0 2006.210.07:20:17.98#ibcon#about to read 6, iclass 30, count 0 2006.210.07:20:17.98#ibcon#read 6, iclass 30, count 0 2006.210.07:20:17.98#ibcon#end of sib2, iclass 30, count 0 2006.210.07:20:17.98#ibcon#*after write, iclass 30, count 0 2006.210.07:20:17.98#ibcon#*before return 0, iclass 30, count 0 2006.210.07:20:17.98#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:17.98#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:17.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:20:17.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:20:17.98$vc4f8/valo=5,652.99 2006.210.07:20:17.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:20:17.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:20:17.98#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:17.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:17.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:17.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:17.98#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:20:17.98#ibcon#first serial, iclass 32, count 0 2006.210.07:20:17.98#ibcon#enter sib2, iclass 32, count 0 2006.210.07:20:17.98#ibcon#flushed, iclass 32, count 0 2006.210.07:20:17.98#ibcon#about to write, iclass 32, count 0 2006.210.07:20:17.98#ibcon#wrote, iclass 32, count 0 2006.210.07:20:17.98#ibcon#about to read 3, iclass 32, count 0 2006.210.07:20:18.00#ibcon#read 3, iclass 32, count 0 2006.210.07:20:18.00#ibcon#about to read 4, iclass 32, count 0 2006.210.07:20:18.00#ibcon#read 4, iclass 32, count 0 2006.210.07:20:18.00#ibcon#about to read 5, iclass 32, count 0 2006.210.07:20:18.00#ibcon#read 5, iclass 32, count 0 2006.210.07:20:18.00#ibcon#about to read 6, iclass 32, count 0 2006.210.07:20:18.00#ibcon#read 6, iclass 32, count 0 2006.210.07:20:18.00#ibcon#end of sib2, iclass 32, count 0 2006.210.07:20:18.00#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:20:18.00#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:20:18.00#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:20:18.00#ibcon#*before write, iclass 32, count 0 2006.210.07:20:18.00#ibcon#enter sib2, iclass 32, count 0 2006.210.07:20:18.00#ibcon#flushed, iclass 32, count 0 2006.210.07:20:18.00#ibcon#about to write, iclass 32, count 0 2006.210.07:20:18.00#ibcon#wrote, iclass 32, count 0 2006.210.07:20:18.00#ibcon#about to read 3, iclass 32, count 0 2006.210.07:20:18.04#ibcon#read 3, iclass 32, count 0 2006.210.07:20:18.04#ibcon#about to read 4, iclass 32, count 0 2006.210.07:20:18.04#ibcon#read 4, iclass 32, count 0 2006.210.07:20:18.04#ibcon#about to read 5, iclass 32, count 0 2006.210.07:20:18.04#ibcon#read 5, iclass 32, count 0 2006.210.07:20:18.04#ibcon#about to read 6, iclass 32, count 0 2006.210.07:20:18.04#ibcon#read 6, iclass 32, count 0 2006.210.07:20:18.04#ibcon#end of sib2, iclass 32, count 0 2006.210.07:20:18.04#ibcon#*after write, iclass 32, count 0 2006.210.07:20:18.04#ibcon#*before return 0, iclass 32, count 0 2006.210.07:20:18.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:18.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:18.04#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:20:18.04#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:20:18.04$vc4f8/va=5,7 2006.210.07:20:18.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:20:18.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:20:18.04#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:18.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:18.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:18.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:18.10#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:20:18.10#ibcon#first serial, iclass 34, count 2 2006.210.07:20:18.10#ibcon#enter sib2, iclass 34, count 2 2006.210.07:20:18.10#ibcon#flushed, iclass 34, count 2 2006.210.07:20:18.10#ibcon#about to write, iclass 34, count 2 2006.210.07:20:18.10#ibcon#wrote, iclass 34, count 2 2006.210.07:20:18.10#ibcon#about to read 3, iclass 34, count 2 2006.210.07:20:18.12#ibcon#read 3, iclass 34, count 2 2006.210.07:20:18.12#ibcon#about to read 4, iclass 34, count 2 2006.210.07:20:18.12#ibcon#read 4, iclass 34, count 2 2006.210.07:20:18.12#ibcon#about to read 5, iclass 34, count 2 2006.210.07:20:18.12#ibcon#read 5, iclass 34, count 2 2006.210.07:20:18.12#ibcon#about to read 6, iclass 34, count 2 2006.210.07:20:18.12#ibcon#read 6, iclass 34, count 2 2006.210.07:20:18.12#ibcon#end of sib2, iclass 34, count 2 2006.210.07:20:18.12#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:20:18.12#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:20:18.12#ibcon#[25=AT05-07\r\n] 2006.210.07:20:18.12#ibcon#*before write, iclass 34, count 2 2006.210.07:20:18.12#ibcon#enter sib2, iclass 34, count 2 2006.210.07:20:18.12#ibcon#flushed, iclass 34, count 2 2006.210.07:20:18.12#ibcon#about to write, iclass 34, count 2 2006.210.07:20:18.12#ibcon#wrote, iclass 34, count 2 2006.210.07:20:18.12#ibcon#about to read 3, iclass 34, count 2 2006.210.07:20:18.15#ibcon#read 3, iclass 34, count 2 2006.210.07:20:18.15#ibcon#about to read 4, iclass 34, count 2 2006.210.07:20:18.15#ibcon#read 4, iclass 34, count 2 2006.210.07:20:18.15#ibcon#about to read 5, iclass 34, count 2 2006.210.07:20:18.15#ibcon#read 5, iclass 34, count 2 2006.210.07:20:18.15#ibcon#about to read 6, iclass 34, count 2 2006.210.07:20:18.15#ibcon#read 6, iclass 34, count 2 2006.210.07:20:18.15#ibcon#end of sib2, iclass 34, count 2 2006.210.07:20:18.15#ibcon#*after write, iclass 34, count 2 2006.210.07:20:18.15#ibcon#*before return 0, iclass 34, count 2 2006.210.07:20:18.15#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:18.15#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:18.15#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:20:18.15#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:18.15#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:18.27#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:18.27#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:18.27#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:20:18.27#ibcon#first serial, iclass 34, count 0 2006.210.07:20:18.27#ibcon#enter sib2, iclass 34, count 0 2006.210.07:20:18.27#ibcon#flushed, iclass 34, count 0 2006.210.07:20:18.27#ibcon#about to write, iclass 34, count 0 2006.210.07:20:18.27#ibcon#wrote, iclass 34, count 0 2006.210.07:20:18.27#ibcon#about to read 3, iclass 34, count 0 2006.210.07:20:18.29#ibcon#read 3, iclass 34, count 0 2006.210.07:20:18.29#ibcon#about to read 4, iclass 34, count 0 2006.210.07:20:18.29#ibcon#read 4, iclass 34, count 0 2006.210.07:20:18.29#ibcon#about to read 5, iclass 34, count 0 2006.210.07:20:18.29#ibcon#read 5, iclass 34, count 0 2006.210.07:20:18.29#ibcon#about to read 6, iclass 34, count 0 2006.210.07:20:18.29#ibcon#read 6, iclass 34, count 0 2006.210.07:20:18.29#ibcon#end of sib2, iclass 34, count 0 2006.210.07:20:18.29#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:20:18.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:20:18.29#ibcon#[25=USB\r\n] 2006.210.07:20:18.29#ibcon#*before write, iclass 34, count 0 2006.210.07:20:18.29#ibcon#enter sib2, iclass 34, count 0 2006.210.07:20:18.29#ibcon#flushed, iclass 34, count 0 2006.210.07:20:18.29#ibcon#about to write, iclass 34, count 0 2006.210.07:20:18.29#ibcon#wrote, iclass 34, count 0 2006.210.07:20:18.29#ibcon#about to read 3, iclass 34, count 0 2006.210.07:20:18.32#ibcon#read 3, iclass 34, count 0 2006.210.07:20:18.32#ibcon#about to read 4, iclass 34, count 0 2006.210.07:20:18.32#ibcon#read 4, iclass 34, count 0 2006.210.07:20:18.32#ibcon#about to read 5, iclass 34, count 0 2006.210.07:20:18.32#ibcon#read 5, iclass 34, count 0 2006.210.07:20:18.32#ibcon#about to read 6, iclass 34, count 0 2006.210.07:20:18.32#ibcon#read 6, iclass 34, count 0 2006.210.07:20:18.32#ibcon#end of sib2, iclass 34, count 0 2006.210.07:20:18.32#ibcon#*after write, iclass 34, count 0 2006.210.07:20:18.32#ibcon#*before return 0, iclass 34, count 0 2006.210.07:20:18.32#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:18.32#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:18.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:20:18.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:20:18.32$vc4f8/valo=6,772.99 2006.210.07:20:18.32#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:20:18.32#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:20:18.32#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:18.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:18.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:18.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:18.32#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:20:18.32#ibcon#first serial, iclass 36, count 0 2006.210.07:20:18.32#ibcon#enter sib2, iclass 36, count 0 2006.210.07:20:18.32#ibcon#flushed, iclass 36, count 0 2006.210.07:20:18.32#ibcon#about to write, iclass 36, count 0 2006.210.07:20:18.32#ibcon#wrote, iclass 36, count 0 2006.210.07:20:18.32#ibcon#about to read 3, iclass 36, count 0 2006.210.07:20:18.34#ibcon#read 3, iclass 36, count 0 2006.210.07:20:18.34#ibcon#about to read 4, iclass 36, count 0 2006.210.07:20:18.34#ibcon#read 4, iclass 36, count 0 2006.210.07:20:18.34#ibcon#about to read 5, iclass 36, count 0 2006.210.07:20:18.34#ibcon#read 5, iclass 36, count 0 2006.210.07:20:18.34#ibcon#about to read 6, iclass 36, count 0 2006.210.07:20:18.34#ibcon#read 6, iclass 36, count 0 2006.210.07:20:18.34#ibcon#end of sib2, iclass 36, count 0 2006.210.07:20:18.34#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:20:18.34#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:20:18.34#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:20:18.34#ibcon#*before write, iclass 36, count 0 2006.210.07:20:18.34#ibcon#enter sib2, iclass 36, count 0 2006.210.07:20:18.34#ibcon#flushed, iclass 36, count 0 2006.210.07:20:18.34#ibcon#about to write, iclass 36, count 0 2006.210.07:20:18.34#ibcon#wrote, iclass 36, count 0 2006.210.07:20:18.34#ibcon#about to read 3, iclass 36, count 0 2006.210.07:20:18.38#ibcon#read 3, iclass 36, count 0 2006.210.07:20:18.38#ibcon#about to read 4, iclass 36, count 0 2006.210.07:20:18.38#ibcon#read 4, iclass 36, count 0 2006.210.07:20:18.38#ibcon#about to read 5, iclass 36, count 0 2006.210.07:20:18.38#ibcon#read 5, iclass 36, count 0 2006.210.07:20:18.38#ibcon#about to read 6, iclass 36, count 0 2006.210.07:20:18.38#ibcon#read 6, iclass 36, count 0 2006.210.07:20:18.38#ibcon#end of sib2, iclass 36, count 0 2006.210.07:20:18.38#ibcon#*after write, iclass 36, count 0 2006.210.07:20:18.38#ibcon#*before return 0, iclass 36, count 0 2006.210.07:20:18.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:18.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:18.38#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:20:18.38#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:20:18.38$vc4f8/va=6,6 2006.210.07:20:18.38#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:20:18.38#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:20:18.38#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:18.38#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:20:18.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:20:18.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:20:18.44#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:20:18.44#ibcon#first serial, iclass 38, count 2 2006.210.07:20:18.44#ibcon#enter sib2, iclass 38, count 2 2006.210.07:20:18.44#ibcon#flushed, iclass 38, count 2 2006.210.07:20:18.44#ibcon#about to write, iclass 38, count 2 2006.210.07:20:18.44#ibcon#wrote, iclass 38, count 2 2006.210.07:20:18.44#ibcon#about to read 3, iclass 38, count 2 2006.210.07:20:18.46#ibcon#read 3, iclass 38, count 2 2006.210.07:20:18.46#ibcon#about to read 4, iclass 38, count 2 2006.210.07:20:18.46#ibcon#read 4, iclass 38, count 2 2006.210.07:20:18.46#ibcon#about to read 5, iclass 38, count 2 2006.210.07:20:18.46#ibcon#read 5, iclass 38, count 2 2006.210.07:20:18.46#ibcon#about to read 6, iclass 38, count 2 2006.210.07:20:18.46#ibcon#read 6, iclass 38, count 2 2006.210.07:20:18.46#ibcon#end of sib2, iclass 38, count 2 2006.210.07:20:18.46#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:20:18.46#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:20:18.46#ibcon#[25=AT06-06\r\n] 2006.210.07:20:18.46#ibcon#*before write, iclass 38, count 2 2006.210.07:20:18.46#ibcon#enter sib2, iclass 38, count 2 2006.210.07:20:18.46#ibcon#flushed, iclass 38, count 2 2006.210.07:20:18.46#ibcon#about to write, iclass 38, count 2 2006.210.07:20:18.46#ibcon#wrote, iclass 38, count 2 2006.210.07:20:18.46#ibcon#about to read 3, iclass 38, count 2 2006.210.07:20:18.49#ibcon#read 3, iclass 38, count 2 2006.210.07:20:18.49#ibcon#about to read 4, iclass 38, count 2 2006.210.07:20:18.49#ibcon#read 4, iclass 38, count 2 2006.210.07:20:18.49#ibcon#about to read 5, iclass 38, count 2 2006.210.07:20:18.49#ibcon#read 5, iclass 38, count 2 2006.210.07:20:18.49#ibcon#about to read 6, iclass 38, count 2 2006.210.07:20:18.49#ibcon#read 6, iclass 38, count 2 2006.210.07:20:18.49#ibcon#end of sib2, iclass 38, count 2 2006.210.07:20:18.49#ibcon#*after write, iclass 38, count 2 2006.210.07:20:18.49#ibcon#*before return 0, iclass 38, count 2 2006.210.07:20:18.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:20:18.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:20:18.49#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:20:18.49#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:18.49#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:20:18.61#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:20:18.61#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:20:18.61#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:20:18.61#ibcon#first serial, iclass 38, count 0 2006.210.07:20:18.61#ibcon#enter sib2, iclass 38, count 0 2006.210.07:20:18.61#ibcon#flushed, iclass 38, count 0 2006.210.07:20:18.61#ibcon#about to write, iclass 38, count 0 2006.210.07:20:18.61#ibcon#wrote, iclass 38, count 0 2006.210.07:20:18.61#ibcon#about to read 3, iclass 38, count 0 2006.210.07:20:18.63#ibcon#read 3, iclass 38, count 0 2006.210.07:20:18.63#ibcon#about to read 4, iclass 38, count 0 2006.210.07:20:18.63#ibcon#read 4, iclass 38, count 0 2006.210.07:20:18.63#ibcon#about to read 5, iclass 38, count 0 2006.210.07:20:18.63#ibcon#read 5, iclass 38, count 0 2006.210.07:20:18.63#ibcon#about to read 6, iclass 38, count 0 2006.210.07:20:18.63#ibcon#read 6, iclass 38, count 0 2006.210.07:20:18.63#ibcon#end of sib2, iclass 38, count 0 2006.210.07:20:18.63#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:20:18.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:20:18.63#ibcon#[25=USB\r\n] 2006.210.07:20:18.63#ibcon#*before write, iclass 38, count 0 2006.210.07:20:18.63#ibcon#enter sib2, iclass 38, count 0 2006.210.07:20:18.63#ibcon#flushed, iclass 38, count 0 2006.210.07:20:18.63#ibcon#about to write, iclass 38, count 0 2006.210.07:20:18.63#ibcon#wrote, iclass 38, count 0 2006.210.07:20:18.63#ibcon#about to read 3, iclass 38, count 0 2006.210.07:20:18.66#ibcon#read 3, iclass 38, count 0 2006.210.07:20:18.66#ibcon#about to read 4, iclass 38, count 0 2006.210.07:20:18.66#ibcon#read 4, iclass 38, count 0 2006.210.07:20:18.66#ibcon#about to read 5, iclass 38, count 0 2006.210.07:20:18.66#ibcon#read 5, iclass 38, count 0 2006.210.07:20:18.66#ibcon#about to read 6, iclass 38, count 0 2006.210.07:20:18.66#ibcon#read 6, iclass 38, count 0 2006.210.07:20:18.66#ibcon#end of sib2, iclass 38, count 0 2006.210.07:20:18.66#ibcon#*after write, iclass 38, count 0 2006.210.07:20:18.66#ibcon#*before return 0, iclass 38, count 0 2006.210.07:20:18.66#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:20:18.66#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:20:18.66#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:20:18.66#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:20:18.66$vc4f8/valo=7,832.99 2006.210.07:20:18.66#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:20:18.66#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:20:18.66#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:18.66#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:20:18.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:20:18.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:20:18.66#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:20:18.66#ibcon#first serial, iclass 40, count 0 2006.210.07:20:18.66#ibcon#enter sib2, iclass 40, count 0 2006.210.07:20:18.66#ibcon#flushed, iclass 40, count 0 2006.210.07:20:18.66#ibcon#about to write, iclass 40, count 0 2006.210.07:20:18.66#ibcon#wrote, iclass 40, count 0 2006.210.07:20:18.66#ibcon#about to read 3, iclass 40, count 0 2006.210.07:20:18.68#ibcon#read 3, iclass 40, count 0 2006.210.07:20:18.68#ibcon#about to read 4, iclass 40, count 0 2006.210.07:20:18.68#ibcon#read 4, iclass 40, count 0 2006.210.07:20:18.68#ibcon#about to read 5, iclass 40, count 0 2006.210.07:20:18.68#ibcon#read 5, iclass 40, count 0 2006.210.07:20:18.68#ibcon#about to read 6, iclass 40, count 0 2006.210.07:20:18.68#ibcon#read 6, iclass 40, count 0 2006.210.07:20:18.68#ibcon#end of sib2, iclass 40, count 0 2006.210.07:20:18.68#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:20:18.68#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:20:18.68#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:20:18.68#ibcon#*before write, iclass 40, count 0 2006.210.07:20:18.68#ibcon#enter sib2, iclass 40, count 0 2006.210.07:20:18.68#ibcon#flushed, iclass 40, count 0 2006.210.07:20:18.68#ibcon#about to write, iclass 40, count 0 2006.210.07:20:18.68#ibcon#wrote, iclass 40, count 0 2006.210.07:20:18.68#ibcon#about to read 3, iclass 40, count 0 2006.210.07:20:18.72#ibcon#read 3, iclass 40, count 0 2006.210.07:20:18.72#ibcon#about to read 4, iclass 40, count 0 2006.210.07:20:18.72#ibcon#read 4, iclass 40, count 0 2006.210.07:20:18.72#ibcon#about to read 5, iclass 40, count 0 2006.210.07:20:18.72#ibcon#read 5, iclass 40, count 0 2006.210.07:20:18.72#ibcon#about to read 6, iclass 40, count 0 2006.210.07:20:18.72#ibcon#read 6, iclass 40, count 0 2006.210.07:20:18.72#ibcon#end of sib2, iclass 40, count 0 2006.210.07:20:18.72#ibcon#*after write, iclass 40, count 0 2006.210.07:20:18.72#ibcon#*before return 0, iclass 40, count 0 2006.210.07:20:18.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:20:18.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:20:18.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:20:18.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:20:18.72$vc4f8/va=7,6 2006.210.07:20:18.72#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:20:18.72#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:20:18.72#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:18.72#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:20:18.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:20:18.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:20:18.78#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:20:18.78#ibcon#first serial, iclass 4, count 2 2006.210.07:20:18.78#ibcon#enter sib2, iclass 4, count 2 2006.210.07:20:18.78#ibcon#flushed, iclass 4, count 2 2006.210.07:20:18.78#ibcon#about to write, iclass 4, count 2 2006.210.07:20:18.78#ibcon#wrote, iclass 4, count 2 2006.210.07:20:18.78#ibcon#about to read 3, iclass 4, count 2 2006.210.07:20:18.80#ibcon#read 3, iclass 4, count 2 2006.210.07:20:18.80#ibcon#about to read 4, iclass 4, count 2 2006.210.07:20:18.80#ibcon#read 4, iclass 4, count 2 2006.210.07:20:18.80#ibcon#about to read 5, iclass 4, count 2 2006.210.07:20:18.80#ibcon#read 5, iclass 4, count 2 2006.210.07:20:18.80#ibcon#about to read 6, iclass 4, count 2 2006.210.07:20:18.80#ibcon#read 6, iclass 4, count 2 2006.210.07:20:18.80#ibcon#end of sib2, iclass 4, count 2 2006.210.07:20:18.80#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:20:18.80#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:20:18.80#ibcon#[25=AT07-06\r\n] 2006.210.07:20:18.80#ibcon#*before write, iclass 4, count 2 2006.210.07:20:18.80#ibcon#enter sib2, iclass 4, count 2 2006.210.07:20:18.80#ibcon#flushed, iclass 4, count 2 2006.210.07:20:18.80#ibcon#about to write, iclass 4, count 2 2006.210.07:20:18.80#ibcon#wrote, iclass 4, count 2 2006.210.07:20:18.80#ibcon#about to read 3, iclass 4, count 2 2006.210.07:20:18.83#ibcon#read 3, iclass 4, count 2 2006.210.07:20:18.83#ibcon#about to read 4, iclass 4, count 2 2006.210.07:20:18.83#ibcon#read 4, iclass 4, count 2 2006.210.07:20:18.83#ibcon#about to read 5, iclass 4, count 2 2006.210.07:20:18.83#ibcon#read 5, iclass 4, count 2 2006.210.07:20:18.83#ibcon#about to read 6, iclass 4, count 2 2006.210.07:20:18.83#ibcon#read 6, iclass 4, count 2 2006.210.07:20:18.83#ibcon#end of sib2, iclass 4, count 2 2006.210.07:20:18.83#ibcon#*after write, iclass 4, count 2 2006.210.07:20:18.83#ibcon#*before return 0, iclass 4, count 2 2006.210.07:20:18.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:20:18.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:20:18.83#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:20:18.83#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:18.83#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:20:18.95#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:20:18.95#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:20:18.95#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:20:18.95#ibcon#first serial, iclass 4, count 0 2006.210.07:20:18.95#ibcon#enter sib2, iclass 4, count 0 2006.210.07:20:18.95#ibcon#flushed, iclass 4, count 0 2006.210.07:20:18.95#ibcon#about to write, iclass 4, count 0 2006.210.07:20:18.95#ibcon#wrote, iclass 4, count 0 2006.210.07:20:18.95#ibcon#about to read 3, iclass 4, count 0 2006.210.07:20:18.97#ibcon#read 3, iclass 4, count 0 2006.210.07:20:18.97#ibcon#about to read 4, iclass 4, count 0 2006.210.07:20:18.97#ibcon#read 4, iclass 4, count 0 2006.210.07:20:18.97#ibcon#about to read 5, iclass 4, count 0 2006.210.07:20:18.97#ibcon#read 5, iclass 4, count 0 2006.210.07:20:18.97#ibcon#about to read 6, iclass 4, count 0 2006.210.07:20:18.97#ibcon#read 6, iclass 4, count 0 2006.210.07:20:18.97#ibcon#end of sib2, iclass 4, count 0 2006.210.07:20:18.97#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:20:18.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:20:18.97#ibcon#[25=USB\r\n] 2006.210.07:20:18.97#ibcon#*before write, iclass 4, count 0 2006.210.07:20:18.97#ibcon#enter sib2, iclass 4, count 0 2006.210.07:20:18.97#ibcon#flushed, iclass 4, count 0 2006.210.07:20:18.97#ibcon#about to write, iclass 4, count 0 2006.210.07:20:18.97#ibcon#wrote, iclass 4, count 0 2006.210.07:20:18.97#ibcon#about to read 3, iclass 4, count 0 2006.210.07:20:19.00#ibcon#read 3, iclass 4, count 0 2006.210.07:20:19.00#ibcon#about to read 4, iclass 4, count 0 2006.210.07:20:19.00#ibcon#read 4, iclass 4, count 0 2006.210.07:20:19.00#ibcon#about to read 5, iclass 4, count 0 2006.210.07:20:19.00#ibcon#read 5, iclass 4, count 0 2006.210.07:20:19.00#ibcon#about to read 6, iclass 4, count 0 2006.210.07:20:19.00#ibcon#read 6, iclass 4, count 0 2006.210.07:20:19.00#ibcon#end of sib2, iclass 4, count 0 2006.210.07:20:19.00#ibcon#*after write, iclass 4, count 0 2006.210.07:20:19.00#ibcon#*before return 0, iclass 4, count 0 2006.210.07:20:19.00#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:20:19.00#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:20:19.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:20:19.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:20:19.00$vc4f8/valo=8,852.99 2006.210.07:20:19.00#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:20:19.00#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:20:19.00#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:19.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:20:19.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:20:19.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:20:19.00#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:20:19.00#ibcon#first serial, iclass 6, count 0 2006.210.07:20:19.00#ibcon#enter sib2, iclass 6, count 0 2006.210.07:20:19.00#ibcon#flushed, iclass 6, count 0 2006.210.07:20:19.00#ibcon#about to write, iclass 6, count 0 2006.210.07:20:19.00#ibcon#wrote, iclass 6, count 0 2006.210.07:20:19.00#ibcon#about to read 3, iclass 6, count 0 2006.210.07:20:19.02#ibcon#read 3, iclass 6, count 0 2006.210.07:20:19.02#ibcon#about to read 4, iclass 6, count 0 2006.210.07:20:19.02#ibcon#read 4, iclass 6, count 0 2006.210.07:20:19.02#ibcon#about to read 5, iclass 6, count 0 2006.210.07:20:19.02#ibcon#read 5, iclass 6, count 0 2006.210.07:20:19.02#ibcon#about to read 6, iclass 6, count 0 2006.210.07:20:19.02#ibcon#read 6, iclass 6, count 0 2006.210.07:20:19.02#ibcon#end of sib2, iclass 6, count 0 2006.210.07:20:19.02#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:20:19.02#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:20:19.02#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:20:19.02#ibcon#*before write, iclass 6, count 0 2006.210.07:20:19.02#ibcon#enter sib2, iclass 6, count 0 2006.210.07:20:19.02#ibcon#flushed, iclass 6, count 0 2006.210.07:20:19.02#ibcon#about to write, iclass 6, count 0 2006.210.07:20:19.02#ibcon#wrote, iclass 6, count 0 2006.210.07:20:19.02#ibcon#about to read 3, iclass 6, count 0 2006.210.07:20:19.06#ibcon#read 3, iclass 6, count 0 2006.210.07:20:19.06#ibcon#about to read 4, iclass 6, count 0 2006.210.07:20:19.06#ibcon#read 4, iclass 6, count 0 2006.210.07:20:19.06#ibcon#about to read 5, iclass 6, count 0 2006.210.07:20:19.06#ibcon#read 5, iclass 6, count 0 2006.210.07:20:19.06#ibcon#about to read 6, iclass 6, count 0 2006.210.07:20:19.06#ibcon#read 6, iclass 6, count 0 2006.210.07:20:19.06#ibcon#end of sib2, iclass 6, count 0 2006.210.07:20:19.06#ibcon#*after write, iclass 6, count 0 2006.210.07:20:19.06#ibcon#*before return 0, iclass 6, count 0 2006.210.07:20:19.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:20:19.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:20:19.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:20:19.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:20:19.06$vc4f8/va=8,7 2006.210.07:20:19.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:20:19.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:20:19.06#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:19.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:20:19.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:20:19.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:20:19.12#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:20:19.12#ibcon#first serial, iclass 10, count 2 2006.210.07:20:19.12#ibcon#enter sib2, iclass 10, count 2 2006.210.07:20:19.12#ibcon#flushed, iclass 10, count 2 2006.210.07:20:19.12#ibcon#about to write, iclass 10, count 2 2006.210.07:20:19.12#ibcon#wrote, iclass 10, count 2 2006.210.07:20:19.12#ibcon#about to read 3, iclass 10, count 2 2006.210.07:20:19.14#ibcon#read 3, iclass 10, count 2 2006.210.07:20:19.14#ibcon#about to read 4, iclass 10, count 2 2006.210.07:20:19.14#ibcon#read 4, iclass 10, count 2 2006.210.07:20:19.14#ibcon#about to read 5, iclass 10, count 2 2006.210.07:20:19.14#ibcon#read 5, iclass 10, count 2 2006.210.07:20:19.14#ibcon#about to read 6, iclass 10, count 2 2006.210.07:20:19.14#ibcon#read 6, iclass 10, count 2 2006.210.07:20:19.14#ibcon#end of sib2, iclass 10, count 2 2006.210.07:20:19.14#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:20:19.14#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:20:19.14#ibcon#[25=AT08-07\r\n] 2006.210.07:20:19.14#ibcon#*before write, iclass 10, count 2 2006.210.07:20:19.14#ibcon#enter sib2, iclass 10, count 2 2006.210.07:20:19.14#ibcon#flushed, iclass 10, count 2 2006.210.07:20:19.14#ibcon#about to write, iclass 10, count 2 2006.210.07:20:19.14#ibcon#wrote, iclass 10, count 2 2006.210.07:20:19.14#ibcon#about to read 3, iclass 10, count 2 2006.210.07:20:19.17#ibcon#read 3, iclass 10, count 2 2006.210.07:20:19.17#ibcon#about to read 4, iclass 10, count 2 2006.210.07:20:19.17#ibcon#read 4, iclass 10, count 2 2006.210.07:20:19.17#ibcon#about to read 5, iclass 10, count 2 2006.210.07:20:19.17#ibcon#read 5, iclass 10, count 2 2006.210.07:20:19.17#ibcon#about to read 6, iclass 10, count 2 2006.210.07:20:19.17#ibcon#read 6, iclass 10, count 2 2006.210.07:20:19.17#ibcon#end of sib2, iclass 10, count 2 2006.210.07:20:19.17#ibcon#*after write, iclass 10, count 2 2006.210.07:20:19.17#ibcon#*before return 0, iclass 10, count 2 2006.210.07:20:19.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:20:19.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:20:19.17#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:20:19.17#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:19.17#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:20:19.29#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:20:19.29#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:20:19.29#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:20:19.29#ibcon#first serial, iclass 10, count 0 2006.210.07:20:19.29#ibcon#enter sib2, iclass 10, count 0 2006.210.07:20:19.29#ibcon#flushed, iclass 10, count 0 2006.210.07:20:19.29#ibcon#about to write, iclass 10, count 0 2006.210.07:20:19.29#ibcon#wrote, iclass 10, count 0 2006.210.07:20:19.29#ibcon#about to read 3, iclass 10, count 0 2006.210.07:20:19.31#ibcon#read 3, iclass 10, count 0 2006.210.07:20:19.31#ibcon#about to read 4, iclass 10, count 0 2006.210.07:20:19.31#ibcon#read 4, iclass 10, count 0 2006.210.07:20:19.31#ibcon#about to read 5, iclass 10, count 0 2006.210.07:20:19.31#ibcon#read 5, iclass 10, count 0 2006.210.07:20:19.31#ibcon#about to read 6, iclass 10, count 0 2006.210.07:20:19.31#ibcon#read 6, iclass 10, count 0 2006.210.07:20:19.31#ibcon#end of sib2, iclass 10, count 0 2006.210.07:20:19.31#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:20:19.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:20:19.31#ibcon#[25=USB\r\n] 2006.210.07:20:19.31#ibcon#*before write, iclass 10, count 0 2006.210.07:20:19.31#ibcon#enter sib2, iclass 10, count 0 2006.210.07:20:19.31#ibcon#flushed, iclass 10, count 0 2006.210.07:20:19.31#ibcon#about to write, iclass 10, count 0 2006.210.07:20:19.31#ibcon#wrote, iclass 10, count 0 2006.210.07:20:19.31#ibcon#about to read 3, iclass 10, count 0 2006.210.07:20:19.34#ibcon#read 3, iclass 10, count 0 2006.210.07:20:19.34#ibcon#about to read 4, iclass 10, count 0 2006.210.07:20:19.34#ibcon#read 4, iclass 10, count 0 2006.210.07:20:19.34#ibcon#about to read 5, iclass 10, count 0 2006.210.07:20:19.34#ibcon#read 5, iclass 10, count 0 2006.210.07:20:19.34#ibcon#about to read 6, iclass 10, count 0 2006.210.07:20:19.34#ibcon#read 6, iclass 10, count 0 2006.210.07:20:19.34#ibcon#end of sib2, iclass 10, count 0 2006.210.07:20:19.34#ibcon#*after write, iclass 10, count 0 2006.210.07:20:19.34#ibcon#*before return 0, iclass 10, count 0 2006.210.07:20:19.34#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:20:19.34#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:20:19.34#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:20:19.34#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:20:19.34$vc4f8/vblo=1,632.99 2006.210.07:20:19.34#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:20:19.34#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:20:19.34#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:19.34#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:20:19.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:20:19.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:20:19.34#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:20:19.34#ibcon#first serial, iclass 12, count 0 2006.210.07:20:19.34#ibcon#enter sib2, iclass 12, count 0 2006.210.07:20:19.34#ibcon#flushed, iclass 12, count 0 2006.210.07:20:19.34#ibcon#about to write, iclass 12, count 0 2006.210.07:20:19.34#ibcon#wrote, iclass 12, count 0 2006.210.07:20:19.34#ibcon#about to read 3, iclass 12, count 0 2006.210.07:20:19.36#ibcon#read 3, iclass 12, count 0 2006.210.07:20:19.36#ibcon#about to read 4, iclass 12, count 0 2006.210.07:20:19.36#ibcon#read 4, iclass 12, count 0 2006.210.07:20:19.36#ibcon#about to read 5, iclass 12, count 0 2006.210.07:20:19.36#ibcon#read 5, iclass 12, count 0 2006.210.07:20:19.36#ibcon#about to read 6, iclass 12, count 0 2006.210.07:20:19.36#ibcon#read 6, iclass 12, count 0 2006.210.07:20:19.36#ibcon#end of sib2, iclass 12, count 0 2006.210.07:20:19.36#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:20:19.36#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:20:19.36#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:20:19.36#ibcon#*before write, iclass 12, count 0 2006.210.07:20:19.36#ibcon#enter sib2, iclass 12, count 0 2006.210.07:20:19.36#ibcon#flushed, iclass 12, count 0 2006.210.07:20:19.36#ibcon#about to write, iclass 12, count 0 2006.210.07:20:19.36#ibcon#wrote, iclass 12, count 0 2006.210.07:20:19.36#ibcon#about to read 3, iclass 12, count 0 2006.210.07:20:19.42#ibcon#read 3, iclass 12, count 0 2006.210.07:20:19.42#ibcon#about to read 4, iclass 12, count 0 2006.210.07:20:19.42#ibcon#read 4, iclass 12, count 0 2006.210.07:20:19.42#ibcon#about to read 5, iclass 12, count 0 2006.210.07:20:19.42#ibcon#read 5, iclass 12, count 0 2006.210.07:20:19.42#ibcon#about to read 6, iclass 12, count 0 2006.210.07:20:19.42#ibcon#read 6, iclass 12, count 0 2006.210.07:20:19.42#ibcon#end of sib2, iclass 12, count 0 2006.210.07:20:19.42#ibcon#*after write, iclass 12, count 0 2006.210.07:20:19.42#ibcon#*before return 0, iclass 12, count 0 2006.210.07:20:19.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:20:19.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:20:19.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:20:19.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:20:19.42$vc4f8/vb=1,4 2006.210.07:20:19.42#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:20:19.42#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:20:19.42#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:19.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:20:19.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:20:19.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:20:19.42#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:20:19.42#ibcon#first serial, iclass 14, count 2 2006.210.07:20:19.42#ibcon#enter sib2, iclass 14, count 2 2006.210.07:20:19.42#ibcon#flushed, iclass 14, count 2 2006.210.07:20:19.42#ibcon#about to write, iclass 14, count 2 2006.210.07:20:19.42#ibcon#wrote, iclass 14, count 2 2006.210.07:20:19.42#ibcon#about to read 3, iclass 14, count 2 2006.210.07:20:19.44#ibcon#read 3, iclass 14, count 2 2006.210.07:20:19.44#ibcon#about to read 4, iclass 14, count 2 2006.210.07:20:19.44#ibcon#read 4, iclass 14, count 2 2006.210.07:20:19.44#ibcon#about to read 5, iclass 14, count 2 2006.210.07:20:19.44#ibcon#read 5, iclass 14, count 2 2006.210.07:20:19.44#ibcon#about to read 6, iclass 14, count 2 2006.210.07:20:19.44#ibcon#read 6, iclass 14, count 2 2006.210.07:20:19.44#ibcon#end of sib2, iclass 14, count 2 2006.210.07:20:19.44#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:20:19.44#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:20:19.44#ibcon#[27=AT01-04\r\n] 2006.210.07:20:19.44#ibcon#*before write, iclass 14, count 2 2006.210.07:20:19.44#ibcon#enter sib2, iclass 14, count 2 2006.210.07:20:19.44#ibcon#flushed, iclass 14, count 2 2006.210.07:20:19.44#ibcon#about to write, iclass 14, count 2 2006.210.07:20:19.44#ibcon#wrote, iclass 14, count 2 2006.210.07:20:19.44#ibcon#about to read 3, iclass 14, count 2 2006.210.07:20:19.47#ibcon#read 3, iclass 14, count 2 2006.210.07:20:19.47#ibcon#about to read 4, iclass 14, count 2 2006.210.07:20:19.47#ibcon#read 4, iclass 14, count 2 2006.210.07:20:19.47#ibcon#about to read 5, iclass 14, count 2 2006.210.07:20:19.47#ibcon#read 5, iclass 14, count 2 2006.210.07:20:19.47#ibcon#about to read 6, iclass 14, count 2 2006.210.07:20:19.47#ibcon#read 6, iclass 14, count 2 2006.210.07:20:19.47#ibcon#end of sib2, iclass 14, count 2 2006.210.07:20:19.47#ibcon#*after write, iclass 14, count 2 2006.210.07:20:19.47#ibcon#*before return 0, iclass 14, count 2 2006.210.07:20:19.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:20:19.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:20:19.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:20:19.47#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:19.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:20:19.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:20:19.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:20:19.59#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:20:19.59#ibcon#first serial, iclass 14, count 0 2006.210.07:20:19.59#ibcon#enter sib2, iclass 14, count 0 2006.210.07:20:19.59#ibcon#flushed, iclass 14, count 0 2006.210.07:20:19.59#ibcon#about to write, iclass 14, count 0 2006.210.07:20:19.59#ibcon#wrote, iclass 14, count 0 2006.210.07:20:19.59#ibcon#about to read 3, iclass 14, count 0 2006.210.07:20:19.61#ibcon#read 3, iclass 14, count 0 2006.210.07:20:19.61#ibcon#about to read 4, iclass 14, count 0 2006.210.07:20:19.61#ibcon#read 4, iclass 14, count 0 2006.210.07:20:19.61#ibcon#about to read 5, iclass 14, count 0 2006.210.07:20:19.61#ibcon#read 5, iclass 14, count 0 2006.210.07:20:19.61#ibcon#about to read 6, iclass 14, count 0 2006.210.07:20:19.61#ibcon#read 6, iclass 14, count 0 2006.210.07:20:19.61#ibcon#end of sib2, iclass 14, count 0 2006.210.07:20:19.61#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:20:19.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:20:19.61#ibcon#[27=USB\r\n] 2006.210.07:20:19.61#ibcon#*before write, iclass 14, count 0 2006.210.07:20:19.61#ibcon#enter sib2, iclass 14, count 0 2006.210.07:20:19.61#ibcon#flushed, iclass 14, count 0 2006.210.07:20:19.61#ibcon#about to write, iclass 14, count 0 2006.210.07:20:19.61#ibcon#wrote, iclass 14, count 0 2006.210.07:20:19.61#ibcon#about to read 3, iclass 14, count 0 2006.210.07:20:19.64#ibcon#read 3, iclass 14, count 0 2006.210.07:20:19.64#ibcon#about to read 4, iclass 14, count 0 2006.210.07:20:19.64#ibcon#read 4, iclass 14, count 0 2006.210.07:20:19.64#ibcon#about to read 5, iclass 14, count 0 2006.210.07:20:19.64#ibcon#read 5, iclass 14, count 0 2006.210.07:20:19.64#ibcon#about to read 6, iclass 14, count 0 2006.210.07:20:19.64#ibcon#read 6, iclass 14, count 0 2006.210.07:20:19.64#ibcon#end of sib2, iclass 14, count 0 2006.210.07:20:19.64#ibcon#*after write, iclass 14, count 0 2006.210.07:20:19.64#ibcon#*before return 0, iclass 14, count 0 2006.210.07:20:19.64#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:20:19.64#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:20:19.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:20:19.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:20:19.64$vc4f8/vblo=2,640.99 2006.210.07:20:19.64#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:20:19.64#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:20:19.64#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:19.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:19.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:19.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:19.64#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:20:19.64#ibcon#first serial, iclass 16, count 0 2006.210.07:20:19.64#ibcon#enter sib2, iclass 16, count 0 2006.210.07:20:19.64#ibcon#flushed, iclass 16, count 0 2006.210.07:20:19.64#ibcon#about to write, iclass 16, count 0 2006.210.07:20:19.64#ibcon#wrote, iclass 16, count 0 2006.210.07:20:19.64#ibcon#about to read 3, iclass 16, count 0 2006.210.07:20:19.66#ibcon#read 3, iclass 16, count 0 2006.210.07:20:19.66#ibcon#about to read 4, iclass 16, count 0 2006.210.07:20:19.66#ibcon#read 4, iclass 16, count 0 2006.210.07:20:19.66#ibcon#about to read 5, iclass 16, count 0 2006.210.07:20:19.66#ibcon#read 5, iclass 16, count 0 2006.210.07:20:19.66#ibcon#about to read 6, iclass 16, count 0 2006.210.07:20:19.66#ibcon#read 6, iclass 16, count 0 2006.210.07:20:19.66#ibcon#end of sib2, iclass 16, count 0 2006.210.07:20:19.66#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:20:19.66#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:20:19.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:20:19.66#ibcon#*before write, iclass 16, count 0 2006.210.07:20:19.66#ibcon#enter sib2, iclass 16, count 0 2006.210.07:20:19.66#ibcon#flushed, iclass 16, count 0 2006.210.07:20:19.66#ibcon#about to write, iclass 16, count 0 2006.210.07:20:19.66#ibcon#wrote, iclass 16, count 0 2006.210.07:20:19.66#ibcon#about to read 3, iclass 16, count 0 2006.210.07:20:19.70#ibcon#read 3, iclass 16, count 0 2006.210.07:20:19.70#ibcon#about to read 4, iclass 16, count 0 2006.210.07:20:19.70#ibcon#read 4, iclass 16, count 0 2006.210.07:20:19.70#ibcon#about to read 5, iclass 16, count 0 2006.210.07:20:19.70#ibcon#read 5, iclass 16, count 0 2006.210.07:20:19.70#ibcon#about to read 6, iclass 16, count 0 2006.210.07:20:19.70#ibcon#read 6, iclass 16, count 0 2006.210.07:20:19.70#ibcon#end of sib2, iclass 16, count 0 2006.210.07:20:19.70#ibcon#*after write, iclass 16, count 0 2006.210.07:20:19.70#ibcon#*before return 0, iclass 16, count 0 2006.210.07:20:19.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:19.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:20:19.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:20:19.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:20:19.70$vc4f8/vb=2,4 2006.210.07:20:19.70#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:20:19.70#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:20:19.70#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:19.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:19.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:19.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:19.76#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:20:19.76#ibcon#first serial, iclass 18, count 2 2006.210.07:20:19.76#ibcon#enter sib2, iclass 18, count 2 2006.210.07:20:19.76#ibcon#flushed, iclass 18, count 2 2006.210.07:20:19.76#ibcon#about to write, iclass 18, count 2 2006.210.07:20:19.76#ibcon#wrote, iclass 18, count 2 2006.210.07:20:19.76#ibcon#about to read 3, iclass 18, count 2 2006.210.07:20:19.78#ibcon#read 3, iclass 18, count 2 2006.210.07:20:19.78#ibcon#about to read 4, iclass 18, count 2 2006.210.07:20:19.78#ibcon#read 4, iclass 18, count 2 2006.210.07:20:19.78#ibcon#about to read 5, iclass 18, count 2 2006.210.07:20:19.78#ibcon#read 5, iclass 18, count 2 2006.210.07:20:19.78#ibcon#about to read 6, iclass 18, count 2 2006.210.07:20:19.78#ibcon#read 6, iclass 18, count 2 2006.210.07:20:19.78#ibcon#end of sib2, iclass 18, count 2 2006.210.07:20:19.78#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:20:19.78#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:20:19.78#ibcon#[27=AT02-04\r\n] 2006.210.07:20:19.78#ibcon#*before write, iclass 18, count 2 2006.210.07:20:19.78#ibcon#enter sib2, iclass 18, count 2 2006.210.07:20:19.78#ibcon#flushed, iclass 18, count 2 2006.210.07:20:19.78#ibcon#about to write, iclass 18, count 2 2006.210.07:20:19.78#ibcon#wrote, iclass 18, count 2 2006.210.07:20:19.78#ibcon#about to read 3, iclass 18, count 2 2006.210.07:20:19.81#ibcon#read 3, iclass 18, count 2 2006.210.07:20:19.81#ibcon#about to read 4, iclass 18, count 2 2006.210.07:20:19.81#ibcon#read 4, iclass 18, count 2 2006.210.07:20:19.81#ibcon#about to read 5, iclass 18, count 2 2006.210.07:20:19.81#ibcon#read 5, iclass 18, count 2 2006.210.07:20:19.81#ibcon#about to read 6, iclass 18, count 2 2006.210.07:20:19.81#ibcon#read 6, iclass 18, count 2 2006.210.07:20:19.81#ibcon#end of sib2, iclass 18, count 2 2006.210.07:20:19.81#ibcon#*after write, iclass 18, count 2 2006.210.07:20:19.81#ibcon#*before return 0, iclass 18, count 2 2006.210.07:20:19.81#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:19.81#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:20:19.81#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:20:19.81#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:19.81#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:19.93#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:19.93#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:19.93#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:20:19.93#ibcon#first serial, iclass 18, count 0 2006.210.07:20:19.93#ibcon#enter sib2, iclass 18, count 0 2006.210.07:20:19.93#ibcon#flushed, iclass 18, count 0 2006.210.07:20:19.93#ibcon#about to write, iclass 18, count 0 2006.210.07:20:19.93#ibcon#wrote, iclass 18, count 0 2006.210.07:20:19.93#ibcon#about to read 3, iclass 18, count 0 2006.210.07:20:19.95#ibcon#read 3, iclass 18, count 0 2006.210.07:20:19.95#ibcon#about to read 4, iclass 18, count 0 2006.210.07:20:19.95#ibcon#read 4, iclass 18, count 0 2006.210.07:20:19.95#ibcon#about to read 5, iclass 18, count 0 2006.210.07:20:19.95#ibcon#read 5, iclass 18, count 0 2006.210.07:20:19.95#ibcon#about to read 6, iclass 18, count 0 2006.210.07:20:19.95#ibcon#read 6, iclass 18, count 0 2006.210.07:20:19.95#ibcon#end of sib2, iclass 18, count 0 2006.210.07:20:19.95#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:20:19.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:20:19.95#ibcon#[27=USB\r\n] 2006.210.07:20:19.95#ibcon#*before write, iclass 18, count 0 2006.210.07:20:19.95#ibcon#enter sib2, iclass 18, count 0 2006.210.07:20:19.95#ibcon#flushed, iclass 18, count 0 2006.210.07:20:19.95#ibcon#about to write, iclass 18, count 0 2006.210.07:20:19.95#ibcon#wrote, iclass 18, count 0 2006.210.07:20:19.95#ibcon#about to read 3, iclass 18, count 0 2006.210.07:20:19.98#ibcon#read 3, iclass 18, count 0 2006.210.07:20:19.98#ibcon#about to read 4, iclass 18, count 0 2006.210.07:20:19.98#ibcon#read 4, iclass 18, count 0 2006.210.07:20:19.98#ibcon#about to read 5, iclass 18, count 0 2006.210.07:20:19.98#ibcon#read 5, iclass 18, count 0 2006.210.07:20:19.98#ibcon#about to read 6, iclass 18, count 0 2006.210.07:20:19.98#ibcon#read 6, iclass 18, count 0 2006.210.07:20:19.98#ibcon#end of sib2, iclass 18, count 0 2006.210.07:20:19.98#ibcon#*after write, iclass 18, count 0 2006.210.07:20:19.98#ibcon#*before return 0, iclass 18, count 0 2006.210.07:20:19.98#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:19.98#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:20:19.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:20:19.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:20:19.98$vc4f8/vblo=3,656.99 2006.210.07:20:19.98#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:20:19.98#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:20:19.98#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:19.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:19.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:19.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:19.98#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:20:19.98#ibcon#first serial, iclass 20, count 0 2006.210.07:20:19.98#ibcon#enter sib2, iclass 20, count 0 2006.210.07:20:19.98#ibcon#flushed, iclass 20, count 0 2006.210.07:20:19.98#ibcon#about to write, iclass 20, count 0 2006.210.07:20:19.98#ibcon#wrote, iclass 20, count 0 2006.210.07:20:19.98#ibcon#about to read 3, iclass 20, count 0 2006.210.07:20:20.00#ibcon#read 3, iclass 20, count 0 2006.210.07:20:20.00#ibcon#about to read 4, iclass 20, count 0 2006.210.07:20:20.00#ibcon#read 4, iclass 20, count 0 2006.210.07:20:20.00#ibcon#about to read 5, iclass 20, count 0 2006.210.07:20:20.00#ibcon#read 5, iclass 20, count 0 2006.210.07:20:20.00#ibcon#about to read 6, iclass 20, count 0 2006.210.07:20:20.00#ibcon#read 6, iclass 20, count 0 2006.210.07:20:20.00#ibcon#end of sib2, iclass 20, count 0 2006.210.07:20:20.00#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:20:20.00#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:20:20.00#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:20:20.00#ibcon#*before write, iclass 20, count 0 2006.210.07:20:20.00#ibcon#enter sib2, iclass 20, count 0 2006.210.07:20:20.00#ibcon#flushed, iclass 20, count 0 2006.210.07:20:20.00#ibcon#about to write, iclass 20, count 0 2006.210.07:20:20.00#ibcon#wrote, iclass 20, count 0 2006.210.07:20:20.00#ibcon#about to read 3, iclass 20, count 0 2006.210.07:20:20.04#ibcon#read 3, iclass 20, count 0 2006.210.07:20:20.04#ibcon#about to read 4, iclass 20, count 0 2006.210.07:20:20.04#ibcon#read 4, iclass 20, count 0 2006.210.07:20:20.04#ibcon#about to read 5, iclass 20, count 0 2006.210.07:20:20.04#ibcon#read 5, iclass 20, count 0 2006.210.07:20:20.04#ibcon#about to read 6, iclass 20, count 0 2006.210.07:20:20.04#ibcon#read 6, iclass 20, count 0 2006.210.07:20:20.04#ibcon#end of sib2, iclass 20, count 0 2006.210.07:20:20.04#ibcon#*after write, iclass 20, count 0 2006.210.07:20:20.04#ibcon#*before return 0, iclass 20, count 0 2006.210.07:20:20.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:20.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:20:20.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:20:20.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:20:20.04$vc4f8/vb=3,3 2006.210.07:20:20.04#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:20:20.04#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:20:20.04#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:20.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:20.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:20.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:20.10#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:20:20.10#ibcon#first serial, iclass 22, count 2 2006.210.07:20:20.10#ibcon#enter sib2, iclass 22, count 2 2006.210.07:20:20.10#ibcon#flushed, iclass 22, count 2 2006.210.07:20:20.10#ibcon#about to write, iclass 22, count 2 2006.210.07:20:20.10#ibcon#wrote, iclass 22, count 2 2006.210.07:20:20.10#ibcon#about to read 3, iclass 22, count 2 2006.210.07:20:20.12#ibcon#read 3, iclass 22, count 2 2006.210.07:20:20.12#ibcon#about to read 4, iclass 22, count 2 2006.210.07:20:20.12#ibcon#read 4, iclass 22, count 2 2006.210.07:20:20.12#ibcon#about to read 5, iclass 22, count 2 2006.210.07:20:20.12#ibcon#read 5, iclass 22, count 2 2006.210.07:20:20.12#ibcon#about to read 6, iclass 22, count 2 2006.210.07:20:20.12#ibcon#read 6, iclass 22, count 2 2006.210.07:20:20.12#ibcon#end of sib2, iclass 22, count 2 2006.210.07:20:20.12#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:20:20.12#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:20:20.12#ibcon#[27=AT03-03\r\n] 2006.210.07:20:20.12#ibcon#*before write, iclass 22, count 2 2006.210.07:20:20.12#ibcon#enter sib2, iclass 22, count 2 2006.210.07:20:20.12#ibcon#flushed, iclass 22, count 2 2006.210.07:20:20.12#ibcon#about to write, iclass 22, count 2 2006.210.07:20:20.12#ibcon#wrote, iclass 22, count 2 2006.210.07:20:20.12#ibcon#about to read 3, iclass 22, count 2 2006.210.07:20:20.15#ibcon#read 3, iclass 22, count 2 2006.210.07:20:20.15#ibcon#about to read 4, iclass 22, count 2 2006.210.07:20:20.15#ibcon#read 4, iclass 22, count 2 2006.210.07:20:20.15#ibcon#about to read 5, iclass 22, count 2 2006.210.07:20:20.15#ibcon#read 5, iclass 22, count 2 2006.210.07:20:20.15#ibcon#about to read 6, iclass 22, count 2 2006.210.07:20:20.15#ibcon#read 6, iclass 22, count 2 2006.210.07:20:20.15#ibcon#end of sib2, iclass 22, count 2 2006.210.07:20:20.15#ibcon#*after write, iclass 22, count 2 2006.210.07:20:20.15#ibcon#*before return 0, iclass 22, count 2 2006.210.07:20:20.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:20.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:20:20.15#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:20:20.15#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:20.15#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:20.27#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:20.27#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:20.27#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:20:20.27#ibcon#first serial, iclass 22, count 0 2006.210.07:20:20.27#ibcon#enter sib2, iclass 22, count 0 2006.210.07:20:20.27#ibcon#flushed, iclass 22, count 0 2006.210.07:20:20.27#ibcon#about to write, iclass 22, count 0 2006.210.07:20:20.27#ibcon#wrote, iclass 22, count 0 2006.210.07:20:20.27#ibcon#about to read 3, iclass 22, count 0 2006.210.07:20:20.29#ibcon#read 3, iclass 22, count 0 2006.210.07:20:20.29#ibcon#about to read 4, iclass 22, count 0 2006.210.07:20:20.29#ibcon#read 4, iclass 22, count 0 2006.210.07:20:20.29#ibcon#about to read 5, iclass 22, count 0 2006.210.07:20:20.29#ibcon#read 5, iclass 22, count 0 2006.210.07:20:20.29#ibcon#about to read 6, iclass 22, count 0 2006.210.07:20:20.29#ibcon#read 6, iclass 22, count 0 2006.210.07:20:20.29#ibcon#end of sib2, iclass 22, count 0 2006.210.07:20:20.29#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:20:20.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:20:20.29#ibcon#[27=USB\r\n] 2006.210.07:20:20.29#ibcon#*before write, iclass 22, count 0 2006.210.07:20:20.29#ibcon#enter sib2, iclass 22, count 0 2006.210.07:20:20.29#ibcon#flushed, iclass 22, count 0 2006.210.07:20:20.29#ibcon#about to write, iclass 22, count 0 2006.210.07:20:20.29#ibcon#wrote, iclass 22, count 0 2006.210.07:20:20.29#ibcon#about to read 3, iclass 22, count 0 2006.210.07:20:20.32#ibcon#read 3, iclass 22, count 0 2006.210.07:20:20.32#ibcon#about to read 4, iclass 22, count 0 2006.210.07:20:20.32#ibcon#read 4, iclass 22, count 0 2006.210.07:20:20.32#ibcon#about to read 5, iclass 22, count 0 2006.210.07:20:20.32#ibcon#read 5, iclass 22, count 0 2006.210.07:20:20.32#ibcon#about to read 6, iclass 22, count 0 2006.210.07:20:20.32#ibcon#read 6, iclass 22, count 0 2006.210.07:20:20.32#ibcon#end of sib2, iclass 22, count 0 2006.210.07:20:20.32#ibcon#*after write, iclass 22, count 0 2006.210.07:20:20.32#ibcon#*before return 0, iclass 22, count 0 2006.210.07:20:20.32#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:20.32#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:20:20.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:20:20.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:20:20.32$vc4f8/vblo=4,712.99 2006.210.07:20:20.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:20:20.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:20:20.32#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:20.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:20.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:20.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:20.32#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:20:20.32#ibcon#first serial, iclass 24, count 0 2006.210.07:20:20.32#ibcon#enter sib2, iclass 24, count 0 2006.210.07:20:20.32#ibcon#flushed, iclass 24, count 0 2006.210.07:20:20.32#ibcon#about to write, iclass 24, count 0 2006.210.07:20:20.32#ibcon#wrote, iclass 24, count 0 2006.210.07:20:20.32#ibcon#about to read 3, iclass 24, count 0 2006.210.07:20:20.34#ibcon#read 3, iclass 24, count 0 2006.210.07:20:20.34#ibcon#about to read 4, iclass 24, count 0 2006.210.07:20:20.34#ibcon#read 4, iclass 24, count 0 2006.210.07:20:20.34#ibcon#about to read 5, iclass 24, count 0 2006.210.07:20:20.34#ibcon#read 5, iclass 24, count 0 2006.210.07:20:20.34#ibcon#about to read 6, iclass 24, count 0 2006.210.07:20:20.34#ibcon#read 6, iclass 24, count 0 2006.210.07:20:20.34#ibcon#end of sib2, iclass 24, count 0 2006.210.07:20:20.34#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:20:20.34#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:20:20.34#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:20:20.34#ibcon#*before write, iclass 24, count 0 2006.210.07:20:20.34#ibcon#enter sib2, iclass 24, count 0 2006.210.07:20:20.34#ibcon#flushed, iclass 24, count 0 2006.210.07:20:20.34#ibcon#about to write, iclass 24, count 0 2006.210.07:20:20.34#ibcon#wrote, iclass 24, count 0 2006.210.07:20:20.34#ibcon#about to read 3, iclass 24, count 0 2006.210.07:20:20.38#ibcon#read 3, iclass 24, count 0 2006.210.07:20:20.38#ibcon#about to read 4, iclass 24, count 0 2006.210.07:20:20.38#ibcon#read 4, iclass 24, count 0 2006.210.07:20:20.38#ibcon#about to read 5, iclass 24, count 0 2006.210.07:20:20.38#ibcon#read 5, iclass 24, count 0 2006.210.07:20:20.38#ibcon#about to read 6, iclass 24, count 0 2006.210.07:20:20.38#ibcon#read 6, iclass 24, count 0 2006.210.07:20:20.38#ibcon#end of sib2, iclass 24, count 0 2006.210.07:20:20.38#ibcon#*after write, iclass 24, count 0 2006.210.07:20:20.38#ibcon#*before return 0, iclass 24, count 0 2006.210.07:20:20.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:20.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:20:20.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:20:20.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:20:20.38$vc4f8/vb=4,3 2006.210.07:20:20.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:20:20.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:20:20.38#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:20.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:20.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:20.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:20.44#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:20:20.44#ibcon#first serial, iclass 26, count 2 2006.210.07:20:20.44#ibcon#enter sib2, iclass 26, count 2 2006.210.07:20:20.44#ibcon#flushed, iclass 26, count 2 2006.210.07:20:20.44#ibcon#about to write, iclass 26, count 2 2006.210.07:20:20.44#ibcon#wrote, iclass 26, count 2 2006.210.07:20:20.44#ibcon#about to read 3, iclass 26, count 2 2006.210.07:20:20.46#ibcon#read 3, iclass 26, count 2 2006.210.07:20:20.46#ibcon#about to read 4, iclass 26, count 2 2006.210.07:20:20.46#ibcon#read 4, iclass 26, count 2 2006.210.07:20:20.46#ibcon#about to read 5, iclass 26, count 2 2006.210.07:20:20.46#ibcon#read 5, iclass 26, count 2 2006.210.07:20:20.46#ibcon#about to read 6, iclass 26, count 2 2006.210.07:20:20.46#ibcon#read 6, iclass 26, count 2 2006.210.07:20:20.46#ibcon#end of sib2, iclass 26, count 2 2006.210.07:20:20.46#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:20:20.46#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:20:20.46#ibcon#[27=AT04-03\r\n] 2006.210.07:20:20.46#ibcon#*before write, iclass 26, count 2 2006.210.07:20:20.46#ibcon#enter sib2, iclass 26, count 2 2006.210.07:20:20.46#ibcon#flushed, iclass 26, count 2 2006.210.07:20:20.46#ibcon#about to write, iclass 26, count 2 2006.210.07:20:20.46#ibcon#wrote, iclass 26, count 2 2006.210.07:20:20.46#ibcon#about to read 3, iclass 26, count 2 2006.210.07:20:20.49#ibcon#read 3, iclass 26, count 2 2006.210.07:20:20.49#ibcon#about to read 4, iclass 26, count 2 2006.210.07:20:20.49#ibcon#read 4, iclass 26, count 2 2006.210.07:20:20.49#ibcon#about to read 5, iclass 26, count 2 2006.210.07:20:20.49#ibcon#read 5, iclass 26, count 2 2006.210.07:20:20.49#ibcon#about to read 6, iclass 26, count 2 2006.210.07:20:20.49#ibcon#read 6, iclass 26, count 2 2006.210.07:20:20.49#ibcon#end of sib2, iclass 26, count 2 2006.210.07:20:20.49#ibcon#*after write, iclass 26, count 2 2006.210.07:20:20.49#ibcon#*before return 0, iclass 26, count 2 2006.210.07:20:20.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:20.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:20:20.49#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:20:20.49#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:20.49#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:20.61#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:20.61#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:20.61#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:20:20.61#ibcon#first serial, iclass 26, count 0 2006.210.07:20:20.61#ibcon#enter sib2, iclass 26, count 0 2006.210.07:20:20.61#ibcon#flushed, iclass 26, count 0 2006.210.07:20:20.61#ibcon#about to write, iclass 26, count 0 2006.210.07:20:20.61#ibcon#wrote, iclass 26, count 0 2006.210.07:20:20.61#ibcon#about to read 3, iclass 26, count 0 2006.210.07:20:20.63#ibcon#read 3, iclass 26, count 0 2006.210.07:20:20.63#ibcon#about to read 4, iclass 26, count 0 2006.210.07:20:20.63#ibcon#read 4, iclass 26, count 0 2006.210.07:20:20.63#ibcon#about to read 5, iclass 26, count 0 2006.210.07:20:20.63#ibcon#read 5, iclass 26, count 0 2006.210.07:20:20.63#ibcon#about to read 6, iclass 26, count 0 2006.210.07:20:20.63#ibcon#read 6, iclass 26, count 0 2006.210.07:20:20.63#ibcon#end of sib2, iclass 26, count 0 2006.210.07:20:20.63#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:20:20.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:20:20.63#ibcon#[27=USB\r\n] 2006.210.07:20:20.63#ibcon#*before write, iclass 26, count 0 2006.210.07:20:20.63#ibcon#enter sib2, iclass 26, count 0 2006.210.07:20:20.63#ibcon#flushed, iclass 26, count 0 2006.210.07:20:20.63#ibcon#about to write, iclass 26, count 0 2006.210.07:20:20.63#ibcon#wrote, iclass 26, count 0 2006.210.07:20:20.63#ibcon#about to read 3, iclass 26, count 0 2006.210.07:20:20.66#ibcon#read 3, iclass 26, count 0 2006.210.07:20:20.66#ibcon#about to read 4, iclass 26, count 0 2006.210.07:20:20.66#ibcon#read 4, iclass 26, count 0 2006.210.07:20:20.66#ibcon#about to read 5, iclass 26, count 0 2006.210.07:20:20.66#ibcon#read 5, iclass 26, count 0 2006.210.07:20:20.66#ibcon#about to read 6, iclass 26, count 0 2006.210.07:20:20.66#ibcon#read 6, iclass 26, count 0 2006.210.07:20:20.66#ibcon#end of sib2, iclass 26, count 0 2006.210.07:20:20.66#ibcon#*after write, iclass 26, count 0 2006.210.07:20:20.66#ibcon#*before return 0, iclass 26, count 0 2006.210.07:20:20.66#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:20.66#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:20:20.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:20:20.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:20:20.66$vc4f8/vblo=5,744.99 2006.210.07:20:20.66#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:20:20.66#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:20:20.66#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:20.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:20.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:20.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:20.66#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:20:20.66#ibcon#first serial, iclass 28, count 0 2006.210.07:20:20.66#ibcon#enter sib2, iclass 28, count 0 2006.210.07:20:20.66#ibcon#flushed, iclass 28, count 0 2006.210.07:20:20.66#ibcon#about to write, iclass 28, count 0 2006.210.07:20:20.66#ibcon#wrote, iclass 28, count 0 2006.210.07:20:20.66#ibcon#about to read 3, iclass 28, count 0 2006.210.07:20:20.68#ibcon#read 3, iclass 28, count 0 2006.210.07:20:20.68#ibcon#about to read 4, iclass 28, count 0 2006.210.07:20:20.68#ibcon#read 4, iclass 28, count 0 2006.210.07:20:20.68#ibcon#about to read 5, iclass 28, count 0 2006.210.07:20:20.68#ibcon#read 5, iclass 28, count 0 2006.210.07:20:20.68#ibcon#about to read 6, iclass 28, count 0 2006.210.07:20:20.68#ibcon#read 6, iclass 28, count 0 2006.210.07:20:20.68#ibcon#end of sib2, iclass 28, count 0 2006.210.07:20:20.68#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:20:20.68#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:20:20.68#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:20:20.68#ibcon#*before write, iclass 28, count 0 2006.210.07:20:20.68#ibcon#enter sib2, iclass 28, count 0 2006.210.07:20:20.68#ibcon#flushed, iclass 28, count 0 2006.210.07:20:20.68#ibcon#about to write, iclass 28, count 0 2006.210.07:20:20.68#ibcon#wrote, iclass 28, count 0 2006.210.07:20:20.68#ibcon#about to read 3, iclass 28, count 0 2006.210.07:20:20.72#ibcon#read 3, iclass 28, count 0 2006.210.07:20:20.72#ibcon#about to read 4, iclass 28, count 0 2006.210.07:20:20.72#ibcon#read 4, iclass 28, count 0 2006.210.07:20:20.72#ibcon#about to read 5, iclass 28, count 0 2006.210.07:20:20.72#ibcon#read 5, iclass 28, count 0 2006.210.07:20:20.72#ibcon#about to read 6, iclass 28, count 0 2006.210.07:20:20.72#ibcon#read 6, iclass 28, count 0 2006.210.07:20:20.72#ibcon#end of sib2, iclass 28, count 0 2006.210.07:20:20.72#ibcon#*after write, iclass 28, count 0 2006.210.07:20:20.72#ibcon#*before return 0, iclass 28, count 0 2006.210.07:20:20.72#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:20.72#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:20:20.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:20:20.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:20:20.72$vc4f8/vb=5,3 2006.210.07:20:20.72#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:20:20.72#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:20:20.72#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:20.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:20.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:20.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:20.78#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:20:20.78#ibcon#first serial, iclass 30, count 2 2006.210.07:20:20.78#ibcon#enter sib2, iclass 30, count 2 2006.210.07:20:20.78#ibcon#flushed, iclass 30, count 2 2006.210.07:20:20.78#ibcon#about to write, iclass 30, count 2 2006.210.07:20:20.78#ibcon#wrote, iclass 30, count 2 2006.210.07:20:20.78#ibcon#about to read 3, iclass 30, count 2 2006.210.07:20:20.80#ibcon#read 3, iclass 30, count 2 2006.210.07:20:20.80#ibcon#about to read 4, iclass 30, count 2 2006.210.07:20:20.80#ibcon#read 4, iclass 30, count 2 2006.210.07:20:20.80#ibcon#about to read 5, iclass 30, count 2 2006.210.07:20:20.80#ibcon#read 5, iclass 30, count 2 2006.210.07:20:20.80#ibcon#about to read 6, iclass 30, count 2 2006.210.07:20:20.80#ibcon#read 6, iclass 30, count 2 2006.210.07:20:20.80#ibcon#end of sib2, iclass 30, count 2 2006.210.07:20:20.80#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:20:20.80#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:20:20.80#ibcon#[27=AT05-03\r\n] 2006.210.07:20:20.80#ibcon#*before write, iclass 30, count 2 2006.210.07:20:20.80#ibcon#enter sib2, iclass 30, count 2 2006.210.07:20:20.80#ibcon#flushed, iclass 30, count 2 2006.210.07:20:20.80#ibcon#about to write, iclass 30, count 2 2006.210.07:20:20.80#ibcon#wrote, iclass 30, count 2 2006.210.07:20:20.80#ibcon#about to read 3, iclass 30, count 2 2006.210.07:20:20.83#ibcon#read 3, iclass 30, count 2 2006.210.07:20:20.83#ibcon#about to read 4, iclass 30, count 2 2006.210.07:20:20.83#ibcon#read 4, iclass 30, count 2 2006.210.07:20:20.83#ibcon#about to read 5, iclass 30, count 2 2006.210.07:20:20.83#ibcon#read 5, iclass 30, count 2 2006.210.07:20:20.83#ibcon#about to read 6, iclass 30, count 2 2006.210.07:20:20.83#ibcon#read 6, iclass 30, count 2 2006.210.07:20:20.83#ibcon#end of sib2, iclass 30, count 2 2006.210.07:20:20.83#ibcon#*after write, iclass 30, count 2 2006.210.07:20:20.83#ibcon#*before return 0, iclass 30, count 2 2006.210.07:20:20.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:20.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:20:20.83#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:20:20.83#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:20.83#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:20.95#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:20.95#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:20.95#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:20:20.95#ibcon#first serial, iclass 30, count 0 2006.210.07:20:20.95#ibcon#enter sib2, iclass 30, count 0 2006.210.07:20:20.95#ibcon#flushed, iclass 30, count 0 2006.210.07:20:20.95#ibcon#about to write, iclass 30, count 0 2006.210.07:20:20.95#ibcon#wrote, iclass 30, count 0 2006.210.07:20:20.95#ibcon#about to read 3, iclass 30, count 0 2006.210.07:20:20.97#ibcon#read 3, iclass 30, count 0 2006.210.07:20:20.97#ibcon#about to read 4, iclass 30, count 0 2006.210.07:20:20.97#ibcon#read 4, iclass 30, count 0 2006.210.07:20:20.97#ibcon#about to read 5, iclass 30, count 0 2006.210.07:20:20.97#ibcon#read 5, iclass 30, count 0 2006.210.07:20:20.97#ibcon#about to read 6, iclass 30, count 0 2006.210.07:20:20.97#ibcon#read 6, iclass 30, count 0 2006.210.07:20:20.97#ibcon#end of sib2, iclass 30, count 0 2006.210.07:20:20.97#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:20:20.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:20:20.97#ibcon#[27=USB\r\n] 2006.210.07:20:20.97#ibcon#*before write, iclass 30, count 0 2006.210.07:20:20.97#ibcon#enter sib2, iclass 30, count 0 2006.210.07:20:20.97#ibcon#flushed, iclass 30, count 0 2006.210.07:20:20.97#ibcon#about to write, iclass 30, count 0 2006.210.07:20:20.97#ibcon#wrote, iclass 30, count 0 2006.210.07:20:20.97#ibcon#about to read 3, iclass 30, count 0 2006.210.07:20:21.00#ibcon#read 3, iclass 30, count 0 2006.210.07:20:21.00#ibcon#about to read 4, iclass 30, count 0 2006.210.07:20:21.00#ibcon#read 4, iclass 30, count 0 2006.210.07:20:21.00#ibcon#about to read 5, iclass 30, count 0 2006.210.07:20:21.00#ibcon#read 5, iclass 30, count 0 2006.210.07:20:21.00#ibcon#about to read 6, iclass 30, count 0 2006.210.07:20:21.00#ibcon#read 6, iclass 30, count 0 2006.210.07:20:21.00#ibcon#end of sib2, iclass 30, count 0 2006.210.07:20:21.00#ibcon#*after write, iclass 30, count 0 2006.210.07:20:21.00#ibcon#*before return 0, iclass 30, count 0 2006.210.07:20:21.00#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:21.00#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:20:21.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:20:21.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:20:21.00$vc4f8/vblo=6,752.99 2006.210.07:20:21.00#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:20:21.00#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:20:21.00#ibcon#ireg 17 cls_cnt 0 2006.210.07:20:21.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:21.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:21.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:21.00#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:20:21.00#ibcon#first serial, iclass 32, count 0 2006.210.07:20:21.00#ibcon#enter sib2, iclass 32, count 0 2006.210.07:20:21.00#ibcon#flushed, iclass 32, count 0 2006.210.07:20:21.00#ibcon#about to write, iclass 32, count 0 2006.210.07:20:21.00#ibcon#wrote, iclass 32, count 0 2006.210.07:20:21.00#ibcon#about to read 3, iclass 32, count 0 2006.210.07:20:21.02#ibcon#read 3, iclass 32, count 0 2006.210.07:20:21.02#ibcon#about to read 4, iclass 32, count 0 2006.210.07:20:21.02#ibcon#read 4, iclass 32, count 0 2006.210.07:20:21.02#ibcon#about to read 5, iclass 32, count 0 2006.210.07:20:21.02#ibcon#read 5, iclass 32, count 0 2006.210.07:20:21.02#ibcon#about to read 6, iclass 32, count 0 2006.210.07:20:21.02#ibcon#read 6, iclass 32, count 0 2006.210.07:20:21.02#ibcon#end of sib2, iclass 32, count 0 2006.210.07:20:21.02#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:20:21.02#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:20:21.02#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:20:21.02#ibcon#*before write, iclass 32, count 0 2006.210.07:20:21.02#ibcon#enter sib2, iclass 32, count 0 2006.210.07:20:21.02#ibcon#flushed, iclass 32, count 0 2006.210.07:20:21.02#ibcon#about to write, iclass 32, count 0 2006.210.07:20:21.02#ibcon#wrote, iclass 32, count 0 2006.210.07:20:21.02#ibcon#about to read 3, iclass 32, count 0 2006.210.07:20:21.06#ibcon#read 3, iclass 32, count 0 2006.210.07:20:21.06#ibcon#about to read 4, iclass 32, count 0 2006.210.07:20:21.06#ibcon#read 4, iclass 32, count 0 2006.210.07:20:21.06#ibcon#about to read 5, iclass 32, count 0 2006.210.07:20:21.06#ibcon#read 5, iclass 32, count 0 2006.210.07:20:21.06#ibcon#about to read 6, iclass 32, count 0 2006.210.07:20:21.06#ibcon#read 6, iclass 32, count 0 2006.210.07:20:21.06#ibcon#end of sib2, iclass 32, count 0 2006.210.07:20:21.06#ibcon#*after write, iclass 32, count 0 2006.210.07:20:21.06#ibcon#*before return 0, iclass 32, count 0 2006.210.07:20:21.06#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:21.06#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:20:21.06#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:20:21.06#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:20:21.06$vc4f8/vb=6,3 2006.210.07:20:21.06#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:20:21.06#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:20:21.06#ibcon#ireg 11 cls_cnt 2 2006.210.07:20:21.06#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:21.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:21.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:21.12#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:20:21.12#ibcon#first serial, iclass 34, count 2 2006.210.07:20:21.12#ibcon#enter sib2, iclass 34, count 2 2006.210.07:20:21.12#ibcon#flushed, iclass 34, count 2 2006.210.07:20:21.12#ibcon#about to write, iclass 34, count 2 2006.210.07:20:21.12#ibcon#wrote, iclass 34, count 2 2006.210.07:20:21.12#ibcon#about to read 3, iclass 34, count 2 2006.210.07:20:21.14#ibcon#read 3, iclass 34, count 2 2006.210.07:20:21.14#ibcon#about to read 4, iclass 34, count 2 2006.210.07:20:21.14#ibcon#read 4, iclass 34, count 2 2006.210.07:20:21.14#ibcon#about to read 5, iclass 34, count 2 2006.210.07:20:21.14#ibcon#read 5, iclass 34, count 2 2006.210.07:20:21.14#ibcon#about to read 6, iclass 34, count 2 2006.210.07:20:21.14#ibcon#read 6, iclass 34, count 2 2006.210.07:20:21.14#ibcon#end of sib2, iclass 34, count 2 2006.210.07:20:21.14#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:20:21.14#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:20:21.14#ibcon#[27=AT06-03\r\n] 2006.210.07:20:21.14#ibcon#*before write, iclass 34, count 2 2006.210.07:20:21.14#ibcon#enter sib2, iclass 34, count 2 2006.210.07:20:21.14#ibcon#flushed, iclass 34, count 2 2006.210.07:20:21.14#ibcon#about to write, iclass 34, count 2 2006.210.07:20:21.14#ibcon#wrote, iclass 34, count 2 2006.210.07:20:21.14#ibcon#about to read 3, iclass 34, count 2 2006.210.07:20:21.17#ibcon#read 3, iclass 34, count 2 2006.210.07:20:21.17#ibcon#about to read 4, iclass 34, count 2 2006.210.07:20:21.17#ibcon#read 4, iclass 34, count 2 2006.210.07:20:21.17#ibcon#about to read 5, iclass 34, count 2 2006.210.07:20:21.17#ibcon#read 5, iclass 34, count 2 2006.210.07:20:21.17#ibcon#about to read 6, iclass 34, count 2 2006.210.07:20:21.17#ibcon#read 6, iclass 34, count 2 2006.210.07:20:21.17#ibcon#end of sib2, iclass 34, count 2 2006.210.07:20:21.17#ibcon#*after write, iclass 34, count 2 2006.210.07:20:21.17#ibcon#*before return 0, iclass 34, count 2 2006.210.07:20:21.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:21.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:20:21.17#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:20:21.17#ibcon#ireg 7 cls_cnt 0 2006.210.07:20:21.17#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:21.29#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:21.29#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:21.29#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:20:21.29#ibcon#first serial, iclass 34, count 0 2006.210.07:20:21.29#ibcon#enter sib2, iclass 34, count 0 2006.210.07:20:21.29#ibcon#flushed, iclass 34, count 0 2006.210.07:20:21.29#ibcon#about to write, iclass 34, count 0 2006.210.07:20:21.29#ibcon#wrote, iclass 34, count 0 2006.210.07:20:21.29#ibcon#about to read 3, iclass 34, count 0 2006.210.07:20:21.31#ibcon#read 3, iclass 34, count 0 2006.210.07:20:21.31#ibcon#about to read 4, iclass 34, count 0 2006.210.07:20:21.31#ibcon#read 4, iclass 34, count 0 2006.210.07:20:21.31#ibcon#about to read 5, iclass 34, count 0 2006.210.07:20:21.31#ibcon#read 5, iclass 34, count 0 2006.210.07:20:21.31#ibcon#about to read 6, iclass 34, count 0 2006.210.07:20:21.31#ibcon#read 6, iclass 34, count 0 2006.210.07:20:21.31#ibcon#end of sib2, iclass 34, count 0 2006.210.07:20:21.31#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:20:21.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:20:21.31#ibcon#[27=USB\r\n] 2006.210.07:20:21.31#ibcon#*before write, iclass 34, count 0 2006.210.07:20:21.31#ibcon#enter sib2, iclass 34, count 0 2006.210.07:20:21.31#ibcon#flushed, iclass 34, count 0 2006.210.07:20:21.31#ibcon#about to write, iclass 34, count 0 2006.210.07:20:21.31#ibcon#wrote, iclass 34, count 0 2006.210.07:20:21.31#ibcon#about to read 3, iclass 34, count 0 2006.210.07:20:21.34#ibcon#read 3, iclass 34, count 0 2006.210.07:20:21.34#ibcon#about to read 4, iclass 34, count 0 2006.210.07:20:21.34#ibcon#read 4, iclass 34, count 0 2006.210.07:20:21.34#ibcon#about to read 5, iclass 34, count 0 2006.210.07:20:21.34#ibcon#read 5, iclass 34, count 0 2006.210.07:20:21.34#ibcon#about to read 6, iclass 34, count 0 2006.210.07:20:21.34#ibcon#read 6, iclass 34, count 0 2006.210.07:20:21.34#ibcon#end of sib2, iclass 34, count 0 2006.210.07:20:21.34#ibcon#*after write, iclass 34, count 0 2006.210.07:20:21.34#ibcon#*before return 0, iclass 34, count 0 2006.210.07:20:21.34#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:21.34#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:20:21.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:20:21.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:20:21.34$vc4f8/vabw=wide 2006.210.07:20:21.34#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:20:21.34#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:20:21.34#ibcon#ireg 8 cls_cnt 0 2006.210.07:20:21.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:21.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:21.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:21.34#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:20:21.34#ibcon#first serial, iclass 36, count 0 2006.210.07:20:21.34#ibcon#enter sib2, iclass 36, count 0 2006.210.07:20:21.34#ibcon#flushed, iclass 36, count 0 2006.210.07:20:21.34#ibcon#about to write, iclass 36, count 0 2006.210.07:20:21.34#ibcon#wrote, iclass 36, count 0 2006.210.07:20:21.34#ibcon#about to read 3, iclass 36, count 0 2006.210.07:20:21.36#ibcon#read 3, iclass 36, count 0 2006.210.07:20:21.36#ibcon#about to read 4, iclass 36, count 0 2006.210.07:20:21.36#ibcon#read 4, iclass 36, count 0 2006.210.07:20:21.36#ibcon#about to read 5, iclass 36, count 0 2006.210.07:20:21.36#ibcon#read 5, iclass 36, count 0 2006.210.07:20:21.36#ibcon#about to read 6, iclass 36, count 0 2006.210.07:20:21.36#ibcon#read 6, iclass 36, count 0 2006.210.07:20:21.36#ibcon#end of sib2, iclass 36, count 0 2006.210.07:20:21.36#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:20:21.36#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:20:21.36#ibcon#[25=BW32\r\n] 2006.210.07:20:21.36#ibcon#*before write, iclass 36, count 0 2006.210.07:20:21.36#ibcon#enter sib2, iclass 36, count 0 2006.210.07:20:21.36#ibcon#flushed, iclass 36, count 0 2006.210.07:20:21.36#ibcon#about to write, iclass 36, count 0 2006.210.07:20:21.36#ibcon#wrote, iclass 36, count 0 2006.210.07:20:21.36#ibcon#about to read 3, iclass 36, count 0 2006.210.07:20:21.39#ibcon#read 3, iclass 36, count 0 2006.210.07:20:21.39#ibcon#about to read 4, iclass 36, count 0 2006.210.07:20:21.39#ibcon#read 4, iclass 36, count 0 2006.210.07:20:21.39#ibcon#about to read 5, iclass 36, count 0 2006.210.07:20:21.39#ibcon#read 5, iclass 36, count 0 2006.210.07:20:21.39#ibcon#about to read 6, iclass 36, count 0 2006.210.07:20:21.39#ibcon#read 6, iclass 36, count 0 2006.210.07:20:21.39#ibcon#end of sib2, iclass 36, count 0 2006.210.07:20:21.39#ibcon#*after write, iclass 36, count 0 2006.210.07:20:21.39#ibcon#*before return 0, iclass 36, count 0 2006.210.07:20:21.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:21.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:20:21.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:20:21.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:20:21.39$vc4f8/vbbw=wide 2006.210.07:20:21.39#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.07:20:21.39#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.07:20:21.39#ibcon#ireg 8 cls_cnt 0 2006.210.07:20:21.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:20:21.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:20:21.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:20:21.46#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:20:21.46#ibcon#first serial, iclass 38, count 0 2006.210.07:20:21.46#ibcon#enter sib2, iclass 38, count 0 2006.210.07:20:21.46#ibcon#flushed, iclass 38, count 0 2006.210.07:20:21.46#ibcon#about to write, iclass 38, count 0 2006.210.07:20:21.46#ibcon#wrote, iclass 38, count 0 2006.210.07:20:21.46#ibcon#about to read 3, iclass 38, count 0 2006.210.07:20:21.48#ibcon#read 3, iclass 38, count 0 2006.210.07:20:21.48#ibcon#about to read 4, iclass 38, count 0 2006.210.07:20:21.48#ibcon#read 4, iclass 38, count 0 2006.210.07:20:21.48#ibcon#about to read 5, iclass 38, count 0 2006.210.07:20:21.48#ibcon#read 5, iclass 38, count 0 2006.210.07:20:21.48#ibcon#about to read 6, iclass 38, count 0 2006.210.07:20:21.48#ibcon#read 6, iclass 38, count 0 2006.210.07:20:21.48#ibcon#end of sib2, iclass 38, count 0 2006.210.07:20:21.48#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:20:21.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:20:21.48#ibcon#[27=BW32\r\n] 2006.210.07:20:21.48#ibcon#*before write, iclass 38, count 0 2006.210.07:20:21.48#ibcon#enter sib2, iclass 38, count 0 2006.210.07:20:21.48#ibcon#flushed, iclass 38, count 0 2006.210.07:20:21.48#ibcon#about to write, iclass 38, count 0 2006.210.07:20:21.48#ibcon#wrote, iclass 38, count 0 2006.210.07:20:21.48#ibcon#about to read 3, iclass 38, count 0 2006.210.07:20:21.51#ibcon#read 3, iclass 38, count 0 2006.210.07:20:21.51#ibcon#about to read 4, iclass 38, count 0 2006.210.07:20:21.51#ibcon#read 4, iclass 38, count 0 2006.210.07:20:21.51#ibcon#about to read 5, iclass 38, count 0 2006.210.07:20:21.51#ibcon#read 5, iclass 38, count 0 2006.210.07:20:21.51#ibcon#about to read 6, iclass 38, count 0 2006.210.07:20:21.51#ibcon#read 6, iclass 38, count 0 2006.210.07:20:21.51#ibcon#end of sib2, iclass 38, count 0 2006.210.07:20:21.51#ibcon#*after write, iclass 38, count 0 2006.210.07:20:21.51#ibcon#*before return 0, iclass 38, count 0 2006.210.07:20:21.51#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:20:21.51#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:20:21.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:20:21.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:20:21.51$4f8m12a/ifd4f 2006.210.07:20:21.51&ifd4f/lo= 2006.210.07:20:21.51&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:20:21.51&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:20:21.51&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:20:21.51&ifd4f/patch= 2006.210.07:20:21.51&ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:20:21.51&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:20:21.51&ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:20:21.51$ifd4f/lo= 2006.210.07:20:21.51$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:20:21.51$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:20:21.51$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:20:21.51$ifd4f/patch= 2006.210.07:20:21.51$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:20:21.51$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:20:21.51$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:20:21.51$4f8m12a/"form=m,16.000,1:2 2006.210.07:20:21.51$4f8m12a/"tpicd 2006.210.07:20:21.51$4f8m12a/echo=off 2006.210.07:20:21.51$4f8m12a/xlog=off 2006.210.07:20:21.51:!2006.210.07:29:50 2006.210.07:20:42.14#trakl#Source acquired 2006.210.07:20:44.14#flagr#flagr/antenna,acquired 2006.210.07:29:50.02:preob 2006.210.07:29:50.02&preob/onsource 2006.210.07:29:51.14/onsource/TRACKING 2006.210.07:29:51.14:!2006.210.07:30:00 2006.210.07:30:00.02:data_valid=on 2006.210.07:30:00.02:midob 2006.210.07:30:00.02&midob/onsource 2006.210.07:30:00.02&midob/wx 2006.210.07:30:00.02&midob/cable 2006.210.07:30:00.02&midob/va 2006.210.07:30:00.02&midob/valo 2006.210.07:30:00.02&midob/vb 2006.210.07:30:00.02&midob/vblo 2006.210.07:30:00.02&midob/vabw 2006.210.07:30:00.02&midob/vbbw 2006.210.07:30:00.02&midob/"form 2006.210.07:30:00.02&midob/xfe 2006.210.07:30:00.02&midob/ifatt 2006.210.07:30:00.02&midob/clockoff 2006.210.07:30:00.02&midob/sy=logmail 2006.210.07:30:00.02&midob/"sy=run setcl adapt & 2006.210.07:30:01.14/onsource/TRACKING 2006.210.07:30:01.14/wx/30.53,1006.2,72 2006.210.07:30:01.31/cable/+6.3956E-03 2006.210.07:30:02.40/va/01,08,usb,yes,32,34 2006.210.07:30:02.40/va/02,07,usb,yes,32,34 2006.210.07:30:02.40/va/03,06,usb,yes,34,34 2006.210.07:30:02.40/va/04,07,usb,yes,33,35 2006.210.07:30:02.40/va/05,07,usb,yes,34,36 2006.210.07:30:02.40/va/06,06,usb,yes,33,33 2006.210.07:30:02.40/va/07,06,usb,yes,34,34 2006.210.07:30:02.40/va/08,07,usb,yes,32,32 2006.210.07:30:02.63/valo/01,532.99,yes,locked 2006.210.07:30:02.63/valo/02,572.99,yes,locked 2006.210.07:30:02.63/valo/03,672.99,yes,locked 2006.210.07:30:02.63/valo/04,832.99,yes,locked 2006.210.07:30:02.63/valo/05,652.99,yes,locked 2006.210.07:30:02.63/valo/06,772.99,yes,locked 2006.210.07:30:02.63/valo/07,832.99,yes,locked 2006.210.07:30:02.63/valo/08,852.99,yes,locked 2006.210.07:30:03.72/vb/01,04,usb,yes,30,29 2006.210.07:30:03.72/vb/02,04,usb,yes,32,33 2006.210.07:30:03.72/vb/03,03,usb,yes,35,40 2006.210.07:30:03.72/vb/04,03,usb,yes,36,37 2006.210.07:30:03.72/vb/05,03,usb,yes,35,40 2006.210.07:30:03.72/vb/06,03,usb,yes,35,39 2006.210.07:30:03.72/vb/07,04,usb,yes,31,31 2006.210.07:30:03.72/vb/08,03,usb,yes,35,39 2006.210.07:30:03.95/vblo/01,632.99,yes,locked 2006.210.07:30:03.95/vblo/02,640.99,yes,locked 2006.210.07:30:03.95/vblo/03,656.99,yes,locked 2006.210.07:30:03.95/vblo/04,712.99,yes,locked 2006.210.07:30:03.95/vblo/05,744.99,yes,locked 2006.210.07:30:03.95/vblo/06,752.99,yes,locked 2006.210.07:30:03.95/vblo/07,734.99,yes,locked 2006.210.07:30:03.95/vblo/08,744.99,yes,locked 2006.210.07:30:04.10/vabw/8 2006.210.07:30:04.24/vbbw/8 2006.210.07:30:04.34/xfe/off,on,12.7 2006.210.07:30:04.71/ifatt/23,28,28,28 2006.210.07:30:05.08/fmout-gps/S +4.33E-07 2006.210.07:30:05.12:!2006.210.07:31:00 2006.210.07:31:00.02:data_valid=off 2006.210.07:31:00.02:postob 2006.210.07:31:00.02&postob/cable 2006.210.07:31:00.02&postob/wx 2006.210.07:31:00.02&postob/clockoff 2006.210.07:31:00.09/cable/+6.3951E-03 2006.210.07:31:00.10/wx/30.54,1006.1,71 2006.210.07:31:01.07/fmout-gps/S +4.35E-07 2006.210.07:31:01.08:scan_name=210-0733,k06210,60 2006.210.07:31:01.08:source=0808+019,081126.71,014652.2,2000.0,ccw 2006.210.07:31:02.15#flagr#flagr/antenna,new-source 2006.210.07:31:02.15:checkk5 2006.210.07:31:02.15&checkk5/chk_autoobs=1 2006.210.07:31:02.15&checkk5/chk_autoobs=2 2006.210.07:31:02.15&checkk5/chk_autoobs=3 2006.210.07:31:02.15&checkk5/chk_autoobs=4 2006.210.07:31:02.15&checkk5/chk_obsdata=1 2006.210.07:31:02.15&checkk5/chk_obsdata=2 2006.210.07:31:02.15&checkk5/chk_obsdata=3 2006.210.07:31:02.15&checkk5/chk_obsdata=4 2006.210.07:31:02.15&checkk5/k5log=1 2006.210.07:31:02.15&checkk5/k5log=2 2006.210.07:31:02.15&checkk5/k5log=3 2006.210.07:31:02.15&checkk5/k5log=4 2006.210.07:31:02.15&checkk5/obsinfo 2006.210.07:31:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:31:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:31:03.23/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:31:03.60/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:31:03.93/chk_obsdata//k5ts1/T2100730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:04.26/chk_obsdata//k5ts2/T2100730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:04.60/chk_obsdata//k5ts3/T2100730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:04.94/chk_obsdata//k5ts4/T2100730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:31:05.60/k5log//k5ts1_log_newline 2006.210.07:31:06.25/k5log//k5ts2_log_newline 2006.210.07:31:06.91/k5log//k5ts3_log_newline 2006.210.07:31:07.57/k5log//k5ts4_log_newline 2006.210.07:31:07.59/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:31:07.59:4f8m12a=1 2006.210.07:31:07.59$4f8m12a/echo=on 2006.210.07:31:07.59$4f8m12a/pcalon 2006.210.07:31:07.59$pcalon/"no phase cal control is implemented here 2006.210.07:31:07.59$4f8m12a/"tpicd=stop 2006.210.07:31:07.59$4f8m12a/vc4f8 2006.210.07:31:07.59$vc4f8/valo=1,532.99 2006.210.07:31:07.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:31:07.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:31:07.60#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:07.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:07.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:07.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:07.60#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:31:07.60#ibcon#first serial, iclass 40, count 0 2006.210.07:31:07.60#ibcon#enter sib2, iclass 40, count 0 2006.210.07:31:07.60#ibcon#flushed, iclass 40, count 0 2006.210.07:31:07.60#ibcon#about to write, iclass 40, count 0 2006.210.07:31:07.60#ibcon#wrote, iclass 40, count 0 2006.210.07:31:07.60#ibcon#about to read 3, iclass 40, count 0 2006.210.07:31:07.61#ibcon#read 3, iclass 40, count 0 2006.210.07:31:07.61#ibcon#about to read 4, iclass 40, count 0 2006.210.07:31:07.61#ibcon#read 4, iclass 40, count 0 2006.210.07:31:07.61#ibcon#about to read 5, iclass 40, count 0 2006.210.07:31:07.61#ibcon#read 5, iclass 40, count 0 2006.210.07:31:07.61#ibcon#about to read 6, iclass 40, count 0 2006.210.07:31:07.61#ibcon#read 6, iclass 40, count 0 2006.210.07:31:07.61#ibcon#end of sib2, iclass 40, count 0 2006.210.07:31:07.61#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:31:07.61#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:31:07.61#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:31:07.61#ibcon#*before write, iclass 40, count 0 2006.210.07:31:07.61#ibcon#enter sib2, iclass 40, count 0 2006.210.07:31:07.61#ibcon#flushed, iclass 40, count 0 2006.210.07:31:07.61#ibcon#about to write, iclass 40, count 0 2006.210.07:31:07.61#ibcon#wrote, iclass 40, count 0 2006.210.07:31:07.61#ibcon#about to read 3, iclass 40, count 0 2006.210.07:31:07.66#ibcon#read 3, iclass 40, count 0 2006.210.07:31:07.66#ibcon#about to read 4, iclass 40, count 0 2006.210.07:31:07.66#ibcon#read 4, iclass 40, count 0 2006.210.07:31:07.66#ibcon#about to read 5, iclass 40, count 0 2006.210.07:31:07.66#ibcon#read 5, iclass 40, count 0 2006.210.07:31:07.66#ibcon#about to read 6, iclass 40, count 0 2006.210.07:31:07.66#ibcon#read 6, iclass 40, count 0 2006.210.07:31:07.66#ibcon#end of sib2, iclass 40, count 0 2006.210.07:31:07.66#ibcon#*after write, iclass 40, count 0 2006.210.07:31:07.66#ibcon#*before return 0, iclass 40, count 0 2006.210.07:31:07.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:07.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:07.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:31:07.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:31:07.67$vc4f8/va=1,8 2006.210.07:31:07.67#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:31:07.67#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:31:07.67#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:07.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:07.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:07.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:07.67#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:31:07.67#ibcon#first serial, iclass 4, count 2 2006.210.07:31:07.67#ibcon#enter sib2, iclass 4, count 2 2006.210.07:31:07.67#ibcon#flushed, iclass 4, count 2 2006.210.07:31:07.67#ibcon#about to write, iclass 4, count 2 2006.210.07:31:07.67#ibcon#wrote, iclass 4, count 2 2006.210.07:31:07.67#ibcon#about to read 3, iclass 4, count 2 2006.210.07:31:07.68#ibcon#read 3, iclass 4, count 2 2006.210.07:31:07.68#ibcon#about to read 4, iclass 4, count 2 2006.210.07:31:07.68#ibcon#read 4, iclass 4, count 2 2006.210.07:31:07.68#ibcon#about to read 5, iclass 4, count 2 2006.210.07:31:07.68#ibcon#read 5, iclass 4, count 2 2006.210.07:31:07.68#ibcon#about to read 6, iclass 4, count 2 2006.210.07:31:07.68#ibcon#read 6, iclass 4, count 2 2006.210.07:31:07.68#ibcon#end of sib2, iclass 4, count 2 2006.210.07:31:07.68#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:31:07.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:31:07.68#ibcon#[25=AT01-08\r\n] 2006.210.07:31:07.68#ibcon#*before write, iclass 4, count 2 2006.210.07:31:07.68#ibcon#enter sib2, iclass 4, count 2 2006.210.07:31:07.68#ibcon#flushed, iclass 4, count 2 2006.210.07:31:07.68#ibcon#about to write, iclass 4, count 2 2006.210.07:31:07.68#ibcon#wrote, iclass 4, count 2 2006.210.07:31:07.68#ibcon#about to read 3, iclass 4, count 2 2006.210.07:31:07.71#ibcon#read 3, iclass 4, count 2 2006.210.07:31:07.71#ibcon#about to read 4, iclass 4, count 2 2006.210.07:31:07.71#ibcon#read 4, iclass 4, count 2 2006.210.07:31:07.71#ibcon#about to read 5, iclass 4, count 2 2006.210.07:31:07.71#ibcon#read 5, iclass 4, count 2 2006.210.07:31:07.71#ibcon#about to read 6, iclass 4, count 2 2006.210.07:31:07.71#ibcon#read 6, iclass 4, count 2 2006.210.07:31:07.71#ibcon#end of sib2, iclass 4, count 2 2006.210.07:31:07.71#ibcon#*after write, iclass 4, count 2 2006.210.07:31:07.71#ibcon#*before return 0, iclass 4, count 2 2006.210.07:31:07.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:07.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:07.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:31:07.71#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:07.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:07.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:07.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:07.83#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:31:07.83#ibcon#first serial, iclass 4, count 0 2006.210.07:31:07.83#ibcon#enter sib2, iclass 4, count 0 2006.210.07:31:07.83#ibcon#flushed, iclass 4, count 0 2006.210.07:31:07.83#ibcon#about to write, iclass 4, count 0 2006.210.07:31:07.83#ibcon#wrote, iclass 4, count 0 2006.210.07:31:07.83#ibcon#about to read 3, iclass 4, count 0 2006.210.07:31:07.85#ibcon#read 3, iclass 4, count 0 2006.210.07:31:07.85#ibcon#about to read 4, iclass 4, count 0 2006.210.07:31:07.85#ibcon#read 4, iclass 4, count 0 2006.210.07:31:07.85#ibcon#about to read 5, iclass 4, count 0 2006.210.07:31:07.85#ibcon#read 5, iclass 4, count 0 2006.210.07:31:07.85#ibcon#about to read 6, iclass 4, count 0 2006.210.07:31:07.85#ibcon#read 6, iclass 4, count 0 2006.210.07:31:07.85#ibcon#end of sib2, iclass 4, count 0 2006.210.07:31:07.85#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:31:07.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:31:07.85#ibcon#[25=USB\r\n] 2006.210.07:31:07.85#ibcon#*before write, iclass 4, count 0 2006.210.07:31:07.85#ibcon#enter sib2, iclass 4, count 0 2006.210.07:31:07.85#ibcon#flushed, iclass 4, count 0 2006.210.07:31:07.85#ibcon#about to write, iclass 4, count 0 2006.210.07:31:07.85#ibcon#wrote, iclass 4, count 0 2006.210.07:31:07.85#ibcon#about to read 3, iclass 4, count 0 2006.210.07:31:07.88#ibcon#read 3, iclass 4, count 0 2006.210.07:31:07.88#ibcon#about to read 4, iclass 4, count 0 2006.210.07:31:07.88#ibcon#read 4, iclass 4, count 0 2006.210.07:31:07.88#ibcon#about to read 5, iclass 4, count 0 2006.210.07:31:07.88#ibcon#read 5, iclass 4, count 0 2006.210.07:31:07.88#ibcon#about to read 6, iclass 4, count 0 2006.210.07:31:07.88#ibcon#read 6, iclass 4, count 0 2006.210.07:31:07.88#ibcon#end of sib2, iclass 4, count 0 2006.210.07:31:07.88#ibcon#*after write, iclass 4, count 0 2006.210.07:31:07.88#ibcon#*before return 0, iclass 4, count 0 2006.210.07:31:07.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:07.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:07.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:31:07.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:31:07.89$vc4f8/valo=2,572.99 2006.210.07:31:07.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:31:07.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:31:07.89#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:07.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:07.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:07.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:07.89#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:31:07.89#ibcon#first serial, iclass 6, count 0 2006.210.07:31:07.89#ibcon#enter sib2, iclass 6, count 0 2006.210.07:31:07.89#ibcon#flushed, iclass 6, count 0 2006.210.07:31:07.89#ibcon#about to write, iclass 6, count 0 2006.210.07:31:07.89#ibcon#wrote, iclass 6, count 0 2006.210.07:31:07.89#ibcon#about to read 3, iclass 6, count 0 2006.210.07:31:07.90#ibcon#read 3, iclass 6, count 0 2006.210.07:31:07.90#ibcon#about to read 4, iclass 6, count 0 2006.210.07:31:07.90#ibcon#read 4, iclass 6, count 0 2006.210.07:31:07.90#ibcon#about to read 5, iclass 6, count 0 2006.210.07:31:07.90#ibcon#read 5, iclass 6, count 0 2006.210.07:31:07.90#ibcon#about to read 6, iclass 6, count 0 2006.210.07:31:07.90#ibcon#read 6, iclass 6, count 0 2006.210.07:31:07.90#ibcon#end of sib2, iclass 6, count 0 2006.210.07:31:07.90#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:31:07.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:31:07.90#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:31:07.90#ibcon#*before write, iclass 6, count 0 2006.210.07:31:07.90#ibcon#enter sib2, iclass 6, count 0 2006.210.07:31:07.90#ibcon#flushed, iclass 6, count 0 2006.210.07:31:07.90#ibcon#about to write, iclass 6, count 0 2006.210.07:31:07.90#ibcon#wrote, iclass 6, count 0 2006.210.07:31:07.90#ibcon#about to read 3, iclass 6, count 0 2006.210.07:31:07.94#ibcon#read 3, iclass 6, count 0 2006.210.07:31:07.94#ibcon#about to read 4, iclass 6, count 0 2006.210.07:31:07.94#ibcon#read 4, iclass 6, count 0 2006.210.07:31:07.94#ibcon#about to read 5, iclass 6, count 0 2006.210.07:31:07.94#ibcon#read 5, iclass 6, count 0 2006.210.07:31:07.94#ibcon#about to read 6, iclass 6, count 0 2006.210.07:31:07.94#ibcon#read 6, iclass 6, count 0 2006.210.07:31:07.94#ibcon#end of sib2, iclass 6, count 0 2006.210.07:31:07.94#ibcon#*after write, iclass 6, count 0 2006.210.07:31:07.94#ibcon#*before return 0, iclass 6, count 0 2006.210.07:31:07.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:07.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:07.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:31:07.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:31:07.95$vc4f8/va=2,7 2006.210.07:31:07.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:31:07.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:31:07.95#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:07.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:07.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:07.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:07.99#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:31:07.99#ibcon#first serial, iclass 10, count 2 2006.210.07:31:07.99#ibcon#enter sib2, iclass 10, count 2 2006.210.07:31:07.99#ibcon#flushed, iclass 10, count 2 2006.210.07:31:07.99#ibcon#about to write, iclass 10, count 2 2006.210.07:31:07.99#ibcon#wrote, iclass 10, count 2 2006.210.07:31:07.99#ibcon#about to read 3, iclass 10, count 2 2006.210.07:31:08.01#ibcon#read 3, iclass 10, count 2 2006.210.07:31:08.01#ibcon#about to read 4, iclass 10, count 2 2006.210.07:31:08.01#ibcon#read 4, iclass 10, count 2 2006.210.07:31:08.01#ibcon#about to read 5, iclass 10, count 2 2006.210.07:31:08.01#ibcon#read 5, iclass 10, count 2 2006.210.07:31:08.01#ibcon#about to read 6, iclass 10, count 2 2006.210.07:31:08.01#ibcon#read 6, iclass 10, count 2 2006.210.07:31:08.01#ibcon#end of sib2, iclass 10, count 2 2006.210.07:31:08.01#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:31:08.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:31:08.01#ibcon#[25=AT02-07\r\n] 2006.210.07:31:08.01#ibcon#*before write, iclass 10, count 2 2006.210.07:31:08.01#ibcon#enter sib2, iclass 10, count 2 2006.210.07:31:08.01#ibcon#flushed, iclass 10, count 2 2006.210.07:31:08.01#ibcon#about to write, iclass 10, count 2 2006.210.07:31:08.01#ibcon#wrote, iclass 10, count 2 2006.210.07:31:08.01#ibcon#about to read 3, iclass 10, count 2 2006.210.07:31:08.04#ibcon#read 3, iclass 10, count 2 2006.210.07:31:08.04#ibcon#about to read 4, iclass 10, count 2 2006.210.07:31:08.04#ibcon#read 4, iclass 10, count 2 2006.210.07:31:08.04#ibcon#about to read 5, iclass 10, count 2 2006.210.07:31:08.04#ibcon#read 5, iclass 10, count 2 2006.210.07:31:08.04#ibcon#about to read 6, iclass 10, count 2 2006.210.07:31:08.04#ibcon#read 6, iclass 10, count 2 2006.210.07:31:08.04#ibcon#end of sib2, iclass 10, count 2 2006.210.07:31:08.04#ibcon#*after write, iclass 10, count 2 2006.210.07:31:08.04#ibcon#*before return 0, iclass 10, count 2 2006.210.07:31:08.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:08.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:08.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:31:08.04#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:08.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:08.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:08.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:08.16#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:31:08.16#ibcon#first serial, iclass 10, count 0 2006.210.07:31:08.16#ibcon#enter sib2, iclass 10, count 0 2006.210.07:31:08.16#ibcon#flushed, iclass 10, count 0 2006.210.07:31:08.16#ibcon#about to write, iclass 10, count 0 2006.210.07:31:08.16#ibcon#wrote, iclass 10, count 0 2006.210.07:31:08.16#ibcon#about to read 3, iclass 10, count 0 2006.210.07:31:08.18#ibcon#read 3, iclass 10, count 0 2006.210.07:31:08.18#ibcon#about to read 4, iclass 10, count 0 2006.210.07:31:08.18#ibcon#read 4, iclass 10, count 0 2006.210.07:31:08.18#ibcon#about to read 5, iclass 10, count 0 2006.210.07:31:08.18#ibcon#read 5, iclass 10, count 0 2006.210.07:31:08.18#ibcon#about to read 6, iclass 10, count 0 2006.210.07:31:08.18#ibcon#read 6, iclass 10, count 0 2006.210.07:31:08.18#ibcon#end of sib2, iclass 10, count 0 2006.210.07:31:08.18#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:31:08.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:31:08.18#ibcon#[25=USB\r\n] 2006.210.07:31:08.18#ibcon#*before write, iclass 10, count 0 2006.210.07:31:08.18#ibcon#enter sib2, iclass 10, count 0 2006.210.07:31:08.18#ibcon#flushed, iclass 10, count 0 2006.210.07:31:08.18#ibcon#about to write, iclass 10, count 0 2006.210.07:31:08.18#ibcon#wrote, iclass 10, count 0 2006.210.07:31:08.18#ibcon#about to read 3, iclass 10, count 0 2006.210.07:31:08.21#ibcon#read 3, iclass 10, count 0 2006.210.07:31:08.21#ibcon#about to read 4, iclass 10, count 0 2006.210.07:31:08.21#ibcon#read 4, iclass 10, count 0 2006.210.07:31:08.21#ibcon#about to read 5, iclass 10, count 0 2006.210.07:31:08.21#ibcon#read 5, iclass 10, count 0 2006.210.07:31:08.21#ibcon#about to read 6, iclass 10, count 0 2006.210.07:31:08.21#ibcon#read 6, iclass 10, count 0 2006.210.07:31:08.21#ibcon#end of sib2, iclass 10, count 0 2006.210.07:31:08.21#ibcon#*after write, iclass 10, count 0 2006.210.07:31:08.21#ibcon#*before return 0, iclass 10, count 0 2006.210.07:31:08.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:08.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:08.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:31:08.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:31:08.22$vc4f8/valo=3,672.99 2006.210.07:31:08.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:31:08.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:31:08.22#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:08.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:08.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:08.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:08.22#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:31:08.22#ibcon#first serial, iclass 12, count 0 2006.210.07:31:08.22#ibcon#enter sib2, iclass 12, count 0 2006.210.07:31:08.22#ibcon#flushed, iclass 12, count 0 2006.210.07:31:08.22#ibcon#about to write, iclass 12, count 0 2006.210.07:31:08.22#ibcon#wrote, iclass 12, count 0 2006.210.07:31:08.22#ibcon#about to read 3, iclass 12, count 0 2006.210.07:31:08.23#ibcon#read 3, iclass 12, count 0 2006.210.07:31:08.23#ibcon#about to read 4, iclass 12, count 0 2006.210.07:31:08.23#ibcon#read 4, iclass 12, count 0 2006.210.07:31:08.23#ibcon#about to read 5, iclass 12, count 0 2006.210.07:31:08.23#ibcon#read 5, iclass 12, count 0 2006.210.07:31:08.23#ibcon#about to read 6, iclass 12, count 0 2006.210.07:31:08.23#ibcon#read 6, iclass 12, count 0 2006.210.07:31:08.23#ibcon#end of sib2, iclass 12, count 0 2006.210.07:31:08.23#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:31:08.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:31:08.23#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:31:08.23#ibcon#*before write, iclass 12, count 0 2006.210.07:31:08.23#ibcon#enter sib2, iclass 12, count 0 2006.210.07:31:08.23#ibcon#flushed, iclass 12, count 0 2006.210.07:31:08.23#ibcon#about to write, iclass 12, count 0 2006.210.07:31:08.23#ibcon#wrote, iclass 12, count 0 2006.210.07:31:08.23#ibcon#about to read 3, iclass 12, count 0 2006.210.07:31:08.27#ibcon#read 3, iclass 12, count 0 2006.210.07:31:08.27#ibcon#about to read 4, iclass 12, count 0 2006.210.07:31:08.27#ibcon#read 4, iclass 12, count 0 2006.210.07:31:08.27#ibcon#about to read 5, iclass 12, count 0 2006.210.07:31:08.27#ibcon#read 5, iclass 12, count 0 2006.210.07:31:08.27#ibcon#about to read 6, iclass 12, count 0 2006.210.07:31:08.27#ibcon#read 6, iclass 12, count 0 2006.210.07:31:08.27#ibcon#end of sib2, iclass 12, count 0 2006.210.07:31:08.27#ibcon#*after write, iclass 12, count 0 2006.210.07:31:08.27#ibcon#*before return 0, iclass 12, count 0 2006.210.07:31:08.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:08.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:08.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:31:08.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:31:08.28$vc4f8/va=3,6 2006.210.07:31:08.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:31:08.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:31:08.28#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:08.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:08.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:08.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:08.32#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:31:08.32#ibcon#first serial, iclass 14, count 2 2006.210.07:31:08.32#ibcon#enter sib2, iclass 14, count 2 2006.210.07:31:08.32#ibcon#flushed, iclass 14, count 2 2006.210.07:31:08.32#ibcon#about to write, iclass 14, count 2 2006.210.07:31:08.32#ibcon#wrote, iclass 14, count 2 2006.210.07:31:08.32#ibcon#about to read 3, iclass 14, count 2 2006.210.07:31:08.34#ibcon#read 3, iclass 14, count 2 2006.210.07:31:08.34#ibcon#about to read 4, iclass 14, count 2 2006.210.07:31:08.34#ibcon#read 4, iclass 14, count 2 2006.210.07:31:08.34#ibcon#about to read 5, iclass 14, count 2 2006.210.07:31:08.34#ibcon#read 5, iclass 14, count 2 2006.210.07:31:08.34#ibcon#about to read 6, iclass 14, count 2 2006.210.07:31:08.34#ibcon#read 6, iclass 14, count 2 2006.210.07:31:08.34#ibcon#end of sib2, iclass 14, count 2 2006.210.07:31:08.34#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:31:08.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:31:08.34#ibcon#[25=AT03-06\r\n] 2006.210.07:31:08.34#ibcon#*before write, iclass 14, count 2 2006.210.07:31:08.34#ibcon#enter sib2, iclass 14, count 2 2006.210.07:31:08.34#ibcon#flushed, iclass 14, count 2 2006.210.07:31:08.34#ibcon#about to write, iclass 14, count 2 2006.210.07:31:08.34#ibcon#wrote, iclass 14, count 2 2006.210.07:31:08.34#ibcon#about to read 3, iclass 14, count 2 2006.210.07:31:08.37#ibcon#read 3, iclass 14, count 2 2006.210.07:31:08.37#ibcon#about to read 4, iclass 14, count 2 2006.210.07:31:08.37#ibcon#read 4, iclass 14, count 2 2006.210.07:31:08.37#ibcon#about to read 5, iclass 14, count 2 2006.210.07:31:08.37#ibcon#read 5, iclass 14, count 2 2006.210.07:31:08.37#ibcon#about to read 6, iclass 14, count 2 2006.210.07:31:08.37#ibcon#read 6, iclass 14, count 2 2006.210.07:31:08.37#ibcon#end of sib2, iclass 14, count 2 2006.210.07:31:08.37#ibcon#*after write, iclass 14, count 2 2006.210.07:31:08.37#ibcon#*before return 0, iclass 14, count 2 2006.210.07:31:08.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:08.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:08.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:31:08.37#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:08.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:08.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:08.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:08.49#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:31:08.49#ibcon#first serial, iclass 14, count 0 2006.210.07:31:08.49#ibcon#enter sib2, iclass 14, count 0 2006.210.07:31:08.49#ibcon#flushed, iclass 14, count 0 2006.210.07:31:08.49#ibcon#about to write, iclass 14, count 0 2006.210.07:31:08.49#ibcon#wrote, iclass 14, count 0 2006.210.07:31:08.49#ibcon#about to read 3, iclass 14, count 0 2006.210.07:31:08.51#ibcon#read 3, iclass 14, count 0 2006.210.07:31:08.51#ibcon#about to read 4, iclass 14, count 0 2006.210.07:31:08.51#ibcon#read 4, iclass 14, count 0 2006.210.07:31:08.51#ibcon#about to read 5, iclass 14, count 0 2006.210.07:31:08.51#ibcon#read 5, iclass 14, count 0 2006.210.07:31:08.51#ibcon#about to read 6, iclass 14, count 0 2006.210.07:31:08.51#ibcon#read 6, iclass 14, count 0 2006.210.07:31:08.51#ibcon#end of sib2, iclass 14, count 0 2006.210.07:31:08.51#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:31:08.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:31:08.51#ibcon#[25=USB\r\n] 2006.210.07:31:08.51#ibcon#*before write, iclass 14, count 0 2006.210.07:31:08.51#ibcon#enter sib2, iclass 14, count 0 2006.210.07:31:08.51#ibcon#flushed, iclass 14, count 0 2006.210.07:31:08.51#ibcon#about to write, iclass 14, count 0 2006.210.07:31:08.51#ibcon#wrote, iclass 14, count 0 2006.210.07:31:08.51#ibcon#about to read 3, iclass 14, count 0 2006.210.07:31:08.54#ibcon#read 3, iclass 14, count 0 2006.210.07:31:08.54#ibcon#about to read 4, iclass 14, count 0 2006.210.07:31:08.54#ibcon#read 4, iclass 14, count 0 2006.210.07:31:08.54#ibcon#about to read 5, iclass 14, count 0 2006.210.07:31:08.54#ibcon#read 5, iclass 14, count 0 2006.210.07:31:08.54#ibcon#about to read 6, iclass 14, count 0 2006.210.07:31:08.54#ibcon#read 6, iclass 14, count 0 2006.210.07:31:08.54#ibcon#end of sib2, iclass 14, count 0 2006.210.07:31:08.54#ibcon#*after write, iclass 14, count 0 2006.210.07:31:08.54#ibcon#*before return 0, iclass 14, count 0 2006.210.07:31:08.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:08.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:08.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:31:08.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:31:08.55$vc4f8/valo=4,832.99 2006.210.07:31:08.55#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:31:08.55#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:31:08.55#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:08.55#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:08.55#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:08.55#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:08.55#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:31:08.55#ibcon#first serial, iclass 16, count 0 2006.210.07:31:08.55#ibcon#enter sib2, iclass 16, count 0 2006.210.07:31:08.55#ibcon#flushed, iclass 16, count 0 2006.210.07:31:08.55#ibcon#about to write, iclass 16, count 0 2006.210.07:31:08.55#ibcon#wrote, iclass 16, count 0 2006.210.07:31:08.55#ibcon#about to read 3, iclass 16, count 0 2006.210.07:31:08.56#ibcon#read 3, iclass 16, count 0 2006.210.07:31:08.56#ibcon#about to read 4, iclass 16, count 0 2006.210.07:31:08.56#ibcon#read 4, iclass 16, count 0 2006.210.07:31:08.56#ibcon#about to read 5, iclass 16, count 0 2006.210.07:31:08.56#ibcon#read 5, iclass 16, count 0 2006.210.07:31:08.56#ibcon#about to read 6, iclass 16, count 0 2006.210.07:31:08.56#ibcon#read 6, iclass 16, count 0 2006.210.07:31:08.56#ibcon#end of sib2, iclass 16, count 0 2006.210.07:31:08.56#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:31:08.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:31:08.56#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:31:08.56#ibcon#*before write, iclass 16, count 0 2006.210.07:31:08.56#ibcon#enter sib2, iclass 16, count 0 2006.210.07:31:08.56#ibcon#flushed, iclass 16, count 0 2006.210.07:31:08.56#ibcon#about to write, iclass 16, count 0 2006.210.07:31:08.56#ibcon#wrote, iclass 16, count 0 2006.210.07:31:08.56#ibcon#about to read 3, iclass 16, count 0 2006.210.07:31:08.60#ibcon#read 3, iclass 16, count 0 2006.210.07:31:08.60#ibcon#about to read 4, iclass 16, count 0 2006.210.07:31:08.60#ibcon#read 4, iclass 16, count 0 2006.210.07:31:08.60#ibcon#about to read 5, iclass 16, count 0 2006.210.07:31:08.60#ibcon#read 5, iclass 16, count 0 2006.210.07:31:08.60#ibcon#about to read 6, iclass 16, count 0 2006.210.07:31:08.60#ibcon#read 6, iclass 16, count 0 2006.210.07:31:08.60#ibcon#end of sib2, iclass 16, count 0 2006.210.07:31:08.60#ibcon#*after write, iclass 16, count 0 2006.210.07:31:08.60#ibcon#*before return 0, iclass 16, count 0 2006.210.07:31:08.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:08.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:08.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:31:08.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:31:08.61$vc4f8/va=4,7 2006.210.07:31:08.61#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:31:08.61#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:31:08.61#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:08.61#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:08.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:08.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:08.65#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:31:08.65#ibcon#first serial, iclass 18, count 2 2006.210.07:31:08.65#ibcon#enter sib2, iclass 18, count 2 2006.210.07:31:08.65#ibcon#flushed, iclass 18, count 2 2006.210.07:31:08.65#ibcon#about to write, iclass 18, count 2 2006.210.07:31:08.65#ibcon#wrote, iclass 18, count 2 2006.210.07:31:08.65#ibcon#about to read 3, iclass 18, count 2 2006.210.07:31:08.67#ibcon#read 3, iclass 18, count 2 2006.210.07:31:08.67#ibcon#about to read 4, iclass 18, count 2 2006.210.07:31:08.67#ibcon#read 4, iclass 18, count 2 2006.210.07:31:08.67#ibcon#about to read 5, iclass 18, count 2 2006.210.07:31:08.67#ibcon#read 5, iclass 18, count 2 2006.210.07:31:08.67#ibcon#about to read 6, iclass 18, count 2 2006.210.07:31:08.67#ibcon#read 6, iclass 18, count 2 2006.210.07:31:08.67#ibcon#end of sib2, iclass 18, count 2 2006.210.07:31:08.67#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:31:08.67#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:31:08.67#ibcon#[25=AT04-07\r\n] 2006.210.07:31:08.67#ibcon#*before write, iclass 18, count 2 2006.210.07:31:08.67#ibcon#enter sib2, iclass 18, count 2 2006.210.07:31:08.67#ibcon#flushed, iclass 18, count 2 2006.210.07:31:08.67#ibcon#about to write, iclass 18, count 2 2006.210.07:31:08.67#ibcon#wrote, iclass 18, count 2 2006.210.07:31:08.67#ibcon#about to read 3, iclass 18, count 2 2006.210.07:31:08.70#ibcon#read 3, iclass 18, count 2 2006.210.07:31:08.70#ibcon#about to read 4, iclass 18, count 2 2006.210.07:31:08.70#ibcon#read 4, iclass 18, count 2 2006.210.07:31:08.70#ibcon#about to read 5, iclass 18, count 2 2006.210.07:31:08.70#ibcon#read 5, iclass 18, count 2 2006.210.07:31:08.70#ibcon#about to read 6, iclass 18, count 2 2006.210.07:31:08.70#ibcon#read 6, iclass 18, count 2 2006.210.07:31:08.70#ibcon#end of sib2, iclass 18, count 2 2006.210.07:31:08.70#ibcon#*after write, iclass 18, count 2 2006.210.07:31:08.70#ibcon#*before return 0, iclass 18, count 2 2006.210.07:31:08.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:08.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:08.70#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:31:08.70#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:08.70#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:08.82#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:08.82#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:08.82#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:31:08.82#ibcon#first serial, iclass 18, count 0 2006.210.07:31:08.82#ibcon#enter sib2, iclass 18, count 0 2006.210.07:31:08.82#ibcon#flushed, iclass 18, count 0 2006.210.07:31:08.82#ibcon#about to write, iclass 18, count 0 2006.210.07:31:08.82#ibcon#wrote, iclass 18, count 0 2006.210.07:31:08.82#ibcon#about to read 3, iclass 18, count 0 2006.210.07:31:08.84#ibcon#read 3, iclass 18, count 0 2006.210.07:31:08.84#ibcon#about to read 4, iclass 18, count 0 2006.210.07:31:08.84#ibcon#read 4, iclass 18, count 0 2006.210.07:31:08.84#ibcon#about to read 5, iclass 18, count 0 2006.210.07:31:08.84#ibcon#read 5, iclass 18, count 0 2006.210.07:31:08.84#ibcon#about to read 6, iclass 18, count 0 2006.210.07:31:08.84#ibcon#read 6, iclass 18, count 0 2006.210.07:31:08.84#ibcon#end of sib2, iclass 18, count 0 2006.210.07:31:08.84#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:31:08.84#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:31:08.84#ibcon#[25=USB\r\n] 2006.210.07:31:08.84#ibcon#*before write, iclass 18, count 0 2006.210.07:31:08.84#ibcon#enter sib2, iclass 18, count 0 2006.210.07:31:08.84#ibcon#flushed, iclass 18, count 0 2006.210.07:31:08.84#ibcon#about to write, iclass 18, count 0 2006.210.07:31:08.84#ibcon#wrote, iclass 18, count 0 2006.210.07:31:08.84#ibcon#about to read 3, iclass 18, count 0 2006.210.07:31:08.87#ibcon#read 3, iclass 18, count 0 2006.210.07:31:08.87#ibcon#about to read 4, iclass 18, count 0 2006.210.07:31:08.87#ibcon#read 4, iclass 18, count 0 2006.210.07:31:08.87#ibcon#about to read 5, iclass 18, count 0 2006.210.07:31:08.87#ibcon#read 5, iclass 18, count 0 2006.210.07:31:08.87#ibcon#about to read 6, iclass 18, count 0 2006.210.07:31:08.87#ibcon#read 6, iclass 18, count 0 2006.210.07:31:08.87#ibcon#end of sib2, iclass 18, count 0 2006.210.07:31:08.87#ibcon#*after write, iclass 18, count 0 2006.210.07:31:08.87#ibcon#*before return 0, iclass 18, count 0 2006.210.07:31:08.87#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:08.87#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:08.87#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:31:08.87#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:31:08.88$vc4f8/valo=5,652.99 2006.210.07:31:08.88#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:31:08.88#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:31:08.88#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:08.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:08.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:08.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:08.88#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:31:08.88#ibcon#first serial, iclass 20, count 0 2006.210.07:31:08.88#ibcon#enter sib2, iclass 20, count 0 2006.210.07:31:08.88#ibcon#flushed, iclass 20, count 0 2006.210.07:31:08.88#ibcon#about to write, iclass 20, count 0 2006.210.07:31:08.88#ibcon#wrote, iclass 20, count 0 2006.210.07:31:08.88#ibcon#about to read 3, iclass 20, count 0 2006.210.07:31:08.89#ibcon#read 3, iclass 20, count 0 2006.210.07:31:08.89#ibcon#about to read 4, iclass 20, count 0 2006.210.07:31:08.89#ibcon#read 4, iclass 20, count 0 2006.210.07:31:08.89#ibcon#about to read 5, iclass 20, count 0 2006.210.07:31:08.89#ibcon#read 5, iclass 20, count 0 2006.210.07:31:08.89#ibcon#about to read 6, iclass 20, count 0 2006.210.07:31:08.89#ibcon#read 6, iclass 20, count 0 2006.210.07:31:08.89#ibcon#end of sib2, iclass 20, count 0 2006.210.07:31:08.89#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:31:08.89#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:31:08.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:31:08.89#ibcon#*before write, iclass 20, count 0 2006.210.07:31:08.89#ibcon#enter sib2, iclass 20, count 0 2006.210.07:31:08.89#ibcon#flushed, iclass 20, count 0 2006.210.07:31:08.89#ibcon#about to write, iclass 20, count 0 2006.210.07:31:08.89#ibcon#wrote, iclass 20, count 0 2006.210.07:31:08.89#ibcon#about to read 3, iclass 20, count 0 2006.210.07:31:08.93#ibcon#read 3, iclass 20, count 0 2006.210.07:31:08.93#ibcon#about to read 4, iclass 20, count 0 2006.210.07:31:08.93#ibcon#read 4, iclass 20, count 0 2006.210.07:31:08.93#ibcon#about to read 5, iclass 20, count 0 2006.210.07:31:08.93#ibcon#read 5, iclass 20, count 0 2006.210.07:31:08.93#ibcon#about to read 6, iclass 20, count 0 2006.210.07:31:08.93#ibcon#read 6, iclass 20, count 0 2006.210.07:31:08.93#ibcon#end of sib2, iclass 20, count 0 2006.210.07:31:08.93#ibcon#*after write, iclass 20, count 0 2006.210.07:31:08.93#ibcon#*before return 0, iclass 20, count 0 2006.210.07:31:08.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:08.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:08.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:31:08.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:31:08.94$vc4f8/va=5,7 2006.210.07:31:08.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:31:08.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:31:08.94#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:08.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:08.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:08.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:08.98#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:31:08.98#ibcon#first serial, iclass 22, count 2 2006.210.07:31:08.98#ibcon#enter sib2, iclass 22, count 2 2006.210.07:31:08.98#ibcon#flushed, iclass 22, count 2 2006.210.07:31:08.98#ibcon#about to write, iclass 22, count 2 2006.210.07:31:08.98#ibcon#wrote, iclass 22, count 2 2006.210.07:31:08.98#ibcon#about to read 3, iclass 22, count 2 2006.210.07:31:09.00#ibcon#read 3, iclass 22, count 2 2006.210.07:31:09.00#ibcon#about to read 4, iclass 22, count 2 2006.210.07:31:09.00#ibcon#read 4, iclass 22, count 2 2006.210.07:31:09.00#ibcon#about to read 5, iclass 22, count 2 2006.210.07:31:09.00#ibcon#read 5, iclass 22, count 2 2006.210.07:31:09.00#ibcon#about to read 6, iclass 22, count 2 2006.210.07:31:09.00#ibcon#read 6, iclass 22, count 2 2006.210.07:31:09.00#ibcon#end of sib2, iclass 22, count 2 2006.210.07:31:09.00#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:31:09.00#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:31:09.00#ibcon#[25=AT05-07\r\n] 2006.210.07:31:09.00#ibcon#*before write, iclass 22, count 2 2006.210.07:31:09.00#ibcon#enter sib2, iclass 22, count 2 2006.210.07:31:09.00#ibcon#flushed, iclass 22, count 2 2006.210.07:31:09.00#ibcon#about to write, iclass 22, count 2 2006.210.07:31:09.00#ibcon#wrote, iclass 22, count 2 2006.210.07:31:09.00#ibcon#about to read 3, iclass 22, count 2 2006.210.07:31:09.03#ibcon#read 3, iclass 22, count 2 2006.210.07:31:09.03#ibcon#about to read 4, iclass 22, count 2 2006.210.07:31:09.03#ibcon#read 4, iclass 22, count 2 2006.210.07:31:09.03#ibcon#about to read 5, iclass 22, count 2 2006.210.07:31:09.03#ibcon#read 5, iclass 22, count 2 2006.210.07:31:09.03#ibcon#about to read 6, iclass 22, count 2 2006.210.07:31:09.03#ibcon#read 6, iclass 22, count 2 2006.210.07:31:09.03#ibcon#end of sib2, iclass 22, count 2 2006.210.07:31:09.03#ibcon#*after write, iclass 22, count 2 2006.210.07:31:09.03#ibcon#*before return 0, iclass 22, count 2 2006.210.07:31:09.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:09.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:09.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:31:09.03#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:09.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:09.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:09.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:09.15#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:31:09.15#ibcon#first serial, iclass 22, count 0 2006.210.07:31:09.15#ibcon#enter sib2, iclass 22, count 0 2006.210.07:31:09.15#ibcon#flushed, iclass 22, count 0 2006.210.07:31:09.15#ibcon#about to write, iclass 22, count 0 2006.210.07:31:09.15#ibcon#wrote, iclass 22, count 0 2006.210.07:31:09.15#ibcon#about to read 3, iclass 22, count 0 2006.210.07:31:09.17#ibcon#read 3, iclass 22, count 0 2006.210.07:31:09.17#ibcon#about to read 4, iclass 22, count 0 2006.210.07:31:09.17#ibcon#read 4, iclass 22, count 0 2006.210.07:31:09.17#ibcon#about to read 5, iclass 22, count 0 2006.210.07:31:09.17#ibcon#read 5, iclass 22, count 0 2006.210.07:31:09.17#ibcon#about to read 6, iclass 22, count 0 2006.210.07:31:09.17#ibcon#read 6, iclass 22, count 0 2006.210.07:31:09.17#ibcon#end of sib2, iclass 22, count 0 2006.210.07:31:09.17#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:31:09.17#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:31:09.17#ibcon#[25=USB\r\n] 2006.210.07:31:09.17#ibcon#*before write, iclass 22, count 0 2006.210.07:31:09.17#ibcon#enter sib2, iclass 22, count 0 2006.210.07:31:09.17#ibcon#flushed, iclass 22, count 0 2006.210.07:31:09.17#ibcon#about to write, iclass 22, count 0 2006.210.07:31:09.17#ibcon#wrote, iclass 22, count 0 2006.210.07:31:09.17#ibcon#about to read 3, iclass 22, count 0 2006.210.07:31:09.20#ibcon#read 3, iclass 22, count 0 2006.210.07:31:09.20#ibcon#about to read 4, iclass 22, count 0 2006.210.07:31:09.20#ibcon#read 4, iclass 22, count 0 2006.210.07:31:09.20#ibcon#about to read 5, iclass 22, count 0 2006.210.07:31:09.20#ibcon#read 5, iclass 22, count 0 2006.210.07:31:09.20#ibcon#about to read 6, iclass 22, count 0 2006.210.07:31:09.20#ibcon#read 6, iclass 22, count 0 2006.210.07:31:09.20#ibcon#end of sib2, iclass 22, count 0 2006.210.07:31:09.20#ibcon#*after write, iclass 22, count 0 2006.210.07:31:09.20#ibcon#*before return 0, iclass 22, count 0 2006.210.07:31:09.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:09.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:09.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:31:09.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:31:09.21$vc4f8/valo=6,772.99 2006.210.07:31:09.21#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:31:09.21#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:31:09.21#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:09.21#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:09.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:09.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:09.21#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:31:09.21#ibcon#first serial, iclass 24, count 0 2006.210.07:31:09.21#ibcon#enter sib2, iclass 24, count 0 2006.210.07:31:09.21#ibcon#flushed, iclass 24, count 0 2006.210.07:31:09.21#ibcon#about to write, iclass 24, count 0 2006.210.07:31:09.21#ibcon#wrote, iclass 24, count 0 2006.210.07:31:09.21#ibcon#about to read 3, iclass 24, count 0 2006.210.07:31:09.22#ibcon#read 3, iclass 24, count 0 2006.210.07:31:09.22#ibcon#about to read 4, iclass 24, count 0 2006.210.07:31:09.22#ibcon#read 4, iclass 24, count 0 2006.210.07:31:09.22#ibcon#about to read 5, iclass 24, count 0 2006.210.07:31:09.22#ibcon#read 5, iclass 24, count 0 2006.210.07:31:09.22#ibcon#about to read 6, iclass 24, count 0 2006.210.07:31:09.22#ibcon#read 6, iclass 24, count 0 2006.210.07:31:09.22#ibcon#end of sib2, iclass 24, count 0 2006.210.07:31:09.22#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:31:09.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:31:09.22#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:31:09.22#ibcon#*before write, iclass 24, count 0 2006.210.07:31:09.22#ibcon#enter sib2, iclass 24, count 0 2006.210.07:31:09.22#ibcon#flushed, iclass 24, count 0 2006.210.07:31:09.22#ibcon#about to write, iclass 24, count 0 2006.210.07:31:09.22#ibcon#wrote, iclass 24, count 0 2006.210.07:31:09.22#ibcon#about to read 3, iclass 24, count 0 2006.210.07:31:09.26#ibcon#read 3, iclass 24, count 0 2006.210.07:31:09.26#ibcon#about to read 4, iclass 24, count 0 2006.210.07:31:09.26#ibcon#read 4, iclass 24, count 0 2006.210.07:31:09.26#ibcon#about to read 5, iclass 24, count 0 2006.210.07:31:09.26#ibcon#read 5, iclass 24, count 0 2006.210.07:31:09.26#ibcon#about to read 6, iclass 24, count 0 2006.210.07:31:09.26#ibcon#read 6, iclass 24, count 0 2006.210.07:31:09.26#ibcon#end of sib2, iclass 24, count 0 2006.210.07:31:09.26#ibcon#*after write, iclass 24, count 0 2006.210.07:31:09.26#ibcon#*before return 0, iclass 24, count 0 2006.210.07:31:09.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:09.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:09.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:31:09.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:31:09.27$vc4f8/va=6,6 2006.210.07:31:09.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:31:09.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:31:09.27#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:09.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:31:09.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:31:09.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:31:09.31#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:31:09.31#ibcon#first serial, iclass 26, count 2 2006.210.07:31:09.31#ibcon#enter sib2, iclass 26, count 2 2006.210.07:31:09.31#ibcon#flushed, iclass 26, count 2 2006.210.07:31:09.31#ibcon#about to write, iclass 26, count 2 2006.210.07:31:09.31#ibcon#wrote, iclass 26, count 2 2006.210.07:31:09.31#ibcon#about to read 3, iclass 26, count 2 2006.210.07:31:09.33#ibcon#read 3, iclass 26, count 2 2006.210.07:31:09.33#ibcon#about to read 4, iclass 26, count 2 2006.210.07:31:09.33#ibcon#read 4, iclass 26, count 2 2006.210.07:31:09.33#ibcon#about to read 5, iclass 26, count 2 2006.210.07:31:09.33#ibcon#read 5, iclass 26, count 2 2006.210.07:31:09.33#ibcon#about to read 6, iclass 26, count 2 2006.210.07:31:09.33#ibcon#read 6, iclass 26, count 2 2006.210.07:31:09.33#ibcon#end of sib2, iclass 26, count 2 2006.210.07:31:09.33#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:31:09.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:31:09.33#ibcon#[25=AT06-06\r\n] 2006.210.07:31:09.33#ibcon#*before write, iclass 26, count 2 2006.210.07:31:09.33#ibcon#enter sib2, iclass 26, count 2 2006.210.07:31:09.33#ibcon#flushed, iclass 26, count 2 2006.210.07:31:09.33#ibcon#about to write, iclass 26, count 2 2006.210.07:31:09.33#ibcon#wrote, iclass 26, count 2 2006.210.07:31:09.33#ibcon#about to read 3, iclass 26, count 2 2006.210.07:31:09.36#ibcon#read 3, iclass 26, count 2 2006.210.07:31:09.36#ibcon#about to read 4, iclass 26, count 2 2006.210.07:31:09.36#ibcon#read 4, iclass 26, count 2 2006.210.07:31:09.36#ibcon#about to read 5, iclass 26, count 2 2006.210.07:31:09.36#ibcon#read 5, iclass 26, count 2 2006.210.07:31:09.36#ibcon#about to read 6, iclass 26, count 2 2006.210.07:31:09.36#ibcon#read 6, iclass 26, count 2 2006.210.07:31:09.36#ibcon#end of sib2, iclass 26, count 2 2006.210.07:31:09.36#ibcon#*after write, iclass 26, count 2 2006.210.07:31:09.36#ibcon#*before return 0, iclass 26, count 2 2006.210.07:31:09.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:31:09.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:31:09.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:31:09.36#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:09.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:31:09.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:31:09.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:31:09.48#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:31:09.48#ibcon#first serial, iclass 26, count 0 2006.210.07:31:09.48#ibcon#enter sib2, iclass 26, count 0 2006.210.07:31:09.48#ibcon#flushed, iclass 26, count 0 2006.210.07:31:09.48#ibcon#about to write, iclass 26, count 0 2006.210.07:31:09.48#ibcon#wrote, iclass 26, count 0 2006.210.07:31:09.48#ibcon#about to read 3, iclass 26, count 0 2006.210.07:31:09.50#ibcon#read 3, iclass 26, count 0 2006.210.07:31:09.50#ibcon#about to read 4, iclass 26, count 0 2006.210.07:31:09.50#ibcon#read 4, iclass 26, count 0 2006.210.07:31:09.50#ibcon#about to read 5, iclass 26, count 0 2006.210.07:31:09.50#ibcon#read 5, iclass 26, count 0 2006.210.07:31:09.50#ibcon#about to read 6, iclass 26, count 0 2006.210.07:31:09.50#ibcon#read 6, iclass 26, count 0 2006.210.07:31:09.50#ibcon#end of sib2, iclass 26, count 0 2006.210.07:31:09.50#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:31:09.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:31:09.50#ibcon#[25=USB\r\n] 2006.210.07:31:09.50#ibcon#*before write, iclass 26, count 0 2006.210.07:31:09.50#ibcon#enter sib2, iclass 26, count 0 2006.210.07:31:09.50#ibcon#flushed, iclass 26, count 0 2006.210.07:31:09.50#ibcon#about to write, iclass 26, count 0 2006.210.07:31:09.50#ibcon#wrote, iclass 26, count 0 2006.210.07:31:09.50#ibcon#about to read 3, iclass 26, count 0 2006.210.07:31:09.53#ibcon#read 3, iclass 26, count 0 2006.210.07:31:09.53#ibcon#about to read 4, iclass 26, count 0 2006.210.07:31:09.53#ibcon#read 4, iclass 26, count 0 2006.210.07:31:09.53#ibcon#about to read 5, iclass 26, count 0 2006.210.07:31:09.53#ibcon#read 5, iclass 26, count 0 2006.210.07:31:09.53#ibcon#about to read 6, iclass 26, count 0 2006.210.07:31:09.53#ibcon#read 6, iclass 26, count 0 2006.210.07:31:09.53#ibcon#end of sib2, iclass 26, count 0 2006.210.07:31:09.53#ibcon#*after write, iclass 26, count 0 2006.210.07:31:09.53#ibcon#*before return 0, iclass 26, count 0 2006.210.07:31:09.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:31:09.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:31:09.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:31:09.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:31:09.54$vc4f8/valo=7,832.99 2006.210.07:31:09.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:31:09.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:31:09.54#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:09.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:31:09.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:31:09.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:31:09.54#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:31:09.54#ibcon#first serial, iclass 28, count 0 2006.210.07:31:09.54#ibcon#enter sib2, iclass 28, count 0 2006.210.07:31:09.54#ibcon#flushed, iclass 28, count 0 2006.210.07:31:09.54#ibcon#about to write, iclass 28, count 0 2006.210.07:31:09.54#ibcon#wrote, iclass 28, count 0 2006.210.07:31:09.54#ibcon#about to read 3, iclass 28, count 0 2006.210.07:31:09.55#ibcon#read 3, iclass 28, count 0 2006.210.07:31:09.55#ibcon#about to read 4, iclass 28, count 0 2006.210.07:31:09.55#ibcon#read 4, iclass 28, count 0 2006.210.07:31:09.55#ibcon#about to read 5, iclass 28, count 0 2006.210.07:31:09.55#ibcon#read 5, iclass 28, count 0 2006.210.07:31:09.55#ibcon#about to read 6, iclass 28, count 0 2006.210.07:31:09.55#ibcon#read 6, iclass 28, count 0 2006.210.07:31:09.55#ibcon#end of sib2, iclass 28, count 0 2006.210.07:31:09.55#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:31:09.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:31:09.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:31:09.55#ibcon#*before write, iclass 28, count 0 2006.210.07:31:09.55#ibcon#enter sib2, iclass 28, count 0 2006.210.07:31:09.55#ibcon#flushed, iclass 28, count 0 2006.210.07:31:09.55#ibcon#about to write, iclass 28, count 0 2006.210.07:31:09.55#ibcon#wrote, iclass 28, count 0 2006.210.07:31:09.55#ibcon#about to read 3, iclass 28, count 0 2006.210.07:31:09.59#ibcon#read 3, iclass 28, count 0 2006.210.07:31:09.59#ibcon#about to read 4, iclass 28, count 0 2006.210.07:31:09.59#ibcon#read 4, iclass 28, count 0 2006.210.07:31:09.59#ibcon#about to read 5, iclass 28, count 0 2006.210.07:31:09.59#ibcon#read 5, iclass 28, count 0 2006.210.07:31:09.59#ibcon#about to read 6, iclass 28, count 0 2006.210.07:31:09.59#ibcon#read 6, iclass 28, count 0 2006.210.07:31:09.59#ibcon#end of sib2, iclass 28, count 0 2006.210.07:31:09.59#ibcon#*after write, iclass 28, count 0 2006.210.07:31:09.59#ibcon#*before return 0, iclass 28, count 0 2006.210.07:31:09.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:31:09.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:31:09.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:31:09.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:31:09.60$vc4f8/va=7,6 2006.210.07:31:09.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:31:09.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:31:09.60#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:09.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:31:09.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:31:09.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:31:09.64#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:31:09.64#ibcon#first serial, iclass 30, count 2 2006.210.07:31:09.64#ibcon#enter sib2, iclass 30, count 2 2006.210.07:31:09.64#ibcon#flushed, iclass 30, count 2 2006.210.07:31:09.64#ibcon#about to write, iclass 30, count 2 2006.210.07:31:09.64#ibcon#wrote, iclass 30, count 2 2006.210.07:31:09.64#ibcon#about to read 3, iclass 30, count 2 2006.210.07:31:09.66#ibcon#read 3, iclass 30, count 2 2006.210.07:31:09.66#ibcon#about to read 4, iclass 30, count 2 2006.210.07:31:09.66#ibcon#read 4, iclass 30, count 2 2006.210.07:31:09.66#ibcon#about to read 5, iclass 30, count 2 2006.210.07:31:09.66#ibcon#read 5, iclass 30, count 2 2006.210.07:31:09.66#ibcon#about to read 6, iclass 30, count 2 2006.210.07:31:09.66#ibcon#read 6, iclass 30, count 2 2006.210.07:31:09.66#ibcon#end of sib2, iclass 30, count 2 2006.210.07:31:09.66#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:31:09.66#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:31:09.66#ibcon#[25=AT07-06\r\n] 2006.210.07:31:09.66#ibcon#*before write, iclass 30, count 2 2006.210.07:31:09.66#ibcon#enter sib2, iclass 30, count 2 2006.210.07:31:09.66#ibcon#flushed, iclass 30, count 2 2006.210.07:31:09.66#ibcon#about to write, iclass 30, count 2 2006.210.07:31:09.66#ibcon#wrote, iclass 30, count 2 2006.210.07:31:09.66#ibcon#about to read 3, iclass 30, count 2 2006.210.07:31:09.69#ibcon#read 3, iclass 30, count 2 2006.210.07:31:09.69#ibcon#about to read 4, iclass 30, count 2 2006.210.07:31:09.69#ibcon#read 4, iclass 30, count 2 2006.210.07:31:09.69#ibcon#about to read 5, iclass 30, count 2 2006.210.07:31:09.69#ibcon#read 5, iclass 30, count 2 2006.210.07:31:09.69#ibcon#about to read 6, iclass 30, count 2 2006.210.07:31:09.69#ibcon#read 6, iclass 30, count 2 2006.210.07:31:09.69#ibcon#end of sib2, iclass 30, count 2 2006.210.07:31:09.69#ibcon#*after write, iclass 30, count 2 2006.210.07:31:09.69#ibcon#*before return 0, iclass 30, count 2 2006.210.07:31:09.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:31:09.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:31:09.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:31:09.69#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:09.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:31:09.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:31:09.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:31:09.81#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:31:09.81#ibcon#first serial, iclass 30, count 0 2006.210.07:31:09.81#ibcon#enter sib2, iclass 30, count 0 2006.210.07:31:09.81#ibcon#flushed, iclass 30, count 0 2006.210.07:31:09.81#ibcon#about to write, iclass 30, count 0 2006.210.07:31:09.81#ibcon#wrote, iclass 30, count 0 2006.210.07:31:09.81#ibcon#about to read 3, iclass 30, count 0 2006.210.07:31:09.83#ibcon#read 3, iclass 30, count 0 2006.210.07:31:09.83#ibcon#about to read 4, iclass 30, count 0 2006.210.07:31:09.83#ibcon#read 4, iclass 30, count 0 2006.210.07:31:09.83#ibcon#about to read 5, iclass 30, count 0 2006.210.07:31:09.83#ibcon#read 5, iclass 30, count 0 2006.210.07:31:09.83#ibcon#about to read 6, iclass 30, count 0 2006.210.07:31:09.83#ibcon#read 6, iclass 30, count 0 2006.210.07:31:09.83#ibcon#end of sib2, iclass 30, count 0 2006.210.07:31:09.83#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:31:09.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:31:09.83#ibcon#[25=USB\r\n] 2006.210.07:31:09.83#ibcon#*before write, iclass 30, count 0 2006.210.07:31:09.83#ibcon#enter sib2, iclass 30, count 0 2006.210.07:31:09.83#ibcon#flushed, iclass 30, count 0 2006.210.07:31:09.83#ibcon#about to write, iclass 30, count 0 2006.210.07:31:09.83#ibcon#wrote, iclass 30, count 0 2006.210.07:31:09.83#ibcon#about to read 3, iclass 30, count 0 2006.210.07:31:09.86#ibcon#read 3, iclass 30, count 0 2006.210.07:31:09.86#ibcon#about to read 4, iclass 30, count 0 2006.210.07:31:09.86#ibcon#read 4, iclass 30, count 0 2006.210.07:31:09.86#ibcon#about to read 5, iclass 30, count 0 2006.210.07:31:09.86#ibcon#read 5, iclass 30, count 0 2006.210.07:31:09.86#ibcon#about to read 6, iclass 30, count 0 2006.210.07:31:09.86#ibcon#read 6, iclass 30, count 0 2006.210.07:31:09.86#ibcon#end of sib2, iclass 30, count 0 2006.210.07:31:09.86#ibcon#*after write, iclass 30, count 0 2006.210.07:31:09.86#ibcon#*before return 0, iclass 30, count 0 2006.210.07:31:09.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:31:09.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:31:09.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:31:09.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:31:09.87$vc4f8/valo=8,852.99 2006.210.07:31:09.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:31:09.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:31:09.87#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:09.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:31:09.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:31:09.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:31:09.87#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:31:09.87#ibcon#first serial, iclass 32, count 0 2006.210.07:31:09.87#ibcon#enter sib2, iclass 32, count 0 2006.210.07:31:09.87#ibcon#flushed, iclass 32, count 0 2006.210.07:31:09.87#ibcon#about to write, iclass 32, count 0 2006.210.07:31:09.87#ibcon#wrote, iclass 32, count 0 2006.210.07:31:09.87#ibcon#about to read 3, iclass 32, count 0 2006.210.07:31:09.88#ibcon#read 3, iclass 32, count 0 2006.210.07:31:09.88#ibcon#about to read 4, iclass 32, count 0 2006.210.07:31:09.88#ibcon#read 4, iclass 32, count 0 2006.210.07:31:09.88#ibcon#about to read 5, iclass 32, count 0 2006.210.07:31:09.88#ibcon#read 5, iclass 32, count 0 2006.210.07:31:09.88#ibcon#about to read 6, iclass 32, count 0 2006.210.07:31:09.88#ibcon#read 6, iclass 32, count 0 2006.210.07:31:09.88#ibcon#end of sib2, iclass 32, count 0 2006.210.07:31:09.88#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:31:09.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:31:09.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:31:09.88#ibcon#*before write, iclass 32, count 0 2006.210.07:31:09.88#ibcon#enter sib2, iclass 32, count 0 2006.210.07:31:09.88#ibcon#flushed, iclass 32, count 0 2006.210.07:31:09.88#ibcon#about to write, iclass 32, count 0 2006.210.07:31:09.88#ibcon#wrote, iclass 32, count 0 2006.210.07:31:09.88#ibcon#about to read 3, iclass 32, count 0 2006.210.07:31:09.92#ibcon#read 3, iclass 32, count 0 2006.210.07:31:09.92#ibcon#about to read 4, iclass 32, count 0 2006.210.07:31:09.92#ibcon#read 4, iclass 32, count 0 2006.210.07:31:09.92#ibcon#about to read 5, iclass 32, count 0 2006.210.07:31:09.92#ibcon#read 5, iclass 32, count 0 2006.210.07:31:09.92#ibcon#about to read 6, iclass 32, count 0 2006.210.07:31:09.92#ibcon#read 6, iclass 32, count 0 2006.210.07:31:09.92#ibcon#end of sib2, iclass 32, count 0 2006.210.07:31:09.92#ibcon#*after write, iclass 32, count 0 2006.210.07:31:09.92#ibcon#*before return 0, iclass 32, count 0 2006.210.07:31:09.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:31:09.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:31:09.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:31:09.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:31:09.93$vc4f8/va=8,7 2006.210.07:31:09.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:31:09.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:31:09.93#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:09.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:31:09.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:31:09.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:31:09.97#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:31:09.97#ibcon#first serial, iclass 34, count 2 2006.210.07:31:09.97#ibcon#enter sib2, iclass 34, count 2 2006.210.07:31:09.97#ibcon#flushed, iclass 34, count 2 2006.210.07:31:09.97#ibcon#about to write, iclass 34, count 2 2006.210.07:31:09.97#ibcon#wrote, iclass 34, count 2 2006.210.07:31:09.97#ibcon#about to read 3, iclass 34, count 2 2006.210.07:31:09.99#ibcon#read 3, iclass 34, count 2 2006.210.07:31:09.99#ibcon#about to read 4, iclass 34, count 2 2006.210.07:31:09.99#ibcon#read 4, iclass 34, count 2 2006.210.07:31:09.99#ibcon#about to read 5, iclass 34, count 2 2006.210.07:31:09.99#ibcon#read 5, iclass 34, count 2 2006.210.07:31:09.99#ibcon#about to read 6, iclass 34, count 2 2006.210.07:31:09.99#ibcon#read 6, iclass 34, count 2 2006.210.07:31:09.99#ibcon#end of sib2, iclass 34, count 2 2006.210.07:31:09.99#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:31:09.99#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:31:09.99#ibcon#[25=AT08-07\r\n] 2006.210.07:31:09.99#ibcon#*before write, iclass 34, count 2 2006.210.07:31:09.99#ibcon#enter sib2, iclass 34, count 2 2006.210.07:31:09.99#ibcon#flushed, iclass 34, count 2 2006.210.07:31:09.99#ibcon#about to write, iclass 34, count 2 2006.210.07:31:09.99#ibcon#wrote, iclass 34, count 2 2006.210.07:31:09.99#ibcon#about to read 3, iclass 34, count 2 2006.210.07:31:10.02#ibcon#read 3, iclass 34, count 2 2006.210.07:31:10.02#ibcon#about to read 4, iclass 34, count 2 2006.210.07:31:10.02#ibcon#read 4, iclass 34, count 2 2006.210.07:31:10.02#ibcon#about to read 5, iclass 34, count 2 2006.210.07:31:10.02#ibcon#read 5, iclass 34, count 2 2006.210.07:31:10.02#ibcon#about to read 6, iclass 34, count 2 2006.210.07:31:10.02#ibcon#read 6, iclass 34, count 2 2006.210.07:31:10.02#ibcon#end of sib2, iclass 34, count 2 2006.210.07:31:10.02#ibcon#*after write, iclass 34, count 2 2006.210.07:31:10.02#ibcon#*before return 0, iclass 34, count 2 2006.210.07:31:10.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:31:10.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:31:10.02#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:31:10.02#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.02#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:31:10.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:31:10.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:31:10.15#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:31:10.15#ibcon#first serial, iclass 34, count 0 2006.210.07:31:10.15#ibcon#enter sib2, iclass 34, count 0 2006.210.07:31:10.15#ibcon#flushed, iclass 34, count 0 2006.210.07:31:10.15#ibcon#about to write, iclass 34, count 0 2006.210.07:31:10.15#ibcon#wrote, iclass 34, count 0 2006.210.07:31:10.15#ibcon#about to read 3, iclass 34, count 0 2006.210.07:31:10.16#ibcon#read 3, iclass 34, count 0 2006.210.07:31:10.16#ibcon#about to read 4, iclass 34, count 0 2006.210.07:31:10.16#ibcon#read 4, iclass 34, count 0 2006.210.07:31:10.16#ibcon#about to read 5, iclass 34, count 0 2006.210.07:31:10.16#ibcon#read 5, iclass 34, count 0 2006.210.07:31:10.16#ibcon#about to read 6, iclass 34, count 0 2006.210.07:31:10.16#ibcon#read 6, iclass 34, count 0 2006.210.07:31:10.16#ibcon#end of sib2, iclass 34, count 0 2006.210.07:31:10.16#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:31:10.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:31:10.16#ibcon#[25=USB\r\n] 2006.210.07:31:10.16#ibcon#*before write, iclass 34, count 0 2006.210.07:31:10.16#ibcon#enter sib2, iclass 34, count 0 2006.210.07:31:10.16#ibcon#flushed, iclass 34, count 0 2006.210.07:31:10.16#ibcon#about to write, iclass 34, count 0 2006.210.07:31:10.16#ibcon#wrote, iclass 34, count 0 2006.210.07:31:10.16#ibcon#about to read 3, iclass 34, count 0 2006.210.07:31:10.19#ibcon#read 3, iclass 34, count 0 2006.210.07:31:10.19#ibcon#about to read 4, iclass 34, count 0 2006.210.07:31:10.19#ibcon#read 4, iclass 34, count 0 2006.210.07:31:10.19#ibcon#about to read 5, iclass 34, count 0 2006.210.07:31:10.19#ibcon#read 5, iclass 34, count 0 2006.210.07:31:10.19#ibcon#about to read 6, iclass 34, count 0 2006.210.07:31:10.19#ibcon#read 6, iclass 34, count 0 2006.210.07:31:10.19#ibcon#end of sib2, iclass 34, count 0 2006.210.07:31:10.19#ibcon#*after write, iclass 34, count 0 2006.210.07:31:10.19#ibcon#*before return 0, iclass 34, count 0 2006.210.07:31:10.19#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:31:10.19#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:31:10.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:31:10.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:31:10.20$vc4f8/vblo=1,632.99 2006.210.07:31:10.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:31:10.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:31:10.20#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:10.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:31:10.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:31:10.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:31:10.20#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:31:10.20#ibcon#first serial, iclass 36, count 0 2006.210.07:31:10.20#ibcon#enter sib2, iclass 36, count 0 2006.210.07:31:10.20#ibcon#flushed, iclass 36, count 0 2006.210.07:31:10.20#ibcon#about to write, iclass 36, count 0 2006.210.07:31:10.20#ibcon#wrote, iclass 36, count 0 2006.210.07:31:10.20#ibcon#about to read 3, iclass 36, count 0 2006.210.07:31:10.21#ibcon#read 3, iclass 36, count 0 2006.210.07:31:10.21#ibcon#about to read 4, iclass 36, count 0 2006.210.07:31:10.21#ibcon#read 4, iclass 36, count 0 2006.210.07:31:10.21#ibcon#about to read 5, iclass 36, count 0 2006.210.07:31:10.21#ibcon#read 5, iclass 36, count 0 2006.210.07:31:10.21#ibcon#about to read 6, iclass 36, count 0 2006.210.07:31:10.21#ibcon#read 6, iclass 36, count 0 2006.210.07:31:10.21#ibcon#end of sib2, iclass 36, count 0 2006.210.07:31:10.21#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:31:10.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:31:10.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:31:10.21#ibcon#*before write, iclass 36, count 0 2006.210.07:31:10.21#ibcon#enter sib2, iclass 36, count 0 2006.210.07:31:10.21#ibcon#flushed, iclass 36, count 0 2006.210.07:31:10.21#ibcon#about to write, iclass 36, count 0 2006.210.07:31:10.21#ibcon#wrote, iclass 36, count 0 2006.210.07:31:10.21#ibcon#about to read 3, iclass 36, count 0 2006.210.07:31:10.25#ibcon#read 3, iclass 36, count 0 2006.210.07:31:10.25#ibcon#about to read 4, iclass 36, count 0 2006.210.07:31:10.25#ibcon#read 4, iclass 36, count 0 2006.210.07:31:10.25#ibcon#about to read 5, iclass 36, count 0 2006.210.07:31:10.25#ibcon#read 5, iclass 36, count 0 2006.210.07:31:10.25#ibcon#about to read 6, iclass 36, count 0 2006.210.07:31:10.25#ibcon#read 6, iclass 36, count 0 2006.210.07:31:10.25#ibcon#end of sib2, iclass 36, count 0 2006.210.07:31:10.25#ibcon#*after write, iclass 36, count 0 2006.210.07:31:10.25#ibcon#*before return 0, iclass 36, count 0 2006.210.07:31:10.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:31:10.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:31:10.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:31:10.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:31:10.26$vc4f8/vb=1,4 2006.210.07:31:10.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:31:10.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:31:10.26#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:10.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:31:10.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:31:10.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:31:10.26#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:31:10.26#ibcon#first serial, iclass 38, count 2 2006.210.07:31:10.26#ibcon#enter sib2, iclass 38, count 2 2006.210.07:31:10.26#ibcon#flushed, iclass 38, count 2 2006.210.07:31:10.26#ibcon#about to write, iclass 38, count 2 2006.210.07:31:10.26#ibcon#wrote, iclass 38, count 2 2006.210.07:31:10.26#ibcon#about to read 3, iclass 38, count 2 2006.210.07:31:10.27#ibcon#read 3, iclass 38, count 2 2006.210.07:31:10.27#ibcon#about to read 4, iclass 38, count 2 2006.210.07:31:10.27#ibcon#read 4, iclass 38, count 2 2006.210.07:31:10.27#ibcon#about to read 5, iclass 38, count 2 2006.210.07:31:10.27#ibcon#read 5, iclass 38, count 2 2006.210.07:31:10.27#ibcon#about to read 6, iclass 38, count 2 2006.210.07:31:10.27#ibcon#read 6, iclass 38, count 2 2006.210.07:31:10.27#ibcon#end of sib2, iclass 38, count 2 2006.210.07:31:10.27#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:31:10.27#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:31:10.27#ibcon#[27=AT01-04\r\n] 2006.210.07:31:10.27#ibcon#*before write, iclass 38, count 2 2006.210.07:31:10.27#ibcon#enter sib2, iclass 38, count 2 2006.210.07:31:10.27#ibcon#flushed, iclass 38, count 2 2006.210.07:31:10.27#ibcon#about to write, iclass 38, count 2 2006.210.07:31:10.27#ibcon#wrote, iclass 38, count 2 2006.210.07:31:10.27#ibcon#about to read 3, iclass 38, count 2 2006.210.07:31:10.30#ibcon#read 3, iclass 38, count 2 2006.210.07:31:10.30#ibcon#about to read 4, iclass 38, count 2 2006.210.07:31:10.30#ibcon#read 4, iclass 38, count 2 2006.210.07:31:10.30#ibcon#about to read 5, iclass 38, count 2 2006.210.07:31:10.30#ibcon#read 5, iclass 38, count 2 2006.210.07:31:10.30#ibcon#about to read 6, iclass 38, count 2 2006.210.07:31:10.30#ibcon#read 6, iclass 38, count 2 2006.210.07:31:10.30#ibcon#end of sib2, iclass 38, count 2 2006.210.07:31:10.30#ibcon#*after write, iclass 38, count 2 2006.210.07:31:10.30#ibcon#*before return 0, iclass 38, count 2 2006.210.07:31:10.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:31:10.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:31:10.30#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:31:10.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.30#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:31:10.42#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:31:10.42#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:31:10.42#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:31:10.42#ibcon#first serial, iclass 38, count 0 2006.210.07:31:10.42#ibcon#enter sib2, iclass 38, count 0 2006.210.07:31:10.42#ibcon#flushed, iclass 38, count 0 2006.210.07:31:10.42#ibcon#about to write, iclass 38, count 0 2006.210.07:31:10.42#ibcon#wrote, iclass 38, count 0 2006.210.07:31:10.42#ibcon#about to read 3, iclass 38, count 0 2006.210.07:31:10.44#ibcon#read 3, iclass 38, count 0 2006.210.07:31:10.44#ibcon#about to read 4, iclass 38, count 0 2006.210.07:31:10.44#ibcon#read 4, iclass 38, count 0 2006.210.07:31:10.44#ibcon#about to read 5, iclass 38, count 0 2006.210.07:31:10.44#ibcon#read 5, iclass 38, count 0 2006.210.07:31:10.44#ibcon#about to read 6, iclass 38, count 0 2006.210.07:31:10.44#ibcon#read 6, iclass 38, count 0 2006.210.07:31:10.44#ibcon#end of sib2, iclass 38, count 0 2006.210.07:31:10.44#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:31:10.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:31:10.44#ibcon#[27=USB\r\n] 2006.210.07:31:10.44#ibcon#*before write, iclass 38, count 0 2006.210.07:31:10.44#ibcon#enter sib2, iclass 38, count 0 2006.210.07:31:10.44#ibcon#flushed, iclass 38, count 0 2006.210.07:31:10.44#ibcon#about to write, iclass 38, count 0 2006.210.07:31:10.44#ibcon#wrote, iclass 38, count 0 2006.210.07:31:10.44#ibcon#about to read 3, iclass 38, count 0 2006.210.07:31:10.47#ibcon#read 3, iclass 38, count 0 2006.210.07:31:10.47#ibcon#about to read 4, iclass 38, count 0 2006.210.07:31:10.47#ibcon#read 4, iclass 38, count 0 2006.210.07:31:10.47#ibcon#about to read 5, iclass 38, count 0 2006.210.07:31:10.47#ibcon#read 5, iclass 38, count 0 2006.210.07:31:10.47#ibcon#about to read 6, iclass 38, count 0 2006.210.07:31:10.47#ibcon#read 6, iclass 38, count 0 2006.210.07:31:10.47#ibcon#end of sib2, iclass 38, count 0 2006.210.07:31:10.47#ibcon#*after write, iclass 38, count 0 2006.210.07:31:10.47#ibcon#*before return 0, iclass 38, count 0 2006.210.07:31:10.47#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:31:10.47#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:31:10.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:31:10.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:31:10.48$vc4f8/vblo=2,640.99 2006.210.07:31:10.48#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:31:10.48#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:31:10.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:10.48#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:10.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:10.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:10.48#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:31:10.48#ibcon#first serial, iclass 40, count 0 2006.210.07:31:10.48#ibcon#enter sib2, iclass 40, count 0 2006.210.07:31:10.48#ibcon#flushed, iclass 40, count 0 2006.210.07:31:10.48#ibcon#about to write, iclass 40, count 0 2006.210.07:31:10.48#ibcon#wrote, iclass 40, count 0 2006.210.07:31:10.48#ibcon#about to read 3, iclass 40, count 0 2006.210.07:31:10.49#ibcon#read 3, iclass 40, count 0 2006.210.07:31:10.49#ibcon#about to read 4, iclass 40, count 0 2006.210.07:31:10.49#ibcon#read 4, iclass 40, count 0 2006.210.07:31:10.49#ibcon#about to read 5, iclass 40, count 0 2006.210.07:31:10.49#ibcon#read 5, iclass 40, count 0 2006.210.07:31:10.49#ibcon#about to read 6, iclass 40, count 0 2006.210.07:31:10.49#ibcon#read 6, iclass 40, count 0 2006.210.07:31:10.49#ibcon#end of sib2, iclass 40, count 0 2006.210.07:31:10.49#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:31:10.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:31:10.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:31:10.49#ibcon#*before write, iclass 40, count 0 2006.210.07:31:10.49#ibcon#enter sib2, iclass 40, count 0 2006.210.07:31:10.49#ibcon#flushed, iclass 40, count 0 2006.210.07:31:10.49#ibcon#about to write, iclass 40, count 0 2006.210.07:31:10.49#ibcon#wrote, iclass 40, count 0 2006.210.07:31:10.49#ibcon#about to read 3, iclass 40, count 0 2006.210.07:31:10.53#ibcon#read 3, iclass 40, count 0 2006.210.07:31:10.53#ibcon#about to read 4, iclass 40, count 0 2006.210.07:31:10.53#ibcon#read 4, iclass 40, count 0 2006.210.07:31:10.53#ibcon#about to read 5, iclass 40, count 0 2006.210.07:31:10.53#ibcon#read 5, iclass 40, count 0 2006.210.07:31:10.53#ibcon#about to read 6, iclass 40, count 0 2006.210.07:31:10.53#ibcon#read 6, iclass 40, count 0 2006.210.07:31:10.53#ibcon#end of sib2, iclass 40, count 0 2006.210.07:31:10.53#ibcon#*after write, iclass 40, count 0 2006.210.07:31:10.53#ibcon#*before return 0, iclass 40, count 0 2006.210.07:31:10.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:10.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:31:10.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:31:10.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:31:10.54$vc4f8/vb=2,4 2006.210.07:31:10.54#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:31:10.54#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:31:10.54#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:10.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:10.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:10.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:10.58#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:31:10.58#ibcon#first serial, iclass 4, count 2 2006.210.07:31:10.58#ibcon#enter sib2, iclass 4, count 2 2006.210.07:31:10.58#ibcon#flushed, iclass 4, count 2 2006.210.07:31:10.58#ibcon#about to write, iclass 4, count 2 2006.210.07:31:10.58#ibcon#wrote, iclass 4, count 2 2006.210.07:31:10.58#ibcon#about to read 3, iclass 4, count 2 2006.210.07:31:10.60#ibcon#read 3, iclass 4, count 2 2006.210.07:31:10.60#ibcon#about to read 4, iclass 4, count 2 2006.210.07:31:10.60#ibcon#read 4, iclass 4, count 2 2006.210.07:31:10.60#ibcon#about to read 5, iclass 4, count 2 2006.210.07:31:10.60#ibcon#read 5, iclass 4, count 2 2006.210.07:31:10.60#ibcon#about to read 6, iclass 4, count 2 2006.210.07:31:10.60#ibcon#read 6, iclass 4, count 2 2006.210.07:31:10.60#ibcon#end of sib2, iclass 4, count 2 2006.210.07:31:10.60#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:31:10.60#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:31:10.60#ibcon#[27=AT02-04\r\n] 2006.210.07:31:10.60#ibcon#*before write, iclass 4, count 2 2006.210.07:31:10.60#ibcon#enter sib2, iclass 4, count 2 2006.210.07:31:10.60#ibcon#flushed, iclass 4, count 2 2006.210.07:31:10.60#ibcon#about to write, iclass 4, count 2 2006.210.07:31:10.60#ibcon#wrote, iclass 4, count 2 2006.210.07:31:10.60#ibcon#about to read 3, iclass 4, count 2 2006.210.07:31:10.63#ibcon#read 3, iclass 4, count 2 2006.210.07:31:10.63#ibcon#about to read 4, iclass 4, count 2 2006.210.07:31:10.63#ibcon#read 4, iclass 4, count 2 2006.210.07:31:10.63#ibcon#about to read 5, iclass 4, count 2 2006.210.07:31:10.63#ibcon#read 5, iclass 4, count 2 2006.210.07:31:10.63#ibcon#about to read 6, iclass 4, count 2 2006.210.07:31:10.63#ibcon#read 6, iclass 4, count 2 2006.210.07:31:10.63#ibcon#end of sib2, iclass 4, count 2 2006.210.07:31:10.63#ibcon#*after write, iclass 4, count 2 2006.210.07:31:10.63#ibcon#*before return 0, iclass 4, count 2 2006.210.07:31:10.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:10.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:31:10.63#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:31:10.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.63#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:10.75#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:10.75#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:10.75#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:31:10.75#ibcon#first serial, iclass 4, count 0 2006.210.07:31:10.75#ibcon#enter sib2, iclass 4, count 0 2006.210.07:31:10.75#ibcon#flushed, iclass 4, count 0 2006.210.07:31:10.75#ibcon#about to write, iclass 4, count 0 2006.210.07:31:10.75#ibcon#wrote, iclass 4, count 0 2006.210.07:31:10.75#ibcon#about to read 3, iclass 4, count 0 2006.210.07:31:10.77#ibcon#read 3, iclass 4, count 0 2006.210.07:31:10.77#ibcon#about to read 4, iclass 4, count 0 2006.210.07:31:10.77#ibcon#read 4, iclass 4, count 0 2006.210.07:31:10.77#ibcon#about to read 5, iclass 4, count 0 2006.210.07:31:10.77#ibcon#read 5, iclass 4, count 0 2006.210.07:31:10.77#ibcon#about to read 6, iclass 4, count 0 2006.210.07:31:10.77#ibcon#read 6, iclass 4, count 0 2006.210.07:31:10.77#ibcon#end of sib2, iclass 4, count 0 2006.210.07:31:10.77#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:31:10.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:31:10.77#ibcon#[27=USB\r\n] 2006.210.07:31:10.77#ibcon#*before write, iclass 4, count 0 2006.210.07:31:10.77#ibcon#enter sib2, iclass 4, count 0 2006.210.07:31:10.77#ibcon#flushed, iclass 4, count 0 2006.210.07:31:10.77#ibcon#about to write, iclass 4, count 0 2006.210.07:31:10.77#ibcon#wrote, iclass 4, count 0 2006.210.07:31:10.77#ibcon#about to read 3, iclass 4, count 0 2006.210.07:31:10.80#ibcon#read 3, iclass 4, count 0 2006.210.07:31:10.80#ibcon#about to read 4, iclass 4, count 0 2006.210.07:31:10.80#ibcon#read 4, iclass 4, count 0 2006.210.07:31:10.80#ibcon#about to read 5, iclass 4, count 0 2006.210.07:31:10.80#ibcon#read 5, iclass 4, count 0 2006.210.07:31:10.80#ibcon#about to read 6, iclass 4, count 0 2006.210.07:31:10.80#ibcon#read 6, iclass 4, count 0 2006.210.07:31:10.80#ibcon#end of sib2, iclass 4, count 0 2006.210.07:31:10.80#ibcon#*after write, iclass 4, count 0 2006.210.07:31:10.80#ibcon#*before return 0, iclass 4, count 0 2006.210.07:31:10.80#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:10.80#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:31:10.80#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:31:10.80#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:31:10.81$vc4f8/vblo=3,656.99 2006.210.07:31:10.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:31:10.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:31:10.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:10.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:10.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:10.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:10.81#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:31:10.81#ibcon#first serial, iclass 6, count 0 2006.210.07:31:10.81#ibcon#enter sib2, iclass 6, count 0 2006.210.07:31:10.81#ibcon#flushed, iclass 6, count 0 2006.210.07:31:10.81#ibcon#about to write, iclass 6, count 0 2006.210.07:31:10.81#ibcon#wrote, iclass 6, count 0 2006.210.07:31:10.81#ibcon#about to read 3, iclass 6, count 0 2006.210.07:31:10.82#ibcon#read 3, iclass 6, count 0 2006.210.07:31:10.82#ibcon#about to read 4, iclass 6, count 0 2006.210.07:31:10.82#ibcon#read 4, iclass 6, count 0 2006.210.07:31:10.82#ibcon#about to read 5, iclass 6, count 0 2006.210.07:31:10.82#ibcon#read 5, iclass 6, count 0 2006.210.07:31:10.82#ibcon#about to read 6, iclass 6, count 0 2006.210.07:31:10.82#ibcon#read 6, iclass 6, count 0 2006.210.07:31:10.82#ibcon#end of sib2, iclass 6, count 0 2006.210.07:31:10.82#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:31:10.82#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:31:10.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:31:10.82#ibcon#*before write, iclass 6, count 0 2006.210.07:31:10.82#ibcon#enter sib2, iclass 6, count 0 2006.210.07:31:10.82#ibcon#flushed, iclass 6, count 0 2006.210.07:31:10.82#ibcon#about to write, iclass 6, count 0 2006.210.07:31:10.82#ibcon#wrote, iclass 6, count 0 2006.210.07:31:10.82#ibcon#about to read 3, iclass 6, count 0 2006.210.07:31:10.86#ibcon#read 3, iclass 6, count 0 2006.210.07:31:10.86#ibcon#about to read 4, iclass 6, count 0 2006.210.07:31:10.86#ibcon#read 4, iclass 6, count 0 2006.210.07:31:10.86#ibcon#about to read 5, iclass 6, count 0 2006.210.07:31:10.86#ibcon#read 5, iclass 6, count 0 2006.210.07:31:10.86#ibcon#about to read 6, iclass 6, count 0 2006.210.07:31:10.86#ibcon#read 6, iclass 6, count 0 2006.210.07:31:10.86#ibcon#end of sib2, iclass 6, count 0 2006.210.07:31:10.86#ibcon#*after write, iclass 6, count 0 2006.210.07:31:10.86#ibcon#*before return 0, iclass 6, count 0 2006.210.07:31:10.86#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:10.86#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:31:10.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:31:10.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:31:10.87$vc4f8/vb=3,3 2006.210.07:31:10.87#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:31:10.87#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:31:10.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:10.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:10.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:10.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:10.91#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:31:10.91#ibcon#first serial, iclass 10, count 2 2006.210.07:31:10.91#ibcon#enter sib2, iclass 10, count 2 2006.210.07:31:10.91#ibcon#flushed, iclass 10, count 2 2006.210.07:31:10.91#ibcon#about to write, iclass 10, count 2 2006.210.07:31:10.91#ibcon#wrote, iclass 10, count 2 2006.210.07:31:10.91#ibcon#about to read 3, iclass 10, count 2 2006.210.07:31:10.93#ibcon#read 3, iclass 10, count 2 2006.210.07:31:10.93#ibcon#about to read 4, iclass 10, count 2 2006.210.07:31:10.93#ibcon#read 4, iclass 10, count 2 2006.210.07:31:10.93#ibcon#about to read 5, iclass 10, count 2 2006.210.07:31:10.93#ibcon#read 5, iclass 10, count 2 2006.210.07:31:10.93#ibcon#about to read 6, iclass 10, count 2 2006.210.07:31:10.93#ibcon#read 6, iclass 10, count 2 2006.210.07:31:10.93#ibcon#end of sib2, iclass 10, count 2 2006.210.07:31:10.93#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:31:10.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:31:10.93#ibcon#[27=AT03-03\r\n] 2006.210.07:31:10.93#ibcon#*before write, iclass 10, count 2 2006.210.07:31:10.93#ibcon#enter sib2, iclass 10, count 2 2006.210.07:31:10.93#ibcon#flushed, iclass 10, count 2 2006.210.07:31:10.93#ibcon#about to write, iclass 10, count 2 2006.210.07:31:10.93#ibcon#wrote, iclass 10, count 2 2006.210.07:31:10.93#ibcon#about to read 3, iclass 10, count 2 2006.210.07:31:10.96#ibcon#read 3, iclass 10, count 2 2006.210.07:31:10.96#ibcon#about to read 4, iclass 10, count 2 2006.210.07:31:10.96#ibcon#read 4, iclass 10, count 2 2006.210.07:31:10.96#ibcon#about to read 5, iclass 10, count 2 2006.210.07:31:10.96#ibcon#read 5, iclass 10, count 2 2006.210.07:31:10.96#ibcon#about to read 6, iclass 10, count 2 2006.210.07:31:10.96#ibcon#read 6, iclass 10, count 2 2006.210.07:31:10.96#ibcon#end of sib2, iclass 10, count 2 2006.210.07:31:10.96#ibcon#*after write, iclass 10, count 2 2006.210.07:31:10.96#ibcon#*before return 0, iclass 10, count 2 2006.210.07:31:10.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:10.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:31:10.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:31:10.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:10.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:11.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:11.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:11.08#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:31:11.08#ibcon#first serial, iclass 10, count 0 2006.210.07:31:11.08#ibcon#enter sib2, iclass 10, count 0 2006.210.07:31:11.08#ibcon#flushed, iclass 10, count 0 2006.210.07:31:11.08#ibcon#about to write, iclass 10, count 0 2006.210.07:31:11.08#ibcon#wrote, iclass 10, count 0 2006.210.07:31:11.08#ibcon#about to read 3, iclass 10, count 0 2006.210.07:31:11.10#ibcon#read 3, iclass 10, count 0 2006.210.07:31:11.10#ibcon#about to read 4, iclass 10, count 0 2006.210.07:31:11.10#ibcon#read 4, iclass 10, count 0 2006.210.07:31:11.10#ibcon#about to read 5, iclass 10, count 0 2006.210.07:31:11.10#ibcon#read 5, iclass 10, count 0 2006.210.07:31:11.10#ibcon#about to read 6, iclass 10, count 0 2006.210.07:31:11.10#ibcon#read 6, iclass 10, count 0 2006.210.07:31:11.10#ibcon#end of sib2, iclass 10, count 0 2006.210.07:31:11.10#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:31:11.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:31:11.10#ibcon#[27=USB\r\n] 2006.210.07:31:11.10#ibcon#*before write, iclass 10, count 0 2006.210.07:31:11.10#ibcon#enter sib2, iclass 10, count 0 2006.210.07:31:11.10#ibcon#flushed, iclass 10, count 0 2006.210.07:31:11.10#ibcon#about to write, iclass 10, count 0 2006.210.07:31:11.10#ibcon#wrote, iclass 10, count 0 2006.210.07:31:11.10#ibcon#about to read 3, iclass 10, count 0 2006.210.07:31:11.13#ibcon#read 3, iclass 10, count 0 2006.210.07:31:11.13#ibcon#about to read 4, iclass 10, count 0 2006.210.07:31:11.13#ibcon#read 4, iclass 10, count 0 2006.210.07:31:11.13#ibcon#about to read 5, iclass 10, count 0 2006.210.07:31:11.13#ibcon#read 5, iclass 10, count 0 2006.210.07:31:11.13#ibcon#about to read 6, iclass 10, count 0 2006.210.07:31:11.13#ibcon#read 6, iclass 10, count 0 2006.210.07:31:11.13#ibcon#end of sib2, iclass 10, count 0 2006.210.07:31:11.13#ibcon#*after write, iclass 10, count 0 2006.210.07:31:11.13#ibcon#*before return 0, iclass 10, count 0 2006.210.07:31:11.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:11.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:31:11.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:31:11.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:31:11.14$vc4f8/vblo=4,712.99 2006.210.07:31:11.14#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:31:11.14#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:31:11.14#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:11.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:11.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:11.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:11.14#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:31:11.14#ibcon#first serial, iclass 12, count 0 2006.210.07:31:11.14#ibcon#enter sib2, iclass 12, count 0 2006.210.07:31:11.14#ibcon#flushed, iclass 12, count 0 2006.210.07:31:11.14#ibcon#about to write, iclass 12, count 0 2006.210.07:31:11.14#ibcon#wrote, iclass 12, count 0 2006.210.07:31:11.14#ibcon#about to read 3, iclass 12, count 0 2006.210.07:31:11.15#ibcon#read 3, iclass 12, count 0 2006.210.07:31:11.15#ibcon#about to read 4, iclass 12, count 0 2006.210.07:31:11.15#ibcon#read 4, iclass 12, count 0 2006.210.07:31:11.15#ibcon#about to read 5, iclass 12, count 0 2006.210.07:31:11.15#ibcon#read 5, iclass 12, count 0 2006.210.07:31:11.15#ibcon#about to read 6, iclass 12, count 0 2006.210.07:31:11.15#ibcon#read 6, iclass 12, count 0 2006.210.07:31:11.15#ibcon#end of sib2, iclass 12, count 0 2006.210.07:31:11.15#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:31:11.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:31:11.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:31:11.15#ibcon#*before write, iclass 12, count 0 2006.210.07:31:11.15#ibcon#enter sib2, iclass 12, count 0 2006.210.07:31:11.15#ibcon#flushed, iclass 12, count 0 2006.210.07:31:11.15#ibcon#about to write, iclass 12, count 0 2006.210.07:31:11.15#ibcon#wrote, iclass 12, count 0 2006.210.07:31:11.15#ibcon#about to read 3, iclass 12, count 0 2006.210.07:31:11.19#ibcon#read 3, iclass 12, count 0 2006.210.07:31:11.19#ibcon#about to read 4, iclass 12, count 0 2006.210.07:31:11.19#ibcon#read 4, iclass 12, count 0 2006.210.07:31:11.19#ibcon#about to read 5, iclass 12, count 0 2006.210.07:31:11.19#ibcon#read 5, iclass 12, count 0 2006.210.07:31:11.19#ibcon#about to read 6, iclass 12, count 0 2006.210.07:31:11.19#ibcon#read 6, iclass 12, count 0 2006.210.07:31:11.19#ibcon#end of sib2, iclass 12, count 0 2006.210.07:31:11.19#ibcon#*after write, iclass 12, count 0 2006.210.07:31:11.19#ibcon#*before return 0, iclass 12, count 0 2006.210.07:31:11.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:11.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:31:11.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:31:11.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:31:11.20$vc4f8/vb=4,3 2006.210.07:31:11.20#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:31:11.20#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:31:11.20#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:11.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:11.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:11.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:11.24#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:31:11.24#ibcon#first serial, iclass 14, count 2 2006.210.07:31:11.24#ibcon#enter sib2, iclass 14, count 2 2006.210.07:31:11.24#ibcon#flushed, iclass 14, count 2 2006.210.07:31:11.24#ibcon#about to write, iclass 14, count 2 2006.210.07:31:11.24#ibcon#wrote, iclass 14, count 2 2006.210.07:31:11.24#ibcon#about to read 3, iclass 14, count 2 2006.210.07:31:11.26#ibcon#read 3, iclass 14, count 2 2006.210.07:31:11.26#ibcon#about to read 4, iclass 14, count 2 2006.210.07:31:11.26#ibcon#read 4, iclass 14, count 2 2006.210.07:31:11.26#ibcon#about to read 5, iclass 14, count 2 2006.210.07:31:11.26#ibcon#read 5, iclass 14, count 2 2006.210.07:31:11.26#ibcon#about to read 6, iclass 14, count 2 2006.210.07:31:11.26#ibcon#read 6, iclass 14, count 2 2006.210.07:31:11.26#ibcon#end of sib2, iclass 14, count 2 2006.210.07:31:11.26#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:31:11.26#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:31:11.26#ibcon#[27=AT04-03\r\n] 2006.210.07:31:11.26#ibcon#*before write, iclass 14, count 2 2006.210.07:31:11.26#ibcon#enter sib2, iclass 14, count 2 2006.210.07:31:11.26#ibcon#flushed, iclass 14, count 2 2006.210.07:31:11.26#ibcon#about to write, iclass 14, count 2 2006.210.07:31:11.26#ibcon#wrote, iclass 14, count 2 2006.210.07:31:11.26#ibcon#about to read 3, iclass 14, count 2 2006.210.07:31:11.29#ibcon#read 3, iclass 14, count 2 2006.210.07:31:11.29#ibcon#about to read 4, iclass 14, count 2 2006.210.07:31:11.29#ibcon#read 4, iclass 14, count 2 2006.210.07:31:11.29#ibcon#about to read 5, iclass 14, count 2 2006.210.07:31:11.29#ibcon#read 5, iclass 14, count 2 2006.210.07:31:11.29#ibcon#about to read 6, iclass 14, count 2 2006.210.07:31:11.29#ibcon#read 6, iclass 14, count 2 2006.210.07:31:11.29#ibcon#end of sib2, iclass 14, count 2 2006.210.07:31:11.29#ibcon#*after write, iclass 14, count 2 2006.210.07:31:11.29#ibcon#*before return 0, iclass 14, count 2 2006.210.07:31:11.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:11.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:31:11.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:31:11.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:11.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:11.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:11.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:11.41#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:31:11.41#ibcon#first serial, iclass 14, count 0 2006.210.07:31:11.41#ibcon#enter sib2, iclass 14, count 0 2006.210.07:31:11.41#ibcon#flushed, iclass 14, count 0 2006.210.07:31:11.41#ibcon#about to write, iclass 14, count 0 2006.210.07:31:11.41#ibcon#wrote, iclass 14, count 0 2006.210.07:31:11.41#ibcon#about to read 3, iclass 14, count 0 2006.210.07:31:11.43#ibcon#read 3, iclass 14, count 0 2006.210.07:31:11.43#ibcon#about to read 4, iclass 14, count 0 2006.210.07:31:11.43#ibcon#read 4, iclass 14, count 0 2006.210.07:31:11.43#ibcon#about to read 5, iclass 14, count 0 2006.210.07:31:11.43#ibcon#read 5, iclass 14, count 0 2006.210.07:31:11.43#ibcon#about to read 6, iclass 14, count 0 2006.210.07:31:11.43#ibcon#read 6, iclass 14, count 0 2006.210.07:31:11.43#ibcon#end of sib2, iclass 14, count 0 2006.210.07:31:11.43#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:31:11.43#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:31:11.43#ibcon#[27=USB\r\n] 2006.210.07:31:11.43#ibcon#*before write, iclass 14, count 0 2006.210.07:31:11.43#ibcon#enter sib2, iclass 14, count 0 2006.210.07:31:11.43#ibcon#flushed, iclass 14, count 0 2006.210.07:31:11.43#ibcon#about to write, iclass 14, count 0 2006.210.07:31:11.43#ibcon#wrote, iclass 14, count 0 2006.210.07:31:11.43#ibcon#about to read 3, iclass 14, count 0 2006.210.07:31:11.46#ibcon#read 3, iclass 14, count 0 2006.210.07:31:11.46#ibcon#about to read 4, iclass 14, count 0 2006.210.07:31:11.46#ibcon#read 4, iclass 14, count 0 2006.210.07:31:11.46#ibcon#about to read 5, iclass 14, count 0 2006.210.07:31:11.46#ibcon#read 5, iclass 14, count 0 2006.210.07:31:11.46#ibcon#about to read 6, iclass 14, count 0 2006.210.07:31:11.46#ibcon#read 6, iclass 14, count 0 2006.210.07:31:11.46#ibcon#end of sib2, iclass 14, count 0 2006.210.07:31:11.46#ibcon#*after write, iclass 14, count 0 2006.210.07:31:11.46#ibcon#*before return 0, iclass 14, count 0 2006.210.07:31:11.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:11.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:31:11.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:31:11.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:31:11.47$vc4f8/vblo=5,744.99 2006.210.07:31:11.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:31:11.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:31:11.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:11.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:11.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:11.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:11.47#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:31:11.47#ibcon#first serial, iclass 16, count 0 2006.210.07:31:11.47#ibcon#enter sib2, iclass 16, count 0 2006.210.07:31:11.47#ibcon#flushed, iclass 16, count 0 2006.210.07:31:11.47#ibcon#about to write, iclass 16, count 0 2006.210.07:31:11.47#ibcon#wrote, iclass 16, count 0 2006.210.07:31:11.47#ibcon#about to read 3, iclass 16, count 0 2006.210.07:31:11.48#ibcon#read 3, iclass 16, count 0 2006.210.07:31:11.48#ibcon#about to read 4, iclass 16, count 0 2006.210.07:31:11.48#ibcon#read 4, iclass 16, count 0 2006.210.07:31:11.48#ibcon#about to read 5, iclass 16, count 0 2006.210.07:31:11.48#ibcon#read 5, iclass 16, count 0 2006.210.07:31:11.48#ibcon#about to read 6, iclass 16, count 0 2006.210.07:31:11.48#ibcon#read 6, iclass 16, count 0 2006.210.07:31:11.48#ibcon#end of sib2, iclass 16, count 0 2006.210.07:31:11.48#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:31:11.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:31:11.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:31:11.48#ibcon#*before write, iclass 16, count 0 2006.210.07:31:11.48#ibcon#enter sib2, iclass 16, count 0 2006.210.07:31:11.48#ibcon#flushed, iclass 16, count 0 2006.210.07:31:11.48#ibcon#about to write, iclass 16, count 0 2006.210.07:31:11.48#ibcon#wrote, iclass 16, count 0 2006.210.07:31:11.48#ibcon#about to read 3, iclass 16, count 0 2006.210.07:31:11.52#ibcon#read 3, iclass 16, count 0 2006.210.07:31:11.52#ibcon#about to read 4, iclass 16, count 0 2006.210.07:31:11.52#ibcon#read 4, iclass 16, count 0 2006.210.07:31:11.52#ibcon#about to read 5, iclass 16, count 0 2006.210.07:31:11.52#ibcon#read 5, iclass 16, count 0 2006.210.07:31:11.52#ibcon#about to read 6, iclass 16, count 0 2006.210.07:31:11.52#ibcon#read 6, iclass 16, count 0 2006.210.07:31:11.52#ibcon#end of sib2, iclass 16, count 0 2006.210.07:31:11.52#ibcon#*after write, iclass 16, count 0 2006.210.07:31:11.52#ibcon#*before return 0, iclass 16, count 0 2006.210.07:31:11.52#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:11.52#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:31:11.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:31:11.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:31:11.53$vc4f8/vb=5,3 2006.210.07:31:11.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:31:11.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:31:11.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:11.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:11.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:11.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:11.57#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:31:11.57#ibcon#first serial, iclass 18, count 2 2006.210.07:31:11.57#ibcon#enter sib2, iclass 18, count 2 2006.210.07:31:11.57#ibcon#flushed, iclass 18, count 2 2006.210.07:31:11.57#ibcon#about to write, iclass 18, count 2 2006.210.07:31:11.57#ibcon#wrote, iclass 18, count 2 2006.210.07:31:11.57#ibcon#about to read 3, iclass 18, count 2 2006.210.07:31:11.59#ibcon#read 3, iclass 18, count 2 2006.210.07:31:11.59#ibcon#about to read 4, iclass 18, count 2 2006.210.07:31:11.59#ibcon#read 4, iclass 18, count 2 2006.210.07:31:11.59#ibcon#about to read 5, iclass 18, count 2 2006.210.07:31:11.59#ibcon#read 5, iclass 18, count 2 2006.210.07:31:11.59#ibcon#about to read 6, iclass 18, count 2 2006.210.07:31:11.59#ibcon#read 6, iclass 18, count 2 2006.210.07:31:11.59#ibcon#end of sib2, iclass 18, count 2 2006.210.07:31:11.59#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:31:11.59#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:31:11.59#ibcon#[27=AT05-03\r\n] 2006.210.07:31:11.59#ibcon#*before write, iclass 18, count 2 2006.210.07:31:11.59#ibcon#enter sib2, iclass 18, count 2 2006.210.07:31:11.59#ibcon#flushed, iclass 18, count 2 2006.210.07:31:11.59#ibcon#about to write, iclass 18, count 2 2006.210.07:31:11.59#ibcon#wrote, iclass 18, count 2 2006.210.07:31:11.59#ibcon#about to read 3, iclass 18, count 2 2006.210.07:31:11.62#ibcon#read 3, iclass 18, count 2 2006.210.07:31:11.62#ibcon#about to read 4, iclass 18, count 2 2006.210.07:31:11.62#ibcon#read 4, iclass 18, count 2 2006.210.07:31:11.62#ibcon#about to read 5, iclass 18, count 2 2006.210.07:31:11.62#ibcon#read 5, iclass 18, count 2 2006.210.07:31:11.62#ibcon#about to read 6, iclass 18, count 2 2006.210.07:31:11.62#ibcon#read 6, iclass 18, count 2 2006.210.07:31:11.62#ibcon#end of sib2, iclass 18, count 2 2006.210.07:31:11.62#ibcon#*after write, iclass 18, count 2 2006.210.07:31:11.62#ibcon#*before return 0, iclass 18, count 2 2006.210.07:31:11.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:11.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:31:11.62#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:31:11.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:11.62#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:11.74#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:11.74#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:11.74#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:31:11.74#ibcon#first serial, iclass 18, count 0 2006.210.07:31:11.74#ibcon#enter sib2, iclass 18, count 0 2006.210.07:31:11.74#ibcon#flushed, iclass 18, count 0 2006.210.07:31:11.74#ibcon#about to write, iclass 18, count 0 2006.210.07:31:11.74#ibcon#wrote, iclass 18, count 0 2006.210.07:31:11.74#ibcon#about to read 3, iclass 18, count 0 2006.210.07:31:11.76#ibcon#read 3, iclass 18, count 0 2006.210.07:31:11.76#ibcon#about to read 4, iclass 18, count 0 2006.210.07:31:11.76#ibcon#read 4, iclass 18, count 0 2006.210.07:31:11.76#ibcon#about to read 5, iclass 18, count 0 2006.210.07:31:11.76#ibcon#read 5, iclass 18, count 0 2006.210.07:31:11.76#ibcon#about to read 6, iclass 18, count 0 2006.210.07:31:11.76#ibcon#read 6, iclass 18, count 0 2006.210.07:31:11.76#ibcon#end of sib2, iclass 18, count 0 2006.210.07:31:11.76#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:31:11.76#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:31:11.76#ibcon#[27=USB\r\n] 2006.210.07:31:11.76#ibcon#*before write, iclass 18, count 0 2006.210.07:31:11.76#ibcon#enter sib2, iclass 18, count 0 2006.210.07:31:11.76#ibcon#flushed, iclass 18, count 0 2006.210.07:31:11.76#ibcon#about to write, iclass 18, count 0 2006.210.07:31:11.76#ibcon#wrote, iclass 18, count 0 2006.210.07:31:11.76#ibcon#about to read 3, iclass 18, count 0 2006.210.07:31:11.79#ibcon#read 3, iclass 18, count 0 2006.210.07:31:11.79#ibcon#about to read 4, iclass 18, count 0 2006.210.07:31:11.79#ibcon#read 4, iclass 18, count 0 2006.210.07:31:11.79#ibcon#about to read 5, iclass 18, count 0 2006.210.07:31:11.79#ibcon#read 5, iclass 18, count 0 2006.210.07:31:11.79#ibcon#about to read 6, iclass 18, count 0 2006.210.07:31:11.79#ibcon#read 6, iclass 18, count 0 2006.210.07:31:11.79#ibcon#end of sib2, iclass 18, count 0 2006.210.07:31:11.79#ibcon#*after write, iclass 18, count 0 2006.210.07:31:11.79#ibcon#*before return 0, iclass 18, count 0 2006.210.07:31:11.79#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:11.79#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:31:11.79#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:31:11.79#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:31:11.80$vc4f8/vblo=6,752.99 2006.210.07:31:11.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:31:11.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:31:11.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:31:11.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:11.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:11.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:11.80#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:31:11.80#ibcon#first serial, iclass 20, count 0 2006.210.07:31:11.80#ibcon#enter sib2, iclass 20, count 0 2006.210.07:31:11.80#ibcon#flushed, iclass 20, count 0 2006.210.07:31:11.80#ibcon#about to write, iclass 20, count 0 2006.210.07:31:11.80#ibcon#wrote, iclass 20, count 0 2006.210.07:31:11.80#ibcon#about to read 3, iclass 20, count 0 2006.210.07:31:11.81#ibcon#read 3, iclass 20, count 0 2006.210.07:31:11.81#ibcon#about to read 4, iclass 20, count 0 2006.210.07:31:11.81#ibcon#read 4, iclass 20, count 0 2006.210.07:31:11.81#ibcon#about to read 5, iclass 20, count 0 2006.210.07:31:11.81#ibcon#read 5, iclass 20, count 0 2006.210.07:31:11.81#ibcon#about to read 6, iclass 20, count 0 2006.210.07:31:11.81#ibcon#read 6, iclass 20, count 0 2006.210.07:31:11.81#ibcon#end of sib2, iclass 20, count 0 2006.210.07:31:11.81#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:31:11.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:31:11.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:31:11.81#ibcon#*before write, iclass 20, count 0 2006.210.07:31:11.81#ibcon#enter sib2, iclass 20, count 0 2006.210.07:31:11.81#ibcon#flushed, iclass 20, count 0 2006.210.07:31:11.81#ibcon#about to write, iclass 20, count 0 2006.210.07:31:11.81#ibcon#wrote, iclass 20, count 0 2006.210.07:31:11.81#ibcon#about to read 3, iclass 20, count 0 2006.210.07:31:11.85#ibcon#read 3, iclass 20, count 0 2006.210.07:31:11.85#ibcon#about to read 4, iclass 20, count 0 2006.210.07:31:11.85#ibcon#read 4, iclass 20, count 0 2006.210.07:31:11.85#ibcon#about to read 5, iclass 20, count 0 2006.210.07:31:11.85#ibcon#read 5, iclass 20, count 0 2006.210.07:31:11.85#ibcon#about to read 6, iclass 20, count 0 2006.210.07:31:11.85#ibcon#read 6, iclass 20, count 0 2006.210.07:31:11.85#ibcon#end of sib2, iclass 20, count 0 2006.210.07:31:11.85#ibcon#*after write, iclass 20, count 0 2006.210.07:31:11.85#ibcon#*before return 0, iclass 20, count 0 2006.210.07:31:11.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:11.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:31:11.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:31:11.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:31:11.86$vc4f8/vb=6,3 2006.210.07:31:11.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:31:11.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:31:11.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:31:11.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:11.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:11.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:11.90#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:31:11.90#ibcon#first serial, iclass 22, count 2 2006.210.07:31:11.90#ibcon#enter sib2, iclass 22, count 2 2006.210.07:31:11.90#ibcon#flushed, iclass 22, count 2 2006.210.07:31:11.90#ibcon#about to write, iclass 22, count 2 2006.210.07:31:11.90#ibcon#wrote, iclass 22, count 2 2006.210.07:31:11.90#ibcon#about to read 3, iclass 22, count 2 2006.210.07:31:11.92#ibcon#read 3, iclass 22, count 2 2006.210.07:31:11.92#ibcon#about to read 4, iclass 22, count 2 2006.210.07:31:11.92#ibcon#read 4, iclass 22, count 2 2006.210.07:31:11.92#ibcon#about to read 5, iclass 22, count 2 2006.210.07:31:11.92#ibcon#read 5, iclass 22, count 2 2006.210.07:31:11.92#ibcon#about to read 6, iclass 22, count 2 2006.210.07:31:11.92#ibcon#read 6, iclass 22, count 2 2006.210.07:31:11.92#ibcon#end of sib2, iclass 22, count 2 2006.210.07:31:11.92#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:31:11.92#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:31:11.92#ibcon#[27=AT06-03\r\n] 2006.210.07:31:11.92#ibcon#*before write, iclass 22, count 2 2006.210.07:31:11.92#ibcon#enter sib2, iclass 22, count 2 2006.210.07:31:11.92#ibcon#flushed, iclass 22, count 2 2006.210.07:31:11.92#ibcon#about to write, iclass 22, count 2 2006.210.07:31:11.92#ibcon#wrote, iclass 22, count 2 2006.210.07:31:11.92#ibcon#about to read 3, iclass 22, count 2 2006.210.07:31:11.95#ibcon#read 3, iclass 22, count 2 2006.210.07:31:11.95#ibcon#about to read 4, iclass 22, count 2 2006.210.07:31:11.95#ibcon#read 4, iclass 22, count 2 2006.210.07:31:11.95#ibcon#about to read 5, iclass 22, count 2 2006.210.07:31:11.95#ibcon#read 5, iclass 22, count 2 2006.210.07:31:11.95#ibcon#about to read 6, iclass 22, count 2 2006.210.07:31:11.95#ibcon#read 6, iclass 22, count 2 2006.210.07:31:11.95#ibcon#end of sib2, iclass 22, count 2 2006.210.07:31:11.95#ibcon#*after write, iclass 22, count 2 2006.210.07:31:11.95#ibcon#*before return 0, iclass 22, count 2 2006.210.07:31:11.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:11.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:31:11.95#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:31:11.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:31:11.95#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:12.07#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:12.07#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:12.07#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:31:12.07#ibcon#first serial, iclass 22, count 0 2006.210.07:31:12.07#ibcon#enter sib2, iclass 22, count 0 2006.210.07:31:12.07#ibcon#flushed, iclass 22, count 0 2006.210.07:31:12.07#ibcon#about to write, iclass 22, count 0 2006.210.07:31:12.07#ibcon#wrote, iclass 22, count 0 2006.210.07:31:12.07#ibcon#about to read 3, iclass 22, count 0 2006.210.07:31:12.09#ibcon#read 3, iclass 22, count 0 2006.210.07:31:12.09#ibcon#about to read 4, iclass 22, count 0 2006.210.07:31:12.09#ibcon#read 4, iclass 22, count 0 2006.210.07:31:12.09#ibcon#about to read 5, iclass 22, count 0 2006.210.07:31:12.09#ibcon#read 5, iclass 22, count 0 2006.210.07:31:12.09#ibcon#about to read 6, iclass 22, count 0 2006.210.07:31:12.09#ibcon#read 6, iclass 22, count 0 2006.210.07:31:12.09#ibcon#end of sib2, iclass 22, count 0 2006.210.07:31:12.09#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:31:12.09#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:31:12.09#ibcon#[27=USB\r\n] 2006.210.07:31:12.09#ibcon#*before write, iclass 22, count 0 2006.210.07:31:12.09#ibcon#enter sib2, iclass 22, count 0 2006.210.07:31:12.09#ibcon#flushed, iclass 22, count 0 2006.210.07:31:12.09#ibcon#about to write, iclass 22, count 0 2006.210.07:31:12.09#ibcon#wrote, iclass 22, count 0 2006.210.07:31:12.09#ibcon#about to read 3, iclass 22, count 0 2006.210.07:31:12.12#ibcon#read 3, iclass 22, count 0 2006.210.07:31:12.12#ibcon#about to read 4, iclass 22, count 0 2006.210.07:31:12.12#ibcon#read 4, iclass 22, count 0 2006.210.07:31:12.12#ibcon#about to read 5, iclass 22, count 0 2006.210.07:31:12.12#ibcon#read 5, iclass 22, count 0 2006.210.07:31:12.12#ibcon#about to read 6, iclass 22, count 0 2006.210.07:31:12.12#ibcon#read 6, iclass 22, count 0 2006.210.07:31:12.12#ibcon#end of sib2, iclass 22, count 0 2006.210.07:31:12.12#ibcon#*after write, iclass 22, count 0 2006.210.07:31:12.12#ibcon#*before return 0, iclass 22, count 0 2006.210.07:31:12.12#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:12.12#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:31:12.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:31:12.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:31:12.13$vc4f8/vabw=wide 2006.210.07:31:12.13#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:31:12.13#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:31:12.13#ibcon#ireg 8 cls_cnt 0 2006.210.07:31:12.13#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:12.13#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:12.13#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:12.13#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:31:12.13#ibcon#first serial, iclass 24, count 0 2006.210.07:31:12.13#ibcon#enter sib2, iclass 24, count 0 2006.210.07:31:12.13#ibcon#flushed, iclass 24, count 0 2006.210.07:31:12.13#ibcon#about to write, iclass 24, count 0 2006.210.07:31:12.13#ibcon#wrote, iclass 24, count 0 2006.210.07:31:12.13#ibcon#about to read 3, iclass 24, count 0 2006.210.07:31:12.15#ibcon#read 3, iclass 24, count 0 2006.210.07:31:12.15#ibcon#about to read 4, iclass 24, count 0 2006.210.07:31:12.15#ibcon#read 4, iclass 24, count 0 2006.210.07:31:12.15#ibcon#about to read 5, iclass 24, count 0 2006.210.07:31:12.15#ibcon#read 5, iclass 24, count 0 2006.210.07:31:12.15#ibcon#about to read 6, iclass 24, count 0 2006.210.07:31:12.15#ibcon#read 6, iclass 24, count 0 2006.210.07:31:12.15#ibcon#end of sib2, iclass 24, count 0 2006.210.07:31:12.15#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:31:12.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:31:12.15#ibcon#[25=BW32\r\n] 2006.210.07:31:12.15#ibcon#*before write, iclass 24, count 0 2006.210.07:31:12.15#ibcon#enter sib2, iclass 24, count 0 2006.210.07:31:12.15#ibcon#flushed, iclass 24, count 0 2006.210.07:31:12.15#ibcon#about to write, iclass 24, count 0 2006.210.07:31:12.15#ibcon#wrote, iclass 24, count 0 2006.210.07:31:12.15#ibcon#about to read 3, iclass 24, count 0 2006.210.07:31:12.17#ibcon#read 3, iclass 24, count 0 2006.210.07:31:12.17#ibcon#about to read 4, iclass 24, count 0 2006.210.07:31:12.17#ibcon#read 4, iclass 24, count 0 2006.210.07:31:12.17#ibcon#about to read 5, iclass 24, count 0 2006.210.07:31:12.17#ibcon#read 5, iclass 24, count 0 2006.210.07:31:12.17#ibcon#about to read 6, iclass 24, count 0 2006.210.07:31:12.17#ibcon#read 6, iclass 24, count 0 2006.210.07:31:12.17#ibcon#end of sib2, iclass 24, count 0 2006.210.07:31:12.17#ibcon#*after write, iclass 24, count 0 2006.210.07:31:12.17#ibcon#*before return 0, iclass 24, count 0 2006.210.07:31:12.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:12.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:31:12.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:31:12.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:31:12.18$vc4f8/vbbw=wide 2006.210.07:31:12.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:31:12.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:31:12.18#ibcon#ireg 8 cls_cnt 0 2006.210.07:31:12.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:31:12.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:31:12.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:31:12.23#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:31:12.23#ibcon#first serial, iclass 26, count 0 2006.210.07:31:12.23#ibcon#enter sib2, iclass 26, count 0 2006.210.07:31:12.23#ibcon#flushed, iclass 26, count 0 2006.210.07:31:12.23#ibcon#about to write, iclass 26, count 0 2006.210.07:31:12.23#ibcon#wrote, iclass 26, count 0 2006.210.07:31:12.23#ibcon#about to read 3, iclass 26, count 0 2006.210.07:31:12.25#ibcon#read 3, iclass 26, count 0 2006.210.07:31:12.25#ibcon#about to read 4, iclass 26, count 0 2006.210.07:31:12.25#ibcon#read 4, iclass 26, count 0 2006.210.07:31:12.25#ibcon#about to read 5, iclass 26, count 0 2006.210.07:31:12.25#ibcon#read 5, iclass 26, count 0 2006.210.07:31:12.25#ibcon#about to read 6, iclass 26, count 0 2006.210.07:31:12.25#ibcon#read 6, iclass 26, count 0 2006.210.07:31:12.25#ibcon#end of sib2, iclass 26, count 0 2006.210.07:31:12.25#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:31:12.25#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:31:12.25#ibcon#[27=BW32\r\n] 2006.210.07:31:12.25#ibcon#*before write, iclass 26, count 0 2006.210.07:31:12.25#ibcon#enter sib2, iclass 26, count 0 2006.210.07:31:12.25#ibcon#flushed, iclass 26, count 0 2006.210.07:31:12.25#ibcon#about to write, iclass 26, count 0 2006.210.07:31:12.25#ibcon#wrote, iclass 26, count 0 2006.210.07:31:12.25#ibcon#about to read 3, iclass 26, count 0 2006.210.07:31:12.28#ibcon#read 3, iclass 26, count 0 2006.210.07:31:12.28#ibcon#about to read 4, iclass 26, count 0 2006.210.07:31:12.28#ibcon#read 4, iclass 26, count 0 2006.210.07:31:12.28#ibcon#about to read 5, iclass 26, count 0 2006.210.07:31:12.28#ibcon#read 5, iclass 26, count 0 2006.210.07:31:12.28#ibcon#about to read 6, iclass 26, count 0 2006.210.07:31:12.28#ibcon#read 6, iclass 26, count 0 2006.210.07:31:12.28#ibcon#end of sib2, iclass 26, count 0 2006.210.07:31:12.28#ibcon#*after write, iclass 26, count 0 2006.210.07:31:12.28#ibcon#*before return 0, iclass 26, count 0 2006.210.07:31:12.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:31:12.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:31:12.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:31:12.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:31:12.29$4f8m12a/ifd4f 2006.210.07:31:12.29$ifd4f/lo= 2006.210.07:31:12.29$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:31:12.29$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:31:12.29$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:31:12.29$ifd4f/patch= 2006.210.07:31:12.29$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:31:12.29$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:31:12.29$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:31:12.29$4f8m12a/"form=m,16.000,1:2 2006.210.07:31:12.29$4f8m12a/"tpicd 2006.210.07:31:12.29$4f8m12a/echo=off 2006.210.07:31:12.29$4f8m12a/xlog=off 2006.210.07:31:12.29:!2006.210.07:33:20 2006.210.07:31:54.13#trakl#Source acquired 2006.210.07:31:55.13#flagr#flagr/antenna,acquired 2006.210.07:33:20.01:preob 2006.210.07:33:21.13/onsource/TRACKING 2006.210.07:33:21.13:!2006.210.07:33:30 2006.210.07:33:30.00:data_valid=on 2006.210.07:33:30.00:midob 2006.210.07:33:30.13/onsource/TRACKING 2006.210.07:33:30.14/wx/30.58,1006.2,73 2006.210.07:33:30.26/cable/+6.3973E-03 2006.210.07:33:31.35/va/01,08,usb,yes,33,35 2006.210.07:33:31.35/va/02,07,usb,yes,34,35 2006.210.07:33:31.35/va/03,06,usb,yes,35,36 2006.210.07:33:31.35/va/04,07,usb,yes,35,37 2006.210.07:33:31.35/va/05,07,usb,yes,35,37 2006.210.07:33:31.35/va/06,06,usb,yes,35,34 2006.210.07:33:31.35/va/07,06,usb,yes,35,35 2006.210.07:33:31.35/va/08,07,usb,yes,33,33 2006.210.07:33:31.58/valo/01,532.99,yes,locked 2006.210.07:33:31.58/valo/02,572.99,yes,locked 2006.210.07:33:31.58/valo/03,672.99,yes,locked 2006.210.07:33:31.58/valo/04,832.99,yes,locked 2006.210.07:33:31.58/valo/05,652.99,yes,locked 2006.210.07:33:31.58/valo/06,772.99,yes,locked 2006.210.07:33:31.58/valo/07,832.99,yes,locked 2006.210.07:33:31.58/valo/08,852.99,yes,locked 2006.210.07:33:32.67/vb/01,04,usb,yes,29,29 2006.210.07:33:32.67/vb/02,04,usb,yes,31,33 2006.210.07:33:32.67/vb/03,03,usb,yes,34,39 2006.210.07:33:32.67/vb/04,03,usb,yes,35,35 2006.210.07:33:32.67/vb/05,03,usb,yes,34,38 2006.210.07:33:32.67/vb/06,03,usb,yes,34,38 2006.210.07:33:32.67/vb/07,04,usb,yes,30,30 2006.210.07:33:32.67/vb/08,03,usb,yes,34,38 2006.210.07:33:32.91/vblo/01,632.99,yes,locked 2006.210.07:33:32.91/vblo/02,640.99,yes,locked 2006.210.07:33:32.91/vblo/03,656.99,yes,locked 2006.210.07:33:32.91/vblo/04,712.99,yes,locked 2006.210.07:33:32.91/vblo/05,744.99,yes,locked 2006.210.07:33:32.91/vblo/06,752.99,yes,locked 2006.210.07:33:32.91/vblo/07,734.99,yes,locked 2006.210.07:33:32.91/vblo/08,744.99,yes,locked 2006.210.07:33:33.06/vabw/8 2006.210.07:33:33.21/vbbw/8 2006.210.07:33:33.30/xfe/off,on,12.5 2006.210.07:33:33.68/ifatt/23,28,28,28 2006.210.07:33:34.07/fmout-gps/S +4.35E-07 2006.210.07:33:34.12:!2006.210.07:34:30 2006.210.07:34:30.01:data_valid=off 2006.210.07:34:30.02:postob 2006.210.07:34:30.14/cable/+6.3949E-03 2006.210.07:34:30.15/wx/30.58,1006.2,73 2006.210.07:34:31.07/fmout-gps/S +4.37E-07 2006.210.07:34:31.07:scan_name=210-0735,k06210,60 2006.210.07:34:31.07:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.210.07:34:32.14#flagr#flagr/antenna,new-source 2006.210.07:34:32.15:checkk5 2006.210.07:34:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:34:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:34:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:34:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:34:33.83/chk_obsdata//k5ts1/T2100733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:34:34.17/chk_obsdata//k5ts2/T2100733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:34:34.49/chk_obsdata//k5ts3/T2100733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:34:34.83/chk_obsdata//k5ts4/T2100733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:34:35.49/k5log//k5ts1_log_newline 2006.210.07:34:36.15/k5log//k5ts2_log_newline 2006.210.07:34:36.80/k5log//k5ts3_log_newline 2006.210.07:34:37.46/k5log//k5ts4_log_newline 2006.210.07:34:37.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:34:37.48:4f8m12a=1 2006.210.07:34:37.48$4f8m12a/echo=on 2006.210.07:34:37.48$4f8m12a/pcalon 2006.210.07:34:37.48$pcalon/"no phase cal control is implemented here 2006.210.07:34:37.48$4f8m12a/"tpicd=stop 2006.210.07:34:37.48$4f8m12a/vc4f8 2006.210.07:34:37.48$vc4f8/valo=1,532.99 2006.210.07:34:37.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:34:37.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:34:37.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:37.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:37.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:37.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:37.49#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:34:37.49#ibcon#first serial, iclass 37, count 0 2006.210.07:34:37.49#ibcon#enter sib2, iclass 37, count 0 2006.210.07:34:37.49#ibcon#flushed, iclass 37, count 0 2006.210.07:34:37.49#ibcon#about to write, iclass 37, count 0 2006.210.07:34:37.49#ibcon#wrote, iclass 37, count 0 2006.210.07:34:37.49#ibcon#about to read 3, iclass 37, count 0 2006.210.07:34:37.50#ibcon#read 3, iclass 37, count 0 2006.210.07:34:37.50#ibcon#about to read 4, iclass 37, count 0 2006.210.07:34:37.50#ibcon#read 4, iclass 37, count 0 2006.210.07:34:37.50#ibcon#about to read 5, iclass 37, count 0 2006.210.07:34:37.50#ibcon#read 5, iclass 37, count 0 2006.210.07:34:37.50#ibcon#about to read 6, iclass 37, count 0 2006.210.07:34:37.50#ibcon#read 6, iclass 37, count 0 2006.210.07:34:37.50#ibcon#end of sib2, iclass 37, count 0 2006.210.07:34:37.50#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:34:37.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:34:37.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:34:37.50#ibcon#*before write, iclass 37, count 0 2006.210.07:34:37.50#ibcon#enter sib2, iclass 37, count 0 2006.210.07:34:37.50#ibcon#flushed, iclass 37, count 0 2006.210.07:34:37.50#ibcon#about to write, iclass 37, count 0 2006.210.07:34:37.50#ibcon#wrote, iclass 37, count 0 2006.210.07:34:37.50#ibcon#about to read 3, iclass 37, count 0 2006.210.07:34:37.55#ibcon#read 3, iclass 37, count 0 2006.210.07:34:37.55#ibcon#about to read 4, iclass 37, count 0 2006.210.07:34:37.55#ibcon#read 4, iclass 37, count 0 2006.210.07:34:37.55#ibcon#about to read 5, iclass 37, count 0 2006.210.07:34:37.55#ibcon#read 5, iclass 37, count 0 2006.210.07:34:37.55#ibcon#about to read 6, iclass 37, count 0 2006.210.07:34:37.55#ibcon#read 6, iclass 37, count 0 2006.210.07:34:37.55#ibcon#end of sib2, iclass 37, count 0 2006.210.07:34:37.55#ibcon#*after write, iclass 37, count 0 2006.210.07:34:37.55#ibcon#*before return 0, iclass 37, count 0 2006.210.07:34:37.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:37.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:37.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:34:37.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:34:37.55$vc4f8/va=1,8 2006.210.07:34:37.55#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:34:37.55#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:34:37.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:37.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:37.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:37.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:37.55#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:34:37.55#ibcon#first serial, iclass 39, count 2 2006.210.07:34:37.55#ibcon#enter sib2, iclass 39, count 2 2006.210.07:34:37.55#ibcon#flushed, iclass 39, count 2 2006.210.07:34:37.55#ibcon#about to write, iclass 39, count 2 2006.210.07:34:37.56#ibcon#wrote, iclass 39, count 2 2006.210.07:34:37.56#ibcon#about to read 3, iclass 39, count 2 2006.210.07:34:37.57#ibcon#read 3, iclass 39, count 2 2006.210.07:34:37.57#ibcon#about to read 4, iclass 39, count 2 2006.210.07:34:37.57#ibcon#read 4, iclass 39, count 2 2006.210.07:34:37.57#ibcon#about to read 5, iclass 39, count 2 2006.210.07:34:37.57#ibcon#read 5, iclass 39, count 2 2006.210.07:34:37.57#ibcon#about to read 6, iclass 39, count 2 2006.210.07:34:37.57#ibcon#read 6, iclass 39, count 2 2006.210.07:34:37.57#ibcon#end of sib2, iclass 39, count 2 2006.210.07:34:37.57#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:34:37.57#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:34:37.57#ibcon#[25=AT01-08\r\n] 2006.210.07:34:37.57#ibcon#*before write, iclass 39, count 2 2006.210.07:34:37.57#ibcon#enter sib2, iclass 39, count 2 2006.210.07:34:37.57#ibcon#flushed, iclass 39, count 2 2006.210.07:34:37.57#ibcon#about to write, iclass 39, count 2 2006.210.07:34:37.57#ibcon#wrote, iclass 39, count 2 2006.210.07:34:37.57#ibcon#about to read 3, iclass 39, count 2 2006.210.07:34:37.60#ibcon#read 3, iclass 39, count 2 2006.210.07:34:37.60#ibcon#about to read 4, iclass 39, count 2 2006.210.07:34:37.60#ibcon#read 4, iclass 39, count 2 2006.210.07:34:37.60#ibcon#about to read 5, iclass 39, count 2 2006.210.07:34:37.60#ibcon#read 5, iclass 39, count 2 2006.210.07:34:37.60#ibcon#about to read 6, iclass 39, count 2 2006.210.07:34:37.60#ibcon#read 6, iclass 39, count 2 2006.210.07:34:37.60#ibcon#end of sib2, iclass 39, count 2 2006.210.07:34:37.60#ibcon#*after write, iclass 39, count 2 2006.210.07:34:37.60#ibcon#*before return 0, iclass 39, count 2 2006.210.07:34:37.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:37.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:37.60#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:34:37.60#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:37.60#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:37.72#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:37.72#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:37.72#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:34:37.72#ibcon#first serial, iclass 39, count 0 2006.210.07:34:37.72#ibcon#enter sib2, iclass 39, count 0 2006.210.07:34:37.72#ibcon#flushed, iclass 39, count 0 2006.210.07:34:37.72#ibcon#about to write, iclass 39, count 0 2006.210.07:34:37.72#ibcon#wrote, iclass 39, count 0 2006.210.07:34:37.72#ibcon#about to read 3, iclass 39, count 0 2006.210.07:34:37.74#ibcon#read 3, iclass 39, count 0 2006.210.07:34:37.74#ibcon#about to read 4, iclass 39, count 0 2006.210.07:34:37.74#ibcon#read 4, iclass 39, count 0 2006.210.07:34:37.74#ibcon#about to read 5, iclass 39, count 0 2006.210.07:34:37.74#ibcon#read 5, iclass 39, count 0 2006.210.07:34:37.74#ibcon#about to read 6, iclass 39, count 0 2006.210.07:34:37.74#ibcon#read 6, iclass 39, count 0 2006.210.07:34:37.74#ibcon#end of sib2, iclass 39, count 0 2006.210.07:34:37.74#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:34:37.74#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:34:37.74#ibcon#[25=USB\r\n] 2006.210.07:34:37.74#ibcon#*before write, iclass 39, count 0 2006.210.07:34:37.74#ibcon#enter sib2, iclass 39, count 0 2006.210.07:34:37.74#ibcon#flushed, iclass 39, count 0 2006.210.07:34:37.74#ibcon#about to write, iclass 39, count 0 2006.210.07:34:37.74#ibcon#wrote, iclass 39, count 0 2006.210.07:34:37.74#ibcon#about to read 3, iclass 39, count 0 2006.210.07:34:37.77#ibcon#read 3, iclass 39, count 0 2006.210.07:34:37.77#ibcon#about to read 4, iclass 39, count 0 2006.210.07:34:37.77#ibcon#read 4, iclass 39, count 0 2006.210.07:34:37.77#ibcon#about to read 5, iclass 39, count 0 2006.210.07:34:37.77#ibcon#read 5, iclass 39, count 0 2006.210.07:34:37.77#ibcon#about to read 6, iclass 39, count 0 2006.210.07:34:37.77#ibcon#read 6, iclass 39, count 0 2006.210.07:34:37.77#ibcon#end of sib2, iclass 39, count 0 2006.210.07:34:37.77#ibcon#*after write, iclass 39, count 0 2006.210.07:34:37.77#ibcon#*before return 0, iclass 39, count 0 2006.210.07:34:37.77#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:37.77#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:37.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:34:37.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:34:37.77$vc4f8/valo=2,572.99 2006.210.07:34:37.77#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:34:37.77#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:34:37.77#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:37.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:37.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:37.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:37.77#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:34:37.77#ibcon#first serial, iclass 3, count 0 2006.210.07:34:37.77#ibcon#enter sib2, iclass 3, count 0 2006.210.07:34:37.77#ibcon#flushed, iclass 3, count 0 2006.210.07:34:37.77#ibcon#about to write, iclass 3, count 0 2006.210.07:34:37.77#ibcon#wrote, iclass 3, count 0 2006.210.07:34:37.77#ibcon#about to read 3, iclass 3, count 0 2006.210.07:34:37.79#ibcon#read 3, iclass 3, count 0 2006.210.07:34:37.79#ibcon#about to read 4, iclass 3, count 0 2006.210.07:34:37.79#ibcon#read 4, iclass 3, count 0 2006.210.07:34:37.79#ibcon#about to read 5, iclass 3, count 0 2006.210.07:34:37.79#ibcon#read 5, iclass 3, count 0 2006.210.07:34:37.79#ibcon#about to read 6, iclass 3, count 0 2006.210.07:34:37.79#ibcon#read 6, iclass 3, count 0 2006.210.07:34:37.79#ibcon#end of sib2, iclass 3, count 0 2006.210.07:34:37.79#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:34:37.79#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:34:37.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:34:37.79#ibcon#*before write, iclass 3, count 0 2006.210.07:34:37.79#ibcon#enter sib2, iclass 3, count 0 2006.210.07:34:37.79#ibcon#flushed, iclass 3, count 0 2006.210.07:34:37.79#ibcon#about to write, iclass 3, count 0 2006.210.07:34:37.79#ibcon#wrote, iclass 3, count 0 2006.210.07:34:37.79#ibcon#about to read 3, iclass 3, count 0 2006.210.07:34:37.83#ibcon#read 3, iclass 3, count 0 2006.210.07:34:37.83#ibcon#about to read 4, iclass 3, count 0 2006.210.07:34:37.83#ibcon#read 4, iclass 3, count 0 2006.210.07:34:37.83#ibcon#about to read 5, iclass 3, count 0 2006.210.07:34:37.83#ibcon#read 5, iclass 3, count 0 2006.210.07:34:37.83#ibcon#about to read 6, iclass 3, count 0 2006.210.07:34:37.83#ibcon#read 6, iclass 3, count 0 2006.210.07:34:37.83#ibcon#end of sib2, iclass 3, count 0 2006.210.07:34:37.83#ibcon#*after write, iclass 3, count 0 2006.210.07:34:37.83#ibcon#*before return 0, iclass 3, count 0 2006.210.07:34:37.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:37.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:37.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:34:37.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:34:37.83$vc4f8/va=2,7 2006.210.07:34:37.83#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:34:37.83#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:34:37.83#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:37.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:37.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:37.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:37.89#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:34:37.89#ibcon#first serial, iclass 5, count 2 2006.210.07:34:37.89#ibcon#enter sib2, iclass 5, count 2 2006.210.07:34:37.89#ibcon#flushed, iclass 5, count 2 2006.210.07:34:37.89#ibcon#about to write, iclass 5, count 2 2006.210.07:34:37.89#ibcon#wrote, iclass 5, count 2 2006.210.07:34:37.89#ibcon#about to read 3, iclass 5, count 2 2006.210.07:34:37.91#ibcon#read 3, iclass 5, count 2 2006.210.07:34:37.91#ibcon#about to read 4, iclass 5, count 2 2006.210.07:34:37.91#ibcon#read 4, iclass 5, count 2 2006.210.07:34:37.91#ibcon#about to read 5, iclass 5, count 2 2006.210.07:34:37.91#ibcon#read 5, iclass 5, count 2 2006.210.07:34:37.91#ibcon#about to read 6, iclass 5, count 2 2006.210.07:34:37.91#ibcon#read 6, iclass 5, count 2 2006.210.07:34:37.91#ibcon#end of sib2, iclass 5, count 2 2006.210.07:34:37.91#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:34:37.91#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:34:37.91#ibcon#[25=AT02-07\r\n] 2006.210.07:34:37.91#ibcon#*before write, iclass 5, count 2 2006.210.07:34:37.91#ibcon#enter sib2, iclass 5, count 2 2006.210.07:34:37.91#ibcon#flushed, iclass 5, count 2 2006.210.07:34:37.91#ibcon#about to write, iclass 5, count 2 2006.210.07:34:37.91#ibcon#wrote, iclass 5, count 2 2006.210.07:34:37.91#ibcon#about to read 3, iclass 5, count 2 2006.210.07:34:37.94#ibcon#read 3, iclass 5, count 2 2006.210.07:34:37.94#ibcon#about to read 4, iclass 5, count 2 2006.210.07:34:37.94#ibcon#read 4, iclass 5, count 2 2006.210.07:34:37.94#ibcon#about to read 5, iclass 5, count 2 2006.210.07:34:37.94#ibcon#read 5, iclass 5, count 2 2006.210.07:34:37.94#ibcon#about to read 6, iclass 5, count 2 2006.210.07:34:37.94#ibcon#read 6, iclass 5, count 2 2006.210.07:34:37.94#ibcon#end of sib2, iclass 5, count 2 2006.210.07:34:37.94#ibcon#*after write, iclass 5, count 2 2006.210.07:34:37.94#ibcon#*before return 0, iclass 5, count 2 2006.210.07:34:37.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:37.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:37.94#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:34:37.94#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:37.94#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:38.06#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:38.06#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:38.06#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:34:38.06#ibcon#first serial, iclass 5, count 0 2006.210.07:34:38.06#ibcon#enter sib2, iclass 5, count 0 2006.210.07:34:38.06#ibcon#flushed, iclass 5, count 0 2006.210.07:34:38.06#ibcon#about to write, iclass 5, count 0 2006.210.07:34:38.06#ibcon#wrote, iclass 5, count 0 2006.210.07:34:38.06#ibcon#about to read 3, iclass 5, count 0 2006.210.07:34:38.08#ibcon#read 3, iclass 5, count 0 2006.210.07:34:38.08#ibcon#about to read 4, iclass 5, count 0 2006.210.07:34:38.08#ibcon#read 4, iclass 5, count 0 2006.210.07:34:38.08#ibcon#about to read 5, iclass 5, count 0 2006.210.07:34:38.08#ibcon#read 5, iclass 5, count 0 2006.210.07:34:38.08#ibcon#about to read 6, iclass 5, count 0 2006.210.07:34:38.08#ibcon#read 6, iclass 5, count 0 2006.210.07:34:38.08#ibcon#end of sib2, iclass 5, count 0 2006.210.07:34:38.08#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:34:38.08#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:34:38.08#ibcon#[25=USB\r\n] 2006.210.07:34:38.08#ibcon#*before write, iclass 5, count 0 2006.210.07:34:38.08#ibcon#enter sib2, iclass 5, count 0 2006.210.07:34:38.08#ibcon#flushed, iclass 5, count 0 2006.210.07:34:38.08#ibcon#about to write, iclass 5, count 0 2006.210.07:34:38.08#ibcon#wrote, iclass 5, count 0 2006.210.07:34:38.08#ibcon#about to read 3, iclass 5, count 0 2006.210.07:34:38.11#ibcon#read 3, iclass 5, count 0 2006.210.07:34:38.11#ibcon#about to read 4, iclass 5, count 0 2006.210.07:34:38.11#ibcon#read 4, iclass 5, count 0 2006.210.07:34:38.11#ibcon#about to read 5, iclass 5, count 0 2006.210.07:34:38.11#ibcon#read 5, iclass 5, count 0 2006.210.07:34:38.11#ibcon#about to read 6, iclass 5, count 0 2006.210.07:34:38.11#ibcon#read 6, iclass 5, count 0 2006.210.07:34:38.11#ibcon#end of sib2, iclass 5, count 0 2006.210.07:34:38.11#ibcon#*after write, iclass 5, count 0 2006.210.07:34:38.11#ibcon#*before return 0, iclass 5, count 0 2006.210.07:34:38.11#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:38.11#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:38.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:34:38.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:34:38.11$vc4f8/valo=3,672.99 2006.210.07:34:38.11#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:34:38.11#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:34:38.11#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:38.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:38.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:38.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:38.11#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:34:38.11#ibcon#first serial, iclass 7, count 0 2006.210.07:34:38.11#ibcon#enter sib2, iclass 7, count 0 2006.210.07:34:38.11#ibcon#flushed, iclass 7, count 0 2006.210.07:34:38.11#ibcon#about to write, iclass 7, count 0 2006.210.07:34:38.11#ibcon#wrote, iclass 7, count 0 2006.210.07:34:38.11#ibcon#about to read 3, iclass 7, count 0 2006.210.07:34:38.13#ibcon#read 3, iclass 7, count 0 2006.210.07:34:38.13#ibcon#about to read 4, iclass 7, count 0 2006.210.07:34:38.13#ibcon#read 4, iclass 7, count 0 2006.210.07:34:38.13#ibcon#about to read 5, iclass 7, count 0 2006.210.07:34:38.13#ibcon#read 5, iclass 7, count 0 2006.210.07:34:38.13#ibcon#about to read 6, iclass 7, count 0 2006.210.07:34:38.13#ibcon#read 6, iclass 7, count 0 2006.210.07:34:38.13#ibcon#end of sib2, iclass 7, count 0 2006.210.07:34:38.13#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:34:38.13#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:34:38.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:34:38.13#ibcon#*before write, iclass 7, count 0 2006.210.07:34:38.13#ibcon#enter sib2, iclass 7, count 0 2006.210.07:34:38.13#ibcon#flushed, iclass 7, count 0 2006.210.07:34:38.13#ibcon#about to write, iclass 7, count 0 2006.210.07:34:38.13#ibcon#wrote, iclass 7, count 0 2006.210.07:34:38.13#ibcon#about to read 3, iclass 7, count 0 2006.210.07:34:38.17#ibcon#read 3, iclass 7, count 0 2006.210.07:34:38.17#ibcon#about to read 4, iclass 7, count 0 2006.210.07:34:38.17#ibcon#read 4, iclass 7, count 0 2006.210.07:34:38.17#ibcon#about to read 5, iclass 7, count 0 2006.210.07:34:38.17#ibcon#read 5, iclass 7, count 0 2006.210.07:34:38.17#ibcon#about to read 6, iclass 7, count 0 2006.210.07:34:38.17#ibcon#read 6, iclass 7, count 0 2006.210.07:34:38.17#ibcon#end of sib2, iclass 7, count 0 2006.210.07:34:38.17#ibcon#*after write, iclass 7, count 0 2006.210.07:34:38.17#ibcon#*before return 0, iclass 7, count 0 2006.210.07:34:38.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:38.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:38.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:34:38.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:34:38.17$vc4f8/va=3,6 2006.210.07:34:38.17#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:34:38.17#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:34:38.17#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:38.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:38.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:38.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:38.23#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:34:38.23#ibcon#first serial, iclass 11, count 2 2006.210.07:34:38.23#ibcon#enter sib2, iclass 11, count 2 2006.210.07:34:38.23#ibcon#flushed, iclass 11, count 2 2006.210.07:34:38.23#ibcon#about to write, iclass 11, count 2 2006.210.07:34:38.23#ibcon#wrote, iclass 11, count 2 2006.210.07:34:38.23#ibcon#about to read 3, iclass 11, count 2 2006.210.07:34:38.25#ibcon#read 3, iclass 11, count 2 2006.210.07:34:38.25#ibcon#about to read 4, iclass 11, count 2 2006.210.07:34:38.25#ibcon#read 4, iclass 11, count 2 2006.210.07:34:38.25#ibcon#about to read 5, iclass 11, count 2 2006.210.07:34:38.25#ibcon#read 5, iclass 11, count 2 2006.210.07:34:38.25#ibcon#about to read 6, iclass 11, count 2 2006.210.07:34:38.25#ibcon#read 6, iclass 11, count 2 2006.210.07:34:38.25#ibcon#end of sib2, iclass 11, count 2 2006.210.07:34:38.25#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:34:38.25#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:34:38.25#ibcon#[25=AT03-06\r\n] 2006.210.07:34:38.25#ibcon#*before write, iclass 11, count 2 2006.210.07:34:38.25#ibcon#enter sib2, iclass 11, count 2 2006.210.07:34:38.25#ibcon#flushed, iclass 11, count 2 2006.210.07:34:38.25#ibcon#about to write, iclass 11, count 2 2006.210.07:34:38.25#ibcon#wrote, iclass 11, count 2 2006.210.07:34:38.25#ibcon#about to read 3, iclass 11, count 2 2006.210.07:34:38.28#ibcon#read 3, iclass 11, count 2 2006.210.07:34:38.28#ibcon#about to read 4, iclass 11, count 2 2006.210.07:34:38.28#ibcon#read 4, iclass 11, count 2 2006.210.07:34:38.28#ibcon#about to read 5, iclass 11, count 2 2006.210.07:34:38.28#ibcon#read 5, iclass 11, count 2 2006.210.07:34:38.28#ibcon#about to read 6, iclass 11, count 2 2006.210.07:34:38.28#ibcon#read 6, iclass 11, count 2 2006.210.07:34:38.28#ibcon#end of sib2, iclass 11, count 2 2006.210.07:34:38.28#ibcon#*after write, iclass 11, count 2 2006.210.07:34:38.28#ibcon#*before return 0, iclass 11, count 2 2006.210.07:34:38.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:38.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:38.28#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:34:38.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:38.28#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:38.40#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:38.40#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:38.40#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:34:38.40#ibcon#first serial, iclass 11, count 0 2006.210.07:34:38.40#ibcon#enter sib2, iclass 11, count 0 2006.210.07:34:38.40#ibcon#flushed, iclass 11, count 0 2006.210.07:34:38.40#ibcon#about to write, iclass 11, count 0 2006.210.07:34:38.40#ibcon#wrote, iclass 11, count 0 2006.210.07:34:38.40#ibcon#about to read 3, iclass 11, count 0 2006.210.07:34:38.42#ibcon#read 3, iclass 11, count 0 2006.210.07:34:38.42#ibcon#about to read 4, iclass 11, count 0 2006.210.07:34:38.42#ibcon#read 4, iclass 11, count 0 2006.210.07:34:38.42#ibcon#about to read 5, iclass 11, count 0 2006.210.07:34:38.42#ibcon#read 5, iclass 11, count 0 2006.210.07:34:38.42#ibcon#about to read 6, iclass 11, count 0 2006.210.07:34:38.42#ibcon#read 6, iclass 11, count 0 2006.210.07:34:38.42#ibcon#end of sib2, iclass 11, count 0 2006.210.07:34:38.42#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:34:38.42#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:34:38.42#ibcon#[25=USB\r\n] 2006.210.07:34:38.42#ibcon#*before write, iclass 11, count 0 2006.210.07:34:38.42#ibcon#enter sib2, iclass 11, count 0 2006.210.07:34:38.42#ibcon#flushed, iclass 11, count 0 2006.210.07:34:38.42#ibcon#about to write, iclass 11, count 0 2006.210.07:34:38.42#ibcon#wrote, iclass 11, count 0 2006.210.07:34:38.42#ibcon#about to read 3, iclass 11, count 0 2006.210.07:34:38.45#ibcon#read 3, iclass 11, count 0 2006.210.07:34:38.45#ibcon#about to read 4, iclass 11, count 0 2006.210.07:34:38.45#ibcon#read 4, iclass 11, count 0 2006.210.07:34:38.45#ibcon#about to read 5, iclass 11, count 0 2006.210.07:34:38.45#ibcon#read 5, iclass 11, count 0 2006.210.07:34:38.45#ibcon#about to read 6, iclass 11, count 0 2006.210.07:34:38.45#ibcon#read 6, iclass 11, count 0 2006.210.07:34:38.45#ibcon#end of sib2, iclass 11, count 0 2006.210.07:34:38.45#ibcon#*after write, iclass 11, count 0 2006.210.07:34:38.45#ibcon#*before return 0, iclass 11, count 0 2006.210.07:34:38.45#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:38.45#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:38.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:34:38.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:34:38.45$vc4f8/valo=4,832.99 2006.210.07:34:38.45#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:34:38.45#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:34:38.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:38.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:38.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:38.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:38.45#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:34:38.45#ibcon#first serial, iclass 13, count 0 2006.210.07:34:38.45#ibcon#enter sib2, iclass 13, count 0 2006.210.07:34:38.45#ibcon#flushed, iclass 13, count 0 2006.210.07:34:38.45#ibcon#about to write, iclass 13, count 0 2006.210.07:34:38.45#ibcon#wrote, iclass 13, count 0 2006.210.07:34:38.45#ibcon#about to read 3, iclass 13, count 0 2006.210.07:34:38.47#ibcon#read 3, iclass 13, count 0 2006.210.07:34:38.47#ibcon#about to read 4, iclass 13, count 0 2006.210.07:34:38.47#ibcon#read 4, iclass 13, count 0 2006.210.07:34:38.47#ibcon#about to read 5, iclass 13, count 0 2006.210.07:34:38.47#ibcon#read 5, iclass 13, count 0 2006.210.07:34:38.47#ibcon#about to read 6, iclass 13, count 0 2006.210.07:34:38.47#ibcon#read 6, iclass 13, count 0 2006.210.07:34:38.47#ibcon#end of sib2, iclass 13, count 0 2006.210.07:34:38.47#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:34:38.47#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:34:38.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:34:38.47#ibcon#*before write, iclass 13, count 0 2006.210.07:34:38.47#ibcon#enter sib2, iclass 13, count 0 2006.210.07:34:38.47#ibcon#flushed, iclass 13, count 0 2006.210.07:34:38.47#ibcon#about to write, iclass 13, count 0 2006.210.07:34:38.47#ibcon#wrote, iclass 13, count 0 2006.210.07:34:38.47#ibcon#about to read 3, iclass 13, count 0 2006.210.07:34:38.51#ibcon#read 3, iclass 13, count 0 2006.210.07:34:38.51#ibcon#about to read 4, iclass 13, count 0 2006.210.07:34:38.51#ibcon#read 4, iclass 13, count 0 2006.210.07:34:38.51#ibcon#about to read 5, iclass 13, count 0 2006.210.07:34:38.51#ibcon#read 5, iclass 13, count 0 2006.210.07:34:38.51#ibcon#about to read 6, iclass 13, count 0 2006.210.07:34:38.51#ibcon#read 6, iclass 13, count 0 2006.210.07:34:38.51#ibcon#end of sib2, iclass 13, count 0 2006.210.07:34:38.51#ibcon#*after write, iclass 13, count 0 2006.210.07:34:38.51#ibcon#*before return 0, iclass 13, count 0 2006.210.07:34:38.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:38.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:38.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:34:38.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:34:38.51$vc4f8/va=4,7 2006.210.07:34:38.51#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:34:38.51#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:34:38.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:38.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:38.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:38.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:38.57#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:34:38.57#ibcon#first serial, iclass 15, count 2 2006.210.07:34:38.57#ibcon#enter sib2, iclass 15, count 2 2006.210.07:34:38.57#ibcon#flushed, iclass 15, count 2 2006.210.07:34:38.57#ibcon#about to write, iclass 15, count 2 2006.210.07:34:38.57#ibcon#wrote, iclass 15, count 2 2006.210.07:34:38.57#ibcon#about to read 3, iclass 15, count 2 2006.210.07:34:38.59#ibcon#read 3, iclass 15, count 2 2006.210.07:34:38.59#ibcon#about to read 4, iclass 15, count 2 2006.210.07:34:38.59#ibcon#read 4, iclass 15, count 2 2006.210.07:34:38.59#ibcon#about to read 5, iclass 15, count 2 2006.210.07:34:38.59#ibcon#read 5, iclass 15, count 2 2006.210.07:34:38.59#ibcon#about to read 6, iclass 15, count 2 2006.210.07:34:38.59#ibcon#read 6, iclass 15, count 2 2006.210.07:34:38.59#ibcon#end of sib2, iclass 15, count 2 2006.210.07:34:38.59#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:34:38.59#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:34:38.59#ibcon#[25=AT04-07\r\n] 2006.210.07:34:38.59#ibcon#*before write, iclass 15, count 2 2006.210.07:34:38.59#ibcon#enter sib2, iclass 15, count 2 2006.210.07:34:38.59#ibcon#flushed, iclass 15, count 2 2006.210.07:34:38.59#ibcon#about to write, iclass 15, count 2 2006.210.07:34:38.59#ibcon#wrote, iclass 15, count 2 2006.210.07:34:38.59#ibcon#about to read 3, iclass 15, count 2 2006.210.07:34:38.62#ibcon#read 3, iclass 15, count 2 2006.210.07:34:38.62#ibcon#about to read 4, iclass 15, count 2 2006.210.07:34:38.62#ibcon#read 4, iclass 15, count 2 2006.210.07:34:38.62#ibcon#about to read 5, iclass 15, count 2 2006.210.07:34:38.62#ibcon#read 5, iclass 15, count 2 2006.210.07:34:38.62#ibcon#about to read 6, iclass 15, count 2 2006.210.07:34:38.62#ibcon#read 6, iclass 15, count 2 2006.210.07:34:38.62#ibcon#end of sib2, iclass 15, count 2 2006.210.07:34:38.62#ibcon#*after write, iclass 15, count 2 2006.210.07:34:38.62#ibcon#*before return 0, iclass 15, count 2 2006.210.07:34:38.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:38.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:38.62#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:34:38.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:38.62#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:38.74#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:38.74#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:38.74#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:34:38.74#ibcon#first serial, iclass 15, count 0 2006.210.07:34:38.74#ibcon#enter sib2, iclass 15, count 0 2006.210.07:34:38.74#ibcon#flushed, iclass 15, count 0 2006.210.07:34:38.74#ibcon#about to write, iclass 15, count 0 2006.210.07:34:38.74#ibcon#wrote, iclass 15, count 0 2006.210.07:34:38.74#ibcon#about to read 3, iclass 15, count 0 2006.210.07:34:38.76#ibcon#read 3, iclass 15, count 0 2006.210.07:34:38.76#ibcon#about to read 4, iclass 15, count 0 2006.210.07:34:38.76#ibcon#read 4, iclass 15, count 0 2006.210.07:34:38.76#ibcon#about to read 5, iclass 15, count 0 2006.210.07:34:38.76#ibcon#read 5, iclass 15, count 0 2006.210.07:34:38.76#ibcon#about to read 6, iclass 15, count 0 2006.210.07:34:38.76#ibcon#read 6, iclass 15, count 0 2006.210.07:34:38.76#ibcon#end of sib2, iclass 15, count 0 2006.210.07:34:38.76#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:34:38.76#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:34:38.76#ibcon#[25=USB\r\n] 2006.210.07:34:38.76#ibcon#*before write, iclass 15, count 0 2006.210.07:34:38.76#ibcon#enter sib2, iclass 15, count 0 2006.210.07:34:38.76#ibcon#flushed, iclass 15, count 0 2006.210.07:34:38.76#ibcon#about to write, iclass 15, count 0 2006.210.07:34:38.76#ibcon#wrote, iclass 15, count 0 2006.210.07:34:38.76#ibcon#about to read 3, iclass 15, count 0 2006.210.07:34:38.79#ibcon#read 3, iclass 15, count 0 2006.210.07:34:38.79#ibcon#about to read 4, iclass 15, count 0 2006.210.07:34:38.79#ibcon#read 4, iclass 15, count 0 2006.210.07:34:38.79#ibcon#about to read 5, iclass 15, count 0 2006.210.07:34:38.79#ibcon#read 5, iclass 15, count 0 2006.210.07:34:38.79#ibcon#about to read 6, iclass 15, count 0 2006.210.07:34:38.79#ibcon#read 6, iclass 15, count 0 2006.210.07:34:38.79#ibcon#end of sib2, iclass 15, count 0 2006.210.07:34:38.79#ibcon#*after write, iclass 15, count 0 2006.210.07:34:38.79#ibcon#*before return 0, iclass 15, count 0 2006.210.07:34:38.79#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:38.79#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:38.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:34:38.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:34:38.79$vc4f8/valo=5,652.99 2006.210.07:34:38.79#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:34:38.79#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:34:38.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:38.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:38.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:38.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:38.79#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:34:38.79#ibcon#first serial, iclass 17, count 0 2006.210.07:34:38.79#ibcon#enter sib2, iclass 17, count 0 2006.210.07:34:38.79#ibcon#flushed, iclass 17, count 0 2006.210.07:34:38.79#ibcon#about to write, iclass 17, count 0 2006.210.07:34:38.79#ibcon#wrote, iclass 17, count 0 2006.210.07:34:38.79#ibcon#about to read 3, iclass 17, count 0 2006.210.07:34:38.81#ibcon#read 3, iclass 17, count 0 2006.210.07:34:38.81#ibcon#about to read 4, iclass 17, count 0 2006.210.07:34:38.81#ibcon#read 4, iclass 17, count 0 2006.210.07:34:38.81#ibcon#about to read 5, iclass 17, count 0 2006.210.07:34:38.81#ibcon#read 5, iclass 17, count 0 2006.210.07:34:38.81#ibcon#about to read 6, iclass 17, count 0 2006.210.07:34:38.81#ibcon#read 6, iclass 17, count 0 2006.210.07:34:38.81#ibcon#end of sib2, iclass 17, count 0 2006.210.07:34:38.81#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:34:38.81#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:34:38.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:34:38.81#ibcon#*before write, iclass 17, count 0 2006.210.07:34:38.81#ibcon#enter sib2, iclass 17, count 0 2006.210.07:34:38.81#ibcon#flushed, iclass 17, count 0 2006.210.07:34:38.81#ibcon#about to write, iclass 17, count 0 2006.210.07:34:38.81#ibcon#wrote, iclass 17, count 0 2006.210.07:34:38.81#ibcon#about to read 3, iclass 17, count 0 2006.210.07:34:38.85#ibcon#read 3, iclass 17, count 0 2006.210.07:34:38.85#ibcon#about to read 4, iclass 17, count 0 2006.210.07:34:38.85#ibcon#read 4, iclass 17, count 0 2006.210.07:34:38.85#ibcon#about to read 5, iclass 17, count 0 2006.210.07:34:38.85#ibcon#read 5, iclass 17, count 0 2006.210.07:34:38.85#ibcon#about to read 6, iclass 17, count 0 2006.210.07:34:38.85#ibcon#read 6, iclass 17, count 0 2006.210.07:34:38.85#ibcon#end of sib2, iclass 17, count 0 2006.210.07:34:38.85#ibcon#*after write, iclass 17, count 0 2006.210.07:34:38.85#ibcon#*before return 0, iclass 17, count 0 2006.210.07:34:38.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:38.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:38.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:34:38.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:34:38.85$vc4f8/va=5,7 2006.210.07:34:38.85#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:34:38.85#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:34:38.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:38.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:38.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:38.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:38.91#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:34:38.91#ibcon#first serial, iclass 19, count 2 2006.210.07:34:38.91#ibcon#enter sib2, iclass 19, count 2 2006.210.07:34:38.91#ibcon#flushed, iclass 19, count 2 2006.210.07:34:38.91#ibcon#about to write, iclass 19, count 2 2006.210.07:34:38.91#ibcon#wrote, iclass 19, count 2 2006.210.07:34:38.91#ibcon#about to read 3, iclass 19, count 2 2006.210.07:34:38.93#ibcon#read 3, iclass 19, count 2 2006.210.07:34:38.93#ibcon#about to read 4, iclass 19, count 2 2006.210.07:34:38.93#ibcon#read 4, iclass 19, count 2 2006.210.07:34:38.93#ibcon#about to read 5, iclass 19, count 2 2006.210.07:34:38.93#ibcon#read 5, iclass 19, count 2 2006.210.07:34:38.93#ibcon#about to read 6, iclass 19, count 2 2006.210.07:34:38.93#ibcon#read 6, iclass 19, count 2 2006.210.07:34:38.93#ibcon#end of sib2, iclass 19, count 2 2006.210.07:34:38.93#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:34:38.93#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:34:38.93#ibcon#[25=AT05-07\r\n] 2006.210.07:34:38.93#ibcon#*before write, iclass 19, count 2 2006.210.07:34:38.93#ibcon#enter sib2, iclass 19, count 2 2006.210.07:34:38.93#ibcon#flushed, iclass 19, count 2 2006.210.07:34:38.93#ibcon#about to write, iclass 19, count 2 2006.210.07:34:38.93#ibcon#wrote, iclass 19, count 2 2006.210.07:34:38.93#ibcon#about to read 3, iclass 19, count 2 2006.210.07:34:38.96#ibcon#read 3, iclass 19, count 2 2006.210.07:34:38.96#ibcon#about to read 4, iclass 19, count 2 2006.210.07:34:38.96#ibcon#read 4, iclass 19, count 2 2006.210.07:34:38.96#ibcon#about to read 5, iclass 19, count 2 2006.210.07:34:38.96#ibcon#read 5, iclass 19, count 2 2006.210.07:34:38.96#ibcon#about to read 6, iclass 19, count 2 2006.210.07:34:38.96#ibcon#read 6, iclass 19, count 2 2006.210.07:34:38.96#ibcon#end of sib2, iclass 19, count 2 2006.210.07:34:38.96#ibcon#*after write, iclass 19, count 2 2006.210.07:34:38.96#ibcon#*before return 0, iclass 19, count 2 2006.210.07:34:38.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:38.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:38.96#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:34:38.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:38.96#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:39.08#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:39.08#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:39.08#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:34:39.08#ibcon#first serial, iclass 19, count 0 2006.210.07:34:39.08#ibcon#enter sib2, iclass 19, count 0 2006.210.07:34:39.08#ibcon#flushed, iclass 19, count 0 2006.210.07:34:39.08#ibcon#about to write, iclass 19, count 0 2006.210.07:34:39.08#ibcon#wrote, iclass 19, count 0 2006.210.07:34:39.08#ibcon#about to read 3, iclass 19, count 0 2006.210.07:34:39.10#ibcon#read 3, iclass 19, count 0 2006.210.07:34:39.10#ibcon#about to read 4, iclass 19, count 0 2006.210.07:34:39.10#ibcon#read 4, iclass 19, count 0 2006.210.07:34:39.10#ibcon#about to read 5, iclass 19, count 0 2006.210.07:34:39.10#ibcon#read 5, iclass 19, count 0 2006.210.07:34:39.10#ibcon#about to read 6, iclass 19, count 0 2006.210.07:34:39.10#ibcon#read 6, iclass 19, count 0 2006.210.07:34:39.10#ibcon#end of sib2, iclass 19, count 0 2006.210.07:34:39.10#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:34:39.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:34:39.10#ibcon#[25=USB\r\n] 2006.210.07:34:39.10#ibcon#*before write, iclass 19, count 0 2006.210.07:34:39.10#ibcon#enter sib2, iclass 19, count 0 2006.210.07:34:39.10#ibcon#flushed, iclass 19, count 0 2006.210.07:34:39.10#ibcon#about to write, iclass 19, count 0 2006.210.07:34:39.10#ibcon#wrote, iclass 19, count 0 2006.210.07:34:39.10#ibcon#about to read 3, iclass 19, count 0 2006.210.07:34:39.13#ibcon#read 3, iclass 19, count 0 2006.210.07:34:39.13#ibcon#about to read 4, iclass 19, count 0 2006.210.07:34:39.13#ibcon#read 4, iclass 19, count 0 2006.210.07:34:39.13#ibcon#about to read 5, iclass 19, count 0 2006.210.07:34:39.13#ibcon#read 5, iclass 19, count 0 2006.210.07:34:39.13#ibcon#about to read 6, iclass 19, count 0 2006.210.07:34:39.13#ibcon#read 6, iclass 19, count 0 2006.210.07:34:39.13#ibcon#end of sib2, iclass 19, count 0 2006.210.07:34:39.13#ibcon#*after write, iclass 19, count 0 2006.210.07:34:39.13#ibcon#*before return 0, iclass 19, count 0 2006.210.07:34:39.13#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:39.13#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:39.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:34:39.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:34:39.13$vc4f8/valo=6,772.99 2006.210.07:34:39.13#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:34:39.13#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:34:39.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:39.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:39.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:39.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:39.13#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:34:39.13#ibcon#first serial, iclass 21, count 0 2006.210.07:34:39.13#ibcon#enter sib2, iclass 21, count 0 2006.210.07:34:39.13#ibcon#flushed, iclass 21, count 0 2006.210.07:34:39.13#ibcon#about to write, iclass 21, count 0 2006.210.07:34:39.13#ibcon#wrote, iclass 21, count 0 2006.210.07:34:39.13#ibcon#about to read 3, iclass 21, count 0 2006.210.07:34:39.15#ibcon#read 3, iclass 21, count 0 2006.210.07:34:39.15#ibcon#about to read 4, iclass 21, count 0 2006.210.07:34:39.15#ibcon#read 4, iclass 21, count 0 2006.210.07:34:39.15#ibcon#about to read 5, iclass 21, count 0 2006.210.07:34:39.15#ibcon#read 5, iclass 21, count 0 2006.210.07:34:39.15#ibcon#about to read 6, iclass 21, count 0 2006.210.07:34:39.15#ibcon#read 6, iclass 21, count 0 2006.210.07:34:39.15#ibcon#end of sib2, iclass 21, count 0 2006.210.07:34:39.15#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:34:39.15#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:34:39.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:34:39.15#ibcon#*before write, iclass 21, count 0 2006.210.07:34:39.15#ibcon#enter sib2, iclass 21, count 0 2006.210.07:34:39.15#ibcon#flushed, iclass 21, count 0 2006.210.07:34:39.15#ibcon#about to write, iclass 21, count 0 2006.210.07:34:39.15#ibcon#wrote, iclass 21, count 0 2006.210.07:34:39.15#ibcon#about to read 3, iclass 21, count 0 2006.210.07:34:39.19#ibcon#read 3, iclass 21, count 0 2006.210.07:34:39.19#ibcon#about to read 4, iclass 21, count 0 2006.210.07:34:39.19#ibcon#read 4, iclass 21, count 0 2006.210.07:34:39.19#ibcon#about to read 5, iclass 21, count 0 2006.210.07:34:39.19#ibcon#read 5, iclass 21, count 0 2006.210.07:34:39.19#ibcon#about to read 6, iclass 21, count 0 2006.210.07:34:39.19#ibcon#read 6, iclass 21, count 0 2006.210.07:34:39.19#ibcon#end of sib2, iclass 21, count 0 2006.210.07:34:39.19#ibcon#*after write, iclass 21, count 0 2006.210.07:34:39.19#ibcon#*before return 0, iclass 21, count 0 2006.210.07:34:39.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:39.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:39.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:34:39.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:34:39.19$vc4f8/va=6,6 2006.210.07:34:39.19#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.07:34:39.19#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.07:34:39.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:39.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:39.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:39.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:39.25#ibcon#enter wrdev, iclass 23, count 2 2006.210.07:34:39.25#ibcon#first serial, iclass 23, count 2 2006.210.07:34:39.25#ibcon#enter sib2, iclass 23, count 2 2006.210.07:34:39.25#ibcon#flushed, iclass 23, count 2 2006.210.07:34:39.25#ibcon#about to write, iclass 23, count 2 2006.210.07:34:39.25#ibcon#wrote, iclass 23, count 2 2006.210.07:34:39.25#ibcon#about to read 3, iclass 23, count 2 2006.210.07:34:39.27#ibcon#read 3, iclass 23, count 2 2006.210.07:34:39.27#ibcon#about to read 4, iclass 23, count 2 2006.210.07:34:39.27#ibcon#read 4, iclass 23, count 2 2006.210.07:34:39.27#ibcon#about to read 5, iclass 23, count 2 2006.210.07:34:39.27#ibcon#read 5, iclass 23, count 2 2006.210.07:34:39.27#ibcon#about to read 6, iclass 23, count 2 2006.210.07:34:39.27#ibcon#read 6, iclass 23, count 2 2006.210.07:34:39.27#ibcon#end of sib2, iclass 23, count 2 2006.210.07:34:39.27#ibcon#*mode == 0, iclass 23, count 2 2006.210.07:34:39.27#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.07:34:39.27#ibcon#[25=AT06-06\r\n] 2006.210.07:34:39.27#ibcon#*before write, iclass 23, count 2 2006.210.07:34:39.27#ibcon#enter sib2, iclass 23, count 2 2006.210.07:34:39.27#ibcon#flushed, iclass 23, count 2 2006.210.07:34:39.27#ibcon#about to write, iclass 23, count 2 2006.210.07:34:39.27#ibcon#wrote, iclass 23, count 2 2006.210.07:34:39.27#ibcon#about to read 3, iclass 23, count 2 2006.210.07:34:39.30#ibcon#read 3, iclass 23, count 2 2006.210.07:34:39.30#ibcon#about to read 4, iclass 23, count 2 2006.210.07:34:39.30#ibcon#read 4, iclass 23, count 2 2006.210.07:34:39.30#ibcon#about to read 5, iclass 23, count 2 2006.210.07:34:39.30#ibcon#read 5, iclass 23, count 2 2006.210.07:34:39.30#ibcon#about to read 6, iclass 23, count 2 2006.210.07:34:39.30#ibcon#read 6, iclass 23, count 2 2006.210.07:34:39.30#ibcon#end of sib2, iclass 23, count 2 2006.210.07:34:39.30#ibcon#*after write, iclass 23, count 2 2006.210.07:34:39.30#ibcon#*before return 0, iclass 23, count 2 2006.210.07:34:39.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:39.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:39.30#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.07:34:39.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:39.30#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:39.42#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:39.42#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:39.42#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:34:39.42#ibcon#first serial, iclass 23, count 0 2006.210.07:34:39.42#ibcon#enter sib2, iclass 23, count 0 2006.210.07:34:39.42#ibcon#flushed, iclass 23, count 0 2006.210.07:34:39.42#ibcon#about to write, iclass 23, count 0 2006.210.07:34:39.42#ibcon#wrote, iclass 23, count 0 2006.210.07:34:39.42#ibcon#about to read 3, iclass 23, count 0 2006.210.07:34:39.44#ibcon#read 3, iclass 23, count 0 2006.210.07:34:39.44#ibcon#about to read 4, iclass 23, count 0 2006.210.07:34:39.44#ibcon#read 4, iclass 23, count 0 2006.210.07:34:39.44#ibcon#about to read 5, iclass 23, count 0 2006.210.07:34:39.44#ibcon#read 5, iclass 23, count 0 2006.210.07:34:39.44#ibcon#about to read 6, iclass 23, count 0 2006.210.07:34:39.44#ibcon#read 6, iclass 23, count 0 2006.210.07:34:39.44#ibcon#end of sib2, iclass 23, count 0 2006.210.07:34:39.44#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:34:39.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:34:39.44#ibcon#[25=USB\r\n] 2006.210.07:34:39.44#ibcon#*before write, iclass 23, count 0 2006.210.07:34:39.44#ibcon#enter sib2, iclass 23, count 0 2006.210.07:34:39.44#ibcon#flushed, iclass 23, count 0 2006.210.07:34:39.44#ibcon#about to write, iclass 23, count 0 2006.210.07:34:39.44#ibcon#wrote, iclass 23, count 0 2006.210.07:34:39.44#ibcon#about to read 3, iclass 23, count 0 2006.210.07:34:39.47#ibcon#read 3, iclass 23, count 0 2006.210.07:34:39.47#ibcon#about to read 4, iclass 23, count 0 2006.210.07:34:39.47#ibcon#read 4, iclass 23, count 0 2006.210.07:34:39.47#ibcon#about to read 5, iclass 23, count 0 2006.210.07:34:39.47#ibcon#read 5, iclass 23, count 0 2006.210.07:34:39.47#ibcon#about to read 6, iclass 23, count 0 2006.210.07:34:39.47#ibcon#read 6, iclass 23, count 0 2006.210.07:34:39.47#ibcon#end of sib2, iclass 23, count 0 2006.210.07:34:39.47#ibcon#*after write, iclass 23, count 0 2006.210.07:34:39.47#ibcon#*before return 0, iclass 23, count 0 2006.210.07:34:39.47#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:39.47#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:39.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:34:39.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:34:39.47$vc4f8/valo=7,832.99 2006.210.07:34:39.47#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.07:34:39.47#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.07:34:39.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:39.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:39.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:39.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:39.47#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:34:39.47#ibcon#first serial, iclass 25, count 0 2006.210.07:34:39.47#ibcon#enter sib2, iclass 25, count 0 2006.210.07:34:39.47#ibcon#flushed, iclass 25, count 0 2006.210.07:34:39.47#ibcon#about to write, iclass 25, count 0 2006.210.07:34:39.47#ibcon#wrote, iclass 25, count 0 2006.210.07:34:39.47#ibcon#about to read 3, iclass 25, count 0 2006.210.07:34:39.49#ibcon#read 3, iclass 25, count 0 2006.210.07:34:39.49#ibcon#about to read 4, iclass 25, count 0 2006.210.07:34:39.49#ibcon#read 4, iclass 25, count 0 2006.210.07:34:39.49#ibcon#about to read 5, iclass 25, count 0 2006.210.07:34:39.49#ibcon#read 5, iclass 25, count 0 2006.210.07:34:39.49#ibcon#about to read 6, iclass 25, count 0 2006.210.07:34:39.49#ibcon#read 6, iclass 25, count 0 2006.210.07:34:39.49#ibcon#end of sib2, iclass 25, count 0 2006.210.07:34:39.49#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:34:39.49#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:34:39.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:34:39.49#ibcon#*before write, iclass 25, count 0 2006.210.07:34:39.49#ibcon#enter sib2, iclass 25, count 0 2006.210.07:34:39.49#ibcon#flushed, iclass 25, count 0 2006.210.07:34:39.49#ibcon#about to write, iclass 25, count 0 2006.210.07:34:39.49#ibcon#wrote, iclass 25, count 0 2006.210.07:34:39.49#ibcon#about to read 3, iclass 25, count 0 2006.210.07:34:39.53#ibcon#read 3, iclass 25, count 0 2006.210.07:34:39.53#ibcon#about to read 4, iclass 25, count 0 2006.210.07:34:39.53#ibcon#read 4, iclass 25, count 0 2006.210.07:34:39.53#ibcon#about to read 5, iclass 25, count 0 2006.210.07:34:39.53#ibcon#read 5, iclass 25, count 0 2006.210.07:34:39.53#ibcon#about to read 6, iclass 25, count 0 2006.210.07:34:39.53#ibcon#read 6, iclass 25, count 0 2006.210.07:34:39.53#ibcon#end of sib2, iclass 25, count 0 2006.210.07:34:39.53#ibcon#*after write, iclass 25, count 0 2006.210.07:34:39.53#ibcon#*before return 0, iclass 25, count 0 2006.210.07:34:39.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:39.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:39.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:34:39.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:34:39.53$vc4f8/va=7,6 2006.210.07:34:39.53#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.07:34:39.53#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.07:34:39.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:39.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:34:39.58#abcon#<5=/08 1.1 3.6 30.58 731006.2\r\n> 2006.210.07:34:39.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:34:39.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:34:39.59#ibcon#enter wrdev, iclass 27, count 2 2006.210.07:34:39.59#ibcon#first serial, iclass 27, count 2 2006.210.07:34:39.59#ibcon#enter sib2, iclass 27, count 2 2006.210.07:34:39.59#ibcon#flushed, iclass 27, count 2 2006.210.07:34:39.59#ibcon#about to write, iclass 27, count 2 2006.210.07:34:39.59#ibcon#wrote, iclass 27, count 2 2006.210.07:34:39.59#ibcon#about to read 3, iclass 27, count 2 2006.210.07:34:39.60#abcon#{5=INTERFACE CLEAR} 2006.210.07:34:39.61#ibcon#read 3, iclass 27, count 2 2006.210.07:34:39.61#ibcon#about to read 4, iclass 27, count 2 2006.210.07:34:39.61#ibcon#read 4, iclass 27, count 2 2006.210.07:34:39.61#ibcon#about to read 5, iclass 27, count 2 2006.210.07:34:39.61#ibcon#read 5, iclass 27, count 2 2006.210.07:34:39.61#ibcon#about to read 6, iclass 27, count 2 2006.210.07:34:39.61#ibcon#read 6, iclass 27, count 2 2006.210.07:34:39.61#ibcon#end of sib2, iclass 27, count 2 2006.210.07:34:39.61#ibcon#*mode == 0, iclass 27, count 2 2006.210.07:34:39.61#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.07:34:39.61#ibcon#[25=AT07-06\r\n] 2006.210.07:34:39.61#ibcon#*before write, iclass 27, count 2 2006.210.07:34:39.61#ibcon#enter sib2, iclass 27, count 2 2006.210.07:34:39.61#ibcon#flushed, iclass 27, count 2 2006.210.07:34:39.61#ibcon#about to write, iclass 27, count 2 2006.210.07:34:39.61#ibcon#wrote, iclass 27, count 2 2006.210.07:34:39.61#ibcon#about to read 3, iclass 27, count 2 2006.210.07:34:39.64#ibcon#read 3, iclass 27, count 2 2006.210.07:34:39.64#ibcon#about to read 4, iclass 27, count 2 2006.210.07:34:39.64#ibcon#read 4, iclass 27, count 2 2006.210.07:34:39.64#ibcon#about to read 5, iclass 27, count 2 2006.210.07:34:39.64#ibcon#read 5, iclass 27, count 2 2006.210.07:34:39.64#ibcon#about to read 6, iclass 27, count 2 2006.210.07:34:39.64#ibcon#read 6, iclass 27, count 2 2006.210.07:34:39.64#ibcon#end of sib2, iclass 27, count 2 2006.210.07:34:39.64#ibcon#*after write, iclass 27, count 2 2006.210.07:34:39.64#ibcon#*before return 0, iclass 27, count 2 2006.210.07:34:39.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:34:39.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:34:39.64#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.07:34:39.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:39.64#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:34:39.66#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:34:39.76#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:34:39.76#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:34:39.76#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:34:39.76#ibcon#first serial, iclass 27, count 0 2006.210.07:34:39.76#ibcon#enter sib2, iclass 27, count 0 2006.210.07:34:39.76#ibcon#flushed, iclass 27, count 0 2006.210.07:34:39.76#ibcon#about to write, iclass 27, count 0 2006.210.07:34:39.76#ibcon#wrote, iclass 27, count 0 2006.210.07:34:39.76#ibcon#about to read 3, iclass 27, count 0 2006.210.07:34:39.78#ibcon#read 3, iclass 27, count 0 2006.210.07:34:39.78#ibcon#about to read 4, iclass 27, count 0 2006.210.07:34:39.78#ibcon#read 4, iclass 27, count 0 2006.210.07:34:39.78#ibcon#about to read 5, iclass 27, count 0 2006.210.07:34:39.78#ibcon#read 5, iclass 27, count 0 2006.210.07:34:39.78#ibcon#about to read 6, iclass 27, count 0 2006.210.07:34:39.78#ibcon#read 6, iclass 27, count 0 2006.210.07:34:39.78#ibcon#end of sib2, iclass 27, count 0 2006.210.07:34:39.78#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:34:39.78#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:34:39.78#ibcon#[25=USB\r\n] 2006.210.07:34:39.78#ibcon#*before write, iclass 27, count 0 2006.210.07:34:39.78#ibcon#enter sib2, iclass 27, count 0 2006.210.07:34:39.78#ibcon#flushed, iclass 27, count 0 2006.210.07:34:39.78#ibcon#about to write, iclass 27, count 0 2006.210.07:34:39.78#ibcon#wrote, iclass 27, count 0 2006.210.07:34:39.78#ibcon#about to read 3, iclass 27, count 0 2006.210.07:34:39.81#ibcon#read 3, iclass 27, count 0 2006.210.07:34:39.81#ibcon#about to read 4, iclass 27, count 0 2006.210.07:34:39.81#ibcon#read 4, iclass 27, count 0 2006.210.07:34:39.81#ibcon#about to read 5, iclass 27, count 0 2006.210.07:34:39.81#ibcon#read 5, iclass 27, count 0 2006.210.07:34:39.81#ibcon#about to read 6, iclass 27, count 0 2006.210.07:34:39.81#ibcon#read 6, iclass 27, count 0 2006.210.07:34:39.81#ibcon#end of sib2, iclass 27, count 0 2006.210.07:34:39.81#ibcon#*after write, iclass 27, count 0 2006.210.07:34:39.81#ibcon#*before return 0, iclass 27, count 0 2006.210.07:34:39.81#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:34:39.81#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:34:39.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:34:39.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:34:39.81$vc4f8/valo=8,852.99 2006.210.07:34:39.81#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.07:34:39.81#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.07:34:39.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:39.81#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:34:39.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:34:39.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:34:39.81#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:34:39.81#ibcon#first serial, iclass 33, count 0 2006.210.07:34:39.81#ibcon#enter sib2, iclass 33, count 0 2006.210.07:34:39.81#ibcon#flushed, iclass 33, count 0 2006.210.07:34:39.81#ibcon#about to write, iclass 33, count 0 2006.210.07:34:39.81#ibcon#wrote, iclass 33, count 0 2006.210.07:34:39.81#ibcon#about to read 3, iclass 33, count 0 2006.210.07:34:39.83#ibcon#read 3, iclass 33, count 0 2006.210.07:34:39.83#ibcon#about to read 4, iclass 33, count 0 2006.210.07:34:39.83#ibcon#read 4, iclass 33, count 0 2006.210.07:34:39.83#ibcon#about to read 5, iclass 33, count 0 2006.210.07:34:39.83#ibcon#read 5, iclass 33, count 0 2006.210.07:34:39.83#ibcon#about to read 6, iclass 33, count 0 2006.210.07:34:39.83#ibcon#read 6, iclass 33, count 0 2006.210.07:34:39.83#ibcon#end of sib2, iclass 33, count 0 2006.210.07:34:39.83#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:34:39.83#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:34:39.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:34:39.83#ibcon#*before write, iclass 33, count 0 2006.210.07:34:39.83#ibcon#enter sib2, iclass 33, count 0 2006.210.07:34:39.83#ibcon#flushed, iclass 33, count 0 2006.210.07:34:39.83#ibcon#about to write, iclass 33, count 0 2006.210.07:34:39.83#ibcon#wrote, iclass 33, count 0 2006.210.07:34:39.83#ibcon#about to read 3, iclass 33, count 0 2006.210.07:34:39.87#ibcon#read 3, iclass 33, count 0 2006.210.07:34:39.87#ibcon#about to read 4, iclass 33, count 0 2006.210.07:34:39.87#ibcon#read 4, iclass 33, count 0 2006.210.07:34:39.87#ibcon#about to read 5, iclass 33, count 0 2006.210.07:34:39.87#ibcon#read 5, iclass 33, count 0 2006.210.07:34:39.87#ibcon#about to read 6, iclass 33, count 0 2006.210.07:34:39.87#ibcon#read 6, iclass 33, count 0 2006.210.07:34:39.87#ibcon#end of sib2, iclass 33, count 0 2006.210.07:34:39.87#ibcon#*after write, iclass 33, count 0 2006.210.07:34:39.87#ibcon#*before return 0, iclass 33, count 0 2006.210.07:34:39.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:34:39.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:34:39.87#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:34:39.87#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:34:39.87$vc4f8/va=8,7 2006.210.07:34:39.87#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.07:34:39.87#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.07:34:39.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:39.87#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:34:39.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:34:39.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:34:39.93#ibcon#enter wrdev, iclass 35, count 2 2006.210.07:34:39.93#ibcon#first serial, iclass 35, count 2 2006.210.07:34:39.93#ibcon#enter sib2, iclass 35, count 2 2006.210.07:34:39.93#ibcon#flushed, iclass 35, count 2 2006.210.07:34:39.93#ibcon#about to write, iclass 35, count 2 2006.210.07:34:39.93#ibcon#wrote, iclass 35, count 2 2006.210.07:34:39.93#ibcon#about to read 3, iclass 35, count 2 2006.210.07:34:39.95#ibcon#read 3, iclass 35, count 2 2006.210.07:34:39.95#ibcon#about to read 4, iclass 35, count 2 2006.210.07:34:39.95#ibcon#read 4, iclass 35, count 2 2006.210.07:34:39.95#ibcon#about to read 5, iclass 35, count 2 2006.210.07:34:39.95#ibcon#read 5, iclass 35, count 2 2006.210.07:34:39.95#ibcon#about to read 6, iclass 35, count 2 2006.210.07:34:39.95#ibcon#read 6, iclass 35, count 2 2006.210.07:34:39.95#ibcon#end of sib2, iclass 35, count 2 2006.210.07:34:39.95#ibcon#*mode == 0, iclass 35, count 2 2006.210.07:34:39.95#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.07:34:39.95#ibcon#[25=AT08-07\r\n] 2006.210.07:34:39.95#ibcon#*before write, iclass 35, count 2 2006.210.07:34:39.95#ibcon#enter sib2, iclass 35, count 2 2006.210.07:34:39.95#ibcon#flushed, iclass 35, count 2 2006.210.07:34:39.95#ibcon#about to write, iclass 35, count 2 2006.210.07:34:39.95#ibcon#wrote, iclass 35, count 2 2006.210.07:34:39.95#ibcon#about to read 3, iclass 35, count 2 2006.210.07:34:39.98#ibcon#read 3, iclass 35, count 2 2006.210.07:34:39.98#ibcon#about to read 4, iclass 35, count 2 2006.210.07:34:39.98#ibcon#read 4, iclass 35, count 2 2006.210.07:34:39.98#ibcon#about to read 5, iclass 35, count 2 2006.210.07:34:39.98#ibcon#read 5, iclass 35, count 2 2006.210.07:34:39.98#ibcon#about to read 6, iclass 35, count 2 2006.210.07:34:39.98#ibcon#read 6, iclass 35, count 2 2006.210.07:34:39.98#ibcon#end of sib2, iclass 35, count 2 2006.210.07:34:39.98#ibcon#*after write, iclass 35, count 2 2006.210.07:34:39.98#ibcon#*before return 0, iclass 35, count 2 2006.210.07:34:39.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:34:39.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:34:39.98#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.07:34:39.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:39.98#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:34:40.10#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:34:40.10#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:34:40.10#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:34:40.10#ibcon#first serial, iclass 35, count 0 2006.210.07:34:40.10#ibcon#enter sib2, iclass 35, count 0 2006.210.07:34:40.10#ibcon#flushed, iclass 35, count 0 2006.210.07:34:40.10#ibcon#about to write, iclass 35, count 0 2006.210.07:34:40.10#ibcon#wrote, iclass 35, count 0 2006.210.07:34:40.10#ibcon#about to read 3, iclass 35, count 0 2006.210.07:34:40.12#ibcon#read 3, iclass 35, count 0 2006.210.07:34:40.12#ibcon#about to read 4, iclass 35, count 0 2006.210.07:34:40.12#ibcon#read 4, iclass 35, count 0 2006.210.07:34:40.12#ibcon#about to read 5, iclass 35, count 0 2006.210.07:34:40.12#ibcon#read 5, iclass 35, count 0 2006.210.07:34:40.12#ibcon#about to read 6, iclass 35, count 0 2006.210.07:34:40.12#ibcon#read 6, iclass 35, count 0 2006.210.07:34:40.12#ibcon#end of sib2, iclass 35, count 0 2006.210.07:34:40.12#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:34:40.12#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:34:40.12#ibcon#[25=USB\r\n] 2006.210.07:34:40.12#ibcon#*before write, iclass 35, count 0 2006.210.07:34:40.12#ibcon#enter sib2, iclass 35, count 0 2006.210.07:34:40.12#ibcon#flushed, iclass 35, count 0 2006.210.07:34:40.12#ibcon#about to write, iclass 35, count 0 2006.210.07:34:40.12#ibcon#wrote, iclass 35, count 0 2006.210.07:34:40.12#ibcon#about to read 3, iclass 35, count 0 2006.210.07:34:40.15#ibcon#read 3, iclass 35, count 0 2006.210.07:34:40.15#ibcon#about to read 4, iclass 35, count 0 2006.210.07:34:40.15#ibcon#read 4, iclass 35, count 0 2006.210.07:34:40.15#ibcon#about to read 5, iclass 35, count 0 2006.210.07:34:40.15#ibcon#read 5, iclass 35, count 0 2006.210.07:34:40.15#ibcon#about to read 6, iclass 35, count 0 2006.210.07:34:40.15#ibcon#read 6, iclass 35, count 0 2006.210.07:34:40.15#ibcon#end of sib2, iclass 35, count 0 2006.210.07:34:40.15#ibcon#*after write, iclass 35, count 0 2006.210.07:34:40.15#ibcon#*before return 0, iclass 35, count 0 2006.210.07:34:40.15#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:34:40.15#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:34:40.15#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:34:40.15#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:34:40.15$vc4f8/vblo=1,632.99 2006.210.07:34:40.15#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:34:40.15#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:34:40.15#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:40.15#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:40.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:40.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:40.15#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:34:40.15#ibcon#first serial, iclass 37, count 0 2006.210.07:34:40.15#ibcon#enter sib2, iclass 37, count 0 2006.210.07:34:40.15#ibcon#flushed, iclass 37, count 0 2006.210.07:34:40.15#ibcon#about to write, iclass 37, count 0 2006.210.07:34:40.15#ibcon#wrote, iclass 37, count 0 2006.210.07:34:40.15#ibcon#about to read 3, iclass 37, count 0 2006.210.07:34:40.17#ibcon#read 3, iclass 37, count 0 2006.210.07:34:40.17#ibcon#about to read 4, iclass 37, count 0 2006.210.07:34:40.17#ibcon#read 4, iclass 37, count 0 2006.210.07:34:40.17#ibcon#about to read 5, iclass 37, count 0 2006.210.07:34:40.17#ibcon#read 5, iclass 37, count 0 2006.210.07:34:40.17#ibcon#about to read 6, iclass 37, count 0 2006.210.07:34:40.17#ibcon#read 6, iclass 37, count 0 2006.210.07:34:40.17#ibcon#end of sib2, iclass 37, count 0 2006.210.07:34:40.17#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:34:40.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:34:40.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:34:40.17#ibcon#*before write, iclass 37, count 0 2006.210.07:34:40.17#ibcon#enter sib2, iclass 37, count 0 2006.210.07:34:40.17#ibcon#flushed, iclass 37, count 0 2006.210.07:34:40.17#ibcon#about to write, iclass 37, count 0 2006.210.07:34:40.17#ibcon#wrote, iclass 37, count 0 2006.210.07:34:40.17#ibcon#about to read 3, iclass 37, count 0 2006.210.07:34:40.21#ibcon#read 3, iclass 37, count 0 2006.210.07:34:40.21#ibcon#about to read 4, iclass 37, count 0 2006.210.07:34:40.21#ibcon#read 4, iclass 37, count 0 2006.210.07:34:40.21#ibcon#about to read 5, iclass 37, count 0 2006.210.07:34:40.21#ibcon#read 5, iclass 37, count 0 2006.210.07:34:40.21#ibcon#about to read 6, iclass 37, count 0 2006.210.07:34:40.21#ibcon#read 6, iclass 37, count 0 2006.210.07:34:40.21#ibcon#end of sib2, iclass 37, count 0 2006.210.07:34:40.21#ibcon#*after write, iclass 37, count 0 2006.210.07:34:40.21#ibcon#*before return 0, iclass 37, count 0 2006.210.07:34:40.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:40.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:34:40.21#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:34:40.21#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:34:40.21$vc4f8/vb=1,4 2006.210.07:34:40.21#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:34:40.21#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:34:40.21#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:40.21#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:40.21#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:40.21#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:40.21#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:34:40.21#ibcon#first serial, iclass 39, count 2 2006.210.07:34:40.21#ibcon#enter sib2, iclass 39, count 2 2006.210.07:34:40.21#ibcon#flushed, iclass 39, count 2 2006.210.07:34:40.21#ibcon#about to write, iclass 39, count 2 2006.210.07:34:40.21#ibcon#wrote, iclass 39, count 2 2006.210.07:34:40.21#ibcon#about to read 3, iclass 39, count 2 2006.210.07:34:40.23#ibcon#read 3, iclass 39, count 2 2006.210.07:34:40.23#ibcon#about to read 4, iclass 39, count 2 2006.210.07:34:40.23#ibcon#read 4, iclass 39, count 2 2006.210.07:34:40.23#ibcon#about to read 5, iclass 39, count 2 2006.210.07:34:40.23#ibcon#read 5, iclass 39, count 2 2006.210.07:34:40.23#ibcon#about to read 6, iclass 39, count 2 2006.210.07:34:40.23#ibcon#read 6, iclass 39, count 2 2006.210.07:34:40.23#ibcon#end of sib2, iclass 39, count 2 2006.210.07:34:40.23#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:34:40.23#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:34:40.23#ibcon#[27=AT01-04\r\n] 2006.210.07:34:40.23#ibcon#*before write, iclass 39, count 2 2006.210.07:34:40.23#ibcon#enter sib2, iclass 39, count 2 2006.210.07:34:40.23#ibcon#flushed, iclass 39, count 2 2006.210.07:34:40.23#ibcon#about to write, iclass 39, count 2 2006.210.07:34:40.23#ibcon#wrote, iclass 39, count 2 2006.210.07:34:40.23#ibcon#about to read 3, iclass 39, count 2 2006.210.07:34:40.26#ibcon#read 3, iclass 39, count 2 2006.210.07:34:40.26#ibcon#about to read 4, iclass 39, count 2 2006.210.07:34:40.26#ibcon#read 4, iclass 39, count 2 2006.210.07:34:40.26#ibcon#about to read 5, iclass 39, count 2 2006.210.07:34:40.26#ibcon#read 5, iclass 39, count 2 2006.210.07:34:40.26#ibcon#about to read 6, iclass 39, count 2 2006.210.07:34:40.26#ibcon#read 6, iclass 39, count 2 2006.210.07:34:40.26#ibcon#end of sib2, iclass 39, count 2 2006.210.07:34:40.26#ibcon#*after write, iclass 39, count 2 2006.210.07:34:40.26#ibcon#*before return 0, iclass 39, count 2 2006.210.07:34:40.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:40.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:34:40.26#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:34:40.26#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:40.26#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:40.38#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:40.38#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:40.38#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:34:40.38#ibcon#first serial, iclass 39, count 0 2006.210.07:34:40.38#ibcon#enter sib2, iclass 39, count 0 2006.210.07:34:40.38#ibcon#flushed, iclass 39, count 0 2006.210.07:34:40.38#ibcon#about to write, iclass 39, count 0 2006.210.07:34:40.38#ibcon#wrote, iclass 39, count 0 2006.210.07:34:40.38#ibcon#about to read 3, iclass 39, count 0 2006.210.07:34:40.40#ibcon#read 3, iclass 39, count 0 2006.210.07:34:40.40#ibcon#about to read 4, iclass 39, count 0 2006.210.07:34:40.40#ibcon#read 4, iclass 39, count 0 2006.210.07:34:40.40#ibcon#about to read 5, iclass 39, count 0 2006.210.07:34:40.40#ibcon#read 5, iclass 39, count 0 2006.210.07:34:40.40#ibcon#about to read 6, iclass 39, count 0 2006.210.07:34:40.40#ibcon#read 6, iclass 39, count 0 2006.210.07:34:40.40#ibcon#end of sib2, iclass 39, count 0 2006.210.07:34:40.40#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:34:40.40#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:34:40.40#ibcon#[27=USB\r\n] 2006.210.07:34:40.40#ibcon#*before write, iclass 39, count 0 2006.210.07:34:40.40#ibcon#enter sib2, iclass 39, count 0 2006.210.07:34:40.40#ibcon#flushed, iclass 39, count 0 2006.210.07:34:40.40#ibcon#about to write, iclass 39, count 0 2006.210.07:34:40.40#ibcon#wrote, iclass 39, count 0 2006.210.07:34:40.40#ibcon#about to read 3, iclass 39, count 0 2006.210.07:34:40.43#ibcon#read 3, iclass 39, count 0 2006.210.07:34:40.43#ibcon#about to read 4, iclass 39, count 0 2006.210.07:34:40.43#ibcon#read 4, iclass 39, count 0 2006.210.07:34:40.43#ibcon#about to read 5, iclass 39, count 0 2006.210.07:34:40.43#ibcon#read 5, iclass 39, count 0 2006.210.07:34:40.43#ibcon#about to read 6, iclass 39, count 0 2006.210.07:34:40.43#ibcon#read 6, iclass 39, count 0 2006.210.07:34:40.43#ibcon#end of sib2, iclass 39, count 0 2006.210.07:34:40.43#ibcon#*after write, iclass 39, count 0 2006.210.07:34:40.43#ibcon#*before return 0, iclass 39, count 0 2006.210.07:34:40.43#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:40.43#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:34:40.43#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:34:40.43#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:34:40.43$vc4f8/vblo=2,640.99 2006.210.07:34:40.43#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:34:40.43#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:34:40.43#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:40.43#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:40.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:40.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:40.43#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:34:40.43#ibcon#first serial, iclass 3, count 0 2006.210.07:34:40.43#ibcon#enter sib2, iclass 3, count 0 2006.210.07:34:40.43#ibcon#flushed, iclass 3, count 0 2006.210.07:34:40.43#ibcon#about to write, iclass 3, count 0 2006.210.07:34:40.43#ibcon#wrote, iclass 3, count 0 2006.210.07:34:40.43#ibcon#about to read 3, iclass 3, count 0 2006.210.07:34:40.45#ibcon#read 3, iclass 3, count 0 2006.210.07:34:40.45#ibcon#about to read 4, iclass 3, count 0 2006.210.07:34:40.45#ibcon#read 4, iclass 3, count 0 2006.210.07:34:40.45#ibcon#about to read 5, iclass 3, count 0 2006.210.07:34:40.45#ibcon#read 5, iclass 3, count 0 2006.210.07:34:40.45#ibcon#about to read 6, iclass 3, count 0 2006.210.07:34:40.45#ibcon#read 6, iclass 3, count 0 2006.210.07:34:40.45#ibcon#end of sib2, iclass 3, count 0 2006.210.07:34:40.45#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:34:40.45#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:34:40.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:34:40.45#ibcon#*before write, iclass 3, count 0 2006.210.07:34:40.45#ibcon#enter sib2, iclass 3, count 0 2006.210.07:34:40.45#ibcon#flushed, iclass 3, count 0 2006.210.07:34:40.45#ibcon#about to write, iclass 3, count 0 2006.210.07:34:40.45#ibcon#wrote, iclass 3, count 0 2006.210.07:34:40.45#ibcon#about to read 3, iclass 3, count 0 2006.210.07:34:40.49#ibcon#read 3, iclass 3, count 0 2006.210.07:34:40.49#ibcon#about to read 4, iclass 3, count 0 2006.210.07:34:40.49#ibcon#read 4, iclass 3, count 0 2006.210.07:34:40.49#ibcon#about to read 5, iclass 3, count 0 2006.210.07:34:40.49#ibcon#read 5, iclass 3, count 0 2006.210.07:34:40.49#ibcon#about to read 6, iclass 3, count 0 2006.210.07:34:40.49#ibcon#read 6, iclass 3, count 0 2006.210.07:34:40.49#ibcon#end of sib2, iclass 3, count 0 2006.210.07:34:40.49#ibcon#*after write, iclass 3, count 0 2006.210.07:34:40.49#ibcon#*before return 0, iclass 3, count 0 2006.210.07:34:40.49#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:40.49#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:34:40.49#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:34:40.49#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:34:40.49$vc4f8/vb=2,4 2006.210.07:34:40.49#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:34:40.49#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:34:40.49#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:40.49#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:40.55#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:40.55#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:40.55#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:34:40.55#ibcon#first serial, iclass 5, count 2 2006.210.07:34:40.55#ibcon#enter sib2, iclass 5, count 2 2006.210.07:34:40.55#ibcon#flushed, iclass 5, count 2 2006.210.07:34:40.55#ibcon#about to write, iclass 5, count 2 2006.210.07:34:40.55#ibcon#wrote, iclass 5, count 2 2006.210.07:34:40.55#ibcon#about to read 3, iclass 5, count 2 2006.210.07:34:40.57#ibcon#read 3, iclass 5, count 2 2006.210.07:34:40.57#ibcon#about to read 4, iclass 5, count 2 2006.210.07:34:40.57#ibcon#read 4, iclass 5, count 2 2006.210.07:34:40.57#ibcon#about to read 5, iclass 5, count 2 2006.210.07:34:40.57#ibcon#read 5, iclass 5, count 2 2006.210.07:34:40.57#ibcon#about to read 6, iclass 5, count 2 2006.210.07:34:40.57#ibcon#read 6, iclass 5, count 2 2006.210.07:34:40.57#ibcon#end of sib2, iclass 5, count 2 2006.210.07:34:40.57#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:34:40.57#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:34:40.57#ibcon#[27=AT02-04\r\n] 2006.210.07:34:40.57#ibcon#*before write, iclass 5, count 2 2006.210.07:34:40.57#ibcon#enter sib2, iclass 5, count 2 2006.210.07:34:40.57#ibcon#flushed, iclass 5, count 2 2006.210.07:34:40.57#ibcon#about to write, iclass 5, count 2 2006.210.07:34:40.57#ibcon#wrote, iclass 5, count 2 2006.210.07:34:40.57#ibcon#about to read 3, iclass 5, count 2 2006.210.07:34:40.60#ibcon#read 3, iclass 5, count 2 2006.210.07:34:40.60#ibcon#about to read 4, iclass 5, count 2 2006.210.07:34:40.60#ibcon#read 4, iclass 5, count 2 2006.210.07:34:40.60#ibcon#about to read 5, iclass 5, count 2 2006.210.07:34:40.60#ibcon#read 5, iclass 5, count 2 2006.210.07:34:40.60#ibcon#about to read 6, iclass 5, count 2 2006.210.07:34:40.60#ibcon#read 6, iclass 5, count 2 2006.210.07:34:40.60#ibcon#end of sib2, iclass 5, count 2 2006.210.07:34:40.60#ibcon#*after write, iclass 5, count 2 2006.210.07:34:40.60#ibcon#*before return 0, iclass 5, count 2 2006.210.07:34:40.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:40.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:34:40.60#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:34:40.60#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:40.60#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:40.72#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:40.72#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:40.72#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:34:40.72#ibcon#first serial, iclass 5, count 0 2006.210.07:34:40.72#ibcon#enter sib2, iclass 5, count 0 2006.210.07:34:40.72#ibcon#flushed, iclass 5, count 0 2006.210.07:34:40.72#ibcon#about to write, iclass 5, count 0 2006.210.07:34:40.72#ibcon#wrote, iclass 5, count 0 2006.210.07:34:40.72#ibcon#about to read 3, iclass 5, count 0 2006.210.07:34:40.74#ibcon#read 3, iclass 5, count 0 2006.210.07:34:40.74#ibcon#about to read 4, iclass 5, count 0 2006.210.07:34:40.74#ibcon#read 4, iclass 5, count 0 2006.210.07:34:40.74#ibcon#about to read 5, iclass 5, count 0 2006.210.07:34:40.74#ibcon#read 5, iclass 5, count 0 2006.210.07:34:40.74#ibcon#about to read 6, iclass 5, count 0 2006.210.07:34:40.74#ibcon#read 6, iclass 5, count 0 2006.210.07:34:40.74#ibcon#end of sib2, iclass 5, count 0 2006.210.07:34:40.74#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:34:40.74#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:34:40.74#ibcon#[27=USB\r\n] 2006.210.07:34:40.74#ibcon#*before write, iclass 5, count 0 2006.210.07:34:40.74#ibcon#enter sib2, iclass 5, count 0 2006.210.07:34:40.74#ibcon#flushed, iclass 5, count 0 2006.210.07:34:40.74#ibcon#about to write, iclass 5, count 0 2006.210.07:34:40.74#ibcon#wrote, iclass 5, count 0 2006.210.07:34:40.74#ibcon#about to read 3, iclass 5, count 0 2006.210.07:34:40.77#ibcon#read 3, iclass 5, count 0 2006.210.07:34:40.77#ibcon#about to read 4, iclass 5, count 0 2006.210.07:34:40.77#ibcon#read 4, iclass 5, count 0 2006.210.07:34:40.77#ibcon#about to read 5, iclass 5, count 0 2006.210.07:34:40.77#ibcon#read 5, iclass 5, count 0 2006.210.07:34:40.77#ibcon#about to read 6, iclass 5, count 0 2006.210.07:34:40.77#ibcon#read 6, iclass 5, count 0 2006.210.07:34:40.77#ibcon#end of sib2, iclass 5, count 0 2006.210.07:34:40.77#ibcon#*after write, iclass 5, count 0 2006.210.07:34:40.77#ibcon#*before return 0, iclass 5, count 0 2006.210.07:34:40.77#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:40.77#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:34:40.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:34:40.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:34:40.77$vc4f8/vblo=3,656.99 2006.210.07:34:40.77#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:34:40.77#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:34:40.77#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:40.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:40.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:40.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:40.77#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:34:40.77#ibcon#first serial, iclass 7, count 0 2006.210.07:34:40.77#ibcon#enter sib2, iclass 7, count 0 2006.210.07:34:40.77#ibcon#flushed, iclass 7, count 0 2006.210.07:34:40.77#ibcon#about to write, iclass 7, count 0 2006.210.07:34:40.77#ibcon#wrote, iclass 7, count 0 2006.210.07:34:40.77#ibcon#about to read 3, iclass 7, count 0 2006.210.07:34:40.79#ibcon#read 3, iclass 7, count 0 2006.210.07:34:40.79#ibcon#about to read 4, iclass 7, count 0 2006.210.07:34:40.79#ibcon#read 4, iclass 7, count 0 2006.210.07:34:40.79#ibcon#about to read 5, iclass 7, count 0 2006.210.07:34:40.79#ibcon#read 5, iclass 7, count 0 2006.210.07:34:40.79#ibcon#about to read 6, iclass 7, count 0 2006.210.07:34:40.79#ibcon#read 6, iclass 7, count 0 2006.210.07:34:40.79#ibcon#end of sib2, iclass 7, count 0 2006.210.07:34:40.79#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:34:40.79#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:34:40.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:34:40.79#ibcon#*before write, iclass 7, count 0 2006.210.07:34:40.79#ibcon#enter sib2, iclass 7, count 0 2006.210.07:34:40.79#ibcon#flushed, iclass 7, count 0 2006.210.07:34:40.79#ibcon#about to write, iclass 7, count 0 2006.210.07:34:40.79#ibcon#wrote, iclass 7, count 0 2006.210.07:34:40.79#ibcon#about to read 3, iclass 7, count 0 2006.210.07:34:40.83#ibcon#read 3, iclass 7, count 0 2006.210.07:34:40.83#ibcon#about to read 4, iclass 7, count 0 2006.210.07:34:40.83#ibcon#read 4, iclass 7, count 0 2006.210.07:34:40.83#ibcon#about to read 5, iclass 7, count 0 2006.210.07:34:40.83#ibcon#read 5, iclass 7, count 0 2006.210.07:34:40.83#ibcon#about to read 6, iclass 7, count 0 2006.210.07:34:40.83#ibcon#read 6, iclass 7, count 0 2006.210.07:34:40.83#ibcon#end of sib2, iclass 7, count 0 2006.210.07:34:40.83#ibcon#*after write, iclass 7, count 0 2006.210.07:34:40.83#ibcon#*before return 0, iclass 7, count 0 2006.210.07:34:40.83#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:40.83#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:34:40.83#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:34:40.83#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:34:40.83$vc4f8/vb=3,3 2006.210.07:34:40.83#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:34:40.83#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:34:40.83#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:40.83#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:40.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:40.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:40.89#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:34:40.89#ibcon#first serial, iclass 11, count 2 2006.210.07:34:40.89#ibcon#enter sib2, iclass 11, count 2 2006.210.07:34:40.89#ibcon#flushed, iclass 11, count 2 2006.210.07:34:40.89#ibcon#about to write, iclass 11, count 2 2006.210.07:34:40.89#ibcon#wrote, iclass 11, count 2 2006.210.07:34:40.89#ibcon#about to read 3, iclass 11, count 2 2006.210.07:34:40.91#ibcon#read 3, iclass 11, count 2 2006.210.07:34:40.91#ibcon#about to read 4, iclass 11, count 2 2006.210.07:34:40.91#ibcon#read 4, iclass 11, count 2 2006.210.07:34:40.91#ibcon#about to read 5, iclass 11, count 2 2006.210.07:34:40.91#ibcon#read 5, iclass 11, count 2 2006.210.07:34:40.91#ibcon#about to read 6, iclass 11, count 2 2006.210.07:34:40.91#ibcon#read 6, iclass 11, count 2 2006.210.07:34:40.91#ibcon#end of sib2, iclass 11, count 2 2006.210.07:34:40.91#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:34:40.91#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:34:40.91#ibcon#[27=AT03-03\r\n] 2006.210.07:34:40.91#ibcon#*before write, iclass 11, count 2 2006.210.07:34:40.91#ibcon#enter sib2, iclass 11, count 2 2006.210.07:34:40.91#ibcon#flushed, iclass 11, count 2 2006.210.07:34:40.91#ibcon#about to write, iclass 11, count 2 2006.210.07:34:40.91#ibcon#wrote, iclass 11, count 2 2006.210.07:34:40.91#ibcon#about to read 3, iclass 11, count 2 2006.210.07:34:40.94#ibcon#read 3, iclass 11, count 2 2006.210.07:34:40.94#ibcon#about to read 4, iclass 11, count 2 2006.210.07:34:40.94#ibcon#read 4, iclass 11, count 2 2006.210.07:34:40.94#ibcon#about to read 5, iclass 11, count 2 2006.210.07:34:40.94#ibcon#read 5, iclass 11, count 2 2006.210.07:34:40.94#ibcon#about to read 6, iclass 11, count 2 2006.210.07:34:40.94#ibcon#read 6, iclass 11, count 2 2006.210.07:34:40.94#ibcon#end of sib2, iclass 11, count 2 2006.210.07:34:40.94#ibcon#*after write, iclass 11, count 2 2006.210.07:34:40.94#ibcon#*before return 0, iclass 11, count 2 2006.210.07:34:40.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:40.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:34:40.94#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:34:40.94#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:40.94#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:41.06#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:41.06#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:41.06#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:34:41.06#ibcon#first serial, iclass 11, count 0 2006.210.07:34:41.06#ibcon#enter sib2, iclass 11, count 0 2006.210.07:34:41.06#ibcon#flushed, iclass 11, count 0 2006.210.07:34:41.06#ibcon#about to write, iclass 11, count 0 2006.210.07:34:41.06#ibcon#wrote, iclass 11, count 0 2006.210.07:34:41.06#ibcon#about to read 3, iclass 11, count 0 2006.210.07:34:41.08#ibcon#read 3, iclass 11, count 0 2006.210.07:34:41.08#ibcon#about to read 4, iclass 11, count 0 2006.210.07:34:41.08#ibcon#read 4, iclass 11, count 0 2006.210.07:34:41.08#ibcon#about to read 5, iclass 11, count 0 2006.210.07:34:41.08#ibcon#read 5, iclass 11, count 0 2006.210.07:34:41.08#ibcon#about to read 6, iclass 11, count 0 2006.210.07:34:41.08#ibcon#read 6, iclass 11, count 0 2006.210.07:34:41.08#ibcon#end of sib2, iclass 11, count 0 2006.210.07:34:41.08#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:34:41.08#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:34:41.08#ibcon#[27=USB\r\n] 2006.210.07:34:41.08#ibcon#*before write, iclass 11, count 0 2006.210.07:34:41.08#ibcon#enter sib2, iclass 11, count 0 2006.210.07:34:41.08#ibcon#flushed, iclass 11, count 0 2006.210.07:34:41.08#ibcon#about to write, iclass 11, count 0 2006.210.07:34:41.08#ibcon#wrote, iclass 11, count 0 2006.210.07:34:41.08#ibcon#about to read 3, iclass 11, count 0 2006.210.07:34:41.11#ibcon#read 3, iclass 11, count 0 2006.210.07:34:41.11#ibcon#about to read 4, iclass 11, count 0 2006.210.07:34:41.11#ibcon#read 4, iclass 11, count 0 2006.210.07:34:41.11#ibcon#about to read 5, iclass 11, count 0 2006.210.07:34:41.11#ibcon#read 5, iclass 11, count 0 2006.210.07:34:41.11#ibcon#about to read 6, iclass 11, count 0 2006.210.07:34:41.11#ibcon#read 6, iclass 11, count 0 2006.210.07:34:41.11#ibcon#end of sib2, iclass 11, count 0 2006.210.07:34:41.11#ibcon#*after write, iclass 11, count 0 2006.210.07:34:41.11#ibcon#*before return 0, iclass 11, count 0 2006.210.07:34:41.11#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:41.11#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:34:41.11#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:34:41.11#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:34:41.11$vc4f8/vblo=4,712.99 2006.210.07:34:41.11#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:34:41.11#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:34:41.11#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:41.11#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:41.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:41.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:41.11#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:34:41.11#ibcon#first serial, iclass 13, count 0 2006.210.07:34:41.11#ibcon#enter sib2, iclass 13, count 0 2006.210.07:34:41.11#ibcon#flushed, iclass 13, count 0 2006.210.07:34:41.11#ibcon#about to write, iclass 13, count 0 2006.210.07:34:41.11#ibcon#wrote, iclass 13, count 0 2006.210.07:34:41.11#ibcon#about to read 3, iclass 13, count 0 2006.210.07:34:41.13#ibcon#read 3, iclass 13, count 0 2006.210.07:34:41.13#ibcon#about to read 4, iclass 13, count 0 2006.210.07:34:41.13#ibcon#read 4, iclass 13, count 0 2006.210.07:34:41.13#ibcon#about to read 5, iclass 13, count 0 2006.210.07:34:41.13#ibcon#read 5, iclass 13, count 0 2006.210.07:34:41.13#ibcon#about to read 6, iclass 13, count 0 2006.210.07:34:41.13#ibcon#read 6, iclass 13, count 0 2006.210.07:34:41.13#ibcon#end of sib2, iclass 13, count 0 2006.210.07:34:41.13#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:34:41.13#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:34:41.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:34:41.13#ibcon#*before write, iclass 13, count 0 2006.210.07:34:41.13#ibcon#enter sib2, iclass 13, count 0 2006.210.07:34:41.13#ibcon#flushed, iclass 13, count 0 2006.210.07:34:41.13#ibcon#about to write, iclass 13, count 0 2006.210.07:34:41.13#ibcon#wrote, iclass 13, count 0 2006.210.07:34:41.13#ibcon#about to read 3, iclass 13, count 0 2006.210.07:34:41.17#ibcon#read 3, iclass 13, count 0 2006.210.07:34:41.17#ibcon#about to read 4, iclass 13, count 0 2006.210.07:34:41.17#ibcon#read 4, iclass 13, count 0 2006.210.07:34:41.17#ibcon#about to read 5, iclass 13, count 0 2006.210.07:34:41.17#ibcon#read 5, iclass 13, count 0 2006.210.07:34:41.17#ibcon#about to read 6, iclass 13, count 0 2006.210.07:34:41.17#ibcon#read 6, iclass 13, count 0 2006.210.07:34:41.17#ibcon#end of sib2, iclass 13, count 0 2006.210.07:34:41.17#ibcon#*after write, iclass 13, count 0 2006.210.07:34:41.17#ibcon#*before return 0, iclass 13, count 0 2006.210.07:34:41.17#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:41.17#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:34:41.17#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:34:41.17#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:34:41.17$vc4f8/vb=4,3 2006.210.07:34:41.17#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:34:41.17#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:34:41.17#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:41.17#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:41.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:41.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:41.23#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:34:41.23#ibcon#first serial, iclass 15, count 2 2006.210.07:34:41.23#ibcon#enter sib2, iclass 15, count 2 2006.210.07:34:41.23#ibcon#flushed, iclass 15, count 2 2006.210.07:34:41.23#ibcon#about to write, iclass 15, count 2 2006.210.07:34:41.23#ibcon#wrote, iclass 15, count 2 2006.210.07:34:41.23#ibcon#about to read 3, iclass 15, count 2 2006.210.07:34:41.25#ibcon#read 3, iclass 15, count 2 2006.210.07:34:41.25#ibcon#about to read 4, iclass 15, count 2 2006.210.07:34:41.25#ibcon#read 4, iclass 15, count 2 2006.210.07:34:41.25#ibcon#about to read 5, iclass 15, count 2 2006.210.07:34:41.25#ibcon#read 5, iclass 15, count 2 2006.210.07:34:41.25#ibcon#about to read 6, iclass 15, count 2 2006.210.07:34:41.25#ibcon#read 6, iclass 15, count 2 2006.210.07:34:41.25#ibcon#end of sib2, iclass 15, count 2 2006.210.07:34:41.25#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:34:41.25#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:34:41.25#ibcon#[27=AT04-03\r\n] 2006.210.07:34:41.25#ibcon#*before write, iclass 15, count 2 2006.210.07:34:41.25#ibcon#enter sib2, iclass 15, count 2 2006.210.07:34:41.25#ibcon#flushed, iclass 15, count 2 2006.210.07:34:41.25#ibcon#about to write, iclass 15, count 2 2006.210.07:34:41.25#ibcon#wrote, iclass 15, count 2 2006.210.07:34:41.25#ibcon#about to read 3, iclass 15, count 2 2006.210.07:34:41.28#ibcon#read 3, iclass 15, count 2 2006.210.07:34:41.28#ibcon#about to read 4, iclass 15, count 2 2006.210.07:34:41.28#ibcon#read 4, iclass 15, count 2 2006.210.07:34:41.28#ibcon#about to read 5, iclass 15, count 2 2006.210.07:34:41.28#ibcon#read 5, iclass 15, count 2 2006.210.07:34:41.28#ibcon#about to read 6, iclass 15, count 2 2006.210.07:34:41.28#ibcon#read 6, iclass 15, count 2 2006.210.07:34:41.28#ibcon#end of sib2, iclass 15, count 2 2006.210.07:34:41.28#ibcon#*after write, iclass 15, count 2 2006.210.07:34:41.28#ibcon#*before return 0, iclass 15, count 2 2006.210.07:34:41.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:41.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:34:41.28#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:34:41.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:41.28#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:41.40#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:41.40#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:41.40#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:34:41.40#ibcon#first serial, iclass 15, count 0 2006.210.07:34:41.40#ibcon#enter sib2, iclass 15, count 0 2006.210.07:34:41.40#ibcon#flushed, iclass 15, count 0 2006.210.07:34:41.40#ibcon#about to write, iclass 15, count 0 2006.210.07:34:41.40#ibcon#wrote, iclass 15, count 0 2006.210.07:34:41.40#ibcon#about to read 3, iclass 15, count 0 2006.210.07:34:41.42#ibcon#read 3, iclass 15, count 0 2006.210.07:34:41.42#ibcon#about to read 4, iclass 15, count 0 2006.210.07:34:41.42#ibcon#read 4, iclass 15, count 0 2006.210.07:34:41.42#ibcon#about to read 5, iclass 15, count 0 2006.210.07:34:41.42#ibcon#read 5, iclass 15, count 0 2006.210.07:34:41.42#ibcon#about to read 6, iclass 15, count 0 2006.210.07:34:41.42#ibcon#read 6, iclass 15, count 0 2006.210.07:34:41.42#ibcon#end of sib2, iclass 15, count 0 2006.210.07:34:41.42#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:34:41.42#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:34:41.42#ibcon#[27=USB\r\n] 2006.210.07:34:41.42#ibcon#*before write, iclass 15, count 0 2006.210.07:34:41.42#ibcon#enter sib2, iclass 15, count 0 2006.210.07:34:41.42#ibcon#flushed, iclass 15, count 0 2006.210.07:34:41.42#ibcon#about to write, iclass 15, count 0 2006.210.07:34:41.42#ibcon#wrote, iclass 15, count 0 2006.210.07:34:41.42#ibcon#about to read 3, iclass 15, count 0 2006.210.07:34:41.45#ibcon#read 3, iclass 15, count 0 2006.210.07:34:41.45#ibcon#about to read 4, iclass 15, count 0 2006.210.07:34:41.45#ibcon#read 4, iclass 15, count 0 2006.210.07:34:41.45#ibcon#about to read 5, iclass 15, count 0 2006.210.07:34:41.45#ibcon#read 5, iclass 15, count 0 2006.210.07:34:41.45#ibcon#about to read 6, iclass 15, count 0 2006.210.07:34:41.45#ibcon#read 6, iclass 15, count 0 2006.210.07:34:41.45#ibcon#end of sib2, iclass 15, count 0 2006.210.07:34:41.45#ibcon#*after write, iclass 15, count 0 2006.210.07:34:41.45#ibcon#*before return 0, iclass 15, count 0 2006.210.07:34:41.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:41.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:34:41.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:34:41.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:34:41.45$vc4f8/vblo=5,744.99 2006.210.07:34:41.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:34:41.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:34:41.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:41.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:41.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:41.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:41.45#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:34:41.45#ibcon#first serial, iclass 17, count 0 2006.210.07:34:41.45#ibcon#enter sib2, iclass 17, count 0 2006.210.07:34:41.45#ibcon#flushed, iclass 17, count 0 2006.210.07:34:41.45#ibcon#about to write, iclass 17, count 0 2006.210.07:34:41.45#ibcon#wrote, iclass 17, count 0 2006.210.07:34:41.45#ibcon#about to read 3, iclass 17, count 0 2006.210.07:34:41.47#ibcon#read 3, iclass 17, count 0 2006.210.07:34:41.47#ibcon#about to read 4, iclass 17, count 0 2006.210.07:34:41.47#ibcon#read 4, iclass 17, count 0 2006.210.07:34:41.47#ibcon#about to read 5, iclass 17, count 0 2006.210.07:34:41.47#ibcon#read 5, iclass 17, count 0 2006.210.07:34:41.47#ibcon#about to read 6, iclass 17, count 0 2006.210.07:34:41.47#ibcon#read 6, iclass 17, count 0 2006.210.07:34:41.47#ibcon#end of sib2, iclass 17, count 0 2006.210.07:34:41.47#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:34:41.47#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:34:41.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:34:41.47#ibcon#*before write, iclass 17, count 0 2006.210.07:34:41.47#ibcon#enter sib2, iclass 17, count 0 2006.210.07:34:41.47#ibcon#flushed, iclass 17, count 0 2006.210.07:34:41.47#ibcon#about to write, iclass 17, count 0 2006.210.07:34:41.47#ibcon#wrote, iclass 17, count 0 2006.210.07:34:41.47#ibcon#about to read 3, iclass 17, count 0 2006.210.07:34:41.51#ibcon#read 3, iclass 17, count 0 2006.210.07:34:41.51#ibcon#about to read 4, iclass 17, count 0 2006.210.07:34:41.51#ibcon#read 4, iclass 17, count 0 2006.210.07:34:41.51#ibcon#about to read 5, iclass 17, count 0 2006.210.07:34:41.51#ibcon#read 5, iclass 17, count 0 2006.210.07:34:41.51#ibcon#about to read 6, iclass 17, count 0 2006.210.07:34:41.51#ibcon#read 6, iclass 17, count 0 2006.210.07:34:41.51#ibcon#end of sib2, iclass 17, count 0 2006.210.07:34:41.51#ibcon#*after write, iclass 17, count 0 2006.210.07:34:41.51#ibcon#*before return 0, iclass 17, count 0 2006.210.07:34:41.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:41.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:34:41.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:34:41.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:34:41.51$vc4f8/vb=5,3 2006.210.07:34:41.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:34:41.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:34:41.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:41.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:41.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:41.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:41.57#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:34:41.57#ibcon#first serial, iclass 19, count 2 2006.210.07:34:41.57#ibcon#enter sib2, iclass 19, count 2 2006.210.07:34:41.57#ibcon#flushed, iclass 19, count 2 2006.210.07:34:41.57#ibcon#about to write, iclass 19, count 2 2006.210.07:34:41.57#ibcon#wrote, iclass 19, count 2 2006.210.07:34:41.57#ibcon#about to read 3, iclass 19, count 2 2006.210.07:34:41.59#ibcon#read 3, iclass 19, count 2 2006.210.07:34:41.59#ibcon#about to read 4, iclass 19, count 2 2006.210.07:34:41.59#ibcon#read 4, iclass 19, count 2 2006.210.07:34:41.59#ibcon#about to read 5, iclass 19, count 2 2006.210.07:34:41.59#ibcon#read 5, iclass 19, count 2 2006.210.07:34:41.59#ibcon#about to read 6, iclass 19, count 2 2006.210.07:34:41.59#ibcon#read 6, iclass 19, count 2 2006.210.07:34:41.59#ibcon#end of sib2, iclass 19, count 2 2006.210.07:34:41.59#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:34:41.59#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:34:41.59#ibcon#[27=AT05-03\r\n] 2006.210.07:34:41.59#ibcon#*before write, iclass 19, count 2 2006.210.07:34:41.59#ibcon#enter sib2, iclass 19, count 2 2006.210.07:34:41.59#ibcon#flushed, iclass 19, count 2 2006.210.07:34:41.59#ibcon#about to write, iclass 19, count 2 2006.210.07:34:41.59#ibcon#wrote, iclass 19, count 2 2006.210.07:34:41.59#ibcon#about to read 3, iclass 19, count 2 2006.210.07:34:41.62#ibcon#read 3, iclass 19, count 2 2006.210.07:34:41.62#ibcon#about to read 4, iclass 19, count 2 2006.210.07:34:41.62#ibcon#read 4, iclass 19, count 2 2006.210.07:34:41.62#ibcon#about to read 5, iclass 19, count 2 2006.210.07:34:41.62#ibcon#read 5, iclass 19, count 2 2006.210.07:34:41.62#ibcon#about to read 6, iclass 19, count 2 2006.210.07:34:41.62#ibcon#read 6, iclass 19, count 2 2006.210.07:34:41.62#ibcon#end of sib2, iclass 19, count 2 2006.210.07:34:41.62#ibcon#*after write, iclass 19, count 2 2006.210.07:34:41.62#ibcon#*before return 0, iclass 19, count 2 2006.210.07:34:41.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:41.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:34:41.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:34:41.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:41.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:41.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:41.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:41.74#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:34:41.74#ibcon#first serial, iclass 19, count 0 2006.210.07:34:41.74#ibcon#enter sib2, iclass 19, count 0 2006.210.07:34:41.74#ibcon#flushed, iclass 19, count 0 2006.210.07:34:41.74#ibcon#about to write, iclass 19, count 0 2006.210.07:34:41.74#ibcon#wrote, iclass 19, count 0 2006.210.07:34:41.74#ibcon#about to read 3, iclass 19, count 0 2006.210.07:34:41.76#ibcon#read 3, iclass 19, count 0 2006.210.07:34:41.76#ibcon#about to read 4, iclass 19, count 0 2006.210.07:34:41.76#ibcon#read 4, iclass 19, count 0 2006.210.07:34:41.76#ibcon#about to read 5, iclass 19, count 0 2006.210.07:34:41.76#ibcon#read 5, iclass 19, count 0 2006.210.07:34:41.76#ibcon#about to read 6, iclass 19, count 0 2006.210.07:34:41.76#ibcon#read 6, iclass 19, count 0 2006.210.07:34:41.76#ibcon#end of sib2, iclass 19, count 0 2006.210.07:34:41.76#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:34:41.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:34:41.76#ibcon#[27=USB\r\n] 2006.210.07:34:41.76#ibcon#*before write, iclass 19, count 0 2006.210.07:34:41.76#ibcon#enter sib2, iclass 19, count 0 2006.210.07:34:41.76#ibcon#flushed, iclass 19, count 0 2006.210.07:34:41.76#ibcon#about to write, iclass 19, count 0 2006.210.07:34:41.76#ibcon#wrote, iclass 19, count 0 2006.210.07:34:41.76#ibcon#about to read 3, iclass 19, count 0 2006.210.07:34:41.79#ibcon#read 3, iclass 19, count 0 2006.210.07:34:41.79#ibcon#about to read 4, iclass 19, count 0 2006.210.07:34:41.79#ibcon#read 4, iclass 19, count 0 2006.210.07:34:41.79#ibcon#about to read 5, iclass 19, count 0 2006.210.07:34:41.79#ibcon#read 5, iclass 19, count 0 2006.210.07:34:41.79#ibcon#about to read 6, iclass 19, count 0 2006.210.07:34:41.79#ibcon#read 6, iclass 19, count 0 2006.210.07:34:41.79#ibcon#end of sib2, iclass 19, count 0 2006.210.07:34:41.79#ibcon#*after write, iclass 19, count 0 2006.210.07:34:41.79#ibcon#*before return 0, iclass 19, count 0 2006.210.07:34:41.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:41.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:34:41.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:34:41.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:34:41.79$vc4f8/vblo=6,752.99 2006.210.07:34:41.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:34:41.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:34:41.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:34:41.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:41.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:41.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:41.79#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:34:41.79#ibcon#first serial, iclass 21, count 0 2006.210.07:34:41.79#ibcon#enter sib2, iclass 21, count 0 2006.210.07:34:41.79#ibcon#flushed, iclass 21, count 0 2006.210.07:34:41.79#ibcon#about to write, iclass 21, count 0 2006.210.07:34:41.79#ibcon#wrote, iclass 21, count 0 2006.210.07:34:41.79#ibcon#about to read 3, iclass 21, count 0 2006.210.07:34:41.81#ibcon#read 3, iclass 21, count 0 2006.210.07:34:41.81#ibcon#about to read 4, iclass 21, count 0 2006.210.07:34:41.81#ibcon#read 4, iclass 21, count 0 2006.210.07:34:41.81#ibcon#about to read 5, iclass 21, count 0 2006.210.07:34:41.81#ibcon#read 5, iclass 21, count 0 2006.210.07:34:41.81#ibcon#about to read 6, iclass 21, count 0 2006.210.07:34:41.81#ibcon#read 6, iclass 21, count 0 2006.210.07:34:41.81#ibcon#end of sib2, iclass 21, count 0 2006.210.07:34:41.81#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:34:41.81#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:34:41.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:34:41.81#ibcon#*before write, iclass 21, count 0 2006.210.07:34:41.81#ibcon#enter sib2, iclass 21, count 0 2006.210.07:34:41.81#ibcon#flushed, iclass 21, count 0 2006.210.07:34:41.81#ibcon#about to write, iclass 21, count 0 2006.210.07:34:41.81#ibcon#wrote, iclass 21, count 0 2006.210.07:34:41.81#ibcon#about to read 3, iclass 21, count 0 2006.210.07:34:41.85#ibcon#read 3, iclass 21, count 0 2006.210.07:34:41.85#ibcon#about to read 4, iclass 21, count 0 2006.210.07:34:41.85#ibcon#read 4, iclass 21, count 0 2006.210.07:34:41.85#ibcon#about to read 5, iclass 21, count 0 2006.210.07:34:41.85#ibcon#read 5, iclass 21, count 0 2006.210.07:34:41.85#ibcon#about to read 6, iclass 21, count 0 2006.210.07:34:41.85#ibcon#read 6, iclass 21, count 0 2006.210.07:34:41.85#ibcon#end of sib2, iclass 21, count 0 2006.210.07:34:41.85#ibcon#*after write, iclass 21, count 0 2006.210.07:34:41.85#ibcon#*before return 0, iclass 21, count 0 2006.210.07:34:41.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:41.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:34:41.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:34:41.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:34:41.85$vc4f8/vb=6,3 2006.210.07:34:41.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.07:34:41.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.07:34:41.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:34:41.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:41.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:41.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:41.91#ibcon#enter wrdev, iclass 23, count 2 2006.210.07:34:41.91#ibcon#first serial, iclass 23, count 2 2006.210.07:34:41.91#ibcon#enter sib2, iclass 23, count 2 2006.210.07:34:41.91#ibcon#flushed, iclass 23, count 2 2006.210.07:34:41.91#ibcon#about to write, iclass 23, count 2 2006.210.07:34:41.91#ibcon#wrote, iclass 23, count 2 2006.210.07:34:41.91#ibcon#about to read 3, iclass 23, count 2 2006.210.07:34:41.93#ibcon#read 3, iclass 23, count 2 2006.210.07:34:41.93#ibcon#about to read 4, iclass 23, count 2 2006.210.07:34:41.93#ibcon#read 4, iclass 23, count 2 2006.210.07:34:41.93#ibcon#about to read 5, iclass 23, count 2 2006.210.07:34:41.93#ibcon#read 5, iclass 23, count 2 2006.210.07:34:41.93#ibcon#about to read 6, iclass 23, count 2 2006.210.07:34:41.93#ibcon#read 6, iclass 23, count 2 2006.210.07:34:41.93#ibcon#end of sib2, iclass 23, count 2 2006.210.07:34:41.93#ibcon#*mode == 0, iclass 23, count 2 2006.210.07:34:41.93#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.07:34:41.93#ibcon#[27=AT06-03\r\n] 2006.210.07:34:41.93#ibcon#*before write, iclass 23, count 2 2006.210.07:34:41.93#ibcon#enter sib2, iclass 23, count 2 2006.210.07:34:41.93#ibcon#flushed, iclass 23, count 2 2006.210.07:34:41.93#ibcon#about to write, iclass 23, count 2 2006.210.07:34:41.93#ibcon#wrote, iclass 23, count 2 2006.210.07:34:41.93#ibcon#about to read 3, iclass 23, count 2 2006.210.07:34:41.96#ibcon#read 3, iclass 23, count 2 2006.210.07:34:41.96#ibcon#about to read 4, iclass 23, count 2 2006.210.07:34:41.96#ibcon#read 4, iclass 23, count 2 2006.210.07:34:41.96#ibcon#about to read 5, iclass 23, count 2 2006.210.07:34:41.96#ibcon#read 5, iclass 23, count 2 2006.210.07:34:41.96#ibcon#about to read 6, iclass 23, count 2 2006.210.07:34:41.96#ibcon#read 6, iclass 23, count 2 2006.210.07:34:41.96#ibcon#end of sib2, iclass 23, count 2 2006.210.07:34:41.96#ibcon#*after write, iclass 23, count 2 2006.210.07:34:41.96#ibcon#*before return 0, iclass 23, count 2 2006.210.07:34:41.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:41.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:34:41.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.07:34:41.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:34:41.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:42.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:42.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:42.08#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:34:42.08#ibcon#first serial, iclass 23, count 0 2006.210.07:34:42.08#ibcon#enter sib2, iclass 23, count 0 2006.210.07:34:42.08#ibcon#flushed, iclass 23, count 0 2006.210.07:34:42.08#ibcon#about to write, iclass 23, count 0 2006.210.07:34:42.08#ibcon#wrote, iclass 23, count 0 2006.210.07:34:42.08#ibcon#about to read 3, iclass 23, count 0 2006.210.07:34:42.10#ibcon#read 3, iclass 23, count 0 2006.210.07:34:42.10#ibcon#about to read 4, iclass 23, count 0 2006.210.07:34:42.10#ibcon#read 4, iclass 23, count 0 2006.210.07:34:42.10#ibcon#about to read 5, iclass 23, count 0 2006.210.07:34:42.10#ibcon#read 5, iclass 23, count 0 2006.210.07:34:42.10#ibcon#about to read 6, iclass 23, count 0 2006.210.07:34:42.10#ibcon#read 6, iclass 23, count 0 2006.210.07:34:42.10#ibcon#end of sib2, iclass 23, count 0 2006.210.07:34:42.10#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:34:42.10#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:34:42.10#ibcon#[27=USB\r\n] 2006.210.07:34:42.10#ibcon#*before write, iclass 23, count 0 2006.210.07:34:42.10#ibcon#enter sib2, iclass 23, count 0 2006.210.07:34:42.10#ibcon#flushed, iclass 23, count 0 2006.210.07:34:42.10#ibcon#about to write, iclass 23, count 0 2006.210.07:34:42.10#ibcon#wrote, iclass 23, count 0 2006.210.07:34:42.10#ibcon#about to read 3, iclass 23, count 0 2006.210.07:34:42.13#ibcon#read 3, iclass 23, count 0 2006.210.07:34:42.13#ibcon#about to read 4, iclass 23, count 0 2006.210.07:34:42.13#ibcon#read 4, iclass 23, count 0 2006.210.07:34:42.13#ibcon#about to read 5, iclass 23, count 0 2006.210.07:34:42.13#ibcon#read 5, iclass 23, count 0 2006.210.07:34:42.13#ibcon#about to read 6, iclass 23, count 0 2006.210.07:34:42.13#ibcon#read 6, iclass 23, count 0 2006.210.07:34:42.13#ibcon#end of sib2, iclass 23, count 0 2006.210.07:34:42.13#ibcon#*after write, iclass 23, count 0 2006.210.07:34:42.13#ibcon#*before return 0, iclass 23, count 0 2006.210.07:34:42.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:42.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:34:42.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:34:42.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:34:42.13$vc4f8/vabw=wide 2006.210.07:34:42.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.07:34:42.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.07:34:42.13#ibcon#ireg 8 cls_cnt 0 2006.210.07:34:42.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:42.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:42.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:42.13#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:34:42.13#ibcon#first serial, iclass 25, count 0 2006.210.07:34:42.13#ibcon#enter sib2, iclass 25, count 0 2006.210.07:34:42.13#ibcon#flushed, iclass 25, count 0 2006.210.07:34:42.13#ibcon#about to write, iclass 25, count 0 2006.210.07:34:42.13#ibcon#wrote, iclass 25, count 0 2006.210.07:34:42.13#ibcon#about to read 3, iclass 25, count 0 2006.210.07:34:42.15#ibcon#read 3, iclass 25, count 0 2006.210.07:34:42.15#ibcon#about to read 4, iclass 25, count 0 2006.210.07:34:42.15#ibcon#read 4, iclass 25, count 0 2006.210.07:34:42.15#ibcon#about to read 5, iclass 25, count 0 2006.210.07:34:42.15#ibcon#read 5, iclass 25, count 0 2006.210.07:34:42.15#ibcon#about to read 6, iclass 25, count 0 2006.210.07:34:42.15#ibcon#read 6, iclass 25, count 0 2006.210.07:34:42.15#ibcon#end of sib2, iclass 25, count 0 2006.210.07:34:42.15#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:34:42.15#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:34:42.15#ibcon#[25=BW32\r\n] 2006.210.07:34:42.15#ibcon#*before write, iclass 25, count 0 2006.210.07:34:42.15#ibcon#enter sib2, iclass 25, count 0 2006.210.07:34:42.15#ibcon#flushed, iclass 25, count 0 2006.210.07:34:42.15#ibcon#about to write, iclass 25, count 0 2006.210.07:34:42.15#ibcon#wrote, iclass 25, count 0 2006.210.07:34:42.15#ibcon#about to read 3, iclass 25, count 0 2006.210.07:34:42.18#ibcon#read 3, iclass 25, count 0 2006.210.07:34:42.18#ibcon#about to read 4, iclass 25, count 0 2006.210.07:34:42.18#ibcon#read 4, iclass 25, count 0 2006.210.07:34:42.18#ibcon#about to read 5, iclass 25, count 0 2006.210.07:34:42.18#ibcon#read 5, iclass 25, count 0 2006.210.07:34:42.18#ibcon#about to read 6, iclass 25, count 0 2006.210.07:34:42.18#ibcon#read 6, iclass 25, count 0 2006.210.07:34:42.18#ibcon#end of sib2, iclass 25, count 0 2006.210.07:34:42.18#ibcon#*after write, iclass 25, count 0 2006.210.07:34:42.18#ibcon#*before return 0, iclass 25, count 0 2006.210.07:34:42.18#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:42.18#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:34:42.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:34:42.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:34:42.18$vc4f8/vbbw=wide 2006.210.07:34:42.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.07:34:42.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.07:34:42.18#ibcon#ireg 8 cls_cnt 0 2006.210.07:34:42.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:34:42.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:34:42.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:34:42.25#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:34:42.25#ibcon#first serial, iclass 27, count 0 2006.210.07:34:42.25#ibcon#enter sib2, iclass 27, count 0 2006.210.07:34:42.25#ibcon#flushed, iclass 27, count 0 2006.210.07:34:42.25#ibcon#about to write, iclass 27, count 0 2006.210.07:34:42.25#ibcon#wrote, iclass 27, count 0 2006.210.07:34:42.25#ibcon#about to read 3, iclass 27, count 0 2006.210.07:34:42.27#ibcon#read 3, iclass 27, count 0 2006.210.07:34:42.27#ibcon#about to read 4, iclass 27, count 0 2006.210.07:34:42.27#ibcon#read 4, iclass 27, count 0 2006.210.07:34:42.27#ibcon#about to read 5, iclass 27, count 0 2006.210.07:34:42.27#ibcon#read 5, iclass 27, count 0 2006.210.07:34:42.27#ibcon#about to read 6, iclass 27, count 0 2006.210.07:34:42.27#ibcon#read 6, iclass 27, count 0 2006.210.07:34:42.27#ibcon#end of sib2, iclass 27, count 0 2006.210.07:34:42.27#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:34:42.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:34:42.27#ibcon#[27=BW32\r\n] 2006.210.07:34:42.27#ibcon#*before write, iclass 27, count 0 2006.210.07:34:42.27#ibcon#enter sib2, iclass 27, count 0 2006.210.07:34:42.27#ibcon#flushed, iclass 27, count 0 2006.210.07:34:42.27#ibcon#about to write, iclass 27, count 0 2006.210.07:34:42.27#ibcon#wrote, iclass 27, count 0 2006.210.07:34:42.27#ibcon#about to read 3, iclass 27, count 0 2006.210.07:34:42.30#ibcon#read 3, iclass 27, count 0 2006.210.07:34:42.30#ibcon#about to read 4, iclass 27, count 0 2006.210.07:34:42.30#ibcon#read 4, iclass 27, count 0 2006.210.07:34:42.30#ibcon#about to read 5, iclass 27, count 0 2006.210.07:34:42.30#ibcon#read 5, iclass 27, count 0 2006.210.07:34:42.30#ibcon#about to read 6, iclass 27, count 0 2006.210.07:34:42.30#ibcon#read 6, iclass 27, count 0 2006.210.07:34:42.30#ibcon#end of sib2, iclass 27, count 0 2006.210.07:34:42.30#ibcon#*after write, iclass 27, count 0 2006.210.07:34:42.30#ibcon#*before return 0, iclass 27, count 0 2006.210.07:34:42.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:34:42.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:34:42.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:34:42.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:34:42.30$4f8m12a/ifd4f 2006.210.07:34:42.30$ifd4f/lo= 2006.210.07:34:42.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:34:42.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:34:42.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:34:42.31$ifd4f/patch= 2006.210.07:34:42.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:34:42.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:34:42.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:34:42.31$4f8m12a/"form=m,16.000,1:2 2006.210.07:34:42.31$4f8m12a/"tpicd 2006.210.07:34:42.31$4f8m12a/echo=off 2006.210.07:34:42.31$4f8m12a/xlog=off 2006.210.07:34:42.31:!2006.210.07:35:10 2006.210.07:34:55.14#trakl#Source acquired 2006.210.07:34:57.14#flagr#flagr/antenna,acquired 2006.210.07:35:10.01:preob 2006.210.07:35:11.14/onsource/TRACKING 2006.210.07:35:11.14:!2006.210.07:35:20 2006.210.07:35:20.00:data_valid=on 2006.210.07:35:20.00:midob 2006.210.07:35:20.14/onsource/TRACKING 2006.210.07:35:20.14/wx/30.59,1006.2,73 2006.210.07:35:20.30/cable/+6.3951E-03 2006.210.07:35:21.39/va/01,08,usb,yes,28,30 2006.210.07:35:21.39/va/02,07,usb,yes,28,30 2006.210.07:35:21.39/va/03,06,usb,yes,30,30 2006.210.07:35:21.39/va/04,07,usb,yes,29,31 2006.210.07:35:21.39/va/05,07,usb,yes,30,32 2006.210.07:35:21.39/va/06,06,usb,yes,29,29 2006.210.07:35:21.39/va/07,06,usb,yes,30,29 2006.210.07:35:21.39/va/08,07,usb,yes,28,28 2006.210.07:35:21.62/valo/01,532.99,yes,locked 2006.210.07:35:21.62/valo/02,572.99,yes,locked 2006.210.07:35:21.62/valo/03,672.99,yes,locked 2006.210.07:35:21.62/valo/04,832.99,yes,locked 2006.210.07:35:21.62/valo/05,652.99,yes,locked 2006.210.07:35:21.62/valo/06,772.99,yes,locked 2006.210.07:35:21.62/valo/07,832.99,yes,locked 2006.210.07:35:21.62/valo/08,852.99,yes,locked 2006.210.07:35:22.71/vb/01,04,usb,yes,28,27 2006.210.07:35:22.71/vb/02,04,usb,yes,30,31 2006.210.07:35:22.71/vb/03,03,usb,yes,33,37 2006.210.07:35:22.71/vb/04,03,usb,yes,34,34 2006.210.07:35:22.71/vb/05,03,usb,yes,32,37 2006.210.07:35:22.71/vb/06,03,usb,yes,33,36 2006.210.07:35:22.71/vb/07,04,usb,yes,29,29 2006.210.07:35:22.71/vb/08,03,usb,yes,33,37 2006.210.07:35:22.95/vblo/01,632.99,yes,locked 2006.210.07:35:22.95/vblo/02,640.99,yes,locked 2006.210.07:35:22.95/vblo/03,656.99,yes,locked 2006.210.07:35:22.95/vblo/04,712.99,yes,locked 2006.210.07:35:22.95/vblo/05,744.99,yes,locked 2006.210.07:35:22.95/vblo/06,752.99,yes,locked 2006.210.07:35:22.95/vblo/07,734.99,yes,locked 2006.210.07:35:22.95/vblo/08,744.99,yes,locked 2006.210.07:35:23.10/vabw/8 2006.210.07:35:23.25/vbbw/8 2006.210.07:35:23.34/xfe/off,on,12.5 2006.210.07:35:23.72/ifatt/23,28,28,28 2006.210.07:35:24.07/fmout-gps/S +4.36E-07 2006.210.07:35:24.12:!2006.210.07:36:20 2006.210.07:36:20.01:data_valid=off 2006.210.07:36:20.01:postob 2006.210.07:36:20.13/cable/+6.3948E-03 2006.210.07:36:20.13/wx/30.60,1006.2,73 2006.210.07:36:21.07/fmout-gps/S +4.37E-07 2006.210.07:36:21.07:scan_name=210-0737,k06210,60 2006.210.07:36:21.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.210.07:36:22.14#flagr#flagr/antenna,new-source 2006.210.07:36:22.14:checkk5 2006.210.07:36:22.49/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:36:22.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:36:23.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:36:23.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:36:23.84/chk_obsdata//k5ts1/T2100735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:36:24.17/chk_obsdata//k5ts2/T2100735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:36:24.50/chk_obsdata//k5ts3/T2100735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:36:24.84/chk_obsdata//k5ts4/T2100735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:36:25.49/k5log//k5ts1_log_newline 2006.210.07:36:26.16/k5log//k5ts2_log_newline 2006.210.07:36:26.82/k5log//k5ts3_log_newline 2006.210.07:36:27.47/k5log//k5ts4_log_newline 2006.210.07:36:27.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:36:27.49:4f8m12a=1 2006.210.07:36:27.49$4f8m12a/echo=on 2006.210.07:36:27.49$4f8m12a/pcalon 2006.210.07:36:27.49$pcalon/"no phase cal control is implemented here 2006.210.07:36:27.49$4f8m12a/"tpicd=stop 2006.210.07:36:27.49$4f8m12a/vc4f8 2006.210.07:36:27.49$vc4f8/valo=1,532.99 2006.210.07:36:27.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.07:36:27.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.07:36:27.50#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:27.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:27.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:27.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:27.50#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:36:27.50#ibcon#first serial, iclass 34, count 0 2006.210.07:36:27.50#ibcon#enter sib2, iclass 34, count 0 2006.210.07:36:27.50#ibcon#flushed, iclass 34, count 0 2006.210.07:36:27.50#ibcon#about to write, iclass 34, count 0 2006.210.07:36:27.50#ibcon#wrote, iclass 34, count 0 2006.210.07:36:27.50#ibcon#about to read 3, iclass 34, count 0 2006.210.07:36:27.51#ibcon#read 3, iclass 34, count 0 2006.210.07:36:27.51#ibcon#about to read 4, iclass 34, count 0 2006.210.07:36:27.51#ibcon#read 4, iclass 34, count 0 2006.210.07:36:27.51#ibcon#about to read 5, iclass 34, count 0 2006.210.07:36:27.51#ibcon#read 5, iclass 34, count 0 2006.210.07:36:27.51#ibcon#about to read 6, iclass 34, count 0 2006.210.07:36:27.51#ibcon#read 6, iclass 34, count 0 2006.210.07:36:27.51#ibcon#end of sib2, iclass 34, count 0 2006.210.07:36:27.51#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:36:27.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:36:27.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:36:27.51#ibcon#*before write, iclass 34, count 0 2006.210.07:36:27.51#ibcon#enter sib2, iclass 34, count 0 2006.210.07:36:27.51#ibcon#flushed, iclass 34, count 0 2006.210.07:36:27.51#ibcon#about to write, iclass 34, count 0 2006.210.07:36:27.51#ibcon#wrote, iclass 34, count 0 2006.210.07:36:27.51#ibcon#about to read 3, iclass 34, count 0 2006.210.07:36:27.56#ibcon#read 3, iclass 34, count 0 2006.210.07:36:27.56#ibcon#about to read 4, iclass 34, count 0 2006.210.07:36:27.56#ibcon#read 4, iclass 34, count 0 2006.210.07:36:27.56#ibcon#about to read 5, iclass 34, count 0 2006.210.07:36:27.56#ibcon#read 5, iclass 34, count 0 2006.210.07:36:27.56#ibcon#about to read 6, iclass 34, count 0 2006.210.07:36:27.56#ibcon#read 6, iclass 34, count 0 2006.210.07:36:27.56#ibcon#end of sib2, iclass 34, count 0 2006.210.07:36:27.56#ibcon#*after write, iclass 34, count 0 2006.210.07:36:27.56#ibcon#*before return 0, iclass 34, count 0 2006.210.07:36:27.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:27.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:27.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:36:27.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:36:27.56$vc4f8/va=1,8 2006.210.07:36:27.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.07:36:27.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.07:36:27.56#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:27.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:27.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:27.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:27.56#ibcon#enter wrdev, iclass 36, count 2 2006.210.07:36:27.56#ibcon#first serial, iclass 36, count 2 2006.210.07:36:27.56#ibcon#enter sib2, iclass 36, count 2 2006.210.07:36:27.56#ibcon#flushed, iclass 36, count 2 2006.210.07:36:27.56#ibcon#about to write, iclass 36, count 2 2006.210.07:36:27.56#ibcon#wrote, iclass 36, count 2 2006.210.07:36:27.56#ibcon#about to read 3, iclass 36, count 2 2006.210.07:36:27.58#ibcon#read 3, iclass 36, count 2 2006.210.07:36:27.58#ibcon#about to read 4, iclass 36, count 2 2006.210.07:36:27.58#ibcon#read 4, iclass 36, count 2 2006.210.07:36:27.58#ibcon#about to read 5, iclass 36, count 2 2006.210.07:36:27.58#ibcon#read 5, iclass 36, count 2 2006.210.07:36:27.58#ibcon#about to read 6, iclass 36, count 2 2006.210.07:36:27.58#ibcon#read 6, iclass 36, count 2 2006.210.07:36:27.58#ibcon#end of sib2, iclass 36, count 2 2006.210.07:36:27.58#ibcon#*mode == 0, iclass 36, count 2 2006.210.07:36:27.58#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.07:36:27.58#ibcon#[25=AT01-08\r\n] 2006.210.07:36:27.58#ibcon#*before write, iclass 36, count 2 2006.210.07:36:27.58#ibcon#enter sib2, iclass 36, count 2 2006.210.07:36:27.58#ibcon#flushed, iclass 36, count 2 2006.210.07:36:27.58#ibcon#about to write, iclass 36, count 2 2006.210.07:36:27.58#ibcon#wrote, iclass 36, count 2 2006.210.07:36:27.58#ibcon#about to read 3, iclass 36, count 2 2006.210.07:36:27.61#ibcon#read 3, iclass 36, count 2 2006.210.07:36:27.61#ibcon#about to read 4, iclass 36, count 2 2006.210.07:36:27.61#ibcon#read 4, iclass 36, count 2 2006.210.07:36:27.61#ibcon#about to read 5, iclass 36, count 2 2006.210.07:36:27.61#ibcon#read 5, iclass 36, count 2 2006.210.07:36:27.61#ibcon#about to read 6, iclass 36, count 2 2006.210.07:36:27.61#ibcon#read 6, iclass 36, count 2 2006.210.07:36:27.61#ibcon#end of sib2, iclass 36, count 2 2006.210.07:36:27.61#ibcon#*after write, iclass 36, count 2 2006.210.07:36:27.61#ibcon#*before return 0, iclass 36, count 2 2006.210.07:36:27.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:27.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:27.61#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.07:36:27.61#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:27.61#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:27.73#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:27.73#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:27.73#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:36:27.73#ibcon#first serial, iclass 36, count 0 2006.210.07:36:27.73#ibcon#enter sib2, iclass 36, count 0 2006.210.07:36:27.73#ibcon#flushed, iclass 36, count 0 2006.210.07:36:27.73#ibcon#about to write, iclass 36, count 0 2006.210.07:36:27.73#ibcon#wrote, iclass 36, count 0 2006.210.07:36:27.73#ibcon#about to read 3, iclass 36, count 0 2006.210.07:36:27.75#ibcon#read 3, iclass 36, count 0 2006.210.07:36:27.75#ibcon#about to read 4, iclass 36, count 0 2006.210.07:36:27.75#ibcon#read 4, iclass 36, count 0 2006.210.07:36:27.75#ibcon#about to read 5, iclass 36, count 0 2006.210.07:36:27.75#ibcon#read 5, iclass 36, count 0 2006.210.07:36:27.75#ibcon#about to read 6, iclass 36, count 0 2006.210.07:36:27.75#ibcon#read 6, iclass 36, count 0 2006.210.07:36:27.75#ibcon#end of sib2, iclass 36, count 0 2006.210.07:36:27.75#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:36:27.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:36:27.75#ibcon#[25=USB\r\n] 2006.210.07:36:27.75#ibcon#*before write, iclass 36, count 0 2006.210.07:36:27.75#ibcon#enter sib2, iclass 36, count 0 2006.210.07:36:27.75#ibcon#flushed, iclass 36, count 0 2006.210.07:36:27.75#ibcon#about to write, iclass 36, count 0 2006.210.07:36:27.75#ibcon#wrote, iclass 36, count 0 2006.210.07:36:27.75#ibcon#about to read 3, iclass 36, count 0 2006.210.07:36:27.78#ibcon#read 3, iclass 36, count 0 2006.210.07:36:27.78#ibcon#about to read 4, iclass 36, count 0 2006.210.07:36:27.78#ibcon#read 4, iclass 36, count 0 2006.210.07:36:27.78#ibcon#about to read 5, iclass 36, count 0 2006.210.07:36:27.78#ibcon#read 5, iclass 36, count 0 2006.210.07:36:27.78#ibcon#about to read 6, iclass 36, count 0 2006.210.07:36:27.78#ibcon#read 6, iclass 36, count 0 2006.210.07:36:27.78#ibcon#end of sib2, iclass 36, count 0 2006.210.07:36:27.78#ibcon#*after write, iclass 36, count 0 2006.210.07:36:27.78#ibcon#*before return 0, iclass 36, count 0 2006.210.07:36:27.78#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:27.78#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:27.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:36:27.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:36:27.78$vc4f8/valo=2,572.99 2006.210.07:36:27.78#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.07:36:27.78#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.07:36:27.78#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:27.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:27.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:27.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:27.78#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:36:27.78#ibcon#first serial, iclass 38, count 0 2006.210.07:36:27.78#ibcon#enter sib2, iclass 38, count 0 2006.210.07:36:27.78#ibcon#flushed, iclass 38, count 0 2006.210.07:36:27.78#ibcon#about to write, iclass 38, count 0 2006.210.07:36:27.78#ibcon#wrote, iclass 38, count 0 2006.210.07:36:27.78#ibcon#about to read 3, iclass 38, count 0 2006.210.07:36:27.80#ibcon#read 3, iclass 38, count 0 2006.210.07:36:27.80#ibcon#about to read 4, iclass 38, count 0 2006.210.07:36:27.80#ibcon#read 4, iclass 38, count 0 2006.210.07:36:27.80#ibcon#about to read 5, iclass 38, count 0 2006.210.07:36:27.80#ibcon#read 5, iclass 38, count 0 2006.210.07:36:27.80#ibcon#about to read 6, iclass 38, count 0 2006.210.07:36:27.80#ibcon#read 6, iclass 38, count 0 2006.210.07:36:27.80#ibcon#end of sib2, iclass 38, count 0 2006.210.07:36:27.80#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:36:27.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:36:27.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:36:27.80#ibcon#*before write, iclass 38, count 0 2006.210.07:36:27.80#ibcon#enter sib2, iclass 38, count 0 2006.210.07:36:27.80#ibcon#flushed, iclass 38, count 0 2006.210.07:36:27.80#ibcon#about to write, iclass 38, count 0 2006.210.07:36:27.80#ibcon#wrote, iclass 38, count 0 2006.210.07:36:27.80#ibcon#about to read 3, iclass 38, count 0 2006.210.07:36:27.84#ibcon#read 3, iclass 38, count 0 2006.210.07:36:27.84#ibcon#about to read 4, iclass 38, count 0 2006.210.07:36:27.84#ibcon#read 4, iclass 38, count 0 2006.210.07:36:27.84#ibcon#about to read 5, iclass 38, count 0 2006.210.07:36:27.84#ibcon#read 5, iclass 38, count 0 2006.210.07:36:27.84#ibcon#about to read 6, iclass 38, count 0 2006.210.07:36:27.84#ibcon#read 6, iclass 38, count 0 2006.210.07:36:27.84#ibcon#end of sib2, iclass 38, count 0 2006.210.07:36:27.84#ibcon#*after write, iclass 38, count 0 2006.210.07:36:27.84#ibcon#*before return 0, iclass 38, count 0 2006.210.07:36:27.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:27.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:27.84#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:36:27.84#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:36:27.84$vc4f8/va=2,7 2006.210.07:36:27.84#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.07:36:27.84#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.07:36:27.84#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:27.84#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:27.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:27.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:27.90#ibcon#enter wrdev, iclass 40, count 2 2006.210.07:36:27.90#ibcon#first serial, iclass 40, count 2 2006.210.07:36:27.90#ibcon#enter sib2, iclass 40, count 2 2006.210.07:36:27.90#ibcon#flushed, iclass 40, count 2 2006.210.07:36:27.90#ibcon#about to write, iclass 40, count 2 2006.210.07:36:27.90#ibcon#wrote, iclass 40, count 2 2006.210.07:36:27.90#ibcon#about to read 3, iclass 40, count 2 2006.210.07:36:27.92#ibcon#read 3, iclass 40, count 2 2006.210.07:36:27.92#ibcon#about to read 4, iclass 40, count 2 2006.210.07:36:27.92#ibcon#read 4, iclass 40, count 2 2006.210.07:36:27.92#ibcon#about to read 5, iclass 40, count 2 2006.210.07:36:27.92#ibcon#read 5, iclass 40, count 2 2006.210.07:36:27.92#ibcon#about to read 6, iclass 40, count 2 2006.210.07:36:27.92#ibcon#read 6, iclass 40, count 2 2006.210.07:36:27.92#ibcon#end of sib2, iclass 40, count 2 2006.210.07:36:27.92#ibcon#*mode == 0, iclass 40, count 2 2006.210.07:36:27.92#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.07:36:27.92#ibcon#[25=AT02-07\r\n] 2006.210.07:36:27.92#ibcon#*before write, iclass 40, count 2 2006.210.07:36:27.92#ibcon#enter sib2, iclass 40, count 2 2006.210.07:36:27.92#ibcon#flushed, iclass 40, count 2 2006.210.07:36:27.92#ibcon#about to write, iclass 40, count 2 2006.210.07:36:27.92#ibcon#wrote, iclass 40, count 2 2006.210.07:36:27.92#ibcon#about to read 3, iclass 40, count 2 2006.210.07:36:27.95#ibcon#read 3, iclass 40, count 2 2006.210.07:36:27.95#ibcon#about to read 4, iclass 40, count 2 2006.210.07:36:27.95#ibcon#read 4, iclass 40, count 2 2006.210.07:36:27.95#ibcon#about to read 5, iclass 40, count 2 2006.210.07:36:27.95#ibcon#read 5, iclass 40, count 2 2006.210.07:36:27.95#ibcon#about to read 6, iclass 40, count 2 2006.210.07:36:27.95#ibcon#read 6, iclass 40, count 2 2006.210.07:36:27.95#ibcon#end of sib2, iclass 40, count 2 2006.210.07:36:27.95#ibcon#*after write, iclass 40, count 2 2006.210.07:36:27.95#ibcon#*before return 0, iclass 40, count 2 2006.210.07:36:27.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:27.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:27.95#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.07:36:27.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:27.95#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:28.07#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:28.07#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:28.07#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:36:28.07#ibcon#first serial, iclass 40, count 0 2006.210.07:36:28.07#ibcon#enter sib2, iclass 40, count 0 2006.210.07:36:28.07#ibcon#flushed, iclass 40, count 0 2006.210.07:36:28.07#ibcon#about to write, iclass 40, count 0 2006.210.07:36:28.07#ibcon#wrote, iclass 40, count 0 2006.210.07:36:28.07#ibcon#about to read 3, iclass 40, count 0 2006.210.07:36:28.09#ibcon#read 3, iclass 40, count 0 2006.210.07:36:28.09#ibcon#about to read 4, iclass 40, count 0 2006.210.07:36:28.09#ibcon#read 4, iclass 40, count 0 2006.210.07:36:28.09#ibcon#about to read 5, iclass 40, count 0 2006.210.07:36:28.09#ibcon#read 5, iclass 40, count 0 2006.210.07:36:28.09#ibcon#about to read 6, iclass 40, count 0 2006.210.07:36:28.09#ibcon#read 6, iclass 40, count 0 2006.210.07:36:28.09#ibcon#end of sib2, iclass 40, count 0 2006.210.07:36:28.09#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:36:28.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:36:28.09#ibcon#[25=USB\r\n] 2006.210.07:36:28.09#ibcon#*before write, iclass 40, count 0 2006.210.07:36:28.09#ibcon#enter sib2, iclass 40, count 0 2006.210.07:36:28.09#ibcon#flushed, iclass 40, count 0 2006.210.07:36:28.09#ibcon#about to write, iclass 40, count 0 2006.210.07:36:28.09#ibcon#wrote, iclass 40, count 0 2006.210.07:36:28.09#ibcon#about to read 3, iclass 40, count 0 2006.210.07:36:28.12#ibcon#read 3, iclass 40, count 0 2006.210.07:36:28.12#ibcon#about to read 4, iclass 40, count 0 2006.210.07:36:28.12#ibcon#read 4, iclass 40, count 0 2006.210.07:36:28.12#ibcon#about to read 5, iclass 40, count 0 2006.210.07:36:28.12#ibcon#read 5, iclass 40, count 0 2006.210.07:36:28.12#ibcon#about to read 6, iclass 40, count 0 2006.210.07:36:28.12#ibcon#read 6, iclass 40, count 0 2006.210.07:36:28.12#ibcon#end of sib2, iclass 40, count 0 2006.210.07:36:28.12#ibcon#*after write, iclass 40, count 0 2006.210.07:36:28.12#ibcon#*before return 0, iclass 40, count 0 2006.210.07:36:28.12#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:28.12#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:28.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:36:28.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:36:28.12$vc4f8/valo=3,672.99 2006.210.07:36:28.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.07:36:28.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.07:36:28.12#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:28.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:28.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:28.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:28.12#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:36:28.12#ibcon#first serial, iclass 4, count 0 2006.210.07:36:28.12#ibcon#enter sib2, iclass 4, count 0 2006.210.07:36:28.12#ibcon#flushed, iclass 4, count 0 2006.210.07:36:28.12#ibcon#about to write, iclass 4, count 0 2006.210.07:36:28.12#ibcon#wrote, iclass 4, count 0 2006.210.07:36:28.12#ibcon#about to read 3, iclass 4, count 0 2006.210.07:36:28.14#ibcon#read 3, iclass 4, count 0 2006.210.07:36:28.14#ibcon#about to read 4, iclass 4, count 0 2006.210.07:36:28.14#ibcon#read 4, iclass 4, count 0 2006.210.07:36:28.14#ibcon#about to read 5, iclass 4, count 0 2006.210.07:36:28.14#ibcon#read 5, iclass 4, count 0 2006.210.07:36:28.14#ibcon#about to read 6, iclass 4, count 0 2006.210.07:36:28.14#ibcon#read 6, iclass 4, count 0 2006.210.07:36:28.14#ibcon#end of sib2, iclass 4, count 0 2006.210.07:36:28.14#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:36:28.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:36:28.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:36:28.14#ibcon#*before write, iclass 4, count 0 2006.210.07:36:28.14#ibcon#enter sib2, iclass 4, count 0 2006.210.07:36:28.14#ibcon#flushed, iclass 4, count 0 2006.210.07:36:28.14#ibcon#about to write, iclass 4, count 0 2006.210.07:36:28.14#ibcon#wrote, iclass 4, count 0 2006.210.07:36:28.14#ibcon#about to read 3, iclass 4, count 0 2006.210.07:36:28.18#ibcon#read 3, iclass 4, count 0 2006.210.07:36:28.18#ibcon#about to read 4, iclass 4, count 0 2006.210.07:36:28.18#ibcon#read 4, iclass 4, count 0 2006.210.07:36:28.18#ibcon#about to read 5, iclass 4, count 0 2006.210.07:36:28.18#ibcon#read 5, iclass 4, count 0 2006.210.07:36:28.18#ibcon#about to read 6, iclass 4, count 0 2006.210.07:36:28.18#ibcon#read 6, iclass 4, count 0 2006.210.07:36:28.18#ibcon#end of sib2, iclass 4, count 0 2006.210.07:36:28.18#ibcon#*after write, iclass 4, count 0 2006.210.07:36:28.18#ibcon#*before return 0, iclass 4, count 0 2006.210.07:36:28.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:28.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:28.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:36:28.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:36:28.18$vc4f8/va=3,6 2006.210.07:36:28.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.07:36:28.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.07:36:28.18#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:28.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:28.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:28.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:28.24#ibcon#enter wrdev, iclass 6, count 2 2006.210.07:36:28.24#ibcon#first serial, iclass 6, count 2 2006.210.07:36:28.24#ibcon#enter sib2, iclass 6, count 2 2006.210.07:36:28.24#ibcon#flushed, iclass 6, count 2 2006.210.07:36:28.24#ibcon#about to write, iclass 6, count 2 2006.210.07:36:28.24#ibcon#wrote, iclass 6, count 2 2006.210.07:36:28.24#ibcon#about to read 3, iclass 6, count 2 2006.210.07:36:28.26#ibcon#read 3, iclass 6, count 2 2006.210.07:36:28.26#ibcon#about to read 4, iclass 6, count 2 2006.210.07:36:28.26#ibcon#read 4, iclass 6, count 2 2006.210.07:36:28.26#ibcon#about to read 5, iclass 6, count 2 2006.210.07:36:28.26#ibcon#read 5, iclass 6, count 2 2006.210.07:36:28.26#ibcon#about to read 6, iclass 6, count 2 2006.210.07:36:28.26#ibcon#read 6, iclass 6, count 2 2006.210.07:36:28.26#ibcon#end of sib2, iclass 6, count 2 2006.210.07:36:28.26#ibcon#*mode == 0, iclass 6, count 2 2006.210.07:36:28.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.07:36:28.26#ibcon#[25=AT03-06\r\n] 2006.210.07:36:28.26#ibcon#*before write, iclass 6, count 2 2006.210.07:36:28.26#ibcon#enter sib2, iclass 6, count 2 2006.210.07:36:28.26#ibcon#flushed, iclass 6, count 2 2006.210.07:36:28.26#ibcon#about to write, iclass 6, count 2 2006.210.07:36:28.26#ibcon#wrote, iclass 6, count 2 2006.210.07:36:28.26#ibcon#about to read 3, iclass 6, count 2 2006.210.07:36:28.29#ibcon#read 3, iclass 6, count 2 2006.210.07:36:28.29#ibcon#about to read 4, iclass 6, count 2 2006.210.07:36:28.29#ibcon#read 4, iclass 6, count 2 2006.210.07:36:28.29#ibcon#about to read 5, iclass 6, count 2 2006.210.07:36:28.29#ibcon#read 5, iclass 6, count 2 2006.210.07:36:28.29#ibcon#about to read 6, iclass 6, count 2 2006.210.07:36:28.29#ibcon#read 6, iclass 6, count 2 2006.210.07:36:28.29#ibcon#end of sib2, iclass 6, count 2 2006.210.07:36:28.29#ibcon#*after write, iclass 6, count 2 2006.210.07:36:28.29#ibcon#*before return 0, iclass 6, count 2 2006.210.07:36:28.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:28.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:28.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.07:36:28.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:28.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:28.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:28.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:28.41#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:36:28.41#ibcon#first serial, iclass 6, count 0 2006.210.07:36:28.41#ibcon#enter sib2, iclass 6, count 0 2006.210.07:36:28.41#ibcon#flushed, iclass 6, count 0 2006.210.07:36:28.41#ibcon#about to write, iclass 6, count 0 2006.210.07:36:28.41#ibcon#wrote, iclass 6, count 0 2006.210.07:36:28.41#ibcon#about to read 3, iclass 6, count 0 2006.210.07:36:28.43#ibcon#read 3, iclass 6, count 0 2006.210.07:36:28.43#ibcon#about to read 4, iclass 6, count 0 2006.210.07:36:28.43#ibcon#read 4, iclass 6, count 0 2006.210.07:36:28.43#ibcon#about to read 5, iclass 6, count 0 2006.210.07:36:28.43#ibcon#read 5, iclass 6, count 0 2006.210.07:36:28.43#ibcon#about to read 6, iclass 6, count 0 2006.210.07:36:28.43#ibcon#read 6, iclass 6, count 0 2006.210.07:36:28.43#ibcon#end of sib2, iclass 6, count 0 2006.210.07:36:28.43#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:36:28.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:36:28.43#ibcon#[25=USB\r\n] 2006.210.07:36:28.43#ibcon#*before write, iclass 6, count 0 2006.210.07:36:28.43#ibcon#enter sib2, iclass 6, count 0 2006.210.07:36:28.43#ibcon#flushed, iclass 6, count 0 2006.210.07:36:28.43#ibcon#about to write, iclass 6, count 0 2006.210.07:36:28.43#ibcon#wrote, iclass 6, count 0 2006.210.07:36:28.43#ibcon#about to read 3, iclass 6, count 0 2006.210.07:36:28.46#ibcon#read 3, iclass 6, count 0 2006.210.07:36:28.46#ibcon#about to read 4, iclass 6, count 0 2006.210.07:36:28.46#ibcon#read 4, iclass 6, count 0 2006.210.07:36:28.46#ibcon#about to read 5, iclass 6, count 0 2006.210.07:36:28.46#ibcon#read 5, iclass 6, count 0 2006.210.07:36:28.46#ibcon#about to read 6, iclass 6, count 0 2006.210.07:36:28.46#ibcon#read 6, iclass 6, count 0 2006.210.07:36:28.46#ibcon#end of sib2, iclass 6, count 0 2006.210.07:36:28.46#ibcon#*after write, iclass 6, count 0 2006.210.07:36:28.46#ibcon#*before return 0, iclass 6, count 0 2006.210.07:36:28.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:28.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:28.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:36:28.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:36:28.46$vc4f8/valo=4,832.99 2006.210.07:36:28.46#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.07:36:28.46#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.07:36:28.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:28.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:36:28.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:36:28.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:36:28.46#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:36:28.46#ibcon#first serial, iclass 10, count 0 2006.210.07:36:28.46#ibcon#enter sib2, iclass 10, count 0 2006.210.07:36:28.46#ibcon#flushed, iclass 10, count 0 2006.210.07:36:28.46#ibcon#about to write, iclass 10, count 0 2006.210.07:36:28.46#ibcon#wrote, iclass 10, count 0 2006.210.07:36:28.46#ibcon#about to read 3, iclass 10, count 0 2006.210.07:36:28.48#ibcon#read 3, iclass 10, count 0 2006.210.07:36:28.48#ibcon#about to read 4, iclass 10, count 0 2006.210.07:36:28.48#ibcon#read 4, iclass 10, count 0 2006.210.07:36:28.48#ibcon#about to read 5, iclass 10, count 0 2006.210.07:36:28.48#ibcon#read 5, iclass 10, count 0 2006.210.07:36:28.48#ibcon#about to read 6, iclass 10, count 0 2006.210.07:36:28.48#ibcon#read 6, iclass 10, count 0 2006.210.07:36:28.48#ibcon#end of sib2, iclass 10, count 0 2006.210.07:36:28.48#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:36:28.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:36:28.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:36:28.48#ibcon#*before write, iclass 10, count 0 2006.210.07:36:28.48#ibcon#enter sib2, iclass 10, count 0 2006.210.07:36:28.48#ibcon#flushed, iclass 10, count 0 2006.210.07:36:28.48#ibcon#about to write, iclass 10, count 0 2006.210.07:36:28.48#ibcon#wrote, iclass 10, count 0 2006.210.07:36:28.48#ibcon#about to read 3, iclass 10, count 0 2006.210.07:36:28.52#ibcon#read 3, iclass 10, count 0 2006.210.07:36:28.52#ibcon#about to read 4, iclass 10, count 0 2006.210.07:36:28.52#ibcon#read 4, iclass 10, count 0 2006.210.07:36:28.52#ibcon#about to read 5, iclass 10, count 0 2006.210.07:36:28.52#ibcon#read 5, iclass 10, count 0 2006.210.07:36:28.52#ibcon#about to read 6, iclass 10, count 0 2006.210.07:36:28.52#ibcon#read 6, iclass 10, count 0 2006.210.07:36:28.52#ibcon#end of sib2, iclass 10, count 0 2006.210.07:36:28.52#ibcon#*after write, iclass 10, count 0 2006.210.07:36:28.52#ibcon#*before return 0, iclass 10, count 0 2006.210.07:36:28.52#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:36:28.52#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:36:28.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:36:28.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:36:28.52$vc4f8/va=4,7 2006.210.07:36:28.52#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.07:36:28.52#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.07:36:28.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:28.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:36:28.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:36:28.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:36:28.58#ibcon#enter wrdev, iclass 12, count 2 2006.210.07:36:28.58#ibcon#first serial, iclass 12, count 2 2006.210.07:36:28.58#ibcon#enter sib2, iclass 12, count 2 2006.210.07:36:28.58#ibcon#flushed, iclass 12, count 2 2006.210.07:36:28.58#ibcon#about to write, iclass 12, count 2 2006.210.07:36:28.58#ibcon#wrote, iclass 12, count 2 2006.210.07:36:28.58#ibcon#about to read 3, iclass 12, count 2 2006.210.07:36:28.60#ibcon#read 3, iclass 12, count 2 2006.210.07:36:28.60#ibcon#about to read 4, iclass 12, count 2 2006.210.07:36:28.60#ibcon#read 4, iclass 12, count 2 2006.210.07:36:28.60#ibcon#about to read 5, iclass 12, count 2 2006.210.07:36:28.60#ibcon#read 5, iclass 12, count 2 2006.210.07:36:28.60#ibcon#about to read 6, iclass 12, count 2 2006.210.07:36:28.60#ibcon#read 6, iclass 12, count 2 2006.210.07:36:28.60#ibcon#end of sib2, iclass 12, count 2 2006.210.07:36:28.60#ibcon#*mode == 0, iclass 12, count 2 2006.210.07:36:28.60#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.07:36:28.60#ibcon#[25=AT04-07\r\n] 2006.210.07:36:28.60#ibcon#*before write, iclass 12, count 2 2006.210.07:36:28.60#ibcon#enter sib2, iclass 12, count 2 2006.210.07:36:28.60#ibcon#flushed, iclass 12, count 2 2006.210.07:36:28.60#ibcon#about to write, iclass 12, count 2 2006.210.07:36:28.60#ibcon#wrote, iclass 12, count 2 2006.210.07:36:28.60#ibcon#about to read 3, iclass 12, count 2 2006.210.07:36:28.63#ibcon#read 3, iclass 12, count 2 2006.210.07:36:28.63#ibcon#about to read 4, iclass 12, count 2 2006.210.07:36:28.63#ibcon#read 4, iclass 12, count 2 2006.210.07:36:28.63#ibcon#about to read 5, iclass 12, count 2 2006.210.07:36:28.63#ibcon#read 5, iclass 12, count 2 2006.210.07:36:28.63#ibcon#about to read 6, iclass 12, count 2 2006.210.07:36:28.63#ibcon#read 6, iclass 12, count 2 2006.210.07:36:28.63#ibcon#end of sib2, iclass 12, count 2 2006.210.07:36:28.63#ibcon#*after write, iclass 12, count 2 2006.210.07:36:28.63#ibcon#*before return 0, iclass 12, count 2 2006.210.07:36:28.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:36:28.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:36:28.63#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.07:36:28.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:28.63#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:36:28.75#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:36:28.75#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:36:28.75#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:36:28.75#ibcon#first serial, iclass 12, count 0 2006.210.07:36:28.75#ibcon#enter sib2, iclass 12, count 0 2006.210.07:36:28.75#ibcon#flushed, iclass 12, count 0 2006.210.07:36:28.75#ibcon#about to write, iclass 12, count 0 2006.210.07:36:28.75#ibcon#wrote, iclass 12, count 0 2006.210.07:36:28.75#ibcon#about to read 3, iclass 12, count 0 2006.210.07:36:28.77#ibcon#read 3, iclass 12, count 0 2006.210.07:36:28.77#ibcon#about to read 4, iclass 12, count 0 2006.210.07:36:28.77#ibcon#read 4, iclass 12, count 0 2006.210.07:36:28.77#ibcon#about to read 5, iclass 12, count 0 2006.210.07:36:28.77#ibcon#read 5, iclass 12, count 0 2006.210.07:36:28.77#ibcon#about to read 6, iclass 12, count 0 2006.210.07:36:28.77#ibcon#read 6, iclass 12, count 0 2006.210.07:36:28.77#ibcon#end of sib2, iclass 12, count 0 2006.210.07:36:28.77#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:36:28.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:36:28.77#ibcon#[25=USB\r\n] 2006.210.07:36:28.77#ibcon#*before write, iclass 12, count 0 2006.210.07:36:28.77#ibcon#enter sib2, iclass 12, count 0 2006.210.07:36:28.77#ibcon#flushed, iclass 12, count 0 2006.210.07:36:28.77#ibcon#about to write, iclass 12, count 0 2006.210.07:36:28.77#ibcon#wrote, iclass 12, count 0 2006.210.07:36:28.77#ibcon#about to read 3, iclass 12, count 0 2006.210.07:36:28.80#ibcon#read 3, iclass 12, count 0 2006.210.07:36:28.80#ibcon#about to read 4, iclass 12, count 0 2006.210.07:36:28.80#ibcon#read 4, iclass 12, count 0 2006.210.07:36:28.80#ibcon#about to read 5, iclass 12, count 0 2006.210.07:36:28.80#ibcon#read 5, iclass 12, count 0 2006.210.07:36:28.80#ibcon#about to read 6, iclass 12, count 0 2006.210.07:36:28.80#ibcon#read 6, iclass 12, count 0 2006.210.07:36:28.80#ibcon#end of sib2, iclass 12, count 0 2006.210.07:36:28.80#ibcon#*after write, iclass 12, count 0 2006.210.07:36:28.80#ibcon#*before return 0, iclass 12, count 0 2006.210.07:36:28.80#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:36:28.80#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:36:28.80#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:36:28.80#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:36:28.80$vc4f8/valo=5,652.99 2006.210.07:36:28.80#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.07:36:28.80#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.07:36:28.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:28.80#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:36:28.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:36:28.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:36:28.80#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:36:28.80#ibcon#first serial, iclass 14, count 0 2006.210.07:36:28.80#ibcon#enter sib2, iclass 14, count 0 2006.210.07:36:28.80#ibcon#flushed, iclass 14, count 0 2006.210.07:36:28.80#ibcon#about to write, iclass 14, count 0 2006.210.07:36:28.80#ibcon#wrote, iclass 14, count 0 2006.210.07:36:28.80#ibcon#about to read 3, iclass 14, count 0 2006.210.07:36:28.82#ibcon#read 3, iclass 14, count 0 2006.210.07:36:28.82#ibcon#about to read 4, iclass 14, count 0 2006.210.07:36:28.82#ibcon#read 4, iclass 14, count 0 2006.210.07:36:28.82#ibcon#about to read 5, iclass 14, count 0 2006.210.07:36:28.82#ibcon#read 5, iclass 14, count 0 2006.210.07:36:28.82#ibcon#about to read 6, iclass 14, count 0 2006.210.07:36:28.82#ibcon#read 6, iclass 14, count 0 2006.210.07:36:28.82#ibcon#end of sib2, iclass 14, count 0 2006.210.07:36:28.82#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:36:28.82#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:36:28.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:36:28.82#ibcon#*before write, iclass 14, count 0 2006.210.07:36:28.82#ibcon#enter sib2, iclass 14, count 0 2006.210.07:36:28.82#ibcon#flushed, iclass 14, count 0 2006.210.07:36:28.82#ibcon#about to write, iclass 14, count 0 2006.210.07:36:28.82#ibcon#wrote, iclass 14, count 0 2006.210.07:36:28.82#ibcon#about to read 3, iclass 14, count 0 2006.210.07:36:28.86#ibcon#read 3, iclass 14, count 0 2006.210.07:36:28.86#ibcon#about to read 4, iclass 14, count 0 2006.210.07:36:28.86#ibcon#read 4, iclass 14, count 0 2006.210.07:36:28.86#ibcon#about to read 5, iclass 14, count 0 2006.210.07:36:28.86#ibcon#read 5, iclass 14, count 0 2006.210.07:36:28.86#ibcon#about to read 6, iclass 14, count 0 2006.210.07:36:28.86#ibcon#read 6, iclass 14, count 0 2006.210.07:36:28.86#ibcon#end of sib2, iclass 14, count 0 2006.210.07:36:28.86#ibcon#*after write, iclass 14, count 0 2006.210.07:36:28.86#ibcon#*before return 0, iclass 14, count 0 2006.210.07:36:28.86#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:36:28.86#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:36:28.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:36:28.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:36:28.86$vc4f8/va=5,7 2006.210.07:36:28.86#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.07:36:28.86#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.07:36:28.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:28.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:28.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:28.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:28.92#ibcon#enter wrdev, iclass 16, count 2 2006.210.07:36:28.92#ibcon#first serial, iclass 16, count 2 2006.210.07:36:28.92#ibcon#enter sib2, iclass 16, count 2 2006.210.07:36:28.92#ibcon#flushed, iclass 16, count 2 2006.210.07:36:28.92#ibcon#about to write, iclass 16, count 2 2006.210.07:36:28.92#ibcon#wrote, iclass 16, count 2 2006.210.07:36:28.92#ibcon#about to read 3, iclass 16, count 2 2006.210.07:36:28.94#ibcon#read 3, iclass 16, count 2 2006.210.07:36:28.94#ibcon#about to read 4, iclass 16, count 2 2006.210.07:36:28.94#ibcon#read 4, iclass 16, count 2 2006.210.07:36:28.94#ibcon#about to read 5, iclass 16, count 2 2006.210.07:36:28.94#ibcon#read 5, iclass 16, count 2 2006.210.07:36:28.94#ibcon#about to read 6, iclass 16, count 2 2006.210.07:36:28.94#ibcon#read 6, iclass 16, count 2 2006.210.07:36:28.94#ibcon#end of sib2, iclass 16, count 2 2006.210.07:36:28.94#ibcon#*mode == 0, iclass 16, count 2 2006.210.07:36:28.94#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.07:36:28.94#ibcon#[25=AT05-07\r\n] 2006.210.07:36:28.94#ibcon#*before write, iclass 16, count 2 2006.210.07:36:28.94#ibcon#enter sib2, iclass 16, count 2 2006.210.07:36:28.94#ibcon#flushed, iclass 16, count 2 2006.210.07:36:28.94#ibcon#about to write, iclass 16, count 2 2006.210.07:36:28.94#ibcon#wrote, iclass 16, count 2 2006.210.07:36:28.94#ibcon#about to read 3, iclass 16, count 2 2006.210.07:36:28.97#ibcon#read 3, iclass 16, count 2 2006.210.07:36:28.97#ibcon#about to read 4, iclass 16, count 2 2006.210.07:36:28.97#ibcon#read 4, iclass 16, count 2 2006.210.07:36:28.97#ibcon#about to read 5, iclass 16, count 2 2006.210.07:36:28.97#ibcon#read 5, iclass 16, count 2 2006.210.07:36:28.97#ibcon#about to read 6, iclass 16, count 2 2006.210.07:36:28.97#ibcon#read 6, iclass 16, count 2 2006.210.07:36:28.97#ibcon#end of sib2, iclass 16, count 2 2006.210.07:36:28.97#ibcon#*after write, iclass 16, count 2 2006.210.07:36:28.97#ibcon#*before return 0, iclass 16, count 2 2006.210.07:36:28.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:28.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:28.97#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.07:36:28.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:28.97#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:29.09#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:29.09#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:29.09#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:36:29.09#ibcon#first serial, iclass 16, count 0 2006.210.07:36:29.09#ibcon#enter sib2, iclass 16, count 0 2006.210.07:36:29.09#ibcon#flushed, iclass 16, count 0 2006.210.07:36:29.09#ibcon#about to write, iclass 16, count 0 2006.210.07:36:29.09#ibcon#wrote, iclass 16, count 0 2006.210.07:36:29.09#ibcon#about to read 3, iclass 16, count 0 2006.210.07:36:29.11#ibcon#read 3, iclass 16, count 0 2006.210.07:36:29.11#ibcon#about to read 4, iclass 16, count 0 2006.210.07:36:29.11#ibcon#read 4, iclass 16, count 0 2006.210.07:36:29.11#ibcon#about to read 5, iclass 16, count 0 2006.210.07:36:29.11#ibcon#read 5, iclass 16, count 0 2006.210.07:36:29.11#ibcon#about to read 6, iclass 16, count 0 2006.210.07:36:29.11#ibcon#read 6, iclass 16, count 0 2006.210.07:36:29.11#ibcon#end of sib2, iclass 16, count 0 2006.210.07:36:29.11#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:36:29.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:36:29.11#ibcon#[25=USB\r\n] 2006.210.07:36:29.11#ibcon#*before write, iclass 16, count 0 2006.210.07:36:29.11#ibcon#enter sib2, iclass 16, count 0 2006.210.07:36:29.11#ibcon#flushed, iclass 16, count 0 2006.210.07:36:29.11#ibcon#about to write, iclass 16, count 0 2006.210.07:36:29.11#ibcon#wrote, iclass 16, count 0 2006.210.07:36:29.11#ibcon#about to read 3, iclass 16, count 0 2006.210.07:36:29.14#ibcon#read 3, iclass 16, count 0 2006.210.07:36:29.14#ibcon#about to read 4, iclass 16, count 0 2006.210.07:36:29.14#ibcon#read 4, iclass 16, count 0 2006.210.07:36:29.14#ibcon#about to read 5, iclass 16, count 0 2006.210.07:36:29.14#ibcon#read 5, iclass 16, count 0 2006.210.07:36:29.14#ibcon#about to read 6, iclass 16, count 0 2006.210.07:36:29.14#ibcon#read 6, iclass 16, count 0 2006.210.07:36:29.14#ibcon#end of sib2, iclass 16, count 0 2006.210.07:36:29.14#ibcon#*after write, iclass 16, count 0 2006.210.07:36:29.14#ibcon#*before return 0, iclass 16, count 0 2006.210.07:36:29.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:29.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:29.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:36:29.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:36:29.14$vc4f8/valo=6,772.99 2006.210.07:36:29.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.07:36:29.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.07:36:29.14#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:29.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:29.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:29.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:29.14#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:36:29.14#ibcon#first serial, iclass 18, count 0 2006.210.07:36:29.14#ibcon#enter sib2, iclass 18, count 0 2006.210.07:36:29.14#ibcon#flushed, iclass 18, count 0 2006.210.07:36:29.14#ibcon#about to write, iclass 18, count 0 2006.210.07:36:29.14#ibcon#wrote, iclass 18, count 0 2006.210.07:36:29.14#ibcon#about to read 3, iclass 18, count 0 2006.210.07:36:29.16#ibcon#read 3, iclass 18, count 0 2006.210.07:36:29.16#ibcon#about to read 4, iclass 18, count 0 2006.210.07:36:29.16#ibcon#read 4, iclass 18, count 0 2006.210.07:36:29.16#ibcon#about to read 5, iclass 18, count 0 2006.210.07:36:29.16#ibcon#read 5, iclass 18, count 0 2006.210.07:36:29.16#ibcon#about to read 6, iclass 18, count 0 2006.210.07:36:29.16#ibcon#read 6, iclass 18, count 0 2006.210.07:36:29.16#ibcon#end of sib2, iclass 18, count 0 2006.210.07:36:29.16#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:36:29.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:36:29.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:36:29.16#ibcon#*before write, iclass 18, count 0 2006.210.07:36:29.16#ibcon#enter sib2, iclass 18, count 0 2006.210.07:36:29.16#ibcon#flushed, iclass 18, count 0 2006.210.07:36:29.16#ibcon#about to write, iclass 18, count 0 2006.210.07:36:29.16#ibcon#wrote, iclass 18, count 0 2006.210.07:36:29.16#ibcon#about to read 3, iclass 18, count 0 2006.210.07:36:29.20#ibcon#read 3, iclass 18, count 0 2006.210.07:36:29.20#ibcon#about to read 4, iclass 18, count 0 2006.210.07:36:29.20#ibcon#read 4, iclass 18, count 0 2006.210.07:36:29.20#ibcon#about to read 5, iclass 18, count 0 2006.210.07:36:29.20#ibcon#read 5, iclass 18, count 0 2006.210.07:36:29.20#ibcon#about to read 6, iclass 18, count 0 2006.210.07:36:29.20#ibcon#read 6, iclass 18, count 0 2006.210.07:36:29.20#ibcon#end of sib2, iclass 18, count 0 2006.210.07:36:29.20#ibcon#*after write, iclass 18, count 0 2006.210.07:36:29.20#ibcon#*before return 0, iclass 18, count 0 2006.210.07:36:29.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:29.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:29.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:36:29.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:36:29.20$vc4f8/va=6,6 2006.210.07:36:29.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.07:36:29.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.07:36:29.20#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:29.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:29.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:29.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:29.26#ibcon#enter wrdev, iclass 20, count 2 2006.210.07:36:29.26#ibcon#first serial, iclass 20, count 2 2006.210.07:36:29.26#ibcon#enter sib2, iclass 20, count 2 2006.210.07:36:29.26#ibcon#flushed, iclass 20, count 2 2006.210.07:36:29.26#ibcon#about to write, iclass 20, count 2 2006.210.07:36:29.26#ibcon#wrote, iclass 20, count 2 2006.210.07:36:29.26#ibcon#about to read 3, iclass 20, count 2 2006.210.07:36:29.28#ibcon#read 3, iclass 20, count 2 2006.210.07:36:29.28#ibcon#about to read 4, iclass 20, count 2 2006.210.07:36:29.28#ibcon#read 4, iclass 20, count 2 2006.210.07:36:29.28#ibcon#about to read 5, iclass 20, count 2 2006.210.07:36:29.28#ibcon#read 5, iclass 20, count 2 2006.210.07:36:29.28#ibcon#about to read 6, iclass 20, count 2 2006.210.07:36:29.28#ibcon#read 6, iclass 20, count 2 2006.210.07:36:29.28#ibcon#end of sib2, iclass 20, count 2 2006.210.07:36:29.28#ibcon#*mode == 0, iclass 20, count 2 2006.210.07:36:29.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.07:36:29.28#ibcon#[25=AT06-06\r\n] 2006.210.07:36:29.28#ibcon#*before write, iclass 20, count 2 2006.210.07:36:29.28#ibcon#enter sib2, iclass 20, count 2 2006.210.07:36:29.28#ibcon#flushed, iclass 20, count 2 2006.210.07:36:29.28#ibcon#about to write, iclass 20, count 2 2006.210.07:36:29.28#ibcon#wrote, iclass 20, count 2 2006.210.07:36:29.28#ibcon#about to read 3, iclass 20, count 2 2006.210.07:36:29.31#ibcon#read 3, iclass 20, count 2 2006.210.07:36:29.31#ibcon#about to read 4, iclass 20, count 2 2006.210.07:36:29.31#ibcon#read 4, iclass 20, count 2 2006.210.07:36:29.31#ibcon#about to read 5, iclass 20, count 2 2006.210.07:36:29.31#ibcon#read 5, iclass 20, count 2 2006.210.07:36:29.31#ibcon#about to read 6, iclass 20, count 2 2006.210.07:36:29.31#ibcon#read 6, iclass 20, count 2 2006.210.07:36:29.31#ibcon#end of sib2, iclass 20, count 2 2006.210.07:36:29.31#ibcon#*after write, iclass 20, count 2 2006.210.07:36:29.31#ibcon#*before return 0, iclass 20, count 2 2006.210.07:36:29.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:29.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:29.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.07:36:29.31#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:29.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:29.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:29.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:29.43#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:36:29.43#ibcon#first serial, iclass 20, count 0 2006.210.07:36:29.43#ibcon#enter sib2, iclass 20, count 0 2006.210.07:36:29.43#ibcon#flushed, iclass 20, count 0 2006.210.07:36:29.43#ibcon#about to write, iclass 20, count 0 2006.210.07:36:29.43#ibcon#wrote, iclass 20, count 0 2006.210.07:36:29.43#ibcon#about to read 3, iclass 20, count 0 2006.210.07:36:29.45#ibcon#read 3, iclass 20, count 0 2006.210.07:36:29.45#ibcon#about to read 4, iclass 20, count 0 2006.210.07:36:29.45#ibcon#read 4, iclass 20, count 0 2006.210.07:36:29.45#ibcon#about to read 5, iclass 20, count 0 2006.210.07:36:29.45#ibcon#read 5, iclass 20, count 0 2006.210.07:36:29.45#ibcon#about to read 6, iclass 20, count 0 2006.210.07:36:29.45#ibcon#read 6, iclass 20, count 0 2006.210.07:36:29.45#ibcon#end of sib2, iclass 20, count 0 2006.210.07:36:29.45#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:36:29.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:36:29.45#ibcon#[25=USB\r\n] 2006.210.07:36:29.45#ibcon#*before write, iclass 20, count 0 2006.210.07:36:29.45#ibcon#enter sib2, iclass 20, count 0 2006.210.07:36:29.45#ibcon#flushed, iclass 20, count 0 2006.210.07:36:29.45#ibcon#about to write, iclass 20, count 0 2006.210.07:36:29.45#ibcon#wrote, iclass 20, count 0 2006.210.07:36:29.45#ibcon#about to read 3, iclass 20, count 0 2006.210.07:36:29.48#ibcon#read 3, iclass 20, count 0 2006.210.07:36:29.48#ibcon#about to read 4, iclass 20, count 0 2006.210.07:36:29.48#ibcon#read 4, iclass 20, count 0 2006.210.07:36:29.48#ibcon#about to read 5, iclass 20, count 0 2006.210.07:36:29.48#ibcon#read 5, iclass 20, count 0 2006.210.07:36:29.48#ibcon#about to read 6, iclass 20, count 0 2006.210.07:36:29.48#ibcon#read 6, iclass 20, count 0 2006.210.07:36:29.48#ibcon#end of sib2, iclass 20, count 0 2006.210.07:36:29.48#ibcon#*after write, iclass 20, count 0 2006.210.07:36:29.48#ibcon#*before return 0, iclass 20, count 0 2006.210.07:36:29.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:29.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:29.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:36:29.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:36:29.48$vc4f8/valo=7,832.99 2006.210.07:36:29.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:36:29.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:36:29.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:29.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:29.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:29.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:29.48#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:36:29.48#ibcon#first serial, iclass 22, count 0 2006.210.07:36:29.48#ibcon#enter sib2, iclass 22, count 0 2006.210.07:36:29.48#ibcon#flushed, iclass 22, count 0 2006.210.07:36:29.48#ibcon#about to write, iclass 22, count 0 2006.210.07:36:29.48#ibcon#wrote, iclass 22, count 0 2006.210.07:36:29.48#ibcon#about to read 3, iclass 22, count 0 2006.210.07:36:29.50#ibcon#read 3, iclass 22, count 0 2006.210.07:36:29.50#ibcon#about to read 4, iclass 22, count 0 2006.210.07:36:29.50#ibcon#read 4, iclass 22, count 0 2006.210.07:36:29.50#ibcon#about to read 5, iclass 22, count 0 2006.210.07:36:29.50#ibcon#read 5, iclass 22, count 0 2006.210.07:36:29.50#ibcon#about to read 6, iclass 22, count 0 2006.210.07:36:29.50#ibcon#read 6, iclass 22, count 0 2006.210.07:36:29.50#ibcon#end of sib2, iclass 22, count 0 2006.210.07:36:29.50#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:36:29.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:36:29.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:36:29.50#ibcon#*before write, iclass 22, count 0 2006.210.07:36:29.50#ibcon#enter sib2, iclass 22, count 0 2006.210.07:36:29.50#ibcon#flushed, iclass 22, count 0 2006.210.07:36:29.50#ibcon#about to write, iclass 22, count 0 2006.210.07:36:29.50#ibcon#wrote, iclass 22, count 0 2006.210.07:36:29.50#ibcon#about to read 3, iclass 22, count 0 2006.210.07:36:29.54#ibcon#read 3, iclass 22, count 0 2006.210.07:36:29.54#ibcon#about to read 4, iclass 22, count 0 2006.210.07:36:29.54#ibcon#read 4, iclass 22, count 0 2006.210.07:36:29.54#ibcon#about to read 5, iclass 22, count 0 2006.210.07:36:29.54#ibcon#read 5, iclass 22, count 0 2006.210.07:36:29.54#ibcon#about to read 6, iclass 22, count 0 2006.210.07:36:29.54#ibcon#read 6, iclass 22, count 0 2006.210.07:36:29.54#ibcon#end of sib2, iclass 22, count 0 2006.210.07:36:29.54#ibcon#*after write, iclass 22, count 0 2006.210.07:36:29.54#ibcon#*before return 0, iclass 22, count 0 2006.210.07:36:29.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:29.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:29.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:36:29.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:36:29.54$vc4f8/va=7,6 2006.210.07:36:29.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.07:36:29.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.07:36:29.54#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:29.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:36:29.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:36:29.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:36:29.60#ibcon#enter wrdev, iclass 24, count 2 2006.210.07:36:29.60#ibcon#first serial, iclass 24, count 2 2006.210.07:36:29.60#ibcon#enter sib2, iclass 24, count 2 2006.210.07:36:29.60#ibcon#flushed, iclass 24, count 2 2006.210.07:36:29.60#ibcon#about to write, iclass 24, count 2 2006.210.07:36:29.60#ibcon#wrote, iclass 24, count 2 2006.210.07:36:29.60#ibcon#about to read 3, iclass 24, count 2 2006.210.07:36:29.62#ibcon#read 3, iclass 24, count 2 2006.210.07:36:29.62#ibcon#about to read 4, iclass 24, count 2 2006.210.07:36:29.62#ibcon#read 4, iclass 24, count 2 2006.210.07:36:29.62#ibcon#about to read 5, iclass 24, count 2 2006.210.07:36:29.62#ibcon#read 5, iclass 24, count 2 2006.210.07:36:29.62#ibcon#about to read 6, iclass 24, count 2 2006.210.07:36:29.62#ibcon#read 6, iclass 24, count 2 2006.210.07:36:29.62#ibcon#end of sib2, iclass 24, count 2 2006.210.07:36:29.62#ibcon#*mode == 0, iclass 24, count 2 2006.210.07:36:29.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.07:36:29.62#ibcon#[25=AT07-06\r\n] 2006.210.07:36:29.62#ibcon#*before write, iclass 24, count 2 2006.210.07:36:29.62#ibcon#enter sib2, iclass 24, count 2 2006.210.07:36:29.62#ibcon#flushed, iclass 24, count 2 2006.210.07:36:29.62#ibcon#about to write, iclass 24, count 2 2006.210.07:36:29.62#ibcon#wrote, iclass 24, count 2 2006.210.07:36:29.62#ibcon#about to read 3, iclass 24, count 2 2006.210.07:36:29.65#ibcon#read 3, iclass 24, count 2 2006.210.07:36:29.65#ibcon#about to read 4, iclass 24, count 2 2006.210.07:36:29.65#ibcon#read 4, iclass 24, count 2 2006.210.07:36:29.65#ibcon#about to read 5, iclass 24, count 2 2006.210.07:36:29.65#ibcon#read 5, iclass 24, count 2 2006.210.07:36:29.65#ibcon#about to read 6, iclass 24, count 2 2006.210.07:36:29.65#ibcon#read 6, iclass 24, count 2 2006.210.07:36:29.65#ibcon#end of sib2, iclass 24, count 2 2006.210.07:36:29.65#ibcon#*after write, iclass 24, count 2 2006.210.07:36:29.65#ibcon#*before return 0, iclass 24, count 2 2006.210.07:36:29.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:36:29.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:36:29.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.07:36:29.65#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:29.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:36:29.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:36:29.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:36:29.77#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:36:29.77#ibcon#first serial, iclass 24, count 0 2006.210.07:36:29.77#ibcon#enter sib2, iclass 24, count 0 2006.210.07:36:29.77#ibcon#flushed, iclass 24, count 0 2006.210.07:36:29.77#ibcon#about to write, iclass 24, count 0 2006.210.07:36:29.77#ibcon#wrote, iclass 24, count 0 2006.210.07:36:29.77#ibcon#about to read 3, iclass 24, count 0 2006.210.07:36:29.79#ibcon#read 3, iclass 24, count 0 2006.210.07:36:29.79#ibcon#about to read 4, iclass 24, count 0 2006.210.07:36:29.79#ibcon#read 4, iclass 24, count 0 2006.210.07:36:29.79#ibcon#about to read 5, iclass 24, count 0 2006.210.07:36:29.79#ibcon#read 5, iclass 24, count 0 2006.210.07:36:29.79#ibcon#about to read 6, iclass 24, count 0 2006.210.07:36:29.79#ibcon#read 6, iclass 24, count 0 2006.210.07:36:29.79#ibcon#end of sib2, iclass 24, count 0 2006.210.07:36:29.79#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:36:29.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:36:29.79#ibcon#[25=USB\r\n] 2006.210.07:36:29.79#ibcon#*before write, iclass 24, count 0 2006.210.07:36:29.79#ibcon#enter sib2, iclass 24, count 0 2006.210.07:36:29.79#ibcon#flushed, iclass 24, count 0 2006.210.07:36:29.79#ibcon#about to write, iclass 24, count 0 2006.210.07:36:29.79#ibcon#wrote, iclass 24, count 0 2006.210.07:36:29.79#ibcon#about to read 3, iclass 24, count 0 2006.210.07:36:29.82#ibcon#read 3, iclass 24, count 0 2006.210.07:36:29.82#ibcon#about to read 4, iclass 24, count 0 2006.210.07:36:29.82#ibcon#read 4, iclass 24, count 0 2006.210.07:36:29.82#ibcon#about to read 5, iclass 24, count 0 2006.210.07:36:29.82#ibcon#read 5, iclass 24, count 0 2006.210.07:36:29.82#ibcon#about to read 6, iclass 24, count 0 2006.210.07:36:29.82#ibcon#read 6, iclass 24, count 0 2006.210.07:36:29.82#ibcon#end of sib2, iclass 24, count 0 2006.210.07:36:29.82#ibcon#*after write, iclass 24, count 0 2006.210.07:36:29.82#ibcon#*before return 0, iclass 24, count 0 2006.210.07:36:29.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:36:29.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:36:29.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:36:29.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:36:29.82$vc4f8/valo=8,852.99 2006.210.07:36:29.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:36:29.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:36:29.82#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:29.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:36:29.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:36:29.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:36:29.82#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:36:29.82#ibcon#first serial, iclass 26, count 0 2006.210.07:36:29.82#ibcon#enter sib2, iclass 26, count 0 2006.210.07:36:29.82#ibcon#flushed, iclass 26, count 0 2006.210.07:36:29.82#ibcon#about to write, iclass 26, count 0 2006.210.07:36:29.82#ibcon#wrote, iclass 26, count 0 2006.210.07:36:29.82#ibcon#about to read 3, iclass 26, count 0 2006.210.07:36:29.84#ibcon#read 3, iclass 26, count 0 2006.210.07:36:29.84#ibcon#about to read 4, iclass 26, count 0 2006.210.07:36:29.84#ibcon#read 4, iclass 26, count 0 2006.210.07:36:29.84#ibcon#about to read 5, iclass 26, count 0 2006.210.07:36:29.84#ibcon#read 5, iclass 26, count 0 2006.210.07:36:29.84#ibcon#about to read 6, iclass 26, count 0 2006.210.07:36:29.84#ibcon#read 6, iclass 26, count 0 2006.210.07:36:29.84#ibcon#end of sib2, iclass 26, count 0 2006.210.07:36:29.84#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:36:29.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:36:29.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:36:29.84#ibcon#*before write, iclass 26, count 0 2006.210.07:36:29.84#ibcon#enter sib2, iclass 26, count 0 2006.210.07:36:29.84#ibcon#flushed, iclass 26, count 0 2006.210.07:36:29.84#ibcon#about to write, iclass 26, count 0 2006.210.07:36:29.84#ibcon#wrote, iclass 26, count 0 2006.210.07:36:29.84#ibcon#about to read 3, iclass 26, count 0 2006.210.07:36:29.88#ibcon#read 3, iclass 26, count 0 2006.210.07:36:29.88#ibcon#about to read 4, iclass 26, count 0 2006.210.07:36:29.88#ibcon#read 4, iclass 26, count 0 2006.210.07:36:29.88#ibcon#about to read 5, iclass 26, count 0 2006.210.07:36:29.88#ibcon#read 5, iclass 26, count 0 2006.210.07:36:29.88#ibcon#about to read 6, iclass 26, count 0 2006.210.07:36:29.88#ibcon#read 6, iclass 26, count 0 2006.210.07:36:29.88#ibcon#end of sib2, iclass 26, count 0 2006.210.07:36:29.88#ibcon#*after write, iclass 26, count 0 2006.210.07:36:29.88#ibcon#*before return 0, iclass 26, count 0 2006.210.07:36:29.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:36:29.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:36:29.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:36:29.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:36:29.88$vc4f8/va=8,7 2006.210.07:36:29.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.07:36:29.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.07:36:29.88#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:29.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:36:29.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:36:29.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:36:29.94#ibcon#enter wrdev, iclass 28, count 2 2006.210.07:36:29.94#ibcon#first serial, iclass 28, count 2 2006.210.07:36:29.94#ibcon#enter sib2, iclass 28, count 2 2006.210.07:36:29.94#ibcon#flushed, iclass 28, count 2 2006.210.07:36:29.94#ibcon#about to write, iclass 28, count 2 2006.210.07:36:29.94#ibcon#wrote, iclass 28, count 2 2006.210.07:36:29.94#ibcon#about to read 3, iclass 28, count 2 2006.210.07:36:29.96#ibcon#read 3, iclass 28, count 2 2006.210.07:36:29.96#ibcon#about to read 4, iclass 28, count 2 2006.210.07:36:29.96#ibcon#read 4, iclass 28, count 2 2006.210.07:36:29.96#ibcon#about to read 5, iclass 28, count 2 2006.210.07:36:29.96#ibcon#read 5, iclass 28, count 2 2006.210.07:36:29.96#ibcon#about to read 6, iclass 28, count 2 2006.210.07:36:29.96#ibcon#read 6, iclass 28, count 2 2006.210.07:36:29.96#ibcon#end of sib2, iclass 28, count 2 2006.210.07:36:29.96#ibcon#*mode == 0, iclass 28, count 2 2006.210.07:36:29.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.07:36:29.96#ibcon#[25=AT08-07\r\n] 2006.210.07:36:29.96#ibcon#*before write, iclass 28, count 2 2006.210.07:36:29.96#ibcon#enter sib2, iclass 28, count 2 2006.210.07:36:29.96#ibcon#flushed, iclass 28, count 2 2006.210.07:36:29.96#ibcon#about to write, iclass 28, count 2 2006.210.07:36:29.96#ibcon#wrote, iclass 28, count 2 2006.210.07:36:29.96#ibcon#about to read 3, iclass 28, count 2 2006.210.07:36:29.99#ibcon#read 3, iclass 28, count 2 2006.210.07:36:29.99#ibcon#about to read 4, iclass 28, count 2 2006.210.07:36:29.99#ibcon#read 4, iclass 28, count 2 2006.210.07:36:29.99#ibcon#about to read 5, iclass 28, count 2 2006.210.07:36:29.99#ibcon#read 5, iclass 28, count 2 2006.210.07:36:29.99#ibcon#about to read 6, iclass 28, count 2 2006.210.07:36:29.99#ibcon#read 6, iclass 28, count 2 2006.210.07:36:29.99#ibcon#end of sib2, iclass 28, count 2 2006.210.07:36:29.99#ibcon#*after write, iclass 28, count 2 2006.210.07:36:29.99#ibcon#*before return 0, iclass 28, count 2 2006.210.07:36:29.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:36:29.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:36:29.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.07:36:29.99#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:29.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:36:30.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:36:30.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:36:30.11#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:36:30.11#ibcon#first serial, iclass 28, count 0 2006.210.07:36:30.11#ibcon#enter sib2, iclass 28, count 0 2006.210.07:36:30.11#ibcon#flushed, iclass 28, count 0 2006.210.07:36:30.11#ibcon#about to write, iclass 28, count 0 2006.210.07:36:30.11#ibcon#wrote, iclass 28, count 0 2006.210.07:36:30.11#ibcon#about to read 3, iclass 28, count 0 2006.210.07:36:30.13#ibcon#read 3, iclass 28, count 0 2006.210.07:36:30.13#ibcon#about to read 4, iclass 28, count 0 2006.210.07:36:30.13#ibcon#read 4, iclass 28, count 0 2006.210.07:36:30.13#ibcon#about to read 5, iclass 28, count 0 2006.210.07:36:30.13#ibcon#read 5, iclass 28, count 0 2006.210.07:36:30.13#ibcon#about to read 6, iclass 28, count 0 2006.210.07:36:30.13#ibcon#read 6, iclass 28, count 0 2006.210.07:36:30.13#ibcon#end of sib2, iclass 28, count 0 2006.210.07:36:30.13#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:36:30.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:36:30.13#ibcon#[25=USB\r\n] 2006.210.07:36:30.13#ibcon#*before write, iclass 28, count 0 2006.210.07:36:30.13#ibcon#enter sib2, iclass 28, count 0 2006.210.07:36:30.13#ibcon#flushed, iclass 28, count 0 2006.210.07:36:30.13#ibcon#about to write, iclass 28, count 0 2006.210.07:36:30.13#ibcon#wrote, iclass 28, count 0 2006.210.07:36:30.13#ibcon#about to read 3, iclass 28, count 0 2006.210.07:36:30.16#ibcon#read 3, iclass 28, count 0 2006.210.07:36:30.16#ibcon#about to read 4, iclass 28, count 0 2006.210.07:36:30.16#ibcon#read 4, iclass 28, count 0 2006.210.07:36:30.16#ibcon#about to read 5, iclass 28, count 0 2006.210.07:36:30.16#ibcon#read 5, iclass 28, count 0 2006.210.07:36:30.16#ibcon#about to read 6, iclass 28, count 0 2006.210.07:36:30.16#ibcon#read 6, iclass 28, count 0 2006.210.07:36:30.16#ibcon#end of sib2, iclass 28, count 0 2006.210.07:36:30.16#ibcon#*after write, iclass 28, count 0 2006.210.07:36:30.16#ibcon#*before return 0, iclass 28, count 0 2006.210.07:36:30.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:36:30.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:36:30.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:36:30.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:36:30.16$vc4f8/vblo=1,632.99 2006.210.07:36:30.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.07:36:30.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.07:36:30.16#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:30.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:36:30.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:36:30.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:36:30.16#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:36:30.16#ibcon#first serial, iclass 30, count 0 2006.210.07:36:30.16#ibcon#enter sib2, iclass 30, count 0 2006.210.07:36:30.16#ibcon#flushed, iclass 30, count 0 2006.210.07:36:30.16#ibcon#about to write, iclass 30, count 0 2006.210.07:36:30.16#ibcon#wrote, iclass 30, count 0 2006.210.07:36:30.16#ibcon#about to read 3, iclass 30, count 0 2006.210.07:36:30.18#ibcon#read 3, iclass 30, count 0 2006.210.07:36:30.18#ibcon#about to read 4, iclass 30, count 0 2006.210.07:36:30.18#ibcon#read 4, iclass 30, count 0 2006.210.07:36:30.18#ibcon#about to read 5, iclass 30, count 0 2006.210.07:36:30.18#ibcon#read 5, iclass 30, count 0 2006.210.07:36:30.18#ibcon#about to read 6, iclass 30, count 0 2006.210.07:36:30.18#ibcon#read 6, iclass 30, count 0 2006.210.07:36:30.18#ibcon#end of sib2, iclass 30, count 0 2006.210.07:36:30.18#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:36:30.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:36:30.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:36:30.18#ibcon#*before write, iclass 30, count 0 2006.210.07:36:30.18#ibcon#enter sib2, iclass 30, count 0 2006.210.07:36:30.18#ibcon#flushed, iclass 30, count 0 2006.210.07:36:30.18#ibcon#about to write, iclass 30, count 0 2006.210.07:36:30.18#ibcon#wrote, iclass 30, count 0 2006.210.07:36:30.18#ibcon#about to read 3, iclass 30, count 0 2006.210.07:36:30.22#ibcon#read 3, iclass 30, count 0 2006.210.07:36:30.22#ibcon#about to read 4, iclass 30, count 0 2006.210.07:36:30.22#ibcon#read 4, iclass 30, count 0 2006.210.07:36:30.22#ibcon#about to read 5, iclass 30, count 0 2006.210.07:36:30.22#ibcon#read 5, iclass 30, count 0 2006.210.07:36:30.22#ibcon#about to read 6, iclass 30, count 0 2006.210.07:36:30.22#ibcon#read 6, iclass 30, count 0 2006.210.07:36:30.22#ibcon#end of sib2, iclass 30, count 0 2006.210.07:36:30.22#ibcon#*after write, iclass 30, count 0 2006.210.07:36:30.22#ibcon#*before return 0, iclass 30, count 0 2006.210.07:36:30.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:36:30.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:36:30.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:36:30.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:36:30.22$vc4f8/vb=1,4 2006.210.07:36:30.22#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.07:36:30.22#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.07:36:30.22#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:30.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:36:30.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:36:30.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:36:30.22#ibcon#enter wrdev, iclass 32, count 2 2006.210.07:36:30.22#ibcon#first serial, iclass 32, count 2 2006.210.07:36:30.22#ibcon#enter sib2, iclass 32, count 2 2006.210.07:36:30.22#ibcon#flushed, iclass 32, count 2 2006.210.07:36:30.22#ibcon#about to write, iclass 32, count 2 2006.210.07:36:30.22#ibcon#wrote, iclass 32, count 2 2006.210.07:36:30.22#ibcon#about to read 3, iclass 32, count 2 2006.210.07:36:30.24#ibcon#read 3, iclass 32, count 2 2006.210.07:36:30.24#ibcon#about to read 4, iclass 32, count 2 2006.210.07:36:30.24#ibcon#read 4, iclass 32, count 2 2006.210.07:36:30.24#ibcon#about to read 5, iclass 32, count 2 2006.210.07:36:30.24#ibcon#read 5, iclass 32, count 2 2006.210.07:36:30.24#ibcon#about to read 6, iclass 32, count 2 2006.210.07:36:30.24#ibcon#read 6, iclass 32, count 2 2006.210.07:36:30.24#ibcon#end of sib2, iclass 32, count 2 2006.210.07:36:30.24#ibcon#*mode == 0, iclass 32, count 2 2006.210.07:36:30.24#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.07:36:30.24#ibcon#[27=AT01-04\r\n] 2006.210.07:36:30.24#ibcon#*before write, iclass 32, count 2 2006.210.07:36:30.24#ibcon#enter sib2, iclass 32, count 2 2006.210.07:36:30.24#ibcon#flushed, iclass 32, count 2 2006.210.07:36:30.24#ibcon#about to write, iclass 32, count 2 2006.210.07:36:30.24#ibcon#wrote, iclass 32, count 2 2006.210.07:36:30.24#ibcon#about to read 3, iclass 32, count 2 2006.210.07:36:30.27#ibcon#read 3, iclass 32, count 2 2006.210.07:36:30.27#ibcon#about to read 4, iclass 32, count 2 2006.210.07:36:30.27#ibcon#read 4, iclass 32, count 2 2006.210.07:36:30.27#ibcon#about to read 5, iclass 32, count 2 2006.210.07:36:30.27#ibcon#read 5, iclass 32, count 2 2006.210.07:36:30.27#ibcon#about to read 6, iclass 32, count 2 2006.210.07:36:30.27#ibcon#read 6, iclass 32, count 2 2006.210.07:36:30.27#ibcon#end of sib2, iclass 32, count 2 2006.210.07:36:30.27#ibcon#*after write, iclass 32, count 2 2006.210.07:36:30.27#ibcon#*before return 0, iclass 32, count 2 2006.210.07:36:30.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:36:30.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:36:30.27#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.07:36:30.27#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:30.27#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:36:30.39#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:36:30.39#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:36:30.39#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:36:30.39#ibcon#first serial, iclass 32, count 0 2006.210.07:36:30.39#ibcon#enter sib2, iclass 32, count 0 2006.210.07:36:30.39#ibcon#flushed, iclass 32, count 0 2006.210.07:36:30.39#ibcon#about to write, iclass 32, count 0 2006.210.07:36:30.39#ibcon#wrote, iclass 32, count 0 2006.210.07:36:30.39#ibcon#about to read 3, iclass 32, count 0 2006.210.07:36:30.41#ibcon#read 3, iclass 32, count 0 2006.210.07:36:30.41#ibcon#about to read 4, iclass 32, count 0 2006.210.07:36:30.41#ibcon#read 4, iclass 32, count 0 2006.210.07:36:30.41#ibcon#about to read 5, iclass 32, count 0 2006.210.07:36:30.41#ibcon#read 5, iclass 32, count 0 2006.210.07:36:30.41#ibcon#about to read 6, iclass 32, count 0 2006.210.07:36:30.41#ibcon#read 6, iclass 32, count 0 2006.210.07:36:30.41#ibcon#end of sib2, iclass 32, count 0 2006.210.07:36:30.41#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:36:30.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:36:30.41#ibcon#[27=USB\r\n] 2006.210.07:36:30.41#ibcon#*before write, iclass 32, count 0 2006.210.07:36:30.41#ibcon#enter sib2, iclass 32, count 0 2006.210.07:36:30.41#ibcon#flushed, iclass 32, count 0 2006.210.07:36:30.41#ibcon#about to write, iclass 32, count 0 2006.210.07:36:30.41#ibcon#wrote, iclass 32, count 0 2006.210.07:36:30.41#ibcon#about to read 3, iclass 32, count 0 2006.210.07:36:30.44#ibcon#read 3, iclass 32, count 0 2006.210.07:36:30.44#ibcon#about to read 4, iclass 32, count 0 2006.210.07:36:30.44#ibcon#read 4, iclass 32, count 0 2006.210.07:36:30.44#ibcon#about to read 5, iclass 32, count 0 2006.210.07:36:30.44#ibcon#read 5, iclass 32, count 0 2006.210.07:36:30.44#ibcon#about to read 6, iclass 32, count 0 2006.210.07:36:30.44#ibcon#read 6, iclass 32, count 0 2006.210.07:36:30.44#ibcon#end of sib2, iclass 32, count 0 2006.210.07:36:30.44#ibcon#*after write, iclass 32, count 0 2006.210.07:36:30.44#ibcon#*before return 0, iclass 32, count 0 2006.210.07:36:30.44#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:36:30.44#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:36:30.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:36:30.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:36:30.44$vc4f8/vblo=2,640.99 2006.210.07:36:30.44#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.07:36:30.44#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.07:36:30.44#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:30.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:30.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:30.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:30.44#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:36:30.44#ibcon#first serial, iclass 34, count 0 2006.210.07:36:30.44#ibcon#enter sib2, iclass 34, count 0 2006.210.07:36:30.44#ibcon#flushed, iclass 34, count 0 2006.210.07:36:30.44#ibcon#about to write, iclass 34, count 0 2006.210.07:36:30.44#ibcon#wrote, iclass 34, count 0 2006.210.07:36:30.44#ibcon#about to read 3, iclass 34, count 0 2006.210.07:36:30.46#ibcon#read 3, iclass 34, count 0 2006.210.07:36:30.46#ibcon#about to read 4, iclass 34, count 0 2006.210.07:36:30.46#ibcon#read 4, iclass 34, count 0 2006.210.07:36:30.46#ibcon#about to read 5, iclass 34, count 0 2006.210.07:36:30.46#ibcon#read 5, iclass 34, count 0 2006.210.07:36:30.46#ibcon#about to read 6, iclass 34, count 0 2006.210.07:36:30.46#ibcon#read 6, iclass 34, count 0 2006.210.07:36:30.46#ibcon#end of sib2, iclass 34, count 0 2006.210.07:36:30.46#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:36:30.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:36:30.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:36:30.46#ibcon#*before write, iclass 34, count 0 2006.210.07:36:30.46#ibcon#enter sib2, iclass 34, count 0 2006.210.07:36:30.46#ibcon#flushed, iclass 34, count 0 2006.210.07:36:30.46#ibcon#about to write, iclass 34, count 0 2006.210.07:36:30.46#ibcon#wrote, iclass 34, count 0 2006.210.07:36:30.46#ibcon#about to read 3, iclass 34, count 0 2006.210.07:36:30.50#ibcon#read 3, iclass 34, count 0 2006.210.07:36:30.50#ibcon#about to read 4, iclass 34, count 0 2006.210.07:36:30.50#ibcon#read 4, iclass 34, count 0 2006.210.07:36:30.50#ibcon#about to read 5, iclass 34, count 0 2006.210.07:36:30.50#ibcon#read 5, iclass 34, count 0 2006.210.07:36:30.50#ibcon#about to read 6, iclass 34, count 0 2006.210.07:36:30.50#ibcon#read 6, iclass 34, count 0 2006.210.07:36:30.50#ibcon#end of sib2, iclass 34, count 0 2006.210.07:36:30.50#ibcon#*after write, iclass 34, count 0 2006.210.07:36:30.50#ibcon#*before return 0, iclass 34, count 0 2006.210.07:36:30.50#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:30.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:36:30.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:36:30.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:36:30.50$vc4f8/vb=2,4 2006.210.07:36:30.50#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.07:36:30.50#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.07:36:30.50#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:30.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:30.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:30.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:30.56#ibcon#enter wrdev, iclass 36, count 2 2006.210.07:36:30.56#ibcon#first serial, iclass 36, count 2 2006.210.07:36:30.56#ibcon#enter sib2, iclass 36, count 2 2006.210.07:36:30.56#ibcon#flushed, iclass 36, count 2 2006.210.07:36:30.56#ibcon#about to write, iclass 36, count 2 2006.210.07:36:30.56#ibcon#wrote, iclass 36, count 2 2006.210.07:36:30.56#ibcon#about to read 3, iclass 36, count 2 2006.210.07:36:30.58#ibcon#read 3, iclass 36, count 2 2006.210.07:36:30.58#ibcon#about to read 4, iclass 36, count 2 2006.210.07:36:30.58#ibcon#read 4, iclass 36, count 2 2006.210.07:36:30.58#ibcon#about to read 5, iclass 36, count 2 2006.210.07:36:30.58#ibcon#read 5, iclass 36, count 2 2006.210.07:36:30.58#ibcon#about to read 6, iclass 36, count 2 2006.210.07:36:30.58#ibcon#read 6, iclass 36, count 2 2006.210.07:36:30.58#ibcon#end of sib2, iclass 36, count 2 2006.210.07:36:30.58#ibcon#*mode == 0, iclass 36, count 2 2006.210.07:36:30.58#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.07:36:30.58#ibcon#[27=AT02-04\r\n] 2006.210.07:36:30.58#ibcon#*before write, iclass 36, count 2 2006.210.07:36:30.58#ibcon#enter sib2, iclass 36, count 2 2006.210.07:36:30.58#ibcon#flushed, iclass 36, count 2 2006.210.07:36:30.58#ibcon#about to write, iclass 36, count 2 2006.210.07:36:30.58#ibcon#wrote, iclass 36, count 2 2006.210.07:36:30.58#ibcon#about to read 3, iclass 36, count 2 2006.210.07:36:30.61#ibcon#read 3, iclass 36, count 2 2006.210.07:36:30.61#ibcon#about to read 4, iclass 36, count 2 2006.210.07:36:30.61#ibcon#read 4, iclass 36, count 2 2006.210.07:36:30.61#ibcon#about to read 5, iclass 36, count 2 2006.210.07:36:30.61#ibcon#read 5, iclass 36, count 2 2006.210.07:36:30.61#ibcon#about to read 6, iclass 36, count 2 2006.210.07:36:30.61#ibcon#read 6, iclass 36, count 2 2006.210.07:36:30.61#ibcon#end of sib2, iclass 36, count 2 2006.210.07:36:30.61#ibcon#*after write, iclass 36, count 2 2006.210.07:36:30.61#ibcon#*before return 0, iclass 36, count 2 2006.210.07:36:30.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:30.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:36:30.61#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.07:36:30.61#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:30.61#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:30.73#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:30.73#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:30.73#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:36:30.73#ibcon#first serial, iclass 36, count 0 2006.210.07:36:30.73#ibcon#enter sib2, iclass 36, count 0 2006.210.07:36:30.73#ibcon#flushed, iclass 36, count 0 2006.210.07:36:30.73#ibcon#about to write, iclass 36, count 0 2006.210.07:36:30.73#ibcon#wrote, iclass 36, count 0 2006.210.07:36:30.73#ibcon#about to read 3, iclass 36, count 0 2006.210.07:36:30.75#ibcon#read 3, iclass 36, count 0 2006.210.07:36:30.75#ibcon#about to read 4, iclass 36, count 0 2006.210.07:36:30.75#ibcon#read 4, iclass 36, count 0 2006.210.07:36:30.75#ibcon#about to read 5, iclass 36, count 0 2006.210.07:36:30.75#ibcon#read 5, iclass 36, count 0 2006.210.07:36:30.75#ibcon#about to read 6, iclass 36, count 0 2006.210.07:36:30.75#ibcon#read 6, iclass 36, count 0 2006.210.07:36:30.75#ibcon#end of sib2, iclass 36, count 0 2006.210.07:36:30.75#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:36:30.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:36:30.75#ibcon#[27=USB\r\n] 2006.210.07:36:30.75#ibcon#*before write, iclass 36, count 0 2006.210.07:36:30.75#ibcon#enter sib2, iclass 36, count 0 2006.210.07:36:30.75#ibcon#flushed, iclass 36, count 0 2006.210.07:36:30.75#ibcon#about to write, iclass 36, count 0 2006.210.07:36:30.75#ibcon#wrote, iclass 36, count 0 2006.210.07:36:30.75#ibcon#about to read 3, iclass 36, count 0 2006.210.07:36:30.78#ibcon#read 3, iclass 36, count 0 2006.210.07:36:30.78#ibcon#about to read 4, iclass 36, count 0 2006.210.07:36:30.78#ibcon#read 4, iclass 36, count 0 2006.210.07:36:30.78#ibcon#about to read 5, iclass 36, count 0 2006.210.07:36:30.78#ibcon#read 5, iclass 36, count 0 2006.210.07:36:30.78#ibcon#about to read 6, iclass 36, count 0 2006.210.07:36:30.78#ibcon#read 6, iclass 36, count 0 2006.210.07:36:30.78#ibcon#end of sib2, iclass 36, count 0 2006.210.07:36:30.78#ibcon#*after write, iclass 36, count 0 2006.210.07:36:30.78#ibcon#*before return 0, iclass 36, count 0 2006.210.07:36:30.78#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:30.78#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:36:30.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:36:30.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:36:30.78$vc4f8/vblo=3,656.99 2006.210.07:36:30.78#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.07:36:30.78#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.07:36:30.78#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:30.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:30.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:30.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:30.78#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:36:30.78#ibcon#first serial, iclass 38, count 0 2006.210.07:36:30.78#ibcon#enter sib2, iclass 38, count 0 2006.210.07:36:30.78#ibcon#flushed, iclass 38, count 0 2006.210.07:36:30.78#ibcon#about to write, iclass 38, count 0 2006.210.07:36:30.78#ibcon#wrote, iclass 38, count 0 2006.210.07:36:30.78#ibcon#about to read 3, iclass 38, count 0 2006.210.07:36:30.80#ibcon#read 3, iclass 38, count 0 2006.210.07:36:30.80#ibcon#about to read 4, iclass 38, count 0 2006.210.07:36:30.80#ibcon#read 4, iclass 38, count 0 2006.210.07:36:30.80#ibcon#about to read 5, iclass 38, count 0 2006.210.07:36:30.80#ibcon#read 5, iclass 38, count 0 2006.210.07:36:30.80#ibcon#about to read 6, iclass 38, count 0 2006.210.07:36:30.80#ibcon#read 6, iclass 38, count 0 2006.210.07:36:30.80#ibcon#end of sib2, iclass 38, count 0 2006.210.07:36:30.80#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:36:30.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:36:30.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:36:30.80#ibcon#*before write, iclass 38, count 0 2006.210.07:36:30.80#ibcon#enter sib2, iclass 38, count 0 2006.210.07:36:30.80#ibcon#flushed, iclass 38, count 0 2006.210.07:36:30.80#ibcon#about to write, iclass 38, count 0 2006.210.07:36:30.80#ibcon#wrote, iclass 38, count 0 2006.210.07:36:30.80#ibcon#about to read 3, iclass 38, count 0 2006.210.07:36:30.84#ibcon#read 3, iclass 38, count 0 2006.210.07:36:30.84#ibcon#about to read 4, iclass 38, count 0 2006.210.07:36:30.84#ibcon#read 4, iclass 38, count 0 2006.210.07:36:30.84#ibcon#about to read 5, iclass 38, count 0 2006.210.07:36:30.84#ibcon#read 5, iclass 38, count 0 2006.210.07:36:30.84#ibcon#about to read 6, iclass 38, count 0 2006.210.07:36:30.84#ibcon#read 6, iclass 38, count 0 2006.210.07:36:30.84#ibcon#end of sib2, iclass 38, count 0 2006.210.07:36:30.84#ibcon#*after write, iclass 38, count 0 2006.210.07:36:30.84#ibcon#*before return 0, iclass 38, count 0 2006.210.07:36:30.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:30.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:36:30.84#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:36:30.84#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:36:30.84$vc4f8/vb=3,3 2006.210.07:36:30.84#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.07:36:30.84#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.07:36:30.84#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:30.84#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:30.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:30.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:30.90#ibcon#enter wrdev, iclass 40, count 2 2006.210.07:36:30.90#ibcon#first serial, iclass 40, count 2 2006.210.07:36:30.90#ibcon#enter sib2, iclass 40, count 2 2006.210.07:36:30.90#ibcon#flushed, iclass 40, count 2 2006.210.07:36:30.90#ibcon#about to write, iclass 40, count 2 2006.210.07:36:30.90#ibcon#wrote, iclass 40, count 2 2006.210.07:36:30.90#ibcon#about to read 3, iclass 40, count 2 2006.210.07:36:30.92#ibcon#read 3, iclass 40, count 2 2006.210.07:36:30.92#ibcon#about to read 4, iclass 40, count 2 2006.210.07:36:30.92#ibcon#read 4, iclass 40, count 2 2006.210.07:36:30.92#ibcon#about to read 5, iclass 40, count 2 2006.210.07:36:30.92#ibcon#read 5, iclass 40, count 2 2006.210.07:36:30.92#ibcon#about to read 6, iclass 40, count 2 2006.210.07:36:30.92#ibcon#read 6, iclass 40, count 2 2006.210.07:36:30.92#ibcon#end of sib2, iclass 40, count 2 2006.210.07:36:30.92#ibcon#*mode == 0, iclass 40, count 2 2006.210.07:36:30.92#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.07:36:30.92#ibcon#[27=AT03-03\r\n] 2006.210.07:36:30.92#ibcon#*before write, iclass 40, count 2 2006.210.07:36:30.92#ibcon#enter sib2, iclass 40, count 2 2006.210.07:36:30.92#ibcon#flushed, iclass 40, count 2 2006.210.07:36:30.92#ibcon#about to write, iclass 40, count 2 2006.210.07:36:30.92#ibcon#wrote, iclass 40, count 2 2006.210.07:36:30.92#ibcon#about to read 3, iclass 40, count 2 2006.210.07:36:30.95#ibcon#read 3, iclass 40, count 2 2006.210.07:36:30.95#ibcon#about to read 4, iclass 40, count 2 2006.210.07:36:30.95#ibcon#read 4, iclass 40, count 2 2006.210.07:36:30.95#ibcon#about to read 5, iclass 40, count 2 2006.210.07:36:30.95#ibcon#read 5, iclass 40, count 2 2006.210.07:36:30.95#ibcon#about to read 6, iclass 40, count 2 2006.210.07:36:30.95#ibcon#read 6, iclass 40, count 2 2006.210.07:36:30.95#ibcon#end of sib2, iclass 40, count 2 2006.210.07:36:30.95#ibcon#*after write, iclass 40, count 2 2006.210.07:36:30.95#ibcon#*before return 0, iclass 40, count 2 2006.210.07:36:30.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:30.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:36:30.95#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.07:36:30.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:30.95#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:31.07#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:31.07#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:31.07#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:36:31.07#ibcon#first serial, iclass 40, count 0 2006.210.07:36:31.07#ibcon#enter sib2, iclass 40, count 0 2006.210.07:36:31.07#ibcon#flushed, iclass 40, count 0 2006.210.07:36:31.07#ibcon#about to write, iclass 40, count 0 2006.210.07:36:31.07#ibcon#wrote, iclass 40, count 0 2006.210.07:36:31.07#ibcon#about to read 3, iclass 40, count 0 2006.210.07:36:31.09#ibcon#read 3, iclass 40, count 0 2006.210.07:36:31.09#ibcon#about to read 4, iclass 40, count 0 2006.210.07:36:31.09#ibcon#read 4, iclass 40, count 0 2006.210.07:36:31.09#ibcon#about to read 5, iclass 40, count 0 2006.210.07:36:31.09#ibcon#read 5, iclass 40, count 0 2006.210.07:36:31.09#ibcon#about to read 6, iclass 40, count 0 2006.210.07:36:31.09#ibcon#read 6, iclass 40, count 0 2006.210.07:36:31.09#ibcon#end of sib2, iclass 40, count 0 2006.210.07:36:31.09#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:36:31.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:36:31.09#ibcon#[27=USB\r\n] 2006.210.07:36:31.09#ibcon#*before write, iclass 40, count 0 2006.210.07:36:31.09#ibcon#enter sib2, iclass 40, count 0 2006.210.07:36:31.09#ibcon#flushed, iclass 40, count 0 2006.210.07:36:31.09#ibcon#about to write, iclass 40, count 0 2006.210.07:36:31.09#ibcon#wrote, iclass 40, count 0 2006.210.07:36:31.09#ibcon#about to read 3, iclass 40, count 0 2006.210.07:36:31.12#ibcon#read 3, iclass 40, count 0 2006.210.07:36:31.12#ibcon#about to read 4, iclass 40, count 0 2006.210.07:36:31.12#ibcon#read 4, iclass 40, count 0 2006.210.07:36:31.12#ibcon#about to read 5, iclass 40, count 0 2006.210.07:36:31.12#ibcon#read 5, iclass 40, count 0 2006.210.07:36:31.12#ibcon#about to read 6, iclass 40, count 0 2006.210.07:36:31.12#ibcon#read 6, iclass 40, count 0 2006.210.07:36:31.12#ibcon#end of sib2, iclass 40, count 0 2006.210.07:36:31.12#ibcon#*after write, iclass 40, count 0 2006.210.07:36:31.12#ibcon#*before return 0, iclass 40, count 0 2006.210.07:36:31.12#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:31.12#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:36:31.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:36:31.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:36:31.12$vc4f8/vblo=4,712.99 2006.210.07:36:31.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.07:36:31.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.07:36:31.12#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:31.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:31.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:31.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:31.12#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:36:31.12#ibcon#first serial, iclass 4, count 0 2006.210.07:36:31.12#ibcon#enter sib2, iclass 4, count 0 2006.210.07:36:31.12#ibcon#flushed, iclass 4, count 0 2006.210.07:36:31.12#ibcon#about to write, iclass 4, count 0 2006.210.07:36:31.12#ibcon#wrote, iclass 4, count 0 2006.210.07:36:31.12#ibcon#about to read 3, iclass 4, count 0 2006.210.07:36:31.14#ibcon#read 3, iclass 4, count 0 2006.210.07:36:31.14#ibcon#about to read 4, iclass 4, count 0 2006.210.07:36:31.14#ibcon#read 4, iclass 4, count 0 2006.210.07:36:31.14#ibcon#about to read 5, iclass 4, count 0 2006.210.07:36:31.14#ibcon#read 5, iclass 4, count 0 2006.210.07:36:31.14#ibcon#about to read 6, iclass 4, count 0 2006.210.07:36:31.14#ibcon#read 6, iclass 4, count 0 2006.210.07:36:31.14#ibcon#end of sib2, iclass 4, count 0 2006.210.07:36:31.14#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:36:31.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:36:31.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:36:31.14#ibcon#*before write, iclass 4, count 0 2006.210.07:36:31.14#ibcon#enter sib2, iclass 4, count 0 2006.210.07:36:31.14#ibcon#flushed, iclass 4, count 0 2006.210.07:36:31.14#ibcon#about to write, iclass 4, count 0 2006.210.07:36:31.14#ibcon#wrote, iclass 4, count 0 2006.210.07:36:31.14#ibcon#about to read 3, iclass 4, count 0 2006.210.07:36:31.18#ibcon#read 3, iclass 4, count 0 2006.210.07:36:31.18#ibcon#about to read 4, iclass 4, count 0 2006.210.07:36:31.18#ibcon#read 4, iclass 4, count 0 2006.210.07:36:31.18#ibcon#about to read 5, iclass 4, count 0 2006.210.07:36:31.18#ibcon#read 5, iclass 4, count 0 2006.210.07:36:31.18#ibcon#about to read 6, iclass 4, count 0 2006.210.07:36:31.18#ibcon#read 6, iclass 4, count 0 2006.210.07:36:31.18#ibcon#end of sib2, iclass 4, count 0 2006.210.07:36:31.18#ibcon#*after write, iclass 4, count 0 2006.210.07:36:31.18#ibcon#*before return 0, iclass 4, count 0 2006.210.07:36:31.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:31.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:36:31.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:36:31.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:36:31.18$vc4f8/vb=4,3 2006.210.07:36:31.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.07:36:31.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.07:36:31.18#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:31.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:31.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:31.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:31.24#ibcon#enter wrdev, iclass 6, count 2 2006.210.07:36:31.24#ibcon#first serial, iclass 6, count 2 2006.210.07:36:31.24#ibcon#enter sib2, iclass 6, count 2 2006.210.07:36:31.24#ibcon#flushed, iclass 6, count 2 2006.210.07:36:31.24#ibcon#about to write, iclass 6, count 2 2006.210.07:36:31.24#ibcon#wrote, iclass 6, count 2 2006.210.07:36:31.24#ibcon#about to read 3, iclass 6, count 2 2006.210.07:36:31.26#ibcon#read 3, iclass 6, count 2 2006.210.07:36:31.26#ibcon#about to read 4, iclass 6, count 2 2006.210.07:36:31.26#ibcon#read 4, iclass 6, count 2 2006.210.07:36:31.26#ibcon#about to read 5, iclass 6, count 2 2006.210.07:36:31.26#ibcon#read 5, iclass 6, count 2 2006.210.07:36:31.26#ibcon#about to read 6, iclass 6, count 2 2006.210.07:36:31.26#ibcon#read 6, iclass 6, count 2 2006.210.07:36:31.26#ibcon#end of sib2, iclass 6, count 2 2006.210.07:36:31.26#ibcon#*mode == 0, iclass 6, count 2 2006.210.07:36:31.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.07:36:31.26#ibcon#[27=AT04-03\r\n] 2006.210.07:36:31.26#ibcon#*before write, iclass 6, count 2 2006.210.07:36:31.26#ibcon#enter sib2, iclass 6, count 2 2006.210.07:36:31.26#ibcon#flushed, iclass 6, count 2 2006.210.07:36:31.26#ibcon#about to write, iclass 6, count 2 2006.210.07:36:31.26#ibcon#wrote, iclass 6, count 2 2006.210.07:36:31.26#ibcon#about to read 3, iclass 6, count 2 2006.210.07:36:31.29#ibcon#read 3, iclass 6, count 2 2006.210.07:36:31.29#ibcon#about to read 4, iclass 6, count 2 2006.210.07:36:31.29#ibcon#read 4, iclass 6, count 2 2006.210.07:36:31.29#ibcon#about to read 5, iclass 6, count 2 2006.210.07:36:31.29#ibcon#read 5, iclass 6, count 2 2006.210.07:36:31.29#ibcon#about to read 6, iclass 6, count 2 2006.210.07:36:31.29#ibcon#read 6, iclass 6, count 2 2006.210.07:36:31.29#ibcon#end of sib2, iclass 6, count 2 2006.210.07:36:31.29#ibcon#*after write, iclass 6, count 2 2006.210.07:36:31.29#ibcon#*before return 0, iclass 6, count 2 2006.210.07:36:31.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:31.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:36:31.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.07:36:31.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:31.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:31.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:31.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:31.41#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:36:31.41#ibcon#first serial, iclass 6, count 0 2006.210.07:36:31.41#ibcon#enter sib2, iclass 6, count 0 2006.210.07:36:31.41#ibcon#flushed, iclass 6, count 0 2006.210.07:36:31.41#ibcon#about to write, iclass 6, count 0 2006.210.07:36:31.41#ibcon#wrote, iclass 6, count 0 2006.210.07:36:31.41#ibcon#about to read 3, iclass 6, count 0 2006.210.07:36:31.43#ibcon#read 3, iclass 6, count 0 2006.210.07:36:31.43#ibcon#about to read 4, iclass 6, count 0 2006.210.07:36:31.43#ibcon#read 4, iclass 6, count 0 2006.210.07:36:31.43#ibcon#about to read 5, iclass 6, count 0 2006.210.07:36:31.43#ibcon#read 5, iclass 6, count 0 2006.210.07:36:31.43#ibcon#about to read 6, iclass 6, count 0 2006.210.07:36:31.43#ibcon#read 6, iclass 6, count 0 2006.210.07:36:31.43#ibcon#end of sib2, iclass 6, count 0 2006.210.07:36:31.43#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:36:31.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:36:31.43#ibcon#[27=USB\r\n] 2006.210.07:36:31.43#ibcon#*before write, iclass 6, count 0 2006.210.07:36:31.43#ibcon#enter sib2, iclass 6, count 0 2006.210.07:36:31.43#ibcon#flushed, iclass 6, count 0 2006.210.07:36:31.43#ibcon#about to write, iclass 6, count 0 2006.210.07:36:31.43#ibcon#wrote, iclass 6, count 0 2006.210.07:36:31.43#ibcon#about to read 3, iclass 6, count 0 2006.210.07:36:31.45#abcon#<5=/08 1.2 3.6 30.59 731006.2\r\n> 2006.210.07:36:31.46#ibcon#read 3, iclass 6, count 0 2006.210.07:36:31.46#ibcon#about to read 4, iclass 6, count 0 2006.210.07:36:31.46#ibcon#read 4, iclass 6, count 0 2006.210.07:36:31.46#ibcon#about to read 5, iclass 6, count 0 2006.210.07:36:31.46#ibcon#read 5, iclass 6, count 0 2006.210.07:36:31.46#ibcon#about to read 6, iclass 6, count 0 2006.210.07:36:31.46#ibcon#read 6, iclass 6, count 0 2006.210.07:36:31.46#ibcon#end of sib2, iclass 6, count 0 2006.210.07:36:31.46#ibcon#*after write, iclass 6, count 0 2006.210.07:36:31.46#ibcon#*before return 0, iclass 6, count 0 2006.210.07:36:31.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:31.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:36:31.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:36:31.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:36:31.46$vc4f8/vblo=5,744.99 2006.210.07:36:31.46#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:36:31.46#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:36:31.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:31.46#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:36:31.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:36:31.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:36:31.46#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:36:31.46#ibcon#first serial, iclass 13, count 0 2006.210.07:36:31.46#ibcon#enter sib2, iclass 13, count 0 2006.210.07:36:31.46#ibcon#flushed, iclass 13, count 0 2006.210.07:36:31.46#ibcon#about to write, iclass 13, count 0 2006.210.07:36:31.46#ibcon#wrote, iclass 13, count 0 2006.210.07:36:31.46#ibcon#about to read 3, iclass 13, count 0 2006.210.07:36:31.47#abcon#{5=INTERFACE CLEAR} 2006.210.07:36:31.48#ibcon#read 3, iclass 13, count 0 2006.210.07:36:31.48#ibcon#about to read 4, iclass 13, count 0 2006.210.07:36:31.48#ibcon#read 4, iclass 13, count 0 2006.210.07:36:31.48#ibcon#about to read 5, iclass 13, count 0 2006.210.07:36:31.48#ibcon#read 5, iclass 13, count 0 2006.210.07:36:31.48#ibcon#about to read 6, iclass 13, count 0 2006.210.07:36:31.48#ibcon#read 6, iclass 13, count 0 2006.210.07:36:31.48#ibcon#end of sib2, iclass 13, count 0 2006.210.07:36:31.48#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:36:31.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:36:31.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:36:31.48#ibcon#*before write, iclass 13, count 0 2006.210.07:36:31.48#ibcon#enter sib2, iclass 13, count 0 2006.210.07:36:31.48#ibcon#flushed, iclass 13, count 0 2006.210.07:36:31.48#ibcon#about to write, iclass 13, count 0 2006.210.07:36:31.48#ibcon#wrote, iclass 13, count 0 2006.210.07:36:31.48#ibcon#about to read 3, iclass 13, count 0 2006.210.07:36:31.52#ibcon#read 3, iclass 13, count 0 2006.210.07:36:31.52#ibcon#about to read 4, iclass 13, count 0 2006.210.07:36:31.52#ibcon#read 4, iclass 13, count 0 2006.210.07:36:31.52#ibcon#about to read 5, iclass 13, count 0 2006.210.07:36:31.52#ibcon#read 5, iclass 13, count 0 2006.210.07:36:31.52#ibcon#about to read 6, iclass 13, count 0 2006.210.07:36:31.52#ibcon#read 6, iclass 13, count 0 2006.210.07:36:31.52#ibcon#end of sib2, iclass 13, count 0 2006.210.07:36:31.52#ibcon#*after write, iclass 13, count 0 2006.210.07:36:31.52#ibcon#*before return 0, iclass 13, count 0 2006.210.07:36:31.52#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:36:31.52#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:36:31.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:36:31.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:36:31.52$vc4f8/vb=5,3 2006.210.07:36:31.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.07:36:31.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.07:36:31.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:31.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:31.53#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:36:31.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:31.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:31.58#ibcon#enter wrdev, iclass 16, count 2 2006.210.07:36:31.58#ibcon#first serial, iclass 16, count 2 2006.210.07:36:31.58#ibcon#enter sib2, iclass 16, count 2 2006.210.07:36:31.58#ibcon#flushed, iclass 16, count 2 2006.210.07:36:31.58#ibcon#about to write, iclass 16, count 2 2006.210.07:36:31.58#ibcon#wrote, iclass 16, count 2 2006.210.07:36:31.58#ibcon#about to read 3, iclass 16, count 2 2006.210.07:36:31.60#ibcon#read 3, iclass 16, count 2 2006.210.07:36:31.60#ibcon#about to read 4, iclass 16, count 2 2006.210.07:36:31.60#ibcon#read 4, iclass 16, count 2 2006.210.07:36:31.60#ibcon#about to read 5, iclass 16, count 2 2006.210.07:36:31.60#ibcon#read 5, iclass 16, count 2 2006.210.07:36:31.60#ibcon#about to read 6, iclass 16, count 2 2006.210.07:36:31.60#ibcon#read 6, iclass 16, count 2 2006.210.07:36:31.60#ibcon#end of sib2, iclass 16, count 2 2006.210.07:36:31.60#ibcon#*mode == 0, iclass 16, count 2 2006.210.07:36:31.60#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.07:36:31.60#ibcon#[27=AT05-03\r\n] 2006.210.07:36:31.60#ibcon#*before write, iclass 16, count 2 2006.210.07:36:31.60#ibcon#enter sib2, iclass 16, count 2 2006.210.07:36:31.60#ibcon#flushed, iclass 16, count 2 2006.210.07:36:31.60#ibcon#about to write, iclass 16, count 2 2006.210.07:36:31.60#ibcon#wrote, iclass 16, count 2 2006.210.07:36:31.60#ibcon#about to read 3, iclass 16, count 2 2006.210.07:36:31.63#ibcon#read 3, iclass 16, count 2 2006.210.07:36:31.63#ibcon#about to read 4, iclass 16, count 2 2006.210.07:36:31.63#ibcon#read 4, iclass 16, count 2 2006.210.07:36:31.63#ibcon#about to read 5, iclass 16, count 2 2006.210.07:36:31.63#ibcon#read 5, iclass 16, count 2 2006.210.07:36:31.63#ibcon#about to read 6, iclass 16, count 2 2006.210.07:36:31.63#ibcon#read 6, iclass 16, count 2 2006.210.07:36:31.63#ibcon#end of sib2, iclass 16, count 2 2006.210.07:36:31.63#ibcon#*after write, iclass 16, count 2 2006.210.07:36:31.63#ibcon#*before return 0, iclass 16, count 2 2006.210.07:36:31.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:31.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:36:31.63#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.07:36:31.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:31.63#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:31.75#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:31.75#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:31.75#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:36:31.75#ibcon#first serial, iclass 16, count 0 2006.210.07:36:31.75#ibcon#enter sib2, iclass 16, count 0 2006.210.07:36:31.75#ibcon#flushed, iclass 16, count 0 2006.210.07:36:31.75#ibcon#about to write, iclass 16, count 0 2006.210.07:36:31.75#ibcon#wrote, iclass 16, count 0 2006.210.07:36:31.75#ibcon#about to read 3, iclass 16, count 0 2006.210.07:36:31.77#ibcon#read 3, iclass 16, count 0 2006.210.07:36:31.77#ibcon#about to read 4, iclass 16, count 0 2006.210.07:36:31.77#ibcon#read 4, iclass 16, count 0 2006.210.07:36:31.77#ibcon#about to read 5, iclass 16, count 0 2006.210.07:36:31.77#ibcon#read 5, iclass 16, count 0 2006.210.07:36:31.77#ibcon#about to read 6, iclass 16, count 0 2006.210.07:36:31.77#ibcon#read 6, iclass 16, count 0 2006.210.07:36:31.77#ibcon#end of sib2, iclass 16, count 0 2006.210.07:36:31.77#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:36:31.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:36:31.77#ibcon#[27=USB\r\n] 2006.210.07:36:31.77#ibcon#*before write, iclass 16, count 0 2006.210.07:36:31.77#ibcon#enter sib2, iclass 16, count 0 2006.210.07:36:31.77#ibcon#flushed, iclass 16, count 0 2006.210.07:36:31.77#ibcon#about to write, iclass 16, count 0 2006.210.07:36:31.77#ibcon#wrote, iclass 16, count 0 2006.210.07:36:31.77#ibcon#about to read 3, iclass 16, count 0 2006.210.07:36:31.80#ibcon#read 3, iclass 16, count 0 2006.210.07:36:31.80#ibcon#about to read 4, iclass 16, count 0 2006.210.07:36:31.80#ibcon#read 4, iclass 16, count 0 2006.210.07:36:31.80#ibcon#about to read 5, iclass 16, count 0 2006.210.07:36:31.80#ibcon#read 5, iclass 16, count 0 2006.210.07:36:31.80#ibcon#about to read 6, iclass 16, count 0 2006.210.07:36:31.80#ibcon#read 6, iclass 16, count 0 2006.210.07:36:31.80#ibcon#end of sib2, iclass 16, count 0 2006.210.07:36:31.80#ibcon#*after write, iclass 16, count 0 2006.210.07:36:31.80#ibcon#*before return 0, iclass 16, count 0 2006.210.07:36:31.80#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:31.80#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:36:31.80#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:36:31.80#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:36:31.80$vc4f8/vblo=6,752.99 2006.210.07:36:31.80#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.07:36:31.80#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.07:36:31.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:36:31.80#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:31.80#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:31.80#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:31.80#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:36:31.80#ibcon#first serial, iclass 18, count 0 2006.210.07:36:31.80#ibcon#enter sib2, iclass 18, count 0 2006.210.07:36:31.80#ibcon#flushed, iclass 18, count 0 2006.210.07:36:31.80#ibcon#about to write, iclass 18, count 0 2006.210.07:36:31.80#ibcon#wrote, iclass 18, count 0 2006.210.07:36:31.80#ibcon#about to read 3, iclass 18, count 0 2006.210.07:36:31.82#ibcon#read 3, iclass 18, count 0 2006.210.07:36:31.82#ibcon#about to read 4, iclass 18, count 0 2006.210.07:36:31.82#ibcon#read 4, iclass 18, count 0 2006.210.07:36:31.82#ibcon#about to read 5, iclass 18, count 0 2006.210.07:36:31.82#ibcon#read 5, iclass 18, count 0 2006.210.07:36:31.82#ibcon#about to read 6, iclass 18, count 0 2006.210.07:36:31.82#ibcon#read 6, iclass 18, count 0 2006.210.07:36:31.82#ibcon#end of sib2, iclass 18, count 0 2006.210.07:36:31.82#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:36:31.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:36:31.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:36:31.82#ibcon#*before write, iclass 18, count 0 2006.210.07:36:31.82#ibcon#enter sib2, iclass 18, count 0 2006.210.07:36:31.82#ibcon#flushed, iclass 18, count 0 2006.210.07:36:31.82#ibcon#about to write, iclass 18, count 0 2006.210.07:36:31.82#ibcon#wrote, iclass 18, count 0 2006.210.07:36:31.82#ibcon#about to read 3, iclass 18, count 0 2006.210.07:36:31.86#ibcon#read 3, iclass 18, count 0 2006.210.07:36:31.86#ibcon#about to read 4, iclass 18, count 0 2006.210.07:36:31.86#ibcon#read 4, iclass 18, count 0 2006.210.07:36:31.86#ibcon#about to read 5, iclass 18, count 0 2006.210.07:36:31.86#ibcon#read 5, iclass 18, count 0 2006.210.07:36:31.86#ibcon#about to read 6, iclass 18, count 0 2006.210.07:36:31.86#ibcon#read 6, iclass 18, count 0 2006.210.07:36:31.86#ibcon#end of sib2, iclass 18, count 0 2006.210.07:36:31.86#ibcon#*after write, iclass 18, count 0 2006.210.07:36:31.86#ibcon#*before return 0, iclass 18, count 0 2006.210.07:36:31.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:31.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:36:31.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:36:31.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:36:31.86$vc4f8/vb=6,3 2006.210.07:36:31.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.07:36:31.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.07:36:31.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:36:31.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:31.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:31.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:31.92#ibcon#enter wrdev, iclass 20, count 2 2006.210.07:36:31.92#ibcon#first serial, iclass 20, count 2 2006.210.07:36:31.92#ibcon#enter sib2, iclass 20, count 2 2006.210.07:36:31.92#ibcon#flushed, iclass 20, count 2 2006.210.07:36:31.92#ibcon#about to write, iclass 20, count 2 2006.210.07:36:31.92#ibcon#wrote, iclass 20, count 2 2006.210.07:36:31.92#ibcon#about to read 3, iclass 20, count 2 2006.210.07:36:31.94#ibcon#read 3, iclass 20, count 2 2006.210.07:36:31.94#ibcon#about to read 4, iclass 20, count 2 2006.210.07:36:31.94#ibcon#read 4, iclass 20, count 2 2006.210.07:36:31.94#ibcon#about to read 5, iclass 20, count 2 2006.210.07:36:31.94#ibcon#read 5, iclass 20, count 2 2006.210.07:36:31.94#ibcon#about to read 6, iclass 20, count 2 2006.210.07:36:31.94#ibcon#read 6, iclass 20, count 2 2006.210.07:36:31.94#ibcon#end of sib2, iclass 20, count 2 2006.210.07:36:31.94#ibcon#*mode == 0, iclass 20, count 2 2006.210.07:36:31.94#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.07:36:31.94#ibcon#[27=AT06-03\r\n] 2006.210.07:36:31.94#ibcon#*before write, iclass 20, count 2 2006.210.07:36:31.94#ibcon#enter sib2, iclass 20, count 2 2006.210.07:36:31.94#ibcon#flushed, iclass 20, count 2 2006.210.07:36:31.94#ibcon#about to write, iclass 20, count 2 2006.210.07:36:31.94#ibcon#wrote, iclass 20, count 2 2006.210.07:36:31.94#ibcon#about to read 3, iclass 20, count 2 2006.210.07:36:31.97#ibcon#read 3, iclass 20, count 2 2006.210.07:36:31.97#ibcon#about to read 4, iclass 20, count 2 2006.210.07:36:31.97#ibcon#read 4, iclass 20, count 2 2006.210.07:36:31.97#ibcon#about to read 5, iclass 20, count 2 2006.210.07:36:31.97#ibcon#read 5, iclass 20, count 2 2006.210.07:36:31.97#ibcon#about to read 6, iclass 20, count 2 2006.210.07:36:31.97#ibcon#read 6, iclass 20, count 2 2006.210.07:36:31.97#ibcon#end of sib2, iclass 20, count 2 2006.210.07:36:31.97#ibcon#*after write, iclass 20, count 2 2006.210.07:36:31.97#ibcon#*before return 0, iclass 20, count 2 2006.210.07:36:31.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:31.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:36:31.97#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.07:36:31.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:36:31.97#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:32.09#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:32.09#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:32.09#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:36:32.09#ibcon#first serial, iclass 20, count 0 2006.210.07:36:32.09#ibcon#enter sib2, iclass 20, count 0 2006.210.07:36:32.09#ibcon#flushed, iclass 20, count 0 2006.210.07:36:32.09#ibcon#about to write, iclass 20, count 0 2006.210.07:36:32.09#ibcon#wrote, iclass 20, count 0 2006.210.07:36:32.09#ibcon#about to read 3, iclass 20, count 0 2006.210.07:36:32.11#ibcon#read 3, iclass 20, count 0 2006.210.07:36:32.11#ibcon#about to read 4, iclass 20, count 0 2006.210.07:36:32.11#ibcon#read 4, iclass 20, count 0 2006.210.07:36:32.11#ibcon#about to read 5, iclass 20, count 0 2006.210.07:36:32.11#ibcon#read 5, iclass 20, count 0 2006.210.07:36:32.11#ibcon#about to read 6, iclass 20, count 0 2006.210.07:36:32.11#ibcon#read 6, iclass 20, count 0 2006.210.07:36:32.11#ibcon#end of sib2, iclass 20, count 0 2006.210.07:36:32.11#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:36:32.11#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:36:32.11#ibcon#[27=USB\r\n] 2006.210.07:36:32.11#ibcon#*before write, iclass 20, count 0 2006.210.07:36:32.11#ibcon#enter sib2, iclass 20, count 0 2006.210.07:36:32.11#ibcon#flushed, iclass 20, count 0 2006.210.07:36:32.11#ibcon#about to write, iclass 20, count 0 2006.210.07:36:32.11#ibcon#wrote, iclass 20, count 0 2006.210.07:36:32.11#ibcon#about to read 3, iclass 20, count 0 2006.210.07:36:32.14#ibcon#read 3, iclass 20, count 0 2006.210.07:36:32.14#ibcon#about to read 4, iclass 20, count 0 2006.210.07:36:32.14#ibcon#read 4, iclass 20, count 0 2006.210.07:36:32.14#ibcon#about to read 5, iclass 20, count 0 2006.210.07:36:32.14#ibcon#read 5, iclass 20, count 0 2006.210.07:36:32.14#ibcon#about to read 6, iclass 20, count 0 2006.210.07:36:32.14#ibcon#read 6, iclass 20, count 0 2006.210.07:36:32.14#ibcon#end of sib2, iclass 20, count 0 2006.210.07:36:32.14#ibcon#*after write, iclass 20, count 0 2006.210.07:36:32.14#ibcon#*before return 0, iclass 20, count 0 2006.210.07:36:32.14#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:32.14#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:36:32.14#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:36:32.14#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:36:32.14$vc4f8/vabw=wide 2006.210.07:36:32.14#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:36:32.14#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:36:32.14#ibcon#ireg 8 cls_cnt 0 2006.210.07:36:32.14#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:32.14#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:32.14#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:32.14#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:36:32.14#ibcon#first serial, iclass 22, count 0 2006.210.07:36:32.14#ibcon#enter sib2, iclass 22, count 0 2006.210.07:36:32.14#ibcon#flushed, iclass 22, count 0 2006.210.07:36:32.14#ibcon#about to write, iclass 22, count 0 2006.210.07:36:32.14#ibcon#wrote, iclass 22, count 0 2006.210.07:36:32.14#ibcon#about to read 3, iclass 22, count 0 2006.210.07:36:32.16#ibcon#read 3, iclass 22, count 0 2006.210.07:36:32.16#ibcon#about to read 4, iclass 22, count 0 2006.210.07:36:32.16#ibcon#read 4, iclass 22, count 0 2006.210.07:36:32.16#ibcon#about to read 5, iclass 22, count 0 2006.210.07:36:32.16#ibcon#read 5, iclass 22, count 0 2006.210.07:36:32.16#ibcon#about to read 6, iclass 22, count 0 2006.210.07:36:32.16#ibcon#read 6, iclass 22, count 0 2006.210.07:36:32.16#ibcon#end of sib2, iclass 22, count 0 2006.210.07:36:32.16#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:36:32.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:36:32.16#ibcon#[25=BW32\r\n] 2006.210.07:36:32.16#ibcon#*before write, iclass 22, count 0 2006.210.07:36:32.16#ibcon#enter sib2, iclass 22, count 0 2006.210.07:36:32.16#ibcon#flushed, iclass 22, count 0 2006.210.07:36:32.16#ibcon#about to write, iclass 22, count 0 2006.210.07:36:32.16#ibcon#wrote, iclass 22, count 0 2006.210.07:36:32.16#ibcon#about to read 3, iclass 22, count 0 2006.210.07:36:32.19#ibcon#read 3, iclass 22, count 0 2006.210.07:36:32.19#ibcon#about to read 4, iclass 22, count 0 2006.210.07:36:32.19#ibcon#read 4, iclass 22, count 0 2006.210.07:36:32.19#ibcon#about to read 5, iclass 22, count 0 2006.210.07:36:32.19#ibcon#read 5, iclass 22, count 0 2006.210.07:36:32.19#ibcon#about to read 6, iclass 22, count 0 2006.210.07:36:32.19#ibcon#read 6, iclass 22, count 0 2006.210.07:36:32.19#ibcon#end of sib2, iclass 22, count 0 2006.210.07:36:32.19#ibcon#*after write, iclass 22, count 0 2006.210.07:36:32.19#ibcon#*before return 0, iclass 22, count 0 2006.210.07:36:32.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:32.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:36:32.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:36:32.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:36:32.19$vc4f8/vbbw=wide 2006.210.07:36:32.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:36:32.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:36:32.19#ibcon#ireg 8 cls_cnt 0 2006.210.07:36:32.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:36:32.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:36:32.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:36:32.26#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:36:32.26#ibcon#first serial, iclass 24, count 0 2006.210.07:36:32.26#ibcon#enter sib2, iclass 24, count 0 2006.210.07:36:32.26#ibcon#flushed, iclass 24, count 0 2006.210.07:36:32.26#ibcon#about to write, iclass 24, count 0 2006.210.07:36:32.26#ibcon#wrote, iclass 24, count 0 2006.210.07:36:32.26#ibcon#about to read 3, iclass 24, count 0 2006.210.07:36:32.28#ibcon#read 3, iclass 24, count 0 2006.210.07:36:32.28#ibcon#about to read 4, iclass 24, count 0 2006.210.07:36:32.28#ibcon#read 4, iclass 24, count 0 2006.210.07:36:32.28#ibcon#about to read 5, iclass 24, count 0 2006.210.07:36:32.28#ibcon#read 5, iclass 24, count 0 2006.210.07:36:32.28#ibcon#about to read 6, iclass 24, count 0 2006.210.07:36:32.28#ibcon#read 6, iclass 24, count 0 2006.210.07:36:32.28#ibcon#end of sib2, iclass 24, count 0 2006.210.07:36:32.28#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:36:32.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:36:32.28#ibcon#[27=BW32\r\n] 2006.210.07:36:32.28#ibcon#*before write, iclass 24, count 0 2006.210.07:36:32.28#ibcon#enter sib2, iclass 24, count 0 2006.210.07:36:32.28#ibcon#flushed, iclass 24, count 0 2006.210.07:36:32.28#ibcon#about to write, iclass 24, count 0 2006.210.07:36:32.28#ibcon#wrote, iclass 24, count 0 2006.210.07:36:32.28#ibcon#about to read 3, iclass 24, count 0 2006.210.07:36:32.31#ibcon#read 3, iclass 24, count 0 2006.210.07:36:32.31#ibcon#about to read 4, iclass 24, count 0 2006.210.07:36:32.31#ibcon#read 4, iclass 24, count 0 2006.210.07:36:32.31#ibcon#about to read 5, iclass 24, count 0 2006.210.07:36:32.31#ibcon#read 5, iclass 24, count 0 2006.210.07:36:32.31#ibcon#about to read 6, iclass 24, count 0 2006.210.07:36:32.31#ibcon#read 6, iclass 24, count 0 2006.210.07:36:32.31#ibcon#end of sib2, iclass 24, count 0 2006.210.07:36:32.31#ibcon#*after write, iclass 24, count 0 2006.210.07:36:32.31#ibcon#*before return 0, iclass 24, count 0 2006.210.07:36:32.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:36:32.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:36:32.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:36:32.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:36:32.31$4f8m12a/ifd4f 2006.210.07:36:32.31$ifd4f/lo= 2006.210.07:36:32.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:36:32.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:36:32.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:36:32.31$ifd4f/patch= 2006.210.07:36:32.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:36:32.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:36:32.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:36:32.32$4f8m12a/"form=m,16.000,1:2 2006.210.07:36:32.32$4f8m12a/"tpicd 2006.210.07:36:32.32$4f8m12a/echo=off 2006.210.07:36:32.32$4f8m12a/xlog=off 2006.210.07:36:32.32:!2006.210.07:37:00 2006.210.07:36:42.14#trakl#Source acquired 2006.210.07:36:44.14#flagr#flagr/antenna,acquired 2006.210.07:37:00.01:preob 2006.210.07:37:01.14/onsource/TRACKING 2006.210.07:37:01.14:!2006.210.07:37:10 2006.210.07:37:10.00:data_valid=on 2006.210.07:37:10.00:midob 2006.210.07:37:10.14/onsource/TRACKING 2006.210.07:37:10.14/wx/30.59,1006.2,73 2006.210.07:37:10.34/cable/+6.3946E-03 2006.210.07:37:11.43/va/01,08,usb,yes,30,31 2006.210.07:37:11.43/va/02,07,usb,yes,30,31 2006.210.07:37:11.43/va/03,06,usb,yes,31,32 2006.210.07:37:11.43/va/04,07,usb,yes,31,33 2006.210.07:37:11.43/va/05,07,usb,yes,32,33 2006.210.07:37:11.43/va/06,06,usb,yes,31,30 2006.210.07:37:11.43/va/07,06,usb,yes,31,31 2006.210.07:37:11.43/va/08,07,usb,yes,30,29 2006.210.07:37:11.66/valo/01,532.99,yes,locked 2006.210.07:37:11.66/valo/02,572.99,yes,locked 2006.210.07:37:11.66/valo/03,672.99,yes,locked 2006.210.07:37:11.66/valo/04,832.99,yes,locked 2006.210.07:37:11.66/valo/05,652.99,yes,locked 2006.210.07:37:11.66/valo/06,772.99,yes,locked 2006.210.07:37:11.66/valo/07,832.99,yes,locked 2006.210.07:37:11.66/valo/08,852.99,yes,locked 2006.210.07:37:12.75/vb/01,04,usb,yes,29,28 2006.210.07:37:12.75/vb/02,04,usb,yes,31,32 2006.210.07:37:12.75/vb/03,03,usb,yes,34,38 2006.210.07:37:12.75/vb/04,03,usb,yes,35,35 2006.210.07:37:12.75/vb/05,03,usb,yes,33,38 2006.210.07:37:12.75/vb/06,03,usb,yes,34,37 2006.210.07:37:12.75/vb/07,04,usb,yes,30,30 2006.210.07:37:12.75/vb/08,03,usb,yes,34,38 2006.210.07:37:12.98/vblo/01,632.99,yes,locked 2006.210.07:37:12.98/vblo/02,640.99,yes,locked 2006.210.07:37:12.98/vblo/03,656.99,yes,locked 2006.210.07:37:12.98/vblo/04,712.99,yes,locked 2006.210.07:37:12.98/vblo/05,744.99,yes,locked 2006.210.07:37:12.98/vblo/06,752.99,yes,locked 2006.210.07:37:12.98/vblo/07,734.99,yes,locked 2006.210.07:37:12.98/vblo/08,744.99,yes,locked 2006.210.07:37:13.13/vabw/8 2006.210.07:37:13.28/vbbw/8 2006.210.07:37:13.37/xfe/off,on,12.5 2006.210.07:37:13.77/ifatt/23,28,28,28 2006.210.07:37:14.07/fmout-gps/S +4.39E-07 2006.210.07:37:14.12:!2006.210.07:38:10 2006.210.07:38:10.01:data_valid=off 2006.210.07:38:10.01:postob 2006.210.07:38:10.13/cable/+6.3945E-03 2006.210.07:38:10.13/wx/30.59,1006.2,75 2006.210.07:38:11.07/fmout-gps/S +4.38E-07 2006.210.07:38:11.07:scan_name=210-0739,k06210,60 2006.210.07:38:11.07:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.210.07:38:12.14#flagr#flagr/antenna,new-source 2006.210.07:38:12.14:checkk5 2006.210.07:38:12.49/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:38:12.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:38:13.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:38:13.52/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:38:13.85/chk_obsdata//k5ts1/T2100737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:38:14.19/chk_obsdata//k5ts2/T2100737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:38:14.52/chk_obsdata//k5ts3/T2100737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:38:14.85/chk_obsdata//k5ts4/T2100737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:38:15.50/k5log//k5ts1_log_newline 2006.210.07:38:16.16/k5log//k5ts2_log_newline 2006.210.07:38:16.82/k5log//k5ts3_log_newline 2006.210.07:38:17.47/k5log//k5ts4_log_newline 2006.210.07:38:17.49/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:38:17.49:4f8m12a=1 2006.210.07:38:17.49$4f8m12a/echo=on 2006.210.07:38:17.49$4f8m12a/pcalon 2006.210.07:38:17.49$pcalon/"no phase cal control is implemented here 2006.210.07:38:17.49$4f8m12a/"tpicd=stop 2006.210.07:38:17.49$4f8m12a/vc4f8 2006.210.07:38:17.49$vc4f8/valo=1,532.99 2006.210.07:38:17.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.07:38:17.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.07:38:17.50#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:17.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:17.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:17.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:17.50#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:38:17.50#ibcon#first serial, iclass 31, count 0 2006.210.07:38:17.50#ibcon#enter sib2, iclass 31, count 0 2006.210.07:38:17.50#ibcon#flushed, iclass 31, count 0 2006.210.07:38:17.50#ibcon#about to write, iclass 31, count 0 2006.210.07:38:17.50#ibcon#wrote, iclass 31, count 0 2006.210.07:38:17.50#ibcon#about to read 3, iclass 31, count 0 2006.210.07:38:17.51#ibcon#read 3, iclass 31, count 0 2006.210.07:38:17.51#ibcon#about to read 4, iclass 31, count 0 2006.210.07:38:17.51#ibcon#read 4, iclass 31, count 0 2006.210.07:38:17.51#ibcon#about to read 5, iclass 31, count 0 2006.210.07:38:17.51#ibcon#read 5, iclass 31, count 0 2006.210.07:38:17.51#ibcon#about to read 6, iclass 31, count 0 2006.210.07:38:17.51#ibcon#read 6, iclass 31, count 0 2006.210.07:38:17.51#ibcon#end of sib2, iclass 31, count 0 2006.210.07:38:17.51#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:38:17.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:38:17.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:38:17.51#ibcon#*before write, iclass 31, count 0 2006.210.07:38:17.51#ibcon#enter sib2, iclass 31, count 0 2006.210.07:38:17.51#ibcon#flushed, iclass 31, count 0 2006.210.07:38:17.51#ibcon#about to write, iclass 31, count 0 2006.210.07:38:17.51#ibcon#wrote, iclass 31, count 0 2006.210.07:38:17.51#ibcon#about to read 3, iclass 31, count 0 2006.210.07:38:17.56#ibcon#read 3, iclass 31, count 0 2006.210.07:38:17.56#ibcon#about to read 4, iclass 31, count 0 2006.210.07:38:17.56#ibcon#read 4, iclass 31, count 0 2006.210.07:38:17.56#ibcon#about to read 5, iclass 31, count 0 2006.210.07:38:17.56#ibcon#read 5, iclass 31, count 0 2006.210.07:38:17.56#ibcon#about to read 6, iclass 31, count 0 2006.210.07:38:17.56#ibcon#read 6, iclass 31, count 0 2006.210.07:38:17.56#ibcon#end of sib2, iclass 31, count 0 2006.210.07:38:17.56#ibcon#*after write, iclass 31, count 0 2006.210.07:38:17.56#ibcon#*before return 0, iclass 31, count 0 2006.210.07:38:17.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:17.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:17.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:38:17.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:38:17.56$vc4f8/va=1,8 2006.210.07:38:17.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.07:38:17.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.07:38:17.56#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:17.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:17.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:17.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:17.56#ibcon#enter wrdev, iclass 33, count 2 2006.210.07:38:17.56#ibcon#first serial, iclass 33, count 2 2006.210.07:38:17.56#ibcon#enter sib2, iclass 33, count 2 2006.210.07:38:17.56#ibcon#flushed, iclass 33, count 2 2006.210.07:38:17.56#ibcon#about to write, iclass 33, count 2 2006.210.07:38:17.56#ibcon#wrote, iclass 33, count 2 2006.210.07:38:17.56#ibcon#about to read 3, iclass 33, count 2 2006.210.07:38:17.58#ibcon#read 3, iclass 33, count 2 2006.210.07:38:17.58#ibcon#about to read 4, iclass 33, count 2 2006.210.07:38:17.58#ibcon#read 4, iclass 33, count 2 2006.210.07:38:17.58#ibcon#about to read 5, iclass 33, count 2 2006.210.07:38:17.58#ibcon#read 5, iclass 33, count 2 2006.210.07:38:17.58#ibcon#about to read 6, iclass 33, count 2 2006.210.07:38:17.58#ibcon#read 6, iclass 33, count 2 2006.210.07:38:17.58#ibcon#end of sib2, iclass 33, count 2 2006.210.07:38:17.58#ibcon#*mode == 0, iclass 33, count 2 2006.210.07:38:17.58#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.07:38:17.58#ibcon#[25=AT01-08\r\n] 2006.210.07:38:17.58#ibcon#*before write, iclass 33, count 2 2006.210.07:38:17.58#ibcon#enter sib2, iclass 33, count 2 2006.210.07:38:17.58#ibcon#flushed, iclass 33, count 2 2006.210.07:38:17.58#ibcon#about to write, iclass 33, count 2 2006.210.07:38:17.58#ibcon#wrote, iclass 33, count 2 2006.210.07:38:17.58#ibcon#about to read 3, iclass 33, count 2 2006.210.07:38:17.61#ibcon#read 3, iclass 33, count 2 2006.210.07:38:17.61#ibcon#about to read 4, iclass 33, count 2 2006.210.07:38:17.61#ibcon#read 4, iclass 33, count 2 2006.210.07:38:17.61#ibcon#about to read 5, iclass 33, count 2 2006.210.07:38:17.61#ibcon#read 5, iclass 33, count 2 2006.210.07:38:17.61#ibcon#about to read 6, iclass 33, count 2 2006.210.07:38:17.61#ibcon#read 6, iclass 33, count 2 2006.210.07:38:17.61#ibcon#end of sib2, iclass 33, count 2 2006.210.07:38:17.61#ibcon#*after write, iclass 33, count 2 2006.210.07:38:17.61#ibcon#*before return 0, iclass 33, count 2 2006.210.07:38:17.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:17.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:17.61#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.07:38:17.61#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:17.61#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:17.73#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:17.73#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:17.73#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:38:17.73#ibcon#first serial, iclass 33, count 0 2006.210.07:38:17.73#ibcon#enter sib2, iclass 33, count 0 2006.210.07:38:17.73#ibcon#flushed, iclass 33, count 0 2006.210.07:38:17.73#ibcon#about to write, iclass 33, count 0 2006.210.07:38:17.73#ibcon#wrote, iclass 33, count 0 2006.210.07:38:17.73#ibcon#about to read 3, iclass 33, count 0 2006.210.07:38:17.75#ibcon#read 3, iclass 33, count 0 2006.210.07:38:17.75#ibcon#about to read 4, iclass 33, count 0 2006.210.07:38:17.75#ibcon#read 4, iclass 33, count 0 2006.210.07:38:17.75#ibcon#about to read 5, iclass 33, count 0 2006.210.07:38:17.75#ibcon#read 5, iclass 33, count 0 2006.210.07:38:17.75#ibcon#about to read 6, iclass 33, count 0 2006.210.07:38:17.75#ibcon#read 6, iclass 33, count 0 2006.210.07:38:17.75#ibcon#end of sib2, iclass 33, count 0 2006.210.07:38:17.75#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:38:17.75#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:38:17.75#ibcon#[25=USB\r\n] 2006.210.07:38:17.75#ibcon#*before write, iclass 33, count 0 2006.210.07:38:17.75#ibcon#enter sib2, iclass 33, count 0 2006.210.07:38:17.75#ibcon#flushed, iclass 33, count 0 2006.210.07:38:17.75#ibcon#about to write, iclass 33, count 0 2006.210.07:38:17.75#ibcon#wrote, iclass 33, count 0 2006.210.07:38:17.75#ibcon#about to read 3, iclass 33, count 0 2006.210.07:38:17.78#ibcon#read 3, iclass 33, count 0 2006.210.07:38:17.78#ibcon#about to read 4, iclass 33, count 0 2006.210.07:38:17.78#ibcon#read 4, iclass 33, count 0 2006.210.07:38:17.78#ibcon#about to read 5, iclass 33, count 0 2006.210.07:38:17.78#ibcon#read 5, iclass 33, count 0 2006.210.07:38:17.78#ibcon#about to read 6, iclass 33, count 0 2006.210.07:38:17.78#ibcon#read 6, iclass 33, count 0 2006.210.07:38:17.78#ibcon#end of sib2, iclass 33, count 0 2006.210.07:38:17.78#ibcon#*after write, iclass 33, count 0 2006.210.07:38:17.78#ibcon#*before return 0, iclass 33, count 0 2006.210.07:38:17.78#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:17.78#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:17.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:38:17.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:38:17.78$vc4f8/valo=2,572.99 2006.210.07:38:17.78#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.07:38:17.78#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.07:38:17.78#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:17.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:17.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:17.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:17.78#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:38:17.78#ibcon#first serial, iclass 35, count 0 2006.210.07:38:17.78#ibcon#enter sib2, iclass 35, count 0 2006.210.07:38:17.78#ibcon#flushed, iclass 35, count 0 2006.210.07:38:17.78#ibcon#about to write, iclass 35, count 0 2006.210.07:38:17.78#ibcon#wrote, iclass 35, count 0 2006.210.07:38:17.78#ibcon#about to read 3, iclass 35, count 0 2006.210.07:38:17.80#ibcon#read 3, iclass 35, count 0 2006.210.07:38:17.80#ibcon#about to read 4, iclass 35, count 0 2006.210.07:38:17.80#ibcon#read 4, iclass 35, count 0 2006.210.07:38:17.80#ibcon#about to read 5, iclass 35, count 0 2006.210.07:38:17.80#ibcon#read 5, iclass 35, count 0 2006.210.07:38:17.80#ibcon#about to read 6, iclass 35, count 0 2006.210.07:38:17.80#ibcon#read 6, iclass 35, count 0 2006.210.07:38:17.80#ibcon#end of sib2, iclass 35, count 0 2006.210.07:38:17.80#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:38:17.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:38:17.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:38:17.80#ibcon#*before write, iclass 35, count 0 2006.210.07:38:17.80#ibcon#enter sib2, iclass 35, count 0 2006.210.07:38:17.80#ibcon#flushed, iclass 35, count 0 2006.210.07:38:17.80#ibcon#about to write, iclass 35, count 0 2006.210.07:38:17.80#ibcon#wrote, iclass 35, count 0 2006.210.07:38:17.80#ibcon#about to read 3, iclass 35, count 0 2006.210.07:38:17.84#ibcon#read 3, iclass 35, count 0 2006.210.07:38:17.84#ibcon#about to read 4, iclass 35, count 0 2006.210.07:38:17.84#ibcon#read 4, iclass 35, count 0 2006.210.07:38:17.84#ibcon#about to read 5, iclass 35, count 0 2006.210.07:38:17.84#ibcon#read 5, iclass 35, count 0 2006.210.07:38:17.84#ibcon#about to read 6, iclass 35, count 0 2006.210.07:38:17.84#ibcon#read 6, iclass 35, count 0 2006.210.07:38:17.84#ibcon#end of sib2, iclass 35, count 0 2006.210.07:38:17.84#ibcon#*after write, iclass 35, count 0 2006.210.07:38:17.84#ibcon#*before return 0, iclass 35, count 0 2006.210.07:38:17.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:17.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:17.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:38:17.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:38:17.84$vc4f8/va=2,7 2006.210.07:38:17.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:38:17.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:38:17.84#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:17.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:17.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:17.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:17.90#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:38:17.90#ibcon#first serial, iclass 37, count 2 2006.210.07:38:17.90#ibcon#enter sib2, iclass 37, count 2 2006.210.07:38:17.90#ibcon#flushed, iclass 37, count 2 2006.210.07:38:17.90#ibcon#about to write, iclass 37, count 2 2006.210.07:38:17.90#ibcon#wrote, iclass 37, count 2 2006.210.07:38:17.90#ibcon#about to read 3, iclass 37, count 2 2006.210.07:38:17.92#ibcon#read 3, iclass 37, count 2 2006.210.07:38:17.92#ibcon#about to read 4, iclass 37, count 2 2006.210.07:38:17.92#ibcon#read 4, iclass 37, count 2 2006.210.07:38:17.92#ibcon#about to read 5, iclass 37, count 2 2006.210.07:38:17.92#ibcon#read 5, iclass 37, count 2 2006.210.07:38:17.92#ibcon#about to read 6, iclass 37, count 2 2006.210.07:38:17.92#ibcon#read 6, iclass 37, count 2 2006.210.07:38:17.92#ibcon#end of sib2, iclass 37, count 2 2006.210.07:38:17.92#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:38:17.92#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:38:17.92#ibcon#[25=AT02-07\r\n] 2006.210.07:38:17.92#ibcon#*before write, iclass 37, count 2 2006.210.07:38:17.92#ibcon#enter sib2, iclass 37, count 2 2006.210.07:38:17.92#ibcon#flushed, iclass 37, count 2 2006.210.07:38:17.92#ibcon#about to write, iclass 37, count 2 2006.210.07:38:17.92#ibcon#wrote, iclass 37, count 2 2006.210.07:38:17.92#ibcon#about to read 3, iclass 37, count 2 2006.210.07:38:17.95#ibcon#read 3, iclass 37, count 2 2006.210.07:38:17.95#ibcon#about to read 4, iclass 37, count 2 2006.210.07:38:17.95#ibcon#read 4, iclass 37, count 2 2006.210.07:38:17.95#ibcon#about to read 5, iclass 37, count 2 2006.210.07:38:17.95#ibcon#read 5, iclass 37, count 2 2006.210.07:38:17.95#ibcon#about to read 6, iclass 37, count 2 2006.210.07:38:17.95#ibcon#read 6, iclass 37, count 2 2006.210.07:38:17.95#ibcon#end of sib2, iclass 37, count 2 2006.210.07:38:17.95#ibcon#*after write, iclass 37, count 2 2006.210.07:38:17.95#ibcon#*before return 0, iclass 37, count 2 2006.210.07:38:17.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:17.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:17.95#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:38:17.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:17.95#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:18.07#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:18.07#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:18.07#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:38:18.07#ibcon#first serial, iclass 37, count 0 2006.210.07:38:18.07#ibcon#enter sib2, iclass 37, count 0 2006.210.07:38:18.07#ibcon#flushed, iclass 37, count 0 2006.210.07:38:18.07#ibcon#about to write, iclass 37, count 0 2006.210.07:38:18.07#ibcon#wrote, iclass 37, count 0 2006.210.07:38:18.07#ibcon#about to read 3, iclass 37, count 0 2006.210.07:38:18.09#ibcon#read 3, iclass 37, count 0 2006.210.07:38:18.09#ibcon#about to read 4, iclass 37, count 0 2006.210.07:38:18.09#ibcon#read 4, iclass 37, count 0 2006.210.07:38:18.09#ibcon#about to read 5, iclass 37, count 0 2006.210.07:38:18.09#ibcon#read 5, iclass 37, count 0 2006.210.07:38:18.09#ibcon#about to read 6, iclass 37, count 0 2006.210.07:38:18.09#ibcon#read 6, iclass 37, count 0 2006.210.07:38:18.09#ibcon#end of sib2, iclass 37, count 0 2006.210.07:38:18.09#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:38:18.09#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:38:18.09#ibcon#[25=USB\r\n] 2006.210.07:38:18.09#ibcon#*before write, iclass 37, count 0 2006.210.07:38:18.09#ibcon#enter sib2, iclass 37, count 0 2006.210.07:38:18.09#ibcon#flushed, iclass 37, count 0 2006.210.07:38:18.09#ibcon#about to write, iclass 37, count 0 2006.210.07:38:18.09#ibcon#wrote, iclass 37, count 0 2006.210.07:38:18.09#ibcon#about to read 3, iclass 37, count 0 2006.210.07:38:18.12#ibcon#read 3, iclass 37, count 0 2006.210.07:38:18.12#ibcon#about to read 4, iclass 37, count 0 2006.210.07:38:18.12#ibcon#read 4, iclass 37, count 0 2006.210.07:38:18.12#ibcon#about to read 5, iclass 37, count 0 2006.210.07:38:18.12#ibcon#read 5, iclass 37, count 0 2006.210.07:38:18.12#ibcon#about to read 6, iclass 37, count 0 2006.210.07:38:18.12#ibcon#read 6, iclass 37, count 0 2006.210.07:38:18.12#ibcon#end of sib2, iclass 37, count 0 2006.210.07:38:18.12#ibcon#*after write, iclass 37, count 0 2006.210.07:38:18.12#ibcon#*before return 0, iclass 37, count 0 2006.210.07:38:18.12#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:18.12#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:18.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:38:18.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:38:18.12$vc4f8/valo=3,672.99 2006.210.07:38:18.12#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.07:38:18.12#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.07:38:18.12#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:18.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:18.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:18.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:18.12#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:38:18.12#ibcon#first serial, iclass 39, count 0 2006.210.07:38:18.12#ibcon#enter sib2, iclass 39, count 0 2006.210.07:38:18.12#ibcon#flushed, iclass 39, count 0 2006.210.07:38:18.12#ibcon#about to write, iclass 39, count 0 2006.210.07:38:18.12#ibcon#wrote, iclass 39, count 0 2006.210.07:38:18.12#ibcon#about to read 3, iclass 39, count 0 2006.210.07:38:18.14#ibcon#read 3, iclass 39, count 0 2006.210.07:38:18.14#ibcon#about to read 4, iclass 39, count 0 2006.210.07:38:18.14#ibcon#read 4, iclass 39, count 0 2006.210.07:38:18.14#ibcon#about to read 5, iclass 39, count 0 2006.210.07:38:18.14#ibcon#read 5, iclass 39, count 0 2006.210.07:38:18.14#ibcon#about to read 6, iclass 39, count 0 2006.210.07:38:18.14#ibcon#read 6, iclass 39, count 0 2006.210.07:38:18.14#ibcon#end of sib2, iclass 39, count 0 2006.210.07:38:18.14#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:38:18.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:38:18.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:38:18.14#ibcon#*before write, iclass 39, count 0 2006.210.07:38:18.14#ibcon#enter sib2, iclass 39, count 0 2006.210.07:38:18.14#ibcon#flushed, iclass 39, count 0 2006.210.07:38:18.14#ibcon#about to write, iclass 39, count 0 2006.210.07:38:18.14#ibcon#wrote, iclass 39, count 0 2006.210.07:38:18.14#ibcon#about to read 3, iclass 39, count 0 2006.210.07:38:18.18#ibcon#read 3, iclass 39, count 0 2006.210.07:38:18.18#ibcon#about to read 4, iclass 39, count 0 2006.210.07:38:18.18#ibcon#read 4, iclass 39, count 0 2006.210.07:38:18.18#ibcon#about to read 5, iclass 39, count 0 2006.210.07:38:18.18#ibcon#read 5, iclass 39, count 0 2006.210.07:38:18.18#ibcon#about to read 6, iclass 39, count 0 2006.210.07:38:18.18#ibcon#read 6, iclass 39, count 0 2006.210.07:38:18.18#ibcon#end of sib2, iclass 39, count 0 2006.210.07:38:18.18#ibcon#*after write, iclass 39, count 0 2006.210.07:38:18.18#ibcon#*before return 0, iclass 39, count 0 2006.210.07:38:18.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:18.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:18.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:38:18.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:38:18.18$vc4f8/va=3,6 2006.210.07:38:18.18#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.07:38:18.18#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.07:38:18.18#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:18.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:18.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:18.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:18.24#ibcon#enter wrdev, iclass 3, count 2 2006.210.07:38:18.24#ibcon#first serial, iclass 3, count 2 2006.210.07:38:18.24#ibcon#enter sib2, iclass 3, count 2 2006.210.07:38:18.24#ibcon#flushed, iclass 3, count 2 2006.210.07:38:18.24#ibcon#about to write, iclass 3, count 2 2006.210.07:38:18.24#ibcon#wrote, iclass 3, count 2 2006.210.07:38:18.24#ibcon#about to read 3, iclass 3, count 2 2006.210.07:38:18.26#ibcon#read 3, iclass 3, count 2 2006.210.07:38:18.26#ibcon#about to read 4, iclass 3, count 2 2006.210.07:38:18.26#ibcon#read 4, iclass 3, count 2 2006.210.07:38:18.26#ibcon#about to read 5, iclass 3, count 2 2006.210.07:38:18.26#ibcon#read 5, iclass 3, count 2 2006.210.07:38:18.26#ibcon#about to read 6, iclass 3, count 2 2006.210.07:38:18.26#ibcon#read 6, iclass 3, count 2 2006.210.07:38:18.26#ibcon#end of sib2, iclass 3, count 2 2006.210.07:38:18.26#ibcon#*mode == 0, iclass 3, count 2 2006.210.07:38:18.26#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.07:38:18.26#ibcon#[25=AT03-06\r\n] 2006.210.07:38:18.26#ibcon#*before write, iclass 3, count 2 2006.210.07:38:18.26#ibcon#enter sib2, iclass 3, count 2 2006.210.07:38:18.26#ibcon#flushed, iclass 3, count 2 2006.210.07:38:18.26#ibcon#about to write, iclass 3, count 2 2006.210.07:38:18.26#ibcon#wrote, iclass 3, count 2 2006.210.07:38:18.26#ibcon#about to read 3, iclass 3, count 2 2006.210.07:38:18.29#ibcon#read 3, iclass 3, count 2 2006.210.07:38:18.29#ibcon#about to read 4, iclass 3, count 2 2006.210.07:38:18.29#ibcon#read 4, iclass 3, count 2 2006.210.07:38:18.29#ibcon#about to read 5, iclass 3, count 2 2006.210.07:38:18.29#ibcon#read 5, iclass 3, count 2 2006.210.07:38:18.29#ibcon#about to read 6, iclass 3, count 2 2006.210.07:38:18.29#ibcon#read 6, iclass 3, count 2 2006.210.07:38:18.29#ibcon#end of sib2, iclass 3, count 2 2006.210.07:38:18.29#ibcon#*after write, iclass 3, count 2 2006.210.07:38:18.29#ibcon#*before return 0, iclass 3, count 2 2006.210.07:38:18.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:18.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:18.29#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.07:38:18.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:18.29#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:18.41#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:18.41#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:18.41#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:38:18.41#ibcon#first serial, iclass 3, count 0 2006.210.07:38:18.41#ibcon#enter sib2, iclass 3, count 0 2006.210.07:38:18.41#ibcon#flushed, iclass 3, count 0 2006.210.07:38:18.41#ibcon#about to write, iclass 3, count 0 2006.210.07:38:18.41#ibcon#wrote, iclass 3, count 0 2006.210.07:38:18.41#ibcon#about to read 3, iclass 3, count 0 2006.210.07:38:18.43#ibcon#read 3, iclass 3, count 0 2006.210.07:38:18.43#ibcon#about to read 4, iclass 3, count 0 2006.210.07:38:18.43#ibcon#read 4, iclass 3, count 0 2006.210.07:38:18.43#ibcon#about to read 5, iclass 3, count 0 2006.210.07:38:18.43#ibcon#read 5, iclass 3, count 0 2006.210.07:38:18.43#ibcon#about to read 6, iclass 3, count 0 2006.210.07:38:18.43#ibcon#read 6, iclass 3, count 0 2006.210.07:38:18.43#ibcon#end of sib2, iclass 3, count 0 2006.210.07:38:18.43#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:38:18.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:38:18.43#ibcon#[25=USB\r\n] 2006.210.07:38:18.43#ibcon#*before write, iclass 3, count 0 2006.210.07:38:18.43#ibcon#enter sib2, iclass 3, count 0 2006.210.07:38:18.43#ibcon#flushed, iclass 3, count 0 2006.210.07:38:18.43#ibcon#about to write, iclass 3, count 0 2006.210.07:38:18.43#ibcon#wrote, iclass 3, count 0 2006.210.07:38:18.43#ibcon#about to read 3, iclass 3, count 0 2006.210.07:38:18.46#ibcon#read 3, iclass 3, count 0 2006.210.07:38:18.46#ibcon#about to read 4, iclass 3, count 0 2006.210.07:38:18.46#ibcon#read 4, iclass 3, count 0 2006.210.07:38:18.46#ibcon#about to read 5, iclass 3, count 0 2006.210.07:38:18.46#ibcon#read 5, iclass 3, count 0 2006.210.07:38:18.46#ibcon#about to read 6, iclass 3, count 0 2006.210.07:38:18.46#ibcon#read 6, iclass 3, count 0 2006.210.07:38:18.46#ibcon#end of sib2, iclass 3, count 0 2006.210.07:38:18.46#ibcon#*after write, iclass 3, count 0 2006.210.07:38:18.46#ibcon#*before return 0, iclass 3, count 0 2006.210.07:38:18.46#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:18.46#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:18.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:38:18.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:38:18.46$vc4f8/valo=4,832.99 2006.210.07:38:18.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.07:38:18.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.07:38:18.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:18.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:18.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:18.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:18.46#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:38:18.46#ibcon#first serial, iclass 5, count 0 2006.210.07:38:18.46#ibcon#enter sib2, iclass 5, count 0 2006.210.07:38:18.46#ibcon#flushed, iclass 5, count 0 2006.210.07:38:18.46#ibcon#about to write, iclass 5, count 0 2006.210.07:38:18.46#ibcon#wrote, iclass 5, count 0 2006.210.07:38:18.46#ibcon#about to read 3, iclass 5, count 0 2006.210.07:38:18.48#ibcon#read 3, iclass 5, count 0 2006.210.07:38:18.48#ibcon#about to read 4, iclass 5, count 0 2006.210.07:38:18.48#ibcon#read 4, iclass 5, count 0 2006.210.07:38:18.48#ibcon#about to read 5, iclass 5, count 0 2006.210.07:38:18.48#ibcon#read 5, iclass 5, count 0 2006.210.07:38:18.48#ibcon#about to read 6, iclass 5, count 0 2006.210.07:38:18.48#ibcon#read 6, iclass 5, count 0 2006.210.07:38:18.48#ibcon#end of sib2, iclass 5, count 0 2006.210.07:38:18.48#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:38:18.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:38:18.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:38:18.48#ibcon#*before write, iclass 5, count 0 2006.210.07:38:18.48#ibcon#enter sib2, iclass 5, count 0 2006.210.07:38:18.48#ibcon#flushed, iclass 5, count 0 2006.210.07:38:18.48#ibcon#about to write, iclass 5, count 0 2006.210.07:38:18.48#ibcon#wrote, iclass 5, count 0 2006.210.07:38:18.48#ibcon#about to read 3, iclass 5, count 0 2006.210.07:38:18.52#ibcon#read 3, iclass 5, count 0 2006.210.07:38:18.52#ibcon#about to read 4, iclass 5, count 0 2006.210.07:38:18.52#ibcon#read 4, iclass 5, count 0 2006.210.07:38:18.52#ibcon#about to read 5, iclass 5, count 0 2006.210.07:38:18.52#ibcon#read 5, iclass 5, count 0 2006.210.07:38:18.52#ibcon#about to read 6, iclass 5, count 0 2006.210.07:38:18.52#ibcon#read 6, iclass 5, count 0 2006.210.07:38:18.52#ibcon#end of sib2, iclass 5, count 0 2006.210.07:38:18.52#ibcon#*after write, iclass 5, count 0 2006.210.07:38:18.52#ibcon#*before return 0, iclass 5, count 0 2006.210.07:38:18.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:18.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:18.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:38:18.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:38:18.52$vc4f8/va=4,7 2006.210.07:38:18.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.07:38:18.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.07:38:18.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:18.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:18.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:18.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:18.58#ibcon#enter wrdev, iclass 7, count 2 2006.210.07:38:18.58#ibcon#first serial, iclass 7, count 2 2006.210.07:38:18.58#ibcon#enter sib2, iclass 7, count 2 2006.210.07:38:18.58#ibcon#flushed, iclass 7, count 2 2006.210.07:38:18.58#ibcon#about to write, iclass 7, count 2 2006.210.07:38:18.58#ibcon#wrote, iclass 7, count 2 2006.210.07:38:18.58#ibcon#about to read 3, iclass 7, count 2 2006.210.07:38:18.60#ibcon#read 3, iclass 7, count 2 2006.210.07:38:18.60#ibcon#about to read 4, iclass 7, count 2 2006.210.07:38:18.60#ibcon#read 4, iclass 7, count 2 2006.210.07:38:18.60#ibcon#about to read 5, iclass 7, count 2 2006.210.07:38:18.60#ibcon#read 5, iclass 7, count 2 2006.210.07:38:18.60#ibcon#about to read 6, iclass 7, count 2 2006.210.07:38:18.60#ibcon#read 6, iclass 7, count 2 2006.210.07:38:18.60#ibcon#end of sib2, iclass 7, count 2 2006.210.07:38:18.60#ibcon#*mode == 0, iclass 7, count 2 2006.210.07:38:18.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.07:38:18.60#ibcon#[25=AT04-07\r\n] 2006.210.07:38:18.60#ibcon#*before write, iclass 7, count 2 2006.210.07:38:18.60#ibcon#enter sib2, iclass 7, count 2 2006.210.07:38:18.60#ibcon#flushed, iclass 7, count 2 2006.210.07:38:18.60#ibcon#about to write, iclass 7, count 2 2006.210.07:38:18.60#ibcon#wrote, iclass 7, count 2 2006.210.07:38:18.60#ibcon#about to read 3, iclass 7, count 2 2006.210.07:38:18.63#ibcon#read 3, iclass 7, count 2 2006.210.07:38:18.63#ibcon#about to read 4, iclass 7, count 2 2006.210.07:38:18.63#ibcon#read 4, iclass 7, count 2 2006.210.07:38:18.63#ibcon#about to read 5, iclass 7, count 2 2006.210.07:38:18.63#ibcon#read 5, iclass 7, count 2 2006.210.07:38:18.63#ibcon#about to read 6, iclass 7, count 2 2006.210.07:38:18.63#ibcon#read 6, iclass 7, count 2 2006.210.07:38:18.63#ibcon#end of sib2, iclass 7, count 2 2006.210.07:38:18.63#ibcon#*after write, iclass 7, count 2 2006.210.07:38:18.63#ibcon#*before return 0, iclass 7, count 2 2006.210.07:38:18.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:18.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:18.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.07:38:18.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:18.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:18.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:18.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:18.75#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:38:18.75#ibcon#first serial, iclass 7, count 0 2006.210.07:38:18.75#ibcon#enter sib2, iclass 7, count 0 2006.210.07:38:18.75#ibcon#flushed, iclass 7, count 0 2006.210.07:38:18.75#ibcon#about to write, iclass 7, count 0 2006.210.07:38:18.75#ibcon#wrote, iclass 7, count 0 2006.210.07:38:18.75#ibcon#about to read 3, iclass 7, count 0 2006.210.07:38:18.77#ibcon#read 3, iclass 7, count 0 2006.210.07:38:18.77#ibcon#about to read 4, iclass 7, count 0 2006.210.07:38:18.77#ibcon#read 4, iclass 7, count 0 2006.210.07:38:18.77#ibcon#about to read 5, iclass 7, count 0 2006.210.07:38:18.77#ibcon#read 5, iclass 7, count 0 2006.210.07:38:18.77#ibcon#about to read 6, iclass 7, count 0 2006.210.07:38:18.77#ibcon#read 6, iclass 7, count 0 2006.210.07:38:18.77#ibcon#end of sib2, iclass 7, count 0 2006.210.07:38:18.77#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:38:18.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:38:18.77#ibcon#[25=USB\r\n] 2006.210.07:38:18.77#ibcon#*before write, iclass 7, count 0 2006.210.07:38:18.77#ibcon#enter sib2, iclass 7, count 0 2006.210.07:38:18.77#ibcon#flushed, iclass 7, count 0 2006.210.07:38:18.77#ibcon#about to write, iclass 7, count 0 2006.210.07:38:18.77#ibcon#wrote, iclass 7, count 0 2006.210.07:38:18.77#ibcon#about to read 3, iclass 7, count 0 2006.210.07:38:18.80#ibcon#read 3, iclass 7, count 0 2006.210.07:38:18.80#ibcon#about to read 4, iclass 7, count 0 2006.210.07:38:18.80#ibcon#read 4, iclass 7, count 0 2006.210.07:38:18.80#ibcon#about to read 5, iclass 7, count 0 2006.210.07:38:18.80#ibcon#read 5, iclass 7, count 0 2006.210.07:38:18.80#ibcon#about to read 6, iclass 7, count 0 2006.210.07:38:18.80#ibcon#read 6, iclass 7, count 0 2006.210.07:38:18.80#ibcon#end of sib2, iclass 7, count 0 2006.210.07:38:18.80#ibcon#*after write, iclass 7, count 0 2006.210.07:38:18.80#ibcon#*before return 0, iclass 7, count 0 2006.210.07:38:18.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:18.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:18.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:38:18.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:38:18.80$vc4f8/valo=5,652.99 2006.210.07:38:18.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.07:38:18.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.07:38:18.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:18.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:18.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:18.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:18.80#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:38:18.80#ibcon#first serial, iclass 11, count 0 2006.210.07:38:18.80#ibcon#enter sib2, iclass 11, count 0 2006.210.07:38:18.80#ibcon#flushed, iclass 11, count 0 2006.210.07:38:18.80#ibcon#about to write, iclass 11, count 0 2006.210.07:38:18.80#ibcon#wrote, iclass 11, count 0 2006.210.07:38:18.80#ibcon#about to read 3, iclass 11, count 0 2006.210.07:38:18.82#ibcon#read 3, iclass 11, count 0 2006.210.07:38:18.82#ibcon#about to read 4, iclass 11, count 0 2006.210.07:38:18.82#ibcon#read 4, iclass 11, count 0 2006.210.07:38:18.82#ibcon#about to read 5, iclass 11, count 0 2006.210.07:38:18.82#ibcon#read 5, iclass 11, count 0 2006.210.07:38:18.82#ibcon#about to read 6, iclass 11, count 0 2006.210.07:38:18.82#ibcon#read 6, iclass 11, count 0 2006.210.07:38:18.82#ibcon#end of sib2, iclass 11, count 0 2006.210.07:38:18.82#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:38:18.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:38:18.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:38:18.82#ibcon#*before write, iclass 11, count 0 2006.210.07:38:18.82#ibcon#enter sib2, iclass 11, count 0 2006.210.07:38:18.82#ibcon#flushed, iclass 11, count 0 2006.210.07:38:18.82#ibcon#about to write, iclass 11, count 0 2006.210.07:38:18.82#ibcon#wrote, iclass 11, count 0 2006.210.07:38:18.82#ibcon#about to read 3, iclass 11, count 0 2006.210.07:38:18.86#ibcon#read 3, iclass 11, count 0 2006.210.07:38:18.86#ibcon#about to read 4, iclass 11, count 0 2006.210.07:38:18.86#ibcon#read 4, iclass 11, count 0 2006.210.07:38:18.86#ibcon#about to read 5, iclass 11, count 0 2006.210.07:38:18.86#ibcon#read 5, iclass 11, count 0 2006.210.07:38:18.86#ibcon#about to read 6, iclass 11, count 0 2006.210.07:38:18.86#ibcon#read 6, iclass 11, count 0 2006.210.07:38:18.86#ibcon#end of sib2, iclass 11, count 0 2006.210.07:38:18.86#ibcon#*after write, iclass 11, count 0 2006.210.07:38:18.86#ibcon#*before return 0, iclass 11, count 0 2006.210.07:38:18.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:18.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:18.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:38:18.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:38:18.86$vc4f8/va=5,7 2006.210.07:38:18.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.07:38:18.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.07:38:18.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:18.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:18.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:18.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:18.92#ibcon#enter wrdev, iclass 13, count 2 2006.210.07:38:18.92#ibcon#first serial, iclass 13, count 2 2006.210.07:38:18.92#ibcon#enter sib2, iclass 13, count 2 2006.210.07:38:18.92#ibcon#flushed, iclass 13, count 2 2006.210.07:38:18.92#ibcon#about to write, iclass 13, count 2 2006.210.07:38:18.92#ibcon#wrote, iclass 13, count 2 2006.210.07:38:18.92#ibcon#about to read 3, iclass 13, count 2 2006.210.07:38:18.94#ibcon#read 3, iclass 13, count 2 2006.210.07:38:18.94#ibcon#about to read 4, iclass 13, count 2 2006.210.07:38:18.94#ibcon#read 4, iclass 13, count 2 2006.210.07:38:18.94#ibcon#about to read 5, iclass 13, count 2 2006.210.07:38:18.94#ibcon#read 5, iclass 13, count 2 2006.210.07:38:18.94#ibcon#about to read 6, iclass 13, count 2 2006.210.07:38:18.94#ibcon#read 6, iclass 13, count 2 2006.210.07:38:18.94#ibcon#end of sib2, iclass 13, count 2 2006.210.07:38:18.94#ibcon#*mode == 0, iclass 13, count 2 2006.210.07:38:18.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.07:38:18.94#ibcon#[25=AT05-07\r\n] 2006.210.07:38:18.94#ibcon#*before write, iclass 13, count 2 2006.210.07:38:18.94#ibcon#enter sib2, iclass 13, count 2 2006.210.07:38:18.94#ibcon#flushed, iclass 13, count 2 2006.210.07:38:18.94#ibcon#about to write, iclass 13, count 2 2006.210.07:38:18.94#ibcon#wrote, iclass 13, count 2 2006.210.07:38:18.94#ibcon#about to read 3, iclass 13, count 2 2006.210.07:38:18.97#ibcon#read 3, iclass 13, count 2 2006.210.07:38:18.97#ibcon#about to read 4, iclass 13, count 2 2006.210.07:38:18.97#ibcon#read 4, iclass 13, count 2 2006.210.07:38:18.97#ibcon#about to read 5, iclass 13, count 2 2006.210.07:38:18.97#ibcon#read 5, iclass 13, count 2 2006.210.07:38:18.97#ibcon#about to read 6, iclass 13, count 2 2006.210.07:38:18.97#ibcon#read 6, iclass 13, count 2 2006.210.07:38:18.97#ibcon#end of sib2, iclass 13, count 2 2006.210.07:38:18.97#ibcon#*after write, iclass 13, count 2 2006.210.07:38:18.97#ibcon#*before return 0, iclass 13, count 2 2006.210.07:38:18.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:18.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:18.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.07:38:18.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:18.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:19.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:19.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:19.09#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:38:19.09#ibcon#first serial, iclass 13, count 0 2006.210.07:38:19.09#ibcon#enter sib2, iclass 13, count 0 2006.210.07:38:19.09#ibcon#flushed, iclass 13, count 0 2006.210.07:38:19.09#ibcon#about to write, iclass 13, count 0 2006.210.07:38:19.09#ibcon#wrote, iclass 13, count 0 2006.210.07:38:19.09#ibcon#about to read 3, iclass 13, count 0 2006.210.07:38:19.11#ibcon#read 3, iclass 13, count 0 2006.210.07:38:19.11#ibcon#about to read 4, iclass 13, count 0 2006.210.07:38:19.11#ibcon#read 4, iclass 13, count 0 2006.210.07:38:19.11#ibcon#about to read 5, iclass 13, count 0 2006.210.07:38:19.11#ibcon#read 5, iclass 13, count 0 2006.210.07:38:19.11#ibcon#about to read 6, iclass 13, count 0 2006.210.07:38:19.11#ibcon#read 6, iclass 13, count 0 2006.210.07:38:19.11#ibcon#end of sib2, iclass 13, count 0 2006.210.07:38:19.11#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:38:19.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:38:19.11#ibcon#[25=USB\r\n] 2006.210.07:38:19.11#ibcon#*before write, iclass 13, count 0 2006.210.07:38:19.11#ibcon#enter sib2, iclass 13, count 0 2006.210.07:38:19.11#ibcon#flushed, iclass 13, count 0 2006.210.07:38:19.11#ibcon#about to write, iclass 13, count 0 2006.210.07:38:19.11#ibcon#wrote, iclass 13, count 0 2006.210.07:38:19.11#ibcon#about to read 3, iclass 13, count 0 2006.210.07:38:19.14#ibcon#read 3, iclass 13, count 0 2006.210.07:38:19.14#ibcon#about to read 4, iclass 13, count 0 2006.210.07:38:19.14#ibcon#read 4, iclass 13, count 0 2006.210.07:38:19.14#ibcon#about to read 5, iclass 13, count 0 2006.210.07:38:19.14#ibcon#read 5, iclass 13, count 0 2006.210.07:38:19.14#ibcon#about to read 6, iclass 13, count 0 2006.210.07:38:19.14#ibcon#read 6, iclass 13, count 0 2006.210.07:38:19.14#ibcon#end of sib2, iclass 13, count 0 2006.210.07:38:19.14#ibcon#*after write, iclass 13, count 0 2006.210.07:38:19.14#ibcon#*before return 0, iclass 13, count 0 2006.210.07:38:19.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:19.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:19.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:38:19.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:38:19.14$vc4f8/valo=6,772.99 2006.210.07:38:19.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.07:38:19.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.07:38:19.14#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:19.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:19.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:19.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:19.14#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:38:19.14#ibcon#first serial, iclass 15, count 0 2006.210.07:38:19.14#ibcon#enter sib2, iclass 15, count 0 2006.210.07:38:19.14#ibcon#flushed, iclass 15, count 0 2006.210.07:38:19.14#ibcon#about to write, iclass 15, count 0 2006.210.07:38:19.14#ibcon#wrote, iclass 15, count 0 2006.210.07:38:19.14#ibcon#about to read 3, iclass 15, count 0 2006.210.07:38:19.16#ibcon#read 3, iclass 15, count 0 2006.210.07:38:19.16#ibcon#about to read 4, iclass 15, count 0 2006.210.07:38:19.16#ibcon#read 4, iclass 15, count 0 2006.210.07:38:19.16#ibcon#about to read 5, iclass 15, count 0 2006.210.07:38:19.16#ibcon#read 5, iclass 15, count 0 2006.210.07:38:19.16#ibcon#about to read 6, iclass 15, count 0 2006.210.07:38:19.16#ibcon#read 6, iclass 15, count 0 2006.210.07:38:19.16#ibcon#end of sib2, iclass 15, count 0 2006.210.07:38:19.16#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:38:19.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:38:19.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:38:19.16#ibcon#*before write, iclass 15, count 0 2006.210.07:38:19.16#ibcon#enter sib2, iclass 15, count 0 2006.210.07:38:19.16#ibcon#flushed, iclass 15, count 0 2006.210.07:38:19.16#ibcon#about to write, iclass 15, count 0 2006.210.07:38:19.16#ibcon#wrote, iclass 15, count 0 2006.210.07:38:19.16#ibcon#about to read 3, iclass 15, count 0 2006.210.07:38:19.20#ibcon#read 3, iclass 15, count 0 2006.210.07:38:19.20#ibcon#about to read 4, iclass 15, count 0 2006.210.07:38:19.20#ibcon#read 4, iclass 15, count 0 2006.210.07:38:19.20#ibcon#about to read 5, iclass 15, count 0 2006.210.07:38:19.20#ibcon#read 5, iclass 15, count 0 2006.210.07:38:19.20#ibcon#about to read 6, iclass 15, count 0 2006.210.07:38:19.20#ibcon#read 6, iclass 15, count 0 2006.210.07:38:19.20#ibcon#end of sib2, iclass 15, count 0 2006.210.07:38:19.20#ibcon#*after write, iclass 15, count 0 2006.210.07:38:19.20#ibcon#*before return 0, iclass 15, count 0 2006.210.07:38:19.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:19.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:19.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:38:19.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:38:19.20$vc4f8/va=6,6 2006.210.07:38:19.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.07:38:19.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.07:38:19.20#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:19.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:38:19.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:38:19.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:38:19.26#ibcon#enter wrdev, iclass 17, count 2 2006.210.07:38:19.26#ibcon#first serial, iclass 17, count 2 2006.210.07:38:19.26#ibcon#enter sib2, iclass 17, count 2 2006.210.07:38:19.26#ibcon#flushed, iclass 17, count 2 2006.210.07:38:19.26#ibcon#about to write, iclass 17, count 2 2006.210.07:38:19.26#ibcon#wrote, iclass 17, count 2 2006.210.07:38:19.26#ibcon#about to read 3, iclass 17, count 2 2006.210.07:38:19.28#ibcon#read 3, iclass 17, count 2 2006.210.07:38:19.28#ibcon#about to read 4, iclass 17, count 2 2006.210.07:38:19.28#ibcon#read 4, iclass 17, count 2 2006.210.07:38:19.28#ibcon#about to read 5, iclass 17, count 2 2006.210.07:38:19.28#ibcon#read 5, iclass 17, count 2 2006.210.07:38:19.28#ibcon#about to read 6, iclass 17, count 2 2006.210.07:38:19.28#ibcon#read 6, iclass 17, count 2 2006.210.07:38:19.28#ibcon#end of sib2, iclass 17, count 2 2006.210.07:38:19.28#ibcon#*mode == 0, iclass 17, count 2 2006.210.07:38:19.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.07:38:19.28#ibcon#[25=AT06-06\r\n] 2006.210.07:38:19.28#ibcon#*before write, iclass 17, count 2 2006.210.07:38:19.28#ibcon#enter sib2, iclass 17, count 2 2006.210.07:38:19.28#ibcon#flushed, iclass 17, count 2 2006.210.07:38:19.28#ibcon#about to write, iclass 17, count 2 2006.210.07:38:19.28#ibcon#wrote, iclass 17, count 2 2006.210.07:38:19.28#ibcon#about to read 3, iclass 17, count 2 2006.210.07:38:19.31#ibcon#read 3, iclass 17, count 2 2006.210.07:38:19.31#ibcon#about to read 4, iclass 17, count 2 2006.210.07:38:19.31#ibcon#read 4, iclass 17, count 2 2006.210.07:38:19.31#ibcon#about to read 5, iclass 17, count 2 2006.210.07:38:19.31#ibcon#read 5, iclass 17, count 2 2006.210.07:38:19.31#ibcon#about to read 6, iclass 17, count 2 2006.210.07:38:19.31#ibcon#read 6, iclass 17, count 2 2006.210.07:38:19.31#ibcon#end of sib2, iclass 17, count 2 2006.210.07:38:19.31#ibcon#*after write, iclass 17, count 2 2006.210.07:38:19.31#ibcon#*before return 0, iclass 17, count 2 2006.210.07:38:19.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:38:19.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:38:19.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.07:38:19.31#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:19.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:38:19.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:38:19.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:38:19.43#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:38:19.43#ibcon#first serial, iclass 17, count 0 2006.210.07:38:19.43#ibcon#enter sib2, iclass 17, count 0 2006.210.07:38:19.43#ibcon#flushed, iclass 17, count 0 2006.210.07:38:19.43#ibcon#about to write, iclass 17, count 0 2006.210.07:38:19.43#ibcon#wrote, iclass 17, count 0 2006.210.07:38:19.43#ibcon#about to read 3, iclass 17, count 0 2006.210.07:38:19.45#ibcon#read 3, iclass 17, count 0 2006.210.07:38:19.45#ibcon#about to read 4, iclass 17, count 0 2006.210.07:38:19.45#ibcon#read 4, iclass 17, count 0 2006.210.07:38:19.45#ibcon#about to read 5, iclass 17, count 0 2006.210.07:38:19.45#ibcon#read 5, iclass 17, count 0 2006.210.07:38:19.45#ibcon#about to read 6, iclass 17, count 0 2006.210.07:38:19.45#ibcon#read 6, iclass 17, count 0 2006.210.07:38:19.45#ibcon#end of sib2, iclass 17, count 0 2006.210.07:38:19.45#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:38:19.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:38:19.45#ibcon#[25=USB\r\n] 2006.210.07:38:19.45#ibcon#*before write, iclass 17, count 0 2006.210.07:38:19.45#ibcon#enter sib2, iclass 17, count 0 2006.210.07:38:19.45#ibcon#flushed, iclass 17, count 0 2006.210.07:38:19.45#ibcon#about to write, iclass 17, count 0 2006.210.07:38:19.45#ibcon#wrote, iclass 17, count 0 2006.210.07:38:19.45#ibcon#about to read 3, iclass 17, count 0 2006.210.07:38:19.48#ibcon#read 3, iclass 17, count 0 2006.210.07:38:19.48#ibcon#about to read 4, iclass 17, count 0 2006.210.07:38:19.48#ibcon#read 4, iclass 17, count 0 2006.210.07:38:19.48#ibcon#about to read 5, iclass 17, count 0 2006.210.07:38:19.48#ibcon#read 5, iclass 17, count 0 2006.210.07:38:19.48#ibcon#about to read 6, iclass 17, count 0 2006.210.07:38:19.48#ibcon#read 6, iclass 17, count 0 2006.210.07:38:19.48#ibcon#end of sib2, iclass 17, count 0 2006.210.07:38:19.48#ibcon#*after write, iclass 17, count 0 2006.210.07:38:19.48#ibcon#*before return 0, iclass 17, count 0 2006.210.07:38:19.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:38:19.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:38:19.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:38:19.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:38:19.48$vc4f8/valo=7,832.99 2006.210.07:38:19.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.07:38:19.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.07:38:19.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:19.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:38:19.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:38:19.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:38:19.48#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:38:19.48#ibcon#first serial, iclass 19, count 0 2006.210.07:38:19.48#ibcon#enter sib2, iclass 19, count 0 2006.210.07:38:19.48#ibcon#flushed, iclass 19, count 0 2006.210.07:38:19.48#ibcon#about to write, iclass 19, count 0 2006.210.07:38:19.48#ibcon#wrote, iclass 19, count 0 2006.210.07:38:19.48#ibcon#about to read 3, iclass 19, count 0 2006.210.07:38:19.50#ibcon#read 3, iclass 19, count 0 2006.210.07:38:19.50#ibcon#about to read 4, iclass 19, count 0 2006.210.07:38:19.50#ibcon#read 4, iclass 19, count 0 2006.210.07:38:19.50#ibcon#about to read 5, iclass 19, count 0 2006.210.07:38:19.50#ibcon#read 5, iclass 19, count 0 2006.210.07:38:19.50#ibcon#about to read 6, iclass 19, count 0 2006.210.07:38:19.50#ibcon#read 6, iclass 19, count 0 2006.210.07:38:19.50#ibcon#end of sib2, iclass 19, count 0 2006.210.07:38:19.50#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:38:19.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:38:19.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:38:19.50#ibcon#*before write, iclass 19, count 0 2006.210.07:38:19.50#ibcon#enter sib2, iclass 19, count 0 2006.210.07:38:19.50#ibcon#flushed, iclass 19, count 0 2006.210.07:38:19.50#ibcon#about to write, iclass 19, count 0 2006.210.07:38:19.50#ibcon#wrote, iclass 19, count 0 2006.210.07:38:19.50#ibcon#about to read 3, iclass 19, count 0 2006.210.07:38:19.54#ibcon#read 3, iclass 19, count 0 2006.210.07:38:19.54#ibcon#about to read 4, iclass 19, count 0 2006.210.07:38:19.54#ibcon#read 4, iclass 19, count 0 2006.210.07:38:19.54#ibcon#about to read 5, iclass 19, count 0 2006.210.07:38:19.54#ibcon#read 5, iclass 19, count 0 2006.210.07:38:19.54#ibcon#about to read 6, iclass 19, count 0 2006.210.07:38:19.54#ibcon#read 6, iclass 19, count 0 2006.210.07:38:19.54#ibcon#end of sib2, iclass 19, count 0 2006.210.07:38:19.54#ibcon#*after write, iclass 19, count 0 2006.210.07:38:19.54#ibcon#*before return 0, iclass 19, count 0 2006.210.07:38:19.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:38:19.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:38:19.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:38:19.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:38:19.54$vc4f8/va=7,6 2006.210.07:38:19.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.07:38:19.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.07:38:19.54#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:19.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:38:19.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:38:19.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:38:19.60#ibcon#enter wrdev, iclass 21, count 2 2006.210.07:38:19.60#ibcon#first serial, iclass 21, count 2 2006.210.07:38:19.60#ibcon#enter sib2, iclass 21, count 2 2006.210.07:38:19.60#ibcon#flushed, iclass 21, count 2 2006.210.07:38:19.60#ibcon#about to write, iclass 21, count 2 2006.210.07:38:19.60#ibcon#wrote, iclass 21, count 2 2006.210.07:38:19.60#ibcon#about to read 3, iclass 21, count 2 2006.210.07:38:19.62#ibcon#read 3, iclass 21, count 2 2006.210.07:38:19.62#ibcon#about to read 4, iclass 21, count 2 2006.210.07:38:19.62#ibcon#read 4, iclass 21, count 2 2006.210.07:38:19.62#ibcon#about to read 5, iclass 21, count 2 2006.210.07:38:19.62#ibcon#read 5, iclass 21, count 2 2006.210.07:38:19.62#ibcon#about to read 6, iclass 21, count 2 2006.210.07:38:19.62#ibcon#read 6, iclass 21, count 2 2006.210.07:38:19.62#ibcon#end of sib2, iclass 21, count 2 2006.210.07:38:19.62#ibcon#*mode == 0, iclass 21, count 2 2006.210.07:38:19.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.07:38:19.62#ibcon#[25=AT07-06\r\n] 2006.210.07:38:19.62#ibcon#*before write, iclass 21, count 2 2006.210.07:38:19.62#ibcon#enter sib2, iclass 21, count 2 2006.210.07:38:19.62#ibcon#flushed, iclass 21, count 2 2006.210.07:38:19.62#ibcon#about to write, iclass 21, count 2 2006.210.07:38:19.62#ibcon#wrote, iclass 21, count 2 2006.210.07:38:19.62#ibcon#about to read 3, iclass 21, count 2 2006.210.07:38:19.65#ibcon#read 3, iclass 21, count 2 2006.210.07:38:19.65#ibcon#about to read 4, iclass 21, count 2 2006.210.07:38:19.65#ibcon#read 4, iclass 21, count 2 2006.210.07:38:19.65#ibcon#about to read 5, iclass 21, count 2 2006.210.07:38:19.65#ibcon#read 5, iclass 21, count 2 2006.210.07:38:19.65#ibcon#about to read 6, iclass 21, count 2 2006.210.07:38:19.65#ibcon#read 6, iclass 21, count 2 2006.210.07:38:19.65#ibcon#end of sib2, iclass 21, count 2 2006.210.07:38:19.65#ibcon#*after write, iclass 21, count 2 2006.210.07:38:19.65#ibcon#*before return 0, iclass 21, count 2 2006.210.07:38:19.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:38:19.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:38:19.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.07:38:19.65#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:19.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:38:19.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:38:19.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:38:19.77#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:38:19.77#ibcon#first serial, iclass 21, count 0 2006.210.07:38:19.77#ibcon#enter sib2, iclass 21, count 0 2006.210.07:38:19.77#ibcon#flushed, iclass 21, count 0 2006.210.07:38:19.77#ibcon#about to write, iclass 21, count 0 2006.210.07:38:19.77#ibcon#wrote, iclass 21, count 0 2006.210.07:38:19.77#ibcon#about to read 3, iclass 21, count 0 2006.210.07:38:19.79#ibcon#read 3, iclass 21, count 0 2006.210.07:38:19.79#ibcon#about to read 4, iclass 21, count 0 2006.210.07:38:19.79#ibcon#read 4, iclass 21, count 0 2006.210.07:38:19.79#ibcon#about to read 5, iclass 21, count 0 2006.210.07:38:19.79#ibcon#read 5, iclass 21, count 0 2006.210.07:38:19.79#ibcon#about to read 6, iclass 21, count 0 2006.210.07:38:19.79#ibcon#read 6, iclass 21, count 0 2006.210.07:38:19.79#ibcon#end of sib2, iclass 21, count 0 2006.210.07:38:19.79#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:38:19.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:38:19.79#ibcon#[25=USB\r\n] 2006.210.07:38:19.79#ibcon#*before write, iclass 21, count 0 2006.210.07:38:19.79#ibcon#enter sib2, iclass 21, count 0 2006.210.07:38:19.79#ibcon#flushed, iclass 21, count 0 2006.210.07:38:19.79#ibcon#about to write, iclass 21, count 0 2006.210.07:38:19.79#ibcon#wrote, iclass 21, count 0 2006.210.07:38:19.79#ibcon#about to read 3, iclass 21, count 0 2006.210.07:38:19.82#ibcon#read 3, iclass 21, count 0 2006.210.07:38:19.82#ibcon#about to read 4, iclass 21, count 0 2006.210.07:38:19.82#ibcon#read 4, iclass 21, count 0 2006.210.07:38:19.82#ibcon#about to read 5, iclass 21, count 0 2006.210.07:38:19.82#ibcon#read 5, iclass 21, count 0 2006.210.07:38:19.82#ibcon#about to read 6, iclass 21, count 0 2006.210.07:38:19.82#ibcon#read 6, iclass 21, count 0 2006.210.07:38:19.82#ibcon#end of sib2, iclass 21, count 0 2006.210.07:38:19.82#ibcon#*after write, iclass 21, count 0 2006.210.07:38:19.82#ibcon#*before return 0, iclass 21, count 0 2006.210.07:38:19.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:38:19.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:38:19.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:38:19.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:38:19.82$vc4f8/valo=8,852.99 2006.210.07:38:19.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.07:38:19.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.07:38:19.82#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:19.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:38:19.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:38:19.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:38:19.82#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:38:19.82#ibcon#first serial, iclass 23, count 0 2006.210.07:38:19.82#ibcon#enter sib2, iclass 23, count 0 2006.210.07:38:19.82#ibcon#flushed, iclass 23, count 0 2006.210.07:38:19.82#ibcon#about to write, iclass 23, count 0 2006.210.07:38:19.82#ibcon#wrote, iclass 23, count 0 2006.210.07:38:19.82#ibcon#about to read 3, iclass 23, count 0 2006.210.07:38:19.84#ibcon#read 3, iclass 23, count 0 2006.210.07:38:19.84#ibcon#about to read 4, iclass 23, count 0 2006.210.07:38:19.84#ibcon#read 4, iclass 23, count 0 2006.210.07:38:19.84#ibcon#about to read 5, iclass 23, count 0 2006.210.07:38:19.84#ibcon#read 5, iclass 23, count 0 2006.210.07:38:19.84#ibcon#about to read 6, iclass 23, count 0 2006.210.07:38:19.84#ibcon#read 6, iclass 23, count 0 2006.210.07:38:19.84#ibcon#end of sib2, iclass 23, count 0 2006.210.07:38:19.84#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:38:19.84#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:38:19.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:38:19.84#ibcon#*before write, iclass 23, count 0 2006.210.07:38:19.84#ibcon#enter sib2, iclass 23, count 0 2006.210.07:38:19.84#ibcon#flushed, iclass 23, count 0 2006.210.07:38:19.84#ibcon#about to write, iclass 23, count 0 2006.210.07:38:19.84#ibcon#wrote, iclass 23, count 0 2006.210.07:38:19.84#ibcon#about to read 3, iclass 23, count 0 2006.210.07:38:19.88#ibcon#read 3, iclass 23, count 0 2006.210.07:38:19.88#ibcon#about to read 4, iclass 23, count 0 2006.210.07:38:19.88#ibcon#read 4, iclass 23, count 0 2006.210.07:38:19.88#ibcon#about to read 5, iclass 23, count 0 2006.210.07:38:19.88#ibcon#read 5, iclass 23, count 0 2006.210.07:38:19.88#ibcon#about to read 6, iclass 23, count 0 2006.210.07:38:19.88#ibcon#read 6, iclass 23, count 0 2006.210.07:38:19.88#ibcon#end of sib2, iclass 23, count 0 2006.210.07:38:19.88#ibcon#*after write, iclass 23, count 0 2006.210.07:38:19.88#ibcon#*before return 0, iclass 23, count 0 2006.210.07:38:19.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:38:19.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:38:19.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:38:19.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:38:19.88$vc4f8/va=8,7 2006.210.07:38:19.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.07:38:19.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.07:38:19.88#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:19.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:38:19.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:38:19.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:38:19.94#ibcon#enter wrdev, iclass 25, count 2 2006.210.07:38:19.94#ibcon#first serial, iclass 25, count 2 2006.210.07:38:19.94#ibcon#enter sib2, iclass 25, count 2 2006.210.07:38:19.94#ibcon#flushed, iclass 25, count 2 2006.210.07:38:19.94#ibcon#about to write, iclass 25, count 2 2006.210.07:38:19.94#ibcon#wrote, iclass 25, count 2 2006.210.07:38:19.94#ibcon#about to read 3, iclass 25, count 2 2006.210.07:38:19.96#ibcon#read 3, iclass 25, count 2 2006.210.07:38:19.96#ibcon#about to read 4, iclass 25, count 2 2006.210.07:38:19.96#ibcon#read 4, iclass 25, count 2 2006.210.07:38:19.96#ibcon#about to read 5, iclass 25, count 2 2006.210.07:38:19.96#ibcon#read 5, iclass 25, count 2 2006.210.07:38:19.96#ibcon#about to read 6, iclass 25, count 2 2006.210.07:38:19.96#ibcon#read 6, iclass 25, count 2 2006.210.07:38:19.96#ibcon#end of sib2, iclass 25, count 2 2006.210.07:38:19.96#ibcon#*mode == 0, iclass 25, count 2 2006.210.07:38:19.96#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.07:38:19.96#ibcon#[25=AT08-07\r\n] 2006.210.07:38:19.96#ibcon#*before write, iclass 25, count 2 2006.210.07:38:19.96#ibcon#enter sib2, iclass 25, count 2 2006.210.07:38:19.96#ibcon#flushed, iclass 25, count 2 2006.210.07:38:19.96#ibcon#about to write, iclass 25, count 2 2006.210.07:38:19.96#ibcon#wrote, iclass 25, count 2 2006.210.07:38:19.96#ibcon#about to read 3, iclass 25, count 2 2006.210.07:38:19.99#ibcon#read 3, iclass 25, count 2 2006.210.07:38:19.99#ibcon#about to read 4, iclass 25, count 2 2006.210.07:38:19.99#ibcon#read 4, iclass 25, count 2 2006.210.07:38:19.99#ibcon#about to read 5, iclass 25, count 2 2006.210.07:38:19.99#ibcon#read 5, iclass 25, count 2 2006.210.07:38:19.99#ibcon#about to read 6, iclass 25, count 2 2006.210.07:38:19.99#ibcon#read 6, iclass 25, count 2 2006.210.07:38:19.99#ibcon#end of sib2, iclass 25, count 2 2006.210.07:38:19.99#ibcon#*after write, iclass 25, count 2 2006.210.07:38:19.99#ibcon#*before return 0, iclass 25, count 2 2006.210.07:38:19.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:38:19.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:38:19.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.07:38:19.99#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:19.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:38:20.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:38:20.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:38:20.11#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:38:20.11#ibcon#first serial, iclass 25, count 0 2006.210.07:38:20.11#ibcon#enter sib2, iclass 25, count 0 2006.210.07:38:20.11#ibcon#flushed, iclass 25, count 0 2006.210.07:38:20.11#ibcon#about to write, iclass 25, count 0 2006.210.07:38:20.11#ibcon#wrote, iclass 25, count 0 2006.210.07:38:20.11#ibcon#about to read 3, iclass 25, count 0 2006.210.07:38:20.13#ibcon#read 3, iclass 25, count 0 2006.210.07:38:20.13#ibcon#about to read 4, iclass 25, count 0 2006.210.07:38:20.13#ibcon#read 4, iclass 25, count 0 2006.210.07:38:20.13#ibcon#about to read 5, iclass 25, count 0 2006.210.07:38:20.13#ibcon#read 5, iclass 25, count 0 2006.210.07:38:20.13#ibcon#about to read 6, iclass 25, count 0 2006.210.07:38:20.13#ibcon#read 6, iclass 25, count 0 2006.210.07:38:20.13#ibcon#end of sib2, iclass 25, count 0 2006.210.07:38:20.13#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:38:20.13#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:38:20.13#ibcon#[25=USB\r\n] 2006.210.07:38:20.13#ibcon#*before write, iclass 25, count 0 2006.210.07:38:20.13#ibcon#enter sib2, iclass 25, count 0 2006.210.07:38:20.13#ibcon#flushed, iclass 25, count 0 2006.210.07:38:20.13#ibcon#about to write, iclass 25, count 0 2006.210.07:38:20.13#ibcon#wrote, iclass 25, count 0 2006.210.07:38:20.13#ibcon#about to read 3, iclass 25, count 0 2006.210.07:38:20.16#ibcon#read 3, iclass 25, count 0 2006.210.07:38:20.16#ibcon#about to read 4, iclass 25, count 0 2006.210.07:38:20.16#ibcon#read 4, iclass 25, count 0 2006.210.07:38:20.16#ibcon#about to read 5, iclass 25, count 0 2006.210.07:38:20.16#ibcon#read 5, iclass 25, count 0 2006.210.07:38:20.16#ibcon#about to read 6, iclass 25, count 0 2006.210.07:38:20.16#ibcon#read 6, iclass 25, count 0 2006.210.07:38:20.16#ibcon#end of sib2, iclass 25, count 0 2006.210.07:38:20.16#ibcon#*after write, iclass 25, count 0 2006.210.07:38:20.16#ibcon#*before return 0, iclass 25, count 0 2006.210.07:38:20.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:38:20.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:38:20.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:38:20.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:38:20.16$vc4f8/vblo=1,632.99 2006.210.07:38:20.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.07:38:20.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.07:38:20.16#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:20.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:38:20.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:38:20.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:38:20.16#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:38:20.16#ibcon#first serial, iclass 27, count 0 2006.210.07:38:20.16#ibcon#enter sib2, iclass 27, count 0 2006.210.07:38:20.16#ibcon#flushed, iclass 27, count 0 2006.210.07:38:20.16#ibcon#about to write, iclass 27, count 0 2006.210.07:38:20.16#ibcon#wrote, iclass 27, count 0 2006.210.07:38:20.16#ibcon#about to read 3, iclass 27, count 0 2006.210.07:38:20.18#ibcon#read 3, iclass 27, count 0 2006.210.07:38:20.18#ibcon#about to read 4, iclass 27, count 0 2006.210.07:38:20.18#ibcon#read 4, iclass 27, count 0 2006.210.07:38:20.18#ibcon#about to read 5, iclass 27, count 0 2006.210.07:38:20.18#ibcon#read 5, iclass 27, count 0 2006.210.07:38:20.18#ibcon#about to read 6, iclass 27, count 0 2006.210.07:38:20.18#ibcon#read 6, iclass 27, count 0 2006.210.07:38:20.18#ibcon#end of sib2, iclass 27, count 0 2006.210.07:38:20.18#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:38:20.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:38:20.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:38:20.18#ibcon#*before write, iclass 27, count 0 2006.210.07:38:20.18#ibcon#enter sib2, iclass 27, count 0 2006.210.07:38:20.18#ibcon#flushed, iclass 27, count 0 2006.210.07:38:20.18#ibcon#about to write, iclass 27, count 0 2006.210.07:38:20.18#ibcon#wrote, iclass 27, count 0 2006.210.07:38:20.18#ibcon#about to read 3, iclass 27, count 0 2006.210.07:38:20.22#ibcon#read 3, iclass 27, count 0 2006.210.07:38:20.22#ibcon#about to read 4, iclass 27, count 0 2006.210.07:38:20.22#ibcon#read 4, iclass 27, count 0 2006.210.07:38:20.22#ibcon#about to read 5, iclass 27, count 0 2006.210.07:38:20.22#ibcon#read 5, iclass 27, count 0 2006.210.07:38:20.22#ibcon#about to read 6, iclass 27, count 0 2006.210.07:38:20.22#ibcon#read 6, iclass 27, count 0 2006.210.07:38:20.22#ibcon#end of sib2, iclass 27, count 0 2006.210.07:38:20.22#ibcon#*after write, iclass 27, count 0 2006.210.07:38:20.22#ibcon#*before return 0, iclass 27, count 0 2006.210.07:38:20.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:38:20.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:38:20.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:38:20.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:38:20.22$vc4f8/vb=1,4 2006.210.07:38:20.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.07:38:20.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.07:38:20.22#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:20.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:38:20.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:38:20.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:38:20.22#ibcon#enter wrdev, iclass 29, count 2 2006.210.07:38:20.22#ibcon#first serial, iclass 29, count 2 2006.210.07:38:20.22#ibcon#enter sib2, iclass 29, count 2 2006.210.07:38:20.22#ibcon#flushed, iclass 29, count 2 2006.210.07:38:20.22#ibcon#about to write, iclass 29, count 2 2006.210.07:38:20.22#ibcon#wrote, iclass 29, count 2 2006.210.07:38:20.22#ibcon#about to read 3, iclass 29, count 2 2006.210.07:38:20.24#ibcon#read 3, iclass 29, count 2 2006.210.07:38:20.24#ibcon#about to read 4, iclass 29, count 2 2006.210.07:38:20.24#ibcon#read 4, iclass 29, count 2 2006.210.07:38:20.24#ibcon#about to read 5, iclass 29, count 2 2006.210.07:38:20.24#ibcon#read 5, iclass 29, count 2 2006.210.07:38:20.24#ibcon#about to read 6, iclass 29, count 2 2006.210.07:38:20.24#ibcon#read 6, iclass 29, count 2 2006.210.07:38:20.24#ibcon#end of sib2, iclass 29, count 2 2006.210.07:38:20.24#ibcon#*mode == 0, iclass 29, count 2 2006.210.07:38:20.24#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.07:38:20.24#ibcon#[27=AT01-04\r\n] 2006.210.07:38:20.24#ibcon#*before write, iclass 29, count 2 2006.210.07:38:20.24#ibcon#enter sib2, iclass 29, count 2 2006.210.07:38:20.24#ibcon#flushed, iclass 29, count 2 2006.210.07:38:20.24#ibcon#about to write, iclass 29, count 2 2006.210.07:38:20.24#ibcon#wrote, iclass 29, count 2 2006.210.07:38:20.24#ibcon#about to read 3, iclass 29, count 2 2006.210.07:38:20.27#ibcon#read 3, iclass 29, count 2 2006.210.07:38:20.27#ibcon#about to read 4, iclass 29, count 2 2006.210.07:38:20.27#ibcon#read 4, iclass 29, count 2 2006.210.07:38:20.27#ibcon#about to read 5, iclass 29, count 2 2006.210.07:38:20.27#ibcon#read 5, iclass 29, count 2 2006.210.07:38:20.27#ibcon#about to read 6, iclass 29, count 2 2006.210.07:38:20.27#ibcon#read 6, iclass 29, count 2 2006.210.07:38:20.27#ibcon#end of sib2, iclass 29, count 2 2006.210.07:38:20.27#ibcon#*after write, iclass 29, count 2 2006.210.07:38:20.27#ibcon#*before return 0, iclass 29, count 2 2006.210.07:38:20.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:38:20.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:38:20.27#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.07:38:20.27#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:20.27#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:38:20.39#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:38:20.39#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:38:20.39#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:38:20.39#ibcon#first serial, iclass 29, count 0 2006.210.07:38:20.39#ibcon#enter sib2, iclass 29, count 0 2006.210.07:38:20.39#ibcon#flushed, iclass 29, count 0 2006.210.07:38:20.39#ibcon#about to write, iclass 29, count 0 2006.210.07:38:20.39#ibcon#wrote, iclass 29, count 0 2006.210.07:38:20.39#ibcon#about to read 3, iclass 29, count 0 2006.210.07:38:20.41#ibcon#read 3, iclass 29, count 0 2006.210.07:38:20.41#ibcon#about to read 4, iclass 29, count 0 2006.210.07:38:20.41#ibcon#read 4, iclass 29, count 0 2006.210.07:38:20.41#ibcon#about to read 5, iclass 29, count 0 2006.210.07:38:20.41#ibcon#read 5, iclass 29, count 0 2006.210.07:38:20.41#ibcon#about to read 6, iclass 29, count 0 2006.210.07:38:20.41#ibcon#read 6, iclass 29, count 0 2006.210.07:38:20.41#ibcon#end of sib2, iclass 29, count 0 2006.210.07:38:20.41#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:38:20.41#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:38:20.41#ibcon#[27=USB\r\n] 2006.210.07:38:20.41#ibcon#*before write, iclass 29, count 0 2006.210.07:38:20.41#ibcon#enter sib2, iclass 29, count 0 2006.210.07:38:20.41#ibcon#flushed, iclass 29, count 0 2006.210.07:38:20.41#ibcon#about to write, iclass 29, count 0 2006.210.07:38:20.41#ibcon#wrote, iclass 29, count 0 2006.210.07:38:20.41#ibcon#about to read 3, iclass 29, count 0 2006.210.07:38:20.44#ibcon#read 3, iclass 29, count 0 2006.210.07:38:20.44#ibcon#about to read 4, iclass 29, count 0 2006.210.07:38:20.44#ibcon#read 4, iclass 29, count 0 2006.210.07:38:20.44#ibcon#about to read 5, iclass 29, count 0 2006.210.07:38:20.44#ibcon#read 5, iclass 29, count 0 2006.210.07:38:20.44#ibcon#about to read 6, iclass 29, count 0 2006.210.07:38:20.44#ibcon#read 6, iclass 29, count 0 2006.210.07:38:20.44#ibcon#end of sib2, iclass 29, count 0 2006.210.07:38:20.44#ibcon#*after write, iclass 29, count 0 2006.210.07:38:20.44#ibcon#*before return 0, iclass 29, count 0 2006.210.07:38:20.44#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:38:20.44#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:38:20.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:38:20.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:38:20.44$vc4f8/vblo=2,640.99 2006.210.07:38:20.44#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.07:38:20.44#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.07:38:20.44#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:20.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:20.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:20.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:20.44#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:38:20.44#ibcon#first serial, iclass 31, count 0 2006.210.07:38:20.44#ibcon#enter sib2, iclass 31, count 0 2006.210.07:38:20.44#ibcon#flushed, iclass 31, count 0 2006.210.07:38:20.44#ibcon#about to write, iclass 31, count 0 2006.210.07:38:20.44#ibcon#wrote, iclass 31, count 0 2006.210.07:38:20.44#ibcon#about to read 3, iclass 31, count 0 2006.210.07:38:20.46#ibcon#read 3, iclass 31, count 0 2006.210.07:38:20.46#ibcon#about to read 4, iclass 31, count 0 2006.210.07:38:20.46#ibcon#read 4, iclass 31, count 0 2006.210.07:38:20.46#ibcon#about to read 5, iclass 31, count 0 2006.210.07:38:20.46#ibcon#read 5, iclass 31, count 0 2006.210.07:38:20.46#ibcon#about to read 6, iclass 31, count 0 2006.210.07:38:20.46#ibcon#read 6, iclass 31, count 0 2006.210.07:38:20.46#ibcon#end of sib2, iclass 31, count 0 2006.210.07:38:20.46#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:38:20.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:38:20.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:38:20.46#ibcon#*before write, iclass 31, count 0 2006.210.07:38:20.46#ibcon#enter sib2, iclass 31, count 0 2006.210.07:38:20.46#ibcon#flushed, iclass 31, count 0 2006.210.07:38:20.46#ibcon#about to write, iclass 31, count 0 2006.210.07:38:20.46#ibcon#wrote, iclass 31, count 0 2006.210.07:38:20.46#ibcon#about to read 3, iclass 31, count 0 2006.210.07:38:20.50#ibcon#read 3, iclass 31, count 0 2006.210.07:38:20.50#ibcon#about to read 4, iclass 31, count 0 2006.210.07:38:20.50#ibcon#read 4, iclass 31, count 0 2006.210.07:38:20.50#ibcon#about to read 5, iclass 31, count 0 2006.210.07:38:20.50#ibcon#read 5, iclass 31, count 0 2006.210.07:38:20.50#ibcon#about to read 6, iclass 31, count 0 2006.210.07:38:20.50#ibcon#read 6, iclass 31, count 0 2006.210.07:38:20.50#ibcon#end of sib2, iclass 31, count 0 2006.210.07:38:20.50#ibcon#*after write, iclass 31, count 0 2006.210.07:38:20.50#ibcon#*before return 0, iclass 31, count 0 2006.210.07:38:20.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:20.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:38:20.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:38:20.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:38:20.50$vc4f8/vb=2,4 2006.210.07:38:20.50#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.07:38:20.50#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.07:38:20.50#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:20.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:20.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:20.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:20.56#ibcon#enter wrdev, iclass 33, count 2 2006.210.07:38:20.56#ibcon#first serial, iclass 33, count 2 2006.210.07:38:20.56#ibcon#enter sib2, iclass 33, count 2 2006.210.07:38:20.56#ibcon#flushed, iclass 33, count 2 2006.210.07:38:20.56#ibcon#about to write, iclass 33, count 2 2006.210.07:38:20.56#ibcon#wrote, iclass 33, count 2 2006.210.07:38:20.56#ibcon#about to read 3, iclass 33, count 2 2006.210.07:38:20.58#ibcon#read 3, iclass 33, count 2 2006.210.07:38:20.58#ibcon#about to read 4, iclass 33, count 2 2006.210.07:38:20.58#ibcon#read 4, iclass 33, count 2 2006.210.07:38:20.58#ibcon#about to read 5, iclass 33, count 2 2006.210.07:38:20.58#ibcon#read 5, iclass 33, count 2 2006.210.07:38:20.58#ibcon#about to read 6, iclass 33, count 2 2006.210.07:38:20.58#ibcon#read 6, iclass 33, count 2 2006.210.07:38:20.58#ibcon#end of sib2, iclass 33, count 2 2006.210.07:38:20.58#ibcon#*mode == 0, iclass 33, count 2 2006.210.07:38:20.58#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.07:38:20.58#ibcon#[27=AT02-04\r\n] 2006.210.07:38:20.58#ibcon#*before write, iclass 33, count 2 2006.210.07:38:20.58#ibcon#enter sib2, iclass 33, count 2 2006.210.07:38:20.58#ibcon#flushed, iclass 33, count 2 2006.210.07:38:20.58#ibcon#about to write, iclass 33, count 2 2006.210.07:38:20.58#ibcon#wrote, iclass 33, count 2 2006.210.07:38:20.58#ibcon#about to read 3, iclass 33, count 2 2006.210.07:38:20.61#ibcon#read 3, iclass 33, count 2 2006.210.07:38:20.61#ibcon#about to read 4, iclass 33, count 2 2006.210.07:38:20.61#ibcon#read 4, iclass 33, count 2 2006.210.07:38:20.61#ibcon#about to read 5, iclass 33, count 2 2006.210.07:38:20.61#ibcon#read 5, iclass 33, count 2 2006.210.07:38:20.61#ibcon#about to read 6, iclass 33, count 2 2006.210.07:38:20.61#ibcon#read 6, iclass 33, count 2 2006.210.07:38:20.61#ibcon#end of sib2, iclass 33, count 2 2006.210.07:38:20.61#ibcon#*after write, iclass 33, count 2 2006.210.07:38:20.61#ibcon#*before return 0, iclass 33, count 2 2006.210.07:38:20.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:20.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:38:20.61#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.07:38:20.61#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:20.61#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:20.73#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:20.73#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:20.73#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:38:20.73#ibcon#first serial, iclass 33, count 0 2006.210.07:38:20.73#ibcon#enter sib2, iclass 33, count 0 2006.210.07:38:20.73#ibcon#flushed, iclass 33, count 0 2006.210.07:38:20.73#ibcon#about to write, iclass 33, count 0 2006.210.07:38:20.73#ibcon#wrote, iclass 33, count 0 2006.210.07:38:20.73#ibcon#about to read 3, iclass 33, count 0 2006.210.07:38:20.75#ibcon#read 3, iclass 33, count 0 2006.210.07:38:20.75#ibcon#about to read 4, iclass 33, count 0 2006.210.07:38:20.75#ibcon#read 4, iclass 33, count 0 2006.210.07:38:20.75#ibcon#about to read 5, iclass 33, count 0 2006.210.07:38:20.75#ibcon#read 5, iclass 33, count 0 2006.210.07:38:20.75#ibcon#about to read 6, iclass 33, count 0 2006.210.07:38:20.75#ibcon#read 6, iclass 33, count 0 2006.210.07:38:20.75#ibcon#end of sib2, iclass 33, count 0 2006.210.07:38:20.75#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:38:20.75#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:38:20.75#ibcon#[27=USB\r\n] 2006.210.07:38:20.75#ibcon#*before write, iclass 33, count 0 2006.210.07:38:20.75#ibcon#enter sib2, iclass 33, count 0 2006.210.07:38:20.75#ibcon#flushed, iclass 33, count 0 2006.210.07:38:20.75#ibcon#about to write, iclass 33, count 0 2006.210.07:38:20.75#ibcon#wrote, iclass 33, count 0 2006.210.07:38:20.75#ibcon#about to read 3, iclass 33, count 0 2006.210.07:38:20.78#ibcon#read 3, iclass 33, count 0 2006.210.07:38:20.78#ibcon#about to read 4, iclass 33, count 0 2006.210.07:38:20.78#ibcon#read 4, iclass 33, count 0 2006.210.07:38:20.78#ibcon#about to read 5, iclass 33, count 0 2006.210.07:38:20.78#ibcon#read 5, iclass 33, count 0 2006.210.07:38:20.78#ibcon#about to read 6, iclass 33, count 0 2006.210.07:38:20.78#ibcon#read 6, iclass 33, count 0 2006.210.07:38:20.78#ibcon#end of sib2, iclass 33, count 0 2006.210.07:38:20.78#ibcon#*after write, iclass 33, count 0 2006.210.07:38:20.78#ibcon#*before return 0, iclass 33, count 0 2006.210.07:38:20.78#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:20.78#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:38:20.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:38:20.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:38:20.78$vc4f8/vblo=3,656.99 2006.210.07:38:20.78#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.07:38:20.78#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.07:38:20.78#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:20.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:20.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:20.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:20.78#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:38:20.78#ibcon#first serial, iclass 35, count 0 2006.210.07:38:20.78#ibcon#enter sib2, iclass 35, count 0 2006.210.07:38:20.78#ibcon#flushed, iclass 35, count 0 2006.210.07:38:20.78#ibcon#about to write, iclass 35, count 0 2006.210.07:38:20.78#ibcon#wrote, iclass 35, count 0 2006.210.07:38:20.78#ibcon#about to read 3, iclass 35, count 0 2006.210.07:38:20.80#ibcon#read 3, iclass 35, count 0 2006.210.07:38:20.80#ibcon#about to read 4, iclass 35, count 0 2006.210.07:38:20.80#ibcon#read 4, iclass 35, count 0 2006.210.07:38:20.80#ibcon#about to read 5, iclass 35, count 0 2006.210.07:38:20.80#ibcon#read 5, iclass 35, count 0 2006.210.07:38:20.80#ibcon#about to read 6, iclass 35, count 0 2006.210.07:38:20.80#ibcon#read 6, iclass 35, count 0 2006.210.07:38:20.80#ibcon#end of sib2, iclass 35, count 0 2006.210.07:38:20.80#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:38:20.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:38:20.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:38:20.80#ibcon#*before write, iclass 35, count 0 2006.210.07:38:20.80#ibcon#enter sib2, iclass 35, count 0 2006.210.07:38:20.80#ibcon#flushed, iclass 35, count 0 2006.210.07:38:20.80#ibcon#about to write, iclass 35, count 0 2006.210.07:38:20.80#ibcon#wrote, iclass 35, count 0 2006.210.07:38:20.80#ibcon#about to read 3, iclass 35, count 0 2006.210.07:38:20.84#ibcon#read 3, iclass 35, count 0 2006.210.07:38:20.84#ibcon#about to read 4, iclass 35, count 0 2006.210.07:38:20.84#ibcon#read 4, iclass 35, count 0 2006.210.07:38:20.84#ibcon#about to read 5, iclass 35, count 0 2006.210.07:38:20.84#ibcon#read 5, iclass 35, count 0 2006.210.07:38:20.84#ibcon#about to read 6, iclass 35, count 0 2006.210.07:38:20.84#ibcon#read 6, iclass 35, count 0 2006.210.07:38:20.84#ibcon#end of sib2, iclass 35, count 0 2006.210.07:38:20.84#ibcon#*after write, iclass 35, count 0 2006.210.07:38:20.84#ibcon#*before return 0, iclass 35, count 0 2006.210.07:38:20.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:20.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:38:20.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:38:20.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:38:20.84$vc4f8/vb=3,3 2006.210.07:38:20.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:38:20.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:38:20.84#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:20.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:20.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:20.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:20.90#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:38:20.90#ibcon#first serial, iclass 37, count 2 2006.210.07:38:20.90#ibcon#enter sib2, iclass 37, count 2 2006.210.07:38:20.90#ibcon#flushed, iclass 37, count 2 2006.210.07:38:20.90#ibcon#about to write, iclass 37, count 2 2006.210.07:38:20.90#ibcon#wrote, iclass 37, count 2 2006.210.07:38:20.90#ibcon#about to read 3, iclass 37, count 2 2006.210.07:38:20.92#ibcon#read 3, iclass 37, count 2 2006.210.07:38:20.92#ibcon#about to read 4, iclass 37, count 2 2006.210.07:38:20.92#ibcon#read 4, iclass 37, count 2 2006.210.07:38:20.92#ibcon#about to read 5, iclass 37, count 2 2006.210.07:38:20.92#ibcon#read 5, iclass 37, count 2 2006.210.07:38:20.92#ibcon#about to read 6, iclass 37, count 2 2006.210.07:38:20.92#ibcon#read 6, iclass 37, count 2 2006.210.07:38:20.92#ibcon#end of sib2, iclass 37, count 2 2006.210.07:38:20.92#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:38:20.92#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:38:20.92#ibcon#[27=AT03-03\r\n] 2006.210.07:38:20.92#ibcon#*before write, iclass 37, count 2 2006.210.07:38:20.92#ibcon#enter sib2, iclass 37, count 2 2006.210.07:38:20.92#ibcon#flushed, iclass 37, count 2 2006.210.07:38:20.92#ibcon#about to write, iclass 37, count 2 2006.210.07:38:20.92#ibcon#wrote, iclass 37, count 2 2006.210.07:38:20.92#ibcon#about to read 3, iclass 37, count 2 2006.210.07:38:20.95#ibcon#read 3, iclass 37, count 2 2006.210.07:38:20.95#ibcon#about to read 4, iclass 37, count 2 2006.210.07:38:20.95#ibcon#read 4, iclass 37, count 2 2006.210.07:38:20.95#ibcon#about to read 5, iclass 37, count 2 2006.210.07:38:20.95#ibcon#read 5, iclass 37, count 2 2006.210.07:38:20.95#ibcon#about to read 6, iclass 37, count 2 2006.210.07:38:20.95#ibcon#read 6, iclass 37, count 2 2006.210.07:38:20.95#ibcon#end of sib2, iclass 37, count 2 2006.210.07:38:20.95#ibcon#*after write, iclass 37, count 2 2006.210.07:38:20.95#ibcon#*before return 0, iclass 37, count 2 2006.210.07:38:20.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:20.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:38:20.95#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:38:20.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:20.95#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:21.07#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:21.07#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:21.07#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:38:21.07#ibcon#first serial, iclass 37, count 0 2006.210.07:38:21.07#ibcon#enter sib2, iclass 37, count 0 2006.210.07:38:21.07#ibcon#flushed, iclass 37, count 0 2006.210.07:38:21.07#ibcon#about to write, iclass 37, count 0 2006.210.07:38:21.07#ibcon#wrote, iclass 37, count 0 2006.210.07:38:21.07#ibcon#about to read 3, iclass 37, count 0 2006.210.07:38:21.09#ibcon#read 3, iclass 37, count 0 2006.210.07:38:21.09#ibcon#about to read 4, iclass 37, count 0 2006.210.07:38:21.09#ibcon#read 4, iclass 37, count 0 2006.210.07:38:21.09#ibcon#about to read 5, iclass 37, count 0 2006.210.07:38:21.09#ibcon#read 5, iclass 37, count 0 2006.210.07:38:21.09#ibcon#about to read 6, iclass 37, count 0 2006.210.07:38:21.09#ibcon#read 6, iclass 37, count 0 2006.210.07:38:21.09#ibcon#end of sib2, iclass 37, count 0 2006.210.07:38:21.09#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:38:21.09#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:38:21.09#ibcon#[27=USB\r\n] 2006.210.07:38:21.09#ibcon#*before write, iclass 37, count 0 2006.210.07:38:21.09#ibcon#enter sib2, iclass 37, count 0 2006.210.07:38:21.09#ibcon#flushed, iclass 37, count 0 2006.210.07:38:21.09#ibcon#about to write, iclass 37, count 0 2006.210.07:38:21.09#ibcon#wrote, iclass 37, count 0 2006.210.07:38:21.09#ibcon#about to read 3, iclass 37, count 0 2006.210.07:38:21.12#ibcon#read 3, iclass 37, count 0 2006.210.07:38:21.12#ibcon#about to read 4, iclass 37, count 0 2006.210.07:38:21.12#ibcon#read 4, iclass 37, count 0 2006.210.07:38:21.12#ibcon#about to read 5, iclass 37, count 0 2006.210.07:38:21.12#ibcon#read 5, iclass 37, count 0 2006.210.07:38:21.12#ibcon#about to read 6, iclass 37, count 0 2006.210.07:38:21.12#ibcon#read 6, iclass 37, count 0 2006.210.07:38:21.12#ibcon#end of sib2, iclass 37, count 0 2006.210.07:38:21.12#ibcon#*after write, iclass 37, count 0 2006.210.07:38:21.12#ibcon#*before return 0, iclass 37, count 0 2006.210.07:38:21.12#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:21.12#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:38:21.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:38:21.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:38:21.12$vc4f8/vblo=4,712.99 2006.210.07:38:21.12#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.07:38:21.12#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.07:38:21.12#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:21.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:21.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:21.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:21.12#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:38:21.12#ibcon#first serial, iclass 39, count 0 2006.210.07:38:21.12#ibcon#enter sib2, iclass 39, count 0 2006.210.07:38:21.12#ibcon#flushed, iclass 39, count 0 2006.210.07:38:21.12#ibcon#about to write, iclass 39, count 0 2006.210.07:38:21.12#ibcon#wrote, iclass 39, count 0 2006.210.07:38:21.12#ibcon#about to read 3, iclass 39, count 0 2006.210.07:38:21.14#ibcon#read 3, iclass 39, count 0 2006.210.07:38:21.14#ibcon#about to read 4, iclass 39, count 0 2006.210.07:38:21.14#ibcon#read 4, iclass 39, count 0 2006.210.07:38:21.14#ibcon#about to read 5, iclass 39, count 0 2006.210.07:38:21.14#ibcon#read 5, iclass 39, count 0 2006.210.07:38:21.14#ibcon#about to read 6, iclass 39, count 0 2006.210.07:38:21.14#ibcon#read 6, iclass 39, count 0 2006.210.07:38:21.14#ibcon#end of sib2, iclass 39, count 0 2006.210.07:38:21.14#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:38:21.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:38:21.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:38:21.14#ibcon#*before write, iclass 39, count 0 2006.210.07:38:21.14#ibcon#enter sib2, iclass 39, count 0 2006.210.07:38:21.14#ibcon#flushed, iclass 39, count 0 2006.210.07:38:21.14#ibcon#about to write, iclass 39, count 0 2006.210.07:38:21.14#ibcon#wrote, iclass 39, count 0 2006.210.07:38:21.14#ibcon#about to read 3, iclass 39, count 0 2006.210.07:38:21.18#ibcon#read 3, iclass 39, count 0 2006.210.07:38:21.18#ibcon#about to read 4, iclass 39, count 0 2006.210.07:38:21.18#ibcon#read 4, iclass 39, count 0 2006.210.07:38:21.18#ibcon#about to read 5, iclass 39, count 0 2006.210.07:38:21.18#ibcon#read 5, iclass 39, count 0 2006.210.07:38:21.18#ibcon#about to read 6, iclass 39, count 0 2006.210.07:38:21.18#ibcon#read 6, iclass 39, count 0 2006.210.07:38:21.18#ibcon#end of sib2, iclass 39, count 0 2006.210.07:38:21.18#ibcon#*after write, iclass 39, count 0 2006.210.07:38:21.18#ibcon#*before return 0, iclass 39, count 0 2006.210.07:38:21.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:21.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:38:21.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:38:21.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:38:21.18$vc4f8/vb=4,3 2006.210.07:38:21.18#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.07:38:21.18#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.07:38:21.18#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:21.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:21.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:21.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:21.24#ibcon#enter wrdev, iclass 3, count 2 2006.210.07:38:21.24#ibcon#first serial, iclass 3, count 2 2006.210.07:38:21.24#ibcon#enter sib2, iclass 3, count 2 2006.210.07:38:21.24#ibcon#flushed, iclass 3, count 2 2006.210.07:38:21.24#ibcon#about to write, iclass 3, count 2 2006.210.07:38:21.24#ibcon#wrote, iclass 3, count 2 2006.210.07:38:21.24#ibcon#about to read 3, iclass 3, count 2 2006.210.07:38:21.26#ibcon#read 3, iclass 3, count 2 2006.210.07:38:21.26#ibcon#about to read 4, iclass 3, count 2 2006.210.07:38:21.26#ibcon#read 4, iclass 3, count 2 2006.210.07:38:21.26#ibcon#about to read 5, iclass 3, count 2 2006.210.07:38:21.26#ibcon#read 5, iclass 3, count 2 2006.210.07:38:21.26#ibcon#about to read 6, iclass 3, count 2 2006.210.07:38:21.26#ibcon#read 6, iclass 3, count 2 2006.210.07:38:21.26#ibcon#end of sib2, iclass 3, count 2 2006.210.07:38:21.26#ibcon#*mode == 0, iclass 3, count 2 2006.210.07:38:21.26#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.07:38:21.26#ibcon#[27=AT04-03\r\n] 2006.210.07:38:21.26#ibcon#*before write, iclass 3, count 2 2006.210.07:38:21.26#ibcon#enter sib2, iclass 3, count 2 2006.210.07:38:21.26#ibcon#flushed, iclass 3, count 2 2006.210.07:38:21.26#ibcon#about to write, iclass 3, count 2 2006.210.07:38:21.26#ibcon#wrote, iclass 3, count 2 2006.210.07:38:21.26#ibcon#about to read 3, iclass 3, count 2 2006.210.07:38:21.29#ibcon#read 3, iclass 3, count 2 2006.210.07:38:21.29#ibcon#about to read 4, iclass 3, count 2 2006.210.07:38:21.29#ibcon#read 4, iclass 3, count 2 2006.210.07:38:21.29#ibcon#about to read 5, iclass 3, count 2 2006.210.07:38:21.29#ibcon#read 5, iclass 3, count 2 2006.210.07:38:21.29#ibcon#about to read 6, iclass 3, count 2 2006.210.07:38:21.29#ibcon#read 6, iclass 3, count 2 2006.210.07:38:21.29#ibcon#end of sib2, iclass 3, count 2 2006.210.07:38:21.29#ibcon#*after write, iclass 3, count 2 2006.210.07:38:21.29#ibcon#*before return 0, iclass 3, count 2 2006.210.07:38:21.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:21.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:38:21.29#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.07:38:21.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:21.29#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:21.41#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:21.41#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:21.41#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:38:21.41#ibcon#first serial, iclass 3, count 0 2006.210.07:38:21.41#ibcon#enter sib2, iclass 3, count 0 2006.210.07:38:21.41#ibcon#flushed, iclass 3, count 0 2006.210.07:38:21.41#ibcon#about to write, iclass 3, count 0 2006.210.07:38:21.41#ibcon#wrote, iclass 3, count 0 2006.210.07:38:21.41#ibcon#about to read 3, iclass 3, count 0 2006.210.07:38:21.43#ibcon#read 3, iclass 3, count 0 2006.210.07:38:21.43#ibcon#about to read 4, iclass 3, count 0 2006.210.07:38:21.43#ibcon#read 4, iclass 3, count 0 2006.210.07:38:21.43#ibcon#about to read 5, iclass 3, count 0 2006.210.07:38:21.43#ibcon#read 5, iclass 3, count 0 2006.210.07:38:21.43#ibcon#about to read 6, iclass 3, count 0 2006.210.07:38:21.43#ibcon#read 6, iclass 3, count 0 2006.210.07:38:21.43#ibcon#end of sib2, iclass 3, count 0 2006.210.07:38:21.43#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:38:21.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:38:21.43#ibcon#[27=USB\r\n] 2006.210.07:38:21.43#ibcon#*before write, iclass 3, count 0 2006.210.07:38:21.43#ibcon#enter sib2, iclass 3, count 0 2006.210.07:38:21.43#ibcon#flushed, iclass 3, count 0 2006.210.07:38:21.43#ibcon#about to write, iclass 3, count 0 2006.210.07:38:21.43#ibcon#wrote, iclass 3, count 0 2006.210.07:38:21.43#ibcon#about to read 3, iclass 3, count 0 2006.210.07:38:21.46#ibcon#read 3, iclass 3, count 0 2006.210.07:38:21.46#ibcon#about to read 4, iclass 3, count 0 2006.210.07:38:21.46#ibcon#read 4, iclass 3, count 0 2006.210.07:38:21.46#ibcon#about to read 5, iclass 3, count 0 2006.210.07:38:21.46#ibcon#read 5, iclass 3, count 0 2006.210.07:38:21.46#ibcon#about to read 6, iclass 3, count 0 2006.210.07:38:21.46#ibcon#read 6, iclass 3, count 0 2006.210.07:38:21.46#ibcon#end of sib2, iclass 3, count 0 2006.210.07:38:21.46#ibcon#*after write, iclass 3, count 0 2006.210.07:38:21.46#ibcon#*before return 0, iclass 3, count 0 2006.210.07:38:21.46#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:21.46#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:38:21.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:38:21.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:38:21.46$vc4f8/vblo=5,744.99 2006.210.07:38:21.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.07:38:21.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.07:38:21.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:21.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:21.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:21.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:21.46#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:38:21.46#ibcon#first serial, iclass 5, count 0 2006.210.07:38:21.46#ibcon#enter sib2, iclass 5, count 0 2006.210.07:38:21.46#ibcon#flushed, iclass 5, count 0 2006.210.07:38:21.46#ibcon#about to write, iclass 5, count 0 2006.210.07:38:21.46#ibcon#wrote, iclass 5, count 0 2006.210.07:38:21.46#ibcon#about to read 3, iclass 5, count 0 2006.210.07:38:21.48#ibcon#read 3, iclass 5, count 0 2006.210.07:38:21.48#ibcon#about to read 4, iclass 5, count 0 2006.210.07:38:21.48#ibcon#read 4, iclass 5, count 0 2006.210.07:38:21.48#ibcon#about to read 5, iclass 5, count 0 2006.210.07:38:21.48#ibcon#read 5, iclass 5, count 0 2006.210.07:38:21.48#ibcon#about to read 6, iclass 5, count 0 2006.210.07:38:21.48#ibcon#read 6, iclass 5, count 0 2006.210.07:38:21.48#ibcon#end of sib2, iclass 5, count 0 2006.210.07:38:21.48#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:38:21.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:38:21.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:38:21.48#ibcon#*before write, iclass 5, count 0 2006.210.07:38:21.48#ibcon#enter sib2, iclass 5, count 0 2006.210.07:38:21.48#ibcon#flushed, iclass 5, count 0 2006.210.07:38:21.48#ibcon#about to write, iclass 5, count 0 2006.210.07:38:21.48#ibcon#wrote, iclass 5, count 0 2006.210.07:38:21.48#ibcon#about to read 3, iclass 5, count 0 2006.210.07:38:21.52#ibcon#read 3, iclass 5, count 0 2006.210.07:38:21.52#ibcon#about to read 4, iclass 5, count 0 2006.210.07:38:21.52#ibcon#read 4, iclass 5, count 0 2006.210.07:38:21.52#ibcon#about to read 5, iclass 5, count 0 2006.210.07:38:21.52#ibcon#read 5, iclass 5, count 0 2006.210.07:38:21.52#ibcon#about to read 6, iclass 5, count 0 2006.210.07:38:21.52#ibcon#read 6, iclass 5, count 0 2006.210.07:38:21.52#ibcon#end of sib2, iclass 5, count 0 2006.210.07:38:21.52#ibcon#*after write, iclass 5, count 0 2006.210.07:38:21.52#ibcon#*before return 0, iclass 5, count 0 2006.210.07:38:21.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:21.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:38:21.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:38:21.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:38:21.52$vc4f8/vb=5,3 2006.210.07:38:21.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.07:38:21.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.07:38:21.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:21.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:21.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:21.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:21.58#ibcon#enter wrdev, iclass 7, count 2 2006.210.07:38:21.58#ibcon#first serial, iclass 7, count 2 2006.210.07:38:21.58#ibcon#enter sib2, iclass 7, count 2 2006.210.07:38:21.58#ibcon#flushed, iclass 7, count 2 2006.210.07:38:21.58#ibcon#about to write, iclass 7, count 2 2006.210.07:38:21.58#ibcon#wrote, iclass 7, count 2 2006.210.07:38:21.58#ibcon#about to read 3, iclass 7, count 2 2006.210.07:38:21.60#ibcon#read 3, iclass 7, count 2 2006.210.07:38:21.60#ibcon#about to read 4, iclass 7, count 2 2006.210.07:38:21.60#ibcon#read 4, iclass 7, count 2 2006.210.07:38:21.60#ibcon#about to read 5, iclass 7, count 2 2006.210.07:38:21.60#ibcon#read 5, iclass 7, count 2 2006.210.07:38:21.60#ibcon#about to read 6, iclass 7, count 2 2006.210.07:38:21.60#ibcon#read 6, iclass 7, count 2 2006.210.07:38:21.60#ibcon#end of sib2, iclass 7, count 2 2006.210.07:38:21.60#ibcon#*mode == 0, iclass 7, count 2 2006.210.07:38:21.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.07:38:21.60#ibcon#[27=AT05-03\r\n] 2006.210.07:38:21.60#ibcon#*before write, iclass 7, count 2 2006.210.07:38:21.60#ibcon#enter sib2, iclass 7, count 2 2006.210.07:38:21.60#ibcon#flushed, iclass 7, count 2 2006.210.07:38:21.60#ibcon#about to write, iclass 7, count 2 2006.210.07:38:21.60#ibcon#wrote, iclass 7, count 2 2006.210.07:38:21.60#ibcon#about to read 3, iclass 7, count 2 2006.210.07:38:21.63#ibcon#read 3, iclass 7, count 2 2006.210.07:38:21.63#ibcon#about to read 4, iclass 7, count 2 2006.210.07:38:21.63#ibcon#read 4, iclass 7, count 2 2006.210.07:38:21.63#ibcon#about to read 5, iclass 7, count 2 2006.210.07:38:21.63#ibcon#read 5, iclass 7, count 2 2006.210.07:38:21.63#ibcon#about to read 6, iclass 7, count 2 2006.210.07:38:21.63#ibcon#read 6, iclass 7, count 2 2006.210.07:38:21.63#ibcon#end of sib2, iclass 7, count 2 2006.210.07:38:21.63#ibcon#*after write, iclass 7, count 2 2006.210.07:38:21.63#ibcon#*before return 0, iclass 7, count 2 2006.210.07:38:21.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:21.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:38:21.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.07:38:21.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:21.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:21.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:21.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:21.75#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:38:21.75#ibcon#first serial, iclass 7, count 0 2006.210.07:38:21.75#ibcon#enter sib2, iclass 7, count 0 2006.210.07:38:21.75#ibcon#flushed, iclass 7, count 0 2006.210.07:38:21.75#ibcon#about to write, iclass 7, count 0 2006.210.07:38:21.75#ibcon#wrote, iclass 7, count 0 2006.210.07:38:21.75#ibcon#about to read 3, iclass 7, count 0 2006.210.07:38:21.77#ibcon#read 3, iclass 7, count 0 2006.210.07:38:21.77#ibcon#about to read 4, iclass 7, count 0 2006.210.07:38:21.77#ibcon#read 4, iclass 7, count 0 2006.210.07:38:21.77#ibcon#about to read 5, iclass 7, count 0 2006.210.07:38:21.77#ibcon#read 5, iclass 7, count 0 2006.210.07:38:21.77#ibcon#about to read 6, iclass 7, count 0 2006.210.07:38:21.77#ibcon#read 6, iclass 7, count 0 2006.210.07:38:21.77#ibcon#end of sib2, iclass 7, count 0 2006.210.07:38:21.77#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:38:21.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:38:21.77#ibcon#[27=USB\r\n] 2006.210.07:38:21.77#ibcon#*before write, iclass 7, count 0 2006.210.07:38:21.77#ibcon#enter sib2, iclass 7, count 0 2006.210.07:38:21.77#ibcon#flushed, iclass 7, count 0 2006.210.07:38:21.77#ibcon#about to write, iclass 7, count 0 2006.210.07:38:21.77#ibcon#wrote, iclass 7, count 0 2006.210.07:38:21.77#ibcon#about to read 3, iclass 7, count 0 2006.210.07:38:21.80#ibcon#read 3, iclass 7, count 0 2006.210.07:38:21.80#ibcon#about to read 4, iclass 7, count 0 2006.210.07:38:21.80#ibcon#read 4, iclass 7, count 0 2006.210.07:38:21.80#ibcon#about to read 5, iclass 7, count 0 2006.210.07:38:21.80#ibcon#read 5, iclass 7, count 0 2006.210.07:38:21.80#ibcon#about to read 6, iclass 7, count 0 2006.210.07:38:21.80#ibcon#read 6, iclass 7, count 0 2006.210.07:38:21.80#ibcon#end of sib2, iclass 7, count 0 2006.210.07:38:21.80#ibcon#*after write, iclass 7, count 0 2006.210.07:38:21.80#ibcon#*before return 0, iclass 7, count 0 2006.210.07:38:21.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:21.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:38:21.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:38:21.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:38:21.80$vc4f8/vblo=6,752.99 2006.210.07:38:21.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.07:38:21.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.07:38:21.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:38:21.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:21.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:21.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:21.80#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:38:21.80#ibcon#first serial, iclass 11, count 0 2006.210.07:38:21.80#ibcon#enter sib2, iclass 11, count 0 2006.210.07:38:21.80#ibcon#flushed, iclass 11, count 0 2006.210.07:38:21.80#ibcon#about to write, iclass 11, count 0 2006.210.07:38:21.80#ibcon#wrote, iclass 11, count 0 2006.210.07:38:21.80#ibcon#about to read 3, iclass 11, count 0 2006.210.07:38:21.82#ibcon#read 3, iclass 11, count 0 2006.210.07:38:21.82#ibcon#about to read 4, iclass 11, count 0 2006.210.07:38:21.82#ibcon#read 4, iclass 11, count 0 2006.210.07:38:21.82#ibcon#about to read 5, iclass 11, count 0 2006.210.07:38:21.82#ibcon#read 5, iclass 11, count 0 2006.210.07:38:21.82#ibcon#about to read 6, iclass 11, count 0 2006.210.07:38:21.82#ibcon#read 6, iclass 11, count 0 2006.210.07:38:21.82#ibcon#end of sib2, iclass 11, count 0 2006.210.07:38:21.82#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:38:21.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:38:21.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:38:21.82#ibcon#*before write, iclass 11, count 0 2006.210.07:38:21.82#ibcon#enter sib2, iclass 11, count 0 2006.210.07:38:21.82#ibcon#flushed, iclass 11, count 0 2006.210.07:38:21.82#ibcon#about to write, iclass 11, count 0 2006.210.07:38:21.82#ibcon#wrote, iclass 11, count 0 2006.210.07:38:21.82#ibcon#about to read 3, iclass 11, count 0 2006.210.07:38:21.86#ibcon#read 3, iclass 11, count 0 2006.210.07:38:21.86#ibcon#about to read 4, iclass 11, count 0 2006.210.07:38:21.86#ibcon#read 4, iclass 11, count 0 2006.210.07:38:21.86#ibcon#about to read 5, iclass 11, count 0 2006.210.07:38:21.86#ibcon#read 5, iclass 11, count 0 2006.210.07:38:21.86#ibcon#about to read 6, iclass 11, count 0 2006.210.07:38:21.86#ibcon#read 6, iclass 11, count 0 2006.210.07:38:21.86#ibcon#end of sib2, iclass 11, count 0 2006.210.07:38:21.86#ibcon#*after write, iclass 11, count 0 2006.210.07:38:21.86#ibcon#*before return 0, iclass 11, count 0 2006.210.07:38:21.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:21.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:38:21.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:38:21.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:38:21.86$vc4f8/vb=6,3 2006.210.07:38:21.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.07:38:21.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.07:38:21.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:38:21.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:21.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:21.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:21.92#ibcon#enter wrdev, iclass 13, count 2 2006.210.07:38:21.92#ibcon#first serial, iclass 13, count 2 2006.210.07:38:21.92#ibcon#enter sib2, iclass 13, count 2 2006.210.07:38:21.92#ibcon#flushed, iclass 13, count 2 2006.210.07:38:21.92#ibcon#about to write, iclass 13, count 2 2006.210.07:38:21.92#ibcon#wrote, iclass 13, count 2 2006.210.07:38:21.92#ibcon#about to read 3, iclass 13, count 2 2006.210.07:38:21.94#ibcon#read 3, iclass 13, count 2 2006.210.07:38:21.94#ibcon#about to read 4, iclass 13, count 2 2006.210.07:38:21.94#ibcon#read 4, iclass 13, count 2 2006.210.07:38:21.94#ibcon#about to read 5, iclass 13, count 2 2006.210.07:38:21.94#ibcon#read 5, iclass 13, count 2 2006.210.07:38:21.94#ibcon#about to read 6, iclass 13, count 2 2006.210.07:38:21.94#ibcon#read 6, iclass 13, count 2 2006.210.07:38:21.94#ibcon#end of sib2, iclass 13, count 2 2006.210.07:38:21.94#ibcon#*mode == 0, iclass 13, count 2 2006.210.07:38:21.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.07:38:21.94#ibcon#[27=AT06-03\r\n] 2006.210.07:38:21.94#ibcon#*before write, iclass 13, count 2 2006.210.07:38:21.94#ibcon#enter sib2, iclass 13, count 2 2006.210.07:38:21.94#ibcon#flushed, iclass 13, count 2 2006.210.07:38:21.94#ibcon#about to write, iclass 13, count 2 2006.210.07:38:21.94#ibcon#wrote, iclass 13, count 2 2006.210.07:38:21.94#ibcon#about to read 3, iclass 13, count 2 2006.210.07:38:21.97#ibcon#read 3, iclass 13, count 2 2006.210.07:38:21.97#ibcon#about to read 4, iclass 13, count 2 2006.210.07:38:21.97#ibcon#read 4, iclass 13, count 2 2006.210.07:38:21.97#ibcon#about to read 5, iclass 13, count 2 2006.210.07:38:21.97#ibcon#read 5, iclass 13, count 2 2006.210.07:38:21.97#ibcon#about to read 6, iclass 13, count 2 2006.210.07:38:21.97#ibcon#read 6, iclass 13, count 2 2006.210.07:38:21.97#ibcon#end of sib2, iclass 13, count 2 2006.210.07:38:21.97#ibcon#*after write, iclass 13, count 2 2006.210.07:38:21.97#ibcon#*before return 0, iclass 13, count 2 2006.210.07:38:21.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:21.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:38:21.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.07:38:21.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:38:21.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:22.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:22.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:22.09#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:38:22.09#ibcon#first serial, iclass 13, count 0 2006.210.07:38:22.09#ibcon#enter sib2, iclass 13, count 0 2006.210.07:38:22.09#ibcon#flushed, iclass 13, count 0 2006.210.07:38:22.09#ibcon#about to write, iclass 13, count 0 2006.210.07:38:22.09#ibcon#wrote, iclass 13, count 0 2006.210.07:38:22.09#ibcon#about to read 3, iclass 13, count 0 2006.210.07:38:22.11#ibcon#read 3, iclass 13, count 0 2006.210.07:38:22.11#ibcon#about to read 4, iclass 13, count 0 2006.210.07:38:22.11#ibcon#read 4, iclass 13, count 0 2006.210.07:38:22.11#ibcon#about to read 5, iclass 13, count 0 2006.210.07:38:22.11#ibcon#read 5, iclass 13, count 0 2006.210.07:38:22.11#ibcon#about to read 6, iclass 13, count 0 2006.210.07:38:22.11#ibcon#read 6, iclass 13, count 0 2006.210.07:38:22.11#ibcon#end of sib2, iclass 13, count 0 2006.210.07:38:22.11#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:38:22.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:38:22.11#ibcon#[27=USB\r\n] 2006.210.07:38:22.11#ibcon#*before write, iclass 13, count 0 2006.210.07:38:22.11#ibcon#enter sib2, iclass 13, count 0 2006.210.07:38:22.11#ibcon#flushed, iclass 13, count 0 2006.210.07:38:22.11#ibcon#about to write, iclass 13, count 0 2006.210.07:38:22.11#ibcon#wrote, iclass 13, count 0 2006.210.07:38:22.11#ibcon#about to read 3, iclass 13, count 0 2006.210.07:38:22.14#ibcon#read 3, iclass 13, count 0 2006.210.07:38:22.14#ibcon#about to read 4, iclass 13, count 0 2006.210.07:38:22.14#ibcon#read 4, iclass 13, count 0 2006.210.07:38:22.14#ibcon#about to read 5, iclass 13, count 0 2006.210.07:38:22.14#ibcon#read 5, iclass 13, count 0 2006.210.07:38:22.14#ibcon#about to read 6, iclass 13, count 0 2006.210.07:38:22.14#ibcon#read 6, iclass 13, count 0 2006.210.07:38:22.14#ibcon#end of sib2, iclass 13, count 0 2006.210.07:38:22.14#ibcon#*after write, iclass 13, count 0 2006.210.07:38:22.14#ibcon#*before return 0, iclass 13, count 0 2006.210.07:38:22.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:22.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:38:22.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:38:22.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:38:22.14$vc4f8/vabw=wide 2006.210.07:38:22.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.07:38:22.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.07:38:22.14#ibcon#ireg 8 cls_cnt 0 2006.210.07:38:22.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:22.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:22.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:22.14#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:38:22.14#ibcon#first serial, iclass 15, count 0 2006.210.07:38:22.14#ibcon#enter sib2, iclass 15, count 0 2006.210.07:38:22.14#ibcon#flushed, iclass 15, count 0 2006.210.07:38:22.14#ibcon#about to write, iclass 15, count 0 2006.210.07:38:22.14#ibcon#wrote, iclass 15, count 0 2006.210.07:38:22.14#ibcon#about to read 3, iclass 15, count 0 2006.210.07:38:22.16#ibcon#read 3, iclass 15, count 0 2006.210.07:38:22.16#ibcon#about to read 4, iclass 15, count 0 2006.210.07:38:22.16#ibcon#read 4, iclass 15, count 0 2006.210.07:38:22.16#ibcon#about to read 5, iclass 15, count 0 2006.210.07:38:22.16#ibcon#read 5, iclass 15, count 0 2006.210.07:38:22.16#ibcon#about to read 6, iclass 15, count 0 2006.210.07:38:22.16#ibcon#read 6, iclass 15, count 0 2006.210.07:38:22.16#ibcon#end of sib2, iclass 15, count 0 2006.210.07:38:22.16#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:38:22.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:38:22.16#ibcon#[25=BW32\r\n] 2006.210.07:38:22.16#ibcon#*before write, iclass 15, count 0 2006.210.07:38:22.16#ibcon#enter sib2, iclass 15, count 0 2006.210.07:38:22.16#ibcon#flushed, iclass 15, count 0 2006.210.07:38:22.16#ibcon#about to write, iclass 15, count 0 2006.210.07:38:22.16#ibcon#wrote, iclass 15, count 0 2006.210.07:38:22.16#ibcon#about to read 3, iclass 15, count 0 2006.210.07:38:22.19#ibcon#read 3, iclass 15, count 0 2006.210.07:38:22.19#ibcon#about to read 4, iclass 15, count 0 2006.210.07:38:22.19#ibcon#read 4, iclass 15, count 0 2006.210.07:38:22.19#ibcon#about to read 5, iclass 15, count 0 2006.210.07:38:22.19#ibcon#read 5, iclass 15, count 0 2006.210.07:38:22.19#ibcon#about to read 6, iclass 15, count 0 2006.210.07:38:22.19#ibcon#read 6, iclass 15, count 0 2006.210.07:38:22.19#ibcon#end of sib2, iclass 15, count 0 2006.210.07:38:22.19#ibcon#*after write, iclass 15, count 0 2006.210.07:38:22.19#ibcon#*before return 0, iclass 15, count 0 2006.210.07:38:22.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:22.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:38:22.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:38:22.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:38:22.19$vc4f8/vbbw=wide 2006.210.07:38:22.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:38:22.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:38:22.19#ibcon#ireg 8 cls_cnt 0 2006.210.07:38:22.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:38:22.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:38:22.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:38:22.26#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:38:22.26#ibcon#first serial, iclass 17, count 0 2006.210.07:38:22.26#ibcon#enter sib2, iclass 17, count 0 2006.210.07:38:22.26#ibcon#flushed, iclass 17, count 0 2006.210.07:38:22.26#ibcon#about to write, iclass 17, count 0 2006.210.07:38:22.26#ibcon#wrote, iclass 17, count 0 2006.210.07:38:22.26#ibcon#about to read 3, iclass 17, count 0 2006.210.07:38:22.28#ibcon#read 3, iclass 17, count 0 2006.210.07:38:22.28#ibcon#about to read 4, iclass 17, count 0 2006.210.07:38:22.28#ibcon#read 4, iclass 17, count 0 2006.210.07:38:22.28#ibcon#about to read 5, iclass 17, count 0 2006.210.07:38:22.28#ibcon#read 5, iclass 17, count 0 2006.210.07:38:22.28#ibcon#about to read 6, iclass 17, count 0 2006.210.07:38:22.28#ibcon#read 6, iclass 17, count 0 2006.210.07:38:22.28#ibcon#end of sib2, iclass 17, count 0 2006.210.07:38:22.28#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:38:22.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:38:22.28#ibcon#[27=BW32\r\n] 2006.210.07:38:22.28#ibcon#*before write, iclass 17, count 0 2006.210.07:38:22.28#ibcon#enter sib2, iclass 17, count 0 2006.210.07:38:22.28#ibcon#flushed, iclass 17, count 0 2006.210.07:38:22.28#ibcon#about to write, iclass 17, count 0 2006.210.07:38:22.28#ibcon#wrote, iclass 17, count 0 2006.210.07:38:22.28#ibcon#about to read 3, iclass 17, count 0 2006.210.07:38:22.31#ibcon#read 3, iclass 17, count 0 2006.210.07:38:22.31#ibcon#about to read 4, iclass 17, count 0 2006.210.07:38:22.31#ibcon#read 4, iclass 17, count 0 2006.210.07:38:22.31#ibcon#about to read 5, iclass 17, count 0 2006.210.07:38:22.31#ibcon#read 5, iclass 17, count 0 2006.210.07:38:22.31#ibcon#about to read 6, iclass 17, count 0 2006.210.07:38:22.31#ibcon#read 6, iclass 17, count 0 2006.210.07:38:22.31#ibcon#end of sib2, iclass 17, count 0 2006.210.07:38:22.31#ibcon#*after write, iclass 17, count 0 2006.210.07:38:22.31#ibcon#*before return 0, iclass 17, count 0 2006.210.07:38:22.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:38:22.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:38:22.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:38:22.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:38:22.31$4f8m12a/ifd4f 2006.210.07:38:22.31$ifd4f/lo= 2006.210.07:38:22.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:38:22.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:38:22.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:38:22.31$ifd4f/patch= 2006.210.07:38:22.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:38:22.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:38:22.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:38:22.31$4f8m12a/"form=m,16.000,1:2 2006.210.07:38:22.31$4f8m12a/"tpicd 2006.210.07:38:22.32$4f8m12a/echo=off 2006.210.07:38:22.32$4f8m12a/xlog=off 2006.210.07:38:22.32:!2006.210.07:38:50 2006.210.07:38:33.14#trakl#Source acquired 2006.210.07:38:34.14#flagr#flagr/antenna,acquired 2006.210.07:38:50.01:preob 2006.210.07:38:51.14/onsource/TRACKING 2006.210.07:38:51.14:!2006.210.07:39:00 2006.210.07:39:00.00:data_valid=on 2006.210.07:39:00.00:midob 2006.210.07:39:00.14/onsource/TRACKING 2006.210.07:39:00.14/wx/30.60,1006.2,76 2006.210.07:39:00.26/cable/+6.3949E-03 2006.210.07:39:01.35/va/01,08,usb,yes,28,30 2006.210.07:39:01.35/va/02,07,usb,yes,29,30 2006.210.07:39:01.35/va/03,06,usb,yes,30,30 2006.210.07:39:01.35/va/04,07,usb,yes,29,32 2006.210.07:39:01.35/va/05,07,usb,yes,30,32 2006.210.07:39:01.35/va/06,06,usb,yes,29,29 2006.210.07:39:01.35/va/07,06,usb,yes,30,29 2006.210.07:39:01.35/va/08,07,usb,yes,28,28 2006.210.07:39:01.58/valo/01,532.99,yes,locked 2006.210.07:39:01.58/valo/02,572.99,yes,locked 2006.210.07:39:01.58/valo/03,672.99,yes,locked 2006.210.07:39:01.58/valo/04,832.99,yes,locked 2006.210.07:39:01.58/valo/05,652.99,yes,locked 2006.210.07:39:01.58/valo/06,772.99,yes,locked 2006.210.07:39:01.58/valo/07,832.99,yes,locked 2006.210.07:39:01.58/valo/08,852.99,yes,locked 2006.210.07:39:02.67/vb/01,04,usb,yes,28,27 2006.210.07:39:02.67/vb/02,04,usb,yes,30,31 2006.210.07:39:02.67/vb/03,03,usb,yes,33,37 2006.210.07:39:02.67/vb/04,03,usb,yes,34,34 2006.210.07:39:02.67/vb/05,03,usb,yes,32,37 2006.210.07:39:02.67/vb/06,03,usb,yes,33,36 2006.210.07:39:02.67/vb/07,04,usb,yes,29,29 2006.210.07:39:02.67/vb/08,03,usb,yes,33,37 2006.210.07:39:02.91/vblo/01,632.99,yes,locked 2006.210.07:39:02.91/vblo/02,640.99,yes,locked 2006.210.07:39:02.91/vblo/03,656.99,yes,locked 2006.210.07:39:02.91/vblo/04,712.99,yes,locked 2006.210.07:39:02.91/vblo/05,744.99,yes,locked 2006.210.07:39:02.91/vblo/06,752.99,yes,locked 2006.210.07:39:02.91/vblo/07,734.99,yes,locked 2006.210.07:39:02.91/vblo/08,744.99,yes,locked 2006.210.07:39:03.06/vabw/8 2006.210.07:39:03.21/vbbw/8 2006.210.07:39:03.30/xfe/off,on,12.5 2006.210.07:39:03.69/ifatt/23,28,28,28 2006.210.07:39:04.07/fmout-gps/S +4.39E-07 2006.210.07:39:04.12:!2006.210.07:40:00 2006.210.07:40:00.01:data_valid=off 2006.210.07:40:00.01:postob 2006.210.07:40:00.18/cable/+6.3941E-03 2006.210.07:40:00.18/wx/30.60,1006.2,75 2006.210.07:40:01.07/fmout-gps/S +4.40E-07 2006.210.07:40:01.07:scan_name=210-0740,k06210,60 2006.210.07:40:01.07:source=1418+546,141946.60,542314.8,2000.0,cw 2006.210.07:40:02.14#flagr#flagr/antenna,new-source 2006.210.07:40:02.14:checkk5 2006.210.07:40:02.49/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:40:02.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:40:03.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:40:03.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:40:03.84/chk_obsdata//k5ts1/T2100739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:40:04.18/chk_obsdata//k5ts2/T2100739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:40:04.51/chk_obsdata//k5ts3/T2100739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:40:04.84/chk_obsdata//k5ts4/T2100739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:40:05.51/k5log//k5ts1_log_newline 2006.210.07:40:06.17/k5log//k5ts2_log_newline 2006.210.07:40:06.83/k5log//k5ts3_log_newline 2006.210.07:40:07.48/k5log//k5ts4_log_newline 2006.210.07:40:07.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:40:07.50:4f8m12a=1 2006.210.07:40:07.50$4f8m12a/echo=on 2006.210.07:40:07.50$4f8m12a/pcalon 2006.210.07:40:07.50$pcalon/"no phase cal control is implemented here 2006.210.07:40:07.50$4f8m12a/"tpicd=stop 2006.210.07:40:07.50$4f8m12a/vc4f8 2006.210.07:40:07.50$vc4f8/valo=1,532.99 2006.210.07:40:07.51#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:40:07.51#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:40:07.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:07.51#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:07.51#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:07.51#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:07.51#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:40:07.51#ibcon#first serial, iclass 28, count 0 2006.210.07:40:07.51#ibcon#enter sib2, iclass 28, count 0 2006.210.07:40:07.51#ibcon#flushed, iclass 28, count 0 2006.210.07:40:07.51#ibcon#about to write, iclass 28, count 0 2006.210.07:40:07.51#ibcon#wrote, iclass 28, count 0 2006.210.07:40:07.51#ibcon#about to read 3, iclass 28, count 0 2006.210.07:40:07.52#ibcon#read 3, iclass 28, count 0 2006.210.07:40:07.52#ibcon#about to read 4, iclass 28, count 0 2006.210.07:40:07.52#ibcon#read 4, iclass 28, count 0 2006.210.07:40:07.52#ibcon#about to read 5, iclass 28, count 0 2006.210.07:40:07.52#ibcon#read 5, iclass 28, count 0 2006.210.07:40:07.52#ibcon#about to read 6, iclass 28, count 0 2006.210.07:40:07.52#ibcon#read 6, iclass 28, count 0 2006.210.07:40:07.52#ibcon#end of sib2, iclass 28, count 0 2006.210.07:40:07.52#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:40:07.52#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:40:07.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:40:07.52#ibcon#*before write, iclass 28, count 0 2006.210.07:40:07.52#ibcon#enter sib2, iclass 28, count 0 2006.210.07:40:07.52#ibcon#flushed, iclass 28, count 0 2006.210.07:40:07.52#ibcon#about to write, iclass 28, count 0 2006.210.07:40:07.52#ibcon#wrote, iclass 28, count 0 2006.210.07:40:07.52#ibcon#about to read 3, iclass 28, count 0 2006.210.07:40:07.57#ibcon#read 3, iclass 28, count 0 2006.210.07:40:07.57#ibcon#about to read 4, iclass 28, count 0 2006.210.07:40:07.57#ibcon#read 4, iclass 28, count 0 2006.210.07:40:07.57#ibcon#about to read 5, iclass 28, count 0 2006.210.07:40:07.57#ibcon#read 5, iclass 28, count 0 2006.210.07:40:07.57#ibcon#about to read 6, iclass 28, count 0 2006.210.07:40:07.57#ibcon#read 6, iclass 28, count 0 2006.210.07:40:07.57#ibcon#end of sib2, iclass 28, count 0 2006.210.07:40:07.57#ibcon#*after write, iclass 28, count 0 2006.210.07:40:07.57#ibcon#*before return 0, iclass 28, count 0 2006.210.07:40:07.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:07.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:07.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:40:07.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:40:07.57$vc4f8/va=1,8 2006.210.07:40:07.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:40:07.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:40:07.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:07.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:07.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:07.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:07.57#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:40:07.57#ibcon#first serial, iclass 30, count 2 2006.210.07:40:07.57#ibcon#enter sib2, iclass 30, count 2 2006.210.07:40:07.57#ibcon#flushed, iclass 30, count 2 2006.210.07:40:07.57#ibcon#about to write, iclass 30, count 2 2006.210.07:40:07.57#ibcon#wrote, iclass 30, count 2 2006.210.07:40:07.57#ibcon#about to read 3, iclass 30, count 2 2006.210.07:40:07.59#ibcon#read 3, iclass 30, count 2 2006.210.07:40:07.59#ibcon#about to read 4, iclass 30, count 2 2006.210.07:40:07.59#ibcon#read 4, iclass 30, count 2 2006.210.07:40:07.59#ibcon#about to read 5, iclass 30, count 2 2006.210.07:40:07.59#ibcon#read 5, iclass 30, count 2 2006.210.07:40:07.59#ibcon#about to read 6, iclass 30, count 2 2006.210.07:40:07.59#ibcon#read 6, iclass 30, count 2 2006.210.07:40:07.59#ibcon#end of sib2, iclass 30, count 2 2006.210.07:40:07.59#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:40:07.59#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:40:07.59#ibcon#[25=AT01-08\r\n] 2006.210.07:40:07.59#ibcon#*before write, iclass 30, count 2 2006.210.07:40:07.59#ibcon#enter sib2, iclass 30, count 2 2006.210.07:40:07.59#ibcon#flushed, iclass 30, count 2 2006.210.07:40:07.59#ibcon#about to write, iclass 30, count 2 2006.210.07:40:07.59#ibcon#wrote, iclass 30, count 2 2006.210.07:40:07.59#ibcon#about to read 3, iclass 30, count 2 2006.210.07:40:07.62#ibcon#read 3, iclass 30, count 2 2006.210.07:40:07.62#ibcon#about to read 4, iclass 30, count 2 2006.210.07:40:07.62#ibcon#read 4, iclass 30, count 2 2006.210.07:40:07.62#ibcon#about to read 5, iclass 30, count 2 2006.210.07:40:07.62#ibcon#read 5, iclass 30, count 2 2006.210.07:40:07.62#ibcon#about to read 6, iclass 30, count 2 2006.210.07:40:07.62#ibcon#read 6, iclass 30, count 2 2006.210.07:40:07.62#ibcon#end of sib2, iclass 30, count 2 2006.210.07:40:07.62#ibcon#*after write, iclass 30, count 2 2006.210.07:40:07.62#ibcon#*before return 0, iclass 30, count 2 2006.210.07:40:07.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:07.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:07.62#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:40:07.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:07.62#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:07.74#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:07.74#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:07.74#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:40:07.74#ibcon#first serial, iclass 30, count 0 2006.210.07:40:07.74#ibcon#enter sib2, iclass 30, count 0 2006.210.07:40:07.74#ibcon#flushed, iclass 30, count 0 2006.210.07:40:07.74#ibcon#about to write, iclass 30, count 0 2006.210.07:40:07.74#ibcon#wrote, iclass 30, count 0 2006.210.07:40:07.74#ibcon#about to read 3, iclass 30, count 0 2006.210.07:40:07.76#ibcon#read 3, iclass 30, count 0 2006.210.07:40:07.76#ibcon#about to read 4, iclass 30, count 0 2006.210.07:40:07.76#ibcon#read 4, iclass 30, count 0 2006.210.07:40:07.76#ibcon#about to read 5, iclass 30, count 0 2006.210.07:40:07.76#ibcon#read 5, iclass 30, count 0 2006.210.07:40:07.76#ibcon#about to read 6, iclass 30, count 0 2006.210.07:40:07.76#ibcon#read 6, iclass 30, count 0 2006.210.07:40:07.76#ibcon#end of sib2, iclass 30, count 0 2006.210.07:40:07.76#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:40:07.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:40:07.76#ibcon#[25=USB\r\n] 2006.210.07:40:07.76#ibcon#*before write, iclass 30, count 0 2006.210.07:40:07.76#ibcon#enter sib2, iclass 30, count 0 2006.210.07:40:07.76#ibcon#flushed, iclass 30, count 0 2006.210.07:40:07.76#ibcon#about to write, iclass 30, count 0 2006.210.07:40:07.76#ibcon#wrote, iclass 30, count 0 2006.210.07:40:07.76#ibcon#about to read 3, iclass 30, count 0 2006.210.07:40:07.79#ibcon#read 3, iclass 30, count 0 2006.210.07:40:07.79#ibcon#about to read 4, iclass 30, count 0 2006.210.07:40:07.79#ibcon#read 4, iclass 30, count 0 2006.210.07:40:07.79#ibcon#about to read 5, iclass 30, count 0 2006.210.07:40:07.79#ibcon#read 5, iclass 30, count 0 2006.210.07:40:07.79#ibcon#about to read 6, iclass 30, count 0 2006.210.07:40:07.79#ibcon#read 6, iclass 30, count 0 2006.210.07:40:07.79#ibcon#end of sib2, iclass 30, count 0 2006.210.07:40:07.79#ibcon#*after write, iclass 30, count 0 2006.210.07:40:07.79#ibcon#*before return 0, iclass 30, count 0 2006.210.07:40:07.79#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:07.79#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:07.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:40:07.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:40:07.79$vc4f8/valo=2,572.99 2006.210.07:40:07.79#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:40:07.79#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:40:07.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:07.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:07.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:07.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:07.79#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:40:07.79#ibcon#first serial, iclass 32, count 0 2006.210.07:40:07.79#ibcon#enter sib2, iclass 32, count 0 2006.210.07:40:07.79#ibcon#flushed, iclass 32, count 0 2006.210.07:40:07.79#ibcon#about to write, iclass 32, count 0 2006.210.07:40:07.79#ibcon#wrote, iclass 32, count 0 2006.210.07:40:07.79#ibcon#about to read 3, iclass 32, count 0 2006.210.07:40:07.81#ibcon#read 3, iclass 32, count 0 2006.210.07:40:07.81#ibcon#about to read 4, iclass 32, count 0 2006.210.07:40:07.81#ibcon#read 4, iclass 32, count 0 2006.210.07:40:07.81#ibcon#about to read 5, iclass 32, count 0 2006.210.07:40:07.81#ibcon#read 5, iclass 32, count 0 2006.210.07:40:07.81#ibcon#about to read 6, iclass 32, count 0 2006.210.07:40:07.81#ibcon#read 6, iclass 32, count 0 2006.210.07:40:07.81#ibcon#end of sib2, iclass 32, count 0 2006.210.07:40:07.81#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:40:07.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:40:07.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:40:07.81#ibcon#*before write, iclass 32, count 0 2006.210.07:40:07.81#ibcon#enter sib2, iclass 32, count 0 2006.210.07:40:07.81#ibcon#flushed, iclass 32, count 0 2006.210.07:40:07.81#ibcon#about to write, iclass 32, count 0 2006.210.07:40:07.81#ibcon#wrote, iclass 32, count 0 2006.210.07:40:07.81#ibcon#about to read 3, iclass 32, count 0 2006.210.07:40:07.85#ibcon#read 3, iclass 32, count 0 2006.210.07:40:07.85#ibcon#about to read 4, iclass 32, count 0 2006.210.07:40:07.85#ibcon#read 4, iclass 32, count 0 2006.210.07:40:07.85#ibcon#about to read 5, iclass 32, count 0 2006.210.07:40:07.85#ibcon#read 5, iclass 32, count 0 2006.210.07:40:07.85#ibcon#about to read 6, iclass 32, count 0 2006.210.07:40:07.85#ibcon#read 6, iclass 32, count 0 2006.210.07:40:07.85#ibcon#end of sib2, iclass 32, count 0 2006.210.07:40:07.85#ibcon#*after write, iclass 32, count 0 2006.210.07:40:07.85#ibcon#*before return 0, iclass 32, count 0 2006.210.07:40:07.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:07.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:07.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:40:07.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:40:07.85$vc4f8/va=2,7 2006.210.07:40:07.85#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:40:07.85#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:40:07.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:07.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:07.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:07.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:07.91#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:40:07.91#ibcon#first serial, iclass 34, count 2 2006.210.07:40:07.91#ibcon#enter sib2, iclass 34, count 2 2006.210.07:40:07.91#ibcon#flushed, iclass 34, count 2 2006.210.07:40:07.91#ibcon#about to write, iclass 34, count 2 2006.210.07:40:07.91#ibcon#wrote, iclass 34, count 2 2006.210.07:40:07.91#ibcon#about to read 3, iclass 34, count 2 2006.210.07:40:07.93#ibcon#read 3, iclass 34, count 2 2006.210.07:40:07.93#ibcon#about to read 4, iclass 34, count 2 2006.210.07:40:07.93#ibcon#read 4, iclass 34, count 2 2006.210.07:40:07.93#ibcon#about to read 5, iclass 34, count 2 2006.210.07:40:07.93#ibcon#read 5, iclass 34, count 2 2006.210.07:40:07.93#ibcon#about to read 6, iclass 34, count 2 2006.210.07:40:07.93#ibcon#read 6, iclass 34, count 2 2006.210.07:40:07.93#ibcon#end of sib2, iclass 34, count 2 2006.210.07:40:07.93#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:40:07.93#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:40:07.93#ibcon#[25=AT02-07\r\n] 2006.210.07:40:07.93#ibcon#*before write, iclass 34, count 2 2006.210.07:40:07.93#ibcon#enter sib2, iclass 34, count 2 2006.210.07:40:07.93#ibcon#flushed, iclass 34, count 2 2006.210.07:40:07.93#ibcon#about to write, iclass 34, count 2 2006.210.07:40:07.93#ibcon#wrote, iclass 34, count 2 2006.210.07:40:07.93#ibcon#about to read 3, iclass 34, count 2 2006.210.07:40:07.96#ibcon#read 3, iclass 34, count 2 2006.210.07:40:07.96#ibcon#about to read 4, iclass 34, count 2 2006.210.07:40:07.96#ibcon#read 4, iclass 34, count 2 2006.210.07:40:07.96#ibcon#about to read 5, iclass 34, count 2 2006.210.07:40:07.96#ibcon#read 5, iclass 34, count 2 2006.210.07:40:07.96#ibcon#about to read 6, iclass 34, count 2 2006.210.07:40:07.96#ibcon#read 6, iclass 34, count 2 2006.210.07:40:07.96#ibcon#end of sib2, iclass 34, count 2 2006.210.07:40:07.96#ibcon#*after write, iclass 34, count 2 2006.210.07:40:07.96#ibcon#*before return 0, iclass 34, count 2 2006.210.07:40:07.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:07.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:07.96#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:40:07.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:07.96#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:08.08#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:08.08#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:08.08#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:40:08.08#ibcon#first serial, iclass 34, count 0 2006.210.07:40:08.08#ibcon#enter sib2, iclass 34, count 0 2006.210.07:40:08.08#ibcon#flushed, iclass 34, count 0 2006.210.07:40:08.08#ibcon#about to write, iclass 34, count 0 2006.210.07:40:08.08#ibcon#wrote, iclass 34, count 0 2006.210.07:40:08.08#ibcon#about to read 3, iclass 34, count 0 2006.210.07:40:08.10#ibcon#read 3, iclass 34, count 0 2006.210.07:40:08.10#ibcon#about to read 4, iclass 34, count 0 2006.210.07:40:08.10#ibcon#read 4, iclass 34, count 0 2006.210.07:40:08.10#ibcon#about to read 5, iclass 34, count 0 2006.210.07:40:08.10#ibcon#read 5, iclass 34, count 0 2006.210.07:40:08.10#ibcon#about to read 6, iclass 34, count 0 2006.210.07:40:08.10#ibcon#read 6, iclass 34, count 0 2006.210.07:40:08.10#ibcon#end of sib2, iclass 34, count 0 2006.210.07:40:08.10#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:40:08.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:40:08.10#ibcon#[25=USB\r\n] 2006.210.07:40:08.10#ibcon#*before write, iclass 34, count 0 2006.210.07:40:08.10#ibcon#enter sib2, iclass 34, count 0 2006.210.07:40:08.10#ibcon#flushed, iclass 34, count 0 2006.210.07:40:08.10#ibcon#about to write, iclass 34, count 0 2006.210.07:40:08.10#ibcon#wrote, iclass 34, count 0 2006.210.07:40:08.10#ibcon#about to read 3, iclass 34, count 0 2006.210.07:40:08.13#ibcon#read 3, iclass 34, count 0 2006.210.07:40:08.13#ibcon#about to read 4, iclass 34, count 0 2006.210.07:40:08.13#ibcon#read 4, iclass 34, count 0 2006.210.07:40:08.13#ibcon#about to read 5, iclass 34, count 0 2006.210.07:40:08.13#ibcon#read 5, iclass 34, count 0 2006.210.07:40:08.13#ibcon#about to read 6, iclass 34, count 0 2006.210.07:40:08.13#ibcon#read 6, iclass 34, count 0 2006.210.07:40:08.13#ibcon#end of sib2, iclass 34, count 0 2006.210.07:40:08.13#ibcon#*after write, iclass 34, count 0 2006.210.07:40:08.13#ibcon#*before return 0, iclass 34, count 0 2006.210.07:40:08.13#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:08.13#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:08.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:40:08.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:40:08.13$vc4f8/valo=3,672.99 2006.210.07:40:08.13#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:40:08.13#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:40:08.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:08.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:08.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:08.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:08.13#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:40:08.13#ibcon#first serial, iclass 36, count 0 2006.210.07:40:08.13#ibcon#enter sib2, iclass 36, count 0 2006.210.07:40:08.13#ibcon#flushed, iclass 36, count 0 2006.210.07:40:08.13#ibcon#about to write, iclass 36, count 0 2006.210.07:40:08.13#ibcon#wrote, iclass 36, count 0 2006.210.07:40:08.13#ibcon#about to read 3, iclass 36, count 0 2006.210.07:40:08.15#ibcon#read 3, iclass 36, count 0 2006.210.07:40:08.15#ibcon#about to read 4, iclass 36, count 0 2006.210.07:40:08.15#ibcon#read 4, iclass 36, count 0 2006.210.07:40:08.15#ibcon#about to read 5, iclass 36, count 0 2006.210.07:40:08.15#ibcon#read 5, iclass 36, count 0 2006.210.07:40:08.15#ibcon#about to read 6, iclass 36, count 0 2006.210.07:40:08.15#ibcon#read 6, iclass 36, count 0 2006.210.07:40:08.15#ibcon#end of sib2, iclass 36, count 0 2006.210.07:40:08.15#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:40:08.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:40:08.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:40:08.15#ibcon#*before write, iclass 36, count 0 2006.210.07:40:08.15#ibcon#enter sib2, iclass 36, count 0 2006.210.07:40:08.15#ibcon#flushed, iclass 36, count 0 2006.210.07:40:08.15#ibcon#about to write, iclass 36, count 0 2006.210.07:40:08.15#ibcon#wrote, iclass 36, count 0 2006.210.07:40:08.15#ibcon#about to read 3, iclass 36, count 0 2006.210.07:40:08.19#ibcon#read 3, iclass 36, count 0 2006.210.07:40:08.19#ibcon#about to read 4, iclass 36, count 0 2006.210.07:40:08.19#ibcon#read 4, iclass 36, count 0 2006.210.07:40:08.19#ibcon#about to read 5, iclass 36, count 0 2006.210.07:40:08.19#ibcon#read 5, iclass 36, count 0 2006.210.07:40:08.19#ibcon#about to read 6, iclass 36, count 0 2006.210.07:40:08.19#ibcon#read 6, iclass 36, count 0 2006.210.07:40:08.19#ibcon#end of sib2, iclass 36, count 0 2006.210.07:40:08.19#ibcon#*after write, iclass 36, count 0 2006.210.07:40:08.19#ibcon#*before return 0, iclass 36, count 0 2006.210.07:40:08.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:08.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:08.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:40:08.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:40:08.19$vc4f8/va=3,6 2006.210.07:40:08.19#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:40:08.19#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:40:08.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:08.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:08.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:08.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:08.25#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:40:08.25#ibcon#first serial, iclass 38, count 2 2006.210.07:40:08.25#ibcon#enter sib2, iclass 38, count 2 2006.210.07:40:08.25#ibcon#flushed, iclass 38, count 2 2006.210.07:40:08.25#ibcon#about to write, iclass 38, count 2 2006.210.07:40:08.25#ibcon#wrote, iclass 38, count 2 2006.210.07:40:08.25#ibcon#about to read 3, iclass 38, count 2 2006.210.07:40:08.27#ibcon#read 3, iclass 38, count 2 2006.210.07:40:08.27#ibcon#about to read 4, iclass 38, count 2 2006.210.07:40:08.27#ibcon#read 4, iclass 38, count 2 2006.210.07:40:08.27#ibcon#about to read 5, iclass 38, count 2 2006.210.07:40:08.27#ibcon#read 5, iclass 38, count 2 2006.210.07:40:08.27#ibcon#about to read 6, iclass 38, count 2 2006.210.07:40:08.27#ibcon#read 6, iclass 38, count 2 2006.210.07:40:08.27#ibcon#end of sib2, iclass 38, count 2 2006.210.07:40:08.27#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:40:08.27#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:40:08.27#ibcon#[25=AT03-06\r\n] 2006.210.07:40:08.27#ibcon#*before write, iclass 38, count 2 2006.210.07:40:08.27#ibcon#enter sib2, iclass 38, count 2 2006.210.07:40:08.27#ibcon#flushed, iclass 38, count 2 2006.210.07:40:08.27#ibcon#about to write, iclass 38, count 2 2006.210.07:40:08.27#ibcon#wrote, iclass 38, count 2 2006.210.07:40:08.27#ibcon#about to read 3, iclass 38, count 2 2006.210.07:40:08.30#ibcon#read 3, iclass 38, count 2 2006.210.07:40:08.30#ibcon#about to read 4, iclass 38, count 2 2006.210.07:40:08.30#ibcon#read 4, iclass 38, count 2 2006.210.07:40:08.30#ibcon#about to read 5, iclass 38, count 2 2006.210.07:40:08.30#ibcon#read 5, iclass 38, count 2 2006.210.07:40:08.30#ibcon#about to read 6, iclass 38, count 2 2006.210.07:40:08.30#ibcon#read 6, iclass 38, count 2 2006.210.07:40:08.30#ibcon#end of sib2, iclass 38, count 2 2006.210.07:40:08.30#ibcon#*after write, iclass 38, count 2 2006.210.07:40:08.30#ibcon#*before return 0, iclass 38, count 2 2006.210.07:40:08.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:08.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:08.30#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:40:08.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:08.30#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:08.42#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:08.42#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:08.42#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:40:08.42#ibcon#first serial, iclass 38, count 0 2006.210.07:40:08.42#ibcon#enter sib2, iclass 38, count 0 2006.210.07:40:08.42#ibcon#flushed, iclass 38, count 0 2006.210.07:40:08.42#ibcon#about to write, iclass 38, count 0 2006.210.07:40:08.42#ibcon#wrote, iclass 38, count 0 2006.210.07:40:08.42#ibcon#about to read 3, iclass 38, count 0 2006.210.07:40:08.44#ibcon#read 3, iclass 38, count 0 2006.210.07:40:08.44#ibcon#about to read 4, iclass 38, count 0 2006.210.07:40:08.44#ibcon#read 4, iclass 38, count 0 2006.210.07:40:08.44#ibcon#about to read 5, iclass 38, count 0 2006.210.07:40:08.44#ibcon#read 5, iclass 38, count 0 2006.210.07:40:08.44#ibcon#about to read 6, iclass 38, count 0 2006.210.07:40:08.44#ibcon#read 6, iclass 38, count 0 2006.210.07:40:08.44#ibcon#end of sib2, iclass 38, count 0 2006.210.07:40:08.44#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:40:08.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:40:08.44#ibcon#[25=USB\r\n] 2006.210.07:40:08.44#ibcon#*before write, iclass 38, count 0 2006.210.07:40:08.44#ibcon#enter sib2, iclass 38, count 0 2006.210.07:40:08.44#ibcon#flushed, iclass 38, count 0 2006.210.07:40:08.44#ibcon#about to write, iclass 38, count 0 2006.210.07:40:08.44#ibcon#wrote, iclass 38, count 0 2006.210.07:40:08.44#ibcon#about to read 3, iclass 38, count 0 2006.210.07:40:08.47#ibcon#read 3, iclass 38, count 0 2006.210.07:40:08.47#ibcon#about to read 4, iclass 38, count 0 2006.210.07:40:08.47#ibcon#read 4, iclass 38, count 0 2006.210.07:40:08.47#ibcon#about to read 5, iclass 38, count 0 2006.210.07:40:08.47#ibcon#read 5, iclass 38, count 0 2006.210.07:40:08.47#ibcon#about to read 6, iclass 38, count 0 2006.210.07:40:08.47#ibcon#read 6, iclass 38, count 0 2006.210.07:40:08.47#ibcon#end of sib2, iclass 38, count 0 2006.210.07:40:08.47#ibcon#*after write, iclass 38, count 0 2006.210.07:40:08.47#ibcon#*before return 0, iclass 38, count 0 2006.210.07:40:08.47#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:08.47#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:08.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:40:08.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:40:08.47$vc4f8/valo=4,832.99 2006.210.07:40:08.47#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:40:08.47#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:40:08.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:08.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:08.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:08.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:08.47#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:40:08.47#ibcon#first serial, iclass 40, count 0 2006.210.07:40:08.47#ibcon#enter sib2, iclass 40, count 0 2006.210.07:40:08.47#ibcon#flushed, iclass 40, count 0 2006.210.07:40:08.47#ibcon#about to write, iclass 40, count 0 2006.210.07:40:08.47#ibcon#wrote, iclass 40, count 0 2006.210.07:40:08.47#ibcon#about to read 3, iclass 40, count 0 2006.210.07:40:08.49#ibcon#read 3, iclass 40, count 0 2006.210.07:40:08.49#ibcon#about to read 4, iclass 40, count 0 2006.210.07:40:08.49#ibcon#read 4, iclass 40, count 0 2006.210.07:40:08.49#ibcon#about to read 5, iclass 40, count 0 2006.210.07:40:08.49#ibcon#read 5, iclass 40, count 0 2006.210.07:40:08.49#ibcon#about to read 6, iclass 40, count 0 2006.210.07:40:08.49#ibcon#read 6, iclass 40, count 0 2006.210.07:40:08.49#ibcon#end of sib2, iclass 40, count 0 2006.210.07:40:08.49#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:40:08.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:40:08.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:40:08.49#ibcon#*before write, iclass 40, count 0 2006.210.07:40:08.49#ibcon#enter sib2, iclass 40, count 0 2006.210.07:40:08.49#ibcon#flushed, iclass 40, count 0 2006.210.07:40:08.49#ibcon#about to write, iclass 40, count 0 2006.210.07:40:08.49#ibcon#wrote, iclass 40, count 0 2006.210.07:40:08.49#ibcon#about to read 3, iclass 40, count 0 2006.210.07:40:08.53#ibcon#read 3, iclass 40, count 0 2006.210.07:40:08.53#ibcon#about to read 4, iclass 40, count 0 2006.210.07:40:08.53#ibcon#read 4, iclass 40, count 0 2006.210.07:40:08.53#ibcon#about to read 5, iclass 40, count 0 2006.210.07:40:08.53#ibcon#read 5, iclass 40, count 0 2006.210.07:40:08.53#ibcon#about to read 6, iclass 40, count 0 2006.210.07:40:08.53#ibcon#read 6, iclass 40, count 0 2006.210.07:40:08.53#ibcon#end of sib2, iclass 40, count 0 2006.210.07:40:08.53#ibcon#*after write, iclass 40, count 0 2006.210.07:40:08.53#ibcon#*before return 0, iclass 40, count 0 2006.210.07:40:08.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:08.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:08.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:40:08.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:40:08.53$vc4f8/va=4,7 2006.210.07:40:08.53#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:40:08.53#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:40:08.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:08.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:08.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:08.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:08.59#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:40:08.59#ibcon#first serial, iclass 4, count 2 2006.210.07:40:08.59#ibcon#enter sib2, iclass 4, count 2 2006.210.07:40:08.59#ibcon#flushed, iclass 4, count 2 2006.210.07:40:08.59#ibcon#about to write, iclass 4, count 2 2006.210.07:40:08.59#ibcon#wrote, iclass 4, count 2 2006.210.07:40:08.59#ibcon#about to read 3, iclass 4, count 2 2006.210.07:40:08.61#ibcon#read 3, iclass 4, count 2 2006.210.07:40:08.61#ibcon#about to read 4, iclass 4, count 2 2006.210.07:40:08.61#ibcon#read 4, iclass 4, count 2 2006.210.07:40:08.61#ibcon#about to read 5, iclass 4, count 2 2006.210.07:40:08.61#ibcon#read 5, iclass 4, count 2 2006.210.07:40:08.61#ibcon#about to read 6, iclass 4, count 2 2006.210.07:40:08.61#ibcon#read 6, iclass 4, count 2 2006.210.07:40:08.61#ibcon#end of sib2, iclass 4, count 2 2006.210.07:40:08.61#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:40:08.61#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:40:08.61#ibcon#[25=AT04-07\r\n] 2006.210.07:40:08.61#ibcon#*before write, iclass 4, count 2 2006.210.07:40:08.61#ibcon#enter sib2, iclass 4, count 2 2006.210.07:40:08.61#ibcon#flushed, iclass 4, count 2 2006.210.07:40:08.61#ibcon#about to write, iclass 4, count 2 2006.210.07:40:08.61#ibcon#wrote, iclass 4, count 2 2006.210.07:40:08.61#ibcon#about to read 3, iclass 4, count 2 2006.210.07:40:08.64#ibcon#read 3, iclass 4, count 2 2006.210.07:40:08.64#ibcon#about to read 4, iclass 4, count 2 2006.210.07:40:08.64#ibcon#read 4, iclass 4, count 2 2006.210.07:40:08.64#ibcon#about to read 5, iclass 4, count 2 2006.210.07:40:08.64#ibcon#read 5, iclass 4, count 2 2006.210.07:40:08.64#ibcon#about to read 6, iclass 4, count 2 2006.210.07:40:08.64#ibcon#read 6, iclass 4, count 2 2006.210.07:40:08.64#ibcon#end of sib2, iclass 4, count 2 2006.210.07:40:08.64#ibcon#*after write, iclass 4, count 2 2006.210.07:40:08.64#ibcon#*before return 0, iclass 4, count 2 2006.210.07:40:08.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:08.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:08.64#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:40:08.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:08.64#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:08.76#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:08.76#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:08.76#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:40:08.76#ibcon#first serial, iclass 4, count 0 2006.210.07:40:08.76#ibcon#enter sib2, iclass 4, count 0 2006.210.07:40:08.76#ibcon#flushed, iclass 4, count 0 2006.210.07:40:08.76#ibcon#about to write, iclass 4, count 0 2006.210.07:40:08.76#ibcon#wrote, iclass 4, count 0 2006.210.07:40:08.76#ibcon#about to read 3, iclass 4, count 0 2006.210.07:40:08.78#ibcon#read 3, iclass 4, count 0 2006.210.07:40:08.78#ibcon#about to read 4, iclass 4, count 0 2006.210.07:40:08.78#ibcon#read 4, iclass 4, count 0 2006.210.07:40:08.78#ibcon#about to read 5, iclass 4, count 0 2006.210.07:40:08.78#ibcon#read 5, iclass 4, count 0 2006.210.07:40:08.78#ibcon#about to read 6, iclass 4, count 0 2006.210.07:40:08.78#ibcon#read 6, iclass 4, count 0 2006.210.07:40:08.78#ibcon#end of sib2, iclass 4, count 0 2006.210.07:40:08.78#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:40:08.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:40:08.78#ibcon#[25=USB\r\n] 2006.210.07:40:08.78#ibcon#*before write, iclass 4, count 0 2006.210.07:40:08.78#ibcon#enter sib2, iclass 4, count 0 2006.210.07:40:08.78#ibcon#flushed, iclass 4, count 0 2006.210.07:40:08.78#ibcon#about to write, iclass 4, count 0 2006.210.07:40:08.78#ibcon#wrote, iclass 4, count 0 2006.210.07:40:08.78#ibcon#about to read 3, iclass 4, count 0 2006.210.07:40:08.81#ibcon#read 3, iclass 4, count 0 2006.210.07:40:08.81#ibcon#about to read 4, iclass 4, count 0 2006.210.07:40:08.81#ibcon#read 4, iclass 4, count 0 2006.210.07:40:08.81#ibcon#about to read 5, iclass 4, count 0 2006.210.07:40:08.81#ibcon#read 5, iclass 4, count 0 2006.210.07:40:08.81#ibcon#about to read 6, iclass 4, count 0 2006.210.07:40:08.81#ibcon#read 6, iclass 4, count 0 2006.210.07:40:08.81#ibcon#end of sib2, iclass 4, count 0 2006.210.07:40:08.81#ibcon#*after write, iclass 4, count 0 2006.210.07:40:08.81#ibcon#*before return 0, iclass 4, count 0 2006.210.07:40:08.81#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:08.81#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:08.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:40:08.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:40:08.81$vc4f8/valo=5,652.99 2006.210.07:40:08.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:40:08.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:40:08.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:08.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:08.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:08.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:08.81#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:40:08.81#ibcon#first serial, iclass 6, count 0 2006.210.07:40:08.81#ibcon#enter sib2, iclass 6, count 0 2006.210.07:40:08.81#ibcon#flushed, iclass 6, count 0 2006.210.07:40:08.81#ibcon#about to write, iclass 6, count 0 2006.210.07:40:08.81#ibcon#wrote, iclass 6, count 0 2006.210.07:40:08.81#ibcon#about to read 3, iclass 6, count 0 2006.210.07:40:08.83#ibcon#read 3, iclass 6, count 0 2006.210.07:40:08.83#ibcon#about to read 4, iclass 6, count 0 2006.210.07:40:08.83#ibcon#read 4, iclass 6, count 0 2006.210.07:40:08.83#ibcon#about to read 5, iclass 6, count 0 2006.210.07:40:08.83#ibcon#read 5, iclass 6, count 0 2006.210.07:40:08.83#ibcon#about to read 6, iclass 6, count 0 2006.210.07:40:08.83#ibcon#read 6, iclass 6, count 0 2006.210.07:40:08.83#ibcon#end of sib2, iclass 6, count 0 2006.210.07:40:08.83#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:40:08.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:40:08.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:40:08.83#ibcon#*before write, iclass 6, count 0 2006.210.07:40:08.83#ibcon#enter sib2, iclass 6, count 0 2006.210.07:40:08.83#ibcon#flushed, iclass 6, count 0 2006.210.07:40:08.83#ibcon#about to write, iclass 6, count 0 2006.210.07:40:08.83#ibcon#wrote, iclass 6, count 0 2006.210.07:40:08.83#ibcon#about to read 3, iclass 6, count 0 2006.210.07:40:08.87#ibcon#read 3, iclass 6, count 0 2006.210.07:40:08.87#ibcon#about to read 4, iclass 6, count 0 2006.210.07:40:08.87#ibcon#read 4, iclass 6, count 0 2006.210.07:40:08.87#ibcon#about to read 5, iclass 6, count 0 2006.210.07:40:08.87#ibcon#read 5, iclass 6, count 0 2006.210.07:40:08.87#ibcon#about to read 6, iclass 6, count 0 2006.210.07:40:08.87#ibcon#read 6, iclass 6, count 0 2006.210.07:40:08.87#ibcon#end of sib2, iclass 6, count 0 2006.210.07:40:08.87#ibcon#*after write, iclass 6, count 0 2006.210.07:40:08.87#ibcon#*before return 0, iclass 6, count 0 2006.210.07:40:08.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:08.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:08.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:40:08.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:40:08.87$vc4f8/va=5,7 2006.210.07:40:08.87#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:40:08.87#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:40:08.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:08.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:08.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:08.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:08.93#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:40:08.93#ibcon#first serial, iclass 10, count 2 2006.210.07:40:08.93#ibcon#enter sib2, iclass 10, count 2 2006.210.07:40:08.93#ibcon#flushed, iclass 10, count 2 2006.210.07:40:08.93#ibcon#about to write, iclass 10, count 2 2006.210.07:40:08.93#ibcon#wrote, iclass 10, count 2 2006.210.07:40:08.93#ibcon#about to read 3, iclass 10, count 2 2006.210.07:40:08.95#ibcon#read 3, iclass 10, count 2 2006.210.07:40:08.95#ibcon#about to read 4, iclass 10, count 2 2006.210.07:40:08.95#ibcon#read 4, iclass 10, count 2 2006.210.07:40:08.95#ibcon#about to read 5, iclass 10, count 2 2006.210.07:40:08.95#ibcon#read 5, iclass 10, count 2 2006.210.07:40:08.95#ibcon#about to read 6, iclass 10, count 2 2006.210.07:40:08.95#ibcon#read 6, iclass 10, count 2 2006.210.07:40:08.95#ibcon#end of sib2, iclass 10, count 2 2006.210.07:40:08.95#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:40:08.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:40:08.95#ibcon#[25=AT05-07\r\n] 2006.210.07:40:08.95#ibcon#*before write, iclass 10, count 2 2006.210.07:40:08.95#ibcon#enter sib2, iclass 10, count 2 2006.210.07:40:08.95#ibcon#flushed, iclass 10, count 2 2006.210.07:40:08.95#ibcon#about to write, iclass 10, count 2 2006.210.07:40:08.95#ibcon#wrote, iclass 10, count 2 2006.210.07:40:08.95#ibcon#about to read 3, iclass 10, count 2 2006.210.07:40:08.98#ibcon#read 3, iclass 10, count 2 2006.210.07:40:08.98#ibcon#about to read 4, iclass 10, count 2 2006.210.07:40:08.98#ibcon#read 4, iclass 10, count 2 2006.210.07:40:08.98#ibcon#about to read 5, iclass 10, count 2 2006.210.07:40:08.98#ibcon#read 5, iclass 10, count 2 2006.210.07:40:08.98#ibcon#about to read 6, iclass 10, count 2 2006.210.07:40:08.98#ibcon#read 6, iclass 10, count 2 2006.210.07:40:08.98#ibcon#end of sib2, iclass 10, count 2 2006.210.07:40:08.98#ibcon#*after write, iclass 10, count 2 2006.210.07:40:08.98#ibcon#*before return 0, iclass 10, count 2 2006.210.07:40:08.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:08.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:08.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:40:08.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:08.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:09.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:09.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:09.10#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:40:09.10#ibcon#first serial, iclass 10, count 0 2006.210.07:40:09.10#ibcon#enter sib2, iclass 10, count 0 2006.210.07:40:09.10#ibcon#flushed, iclass 10, count 0 2006.210.07:40:09.10#ibcon#about to write, iclass 10, count 0 2006.210.07:40:09.10#ibcon#wrote, iclass 10, count 0 2006.210.07:40:09.10#ibcon#about to read 3, iclass 10, count 0 2006.210.07:40:09.12#ibcon#read 3, iclass 10, count 0 2006.210.07:40:09.12#ibcon#about to read 4, iclass 10, count 0 2006.210.07:40:09.12#ibcon#read 4, iclass 10, count 0 2006.210.07:40:09.12#ibcon#about to read 5, iclass 10, count 0 2006.210.07:40:09.12#ibcon#read 5, iclass 10, count 0 2006.210.07:40:09.12#ibcon#about to read 6, iclass 10, count 0 2006.210.07:40:09.12#ibcon#read 6, iclass 10, count 0 2006.210.07:40:09.12#ibcon#end of sib2, iclass 10, count 0 2006.210.07:40:09.12#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:40:09.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:40:09.12#ibcon#[25=USB\r\n] 2006.210.07:40:09.12#ibcon#*before write, iclass 10, count 0 2006.210.07:40:09.12#ibcon#enter sib2, iclass 10, count 0 2006.210.07:40:09.12#ibcon#flushed, iclass 10, count 0 2006.210.07:40:09.12#ibcon#about to write, iclass 10, count 0 2006.210.07:40:09.12#ibcon#wrote, iclass 10, count 0 2006.210.07:40:09.12#ibcon#about to read 3, iclass 10, count 0 2006.210.07:40:09.15#ibcon#read 3, iclass 10, count 0 2006.210.07:40:09.15#ibcon#about to read 4, iclass 10, count 0 2006.210.07:40:09.15#ibcon#read 4, iclass 10, count 0 2006.210.07:40:09.15#ibcon#about to read 5, iclass 10, count 0 2006.210.07:40:09.15#ibcon#read 5, iclass 10, count 0 2006.210.07:40:09.15#ibcon#about to read 6, iclass 10, count 0 2006.210.07:40:09.15#ibcon#read 6, iclass 10, count 0 2006.210.07:40:09.15#ibcon#end of sib2, iclass 10, count 0 2006.210.07:40:09.15#ibcon#*after write, iclass 10, count 0 2006.210.07:40:09.15#ibcon#*before return 0, iclass 10, count 0 2006.210.07:40:09.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:09.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:09.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:40:09.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:40:09.15$vc4f8/valo=6,772.99 2006.210.07:40:09.15#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:40:09.15#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:40:09.15#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:09.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:09.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:09.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:09.15#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:40:09.15#ibcon#first serial, iclass 12, count 0 2006.210.07:40:09.15#ibcon#enter sib2, iclass 12, count 0 2006.210.07:40:09.15#ibcon#flushed, iclass 12, count 0 2006.210.07:40:09.15#ibcon#about to write, iclass 12, count 0 2006.210.07:40:09.15#ibcon#wrote, iclass 12, count 0 2006.210.07:40:09.15#ibcon#about to read 3, iclass 12, count 0 2006.210.07:40:09.17#ibcon#read 3, iclass 12, count 0 2006.210.07:40:09.17#ibcon#about to read 4, iclass 12, count 0 2006.210.07:40:09.17#ibcon#read 4, iclass 12, count 0 2006.210.07:40:09.17#ibcon#about to read 5, iclass 12, count 0 2006.210.07:40:09.17#ibcon#read 5, iclass 12, count 0 2006.210.07:40:09.17#ibcon#about to read 6, iclass 12, count 0 2006.210.07:40:09.17#ibcon#read 6, iclass 12, count 0 2006.210.07:40:09.17#ibcon#end of sib2, iclass 12, count 0 2006.210.07:40:09.17#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:40:09.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:40:09.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:40:09.17#ibcon#*before write, iclass 12, count 0 2006.210.07:40:09.17#ibcon#enter sib2, iclass 12, count 0 2006.210.07:40:09.17#ibcon#flushed, iclass 12, count 0 2006.210.07:40:09.17#ibcon#about to write, iclass 12, count 0 2006.210.07:40:09.17#ibcon#wrote, iclass 12, count 0 2006.210.07:40:09.17#ibcon#about to read 3, iclass 12, count 0 2006.210.07:40:09.21#ibcon#read 3, iclass 12, count 0 2006.210.07:40:09.21#ibcon#about to read 4, iclass 12, count 0 2006.210.07:40:09.21#ibcon#read 4, iclass 12, count 0 2006.210.07:40:09.21#ibcon#about to read 5, iclass 12, count 0 2006.210.07:40:09.21#ibcon#read 5, iclass 12, count 0 2006.210.07:40:09.21#ibcon#about to read 6, iclass 12, count 0 2006.210.07:40:09.21#ibcon#read 6, iclass 12, count 0 2006.210.07:40:09.21#ibcon#end of sib2, iclass 12, count 0 2006.210.07:40:09.21#ibcon#*after write, iclass 12, count 0 2006.210.07:40:09.21#ibcon#*before return 0, iclass 12, count 0 2006.210.07:40:09.21#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:09.21#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:09.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:40:09.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:40:09.21$vc4f8/va=6,6 2006.210.07:40:09.21#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:40:09.21#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:40:09.21#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:09.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:40:09.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:40:09.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:40:09.27#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:40:09.27#ibcon#first serial, iclass 14, count 2 2006.210.07:40:09.27#ibcon#enter sib2, iclass 14, count 2 2006.210.07:40:09.27#ibcon#flushed, iclass 14, count 2 2006.210.07:40:09.27#ibcon#about to write, iclass 14, count 2 2006.210.07:40:09.27#ibcon#wrote, iclass 14, count 2 2006.210.07:40:09.27#ibcon#about to read 3, iclass 14, count 2 2006.210.07:40:09.29#ibcon#read 3, iclass 14, count 2 2006.210.07:40:09.29#ibcon#about to read 4, iclass 14, count 2 2006.210.07:40:09.29#ibcon#read 4, iclass 14, count 2 2006.210.07:40:09.29#ibcon#about to read 5, iclass 14, count 2 2006.210.07:40:09.29#ibcon#read 5, iclass 14, count 2 2006.210.07:40:09.29#ibcon#about to read 6, iclass 14, count 2 2006.210.07:40:09.29#ibcon#read 6, iclass 14, count 2 2006.210.07:40:09.29#ibcon#end of sib2, iclass 14, count 2 2006.210.07:40:09.29#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:40:09.29#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:40:09.29#ibcon#[25=AT06-06\r\n] 2006.210.07:40:09.29#ibcon#*before write, iclass 14, count 2 2006.210.07:40:09.29#ibcon#enter sib2, iclass 14, count 2 2006.210.07:40:09.29#ibcon#flushed, iclass 14, count 2 2006.210.07:40:09.29#ibcon#about to write, iclass 14, count 2 2006.210.07:40:09.29#ibcon#wrote, iclass 14, count 2 2006.210.07:40:09.29#ibcon#about to read 3, iclass 14, count 2 2006.210.07:40:09.32#ibcon#read 3, iclass 14, count 2 2006.210.07:40:09.32#ibcon#about to read 4, iclass 14, count 2 2006.210.07:40:09.32#ibcon#read 4, iclass 14, count 2 2006.210.07:40:09.32#ibcon#about to read 5, iclass 14, count 2 2006.210.07:40:09.32#ibcon#read 5, iclass 14, count 2 2006.210.07:40:09.32#ibcon#about to read 6, iclass 14, count 2 2006.210.07:40:09.32#ibcon#read 6, iclass 14, count 2 2006.210.07:40:09.32#ibcon#end of sib2, iclass 14, count 2 2006.210.07:40:09.32#ibcon#*after write, iclass 14, count 2 2006.210.07:40:09.32#ibcon#*before return 0, iclass 14, count 2 2006.210.07:40:09.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:40:09.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:40:09.32#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:40:09.32#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:09.32#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:40:09.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:40:09.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:40:09.44#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:40:09.44#ibcon#first serial, iclass 14, count 0 2006.210.07:40:09.44#ibcon#enter sib2, iclass 14, count 0 2006.210.07:40:09.44#ibcon#flushed, iclass 14, count 0 2006.210.07:40:09.44#ibcon#about to write, iclass 14, count 0 2006.210.07:40:09.44#ibcon#wrote, iclass 14, count 0 2006.210.07:40:09.44#ibcon#about to read 3, iclass 14, count 0 2006.210.07:40:09.46#ibcon#read 3, iclass 14, count 0 2006.210.07:40:09.46#ibcon#about to read 4, iclass 14, count 0 2006.210.07:40:09.46#ibcon#read 4, iclass 14, count 0 2006.210.07:40:09.46#ibcon#about to read 5, iclass 14, count 0 2006.210.07:40:09.46#ibcon#read 5, iclass 14, count 0 2006.210.07:40:09.46#ibcon#about to read 6, iclass 14, count 0 2006.210.07:40:09.46#ibcon#read 6, iclass 14, count 0 2006.210.07:40:09.46#ibcon#end of sib2, iclass 14, count 0 2006.210.07:40:09.46#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:40:09.46#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:40:09.46#ibcon#[25=USB\r\n] 2006.210.07:40:09.46#ibcon#*before write, iclass 14, count 0 2006.210.07:40:09.46#ibcon#enter sib2, iclass 14, count 0 2006.210.07:40:09.46#ibcon#flushed, iclass 14, count 0 2006.210.07:40:09.46#ibcon#about to write, iclass 14, count 0 2006.210.07:40:09.46#ibcon#wrote, iclass 14, count 0 2006.210.07:40:09.46#ibcon#about to read 3, iclass 14, count 0 2006.210.07:40:09.49#ibcon#read 3, iclass 14, count 0 2006.210.07:40:09.49#ibcon#about to read 4, iclass 14, count 0 2006.210.07:40:09.49#ibcon#read 4, iclass 14, count 0 2006.210.07:40:09.49#ibcon#about to read 5, iclass 14, count 0 2006.210.07:40:09.49#ibcon#read 5, iclass 14, count 0 2006.210.07:40:09.49#ibcon#about to read 6, iclass 14, count 0 2006.210.07:40:09.49#ibcon#read 6, iclass 14, count 0 2006.210.07:40:09.49#ibcon#end of sib2, iclass 14, count 0 2006.210.07:40:09.49#ibcon#*after write, iclass 14, count 0 2006.210.07:40:09.49#ibcon#*before return 0, iclass 14, count 0 2006.210.07:40:09.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:40:09.49#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:40:09.49#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:40:09.49#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:40:09.49$vc4f8/valo=7,832.99 2006.210.07:40:09.49#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:40:09.49#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:40:09.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:09.49#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:40:09.49#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:40:09.49#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:40:09.49#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:40:09.49#ibcon#first serial, iclass 16, count 0 2006.210.07:40:09.49#ibcon#enter sib2, iclass 16, count 0 2006.210.07:40:09.49#ibcon#flushed, iclass 16, count 0 2006.210.07:40:09.49#ibcon#about to write, iclass 16, count 0 2006.210.07:40:09.49#ibcon#wrote, iclass 16, count 0 2006.210.07:40:09.49#ibcon#about to read 3, iclass 16, count 0 2006.210.07:40:09.51#ibcon#read 3, iclass 16, count 0 2006.210.07:40:09.51#ibcon#about to read 4, iclass 16, count 0 2006.210.07:40:09.51#ibcon#read 4, iclass 16, count 0 2006.210.07:40:09.51#ibcon#about to read 5, iclass 16, count 0 2006.210.07:40:09.51#ibcon#read 5, iclass 16, count 0 2006.210.07:40:09.51#ibcon#about to read 6, iclass 16, count 0 2006.210.07:40:09.51#ibcon#read 6, iclass 16, count 0 2006.210.07:40:09.51#ibcon#end of sib2, iclass 16, count 0 2006.210.07:40:09.51#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:40:09.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:40:09.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:40:09.51#ibcon#*before write, iclass 16, count 0 2006.210.07:40:09.51#ibcon#enter sib2, iclass 16, count 0 2006.210.07:40:09.51#ibcon#flushed, iclass 16, count 0 2006.210.07:40:09.51#ibcon#about to write, iclass 16, count 0 2006.210.07:40:09.51#ibcon#wrote, iclass 16, count 0 2006.210.07:40:09.51#ibcon#about to read 3, iclass 16, count 0 2006.210.07:40:09.55#ibcon#read 3, iclass 16, count 0 2006.210.07:40:09.55#ibcon#about to read 4, iclass 16, count 0 2006.210.07:40:09.55#ibcon#read 4, iclass 16, count 0 2006.210.07:40:09.55#ibcon#about to read 5, iclass 16, count 0 2006.210.07:40:09.55#ibcon#read 5, iclass 16, count 0 2006.210.07:40:09.55#ibcon#about to read 6, iclass 16, count 0 2006.210.07:40:09.55#ibcon#read 6, iclass 16, count 0 2006.210.07:40:09.55#ibcon#end of sib2, iclass 16, count 0 2006.210.07:40:09.55#ibcon#*after write, iclass 16, count 0 2006.210.07:40:09.55#ibcon#*before return 0, iclass 16, count 0 2006.210.07:40:09.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:40:09.55#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:40:09.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:40:09.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:40:09.55$vc4f8/va=7,6 2006.210.07:40:09.55#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:40:09.55#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:40:09.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:09.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:40:09.61#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:40:09.61#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:40:09.61#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:40:09.61#ibcon#first serial, iclass 18, count 2 2006.210.07:40:09.61#ibcon#enter sib2, iclass 18, count 2 2006.210.07:40:09.61#ibcon#flushed, iclass 18, count 2 2006.210.07:40:09.61#ibcon#about to write, iclass 18, count 2 2006.210.07:40:09.61#ibcon#wrote, iclass 18, count 2 2006.210.07:40:09.61#ibcon#about to read 3, iclass 18, count 2 2006.210.07:40:09.63#ibcon#read 3, iclass 18, count 2 2006.210.07:40:09.63#ibcon#about to read 4, iclass 18, count 2 2006.210.07:40:09.63#ibcon#read 4, iclass 18, count 2 2006.210.07:40:09.63#ibcon#about to read 5, iclass 18, count 2 2006.210.07:40:09.63#ibcon#read 5, iclass 18, count 2 2006.210.07:40:09.63#ibcon#about to read 6, iclass 18, count 2 2006.210.07:40:09.63#ibcon#read 6, iclass 18, count 2 2006.210.07:40:09.63#ibcon#end of sib2, iclass 18, count 2 2006.210.07:40:09.63#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:40:09.63#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:40:09.63#ibcon#[25=AT07-06\r\n] 2006.210.07:40:09.63#ibcon#*before write, iclass 18, count 2 2006.210.07:40:09.63#ibcon#enter sib2, iclass 18, count 2 2006.210.07:40:09.63#ibcon#flushed, iclass 18, count 2 2006.210.07:40:09.63#ibcon#about to write, iclass 18, count 2 2006.210.07:40:09.63#ibcon#wrote, iclass 18, count 2 2006.210.07:40:09.63#ibcon#about to read 3, iclass 18, count 2 2006.210.07:40:09.66#ibcon#read 3, iclass 18, count 2 2006.210.07:40:09.66#ibcon#about to read 4, iclass 18, count 2 2006.210.07:40:09.66#ibcon#read 4, iclass 18, count 2 2006.210.07:40:09.66#ibcon#about to read 5, iclass 18, count 2 2006.210.07:40:09.66#ibcon#read 5, iclass 18, count 2 2006.210.07:40:09.66#ibcon#about to read 6, iclass 18, count 2 2006.210.07:40:09.66#ibcon#read 6, iclass 18, count 2 2006.210.07:40:09.66#ibcon#end of sib2, iclass 18, count 2 2006.210.07:40:09.66#ibcon#*after write, iclass 18, count 2 2006.210.07:40:09.66#ibcon#*before return 0, iclass 18, count 2 2006.210.07:40:09.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:40:09.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:40:09.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:40:09.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:09.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:40:09.78#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:40:09.78#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:40:09.78#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:40:09.78#ibcon#first serial, iclass 18, count 0 2006.210.07:40:09.78#ibcon#enter sib2, iclass 18, count 0 2006.210.07:40:09.78#ibcon#flushed, iclass 18, count 0 2006.210.07:40:09.78#ibcon#about to write, iclass 18, count 0 2006.210.07:40:09.78#ibcon#wrote, iclass 18, count 0 2006.210.07:40:09.78#ibcon#about to read 3, iclass 18, count 0 2006.210.07:40:09.80#ibcon#read 3, iclass 18, count 0 2006.210.07:40:09.80#ibcon#about to read 4, iclass 18, count 0 2006.210.07:40:09.80#ibcon#read 4, iclass 18, count 0 2006.210.07:40:09.80#ibcon#about to read 5, iclass 18, count 0 2006.210.07:40:09.80#ibcon#read 5, iclass 18, count 0 2006.210.07:40:09.80#ibcon#about to read 6, iclass 18, count 0 2006.210.07:40:09.80#ibcon#read 6, iclass 18, count 0 2006.210.07:40:09.80#ibcon#end of sib2, iclass 18, count 0 2006.210.07:40:09.80#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:40:09.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:40:09.80#ibcon#[25=USB\r\n] 2006.210.07:40:09.80#ibcon#*before write, iclass 18, count 0 2006.210.07:40:09.80#ibcon#enter sib2, iclass 18, count 0 2006.210.07:40:09.80#ibcon#flushed, iclass 18, count 0 2006.210.07:40:09.80#ibcon#about to write, iclass 18, count 0 2006.210.07:40:09.80#ibcon#wrote, iclass 18, count 0 2006.210.07:40:09.80#ibcon#about to read 3, iclass 18, count 0 2006.210.07:40:09.83#ibcon#read 3, iclass 18, count 0 2006.210.07:40:09.83#ibcon#about to read 4, iclass 18, count 0 2006.210.07:40:09.83#ibcon#read 4, iclass 18, count 0 2006.210.07:40:09.83#ibcon#about to read 5, iclass 18, count 0 2006.210.07:40:09.83#ibcon#read 5, iclass 18, count 0 2006.210.07:40:09.83#ibcon#about to read 6, iclass 18, count 0 2006.210.07:40:09.83#ibcon#read 6, iclass 18, count 0 2006.210.07:40:09.83#ibcon#end of sib2, iclass 18, count 0 2006.210.07:40:09.83#ibcon#*after write, iclass 18, count 0 2006.210.07:40:09.83#ibcon#*before return 0, iclass 18, count 0 2006.210.07:40:09.83#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:40:09.83#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:40:09.83#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:40:09.83#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:40:09.83$vc4f8/valo=8,852.99 2006.210.07:40:09.83#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:40:09.83#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:40:09.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:09.83#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:40:09.83#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:40:09.83#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:40:09.83#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:40:09.83#ibcon#first serial, iclass 20, count 0 2006.210.07:40:09.83#ibcon#enter sib2, iclass 20, count 0 2006.210.07:40:09.83#ibcon#flushed, iclass 20, count 0 2006.210.07:40:09.83#ibcon#about to write, iclass 20, count 0 2006.210.07:40:09.83#ibcon#wrote, iclass 20, count 0 2006.210.07:40:09.83#ibcon#about to read 3, iclass 20, count 0 2006.210.07:40:09.85#ibcon#read 3, iclass 20, count 0 2006.210.07:40:09.85#ibcon#about to read 4, iclass 20, count 0 2006.210.07:40:09.85#ibcon#read 4, iclass 20, count 0 2006.210.07:40:09.85#ibcon#about to read 5, iclass 20, count 0 2006.210.07:40:09.85#ibcon#read 5, iclass 20, count 0 2006.210.07:40:09.85#ibcon#about to read 6, iclass 20, count 0 2006.210.07:40:09.85#ibcon#read 6, iclass 20, count 0 2006.210.07:40:09.85#ibcon#end of sib2, iclass 20, count 0 2006.210.07:40:09.85#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:40:09.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:40:09.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:40:09.85#ibcon#*before write, iclass 20, count 0 2006.210.07:40:09.85#ibcon#enter sib2, iclass 20, count 0 2006.210.07:40:09.85#ibcon#flushed, iclass 20, count 0 2006.210.07:40:09.85#ibcon#about to write, iclass 20, count 0 2006.210.07:40:09.85#ibcon#wrote, iclass 20, count 0 2006.210.07:40:09.85#ibcon#about to read 3, iclass 20, count 0 2006.210.07:40:09.89#ibcon#read 3, iclass 20, count 0 2006.210.07:40:09.89#ibcon#about to read 4, iclass 20, count 0 2006.210.07:40:09.89#ibcon#read 4, iclass 20, count 0 2006.210.07:40:09.89#ibcon#about to read 5, iclass 20, count 0 2006.210.07:40:09.89#ibcon#read 5, iclass 20, count 0 2006.210.07:40:09.89#ibcon#about to read 6, iclass 20, count 0 2006.210.07:40:09.89#ibcon#read 6, iclass 20, count 0 2006.210.07:40:09.89#ibcon#end of sib2, iclass 20, count 0 2006.210.07:40:09.89#ibcon#*after write, iclass 20, count 0 2006.210.07:40:09.89#ibcon#*before return 0, iclass 20, count 0 2006.210.07:40:09.89#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:40:09.89#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:40:09.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:40:09.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:40:09.89$vc4f8/va=8,7 2006.210.07:40:09.89#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:40:09.89#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:40:09.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:09.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:40:09.95#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:40:09.95#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:40:09.95#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:40:09.95#ibcon#first serial, iclass 22, count 2 2006.210.07:40:09.95#ibcon#enter sib2, iclass 22, count 2 2006.210.07:40:09.95#ibcon#flushed, iclass 22, count 2 2006.210.07:40:09.95#ibcon#about to write, iclass 22, count 2 2006.210.07:40:09.95#ibcon#wrote, iclass 22, count 2 2006.210.07:40:09.95#ibcon#about to read 3, iclass 22, count 2 2006.210.07:40:09.97#ibcon#read 3, iclass 22, count 2 2006.210.07:40:09.97#ibcon#about to read 4, iclass 22, count 2 2006.210.07:40:09.97#ibcon#read 4, iclass 22, count 2 2006.210.07:40:09.97#ibcon#about to read 5, iclass 22, count 2 2006.210.07:40:09.97#ibcon#read 5, iclass 22, count 2 2006.210.07:40:09.97#ibcon#about to read 6, iclass 22, count 2 2006.210.07:40:09.97#ibcon#read 6, iclass 22, count 2 2006.210.07:40:09.97#ibcon#end of sib2, iclass 22, count 2 2006.210.07:40:09.97#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:40:09.97#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:40:09.97#ibcon#[25=AT08-07\r\n] 2006.210.07:40:09.97#ibcon#*before write, iclass 22, count 2 2006.210.07:40:09.97#ibcon#enter sib2, iclass 22, count 2 2006.210.07:40:09.97#ibcon#flushed, iclass 22, count 2 2006.210.07:40:09.97#ibcon#about to write, iclass 22, count 2 2006.210.07:40:09.97#ibcon#wrote, iclass 22, count 2 2006.210.07:40:09.97#ibcon#about to read 3, iclass 22, count 2 2006.210.07:40:10.00#ibcon#read 3, iclass 22, count 2 2006.210.07:40:10.00#ibcon#about to read 4, iclass 22, count 2 2006.210.07:40:10.00#ibcon#read 4, iclass 22, count 2 2006.210.07:40:10.00#ibcon#about to read 5, iclass 22, count 2 2006.210.07:40:10.00#ibcon#read 5, iclass 22, count 2 2006.210.07:40:10.00#ibcon#about to read 6, iclass 22, count 2 2006.210.07:40:10.00#ibcon#read 6, iclass 22, count 2 2006.210.07:40:10.00#ibcon#end of sib2, iclass 22, count 2 2006.210.07:40:10.00#ibcon#*after write, iclass 22, count 2 2006.210.07:40:10.00#ibcon#*before return 0, iclass 22, count 2 2006.210.07:40:10.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:40:10.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:40:10.00#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:40:10.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:10.00#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:40:10.12#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:40:10.12#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:40:10.12#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:40:10.12#ibcon#first serial, iclass 22, count 0 2006.210.07:40:10.12#ibcon#enter sib2, iclass 22, count 0 2006.210.07:40:10.12#ibcon#flushed, iclass 22, count 0 2006.210.07:40:10.12#ibcon#about to write, iclass 22, count 0 2006.210.07:40:10.12#ibcon#wrote, iclass 22, count 0 2006.210.07:40:10.12#ibcon#about to read 3, iclass 22, count 0 2006.210.07:40:10.14#ibcon#read 3, iclass 22, count 0 2006.210.07:40:10.14#ibcon#about to read 4, iclass 22, count 0 2006.210.07:40:10.14#ibcon#read 4, iclass 22, count 0 2006.210.07:40:10.14#ibcon#about to read 5, iclass 22, count 0 2006.210.07:40:10.14#ibcon#read 5, iclass 22, count 0 2006.210.07:40:10.14#ibcon#about to read 6, iclass 22, count 0 2006.210.07:40:10.14#ibcon#read 6, iclass 22, count 0 2006.210.07:40:10.14#ibcon#end of sib2, iclass 22, count 0 2006.210.07:40:10.14#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:40:10.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:40:10.14#ibcon#[25=USB\r\n] 2006.210.07:40:10.14#ibcon#*before write, iclass 22, count 0 2006.210.07:40:10.14#ibcon#enter sib2, iclass 22, count 0 2006.210.07:40:10.14#ibcon#flushed, iclass 22, count 0 2006.210.07:40:10.14#ibcon#about to write, iclass 22, count 0 2006.210.07:40:10.14#ibcon#wrote, iclass 22, count 0 2006.210.07:40:10.14#ibcon#about to read 3, iclass 22, count 0 2006.210.07:40:10.17#ibcon#read 3, iclass 22, count 0 2006.210.07:40:10.17#ibcon#about to read 4, iclass 22, count 0 2006.210.07:40:10.17#ibcon#read 4, iclass 22, count 0 2006.210.07:40:10.17#ibcon#about to read 5, iclass 22, count 0 2006.210.07:40:10.17#ibcon#read 5, iclass 22, count 0 2006.210.07:40:10.17#ibcon#about to read 6, iclass 22, count 0 2006.210.07:40:10.17#ibcon#read 6, iclass 22, count 0 2006.210.07:40:10.17#ibcon#end of sib2, iclass 22, count 0 2006.210.07:40:10.17#ibcon#*after write, iclass 22, count 0 2006.210.07:40:10.17#ibcon#*before return 0, iclass 22, count 0 2006.210.07:40:10.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:40:10.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:40:10.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:40:10.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:40:10.17$vc4f8/vblo=1,632.99 2006.210.07:40:10.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:40:10.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:40:10.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:10.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:40:10.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:40:10.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:40:10.17#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:40:10.17#ibcon#first serial, iclass 24, count 0 2006.210.07:40:10.17#ibcon#enter sib2, iclass 24, count 0 2006.210.07:40:10.17#ibcon#flushed, iclass 24, count 0 2006.210.07:40:10.17#ibcon#about to write, iclass 24, count 0 2006.210.07:40:10.17#ibcon#wrote, iclass 24, count 0 2006.210.07:40:10.17#ibcon#about to read 3, iclass 24, count 0 2006.210.07:40:10.19#ibcon#read 3, iclass 24, count 0 2006.210.07:40:10.19#ibcon#about to read 4, iclass 24, count 0 2006.210.07:40:10.19#ibcon#read 4, iclass 24, count 0 2006.210.07:40:10.19#ibcon#about to read 5, iclass 24, count 0 2006.210.07:40:10.19#ibcon#read 5, iclass 24, count 0 2006.210.07:40:10.19#ibcon#about to read 6, iclass 24, count 0 2006.210.07:40:10.19#ibcon#read 6, iclass 24, count 0 2006.210.07:40:10.19#ibcon#end of sib2, iclass 24, count 0 2006.210.07:40:10.19#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:40:10.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:40:10.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:40:10.19#ibcon#*before write, iclass 24, count 0 2006.210.07:40:10.19#ibcon#enter sib2, iclass 24, count 0 2006.210.07:40:10.19#ibcon#flushed, iclass 24, count 0 2006.210.07:40:10.19#ibcon#about to write, iclass 24, count 0 2006.210.07:40:10.19#ibcon#wrote, iclass 24, count 0 2006.210.07:40:10.19#ibcon#about to read 3, iclass 24, count 0 2006.210.07:40:10.23#ibcon#read 3, iclass 24, count 0 2006.210.07:40:10.23#ibcon#about to read 4, iclass 24, count 0 2006.210.07:40:10.23#ibcon#read 4, iclass 24, count 0 2006.210.07:40:10.23#ibcon#about to read 5, iclass 24, count 0 2006.210.07:40:10.23#ibcon#read 5, iclass 24, count 0 2006.210.07:40:10.23#ibcon#about to read 6, iclass 24, count 0 2006.210.07:40:10.23#ibcon#read 6, iclass 24, count 0 2006.210.07:40:10.23#ibcon#end of sib2, iclass 24, count 0 2006.210.07:40:10.23#ibcon#*after write, iclass 24, count 0 2006.210.07:40:10.23#ibcon#*before return 0, iclass 24, count 0 2006.210.07:40:10.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:40:10.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:40:10.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:40:10.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:40:10.23$vc4f8/vb=1,4 2006.210.07:40:10.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:40:10.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:40:10.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:10.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:40:10.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:40:10.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:40:10.23#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:40:10.23#ibcon#first serial, iclass 26, count 2 2006.210.07:40:10.23#ibcon#enter sib2, iclass 26, count 2 2006.210.07:40:10.23#ibcon#flushed, iclass 26, count 2 2006.210.07:40:10.23#ibcon#about to write, iclass 26, count 2 2006.210.07:40:10.23#ibcon#wrote, iclass 26, count 2 2006.210.07:40:10.23#ibcon#about to read 3, iclass 26, count 2 2006.210.07:40:10.25#ibcon#read 3, iclass 26, count 2 2006.210.07:40:10.25#ibcon#about to read 4, iclass 26, count 2 2006.210.07:40:10.25#ibcon#read 4, iclass 26, count 2 2006.210.07:40:10.25#ibcon#about to read 5, iclass 26, count 2 2006.210.07:40:10.25#ibcon#read 5, iclass 26, count 2 2006.210.07:40:10.25#ibcon#about to read 6, iclass 26, count 2 2006.210.07:40:10.25#ibcon#read 6, iclass 26, count 2 2006.210.07:40:10.25#ibcon#end of sib2, iclass 26, count 2 2006.210.07:40:10.25#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:40:10.25#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:40:10.25#ibcon#[27=AT01-04\r\n] 2006.210.07:40:10.25#ibcon#*before write, iclass 26, count 2 2006.210.07:40:10.25#ibcon#enter sib2, iclass 26, count 2 2006.210.07:40:10.25#ibcon#flushed, iclass 26, count 2 2006.210.07:40:10.25#ibcon#about to write, iclass 26, count 2 2006.210.07:40:10.25#ibcon#wrote, iclass 26, count 2 2006.210.07:40:10.25#ibcon#about to read 3, iclass 26, count 2 2006.210.07:40:10.28#ibcon#read 3, iclass 26, count 2 2006.210.07:40:10.28#ibcon#about to read 4, iclass 26, count 2 2006.210.07:40:10.28#ibcon#read 4, iclass 26, count 2 2006.210.07:40:10.28#ibcon#about to read 5, iclass 26, count 2 2006.210.07:40:10.28#ibcon#read 5, iclass 26, count 2 2006.210.07:40:10.28#ibcon#about to read 6, iclass 26, count 2 2006.210.07:40:10.28#ibcon#read 6, iclass 26, count 2 2006.210.07:40:10.28#ibcon#end of sib2, iclass 26, count 2 2006.210.07:40:10.28#ibcon#*after write, iclass 26, count 2 2006.210.07:40:10.28#ibcon#*before return 0, iclass 26, count 2 2006.210.07:40:10.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:40:10.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:40:10.28#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:40:10.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:10.28#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:40:10.40#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:40:10.40#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:40:10.40#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:40:10.40#ibcon#first serial, iclass 26, count 0 2006.210.07:40:10.40#ibcon#enter sib2, iclass 26, count 0 2006.210.07:40:10.40#ibcon#flushed, iclass 26, count 0 2006.210.07:40:10.40#ibcon#about to write, iclass 26, count 0 2006.210.07:40:10.40#ibcon#wrote, iclass 26, count 0 2006.210.07:40:10.40#ibcon#about to read 3, iclass 26, count 0 2006.210.07:40:10.42#ibcon#read 3, iclass 26, count 0 2006.210.07:40:10.42#ibcon#about to read 4, iclass 26, count 0 2006.210.07:40:10.42#ibcon#read 4, iclass 26, count 0 2006.210.07:40:10.42#ibcon#about to read 5, iclass 26, count 0 2006.210.07:40:10.42#ibcon#read 5, iclass 26, count 0 2006.210.07:40:10.42#ibcon#about to read 6, iclass 26, count 0 2006.210.07:40:10.42#ibcon#read 6, iclass 26, count 0 2006.210.07:40:10.42#ibcon#end of sib2, iclass 26, count 0 2006.210.07:40:10.42#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:40:10.42#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:40:10.42#ibcon#[27=USB\r\n] 2006.210.07:40:10.42#ibcon#*before write, iclass 26, count 0 2006.210.07:40:10.42#ibcon#enter sib2, iclass 26, count 0 2006.210.07:40:10.42#ibcon#flushed, iclass 26, count 0 2006.210.07:40:10.42#ibcon#about to write, iclass 26, count 0 2006.210.07:40:10.42#ibcon#wrote, iclass 26, count 0 2006.210.07:40:10.42#ibcon#about to read 3, iclass 26, count 0 2006.210.07:40:10.45#ibcon#read 3, iclass 26, count 0 2006.210.07:40:10.45#ibcon#about to read 4, iclass 26, count 0 2006.210.07:40:10.45#ibcon#read 4, iclass 26, count 0 2006.210.07:40:10.45#ibcon#about to read 5, iclass 26, count 0 2006.210.07:40:10.45#ibcon#read 5, iclass 26, count 0 2006.210.07:40:10.45#ibcon#about to read 6, iclass 26, count 0 2006.210.07:40:10.45#ibcon#read 6, iclass 26, count 0 2006.210.07:40:10.45#ibcon#end of sib2, iclass 26, count 0 2006.210.07:40:10.45#ibcon#*after write, iclass 26, count 0 2006.210.07:40:10.45#ibcon#*before return 0, iclass 26, count 0 2006.210.07:40:10.45#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:40:10.45#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:40:10.45#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:40:10.45#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:40:10.45$vc4f8/vblo=2,640.99 2006.210.07:40:10.45#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:40:10.45#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:40:10.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:10.45#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:10.45#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:10.45#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:10.45#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:40:10.45#ibcon#first serial, iclass 28, count 0 2006.210.07:40:10.45#ibcon#enter sib2, iclass 28, count 0 2006.210.07:40:10.45#ibcon#flushed, iclass 28, count 0 2006.210.07:40:10.45#ibcon#about to write, iclass 28, count 0 2006.210.07:40:10.45#ibcon#wrote, iclass 28, count 0 2006.210.07:40:10.45#ibcon#about to read 3, iclass 28, count 0 2006.210.07:40:10.47#ibcon#read 3, iclass 28, count 0 2006.210.07:40:10.47#ibcon#about to read 4, iclass 28, count 0 2006.210.07:40:10.47#ibcon#read 4, iclass 28, count 0 2006.210.07:40:10.47#ibcon#about to read 5, iclass 28, count 0 2006.210.07:40:10.47#ibcon#read 5, iclass 28, count 0 2006.210.07:40:10.47#ibcon#about to read 6, iclass 28, count 0 2006.210.07:40:10.47#ibcon#read 6, iclass 28, count 0 2006.210.07:40:10.47#ibcon#end of sib2, iclass 28, count 0 2006.210.07:40:10.47#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:40:10.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:40:10.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:40:10.47#ibcon#*before write, iclass 28, count 0 2006.210.07:40:10.47#ibcon#enter sib2, iclass 28, count 0 2006.210.07:40:10.47#ibcon#flushed, iclass 28, count 0 2006.210.07:40:10.47#ibcon#about to write, iclass 28, count 0 2006.210.07:40:10.47#ibcon#wrote, iclass 28, count 0 2006.210.07:40:10.47#ibcon#about to read 3, iclass 28, count 0 2006.210.07:40:10.51#ibcon#read 3, iclass 28, count 0 2006.210.07:40:10.51#ibcon#about to read 4, iclass 28, count 0 2006.210.07:40:10.51#ibcon#read 4, iclass 28, count 0 2006.210.07:40:10.51#ibcon#about to read 5, iclass 28, count 0 2006.210.07:40:10.51#ibcon#read 5, iclass 28, count 0 2006.210.07:40:10.51#ibcon#about to read 6, iclass 28, count 0 2006.210.07:40:10.51#ibcon#read 6, iclass 28, count 0 2006.210.07:40:10.51#ibcon#end of sib2, iclass 28, count 0 2006.210.07:40:10.51#ibcon#*after write, iclass 28, count 0 2006.210.07:40:10.51#ibcon#*before return 0, iclass 28, count 0 2006.210.07:40:10.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:10.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:40:10.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:40:10.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:40:10.51$vc4f8/vb=2,4 2006.210.07:40:10.51#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:40:10.51#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:40:10.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:10.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:10.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:10.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:10.57#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:40:10.57#ibcon#first serial, iclass 30, count 2 2006.210.07:40:10.57#ibcon#enter sib2, iclass 30, count 2 2006.210.07:40:10.57#ibcon#flushed, iclass 30, count 2 2006.210.07:40:10.57#ibcon#about to write, iclass 30, count 2 2006.210.07:40:10.57#ibcon#wrote, iclass 30, count 2 2006.210.07:40:10.57#ibcon#about to read 3, iclass 30, count 2 2006.210.07:40:10.59#ibcon#read 3, iclass 30, count 2 2006.210.07:40:10.59#ibcon#about to read 4, iclass 30, count 2 2006.210.07:40:10.59#ibcon#read 4, iclass 30, count 2 2006.210.07:40:10.59#ibcon#about to read 5, iclass 30, count 2 2006.210.07:40:10.59#ibcon#read 5, iclass 30, count 2 2006.210.07:40:10.59#ibcon#about to read 6, iclass 30, count 2 2006.210.07:40:10.59#ibcon#read 6, iclass 30, count 2 2006.210.07:40:10.59#ibcon#end of sib2, iclass 30, count 2 2006.210.07:40:10.59#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:40:10.59#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:40:10.59#ibcon#[27=AT02-04\r\n] 2006.210.07:40:10.59#ibcon#*before write, iclass 30, count 2 2006.210.07:40:10.59#ibcon#enter sib2, iclass 30, count 2 2006.210.07:40:10.59#ibcon#flushed, iclass 30, count 2 2006.210.07:40:10.59#ibcon#about to write, iclass 30, count 2 2006.210.07:40:10.59#ibcon#wrote, iclass 30, count 2 2006.210.07:40:10.59#ibcon#about to read 3, iclass 30, count 2 2006.210.07:40:10.62#ibcon#read 3, iclass 30, count 2 2006.210.07:40:10.62#ibcon#about to read 4, iclass 30, count 2 2006.210.07:40:10.62#ibcon#read 4, iclass 30, count 2 2006.210.07:40:10.62#ibcon#about to read 5, iclass 30, count 2 2006.210.07:40:10.62#ibcon#read 5, iclass 30, count 2 2006.210.07:40:10.62#ibcon#about to read 6, iclass 30, count 2 2006.210.07:40:10.62#ibcon#read 6, iclass 30, count 2 2006.210.07:40:10.62#ibcon#end of sib2, iclass 30, count 2 2006.210.07:40:10.62#ibcon#*after write, iclass 30, count 2 2006.210.07:40:10.62#ibcon#*before return 0, iclass 30, count 2 2006.210.07:40:10.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:10.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:40:10.62#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:40:10.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:10.62#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:10.74#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:10.74#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:10.74#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:40:10.74#ibcon#first serial, iclass 30, count 0 2006.210.07:40:10.74#ibcon#enter sib2, iclass 30, count 0 2006.210.07:40:10.74#ibcon#flushed, iclass 30, count 0 2006.210.07:40:10.74#ibcon#about to write, iclass 30, count 0 2006.210.07:40:10.74#ibcon#wrote, iclass 30, count 0 2006.210.07:40:10.74#ibcon#about to read 3, iclass 30, count 0 2006.210.07:40:10.76#ibcon#read 3, iclass 30, count 0 2006.210.07:40:10.76#ibcon#about to read 4, iclass 30, count 0 2006.210.07:40:10.76#ibcon#read 4, iclass 30, count 0 2006.210.07:40:10.76#ibcon#about to read 5, iclass 30, count 0 2006.210.07:40:10.76#ibcon#read 5, iclass 30, count 0 2006.210.07:40:10.76#ibcon#about to read 6, iclass 30, count 0 2006.210.07:40:10.76#ibcon#read 6, iclass 30, count 0 2006.210.07:40:10.76#ibcon#end of sib2, iclass 30, count 0 2006.210.07:40:10.76#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:40:10.76#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:40:10.76#ibcon#[27=USB\r\n] 2006.210.07:40:10.76#ibcon#*before write, iclass 30, count 0 2006.210.07:40:10.76#ibcon#enter sib2, iclass 30, count 0 2006.210.07:40:10.76#ibcon#flushed, iclass 30, count 0 2006.210.07:40:10.76#ibcon#about to write, iclass 30, count 0 2006.210.07:40:10.76#ibcon#wrote, iclass 30, count 0 2006.210.07:40:10.76#ibcon#about to read 3, iclass 30, count 0 2006.210.07:40:10.79#ibcon#read 3, iclass 30, count 0 2006.210.07:40:10.79#ibcon#about to read 4, iclass 30, count 0 2006.210.07:40:10.79#ibcon#read 4, iclass 30, count 0 2006.210.07:40:10.79#ibcon#about to read 5, iclass 30, count 0 2006.210.07:40:10.79#ibcon#read 5, iclass 30, count 0 2006.210.07:40:10.79#ibcon#about to read 6, iclass 30, count 0 2006.210.07:40:10.79#ibcon#read 6, iclass 30, count 0 2006.210.07:40:10.79#ibcon#end of sib2, iclass 30, count 0 2006.210.07:40:10.79#ibcon#*after write, iclass 30, count 0 2006.210.07:40:10.79#ibcon#*before return 0, iclass 30, count 0 2006.210.07:40:10.79#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:10.79#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:40:10.79#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:40:10.79#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:40:10.79$vc4f8/vblo=3,656.99 2006.210.07:40:10.79#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:40:10.79#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:40:10.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:10.79#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:10.79#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:10.79#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:10.79#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:40:10.79#ibcon#first serial, iclass 32, count 0 2006.210.07:40:10.79#ibcon#enter sib2, iclass 32, count 0 2006.210.07:40:10.79#ibcon#flushed, iclass 32, count 0 2006.210.07:40:10.79#ibcon#about to write, iclass 32, count 0 2006.210.07:40:10.79#ibcon#wrote, iclass 32, count 0 2006.210.07:40:10.79#ibcon#about to read 3, iclass 32, count 0 2006.210.07:40:10.81#ibcon#read 3, iclass 32, count 0 2006.210.07:40:10.81#ibcon#about to read 4, iclass 32, count 0 2006.210.07:40:10.81#ibcon#read 4, iclass 32, count 0 2006.210.07:40:10.81#ibcon#about to read 5, iclass 32, count 0 2006.210.07:40:10.81#ibcon#read 5, iclass 32, count 0 2006.210.07:40:10.81#ibcon#about to read 6, iclass 32, count 0 2006.210.07:40:10.81#ibcon#read 6, iclass 32, count 0 2006.210.07:40:10.81#ibcon#end of sib2, iclass 32, count 0 2006.210.07:40:10.81#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:40:10.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:40:10.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:40:10.81#ibcon#*before write, iclass 32, count 0 2006.210.07:40:10.81#ibcon#enter sib2, iclass 32, count 0 2006.210.07:40:10.81#ibcon#flushed, iclass 32, count 0 2006.210.07:40:10.81#ibcon#about to write, iclass 32, count 0 2006.210.07:40:10.81#ibcon#wrote, iclass 32, count 0 2006.210.07:40:10.81#ibcon#about to read 3, iclass 32, count 0 2006.210.07:40:10.85#ibcon#read 3, iclass 32, count 0 2006.210.07:40:10.85#ibcon#about to read 4, iclass 32, count 0 2006.210.07:40:10.85#ibcon#read 4, iclass 32, count 0 2006.210.07:40:10.85#ibcon#about to read 5, iclass 32, count 0 2006.210.07:40:10.85#ibcon#read 5, iclass 32, count 0 2006.210.07:40:10.85#ibcon#about to read 6, iclass 32, count 0 2006.210.07:40:10.85#ibcon#read 6, iclass 32, count 0 2006.210.07:40:10.85#ibcon#end of sib2, iclass 32, count 0 2006.210.07:40:10.85#ibcon#*after write, iclass 32, count 0 2006.210.07:40:10.85#ibcon#*before return 0, iclass 32, count 0 2006.210.07:40:10.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:10.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:40:10.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:40:10.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:40:10.85$vc4f8/vb=3,3 2006.210.07:40:10.85#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:40:10.85#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:40:10.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:10.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:10.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:10.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:10.91#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:40:10.91#ibcon#first serial, iclass 34, count 2 2006.210.07:40:10.91#ibcon#enter sib2, iclass 34, count 2 2006.210.07:40:10.91#ibcon#flushed, iclass 34, count 2 2006.210.07:40:10.91#ibcon#about to write, iclass 34, count 2 2006.210.07:40:10.91#ibcon#wrote, iclass 34, count 2 2006.210.07:40:10.91#ibcon#about to read 3, iclass 34, count 2 2006.210.07:40:10.93#ibcon#read 3, iclass 34, count 2 2006.210.07:40:10.93#ibcon#about to read 4, iclass 34, count 2 2006.210.07:40:10.93#ibcon#read 4, iclass 34, count 2 2006.210.07:40:10.93#ibcon#about to read 5, iclass 34, count 2 2006.210.07:40:10.93#ibcon#read 5, iclass 34, count 2 2006.210.07:40:10.93#ibcon#about to read 6, iclass 34, count 2 2006.210.07:40:10.93#ibcon#read 6, iclass 34, count 2 2006.210.07:40:10.93#ibcon#end of sib2, iclass 34, count 2 2006.210.07:40:10.93#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:40:10.93#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:40:10.93#ibcon#[27=AT03-03\r\n] 2006.210.07:40:10.93#ibcon#*before write, iclass 34, count 2 2006.210.07:40:10.93#ibcon#enter sib2, iclass 34, count 2 2006.210.07:40:10.93#ibcon#flushed, iclass 34, count 2 2006.210.07:40:10.93#ibcon#about to write, iclass 34, count 2 2006.210.07:40:10.93#ibcon#wrote, iclass 34, count 2 2006.210.07:40:10.93#ibcon#about to read 3, iclass 34, count 2 2006.210.07:40:10.96#ibcon#read 3, iclass 34, count 2 2006.210.07:40:10.96#ibcon#about to read 4, iclass 34, count 2 2006.210.07:40:10.96#ibcon#read 4, iclass 34, count 2 2006.210.07:40:10.96#ibcon#about to read 5, iclass 34, count 2 2006.210.07:40:10.96#ibcon#read 5, iclass 34, count 2 2006.210.07:40:10.96#ibcon#about to read 6, iclass 34, count 2 2006.210.07:40:10.96#ibcon#read 6, iclass 34, count 2 2006.210.07:40:10.96#ibcon#end of sib2, iclass 34, count 2 2006.210.07:40:10.96#ibcon#*after write, iclass 34, count 2 2006.210.07:40:10.96#ibcon#*before return 0, iclass 34, count 2 2006.210.07:40:10.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:10.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:40:10.96#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:40:10.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:10.96#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:11.08#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:11.08#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:11.08#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:40:11.08#ibcon#first serial, iclass 34, count 0 2006.210.07:40:11.08#ibcon#enter sib2, iclass 34, count 0 2006.210.07:40:11.08#ibcon#flushed, iclass 34, count 0 2006.210.07:40:11.08#ibcon#about to write, iclass 34, count 0 2006.210.07:40:11.08#ibcon#wrote, iclass 34, count 0 2006.210.07:40:11.08#ibcon#about to read 3, iclass 34, count 0 2006.210.07:40:11.10#ibcon#read 3, iclass 34, count 0 2006.210.07:40:11.10#ibcon#about to read 4, iclass 34, count 0 2006.210.07:40:11.10#ibcon#read 4, iclass 34, count 0 2006.210.07:40:11.10#ibcon#about to read 5, iclass 34, count 0 2006.210.07:40:11.10#ibcon#read 5, iclass 34, count 0 2006.210.07:40:11.10#ibcon#about to read 6, iclass 34, count 0 2006.210.07:40:11.10#ibcon#read 6, iclass 34, count 0 2006.210.07:40:11.10#ibcon#end of sib2, iclass 34, count 0 2006.210.07:40:11.10#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:40:11.10#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:40:11.10#ibcon#[27=USB\r\n] 2006.210.07:40:11.10#ibcon#*before write, iclass 34, count 0 2006.210.07:40:11.10#ibcon#enter sib2, iclass 34, count 0 2006.210.07:40:11.10#ibcon#flushed, iclass 34, count 0 2006.210.07:40:11.10#ibcon#about to write, iclass 34, count 0 2006.210.07:40:11.10#ibcon#wrote, iclass 34, count 0 2006.210.07:40:11.10#ibcon#about to read 3, iclass 34, count 0 2006.210.07:40:11.13#ibcon#read 3, iclass 34, count 0 2006.210.07:40:11.13#ibcon#about to read 4, iclass 34, count 0 2006.210.07:40:11.13#ibcon#read 4, iclass 34, count 0 2006.210.07:40:11.13#ibcon#about to read 5, iclass 34, count 0 2006.210.07:40:11.13#ibcon#read 5, iclass 34, count 0 2006.210.07:40:11.13#ibcon#about to read 6, iclass 34, count 0 2006.210.07:40:11.13#ibcon#read 6, iclass 34, count 0 2006.210.07:40:11.13#ibcon#end of sib2, iclass 34, count 0 2006.210.07:40:11.13#ibcon#*after write, iclass 34, count 0 2006.210.07:40:11.13#ibcon#*before return 0, iclass 34, count 0 2006.210.07:40:11.13#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:11.13#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:40:11.13#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:40:11.13#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:40:11.13$vc4f8/vblo=4,712.99 2006.210.07:40:11.13#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:40:11.13#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:40:11.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:11.13#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:11.13#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:11.13#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:11.13#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:40:11.13#ibcon#first serial, iclass 36, count 0 2006.210.07:40:11.13#ibcon#enter sib2, iclass 36, count 0 2006.210.07:40:11.13#ibcon#flushed, iclass 36, count 0 2006.210.07:40:11.13#ibcon#about to write, iclass 36, count 0 2006.210.07:40:11.13#ibcon#wrote, iclass 36, count 0 2006.210.07:40:11.13#ibcon#about to read 3, iclass 36, count 0 2006.210.07:40:11.15#ibcon#read 3, iclass 36, count 0 2006.210.07:40:11.15#ibcon#about to read 4, iclass 36, count 0 2006.210.07:40:11.15#ibcon#read 4, iclass 36, count 0 2006.210.07:40:11.15#ibcon#about to read 5, iclass 36, count 0 2006.210.07:40:11.15#ibcon#read 5, iclass 36, count 0 2006.210.07:40:11.15#ibcon#about to read 6, iclass 36, count 0 2006.210.07:40:11.15#ibcon#read 6, iclass 36, count 0 2006.210.07:40:11.15#ibcon#end of sib2, iclass 36, count 0 2006.210.07:40:11.15#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:40:11.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:40:11.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:40:11.15#ibcon#*before write, iclass 36, count 0 2006.210.07:40:11.15#ibcon#enter sib2, iclass 36, count 0 2006.210.07:40:11.15#ibcon#flushed, iclass 36, count 0 2006.210.07:40:11.15#ibcon#about to write, iclass 36, count 0 2006.210.07:40:11.15#ibcon#wrote, iclass 36, count 0 2006.210.07:40:11.15#ibcon#about to read 3, iclass 36, count 0 2006.210.07:40:11.19#ibcon#read 3, iclass 36, count 0 2006.210.07:40:11.19#ibcon#about to read 4, iclass 36, count 0 2006.210.07:40:11.19#ibcon#read 4, iclass 36, count 0 2006.210.07:40:11.19#ibcon#about to read 5, iclass 36, count 0 2006.210.07:40:11.19#ibcon#read 5, iclass 36, count 0 2006.210.07:40:11.19#ibcon#about to read 6, iclass 36, count 0 2006.210.07:40:11.19#ibcon#read 6, iclass 36, count 0 2006.210.07:40:11.19#ibcon#end of sib2, iclass 36, count 0 2006.210.07:40:11.19#ibcon#*after write, iclass 36, count 0 2006.210.07:40:11.19#ibcon#*before return 0, iclass 36, count 0 2006.210.07:40:11.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:11.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:40:11.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:40:11.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:40:11.19$vc4f8/vb=4,3 2006.210.07:40:11.19#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:40:11.19#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:40:11.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:11.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:11.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:11.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:11.25#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:40:11.25#ibcon#first serial, iclass 38, count 2 2006.210.07:40:11.25#ibcon#enter sib2, iclass 38, count 2 2006.210.07:40:11.25#ibcon#flushed, iclass 38, count 2 2006.210.07:40:11.25#ibcon#about to write, iclass 38, count 2 2006.210.07:40:11.25#ibcon#wrote, iclass 38, count 2 2006.210.07:40:11.25#ibcon#about to read 3, iclass 38, count 2 2006.210.07:40:11.27#ibcon#read 3, iclass 38, count 2 2006.210.07:40:11.27#ibcon#about to read 4, iclass 38, count 2 2006.210.07:40:11.27#ibcon#read 4, iclass 38, count 2 2006.210.07:40:11.27#ibcon#about to read 5, iclass 38, count 2 2006.210.07:40:11.27#ibcon#read 5, iclass 38, count 2 2006.210.07:40:11.27#ibcon#about to read 6, iclass 38, count 2 2006.210.07:40:11.27#ibcon#read 6, iclass 38, count 2 2006.210.07:40:11.27#ibcon#end of sib2, iclass 38, count 2 2006.210.07:40:11.27#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:40:11.27#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:40:11.27#ibcon#[27=AT04-03\r\n] 2006.210.07:40:11.27#ibcon#*before write, iclass 38, count 2 2006.210.07:40:11.27#ibcon#enter sib2, iclass 38, count 2 2006.210.07:40:11.27#ibcon#flushed, iclass 38, count 2 2006.210.07:40:11.27#ibcon#about to write, iclass 38, count 2 2006.210.07:40:11.27#ibcon#wrote, iclass 38, count 2 2006.210.07:40:11.27#ibcon#about to read 3, iclass 38, count 2 2006.210.07:40:11.30#ibcon#read 3, iclass 38, count 2 2006.210.07:40:11.30#ibcon#about to read 4, iclass 38, count 2 2006.210.07:40:11.30#ibcon#read 4, iclass 38, count 2 2006.210.07:40:11.30#ibcon#about to read 5, iclass 38, count 2 2006.210.07:40:11.30#ibcon#read 5, iclass 38, count 2 2006.210.07:40:11.30#ibcon#about to read 6, iclass 38, count 2 2006.210.07:40:11.30#ibcon#read 6, iclass 38, count 2 2006.210.07:40:11.30#ibcon#end of sib2, iclass 38, count 2 2006.210.07:40:11.30#ibcon#*after write, iclass 38, count 2 2006.210.07:40:11.30#ibcon#*before return 0, iclass 38, count 2 2006.210.07:40:11.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:11.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:40:11.30#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:40:11.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:11.30#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:11.42#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:11.42#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:11.42#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:40:11.42#ibcon#first serial, iclass 38, count 0 2006.210.07:40:11.42#ibcon#enter sib2, iclass 38, count 0 2006.210.07:40:11.42#ibcon#flushed, iclass 38, count 0 2006.210.07:40:11.42#ibcon#about to write, iclass 38, count 0 2006.210.07:40:11.42#ibcon#wrote, iclass 38, count 0 2006.210.07:40:11.42#ibcon#about to read 3, iclass 38, count 0 2006.210.07:40:11.44#ibcon#read 3, iclass 38, count 0 2006.210.07:40:11.44#ibcon#about to read 4, iclass 38, count 0 2006.210.07:40:11.44#ibcon#read 4, iclass 38, count 0 2006.210.07:40:11.44#ibcon#about to read 5, iclass 38, count 0 2006.210.07:40:11.44#ibcon#read 5, iclass 38, count 0 2006.210.07:40:11.44#ibcon#about to read 6, iclass 38, count 0 2006.210.07:40:11.44#ibcon#read 6, iclass 38, count 0 2006.210.07:40:11.44#ibcon#end of sib2, iclass 38, count 0 2006.210.07:40:11.44#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:40:11.44#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:40:11.44#ibcon#[27=USB\r\n] 2006.210.07:40:11.44#ibcon#*before write, iclass 38, count 0 2006.210.07:40:11.44#ibcon#enter sib2, iclass 38, count 0 2006.210.07:40:11.44#ibcon#flushed, iclass 38, count 0 2006.210.07:40:11.44#ibcon#about to write, iclass 38, count 0 2006.210.07:40:11.44#ibcon#wrote, iclass 38, count 0 2006.210.07:40:11.44#ibcon#about to read 3, iclass 38, count 0 2006.210.07:40:11.47#ibcon#read 3, iclass 38, count 0 2006.210.07:40:11.47#ibcon#about to read 4, iclass 38, count 0 2006.210.07:40:11.47#ibcon#read 4, iclass 38, count 0 2006.210.07:40:11.47#ibcon#about to read 5, iclass 38, count 0 2006.210.07:40:11.47#ibcon#read 5, iclass 38, count 0 2006.210.07:40:11.47#ibcon#about to read 6, iclass 38, count 0 2006.210.07:40:11.47#ibcon#read 6, iclass 38, count 0 2006.210.07:40:11.47#ibcon#end of sib2, iclass 38, count 0 2006.210.07:40:11.47#ibcon#*after write, iclass 38, count 0 2006.210.07:40:11.47#ibcon#*before return 0, iclass 38, count 0 2006.210.07:40:11.47#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:11.47#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:40:11.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:40:11.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:40:11.47$vc4f8/vblo=5,744.99 2006.210.07:40:11.47#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:40:11.47#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:40:11.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:11.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:11.47#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:11.47#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:11.47#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:40:11.47#ibcon#first serial, iclass 40, count 0 2006.210.07:40:11.47#ibcon#enter sib2, iclass 40, count 0 2006.210.07:40:11.47#ibcon#flushed, iclass 40, count 0 2006.210.07:40:11.47#ibcon#about to write, iclass 40, count 0 2006.210.07:40:11.47#ibcon#wrote, iclass 40, count 0 2006.210.07:40:11.47#ibcon#about to read 3, iclass 40, count 0 2006.210.07:40:11.49#ibcon#read 3, iclass 40, count 0 2006.210.07:40:11.49#ibcon#about to read 4, iclass 40, count 0 2006.210.07:40:11.49#ibcon#read 4, iclass 40, count 0 2006.210.07:40:11.49#ibcon#about to read 5, iclass 40, count 0 2006.210.07:40:11.49#ibcon#read 5, iclass 40, count 0 2006.210.07:40:11.49#ibcon#about to read 6, iclass 40, count 0 2006.210.07:40:11.49#ibcon#read 6, iclass 40, count 0 2006.210.07:40:11.49#ibcon#end of sib2, iclass 40, count 0 2006.210.07:40:11.49#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:40:11.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:40:11.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:40:11.49#ibcon#*before write, iclass 40, count 0 2006.210.07:40:11.49#ibcon#enter sib2, iclass 40, count 0 2006.210.07:40:11.49#ibcon#flushed, iclass 40, count 0 2006.210.07:40:11.49#ibcon#about to write, iclass 40, count 0 2006.210.07:40:11.49#ibcon#wrote, iclass 40, count 0 2006.210.07:40:11.49#ibcon#about to read 3, iclass 40, count 0 2006.210.07:40:11.53#ibcon#read 3, iclass 40, count 0 2006.210.07:40:11.53#ibcon#about to read 4, iclass 40, count 0 2006.210.07:40:11.53#ibcon#read 4, iclass 40, count 0 2006.210.07:40:11.53#ibcon#about to read 5, iclass 40, count 0 2006.210.07:40:11.53#ibcon#read 5, iclass 40, count 0 2006.210.07:40:11.53#ibcon#about to read 6, iclass 40, count 0 2006.210.07:40:11.53#ibcon#read 6, iclass 40, count 0 2006.210.07:40:11.53#ibcon#end of sib2, iclass 40, count 0 2006.210.07:40:11.53#ibcon#*after write, iclass 40, count 0 2006.210.07:40:11.53#ibcon#*before return 0, iclass 40, count 0 2006.210.07:40:11.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:11.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:40:11.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:40:11.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:40:11.53$vc4f8/vb=5,3 2006.210.07:40:11.53#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:40:11.53#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:40:11.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:11.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:11.59#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:11.59#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:11.59#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:40:11.59#ibcon#first serial, iclass 4, count 2 2006.210.07:40:11.59#ibcon#enter sib2, iclass 4, count 2 2006.210.07:40:11.59#ibcon#flushed, iclass 4, count 2 2006.210.07:40:11.59#ibcon#about to write, iclass 4, count 2 2006.210.07:40:11.59#ibcon#wrote, iclass 4, count 2 2006.210.07:40:11.59#ibcon#about to read 3, iclass 4, count 2 2006.210.07:40:11.61#ibcon#read 3, iclass 4, count 2 2006.210.07:40:11.61#ibcon#about to read 4, iclass 4, count 2 2006.210.07:40:11.61#ibcon#read 4, iclass 4, count 2 2006.210.07:40:11.61#ibcon#about to read 5, iclass 4, count 2 2006.210.07:40:11.61#ibcon#read 5, iclass 4, count 2 2006.210.07:40:11.61#ibcon#about to read 6, iclass 4, count 2 2006.210.07:40:11.61#ibcon#read 6, iclass 4, count 2 2006.210.07:40:11.61#ibcon#end of sib2, iclass 4, count 2 2006.210.07:40:11.61#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:40:11.61#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:40:11.61#ibcon#[27=AT05-03\r\n] 2006.210.07:40:11.61#ibcon#*before write, iclass 4, count 2 2006.210.07:40:11.61#ibcon#enter sib2, iclass 4, count 2 2006.210.07:40:11.61#ibcon#flushed, iclass 4, count 2 2006.210.07:40:11.61#ibcon#about to write, iclass 4, count 2 2006.210.07:40:11.61#ibcon#wrote, iclass 4, count 2 2006.210.07:40:11.61#ibcon#about to read 3, iclass 4, count 2 2006.210.07:40:11.64#ibcon#read 3, iclass 4, count 2 2006.210.07:40:11.64#ibcon#about to read 4, iclass 4, count 2 2006.210.07:40:11.64#ibcon#read 4, iclass 4, count 2 2006.210.07:40:11.64#ibcon#about to read 5, iclass 4, count 2 2006.210.07:40:11.64#ibcon#read 5, iclass 4, count 2 2006.210.07:40:11.64#ibcon#about to read 6, iclass 4, count 2 2006.210.07:40:11.64#ibcon#read 6, iclass 4, count 2 2006.210.07:40:11.64#ibcon#end of sib2, iclass 4, count 2 2006.210.07:40:11.64#ibcon#*after write, iclass 4, count 2 2006.210.07:40:11.64#ibcon#*before return 0, iclass 4, count 2 2006.210.07:40:11.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:11.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:40:11.64#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:40:11.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:11.64#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:11.76#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:11.76#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:11.76#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:40:11.76#ibcon#first serial, iclass 4, count 0 2006.210.07:40:11.76#ibcon#enter sib2, iclass 4, count 0 2006.210.07:40:11.76#ibcon#flushed, iclass 4, count 0 2006.210.07:40:11.76#ibcon#about to write, iclass 4, count 0 2006.210.07:40:11.76#ibcon#wrote, iclass 4, count 0 2006.210.07:40:11.76#ibcon#about to read 3, iclass 4, count 0 2006.210.07:40:11.78#ibcon#read 3, iclass 4, count 0 2006.210.07:40:11.78#ibcon#about to read 4, iclass 4, count 0 2006.210.07:40:11.78#ibcon#read 4, iclass 4, count 0 2006.210.07:40:11.78#ibcon#about to read 5, iclass 4, count 0 2006.210.07:40:11.78#ibcon#read 5, iclass 4, count 0 2006.210.07:40:11.78#ibcon#about to read 6, iclass 4, count 0 2006.210.07:40:11.78#ibcon#read 6, iclass 4, count 0 2006.210.07:40:11.78#ibcon#end of sib2, iclass 4, count 0 2006.210.07:40:11.78#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:40:11.78#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:40:11.78#ibcon#[27=USB\r\n] 2006.210.07:40:11.78#ibcon#*before write, iclass 4, count 0 2006.210.07:40:11.78#ibcon#enter sib2, iclass 4, count 0 2006.210.07:40:11.78#ibcon#flushed, iclass 4, count 0 2006.210.07:40:11.78#ibcon#about to write, iclass 4, count 0 2006.210.07:40:11.78#ibcon#wrote, iclass 4, count 0 2006.210.07:40:11.78#ibcon#about to read 3, iclass 4, count 0 2006.210.07:40:11.81#ibcon#read 3, iclass 4, count 0 2006.210.07:40:11.81#ibcon#about to read 4, iclass 4, count 0 2006.210.07:40:11.81#ibcon#read 4, iclass 4, count 0 2006.210.07:40:11.81#ibcon#about to read 5, iclass 4, count 0 2006.210.07:40:11.81#ibcon#read 5, iclass 4, count 0 2006.210.07:40:11.81#ibcon#about to read 6, iclass 4, count 0 2006.210.07:40:11.81#ibcon#read 6, iclass 4, count 0 2006.210.07:40:11.81#ibcon#end of sib2, iclass 4, count 0 2006.210.07:40:11.81#ibcon#*after write, iclass 4, count 0 2006.210.07:40:11.81#ibcon#*before return 0, iclass 4, count 0 2006.210.07:40:11.81#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:11.81#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:40:11.81#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:40:11.81#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:40:11.81$vc4f8/vblo=6,752.99 2006.210.07:40:11.81#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:40:11.81#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:40:11.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:40:11.81#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:11.81#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:11.81#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:11.81#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:40:11.81#ibcon#first serial, iclass 6, count 0 2006.210.07:40:11.81#ibcon#enter sib2, iclass 6, count 0 2006.210.07:40:11.81#ibcon#flushed, iclass 6, count 0 2006.210.07:40:11.81#ibcon#about to write, iclass 6, count 0 2006.210.07:40:11.81#ibcon#wrote, iclass 6, count 0 2006.210.07:40:11.81#ibcon#about to read 3, iclass 6, count 0 2006.210.07:40:11.83#ibcon#read 3, iclass 6, count 0 2006.210.07:40:11.83#ibcon#about to read 4, iclass 6, count 0 2006.210.07:40:11.83#ibcon#read 4, iclass 6, count 0 2006.210.07:40:11.83#ibcon#about to read 5, iclass 6, count 0 2006.210.07:40:11.83#ibcon#read 5, iclass 6, count 0 2006.210.07:40:11.83#ibcon#about to read 6, iclass 6, count 0 2006.210.07:40:11.83#ibcon#read 6, iclass 6, count 0 2006.210.07:40:11.83#ibcon#end of sib2, iclass 6, count 0 2006.210.07:40:11.83#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:40:11.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:40:11.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:40:11.83#ibcon#*before write, iclass 6, count 0 2006.210.07:40:11.83#ibcon#enter sib2, iclass 6, count 0 2006.210.07:40:11.83#ibcon#flushed, iclass 6, count 0 2006.210.07:40:11.83#ibcon#about to write, iclass 6, count 0 2006.210.07:40:11.83#ibcon#wrote, iclass 6, count 0 2006.210.07:40:11.83#ibcon#about to read 3, iclass 6, count 0 2006.210.07:40:11.87#ibcon#read 3, iclass 6, count 0 2006.210.07:40:11.87#ibcon#about to read 4, iclass 6, count 0 2006.210.07:40:11.87#ibcon#read 4, iclass 6, count 0 2006.210.07:40:11.87#ibcon#about to read 5, iclass 6, count 0 2006.210.07:40:11.87#ibcon#read 5, iclass 6, count 0 2006.210.07:40:11.87#ibcon#about to read 6, iclass 6, count 0 2006.210.07:40:11.87#ibcon#read 6, iclass 6, count 0 2006.210.07:40:11.87#ibcon#end of sib2, iclass 6, count 0 2006.210.07:40:11.87#ibcon#*after write, iclass 6, count 0 2006.210.07:40:11.87#ibcon#*before return 0, iclass 6, count 0 2006.210.07:40:11.87#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:11.87#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:40:11.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:40:11.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:40:11.87$vc4f8/vb=6,3 2006.210.07:40:11.87#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:40:11.87#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:40:11.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:40:11.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:11.93#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:11.93#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:11.93#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:40:11.93#ibcon#first serial, iclass 10, count 2 2006.210.07:40:11.93#ibcon#enter sib2, iclass 10, count 2 2006.210.07:40:11.93#ibcon#flushed, iclass 10, count 2 2006.210.07:40:11.93#ibcon#about to write, iclass 10, count 2 2006.210.07:40:11.93#ibcon#wrote, iclass 10, count 2 2006.210.07:40:11.93#ibcon#about to read 3, iclass 10, count 2 2006.210.07:40:11.95#ibcon#read 3, iclass 10, count 2 2006.210.07:40:11.95#ibcon#about to read 4, iclass 10, count 2 2006.210.07:40:11.95#ibcon#read 4, iclass 10, count 2 2006.210.07:40:11.95#ibcon#about to read 5, iclass 10, count 2 2006.210.07:40:11.95#ibcon#read 5, iclass 10, count 2 2006.210.07:40:11.95#ibcon#about to read 6, iclass 10, count 2 2006.210.07:40:11.95#ibcon#read 6, iclass 10, count 2 2006.210.07:40:11.95#ibcon#end of sib2, iclass 10, count 2 2006.210.07:40:11.95#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:40:11.95#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:40:11.95#ibcon#[27=AT06-03\r\n] 2006.210.07:40:11.95#ibcon#*before write, iclass 10, count 2 2006.210.07:40:11.95#ibcon#enter sib2, iclass 10, count 2 2006.210.07:40:11.95#ibcon#flushed, iclass 10, count 2 2006.210.07:40:11.95#ibcon#about to write, iclass 10, count 2 2006.210.07:40:11.95#ibcon#wrote, iclass 10, count 2 2006.210.07:40:11.95#ibcon#about to read 3, iclass 10, count 2 2006.210.07:40:11.98#ibcon#read 3, iclass 10, count 2 2006.210.07:40:11.98#ibcon#about to read 4, iclass 10, count 2 2006.210.07:40:11.98#ibcon#read 4, iclass 10, count 2 2006.210.07:40:11.98#ibcon#about to read 5, iclass 10, count 2 2006.210.07:40:11.98#ibcon#read 5, iclass 10, count 2 2006.210.07:40:11.98#ibcon#about to read 6, iclass 10, count 2 2006.210.07:40:11.98#ibcon#read 6, iclass 10, count 2 2006.210.07:40:11.98#ibcon#end of sib2, iclass 10, count 2 2006.210.07:40:11.98#ibcon#*after write, iclass 10, count 2 2006.210.07:40:11.98#ibcon#*before return 0, iclass 10, count 2 2006.210.07:40:11.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:11.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:40:11.98#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:40:11.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:40:11.98#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:12.10#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:12.10#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:12.10#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:40:12.10#ibcon#first serial, iclass 10, count 0 2006.210.07:40:12.10#ibcon#enter sib2, iclass 10, count 0 2006.210.07:40:12.10#ibcon#flushed, iclass 10, count 0 2006.210.07:40:12.10#ibcon#about to write, iclass 10, count 0 2006.210.07:40:12.10#ibcon#wrote, iclass 10, count 0 2006.210.07:40:12.10#ibcon#about to read 3, iclass 10, count 0 2006.210.07:40:12.12#ibcon#read 3, iclass 10, count 0 2006.210.07:40:12.12#ibcon#about to read 4, iclass 10, count 0 2006.210.07:40:12.12#ibcon#read 4, iclass 10, count 0 2006.210.07:40:12.12#ibcon#about to read 5, iclass 10, count 0 2006.210.07:40:12.12#ibcon#read 5, iclass 10, count 0 2006.210.07:40:12.12#ibcon#about to read 6, iclass 10, count 0 2006.210.07:40:12.12#ibcon#read 6, iclass 10, count 0 2006.210.07:40:12.12#ibcon#end of sib2, iclass 10, count 0 2006.210.07:40:12.12#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:40:12.12#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:40:12.12#ibcon#[27=USB\r\n] 2006.210.07:40:12.12#ibcon#*before write, iclass 10, count 0 2006.210.07:40:12.12#ibcon#enter sib2, iclass 10, count 0 2006.210.07:40:12.12#ibcon#flushed, iclass 10, count 0 2006.210.07:40:12.12#ibcon#about to write, iclass 10, count 0 2006.210.07:40:12.12#ibcon#wrote, iclass 10, count 0 2006.210.07:40:12.12#ibcon#about to read 3, iclass 10, count 0 2006.210.07:40:12.15#ibcon#read 3, iclass 10, count 0 2006.210.07:40:12.15#ibcon#about to read 4, iclass 10, count 0 2006.210.07:40:12.15#ibcon#read 4, iclass 10, count 0 2006.210.07:40:12.15#ibcon#about to read 5, iclass 10, count 0 2006.210.07:40:12.15#ibcon#read 5, iclass 10, count 0 2006.210.07:40:12.15#ibcon#about to read 6, iclass 10, count 0 2006.210.07:40:12.15#ibcon#read 6, iclass 10, count 0 2006.210.07:40:12.15#ibcon#end of sib2, iclass 10, count 0 2006.210.07:40:12.15#ibcon#*after write, iclass 10, count 0 2006.210.07:40:12.15#ibcon#*before return 0, iclass 10, count 0 2006.210.07:40:12.15#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:12.15#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:40:12.15#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:40:12.15#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:40:12.15$vc4f8/vabw=wide 2006.210.07:40:12.15#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:40:12.15#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:40:12.15#ibcon#ireg 8 cls_cnt 0 2006.210.07:40:12.15#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:12.15#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:12.15#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:12.15#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:40:12.15#ibcon#first serial, iclass 12, count 0 2006.210.07:40:12.15#ibcon#enter sib2, iclass 12, count 0 2006.210.07:40:12.15#ibcon#flushed, iclass 12, count 0 2006.210.07:40:12.15#ibcon#about to write, iclass 12, count 0 2006.210.07:40:12.15#ibcon#wrote, iclass 12, count 0 2006.210.07:40:12.15#ibcon#about to read 3, iclass 12, count 0 2006.210.07:40:12.17#ibcon#read 3, iclass 12, count 0 2006.210.07:40:12.17#ibcon#about to read 4, iclass 12, count 0 2006.210.07:40:12.17#ibcon#read 4, iclass 12, count 0 2006.210.07:40:12.17#ibcon#about to read 5, iclass 12, count 0 2006.210.07:40:12.17#ibcon#read 5, iclass 12, count 0 2006.210.07:40:12.17#ibcon#about to read 6, iclass 12, count 0 2006.210.07:40:12.17#ibcon#read 6, iclass 12, count 0 2006.210.07:40:12.17#ibcon#end of sib2, iclass 12, count 0 2006.210.07:40:12.17#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:40:12.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:40:12.17#ibcon#[25=BW32\r\n] 2006.210.07:40:12.17#ibcon#*before write, iclass 12, count 0 2006.210.07:40:12.17#ibcon#enter sib2, iclass 12, count 0 2006.210.07:40:12.17#ibcon#flushed, iclass 12, count 0 2006.210.07:40:12.17#ibcon#about to write, iclass 12, count 0 2006.210.07:40:12.17#ibcon#wrote, iclass 12, count 0 2006.210.07:40:12.17#ibcon#about to read 3, iclass 12, count 0 2006.210.07:40:12.20#ibcon#read 3, iclass 12, count 0 2006.210.07:40:12.20#ibcon#about to read 4, iclass 12, count 0 2006.210.07:40:12.20#ibcon#read 4, iclass 12, count 0 2006.210.07:40:12.20#ibcon#about to read 5, iclass 12, count 0 2006.210.07:40:12.20#ibcon#read 5, iclass 12, count 0 2006.210.07:40:12.20#ibcon#about to read 6, iclass 12, count 0 2006.210.07:40:12.20#ibcon#read 6, iclass 12, count 0 2006.210.07:40:12.20#ibcon#end of sib2, iclass 12, count 0 2006.210.07:40:12.20#ibcon#*after write, iclass 12, count 0 2006.210.07:40:12.20#ibcon#*before return 0, iclass 12, count 0 2006.210.07:40:12.20#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:12.20#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:40:12.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:40:12.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:40:12.20$vc4f8/vbbw=wide 2006.210.07:40:12.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.07:40:12.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.07:40:12.20#ibcon#ireg 8 cls_cnt 0 2006.210.07:40:12.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:40:12.27#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:40:12.27#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:40:12.27#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:40:12.27#ibcon#first serial, iclass 14, count 0 2006.210.07:40:12.27#ibcon#enter sib2, iclass 14, count 0 2006.210.07:40:12.27#ibcon#flushed, iclass 14, count 0 2006.210.07:40:12.27#ibcon#about to write, iclass 14, count 0 2006.210.07:40:12.27#ibcon#wrote, iclass 14, count 0 2006.210.07:40:12.27#ibcon#about to read 3, iclass 14, count 0 2006.210.07:40:12.29#ibcon#read 3, iclass 14, count 0 2006.210.07:40:12.29#ibcon#about to read 4, iclass 14, count 0 2006.210.07:40:12.29#ibcon#read 4, iclass 14, count 0 2006.210.07:40:12.29#ibcon#about to read 5, iclass 14, count 0 2006.210.07:40:12.29#ibcon#read 5, iclass 14, count 0 2006.210.07:40:12.29#ibcon#about to read 6, iclass 14, count 0 2006.210.07:40:12.29#ibcon#read 6, iclass 14, count 0 2006.210.07:40:12.29#ibcon#end of sib2, iclass 14, count 0 2006.210.07:40:12.29#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:40:12.29#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:40:12.29#ibcon#[27=BW32\r\n] 2006.210.07:40:12.29#ibcon#*before write, iclass 14, count 0 2006.210.07:40:12.29#ibcon#enter sib2, iclass 14, count 0 2006.210.07:40:12.29#ibcon#flushed, iclass 14, count 0 2006.210.07:40:12.29#ibcon#about to write, iclass 14, count 0 2006.210.07:40:12.29#ibcon#wrote, iclass 14, count 0 2006.210.07:40:12.29#ibcon#about to read 3, iclass 14, count 0 2006.210.07:40:12.32#ibcon#read 3, iclass 14, count 0 2006.210.07:40:12.32#ibcon#about to read 4, iclass 14, count 0 2006.210.07:40:12.32#ibcon#read 4, iclass 14, count 0 2006.210.07:40:12.32#ibcon#about to read 5, iclass 14, count 0 2006.210.07:40:12.32#ibcon#read 5, iclass 14, count 0 2006.210.07:40:12.32#ibcon#about to read 6, iclass 14, count 0 2006.210.07:40:12.32#ibcon#read 6, iclass 14, count 0 2006.210.07:40:12.32#ibcon#end of sib2, iclass 14, count 0 2006.210.07:40:12.32#ibcon#*after write, iclass 14, count 0 2006.210.07:40:12.32#ibcon#*before return 0, iclass 14, count 0 2006.210.07:40:12.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:40:12.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:40:12.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:40:12.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:40:12.32$4f8m12a/ifd4f 2006.210.07:40:12.32$ifd4f/lo= 2006.210.07:40:12.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:40:12.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:40:12.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:40:12.32$ifd4f/patch= 2006.210.07:40:12.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:40:12.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:40:12.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:40:12.32$4f8m12a/"form=m,16.000,1:2 2006.210.07:40:12.32$4f8m12a/"tpicd 2006.210.07:40:12.32$4f8m12a/echo=off 2006.210.07:40:12.32$4f8m12a/xlog=off 2006.210.07:40:12.32:!2006.210.07:40:40 2006.210.07:40:22.13#trakl#Source acquired 2006.210.07:40:24.13#flagr#flagr/antenna,acquired 2006.210.07:40:40.00:preob 2006.210.07:40:40.13/onsource/TRACKING 2006.210.07:40:40.13:!2006.210.07:40:50 2006.210.07:40:50.00:data_valid=on 2006.210.07:40:50.00:midob 2006.210.07:40:51.13/onsource/TRACKING 2006.210.07:40:51.13/wx/30.60,1006.2,76 2006.210.07:40:51.34/cable/+6.3927E-03 2006.210.07:40:52.43/va/01,08,usb,yes,28,30 2006.210.07:40:52.43/va/02,07,usb,yes,28,30 2006.210.07:40:52.43/va/03,06,usb,yes,30,30 2006.210.07:40:52.43/va/04,07,usb,yes,29,31 2006.210.07:40:52.43/va/05,07,usb,yes,30,32 2006.210.07:40:52.43/va/06,06,usb,yes,29,29 2006.210.07:40:52.43/va/07,06,usb,yes,30,29 2006.210.07:40:52.43/va/08,07,usb,yes,28,27 2006.210.07:40:52.66/valo/01,532.99,yes,locked 2006.210.07:40:52.66/valo/02,572.99,yes,locked 2006.210.07:40:52.66/valo/03,672.99,yes,locked 2006.210.07:40:52.66/valo/04,832.99,yes,locked 2006.210.07:40:52.66/valo/05,652.99,yes,locked 2006.210.07:40:52.66/valo/06,772.99,yes,locked 2006.210.07:40:52.66/valo/07,832.99,yes,locked 2006.210.07:40:52.66/valo/08,852.99,yes,locked 2006.210.07:40:53.75/vb/01,04,usb,yes,28,27 2006.210.07:40:53.75/vb/02,04,usb,yes,30,31 2006.210.07:40:53.75/vb/03,03,usb,yes,33,37 2006.210.07:40:53.75/vb/04,03,usb,yes,34,34 2006.210.07:40:53.75/vb/05,03,usb,yes,32,36 2006.210.07:40:53.75/vb/06,03,usb,yes,33,36 2006.210.07:40:53.75/vb/07,04,usb,yes,29,28 2006.210.07:40:53.75/vb/08,03,usb,yes,33,36 2006.210.07:40:53.98/vblo/01,632.99,yes,locked 2006.210.07:40:53.98/vblo/02,640.99,yes,locked 2006.210.07:40:53.98/vblo/03,656.99,yes,locked 2006.210.07:40:53.98/vblo/04,712.99,yes,locked 2006.210.07:40:53.98/vblo/05,744.99,yes,locked 2006.210.07:40:53.98/vblo/06,752.99,yes,locked 2006.210.07:40:53.98/vblo/07,734.99,yes,locked 2006.210.07:40:53.98/vblo/08,744.99,yes,locked 2006.210.07:40:54.13/vabw/8 2006.210.07:40:54.28/vbbw/8 2006.210.07:40:54.37/xfe/off,on,13.0 2006.210.07:40:54.74/ifatt/23,28,28,28 2006.210.07:40:55.07/fmout-gps/S +4.43E-07 2006.210.07:40:55.11:!2006.210.07:41:50 2006.210.07:41:50.00:data_valid=off 2006.210.07:41:50.00:postob 2006.210.07:41:50.10/cable/+6.3961E-03 2006.210.07:41:50.10/wx/30.59,1006.2,75 2006.210.07:41:51.07/fmout-gps/S +4.45E-07 2006.210.07:41:51.07:scan_name=210-0742,k06210,60 2006.210.07:41:51.07:source=1739+522,174036.98,521143.4,2000.0,cw 2006.210.07:41:51.13#flagr#flagr/antenna,new-source 2006.210.07:41:52.13:checkk5 2006.210.07:41:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:41:52.81/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:41:53.16/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:41:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:41:53.84/chk_obsdata//k5ts1/T2100740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:41:54.17/chk_obsdata//k5ts2/T2100740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:41:54.50/chk_obsdata//k5ts3/T2100740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:41:54.83/chk_obsdata//k5ts4/T2100740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:41:55.50/k5log//k5ts1_log_newline 2006.210.07:41:56.16/k5log//k5ts2_log_newline 2006.210.07:41:56.81/k5log//k5ts3_log_newline 2006.210.07:41:57.46/k5log//k5ts4_log_newline 2006.210.07:41:57.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:41:57.48:4f8m12a=1 2006.210.07:41:57.48$4f8m12a/echo=on 2006.210.07:41:57.48$4f8m12a/pcalon 2006.210.07:41:57.48$pcalon/"no phase cal control is implemented here 2006.210.07:41:57.48$4f8m12a/"tpicd=stop 2006.210.07:41:57.48$4f8m12a/vc4f8 2006.210.07:41:57.48$vc4f8/valo=1,532.99 2006.210.07:41:57.48#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.07:41:57.48#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.07:41:57.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:57.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:41:57.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:41:57.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:41:57.48#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:41:57.48#ibcon#first serial, iclass 25, count 0 2006.210.07:41:57.48#ibcon#enter sib2, iclass 25, count 0 2006.210.07:41:57.48#ibcon#flushed, iclass 25, count 0 2006.210.07:41:57.49#ibcon#about to write, iclass 25, count 0 2006.210.07:41:57.49#ibcon#wrote, iclass 25, count 0 2006.210.07:41:57.49#ibcon#about to read 3, iclass 25, count 0 2006.210.07:41:57.50#ibcon#read 3, iclass 25, count 0 2006.210.07:41:57.50#ibcon#about to read 4, iclass 25, count 0 2006.210.07:41:57.50#ibcon#read 4, iclass 25, count 0 2006.210.07:41:57.50#ibcon#about to read 5, iclass 25, count 0 2006.210.07:41:57.50#ibcon#read 5, iclass 25, count 0 2006.210.07:41:57.50#ibcon#about to read 6, iclass 25, count 0 2006.210.07:41:57.50#ibcon#read 6, iclass 25, count 0 2006.210.07:41:57.50#ibcon#end of sib2, iclass 25, count 0 2006.210.07:41:57.50#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:41:57.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:41:57.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:41:57.50#ibcon#*before write, iclass 25, count 0 2006.210.07:41:57.50#ibcon#enter sib2, iclass 25, count 0 2006.210.07:41:57.50#ibcon#flushed, iclass 25, count 0 2006.210.07:41:57.50#ibcon#about to write, iclass 25, count 0 2006.210.07:41:57.50#ibcon#wrote, iclass 25, count 0 2006.210.07:41:57.50#ibcon#about to read 3, iclass 25, count 0 2006.210.07:41:57.55#ibcon#read 3, iclass 25, count 0 2006.210.07:41:57.55#ibcon#about to read 4, iclass 25, count 0 2006.210.07:41:57.55#ibcon#read 4, iclass 25, count 0 2006.210.07:41:57.55#ibcon#about to read 5, iclass 25, count 0 2006.210.07:41:57.55#ibcon#read 5, iclass 25, count 0 2006.210.07:41:57.55#ibcon#about to read 6, iclass 25, count 0 2006.210.07:41:57.55#ibcon#read 6, iclass 25, count 0 2006.210.07:41:57.55#ibcon#end of sib2, iclass 25, count 0 2006.210.07:41:57.55#ibcon#*after write, iclass 25, count 0 2006.210.07:41:57.55#ibcon#*before return 0, iclass 25, count 0 2006.210.07:41:57.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:41:57.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:41:57.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:41:57.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:41:57.55$vc4f8/va=1,8 2006.210.07:41:57.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.07:41:57.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.07:41:57.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:57.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:41:57.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:41:57.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:41:57.55#ibcon#enter wrdev, iclass 27, count 2 2006.210.07:41:57.55#ibcon#first serial, iclass 27, count 2 2006.210.07:41:57.55#ibcon#enter sib2, iclass 27, count 2 2006.210.07:41:57.55#ibcon#flushed, iclass 27, count 2 2006.210.07:41:57.55#ibcon#about to write, iclass 27, count 2 2006.210.07:41:57.55#ibcon#wrote, iclass 27, count 2 2006.210.07:41:57.55#ibcon#about to read 3, iclass 27, count 2 2006.210.07:41:57.57#ibcon#read 3, iclass 27, count 2 2006.210.07:41:57.57#ibcon#about to read 4, iclass 27, count 2 2006.210.07:41:57.57#ibcon#read 4, iclass 27, count 2 2006.210.07:41:57.57#ibcon#about to read 5, iclass 27, count 2 2006.210.07:41:57.57#ibcon#read 5, iclass 27, count 2 2006.210.07:41:57.57#ibcon#about to read 6, iclass 27, count 2 2006.210.07:41:57.57#ibcon#read 6, iclass 27, count 2 2006.210.07:41:57.57#ibcon#end of sib2, iclass 27, count 2 2006.210.07:41:57.57#ibcon#*mode == 0, iclass 27, count 2 2006.210.07:41:57.57#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.07:41:57.57#ibcon#[25=AT01-08\r\n] 2006.210.07:41:57.57#ibcon#*before write, iclass 27, count 2 2006.210.07:41:57.57#ibcon#enter sib2, iclass 27, count 2 2006.210.07:41:57.57#ibcon#flushed, iclass 27, count 2 2006.210.07:41:57.57#ibcon#about to write, iclass 27, count 2 2006.210.07:41:57.57#ibcon#wrote, iclass 27, count 2 2006.210.07:41:57.57#ibcon#about to read 3, iclass 27, count 2 2006.210.07:41:57.60#ibcon#read 3, iclass 27, count 2 2006.210.07:41:57.60#ibcon#about to read 4, iclass 27, count 2 2006.210.07:41:57.60#ibcon#read 4, iclass 27, count 2 2006.210.07:41:57.60#ibcon#about to read 5, iclass 27, count 2 2006.210.07:41:57.60#ibcon#read 5, iclass 27, count 2 2006.210.07:41:57.60#ibcon#about to read 6, iclass 27, count 2 2006.210.07:41:57.60#ibcon#read 6, iclass 27, count 2 2006.210.07:41:57.60#ibcon#end of sib2, iclass 27, count 2 2006.210.07:41:57.60#ibcon#*after write, iclass 27, count 2 2006.210.07:41:57.60#ibcon#*before return 0, iclass 27, count 2 2006.210.07:41:57.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:41:57.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:41:57.60#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.07:41:57.60#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:57.60#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:41:57.72#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:41:57.72#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:41:57.72#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:41:57.72#ibcon#first serial, iclass 27, count 0 2006.210.07:41:57.72#ibcon#enter sib2, iclass 27, count 0 2006.210.07:41:57.72#ibcon#flushed, iclass 27, count 0 2006.210.07:41:57.72#ibcon#about to write, iclass 27, count 0 2006.210.07:41:57.72#ibcon#wrote, iclass 27, count 0 2006.210.07:41:57.72#ibcon#about to read 3, iclass 27, count 0 2006.210.07:41:57.74#ibcon#read 3, iclass 27, count 0 2006.210.07:41:57.74#ibcon#about to read 4, iclass 27, count 0 2006.210.07:41:57.74#ibcon#read 4, iclass 27, count 0 2006.210.07:41:57.74#ibcon#about to read 5, iclass 27, count 0 2006.210.07:41:57.74#ibcon#read 5, iclass 27, count 0 2006.210.07:41:57.74#ibcon#about to read 6, iclass 27, count 0 2006.210.07:41:57.74#ibcon#read 6, iclass 27, count 0 2006.210.07:41:57.74#ibcon#end of sib2, iclass 27, count 0 2006.210.07:41:57.74#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:41:57.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:41:57.74#ibcon#[25=USB\r\n] 2006.210.07:41:57.74#ibcon#*before write, iclass 27, count 0 2006.210.07:41:57.74#ibcon#enter sib2, iclass 27, count 0 2006.210.07:41:57.74#ibcon#flushed, iclass 27, count 0 2006.210.07:41:57.74#ibcon#about to write, iclass 27, count 0 2006.210.07:41:57.74#ibcon#wrote, iclass 27, count 0 2006.210.07:41:57.74#ibcon#about to read 3, iclass 27, count 0 2006.210.07:41:57.77#ibcon#read 3, iclass 27, count 0 2006.210.07:41:57.77#ibcon#about to read 4, iclass 27, count 0 2006.210.07:41:57.77#ibcon#read 4, iclass 27, count 0 2006.210.07:41:57.77#ibcon#about to read 5, iclass 27, count 0 2006.210.07:41:57.77#ibcon#read 5, iclass 27, count 0 2006.210.07:41:57.77#ibcon#about to read 6, iclass 27, count 0 2006.210.07:41:57.77#ibcon#read 6, iclass 27, count 0 2006.210.07:41:57.77#ibcon#end of sib2, iclass 27, count 0 2006.210.07:41:57.77#ibcon#*after write, iclass 27, count 0 2006.210.07:41:57.77#ibcon#*before return 0, iclass 27, count 0 2006.210.07:41:57.77#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:41:57.77#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:41:57.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:41:57.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:41:57.77$vc4f8/valo=2,572.99 2006.210.07:41:57.77#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.07:41:57.77#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.07:41:57.77#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:57.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:41:57.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:41:57.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:41:57.77#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:41:57.77#ibcon#first serial, iclass 29, count 0 2006.210.07:41:57.77#ibcon#enter sib2, iclass 29, count 0 2006.210.07:41:57.77#ibcon#flushed, iclass 29, count 0 2006.210.07:41:57.77#ibcon#about to write, iclass 29, count 0 2006.210.07:41:57.77#ibcon#wrote, iclass 29, count 0 2006.210.07:41:57.77#ibcon#about to read 3, iclass 29, count 0 2006.210.07:41:57.79#ibcon#read 3, iclass 29, count 0 2006.210.07:41:57.79#ibcon#about to read 4, iclass 29, count 0 2006.210.07:41:57.79#ibcon#read 4, iclass 29, count 0 2006.210.07:41:57.79#ibcon#about to read 5, iclass 29, count 0 2006.210.07:41:57.79#ibcon#read 5, iclass 29, count 0 2006.210.07:41:57.79#ibcon#about to read 6, iclass 29, count 0 2006.210.07:41:57.79#ibcon#read 6, iclass 29, count 0 2006.210.07:41:57.79#ibcon#end of sib2, iclass 29, count 0 2006.210.07:41:57.79#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:41:57.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:41:57.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:41:57.79#ibcon#*before write, iclass 29, count 0 2006.210.07:41:57.79#ibcon#enter sib2, iclass 29, count 0 2006.210.07:41:57.79#ibcon#flushed, iclass 29, count 0 2006.210.07:41:57.79#ibcon#about to write, iclass 29, count 0 2006.210.07:41:57.79#ibcon#wrote, iclass 29, count 0 2006.210.07:41:57.79#ibcon#about to read 3, iclass 29, count 0 2006.210.07:41:57.83#ibcon#read 3, iclass 29, count 0 2006.210.07:41:57.83#ibcon#about to read 4, iclass 29, count 0 2006.210.07:41:57.83#ibcon#read 4, iclass 29, count 0 2006.210.07:41:57.83#ibcon#about to read 5, iclass 29, count 0 2006.210.07:41:57.83#ibcon#read 5, iclass 29, count 0 2006.210.07:41:57.83#ibcon#about to read 6, iclass 29, count 0 2006.210.07:41:57.83#ibcon#read 6, iclass 29, count 0 2006.210.07:41:57.83#ibcon#end of sib2, iclass 29, count 0 2006.210.07:41:57.83#ibcon#*after write, iclass 29, count 0 2006.210.07:41:57.83#ibcon#*before return 0, iclass 29, count 0 2006.210.07:41:57.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:41:57.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:41:57.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:41:57.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:41:57.83$vc4f8/va=2,7 2006.210.07:41:57.83#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.07:41:57.83#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.07:41:57.83#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:57.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:41:57.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:41:57.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:41:57.89#ibcon#enter wrdev, iclass 31, count 2 2006.210.07:41:57.89#ibcon#first serial, iclass 31, count 2 2006.210.07:41:57.89#ibcon#enter sib2, iclass 31, count 2 2006.210.07:41:57.89#ibcon#flushed, iclass 31, count 2 2006.210.07:41:57.89#ibcon#about to write, iclass 31, count 2 2006.210.07:41:57.89#ibcon#wrote, iclass 31, count 2 2006.210.07:41:57.89#ibcon#about to read 3, iclass 31, count 2 2006.210.07:41:57.91#ibcon#read 3, iclass 31, count 2 2006.210.07:41:57.91#ibcon#about to read 4, iclass 31, count 2 2006.210.07:41:57.91#ibcon#read 4, iclass 31, count 2 2006.210.07:41:57.91#ibcon#about to read 5, iclass 31, count 2 2006.210.07:41:57.91#ibcon#read 5, iclass 31, count 2 2006.210.07:41:57.91#ibcon#about to read 6, iclass 31, count 2 2006.210.07:41:57.91#ibcon#read 6, iclass 31, count 2 2006.210.07:41:57.91#ibcon#end of sib2, iclass 31, count 2 2006.210.07:41:57.91#ibcon#*mode == 0, iclass 31, count 2 2006.210.07:41:57.91#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.07:41:57.91#ibcon#[25=AT02-07\r\n] 2006.210.07:41:57.91#ibcon#*before write, iclass 31, count 2 2006.210.07:41:57.91#ibcon#enter sib2, iclass 31, count 2 2006.210.07:41:57.91#ibcon#flushed, iclass 31, count 2 2006.210.07:41:57.91#ibcon#about to write, iclass 31, count 2 2006.210.07:41:57.91#ibcon#wrote, iclass 31, count 2 2006.210.07:41:57.91#ibcon#about to read 3, iclass 31, count 2 2006.210.07:41:57.94#ibcon#read 3, iclass 31, count 2 2006.210.07:41:57.94#ibcon#about to read 4, iclass 31, count 2 2006.210.07:41:57.94#ibcon#read 4, iclass 31, count 2 2006.210.07:41:57.94#ibcon#about to read 5, iclass 31, count 2 2006.210.07:41:57.94#ibcon#read 5, iclass 31, count 2 2006.210.07:41:57.94#ibcon#about to read 6, iclass 31, count 2 2006.210.07:41:57.94#ibcon#read 6, iclass 31, count 2 2006.210.07:41:57.94#ibcon#end of sib2, iclass 31, count 2 2006.210.07:41:57.94#ibcon#*after write, iclass 31, count 2 2006.210.07:41:57.94#ibcon#*before return 0, iclass 31, count 2 2006.210.07:41:57.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:41:57.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:41:57.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.07:41:57.94#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:57.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:41:58.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:41:58.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:41:58.06#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:41:58.06#ibcon#first serial, iclass 31, count 0 2006.210.07:41:58.06#ibcon#enter sib2, iclass 31, count 0 2006.210.07:41:58.06#ibcon#flushed, iclass 31, count 0 2006.210.07:41:58.06#ibcon#about to write, iclass 31, count 0 2006.210.07:41:58.06#ibcon#wrote, iclass 31, count 0 2006.210.07:41:58.06#ibcon#about to read 3, iclass 31, count 0 2006.210.07:41:58.08#ibcon#read 3, iclass 31, count 0 2006.210.07:41:58.08#ibcon#about to read 4, iclass 31, count 0 2006.210.07:41:58.08#ibcon#read 4, iclass 31, count 0 2006.210.07:41:58.08#ibcon#about to read 5, iclass 31, count 0 2006.210.07:41:58.08#ibcon#read 5, iclass 31, count 0 2006.210.07:41:58.08#ibcon#about to read 6, iclass 31, count 0 2006.210.07:41:58.08#ibcon#read 6, iclass 31, count 0 2006.210.07:41:58.08#ibcon#end of sib2, iclass 31, count 0 2006.210.07:41:58.08#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:41:58.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:41:58.08#ibcon#[25=USB\r\n] 2006.210.07:41:58.08#ibcon#*before write, iclass 31, count 0 2006.210.07:41:58.08#ibcon#enter sib2, iclass 31, count 0 2006.210.07:41:58.08#ibcon#flushed, iclass 31, count 0 2006.210.07:41:58.08#ibcon#about to write, iclass 31, count 0 2006.210.07:41:58.08#ibcon#wrote, iclass 31, count 0 2006.210.07:41:58.08#ibcon#about to read 3, iclass 31, count 0 2006.210.07:41:58.11#ibcon#read 3, iclass 31, count 0 2006.210.07:41:58.11#ibcon#about to read 4, iclass 31, count 0 2006.210.07:41:58.11#ibcon#read 4, iclass 31, count 0 2006.210.07:41:58.11#ibcon#about to read 5, iclass 31, count 0 2006.210.07:41:58.11#ibcon#read 5, iclass 31, count 0 2006.210.07:41:58.11#ibcon#about to read 6, iclass 31, count 0 2006.210.07:41:58.11#ibcon#read 6, iclass 31, count 0 2006.210.07:41:58.11#ibcon#end of sib2, iclass 31, count 0 2006.210.07:41:58.11#ibcon#*after write, iclass 31, count 0 2006.210.07:41:58.11#ibcon#*before return 0, iclass 31, count 0 2006.210.07:41:58.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:41:58.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:41:58.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:41:58.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:41:58.11$vc4f8/valo=3,672.99 2006.210.07:41:58.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.07:41:58.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.07:41:58.11#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:58.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:41:58.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:41:58.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:41:58.11#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:41:58.11#ibcon#first serial, iclass 33, count 0 2006.210.07:41:58.11#ibcon#enter sib2, iclass 33, count 0 2006.210.07:41:58.11#ibcon#flushed, iclass 33, count 0 2006.210.07:41:58.11#ibcon#about to write, iclass 33, count 0 2006.210.07:41:58.11#ibcon#wrote, iclass 33, count 0 2006.210.07:41:58.11#ibcon#about to read 3, iclass 33, count 0 2006.210.07:41:58.13#ibcon#read 3, iclass 33, count 0 2006.210.07:41:58.13#ibcon#about to read 4, iclass 33, count 0 2006.210.07:41:58.13#ibcon#read 4, iclass 33, count 0 2006.210.07:41:58.13#ibcon#about to read 5, iclass 33, count 0 2006.210.07:41:58.13#ibcon#read 5, iclass 33, count 0 2006.210.07:41:58.13#ibcon#about to read 6, iclass 33, count 0 2006.210.07:41:58.13#ibcon#read 6, iclass 33, count 0 2006.210.07:41:58.13#ibcon#end of sib2, iclass 33, count 0 2006.210.07:41:58.13#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:41:58.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:41:58.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:41:58.13#ibcon#*before write, iclass 33, count 0 2006.210.07:41:58.13#ibcon#enter sib2, iclass 33, count 0 2006.210.07:41:58.13#ibcon#flushed, iclass 33, count 0 2006.210.07:41:58.13#ibcon#about to write, iclass 33, count 0 2006.210.07:41:58.13#ibcon#wrote, iclass 33, count 0 2006.210.07:41:58.13#ibcon#about to read 3, iclass 33, count 0 2006.210.07:41:58.17#ibcon#read 3, iclass 33, count 0 2006.210.07:41:58.17#ibcon#about to read 4, iclass 33, count 0 2006.210.07:41:58.17#ibcon#read 4, iclass 33, count 0 2006.210.07:41:58.17#ibcon#about to read 5, iclass 33, count 0 2006.210.07:41:58.17#ibcon#read 5, iclass 33, count 0 2006.210.07:41:58.17#ibcon#about to read 6, iclass 33, count 0 2006.210.07:41:58.17#ibcon#read 6, iclass 33, count 0 2006.210.07:41:58.17#ibcon#end of sib2, iclass 33, count 0 2006.210.07:41:58.17#ibcon#*after write, iclass 33, count 0 2006.210.07:41:58.17#ibcon#*before return 0, iclass 33, count 0 2006.210.07:41:58.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:41:58.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:41:58.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:41:58.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:41:58.17$vc4f8/va=3,6 2006.210.07:41:58.17#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.07:41:58.17#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.07:41:58.17#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:58.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:41:58.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:41:58.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:41:58.23#ibcon#enter wrdev, iclass 35, count 2 2006.210.07:41:58.23#ibcon#first serial, iclass 35, count 2 2006.210.07:41:58.23#ibcon#enter sib2, iclass 35, count 2 2006.210.07:41:58.23#ibcon#flushed, iclass 35, count 2 2006.210.07:41:58.23#ibcon#about to write, iclass 35, count 2 2006.210.07:41:58.23#ibcon#wrote, iclass 35, count 2 2006.210.07:41:58.23#ibcon#about to read 3, iclass 35, count 2 2006.210.07:41:58.25#ibcon#read 3, iclass 35, count 2 2006.210.07:41:58.25#ibcon#about to read 4, iclass 35, count 2 2006.210.07:41:58.25#ibcon#read 4, iclass 35, count 2 2006.210.07:41:58.25#ibcon#about to read 5, iclass 35, count 2 2006.210.07:41:58.25#ibcon#read 5, iclass 35, count 2 2006.210.07:41:58.25#ibcon#about to read 6, iclass 35, count 2 2006.210.07:41:58.25#ibcon#read 6, iclass 35, count 2 2006.210.07:41:58.25#ibcon#end of sib2, iclass 35, count 2 2006.210.07:41:58.25#ibcon#*mode == 0, iclass 35, count 2 2006.210.07:41:58.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.07:41:58.25#ibcon#[25=AT03-06\r\n] 2006.210.07:41:58.25#ibcon#*before write, iclass 35, count 2 2006.210.07:41:58.25#ibcon#enter sib2, iclass 35, count 2 2006.210.07:41:58.25#ibcon#flushed, iclass 35, count 2 2006.210.07:41:58.25#ibcon#about to write, iclass 35, count 2 2006.210.07:41:58.25#ibcon#wrote, iclass 35, count 2 2006.210.07:41:58.25#ibcon#about to read 3, iclass 35, count 2 2006.210.07:41:58.28#ibcon#read 3, iclass 35, count 2 2006.210.07:41:58.28#ibcon#about to read 4, iclass 35, count 2 2006.210.07:41:58.28#ibcon#read 4, iclass 35, count 2 2006.210.07:41:58.28#ibcon#about to read 5, iclass 35, count 2 2006.210.07:41:58.28#ibcon#read 5, iclass 35, count 2 2006.210.07:41:58.28#ibcon#about to read 6, iclass 35, count 2 2006.210.07:41:58.28#ibcon#read 6, iclass 35, count 2 2006.210.07:41:58.28#ibcon#end of sib2, iclass 35, count 2 2006.210.07:41:58.28#ibcon#*after write, iclass 35, count 2 2006.210.07:41:58.28#ibcon#*before return 0, iclass 35, count 2 2006.210.07:41:58.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:41:58.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:41:58.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.07:41:58.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:58.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:41:58.40#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:41:58.40#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:41:58.40#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:41:58.40#ibcon#first serial, iclass 35, count 0 2006.210.07:41:58.40#ibcon#enter sib2, iclass 35, count 0 2006.210.07:41:58.40#ibcon#flushed, iclass 35, count 0 2006.210.07:41:58.40#ibcon#about to write, iclass 35, count 0 2006.210.07:41:58.40#ibcon#wrote, iclass 35, count 0 2006.210.07:41:58.40#ibcon#about to read 3, iclass 35, count 0 2006.210.07:41:58.42#ibcon#read 3, iclass 35, count 0 2006.210.07:41:58.42#ibcon#about to read 4, iclass 35, count 0 2006.210.07:41:58.42#ibcon#read 4, iclass 35, count 0 2006.210.07:41:58.42#ibcon#about to read 5, iclass 35, count 0 2006.210.07:41:58.42#ibcon#read 5, iclass 35, count 0 2006.210.07:41:58.42#ibcon#about to read 6, iclass 35, count 0 2006.210.07:41:58.42#ibcon#read 6, iclass 35, count 0 2006.210.07:41:58.42#ibcon#end of sib2, iclass 35, count 0 2006.210.07:41:58.42#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:41:58.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:41:58.42#ibcon#[25=USB\r\n] 2006.210.07:41:58.42#ibcon#*before write, iclass 35, count 0 2006.210.07:41:58.42#ibcon#enter sib2, iclass 35, count 0 2006.210.07:41:58.42#ibcon#flushed, iclass 35, count 0 2006.210.07:41:58.42#ibcon#about to write, iclass 35, count 0 2006.210.07:41:58.42#ibcon#wrote, iclass 35, count 0 2006.210.07:41:58.42#ibcon#about to read 3, iclass 35, count 0 2006.210.07:41:58.45#ibcon#read 3, iclass 35, count 0 2006.210.07:41:58.45#ibcon#about to read 4, iclass 35, count 0 2006.210.07:41:58.45#ibcon#read 4, iclass 35, count 0 2006.210.07:41:58.45#ibcon#about to read 5, iclass 35, count 0 2006.210.07:41:58.45#ibcon#read 5, iclass 35, count 0 2006.210.07:41:58.45#ibcon#about to read 6, iclass 35, count 0 2006.210.07:41:58.45#ibcon#read 6, iclass 35, count 0 2006.210.07:41:58.45#ibcon#end of sib2, iclass 35, count 0 2006.210.07:41:58.45#ibcon#*after write, iclass 35, count 0 2006.210.07:41:58.45#ibcon#*before return 0, iclass 35, count 0 2006.210.07:41:58.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:41:58.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:41:58.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:41:58.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:41:58.45$vc4f8/valo=4,832.99 2006.210.07:41:58.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:41:58.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:41:58.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:58.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:41:58.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:41:58.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:41:58.45#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:41:58.45#ibcon#first serial, iclass 37, count 0 2006.210.07:41:58.45#ibcon#enter sib2, iclass 37, count 0 2006.210.07:41:58.45#ibcon#flushed, iclass 37, count 0 2006.210.07:41:58.45#ibcon#about to write, iclass 37, count 0 2006.210.07:41:58.45#ibcon#wrote, iclass 37, count 0 2006.210.07:41:58.45#ibcon#about to read 3, iclass 37, count 0 2006.210.07:41:58.47#ibcon#read 3, iclass 37, count 0 2006.210.07:41:58.47#ibcon#about to read 4, iclass 37, count 0 2006.210.07:41:58.47#ibcon#read 4, iclass 37, count 0 2006.210.07:41:58.47#ibcon#about to read 5, iclass 37, count 0 2006.210.07:41:58.47#ibcon#read 5, iclass 37, count 0 2006.210.07:41:58.47#ibcon#about to read 6, iclass 37, count 0 2006.210.07:41:58.47#ibcon#read 6, iclass 37, count 0 2006.210.07:41:58.47#ibcon#end of sib2, iclass 37, count 0 2006.210.07:41:58.47#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:41:58.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:41:58.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:41:58.47#ibcon#*before write, iclass 37, count 0 2006.210.07:41:58.47#ibcon#enter sib2, iclass 37, count 0 2006.210.07:41:58.47#ibcon#flushed, iclass 37, count 0 2006.210.07:41:58.47#ibcon#about to write, iclass 37, count 0 2006.210.07:41:58.47#ibcon#wrote, iclass 37, count 0 2006.210.07:41:58.47#ibcon#about to read 3, iclass 37, count 0 2006.210.07:41:58.51#ibcon#read 3, iclass 37, count 0 2006.210.07:41:58.51#ibcon#about to read 4, iclass 37, count 0 2006.210.07:41:58.51#ibcon#read 4, iclass 37, count 0 2006.210.07:41:58.51#ibcon#about to read 5, iclass 37, count 0 2006.210.07:41:58.51#ibcon#read 5, iclass 37, count 0 2006.210.07:41:58.51#ibcon#about to read 6, iclass 37, count 0 2006.210.07:41:58.51#ibcon#read 6, iclass 37, count 0 2006.210.07:41:58.51#ibcon#end of sib2, iclass 37, count 0 2006.210.07:41:58.51#ibcon#*after write, iclass 37, count 0 2006.210.07:41:58.51#ibcon#*before return 0, iclass 37, count 0 2006.210.07:41:58.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:41:58.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:41:58.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:41:58.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:41:58.51$vc4f8/va=4,7 2006.210.07:41:58.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:41:58.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:41:58.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:58.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:41:58.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:41:58.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:41:58.57#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:41:58.57#ibcon#first serial, iclass 39, count 2 2006.210.07:41:58.57#ibcon#enter sib2, iclass 39, count 2 2006.210.07:41:58.57#ibcon#flushed, iclass 39, count 2 2006.210.07:41:58.57#ibcon#about to write, iclass 39, count 2 2006.210.07:41:58.57#ibcon#wrote, iclass 39, count 2 2006.210.07:41:58.57#ibcon#about to read 3, iclass 39, count 2 2006.210.07:41:58.59#ibcon#read 3, iclass 39, count 2 2006.210.07:41:58.59#ibcon#about to read 4, iclass 39, count 2 2006.210.07:41:58.59#ibcon#read 4, iclass 39, count 2 2006.210.07:41:58.59#ibcon#about to read 5, iclass 39, count 2 2006.210.07:41:58.59#ibcon#read 5, iclass 39, count 2 2006.210.07:41:58.59#ibcon#about to read 6, iclass 39, count 2 2006.210.07:41:58.59#ibcon#read 6, iclass 39, count 2 2006.210.07:41:58.59#ibcon#end of sib2, iclass 39, count 2 2006.210.07:41:58.59#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:41:58.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:41:58.59#ibcon#[25=AT04-07\r\n] 2006.210.07:41:58.59#ibcon#*before write, iclass 39, count 2 2006.210.07:41:58.59#ibcon#enter sib2, iclass 39, count 2 2006.210.07:41:58.59#ibcon#flushed, iclass 39, count 2 2006.210.07:41:58.59#ibcon#about to write, iclass 39, count 2 2006.210.07:41:58.59#ibcon#wrote, iclass 39, count 2 2006.210.07:41:58.59#ibcon#about to read 3, iclass 39, count 2 2006.210.07:41:58.62#ibcon#read 3, iclass 39, count 2 2006.210.07:41:58.62#ibcon#about to read 4, iclass 39, count 2 2006.210.07:41:58.62#ibcon#read 4, iclass 39, count 2 2006.210.07:41:58.62#ibcon#about to read 5, iclass 39, count 2 2006.210.07:41:58.62#ibcon#read 5, iclass 39, count 2 2006.210.07:41:58.62#ibcon#about to read 6, iclass 39, count 2 2006.210.07:41:58.62#ibcon#read 6, iclass 39, count 2 2006.210.07:41:58.62#ibcon#end of sib2, iclass 39, count 2 2006.210.07:41:58.62#ibcon#*after write, iclass 39, count 2 2006.210.07:41:58.62#ibcon#*before return 0, iclass 39, count 2 2006.210.07:41:58.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:41:58.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:41:58.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:41:58.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:58.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:41:58.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:41:58.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:41:58.74#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:41:58.74#ibcon#first serial, iclass 39, count 0 2006.210.07:41:58.74#ibcon#enter sib2, iclass 39, count 0 2006.210.07:41:58.74#ibcon#flushed, iclass 39, count 0 2006.210.07:41:58.74#ibcon#about to write, iclass 39, count 0 2006.210.07:41:58.74#ibcon#wrote, iclass 39, count 0 2006.210.07:41:58.74#ibcon#about to read 3, iclass 39, count 0 2006.210.07:41:58.76#ibcon#read 3, iclass 39, count 0 2006.210.07:41:58.76#ibcon#about to read 4, iclass 39, count 0 2006.210.07:41:58.76#ibcon#read 4, iclass 39, count 0 2006.210.07:41:58.76#ibcon#about to read 5, iclass 39, count 0 2006.210.07:41:58.76#ibcon#read 5, iclass 39, count 0 2006.210.07:41:58.76#ibcon#about to read 6, iclass 39, count 0 2006.210.07:41:58.76#ibcon#read 6, iclass 39, count 0 2006.210.07:41:58.76#ibcon#end of sib2, iclass 39, count 0 2006.210.07:41:58.76#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:41:58.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:41:58.76#ibcon#[25=USB\r\n] 2006.210.07:41:58.76#ibcon#*before write, iclass 39, count 0 2006.210.07:41:58.76#ibcon#enter sib2, iclass 39, count 0 2006.210.07:41:58.76#ibcon#flushed, iclass 39, count 0 2006.210.07:41:58.76#ibcon#about to write, iclass 39, count 0 2006.210.07:41:58.76#ibcon#wrote, iclass 39, count 0 2006.210.07:41:58.76#ibcon#about to read 3, iclass 39, count 0 2006.210.07:41:58.79#ibcon#read 3, iclass 39, count 0 2006.210.07:41:58.79#ibcon#about to read 4, iclass 39, count 0 2006.210.07:41:58.79#ibcon#read 4, iclass 39, count 0 2006.210.07:41:58.79#ibcon#about to read 5, iclass 39, count 0 2006.210.07:41:58.79#ibcon#read 5, iclass 39, count 0 2006.210.07:41:58.79#ibcon#about to read 6, iclass 39, count 0 2006.210.07:41:58.79#ibcon#read 6, iclass 39, count 0 2006.210.07:41:58.79#ibcon#end of sib2, iclass 39, count 0 2006.210.07:41:58.79#ibcon#*after write, iclass 39, count 0 2006.210.07:41:58.79#ibcon#*before return 0, iclass 39, count 0 2006.210.07:41:58.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:41:58.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:41:58.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:41:58.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:41:58.79$vc4f8/valo=5,652.99 2006.210.07:41:58.79#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:41:58.79#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:41:58.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:58.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:41:58.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:41:58.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:41:58.79#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:41:58.79#ibcon#first serial, iclass 3, count 0 2006.210.07:41:58.79#ibcon#enter sib2, iclass 3, count 0 2006.210.07:41:58.79#ibcon#flushed, iclass 3, count 0 2006.210.07:41:58.79#ibcon#about to write, iclass 3, count 0 2006.210.07:41:58.79#ibcon#wrote, iclass 3, count 0 2006.210.07:41:58.79#ibcon#about to read 3, iclass 3, count 0 2006.210.07:41:58.81#ibcon#read 3, iclass 3, count 0 2006.210.07:41:58.81#ibcon#about to read 4, iclass 3, count 0 2006.210.07:41:58.81#ibcon#read 4, iclass 3, count 0 2006.210.07:41:58.81#ibcon#about to read 5, iclass 3, count 0 2006.210.07:41:58.81#ibcon#read 5, iclass 3, count 0 2006.210.07:41:58.81#ibcon#about to read 6, iclass 3, count 0 2006.210.07:41:58.81#ibcon#read 6, iclass 3, count 0 2006.210.07:41:58.81#ibcon#end of sib2, iclass 3, count 0 2006.210.07:41:58.81#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:41:58.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:41:58.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:41:58.81#ibcon#*before write, iclass 3, count 0 2006.210.07:41:58.81#ibcon#enter sib2, iclass 3, count 0 2006.210.07:41:58.81#ibcon#flushed, iclass 3, count 0 2006.210.07:41:58.81#ibcon#about to write, iclass 3, count 0 2006.210.07:41:58.81#ibcon#wrote, iclass 3, count 0 2006.210.07:41:58.81#ibcon#about to read 3, iclass 3, count 0 2006.210.07:41:58.85#ibcon#read 3, iclass 3, count 0 2006.210.07:41:58.85#ibcon#about to read 4, iclass 3, count 0 2006.210.07:41:58.85#ibcon#read 4, iclass 3, count 0 2006.210.07:41:58.85#ibcon#about to read 5, iclass 3, count 0 2006.210.07:41:58.85#ibcon#read 5, iclass 3, count 0 2006.210.07:41:58.85#ibcon#about to read 6, iclass 3, count 0 2006.210.07:41:58.85#ibcon#read 6, iclass 3, count 0 2006.210.07:41:58.85#ibcon#end of sib2, iclass 3, count 0 2006.210.07:41:58.85#ibcon#*after write, iclass 3, count 0 2006.210.07:41:58.85#ibcon#*before return 0, iclass 3, count 0 2006.210.07:41:58.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:41:58.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:41:58.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:41:58.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:41:58.85$vc4f8/va=5,7 2006.210.07:41:58.85#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:41:58.85#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:41:58.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:58.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:41:58.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:41:58.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:41:58.91#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:41:58.91#ibcon#first serial, iclass 5, count 2 2006.210.07:41:58.91#ibcon#enter sib2, iclass 5, count 2 2006.210.07:41:58.91#ibcon#flushed, iclass 5, count 2 2006.210.07:41:58.91#ibcon#about to write, iclass 5, count 2 2006.210.07:41:58.91#ibcon#wrote, iclass 5, count 2 2006.210.07:41:58.91#ibcon#about to read 3, iclass 5, count 2 2006.210.07:41:58.93#ibcon#read 3, iclass 5, count 2 2006.210.07:41:58.93#ibcon#about to read 4, iclass 5, count 2 2006.210.07:41:58.93#ibcon#read 4, iclass 5, count 2 2006.210.07:41:58.93#ibcon#about to read 5, iclass 5, count 2 2006.210.07:41:58.93#ibcon#read 5, iclass 5, count 2 2006.210.07:41:58.93#ibcon#about to read 6, iclass 5, count 2 2006.210.07:41:58.93#ibcon#read 6, iclass 5, count 2 2006.210.07:41:58.93#ibcon#end of sib2, iclass 5, count 2 2006.210.07:41:58.93#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:41:58.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:41:58.93#ibcon#[25=AT05-07\r\n] 2006.210.07:41:58.93#ibcon#*before write, iclass 5, count 2 2006.210.07:41:58.93#ibcon#enter sib2, iclass 5, count 2 2006.210.07:41:58.93#ibcon#flushed, iclass 5, count 2 2006.210.07:41:58.93#ibcon#about to write, iclass 5, count 2 2006.210.07:41:58.93#ibcon#wrote, iclass 5, count 2 2006.210.07:41:58.93#ibcon#about to read 3, iclass 5, count 2 2006.210.07:41:58.96#ibcon#read 3, iclass 5, count 2 2006.210.07:41:58.96#ibcon#about to read 4, iclass 5, count 2 2006.210.07:41:58.96#ibcon#read 4, iclass 5, count 2 2006.210.07:41:58.96#ibcon#about to read 5, iclass 5, count 2 2006.210.07:41:58.96#ibcon#read 5, iclass 5, count 2 2006.210.07:41:58.96#ibcon#about to read 6, iclass 5, count 2 2006.210.07:41:58.96#ibcon#read 6, iclass 5, count 2 2006.210.07:41:58.96#ibcon#end of sib2, iclass 5, count 2 2006.210.07:41:58.96#ibcon#*after write, iclass 5, count 2 2006.210.07:41:58.96#ibcon#*before return 0, iclass 5, count 2 2006.210.07:41:58.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:41:58.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:41:58.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:41:58.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:58.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:41:59.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:41:59.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:41:59.08#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:41:59.08#ibcon#first serial, iclass 5, count 0 2006.210.07:41:59.08#ibcon#enter sib2, iclass 5, count 0 2006.210.07:41:59.08#ibcon#flushed, iclass 5, count 0 2006.210.07:41:59.08#ibcon#about to write, iclass 5, count 0 2006.210.07:41:59.08#ibcon#wrote, iclass 5, count 0 2006.210.07:41:59.08#ibcon#about to read 3, iclass 5, count 0 2006.210.07:41:59.10#ibcon#read 3, iclass 5, count 0 2006.210.07:41:59.10#ibcon#about to read 4, iclass 5, count 0 2006.210.07:41:59.10#ibcon#read 4, iclass 5, count 0 2006.210.07:41:59.10#ibcon#about to read 5, iclass 5, count 0 2006.210.07:41:59.10#ibcon#read 5, iclass 5, count 0 2006.210.07:41:59.10#ibcon#about to read 6, iclass 5, count 0 2006.210.07:41:59.10#ibcon#read 6, iclass 5, count 0 2006.210.07:41:59.10#ibcon#end of sib2, iclass 5, count 0 2006.210.07:41:59.10#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:41:59.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:41:59.10#ibcon#[25=USB\r\n] 2006.210.07:41:59.10#ibcon#*before write, iclass 5, count 0 2006.210.07:41:59.10#ibcon#enter sib2, iclass 5, count 0 2006.210.07:41:59.10#ibcon#flushed, iclass 5, count 0 2006.210.07:41:59.10#ibcon#about to write, iclass 5, count 0 2006.210.07:41:59.10#ibcon#wrote, iclass 5, count 0 2006.210.07:41:59.10#ibcon#about to read 3, iclass 5, count 0 2006.210.07:41:59.13#ibcon#read 3, iclass 5, count 0 2006.210.07:41:59.13#ibcon#about to read 4, iclass 5, count 0 2006.210.07:41:59.13#ibcon#read 4, iclass 5, count 0 2006.210.07:41:59.13#ibcon#about to read 5, iclass 5, count 0 2006.210.07:41:59.13#ibcon#read 5, iclass 5, count 0 2006.210.07:41:59.13#ibcon#about to read 6, iclass 5, count 0 2006.210.07:41:59.13#ibcon#read 6, iclass 5, count 0 2006.210.07:41:59.13#ibcon#end of sib2, iclass 5, count 0 2006.210.07:41:59.13#ibcon#*after write, iclass 5, count 0 2006.210.07:41:59.13#ibcon#*before return 0, iclass 5, count 0 2006.210.07:41:59.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:41:59.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:41:59.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:41:59.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:41:59.13$vc4f8/valo=6,772.99 2006.210.07:41:59.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:41:59.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:41:59.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:59.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:41:59.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:41:59.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:41:59.13#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:41:59.13#ibcon#first serial, iclass 7, count 0 2006.210.07:41:59.13#ibcon#enter sib2, iclass 7, count 0 2006.210.07:41:59.13#ibcon#flushed, iclass 7, count 0 2006.210.07:41:59.13#ibcon#about to write, iclass 7, count 0 2006.210.07:41:59.13#ibcon#wrote, iclass 7, count 0 2006.210.07:41:59.13#ibcon#about to read 3, iclass 7, count 0 2006.210.07:41:59.15#ibcon#read 3, iclass 7, count 0 2006.210.07:41:59.15#ibcon#about to read 4, iclass 7, count 0 2006.210.07:41:59.15#ibcon#read 4, iclass 7, count 0 2006.210.07:41:59.15#ibcon#about to read 5, iclass 7, count 0 2006.210.07:41:59.15#ibcon#read 5, iclass 7, count 0 2006.210.07:41:59.15#ibcon#about to read 6, iclass 7, count 0 2006.210.07:41:59.15#ibcon#read 6, iclass 7, count 0 2006.210.07:41:59.15#ibcon#end of sib2, iclass 7, count 0 2006.210.07:41:59.15#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:41:59.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:41:59.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:41:59.15#ibcon#*before write, iclass 7, count 0 2006.210.07:41:59.15#ibcon#enter sib2, iclass 7, count 0 2006.210.07:41:59.15#ibcon#flushed, iclass 7, count 0 2006.210.07:41:59.15#ibcon#about to write, iclass 7, count 0 2006.210.07:41:59.15#ibcon#wrote, iclass 7, count 0 2006.210.07:41:59.15#ibcon#about to read 3, iclass 7, count 0 2006.210.07:41:59.19#ibcon#read 3, iclass 7, count 0 2006.210.07:41:59.19#ibcon#about to read 4, iclass 7, count 0 2006.210.07:41:59.19#ibcon#read 4, iclass 7, count 0 2006.210.07:41:59.19#ibcon#about to read 5, iclass 7, count 0 2006.210.07:41:59.19#ibcon#read 5, iclass 7, count 0 2006.210.07:41:59.19#ibcon#about to read 6, iclass 7, count 0 2006.210.07:41:59.19#ibcon#read 6, iclass 7, count 0 2006.210.07:41:59.19#ibcon#end of sib2, iclass 7, count 0 2006.210.07:41:59.19#ibcon#*after write, iclass 7, count 0 2006.210.07:41:59.19#ibcon#*before return 0, iclass 7, count 0 2006.210.07:41:59.19#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:41:59.19#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:41:59.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:41:59.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:41:59.19$vc4f8/va=6,6 2006.210.07:41:59.19#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:41:59.19#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:41:59.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:59.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:41:59.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:41:59.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:41:59.25#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:41:59.25#ibcon#first serial, iclass 11, count 2 2006.210.07:41:59.25#ibcon#enter sib2, iclass 11, count 2 2006.210.07:41:59.25#ibcon#flushed, iclass 11, count 2 2006.210.07:41:59.25#ibcon#about to write, iclass 11, count 2 2006.210.07:41:59.25#ibcon#wrote, iclass 11, count 2 2006.210.07:41:59.25#ibcon#about to read 3, iclass 11, count 2 2006.210.07:41:59.27#ibcon#read 3, iclass 11, count 2 2006.210.07:41:59.27#ibcon#about to read 4, iclass 11, count 2 2006.210.07:41:59.27#ibcon#read 4, iclass 11, count 2 2006.210.07:41:59.27#ibcon#about to read 5, iclass 11, count 2 2006.210.07:41:59.27#ibcon#read 5, iclass 11, count 2 2006.210.07:41:59.27#ibcon#about to read 6, iclass 11, count 2 2006.210.07:41:59.27#ibcon#read 6, iclass 11, count 2 2006.210.07:41:59.27#ibcon#end of sib2, iclass 11, count 2 2006.210.07:41:59.27#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:41:59.27#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:41:59.27#ibcon#[25=AT06-06\r\n] 2006.210.07:41:59.27#ibcon#*before write, iclass 11, count 2 2006.210.07:41:59.27#ibcon#enter sib2, iclass 11, count 2 2006.210.07:41:59.27#ibcon#flushed, iclass 11, count 2 2006.210.07:41:59.27#ibcon#about to write, iclass 11, count 2 2006.210.07:41:59.27#ibcon#wrote, iclass 11, count 2 2006.210.07:41:59.27#ibcon#about to read 3, iclass 11, count 2 2006.210.07:41:59.30#ibcon#read 3, iclass 11, count 2 2006.210.07:41:59.30#ibcon#about to read 4, iclass 11, count 2 2006.210.07:41:59.30#ibcon#read 4, iclass 11, count 2 2006.210.07:41:59.30#ibcon#about to read 5, iclass 11, count 2 2006.210.07:41:59.30#ibcon#read 5, iclass 11, count 2 2006.210.07:41:59.30#ibcon#about to read 6, iclass 11, count 2 2006.210.07:41:59.30#ibcon#read 6, iclass 11, count 2 2006.210.07:41:59.30#ibcon#end of sib2, iclass 11, count 2 2006.210.07:41:59.30#ibcon#*after write, iclass 11, count 2 2006.210.07:41:59.30#ibcon#*before return 0, iclass 11, count 2 2006.210.07:41:59.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:41:59.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:41:59.30#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:41:59.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:59.30#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:41:59.42#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:41:59.42#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:41:59.42#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:41:59.42#ibcon#first serial, iclass 11, count 0 2006.210.07:41:59.42#ibcon#enter sib2, iclass 11, count 0 2006.210.07:41:59.42#ibcon#flushed, iclass 11, count 0 2006.210.07:41:59.42#ibcon#about to write, iclass 11, count 0 2006.210.07:41:59.42#ibcon#wrote, iclass 11, count 0 2006.210.07:41:59.42#ibcon#about to read 3, iclass 11, count 0 2006.210.07:41:59.44#ibcon#read 3, iclass 11, count 0 2006.210.07:41:59.44#ibcon#about to read 4, iclass 11, count 0 2006.210.07:41:59.44#ibcon#read 4, iclass 11, count 0 2006.210.07:41:59.44#ibcon#about to read 5, iclass 11, count 0 2006.210.07:41:59.44#ibcon#read 5, iclass 11, count 0 2006.210.07:41:59.44#ibcon#about to read 6, iclass 11, count 0 2006.210.07:41:59.44#ibcon#read 6, iclass 11, count 0 2006.210.07:41:59.44#ibcon#end of sib2, iclass 11, count 0 2006.210.07:41:59.44#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:41:59.44#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:41:59.44#ibcon#[25=USB\r\n] 2006.210.07:41:59.44#ibcon#*before write, iclass 11, count 0 2006.210.07:41:59.44#ibcon#enter sib2, iclass 11, count 0 2006.210.07:41:59.44#ibcon#flushed, iclass 11, count 0 2006.210.07:41:59.44#ibcon#about to write, iclass 11, count 0 2006.210.07:41:59.44#ibcon#wrote, iclass 11, count 0 2006.210.07:41:59.44#ibcon#about to read 3, iclass 11, count 0 2006.210.07:41:59.47#ibcon#read 3, iclass 11, count 0 2006.210.07:41:59.47#ibcon#about to read 4, iclass 11, count 0 2006.210.07:41:59.47#ibcon#read 4, iclass 11, count 0 2006.210.07:41:59.47#ibcon#about to read 5, iclass 11, count 0 2006.210.07:41:59.47#ibcon#read 5, iclass 11, count 0 2006.210.07:41:59.47#ibcon#about to read 6, iclass 11, count 0 2006.210.07:41:59.47#ibcon#read 6, iclass 11, count 0 2006.210.07:41:59.47#ibcon#end of sib2, iclass 11, count 0 2006.210.07:41:59.47#ibcon#*after write, iclass 11, count 0 2006.210.07:41:59.47#ibcon#*before return 0, iclass 11, count 0 2006.210.07:41:59.47#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:41:59.47#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:41:59.47#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:41:59.47#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:41:59.47$vc4f8/valo=7,832.99 2006.210.07:41:59.47#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:41:59.47#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:41:59.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:59.47#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:41:59.47#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:41:59.47#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:41:59.47#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:41:59.47#ibcon#first serial, iclass 13, count 0 2006.210.07:41:59.47#ibcon#enter sib2, iclass 13, count 0 2006.210.07:41:59.47#ibcon#flushed, iclass 13, count 0 2006.210.07:41:59.47#ibcon#about to write, iclass 13, count 0 2006.210.07:41:59.47#ibcon#wrote, iclass 13, count 0 2006.210.07:41:59.47#ibcon#about to read 3, iclass 13, count 0 2006.210.07:41:59.49#ibcon#read 3, iclass 13, count 0 2006.210.07:41:59.49#ibcon#about to read 4, iclass 13, count 0 2006.210.07:41:59.49#ibcon#read 4, iclass 13, count 0 2006.210.07:41:59.49#ibcon#about to read 5, iclass 13, count 0 2006.210.07:41:59.49#ibcon#read 5, iclass 13, count 0 2006.210.07:41:59.49#ibcon#about to read 6, iclass 13, count 0 2006.210.07:41:59.49#ibcon#read 6, iclass 13, count 0 2006.210.07:41:59.49#ibcon#end of sib2, iclass 13, count 0 2006.210.07:41:59.49#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:41:59.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:41:59.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:41:59.49#ibcon#*before write, iclass 13, count 0 2006.210.07:41:59.49#ibcon#enter sib2, iclass 13, count 0 2006.210.07:41:59.49#ibcon#flushed, iclass 13, count 0 2006.210.07:41:59.49#ibcon#about to write, iclass 13, count 0 2006.210.07:41:59.49#ibcon#wrote, iclass 13, count 0 2006.210.07:41:59.49#ibcon#about to read 3, iclass 13, count 0 2006.210.07:41:59.53#ibcon#read 3, iclass 13, count 0 2006.210.07:41:59.53#ibcon#about to read 4, iclass 13, count 0 2006.210.07:41:59.53#ibcon#read 4, iclass 13, count 0 2006.210.07:41:59.53#ibcon#about to read 5, iclass 13, count 0 2006.210.07:41:59.53#ibcon#read 5, iclass 13, count 0 2006.210.07:41:59.53#ibcon#about to read 6, iclass 13, count 0 2006.210.07:41:59.53#ibcon#read 6, iclass 13, count 0 2006.210.07:41:59.53#ibcon#end of sib2, iclass 13, count 0 2006.210.07:41:59.53#ibcon#*after write, iclass 13, count 0 2006.210.07:41:59.53#ibcon#*before return 0, iclass 13, count 0 2006.210.07:41:59.53#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:41:59.53#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:41:59.53#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:41:59.53#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:41:59.53$vc4f8/va=7,6 2006.210.07:41:59.53#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:41:59.53#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:41:59.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:59.53#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:41:59.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:41:59.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:41:59.59#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:41:59.59#ibcon#first serial, iclass 15, count 2 2006.210.07:41:59.59#ibcon#enter sib2, iclass 15, count 2 2006.210.07:41:59.59#ibcon#flushed, iclass 15, count 2 2006.210.07:41:59.59#ibcon#about to write, iclass 15, count 2 2006.210.07:41:59.59#ibcon#wrote, iclass 15, count 2 2006.210.07:41:59.59#ibcon#about to read 3, iclass 15, count 2 2006.210.07:41:59.61#ibcon#read 3, iclass 15, count 2 2006.210.07:41:59.61#ibcon#about to read 4, iclass 15, count 2 2006.210.07:41:59.61#ibcon#read 4, iclass 15, count 2 2006.210.07:41:59.61#ibcon#about to read 5, iclass 15, count 2 2006.210.07:41:59.61#ibcon#read 5, iclass 15, count 2 2006.210.07:41:59.61#ibcon#about to read 6, iclass 15, count 2 2006.210.07:41:59.61#ibcon#read 6, iclass 15, count 2 2006.210.07:41:59.61#ibcon#end of sib2, iclass 15, count 2 2006.210.07:41:59.61#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:41:59.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:41:59.61#ibcon#[25=AT07-06\r\n] 2006.210.07:41:59.61#ibcon#*before write, iclass 15, count 2 2006.210.07:41:59.61#ibcon#enter sib2, iclass 15, count 2 2006.210.07:41:59.61#ibcon#flushed, iclass 15, count 2 2006.210.07:41:59.61#ibcon#about to write, iclass 15, count 2 2006.210.07:41:59.61#ibcon#wrote, iclass 15, count 2 2006.210.07:41:59.61#ibcon#about to read 3, iclass 15, count 2 2006.210.07:41:59.64#ibcon#read 3, iclass 15, count 2 2006.210.07:41:59.64#ibcon#about to read 4, iclass 15, count 2 2006.210.07:41:59.64#ibcon#read 4, iclass 15, count 2 2006.210.07:41:59.64#ibcon#about to read 5, iclass 15, count 2 2006.210.07:41:59.64#ibcon#read 5, iclass 15, count 2 2006.210.07:41:59.64#ibcon#about to read 6, iclass 15, count 2 2006.210.07:41:59.64#ibcon#read 6, iclass 15, count 2 2006.210.07:41:59.64#ibcon#end of sib2, iclass 15, count 2 2006.210.07:41:59.64#ibcon#*after write, iclass 15, count 2 2006.210.07:41:59.64#ibcon#*before return 0, iclass 15, count 2 2006.210.07:41:59.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:41:59.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:41:59.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:41:59.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:59.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:41:59.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:41:59.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:41:59.76#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:41:59.76#ibcon#first serial, iclass 15, count 0 2006.210.07:41:59.76#ibcon#enter sib2, iclass 15, count 0 2006.210.07:41:59.76#ibcon#flushed, iclass 15, count 0 2006.210.07:41:59.76#ibcon#about to write, iclass 15, count 0 2006.210.07:41:59.76#ibcon#wrote, iclass 15, count 0 2006.210.07:41:59.76#ibcon#about to read 3, iclass 15, count 0 2006.210.07:41:59.78#ibcon#read 3, iclass 15, count 0 2006.210.07:41:59.78#ibcon#about to read 4, iclass 15, count 0 2006.210.07:41:59.78#ibcon#read 4, iclass 15, count 0 2006.210.07:41:59.78#ibcon#about to read 5, iclass 15, count 0 2006.210.07:41:59.78#ibcon#read 5, iclass 15, count 0 2006.210.07:41:59.78#ibcon#about to read 6, iclass 15, count 0 2006.210.07:41:59.78#ibcon#read 6, iclass 15, count 0 2006.210.07:41:59.78#ibcon#end of sib2, iclass 15, count 0 2006.210.07:41:59.78#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:41:59.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:41:59.78#ibcon#[25=USB\r\n] 2006.210.07:41:59.78#ibcon#*before write, iclass 15, count 0 2006.210.07:41:59.78#ibcon#enter sib2, iclass 15, count 0 2006.210.07:41:59.78#ibcon#flushed, iclass 15, count 0 2006.210.07:41:59.78#ibcon#about to write, iclass 15, count 0 2006.210.07:41:59.78#ibcon#wrote, iclass 15, count 0 2006.210.07:41:59.78#ibcon#about to read 3, iclass 15, count 0 2006.210.07:41:59.81#ibcon#read 3, iclass 15, count 0 2006.210.07:41:59.81#ibcon#about to read 4, iclass 15, count 0 2006.210.07:41:59.81#ibcon#read 4, iclass 15, count 0 2006.210.07:41:59.81#ibcon#about to read 5, iclass 15, count 0 2006.210.07:41:59.81#ibcon#read 5, iclass 15, count 0 2006.210.07:41:59.81#ibcon#about to read 6, iclass 15, count 0 2006.210.07:41:59.81#ibcon#read 6, iclass 15, count 0 2006.210.07:41:59.81#ibcon#end of sib2, iclass 15, count 0 2006.210.07:41:59.81#ibcon#*after write, iclass 15, count 0 2006.210.07:41:59.81#ibcon#*before return 0, iclass 15, count 0 2006.210.07:41:59.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:41:59.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:41:59.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:41:59.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:41:59.81$vc4f8/valo=8,852.99 2006.210.07:41:59.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:41:59.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:41:59.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:41:59.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:41:59.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:41:59.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:41:59.81#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:41:59.81#ibcon#first serial, iclass 17, count 0 2006.210.07:41:59.81#ibcon#enter sib2, iclass 17, count 0 2006.210.07:41:59.81#ibcon#flushed, iclass 17, count 0 2006.210.07:41:59.81#ibcon#about to write, iclass 17, count 0 2006.210.07:41:59.81#ibcon#wrote, iclass 17, count 0 2006.210.07:41:59.81#ibcon#about to read 3, iclass 17, count 0 2006.210.07:41:59.83#ibcon#read 3, iclass 17, count 0 2006.210.07:41:59.83#ibcon#about to read 4, iclass 17, count 0 2006.210.07:41:59.83#ibcon#read 4, iclass 17, count 0 2006.210.07:41:59.83#ibcon#about to read 5, iclass 17, count 0 2006.210.07:41:59.83#ibcon#read 5, iclass 17, count 0 2006.210.07:41:59.83#ibcon#about to read 6, iclass 17, count 0 2006.210.07:41:59.83#ibcon#read 6, iclass 17, count 0 2006.210.07:41:59.83#ibcon#end of sib2, iclass 17, count 0 2006.210.07:41:59.83#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:41:59.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:41:59.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:41:59.83#ibcon#*before write, iclass 17, count 0 2006.210.07:41:59.83#ibcon#enter sib2, iclass 17, count 0 2006.210.07:41:59.83#ibcon#flushed, iclass 17, count 0 2006.210.07:41:59.83#ibcon#about to write, iclass 17, count 0 2006.210.07:41:59.83#ibcon#wrote, iclass 17, count 0 2006.210.07:41:59.83#ibcon#about to read 3, iclass 17, count 0 2006.210.07:41:59.87#ibcon#read 3, iclass 17, count 0 2006.210.07:41:59.87#ibcon#about to read 4, iclass 17, count 0 2006.210.07:41:59.87#ibcon#read 4, iclass 17, count 0 2006.210.07:41:59.87#ibcon#about to read 5, iclass 17, count 0 2006.210.07:41:59.87#ibcon#read 5, iclass 17, count 0 2006.210.07:41:59.87#ibcon#about to read 6, iclass 17, count 0 2006.210.07:41:59.87#ibcon#read 6, iclass 17, count 0 2006.210.07:41:59.87#ibcon#end of sib2, iclass 17, count 0 2006.210.07:41:59.87#ibcon#*after write, iclass 17, count 0 2006.210.07:41:59.87#ibcon#*before return 0, iclass 17, count 0 2006.210.07:41:59.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:41:59.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:41:59.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:41:59.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:41:59.87$vc4f8/va=8,7 2006.210.07:41:59.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:41:59.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:41:59.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:41:59.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:41:59.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:41:59.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:41:59.93#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:41:59.93#ibcon#first serial, iclass 19, count 2 2006.210.07:41:59.93#ibcon#enter sib2, iclass 19, count 2 2006.210.07:41:59.93#ibcon#flushed, iclass 19, count 2 2006.210.07:41:59.93#ibcon#about to write, iclass 19, count 2 2006.210.07:41:59.93#ibcon#wrote, iclass 19, count 2 2006.210.07:41:59.93#ibcon#about to read 3, iclass 19, count 2 2006.210.07:41:59.95#ibcon#read 3, iclass 19, count 2 2006.210.07:41:59.95#ibcon#about to read 4, iclass 19, count 2 2006.210.07:41:59.95#ibcon#read 4, iclass 19, count 2 2006.210.07:41:59.95#ibcon#about to read 5, iclass 19, count 2 2006.210.07:41:59.95#ibcon#read 5, iclass 19, count 2 2006.210.07:41:59.95#ibcon#about to read 6, iclass 19, count 2 2006.210.07:41:59.95#ibcon#read 6, iclass 19, count 2 2006.210.07:41:59.95#ibcon#end of sib2, iclass 19, count 2 2006.210.07:41:59.95#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:41:59.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:41:59.95#ibcon#[25=AT08-07\r\n] 2006.210.07:41:59.95#ibcon#*before write, iclass 19, count 2 2006.210.07:41:59.95#ibcon#enter sib2, iclass 19, count 2 2006.210.07:41:59.95#ibcon#flushed, iclass 19, count 2 2006.210.07:41:59.95#ibcon#about to write, iclass 19, count 2 2006.210.07:41:59.95#ibcon#wrote, iclass 19, count 2 2006.210.07:41:59.95#ibcon#about to read 3, iclass 19, count 2 2006.210.07:41:59.98#ibcon#read 3, iclass 19, count 2 2006.210.07:41:59.98#ibcon#about to read 4, iclass 19, count 2 2006.210.07:41:59.98#ibcon#read 4, iclass 19, count 2 2006.210.07:41:59.98#ibcon#about to read 5, iclass 19, count 2 2006.210.07:41:59.98#ibcon#read 5, iclass 19, count 2 2006.210.07:41:59.98#ibcon#about to read 6, iclass 19, count 2 2006.210.07:41:59.98#ibcon#read 6, iclass 19, count 2 2006.210.07:41:59.98#ibcon#end of sib2, iclass 19, count 2 2006.210.07:41:59.98#ibcon#*after write, iclass 19, count 2 2006.210.07:41:59.98#ibcon#*before return 0, iclass 19, count 2 2006.210.07:41:59.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:41:59.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:41:59.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:41:59.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:41:59.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:42:00.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:42:00.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:42:00.10#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:42:00.10#ibcon#first serial, iclass 19, count 0 2006.210.07:42:00.10#ibcon#enter sib2, iclass 19, count 0 2006.210.07:42:00.10#ibcon#flushed, iclass 19, count 0 2006.210.07:42:00.10#ibcon#about to write, iclass 19, count 0 2006.210.07:42:00.10#ibcon#wrote, iclass 19, count 0 2006.210.07:42:00.10#ibcon#about to read 3, iclass 19, count 0 2006.210.07:42:00.12#ibcon#read 3, iclass 19, count 0 2006.210.07:42:00.12#ibcon#about to read 4, iclass 19, count 0 2006.210.07:42:00.12#ibcon#read 4, iclass 19, count 0 2006.210.07:42:00.12#ibcon#about to read 5, iclass 19, count 0 2006.210.07:42:00.12#ibcon#read 5, iclass 19, count 0 2006.210.07:42:00.12#ibcon#about to read 6, iclass 19, count 0 2006.210.07:42:00.12#ibcon#read 6, iclass 19, count 0 2006.210.07:42:00.12#ibcon#end of sib2, iclass 19, count 0 2006.210.07:42:00.12#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:42:00.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:42:00.12#ibcon#[25=USB\r\n] 2006.210.07:42:00.12#ibcon#*before write, iclass 19, count 0 2006.210.07:42:00.12#ibcon#enter sib2, iclass 19, count 0 2006.210.07:42:00.12#ibcon#flushed, iclass 19, count 0 2006.210.07:42:00.12#ibcon#about to write, iclass 19, count 0 2006.210.07:42:00.12#ibcon#wrote, iclass 19, count 0 2006.210.07:42:00.12#ibcon#about to read 3, iclass 19, count 0 2006.210.07:42:00.15#ibcon#read 3, iclass 19, count 0 2006.210.07:42:00.15#ibcon#about to read 4, iclass 19, count 0 2006.210.07:42:00.15#ibcon#read 4, iclass 19, count 0 2006.210.07:42:00.15#ibcon#about to read 5, iclass 19, count 0 2006.210.07:42:00.15#ibcon#read 5, iclass 19, count 0 2006.210.07:42:00.15#ibcon#about to read 6, iclass 19, count 0 2006.210.07:42:00.15#ibcon#read 6, iclass 19, count 0 2006.210.07:42:00.15#ibcon#end of sib2, iclass 19, count 0 2006.210.07:42:00.15#ibcon#*after write, iclass 19, count 0 2006.210.07:42:00.15#ibcon#*before return 0, iclass 19, count 0 2006.210.07:42:00.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:42:00.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:42:00.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:42:00.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:42:00.15$vc4f8/vblo=1,632.99 2006.210.07:42:00.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:42:00.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:42:00.15#ibcon#ireg 17 cls_cnt 0 2006.210.07:42:00.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:42:00.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:42:00.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:42:00.15#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:42:00.15#ibcon#first serial, iclass 21, count 0 2006.210.07:42:00.15#ibcon#enter sib2, iclass 21, count 0 2006.210.07:42:00.15#ibcon#flushed, iclass 21, count 0 2006.210.07:42:00.15#ibcon#about to write, iclass 21, count 0 2006.210.07:42:00.15#ibcon#wrote, iclass 21, count 0 2006.210.07:42:00.15#ibcon#about to read 3, iclass 21, count 0 2006.210.07:42:00.17#ibcon#read 3, iclass 21, count 0 2006.210.07:42:00.17#ibcon#about to read 4, iclass 21, count 0 2006.210.07:42:00.17#ibcon#read 4, iclass 21, count 0 2006.210.07:42:00.17#ibcon#about to read 5, iclass 21, count 0 2006.210.07:42:00.17#ibcon#read 5, iclass 21, count 0 2006.210.07:42:00.17#ibcon#about to read 6, iclass 21, count 0 2006.210.07:42:00.17#ibcon#read 6, iclass 21, count 0 2006.210.07:42:00.17#ibcon#end of sib2, iclass 21, count 0 2006.210.07:42:00.17#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:42:00.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:42:00.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:42:00.17#ibcon#*before write, iclass 21, count 0 2006.210.07:42:00.17#ibcon#enter sib2, iclass 21, count 0 2006.210.07:42:00.17#ibcon#flushed, iclass 21, count 0 2006.210.07:42:00.17#ibcon#about to write, iclass 21, count 0 2006.210.07:42:00.17#ibcon#wrote, iclass 21, count 0 2006.210.07:42:00.17#ibcon#about to read 3, iclass 21, count 0 2006.210.07:42:00.21#ibcon#read 3, iclass 21, count 0 2006.210.07:42:00.21#ibcon#about to read 4, iclass 21, count 0 2006.210.07:42:00.21#ibcon#read 4, iclass 21, count 0 2006.210.07:42:00.21#ibcon#about to read 5, iclass 21, count 0 2006.210.07:42:00.21#ibcon#read 5, iclass 21, count 0 2006.210.07:42:00.21#ibcon#about to read 6, iclass 21, count 0 2006.210.07:42:00.21#ibcon#read 6, iclass 21, count 0 2006.210.07:42:00.21#ibcon#end of sib2, iclass 21, count 0 2006.210.07:42:00.21#ibcon#*after write, iclass 21, count 0 2006.210.07:42:00.21#ibcon#*before return 0, iclass 21, count 0 2006.210.07:42:00.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:42:00.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:42:00.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:42:00.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:42:00.21$vc4f8/vb=1,4 2006.210.07:42:00.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.07:42:00.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.07:42:00.21#ibcon#ireg 11 cls_cnt 2 2006.210.07:42:00.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:42:00.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:42:00.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:42:00.21#ibcon#enter wrdev, iclass 23, count 2 2006.210.07:42:00.21#ibcon#first serial, iclass 23, count 2 2006.210.07:42:00.21#ibcon#enter sib2, iclass 23, count 2 2006.210.07:42:00.21#ibcon#flushed, iclass 23, count 2 2006.210.07:42:00.21#ibcon#about to write, iclass 23, count 2 2006.210.07:42:00.21#ibcon#wrote, iclass 23, count 2 2006.210.07:42:00.21#ibcon#about to read 3, iclass 23, count 2 2006.210.07:42:00.23#ibcon#read 3, iclass 23, count 2 2006.210.07:42:00.23#ibcon#about to read 4, iclass 23, count 2 2006.210.07:42:00.23#ibcon#read 4, iclass 23, count 2 2006.210.07:42:00.23#ibcon#about to read 5, iclass 23, count 2 2006.210.07:42:00.23#ibcon#read 5, iclass 23, count 2 2006.210.07:42:00.23#ibcon#about to read 6, iclass 23, count 2 2006.210.07:42:00.23#ibcon#read 6, iclass 23, count 2 2006.210.07:42:00.23#ibcon#end of sib2, iclass 23, count 2 2006.210.07:42:00.23#ibcon#*mode == 0, iclass 23, count 2 2006.210.07:42:00.23#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.07:42:00.23#ibcon#[27=AT01-04\r\n] 2006.210.07:42:00.23#ibcon#*before write, iclass 23, count 2 2006.210.07:42:00.23#ibcon#enter sib2, iclass 23, count 2 2006.210.07:42:00.23#ibcon#flushed, iclass 23, count 2 2006.210.07:42:00.23#ibcon#about to write, iclass 23, count 2 2006.210.07:42:00.23#ibcon#wrote, iclass 23, count 2 2006.210.07:42:00.23#ibcon#about to read 3, iclass 23, count 2 2006.210.07:42:00.26#ibcon#read 3, iclass 23, count 2 2006.210.07:42:00.26#ibcon#about to read 4, iclass 23, count 2 2006.210.07:42:00.26#ibcon#read 4, iclass 23, count 2 2006.210.07:42:00.26#ibcon#about to read 5, iclass 23, count 2 2006.210.07:42:00.26#ibcon#read 5, iclass 23, count 2 2006.210.07:42:00.26#ibcon#about to read 6, iclass 23, count 2 2006.210.07:42:00.26#ibcon#read 6, iclass 23, count 2 2006.210.07:42:00.26#ibcon#end of sib2, iclass 23, count 2 2006.210.07:42:00.26#ibcon#*after write, iclass 23, count 2 2006.210.07:42:00.26#ibcon#*before return 0, iclass 23, count 2 2006.210.07:42:00.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:42:00.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:42:00.26#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.07:42:00.26#ibcon#ireg 7 cls_cnt 0 2006.210.07:42:00.26#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:42:00.38#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:42:00.38#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:42:00.38#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:42:00.38#ibcon#first serial, iclass 23, count 0 2006.210.07:42:00.38#ibcon#enter sib2, iclass 23, count 0 2006.210.07:42:00.38#ibcon#flushed, iclass 23, count 0 2006.210.07:42:00.38#ibcon#about to write, iclass 23, count 0 2006.210.07:42:00.38#ibcon#wrote, iclass 23, count 0 2006.210.07:42:00.38#ibcon#about to read 3, iclass 23, count 0 2006.210.07:42:00.40#ibcon#read 3, iclass 23, count 0 2006.210.07:42:00.40#ibcon#about to read 4, iclass 23, count 0 2006.210.07:42:00.40#ibcon#read 4, iclass 23, count 0 2006.210.07:42:00.40#ibcon#about to read 5, iclass 23, count 0 2006.210.07:42:00.40#ibcon#read 5, iclass 23, count 0 2006.210.07:42:00.40#ibcon#about to read 6, iclass 23, count 0 2006.210.07:42:00.40#ibcon#read 6, iclass 23, count 0 2006.210.07:42:00.40#ibcon#end of sib2, iclass 23, count 0 2006.210.07:42:00.40#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:42:00.40#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:42:00.40#ibcon#[27=USB\r\n] 2006.210.07:42:00.40#ibcon#*before write, iclass 23, count 0 2006.210.07:42:00.40#ibcon#enter sib2, iclass 23, count 0 2006.210.07:42:00.40#ibcon#flushed, iclass 23, count 0 2006.210.07:42:00.40#ibcon#about to write, iclass 23, count 0 2006.210.07:42:00.40#ibcon#wrote, iclass 23, count 0 2006.210.07:42:00.40#ibcon#about to read 3, iclass 23, count 0 2006.210.07:42:00.43#ibcon#read 3, iclass 23, count 0 2006.210.07:42:00.43#ibcon#about to read 4, iclass 23, count 0 2006.210.07:42:00.43#ibcon#read 4, iclass 23, count 0 2006.210.07:42:00.43#ibcon#about to read 5, iclass 23, count 0 2006.210.07:42:00.43#ibcon#read 5, iclass 23, count 0 2006.210.07:42:00.43#ibcon#about to read 6, iclass 23, count 0 2006.210.07:42:00.43#ibcon#read 6, iclass 23, count 0 2006.210.07:42:00.43#ibcon#end of sib2, iclass 23, count 0 2006.210.07:42:00.43#ibcon#*after write, iclass 23, count 0 2006.210.07:42:00.43#ibcon#*before return 0, iclass 23, count 0 2006.210.07:42:00.43#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:42:00.43#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:42:00.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:42:00.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:42:00.43$vc4f8/vblo=2,640.99 2006.210.07:42:00.43#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.07:42:00.43#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.07:42:00.43#ibcon#ireg 17 cls_cnt 0 2006.210.07:42:00.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:42:00.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:42:00.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:42:00.43#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:42:00.43#ibcon#first serial, iclass 25, count 0 2006.210.07:42:00.43#ibcon#enter sib2, iclass 25, count 0 2006.210.07:42:00.43#ibcon#flushed, iclass 25, count 0 2006.210.07:42:00.43#ibcon#about to write, iclass 25, count 0 2006.210.07:42:00.43#ibcon#wrote, iclass 25, count 0 2006.210.07:42:00.43#ibcon#about to read 3, iclass 25, count 0 2006.210.07:42:00.45#ibcon#read 3, iclass 25, count 0 2006.210.07:42:00.45#ibcon#about to read 4, iclass 25, count 0 2006.210.07:42:00.45#ibcon#read 4, iclass 25, count 0 2006.210.07:42:00.45#ibcon#about to read 5, iclass 25, count 0 2006.210.07:42:00.45#ibcon#read 5, iclass 25, count 0 2006.210.07:42:00.45#ibcon#about to read 6, iclass 25, count 0 2006.210.07:42:00.45#ibcon#read 6, iclass 25, count 0 2006.210.07:42:00.45#ibcon#end of sib2, iclass 25, count 0 2006.210.07:42:00.45#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:42:00.45#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:42:00.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:42:00.45#ibcon#*before write, iclass 25, count 0 2006.210.07:42:00.45#ibcon#enter sib2, iclass 25, count 0 2006.210.07:42:00.45#ibcon#flushed, iclass 25, count 0 2006.210.07:42:00.45#ibcon#about to write, iclass 25, count 0 2006.210.07:42:00.45#ibcon#wrote, iclass 25, count 0 2006.210.07:42:00.45#ibcon#about to read 3, iclass 25, count 0 2006.210.07:42:00.49#ibcon#read 3, iclass 25, count 0 2006.210.07:42:00.49#ibcon#about to read 4, iclass 25, count 0 2006.210.07:42:00.49#ibcon#read 4, iclass 25, count 0 2006.210.07:42:00.49#ibcon#about to read 5, iclass 25, count 0 2006.210.07:42:00.49#ibcon#read 5, iclass 25, count 0 2006.210.07:42:00.49#ibcon#about to read 6, iclass 25, count 0 2006.210.07:42:00.49#ibcon#read 6, iclass 25, count 0 2006.210.07:42:00.49#ibcon#end of sib2, iclass 25, count 0 2006.210.07:42:00.49#ibcon#*after write, iclass 25, count 0 2006.210.07:42:00.49#ibcon#*before return 0, iclass 25, count 0 2006.210.07:42:00.49#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:42:00.49#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:42:00.49#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:42:00.49#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:42:00.49$vc4f8/vb=2,4 2006.210.07:42:00.49#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.07:42:00.49#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.07:42:00.49#ibcon#ireg 11 cls_cnt 2 2006.210.07:42:00.49#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:42:00.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:42:00.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:42:00.55#ibcon#enter wrdev, iclass 27, count 2 2006.210.07:42:00.55#ibcon#first serial, iclass 27, count 2 2006.210.07:42:00.55#ibcon#enter sib2, iclass 27, count 2 2006.210.07:42:00.55#ibcon#flushed, iclass 27, count 2 2006.210.07:42:00.55#ibcon#about to write, iclass 27, count 2 2006.210.07:42:00.55#ibcon#wrote, iclass 27, count 2 2006.210.07:42:00.55#ibcon#about to read 3, iclass 27, count 2 2006.210.07:42:00.57#ibcon#read 3, iclass 27, count 2 2006.210.07:42:00.57#ibcon#about to read 4, iclass 27, count 2 2006.210.07:42:00.57#ibcon#read 4, iclass 27, count 2 2006.210.07:42:00.57#ibcon#about to read 5, iclass 27, count 2 2006.210.07:42:00.57#ibcon#read 5, iclass 27, count 2 2006.210.07:42:00.57#ibcon#about to read 6, iclass 27, count 2 2006.210.07:42:00.57#ibcon#read 6, iclass 27, count 2 2006.210.07:42:00.57#ibcon#end of sib2, iclass 27, count 2 2006.210.07:42:00.57#ibcon#*mode == 0, iclass 27, count 2 2006.210.07:42:00.57#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.07:42:00.57#ibcon#[27=AT02-04\r\n] 2006.210.07:42:00.57#ibcon#*before write, iclass 27, count 2 2006.210.07:42:00.57#ibcon#enter sib2, iclass 27, count 2 2006.210.07:42:00.57#ibcon#flushed, iclass 27, count 2 2006.210.07:42:00.57#ibcon#about to write, iclass 27, count 2 2006.210.07:42:00.57#ibcon#wrote, iclass 27, count 2 2006.210.07:42:00.57#ibcon#about to read 3, iclass 27, count 2 2006.210.07:42:00.60#ibcon#read 3, iclass 27, count 2 2006.210.07:42:00.60#ibcon#about to read 4, iclass 27, count 2 2006.210.07:42:00.60#ibcon#read 4, iclass 27, count 2 2006.210.07:42:00.60#ibcon#about to read 5, iclass 27, count 2 2006.210.07:42:00.60#ibcon#read 5, iclass 27, count 2 2006.210.07:42:00.60#ibcon#about to read 6, iclass 27, count 2 2006.210.07:42:00.60#ibcon#read 6, iclass 27, count 2 2006.210.07:42:00.60#ibcon#end of sib2, iclass 27, count 2 2006.210.07:42:00.60#ibcon#*after write, iclass 27, count 2 2006.210.07:42:00.60#ibcon#*before return 0, iclass 27, count 2 2006.210.07:42:00.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:42:00.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:42:00.60#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.07:42:00.60#ibcon#ireg 7 cls_cnt 0 2006.210.07:42:00.60#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:42:00.72#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:42:00.72#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:42:00.72#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:42:00.72#ibcon#first serial, iclass 27, count 0 2006.210.07:42:00.72#ibcon#enter sib2, iclass 27, count 0 2006.210.07:42:00.72#ibcon#flushed, iclass 27, count 0 2006.210.07:42:00.72#ibcon#about to write, iclass 27, count 0 2006.210.07:42:00.72#ibcon#wrote, iclass 27, count 0 2006.210.07:42:00.72#ibcon#about to read 3, iclass 27, count 0 2006.210.07:42:00.74#ibcon#read 3, iclass 27, count 0 2006.210.07:42:00.74#ibcon#about to read 4, iclass 27, count 0 2006.210.07:42:00.74#ibcon#read 4, iclass 27, count 0 2006.210.07:42:00.74#ibcon#about to read 5, iclass 27, count 0 2006.210.07:42:00.74#ibcon#read 5, iclass 27, count 0 2006.210.07:42:00.74#ibcon#about to read 6, iclass 27, count 0 2006.210.07:42:00.74#ibcon#read 6, iclass 27, count 0 2006.210.07:42:00.74#ibcon#end of sib2, iclass 27, count 0 2006.210.07:42:00.74#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:42:00.74#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:42:00.74#ibcon#[27=USB\r\n] 2006.210.07:42:00.74#ibcon#*before write, iclass 27, count 0 2006.210.07:42:00.74#ibcon#enter sib2, iclass 27, count 0 2006.210.07:42:00.74#ibcon#flushed, iclass 27, count 0 2006.210.07:42:00.74#ibcon#about to write, iclass 27, count 0 2006.210.07:42:00.74#ibcon#wrote, iclass 27, count 0 2006.210.07:42:00.74#ibcon#about to read 3, iclass 27, count 0 2006.210.07:42:00.77#ibcon#read 3, iclass 27, count 0 2006.210.07:42:00.77#ibcon#about to read 4, iclass 27, count 0 2006.210.07:42:00.77#ibcon#read 4, iclass 27, count 0 2006.210.07:42:00.77#ibcon#about to read 5, iclass 27, count 0 2006.210.07:42:00.77#ibcon#read 5, iclass 27, count 0 2006.210.07:42:00.77#ibcon#about to read 6, iclass 27, count 0 2006.210.07:42:00.77#ibcon#read 6, iclass 27, count 0 2006.210.07:42:00.77#ibcon#end of sib2, iclass 27, count 0 2006.210.07:42:00.77#ibcon#*after write, iclass 27, count 0 2006.210.07:42:00.77#ibcon#*before return 0, iclass 27, count 0 2006.210.07:42:00.77#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:42:00.77#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:42:00.77#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:42:00.77#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:42:00.77$vc4f8/vblo=3,656.99 2006.210.07:42:00.77#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.07:42:00.77#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.07:42:00.77#ibcon#ireg 17 cls_cnt 0 2006.210.07:42:00.77#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:42:00.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:42:00.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:42:00.77#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:42:00.77#ibcon#first serial, iclass 29, count 0 2006.210.07:42:00.77#ibcon#enter sib2, iclass 29, count 0 2006.210.07:42:00.77#ibcon#flushed, iclass 29, count 0 2006.210.07:42:00.77#ibcon#about to write, iclass 29, count 0 2006.210.07:42:00.77#ibcon#wrote, iclass 29, count 0 2006.210.07:42:00.77#ibcon#about to read 3, iclass 29, count 0 2006.210.07:42:00.79#ibcon#read 3, iclass 29, count 0 2006.210.07:42:00.79#ibcon#about to read 4, iclass 29, count 0 2006.210.07:42:00.79#ibcon#read 4, iclass 29, count 0 2006.210.07:42:00.79#ibcon#about to read 5, iclass 29, count 0 2006.210.07:42:00.79#ibcon#read 5, iclass 29, count 0 2006.210.07:42:00.79#ibcon#about to read 6, iclass 29, count 0 2006.210.07:42:00.79#ibcon#read 6, iclass 29, count 0 2006.210.07:42:00.79#ibcon#end of sib2, iclass 29, count 0 2006.210.07:42:00.79#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:42:00.79#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:42:00.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:42:00.79#ibcon#*before write, iclass 29, count 0 2006.210.07:42:00.79#ibcon#enter sib2, iclass 29, count 0 2006.210.07:42:00.79#ibcon#flushed, iclass 29, count 0 2006.210.07:42:00.79#ibcon#about to write, iclass 29, count 0 2006.210.07:42:00.79#ibcon#wrote, iclass 29, count 0 2006.210.07:42:00.79#ibcon#about to read 3, iclass 29, count 0 2006.210.07:42:00.83#ibcon#read 3, iclass 29, count 0 2006.210.07:42:00.83#ibcon#about to read 4, iclass 29, count 0 2006.210.07:42:00.83#ibcon#read 4, iclass 29, count 0 2006.210.07:42:00.83#ibcon#about to read 5, iclass 29, count 0 2006.210.07:42:00.83#ibcon#read 5, iclass 29, count 0 2006.210.07:42:00.83#ibcon#about to read 6, iclass 29, count 0 2006.210.07:42:00.83#ibcon#read 6, iclass 29, count 0 2006.210.07:42:00.83#ibcon#end of sib2, iclass 29, count 0 2006.210.07:42:00.83#ibcon#*after write, iclass 29, count 0 2006.210.07:42:00.83#ibcon#*before return 0, iclass 29, count 0 2006.210.07:42:00.83#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:42:00.83#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:42:00.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:42:00.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:42:00.83$vc4f8/vb=3,3 2006.210.07:42:00.83#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.07:42:00.83#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.07:42:00.83#ibcon#ireg 11 cls_cnt 2 2006.210.07:42:00.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:42:00.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:42:00.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:42:00.89#ibcon#enter wrdev, iclass 31, count 2 2006.210.07:42:00.89#ibcon#first serial, iclass 31, count 2 2006.210.07:42:00.89#ibcon#enter sib2, iclass 31, count 2 2006.210.07:42:00.89#ibcon#flushed, iclass 31, count 2 2006.210.07:42:00.89#ibcon#about to write, iclass 31, count 2 2006.210.07:42:00.89#ibcon#wrote, iclass 31, count 2 2006.210.07:42:00.89#ibcon#about to read 3, iclass 31, count 2 2006.210.07:42:00.91#ibcon#read 3, iclass 31, count 2 2006.210.07:42:00.91#ibcon#about to read 4, iclass 31, count 2 2006.210.07:42:00.91#ibcon#read 4, iclass 31, count 2 2006.210.07:42:00.91#ibcon#about to read 5, iclass 31, count 2 2006.210.07:42:00.91#ibcon#read 5, iclass 31, count 2 2006.210.07:42:00.91#ibcon#about to read 6, iclass 31, count 2 2006.210.07:42:00.91#ibcon#read 6, iclass 31, count 2 2006.210.07:42:00.91#ibcon#end of sib2, iclass 31, count 2 2006.210.07:42:00.91#ibcon#*mode == 0, iclass 31, count 2 2006.210.07:42:00.91#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.07:42:00.91#ibcon#[27=AT03-03\r\n] 2006.210.07:42:00.91#ibcon#*before write, iclass 31, count 2 2006.210.07:42:00.91#ibcon#enter sib2, iclass 31, count 2 2006.210.07:42:00.91#ibcon#flushed, iclass 31, count 2 2006.210.07:42:00.91#ibcon#about to write, iclass 31, count 2 2006.210.07:42:00.91#ibcon#wrote, iclass 31, count 2 2006.210.07:42:00.91#ibcon#about to read 3, iclass 31, count 2 2006.210.07:42:00.94#ibcon#read 3, iclass 31, count 2 2006.210.07:42:00.94#ibcon#about to read 4, iclass 31, count 2 2006.210.07:42:00.94#ibcon#read 4, iclass 31, count 2 2006.210.07:42:00.94#ibcon#about to read 5, iclass 31, count 2 2006.210.07:42:00.94#ibcon#read 5, iclass 31, count 2 2006.210.07:42:00.94#ibcon#about to read 6, iclass 31, count 2 2006.210.07:42:00.94#ibcon#read 6, iclass 31, count 2 2006.210.07:42:00.94#ibcon#end of sib2, iclass 31, count 2 2006.210.07:42:00.94#ibcon#*after write, iclass 31, count 2 2006.210.07:42:00.94#ibcon#*before return 0, iclass 31, count 2 2006.210.07:42:00.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:42:00.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:42:00.94#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.07:42:00.94#ibcon#ireg 7 cls_cnt 0 2006.210.07:42:00.94#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:42:01.06#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:42:01.06#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:42:01.06#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:42:01.06#ibcon#first serial, iclass 31, count 0 2006.210.07:42:01.06#ibcon#enter sib2, iclass 31, count 0 2006.210.07:42:01.06#ibcon#flushed, iclass 31, count 0 2006.210.07:42:01.06#ibcon#about to write, iclass 31, count 0 2006.210.07:42:01.06#ibcon#wrote, iclass 31, count 0 2006.210.07:42:01.06#ibcon#about to read 3, iclass 31, count 0 2006.210.07:42:01.08#ibcon#read 3, iclass 31, count 0 2006.210.07:42:01.08#ibcon#about to read 4, iclass 31, count 0 2006.210.07:42:01.08#ibcon#read 4, iclass 31, count 0 2006.210.07:42:01.08#ibcon#about to read 5, iclass 31, count 0 2006.210.07:42:01.08#ibcon#read 5, iclass 31, count 0 2006.210.07:42:01.08#ibcon#about to read 6, iclass 31, count 0 2006.210.07:42:01.08#ibcon#read 6, iclass 31, count 0 2006.210.07:42:01.08#ibcon#end of sib2, iclass 31, count 0 2006.210.07:42:01.08#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:42:01.08#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:42:01.08#ibcon#[27=USB\r\n] 2006.210.07:42:01.08#ibcon#*before write, iclass 31, count 0 2006.210.07:42:01.08#ibcon#enter sib2, iclass 31, count 0 2006.210.07:42:01.08#ibcon#flushed, iclass 31, count 0 2006.210.07:42:01.08#ibcon#about to write, iclass 31, count 0 2006.210.07:42:01.08#ibcon#wrote, iclass 31, count 0 2006.210.07:42:01.08#ibcon#about to read 3, iclass 31, count 0 2006.210.07:42:01.11#ibcon#read 3, iclass 31, count 0 2006.210.07:42:01.11#ibcon#about to read 4, iclass 31, count 0 2006.210.07:42:01.11#ibcon#read 4, iclass 31, count 0 2006.210.07:42:01.11#ibcon#about to read 5, iclass 31, count 0 2006.210.07:42:01.11#ibcon#read 5, iclass 31, count 0 2006.210.07:42:01.11#ibcon#about to read 6, iclass 31, count 0 2006.210.07:42:01.11#ibcon#read 6, iclass 31, count 0 2006.210.07:42:01.11#ibcon#end of sib2, iclass 31, count 0 2006.210.07:42:01.11#ibcon#*after write, iclass 31, count 0 2006.210.07:42:01.11#ibcon#*before return 0, iclass 31, count 0 2006.210.07:42:01.11#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:42:01.11#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:42:01.11#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:42:01.11#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:42:01.11$vc4f8/vblo=4,712.99 2006.210.07:42:01.11#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.07:42:01.11#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.07:42:01.11#ibcon#ireg 17 cls_cnt 0 2006.210.07:42:01.11#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:42:01.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:42:01.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:42:01.11#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:42:01.11#ibcon#first serial, iclass 33, count 0 2006.210.07:42:01.11#ibcon#enter sib2, iclass 33, count 0 2006.210.07:42:01.11#ibcon#flushed, iclass 33, count 0 2006.210.07:42:01.11#ibcon#about to write, iclass 33, count 0 2006.210.07:42:01.11#ibcon#wrote, iclass 33, count 0 2006.210.07:42:01.11#ibcon#about to read 3, iclass 33, count 0 2006.210.07:42:01.13#ibcon#read 3, iclass 33, count 0 2006.210.07:42:01.13#ibcon#about to read 4, iclass 33, count 0 2006.210.07:42:01.13#ibcon#read 4, iclass 33, count 0 2006.210.07:42:01.13#ibcon#about to read 5, iclass 33, count 0 2006.210.07:42:01.13#ibcon#read 5, iclass 33, count 0 2006.210.07:42:01.13#ibcon#about to read 6, iclass 33, count 0 2006.210.07:42:01.13#ibcon#read 6, iclass 33, count 0 2006.210.07:42:01.13#ibcon#end of sib2, iclass 33, count 0 2006.210.07:42:01.13#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:42:01.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:42:01.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:42:01.13#ibcon#*before write, iclass 33, count 0 2006.210.07:42:01.13#ibcon#enter sib2, iclass 33, count 0 2006.210.07:42:01.13#ibcon#flushed, iclass 33, count 0 2006.210.07:42:01.13#ibcon#about to write, iclass 33, count 0 2006.210.07:42:01.13#ibcon#wrote, iclass 33, count 0 2006.210.07:42:01.13#ibcon#about to read 3, iclass 33, count 0 2006.210.07:42:01.17#ibcon#read 3, iclass 33, count 0 2006.210.07:42:01.17#ibcon#about to read 4, iclass 33, count 0 2006.210.07:42:01.17#ibcon#read 4, iclass 33, count 0 2006.210.07:42:01.17#ibcon#about to read 5, iclass 33, count 0 2006.210.07:42:01.17#ibcon#read 5, iclass 33, count 0 2006.210.07:42:01.17#ibcon#about to read 6, iclass 33, count 0 2006.210.07:42:01.17#ibcon#read 6, iclass 33, count 0 2006.210.07:42:01.17#ibcon#end of sib2, iclass 33, count 0 2006.210.07:42:01.17#ibcon#*after write, iclass 33, count 0 2006.210.07:42:01.17#ibcon#*before return 0, iclass 33, count 0 2006.210.07:42:01.17#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:42:01.17#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:42:01.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:42:01.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:42:01.17$vc4f8/vb=4,3 2006.210.07:42:01.17#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.07:42:01.17#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.07:42:01.17#ibcon#ireg 11 cls_cnt 2 2006.210.07:42:01.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:42:01.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:42:01.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:42:01.23#ibcon#enter wrdev, iclass 35, count 2 2006.210.07:42:01.23#ibcon#first serial, iclass 35, count 2 2006.210.07:42:01.23#ibcon#enter sib2, iclass 35, count 2 2006.210.07:42:01.23#ibcon#flushed, iclass 35, count 2 2006.210.07:42:01.23#ibcon#about to write, iclass 35, count 2 2006.210.07:42:01.23#ibcon#wrote, iclass 35, count 2 2006.210.07:42:01.23#ibcon#about to read 3, iclass 35, count 2 2006.210.07:42:01.25#ibcon#read 3, iclass 35, count 2 2006.210.07:42:01.25#ibcon#about to read 4, iclass 35, count 2 2006.210.07:42:01.25#ibcon#read 4, iclass 35, count 2 2006.210.07:42:01.25#ibcon#about to read 5, iclass 35, count 2 2006.210.07:42:01.25#ibcon#read 5, iclass 35, count 2 2006.210.07:42:01.25#ibcon#about to read 6, iclass 35, count 2 2006.210.07:42:01.25#ibcon#read 6, iclass 35, count 2 2006.210.07:42:01.25#ibcon#end of sib2, iclass 35, count 2 2006.210.07:42:01.25#ibcon#*mode == 0, iclass 35, count 2 2006.210.07:42:01.25#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.07:42:01.25#ibcon#[27=AT04-03\r\n] 2006.210.07:42:01.25#ibcon#*before write, iclass 35, count 2 2006.210.07:42:01.25#ibcon#enter sib2, iclass 35, count 2 2006.210.07:42:01.25#ibcon#flushed, iclass 35, count 2 2006.210.07:42:01.25#ibcon#about to write, iclass 35, count 2 2006.210.07:42:01.25#ibcon#wrote, iclass 35, count 2 2006.210.07:42:01.25#ibcon#about to read 3, iclass 35, count 2 2006.210.07:42:01.28#ibcon#read 3, iclass 35, count 2 2006.210.07:42:01.28#ibcon#about to read 4, iclass 35, count 2 2006.210.07:42:01.28#ibcon#read 4, iclass 35, count 2 2006.210.07:42:01.28#ibcon#about to read 5, iclass 35, count 2 2006.210.07:42:01.28#ibcon#read 5, iclass 35, count 2 2006.210.07:42:01.28#ibcon#about to read 6, iclass 35, count 2 2006.210.07:42:01.28#ibcon#read 6, iclass 35, count 2 2006.210.07:42:01.28#ibcon#end of sib2, iclass 35, count 2 2006.210.07:42:01.28#ibcon#*after write, iclass 35, count 2 2006.210.07:42:01.28#ibcon#*before return 0, iclass 35, count 2 2006.210.07:42:01.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:42:01.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:42:01.28#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.07:42:01.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:42:01.28#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:42:01.40#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:42:01.40#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:42:01.40#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:42:01.40#ibcon#first serial, iclass 35, count 0 2006.210.07:42:01.40#ibcon#enter sib2, iclass 35, count 0 2006.210.07:42:01.40#ibcon#flushed, iclass 35, count 0 2006.210.07:42:01.40#ibcon#about to write, iclass 35, count 0 2006.210.07:42:01.40#ibcon#wrote, iclass 35, count 0 2006.210.07:42:01.40#ibcon#about to read 3, iclass 35, count 0 2006.210.07:42:01.42#ibcon#read 3, iclass 35, count 0 2006.210.07:42:01.42#ibcon#about to read 4, iclass 35, count 0 2006.210.07:42:01.42#ibcon#read 4, iclass 35, count 0 2006.210.07:42:01.42#ibcon#about to read 5, iclass 35, count 0 2006.210.07:42:01.42#ibcon#read 5, iclass 35, count 0 2006.210.07:42:01.42#ibcon#about to read 6, iclass 35, count 0 2006.210.07:42:01.42#ibcon#read 6, iclass 35, count 0 2006.210.07:42:01.42#ibcon#end of sib2, iclass 35, count 0 2006.210.07:42:01.42#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:42:01.42#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:42:01.42#ibcon#[27=USB\r\n] 2006.210.07:42:01.42#ibcon#*before write, iclass 35, count 0 2006.210.07:42:01.42#ibcon#enter sib2, iclass 35, count 0 2006.210.07:42:01.42#ibcon#flushed, iclass 35, count 0 2006.210.07:42:01.42#ibcon#about to write, iclass 35, count 0 2006.210.07:42:01.42#ibcon#wrote, iclass 35, count 0 2006.210.07:42:01.42#ibcon#about to read 3, iclass 35, count 0 2006.210.07:42:01.45#ibcon#read 3, iclass 35, count 0 2006.210.07:42:01.45#ibcon#about to read 4, iclass 35, count 0 2006.210.07:42:01.45#ibcon#read 4, iclass 35, count 0 2006.210.07:42:01.45#ibcon#about to read 5, iclass 35, count 0 2006.210.07:42:01.45#ibcon#read 5, iclass 35, count 0 2006.210.07:42:01.45#ibcon#about to read 6, iclass 35, count 0 2006.210.07:42:01.45#ibcon#read 6, iclass 35, count 0 2006.210.07:42:01.45#ibcon#end of sib2, iclass 35, count 0 2006.210.07:42:01.45#ibcon#*after write, iclass 35, count 0 2006.210.07:42:01.45#ibcon#*before return 0, iclass 35, count 0 2006.210.07:42:01.45#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:42:01.45#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:42:01.45#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:42:01.45#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:42:01.45$vc4f8/vblo=5,744.99 2006.210.07:42:01.45#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:42:01.45#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:42:01.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:42:01.45#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:42:01.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:42:01.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:42:01.45#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:42:01.45#ibcon#first serial, iclass 37, count 0 2006.210.07:42:01.45#ibcon#enter sib2, iclass 37, count 0 2006.210.07:42:01.45#ibcon#flushed, iclass 37, count 0 2006.210.07:42:01.45#ibcon#about to write, iclass 37, count 0 2006.210.07:42:01.45#ibcon#wrote, iclass 37, count 0 2006.210.07:42:01.45#ibcon#about to read 3, iclass 37, count 0 2006.210.07:42:01.47#ibcon#read 3, iclass 37, count 0 2006.210.07:42:01.47#ibcon#about to read 4, iclass 37, count 0 2006.210.07:42:01.47#ibcon#read 4, iclass 37, count 0 2006.210.07:42:01.47#ibcon#about to read 5, iclass 37, count 0 2006.210.07:42:01.47#ibcon#read 5, iclass 37, count 0 2006.210.07:42:01.47#ibcon#about to read 6, iclass 37, count 0 2006.210.07:42:01.47#ibcon#read 6, iclass 37, count 0 2006.210.07:42:01.47#ibcon#end of sib2, iclass 37, count 0 2006.210.07:42:01.47#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:42:01.47#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:42:01.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:42:01.47#ibcon#*before write, iclass 37, count 0 2006.210.07:42:01.47#ibcon#enter sib2, iclass 37, count 0 2006.210.07:42:01.47#ibcon#flushed, iclass 37, count 0 2006.210.07:42:01.47#ibcon#about to write, iclass 37, count 0 2006.210.07:42:01.47#ibcon#wrote, iclass 37, count 0 2006.210.07:42:01.47#ibcon#about to read 3, iclass 37, count 0 2006.210.07:42:01.51#ibcon#read 3, iclass 37, count 0 2006.210.07:42:01.51#ibcon#about to read 4, iclass 37, count 0 2006.210.07:42:01.51#ibcon#read 4, iclass 37, count 0 2006.210.07:42:01.51#ibcon#about to read 5, iclass 37, count 0 2006.210.07:42:01.51#ibcon#read 5, iclass 37, count 0 2006.210.07:42:01.51#ibcon#about to read 6, iclass 37, count 0 2006.210.07:42:01.51#ibcon#read 6, iclass 37, count 0 2006.210.07:42:01.51#ibcon#end of sib2, iclass 37, count 0 2006.210.07:42:01.51#ibcon#*after write, iclass 37, count 0 2006.210.07:42:01.51#ibcon#*before return 0, iclass 37, count 0 2006.210.07:42:01.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:42:01.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:42:01.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:42:01.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:42:01.51$vc4f8/vb=5,3 2006.210.07:42:01.51#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:42:01.51#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:42:01.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:42:01.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:42:01.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:42:01.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:42:01.57#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:42:01.57#ibcon#first serial, iclass 39, count 2 2006.210.07:42:01.57#ibcon#enter sib2, iclass 39, count 2 2006.210.07:42:01.57#ibcon#flushed, iclass 39, count 2 2006.210.07:42:01.57#ibcon#about to write, iclass 39, count 2 2006.210.07:42:01.57#ibcon#wrote, iclass 39, count 2 2006.210.07:42:01.57#ibcon#about to read 3, iclass 39, count 2 2006.210.07:42:01.59#ibcon#read 3, iclass 39, count 2 2006.210.07:42:01.59#ibcon#about to read 4, iclass 39, count 2 2006.210.07:42:01.59#ibcon#read 4, iclass 39, count 2 2006.210.07:42:01.59#ibcon#about to read 5, iclass 39, count 2 2006.210.07:42:01.59#ibcon#read 5, iclass 39, count 2 2006.210.07:42:01.59#ibcon#about to read 6, iclass 39, count 2 2006.210.07:42:01.59#ibcon#read 6, iclass 39, count 2 2006.210.07:42:01.59#ibcon#end of sib2, iclass 39, count 2 2006.210.07:42:01.59#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:42:01.59#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:42:01.59#ibcon#[27=AT05-03\r\n] 2006.210.07:42:01.59#ibcon#*before write, iclass 39, count 2 2006.210.07:42:01.59#ibcon#enter sib2, iclass 39, count 2 2006.210.07:42:01.59#ibcon#flushed, iclass 39, count 2 2006.210.07:42:01.59#ibcon#about to write, iclass 39, count 2 2006.210.07:42:01.59#ibcon#wrote, iclass 39, count 2 2006.210.07:42:01.59#ibcon#about to read 3, iclass 39, count 2 2006.210.07:42:01.62#ibcon#read 3, iclass 39, count 2 2006.210.07:42:01.62#ibcon#about to read 4, iclass 39, count 2 2006.210.07:42:01.62#ibcon#read 4, iclass 39, count 2 2006.210.07:42:01.62#ibcon#about to read 5, iclass 39, count 2 2006.210.07:42:01.62#ibcon#read 5, iclass 39, count 2 2006.210.07:42:01.62#ibcon#about to read 6, iclass 39, count 2 2006.210.07:42:01.62#ibcon#read 6, iclass 39, count 2 2006.210.07:42:01.62#ibcon#end of sib2, iclass 39, count 2 2006.210.07:42:01.62#ibcon#*after write, iclass 39, count 2 2006.210.07:42:01.62#ibcon#*before return 0, iclass 39, count 2 2006.210.07:42:01.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:42:01.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:42:01.62#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:42:01.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:42:01.62#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:42:01.74#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:42:01.74#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:42:01.74#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:42:01.74#ibcon#first serial, iclass 39, count 0 2006.210.07:42:01.74#ibcon#enter sib2, iclass 39, count 0 2006.210.07:42:01.74#ibcon#flushed, iclass 39, count 0 2006.210.07:42:01.74#ibcon#about to write, iclass 39, count 0 2006.210.07:42:01.74#ibcon#wrote, iclass 39, count 0 2006.210.07:42:01.74#ibcon#about to read 3, iclass 39, count 0 2006.210.07:42:01.76#ibcon#read 3, iclass 39, count 0 2006.210.07:42:01.76#ibcon#about to read 4, iclass 39, count 0 2006.210.07:42:01.76#ibcon#read 4, iclass 39, count 0 2006.210.07:42:01.76#ibcon#about to read 5, iclass 39, count 0 2006.210.07:42:01.76#ibcon#read 5, iclass 39, count 0 2006.210.07:42:01.76#ibcon#about to read 6, iclass 39, count 0 2006.210.07:42:01.76#ibcon#read 6, iclass 39, count 0 2006.210.07:42:01.76#ibcon#end of sib2, iclass 39, count 0 2006.210.07:42:01.76#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:42:01.76#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:42:01.76#ibcon#[27=USB\r\n] 2006.210.07:42:01.76#ibcon#*before write, iclass 39, count 0 2006.210.07:42:01.76#ibcon#enter sib2, iclass 39, count 0 2006.210.07:42:01.76#ibcon#flushed, iclass 39, count 0 2006.210.07:42:01.76#ibcon#about to write, iclass 39, count 0 2006.210.07:42:01.76#ibcon#wrote, iclass 39, count 0 2006.210.07:42:01.76#ibcon#about to read 3, iclass 39, count 0 2006.210.07:42:01.79#ibcon#read 3, iclass 39, count 0 2006.210.07:42:01.79#ibcon#about to read 4, iclass 39, count 0 2006.210.07:42:01.79#ibcon#read 4, iclass 39, count 0 2006.210.07:42:01.79#ibcon#about to read 5, iclass 39, count 0 2006.210.07:42:01.79#ibcon#read 5, iclass 39, count 0 2006.210.07:42:01.79#ibcon#about to read 6, iclass 39, count 0 2006.210.07:42:01.79#ibcon#read 6, iclass 39, count 0 2006.210.07:42:01.79#ibcon#end of sib2, iclass 39, count 0 2006.210.07:42:01.79#ibcon#*after write, iclass 39, count 0 2006.210.07:42:01.79#ibcon#*before return 0, iclass 39, count 0 2006.210.07:42:01.79#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:42:01.79#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:42:01.79#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:42:01.79#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:42:01.79$vc4f8/vblo=6,752.99 2006.210.07:42:01.79#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:42:01.79#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:42:01.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:42:01.79#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:42:01.79#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:42:01.79#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:42:01.79#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:42:01.79#ibcon#first serial, iclass 3, count 0 2006.210.07:42:01.79#ibcon#enter sib2, iclass 3, count 0 2006.210.07:42:01.79#ibcon#flushed, iclass 3, count 0 2006.210.07:42:01.79#ibcon#about to write, iclass 3, count 0 2006.210.07:42:01.79#ibcon#wrote, iclass 3, count 0 2006.210.07:42:01.79#ibcon#about to read 3, iclass 3, count 0 2006.210.07:42:01.81#ibcon#read 3, iclass 3, count 0 2006.210.07:42:01.81#ibcon#about to read 4, iclass 3, count 0 2006.210.07:42:01.81#ibcon#read 4, iclass 3, count 0 2006.210.07:42:01.81#ibcon#about to read 5, iclass 3, count 0 2006.210.07:42:01.81#ibcon#read 5, iclass 3, count 0 2006.210.07:42:01.81#ibcon#about to read 6, iclass 3, count 0 2006.210.07:42:01.81#ibcon#read 6, iclass 3, count 0 2006.210.07:42:01.81#ibcon#end of sib2, iclass 3, count 0 2006.210.07:42:01.81#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:42:01.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:42:01.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:42:01.81#ibcon#*before write, iclass 3, count 0 2006.210.07:42:01.81#ibcon#enter sib2, iclass 3, count 0 2006.210.07:42:01.81#ibcon#flushed, iclass 3, count 0 2006.210.07:42:01.81#ibcon#about to write, iclass 3, count 0 2006.210.07:42:01.81#ibcon#wrote, iclass 3, count 0 2006.210.07:42:01.81#ibcon#about to read 3, iclass 3, count 0 2006.210.07:42:01.85#ibcon#read 3, iclass 3, count 0 2006.210.07:42:01.85#ibcon#about to read 4, iclass 3, count 0 2006.210.07:42:01.85#ibcon#read 4, iclass 3, count 0 2006.210.07:42:01.85#ibcon#about to read 5, iclass 3, count 0 2006.210.07:42:01.85#ibcon#read 5, iclass 3, count 0 2006.210.07:42:01.85#ibcon#about to read 6, iclass 3, count 0 2006.210.07:42:01.85#ibcon#read 6, iclass 3, count 0 2006.210.07:42:01.85#ibcon#end of sib2, iclass 3, count 0 2006.210.07:42:01.85#ibcon#*after write, iclass 3, count 0 2006.210.07:42:01.85#ibcon#*before return 0, iclass 3, count 0 2006.210.07:42:01.85#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:42:01.85#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:42:01.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:42:01.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:42:01.85$vc4f8/vb=6,3 2006.210.07:42:01.85#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:42:01.85#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:42:01.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:42:01.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:42:01.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:42:01.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:42:01.91#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:42:01.91#ibcon#first serial, iclass 5, count 2 2006.210.07:42:01.91#ibcon#enter sib2, iclass 5, count 2 2006.210.07:42:01.91#ibcon#flushed, iclass 5, count 2 2006.210.07:42:01.91#ibcon#about to write, iclass 5, count 2 2006.210.07:42:01.91#ibcon#wrote, iclass 5, count 2 2006.210.07:42:01.91#ibcon#about to read 3, iclass 5, count 2 2006.210.07:42:01.93#ibcon#read 3, iclass 5, count 2 2006.210.07:42:01.93#ibcon#about to read 4, iclass 5, count 2 2006.210.07:42:01.93#ibcon#read 4, iclass 5, count 2 2006.210.07:42:01.93#ibcon#about to read 5, iclass 5, count 2 2006.210.07:42:01.93#ibcon#read 5, iclass 5, count 2 2006.210.07:42:01.93#ibcon#about to read 6, iclass 5, count 2 2006.210.07:42:01.93#ibcon#read 6, iclass 5, count 2 2006.210.07:42:01.93#ibcon#end of sib2, iclass 5, count 2 2006.210.07:42:01.93#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:42:01.93#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:42:01.93#ibcon#[27=AT06-03\r\n] 2006.210.07:42:01.93#ibcon#*before write, iclass 5, count 2 2006.210.07:42:01.93#ibcon#enter sib2, iclass 5, count 2 2006.210.07:42:01.93#ibcon#flushed, iclass 5, count 2 2006.210.07:42:01.93#ibcon#about to write, iclass 5, count 2 2006.210.07:42:01.93#ibcon#wrote, iclass 5, count 2 2006.210.07:42:01.93#ibcon#about to read 3, iclass 5, count 2 2006.210.07:42:01.96#ibcon#read 3, iclass 5, count 2 2006.210.07:42:01.96#ibcon#about to read 4, iclass 5, count 2 2006.210.07:42:01.96#ibcon#read 4, iclass 5, count 2 2006.210.07:42:01.96#ibcon#about to read 5, iclass 5, count 2 2006.210.07:42:01.96#ibcon#read 5, iclass 5, count 2 2006.210.07:42:01.96#ibcon#about to read 6, iclass 5, count 2 2006.210.07:42:01.96#ibcon#read 6, iclass 5, count 2 2006.210.07:42:01.96#ibcon#end of sib2, iclass 5, count 2 2006.210.07:42:01.96#ibcon#*after write, iclass 5, count 2 2006.210.07:42:01.96#ibcon#*before return 0, iclass 5, count 2 2006.210.07:42:01.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:42:01.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:42:01.96#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:42:01.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:42:01.96#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:42:02.08#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:42:02.08#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:42:02.08#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:42:02.08#ibcon#first serial, iclass 5, count 0 2006.210.07:42:02.08#ibcon#enter sib2, iclass 5, count 0 2006.210.07:42:02.08#ibcon#flushed, iclass 5, count 0 2006.210.07:42:02.08#ibcon#about to write, iclass 5, count 0 2006.210.07:42:02.08#ibcon#wrote, iclass 5, count 0 2006.210.07:42:02.08#ibcon#about to read 3, iclass 5, count 0 2006.210.07:42:02.10#ibcon#read 3, iclass 5, count 0 2006.210.07:42:02.10#ibcon#about to read 4, iclass 5, count 0 2006.210.07:42:02.10#ibcon#read 4, iclass 5, count 0 2006.210.07:42:02.10#ibcon#about to read 5, iclass 5, count 0 2006.210.07:42:02.10#ibcon#read 5, iclass 5, count 0 2006.210.07:42:02.10#ibcon#about to read 6, iclass 5, count 0 2006.210.07:42:02.10#ibcon#read 6, iclass 5, count 0 2006.210.07:42:02.10#ibcon#end of sib2, iclass 5, count 0 2006.210.07:42:02.10#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:42:02.10#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:42:02.10#ibcon#[27=USB\r\n] 2006.210.07:42:02.10#ibcon#*before write, iclass 5, count 0 2006.210.07:42:02.10#ibcon#enter sib2, iclass 5, count 0 2006.210.07:42:02.10#ibcon#flushed, iclass 5, count 0 2006.210.07:42:02.10#ibcon#about to write, iclass 5, count 0 2006.210.07:42:02.10#ibcon#wrote, iclass 5, count 0 2006.210.07:42:02.10#ibcon#about to read 3, iclass 5, count 0 2006.210.07:42:02.13#ibcon#read 3, iclass 5, count 0 2006.210.07:42:02.13#ibcon#about to read 4, iclass 5, count 0 2006.210.07:42:02.13#ibcon#read 4, iclass 5, count 0 2006.210.07:42:02.13#ibcon#about to read 5, iclass 5, count 0 2006.210.07:42:02.13#ibcon#read 5, iclass 5, count 0 2006.210.07:42:02.13#ibcon#about to read 6, iclass 5, count 0 2006.210.07:42:02.13#ibcon#read 6, iclass 5, count 0 2006.210.07:42:02.13#ibcon#end of sib2, iclass 5, count 0 2006.210.07:42:02.13#ibcon#*after write, iclass 5, count 0 2006.210.07:42:02.13#ibcon#*before return 0, iclass 5, count 0 2006.210.07:42:02.13#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:42:02.13#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:42:02.13#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:42:02.13#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:42:02.13$vc4f8/vabw=wide 2006.210.07:42:02.13#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:42:02.13#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:42:02.13#ibcon#ireg 8 cls_cnt 0 2006.210.07:42:02.13#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:42:02.13#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:42:02.13#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:42:02.13#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:42:02.13#ibcon#first serial, iclass 7, count 0 2006.210.07:42:02.13#ibcon#enter sib2, iclass 7, count 0 2006.210.07:42:02.13#ibcon#flushed, iclass 7, count 0 2006.210.07:42:02.13#ibcon#about to write, iclass 7, count 0 2006.210.07:42:02.13#ibcon#wrote, iclass 7, count 0 2006.210.07:42:02.13#ibcon#about to read 3, iclass 7, count 0 2006.210.07:42:02.15#ibcon#read 3, iclass 7, count 0 2006.210.07:42:02.15#ibcon#about to read 4, iclass 7, count 0 2006.210.07:42:02.15#ibcon#read 4, iclass 7, count 0 2006.210.07:42:02.15#ibcon#about to read 5, iclass 7, count 0 2006.210.07:42:02.15#ibcon#read 5, iclass 7, count 0 2006.210.07:42:02.15#ibcon#about to read 6, iclass 7, count 0 2006.210.07:42:02.15#ibcon#read 6, iclass 7, count 0 2006.210.07:42:02.15#ibcon#end of sib2, iclass 7, count 0 2006.210.07:42:02.15#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:42:02.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:42:02.15#ibcon#[25=BW32\r\n] 2006.210.07:42:02.15#ibcon#*before write, iclass 7, count 0 2006.210.07:42:02.15#ibcon#enter sib2, iclass 7, count 0 2006.210.07:42:02.15#ibcon#flushed, iclass 7, count 0 2006.210.07:42:02.15#ibcon#about to write, iclass 7, count 0 2006.210.07:42:02.15#ibcon#wrote, iclass 7, count 0 2006.210.07:42:02.15#ibcon#about to read 3, iclass 7, count 0 2006.210.07:42:02.18#ibcon#read 3, iclass 7, count 0 2006.210.07:42:02.18#ibcon#about to read 4, iclass 7, count 0 2006.210.07:42:02.18#ibcon#read 4, iclass 7, count 0 2006.210.07:42:02.18#ibcon#about to read 5, iclass 7, count 0 2006.210.07:42:02.18#ibcon#read 5, iclass 7, count 0 2006.210.07:42:02.18#ibcon#about to read 6, iclass 7, count 0 2006.210.07:42:02.18#ibcon#read 6, iclass 7, count 0 2006.210.07:42:02.18#ibcon#end of sib2, iclass 7, count 0 2006.210.07:42:02.18#ibcon#*after write, iclass 7, count 0 2006.210.07:42:02.18#ibcon#*before return 0, iclass 7, count 0 2006.210.07:42:02.18#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:42:02.18#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:42:02.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:42:02.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:42:02.18$vc4f8/vbbw=wide 2006.210.07:42:02.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.07:42:02.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.07:42:02.18#ibcon#ireg 8 cls_cnt 0 2006.210.07:42:02.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:42:02.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:42:02.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:42:02.25#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:42:02.25#ibcon#first serial, iclass 11, count 0 2006.210.07:42:02.25#ibcon#enter sib2, iclass 11, count 0 2006.210.07:42:02.25#ibcon#flushed, iclass 11, count 0 2006.210.07:42:02.25#ibcon#about to write, iclass 11, count 0 2006.210.07:42:02.25#ibcon#wrote, iclass 11, count 0 2006.210.07:42:02.25#ibcon#about to read 3, iclass 11, count 0 2006.210.07:42:02.27#ibcon#read 3, iclass 11, count 0 2006.210.07:42:02.27#ibcon#about to read 4, iclass 11, count 0 2006.210.07:42:02.27#ibcon#read 4, iclass 11, count 0 2006.210.07:42:02.27#ibcon#about to read 5, iclass 11, count 0 2006.210.07:42:02.27#ibcon#read 5, iclass 11, count 0 2006.210.07:42:02.27#ibcon#about to read 6, iclass 11, count 0 2006.210.07:42:02.27#ibcon#read 6, iclass 11, count 0 2006.210.07:42:02.27#ibcon#end of sib2, iclass 11, count 0 2006.210.07:42:02.27#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:42:02.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:42:02.27#ibcon#[27=BW32\r\n] 2006.210.07:42:02.27#ibcon#*before write, iclass 11, count 0 2006.210.07:42:02.27#ibcon#enter sib2, iclass 11, count 0 2006.210.07:42:02.27#ibcon#flushed, iclass 11, count 0 2006.210.07:42:02.27#ibcon#about to write, iclass 11, count 0 2006.210.07:42:02.27#ibcon#wrote, iclass 11, count 0 2006.210.07:42:02.27#ibcon#about to read 3, iclass 11, count 0 2006.210.07:42:02.30#ibcon#read 3, iclass 11, count 0 2006.210.07:42:02.30#ibcon#about to read 4, iclass 11, count 0 2006.210.07:42:02.30#ibcon#read 4, iclass 11, count 0 2006.210.07:42:02.30#ibcon#about to read 5, iclass 11, count 0 2006.210.07:42:02.30#ibcon#read 5, iclass 11, count 0 2006.210.07:42:02.30#ibcon#about to read 6, iclass 11, count 0 2006.210.07:42:02.30#ibcon#read 6, iclass 11, count 0 2006.210.07:42:02.30#ibcon#end of sib2, iclass 11, count 0 2006.210.07:42:02.30#ibcon#*after write, iclass 11, count 0 2006.210.07:42:02.30#ibcon#*before return 0, iclass 11, count 0 2006.210.07:42:02.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:42:02.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:42:02.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:42:02.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:42:02.30$4f8m12a/ifd4f 2006.210.07:42:02.30$ifd4f/lo= 2006.210.07:42:02.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:42:02.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:42:02.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:42:02.30$ifd4f/patch= 2006.210.07:42:02.30$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:42:02.30$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:42:02.30$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:42:02.30$4f8m12a/"form=m,16.000,1:2 2006.210.07:42:02.30$4f8m12a/"tpicd 2006.210.07:42:02.30$4f8m12a/echo=off 2006.210.07:42:02.30$4f8m12a/xlog=off 2006.210.07:42:02.30:!2006.210.07:42:30 2006.210.07:42:13.14#trakl#Source acquired 2006.210.07:42:15.14#flagr#flagr/antenna,acquired 2006.210.07:42:30.00:preob 2006.210.07:42:31.14/onsource/TRACKING 2006.210.07:42:31.14:!2006.210.07:42:40 2006.210.07:42:40.00:data_valid=on 2006.210.07:42:40.00:midob 2006.210.07:42:40.14/onsource/TRACKING 2006.210.07:42:40.14/wx/30.58,1006.2,74 2006.210.07:42:40.33/cable/+6.3943E-03 2006.210.07:42:41.42/va/01,08,usb,yes,29,30 2006.210.07:42:41.42/va/02,07,usb,yes,29,30 2006.210.07:42:41.42/va/03,06,usb,yes,30,30 2006.210.07:42:41.42/va/04,07,usb,yes,29,32 2006.210.07:42:41.42/va/05,07,usb,yes,31,32 2006.210.07:42:41.42/va/06,06,usb,yes,30,30 2006.210.07:42:41.42/va/07,06,usb,yes,30,30 2006.210.07:42:41.42/va/08,07,usb,yes,29,28 2006.210.07:42:41.65/valo/01,532.99,yes,locked 2006.210.07:42:41.65/valo/02,572.99,yes,locked 2006.210.07:42:41.65/valo/03,672.99,yes,locked 2006.210.07:42:41.65/valo/04,832.99,yes,locked 2006.210.07:42:41.65/valo/05,652.99,yes,locked 2006.210.07:42:41.65/valo/06,772.99,yes,locked 2006.210.07:42:41.65/valo/07,832.99,yes,locked 2006.210.07:42:41.65/valo/08,852.99,yes,locked 2006.210.07:42:42.74/vb/01,04,usb,yes,29,27 2006.210.07:42:42.74/vb/02,04,usb,yes,30,32 2006.210.07:42:42.74/vb/03,03,usb,yes,33,38 2006.210.07:42:42.74/vb/04,03,usb,yes,34,34 2006.210.07:42:42.74/vb/05,03,usb,yes,33,37 2006.210.07:42:42.74/vb/06,03,usb,yes,33,37 2006.210.07:42:42.74/vb/07,04,usb,yes,29,29 2006.210.07:42:42.74/vb/08,03,usb,yes,33,37 2006.210.07:42:42.98/vblo/01,632.99,yes,locked 2006.210.07:42:42.98/vblo/02,640.99,yes,locked 2006.210.07:42:42.98/vblo/03,656.99,yes,locked 2006.210.07:42:42.98/vblo/04,712.99,yes,locked 2006.210.07:42:42.98/vblo/05,744.99,yes,locked 2006.210.07:42:42.98/vblo/06,752.99,yes,locked 2006.210.07:42:42.98/vblo/07,734.99,yes,locked 2006.210.07:42:42.98/vblo/08,744.99,yes,locked 2006.210.07:42:43.13/vabw/8 2006.210.07:42:43.28/vbbw/8 2006.210.07:42:43.37/xfe/off,on,13.0 2006.210.07:42:43.74/ifatt/23,28,28,28 2006.210.07:42:44.07/fmout-gps/S +4.47E-07 2006.210.07:42:44.11:!2006.210.07:43:40 2006.210.07:43:40.00:data_valid=off 2006.210.07:43:40.00:postob 2006.210.07:43:40.22/cable/+6.3943E-03 2006.210.07:43:40.22/wx/30.56,1006.2,75 2006.210.07:43:41.07/fmout-gps/S +4.50E-07 2006.210.07:43:41.07:scan_name=210-0744,k06210,60 2006.210.07:43:41.07:source=3c371,180650.68,694928.1,2000.0,cw 2006.210.07:43:41.14#flagr#flagr/antenna,new-source 2006.210.07:43:42.14:checkk5 2006.210.07:43:42.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:43:42.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:43:43.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:43:43.52/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:43:43.85/chk_obsdata//k5ts1/T2100742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:43:44.18/chk_obsdata//k5ts2/T2100742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:43:44.51/chk_obsdata//k5ts3/T2100742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:43:44.84/chk_obsdata//k5ts4/T2100742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:43:45.50/k5log//k5ts1_log_newline 2006.210.07:43:46.16/k5log//k5ts2_log_newline 2006.210.07:43:46.82/k5log//k5ts3_log_newline 2006.210.07:43:47.48/k5log//k5ts4_log_newline 2006.210.07:43:47.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:43:47.51:4f8m12a=1 2006.210.07:43:47.51$4f8m12a/echo=on 2006.210.07:43:47.51$4f8m12a/pcalon 2006.210.07:43:47.51$pcalon/"no phase cal control is implemented here 2006.210.07:43:47.51$4f8m12a/"tpicd=stop 2006.210.07:43:47.51$4f8m12a/vc4f8 2006.210.07:43:47.51$vc4f8/valo=1,532.99 2006.210.07:43:47.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.07:43:47.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.07:43:47.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:47.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:47.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:47.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:47.51#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:43:47.51#ibcon#first serial, iclass 18, count 0 2006.210.07:43:47.51#ibcon#enter sib2, iclass 18, count 0 2006.210.07:43:47.51#ibcon#flushed, iclass 18, count 0 2006.210.07:43:47.51#ibcon#about to write, iclass 18, count 0 2006.210.07:43:47.51#ibcon#wrote, iclass 18, count 0 2006.210.07:43:47.51#ibcon#about to read 3, iclass 18, count 0 2006.210.07:43:47.52#ibcon#read 3, iclass 18, count 0 2006.210.07:43:47.52#ibcon#about to read 4, iclass 18, count 0 2006.210.07:43:47.52#ibcon#read 4, iclass 18, count 0 2006.210.07:43:47.52#ibcon#about to read 5, iclass 18, count 0 2006.210.07:43:47.52#ibcon#read 5, iclass 18, count 0 2006.210.07:43:47.52#ibcon#about to read 6, iclass 18, count 0 2006.210.07:43:47.52#ibcon#read 6, iclass 18, count 0 2006.210.07:43:47.52#ibcon#end of sib2, iclass 18, count 0 2006.210.07:43:47.52#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:43:47.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:43:47.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:43:47.52#ibcon#*before write, iclass 18, count 0 2006.210.07:43:47.52#ibcon#enter sib2, iclass 18, count 0 2006.210.07:43:47.52#ibcon#flushed, iclass 18, count 0 2006.210.07:43:47.52#ibcon#about to write, iclass 18, count 0 2006.210.07:43:47.52#ibcon#wrote, iclass 18, count 0 2006.210.07:43:47.52#ibcon#about to read 3, iclass 18, count 0 2006.210.07:43:47.57#ibcon#read 3, iclass 18, count 0 2006.210.07:43:47.57#ibcon#about to read 4, iclass 18, count 0 2006.210.07:43:47.57#ibcon#read 4, iclass 18, count 0 2006.210.07:43:47.57#ibcon#about to read 5, iclass 18, count 0 2006.210.07:43:47.57#ibcon#read 5, iclass 18, count 0 2006.210.07:43:47.57#ibcon#about to read 6, iclass 18, count 0 2006.210.07:43:47.57#ibcon#read 6, iclass 18, count 0 2006.210.07:43:47.57#ibcon#end of sib2, iclass 18, count 0 2006.210.07:43:47.57#ibcon#*after write, iclass 18, count 0 2006.210.07:43:47.57#ibcon#*before return 0, iclass 18, count 0 2006.210.07:43:47.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:47.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:47.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:43:47.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:43:47.57$vc4f8/va=1,8 2006.210.07:43:47.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.07:43:47.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.07:43:47.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:47.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:47.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:47.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:47.57#ibcon#enter wrdev, iclass 20, count 2 2006.210.07:43:47.57#ibcon#first serial, iclass 20, count 2 2006.210.07:43:47.57#ibcon#enter sib2, iclass 20, count 2 2006.210.07:43:47.57#ibcon#flushed, iclass 20, count 2 2006.210.07:43:47.57#ibcon#about to write, iclass 20, count 2 2006.210.07:43:47.57#ibcon#wrote, iclass 20, count 2 2006.210.07:43:47.57#ibcon#about to read 3, iclass 20, count 2 2006.210.07:43:47.59#ibcon#read 3, iclass 20, count 2 2006.210.07:43:47.59#ibcon#about to read 4, iclass 20, count 2 2006.210.07:43:47.59#ibcon#read 4, iclass 20, count 2 2006.210.07:43:47.59#ibcon#about to read 5, iclass 20, count 2 2006.210.07:43:47.59#ibcon#read 5, iclass 20, count 2 2006.210.07:43:47.59#ibcon#about to read 6, iclass 20, count 2 2006.210.07:43:47.59#ibcon#read 6, iclass 20, count 2 2006.210.07:43:47.59#ibcon#end of sib2, iclass 20, count 2 2006.210.07:43:47.59#ibcon#*mode == 0, iclass 20, count 2 2006.210.07:43:47.59#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.07:43:47.59#ibcon#[25=AT01-08\r\n] 2006.210.07:43:47.59#ibcon#*before write, iclass 20, count 2 2006.210.07:43:47.59#ibcon#enter sib2, iclass 20, count 2 2006.210.07:43:47.59#ibcon#flushed, iclass 20, count 2 2006.210.07:43:47.59#ibcon#about to write, iclass 20, count 2 2006.210.07:43:47.59#ibcon#wrote, iclass 20, count 2 2006.210.07:43:47.59#ibcon#about to read 3, iclass 20, count 2 2006.210.07:43:47.62#ibcon#read 3, iclass 20, count 2 2006.210.07:43:47.62#ibcon#about to read 4, iclass 20, count 2 2006.210.07:43:47.62#ibcon#read 4, iclass 20, count 2 2006.210.07:43:47.62#ibcon#about to read 5, iclass 20, count 2 2006.210.07:43:47.62#ibcon#read 5, iclass 20, count 2 2006.210.07:43:47.62#ibcon#about to read 6, iclass 20, count 2 2006.210.07:43:47.62#ibcon#read 6, iclass 20, count 2 2006.210.07:43:47.62#ibcon#end of sib2, iclass 20, count 2 2006.210.07:43:47.62#ibcon#*after write, iclass 20, count 2 2006.210.07:43:47.62#ibcon#*before return 0, iclass 20, count 2 2006.210.07:43:47.62#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:47.62#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:47.62#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.07:43:47.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:47.62#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:47.74#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:47.74#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:47.74#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:43:47.74#ibcon#first serial, iclass 20, count 0 2006.210.07:43:47.74#ibcon#enter sib2, iclass 20, count 0 2006.210.07:43:47.74#ibcon#flushed, iclass 20, count 0 2006.210.07:43:47.74#ibcon#about to write, iclass 20, count 0 2006.210.07:43:47.74#ibcon#wrote, iclass 20, count 0 2006.210.07:43:47.74#ibcon#about to read 3, iclass 20, count 0 2006.210.07:43:47.76#ibcon#read 3, iclass 20, count 0 2006.210.07:43:47.76#ibcon#about to read 4, iclass 20, count 0 2006.210.07:43:47.76#ibcon#read 4, iclass 20, count 0 2006.210.07:43:47.76#ibcon#about to read 5, iclass 20, count 0 2006.210.07:43:47.76#ibcon#read 5, iclass 20, count 0 2006.210.07:43:47.76#ibcon#about to read 6, iclass 20, count 0 2006.210.07:43:47.76#ibcon#read 6, iclass 20, count 0 2006.210.07:43:47.76#ibcon#end of sib2, iclass 20, count 0 2006.210.07:43:47.76#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:43:47.76#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:43:47.76#ibcon#[25=USB\r\n] 2006.210.07:43:47.76#ibcon#*before write, iclass 20, count 0 2006.210.07:43:47.76#ibcon#enter sib2, iclass 20, count 0 2006.210.07:43:47.76#ibcon#flushed, iclass 20, count 0 2006.210.07:43:47.76#ibcon#about to write, iclass 20, count 0 2006.210.07:43:47.76#ibcon#wrote, iclass 20, count 0 2006.210.07:43:47.76#ibcon#about to read 3, iclass 20, count 0 2006.210.07:43:47.79#ibcon#read 3, iclass 20, count 0 2006.210.07:43:47.79#ibcon#about to read 4, iclass 20, count 0 2006.210.07:43:47.79#ibcon#read 4, iclass 20, count 0 2006.210.07:43:47.79#ibcon#about to read 5, iclass 20, count 0 2006.210.07:43:47.79#ibcon#read 5, iclass 20, count 0 2006.210.07:43:47.79#ibcon#about to read 6, iclass 20, count 0 2006.210.07:43:47.79#ibcon#read 6, iclass 20, count 0 2006.210.07:43:47.79#ibcon#end of sib2, iclass 20, count 0 2006.210.07:43:47.79#ibcon#*after write, iclass 20, count 0 2006.210.07:43:47.79#ibcon#*before return 0, iclass 20, count 0 2006.210.07:43:47.79#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:47.79#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:47.79#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:43:47.79#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:43:47.79$vc4f8/valo=2,572.99 2006.210.07:43:47.79#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:43:47.79#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:43:47.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:47.79#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:47.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:47.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:47.79#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:43:47.79#ibcon#first serial, iclass 22, count 0 2006.210.07:43:47.79#ibcon#enter sib2, iclass 22, count 0 2006.210.07:43:47.79#ibcon#flushed, iclass 22, count 0 2006.210.07:43:47.79#ibcon#about to write, iclass 22, count 0 2006.210.07:43:47.79#ibcon#wrote, iclass 22, count 0 2006.210.07:43:47.79#ibcon#about to read 3, iclass 22, count 0 2006.210.07:43:47.81#ibcon#read 3, iclass 22, count 0 2006.210.07:43:47.81#ibcon#about to read 4, iclass 22, count 0 2006.210.07:43:47.81#ibcon#read 4, iclass 22, count 0 2006.210.07:43:47.81#ibcon#about to read 5, iclass 22, count 0 2006.210.07:43:47.81#ibcon#read 5, iclass 22, count 0 2006.210.07:43:47.81#ibcon#about to read 6, iclass 22, count 0 2006.210.07:43:47.81#ibcon#read 6, iclass 22, count 0 2006.210.07:43:47.81#ibcon#end of sib2, iclass 22, count 0 2006.210.07:43:47.81#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:43:47.81#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:43:47.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:43:47.81#ibcon#*before write, iclass 22, count 0 2006.210.07:43:47.81#ibcon#enter sib2, iclass 22, count 0 2006.210.07:43:47.81#ibcon#flushed, iclass 22, count 0 2006.210.07:43:47.81#ibcon#about to write, iclass 22, count 0 2006.210.07:43:47.81#ibcon#wrote, iclass 22, count 0 2006.210.07:43:47.81#ibcon#about to read 3, iclass 22, count 0 2006.210.07:43:47.85#ibcon#read 3, iclass 22, count 0 2006.210.07:43:47.85#ibcon#about to read 4, iclass 22, count 0 2006.210.07:43:47.85#ibcon#read 4, iclass 22, count 0 2006.210.07:43:47.85#ibcon#about to read 5, iclass 22, count 0 2006.210.07:43:47.85#ibcon#read 5, iclass 22, count 0 2006.210.07:43:47.85#ibcon#about to read 6, iclass 22, count 0 2006.210.07:43:47.85#ibcon#read 6, iclass 22, count 0 2006.210.07:43:47.85#ibcon#end of sib2, iclass 22, count 0 2006.210.07:43:47.85#ibcon#*after write, iclass 22, count 0 2006.210.07:43:47.85#ibcon#*before return 0, iclass 22, count 0 2006.210.07:43:47.85#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:47.85#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:47.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:43:47.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:43:47.85$vc4f8/va=2,7 2006.210.07:43:47.85#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.07:43:47.85#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.07:43:47.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:47.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:47.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:47.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:47.91#ibcon#enter wrdev, iclass 24, count 2 2006.210.07:43:47.91#ibcon#first serial, iclass 24, count 2 2006.210.07:43:47.91#ibcon#enter sib2, iclass 24, count 2 2006.210.07:43:47.91#ibcon#flushed, iclass 24, count 2 2006.210.07:43:47.91#ibcon#about to write, iclass 24, count 2 2006.210.07:43:47.91#ibcon#wrote, iclass 24, count 2 2006.210.07:43:47.91#ibcon#about to read 3, iclass 24, count 2 2006.210.07:43:47.93#ibcon#read 3, iclass 24, count 2 2006.210.07:43:47.93#ibcon#about to read 4, iclass 24, count 2 2006.210.07:43:47.93#ibcon#read 4, iclass 24, count 2 2006.210.07:43:47.93#ibcon#about to read 5, iclass 24, count 2 2006.210.07:43:47.93#ibcon#read 5, iclass 24, count 2 2006.210.07:43:47.93#ibcon#about to read 6, iclass 24, count 2 2006.210.07:43:47.93#ibcon#read 6, iclass 24, count 2 2006.210.07:43:47.93#ibcon#end of sib2, iclass 24, count 2 2006.210.07:43:47.93#ibcon#*mode == 0, iclass 24, count 2 2006.210.07:43:47.93#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.07:43:47.93#ibcon#[25=AT02-07\r\n] 2006.210.07:43:47.93#ibcon#*before write, iclass 24, count 2 2006.210.07:43:47.93#ibcon#enter sib2, iclass 24, count 2 2006.210.07:43:47.93#ibcon#flushed, iclass 24, count 2 2006.210.07:43:47.93#ibcon#about to write, iclass 24, count 2 2006.210.07:43:47.93#ibcon#wrote, iclass 24, count 2 2006.210.07:43:47.93#ibcon#about to read 3, iclass 24, count 2 2006.210.07:43:47.96#ibcon#read 3, iclass 24, count 2 2006.210.07:43:47.96#ibcon#about to read 4, iclass 24, count 2 2006.210.07:43:47.96#ibcon#read 4, iclass 24, count 2 2006.210.07:43:47.96#ibcon#about to read 5, iclass 24, count 2 2006.210.07:43:47.96#ibcon#read 5, iclass 24, count 2 2006.210.07:43:47.96#ibcon#about to read 6, iclass 24, count 2 2006.210.07:43:47.96#ibcon#read 6, iclass 24, count 2 2006.210.07:43:47.96#ibcon#end of sib2, iclass 24, count 2 2006.210.07:43:47.96#ibcon#*after write, iclass 24, count 2 2006.210.07:43:47.96#ibcon#*before return 0, iclass 24, count 2 2006.210.07:43:47.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:47.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:47.96#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.07:43:47.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:47.96#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:48.08#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:48.08#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:48.08#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:43:48.08#ibcon#first serial, iclass 24, count 0 2006.210.07:43:48.08#ibcon#enter sib2, iclass 24, count 0 2006.210.07:43:48.08#ibcon#flushed, iclass 24, count 0 2006.210.07:43:48.08#ibcon#about to write, iclass 24, count 0 2006.210.07:43:48.08#ibcon#wrote, iclass 24, count 0 2006.210.07:43:48.08#ibcon#about to read 3, iclass 24, count 0 2006.210.07:43:48.10#ibcon#read 3, iclass 24, count 0 2006.210.07:43:48.10#ibcon#about to read 4, iclass 24, count 0 2006.210.07:43:48.10#ibcon#read 4, iclass 24, count 0 2006.210.07:43:48.10#ibcon#about to read 5, iclass 24, count 0 2006.210.07:43:48.10#ibcon#read 5, iclass 24, count 0 2006.210.07:43:48.10#ibcon#about to read 6, iclass 24, count 0 2006.210.07:43:48.10#ibcon#read 6, iclass 24, count 0 2006.210.07:43:48.10#ibcon#end of sib2, iclass 24, count 0 2006.210.07:43:48.10#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:43:48.10#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:43:48.10#ibcon#[25=USB\r\n] 2006.210.07:43:48.10#ibcon#*before write, iclass 24, count 0 2006.210.07:43:48.10#ibcon#enter sib2, iclass 24, count 0 2006.210.07:43:48.10#ibcon#flushed, iclass 24, count 0 2006.210.07:43:48.10#ibcon#about to write, iclass 24, count 0 2006.210.07:43:48.10#ibcon#wrote, iclass 24, count 0 2006.210.07:43:48.10#ibcon#about to read 3, iclass 24, count 0 2006.210.07:43:48.13#ibcon#read 3, iclass 24, count 0 2006.210.07:43:48.13#ibcon#about to read 4, iclass 24, count 0 2006.210.07:43:48.13#ibcon#read 4, iclass 24, count 0 2006.210.07:43:48.13#ibcon#about to read 5, iclass 24, count 0 2006.210.07:43:48.13#ibcon#read 5, iclass 24, count 0 2006.210.07:43:48.13#ibcon#about to read 6, iclass 24, count 0 2006.210.07:43:48.13#ibcon#read 6, iclass 24, count 0 2006.210.07:43:48.13#ibcon#end of sib2, iclass 24, count 0 2006.210.07:43:48.13#ibcon#*after write, iclass 24, count 0 2006.210.07:43:48.13#ibcon#*before return 0, iclass 24, count 0 2006.210.07:43:48.13#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:48.13#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:48.13#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:43:48.13#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:43:48.13$vc4f8/valo=3,672.99 2006.210.07:43:48.13#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:43:48.13#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:43:48.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:48.13#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:48.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:48.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:48.13#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:43:48.13#ibcon#first serial, iclass 26, count 0 2006.210.07:43:48.13#ibcon#enter sib2, iclass 26, count 0 2006.210.07:43:48.13#ibcon#flushed, iclass 26, count 0 2006.210.07:43:48.13#ibcon#about to write, iclass 26, count 0 2006.210.07:43:48.13#ibcon#wrote, iclass 26, count 0 2006.210.07:43:48.13#ibcon#about to read 3, iclass 26, count 0 2006.210.07:43:48.15#ibcon#read 3, iclass 26, count 0 2006.210.07:43:48.15#ibcon#about to read 4, iclass 26, count 0 2006.210.07:43:48.15#ibcon#read 4, iclass 26, count 0 2006.210.07:43:48.15#ibcon#about to read 5, iclass 26, count 0 2006.210.07:43:48.15#ibcon#read 5, iclass 26, count 0 2006.210.07:43:48.15#ibcon#about to read 6, iclass 26, count 0 2006.210.07:43:48.15#ibcon#read 6, iclass 26, count 0 2006.210.07:43:48.15#ibcon#end of sib2, iclass 26, count 0 2006.210.07:43:48.15#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:43:48.15#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:43:48.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:43:48.15#ibcon#*before write, iclass 26, count 0 2006.210.07:43:48.15#ibcon#enter sib2, iclass 26, count 0 2006.210.07:43:48.15#ibcon#flushed, iclass 26, count 0 2006.210.07:43:48.15#ibcon#about to write, iclass 26, count 0 2006.210.07:43:48.15#ibcon#wrote, iclass 26, count 0 2006.210.07:43:48.15#ibcon#about to read 3, iclass 26, count 0 2006.210.07:43:48.19#ibcon#read 3, iclass 26, count 0 2006.210.07:43:48.19#ibcon#about to read 4, iclass 26, count 0 2006.210.07:43:48.19#ibcon#read 4, iclass 26, count 0 2006.210.07:43:48.19#ibcon#about to read 5, iclass 26, count 0 2006.210.07:43:48.19#ibcon#read 5, iclass 26, count 0 2006.210.07:43:48.19#ibcon#about to read 6, iclass 26, count 0 2006.210.07:43:48.19#ibcon#read 6, iclass 26, count 0 2006.210.07:43:48.19#ibcon#end of sib2, iclass 26, count 0 2006.210.07:43:48.19#ibcon#*after write, iclass 26, count 0 2006.210.07:43:48.19#ibcon#*before return 0, iclass 26, count 0 2006.210.07:43:48.19#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:48.19#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:48.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:43:48.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:43:48.19$vc4f8/va=3,6 2006.210.07:43:48.19#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.07:43:48.19#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.07:43:48.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:48.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:48.25#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:48.25#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:48.25#ibcon#enter wrdev, iclass 28, count 2 2006.210.07:43:48.25#ibcon#first serial, iclass 28, count 2 2006.210.07:43:48.25#ibcon#enter sib2, iclass 28, count 2 2006.210.07:43:48.25#ibcon#flushed, iclass 28, count 2 2006.210.07:43:48.25#ibcon#about to write, iclass 28, count 2 2006.210.07:43:48.25#ibcon#wrote, iclass 28, count 2 2006.210.07:43:48.25#ibcon#about to read 3, iclass 28, count 2 2006.210.07:43:48.27#ibcon#read 3, iclass 28, count 2 2006.210.07:43:48.27#ibcon#about to read 4, iclass 28, count 2 2006.210.07:43:48.27#ibcon#read 4, iclass 28, count 2 2006.210.07:43:48.27#ibcon#about to read 5, iclass 28, count 2 2006.210.07:43:48.27#ibcon#read 5, iclass 28, count 2 2006.210.07:43:48.27#ibcon#about to read 6, iclass 28, count 2 2006.210.07:43:48.27#ibcon#read 6, iclass 28, count 2 2006.210.07:43:48.27#ibcon#end of sib2, iclass 28, count 2 2006.210.07:43:48.27#ibcon#*mode == 0, iclass 28, count 2 2006.210.07:43:48.27#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.07:43:48.27#ibcon#[25=AT03-06\r\n] 2006.210.07:43:48.27#ibcon#*before write, iclass 28, count 2 2006.210.07:43:48.27#ibcon#enter sib2, iclass 28, count 2 2006.210.07:43:48.27#ibcon#flushed, iclass 28, count 2 2006.210.07:43:48.27#ibcon#about to write, iclass 28, count 2 2006.210.07:43:48.27#ibcon#wrote, iclass 28, count 2 2006.210.07:43:48.27#ibcon#about to read 3, iclass 28, count 2 2006.210.07:43:48.30#ibcon#read 3, iclass 28, count 2 2006.210.07:43:48.30#ibcon#about to read 4, iclass 28, count 2 2006.210.07:43:48.30#ibcon#read 4, iclass 28, count 2 2006.210.07:43:48.30#ibcon#about to read 5, iclass 28, count 2 2006.210.07:43:48.30#ibcon#read 5, iclass 28, count 2 2006.210.07:43:48.30#ibcon#about to read 6, iclass 28, count 2 2006.210.07:43:48.30#ibcon#read 6, iclass 28, count 2 2006.210.07:43:48.30#ibcon#end of sib2, iclass 28, count 2 2006.210.07:43:48.30#ibcon#*after write, iclass 28, count 2 2006.210.07:43:48.30#ibcon#*before return 0, iclass 28, count 2 2006.210.07:43:48.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:48.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:48.30#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.07:43:48.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:48.30#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:48.42#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:48.42#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:48.42#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:43:48.42#ibcon#first serial, iclass 28, count 0 2006.210.07:43:48.42#ibcon#enter sib2, iclass 28, count 0 2006.210.07:43:48.42#ibcon#flushed, iclass 28, count 0 2006.210.07:43:48.42#ibcon#about to write, iclass 28, count 0 2006.210.07:43:48.42#ibcon#wrote, iclass 28, count 0 2006.210.07:43:48.42#ibcon#about to read 3, iclass 28, count 0 2006.210.07:43:48.44#ibcon#read 3, iclass 28, count 0 2006.210.07:43:48.44#ibcon#about to read 4, iclass 28, count 0 2006.210.07:43:48.44#ibcon#read 4, iclass 28, count 0 2006.210.07:43:48.44#ibcon#about to read 5, iclass 28, count 0 2006.210.07:43:48.44#ibcon#read 5, iclass 28, count 0 2006.210.07:43:48.44#ibcon#about to read 6, iclass 28, count 0 2006.210.07:43:48.44#ibcon#read 6, iclass 28, count 0 2006.210.07:43:48.44#ibcon#end of sib2, iclass 28, count 0 2006.210.07:43:48.44#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:43:48.44#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:43:48.44#ibcon#[25=USB\r\n] 2006.210.07:43:48.44#ibcon#*before write, iclass 28, count 0 2006.210.07:43:48.44#ibcon#enter sib2, iclass 28, count 0 2006.210.07:43:48.44#ibcon#flushed, iclass 28, count 0 2006.210.07:43:48.44#ibcon#about to write, iclass 28, count 0 2006.210.07:43:48.44#ibcon#wrote, iclass 28, count 0 2006.210.07:43:48.44#ibcon#about to read 3, iclass 28, count 0 2006.210.07:43:48.47#ibcon#read 3, iclass 28, count 0 2006.210.07:43:48.47#ibcon#about to read 4, iclass 28, count 0 2006.210.07:43:48.47#ibcon#read 4, iclass 28, count 0 2006.210.07:43:48.47#ibcon#about to read 5, iclass 28, count 0 2006.210.07:43:48.47#ibcon#read 5, iclass 28, count 0 2006.210.07:43:48.47#ibcon#about to read 6, iclass 28, count 0 2006.210.07:43:48.47#ibcon#read 6, iclass 28, count 0 2006.210.07:43:48.47#ibcon#end of sib2, iclass 28, count 0 2006.210.07:43:48.47#ibcon#*after write, iclass 28, count 0 2006.210.07:43:48.47#ibcon#*before return 0, iclass 28, count 0 2006.210.07:43:48.47#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:48.47#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:48.47#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:43:48.47#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:43:48.47$vc4f8/valo=4,832.99 2006.210.07:43:48.47#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.07:43:48.47#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.07:43:48.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:48.47#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:48.47#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:48.47#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:48.47#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:43:48.47#ibcon#first serial, iclass 30, count 0 2006.210.07:43:48.47#ibcon#enter sib2, iclass 30, count 0 2006.210.07:43:48.47#ibcon#flushed, iclass 30, count 0 2006.210.07:43:48.47#ibcon#about to write, iclass 30, count 0 2006.210.07:43:48.47#ibcon#wrote, iclass 30, count 0 2006.210.07:43:48.47#ibcon#about to read 3, iclass 30, count 0 2006.210.07:43:48.49#ibcon#read 3, iclass 30, count 0 2006.210.07:43:48.49#ibcon#about to read 4, iclass 30, count 0 2006.210.07:43:48.49#ibcon#read 4, iclass 30, count 0 2006.210.07:43:48.49#ibcon#about to read 5, iclass 30, count 0 2006.210.07:43:48.49#ibcon#read 5, iclass 30, count 0 2006.210.07:43:48.49#ibcon#about to read 6, iclass 30, count 0 2006.210.07:43:48.49#ibcon#read 6, iclass 30, count 0 2006.210.07:43:48.49#ibcon#end of sib2, iclass 30, count 0 2006.210.07:43:48.49#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:43:48.49#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:43:48.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:43:48.49#ibcon#*before write, iclass 30, count 0 2006.210.07:43:48.49#ibcon#enter sib2, iclass 30, count 0 2006.210.07:43:48.49#ibcon#flushed, iclass 30, count 0 2006.210.07:43:48.49#ibcon#about to write, iclass 30, count 0 2006.210.07:43:48.49#ibcon#wrote, iclass 30, count 0 2006.210.07:43:48.49#ibcon#about to read 3, iclass 30, count 0 2006.210.07:43:48.53#ibcon#read 3, iclass 30, count 0 2006.210.07:43:48.53#ibcon#about to read 4, iclass 30, count 0 2006.210.07:43:48.53#ibcon#read 4, iclass 30, count 0 2006.210.07:43:48.53#ibcon#about to read 5, iclass 30, count 0 2006.210.07:43:48.53#ibcon#read 5, iclass 30, count 0 2006.210.07:43:48.53#ibcon#about to read 6, iclass 30, count 0 2006.210.07:43:48.53#ibcon#read 6, iclass 30, count 0 2006.210.07:43:48.53#ibcon#end of sib2, iclass 30, count 0 2006.210.07:43:48.53#ibcon#*after write, iclass 30, count 0 2006.210.07:43:48.53#ibcon#*before return 0, iclass 30, count 0 2006.210.07:43:48.53#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:48.53#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:48.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:43:48.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:43:48.53$vc4f8/va=4,7 2006.210.07:43:48.53#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.07:43:48.53#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.07:43:48.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:48.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:48.59#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:48.59#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:48.59#ibcon#enter wrdev, iclass 32, count 2 2006.210.07:43:48.59#ibcon#first serial, iclass 32, count 2 2006.210.07:43:48.59#ibcon#enter sib2, iclass 32, count 2 2006.210.07:43:48.59#ibcon#flushed, iclass 32, count 2 2006.210.07:43:48.59#ibcon#about to write, iclass 32, count 2 2006.210.07:43:48.59#ibcon#wrote, iclass 32, count 2 2006.210.07:43:48.59#ibcon#about to read 3, iclass 32, count 2 2006.210.07:43:48.61#ibcon#read 3, iclass 32, count 2 2006.210.07:43:48.61#ibcon#about to read 4, iclass 32, count 2 2006.210.07:43:48.61#ibcon#read 4, iclass 32, count 2 2006.210.07:43:48.61#ibcon#about to read 5, iclass 32, count 2 2006.210.07:43:48.61#ibcon#read 5, iclass 32, count 2 2006.210.07:43:48.61#ibcon#about to read 6, iclass 32, count 2 2006.210.07:43:48.61#ibcon#read 6, iclass 32, count 2 2006.210.07:43:48.61#ibcon#end of sib2, iclass 32, count 2 2006.210.07:43:48.61#ibcon#*mode == 0, iclass 32, count 2 2006.210.07:43:48.61#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.07:43:48.61#ibcon#[25=AT04-07\r\n] 2006.210.07:43:48.61#ibcon#*before write, iclass 32, count 2 2006.210.07:43:48.61#ibcon#enter sib2, iclass 32, count 2 2006.210.07:43:48.61#ibcon#flushed, iclass 32, count 2 2006.210.07:43:48.61#ibcon#about to write, iclass 32, count 2 2006.210.07:43:48.61#ibcon#wrote, iclass 32, count 2 2006.210.07:43:48.61#ibcon#about to read 3, iclass 32, count 2 2006.210.07:43:48.64#ibcon#read 3, iclass 32, count 2 2006.210.07:43:48.64#ibcon#about to read 4, iclass 32, count 2 2006.210.07:43:48.64#ibcon#read 4, iclass 32, count 2 2006.210.07:43:48.64#ibcon#about to read 5, iclass 32, count 2 2006.210.07:43:48.64#ibcon#read 5, iclass 32, count 2 2006.210.07:43:48.64#ibcon#about to read 6, iclass 32, count 2 2006.210.07:43:48.64#ibcon#read 6, iclass 32, count 2 2006.210.07:43:48.64#ibcon#end of sib2, iclass 32, count 2 2006.210.07:43:48.64#ibcon#*after write, iclass 32, count 2 2006.210.07:43:48.64#ibcon#*before return 0, iclass 32, count 2 2006.210.07:43:48.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:48.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:48.64#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.07:43:48.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:48.64#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:48.76#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:48.76#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:48.76#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:43:48.76#ibcon#first serial, iclass 32, count 0 2006.210.07:43:48.76#ibcon#enter sib2, iclass 32, count 0 2006.210.07:43:48.76#ibcon#flushed, iclass 32, count 0 2006.210.07:43:48.76#ibcon#about to write, iclass 32, count 0 2006.210.07:43:48.76#ibcon#wrote, iclass 32, count 0 2006.210.07:43:48.76#ibcon#about to read 3, iclass 32, count 0 2006.210.07:43:48.78#ibcon#read 3, iclass 32, count 0 2006.210.07:43:48.78#ibcon#about to read 4, iclass 32, count 0 2006.210.07:43:48.78#ibcon#read 4, iclass 32, count 0 2006.210.07:43:48.78#ibcon#about to read 5, iclass 32, count 0 2006.210.07:43:48.78#ibcon#read 5, iclass 32, count 0 2006.210.07:43:48.78#ibcon#about to read 6, iclass 32, count 0 2006.210.07:43:48.78#ibcon#read 6, iclass 32, count 0 2006.210.07:43:48.78#ibcon#end of sib2, iclass 32, count 0 2006.210.07:43:48.78#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:43:48.78#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:43:48.78#ibcon#[25=USB\r\n] 2006.210.07:43:48.78#ibcon#*before write, iclass 32, count 0 2006.210.07:43:48.78#ibcon#enter sib2, iclass 32, count 0 2006.210.07:43:48.78#ibcon#flushed, iclass 32, count 0 2006.210.07:43:48.78#ibcon#about to write, iclass 32, count 0 2006.210.07:43:48.78#ibcon#wrote, iclass 32, count 0 2006.210.07:43:48.78#ibcon#about to read 3, iclass 32, count 0 2006.210.07:43:48.81#ibcon#read 3, iclass 32, count 0 2006.210.07:43:48.81#ibcon#about to read 4, iclass 32, count 0 2006.210.07:43:48.81#ibcon#read 4, iclass 32, count 0 2006.210.07:43:48.81#ibcon#about to read 5, iclass 32, count 0 2006.210.07:43:48.81#ibcon#read 5, iclass 32, count 0 2006.210.07:43:48.81#ibcon#about to read 6, iclass 32, count 0 2006.210.07:43:48.81#ibcon#read 6, iclass 32, count 0 2006.210.07:43:48.81#ibcon#end of sib2, iclass 32, count 0 2006.210.07:43:48.81#ibcon#*after write, iclass 32, count 0 2006.210.07:43:48.81#ibcon#*before return 0, iclass 32, count 0 2006.210.07:43:48.81#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:48.81#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:48.81#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:43:48.81#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:43:48.81$vc4f8/valo=5,652.99 2006.210.07:43:48.81#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.07:43:48.81#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.07:43:48.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:48.81#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:48.81#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:48.81#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:48.81#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:43:48.81#ibcon#first serial, iclass 34, count 0 2006.210.07:43:48.81#ibcon#enter sib2, iclass 34, count 0 2006.210.07:43:48.81#ibcon#flushed, iclass 34, count 0 2006.210.07:43:48.81#ibcon#about to write, iclass 34, count 0 2006.210.07:43:48.81#ibcon#wrote, iclass 34, count 0 2006.210.07:43:48.81#ibcon#about to read 3, iclass 34, count 0 2006.210.07:43:48.83#ibcon#read 3, iclass 34, count 0 2006.210.07:43:48.83#ibcon#about to read 4, iclass 34, count 0 2006.210.07:43:48.83#ibcon#read 4, iclass 34, count 0 2006.210.07:43:48.83#ibcon#about to read 5, iclass 34, count 0 2006.210.07:43:48.83#ibcon#read 5, iclass 34, count 0 2006.210.07:43:48.83#ibcon#about to read 6, iclass 34, count 0 2006.210.07:43:48.83#ibcon#read 6, iclass 34, count 0 2006.210.07:43:48.83#ibcon#end of sib2, iclass 34, count 0 2006.210.07:43:48.83#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:43:48.83#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:43:48.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:43:48.83#ibcon#*before write, iclass 34, count 0 2006.210.07:43:48.83#ibcon#enter sib2, iclass 34, count 0 2006.210.07:43:48.83#ibcon#flushed, iclass 34, count 0 2006.210.07:43:48.83#ibcon#about to write, iclass 34, count 0 2006.210.07:43:48.83#ibcon#wrote, iclass 34, count 0 2006.210.07:43:48.83#ibcon#about to read 3, iclass 34, count 0 2006.210.07:43:48.87#ibcon#read 3, iclass 34, count 0 2006.210.07:43:48.87#ibcon#about to read 4, iclass 34, count 0 2006.210.07:43:48.87#ibcon#read 4, iclass 34, count 0 2006.210.07:43:48.87#ibcon#about to read 5, iclass 34, count 0 2006.210.07:43:48.87#ibcon#read 5, iclass 34, count 0 2006.210.07:43:48.87#ibcon#about to read 6, iclass 34, count 0 2006.210.07:43:48.87#ibcon#read 6, iclass 34, count 0 2006.210.07:43:48.87#ibcon#end of sib2, iclass 34, count 0 2006.210.07:43:48.87#ibcon#*after write, iclass 34, count 0 2006.210.07:43:48.87#ibcon#*before return 0, iclass 34, count 0 2006.210.07:43:48.87#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:48.87#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:48.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:43:48.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:43:48.87$vc4f8/va=5,7 2006.210.07:43:48.87#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:43:48.87#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:43:48.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:48.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:43:48.91#abcon#<5=/08 1.3 3.9 30.56 751006.2\r\n> 2006.210.07:43:48.93#abcon#{5=INTERFACE CLEAR} 2006.210.07:43:48.93#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:43:48.93#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:43:48.93#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:43:48.93#ibcon#first serial, iclass 37, count 2 2006.210.07:43:48.93#ibcon#enter sib2, iclass 37, count 2 2006.210.07:43:48.93#ibcon#flushed, iclass 37, count 2 2006.210.07:43:48.93#ibcon#about to write, iclass 37, count 2 2006.210.07:43:48.93#ibcon#wrote, iclass 37, count 2 2006.210.07:43:48.93#ibcon#about to read 3, iclass 37, count 2 2006.210.07:43:48.95#ibcon#read 3, iclass 37, count 2 2006.210.07:43:48.95#ibcon#about to read 4, iclass 37, count 2 2006.210.07:43:48.95#ibcon#read 4, iclass 37, count 2 2006.210.07:43:48.95#ibcon#about to read 5, iclass 37, count 2 2006.210.07:43:48.95#ibcon#read 5, iclass 37, count 2 2006.210.07:43:48.95#ibcon#about to read 6, iclass 37, count 2 2006.210.07:43:48.95#ibcon#read 6, iclass 37, count 2 2006.210.07:43:48.95#ibcon#end of sib2, iclass 37, count 2 2006.210.07:43:48.95#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:43:48.95#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:43:48.95#ibcon#[25=AT05-07\r\n] 2006.210.07:43:48.95#ibcon#*before write, iclass 37, count 2 2006.210.07:43:48.95#ibcon#enter sib2, iclass 37, count 2 2006.210.07:43:48.95#ibcon#flushed, iclass 37, count 2 2006.210.07:43:48.95#ibcon#about to write, iclass 37, count 2 2006.210.07:43:48.95#ibcon#wrote, iclass 37, count 2 2006.210.07:43:48.95#ibcon#about to read 3, iclass 37, count 2 2006.210.07:43:48.98#ibcon#read 3, iclass 37, count 2 2006.210.07:43:48.98#ibcon#about to read 4, iclass 37, count 2 2006.210.07:43:48.98#ibcon#read 4, iclass 37, count 2 2006.210.07:43:48.98#ibcon#about to read 5, iclass 37, count 2 2006.210.07:43:48.98#ibcon#read 5, iclass 37, count 2 2006.210.07:43:48.98#ibcon#about to read 6, iclass 37, count 2 2006.210.07:43:48.98#ibcon#read 6, iclass 37, count 2 2006.210.07:43:48.98#ibcon#end of sib2, iclass 37, count 2 2006.210.07:43:48.98#ibcon#*after write, iclass 37, count 2 2006.210.07:43:48.98#ibcon#*before return 0, iclass 37, count 2 2006.210.07:43:48.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:43:48.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:43:48.98#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:43:48.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:48.98#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:43:48.99#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:43:49.10#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:43:49.10#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:43:49.10#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:43:49.10#ibcon#first serial, iclass 37, count 0 2006.210.07:43:49.10#ibcon#enter sib2, iclass 37, count 0 2006.210.07:43:49.10#ibcon#flushed, iclass 37, count 0 2006.210.07:43:49.10#ibcon#about to write, iclass 37, count 0 2006.210.07:43:49.10#ibcon#wrote, iclass 37, count 0 2006.210.07:43:49.10#ibcon#about to read 3, iclass 37, count 0 2006.210.07:43:49.12#ibcon#read 3, iclass 37, count 0 2006.210.07:43:49.12#ibcon#about to read 4, iclass 37, count 0 2006.210.07:43:49.12#ibcon#read 4, iclass 37, count 0 2006.210.07:43:49.12#ibcon#about to read 5, iclass 37, count 0 2006.210.07:43:49.12#ibcon#read 5, iclass 37, count 0 2006.210.07:43:49.12#ibcon#about to read 6, iclass 37, count 0 2006.210.07:43:49.12#ibcon#read 6, iclass 37, count 0 2006.210.07:43:49.12#ibcon#end of sib2, iclass 37, count 0 2006.210.07:43:49.12#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:43:49.12#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:43:49.12#ibcon#[25=USB\r\n] 2006.210.07:43:49.12#ibcon#*before write, iclass 37, count 0 2006.210.07:43:49.12#ibcon#enter sib2, iclass 37, count 0 2006.210.07:43:49.12#ibcon#flushed, iclass 37, count 0 2006.210.07:43:49.12#ibcon#about to write, iclass 37, count 0 2006.210.07:43:49.12#ibcon#wrote, iclass 37, count 0 2006.210.07:43:49.12#ibcon#about to read 3, iclass 37, count 0 2006.210.07:43:49.15#ibcon#read 3, iclass 37, count 0 2006.210.07:43:49.15#ibcon#about to read 4, iclass 37, count 0 2006.210.07:43:49.15#ibcon#read 4, iclass 37, count 0 2006.210.07:43:49.15#ibcon#about to read 5, iclass 37, count 0 2006.210.07:43:49.15#ibcon#read 5, iclass 37, count 0 2006.210.07:43:49.15#ibcon#about to read 6, iclass 37, count 0 2006.210.07:43:49.15#ibcon#read 6, iclass 37, count 0 2006.210.07:43:49.15#ibcon#end of sib2, iclass 37, count 0 2006.210.07:43:49.15#ibcon#*after write, iclass 37, count 0 2006.210.07:43:49.15#ibcon#*before return 0, iclass 37, count 0 2006.210.07:43:49.15#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:43:49.15#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:43:49.15#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:43:49.15#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:43:49.15$vc4f8/valo=6,772.99 2006.210.07:43:49.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.07:43:49.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.07:43:49.15#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:49.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:49.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:49.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:49.15#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:43:49.15#ibcon#first serial, iclass 4, count 0 2006.210.07:43:49.15#ibcon#enter sib2, iclass 4, count 0 2006.210.07:43:49.15#ibcon#flushed, iclass 4, count 0 2006.210.07:43:49.15#ibcon#about to write, iclass 4, count 0 2006.210.07:43:49.15#ibcon#wrote, iclass 4, count 0 2006.210.07:43:49.15#ibcon#about to read 3, iclass 4, count 0 2006.210.07:43:49.17#ibcon#read 3, iclass 4, count 0 2006.210.07:43:49.17#ibcon#about to read 4, iclass 4, count 0 2006.210.07:43:49.17#ibcon#read 4, iclass 4, count 0 2006.210.07:43:49.17#ibcon#about to read 5, iclass 4, count 0 2006.210.07:43:49.17#ibcon#read 5, iclass 4, count 0 2006.210.07:43:49.17#ibcon#about to read 6, iclass 4, count 0 2006.210.07:43:49.17#ibcon#read 6, iclass 4, count 0 2006.210.07:43:49.17#ibcon#end of sib2, iclass 4, count 0 2006.210.07:43:49.17#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:43:49.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:43:49.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:43:49.17#ibcon#*before write, iclass 4, count 0 2006.210.07:43:49.17#ibcon#enter sib2, iclass 4, count 0 2006.210.07:43:49.17#ibcon#flushed, iclass 4, count 0 2006.210.07:43:49.17#ibcon#about to write, iclass 4, count 0 2006.210.07:43:49.17#ibcon#wrote, iclass 4, count 0 2006.210.07:43:49.17#ibcon#about to read 3, iclass 4, count 0 2006.210.07:43:49.21#ibcon#read 3, iclass 4, count 0 2006.210.07:43:49.21#ibcon#about to read 4, iclass 4, count 0 2006.210.07:43:49.21#ibcon#read 4, iclass 4, count 0 2006.210.07:43:49.21#ibcon#about to read 5, iclass 4, count 0 2006.210.07:43:49.21#ibcon#read 5, iclass 4, count 0 2006.210.07:43:49.21#ibcon#about to read 6, iclass 4, count 0 2006.210.07:43:49.21#ibcon#read 6, iclass 4, count 0 2006.210.07:43:49.21#ibcon#end of sib2, iclass 4, count 0 2006.210.07:43:49.21#ibcon#*after write, iclass 4, count 0 2006.210.07:43:49.21#ibcon#*before return 0, iclass 4, count 0 2006.210.07:43:49.21#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:49.21#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:49.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:43:49.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:43:49.21$vc4f8/va=6,6 2006.210.07:43:49.21#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.07:43:49.21#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.07:43:49.21#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:49.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:43:49.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:43:49.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:43:49.27#ibcon#enter wrdev, iclass 6, count 2 2006.210.07:43:49.27#ibcon#first serial, iclass 6, count 2 2006.210.07:43:49.27#ibcon#enter sib2, iclass 6, count 2 2006.210.07:43:49.27#ibcon#flushed, iclass 6, count 2 2006.210.07:43:49.27#ibcon#about to write, iclass 6, count 2 2006.210.07:43:49.27#ibcon#wrote, iclass 6, count 2 2006.210.07:43:49.27#ibcon#about to read 3, iclass 6, count 2 2006.210.07:43:49.29#ibcon#read 3, iclass 6, count 2 2006.210.07:43:49.29#ibcon#about to read 4, iclass 6, count 2 2006.210.07:43:49.29#ibcon#read 4, iclass 6, count 2 2006.210.07:43:49.29#ibcon#about to read 5, iclass 6, count 2 2006.210.07:43:49.29#ibcon#read 5, iclass 6, count 2 2006.210.07:43:49.29#ibcon#about to read 6, iclass 6, count 2 2006.210.07:43:49.29#ibcon#read 6, iclass 6, count 2 2006.210.07:43:49.29#ibcon#end of sib2, iclass 6, count 2 2006.210.07:43:49.29#ibcon#*mode == 0, iclass 6, count 2 2006.210.07:43:49.29#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.07:43:49.29#ibcon#[25=AT06-06\r\n] 2006.210.07:43:49.29#ibcon#*before write, iclass 6, count 2 2006.210.07:43:49.29#ibcon#enter sib2, iclass 6, count 2 2006.210.07:43:49.29#ibcon#flushed, iclass 6, count 2 2006.210.07:43:49.29#ibcon#about to write, iclass 6, count 2 2006.210.07:43:49.29#ibcon#wrote, iclass 6, count 2 2006.210.07:43:49.29#ibcon#about to read 3, iclass 6, count 2 2006.210.07:43:49.32#ibcon#read 3, iclass 6, count 2 2006.210.07:43:49.32#ibcon#about to read 4, iclass 6, count 2 2006.210.07:43:49.32#ibcon#read 4, iclass 6, count 2 2006.210.07:43:49.32#ibcon#about to read 5, iclass 6, count 2 2006.210.07:43:49.32#ibcon#read 5, iclass 6, count 2 2006.210.07:43:49.32#ibcon#about to read 6, iclass 6, count 2 2006.210.07:43:49.32#ibcon#read 6, iclass 6, count 2 2006.210.07:43:49.32#ibcon#end of sib2, iclass 6, count 2 2006.210.07:43:49.32#ibcon#*after write, iclass 6, count 2 2006.210.07:43:49.32#ibcon#*before return 0, iclass 6, count 2 2006.210.07:43:49.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:43:49.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:43:49.32#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.07:43:49.32#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:49.32#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:43:49.44#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:43:49.44#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:43:49.44#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:43:49.44#ibcon#first serial, iclass 6, count 0 2006.210.07:43:49.44#ibcon#enter sib2, iclass 6, count 0 2006.210.07:43:49.44#ibcon#flushed, iclass 6, count 0 2006.210.07:43:49.44#ibcon#about to write, iclass 6, count 0 2006.210.07:43:49.44#ibcon#wrote, iclass 6, count 0 2006.210.07:43:49.44#ibcon#about to read 3, iclass 6, count 0 2006.210.07:43:49.46#ibcon#read 3, iclass 6, count 0 2006.210.07:43:49.46#ibcon#about to read 4, iclass 6, count 0 2006.210.07:43:49.46#ibcon#read 4, iclass 6, count 0 2006.210.07:43:49.46#ibcon#about to read 5, iclass 6, count 0 2006.210.07:43:49.46#ibcon#read 5, iclass 6, count 0 2006.210.07:43:49.46#ibcon#about to read 6, iclass 6, count 0 2006.210.07:43:49.46#ibcon#read 6, iclass 6, count 0 2006.210.07:43:49.46#ibcon#end of sib2, iclass 6, count 0 2006.210.07:43:49.46#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:43:49.46#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:43:49.46#ibcon#[25=USB\r\n] 2006.210.07:43:49.46#ibcon#*before write, iclass 6, count 0 2006.210.07:43:49.46#ibcon#enter sib2, iclass 6, count 0 2006.210.07:43:49.46#ibcon#flushed, iclass 6, count 0 2006.210.07:43:49.46#ibcon#about to write, iclass 6, count 0 2006.210.07:43:49.46#ibcon#wrote, iclass 6, count 0 2006.210.07:43:49.46#ibcon#about to read 3, iclass 6, count 0 2006.210.07:43:49.49#ibcon#read 3, iclass 6, count 0 2006.210.07:43:49.49#ibcon#about to read 4, iclass 6, count 0 2006.210.07:43:49.49#ibcon#read 4, iclass 6, count 0 2006.210.07:43:49.49#ibcon#about to read 5, iclass 6, count 0 2006.210.07:43:49.49#ibcon#read 5, iclass 6, count 0 2006.210.07:43:49.49#ibcon#about to read 6, iclass 6, count 0 2006.210.07:43:49.49#ibcon#read 6, iclass 6, count 0 2006.210.07:43:49.49#ibcon#end of sib2, iclass 6, count 0 2006.210.07:43:49.49#ibcon#*after write, iclass 6, count 0 2006.210.07:43:49.49#ibcon#*before return 0, iclass 6, count 0 2006.210.07:43:49.49#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:43:49.49#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:43:49.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:43:49.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:43:49.49$vc4f8/valo=7,832.99 2006.210.07:43:49.49#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.07:43:49.49#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.07:43:49.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:49.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:43:49.49#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:43:49.49#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:43:49.49#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:43:49.49#ibcon#first serial, iclass 10, count 0 2006.210.07:43:49.49#ibcon#enter sib2, iclass 10, count 0 2006.210.07:43:49.49#ibcon#flushed, iclass 10, count 0 2006.210.07:43:49.49#ibcon#about to write, iclass 10, count 0 2006.210.07:43:49.49#ibcon#wrote, iclass 10, count 0 2006.210.07:43:49.49#ibcon#about to read 3, iclass 10, count 0 2006.210.07:43:49.51#ibcon#read 3, iclass 10, count 0 2006.210.07:43:49.51#ibcon#about to read 4, iclass 10, count 0 2006.210.07:43:49.51#ibcon#read 4, iclass 10, count 0 2006.210.07:43:49.51#ibcon#about to read 5, iclass 10, count 0 2006.210.07:43:49.51#ibcon#read 5, iclass 10, count 0 2006.210.07:43:49.51#ibcon#about to read 6, iclass 10, count 0 2006.210.07:43:49.51#ibcon#read 6, iclass 10, count 0 2006.210.07:43:49.51#ibcon#end of sib2, iclass 10, count 0 2006.210.07:43:49.51#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:43:49.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:43:49.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:43:49.51#ibcon#*before write, iclass 10, count 0 2006.210.07:43:49.51#ibcon#enter sib2, iclass 10, count 0 2006.210.07:43:49.51#ibcon#flushed, iclass 10, count 0 2006.210.07:43:49.51#ibcon#about to write, iclass 10, count 0 2006.210.07:43:49.51#ibcon#wrote, iclass 10, count 0 2006.210.07:43:49.51#ibcon#about to read 3, iclass 10, count 0 2006.210.07:43:49.55#ibcon#read 3, iclass 10, count 0 2006.210.07:43:49.55#ibcon#about to read 4, iclass 10, count 0 2006.210.07:43:49.55#ibcon#read 4, iclass 10, count 0 2006.210.07:43:49.55#ibcon#about to read 5, iclass 10, count 0 2006.210.07:43:49.55#ibcon#read 5, iclass 10, count 0 2006.210.07:43:49.55#ibcon#about to read 6, iclass 10, count 0 2006.210.07:43:49.55#ibcon#read 6, iclass 10, count 0 2006.210.07:43:49.55#ibcon#end of sib2, iclass 10, count 0 2006.210.07:43:49.55#ibcon#*after write, iclass 10, count 0 2006.210.07:43:49.55#ibcon#*before return 0, iclass 10, count 0 2006.210.07:43:49.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:43:49.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:43:49.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:43:49.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:43:49.55$vc4f8/va=7,6 2006.210.07:43:49.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.07:43:49.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.07:43:49.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:49.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:43:49.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:43:49.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:43:49.61#ibcon#enter wrdev, iclass 12, count 2 2006.210.07:43:49.61#ibcon#first serial, iclass 12, count 2 2006.210.07:43:49.61#ibcon#enter sib2, iclass 12, count 2 2006.210.07:43:49.61#ibcon#flushed, iclass 12, count 2 2006.210.07:43:49.61#ibcon#about to write, iclass 12, count 2 2006.210.07:43:49.61#ibcon#wrote, iclass 12, count 2 2006.210.07:43:49.61#ibcon#about to read 3, iclass 12, count 2 2006.210.07:43:49.63#ibcon#read 3, iclass 12, count 2 2006.210.07:43:49.63#ibcon#about to read 4, iclass 12, count 2 2006.210.07:43:49.63#ibcon#read 4, iclass 12, count 2 2006.210.07:43:49.63#ibcon#about to read 5, iclass 12, count 2 2006.210.07:43:49.63#ibcon#read 5, iclass 12, count 2 2006.210.07:43:49.63#ibcon#about to read 6, iclass 12, count 2 2006.210.07:43:49.63#ibcon#read 6, iclass 12, count 2 2006.210.07:43:49.63#ibcon#end of sib2, iclass 12, count 2 2006.210.07:43:49.63#ibcon#*mode == 0, iclass 12, count 2 2006.210.07:43:49.63#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.07:43:49.63#ibcon#[25=AT07-06\r\n] 2006.210.07:43:49.63#ibcon#*before write, iclass 12, count 2 2006.210.07:43:49.63#ibcon#enter sib2, iclass 12, count 2 2006.210.07:43:49.63#ibcon#flushed, iclass 12, count 2 2006.210.07:43:49.63#ibcon#about to write, iclass 12, count 2 2006.210.07:43:49.63#ibcon#wrote, iclass 12, count 2 2006.210.07:43:49.63#ibcon#about to read 3, iclass 12, count 2 2006.210.07:43:49.66#ibcon#read 3, iclass 12, count 2 2006.210.07:43:49.66#ibcon#about to read 4, iclass 12, count 2 2006.210.07:43:49.66#ibcon#read 4, iclass 12, count 2 2006.210.07:43:49.66#ibcon#about to read 5, iclass 12, count 2 2006.210.07:43:49.66#ibcon#read 5, iclass 12, count 2 2006.210.07:43:49.66#ibcon#about to read 6, iclass 12, count 2 2006.210.07:43:49.66#ibcon#read 6, iclass 12, count 2 2006.210.07:43:49.66#ibcon#end of sib2, iclass 12, count 2 2006.210.07:43:49.66#ibcon#*after write, iclass 12, count 2 2006.210.07:43:49.66#ibcon#*before return 0, iclass 12, count 2 2006.210.07:43:49.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:43:49.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:43:49.66#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.07:43:49.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:49.66#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:43:49.78#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:43:49.78#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:43:49.78#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:43:49.78#ibcon#first serial, iclass 12, count 0 2006.210.07:43:49.78#ibcon#enter sib2, iclass 12, count 0 2006.210.07:43:49.78#ibcon#flushed, iclass 12, count 0 2006.210.07:43:49.78#ibcon#about to write, iclass 12, count 0 2006.210.07:43:49.78#ibcon#wrote, iclass 12, count 0 2006.210.07:43:49.78#ibcon#about to read 3, iclass 12, count 0 2006.210.07:43:49.80#ibcon#read 3, iclass 12, count 0 2006.210.07:43:49.80#ibcon#about to read 4, iclass 12, count 0 2006.210.07:43:49.80#ibcon#read 4, iclass 12, count 0 2006.210.07:43:49.80#ibcon#about to read 5, iclass 12, count 0 2006.210.07:43:49.80#ibcon#read 5, iclass 12, count 0 2006.210.07:43:49.80#ibcon#about to read 6, iclass 12, count 0 2006.210.07:43:49.80#ibcon#read 6, iclass 12, count 0 2006.210.07:43:49.80#ibcon#end of sib2, iclass 12, count 0 2006.210.07:43:49.80#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:43:49.80#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:43:49.80#ibcon#[25=USB\r\n] 2006.210.07:43:49.80#ibcon#*before write, iclass 12, count 0 2006.210.07:43:49.80#ibcon#enter sib2, iclass 12, count 0 2006.210.07:43:49.80#ibcon#flushed, iclass 12, count 0 2006.210.07:43:49.80#ibcon#about to write, iclass 12, count 0 2006.210.07:43:49.80#ibcon#wrote, iclass 12, count 0 2006.210.07:43:49.80#ibcon#about to read 3, iclass 12, count 0 2006.210.07:43:49.83#ibcon#read 3, iclass 12, count 0 2006.210.07:43:49.83#ibcon#about to read 4, iclass 12, count 0 2006.210.07:43:49.83#ibcon#read 4, iclass 12, count 0 2006.210.07:43:49.83#ibcon#about to read 5, iclass 12, count 0 2006.210.07:43:49.83#ibcon#read 5, iclass 12, count 0 2006.210.07:43:49.83#ibcon#about to read 6, iclass 12, count 0 2006.210.07:43:49.83#ibcon#read 6, iclass 12, count 0 2006.210.07:43:49.83#ibcon#end of sib2, iclass 12, count 0 2006.210.07:43:49.83#ibcon#*after write, iclass 12, count 0 2006.210.07:43:49.83#ibcon#*before return 0, iclass 12, count 0 2006.210.07:43:49.83#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:43:49.83#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:43:49.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:43:49.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:43:49.83$vc4f8/valo=8,852.99 2006.210.07:43:49.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.07:43:49.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.07:43:49.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:49.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:43:49.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:43:49.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:43:49.83#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:43:49.83#ibcon#first serial, iclass 14, count 0 2006.210.07:43:49.83#ibcon#enter sib2, iclass 14, count 0 2006.210.07:43:49.83#ibcon#flushed, iclass 14, count 0 2006.210.07:43:49.83#ibcon#about to write, iclass 14, count 0 2006.210.07:43:49.83#ibcon#wrote, iclass 14, count 0 2006.210.07:43:49.83#ibcon#about to read 3, iclass 14, count 0 2006.210.07:43:49.85#ibcon#read 3, iclass 14, count 0 2006.210.07:43:49.85#ibcon#about to read 4, iclass 14, count 0 2006.210.07:43:49.85#ibcon#read 4, iclass 14, count 0 2006.210.07:43:49.85#ibcon#about to read 5, iclass 14, count 0 2006.210.07:43:49.85#ibcon#read 5, iclass 14, count 0 2006.210.07:43:49.85#ibcon#about to read 6, iclass 14, count 0 2006.210.07:43:49.85#ibcon#read 6, iclass 14, count 0 2006.210.07:43:49.85#ibcon#end of sib2, iclass 14, count 0 2006.210.07:43:49.85#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:43:49.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:43:49.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:43:49.85#ibcon#*before write, iclass 14, count 0 2006.210.07:43:49.85#ibcon#enter sib2, iclass 14, count 0 2006.210.07:43:49.85#ibcon#flushed, iclass 14, count 0 2006.210.07:43:49.85#ibcon#about to write, iclass 14, count 0 2006.210.07:43:49.85#ibcon#wrote, iclass 14, count 0 2006.210.07:43:49.85#ibcon#about to read 3, iclass 14, count 0 2006.210.07:43:49.89#ibcon#read 3, iclass 14, count 0 2006.210.07:43:49.89#ibcon#about to read 4, iclass 14, count 0 2006.210.07:43:49.89#ibcon#read 4, iclass 14, count 0 2006.210.07:43:49.89#ibcon#about to read 5, iclass 14, count 0 2006.210.07:43:49.89#ibcon#read 5, iclass 14, count 0 2006.210.07:43:49.89#ibcon#about to read 6, iclass 14, count 0 2006.210.07:43:49.89#ibcon#read 6, iclass 14, count 0 2006.210.07:43:49.89#ibcon#end of sib2, iclass 14, count 0 2006.210.07:43:49.89#ibcon#*after write, iclass 14, count 0 2006.210.07:43:49.89#ibcon#*before return 0, iclass 14, count 0 2006.210.07:43:49.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:43:49.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:43:49.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:43:49.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:43:49.89$vc4f8/va=8,7 2006.210.07:43:49.89#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.07:43:49.89#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.07:43:49.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:49.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:43:49.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:43:49.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:43:49.95#ibcon#enter wrdev, iclass 16, count 2 2006.210.07:43:49.95#ibcon#first serial, iclass 16, count 2 2006.210.07:43:49.95#ibcon#enter sib2, iclass 16, count 2 2006.210.07:43:49.95#ibcon#flushed, iclass 16, count 2 2006.210.07:43:49.95#ibcon#about to write, iclass 16, count 2 2006.210.07:43:49.95#ibcon#wrote, iclass 16, count 2 2006.210.07:43:49.95#ibcon#about to read 3, iclass 16, count 2 2006.210.07:43:49.97#ibcon#read 3, iclass 16, count 2 2006.210.07:43:49.97#ibcon#about to read 4, iclass 16, count 2 2006.210.07:43:49.97#ibcon#read 4, iclass 16, count 2 2006.210.07:43:49.97#ibcon#about to read 5, iclass 16, count 2 2006.210.07:43:49.97#ibcon#read 5, iclass 16, count 2 2006.210.07:43:49.97#ibcon#about to read 6, iclass 16, count 2 2006.210.07:43:49.97#ibcon#read 6, iclass 16, count 2 2006.210.07:43:49.97#ibcon#end of sib2, iclass 16, count 2 2006.210.07:43:49.97#ibcon#*mode == 0, iclass 16, count 2 2006.210.07:43:49.97#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.07:43:49.97#ibcon#[25=AT08-07\r\n] 2006.210.07:43:49.97#ibcon#*before write, iclass 16, count 2 2006.210.07:43:49.97#ibcon#enter sib2, iclass 16, count 2 2006.210.07:43:49.97#ibcon#flushed, iclass 16, count 2 2006.210.07:43:49.97#ibcon#about to write, iclass 16, count 2 2006.210.07:43:49.97#ibcon#wrote, iclass 16, count 2 2006.210.07:43:49.97#ibcon#about to read 3, iclass 16, count 2 2006.210.07:43:50.00#ibcon#read 3, iclass 16, count 2 2006.210.07:43:50.00#ibcon#about to read 4, iclass 16, count 2 2006.210.07:43:50.00#ibcon#read 4, iclass 16, count 2 2006.210.07:43:50.00#ibcon#about to read 5, iclass 16, count 2 2006.210.07:43:50.00#ibcon#read 5, iclass 16, count 2 2006.210.07:43:50.00#ibcon#about to read 6, iclass 16, count 2 2006.210.07:43:50.00#ibcon#read 6, iclass 16, count 2 2006.210.07:43:50.00#ibcon#end of sib2, iclass 16, count 2 2006.210.07:43:50.00#ibcon#*after write, iclass 16, count 2 2006.210.07:43:50.00#ibcon#*before return 0, iclass 16, count 2 2006.210.07:43:50.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:43:50.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:43:50.00#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.07:43:50.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:50.00#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:43:50.12#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:43:50.12#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:43:50.12#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:43:50.12#ibcon#first serial, iclass 16, count 0 2006.210.07:43:50.12#ibcon#enter sib2, iclass 16, count 0 2006.210.07:43:50.12#ibcon#flushed, iclass 16, count 0 2006.210.07:43:50.12#ibcon#about to write, iclass 16, count 0 2006.210.07:43:50.12#ibcon#wrote, iclass 16, count 0 2006.210.07:43:50.12#ibcon#about to read 3, iclass 16, count 0 2006.210.07:43:50.14#ibcon#read 3, iclass 16, count 0 2006.210.07:43:50.14#ibcon#about to read 4, iclass 16, count 0 2006.210.07:43:50.14#ibcon#read 4, iclass 16, count 0 2006.210.07:43:50.14#ibcon#about to read 5, iclass 16, count 0 2006.210.07:43:50.14#ibcon#read 5, iclass 16, count 0 2006.210.07:43:50.14#ibcon#about to read 6, iclass 16, count 0 2006.210.07:43:50.14#ibcon#read 6, iclass 16, count 0 2006.210.07:43:50.14#ibcon#end of sib2, iclass 16, count 0 2006.210.07:43:50.14#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:43:50.14#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:43:50.14#ibcon#[25=USB\r\n] 2006.210.07:43:50.14#ibcon#*before write, iclass 16, count 0 2006.210.07:43:50.14#ibcon#enter sib2, iclass 16, count 0 2006.210.07:43:50.14#ibcon#flushed, iclass 16, count 0 2006.210.07:43:50.14#ibcon#about to write, iclass 16, count 0 2006.210.07:43:50.14#ibcon#wrote, iclass 16, count 0 2006.210.07:43:50.14#ibcon#about to read 3, iclass 16, count 0 2006.210.07:43:50.17#ibcon#read 3, iclass 16, count 0 2006.210.07:43:50.17#ibcon#about to read 4, iclass 16, count 0 2006.210.07:43:50.17#ibcon#read 4, iclass 16, count 0 2006.210.07:43:50.17#ibcon#about to read 5, iclass 16, count 0 2006.210.07:43:50.17#ibcon#read 5, iclass 16, count 0 2006.210.07:43:50.17#ibcon#about to read 6, iclass 16, count 0 2006.210.07:43:50.17#ibcon#read 6, iclass 16, count 0 2006.210.07:43:50.17#ibcon#end of sib2, iclass 16, count 0 2006.210.07:43:50.17#ibcon#*after write, iclass 16, count 0 2006.210.07:43:50.17#ibcon#*before return 0, iclass 16, count 0 2006.210.07:43:50.17#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:43:50.17#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:43:50.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:43:50.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:43:50.17$vc4f8/vblo=1,632.99 2006.210.07:43:50.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.07:43:50.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.07:43:50.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:50.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:50.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:50.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:50.17#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:43:50.17#ibcon#first serial, iclass 18, count 0 2006.210.07:43:50.17#ibcon#enter sib2, iclass 18, count 0 2006.210.07:43:50.17#ibcon#flushed, iclass 18, count 0 2006.210.07:43:50.17#ibcon#about to write, iclass 18, count 0 2006.210.07:43:50.17#ibcon#wrote, iclass 18, count 0 2006.210.07:43:50.17#ibcon#about to read 3, iclass 18, count 0 2006.210.07:43:50.19#ibcon#read 3, iclass 18, count 0 2006.210.07:43:50.19#ibcon#about to read 4, iclass 18, count 0 2006.210.07:43:50.19#ibcon#read 4, iclass 18, count 0 2006.210.07:43:50.19#ibcon#about to read 5, iclass 18, count 0 2006.210.07:43:50.19#ibcon#read 5, iclass 18, count 0 2006.210.07:43:50.19#ibcon#about to read 6, iclass 18, count 0 2006.210.07:43:50.19#ibcon#read 6, iclass 18, count 0 2006.210.07:43:50.19#ibcon#end of sib2, iclass 18, count 0 2006.210.07:43:50.19#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:43:50.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:43:50.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:43:50.19#ibcon#*before write, iclass 18, count 0 2006.210.07:43:50.19#ibcon#enter sib2, iclass 18, count 0 2006.210.07:43:50.19#ibcon#flushed, iclass 18, count 0 2006.210.07:43:50.19#ibcon#about to write, iclass 18, count 0 2006.210.07:43:50.19#ibcon#wrote, iclass 18, count 0 2006.210.07:43:50.19#ibcon#about to read 3, iclass 18, count 0 2006.210.07:43:50.23#ibcon#read 3, iclass 18, count 0 2006.210.07:43:50.23#ibcon#about to read 4, iclass 18, count 0 2006.210.07:43:50.23#ibcon#read 4, iclass 18, count 0 2006.210.07:43:50.23#ibcon#about to read 5, iclass 18, count 0 2006.210.07:43:50.23#ibcon#read 5, iclass 18, count 0 2006.210.07:43:50.23#ibcon#about to read 6, iclass 18, count 0 2006.210.07:43:50.23#ibcon#read 6, iclass 18, count 0 2006.210.07:43:50.23#ibcon#end of sib2, iclass 18, count 0 2006.210.07:43:50.23#ibcon#*after write, iclass 18, count 0 2006.210.07:43:50.23#ibcon#*before return 0, iclass 18, count 0 2006.210.07:43:50.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:50.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:43:50.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:43:50.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:43:50.23$vc4f8/vb=1,4 2006.210.07:43:50.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.07:43:50.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.07:43:50.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:50.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:50.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:50.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:50.23#ibcon#enter wrdev, iclass 20, count 2 2006.210.07:43:50.23#ibcon#first serial, iclass 20, count 2 2006.210.07:43:50.23#ibcon#enter sib2, iclass 20, count 2 2006.210.07:43:50.23#ibcon#flushed, iclass 20, count 2 2006.210.07:43:50.23#ibcon#about to write, iclass 20, count 2 2006.210.07:43:50.23#ibcon#wrote, iclass 20, count 2 2006.210.07:43:50.23#ibcon#about to read 3, iclass 20, count 2 2006.210.07:43:50.25#ibcon#read 3, iclass 20, count 2 2006.210.07:43:50.25#ibcon#about to read 4, iclass 20, count 2 2006.210.07:43:50.25#ibcon#read 4, iclass 20, count 2 2006.210.07:43:50.25#ibcon#about to read 5, iclass 20, count 2 2006.210.07:43:50.25#ibcon#read 5, iclass 20, count 2 2006.210.07:43:50.25#ibcon#about to read 6, iclass 20, count 2 2006.210.07:43:50.25#ibcon#read 6, iclass 20, count 2 2006.210.07:43:50.25#ibcon#end of sib2, iclass 20, count 2 2006.210.07:43:50.25#ibcon#*mode == 0, iclass 20, count 2 2006.210.07:43:50.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.07:43:50.25#ibcon#[27=AT01-04\r\n] 2006.210.07:43:50.25#ibcon#*before write, iclass 20, count 2 2006.210.07:43:50.25#ibcon#enter sib2, iclass 20, count 2 2006.210.07:43:50.25#ibcon#flushed, iclass 20, count 2 2006.210.07:43:50.25#ibcon#about to write, iclass 20, count 2 2006.210.07:43:50.25#ibcon#wrote, iclass 20, count 2 2006.210.07:43:50.25#ibcon#about to read 3, iclass 20, count 2 2006.210.07:43:50.28#ibcon#read 3, iclass 20, count 2 2006.210.07:43:50.28#ibcon#about to read 4, iclass 20, count 2 2006.210.07:43:50.28#ibcon#read 4, iclass 20, count 2 2006.210.07:43:50.28#ibcon#about to read 5, iclass 20, count 2 2006.210.07:43:50.28#ibcon#read 5, iclass 20, count 2 2006.210.07:43:50.28#ibcon#about to read 6, iclass 20, count 2 2006.210.07:43:50.28#ibcon#read 6, iclass 20, count 2 2006.210.07:43:50.28#ibcon#end of sib2, iclass 20, count 2 2006.210.07:43:50.28#ibcon#*after write, iclass 20, count 2 2006.210.07:43:50.28#ibcon#*before return 0, iclass 20, count 2 2006.210.07:43:50.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:50.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:43:50.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.07:43:50.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:50.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:50.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:50.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:50.40#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:43:50.40#ibcon#first serial, iclass 20, count 0 2006.210.07:43:50.40#ibcon#enter sib2, iclass 20, count 0 2006.210.07:43:50.40#ibcon#flushed, iclass 20, count 0 2006.210.07:43:50.40#ibcon#about to write, iclass 20, count 0 2006.210.07:43:50.40#ibcon#wrote, iclass 20, count 0 2006.210.07:43:50.40#ibcon#about to read 3, iclass 20, count 0 2006.210.07:43:50.42#ibcon#read 3, iclass 20, count 0 2006.210.07:43:50.42#ibcon#about to read 4, iclass 20, count 0 2006.210.07:43:50.42#ibcon#read 4, iclass 20, count 0 2006.210.07:43:50.42#ibcon#about to read 5, iclass 20, count 0 2006.210.07:43:50.42#ibcon#read 5, iclass 20, count 0 2006.210.07:43:50.42#ibcon#about to read 6, iclass 20, count 0 2006.210.07:43:50.42#ibcon#read 6, iclass 20, count 0 2006.210.07:43:50.42#ibcon#end of sib2, iclass 20, count 0 2006.210.07:43:50.42#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:43:50.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:43:50.42#ibcon#[27=USB\r\n] 2006.210.07:43:50.42#ibcon#*before write, iclass 20, count 0 2006.210.07:43:50.42#ibcon#enter sib2, iclass 20, count 0 2006.210.07:43:50.42#ibcon#flushed, iclass 20, count 0 2006.210.07:43:50.42#ibcon#about to write, iclass 20, count 0 2006.210.07:43:50.42#ibcon#wrote, iclass 20, count 0 2006.210.07:43:50.42#ibcon#about to read 3, iclass 20, count 0 2006.210.07:43:50.45#ibcon#read 3, iclass 20, count 0 2006.210.07:43:50.45#ibcon#about to read 4, iclass 20, count 0 2006.210.07:43:50.45#ibcon#read 4, iclass 20, count 0 2006.210.07:43:50.45#ibcon#about to read 5, iclass 20, count 0 2006.210.07:43:50.45#ibcon#read 5, iclass 20, count 0 2006.210.07:43:50.45#ibcon#about to read 6, iclass 20, count 0 2006.210.07:43:50.45#ibcon#read 6, iclass 20, count 0 2006.210.07:43:50.45#ibcon#end of sib2, iclass 20, count 0 2006.210.07:43:50.45#ibcon#*after write, iclass 20, count 0 2006.210.07:43:50.45#ibcon#*before return 0, iclass 20, count 0 2006.210.07:43:50.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:50.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:43:50.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:43:50.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:43:50.45$vc4f8/vblo=2,640.99 2006.210.07:43:50.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:43:50.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:43:50.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:50.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:50.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:50.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:50.45#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:43:50.45#ibcon#first serial, iclass 22, count 0 2006.210.07:43:50.45#ibcon#enter sib2, iclass 22, count 0 2006.210.07:43:50.45#ibcon#flushed, iclass 22, count 0 2006.210.07:43:50.45#ibcon#about to write, iclass 22, count 0 2006.210.07:43:50.45#ibcon#wrote, iclass 22, count 0 2006.210.07:43:50.45#ibcon#about to read 3, iclass 22, count 0 2006.210.07:43:50.47#ibcon#read 3, iclass 22, count 0 2006.210.07:43:50.47#ibcon#about to read 4, iclass 22, count 0 2006.210.07:43:50.47#ibcon#read 4, iclass 22, count 0 2006.210.07:43:50.47#ibcon#about to read 5, iclass 22, count 0 2006.210.07:43:50.47#ibcon#read 5, iclass 22, count 0 2006.210.07:43:50.47#ibcon#about to read 6, iclass 22, count 0 2006.210.07:43:50.47#ibcon#read 6, iclass 22, count 0 2006.210.07:43:50.47#ibcon#end of sib2, iclass 22, count 0 2006.210.07:43:50.47#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:43:50.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:43:50.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:43:50.47#ibcon#*before write, iclass 22, count 0 2006.210.07:43:50.47#ibcon#enter sib2, iclass 22, count 0 2006.210.07:43:50.47#ibcon#flushed, iclass 22, count 0 2006.210.07:43:50.47#ibcon#about to write, iclass 22, count 0 2006.210.07:43:50.47#ibcon#wrote, iclass 22, count 0 2006.210.07:43:50.47#ibcon#about to read 3, iclass 22, count 0 2006.210.07:43:50.51#ibcon#read 3, iclass 22, count 0 2006.210.07:43:50.51#ibcon#about to read 4, iclass 22, count 0 2006.210.07:43:50.51#ibcon#read 4, iclass 22, count 0 2006.210.07:43:50.51#ibcon#about to read 5, iclass 22, count 0 2006.210.07:43:50.51#ibcon#read 5, iclass 22, count 0 2006.210.07:43:50.51#ibcon#about to read 6, iclass 22, count 0 2006.210.07:43:50.51#ibcon#read 6, iclass 22, count 0 2006.210.07:43:50.51#ibcon#end of sib2, iclass 22, count 0 2006.210.07:43:50.51#ibcon#*after write, iclass 22, count 0 2006.210.07:43:50.51#ibcon#*before return 0, iclass 22, count 0 2006.210.07:43:50.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:50.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:43:50.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:43:50.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:43:50.51$vc4f8/vb=2,4 2006.210.07:43:50.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.07:43:50.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.07:43:50.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:50.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:50.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:50.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:50.57#ibcon#enter wrdev, iclass 24, count 2 2006.210.07:43:50.57#ibcon#first serial, iclass 24, count 2 2006.210.07:43:50.57#ibcon#enter sib2, iclass 24, count 2 2006.210.07:43:50.57#ibcon#flushed, iclass 24, count 2 2006.210.07:43:50.57#ibcon#about to write, iclass 24, count 2 2006.210.07:43:50.57#ibcon#wrote, iclass 24, count 2 2006.210.07:43:50.57#ibcon#about to read 3, iclass 24, count 2 2006.210.07:43:50.59#ibcon#read 3, iclass 24, count 2 2006.210.07:43:50.59#ibcon#about to read 4, iclass 24, count 2 2006.210.07:43:50.59#ibcon#read 4, iclass 24, count 2 2006.210.07:43:50.59#ibcon#about to read 5, iclass 24, count 2 2006.210.07:43:50.59#ibcon#read 5, iclass 24, count 2 2006.210.07:43:50.59#ibcon#about to read 6, iclass 24, count 2 2006.210.07:43:50.59#ibcon#read 6, iclass 24, count 2 2006.210.07:43:50.59#ibcon#end of sib2, iclass 24, count 2 2006.210.07:43:50.59#ibcon#*mode == 0, iclass 24, count 2 2006.210.07:43:50.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.07:43:50.59#ibcon#[27=AT02-04\r\n] 2006.210.07:43:50.59#ibcon#*before write, iclass 24, count 2 2006.210.07:43:50.59#ibcon#enter sib2, iclass 24, count 2 2006.210.07:43:50.59#ibcon#flushed, iclass 24, count 2 2006.210.07:43:50.59#ibcon#about to write, iclass 24, count 2 2006.210.07:43:50.59#ibcon#wrote, iclass 24, count 2 2006.210.07:43:50.59#ibcon#about to read 3, iclass 24, count 2 2006.210.07:43:50.62#ibcon#read 3, iclass 24, count 2 2006.210.07:43:50.62#ibcon#about to read 4, iclass 24, count 2 2006.210.07:43:50.62#ibcon#read 4, iclass 24, count 2 2006.210.07:43:50.62#ibcon#about to read 5, iclass 24, count 2 2006.210.07:43:50.62#ibcon#read 5, iclass 24, count 2 2006.210.07:43:50.62#ibcon#about to read 6, iclass 24, count 2 2006.210.07:43:50.62#ibcon#read 6, iclass 24, count 2 2006.210.07:43:50.62#ibcon#end of sib2, iclass 24, count 2 2006.210.07:43:50.62#ibcon#*after write, iclass 24, count 2 2006.210.07:43:50.62#ibcon#*before return 0, iclass 24, count 2 2006.210.07:43:50.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:50.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:43:50.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.07:43:50.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:50.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:50.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:50.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:50.74#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:43:50.74#ibcon#first serial, iclass 24, count 0 2006.210.07:43:50.74#ibcon#enter sib2, iclass 24, count 0 2006.210.07:43:50.74#ibcon#flushed, iclass 24, count 0 2006.210.07:43:50.74#ibcon#about to write, iclass 24, count 0 2006.210.07:43:50.74#ibcon#wrote, iclass 24, count 0 2006.210.07:43:50.74#ibcon#about to read 3, iclass 24, count 0 2006.210.07:43:50.76#ibcon#read 3, iclass 24, count 0 2006.210.07:43:50.76#ibcon#about to read 4, iclass 24, count 0 2006.210.07:43:50.76#ibcon#read 4, iclass 24, count 0 2006.210.07:43:50.76#ibcon#about to read 5, iclass 24, count 0 2006.210.07:43:50.76#ibcon#read 5, iclass 24, count 0 2006.210.07:43:50.76#ibcon#about to read 6, iclass 24, count 0 2006.210.07:43:50.76#ibcon#read 6, iclass 24, count 0 2006.210.07:43:50.76#ibcon#end of sib2, iclass 24, count 0 2006.210.07:43:50.76#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:43:50.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:43:50.76#ibcon#[27=USB\r\n] 2006.210.07:43:50.76#ibcon#*before write, iclass 24, count 0 2006.210.07:43:50.76#ibcon#enter sib2, iclass 24, count 0 2006.210.07:43:50.76#ibcon#flushed, iclass 24, count 0 2006.210.07:43:50.76#ibcon#about to write, iclass 24, count 0 2006.210.07:43:50.76#ibcon#wrote, iclass 24, count 0 2006.210.07:43:50.76#ibcon#about to read 3, iclass 24, count 0 2006.210.07:43:50.79#ibcon#read 3, iclass 24, count 0 2006.210.07:43:50.79#ibcon#about to read 4, iclass 24, count 0 2006.210.07:43:50.79#ibcon#read 4, iclass 24, count 0 2006.210.07:43:50.79#ibcon#about to read 5, iclass 24, count 0 2006.210.07:43:50.79#ibcon#read 5, iclass 24, count 0 2006.210.07:43:50.79#ibcon#about to read 6, iclass 24, count 0 2006.210.07:43:50.79#ibcon#read 6, iclass 24, count 0 2006.210.07:43:50.79#ibcon#end of sib2, iclass 24, count 0 2006.210.07:43:50.79#ibcon#*after write, iclass 24, count 0 2006.210.07:43:50.79#ibcon#*before return 0, iclass 24, count 0 2006.210.07:43:50.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:50.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:43:50.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:43:50.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:43:50.79$vc4f8/vblo=3,656.99 2006.210.07:43:50.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:43:50.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:43:50.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:50.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:50.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:50.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:50.79#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:43:50.79#ibcon#first serial, iclass 26, count 0 2006.210.07:43:50.79#ibcon#enter sib2, iclass 26, count 0 2006.210.07:43:50.79#ibcon#flushed, iclass 26, count 0 2006.210.07:43:50.79#ibcon#about to write, iclass 26, count 0 2006.210.07:43:50.79#ibcon#wrote, iclass 26, count 0 2006.210.07:43:50.79#ibcon#about to read 3, iclass 26, count 0 2006.210.07:43:50.81#ibcon#read 3, iclass 26, count 0 2006.210.07:43:50.81#ibcon#about to read 4, iclass 26, count 0 2006.210.07:43:50.81#ibcon#read 4, iclass 26, count 0 2006.210.07:43:50.81#ibcon#about to read 5, iclass 26, count 0 2006.210.07:43:50.81#ibcon#read 5, iclass 26, count 0 2006.210.07:43:50.81#ibcon#about to read 6, iclass 26, count 0 2006.210.07:43:50.81#ibcon#read 6, iclass 26, count 0 2006.210.07:43:50.81#ibcon#end of sib2, iclass 26, count 0 2006.210.07:43:50.81#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:43:50.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:43:50.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:43:50.81#ibcon#*before write, iclass 26, count 0 2006.210.07:43:50.81#ibcon#enter sib2, iclass 26, count 0 2006.210.07:43:50.81#ibcon#flushed, iclass 26, count 0 2006.210.07:43:50.81#ibcon#about to write, iclass 26, count 0 2006.210.07:43:50.81#ibcon#wrote, iclass 26, count 0 2006.210.07:43:50.81#ibcon#about to read 3, iclass 26, count 0 2006.210.07:43:50.85#ibcon#read 3, iclass 26, count 0 2006.210.07:43:50.85#ibcon#about to read 4, iclass 26, count 0 2006.210.07:43:50.85#ibcon#read 4, iclass 26, count 0 2006.210.07:43:50.85#ibcon#about to read 5, iclass 26, count 0 2006.210.07:43:50.85#ibcon#read 5, iclass 26, count 0 2006.210.07:43:50.85#ibcon#about to read 6, iclass 26, count 0 2006.210.07:43:50.85#ibcon#read 6, iclass 26, count 0 2006.210.07:43:50.85#ibcon#end of sib2, iclass 26, count 0 2006.210.07:43:50.85#ibcon#*after write, iclass 26, count 0 2006.210.07:43:50.85#ibcon#*before return 0, iclass 26, count 0 2006.210.07:43:50.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:50.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:43:50.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:43:50.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:43:50.85$vc4f8/vb=3,3 2006.210.07:43:50.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.07:43:50.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.07:43:50.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:50.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:50.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:50.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:50.91#ibcon#enter wrdev, iclass 28, count 2 2006.210.07:43:50.91#ibcon#first serial, iclass 28, count 2 2006.210.07:43:50.91#ibcon#enter sib2, iclass 28, count 2 2006.210.07:43:50.91#ibcon#flushed, iclass 28, count 2 2006.210.07:43:50.91#ibcon#about to write, iclass 28, count 2 2006.210.07:43:50.91#ibcon#wrote, iclass 28, count 2 2006.210.07:43:50.91#ibcon#about to read 3, iclass 28, count 2 2006.210.07:43:50.93#ibcon#read 3, iclass 28, count 2 2006.210.07:43:50.93#ibcon#about to read 4, iclass 28, count 2 2006.210.07:43:50.93#ibcon#read 4, iclass 28, count 2 2006.210.07:43:50.93#ibcon#about to read 5, iclass 28, count 2 2006.210.07:43:50.93#ibcon#read 5, iclass 28, count 2 2006.210.07:43:50.93#ibcon#about to read 6, iclass 28, count 2 2006.210.07:43:50.93#ibcon#read 6, iclass 28, count 2 2006.210.07:43:50.93#ibcon#end of sib2, iclass 28, count 2 2006.210.07:43:50.93#ibcon#*mode == 0, iclass 28, count 2 2006.210.07:43:50.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.07:43:50.93#ibcon#[27=AT03-03\r\n] 2006.210.07:43:50.93#ibcon#*before write, iclass 28, count 2 2006.210.07:43:50.93#ibcon#enter sib2, iclass 28, count 2 2006.210.07:43:50.93#ibcon#flushed, iclass 28, count 2 2006.210.07:43:50.93#ibcon#about to write, iclass 28, count 2 2006.210.07:43:50.93#ibcon#wrote, iclass 28, count 2 2006.210.07:43:50.93#ibcon#about to read 3, iclass 28, count 2 2006.210.07:43:50.96#ibcon#read 3, iclass 28, count 2 2006.210.07:43:50.96#ibcon#about to read 4, iclass 28, count 2 2006.210.07:43:50.96#ibcon#read 4, iclass 28, count 2 2006.210.07:43:50.96#ibcon#about to read 5, iclass 28, count 2 2006.210.07:43:50.96#ibcon#read 5, iclass 28, count 2 2006.210.07:43:50.96#ibcon#about to read 6, iclass 28, count 2 2006.210.07:43:50.96#ibcon#read 6, iclass 28, count 2 2006.210.07:43:50.96#ibcon#end of sib2, iclass 28, count 2 2006.210.07:43:50.96#ibcon#*after write, iclass 28, count 2 2006.210.07:43:50.96#ibcon#*before return 0, iclass 28, count 2 2006.210.07:43:50.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:50.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:43:50.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.07:43:50.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:50.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:51.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:51.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:51.08#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:43:51.08#ibcon#first serial, iclass 28, count 0 2006.210.07:43:51.08#ibcon#enter sib2, iclass 28, count 0 2006.210.07:43:51.08#ibcon#flushed, iclass 28, count 0 2006.210.07:43:51.08#ibcon#about to write, iclass 28, count 0 2006.210.07:43:51.08#ibcon#wrote, iclass 28, count 0 2006.210.07:43:51.08#ibcon#about to read 3, iclass 28, count 0 2006.210.07:43:51.10#ibcon#read 3, iclass 28, count 0 2006.210.07:43:51.10#ibcon#about to read 4, iclass 28, count 0 2006.210.07:43:51.10#ibcon#read 4, iclass 28, count 0 2006.210.07:43:51.10#ibcon#about to read 5, iclass 28, count 0 2006.210.07:43:51.10#ibcon#read 5, iclass 28, count 0 2006.210.07:43:51.10#ibcon#about to read 6, iclass 28, count 0 2006.210.07:43:51.10#ibcon#read 6, iclass 28, count 0 2006.210.07:43:51.10#ibcon#end of sib2, iclass 28, count 0 2006.210.07:43:51.10#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:43:51.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:43:51.10#ibcon#[27=USB\r\n] 2006.210.07:43:51.10#ibcon#*before write, iclass 28, count 0 2006.210.07:43:51.10#ibcon#enter sib2, iclass 28, count 0 2006.210.07:43:51.10#ibcon#flushed, iclass 28, count 0 2006.210.07:43:51.10#ibcon#about to write, iclass 28, count 0 2006.210.07:43:51.10#ibcon#wrote, iclass 28, count 0 2006.210.07:43:51.10#ibcon#about to read 3, iclass 28, count 0 2006.210.07:43:51.13#ibcon#read 3, iclass 28, count 0 2006.210.07:43:51.13#ibcon#about to read 4, iclass 28, count 0 2006.210.07:43:51.13#ibcon#read 4, iclass 28, count 0 2006.210.07:43:51.13#ibcon#about to read 5, iclass 28, count 0 2006.210.07:43:51.13#ibcon#read 5, iclass 28, count 0 2006.210.07:43:51.13#ibcon#about to read 6, iclass 28, count 0 2006.210.07:43:51.13#ibcon#read 6, iclass 28, count 0 2006.210.07:43:51.13#ibcon#end of sib2, iclass 28, count 0 2006.210.07:43:51.13#ibcon#*after write, iclass 28, count 0 2006.210.07:43:51.13#ibcon#*before return 0, iclass 28, count 0 2006.210.07:43:51.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:51.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:43:51.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:43:51.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:43:51.13$vc4f8/vblo=4,712.99 2006.210.07:43:51.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.07:43:51.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.07:43:51.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:51.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:51.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:51.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:51.13#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:43:51.13#ibcon#first serial, iclass 30, count 0 2006.210.07:43:51.13#ibcon#enter sib2, iclass 30, count 0 2006.210.07:43:51.13#ibcon#flushed, iclass 30, count 0 2006.210.07:43:51.13#ibcon#about to write, iclass 30, count 0 2006.210.07:43:51.13#ibcon#wrote, iclass 30, count 0 2006.210.07:43:51.13#ibcon#about to read 3, iclass 30, count 0 2006.210.07:43:51.15#ibcon#read 3, iclass 30, count 0 2006.210.07:43:51.15#ibcon#about to read 4, iclass 30, count 0 2006.210.07:43:51.15#ibcon#read 4, iclass 30, count 0 2006.210.07:43:51.15#ibcon#about to read 5, iclass 30, count 0 2006.210.07:43:51.15#ibcon#read 5, iclass 30, count 0 2006.210.07:43:51.15#ibcon#about to read 6, iclass 30, count 0 2006.210.07:43:51.15#ibcon#read 6, iclass 30, count 0 2006.210.07:43:51.15#ibcon#end of sib2, iclass 30, count 0 2006.210.07:43:51.15#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:43:51.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:43:51.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:43:51.15#ibcon#*before write, iclass 30, count 0 2006.210.07:43:51.15#ibcon#enter sib2, iclass 30, count 0 2006.210.07:43:51.15#ibcon#flushed, iclass 30, count 0 2006.210.07:43:51.15#ibcon#about to write, iclass 30, count 0 2006.210.07:43:51.15#ibcon#wrote, iclass 30, count 0 2006.210.07:43:51.15#ibcon#about to read 3, iclass 30, count 0 2006.210.07:43:51.19#ibcon#read 3, iclass 30, count 0 2006.210.07:43:51.19#ibcon#about to read 4, iclass 30, count 0 2006.210.07:43:51.19#ibcon#read 4, iclass 30, count 0 2006.210.07:43:51.19#ibcon#about to read 5, iclass 30, count 0 2006.210.07:43:51.19#ibcon#read 5, iclass 30, count 0 2006.210.07:43:51.19#ibcon#about to read 6, iclass 30, count 0 2006.210.07:43:51.19#ibcon#read 6, iclass 30, count 0 2006.210.07:43:51.19#ibcon#end of sib2, iclass 30, count 0 2006.210.07:43:51.19#ibcon#*after write, iclass 30, count 0 2006.210.07:43:51.19#ibcon#*before return 0, iclass 30, count 0 2006.210.07:43:51.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:51.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:43:51.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:43:51.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:43:51.19$vc4f8/vb=4,3 2006.210.07:43:51.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.07:43:51.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.07:43:51.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:51.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:51.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:51.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:51.25#ibcon#enter wrdev, iclass 32, count 2 2006.210.07:43:51.25#ibcon#first serial, iclass 32, count 2 2006.210.07:43:51.25#ibcon#enter sib2, iclass 32, count 2 2006.210.07:43:51.25#ibcon#flushed, iclass 32, count 2 2006.210.07:43:51.25#ibcon#about to write, iclass 32, count 2 2006.210.07:43:51.25#ibcon#wrote, iclass 32, count 2 2006.210.07:43:51.25#ibcon#about to read 3, iclass 32, count 2 2006.210.07:43:51.27#ibcon#read 3, iclass 32, count 2 2006.210.07:43:51.27#ibcon#about to read 4, iclass 32, count 2 2006.210.07:43:51.27#ibcon#read 4, iclass 32, count 2 2006.210.07:43:51.27#ibcon#about to read 5, iclass 32, count 2 2006.210.07:43:51.27#ibcon#read 5, iclass 32, count 2 2006.210.07:43:51.27#ibcon#about to read 6, iclass 32, count 2 2006.210.07:43:51.27#ibcon#read 6, iclass 32, count 2 2006.210.07:43:51.27#ibcon#end of sib2, iclass 32, count 2 2006.210.07:43:51.27#ibcon#*mode == 0, iclass 32, count 2 2006.210.07:43:51.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.07:43:51.27#ibcon#[27=AT04-03\r\n] 2006.210.07:43:51.27#ibcon#*before write, iclass 32, count 2 2006.210.07:43:51.27#ibcon#enter sib2, iclass 32, count 2 2006.210.07:43:51.27#ibcon#flushed, iclass 32, count 2 2006.210.07:43:51.27#ibcon#about to write, iclass 32, count 2 2006.210.07:43:51.27#ibcon#wrote, iclass 32, count 2 2006.210.07:43:51.27#ibcon#about to read 3, iclass 32, count 2 2006.210.07:43:51.30#ibcon#read 3, iclass 32, count 2 2006.210.07:43:51.30#ibcon#about to read 4, iclass 32, count 2 2006.210.07:43:51.30#ibcon#read 4, iclass 32, count 2 2006.210.07:43:51.30#ibcon#about to read 5, iclass 32, count 2 2006.210.07:43:51.30#ibcon#read 5, iclass 32, count 2 2006.210.07:43:51.30#ibcon#about to read 6, iclass 32, count 2 2006.210.07:43:51.30#ibcon#read 6, iclass 32, count 2 2006.210.07:43:51.30#ibcon#end of sib2, iclass 32, count 2 2006.210.07:43:51.30#ibcon#*after write, iclass 32, count 2 2006.210.07:43:51.30#ibcon#*before return 0, iclass 32, count 2 2006.210.07:43:51.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:51.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:43:51.30#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.07:43:51.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:51.30#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:51.42#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:51.42#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:51.42#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:43:51.42#ibcon#first serial, iclass 32, count 0 2006.210.07:43:51.42#ibcon#enter sib2, iclass 32, count 0 2006.210.07:43:51.42#ibcon#flushed, iclass 32, count 0 2006.210.07:43:51.42#ibcon#about to write, iclass 32, count 0 2006.210.07:43:51.42#ibcon#wrote, iclass 32, count 0 2006.210.07:43:51.42#ibcon#about to read 3, iclass 32, count 0 2006.210.07:43:51.44#ibcon#read 3, iclass 32, count 0 2006.210.07:43:51.44#ibcon#about to read 4, iclass 32, count 0 2006.210.07:43:51.44#ibcon#read 4, iclass 32, count 0 2006.210.07:43:51.44#ibcon#about to read 5, iclass 32, count 0 2006.210.07:43:51.44#ibcon#read 5, iclass 32, count 0 2006.210.07:43:51.44#ibcon#about to read 6, iclass 32, count 0 2006.210.07:43:51.44#ibcon#read 6, iclass 32, count 0 2006.210.07:43:51.44#ibcon#end of sib2, iclass 32, count 0 2006.210.07:43:51.44#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:43:51.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:43:51.44#ibcon#[27=USB\r\n] 2006.210.07:43:51.44#ibcon#*before write, iclass 32, count 0 2006.210.07:43:51.44#ibcon#enter sib2, iclass 32, count 0 2006.210.07:43:51.44#ibcon#flushed, iclass 32, count 0 2006.210.07:43:51.44#ibcon#about to write, iclass 32, count 0 2006.210.07:43:51.44#ibcon#wrote, iclass 32, count 0 2006.210.07:43:51.44#ibcon#about to read 3, iclass 32, count 0 2006.210.07:43:51.47#ibcon#read 3, iclass 32, count 0 2006.210.07:43:51.47#ibcon#about to read 4, iclass 32, count 0 2006.210.07:43:51.47#ibcon#read 4, iclass 32, count 0 2006.210.07:43:51.47#ibcon#about to read 5, iclass 32, count 0 2006.210.07:43:51.47#ibcon#read 5, iclass 32, count 0 2006.210.07:43:51.47#ibcon#about to read 6, iclass 32, count 0 2006.210.07:43:51.47#ibcon#read 6, iclass 32, count 0 2006.210.07:43:51.47#ibcon#end of sib2, iclass 32, count 0 2006.210.07:43:51.47#ibcon#*after write, iclass 32, count 0 2006.210.07:43:51.47#ibcon#*before return 0, iclass 32, count 0 2006.210.07:43:51.47#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:51.47#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:43:51.47#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:43:51.47#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:43:51.47$vc4f8/vblo=5,744.99 2006.210.07:43:51.47#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.07:43:51.47#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.07:43:51.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:51.47#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:51.47#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:51.47#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:51.47#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:43:51.47#ibcon#first serial, iclass 34, count 0 2006.210.07:43:51.47#ibcon#enter sib2, iclass 34, count 0 2006.210.07:43:51.47#ibcon#flushed, iclass 34, count 0 2006.210.07:43:51.47#ibcon#about to write, iclass 34, count 0 2006.210.07:43:51.47#ibcon#wrote, iclass 34, count 0 2006.210.07:43:51.47#ibcon#about to read 3, iclass 34, count 0 2006.210.07:43:51.49#ibcon#read 3, iclass 34, count 0 2006.210.07:43:51.49#ibcon#about to read 4, iclass 34, count 0 2006.210.07:43:51.49#ibcon#read 4, iclass 34, count 0 2006.210.07:43:51.49#ibcon#about to read 5, iclass 34, count 0 2006.210.07:43:51.49#ibcon#read 5, iclass 34, count 0 2006.210.07:43:51.49#ibcon#about to read 6, iclass 34, count 0 2006.210.07:43:51.49#ibcon#read 6, iclass 34, count 0 2006.210.07:43:51.49#ibcon#end of sib2, iclass 34, count 0 2006.210.07:43:51.49#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:43:51.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:43:51.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:43:51.49#ibcon#*before write, iclass 34, count 0 2006.210.07:43:51.49#ibcon#enter sib2, iclass 34, count 0 2006.210.07:43:51.49#ibcon#flushed, iclass 34, count 0 2006.210.07:43:51.49#ibcon#about to write, iclass 34, count 0 2006.210.07:43:51.49#ibcon#wrote, iclass 34, count 0 2006.210.07:43:51.49#ibcon#about to read 3, iclass 34, count 0 2006.210.07:43:51.53#ibcon#read 3, iclass 34, count 0 2006.210.07:43:51.53#ibcon#about to read 4, iclass 34, count 0 2006.210.07:43:51.53#ibcon#read 4, iclass 34, count 0 2006.210.07:43:51.53#ibcon#about to read 5, iclass 34, count 0 2006.210.07:43:51.53#ibcon#read 5, iclass 34, count 0 2006.210.07:43:51.53#ibcon#about to read 6, iclass 34, count 0 2006.210.07:43:51.53#ibcon#read 6, iclass 34, count 0 2006.210.07:43:51.53#ibcon#end of sib2, iclass 34, count 0 2006.210.07:43:51.53#ibcon#*after write, iclass 34, count 0 2006.210.07:43:51.53#ibcon#*before return 0, iclass 34, count 0 2006.210.07:43:51.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:51.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:43:51.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:43:51.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:43:51.53$vc4f8/vb=5,3 2006.210.07:43:51.53#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.07:43:51.53#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.07:43:51.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:51.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:43:51.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:43:51.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:43:51.59#ibcon#enter wrdev, iclass 36, count 2 2006.210.07:43:51.59#ibcon#first serial, iclass 36, count 2 2006.210.07:43:51.59#ibcon#enter sib2, iclass 36, count 2 2006.210.07:43:51.59#ibcon#flushed, iclass 36, count 2 2006.210.07:43:51.59#ibcon#about to write, iclass 36, count 2 2006.210.07:43:51.59#ibcon#wrote, iclass 36, count 2 2006.210.07:43:51.59#ibcon#about to read 3, iclass 36, count 2 2006.210.07:43:51.61#ibcon#read 3, iclass 36, count 2 2006.210.07:43:51.61#ibcon#about to read 4, iclass 36, count 2 2006.210.07:43:51.61#ibcon#read 4, iclass 36, count 2 2006.210.07:43:51.61#ibcon#about to read 5, iclass 36, count 2 2006.210.07:43:51.61#ibcon#read 5, iclass 36, count 2 2006.210.07:43:51.61#ibcon#about to read 6, iclass 36, count 2 2006.210.07:43:51.61#ibcon#read 6, iclass 36, count 2 2006.210.07:43:51.61#ibcon#end of sib2, iclass 36, count 2 2006.210.07:43:51.61#ibcon#*mode == 0, iclass 36, count 2 2006.210.07:43:51.61#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.07:43:51.61#ibcon#[27=AT05-03\r\n] 2006.210.07:43:51.61#ibcon#*before write, iclass 36, count 2 2006.210.07:43:51.61#ibcon#enter sib2, iclass 36, count 2 2006.210.07:43:51.61#ibcon#flushed, iclass 36, count 2 2006.210.07:43:51.61#ibcon#about to write, iclass 36, count 2 2006.210.07:43:51.61#ibcon#wrote, iclass 36, count 2 2006.210.07:43:51.61#ibcon#about to read 3, iclass 36, count 2 2006.210.07:43:51.64#ibcon#read 3, iclass 36, count 2 2006.210.07:43:51.64#ibcon#about to read 4, iclass 36, count 2 2006.210.07:43:51.64#ibcon#read 4, iclass 36, count 2 2006.210.07:43:51.64#ibcon#about to read 5, iclass 36, count 2 2006.210.07:43:51.64#ibcon#read 5, iclass 36, count 2 2006.210.07:43:51.64#ibcon#about to read 6, iclass 36, count 2 2006.210.07:43:51.64#ibcon#read 6, iclass 36, count 2 2006.210.07:43:51.64#ibcon#end of sib2, iclass 36, count 2 2006.210.07:43:51.64#ibcon#*after write, iclass 36, count 2 2006.210.07:43:51.64#ibcon#*before return 0, iclass 36, count 2 2006.210.07:43:51.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:43:51.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:43:51.64#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.07:43:51.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:51.64#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:43:51.76#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:43:51.76#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:43:51.76#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:43:51.76#ibcon#first serial, iclass 36, count 0 2006.210.07:43:51.76#ibcon#enter sib2, iclass 36, count 0 2006.210.07:43:51.76#ibcon#flushed, iclass 36, count 0 2006.210.07:43:51.76#ibcon#about to write, iclass 36, count 0 2006.210.07:43:51.76#ibcon#wrote, iclass 36, count 0 2006.210.07:43:51.76#ibcon#about to read 3, iclass 36, count 0 2006.210.07:43:51.78#ibcon#read 3, iclass 36, count 0 2006.210.07:43:51.78#ibcon#about to read 4, iclass 36, count 0 2006.210.07:43:51.78#ibcon#read 4, iclass 36, count 0 2006.210.07:43:51.78#ibcon#about to read 5, iclass 36, count 0 2006.210.07:43:51.78#ibcon#read 5, iclass 36, count 0 2006.210.07:43:51.78#ibcon#about to read 6, iclass 36, count 0 2006.210.07:43:51.78#ibcon#read 6, iclass 36, count 0 2006.210.07:43:51.78#ibcon#end of sib2, iclass 36, count 0 2006.210.07:43:51.78#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:43:51.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:43:51.78#ibcon#[27=USB\r\n] 2006.210.07:43:51.78#ibcon#*before write, iclass 36, count 0 2006.210.07:43:51.78#ibcon#enter sib2, iclass 36, count 0 2006.210.07:43:51.78#ibcon#flushed, iclass 36, count 0 2006.210.07:43:51.78#ibcon#about to write, iclass 36, count 0 2006.210.07:43:51.78#ibcon#wrote, iclass 36, count 0 2006.210.07:43:51.78#ibcon#about to read 3, iclass 36, count 0 2006.210.07:43:51.81#ibcon#read 3, iclass 36, count 0 2006.210.07:43:51.81#ibcon#about to read 4, iclass 36, count 0 2006.210.07:43:51.81#ibcon#read 4, iclass 36, count 0 2006.210.07:43:51.81#ibcon#about to read 5, iclass 36, count 0 2006.210.07:43:51.81#ibcon#read 5, iclass 36, count 0 2006.210.07:43:51.81#ibcon#about to read 6, iclass 36, count 0 2006.210.07:43:51.81#ibcon#read 6, iclass 36, count 0 2006.210.07:43:51.81#ibcon#end of sib2, iclass 36, count 0 2006.210.07:43:51.81#ibcon#*after write, iclass 36, count 0 2006.210.07:43:51.81#ibcon#*before return 0, iclass 36, count 0 2006.210.07:43:51.81#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:43:51.81#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:43:51.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:43:51.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:43:51.81$vc4f8/vblo=6,752.99 2006.210.07:43:51.81#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.07:43:51.81#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.07:43:51.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:43:51.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:43:51.81#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:43:51.81#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:43:51.81#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:43:51.81#ibcon#first serial, iclass 38, count 0 2006.210.07:43:51.81#ibcon#enter sib2, iclass 38, count 0 2006.210.07:43:51.81#ibcon#flushed, iclass 38, count 0 2006.210.07:43:51.81#ibcon#about to write, iclass 38, count 0 2006.210.07:43:51.81#ibcon#wrote, iclass 38, count 0 2006.210.07:43:51.81#ibcon#about to read 3, iclass 38, count 0 2006.210.07:43:51.83#ibcon#read 3, iclass 38, count 0 2006.210.07:43:51.83#ibcon#about to read 4, iclass 38, count 0 2006.210.07:43:51.83#ibcon#read 4, iclass 38, count 0 2006.210.07:43:51.83#ibcon#about to read 5, iclass 38, count 0 2006.210.07:43:51.83#ibcon#read 5, iclass 38, count 0 2006.210.07:43:51.83#ibcon#about to read 6, iclass 38, count 0 2006.210.07:43:51.83#ibcon#read 6, iclass 38, count 0 2006.210.07:43:51.83#ibcon#end of sib2, iclass 38, count 0 2006.210.07:43:51.83#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:43:51.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:43:51.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:43:51.83#ibcon#*before write, iclass 38, count 0 2006.210.07:43:51.83#ibcon#enter sib2, iclass 38, count 0 2006.210.07:43:51.83#ibcon#flushed, iclass 38, count 0 2006.210.07:43:51.83#ibcon#about to write, iclass 38, count 0 2006.210.07:43:51.83#ibcon#wrote, iclass 38, count 0 2006.210.07:43:51.83#ibcon#about to read 3, iclass 38, count 0 2006.210.07:43:51.87#ibcon#read 3, iclass 38, count 0 2006.210.07:43:51.87#ibcon#about to read 4, iclass 38, count 0 2006.210.07:43:51.87#ibcon#read 4, iclass 38, count 0 2006.210.07:43:51.87#ibcon#about to read 5, iclass 38, count 0 2006.210.07:43:51.87#ibcon#read 5, iclass 38, count 0 2006.210.07:43:51.87#ibcon#about to read 6, iclass 38, count 0 2006.210.07:43:51.87#ibcon#read 6, iclass 38, count 0 2006.210.07:43:51.87#ibcon#end of sib2, iclass 38, count 0 2006.210.07:43:51.87#ibcon#*after write, iclass 38, count 0 2006.210.07:43:51.87#ibcon#*before return 0, iclass 38, count 0 2006.210.07:43:51.87#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:43:51.87#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:43:51.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:43:51.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:43:51.87$vc4f8/vb=6,3 2006.210.07:43:51.87#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.07:43:51.87#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.07:43:51.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:43:51.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:43:51.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:43:51.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:43:51.93#ibcon#enter wrdev, iclass 40, count 2 2006.210.07:43:51.93#ibcon#first serial, iclass 40, count 2 2006.210.07:43:51.93#ibcon#enter sib2, iclass 40, count 2 2006.210.07:43:51.93#ibcon#flushed, iclass 40, count 2 2006.210.07:43:51.93#ibcon#about to write, iclass 40, count 2 2006.210.07:43:51.93#ibcon#wrote, iclass 40, count 2 2006.210.07:43:51.93#ibcon#about to read 3, iclass 40, count 2 2006.210.07:43:51.95#ibcon#read 3, iclass 40, count 2 2006.210.07:43:51.95#ibcon#about to read 4, iclass 40, count 2 2006.210.07:43:51.95#ibcon#read 4, iclass 40, count 2 2006.210.07:43:51.95#ibcon#about to read 5, iclass 40, count 2 2006.210.07:43:51.95#ibcon#read 5, iclass 40, count 2 2006.210.07:43:51.95#ibcon#about to read 6, iclass 40, count 2 2006.210.07:43:51.95#ibcon#read 6, iclass 40, count 2 2006.210.07:43:51.95#ibcon#end of sib2, iclass 40, count 2 2006.210.07:43:51.95#ibcon#*mode == 0, iclass 40, count 2 2006.210.07:43:51.95#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.07:43:51.95#ibcon#[27=AT06-03\r\n] 2006.210.07:43:51.95#ibcon#*before write, iclass 40, count 2 2006.210.07:43:51.95#ibcon#enter sib2, iclass 40, count 2 2006.210.07:43:51.95#ibcon#flushed, iclass 40, count 2 2006.210.07:43:51.95#ibcon#about to write, iclass 40, count 2 2006.210.07:43:51.95#ibcon#wrote, iclass 40, count 2 2006.210.07:43:51.95#ibcon#about to read 3, iclass 40, count 2 2006.210.07:43:51.98#ibcon#read 3, iclass 40, count 2 2006.210.07:43:51.98#ibcon#about to read 4, iclass 40, count 2 2006.210.07:43:51.98#ibcon#read 4, iclass 40, count 2 2006.210.07:43:51.98#ibcon#about to read 5, iclass 40, count 2 2006.210.07:43:51.98#ibcon#read 5, iclass 40, count 2 2006.210.07:43:51.98#ibcon#about to read 6, iclass 40, count 2 2006.210.07:43:51.98#ibcon#read 6, iclass 40, count 2 2006.210.07:43:51.98#ibcon#end of sib2, iclass 40, count 2 2006.210.07:43:51.98#ibcon#*after write, iclass 40, count 2 2006.210.07:43:51.98#ibcon#*before return 0, iclass 40, count 2 2006.210.07:43:51.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:43:51.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:43:51.98#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.07:43:51.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:43:51.98#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:43:52.10#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:43:52.10#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:43:52.10#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:43:52.10#ibcon#first serial, iclass 40, count 0 2006.210.07:43:52.10#ibcon#enter sib2, iclass 40, count 0 2006.210.07:43:52.10#ibcon#flushed, iclass 40, count 0 2006.210.07:43:52.10#ibcon#about to write, iclass 40, count 0 2006.210.07:43:52.10#ibcon#wrote, iclass 40, count 0 2006.210.07:43:52.10#ibcon#about to read 3, iclass 40, count 0 2006.210.07:43:52.12#ibcon#read 3, iclass 40, count 0 2006.210.07:43:52.12#ibcon#about to read 4, iclass 40, count 0 2006.210.07:43:52.12#ibcon#read 4, iclass 40, count 0 2006.210.07:43:52.12#ibcon#about to read 5, iclass 40, count 0 2006.210.07:43:52.12#ibcon#read 5, iclass 40, count 0 2006.210.07:43:52.12#ibcon#about to read 6, iclass 40, count 0 2006.210.07:43:52.12#ibcon#read 6, iclass 40, count 0 2006.210.07:43:52.12#ibcon#end of sib2, iclass 40, count 0 2006.210.07:43:52.12#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:43:52.12#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:43:52.12#ibcon#[27=USB\r\n] 2006.210.07:43:52.12#ibcon#*before write, iclass 40, count 0 2006.210.07:43:52.12#ibcon#enter sib2, iclass 40, count 0 2006.210.07:43:52.12#ibcon#flushed, iclass 40, count 0 2006.210.07:43:52.12#ibcon#about to write, iclass 40, count 0 2006.210.07:43:52.12#ibcon#wrote, iclass 40, count 0 2006.210.07:43:52.12#ibcon#about to read 3, iclass 40, count 0 2006.210.07:43:52.15#ibcon#read 3, iclass 40, count 0 2006.210.07:43:52.15#ibcon#about to read 4, iclass 40, count 0 2006.210.07:43:52.15#ibcon#read 4, iclass 40, count 0 2006.210.07:43:52.15#ibcon#about to read 5, iclass 40, count 0 2006.210.07:43:52.15#ibcon#read 5, iclass 40, count 0 2006.210.07:43:52.15#ibcon#about to read 6, iclass 40, count 0 2006.210.07:43:52.15#ibcon#read 6, iclass 40, count 0 2006.210.07:43:52.15#ibcon#end of sib2, iclass 40, count 0 2006.210.07:43:52.15#ibcon#*after write, iclass 40, count 0 2006.210.07:43:52.15#ibcon#*before return 0, iclass 40, count 0 2006.210.07:43:52.15#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:43:52.15#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:43:52.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:43:52.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:43:52.15$vc4f8/vabw=wide 2006.210.07:43:52.15#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.07:43:52.15#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.07:43:52.15#ibcon#ireg 8 cls_cnt 0 2006.210.07:43:52.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:52.15#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:52.15#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:52.15#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:43:52.15#ibcon#first serial, iclass 4, count 0 2006.210.07:43:52.15#ibcon#enter sib2, iclass 4, count 0 2006.210.07:43:52.15#ibcon#flushed, iclass 4, count 0 2006.210.07:43:52.15#ibcon#about to write, iclass 4, count 0 2006.210.07:43:52.15#ibcon#wrote, iclass 4, count 0 2006.210.07:43:52.15#ibcon#about to read 3, iclass 4, count 0 2006.210.07:43:52.17#ibcon#read 3, iclass 4, count 0 2006.210.07:43:52.17#ibcon#about to read 4, iclass 4, count 0 2006.210.07:43:52.17#ibcon#read 4, iclass 4, count 0 2006.210.07:43:52.17#ibcon#about to read 5, iclass 4, count 0 2006.210.07:43:52.17#ibcon#read 5, iclass 4, count 0 2006.210.07:43:52.17#ibcon#about to read 6, iclass 4, count 0 2006.210.07:43:52.17#ibcon#read 6, iclass 4, count 0 2006.210.07:43:52.17#ibcon#end of sib2, iclass 4, count 0 2006.210.07:43:52.17#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:43:52.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:43:52.17#ibcon#[25=BW32\r\n] 2006.210.07:43:52.17#ibcon#*before write, iclass 4, count 0 2006.210.07:43:52.17#ibcon#enter sib2, iclass 4, count 0 2006.210.07:43:52.17#ibcon#flushed, iclass 4, count 0 2006.210.07:43:52.17#ibcon#about to write, iclass 4, count 0 2006.210.07:43:52.17#ibcon#wrote, iclass 4, count 0 2006.210.07:43:52.17#ibcon#about to read 3, iclass 4, count 0 2006.210.07:43:52.20#ibcon#read 3, iclass 4, count 0 2006.210.07:43:52.20#ibcon#about to read 4, iclass 4, count 0 2006.210.07:43:52.20#ibcon#read 4, iclass 4, count 0 2006.210.07:43:52.20#ibcon#about to read 5, iclass 4, count 0 2006.210.07:43:52.20#ibcon#read 5, iclass 4, count 0 2006.210.07:43:52.20#ibcon#about to read 6, iclass 4, count 0 2006.210.07:43:52.20#ibcon#read 6, iclass 4, count 0 2006.210.07:43:52.20#ibcon#end of sib2, iclass 4, count 0 2006.210.07:43:52.20#ibcon#*after write, iclass 4, count 0 2006.210.07:43:52.20#ibcon#*before return 0, iclass 4, count 0 2006.210.07:43:52.20#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:52.20#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:43:52.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:43:52.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:43:52.20$vc4f8/vbbw=wide 2006.210.07:43:52.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:43:52.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:43:52.20#ibcon#ireg 8 cls_cnt 0 2006.210.07:43:52.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:43:52.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:43:52.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:43:52.27#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:43:52.27#ibcon#first serial, iclass 6, count 0 2006.210.07:43:52.27#ibcon#enter sib2, iclass 6, count 0 2006.210.07:43:52.27#ibcon#flushed, iclass 6, count 0 2006.210.07:43:52.27#ibcon#about to write, iclass 6, count 0 2006.210.07:43:52.27#ibcon#wrote, iclass 6, count 0 2006.210.07:43:52.27#ibcon#about to read 3, iclass 6, count 0 2006.210.07:43:52.29#ibcon#read 3, iclass 6, count 0 2006.210.07:43:52.29#ibcon#about to read 4, iclass 6, count 0 2006.210.07:43:52.29#ibcon#read 4, iclass 6, count 0 2006.210.07:43:52.29#ibcon#about to read 5, iclass 6, count 0 2006.210.07:43:52.29#ibcon#read 5, iclass 6, count 0 2006.210.07:43:52.29#ibcon#about to read 6, iclass 6, count 0 2006.210.07:43:52.29#ibcon#read 6, iclass 6, count 0 2006.210.07:43:52.29#ibcon#end of sib2, iclass 6, count 0 2006.210.07:43:52.29#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:43:52.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:43:52.29#ibcon#[27=BW32\r\n] 2006.210.07:43:52.29#ibcon#*before write, iclass 6, count 0 2006.210.07:43:52.29#ibcon#enter sib2, iclass 6, count 0 2006.210.07:43:52.29#ibcon#flushed, iclass 6, count 0 2006.210.07:43:52.29#ibcon#about to write, iclass 6, count 0 2006.210.07:43:52.29#ibcon#wrote, iclass 6, count 0 2006.210.07:43:52.29#ibcon#about to read 3, iclass 6, count 0 2006.210.07:43:52.32#ibcon#read 3, iclass 6, count 0 2006.210.07:43:52.32#ibcon#about to read 4, iclass 6, count 0 2006.210.07:43:52.32#ibcon#read 4, iclass 6, count 0 2006.210.07:43:52.32#ibcon#about to read 5, iclass 6, count 0 2006.210.07:43:52.32#ibcon#read 5, iclass 6, count 0 2006.210.07:43:52.32#ibcon#about to read 6, iclass 6, count 0 2006.210.07:43:52.32#ibcon#read 6, iclass 6, count 0 2006.210.07:43:52.32#ibcon#end of sib2, iclass 6, count 0 2006.210.07:43:52.32#ibcon#*after write, iclass 6, count 0 2006.210.07:43:52.32#ibcon#*before return 0, iclass 6, count 0 2006.210.07:43:52.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:43:52.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:43:52.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:43:52.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:43:52.32$4f8m12a/ifd4f 2006.210.07:43:52.32$ifd4f/lo= 2006.210.07:43:52.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:43:52.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:43:52.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:43:52.32$ifd4f/patch= 2006.210.07:43:52.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:43:52.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:43:52.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:43:52.32$4f8m12a/"form=m,16.000,1:2 2006.210.07:43:52.32$4f8m12a/"tpicd 2006.210.07:43:52.32$4f8m12a/echo=off 2006.210.07:43:52.32$4f8m12a/xlog=off 2006.210.07:43:52.32:!2006.210.07:44:20 2006.210.07:43:59.14#trakl#Source acquired 2006.210.07:43:59.14#flagr#flagr/antenna,acquired 2006.210.07:44:20.00:preob 2006.210.07:44:21.14/onsource/TRACKING 2006.210.07:44:21.14:!2006.210.07:44:30 2006.210.07:44:30.00:data_valid=on 2006.210.07:44:30.00:midob 2006.210.07:44:30.14/onsource/TRACKING 2006.210.07:44:30.14/wx/30.55,1006.2,76 2006.210.07:44:30.35/cable/+6.3943E-03 2006.210.07:44:31.44/va/01,08,usb,yes,29,30 2006.210.07:44:31.44/va/02,07,usb,yes,29,30 2006.210.07:44:31.44/va/03,06,usb,yes,30,31 2006.210.07:44:31.44/va/04,07,usb,yes,30,32 2006.210.07:44:31.44/va/05,07,usb,yes,31,32 2006.210.07:44:31.44/va/06,06,usb,yes,30,30 2006.210.07:44:31.44/va/07,06,usb,yes,30,30 2006.210.07:44:31.44/va/08,07,usb,yes,29,28 2006.210.07:44:31.67/valo/01,532.99,yes,locked 2006.210.07:44:31.67/valo/02,572.99,yes,locked 2006.210.07:44:31.67/valo/03,672.99,yes,locked 2006.210.07:44:31.67/valo/04,832.99,yes,locked 2006.210.07:44:31.67/valo/05,652.99,yes,locked 2006.210.07:44:31.67/valo/06,772.99,yes,locked 2006.210.07:44:31.67/valo/07,832.99,yes,locked 2006.210.07:44:31.67/valo/08,852.99,yes,locked 2006.210.07:44:32.76/vb/01,04,usb,yes,29,27 2006.210.07:44:32.76/vb/02,04,usb,yes,30,32 2006.210.07:44:32.76/vb/03,03,usb,yes,33,38 2006.210.07:44:32.76/vb/04,03,usb,yes,34,34 2006.210.07:44:32.76/vb/05,03,usb,yes,33,37 2006.210.07:44:32.76/vb/06,03,usb,yes,33,37 2006.210.07:44:32.76/vb/07,04,usb,yes,29,29 2006.210.07:44:32.76/vb/08,03,usb,yes,33,37 2006.210.07:44:33.00/vblo/01,632.99,yes,locked 2006.210.07:44:33.00/vblo/02,640.99,yes,locked 2006.210.07:44:33.00/vblo/03,656.99,yes,locked 2006.210.07:44:33.00/vblo/04,712.99,yes,locked 2006.210.07:44:33.00/vblo/05,744.99,yes,locked 2006.210.07:44:33.00/vblo/06,752.99,yes,locked 2006.210.07:44:33.00/vblo/07,734.99,yes,locked 2006.210.07:44:33.00/vblo/08,744.99,yes,locked 2006.210.07:44:33.15/vabw/8 2006.210.07:44:33.30/vbbw/8 2006.210.07:44:33.39/xfe/off,on,13.0 2006.210.07:44:33.77/ifatt/23,28,28,28 2006.210.07:44:34.07/fmout-gps/S +4.50E-07 2006.210.07:44:34.11:!2006.210.07:45:30 2006.210.07:45:30.00:data_valid=off 2006.210.07:45:30.00:postob 2006.210.07:45:30.13/cable/+6.3940E-03 2006.210.07:45:30.13/wx/30.55,1006.2,75 2006.210.07:45:31.08/fmout-gps/S +4.51E-07 2006.210.07:45:31.08:scan_name=210-0746,k06210,100 2006.210.07:45:31.08:source=1004+141,100741.50,135629.6,2000.0,ccw 2006.210.07:45:31.14#flagr#flagr/antenna,new-source 2006.210.07:45:32.14:checkk5 2006.210.07:45:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:45:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:45:33.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:45:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:45:33.84/chk_obsdata//k5ts1/T2100744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:45:34.18/chk_obsdata//k5ts2/T2100744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:45:34.51/chk_obsdata//k5ts3/T2100744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:45:34.86/chk_obsdata//k5ts4/T2100744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:45:35.53/k5log//k5ts1_log_newline 2006.210.07:45:36.19/k5log//k5ts2_log_newline 2006.210.07:45:36.85/k5log//k5ts3_log_newline 2006.210.07:45:37.52/k5log//k5ts4_log_newline 2006.210.07:45:37.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:45:37.54:4f8m12a=1 2006.210.07:45:37.54$4f8m12a/echo=on 2006.210.07:45:37.54$4f8m12a/pcalon 2006.210.07:45:37.54$pcalon/"no phase cal control is implemented here 2006.210.07:45:37.54$4f8m12a/"tpicd=stop 2006.210.07:45:37.54$4f8m12a/vc4f8 2006.210.07:45:37.54$vc4f8/valo=1,532.99 2006.210.07:45:37.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.07:45:37.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.07:45:37.55#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:37.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:37.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:37.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:37.55#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:45:37.55#ibcon#first serial, iclass 15, count 0 2006.210.07:45:37.55#ibcon#enter sib2, iclass 15, count 0 2006.210.07:45:37.55#ibcon#flushed, iclass 15, count 0 2006.210.07:45:37.55#ibcon#about to write, iclass 15, count 0 2006.210.07:45:37.55#ibcon#wrote, iclass 15, count 0 2006.210.07:45:37.55#ibcon#about to read 3, iclass 15, count 0 2006.210.07:45:37.56#ibcon#read 3, iclass 15, count 0 2006.210.07:45:37.56#ibcon#about to read 4, iclass 15, count 0 2006.210.07:45:37.56#ibcon#read 4, iclass 15, count 0 2006.210.07:45:37.56#ibcon#about to read 5, iclass 15, count 0 2006.210.07:45:37.56#ibcon#read 5, iclass 15, count 0 2006.210.07:45:37.56#ibcon#about to read 6, iclass 15, count 0 2006.210.07:45:37.56#ibcon#read 6, iclass 15, count 0 2006.210.07:45:37.56#ibcon#end of sib2, iclass 15, count 0 2006.210.07:45:37.56#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:45:37.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:45:37.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:45:37.56#ibcon#*before write, iclass 15, count 0 2006.210.07:45:37.56#ibcon#enter sib2, iclass 15, count 0 2006.210.07:45:37.56#ibcon#flushed, iclass 15, count 0 2006.210.07:45:37.56#ibcon#about to write, iclass 15, count 0 2006.210.07:45:37.56#ibcon#wrote, iclass 15, count 0 2006.210.07:45:37.56#ibcon#about to read 3, iclass 15, count 0 2006.210.07:45:37.61#ibcon#read 3, iclass 15, count 0 2006.210.07:45:37.61#ibcon#about to read 4, iclass 15, count 0 2006.210.07:45:37.61#ibcon#read 4, iclass 15, count 0 2006.210.07:45:37.61#ibcon#about to read 5, iclass 15, count 0 2006.210.07:45:37.61#ibcon#read 5, iclass 15, count 0 2006.210.07:45:37.61#ibcon#about to read 6, iclass 15, count 0 2006.210.07:45:37.61#ibcon#read 6, iclass 15, count 0 2006.210.07:45:37.61#ibcon#end of sib2, iclass 15, count 0 2006.210.07:45:37.61#ibcon#*after write, iclass 15, count 0 2006.210.07:45:37.61#ibcon#*before return 0, iclass 15, count 0 2006.210.07:45:37.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:37.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:37.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:45:37.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:45:37.61$vc4f8/va=1,8 2006.210.07:45:37.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.07:45:37.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.07:45:37.61#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:37.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:37.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:37.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:37.61#ibcon#enter wrdev, iclass 17, count 2 2006.210.07:45:37.61#ibcon#first serial, iclass 17, count 2 2006.210.07:45:37.61#ibcon#enter sib2, iclass 17, count 2 2006.210.07:45:37.61#ibcon#flushed, iclass 17, count 2 2006.210.07:45:37.61#ibcon#about to write, iclass 17, count 2 2006.210.07:45:37.61#ibcon#wrote, iclass 17, count 2 2006.210.07:45:37.61#ibcon#about to read 3, iclass 17, count 2 2006.210.07:45:37.63#ibcon#read 3, iclass 17, count 2 2006.210.07:45:37.63#ibcon#about to read 4, iclass 17, count 2 2006.210.07:45:37.63#ibcon#read 4, iclass 17, count 2 2006.210.07:45:37.63#ibcon#about to read 5, iclass 17, count 2 2006.210.07:45:37.63#ibcon#read 5, iclass 17, count 2 2006.210.07:45:37.63#ibcon#about to read 6, iclass 17, count 2 2006.210.07:45:37.63#ibcon#read 6, iclass 17, count 2 2006.210.07:45:37.63#ibcon#end of sib2, iclass 17, count 2 2006.210.07:45:37.63#ibcon#*mode == 0, iclass 17, count 2 2006.210.07:45:37.63#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.07:45:37.63#ibcon#[25=AT01-08\r\n] 2006.210.07:45:37.63#ibcon#*before write, iclass 17, count 2 2006.210.07:45:37.63#ibcon#enter sib2, iclass 17, count 2 2006.210.07:45:37.63#ibcon#flushed, iclass 17, count 2 2006.210.07:45:37.63#ibcon#about to write, iclass 17, count 2 2006.210.07:45:37.63#ibcon#wrote, iclass 17, count 2 2006.210.07:45:37.63#ibcon#about to read 3, iclass 17, count 2 2006.210.07:45:37.66#ibcon#read 3, iclass 17, count 2 2006.210.07:45:37.66#ibcon#about to read 4, iclass 17, count 2 2006.210.07:45:37.66#ibcon#read 4, iclass 17, count 2 2006.210.07:45:37.66#ibcon#about to read 5, iclass 17, count 2 2006.210.07:45:37.66#ibcon#read 5, iclass 17, count 2 2006.210.07:45:37.66#ibcon#about to read 6, iclass 17, count 2 2006.210.07:45:37.66#ibcon#read 6, iclass 17, count 2 2006.210.07:45:37.66#ibcon#end of sib2, iclass 17, count 2 2006.210.07:45:37.66#ibcon#*after write, iclass 17, count 2 2006.210.07:45:37.66#ibcon#*before return 0, iclass 17, count 2 2006.210.07:45:37.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:37.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:37.66#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.07:45:37.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:37.66#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:37.78#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:37.78#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:37.78#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:45:37.78#ibcon#first serial, iclass 17, count 0 2006.210.07:45:37.78#ibcon#enter sib2, iclass 17, count 0 2006.210.07:45:37.78#ibcon#flushed, iclass 17, count 0 2006.210.07:45:37.78#ibcon#about to write, iclass 17, count 0 2006.210.07:45:37.78#ibcon#wrote, iclass 17, count 0 2006.210.07:45:37.78#ibcon#about to read 3, iclass 17, count 0 2006.210.07:45:37.80#ibcon#read 3, iclass 17, count 0 2006.210.07:45:37.80#ibcon#about to read 4, iclass 17, count 0 2006.210.07:45:37.80#ibcon#read 4, iclass 17, count 0 2006.210.07:45:37.80#ibcon#about to read 5, iclass 17, count 0 2006.210.07:45:37.80#ibcon#read 5, iclass 17, count 0 2006.210.07:45:37.80#ibcon#about to read 6, iclass 17, count 0 2006.210.07:45:37.80#ibcon#read 6, iclass 17, count 0 2006.210.07:45:37.80#ibcon#end of sib2, iclass 17, count 0 2006.210.07:45:37.80#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:45:37.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:45:37.80#ibcon#[25=USB\r\n] 2006.210.07:45:37.80#ibcon#*before write, iclass 17, count 0 2006.210.07:45:37.80#ibcon#enter sib2, iclass 17, count 0 2006.210.07:45:37.80#ibcon#flushed, iclass 17, count 0 2006.210.07:45:37.80#ibcon#about to write, iclass 17, count 0 2006.210.07:45:37.80#ibcon#wrote, iclass 17, count 0 2006.210.07:45:37.80#ibcon#about to read 3, iclass 17, count 0 2006.210.07:45:37.83#ibcon#read 3, iclass 17, count 0 2006.210.07:45:37.83#ibcon#about to read 4, iclass 17, count 0 2006.210.07:45:37.83#ibcon#read 4, iclass 17, count 0 2006.210.07:45:37.83#ibcon#about to read 5, iclass 17, count 0 2006.210.07:45:37.83#ibcon#read 5, iclass 17, count 0 2006.210.07:45:37.83#ibcon#about to read 6, iclass 17, count 0 2006.210.07:45:37.83#ibcon#read 6, iclass 17, count 0 2006.210.07:45:37.83#ibcon#end of sib2, iclass 17, count 0 2006.210.07:45:37.83#ibcon#*after write, iclass 17, count 0 2006.210.07:45:37.83#ibcon#*before return 0, iclass 17, count 0 2006.210.07:45:37.83#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:37.83#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:37.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:45:37.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:45:37.83$vc4f8/valo=2,572.99 2006.210.07:45:37.83#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.07:45:37.83#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.07:45:37.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:37.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:45:37.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:45:37.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:45:37.83#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:45:37.83#ibcon#first serial, iclass 19, count 0 2006.210.07:45:37.83#ibcon#enter sib2, iclass 19, count 0 2006.210.07:45:37.83#ibcon#flushed, iclass 19, count 0 2006.210.07:45:37.83#ibcon#about to write, iclass 19, count 0 2006.210.07:45:37.83#ibcon#wrote, iclass 19, count 0 2006.210.07:45:37.83#ibcon#about to read 3, iclass 19, count 0 2006.210.07:45:37.85#ibcon#read 3, iclass 19, count 0 2006.210.07:45:37.85#ibcon#about to read 4, iclass 19, count 0 2006.210.07:45:37.85#ibcon#read 4, iclass 19, count 0 2006.210.07:45:37.85#ibcon#about to read 5, iclass 19, count 0 2006.210.07:45:37.85#ibcon#read 5, iclass 19, count 0 2006.210.07:45:37.85#ibcon#about to read 6, iclass 19, count 0 2006.210.07:45:37.85#ibcon#read 6, iclass 19, count 0 2006.210.07:45:37.85#ibcon#end of sib2, iclass 19, count 0 2006.210.07:45:37.85#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:45:37.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:45:37.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:45:37.85#ibcon#*before write, iclass 19, count 0 2006.210.07:45:37.85#ibcon#enter sib2, iclass 19, count 0 2006.210.07:45:37.85#ibcon#flushed, iclass 19, count 0 2006.210.07:45:37.85#ibcon#about to write, iclass 19, count 0 2006.210.07:45:37.85#ibcon#wrote, iclass 19, count 0 2006.210.07:45:37.85#ibcon#about to read 3, iclass 19, count 0 2006.210.07:45:37.89#ibcon#read 3, iclass 19, count 0 2006.210.07:45:37.89#ibcon#about to read 4, iclass 19, count 0 2006.210.07:45:37.89#ibcon#read 4, iclass 19, count 0 2006.210.07:45:37.89#ibcon#about to read 5, iclass 19, count 0 2006.210.07:45:37.89#ibcon#read 5, iclass 19, count 0 2006.210.07:45:37.89#ibcon#about to read 6, iclass 19, count 0 2006.210.07:45:37.89#ibcon#read 6, iclass 19, count 0 2006.210.07:45:37.89#ibcon#end of sib2, iclass 19, count 0 2006.210.07:45:37.89#ibcon#*after write, iclass 19, count 0 2006.210.07:45:37.89#ibcon#*before return 0, iclass 19, count 0 2006.210.07:45:37.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:45:37.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:45:37.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:45:37.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:45:37.89$vc4f8/va=2,7 2006.210.07:45:37.89#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.07:45:37.89#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.07:45:37.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:37.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:45:37.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:45:37.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:45:37.95#ibcon#enter wrdev, iclass 21, count 2 2006.210.07:45:37.95#ibcon#first serial, iclass 21, count 2 2006.210.07:45:37.95#ibcon#enter sib2, iclass 21, count 2 2006.210.07:45:37.95#ibcon#flushed, iclass 21, count 2 2006.210.07:45:37.95#ibcon#about to write, iclass 21, count 2 2006.210.07:45:37.95#ibcon#wrote, iclass 21, count 2 2006.210.07:45:37.95#ibcon#about to read 3, iclass 21, count 2 2006.210.07:45:37.97#ibcon#read 3, iclass 21, count 2 2006.210.07:45:37.97#ibcon#about to read 4, iclass 21, count 2 2006.210.07:45:37.97#ibcon#read 4, iclass 21, count 2 2006.210.07:45:37.97#ibcon#about to read 5, iclass 21, count 2 2006.210.07:45:37.97#ibcon#read 5, iclass 21, count 2 2006.210.07:45:37.97#ibcon#about to read 6, iclass 21, count 2 2006.210.07:45:37.97#ibcon#read 6, iclass 21, count 2 2006.210.07:45:37.97#ibcon#end of sib2, iclass 21, count 2 2006.210.07:45:37.97#ibcon#*mode == 0, iclass 21, count 2 2006.210.07:45:37.97#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.07:45:37.97#ibcon#[25=AT02-07\r\n] 2006.210.07:45:37.97#ibcon#*before write, iclass 21, count 2 2006.210.07:45:37.97#ibcon#enter sib2, iclass 21, count 2 2006.210.07:45:37.97#ibcon#flushed, iclass 21, count 2 2006.210.07:45:37.97#ibcon#about to write, iclass 21, count 2 2006.210.07:45:37.97#ibcon#wrote, iclass 21, count 2 2006.210.07:45:37.97#ibcon#about to read 3, iclass 21, count 2 2006.210.07:45:38.00#ibcon#read 3, iclass 21, count 2 2006.210.07:45:38.00#ibcon#about to read 4, iclass 21, count 2 2006.210.07:45:38.00#ibcon#read 4, iclass 21, count 2 2006.210.07:45:38.00#ibcon#about to read 5, iclass 21, count 2 2006.210.07:45:38.00#ibcon#read 5, iclass 21, count 2 2006.210.07:45:38.00#ibcon#about to read 6, iclass 21, count 2 2006.210.07:45:38.00#ibcon#read 6, iclass 21, count 2 2006.210.07:45:38.00#ibcon#end of sib2, iclass 21, count 2 2006.210.07:45:38.00#ibcon#*after write, iclass 21, count 2 2006.210.07:45:38.00#ibcon#*before return 0, iclass 21, count 2 2006.210.07:45:38.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:45:38.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:45:38.00#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.07:45:38.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:38.00#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:45:38.12#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:45:38.12#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:45:38.12#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:45:38.12#ibcon#first serial, iclass 21, count 0 2006.210.07:45:38.12#ibcon#enter sib2, iclass 21, count 0 2006.210.07:45:38.12#ibcon#flushed, iclass 21, count 0 2006.210.07:45:38.12#ibcon#about to write, iclass 21, count 0 2006.210.07:45:38.12#ibcon#wrote, iclass 21, count 0 2006.210.07:45:38.12#ibcon#about to read 3, iclass 21, count 0 2006.210.07:45:38.14#ibcon#read 3, iclass 21, count 0 2006.210.07:45:38.14#ibcon#about to read 4, iclass 21, count 0 2006.210.07:45:38.14#ibcon#read 4, iclass 21, count 0 2006.210.07:45:38.14#ibcon#about to read 5, iclass 21, count 0 2006.210.07:45:38.14#ibcon#read 5, iclass 21, count 0 2006.210.07:45:38.14#ibcon#about to read 6, iclass 21, count 0 2006.210.07:45:38.14#ibcon#read 6, iclass 21, count 0 2006.210.07:45:38.14#ibcon#end of sib2, iclass 21, count 0 2006.210.07:45:38.14#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:45:38.14#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:45:38.14#ibcon#[25=USB\r\n] 2006.210.07:45:38.14#ibcon#*before write, iclass 21, count 0 2006.210.07:45:38.14#ibcon#enter sib2, iclass 21, count 0 2006.210.07:45:38.14#ibcon#flushed, iclass 21, count 0 2006.210.07:45:38.14#ibcon#about to write, iclass 21, count 0 2006.210.07:45:38.14#ibcon#wrote, iclass 21, count 0 2006.210.07:45:38.14#ibcon#about to read 3, iclass 21, count 0 2006.210.07:45:38.17#ibcon#read 3, iclass 21, count 0 2006.210.07:45:38.17#ibcon#about to read 4, iclass 21, count 0 2006.210.07:45:38.17#ibcon#read 4, iclass 21, count 0 2006.210.07:45:38.17#ibcon#about to read 5, iclass 21, count 0 2006.210.07:45:38.17#ibcon#read 5, iclass 21, count 0 2006.210.07:45:38.17#ibcon#about to read 6, iclass 21, count 0 2006.210.07:45:38.17#ibcon#read 6, iclass 21, count 0 2006.210.07:45:38.17#ibcon#end of sib2, iclass 21, count 0 2006.210.07:45:38.17#ibcon#*after write, iclass 21, count 0 2006.210.07:45:38.17#ibcon#*before return 0, iclass 21, count 0 2006.210.07:45:38.17#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:45:38.17#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:45:38.17#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:45:38.17#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:45:38.17$vc4f8/valo=3,672.99 2006.210.07:45:38.17#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.07:45:38.17#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.07:45:38.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:38.17#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:45:38.17#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:45:38.17#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:45:38.17#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:45:38.17#ibcon#first serial, iclass 23, count 0 2006.210.07:45:38.17#ibcon#enter sib2, iclass 23, count 0 2006.210.07:45:38.17#ibcon#flushed, iclass 23, count 0 2006.210.07:45:38.17#ibcon#about to write, iclass 23, count 0 2006.210.07:45:38.17#ibcon#wrote, iclass 23, count 0 2006.210.07:45:38.17#ibcon#about to read 3, iclass 23, count 0 2006.210.07:45:38.19#ibcon#read 3, iclass 23, count 0 2006.210.07:45:38.19#ibcon#about to read 4, iclass 23, count 0 2006.210.07:45:38.19#ibcon#read 4, iclass 23, count 0 2006.210.07:45:38.19#ibcon#about to read 5, iclass 23, count 0 2006.210.07:45:38.19#ibcon#read 5, iclass 23, count 0 2006.210.07:45:38.19#ibcon#about to read 6, iclass 23, count 0 2006.210.07:45:38.19#ibcon#read 6, iclass 23, count 0 2006.210.07:45:38.19#ibcon#end of sib2, iclass 23, count 0 2006.210.07:45:38.19#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:45:38.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:45:38.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:45:38.19#ibcon#*before write, iclass 23, count 0 2006.210.07:45:38.19#ibcon#enter sib2, iclass 23, count 0 2006.210.07:45:38.19#ibcon#flushed, iclass 23, count 0 2006.210.07:45:38.19#ibcon#about to write, iclass 23, count 0 2006.210.07:45:38.19#ibcon#wrote, iclass 23, count 0 2006.210.07:45:38.19#ibcon#about to read 3, iclass 23, count 0 2006.210.07:45:38.23#ibcon#read 3, iclass 23, count 0 2006.210.07:45:38.23#ibcon#about to read 4, iclass 23, count 0 2006.210.07:45:38.23#ibcon#read 4, iclass 23, count 0 2006.210.07:45:38.23#ibcon#about to read 5, iclass 23, count 0 2006.210.07:45:38.23#ibcon#read 5, iclass 23, count 0 2006.210.07:45:38.23#ibcon#about to read 6, iclass 23, count 0 2006.210.07:45:38.23#ibcon#read 6, iclass 23, count 0 2006.210.07:45:38.23#ibcon#end of sib2, iclass 23, count 0 2006.210.07:45:38.23#ibcon#*after write, iclass 23, count 0 2006.210.07:45:38.23#ibcon#*before return 0, iclass 23, count 0 2006.210.07:45:38.23#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:45:38.23#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.07:45:38.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:45:38.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:45:38.23$vc4f8/va=3,6 2006.210.07:45:38.23#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.07:45:38.23#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.07:45:38.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:38.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:38.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:38.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:38.29#ibcon#enter wrdev, iclass 25, count 2 2006.210.07:45:38.29#ibcon#first serial, iclass 25, count 2 2006.210.07:45:38.29#ibcon#enter sib2, iclass 25, count 2 2006.210.07:45:38.29#ibcon#flushed, iclass 25, count 2 2006.210.07:45:38.29#ibcon#about to write, iclass 25, count 2 2006.210.07:45:38.29#ibcon#wrote, iclass 25, count 2 2006.210.07:45:38.29#ibcon#about to read 3, iclass 25, count 2 2006.210.07:45:38.31#ibcon#read 3, iclass 25, count 2 2006.210.07:45:38.31#ibcon#about to read 4, iclass 25, count 2 2006.210.07:45:38.31#ibcon#read 4, iclass 25, count 2 2006.210.07:45:38.31#ibcon#about to read 5, iclass 25, count 2 2006.210.07:45:38.31#ibcon#read 5, iclass 25, count 2 2006.210.07:45:38.31#ibcon#about to read 6, iclass 25, count 2 2006.210.07:45:38.31#ibcon#read 6, iclass 25, count 2 2006.210.07:45:38.31#ibcon#end of sib2, iclass 25, count 2 2006.210.07:45:38.31#ibcon#*mode == 0, iclass 25, count 2 2006.210.07:45:38.31#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.07:45:38.31#ibcon#[25=AT03-06\r\n] 2006.210.07:45:38.31#ibcon#*before write, iclass 25, count 2 2006.210.07:45:38.31#ibcon#enter sib2, iclass 25, count 2 2006.210.07:45:38.31#ibcon#flushed, iclass 25, count 2 2006.210.07:45:38.31#ibcon#about to write, iclass 25, count 2 2006.210.07:45:38.31#ibcon#wrote, iclass 25, count 2 2006.210.07:45:38.31#ibcon#about to read 3, iclass 25, count 2 2006.210.07:45:38.34#ibcon#read 3, iclass 25, count 2 2006.210.07:45:38.34#ibcon#about to read 4, iclass 25, count 2 2006.210.07:45:38.34#ibcon#read 4, iclass 25, count 2 2006.210.07:45:38.34#ibcon#about to read 5, iclass 25, count 2 2006.210.07:45:38.34#ibcon#read 5, iclass 25, count 2 2006.210.07:45:38.34#ibcon#about to read 6, iclass 25, count 2 2006.210.07:45:38.34#ibcon#read 6, iclass 25, count 2 2006.210.07:45:38.34#ibcon#end of sib2, iclass 25, count 2 2006.210.07:45:38.34#ibcon#*after write, iclass 25, count 2 2006.210.07:45:38.34#ibcon#*before return 0, iclass 25, count 2 2006.210.07:45:38.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:38.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:38.34#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.07:45:38.34#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:38.34#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:38.46#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:38.46#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:38.46#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:45:38.46#ibcon#first serial, iclass 25, count 0 2006.210.07:45:38.46#ibcon#enter sib2, iclass 25, count 0 2006.210.07:45:38.46#ibcon#flushed, iclass 25, count 0 2006.210.07:45:38.46#ibcon#about to write, iclass 25, count 0 2006.210.07:45:38.46#ibcon#wrote, iclass 25, count 0 2006.210.07:45:38.46#ibcon#about to read 3, iclass 25, count 0 2006.210.07:45:38.48#ibcon#read 3, iclass 25, count 0 2006.210.07:45:38.48#ibcon#about to read 4, iclass 25, count 0 2006.210.07:45:38.48#ibcon#read 4, iclass 25, count 0 2006.210.07:45:38.48#ibcon#about to read 5, iclass 25, count 0 2006.210.07:45:38.48#ibcon#read 5, iclass 25, count 0 2006.210.07:45:38.48#ibcon#about to read 6, iclass 25, count 0 2006.210.07:45:38.48#ibcon#read 6, iclass 25, count 0 2006.210.07:45:38.48#ibcon#end of sib2, iclass 25, count 0 2006.210.07:45:38.48#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:45:38.48#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:45:38.48#ibcon#[25=USB\r\n] 2006.210.07:45:38.48#ibcon#*before write, iclass 25, count 0 2006.210.07:45:38.48#ibcon#enter sib2, iclass 25, count 0 2006.210.07:45:38.48#ibcon#flushed, iclass 25, count 0 2006.210.07:45:38.48#ibcon#about to write, iclass 25, count 0 2006.210.07:45:38.48#ibcon#wrote, iclass 25, count 0 2006.210.07:45:38.48#ibcon#about to read 3, iclass 25, count 0 2006.210.07:45:38.51#ibcon#read 3, iclass 25, count 0 2006.210.07:45:38.51#ibcon#about to read 4, iclass 25, count 0 2006.210.07:45:38.51#ibcon#read 4, iclass 25, count 0 2006.210.07:45:38.51#ibcon#about to read 5, iclass 25, count 0 2006.210.07:45:38.51#ibcon#read 5, iclass 25, count 0 2006.210.07:45:38.51#ibcon#about to read 6, iclass 25, count 0 2006.210.07:45:38.51#ibcon#read 6, iclass 25, count 0 2006.210.07:45:38.51#ibcon#end of sib2, iclass 25, count 0 2006.210.07:45:38.51#ibcon#*after write, iclass 25, count 0 2006.210.07:45:38.51#ibcon#*before return 0, iclass 25, count 0 2006.210.07:45:38.51#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:38.51#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:38.51#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:45:38.51#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:45:38.51$vc4f8/valo=4,832.99 2006.210.07:45:38.51#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.07:45:38.51#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.07:45:38.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:38.51#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:38.51#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:38.51#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:38.51#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:45:38.51#ibcon#first serial, iclass 27, count 0 2006.210.07:45:38.51#ibcon#enter sib2, iclass 27, count 0 2006.210.07:45:38.51#ibcon#flushed, iclass 27, count 0 2006.210.07:45:38.51#ibcon#about to write, iclass 27, count 0 2006.210.07:45:38.51#ibcon#wrote, iclass 27, count 0 2006.210.07:45:38.51#ibcon#about to read 3, iclass 27, count 0 2006.210.07:45:38.53#ibcon#read 3, iclass 27, count 0 2006.210.07:45:38.53#ibcon#about to read 4, iclass 27, count 0 2006.210.07:45:38.53#ibcon#read 4, iclass 27, count 0 2006.210.07:45:38.53#ibcon#about to read 5, iclass 27, count 0 2006.210.07:45:38.53#ibcon#read 5, iclass 27, count 0 2006.210.07:45:38.53#ibcon#about to read 6, iclass 27, count 0 2006.210.07:45:38.53#ibcon#read 6, iclass 27, count 0 2006.210.07:45:38.53#ibcon#end of sib2, iclass 27, count 0 2006.210.07:45:38.53#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:45:38.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:45:38.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:45:38.53#ibcon#*before write, iclass 27, count 0 2006.210.07:45:38.53#ibcon#enter sib2, iclass 27, count 0 2006.210.07:45:38.53#ibcon#flushed, iclass 27, count 0 2006.210.07:45:38.53#ibcon#about to write, iclass 27, count 0 2006.210.07:45:38.53#ibcon#wrote, iclass 27, count 0 2006.210.07:45:38.53#ibcon#about to read 3, iclass 27, count 0 2006.210.07:45:38.57#ibcon#read 3, iclass 27, count 0 2006.210.07:45:38.57#ibcon#about to read 4, iclass 27, count 0 2006.210.07:45:38.57#ibcon#read 4, iclass 27, count 0 2006.210.07:45:38.57#ibcon#about to read 5, iclass 27, count 0 2006.210.07:45:38.57#ibcon#read 5, iclass 27, count 0 2006.210.07:45:38.57#ibcon#about to read 6, iclass 27, count 0 2006.210.07:45:38.57#ibcon#read 6, iclass 27, count 0 2006.210.07:45:38.57#ibcon#end of sib2, iclass 27, count 0 2006.210.07:45:38.57#ibcon#*after write, iclass 27, count 0 2006.210.07:45:38.57#ibcon#*before return 0, iclass 27, count 0 2006.210.07:45:38.57#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:38.57#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:38.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:45:38.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:45:38.57$vc4f8/va=4,7 2006.210.07:45:38.57#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.07:45:38.57#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.07:45:38.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:38.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:38.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:38.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:38.63#ibcon#enter wrdev, iclass 29, count 2 2006.210.07:45:38.63#ibcon#first serial, iclass 29, count 2 2006.210.07:45:38.63#ibcon#enter sib2, iclass 29, count 2 2006.210.07:45:38.63#ibcon#flushed, iclass 29, count 2 2006.210.07:45:38.63#ibcon#about to write, iclass 29, count 2 2006.210.07:45:38.63#ibcon#wrote, iclass 29, count 2 2006.210.07:45:38.63#ibcon#about to read 3, iclass 29, count 2 2006.210.07:45:38.65#ibcon#read 3, iclass 29, count 2 2006.210.07:45:38.65#ibcon#about to read 4, iclass 29, count 2 2006.210.07:45:38.65#ibcon#read 4, iclass 29, count 2 2006.210.07:45:38.65#ibcon#about to read 5, iclass 29, count 2 2006.210.07:45:38.65#ibcon#read 5, iclass 29, count 2 2006.210.07:45:38.65#ibcon#about to read 6, iclass 29, count 2 2006.210.07:45:38.65#ibcon#read 6, iclass 29, count 2 2006.210.07:45:38.65#ibcon#end of sib2, iclass 29, count 2 2006.210.07:45:38.65#ibcon#*mode == 0, iclass 29, count 2 2006.210.07:45:38.65#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.07:45:38.65#ibcon#[25=AT04-07\r\n] 2006.210.07:45:38.65#ibcon#*before write, iclass 29, count 2 2006.210.07:45:38.65#ibcon#enter sib2, iclass 29, count 2 2006.210.07:45:38.65#ibcon#flushed, iclass 29, count 2 2006.210.07:45:38.65#ibcon#about to write, iclass 29, count 2 2006.210.07:45:38.65#ibcon#wrote, iclass 29, count 2 2006.210.07:45:38.65#ibcon#about to read 3, iclass 29, count 2 2006.210.07:45:38.68#ibcon#read 3, iclass 29, count 2 2006.210.07:45:38.68#ibcon#about to read 4, iclass 29, count 2 2006.210.07:45:38.68#ibcon#read 4, iclass 29, count 2 2006.210.07:45:38.68#ibcon#about to read 5, iclass 29, count 2 2006.210.07:45:38.68#ibcon#read 5, iclass 29, count 2 2006.210.07:45:38.68#ibcon#about to read 6, iclass 29, count 2 2006.210.07:45:38.68#ibcon#read 6, iclass 29, count 2 2006.210.07:45:38.68#ibcon#end of sib2, iclass 29, count 2 2006.210.07:45:38.68#ibcon#*after write, iclass 29, count 2 2006.210.07:45:38.68#ibcon#*before return 0, iclass 29, count 2 2006.210.07:45:38.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:38.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:38.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.07:45:38.68#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:38.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:38.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:38.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:38.80#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:45:38.80#ibcon#first serial, iclass 29, count 0 2006.210.07:45:38.80#ibcon#enter sib2, iclass 29, count 0 2006.210.07:45:38.80#ibcon#flushed, iclass 29, count 0 2006.210.07:45:38.80#ibcon#about to write, iclass 29, count 0 2006.210.07:45:38.80#ibcon#wrote, iclass 29, count 0 2006.210.07:45:38.80#ibcon#about to read 3, iclass 29, count 0 2006.210.07:45:38.82#ibcon#read 3, iclass 29, count 0 2006.210.07:45:38.82#ibcon#about to read 4, iclass 29, count 0 2006.210.07:45:38.82#ibcon#read 4, iclass 29, count 0 2006.210.07:45:38.82#ibcon#about to read 5, iclass 29, count 0 2006.210.07:45:38.82#ibcon#read 5, iclass 29, count 0 2006.210.07:45:38.82#ibcon#about to read 6, iclass 29, count 0 2006.210.07:45:38.82#ibcon#read 6, iclass 29, count 0 2006.210.07:45:38.82#ibcon#end of sib2, iclass 29, count 0 2006.210.07:45:38.82#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:45:38.82#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:45:38.82#ibcon#[25=USB\r\n] 2006.210.07:45:38.82#ibcon#*before write, iclass 29, count 0 2006.210.07:45:38.82#ibcon#enter sib2, iclass 29, count 0 2006.210.07:45:38.82#ibcon#flushed, iclass 29, count 0 2006.210.07:45:38.82#ibcon#about to write, iclass 29, count 0 2006.210.07:45:38.82#ibcon#wrote, iclass 29, count 0 2006.210.07:45:38.82#ibcon#about to read 3, iclass 29, count 0 2006.210.07:45:38.85#ibcon#read 3, iclass 29, count 0 2006.210.07:45:38.85#ibcon#about to read 4, iclass 29, count 0 2006.210.07:45:38.85#ibcon#read 4, iclass 29, count 0 2006.210.07:45:38.85#ibcon#about to read 5, iclass 29, count 0 2006.210.07:45:38.85#ibcon#read 5, iclass 29, count 0 2006.210.07:45:38.85#ibcon#about to read 6, iclass 29, count 0 2006.210.07:45:38.85#ibcon#read 6, iclass 29, count 0 2006.210.07:45:38.85#ibcon#end of sib2, iclass 29, count 0 2006.210.07:45:38.85#ibcon#*after write, iclass 29, count 0 2006.210.07:45:38.85#ibcon#*before return 0, iclass 29, count 0 2006.210.07:45:38.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:38.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:38.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:45:38.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:45:38.85$vc4f8/valo=5,652.99 2006.210.07:45:38.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.07:45:38.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.07:45:38.85#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:38.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:38.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:38.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:38.85#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:45:38.85#ibcon#first serial, iclass 31, count 0 2006.210.07:45:38.85#ibcon#enter sib2, iclass 31, count 0 2006.210.07:45:38.85#ibcon#flushed, iclass 31, count 0 2006.210.07:45:38.85#ibcon#about to write, iclass 31, count 0 2006.210.07:45:38.85#ibcon#wrote, iclass 31, count 0 2006.210.07:45:38.85#ibcon#about to read 3, iclass 31, count 0 2006.210.07:45:38.87#ibcon#read 3, iclass 31, count 0 2006.210.07:45:38.87#ibcon#about to read 4, iclass 31, count 0 2006.210.07:45:38.87#ibcon#read 4, iclass 31, count 0 2006.210.07:45:38.87#ibcon#about to read 5, iclass 31, count 0 2006.210.07:45:38.87#ibcon#read 5, iclass 31, count 0 2006.210.07:45:38.87#ibcon#about to read 6, iclass 31, count 0 2006.210.07:45:38.87#ibcon#read 6, iclass 31, count 0 2006.210.07:45:38.87#ibcon#end of sib2, iclass 31, count 0 2006.210.07:45:38.87#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:45:38.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:45:38.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:45:38.87#ibcon#*before write, iclass 31, count 0 2006.210.07:45:38.87#ibcon#enter sib2, iclass 31, count 0 2006.210.07:45:38.87#ibcon#flushed, iclass 31, count 0 2006.210.07:45:38.87#ibcon#about to write, iclass 31, count 0 2006.210.07:45:38.87#ibcon#wrote, iclass 31, count 0 2006.210.07:45:38.87#ibcon#about to read 3, iclass 31, count 0 2006.210.07:45:38.91#ibcon#read 3, iclass 31, count 0 2006.210.07:45:38.91#ibcon#about to read 4, iclass 31, count 0 2006.210.07:45:38.91#ibcon#read 4, iclass 31, count 0 2006.210.07:45:38.91#ibcon#about to read 5, iclass 31, count 0 2006.210.07:45:38.91#ibcon#read 5, iclass 31, count 0 2006.210.07:45:38.91#ibcon#about to read 6, iclass 31, count 0 2006.210.07:45:38.91#ibcon#read 6, iclass 31, count 0 2006.210.07:45:38.91#ibcon#end of sib2, iclass 31, count 0 2006.210.07:45:38.91#ibcon#*after write, iclass 31, count 0 2006.210.07:45:38.91#ibcon#*before return 0, iclass 31, count 0 2006.210.07:45:38.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:38.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:38.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:45:38.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:45:38.91$vc4f8/va=5,7 2006.210.07:45:38.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.07:45:38.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.07:45:38.91#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:38.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:38.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:38.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:38.97#ibcon#enter wrdev, iclass 33, count 2 2006.210.07:45:38.97#ibcon#first serial, iclass 33, count 2 2006.210.07:45:38.97#ibcon#enter sib2, iclass 33, count 2 2006.210.07:45:38.97#ibcon#flushed, iclass 33, count 2 2006.210.07:45:38.97#ibcon#about to write, iclass 33, count 2 2006.210.07:45:38.97#ibcon#wrote, iclass 33, count 2 2006.210.07:45:38.97#ibcon#about to read 3, iclass 33, count 2 2006.210.07:45:38.99#ibcon#read 3, iclass 33, count 2 2006.210.07:45:38.99#ibcon#about to read 4, iclass 33, count 2 2006.210.07:45:38.99#ibcon#read 4, iclass 33, count 2 2006.210.07:45:38.99#ibcon#about to read 5, iclass 33, count 2 2006.210.07:45:38.99#ibcon#read 5, iclass 33, count 2 2006.210.07:45:38.99#ibcon#about to read 6, iclass 33, count 2 2006.210.07:45:38.99#ibcon#read 6, iclass 33, count 2 2006.210.07:45:38.99#ibcon#end of sib2, iclass 33, count 2 2006.210.07:45:38.99#ibcon#*mode == 0, iclass 33, count 2 2006.210.07:45:38.99#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.07:45:38.99#ibcon#[25=AT05-07\r\n] 2006.210.07:45:38.99#ibcon#*before write, iclass 33, count 2 2006.210.07:45:38.99#ibcon#enter sib2, iclass 33, count 2 2006.210.07:45:38.99#ibcon#flushed, iclass 33, count 2 2006.210.07:45:38.99#ibcon#about to write, iclass 33, count 2 2006.210.07:45:38.99#ibcon#wrote, iclass 33, count 2 2006.210.07:45:38.99#ibcon#about to read 3, iclass 33, count 2 2006.210.07:45:39.02#ibcon#read 3, iclass 33, count 2 2006.210.07:45:39.02#ibcon#about to read 4, iclass 33, count 2 2006.210.07:45:39.02#ibcon#read 4, iclass 33, count 2 2006.210.07:45:39.02#ibcon#about to read 5, iclass 33, count 2 2006.210.07:45:39.02#ibcon#read 5, iclass 33, count 2 2006.210.07:45:39.02#ibcon#about to read 6, iclass 33, count 2 2006.210.07:45:39.02#ibcon#read 6, iclass 33, count 2 2006.210.07:45:39.02#ibcon#end of sib2, iclass 33, count 2 2006.210.07:45:39.02#ibcon#*after write, iclass 33, count 2 2006.210.07:45:39.02#ibcon#*before return 0, iclass 33, count 2 2006.210.07:45:39.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:39.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:39.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.07:45:39.02#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:39.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:39.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:39.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:39.14#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:45:39.14#ibcon#first serial, iclass 33, count 0 2006.210.07:45:39.14#ibcon#enter sib2, iclass 33, count 0 2006.210.07:45:39.14#ibcon#flushed, iclass 33, count 0 2006.210.07:45:39.14#ibcon#about to write, iclass 33, count 0 2006.210.07:45:39.14#ibcon#wrote, iclass 33, count 0 2006.210.07:45:39.14#ibcon#about to read 3, iclass 33, count 0 2006.210.07:45:39.16#ibcon#read 3, iclass 33, count 0 2006.210.07:45:39.16#ibcon#about to read 4, iclass 33, count 0 2006.210.07:45:39.16#ibcon#read 4, iclass 33, count 0 2006.210.07:45:39.16#ibcon#about to read 5, iclass 33, count 0 2006.210.07:45:39.16#ibcon#read 5, iclass 33, count 0 2006.210.07:45:39.16#ibcon#about to read 6, iclass 33, count 0 2006.210.07:45:39.16#ibcon#read 6, iclass 33, count 0 2006.210.07:45:39.16#ibcon#end of sib2, iclass 33, count 0 2006.210.07:45:39.16#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:45:39.16#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:45:39.16#ibcon#[25=USB\r\n] 2006.210.07:45:39.16#ibcon#*before write, iclass 33, count 0 2006.210.07:45:39.16#ibcon#enter sib2, iclass 33, count 0 2006.210.07:45:39.16#ibcon#flushed, iclass 33, count 0 2006.210.07:45:39.16#ibcon#about to write, iclass 33, count 0 2006.210.07:45:39.16#ibcon#wrote, iclass 33, count 0 2006.210.07:45:39.16#ibcon#about to read 3, iclass 33, count 0 2006.210.07:45:39.19#ibcon#read 3, iclass 33, count 0 2006.210.07:45:39.19#ibcon#about to read 4, iclass 33, count 0 2006.210.07:45:39.19#ibcon#read 4, iclass 33, count 0 2006.210.07:45:39.19#ibcon#about to read 5, iclass 33, count 0 2006.210.07:45:39.19#ibcon#read 5, iclass 33, count 0 2006.210.07:45:39.19#ibcon#about to read 6, iclass 33, count 0 2006.210.07:45:39.19#ibcon#read 6, iclass 33, count 0 2006.210.07:45:39.19#ibcon#end of sib2, iclass 33, count 0 2006.210.07:45:39.19#ibcon#*after write, iclass 33, count 0 2006.210.07:45:39.19#ibcon#*before return 0, iclass 33, count 0 2006.210.07:45:39.19#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:39.19#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:39.19#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:45:39.19#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:45:39.19$vc4f8/valo=6,772.99 2006.210.07:45:39.19#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.07:45:39.19#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.07:45:39.19#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:39.19#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:39.19#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:39.19#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:39.19#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:45:39.19#ibcon#first serial, iclass 35, count 0 2006.210.07:45:39.19#ibcon#enter sib2, iclass 35, count 0 2006.210.07:45:39.19#ibcon#flushed, iclass 35, count 0 2006.210.07:45:39.19#ibcon#about to write, iclass 35, count 0 2006.210.07:45:39.19#ibcon#wrote, iclass 35, count 0 2006.210.07:45:39.19#ibcon#about to read 3, iclass 35, count 0 2006.210.07:45:39.21#ibcon#read 3, iclass 35, count 0 2006.210.07:45:39.21#ibcon#about to read 4, iclass 35, count 0 2006.210.07:45:39.21#ibcon#read 4, iclass 35, count 0 2006.210.07:45:39.21#ibcon#about to read 5, iclass 35, count 0 2006.210.07:45:39.21#ibcon#read 5, iclass 35, count 0 2006.210.07:45:39.21#ibcon#about to read 6, iclass 35, count 0 2006.210.07:45:39.21#ibcon#read 6, iclass 35, count 0 2006.210.07:45:39.21#ibcon#end of sib2, iclass 35, count 0 2006.210.07:45:39.21#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:45:39.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:45:39.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:45:39.21#ibcon#*before write, iclass 35, count 0 2006.210.07:45:39.21#ibcon#enter sib2, iclass 35, count 0 2006.210.07:45:39.21#ibcon#flushed, iclass 35, count 0 2006.210.07:45:39.21#ibcon#about to write, iclass 35, count 0 2006.210.07:45:39.21#ibcon#wrote, iclass 35, count 0 2006.210.07:45:39.21#ibcon#about to read 3, iclass 35, count 0 2006.210.07:45:39.25#ibcon#read 3, iclass 35, count 0 2006.210.07:45:39.25#ibcon#about to read 4, iclass 35, count 0 2006.210.07:45:39.25#ibcon#read 4, iclass 35, count 0 2006.210.07:45:39.25#ibcon#about to read 5, iclass 35, count 0 2006.210.07:45:39.25#ibcon#read 5, iclass 35, count 0 2006.210.07:45:39.25#ibcon#about to read 6, iclass 35, count 0 2006.210.07:45:39.25#ibcon#read 6, iclass 35, count 0 2006.210.07:45:39.25#ibcon#end of sib2, iclass 35, count 0 2006.210.07:45:39.25#ibcon#*after write, iclass 35, count 0 2006.210.07:45:39.25#ibcon#*before return 0, iclass 35, count 0 2006.210.07:45:39.25#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:39.25#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:39.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:45:39.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:45:39.25$vc4f8/va=6,6 2006.210.07:45:39.25#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:45:39.25#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:45:39.25#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:39.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:39.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:39.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:39.31#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:45:39.31#ibcon#first serial, iclass 37, count 2 2006.210.07:45:39.31#ibcon#enter sib2, iclass 37, count 2 2006.210.07:45:39.31#ibcon#flushed, iclass 37, count 2 2006.210.07:45:39.31#ibcon#about to write, iclass 37, count 2 2006.210.07:45:39.31#ibcon#wrote, iclass 37, count 2 2006.210.07:45:39.31#ibcon#about to read 3, iclass 37, count 2 2006.210.07:45:39.33#ibcon#read 3, iclass 37, count 2 2006.210.07:45:39.33#ibcon#about to read 4, iclass 37, count 2 2006.210.07:45:39.33#ibcon#read 4, iclass 37, count 2 2006.210.07:45:39.33#ibcon#about to read 5, iclass 37, count 2 2006.210.07:45:39.33#ibcon#read 5, iclass 37, count 2 2006.210.07:45:39.33#ibcon#about to read 6, iclass 37, count 2 2006.210.07:45:39.33#ibcon#read 6, iclass 37, count 2 2006.210.07:45:39.33#ibcon#end of sib2, iclass 37, count 2 2006.210.07:45:39.33#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:45:39.33#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:45:39.33#ibcon#[25=AT06-06\r\n] 2006.210.07:45:39.33#ibcon#*before write, iclass 37, count 2 2006.210.07:45:39.33#ibcon#enter sib2, iclass 37, count 2 2006.210.07:45:39.33#ibcon#flushed, iclass 37, count 2 2006.210.07:45:39.33#ibcon#about to write, iclass 37, count 2 2006.210.07:45:39.33#ibcon#wrote, iclass 37, count 2 2006.210.07:45:39.33#ibcon#about to read 3, iclass 37, count 2 2006.210.07:45:39.36#ibcon#read 3, iclass 37, count 2 2006.210.07:45:39.36#ibcon#about to read 4, iclass 37, count 2 2006.210.07:45:39.36#ibcon#read 4, iclass 37, count 2 2006.210.07:45:39.36#ibcon#about to read 5, iclass 37, count 2 2006.210.07:45:39.36#ibcon#read 5, iclass 37, count 2 2006.210.07:45:39.36#ibcon#about to read 6, iclass 37, count 2 2006.210.07:45:39.36#ibcon#read 6, iclass 37, count 2 2006.210.07:45:39.36#ibcon#end of sib2, iclass 37, count 2 2006.210.07:45:39.36#ibcon#*after write, iclass 37, count 2 2006.210.07:45:39.36#ibcon#*before return 0, iclass 37, count 2 2006.210.07:45:39.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:39.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:39.36#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:45:39.36#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:39.36#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:39.48#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:39.48#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:39.48#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:45:39.48#ibcon#first serial, iclass 37, count 0 2006.210.07:45:39.48#ibcon#enter sib2, iclass 37, count 0 2006.210.07:45:39.48#ibcon#flushed, iclass 37, count 0 2006.210.07:45:39.48#ibcon#about to write, iclass 37, count 0 2006.210.07:45:39.48#ibcon#wrote, iclass 37, count 0 2006.210.07:45:39.48#ibcon#about to read 3, iclass 37, count 0 2006.210.07:45:39.50#ibcon#read 3, iclass 37, count 0 2006.210.07:45:39.50#ibcon#about to read 4, iclass 37, count 0 2006.210.07:45:39.50#ibcon#read 4, iclass 37, count 0 2006.210.07:45:39.50#ibcon#about to read 5, iclass 37, count 0 2006.210.07:45:39.50#ibcon#read 5, iclass 37, count 0 2006.210.07:45:39.50#ibcon#about to read 6, iclass 37, count 0 2006.210.07:45:39.50#ibcon#read 6, iclass 37, count 0 2006.210.07:45:39.50#ibcon#end of sib2, iclass 37, count 0 2006.210.07:45:39.50#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:45:39.50#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:45:39.50#ibcon#[25=USB\r\n] 2006.210.07:45:39.50#ibcon#*before write, iclass 37, count 0 2006.210.07:45:39.50#ibcon#enter sib2, iclass 37, count 0 2006.210.07:45:39.50#ibcon#flushed, iclass 37, count 0 2006.210.07:45:39.50#ibcon#about to write, iclass 37, count 0 2006.210.07:45:39.50#ibcon#wrote, iclass 37, count 0 2006.210.07:45:39.50#ibcon#about to read 3, iclass 37, count 0 2006.210.07:45:39.53#ibcon#read 3, iclass 37, count 0 2006.210.07:45:39.53#ibcon#about to read 4, iclass 37, count 0 2006.210.07:45:39.53#ibcon#read 4, iclass 37, count 0 2006.210.07:45:39.53#ibcon#about to read 5, iclass 37, count 0 2006.210.07:45:39.53#ibcon#read 5, iclass 37, count 0 2006.210.07:45:39.53#ibcon#about to read 6, iclass 37, count 0 2006.210.07:45:39.53#ibcon#read 6, iclass 37, count 0 2006.210.07:45:39.53#ibcon#end of sib2, iclass 37, count 0 2006.210.07:45:39.53#ibcon#*after write, iclass 37, count 0 2006.210.07:45:39.53#ibcon#*before return 0, iclass 37, count 0 2006.210.07:45:39.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:39.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:39.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:45:39.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:45:39.53$vc4f8/valo=7,832.99 2006.210.07:45:39.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.07:45:39.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.07:45:39.53#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:39.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:39.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:39.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:39.53#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:45:39.53#ibcon#first serial, iclass 39, count 0 2006.210.07:45:39.53#ibcon#enter sib2, iclass 39, count 0 2006.210.07:45:39.53#ibcon#flushed, iclass 39, count 0 2006.210.07:45:39.53#ibcon#about to write, iclass 39, count 0 2006.210.07:45:39.53#ibcon#wrote, iclass 39, count 0 2006.210.07:45:39.53#ibcon#about to read 3, iclass 39, count 0 2006.210.07:45:39.55#ibcon#read 3, iclass 39, count 0 2006.210.07:45:39.55#ibcon#about to read 4, iclass 39, count 0 2006.210.07:45:39.55#ibcon#read 4, iclass 39, count 0 2006.210.07:45:39.55#ibcon#about to read 5, iclass 39, count 0 2006.210.07:45:39.55#ibcon#read 5, iclass 39, count 0 2006.210.07:45:39.55#ibcon#about to read 6, iclass 39, count 0 2006.210.07:45:39.55#ibcon#read 6, iclass 39, count 0 2006.210.07:45:39.55#ibcon#end of sib2, iclass 39, count 0 2006.210.07:45:39.55#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:45:39.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:45:39.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:45:39.55#ibcon#*before write, iclass 39, count 0 2006.210.07:45:39.55#ibcon#enter sib2, iclass 39, count 0 2006.210.07:45:39.55#ibcon#flushed, iclass 39, count 0 2006.210.07:45:39.55#ibcon#about to write, iclass 39, count 0 2006.210.07:45:39.55#ibcon#wrote, iclass 39, count 0 2006.210.07:45:39.55#ibcon#about to read 3, iclass 39, count 0 2006.210.07:45:39.59#ibcon#read 3, iclass 39, count 0 2006.210.07:45:39.59#ibcon#about to read 4, iclass 39, count 0 2006.210.07:45:39.59#ibcon#read 4, iclass 39, count 0 2006.210.07:45:39.59#ibcon#about to read 5, iclass 39, count 0 2006.210.07:45:39.59#ibcon#read 5, iclass 39, count 0 2006.210.07:45:39.59#ibcon#about to read 6, iclass 39, count 0 2006.210.07:45:39.59#ibcon#read 6, iclass 39, count 0 2006.210.07:45:39.59#ibcon#end of sib2, iclass 39, count 0 2006.210.07:45:39.59#ibcon#*after write, iclass 39, count 0 2006.210.07:45:39.59#ibcon#*before return 0, iclass 39, count 0 2006.210.07:45:39.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:39.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:39.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:45:39.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:45:39.59$vc4f8/va=7,6 2006.210.07:45:39.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.07:45:39.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.07:45:39.59#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:39.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:45:39.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:45:39.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:45:39.65#ibcon#enter wrdev, iclass 3, count 2 2006.210.07:45:39.65#ibcon#first serial, iclass 3, count 2 2006.210.07:45:39.65#ibcon#enter sib2, iclass 3, count 2 2006.210.07:45:39.65#ibcon#flushed, iclass 3, count 2 2006.210.07:45:39.65#ibcon#about to write, iclass 3, count 2 2006.210.07:45:39.65#ibcon#wrote, iclass 3, count 2 2006.210.07:45:39.65#ibcon#about to read 3, iclass 3, count 2 2006.210.07:45:39.67#ibcon#read 3, iclass 3, count 2 2006.210.07:45:39.67#ibcon#about to read 4, iclass 3, count 2 2006.210.07:45:39.67#ibcon#read 4, iclass 3, count 2 2006.210.07:45:39.67#ibcon#about to read 5, iclass 3, count 2 2006.210.07:45:39.67#ibcon#read 5, iclass 3, count 2 2006.210.07:45:39.67#ibcon#about to read 6, iclass 3, count 2 2006.210.07:45:39.67#ibcon#read 6, iclass 3, count 2 2006.210.07:45:39.67#ibcon#end of sib2, iclass 3, count 2 2006.210.07:45:39.67#ibcon#*mode == 0, iclass 3, count 2 2006.210.07:45:39.67#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.07:45:39.67#ibcon#[25=AT07-06\r\n] 2006.210.07:45:39.67#ibcon#*before write, iclass 3, count 2 2006.210.07:45:39.67#ibcon#enter sib2, iclass 3, count 2 2006.210.07:45:39.67#ibcon#flushed, iclass 3, count 2 2006.210.07:45:39.67#ibcon#about to write, iclass 3, count 2 2006.210.07:45:39.67#ibcon#wrote, iclass 3, count 2 2006.210.07:45:39.67#ibcon#about to read 3, iclass 3, count 2 2006.210.07:45:39.70#ibcon#read 3, iclass 3, count 2 2006.210.07:45:39.70#ibcon#about to read 4, iclass 3, count 2 2006.210.07:45:39.70#ibcon#read 4, iclass 3, count 2 2006.210.07:45:39.70#ibcon#about to read 5, iclass 3, count 2 2006.210.07:45:39.70#ibcon#read 5, iclass 3, count 2 2006.210.07:45:39.70#ibcon#about to read 6, iclass 3, count 2 2006.210.07:45:39.70#ibcon#read 6, iclass 3, count 2 2006.210.07:45:39.70#ibcon#end of sib2, iclass 3, count 2 2006.210.07:45:39.70#ibcon#*after write, iclass 3, count 2 2006.210.07:45:39.70#ibcon#*before return 0, iclass 3, count 2 2006.210.07:45:39.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:45:39.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:45:39.70#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.07:45:39.70#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:39.70#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:45:39.82#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:45:39.82#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:45:39.82#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:45:39.82#ibcon#first serial, iclass 3, count 0 2006.210.07:45:39.82#ibcon#enter sib2, iclass 3, count 0 2006.210.07:45:39.82#ibcon#flushed, iclass 3, count 0 2006.210.07:45:39.82#ibcon#about to write, iclass 3, count 0 2006.210.07:45:39.82#ibcon#wrote, iclass 3, count 0 2006.210.07:45:39.82#ibcon#about to read 3, iclass 3, count 0 2006.210.07:45:39.84#ibcon#read 3, iclass 3, count 0 2006.210.07:45:39.84#ibcon#about to read 4, iclass 3, count 0 2006.210.07:45:39.84#ibcon#read 4, iclass 3, count 0 2006.210.07:45:39.84#ibcon#about to read 5, iclass 3, count 0 2006.210.07:45:39.84#ibcon#read 5, iclass 3, count 0 2006.210.07:45:39.84#ibcon#about to read 6, iclass 3, count 0 2006.210.07:45:39.84#ibcon#read 6, iclass 3, count 0 2006.210.07:45:39.84#ibcon#end of sib2, iclass 3, count 0 2006.210.07:45:39.84#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:45:39.84#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:45:39.84#ibcon#[25=USB\r\n] 2006.210.07:45:39.84#ibcon#*before write, iclass 3, count 0 2006.210.07:45:39.84#ibcon#enter sib2, iclass 3, count 0 2006.210.07:45:39.84#ibcon#flushed, iclass 3, count 0 2006.210.07:45:39.84#ibcon#about to write, iclass 3, count 0 2006.210.07:45:39.84#ibcon#wrote, iclass 3, count 0 2006.210.07:45:39.84#ibcon#about to read 3, iclass 3, count 0 2006.210.07:45:39.87#ibcon#read 3, iclass 3, count 0 2006.210.07:45:39.87#ibcon#about to read 4, iclass 3, count 0 2006.210.07:45:39.87#ibcon#read 4, iclass 3, count 0 2006.210.07:45:39.87#ibcon#about to read 5, iclass 3, count 0 2006.210.07:45:39.87#ibcon#read 5, iclass 3, count 0 2006.210.07:45:39.87#ibcon#about to read 6, iclass 3, count 0 2006.210.07:45:39.87#ibcon#read 6, iclass 3, count 0 2006.210.07:45:39.87#ibcon#end of sib2, iclass 3, count 0 2006.210.07:45:39.87#ibcon#*after write, iclass 3, count 0 2006.210.07:45:39.87#ibcon#*before return 0, iclass 3, count 0 2006.210.07:45:39.87#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:45:39.87#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:45:39.87#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:45:39.87#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:45:39.87$vc4f8/valo=8,852.99 2006.210.07:45:39.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.07:45:39.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.07:45:39.87#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:39.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:45:39.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:45:39.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:45:39.87#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:45:39.87#ibcon#first serial, iclass 5, count 0 2006.210.07:45:39.87#ibcon#enter sib2, iclass 5, count 0 2006.210.07:45:39.87#ibcon#flushed, iclass 5, count 0 2006.210.07:45:39.87#ibcon#about to write, iclass 5, count 0 2006.210.07:45:39.87#ibcon#wrote, iclass 5, count 0 2006.210.07:45:39.87#ibcon#about to read 3, iclass 5, count 0 2006.210.07:45:39.89#ibcon#read 3, iclass 5, count 0 2006.210.07:45:39.89#ibcon#about to read 4, iclass 5, count 0 2006.210.07:45:39.89#ibcon#read 4, iclass 5, count 0 2006.210.07:45:39.89#ibcon#about to read 5, iclass 5, count 0 2006.210.07:45:39.89#ibcon#read 5, iclass 5, count 0 2006.210.07:45:39.89#ibcon#about to read 6, iclass 5, count 0 2006.210.07:45:39.89#ibcon#read 6, iclass 5, count 0 2006.210.07:45:39.89#ibcon#end of sib2, iclass 5, count 0 2006.210.07:45:39.89#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:45:39.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:45:39.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:45:39.89#ibcon#*before write, iclass 5, count 0 2006.210.07:45:39.89#ibcon#enter sib2, iclass 5, count 0 2006.210.07:45:39.89#ibcon#flushed, iclass 5, count 0 2006.210.07:45:39.89#ibcon#about to write, iclass 5, count 0 2006.210.07:45:39.89#ibcon#wrote, iclass 5, count 0 2006.210.07:45:39.89#ibcon#about to read 3, iclass 5, count 0 2006.210.07:45:39.93#ibcon#read 3, iclass 5, count 0 2006.210.07:45:39.93#ibcon#about to read 4, iclass 5, count 0 2006.210.07:45:39.93#ibcon#read 4, iclass 5, count 0 2006.210.07:45:39.93#ibcon#about to read 5, iclass 5, count 0 2006.210.07:45:39.93#ibcon#read 5, iclass 5, count 0 2006.210.07:45:39.93#ibcon#about to read 6, iclass 5, count 0 2006.210.07:45:39.93#ibcon#read 6, iclass 5, count 0 2006.210.07:45:39.93#ibcon#end of sib2, iclass 5, count 0 2006.210.07:45:39.93#ibcon#*after write, iclass 5, count 0 2006.210.07:45:39.93#ibcon#*before return 0, iclass 5, count 0 2006.210.07:45:39.93#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:45:39.93#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:45:39.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:45:39.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:45:39.93$vc4f8/va=8,7 2006.210.07:45:39.93#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.07:45:39.93#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.07:45:39.93#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:39.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:45:39.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:45:39.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:45:39.99#ibcon#enter wrdev, iclass 7, count 2 2006.210.07:45:39.99#ibcon#first serial, iclass 7, count 2 2006.210.07:45:39.99#ibcon#enter sib2, iclass 7, count 2 2006.210.07:45:39.99#ibcon#flushed, iclass 7, count 2 2006.210.07:45:39.99#ibcon#about to write, iclass 7, count 2 2006.210.07:45:39.99#ibcon#wrote, iclass 7, count 2 2006.210.07:45:39.99#ibcon#about to read 3, iclass 7, count 2 2006.210.07:45:40.01#ibcon#read 3, iclass 7, count 2 2006.210.07:45:40.01#ibcon#about to read 4, iclass 7, count 2 2006.210.07:45:40.01#ibcon#read 4, iclass 7, count 2 2006.210.07:45:40.01#ibcon#about to read 5, iclass 7, count 2 2006.210.07:45:40.01#ibcon#read 5, iclass 7, count 2 2006.210.07:45:40.01#ibcon#about to read 6, iclass 7, count 2 2006.210.07:45:40.01#ibcon#read 6, iclass 7, count 2 2006.210.07:45:40.01#ibcon#end of sib2, iclass 7, count 2 2006.210.07:45:40.01#ibcon#*mode == 0, iclass 7, count 2 2006.210.07:45:40.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.07:45:40.01#ibcon#[25=AT08-07\r\n] 2006.210.07:45:40.01#ibcon#*before write, iclass 7, count 2 2006.210.07:45:40.01#ibcon#enter sib2, iclass 7, count 2 2006.210.07:45:40.01#ibcon#flushed, iclass 7, count 2 2006.210.07:45:40.01#ibcon#about to write, iclass 7, count 2 2006.210.07:45:40.01#ibcon#wrote, iclass 7, count 2 2006.210.07:45:40.01#ibcon#about to read 3, iclass 7, count 2 2006.210.07:45:40.04#ibcon#read 3, iclass 7, count 2 2006.210.07:45:40.04#ibcon#about to read 4, iclass 7, count 2 2006.210.07:45:40.04#ibcon#read 4, iclass 7, count 2 2006.210.07:45:40.04#ibcon#about to read 5, iclass 7, count 2 2006.210.07:45:40.04#ibcon#read 5, iclass 7, count 2 2006.210.07:45:40.04#ibcon#about to read 6, iclass 7, count 2 2006.210.07:45:40.04#ibcon#read 6, iclass 7, count 2 2006.210.07:45:40.04#ibcon#end of sib2, iclass 7, count 2 2006.210.07:45:40.04#ibcon#*after write, iclass 7, count 2 2006.210.07:45:40.04#ibcon#*before return 0, iclass 7, count 2 2006.210.07:45:40.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:45:40.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:45:40.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.07:45:40.04#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:40.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:45:40.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:45:40.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:45:40.16#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:45:40.16#ibcon#first serial, iclass 7, count 0 2006.210.07:45:40.16#ibcon#enter sib2, iclass 7, count 0 2006.210.07:45:40.16#ibcon#flushed, iclass 7, count 0 2006.210.07:45:40.16#ibcon#about to write, iclass 7, count 0 2006.210.07:45:40.16#ibcon#wrote, iclass 7, count 0 2006.210.07:45:40.16#ibcon#about to read 3, iclass 7, count 0 2006.210.07:45:40.18#ibcon#read 3, iclass 7, count 0 2006.210.07:45:40.18#ibcon#about to read 4, iclass 7, count 0 2006.210.07:45:40.18#ibcon#read 4, iclass 7, count 0 2006.210.07:45:40.18#ibcon#about to read 5, iclass 7, count 0 2006.210.07:45:40.18#ibcon#read 5, iclass 7, count 0 2006.210.07:45:40.18#ibcon#about to read 6, iclass 7, count 0 2006.210.07:45:40.18#ibcon#read 6, iclass 7, count 0 2006.210.07:45:40.18#ibcon#end of sib2, iclass 7, count 0 2006.210.07:45:40.18#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:45:40.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:45:40.18#ibcon#[25=USB\r\n] 2006.210.07:45:40.18#ibcon#*before write, iclass 7, count 0 2006.210.07:45:40.18#ibcon#enter sib2, iclass 7, count 0 2006.210.07:45:40.18#ibcon#flushed, iclass 7, count 0 2006.210.07:45:40.18#ibcon#about to write, iclass 7, count 0 2006.210.07:45:40.18#ibcon#wrote, iclass 7, count 0 2006.210.07:45:40.18#ibcon#about to read 3, iclass 7, count 0 2006.210.07:45:40.21#ibcon#read 3, iclass 7, count 0 2006.210.07:45:40.21#ibcon#about to read 4, iclass 7, count 0 2006.210.07:45:40.21#ibcon#read 4, iclass 7, count 0 2006.210.07:45:40.21#ibcon#about to read 5, iclass 7, count 0 2006.210.07:45:40.21#ibcon#read 5, iclass 7, count 0 2006.210.07:45:40.21#ibcon#about to read 6, iclass 7, count 0 2006.210.07:45:40.21#ibcon#read 6, iclass 7, count 0 2006.210.07:45:40.21#ibcon#end of sib2, iclass 7, count 0 2006.210.07:45:40.21#ibcon#*after write, iclass 7, count 0 2006.210.07:45:40.21#ibcon#*before return 0, iclass 7, count 0 2006.210.07:45:40.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:45:40.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:45:40.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:45:40.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:45:40.21$vc4f8/vblo=1,632.99 2006.210.07:45:40.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.07:45:40.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.07:45:40.21#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:40.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:45:40.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:45:40.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:45:40.21#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:45:40.21#ibcon#first serial, iclass 11, count 0 2006.210.07:45:40.21#ibcon#enter sib2, iclass 11, count 0 2006.210.07:45:40.21#ibcon#flushed, iclass 11, count 0 2006.210.07:45:40.21#ibcon#about to write, iclass 11, count 0 2006.210.07:45:40.21#ibcon#wrote, iclass 11, count 0 2006.210.07:45:40.21#ibcon#about to read 3, iclass 11, count 0 2006.210.07:45:40.23#ibcon#read 3, iclass 11, count 0 2006.210.07:45:40.23#ibcon#about to read 4, iclass 11, count 0 2006.210.07:45:40.23#ibcon#read 4, iclass 11, count 0 2006.210.07:45:40.23#ibcon#about to read 5, iclass 11, count 0 2006.210.07:45:40.23#ibcon#read 5, iclass 11, count 0 2006.210.07:45:40.23#ibcon#about to read 6, iclass 11, count 0 2006.210.07:45:40.23#ibcon#read 6, iclass 11, count 0 2006.210.07:45:40.23#ibcon#end of sib2, iclass 11, count 0 2006.210.07:45:40.23#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:45:40.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:45:40.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:45:40.23#ibcon#*before write, iclass 11, count 0 2006.210.07:45:40.23#ibcon#enter sib2, iclass 11, count 0 2006.210.07:45:40.23#ibcon#flushed, iclass 11, count 0 2006.210.07:45:40.23#ibcon#about to write, iclass 11, count 0 2006.210.07:45:40.23#ibcon#wrote, iclass 11, count 0 2006.210.07:45:40.23#ibcon#about to read 3, iclass 11, count 0 2006.210.07:45:40.27#ibcon#read 3, iclass 11, count 0 2006.210.07:45:40.27#ibcon#about to read 4, iclass 11, count 0 2006.210.07:45:40.27#ibcon#read 4, iclass 11, count 0 2006.210.07:45:40.27#ibcon#about to read 5, iclass 11, count 0 2006.210.07:45:40.27#ibcon#read 5, iclass 11, count 0 2006.210.07:45:40.27#ibcon#about to read 6, iclass 11, count 0 2006.210.07:45:40.27#ibcon#read 6, iclass 11, count 0 2006.210.07:45:40.27#ibcon#end of sib2, iclass 11, count 0 2006.210.07:45:40.27#ibcon#*after write, iclass 11, count 0 2006.210.07:45:40.27#ibcon#*before return 0, iclass 11, count 0 2006.210.07:45:40.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:45:40.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:45:40.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:45:40.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:45:40.27$vc4f8/vb=1,4 2006.210.07:45:40.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.07:45:40.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.07:45:40.27#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:40.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:45:40.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:45:40.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:45:40.27#ibcon#enter wrdev, iclass 13, count 2 2006.210.07:45:40.27#ibcon#first serial, iclass 13, count 2 2006.210.07:45:40.27#ibcon#enter sib2, iclass 13, count 2 2006.210.07:45:40.27#ibcon#flushed, iclass 13, count 2 2006.210.07:45:40.27#ibcon#about to write, iclass 13, count 2 2006.210.07:45:40.27#ibcon#wrote, iclass 13, count 2 2006.210.07:45:40.27#ibcon#about to read 3, iclass 13, count 2 2006.210.07:45:40.29#ibcon#read 3, iclass 13, count 2 2006.210.07:45:40.29#ibcon#about to read 4, iclass 13, count 2 2006.210.07:45:40.29#ibcon#read 4, iclass 13, count 2 2006.210.07:45:40.29#ibcon#about to read 5, iclass 13, count 2 2006.210.07:45:40.29#ibcon#read 5, iclass 13, count 2 2006.210.07:45:40.29#ibcon#about to read 6, iclass 13, count 2 2006.210.07:45:40.29#ibcon#read 6, iclass 13, count 2 2006.210.07:45:40.29#ibcon#end of sib2, iclass 13, count 2 2006.210.07:45:40.29#ibcon#*mode == 0, iclass 13, count 2 2006.210.07:45:40.29#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.07:45:40.29#ibcon#[27=AT01-04\r\n] 2006.210.07:45:40.29#ibcon#*before write, iclass 13, count 2 2006.210.07:45:40.29#ibcon#enter sib2, iclass 13, count 2 2006.210.07:45:40.29#ibcon#flushed, iclass 13, count 2 2006.210.07:45:40.29#ibcon#about to write, iclass 13, count 2 2006.210.07:45:40.29#ibcon#wrote, iclass 13, count 2 2006.210.07:45:40.29#ibcon#about to read 3, iclass 13, count 2 2006.210.07:45:40.32#ibcon#read 3, iclass 13, count 2 2006.210.07:45:40.32#ibcon#about to read 4, iclass 13, count 2 2006.210.07:45:40.32#ibcon#read 4, iclass 13, count 2 2006.210.07:45:40.32#ibcon#about to read 5, iclass 13, count 2 2006.210.07:45:40.32#ibcon#read 5, iclass 13, count 2 2006.210.07:45:40.32#ibcon#about to read 6, iclass 13, count 2 2006.210.07:45:40.32#ibcon#read 6, iclass 13, count 2 2006.210.07:45:40.32#ibcon#end of sib2, iclass 13, count 2 2006.210.07:45:40.32#ibcon#*after write, iclass 13, count 2 2006.210.07:45:40.32#ibcon#*before return 0, iclass 13, count 2 2006.210.07:45:40.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:45:40.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:45:40.32#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.07:45:40.32#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:40.32#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:45:40.44#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:45:40.44#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:45:40.44#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:45:40.44#ibcon#first serial, iclass 13, count 0 2006.210.07:45:40.44#ibcon#enter sib2, iclass 13, count 0 2006.210.07:45:40.44#ibcon#flushed, iclass 13, count 0 2006.210.07:45:40.44#ibcon#about to write, iclass 13, count 0 2006.210.07:45:40.44#ibcon#wrote, iclass 13, count 0 2006.210.07:45:40.44#ibcon#about to read 3, iclass 13, count 0 2006.210.07:45:40.46#ibcon#read 3, iclass 13, count 0 2006.210.07:45:40.46#ibcon#about to read 4, iclass 13, count 0 2006.210.07:45:40.46#ibcon#read 4, iclass 13, count 0 2006.210.07:45:40.46#ibcon#about to read 5, iclass 13, count 0 2006.210.07:45:40.46#ibcon#read 5, iclass 13, count 0 2006.210.07:45:40.46#ibcon#about to read 6, iclass 13, count 0 2006.210.07:45:40.46#ibcon#read 6, iclass 13, count 0 2006.210.07:45:40.46#ibcon#end of sib2, iclass 13, count 0 2006.210.07:45:40.46#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:45:40.46#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:45:40.46#ibcon#[27=USB\r\n] 2006.210.07:45:40.46#ibcon#*before write, iclass 13, count 0 2006.210.07:45:40.46#ibcon#enter sib2, iclass 13, count 0 2006.210.07:45:40.46#ibcon#flushed, iclass 13, count 0 2006.210.07:45:40.46#ibcon#about to write, iclass 13, count 0 2006.210.07:45:40.46#ibcon#wrote, iclass 13, count 0 2006.210.07:45:40.46#ibcon#about to read 3, iclass 13, count 0 2006.210.07:45:40.49#ibcon#read 3, iclass 13, count 0 2006.210.07:45:40.49#ibcon#about to read 4, iclass 13, count 0 2006.210.07:45:40.49#ibcon#read 4, iclass 13, count 0 2006.210.07:45:40.49#ibcon#about to read 5, iclass 13, count 0 2006.210.07:45:40.49#ibcon#read 5, iclass 13, count 0 2006.210.07:45:40.49#ibcon#about to read 6, iclass 13, count 0 2006.210.07:45:40.49#ibcon#read 6, iclass 13, count 0 2006.210.07:45:40.49#ibcon#end of sib2, iclass 13, count 0 2006.210.07:45:40.49#ibcon#*after write, iclass 13, count 0 2006.210.07:45:40.49#ibcon#*before return 0, iclass 13, count 0 2006.210.07:45:40.49#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:45:40.49#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:45:40.49#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:45:40.49#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:45:40.49$vc4f8/vblo=2,640.99 2006.210.07:45:40.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.07:45:40.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.07:45:40.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:40.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:40.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:40.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:40.49#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:45:40.49#ibcon#first serial, iclass 15, count 0 2006.210.07:45:40.49#ibcon#enter sib2, iclass 15, count 0 2006.210.07:45:40.49#ibcon#flushed, iclass 15, count 0 2006.210.07:45:40.49#ibcon#about to write, iclass 15, count 0 2006.210.07:45:40.49#ibcon#wrote, iclass 15, count 0 2006.210.07:45:40.49#ibcon#about to read 3, iclass 15, count 0 2006.210.07:45:40.51#ibcon#read 3, iclass 15, count 0 2006.210.07:45:40.51#ibcon#about to read 4, iclass 15, count 0 2006.210.07:45:40.51#ibcon#read 4, iclass 15, count 0 2006.210.07:45:40.51#ibcon#about to read 5, iclass 15, count 0 2006.210.07:45:40.51#ibcon#read 5, iclass 15, count 0 2006.210.07:45:40.51#ibcon#about to read 6, iclass 15, count 0 2006.210.07:45:40.51#ibcon#read 6, iclass 15, count 0 2006.210.07:45:40.51#ibcon#end of sib2, iclass 15, count 0 2006.210.07:45:40.51#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:45:40.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:45:40.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:45:40.51#ibcon#*before write, iclass 15, count 0 2006.210.07:45:40.51#ibcon#enter sib2, iclass 15, count 0 2006.210.07:45:40.51#ibcon#flushed, iclass 15, count 0 2006.210.07:45:40.51#ibcon#about to write, iclass 15, count 0 2006.210.07:45:40.51#ibcon#wrote, iclass 15, count 0 2006.210.07:45:40.51#ibcon#about to read 3, iclass 15, count 0 2006.210.07:45:40.55#ibcon#read 3, iclass 15, count 0 2006.210.07:45:40.55#ibcon#about to read 4, iclass 15, count 0 2006.210.07:45:40.55#ibcon#read 4, iclass 15, count 0 2006.210.07:45:40.55#ibcon#about to read 5, iclass 15, count 0 2006.210.07:45:40.55#ibcon#read 5, iclass 15, count 0 2006.210.07:45:40.55#ibcon#about to read 6, iclass 15, count 0 2006.210.07:45:40.55#ibcon#read 6, iclass 15, count 0 2006.210.07:45:40.55#ibcon#end of sib2, iclass 15, count 0 2006.210.07:45:40.55#ibcon#*after write, iclass 15, count 0 2006.210.07:45:40.55#ibcon#*before return 0, iclass 15, count 0 2006.210.07:45:40.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:40.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:45:40.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:45:40.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:45:40.55$vc4f8/vb=2,4 2006.210.07:45:40.55#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.07:45:40.55#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.07:45:40.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:40.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:40.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:40.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:40.61#ibcon#enter wrdev, iclass 17, count 2 2006.210.07:45:40.61#ibcon#first serial, iclass 17, count 2 2006.210.07:45:40.61#ibcon#enter sib2, iclass 17, count 2 2006.210.07:45:40.61#ibcon#flushed, iclass 17, count 2 2006.210.07:45:40.61#ibcon#about to write, iclass 17, count 2 2006.210.07:45:40.61#ibcon#wrote, iclass 17, count 2 2006.210.07:45:40.61#ibcon#about to read 3, iclass 17, count 2 2006.210.07:45:40.63#ibcon#read 3, iclass 17, count 2 2006.210.07:45:40.63#ibcon#about to read 4, iclass 17, count 2 2006.210.07:45:40.63#ibcon#read 4, iclass 17, count 2 2006.210.07:45:40.63#ibcon#about to read 5, iclass 17, count 2 2006.210.07:45:40.63#ibcon#read 5, iclass 17, count 2 2006.210.07:45:40.63#ibcon#about to read 6, iclass 17, count 2 2006.210.07:45:40.63#ibcon#read 6, iclass 17, count 2 2006.210.07:45:40.63#ibcon#end of sib2, iclass 17, count 2 2006.210.07:45:40.63#ibcon#*mode == 0, iclass 17, count 2 2006.210.07:45:40.63#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.07:45:40.63#ibcon#[27=AT02-04\r\n] 2006.210.07:45:40.63#ibcon#*before write, iclass 17, count 2 2006.210.07:45:40.63#ibcon#enter sib2, iclass 17, count 2 2006.210.07:45:40.63#ibcon#flushed, iclass 17, count 2 2006.210.07:45:40.63#ibcon#about to write, iclass 17, count 2 2006.210.07:45:40.63#ibcon#wrote, iclass 17, count 2 2006.210.07:45:40.63#ibcon#about to read 3, iclass 17, count 2 2006.210.07:45:40.66#ibcon#read 3, iclass 17, count 2 2006.210.07:45:40.66#ibcon#about to read 4, iclass 17, count 2 2006.210.07:45:40.66#ibcon#read 4, iclass 17, count 2 2006.210.07:45:40.66#ibcon#about to read 5, iclass 17, count 2 2006.210.07:45:40.66#ibcon#read 5, iclass 17, count 2 2006.210.07:45:40.66#ibcon#about to read 6, iclass 17, count 2 2006.210.07:45:40.66#ibcon#read 6, iclass 17, count 2 2006.210.07:45:40.66#ibcon#end of sib2, iclass 17, count 2 2006.210.07:45:40.66#ibcon#*after write, iclass 17, count 2 2006.210.07:45:40.66#ibcon#*before return 0, iclass 17, count 2 2006.210.07:45:40.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:40.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:45:40.66#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.07:45:40.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:40.66#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:40.78#abcon#<5=/08 1.3 3.9 30.55 741006.2\r\n> 2006.210.07:45:40.78#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:40.78#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:40.78#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:45:40.78#ibcon#first serial, iclass 17, count 0 2006.210.07:45:40.78#ibcon#enter sib2, iclass 17, count 0 2006.210.07:45:40.78#ibcon#flushed, iclass 17, count 0 2006.210.07:45:40.78#ibcon#about to write, iclass 17, count 0 2006.210.07:45:40.78#ibcon#wrote, iclass 17, count 0 2006.210.07:45:40.78#ibcon#about to read 3, iclass 17, count 0 2006.210.07:45:40.80#ibcon#read 3, iclass 17, count 0 2006.210.07:45:40.80#ibcon#about to read 4, iclass 17, count 0 2006.210.07:45:40.80#ibcon#read 4, iclass 17, count 0 2006.210.07:45:40.80#ibcon#about to read 5, iclass 17, count 0 2006.210.07:45:40.80#ibcon#read 5, iclass 17, count 0 2006.210.07:45:40.80#ibcon#about to read 6, iclass 17, count 0 2006.210.07:45:40.80#ibcon#read 6, iclass 17, count 0 2006.210.07:45:40.80#ibcon#end of sib2, iclass 17, count 0 2006.210.07:45:40.80#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:45:40.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:45:40.80#ibcon#[27=USB\r\n] 2006.210.07:45:40.80#ibcon#*before write, iclass 17, count 0 2006.210.07:45:40.80#ibcon#enter sib2, iclass 17, count 0 2006.210.07:45:40.80#ibcon#flushed, iclass 17, count 0 2006.210.07:45:40.80#ibcon#about to write, iclass 17, count 0 2006.210.07:45:40.80#ibcon#wrote, iclass 17, count 0 2006.210.07:45:40.80#ibcon#about to read 3, iclass 17, count 0 2006.210.07:45:40.80#abcon#{5=INTERFACE CLEAR} 2006.210.07:45:40.83#ibcon#read 3, iclass 17, count 0 2006.210.07:45:40.83#ibcon#about to read 4, iclass 17, count 0 2006.210.07:45:40.83#ibcon#read 4, iclass 17, count 0 2006.210.07:45:40.83#ibcon#about to read 5, iclass 17, count 0 2006.210.07:45:40.83#ibcon#read 5, iclass 17, count 0 2006.210.07:45:40.83#ibcon#about to read 6, iclass 17, count 0 2006.210.07:45:40.83#ibcon#read 6, iclass 17, count 0 2006.210.07:45:40.83#ibcon#end of sib2, iclass 17, count 0 2006.210.07:45:40.83#ibcon#*after write, iclass 17, count 0 2006.210.07:45:40.83#ibcon#*before return 0, iclass 17, count 0 2006.210.07:45:40.83#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:40.83#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:45:40.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:45:40.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:45:40.83$vc4f8/vblo=3,656.99 2006.210.07:45:40.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:45:40.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:45:40.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:40.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:45:40.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:45:40.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:45:40.83#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:45:40.83#ibcon#first serial, iclass 22, count 0 2006.210.07:45:40.83#ibcon#enter sib2, iclass 22, count 0 2006.210.07:45:40.83#ibcon#flushed, iclass 22, count 0 2006.210.07:45:40.83#ibcon#about to write, iclass 22, count 0 2006.210.07:45:40.83#ibcon#wrote, iclass 22, count 0 2006.210.07:45:40.83#ibcon#about to read 3, iclass 22, count 0 2006.210.07:45:40.85#ibcon#read 3, iclass 22, count 0 2006.210.07:45:40.85#ibcon#about to read 4, iclass 22, count 0 2006.210.07:45:40.85#ibcon#read 4, iclass 22, count 0 2006.210.07:45:40.85#ibcon#about to read 5, iclass 22, count 0 2006.210.07:45:40.85#ibcon#read 5, iclass 22, count 0 2006.210.07:45:40.85#ibcon#about to read 6, iclass 22, count 0 2006.210.07:45:40.85#ibcon#read 6, iclass 22, count 0 2006.210.07:45:40.85#ibcon#end of sib2, iclass 22, count 0 2006.210.07:45:40.85#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:45:40.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:45:40.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:45:40.85#ibcon#*before write, iclass 22, count 0 2006.210.07:45:40.85#ibcon#enter sib2, iclass 22, count 0 2006.210.07:45:40.85#ibcon#flushed, iclass 22, count 0 2006.210.07:45:40.85#ibcon#about to write, iclass 22, count 0 2006.210.07:45:40.85#ibcon#wrote, iclass 22, count 0 2006.210.07:45:40.85#ibcon#about to read 3, iclass 22, count 0 2006.210.07:45:40.86#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:45:40.89#ibcon#read 3, iclass 22, count 0 2006.210.07:45:40.89#ibcon#about to read 4, iclass 22, count 0 2006.210.07:45:40.89#ibcon#read 4, iclass 22, count 0 2006.210.07:45:40.89#ibcon#about to read 5, iclass 22, count 0 2006.210.07:45:40.89#ibcon#read 5, iclass 22, count 0 2006.210.07:45:40.89#ibcon#about to read 6, iclass 22, count 0 2006.210.07:45:40.89#ibcon#read 6, iclass 22, count 0 2006.210.07:45:40.89#ibcon#end of sib2, iclass 22, count 0 2006.210.07:45:40.89#ibcon#*after write, iclass 22, count 0 2006.210.07:45:40.89#ibcon#*before return 0, iclass 22, count 0 2006.210.07:45:40.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:45:40.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:45:40.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:45:40.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:45:40.89$vc4f8/vb=3,3 2006.210.07:45:40.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.07:45:40.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.07:45:40.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:40.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:40.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:40.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:40.95#ibcon#enter wrdev, iclass 25, count 2 2006.210.07:45:40.95#ibcon#first serial, iclass 25, count 2 2006.210.07:45:40.95#ibcon#enter sib2, iclass 25, count 2 2006.210.07:45:40.95#ibcon#flushed, iclass 25, count 2 2006.210.07:45:40.95#ibcon#about to write, iclass 25, count 2 2006.210.07:45:40.95#ibcon#wrote, iclass 25, count 2 2006.210.07:45:40.95#ibcon#about to read 3, iclass 25, count 2 2006.210.07:45:40.97#ibcon#read 3, iclass 25, count 2 2006.210.07:45:40.97#ibcon#about to read 4, iclass 25, count 2 2006.210.07:45:40.97#ibcon#read 4, iclass 25, count 2 2006.210.07:45:40.97#ibcon#about to read 5, iclass 25, count 2 2006.210.07:45:40.97#ibcon#read 5, iclass 25, count 2 2006.210.07:45:40.97#ibcon#about to read 6, iclass 25, count 2 2006.210.07:45:40.97#ibcon#read 6, iclass 25, count 2 2006.210.07:45:40.97#ibcon#end of sib2, iclass 25, count 2 2006.210.07:45:40.97#ibcon#*mode == 0, iclass 25, count 2 2006.210.07:45:40.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.07:45:40.97#ibcon#[27=AT03-03\r\n] 2006.210.07:45:40.97#ibcon#*before write, iclass 25, count 2 2006.210.07:45:40.97#ibcon#enter sib2, iclass 25, count 2 2006.210.07:45:40.97#ibcon#flushed, iclass 25, count 2 2006.210.07:45:40.97#ibcon#about to write, iclass 25, count 2 2006.210.07:45:40.97#ibcon#wrote, iclass 25, count 2 2006.210.07:45:40.97#ibcon#about to read 3, iclass 25, count 2 2006.210.07:45:41.00#ibcon#read 3, iclass 25, count 2 2006.210.07:45:41.00#ibcon#about to read 4, iclass 25, count 2 2006.210.07:45:41.00#ibcon#read 4, iclass 25, count 2 2006.210.07:45:41.00#ibcon#about to read 5, iclass 25, count 2 2006.210.07:45:41.00#ibcon#read 5, iclass 25, count 2 2006.210.07:45:41.00#ibcon#about to read 6, iclass 25, count 2 2006.210.07:45:41.00#ibcon#read 6, iclass 25, count 2 2006.210.07:45:41.00#ibcon#end of sib2, iclass 25, count 2 2006.210.07:45:41.00#ibcon#*after write, iclass 25, count 2 2006.210.07:45:41.00#ibcon#*before return 0, iclass 25, count 2 2006.210.07:45:41.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:41.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.07:45:41.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.07:45:41.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:41.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:41.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:41.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:41.12#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:45:41.12#ibcon#first serial, iclass 25, count 0 2006.210.07:45:41.12#ibcon#enter sib2, iclass 25, count 0 2006.210.07:45:41.12#ibcon#flushed, iclass 25, count 0 2006.210.07:45:41.12#ibcon#about to write, iclass 25, count 0 2006.210.07:45:41.12#ibcon#wrote, iclass 25, count 0 2006.210.07:45:41.12#ibcon#about to read 3, iclass 25, count 0 2006.210.07:45:41.14#ibcon#read 3, iclass 25, count 0 2006.210.07:45:41.14#ibcon#about to read 4, iclass 25, count 0 2006.210.07:45:41.14#ibcon#read 4, iclass 25, count 0 2006.210.07:45:41.14#ibcon#about to read 5, iclass 25, count 0 2006.210.07:45:41.14#ibcon#read 5, iclass 25, count 0 2006.210.07:45:41.14#ibcon#about to read 6, iclass 25, count 0 2006.210.07:45:41.14#ibcon#read 6, iclass 25, count 0 2006.210.07:45:41.14#ibcon#end of sib2, iclass 25, count 0 2006.210.07:45:41.14#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:45:41.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:45:41.14#ibcon#[27=USB\r\n] 2006.210.07:45:41.14#ibcon#*before write, iclass 25, count 0 2006.210.07:45:41.14#ibcon#enter sib2, iclass 25, count 0 2006.210.07:45:41.14#ibcon#flushed, iclass 25, count 0 2006.210.07:45:41.14#ibcon#about to write, iclass 25, count 0 2006.210.07:45:41.14#ibcon#wrote, iclass 25, count 0 2006.210.07:45:41.14#ibcon#about to read 3, iclass 25, count 0 2006.210.07:45:41.17#ibcon#read 3, iclass 25, count 0 2006.210.07:45:41.17#ibcon#about to read 4, iclass 25, count 0 2006.210.07:45:41.17#ibcon#read 4, iclass 25, count 0 2006.210.07:45:41.17#ibcon#about to read 5, iclass 25, count 0 2006.210.07:45:41.17#ibcon#read 5, iclass 25, count 0 2006.210.07:45:41.17#ibcon#about to read 6, iclass 25, count 0 2006.210.07:45:41.17#ibcon#read 6, iclass 25, count 0 2006.210.07:45:41.17#ibcon#end of sib2, iclass 25, count 0 2006.210.07:45:41.17#ibcon#*after write, iclass 25, count 0 2006.210.07:45:41.17#ibcon#*before return 0, iclass 25, count 0 2006.210.07:45:41.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:41.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.07:45:41.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:45:41.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:45:41.17$vc4f8/vblo=4,712.99 2006.210.07:45:41.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.07:45:41.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.07:45:41.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:41.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:41.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:41.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:41.17#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:45:41.17#ibcon#first serial, iclass 27, count 0 2006.210.07:45:41.17#ibcon#enter sib2, iclass 27, count 0 2006.210.07:45:41.17#ibcon#flushed, iclass 27, count 0 2006.210.07:45:41.17#ibcon#about to write, iclass 27, count 0 2006.210.07:45:41.17#ibcon#wrote, iclass 27, count 0 2006.210.07:45:41.17#ibcon#about to read 3, iclass 27, count 0 2006.210.07:45:41.19#ibcon#read 3, iclass 27, count 0 2006.210.07:45:41.19#ibcon#about to read 4, iclass 27, count 0 2006.210.07:45:41.19#ibcon#read 4, iclass 27, count 0 2006.210.07:45:41.19#ibcon#about to read 5, iclass 27, count 0 2006.210.07:45:41.19#ibcon#read 5, iclass 27, count 0 2006.210.07:45:41.19#ibcon#about to read 6, iclass 27, count 0 2006.210.07:45:41.19#ibcon#read 6, iclass 27, count 0 2006.210.07:45:41.19#ibcon#end of sib2, iclass 27, count 0 2006.210.07:45:41.19#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:45:41.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:45:41.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:45:41.19#ibcon#*before write, iclass 27, count 0 2006.210.07:45:41.19#ibcon#enter sib2, iclass 27, count 0 2006.210.07:45:41.19#ibcon#flushed, iclass 27, count 0 2006.210.07:45:41.19#ibcon#about to write, iclass 27, count 0 2006.210.07:45:41.19#ibcon#wrote, iclass 27, count 0 2006.210.07:45:41.19#ibcon#about to read 3, iclass 27, count 0 2006.210.07:45:41.23#ibcon#read 3, iclass 27, count 0 2006.210.07:45:41.23#ibcon#about to read 4, iclass 27, count 0 2006.210.07:45:41.23#ibcon#read 4, iclass 27, count 0 2006.210.07:45:41.23#ibcon#about to read 5, iclass 27, count 0 2006.210.07:45:41.23#ibcon#read 5, iclass 27, count 0 2006.210.07:45:41.23#ibcon#about to read 6, iclass 27, count 0 2006.210.07:45:41.23#ibcon#read 6, iclass 27, count 0 2006.210.07:45:41.23#ibcon#end of sib2, iclass 27, count 0 2006.210.07:45:41.23#ibcon#*after write, iclass 27, count 0 2006.210.07:45:41.23#ibcon#*before return 0, iclass 27, count 0 2006.210.07:45:41.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:41.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:45:41.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:45:41.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:45:41.23$vc4f8/vb=4,3 2006.210.07:45:41.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.07:45:41.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.07:45:41.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:41.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:41.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:41.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:41.29#ibcon#enter wrdev, iclass 29, count 2 2006.210.07:45:41.29#ibcon#first serial, iclass 29, count 2 2006.210.07:45:41.29#ibcon#enter sib2, iclass 29, count 2 2006.210.07:45:41.29#ibcon#flushed, iclass 29, count 2 2006.210.07:45:41.29#ibcon#about to write, iclass 29, count 2 2006.210.07:45:41.29#ibcon#wrote, iclass 29, count 2 2006.210.07:45:41.29#ibcon#about to read 3, iclass 29, count 2 2006.210.07:45:41.31#ibcon#read 3, iclass 29, count 2 2006.210.07:45:41.31#ibcon#about to read 4, iclass 29, count 2 2006.210.07:45:41.31#ibcon#read 4, iclass 29, count 2 2006.210.07:45:41.31#ibcon#about to read 5, iclass 29, count 2 2006.210.07:45:41.31#ibcon#read 5, iclass 29, count 2 2006.210.07:45:41.31#ibcon#about to read 6, iclass 29, count 2 2006.210.07:45:41.31#ibcon#read 6, iclass 29, count 2 2006.210.07:45:41.31#ibcon#end of sib2, iclass 29, count 2 2006.210.07:45:41.31#ibcon#*mode == 0, iclass 29, count 2 2006.210.07:45:41.31#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.07:45:41.31#ibcon#[27=AT04-03\r\n] 2006.210.07:45:41.31#ibcon#*before write, iclass 29, count 2 2006.210.07:45:41.31#ibcon#enter sib2, iclass 29, count 2 2006.210.07:45:41.31#ibcon#flushed, iclass 29, count 2 2006.210.07:45:41.31#ibcon#about to write, iclass 29, count 2 2006.210.07:45:41.31#ibcon#wrote, iclass 29, count 2 2006.210.07:45:41.31#ibcon#about to read 3, iclass 29, count 2 2006.210.07:45:41.34#ibcon#read 3, iclass 29, count 2 2006.210.07:45:41.34#ibcon#about to read 4, iclass 29, count 2 2006.210.07:45:41.34#ibcon#read 4, iclass 29, count 2 2006.210.07:45:41.34#ibcon#about to read 5, iclass 29, count 2 2006.210.07:45:41.34#ibcon#read 5, iclass 29, count 2 2006.210.07:45:41.34#ibcon#about to read 6, iclass 29, count 2 2006.210.07:45:41.34#ibcon#read 6, iclass 29, count 2 2006.210.07:45:41.34#ibcon#end of sib2, iclass 29, count 2 2006.210.07:45:41.34#ibcon#*after write, iclass 29, count 2 2006.210.07:45:41.34#ibcon#*before return 0, iclass 29, count 2 2006.210.07:45:41.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:41.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:45:41.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.07:45:41.34#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:41.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:41.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:41.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:41.46#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:45:41.46#ibcon#first serial, iclass 29, count 0 2006.210.07:45:41.46#ibcon#enter sib2, iclass 29, count 0 2006.210.07:45:41.46#ibcon#flushed, iclass 29, count 0 2006.210.07:45:41.46#ibcon#about to write, iclass 29, count 0 2006.210.07:45:41.46#ibcon#wrote, iclass 29, count 0 2006.210.07:45:41.46#ibcon#about to read 3, iclass 29, count 0 2006.210.07:45:41.48#ibcon#read 3, iclass 29, count 0 2006.210.07:45:41.48#ibcon#about to read 4, iclass 29, count 0 2006.210.07:45:41.48#ibcon#read 4, iclass 29, count 0 2006.210.07:45:41.48#ibcon#about to read 5, iclass 29, count 0 2006.210.07:45:41.48#ibcon#read 5, iclass 29, count 0 2006.210.07:45:41.48#ibcon#about to read 6, iclass 29, count 0 2006.210.07:45:41.48#ibcon#read 6, iclass 29, count 0 2006.210.07:45:41.48#ibcon#end of sib2, iclass 29, count 0 2006.210.07:45:41.48#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:45:41.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:45:41.48#ibcon#[27=USB\r\n] 2006.210.07:45:41.48#ibcon#*before write, iclass 29, count 0 2006.210.07:45:41.48#ibcon#enter sib2, iclass 29, count 0 2006.210.07:45:41.48#ibcon#flushed, iclass 29, count 0 2006.210.07:45:41.48#ibcon#about to write, iclass 29, count 0 2006.210.07:45:41.48#ibcon#wrote, iclass 29, count 0 2006.210.07:45:41.48#ibcon#about to read 3, iclass 29, count 0 2006.210.07:45:41.51#ibcon#read 3, iclass 29, count 0 2006.210.07:45:41.51#ibcon#about to read 4, iclass 29, count 0 2006.210.07:45:41.51#ibcon#read 4, iclass 29, count 0 2006.210.07:45:41.51#ibcon#about to read 5, iclass 29, count 0 2006.210.07:45:41.51#ibcon#read 5, iclass 29, count 0 2006.210.07:45:41.51#ibcon#about to read 6, iclass 29, count 0 2006.210.07:45:41.51#ibcon#read 6, iclass 29, count 0 2006.210.07:45:41.51#ibcon#end of sib2, iclass 29, count 0 2006.210.07:45:41.51#ibcon#*after write, iclass 29, count 0 2006.210.07:45:41.51#ibcon#*before return 0, iclass 29, count 0 2006.210.07:45:41.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:41.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:45:41.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:45:41.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:45:41.51$vc4f8/vblo=5,744.99 2006.210.07:45:41.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.07:45:41.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.07:45:41.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:41.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:41.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:41.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:41.51#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:45:41.51#ibcon#first serial, iclass 31, count 0 2006.210.07:45:41.51#ibcon#enter sib2, iclass 31, count 0 2006.210.07:45:41.51#ibcon#flushed, iclass 31, count 0 2006.210.07:45:41.51#ibcon#about to write, iclass 31, count 0 2006.210.07:45:41.51#ibcon#wrote, iclass 31, count 0 2006.210.07:45:41.51#ibcon#about to read 3, iclass 31, count 0 2006.210.07:45:41.53#ibcon#read 3, iclass 31, count 0 2006.210.07:45:41.53#ibcon#about to read 4, iclass 31, count 0 2006.210.07:45:41.53#ibcon#read 4, iclass 31, count 0 2006.210.07:45:41.53#ibcon#about to read 5, iclass 31, count 0 2006.210.07:45:41.53#ibcon#read 5, iclass 31, count 0 2006.210.07:45:41.53#ibcon#about to read 6, iclass 31, count 0 2006.210.07:45:41.53#ibcon#read 6, iclass 31, count 0 2006.210.07:45:41.53#ibcon#end of sib2, iclass 31, count 0 2006.210.07:45:41.53#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:45:41.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:45:41.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:45:41.53#ibcon#*before write, iclass 31, count 0 2006.210.07:45:41.53#ibcon#enter sib2, iclass 31, count 0 2006.210.07:45:41.53#ibcon#flushed, iclass 31, count 0 2006.210.07:45:41.53#ibcon#about to write, iclass 31, count 0 2006.210.07:45:41.53#ibcon#wrote, iclass 31, count 0 2006.210.07:45:41.53#ibcon#about to read 3, iclass 31, count 0 2006.210.07:45:41.57#ibcon#read 3, iclass 31, count 0 2006.210.07:45:41.57#ibcon#about to read 4, iclass 31, count 0 2006.210.07:45:41.57#ibcon#read 4, iclass 31, count 0 2006.210.07:45:41.57#ibcon#about to read 5, iclass 31, count 0 2006.210.07:45:41.57#ibcon#read 5, iclass 31, count 0 2006.210.07:45:41.57#ibcon#about to read 6, iclass 31, count 0 2006.210.07:45:41.57#ibcon#read 6, iclass 31, count 0 2006.210.07:45:41.57#ibcon#end of sib2, iclass 31, count 0 2006.210.07:45:41.57#ibcon#*after write, iclass 31, count 0 2006.210.07:45:41.57#ibcon#*before return 0, iclass 31, count 0 2006.210.07:45:41.57#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:41.57#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:45:41.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:45:41.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:45:41.57$vc4f8/vb=5,3 2006.210.07:45:41.57#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.07:45:41.57#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.07:45:41.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:41.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:41.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:41.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:41.63#ibcon#enter wrdev, iclass 33, count 2 2006.210.07:45:41.63#ibcon#first serial, iclass 33, count 2 2006.210.07:45:41.63#ibcon#enter sib2, iclass 33, count 2 2006.210.07:45:41.63#ibcon#flushed, iclass 33, count 2 2006.210.07:45:41.63#ibcon#about to write, iclass 33, count 2 2006.210.07:45:41.63#ibcon#wrote, iclass 33, count 2 2006.210.07:45:41.63#ibcon#about to read 3, iclass 33, count 2 2006.210.07:45:41.65#ibcon#read 3, iclass 33, count 2 2006.210.07:45:41.65#ibcon#about to read 4, iclass 33, count 2 2006.210.07:45:41.65#ibcon#read 4, iclass 33, count 2 2006.210.07:45:41.65#ibcon#about to read 5, iclass 33, count 2 2006.210.07:45:41.65#ibcon#read 5, iclass 33, count 2 2006.210.07:45:41.65#ibcon#about to read 6, iclass 33, count 2 2006.210.07:45:41.65#ibcon#read 6, iclass 33, count 2 2006.210.07:45:41.65#ibcon#end of sib2, iclass 33, count 2 2006.210.07:45:41.65#ibcon#*mode == 0, iclass 33, count 2 2006.210.07:45:41.65#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.07:45:41.65#ibcon#[27=AT05-03\r\n] 2006.210.07:45:41.65#ibcon#*before write, iclass 33, count 2 2006.210.07:45:41.65#ibcon#enter sib2, iclass 33, count 2 2006.210.07:45:41.65#ibcon#flushed, iclass 33, count 2 2006.210.07:45:41.65#ibcon#about to write, iclass 33, count 2 2006.210.07:45:41.65#ibcon#wrote, iclass 33, count 2 2006.210.07:45:41.65#ibcon#about to read 3, iclass 33, count 2 2006.210.07:45:41.68#ibcon#read 3, iclass 33, count 2 2006.210.07:45:41.68#ibcon#about to read 4, iclass 33, count 2 2006.210.07:45:41.68#ibcon#read 4, iclass 33, count 2 2006.210.07:45:41.68#ibcon#about to read 5, iclass 33, count 2 2006.210.07:45:41.68#ibcon#read 5, iclass 33, count 2 2006.210.07:45:41.68#ibcon#about to read 6, iclass 33, count 2 2006.210.07:45:41.68#ibcon#read 6, iclass 33, count 2 2006.210.07:45:41.68#ibcon#end of sib2, iclass 33, count 2 2006.210.07:45:41.68#ibcon#*after write, iclass 33, count 2 2006.210.07:45:41.68#ibcon#*before return 0, iclass 33, count 2 2006.210.07:45:41.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:41.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:45:41.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.07:45:41.68#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:41.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:41.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:41.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:41.80#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:45:41.80#ibcon#first serial, iclass 33, count 0 2006.210.07:45:41.80#ibcon#enter sib2, iclass 33, count 0 2006.210.07:45:41.80#ibcon#flushed, iclass 33, count 0 2006.210.07:45:41.80#ibcon#about to write, iclass 33, count 0 2006.210.07:45:41.80#ibcon#wrote, iclass 33, count 0 2006.210.07:45:41.80#ibcon#about to read 3, iclass 33, count 0 2006.210.07:45:41.82#ibcon#read 3, iclass 33, count 0 2006.210.07:45:41.82#ibcon#about to read 4, iclass 33, count 0 2006.210.07:45:41.82#ibcon#read 4, iclass 33, count 0 2006.210.07:45:41.82#ibcon#about to read 5, iclass 33, count 0 2006.210.07:45:41.82#ibcon#read 5, iclass 33, count 0 2006.210.07:45:41.82#ibcon#about to read 6, iclass 33, count 0 2006.210.07:45:41.82#ibcon#read 6, iclass 33, count 0 2006.210.07:45:41.82#ibcon#end of sib2, iclass 33, count 0 2006.210.07:45:41.82#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:45:41.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:45:41.82#ibcon#[27=USB\r\n] 2006.210.07:45:41.82#ibcon#*before write, iclass 33, count 0 2006.210.07:45:41.82#ibcon#enter sib2, iclass 33, count 0 2006.210.07:45:41.82#ibcon#flushed, iclass 33, count 0 2006.210.07:45:41.82#ibcon#about to write, iclass 33, count 0 2006.210.07:45:41.82#ibcon#wrote, iclass 33, count 0 2006.210.07:45:41.82#ibcon#about to read 3, iclass 33, count 0 2006.210.07:45:41.85#ibcon#read 3, iclass 33, count 0 2006.210.07:45:41.85#ibcon#about to read 4, iclass 33, count 0 2006.210.07:45:41.85#ibcon#read 4, iclass 33, count 0 2006.210.07:45:41.85#ibcon#about to read 5, iclass 33, count 0 2006.210.07:45:41.85#ibcon#read 5, iclass 33, count 0 2006.210.07:45:41.85#ibcon#about to read 6, iclass 33, count 0 2006.210.07:45:41.85#ibcon#read 6, iclass 33, count 0 2006.210.07:45:41.85#ibcon#end of sib2, iclass 33, count 0 2006.210.07:45:41.85#ibcon#*after write, iclass 33, count 0 2006.210.07:45:41.85#ibcon#*before return 0, iclass 33, count 0 2006.210.07:45:41.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:41.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:45:41.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:45:41.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:45:41.85$vc4f8/vblo=6,752.99 2006.210.07:45:41.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.07:45:41.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.07:45:41.85#ibcon#ireg 17 cls_cnt 0 2006.210.07:45:41.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:41.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:41.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:41.85#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:45:41.85#ibcon#first serial, iclass 35, count 0 2006.210.07:45:41.85#ibcon#enter sib2, iclass 35, count 0 2006.210.07:45:41.85#ibcon#flushed, iclass 35, count 0 2006.210.07:45:41.85#ibcon#about to write, iclass 35, count 0 2006.210.07:45:41.85#ibcon#wrote, iclass 35, count 0 2006.210.07:45:41.85#ibcon#about to read 3, iclass 35, count 0 2006.210.07:45:41.87#ibcon#read 3, iclass 35, count 0 2006.210.07:45:41.87#ibcon#about to read 4, iclass 35, count 0 2006.210.07:45:41.87#ibcon#read 4, iclass 35, count 0 2006.210.07:45:41.87#ibcon#about to read 5, iclass 35, count 0 2006.210.07:45:41.87#ibcon#read 5, iclass 35, count 0 2006.210.07:45:41.87#ibcon#about to read 6, iclass 35, count 0 2006.210.07:45:41.87#ibcon#read 6, iclass 35, count 0 2006.210.07:45:41.87#ibcon#end of sib2, iclass 35, count 0 2006.210.07:45:41.87#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:45:41.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:45:41.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:45:41.87#ibcon#*before write, iclass 35, count 0 2006.210.07:45:41.87#ibcon#enter sib2, iclass 35, count 0 2006.210.07:45:41.87#ibcon#flushed, iclass 35, count 0 2006.210.07:45:41.87#ibcon#about to write, iclass 35, count 0 2006.210.07:45:41.87#ibcon#wrote, iclass 35, count 0 2006.210.07:45:41.87#ibcon#about to read 3, iclass 35, count 0 2006.210.07:45:41.91#ibcon#read 3, iclass 35, count 0 2006.210.07:45:41.91#ibcon#about to read 4, iclass 35, count 0 2006.210.07:45:41.91#ibcon#read 4, iclass 35, count 0 2006.210.07:45:41.91#ibcon#about to read 5, iclass 35, count 0 2006.210.07:45:41.91#ibcon#read 5, iclass 35, count 0 2006.210.07:45:41.91#ibcon#about to read 6, iclass 35, count 0 2006.210.07:45:41.91#ibcon#read 6, iclass 35, count 0 2006.210.07:45:41.91#ibcon#end of sib2, iclass 35, count 0 2006.210.07:45:41.91#ibcon#*after write, iclass 35, count 0 2006.210.07:45:41.91#ibcon#*before return 0, iclass 35, count 0 2006.210.07:45:41.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:41.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:45:41.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:45:41.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:45:41.91$vc4f8/vb=6,3 2006.210.07:45:41.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:45:41.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:45:41.91#ibcon#ireg 11 cls_cnt 2 2006.210.07:45:41.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:41.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:41.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:41.97#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:45:41.97#ibcon#first serial, iclass 37, count 2 2006.210.07:45:41.97#ibcon#enter sib2, iclass 37, count 2 2006.210.07:45:41.97#ibcon#flushed, iclass 37, count 2 2006.210.07:45:41.97#ibcon#about to write, iclass 37, count 2 2006.210.07:45:41.97#ibcon#wrote, iclass 37, count 2 2006.210.07:45:41.97#ibcon#about to read 3, iclass 37, count 2 2006.210.07:45:41.99#ibcon#read 3, iclass 37, count 2 2006.210.07:45:41.99#ibcon#about to read 4, iclass 37, count 2 2006.210.07:45:41.99#ibcon#read 4, iclass 37, count 2 2006.210.07:45:41.99#ibcon#about to read 5, iclass 37, count 2 2006.210.07:45:41.99#ibcon#read 5, iclass 37, count 2 2006.210.07:45:41.99#ibcon#about to read 6, iclass 37, count 2 2006.210.07:45:41.99#ibcon#read 6, iclass 37, count 2 2006.210.07:45:41.99#ibcon#end of sib2, iclass 37, count 2 2006.210.07:45:41.99#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:45:41.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:45:41.99#ibcon#[27=AT06-03\r\n] 2006.210.07:45:41.99#ibcon#*before write, iclass 37, count 2 2006.210.07:45:41.99#ibcon#enter sib2, iclass 37, count 2 2006.210.07:45:41.99#ibcon#flushed, iclass 37, count 2 2006.210.07:45:41.99#ibcon#about to write, iclass 37, count 2 2006.210.07:45:41.99#ibcon#wrote, iclass 37, count 2 2006.210.07:45:41.99#ibcon#about to read 3, iclass 37, count 2 2006.210.07:45:42.02#ibcon#read 3, iclass 37, count 2 2006.210.07:45:42.02#ibcon#about to read 4, iclass 37, count 2 2006.210.07:45:42.02#ibcon#read 4, iclass 37, count 2 2006.210.07:45:42.02#ibcon#about to read 5, iclass 37, count 2 2006.210.07:45:42.02#ibcon#read 5, iclass 37, count 2 2006.210.07:45:42.02#ibcon#about to read 6, iclass 37, count 2 2006.210.07:45:42.02#ibcon#read 6, iclass 37, count 2 2006.210.07:45:42.02#ibcon#end of sib2, iclass 37, count 2 2006.210.07:45:42.02#ibcon#*after write, iclass 37, count 2 2006.210.07:45:42.02#ibcon#*before return 0, iclass 37, count 2 2006.210.07:45:42.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:42.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:45:42.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:45:42.02#ibcon#ireg 7 cls_cnt 0 2006.210.07:45:42.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:42.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:42.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:42.14#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:45:42.14#ibcon#first serial, iclass 37, count 0 2006.210.07:45:42.14#ibcon#enter sib2, iclass 37, count 0 2006.210.07:45:42.14#ibcon#flushed, iclass 37, count 0 2006.210.07:45:42.14#ibcon#about to write, iclass 37, count 0 2006.210.07:45:42.14#ibcon#wrote, iclass 37, count 0 2006.210.07:45:42.14#ibcon#about to read 3, iclass 37, count 0 2006.210.07:45:42.16#ibcon#read 3, iclass 37, count 0 2006.210.07:45:42.16#ibcon#about to read 4, iclass 37, count 0 2006.210.07:45:42.16#ibcon#read 4, iclass 37, count 0 2006.210.07:45:42.16#ibcon#about to read 5, iclass 37, count 0 2006.210.07:45:42.16#ibcon#read 5, iclass 37, count 0 2006.210.07:45:42.16#ibcon#about to read 6, iclass 37, count 0 2006.210.07:45:42.16#ibcon#read 6, iclass 37, count 0 2006.210.07:45:42.16#ibcon#end of sib2, iclass 37, count 0 2006.210.07:45:42.16#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:45:42.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:45:42.16#ibcon#[27=USB\r\n] 2006.210.07:45:42.16#ibcon#*before write, iclass 37, count 0 2006.210.07:45:42.16#ibcon#enter sib2, iclass 37, count 0 2006.210.07:45:42.16#ibcon#flushed, iclass 37, count 0 2006.210.07:45:42.16#ibcon#about to write, iclass 37, count 0 2006.210.07:45:42.16#ibcon#wrote, iclass 37, count 0 2006.210.07:45:42.16#ibcon#about to read 3, iclass 37, count 0 2006.210.07:45:42.19#ibcon#read 3, iclass 37, count 0 2006.210.07:45:42.19#ibcon#about to read 4, iclass 37, count 0 2006.210.07:45:42.19#ibcon#read 4, iclass 37, count 0 2006.210.07:45:42.19#ibcon#about to read 5, iclass 37, count 0 2006.210.07:45:42.19#ibcon#read 5, iclass 37, count 0 2006.210.07:45:42.19#ibcon#about to read 6, iclass 37, count 0 2006.210.07:45:42.19#ibcon#read 6, iclass 37, count 0 2006.210.07:45:42.19#ibcon#end of sib2, iclass 37, count 0 2006.210.07:45:42.19#ibcon#*after write, iclass 37, count 0 2006.210.07:45:42.19#ibcon#*before return 0, iclass 37, count 0 2006.210.07:45:42.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:42.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:45:42.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:45:42.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:45:42.19$vc4f8/vabw=wide 2006.210.07:45:42.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.07:45:42.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.07:45:42.19#ibcon#ireg 8 cls_cnt 0 2006.210.07:45:42.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:42.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:42.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:42.19#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:45:42.19#ibcon#first serial, iclass 39, count 0 2006.210.07:45:42.19#ibcon#enter sib2, iclass 39, count 0 2006.210.07:45:42.19#ibcon#flushed, iclass 39, count 0 2006.210.07:45:42.19#ibcon#about to write, iclass 39, count 0 2006.210.07:45:42.19#ibcon#wrote, iclass 39, count 0 2006.210.07:45:42.19#ibcon#about to read 3, iclass 39, count 0 2006.210.07:45:42.21#ibcon#read 3, iclass 39, count 0 2006.210.07:45:42.21#ibcon#about to read 4, iclass 39, count 0 2006.210.07:45:42.21#ibcon#read 4, iclass 39, count 0 2006.210.07:45:42.21#ibcon#about to read 5, iclass 39, count 0 2006.210.07:45:42.21#ibcon#read 5, iclass 39, count 0 2006.210.07:45:42.21#ibcon#about to read 6, iclass 39, count 0 2006.210.07:45:42.21#ibcon#read 6, iclass 39, count 0 2006.210.07:45:42.21#ibcon#end of sib2, iclass 39, count 0 2006.210.07:45:42.21#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:45:42.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:45:42.21#ibcon#[25=BW32\r\n] 2006.210.07:45:42.21#ibcon#*before write, iclass 39, count 0 2006.210.07:45:42.21#ibcon#enter sib2, iclass 39, count 0 2006.210.07:45:42.21#ibcon#flushed, iclass 39, count 0 2006.210.07:45:42.21#ibcon#about to write, iclass 39, count 0 2006.210.07:45:42.21#ibcon#wrote, iclass 39, count 0 2006.210.07:45:42.21#ibcon#about to read 3, iclass 39, count 0 2006.210.07:45:42.24#ibcon#read 3, iclass 39, count 0 2006.210.07:45:42.24#ibcon#about to read 4, iclass 39, count 0 2006.210.07:45:42.24#ibcon#read 4, iclass 39, count 0 2006.210.07:45:42.24#ibcon#about to read 5, iclass 39, count 0 2006.210.07:45:42.24#ibcon#read 5, iclass 39, count 0 2006.210.07:45:42.24#ibcon#about to read 6, iclass 39, count 0 2006.210.07:45:42.24#ibcon#read 6, iclass 39, count 0 2006.210.07:45:42.24#ibcon#end of sib2, iclass 39, count 0 2006.210.07:45:42.24#ibcon#*after write, iclass 39, count 0 2006.210.07:45:42.24#ibcon#*before return 0, iclass 39, count 0 2006.210.07:45:42.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:42.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:45:42.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:45:42.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:45:42.24$vc4f8/vbbw=wide 2006.210.07:45:42.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:45:42.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:45:42.24#ibcon#ireg 8 cls_cnt 0 2006.210.07:45:42.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:45:42.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:45:42.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:45:42.31#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:45:42.31#ibcon#first serial, iclass 3, count 0 2006.210.07:45:42.31#ibcon#enter sib2, iclass 3, count 0 2006.210.07:45:42.31#ibcon#flushed, iclass 3, count 0 2006.210.07:45:42.31#ibcon#about to write, iclass 3, count 0 2006.210.07:45:42.31#ibcon#wrote, iclass 3, count 0 2006.210.07:45:42.31#ibcon#about to read 3, iclass 3, count 0 2006.210.07:45:42.33#ibcon#read 3, iclass 3, count 0 2006.210.07:45:42.33#ibcon#about to read 4, iclass 3, count 0 2006.210.07:45:42.33#ibcon#read 4, iclass 3, count 0 2006.210.07:45:42.33#ibcon#about to read 5, iclass 3, count 0 2006.210.07:45:42.33#ibcon#read 5, iclass 3, count 0 2006.210.07:45:42.33#ibcon#about to read 6, iclass 3, count 0 2006.210.07:45:42.33#ibcon#read 6, iclass 3, count 0 2006.210.07:45:42.33#ibcon#end of sib2, iclass 3, count 0 2006.210.07:45:42.33#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:45:42.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:45:42.33#ibcon#[27=BW32\r\n] 2006.210.07:45:42.33#ibcon#*before write, iclass 3, count 0 2006.210.07:45:42.33#ibcon#enter sib2, iclass 3, count 0 2006.210.07:45:42.33#ibcon#flushed, iclass 3, count 0 2006.210.07:45:42.33#ibcon#about to write, iclass 3, count 0 2006.210.07:45:42.33#ibcon#wrote, iclass 3, count 0 2006.210.07:45:42.33#ibcon#about to read 3, iclass 3, count 0 2006.210.07:45:42.36#ibcon#read 3, iclass 3, count 0 2006.210.07:45:42.36#ibcon#about to read 4, iclass 3, count 0 2006.210.07:45:42.36#ibcon#read 4, iclass 3, count 0 2006.210.07:45:42.36#ibcon#about to read 5, iclass 3, count 0 2006.210.07:45:42.36#ibcon#read 5, iclass 3, count 0 2006.210.07:45:42.36#ibcon#about to read 6, iclass 3, count 0 2006.210.07:45:42.36#ibcon#read 6, iclass 3, count 0 2006.210.07:45:42.36#ibcon#end of sib2, iclass 3, count 0 2006.210.07:45:42.36#ibcon#*after write, iclass 3, count 0 2006.210.07:45:42.36#ibcon#*before return 0, iclass 3, count 0 2006.210.07:45:42.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:45:42.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:45:42.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:45:42.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:45:42.36$4f8m12a/ifd4f 2006.210.07:45:42.36$ifd4f/lo= 2006.210.07:45:42.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:45:42.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:45:42.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:45:42.36$ifd4f/patch= 2006.210.07:45:42.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:45:42.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:45:42.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:45:42.36$4f8m12a/"form=m,16.000,1:2 2006.210.07:45:42.36$4f8m12a/"tpicd 2006.210.07:45:42.36$4f8m12a/echo=off 2006.210.07:45:42.36$4f8m12a/xlog=off 2006.210.07:45:42.36:!2006.210.07:46:40 2006.210.07:46:22.14#trakl#Source acquired 2006.210.07:46:22.14#flagr#flagr/antenna,acquired 2006.210.07:46:40.00:preob 2006.210.07:46:41.14/onsource/TRACKING 2006.210.07:46:41.14:!2006.210.07:46:50 2006.210.07:46:50.00:data_valid=on 2006.210.07:46:50.00:midob 2006.210.07:46:50.14/onsource/TRACKING 2006.210.07:46:50.14/wx/30.55,1006.2,73 2006.210.07:46:50.38/cable/+6.3957E-03 2006.210.07:46:51.47/va/01,08,usb,yes,29,30 2006.210.07:46:51.47/va/02,07,usb,yes,29,30 2006.210.07:46:51.47/va/03,06,usb,yes,30,31 2006.210.07:46:51.47/va/04,07,usb,yes,30,32 2006.210.07:46:51.47/va/05,07,usb,yes,30,32 2006.210.07:46:51.47/va/06,06,usb,yes,30,29 2006.210.07:46:51.47/va/07,06,usb,yes,30,30 2006.210.07:46:51.47/va/08,07,usb,yes,29,28 2006.210.07:46:51.70/valo/01,532.99,yes,locked 2006.210.07:46:51.70/valo/02,572.99,yes,locked 2006.210.07:46:51.70/valo/03,672.99,yes,locked 2006.210.07:46:51.70/valo/04,832.99,yes,locked 2006.210.07:46:51.70/valo/05,652.99,yes,locked 2006.210.07:46:51.70/valo/06,772.99,yes,locked 2006.210.07:46:51.70/valo/07,832.99,yes,locked 2006.210.07:46:51.70/valo/08,852.99,yes,locked 2006.210.07:46:52.79/vb/01,04,usb,yes,28,27 2006.210.07:46:52.79/vb/02,04,usb,yes,30,31 2006.210.07:46:52.79/vb/03,03,usb,yes,33,37 2006.210.07:46:52.79/vb/04,03,usb,yes,34,34 2006.210.07:46:52.79/vb/05,03,usb,yes,33,37 2006.210.07:46:52.79/vb/06,03,usb,yes,33,37 2006.210.07:46:52.79/vb/07,04,usb,yes,29,29 2006.210.07:46:52.79/vb/08,03,usb,yes,33,37 2006.210.07:46:53.02/vblo/01,632.99,yes,locked 2006.210.07:46:53.02/vblo/02,640.99,yes,locked 2006.210.07:46:53.02/vblo/03,656.99,yes,locked 2006.210.07:46:53.02/vblo/04,712.99,yes,locked 2006.210.07:46:53.02/vblo/05,744.99,yes,locked 2006.210.07:46:53.02/vblo/06,752.99,yes,locked 2006.210.07:46:53.02/vblo/07,734.99,yes,locked 2006.210.07:46:53.02/vblo/08,744.99,yes,locked 2006.210.07:46:53.17/vabw/8 2006.210.07:46:53.32/vbbw/8 2006.210.07:46:53.41/xfe/off,on,12.7 2006.210.07:46:53.80/ifatt/23,28,28,28 2006.210.07:46:54.07/fmout-gps/S +4.54E-07 2006.210.07:46:54.11:!2006.210.07:48:30 2006.210.07:48:30.00:data_valid=off 2006.210.07:48:30.00:postob 2006.210.07:48:30.14/cable/+6.3951E-03 2006.210.07:48:30.14/wx/30.55,1006.3,73 2006.210.07:48:31.07/fmout-gps/S +4.58E-07 2006.210.07:48:31.07:scan_name=210-0749,k06210,60 2006.210.07:48:31.07:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.210.07:48:32.13#flagr#flagr/antenna,new-source 2006.210.07:48:32.13:checkk5 2006.210.07:48:32.49/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:48:32.84/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:48:33.18/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:48:33.52/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:48:33.85/chk_obsdata//k5ts1/T2100746??a.dat file size is correct (nominal:800MB, actual:792MB). 2006.210.07:48:34.18/chk_obsdata//k5ts2/T2100746??b.dat file size is correct (nominal:800MB, actual:792MB). 2006.210.07:48:34.51/chk_obsdata//k5ts3/T2100746??c.dat file size is correct (nominal:800MB, actual:792MB). 2006.210.07:48:34.85/chk_obsdata//k5ts4/T2100746??d.dat file size is correct (nominal:800MB, actual:792MB). 2006.210.07:48:35.50/k5log//k5ts1_log_newline 2006.210.07:48:36.17/k5log//k5ts2_log_newline 2006.210.07:48:36.82/k5log//k5ts3_log_newline 2006.210.07:48:37.48/k5log//k5ts4_log_newline 2006.210.07:48:37.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:48:37.50:4f8m12a=1 2006.210.07:48:37.50$4f8m12a/echo=on 2006.210.07:48:37.50$4f8m12a/pcalon 2006.210.07:48:37.50$pcalon/"no phase cal control is implemented here 2006.210.07:48:37.50$4f8m12a/"tpicd=stop 2006.210.07:48:37.50$4f8m12a/vc4f8 2006.210.07:48:37.50$vc4f8/valo=1,532.99 2006.210.07:48:37.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:48:37.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:48:37.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:37.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:37.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:37.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:37.51#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:48:37.51#ibcon#first serial, iclass 40, count 0 2006.210.07:48:37.51#ibcon#enter sib2, iclass 40, count 0 2006.210.07:48:37.51#ibcon#flushed, iclass 40, count 0 2006.210.07:48:37.51#ibcon#about to write, iclass 40, count 0 2006.210.07:48:37.51#ibcon#wrote, iclass 40, count 0 2006.210.07:48:37.51#ibcon#about to read 3, iclass 40, count 0 2006.210.07:48:37.52#ibcon#read 3, iclass 40, count 0 2006.210.07:48:37.52#ibcon#about to read 4, iclass 40, count 0 2006.210.07:48:37.52#ibcon#read 4, iclass 40, count 0 2006.210.07:48:37.52#ibcon#about to read 5, iclass 40, count 0 2006.210.07:48:37.52#ibcon#read 5, iclass 40, count 0 2006.210.07:48:37.52#ibcon#about to read 6, iclass 40, count 0 2006.210.07:48:37.52#ibcon#read 6, iclass 40, count 0 2006.210.07:48:37.52#ibcon#end of sib2, iclass 40, count 0 2006.210.07:48:37.52#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:48:37.52#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:48:37.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:48:37.52#ibcon#*before write, iclass 40, count 0 2006.210.07:48:37.52#ibcon#enter sib2, iclass 40, count 0 2006.210.07:48:37.52#ibcon#flushed, iclass 40, count 0 2006.210.07:48:37.52#ibcon#about to write, iclass 40, count 0 2006.210.07:48:37.52#ibcon#wrote, iclass 40, count 0 2006.210.07:48:37.52#ibcon#about to read 3, iclass 40, count 0 2006.210.07:48:37.57#ibcon#read 3, iclass 40, count 0 2006.210.07:48:37.57#ibcon#about to read 4, iclass 40, count 0 2006.210.07:48:37.57#ibcon#read 4, iclass 40, count 0 2006.210.07:48:37.57#ibcon#about to read 5, iclass 40, count 0 2006.210.07:48:37.57#ibcon#read 5, iclass 40, count 0 2006.210.07:48:37.57#ibcon#about to read 6, iclass 40, count 0 2006.210.07:48:37.57#ibcon#read 6, iclass 40, count 0 2006.210.07:48:37.57#ibcon#end of sib2, iclass 40, count 0 2006.210.07:48:37.57#ibcon#*after write, iclass 40, count 0 2006.210.07:48:37.57#ibcon#*before return 0, iclass 40, count 0 2006.210.07:48:37.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:37.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:37.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:48:37.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:48:37.57$vc4f8/va=1,8 2006.210.07:48:37.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:48:37.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:48:37.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:37.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:37.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:37.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:37.57#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:48:37.57#ibcon#first serial, iclass 4, count 2 2006.210.07:48:37.57#ibcon#enter sib2, iclass 4, count 2 2006.210.07:48:37.57#ibcon#flushed, iclass 4, count 2 2006.210.07:48:37.57#ibcon#about to write, iclass 4, count 2 2006.210.07:48:37.57#ibcon#wrote, iclass 4, count 2 2006.210.07:48:37.57#ibcon#about to read 3, iclass 4, count 2 2006.210.07:48:37.59#ibcon#read 3, iclass 4, count 2 2006.210.07:48:37.59#ibcon#about to read 4, iclass 4, count 2 2006.210.07:48:37.59#ibcon#read 4, iclass 4, count 2 2006.210.07:48:37.59#ibcon#about to read 5, iclass 4, count 2 2006.210.07:48:37.59#ibcon#read 5, iclass 4, count 2 2006.210.07:48:37.59#ibcon#about to read 6, iclass 4, count 2 2006.210.07:48:37.59#ibcon#read 6, iclass 4, count 2 2006.210.07:48:37.59#ibcon#end of sib2, iclass 4, count 2 2006.210.07:48:37.59#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:48:37.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:48:37.59#ibcon#[25=AT01-08\r\n] 2006.210.07:48:37.59#ibcon#*before write, iclass 4, count 2 2006.210.07:48:37.59#ibcon#enter sib2, iclass 4, count 2 2006.210.07:48:37.59#ibcon#flushed, iclass 4, count 2 2006.210.07:48:37.59#ibcon#about to write, iclass 4, count 2 2006.210.07:48:37.59#ibcon#wrote, iclass 4, count 2 2006.210.07:48:37.59#ibcon#about to read 3, iclass 4, count 2 2006.210.07:48:37.62#ibcon#read 3, iclass 4, count 2 2006.210.07:48:37.62#ibcon#about to read 4, iclass 4, count 2 2006.210.07:48:37.62#ibcon#read 4, iclass 4, count 2 2006.210.07:48:37.62#ibcon#about to read 5, iclass 4, count 2 2006.210.07:48:37.62#ibcon#read 5, iclass 4, count 2 2006.210.07:48:37.62#ibcon#about to read 6, iclass 4, count 2 2006.210.07:48:37.62#ibcon#read 6, iclass 4, count 2 2006.210.07:48:37.62#ibcon#end of sib2, iclass 4, count 2 2006.210.07:48:37.62#ibcon#*after write, iclass 4, count 2 2006.210.07:48:37.62#ibcon#*before return 0, iclass 4, count 2 2006.210.07:48:37.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:37.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:37.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:48:37.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:37.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:37.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:37.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:37.74#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:48:37.74#ibcon#first serial, iclass 4, count 0 2006.210.07:48:37.74#ibcon#enter sib2, iclass 4, count 0 2006.210.07:48:37.74#ibcon#flushed, iclass 4, count 0 2006.210.07:48:37.74#ibcon#about to write, iclass 4, count 0 2006.210.07:48:37.74#ibcon#wrote, iclass 4, count 0 2006.210.07:48:37.74#ibcon#about to read 3, iclass 4, count 0 2006.210.07:48:37.76#ibcon#read 3, iclass 4, count 0 2006.210.07:48:37.76#ibcon#about to read 4, iclass 4, count 0 2006.210.07:48:37.76#ibcon#read 4, iclass 4, count 0 2006.210.07:48:37.76#ibcon#about to read 5, iclass 4, count 0 2006.210.07:48:37.76#ibcon#read 5, iclass 4, count 0 2006.210.07:48:37.76#ibcon#about to read 6, iclass 4, count 0 2006.210.07:48:37.76#ibcon#read 6, iclass 4, count 0 2006.210.07:48:37.76#ibcon#end of sib2, iclass 4, count 0 2006.210.07:48:37.76#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:48:37.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:48:37.76#ibcon#[25=USB\r\n] 2006.210.07:48:37.76#ibcon#*before write, iclass 4, count 0 2006.210.07:48:37.76#ibcon#enter sib2, iclass 4, count 0 2006.210.07:48:37.76#ibcon#flushed, iclass 4, count 0 2006.210.07:48:37.76#ibcon#about to write, iclass 4, count 0 2006.210.07:48:37.76#ibcon#wrote, iclass 4, count 0 2006.210.07:48:37.76#ibcon#about to read 3, iclass 4, count 0 2006.210.07:48:37.79#ibcon#read 3, iclass 4, count 0 2006.210.07:48:37.79#ibcon#about to read 4, iclass 4, count 0 2006.210.07:48:37.79#ibcon#read 4, iclass 4, count 0 2006.210.07:48:37.79#ibcon#about to read 5, iclass 4, count 0 2006.210.07:48:37.79#ibcon#read 5, iclass 4, count 0 2006.210.07:48:37.79#ibcon#about to read 6, iclass 4, count 0 2006.210.07:48:37.79#ibcon#read 6, iclass 4, count 0 2006.210.07:48:37.79#ibcon#end of sib2, iclass 4, count 0 2006.210.07:48:37.79#ibcon#*after write, iclass 4, count 0 2006.210.07:48:37.79#ibcon#*before return 0, iclass 4, count 0 2006.210.07:48:37.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:37.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:37.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:48:37.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:48:37.79$vc4f8/valo=2,572.99 2006.210.07:48:37.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:48:37.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:48:37.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:37.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:37.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:37.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:37.79#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:48:37.79#ibcon#first serial, iclass 6, count 0 2006.210.07:48:37.79#ibcon#enter sib2, iclass 6, count 0 2006.210.07:48:37.79#ibcon#flushed, iclass 6, count 0 2006.210.07:48:37.79#ibcon#about to write, iclass 6, count 0 2006.210.07:48:37.79#ibcon#wrote, iclass 6, count 0 2006.210.07:48:37.79#ibcon#about to read 3, iclass 6, count 0 2006.210.07:48:37.81#ibcon#read 3, iclass 6, count 0 2006.210.07:48:37.81#ibcon#about to read 4, iclass 6, count 0 2006.210.07:48:37.81#ibcon#read 4, iclass 6, count 0 2006.210.07:48:37.81#ibcon#about to read 5, iclass 6, count 0 2006.210.07:48:37.81#ibcon#read 5, iclass 6, count 0 2006.210.07:48:37.81#ibcon#about to read 6, iclass 6, count 0 2006.210.07:48:37.81#ibcon#read 6, iclass 6, count 0 2006.210.07:48:37.81#ibcon#end of sib2, iclass 6, count 0 2006.210.07:48:37.81#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:48:37.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:48:37.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:48:37.81#ibcon#*before write, iclass 6, count 0 2006.210.07:48:37.81#ibcon#enter sib2, iclass 6, count 0 2006.210.07:48:37.81#ibcon#flushed, iclass 6, count 0 2006.210.07:48:37.81#ibcon#about to write, iclass 6, count 0 2006.210.07:48:37.81#ibcon#wrote, iclass 6, count 0 2006.210.07:48:37.81#ibcon#about to read 3, iclass 6, count 0 2006.210.07:48:37.85#ibcon#read 3, iclass 6, count 0 2006.210.07:48:37.85#ibcon#about to read 4, iclass 6, count 0 2006.210.07:48:37.85#ibcon#read 4, iclass 6, count 0 2006.210.07:48:37.85#ibcon#about to read 5, iclass 6, count 0 2006.210.07:48:37.85#ibcon#read 5, iclass 6, count 0 2006.210.07:48:37.85#ibcon#about to read 6, iclass 6, count 0 2006.210.07:48:37.85#ibcon#read 6, iclass 6, count 0 2006.210.07:48:37.85#ibcon#end of sib2, iclass 6, count 0 2006.210.07:48:37.85#ibcon#*after write, iclass 6, count 0 2006.210.07:48:37.85#ibcon#*before return 0, iclass 6, count 0 2006.210.07:48:37.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:37.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:37.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:48:37.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:48:37.85$vc4f8/va=2,7 2006.210.07:48:37.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:48:37.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:48:37.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:37.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:37.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:37.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:37.91#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:48:37.91#ibcon#first serial, iclass 10, count 2 2006.210.07:48:37.91#ibcon#enter sib2, iclass 10, count 2 2006.210.07:48:37.91#ibcon#flushed, iclass 10, count 2 2006.210.07:48:37.91#ibcon#about to write, iclass 10, count 2 2006.210.07:48:37.91#ibcon#wrote, iclass 10, count 2 2006.210.07:48:37.91#ibcon#about to read 3, iclass 10, count 2 2006.210.07:48:37.93#ibcon#read 3, iclass 10, count 2 2006.210.07:48:37.93#ibcon#about to read 4, iclass 10, count 2 2006.210.07:48:37.93#ibcon#read 4, iclass 10, count 2 2006.210.07:48:37.93#ibcon#about to read 5, iclass 10, count 2 2006.210.07:48:37.93#ibcon#read 5, iclass 10, count 2 2006.210.07:48:37.93#ibcon#about to read 6, iclass 10, count 2 2006.210.07:48:37.93#ibcon#read 6, iclass 10, count 2 2006.210.07:48:37.93#ibcon#end of sib2, iclass 10, count 2 2006.210.07:48:37.93#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:48:37.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:48:37.93#ibcon#[25=AT02-07\r\n] 2006.210.07:48:37.93#ibcon#*before write, iclass 10, count 2 2006.210.07:48:37.93#ibcon#enter sib2, iclass 10, count 2 2006.210.07:48:37.93#ibcon#flushed, iclass 10, count 2 2006.210.07:48:37.93#ibcon#about to write, iclass 10, count 2 2006.210.07:48:37.93#ibcon#wrote, iclass 10, count 2 2006.210.07:48:37.93#ibcon#about to read 3, iclass 10, count 2 2006.210.07:48:37.96#ibcon#read 3, iclass 10, count 2 2006.210.07:48:37.96#ibcon#about to read 4, iclass 10, count 2 2006.210.07:48:37.96#ibcon#read 4, iclass 10, count 2 2006.210.07:48:37.96#ibcon#about to read 5, iclass 10, count 2 2006.210.07:48:37.96#ibcon#read 5, iclass 10, count 2 2006.210.07:48:37.96#ibcon#about to read 6, iclass 10, count 2 2006.210.07:48:37.96#ibcon#read 6, iclass 10, count 2 2006.210.07:48:37.96#ibcon#end of sib2, iclass 10, count 2 2006.210.07:48:37.96#ibcon#*after write, iclass 10, count 2 2006.210.07:48:37.96#ibcon#*before return 0, iclass 10, count 2 2006.210.07:48:37.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:37.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:37.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:48:37.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:37.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:38.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:38.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:38.08#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:48:38.08#ibcon#first serial, iclass 10, count 0 2006.210.07:48:38.08#ibcon#enter sib2, iclass 10, count 0 2006.210.07:48:38.08#ibcon#flushed, iclass 10, count 0 2006.210.07:48:38.08#ibcon#about to write, iclass 10, count 0 2006.210.07:48:38.08#ibcon#wrote, iclass 10, count 0 2006.210.07:48:38.08#ibcon#about to read 3, iclass 10, count 0 2006.210.07:48:38.10#ibcon#read 3, iclass 10, count 0 2006.210.07:48:38.10#ibcon#about to read 4, iclass 10, count 0 2006.210.07:48:38.10#ibcon#read 4, iclass 10, count 0 2006.210.07:48:38.10#ibcon#about to read 5, iclass 10, count 0 2006.210.07:48:38.10#ibcon#read 5, iclass 10, count 0 2006.210.07:48:38.10#ibcon#about to read 6, iclass 10, count 0 2006.210.07:48:38.10#ibcon#read 6, iclass 10, count 0 2006.210.07:48:38.10#ibcon#end of sib2, iclass 10, count 0 2006.210.07:48:38.10#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:48:38.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:48:38.10#ibcon#[25=USB\r\n] 2006.210.07:48:38.10#ibcon#*before write, iclass 10, count 0 2006.210.07:48:38.10#ibcon#enter sib2, iclass 10, count 0 2006.210.07:48:38.10#ibcon#flushed, iclass 10, count 0 2006.210.07:48:38.10#ibcon#about to write, iclass 10, count 0 2006.210.07:48:38.10#ibcon#wrote, iclass 10, count 0 2006.210.07:48:38.10#ibcon#about to read 3, iclass 10, count 0 2006.210.07:48:38.13#ibcon#read 3, iclass 10, count 0 2006.210.07:48:38.13#ibcon#about to read 4, iclass 10, count 0 2006.210.07:48:38.13#ibcon#read 4, iclass 10, count 0 2006.210.07:48:38.13#ibcon#about to read 5, iclass 10, count 0 2006.210.07:48:38.13#ibcon#read 5, iclass 10, count 0 2006.210.07:48:38.13#ibcon#about to read 6, iclass 10, count 0 2006.210.07:48:38.13#ibcon#read 6, iclass 10, count 0 2006.210.07:48:38.13#ibcon#end of sib2, iclass 10, count 0 2006.210.07:48:38.13#ibcon#*after write, iclass 10, count 0 2006.210.07:48:38.13#ibcon#*before return 0, iclass 10, count 0 2006.210.07:48:38.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:38.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:38.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:48:38.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:48:38.13$vc4f8/valo=3,672.99 2006.210.07:48:38.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:48:38.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:48:38.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:38.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:38.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:38.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:38.13#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:48:38.13#ibcon#first serial, iclass 12, count 0 2006.210.07:48:38.13#ibcon#enter sib2, iclass 12, count 0 2006.210.07:48:38.13#ibcon#flushed, iclass 12, count 0 2006.210.07:48:38.13#ibcon#about to write, iclass 12, count 0 2006.210.07:48:38.13#ibcon#wrote, iclass 12, count 0 2006.210.07:48:38.13#ibcon#about to read 3, iclass 12, count 0 2006.210.07:48:38.15#ibcon#read 3, iclass 12, count 0 2006.210.07:48:38.15#ibcon#about to read 4, iclass 12, count 0 2006.210.07:48:38.15#ibcon#read 4, iclass 12, count 0 2006.210.07:48:38.15#ibcon#about to read 5, iclass 12, count 0 2006.210.07:48:38.15#ibcon#read 5, iclass 12, count 0 2006.210.07:48:38.15#ibcon#about to read 6, iclass 12, count 0 2006.210.07:48:38.15#ibcon#read 6, iclass 12, count 0 2006.210.07:48:38.15#ibcon#end of sib2, iclass 12, count 0 2006.210.07:48:38.15#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:48:38.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:48:38.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:48:38.15#ibcon#*before write, iclass 12, count 0 2006.210.07:48:38.15#ibcon#enter sib2, iclass 12, count 0 2006.210.07:48:38.15#ibcon#flushed, iclass 12, count 0 2006.210.07:48:38.15#ibcon#about to write, iclass 12, count 0 2006.210.07:48:38.15#ibcon#wrote, iclass 12, count 0 2006.210.07:48:38.15#ibcon#about to read 3, iclass 12, count 0 2006.210.07:48:38.19#ibcon#read 3, iclass 12, count 0 2006.210.07:48:38.19#ibcon#about to read 4, iclass 12, count 0 2006.210.07:48:38.19#ibcon#read 4, iclass 12, count 0 2006.210.07:48:38.19#ibcon#about to read 5, iclass 12, count 0 2006.210.07:48:38.19#ibcon#read 5, iclass 12, count 0 2006.210.07:48:38.19#ibcon#about to read 6, iclass 12, count 0 2006.210.07:48:38.19#ibcon#read 6, iclass 12, count 0 2006.210.07:48:38.19#ibcon#end of sib2, iclass 12, count 0 2006.210.07:48:38.19#ibcon#*after write, iclass 12, count 0 2006.210.07:48:38.19#ibcon#*before return 0, iclass 12, count 0 2006.210.07:48:38.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:38.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:38.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:48:38.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:48:38.19$vc4f8/va=3,6 2006.210.07:48:38.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:48:38.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:48:38.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:38.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:38.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:38.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:38.25#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:48:38.25#ibcon#first serial, iclass 14, count 2 2006.210.07:48:38.25#ibcon#enter sib2, iclass 14, count 2 2006.210.07:48:38.25#ibcon#flushed, iclass 14, count 2 2006.210.07:48:38.25#ibcon#about to write, iclass 14, count 2 2006.210.07:48:38.25#ibcon#wrote, iclass 14, count 2 2006.210.07:48:38.25#ibcon#about to read 3, iclass 14, count 2 2006.210.07:48:38.27#ibcon#read 3, iclass 14, count 2 2006.210.07:48:38.27#ibcon#about to read 4, iclass 14, count 2 2006.210.07:48:38.27#ibcon#read 4, iclass 14, count 2 2006.210.07:48:38.27#ibcon#about to read 5, iclass 14, count 2 2006.210.07:48:38.27#ibcon#read 5, iclass 14, count 2 2006.210.07:48:38.27#ibcon#about to read 6, iclass 14, count 2 2006.210.07:48:38.27#ibcon#read 6, iclass 14, count 2 2006.210.07:48:38.27#ibcon#end of sib2, iclass 14, count 2 2006.210.07:48:38.27#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:48:38.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:48:38.27#ibcon#[25=AT03-06\r\n] 2006.210.07:48:38.27#ibcon#*before write, iclass 14, count 2 2006.210.07:48:38.27#ibcon#enter sib2, iclass 14, count 2 2006.210.07:48:38.27#ibcon#flushed, iclass 14, count 2 2006.210.07:48:38.27#ibcon#about to write, iclass 14, count 2 2006.210.07:48:38.27#ibcon#wrote, iclass 14, count 2 2006.210.07:48:38.27#ibcon#about to read 3, iclass 14, count 2 2006.210.07:48:38.30#ibcon#read 3, iclass 14, count 2 2006.210.07:48:38.30#ibcon#about to read 4, iclass 14, count 2 2006.210.07:48:38.30#ibcon#read 4, iclass 14, count 2 2006.210.07:48:38.30#ibcon#about to read 5, iclass 14, count 2 2006.210.07:48:38.30#ibcon#read 5, iclass 14, count 2 2006.210.07:48:38.30#ibcon#about to read 6, iclass 14, count 2 2006.210.07:48:38.30#ibcon#read 6, iclass 14, count 2 2006.210.07:48:38.30#ibcon#end of sib2, iclass 14, count 2 2006.210.07:48:38.30#ibcon#*after write, iclass 14, count 2 2006.210.07:48:38.30#ibcon#*before return 0, iclass 14, count 2 2006.210.07:48:38.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:38.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:38.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:48:38.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:38.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:38.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:38.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:38.42#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:48:38.42#ibcon#first serial, iclass 14, count 0 2006.210.07:48:38.42#ibcon#enter sib2, iclass 14, count 0 2006.210.07:48:38.42#ibcon#flushed, iclass 14, count 0 2006.210.07:48:38.42#ibcon#about to write, iclass 14, count 0 2006.210.07:48:38.42#ibcon#wrote, iclass 14, count 0 2006.210.07:48:38.42#ibcon#about to read 3, iclass 14, count 0 2006.210.07:48:38.44#ibcon#read 3, iclass 14, count 0 2006.210.07:48:38.44#ibcon#about to read 4, iclass 14, count 0 2006.210.07:48:38.44#ibcon#read 4, iclass 14, count 0 2006.210.07:48:38.44#ibcon#about to read 5, iclass 14, count 0 2006.210.07:48:38.44#ibcon#read 5, iclass 14, count 0 2006.210.07:48:38.44#ibcon#about to read 6, iclass 14, count 0 2006.210.07:48:38.44#ibcon#read 6, iclass 14, count 0 2006.210.07:48:38.44#ibcon#end of sib2, iclass 14, count 0 2006.210.07:48:38.44#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:48:38.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:48:38.44#ibcon#[25=USB\r\n] 2006.210.07:48:38.44#ibcon#*before write, iclass 14, count 0 2006.210.07:48:38.44#ibcon#enter sib2, iclass 14, count 0 2006.210.07:48:38.44#ibcon#flushed, iclass 14, count 0 2006.210.07:48:38.44#ibcon#about to write, iclass 14, count 0 2006.210.07:48:38.44#ibcon#wrote, iclass 14, count 0 2006.210.07:48:38.44#ibcon#about to read 3, iclass 14, count 0 2006.210.07:48:38.47#ibcon#read 3, iclass 14, count 0 2006.210.07:48:38.47#ibcon#about to read 4, iclass 14, count 0 2006.210.07:48:38.47#ibcon#read 4, iclass 14, count 0 2006.210.07:48:38.47#ibcon#about to read 5, iclass 14, count 0 2006.210.07:48:38.47#ibcon#read 5, iclass 14, count 0 2006.210.07:48:38.47#ibcon#about to read 6, iclass 14, count 0 2006.210.07:48:38.47#ibcon#read 6, iclass 14, count 0 2006.210.07:48:38.47#ibcon#end of sib2, iclass 14, count 0 2006.210.07:48:38.47#ibcon#*after write, iclass 14, count 0 2006.210.07:48:38.47#ibcon#*before return 0, iclass 14, count 0 2006.210.07:48:38.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:38.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:38.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:48:38.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:48:38.47$vc4f8/valo=4,832.99 2006.210.07:48:38.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:48:38.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:48:38.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:38.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:38.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:38.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:38.47#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:48:38.47#ibcon#first serial, iclass 16, count 0 2006.210.07:48:38.47#ibcon#enter sib2, iclass 16, count 0 2006.210.07:48:38.47#ibcon#flushed, iclass 16, count 0 2006.210.07:48:38.47#ibcon#about to write, iclass 16, count 0 2006.210.07:48:38.47#ibcon#wrote, iclass 16, count 0 2006.210.07:48:38.47#ibcon#about to read 3, iclass 16, count 0 2006.210.07:48:38.49#ibcon#read 3, iclass 16, count 0 2006.210.07:48:38.49#ibcon#about to read 4, iclass 16, count 0 2006.210.07:48:38.49#ibcon#read 4, iclass 16, count 0 2006.210.07:48:38.49#ibcon#about to read 5, iclass 16, count 0 2006.210.07:48:38.49#ibcon#read 5, iclass 16, count 0 2006.210.07:48:38.49#ibcon#about to read 6, iclass 16, count 0 2006.210.07:48:38.49#ibcon#read 6, iclass 16, count 0 2006.210.07:48:38.49#ibcon#end of sib2, iclass 16, count 0 2006.210.07:48:38.49#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:48:38.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:48:38.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:48:38.49#ibcon#*before write, iclass 16, count 0 2006.210.07:48:38.49#ibcon#enter sib2, iclass 16, count 0 2006.210.07:48:38.49#ibcon#flushed, iclass 16, count 0 2006.210.07:48:38.49#ibcon#about to write, iclass 16, count 0 2006.210.07:48:38.49#ibcon#wrote, iclass 16, count 0 2006.210.07:48:38.49#ibcon#about to read 3, iclass 16, count 0 2006.210.07:48:38.53#ibcon#read 3, iclass 16, count 0 2006.210.07:48:38.53#ibcon#about to read 4, iclass 16, count 0 2006.210.07:48:38.53#ibcon#read 4, iclass 16, count 0 2006.210.07:48:38.53#ibcon#about to read 5, iclass 16, count 0 2006.210.07:48:38.53#ibcon#read 5, iclass 16, count 0 2006.210.07:48:38.53#ibcon#about to read 6, iclass 16, count 0 2006.210.07:48:38.53#ibcon#read 6, iclass 16, count 0 2006.210.07:48:38.53#ibcon#end of sib2, iclass 16, count 0 2006.210.07:48:38.53#ibcon#*after write, iclass 16, count 0 2006.210.07:48:38.53#ibcon#*before return 0, iclass 16, count 0 2006.210.07:48:38.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:38.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:38.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:48:38.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:48:38.53$vc4f8/va=4,7 2006.210.07:48:38.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:48:38.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:48:38.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:38.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:38.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:38.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:38.59#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:48:38.59#ibcon#first serial, iclass 18, count 2 2006.210.07:48:38.59#ibcon#enter sib2, iclass 18, count 2 2006.210.07:48:38.59#ibcon#flushed, iclass 18, count 2 2006.210.07:48:38.59#ibcon#about to write, iclass 18, count 2 2006.210.07:48:38.59#ibcon#wrote, iclass 18, count 2 2006.210.07:48:38.59#ibcon#about to read 3, iclass 18, count 2 2006.210.07:48:38.61#ibcon#read 3, iclass 18, count 2 2006.210.07:48:38.61#ibcon#about to read 4, iclass 18, count 2 2006.210.07:48:38.61#ibcon#read 4, iclass 18, count 2 2006.210.07:48:38.61#ibcon#about to read 5, iclass 18, count 2 2006.210.07:48:38.61#ibcon#read 5, iclass 18, count 2 2006.210.07:48:38.61#ibcon#about to read 6, iclass 18, count 2 2006.210.07:48:38.61#ibcon#read 6, iclass 18, count 2 2006.210.07:48:38.61#ibcon#end of sib2, iclass 18, count 2 2006.210.07:48:38.61#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:48:38.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:48:38.61#ibcon#[25=AT04-07\r\n] 2006.210.07:48:38.61#ibcon#*before write, iclass 18, count 2 2006.210.07:48:38.61#ibcon#enter sib2, iclass 18, count 2 2006.210.07:48:38.61#ibcon#flushed, iclass 18, count 2 2006.210.07:48:38.61#ibcon#about to write, iclass 18, count 2 2006.210.07:48:38.61#ibcon#wrote, iclass 18, count 2 2006.210.07:48:38.61#ibcon#about to read 3, iclass 18, count 2 2006.210.07:48:38.64#ibcon#read 3, iclass 18, count 2 2006.210.07:48:38.64#ibcon#about to read 4, iclass 18, count 2 2006.210.07:48:38.64#ibcon#read 4, iclass 18, count 2 2006.210.07:48:38.64#ibcon#about to read 5, iclass 18, count 2 2006.210.07:48:38.64#ibcon#read 5, iclass 18, count 2 2006.210.07:48:38.64#ibcon#about to read 6, iclass 18, count 2 2006.210.07:48:38.64#ibcon#read 6, iclass 18, count 2 2006.210.07:48:38.64#ibcon#end of sib2, iclass 18, count 2 2006.210.07:48:38.64#ibcon#*after write, iclass 18, count 2 2006.210.07:48:38.64#ibcon#*before return 0, iclass 18, count 2 2006.210.07:48:38.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:38.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:38.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:48:38.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:38.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:38.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:38.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:38.76#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:48:38.76#ibcon#first serial, iclass 18, count 0 2006.210.07:48:38.76#ibcon#enter sib2, iclass 18, count 0 2006.210.07:48:38.76#ibcon#flushed, iclass 18, count 0 2006.210.07:48:38.76#ibcon#about to write, iclass 18, count 0 2006.210.07:48:38.76#ibcon#wrote, iclass 18, count 0 2006.210.07:48:38.76#ibcon#about to read 3, iclass 18, count 0 2006.210.07:48:38.78#ibcon#read 3, iclass 18, count 0 2006.210.07:48:38.78#ibcon#about to read 4, iclass 18, count 0 2006.210.07:48:38.78#ibcon#read 4, iclass 18, count 0 2006.210.07:48:38.78#ibcon#about to read 5, iclass 18, count 0 2006.210.07:48:38.78#ibcon#read 5, iclass 18, count 0 2006.210.07:48:38.78#ibcon#about to read 6, iclass 18, count 0 2006.210.07:48:38.78#ibcon#read 6, iclass 18, count 0 2006.210.07:48:38.78#ibcon#end of sib2, iclass 18, count 0 2006.210.07:48:38.78#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:48:38.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:48:38.78#ibcon#[25=USB\r\n] 2006.210.07:48:38.78#ibcon#*before write, iclass 18, count 0 2006.210.07:48:38.78#ibcon#enter sib2, iclass 18, count 0 2006.210.07:48:38.78#ibcon#flushed, iclass 18, count 0 2006.210.07:48:38.78#ibcon#about to write, iclass 18, count 0 2006.210.07:48:38.78#ibcon#wrote, iclass 18, count 0 2006.210.07:48:38.78#ibcon#about to read 3, iclass 18, count 0 2006.210.07:48:38.81#ibcon#read 3, iclass 18, count 0 2006.210.07:48:38.81#ibcon#about to read 4, iclass 18, count 0 2006.210.07:48:38.81#ibcon#read 4, iclass 18, count 0 2006.210.07:48:38.81#ibcon#about to read 5, iclass 18, count 0 2006.210.07:48:38.81#ibcon#read 5, iclass 18, count 0 2006.210.07:48:38.81#ibcon#about to read 6, iclass 18, count 0 2006.210.07:48:38.81#ibcon#read 6, iclass 18, count 0 2006.210.07:48:38.81#ibcon#end of sib2, iclass 18, count 0 2006.210.07:48:38.81#ibcon#*after write, iclass 18, count 0 2006.210.07:48:38.81#ibcon#*before return 0, iclass 18, count 0 2006.210.07:48:38.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:38.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:38.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:48:38.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:48:38.81$vc4f8/valo=5,652.99 2006.210.07:48:38.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:48:38.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:48:38.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:38.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:38.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:38.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:38.81#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:48:38.81#ibcon#first serial, iclass 20, count 0 2006.210.07:48:38.81#ibcon#enter sib2, iclass 20, count 0 2006.210.07:48:38.81#ibcon#flushed, iclass 20, count 0 2006.210.07:48:38.81#ibcon#about to write, iclass 20, count 0 2006.210.07:48:38.81#ibcon#wrote, iclass 20, count 0 2006.210.07:48:38.81#ibcon#about to read 3, iclass 20, count 0 2006.210.07:48:38.83#ibcon#read 3, iclass 20, count 0 2006.210.07:48:38.83#ibcon#about to read 4, iclass 20, count 0 2006.210.07:48:38.83#ibcon#read 4, iclass 20, count 0 2006.210.07:48:38.83#ibcon#about to read 5, iclass 20, count 0 2006.210.07:48:38.83#ibcon#read 5, iclass 20, count 0 2006.210.07:48:38.83#ibcon#about to read 6, iclass 20, count 0 2006.210.07:48:38.83#ibcon#read 6, iclass 20, count 0 2006.210.07:48:38.83#ibcon#end of sib2, iclass 20, count 0 2006.210.07:48:38.83#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:48:38.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:48:38.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:48:38.83#ibcon#*before write, iclass 20, count 0 2006.210.07:48:38.83#ibcon#enter sib2, iclass 20, count 0 2006.210.07:48:38.83#ibcon#flushed, iclass 20, count 0 2006.210.07:48:38.83#ibcon#about to write, iclass 20, count 0 2006.210.07:48:38.83#ibcon#wrote, iclass 20, count 0 2006.210.07:48:38.83#ibcon#about to read 3, iclass 20, count 0 2006.210.07:48:38.87#ibcon#read 3, iclass 20, count 0 2006.210.07:48:38.87#ibcon#about to read 4, iclass 20, count 0 2006.210.07:48:38.87#ibcon#read 4, iclass 20, count 0 2006.210.07:48:38.87#ibcon#about to read 5, iclass 20, count 0 2006.210.07:48:38.87#ibcon#read 5, iclass 20, count 0 2006.210.07:48:38.87#ibcon#about to read 6, iclass 20, count 0 2006.210.07:48:38.87#ibcon#read 6, iclass 20, count 0 2006.210.07:48:38.87#ibcon#end of sib2, iclass 20, count 0 2006.210.07:48:38.87#ibcon#*after write, iclass 20, count 0 2006.210.07:48:38.87#ibcon#*before return 0, iclass 20, count 0 2006.210.07:48:38.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:38.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:38.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:48:38.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:48:38.87$vc4f8/va=5,7 2006.210.07:48:38.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:48:38.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:48:38.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:38.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:38.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:38.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:38.93#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:48:38.93#ibcon#first serial, iclass 22, count 2 2006.210.07:48:38.93#ibcon#enter sib2, iclass 22, count 2 2006.210.07:48:38.93#ibcon#flushed, iclass 22, count 2 2006.210.07:48:38.93#ibcon#about to write, iclass 22, count 2 2006.210.07:48:38.93#ibcon#wrote, iclass 22, count 2 2006.210.07:48:38.93#ibcon#about to read 3, iclass 22, count 2 2006.210.07:48:38.95#ibcon#read 3, iclass 22, count 2 2006.210.07:48:38.95#ibcon#about to read 4, iclass 22, count 2 2006.210.07:48:38.95#ibcon#read 4, iclass 22, count 2 2006.210.07:48:38.95#ibcon#about to read 5, iclass 22, count 2 2006.210.07:48:38.95#ibcon#read 5, iclass 22, count 2 2006.210.07:48:38.95#ibcon#about to read 6, iclass 22, count 2 2006.210.07:48:38.95#ibcon#read 6, iclass 22, count 2 2006.210.07:48:38.95#ibcon#end of sib2, iclass 22, count 2 2006.210.07:48:38.95#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:48:38.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:48:38.95#ibcon#[25=AT05-07\r\n] 2006.210.07:48:38.95#ibcon#*before write, iclass 22, count 2 2006.210.07:48:38.95#ibcon#enter sib2, iclass 22, count 2 2006.210.07:48:38.95#ibcon#flushed, iclass 22, count 2 2006.210.07:48:38.95#ibcon#about to write, iclass 22, count 2 2006.210.07:48:38.95#ibcon#wrote, iclass 22, count 2 2006.210.07:48:38.95#ibcon#about to read 3, iclass 22, count 2 2006.210.07:48:38.98#ibcon#read 3, iclass 22, count 2 2006.210.07:48:38.98#ibcon#about to read 4, iclass 22, count 2 2006.210.07:48:38.98#ibcon#read 4, iclass 22, count 2 2006.210.07:48:38.98#ibcon#about to read 5, iclass 22, count 2 2006.210.07:48:38.98#ibcon#read 5, iclass 22, count 2 2006.210.07:48:38.98#ibcon#about to read 6, iclass 22, count 2 2006.210.07:48:38.98#ibcon#read 6, iclass 22, count 2 2006.210.07:48:38.98#ibcon#end of sib2, iclass 22, count 2 2006.210.07:48:38.98#ibcon#*after write, iclass 22, count 2 2006.210.07:48:38.98#ibcon#*before return 0, iclass 22, count 2 2006.210.07:48:38.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:38.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:38.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:48:38.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:38.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:39.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:39.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:39.10#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:48:39.10#ibcon#first serial, iclass 22, count 0 2006.210.07:48:39.10#ibcon#enter sib2, iclass 22, count 0 2006.210.07:48:39.10#ibcon#flushed, iclass 22, count 0 2006.210.07:48:39.10#ibcon#about to write, iclass 22, count 0 2006.210.07:48:39.10#ibcon#wrote, iclass 22, count 0 2006.210.07:48:39.10#ibcon#about to read 3, iclass 22, count 0 2006.210.07:48:39.12#ibcon#read 3, iclass 22, count 0 2006.210.07:48:39.12#ibcon#about to read 4, iclass 22, count 0 2006.210.07:48:39.12#ibcon#read 4, iclass 22, count 0 2006.210.07:48:39.12#ibcon#about to read 5, iclass 22, count 0 2006.210.07:48:39.12#ibcon#read 5, iclass 22, count 0 2006.210.07:48:39.12#ibcon#about to read 6, iclass 22, count 0 2006.210.07:48:39.12#ibcon#read 6, iclass 22, count 0 2006.210.07:48:39.12#ibcon#end of sib2, iclass 22, count 0 2006.210.07:48:39.12#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:48:39.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:48:39.12#ibcon#[25=USB\r\n] 2006.210.07:48:39.12#ibcon#*before write, iclass 22, count 0 2006.210.07:48:39.12#ibcon#enter sib2, iclass 22, count 0 2006.210.07:48:39.12#ibcon#flushed, iclass 22, count 0 2006.210.07:48:39.12#ibcon#about to write, iclass 22, count 0 2006.210.07:48:39.12#ibcon#wrote, iclass 22, count 0 2006.210.07:48:39.12#ibcon#about to read 3, iclass 22, count 0 2006.210.07:48:39.15#ibcon#read 3, iclass 22, count 0 2006.210.07:48:39.15#ibcon#about to read 4, iclass 22, count 0 2006.210.07:48:39.15#ibcon#read 4, iclass 22, count 0 2006.210.07:48:39.15#ibcon#about to read 5, iclass 22, count 0 2006.210.07:48:39.15#ibcon#read 5, iclass 22, count 0 2006.210.07:48:39.15#ibcon#about to read 6, iclass 22, count 0 2006.210.07:48:39.15#ibcon#read 6, iclass 22, count 0 2006.210.07:48:39.15#ibcon#end of sib2, iclass 22, count 0 2006.210.07:48:39.15#ibcon#*after write, iclass 22, count 0 2006.210.07:48:39.15#ibcon#*before return 0, iclass 22, count 0 2006.210.07:48:39.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:39.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:39.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:48:39.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:48:39.15$vc4f8/valo=6,772.99 2006.210.07:48:39.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:48:39.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:48:39.15#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:39.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:39.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:39.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:39.15#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:48:39.15#ibcon#first serial, iclass 24, count 0 2006.210.07:48:39.15#ibcon#enter sib2, iclass 24, count 0 2006.210.07:48:39.15#ibcon#flushed, iclass 24, count 0 2006.210.07:48:39.15#ibcon#about to write, iclass 24, count 0 2006.210.07:48:39.15#ibcon#wrote, iclass 24, count 0 2006.210.07:48:39.15#ibcon#about to read 3, iclass 24, count 0 2006.210.07:48:39.17#ibcon#read 3, iclass 24, count 0 2006.210.07:48:39.17#ibcon#about to read 4, iclass 24, count 0 2006.210.07:48:39.17#ibcon#read 4, iclass 24, count 0 2006.210.07:48:39.17#ibcon#about to read 5, iclass 24, count 0 2006.210.07:48:39.17#ibcon#read 5, iclass 24, count 0 2006.210.07:48:39.17#ibcon#about to read 6, iclass 24, count 0 2006.210.07:48:39.17#ibcon#read 6, iclass 24, count 0 2006.210.07:48:39.17#ibcon#end of sib2, iclass 24, count 0 2006.210.07:48:39.17#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:48:39.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:48:39.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:48:39.17#ibcon#*before write, iclass 24, count 0 2006.210.07:48:39.17#ibcon#enter sib2, iclass 24, count 0 2006.210.07:48:39.17#ibcon#flushed, iclass 24, count 0 2006.210.07:48:39.17#ibcon#about to write, iclass 24, count 0 2006.210.07:48:39.17#ibcon#wrote, iclass 24, count 0 2006.210.07:48:39.17#ibcon#about to read 3, iclass 24, count 0 2006.210.07:48:39.21#ibcon#read 3, iclass 24, count 0 2006.210.07:48:39.21#ibcon#about to read 4, iclass 24, count 0 2006.210.07:48:39.21#ibcon#read 4, iclass 24, count 0 2006.210.07:48:39.21#ibcon#about to read 5, iclass 24, count 0 2006.210.07:48:39.21#ibcon#read 5, iclass 24, count 0 2006.210.07:48:39.21#ibcon#about to read 6, iclass 24, count 0 2006.210.07:48:39.21#ibcon#read 6, iclass 24, count 0 2006.210.07:48:39.21#ibcon#end of sib2, iclass 24, count 0 2006.210.07:48:39.21#ibcon#*after write, iclass 24, count 0 2006.210.07:48:39.21#ibcon#*before return 0, iclass 24, count 0 2006.210.07:48:39.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:39.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:39.21#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:48:39.21#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:48:39.21$vc4f8/va=6,6 2006.210.07:48:39.21#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:48:39.21#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:48:39.21#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:39.21#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:48:39.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:48:39.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:48:39.27#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:48:39.27#ibcon#first serial, iclass 26, count 2 2006.210.07:48:39.27#ibcon#enter sib2, iclass 26, count 2 2006.210.07:48:39.27#ibcon#flushed, iclass 26, count 2 2006.210.07:48:39.27#ibcon#about to write, iclass 26, count 2 2006.210.07:48:39.27#ibcon#wrote, iclass 26, count 2 2006.210.07:48:39.27#ibcon#about to read 3, iclass 26, count 2 2006.210.07:48:39.29#ibcon#read 3, iclass 26, count 2 2006.210.07:48:39.29#ibcon#about to read 4, iclass 26, count 2 2006.210.07:48:39.29#ibcon#read 4, iclass 26, count 2 2006.210.07:48:39.29#ibcon#about to read 5, iclass 26, count 2 2006.210.07:48:39.29#ibcon#read 5, iclass 26, count 2 2006.210.07:48:39.29#ibcon#about to read 6, iclass 26, count 2 2006.210.07:48:39.29#ibcon#read 6, iclass 26, count 2 2006.210.07:48:39.29#ibcon#end of sib2, iclass 26, count 2 2006.210.07:48:39.29#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:48:39.29#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:48:39.29#ibcon#[25=AT06-06\r\n] 2006.210.07:48:39.29#ibcon#*before write, iclass 26, count 2 2006.210.07:48:39.29#ibcon#enter sib2, iclass 26, count 2 2006.210.07:48:39.29#ibcon#flushed, iclass 26, count 2 2006.210.07:48:39.29#ibcon#about to write, iclass 26, count 2 2006.210.07:48:39.29#ibcon#wrote, iclass 26, count 2 2006.210.07:48:39.29#ibcon#about to read 3, iclass 26, count 2 2006.210.07:48:39.32#ibcon#read 3, iclass 26, count 2 2006.210.07:48:39.32#ibcon#about to read 4, iclass 26, count 2 2006.210.07:48:39.32#ibcon#read 4, iclass 26, count 2 2006.210.07:48:39.32#ibcon#about to read 5, iclass 26, count 2 2006.210.07:48:39.32#ibcon#read 5, iclass 26, count 2 2006.210.07:48:39.32#ibcon#about to read 6, iclass 26, count 2 2006.210.07:48:39.32#ibcon#read 6, iclass 26, count 2 2006.210.07:48:39.32#ibcon#end of sib2, iclass 26, count 2 2006.210.07:48:39.32#ibcon#*after write, iclass 26, count 2 2006.210.07:48:39.32#ibcon#*before return 0, iclass 26, count 2 2006.210.07:48:39.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:48:39.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:48:39.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:48:39.32#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:39.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:48:39.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:48:39.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:48:39.44#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:48:39.44#ibcon#first serial, iclass 26, count 0 2006.210.07:48:39.44#ibcon#enter sib2, iclass 26, count 0 2006.210.07:48:39.44#ibcon#flushed, iclass 26, count 0 2006.210.07:48:39.44#ibcon#about to write, iclass 26, count 0 2006.210.07:48:39.44#ibcon#wrote, iclass 26, count 0 2006.210.07:48:39.44#ibcon#about to read 3, iclass 26, count 0 2006.210.07:48:39.46#ibcon#read 3, iclass 26, count 0 2006.210.07:48:39.46#ibcon#about to read 4, iclass 26, count 0 2006.210.07:48:39.46#ibcon#read 4, iclass 26, count 0 2006.210.07:48:39.46#ibcon#about to read 5, iclass 26, count 0 2006.210.07:48:39.46#ibcon#read 5, iclass 26, count 0 2006.210.07:48:39.46#ibcon#about to read 6, iclass 26, count 0 2006.210.07:48:39.46#ibcon#read 6, iclass 26, count 0 2006.210.07:48:39.46#ibcon#end of sib2, iclass 26, count 0 2006.210.07:48:39.46#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:48:39.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:48:39.46#ibcon#[25=USB\r\n] 2006.210.07:48:39.46#ibcon#*before write, iclass 26, count 0 2006.210.07:48:39.46#ibcon#enter sib2, iclass 26, count 0 2006.210.07:48:39.46#ibcon#flushed, iclass 26, count 0 2006.210.07:48:39.46#ibcon#about to write, iclass 26, count 0 2006.210.07:48:39.46#ibcon#wrote, iclass 26, count 0 2006.210.07:48:39.46#ibcon#about to read 3, iclass 26, count 0 2006.210.07:48:39.49#ibcon#read 3, iclass 26, count 0 2006.210.07:48:39.49#ibcon#about to read 4, iclass 26, count 0 2006.210.07:48:39.49#ibcon#read 4, iclass 26, count 0 2006.210.07:48:39.49#ibcon#about to read 5, iclass 26, count 0 2006.210.07:48:39.49#ibcon#read 5, iclass 26, count 0 2006.210.07:48:39.49#ibcon#about to read 6, iclass 26, count 0 2006.210.07:48:39.49#ibcon#read 6, iclass 26, count 0 2006.210.07:48:39.49#ibcon#end of sib2, iclass 26, count 0 2006.210.07:48:39.49#ibcon#*after write, iclass 26, count 0 2006.210.07:48:39.49#ibcon#*before return 0, iclass 26, count 0 2006.210.07:48:39.49#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:48:39.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:48:39.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:48:39.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:48:39.49$vc4f8/valo=7,832.99 2006.210.07:48:39.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:48:39.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:48:39.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:39.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:48:39.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:48:39.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:48:39.49#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:48:39.49#ibcon#first serial, iclass 28, count 0 2006.210.07:48:39.49#ibcon#enter sib2, iclass 28, count 0 2006.210.07:48:39.49#ibcon#flushed, iclass 28, count 0 2006.210.07:48:39.49#ibcon#about to write, iclass 28, count 0 2006.210.07:48:39.49#ibcon#wrote, iclass 28, count 0 2006.210.07:48:39.49#ibcon#about to read 3, iclass 28, count 0 2006.210.07:48:39.51#ibcon#read 3, iclass 28, count 0 2006.210.07:48:39.51#ibcon#about to read 4, iclass 28, count 0 2006.210.07:48:39.51#ibcon#read 4, iclass 28, count 0 2006.210.07:48:39.51#ibcon#about to read 5, iclass 28, count 0 2006.210.07:48:39.51#ibcon#read 5, iclass 28, count 0 2006.210.07:48:39.51#ibcon#about to read 6, iclass 28, count 0 2006.210.07:48:39.51#ibcon#read 6, iclass 28, count 0 2006.210.07:48:39.51#ibcon#end of sib2, iclass 28, count 0 2006.210.07:48:39.51#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:48:39.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:48:39.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:48:39.51#ibcon#*before write, iclass 28, count 0 2006.210.07:48:39.51#ibcon#enter sib2, iclass 28, count 0 2006.210.07:48:39.51#ibcon#flushed, iclass 28, count 0 2006.210.07:48:39.51#ibcon#about to write, iclass 28, count 0 2006.210.07:48:39.51#ibcon#wrote, iclass 28, count 0 2006.210.07:48:39.51#ibcon#about to read 3, iclass 28, count 0 2006.210.07:48:39.55#ibcon#read 3, iclass 28, count 0 2006.210.07:48:39.55#ibcon#about to read 4, iclass 28, count 0 2006.210.07:48:39.55#ibcon#read 4, iclass 28, count 0 2006.210.07:48:39.55#ibcon#about to read 5, iclass 28, count 0 2006.210.07:48:39.55#ibcon#read 5, iclass 28, count 0 2006.210.07:48:39.55#ibcon#about to read 6, iclass 28, count 0 2006.210.07:48:39.55#ibcon#read 6, iclass 28, count 0 2006.210.07:48:39.55#ibcon#end of sib2, iclass 28, count 0 2006.210.07:48:39.55#ibcon#*after write, iclass 28, count 0 2006.210.07:48:39.55#ibcon#*before return 0, iclass 28, count 0 2006.210.07:48:39.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:48:39.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:48:39.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:48:39.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:48:39.55$vc4f8/va=7,6 2006.210.07:48:39.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:48:39.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:48:39.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:39.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:48:39.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:48:39.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:48:39.61#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:48:39.61#ibcon#first serial, iclass 30, count 2 2006.210.07:48:39.61#ibcon#enter sib2, iclass 30, count 2 2006.210.07:48:39.61#ibcon#flushed, iclass 30, count 2 2006.210.07:48:39.61#ibcon#about to write, iclass 30, count 2 2006.210.07:48:39.61#ibcon#wrote, iclass 30, count 2 2006.210.07:48:39.61#ibcon#about to read 3, iclass 30, count 2 2006.210.07:48:39.63#ibcon#read 3, iclass 30, count 2 2006.210.07:48:39.63#ibcon#about to read 4, iclass 30, count 2 2006.210.07:48:39.63#ibcon#read 4, iclass 30, count 2 2006.210.07:48:39.63#ibcon#about to read 5, iclass 30, count 2 2006.210.07:48:39.63#ibcon#read 5, iclass 30, count 2 2006.210.07:48:39.63#ibcon#about to read 6, iclass 30, count 2 2006.210.07:48:39.63#ibcon#read 6, iclass 30, count 2 2006.210.07:48:39.63#ibcon#end of sib2, iclass 30, count 2 2006.210.07:48:39.63#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:48:39.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:48:39.63#ibcon#[25=AT07-06\r\n] 2006.210.07:48:39.63#ibcon#*before write, iclass 30, count 2 2006.210.07:48:39.63#ibcon#enter sib2, iclass 30, count 2 2006.210.07:48:39.63#ibcon#flushed, iclass 30, count 2 2006.210.07:48:39.63#ibcon#about to write, iclass 30, count 2 2006.210.07:48:39.63#ibcon#wrote, iclass 30, count 2 2006.210.07:48:39.63#ibcon#about to read 3, iclass 30, count 2 2006.210.07:48:39.66#ibcon#read 3, iclass 30, count 2 2006.210.07:48:39.66#ibcon#about to read 4, iclass 30, count 2 2006.210.07:48:39.66#ibcon#read 4, iclass 30, count 2 2006.210.07:48:39.66#ibcon#about to read 5, iclass 30, count 2 2006.210.07:48:39.66#ibcon#read 5, iclass 30, count 2 2006.210.07:48:39.66#ibcon#about to read 6, iclass 30, count 2 2006.210.07:48:39.66#ibcon#read 6, iclass 30, count 2 2006.210.07:48:39.66#ibcon#end of sib2, iclass 30, count 2 2006.210.07:48:39.66#ibcon#*after write, iclass 30, count 2 2006.210.07:48:39.66#ibcon#*before return 0, iclass 30, count 2 2006.210.07:48:39.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:48:39.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:48:39.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:48:39.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:39.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:48:39.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:48:39.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:48:39.78#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:48:39.78#ibcon#first serial, iclass 30, count 0 2006.210.07:48:39.78#ibcon#enter sib2, iclass 30, count 0 2006.210.07:48:39.78#ibcon#flushed, iclass 30, count 0 2006.210.07:48:39.78#ibcon#about to write, iclass 30, count 0 2006.210.07:48:39.78#ibcon#wrote, iclass 30, count 0 2006.210.07:48:39.78#ibcon#about to read 3, iclass 30, count 0 2006.210.07:48:39.80#ibcon#read 3, iclass 30, count 0 2006.210.07:48:39.80#ibcon#about to read 4, iclass 30, count 0 2006.210.07:48:39.80#ibcon#read 4, iclass 30, count 0 2006.210.07:48:39.80#ibcon#about to read 5, iclass 30, count 0 2006.210.07:48:39.80#ibcon#read 5, iclass 30, count 0 2006.210.07:48:39.80#ibcon#about to read 6, iclass 30, count 0 2006.210.07:48:39.80#ibcon#read 6, iclass 30, count 0 2006.210.07:48:39.80#ibcon#end of sib2, iclass 30, count 0 2006.210.07:48:39.80#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:48:39.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:48:39.80#ibcon#[25=USB\r\n] 2006.210.07:48:39.80#ibcon#*before write, iclass 30, count 0 2006.210.07:48:39.80#ibcon#enter sib2, iclass 30, count 0 2006.210.07:48:39.80#ibcon#flushed, iclass 30, count 0 2006.210.07:48:39.80#ibcon#about to write, iclass 30, count 0 2006.210.07:48:39.80#ibcon#wrote, iclass 30, count 0 2006.210.07:48:39.80#ibcon#about to read 3, iclass 30, count 0 2006.210.07:48:39.83#ibcon#read 3, iclass 30, count 0 2006.210.07:48:39.83#ibcon#about to read 4, iclass 30, count 0 2006.210.07:48:39.83#ibcon#read 4, iclass 30, count 0 2006.210.07:48:39.83#ibcon#about to read 5, iclass 30, count 0 2006.210.07:48:39.83#ibcon#read 5, iclass 30, count 0 2006.210.07:48:39.83#ibcon#about to read 6, iclass 30, count 0 2006.210.07:48:39.83#ibcon#read 6, iclass 30, count 0 2006.210.07:48:39.83#ibcon#end of sib2, iclass 30, count 0 2006.210.07:48:39.83#ibcon#*after write, iclass 30, count 0 2006.210.07:48:39.83#ibcon#*before return 0, iclass 30, count 0 2006.210.07:48:39.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:48:39.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:48:39.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:48:39.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:48:39.83$vc4f8/valo=8,852.99 2006.210.07:48:39.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:48:39.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:48:39.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:39.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:48:39.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:48:39.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:48:39.83#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:48:39.83#ibcon#first serial, iclass 32, count 0 2006.210.07:48:39.83#ibcon#enter sib2, iclass 32, count 0 2006.210.07:48:39.83#ibcon#flushed, iclass 32, count 0 2006.210.07:48:39.83#ibcon#about to write, iclass 32, count 0 2006.210.07:48:39.83#ibcon#wrote, iclass 32, count 0 2006.210.07:48:39.83#ibcon#about to read 3, iclass 32, count 0 2006.210.07:48:39.85#ibcon#read 3, iclass 32, count 0 2006.210.07:48:39.85#ibcon#about to read 4, iclass 32, count 0 2006.210.07:48:39.85#ibcon#read 4, iclass 32, count 0 2006.210.07:48:39.85#ibcon#about to read 5, iclass 32, count 0 2006.210.07:48:39.85#ibcon#read 5, iclass 32, count 0 2006.210.07:48:39.85#ibcon#about to read 6, iclass 32, count 0 2006.210.07:48:39.85#ibcon#read 6, iclass 32, count 0 2006.210.07:48:39.85#ibcon#end of sib2, iclass 32, count 0 2006.210.07:48:39.85#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:48:39.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:48:39.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:48:39.85#ibcon#*before write, iclass 32, count 0 2006.210.07:48:39.85#ibcon#enter sib2, iclass 32, count 0 2006.210.07:48:39.85#ibcon#flushed, iclass 32, count 0 2006.210.07:48:39.85#ibcon#about to write, iclass 32, count 0 2006.210.07:48:39.85#ibcon#wrote, iclass 32, count 0 2006.210.07:48:39.85#ibcon#about to read 3, iclass 32, count 0 2006.210.07:48:39.89#ibcon#read 3, iclass 32, count 0 2006.210.07:48:39.89#ibcon#about to read 4, iclass 32, count 0 2006.210.07:48:39.89#ibcon#read 4, iclass 32, count 0 2006.210.07:48:39.89#ibcon#about to read 5, iclass 32, count 0 2006.210.07:48:39.89#ibcon#read 5, iclass 32, count 0 2006.210.07:48:39.89#ibcon#about to read 6, iclass 32, count 0 2006.210.07:48:39.89#ibcon#read 6, iclass 32, count 0 2006.210.07:48:39.89#ibcon#end of sib2, iclass 32, count 0 2006.210.07:48:39.89#ibcon#*after write, iclass 32, count 0 2006.210.07:48:39.89#ibcon#*before return 0, iclass 32, count 0 2006.210.07:48:39.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:48:39.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:48:39.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:48:39.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:48:39.89$vc4f8/va=8,7 2006.210.07:48:39.89#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:48:39.89#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:48:39.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:39.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:48:39.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:48:39.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:48:39.95#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:48:39.95#ibcon#first serial, iclass 34, count 2 2006.210.07:48:39.95#ibcon#enter sib2, iclass 34, count 2 2006.210.07:48:39.95#ibcon#flushed, iclass 34, count 2 2006.210.07:48:39.95#ibcon#about to write, iclass 34, count 2 2006.210.07:48:39.95#ibcon#wrote, iclass 34, count 2 2006.210.07:48:39.95#ibcon#about to read 3, iclass 34, count 2 2006.210.07:48:39.97#ibcon#read 3, iclass 34, count 2 2006.210.07:48:39.97#ibcon#about to read 4, iclass 34, count 2 2006.210.07:48:39.97#ibcon#read 4, iclass 34, count 2 2006.210.07:48:39.97#ibcon#about to read 5, iclass 34, count 2 2006.210.07:48:39.97#ibcon#read 5, iclass 34, count 2 2006.210.07:48:39.97#ibcon#about to read 6, iclass 34, count 2 2006.210.07:48:39.97#ibcon#read 6, iclass 34, count 2 2006.210.07:48:39.97#ibcon#end of sib2, iclass 34, count 2 2006.210.07:48:39.97#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:48:39.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:48:39.97#ibcon#[25=AT08-07\r\n] 2006.210.07:48:39.97#ibcon#*before write, iclass 34, count 2 2006.210.07:48:39.97#ibcon#enter sib2, iclass 34, count 2 2006.210.07:48:39.97#ibcon#flushed, iclass 34, count 2 2006.210.07:48:39.97#ibcon#about to write, iclass 34, count 2 2006.210.07:48:39.97#ibcon#wrote, iclass 34, count 2 2006.210.07:48:39.97#ibcon#about to read 3, iclass 34, count 2 2006.210.07:48:40.00#ibcon#read 3, iclass 34, count 2 2006.210.07:48:40.00#ibcon#about to read 4, iclass 34, count 2 2006.210.07:48:40.00#ibcon#read 4, iclass 34, count 2 2006.210.07:48:40.00#ibcon#about to read 5, iclass 34, count 2 2006.210.07:48:40.00#ibcon#read 5, iclass 34, count 2 2006.210.07:48:40.00#ibcon#about to read 6, iclass 34, count 2 2006.210.07:48:40.00#ibcon#read 6, iclass 34, count 2 2006.210.07:48:40.00#ibcon#end of sib2, iclass 34, count 2 2006.210.07:48:40.00#ibcon#*after write, iclass 34, count 2 2006.210.07:48:40.00#ibcon#*before return 0, iclass 34, count 2 2006.210.07:48:40.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:48:40.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:48:40.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:48:40.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:40.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:48:40.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:48:40.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:48:40.12#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:48:40.12#ibcon#first serial, iclass 34, count 0 2006.210.07:48:40.12#ibcon#enter sib2, iclass 34, count 0 2006.210.07:48:40.12#ibcon#flushed, iclass 34, count 0 2006.210.07:48:40.12#ibcon#about to write, iclass 34, count 0 2006.210.07:48:40.12#ibcon#wrote, iclass 34, count 0 2006.210.07:48:40.12#ibcon#about to read 3, iclass 34, count 0 2006.210.07:48:40.14#ibcon#read 3, iclass 34, count 0 2006.210.07:48:40.14#ibcon#about to read 4, iclass 34, count 0 2006.210.07:48:40.14#ibcon#read 4, iclass 34, count 0 2006.210.07:48:40.14#ibcon#about to read 5, iclass 34, count 0 2006.210.07:48:40.14#ibcon#read 5, iclass 34, count 0 2006.210.07:48:40.14#ibcon#about to read 6, iclass 34, count 0 2006.210.07:48:40.14#ibcon#read 6, iclass 34, count 0 2006.210.07:48:40.14#ibcon#end of sib2, iclass 34, count 0 2006.210.07:48:40.14#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:48:40.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:48:40.14#ibcon#[25=USB\r\n] 2006.210.07:48:40.14#ibcon#*before write, iclass 34, count 0 2006.210.07:48:40.14#ibcon#enter sib2, iclass 34, count 0 2006.210.07:48:40.14#ibcon#flushed, iclass 34, count 0 2006.210.07:48:40.14#ibcon#about to write, iclass 34, count 0 2006.210.07:48:40.14#ibcon#wrote, iclass 34, count 0 2006.210.07:48:40.14#ibcon#about to read 3, iclass 34, count 0 2006.210.07:48:40.17#ibcon#read 3, iclass 34, count 0 2006.210.07:48:40.17#ibcon#about to read 4, iclass 34, count 0 2006.210.07:48:40.17#ibcon#read 4, iclass 34, count 0 2006.210.07:48:40.17#ibcon#about to read 5, iclass 34, count 0 2006.210.07:48:40.17#ibcon#read 5, iclass 34, count 0 2006.210.07:48:40.17#ibcon#about to read 6, iclass 34, count 0 2006.210.07:48:40.17#ibcon#read 6, iclass 34, count 0 2006.210.07:48:40.17#ibcon#end of sib2, iclass 34, count 0 2006.210.07:48:40.17#ibcon#*after write, iclass 34, count 0 2006.210.07:48:40.17#ibcon#*before return 0, iclass 34, count 0 2006.210.07:48:40.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:48:40.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:48:40.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:48:40.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:48:40.17$vc4f8/vblo=1,632.99 2006.210.07:48:40.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:48:40.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:48:40.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:40.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:48:40.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:48:40.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:48:40.17#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:48:40.17#ibcon#first serial, iclass 36, count 0 2006.210.07:48:40.17#ibcon#enter sib2, iclass 36, count 0 2006.210.07:48:40.17#ibcon#flushed, iclass 36, count 0 2006.210.07:48:40.17#ibcon#about to write, iclass 36, count 0 2006.210.07:48:40.17#ibcon#wrote, iclass 36, count 0 2006.210.07:48:40.17#ibcon#about to read 3, iclass 36, count 0 2006.210.07:48:40.19#ibcon#read 3, iclass 36, count 0 2006.210.07:48:40.19#ibcon#about to read 4, iclass 36, count 0 2006.210.07:48:40.19#ibcon#read 4, iclass 36, count 0 2006.210.07:48:40.19#ibcon#about to read 5, iclass 36, count 0 2006.210.07:48:40.19#ibcon#read 5, iclass 36, count 0 2006.210.07:48:40.19#ibcon#about to read 6, iclass 36, count 0 2006.210.07:48:40.19#ibcon#read 6, iclass 36, count 0 2006.210.07:48:40.19#ibcon#end of sib2, iclass 36, count 0 2006.210.07:48:40.19#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:48:40.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:48:40.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:48:40.19#ibcon#*before write, iclass 36, count 0 2006.210.07:48:40.19#ibcon#enter sib2, iclass 36, count 0 2006.210.07:48:40.19#ibcon#flushed, iclass 36, count 0 2006.210.07:48:40.19#ibcon#about to write, iclass 36, count 0 2006.210.07:48:40.19#ibcon#wrote, iclass 36, count 0 2006.210.07:48:40.19#ibcon#about to read 3, iclass 36, count 0 2006.210.07:48:40.23#ibcon#read 3, iclass 36, count 0 2006.210.07:48:40.23#ibcon#about to read 4, iclass 36, count 0 2006.210.07:48:40.23#ibcon#read 4, iclass 36, count 0 2006.210.07:48:40.23#ibcon#about to read 5, iclass 36, count 0 2006.210.07:48:40.23#ibcon#read 5, iclass 36, count 0 2006.210.07:48:40.23#ibcon#about to read 6, iclass 36, count 0 2006.210.07:48:40.23#ibcon#read 6, iclass 36, count 0 2006.210.07:48:40.23#ibcon#end of sib2, iclass 36, count 0 2006.210.07:48:40.23#ibcon#*after write, iclass 36, count 0 2006.210.07:48:40.23#ibcon#*before return 0, iclass 36, count 0 2006.210.07:48:40.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:48:40.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:48:40.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:48:40.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:48:40.23$vc4f8/vb=1,4 2006.210.07:48:40.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:48:40.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:48:40.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:40.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:48:40.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:48:40.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:48:40.23#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:48:40.23#ibcon#first serial, iclass 38, count 2 2006.210.07:48:40.23#ibcon#enter sib2, iclass 38, count 2 2006.210.07:48:40.23#ibcon#flushed, iclass 38, count 2 2006.210.07:48:40.23#ibcon#about to write, iclass 38, count 2 2006.210.07:48:40.23#ibcon#wrote, iclass 38, count 2 2006.210.07:48:40.23#ibcon#about to read 3, iclass 38, count 2 2006.210.07:48:40.25#ibcon#read 3, iclass 38, count 2 2006.210.07:48:40.25#ibcon#about to read 4, iclass 38, count 2 2006.210.07:48:40.25#ibcon#read 4, iclass 38, count 2 2006.210.07:48:40.25#ibcon#about to read 5, iclass 38, count 2 2006.210.07:48:40.25#ibcon#read 5, iclass 38, count 2 2006.210.07:48:40.25#ibcon#about to read 6, iclass 38, count 2 2006.210.07:48:40.25#ibcon#read 6, iclass 38, count 2 2006.210.07:48:40.25#ibcon#end of sib2, iclass 38, count 2 2006.210.07:48:40.25#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:48:40.25#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:48:40.25#ibcon#[27=AT01-04\r\n] 2006.210.07:48:40.25#ibcon#*before write, iclass 38, count 2 2006.210.07:48:40.25#ibcon#enter sib2, iclass 38, count 2 2006.210.07:48:40.25#ibcon#flushed, iclass 38, count 2 2006.210.07:48:40.25#ibcon#about to write, iclass 38, count 2 2006.210.07:48:40.25#ibcon#wrote, iclass 38, count 2 2006.210.07:48:40.25#ibcon#about to read 3, iclass 38, count 2 2006.210.07:48:40.28#ibcon#read 3, iclass 38, count 2 2006.210.07:48:40.28#ibcon#about to read 4, iclass 38, count 2 2006.210.07:48:40.28#ibcon#read 4, iclass 38, count 2 2006.210.07:48:40.28#ibcon#about to read 5, iclass 38, count 2 2006.210.07:48:40.28#ibcon#read 5, iclass 38, count 2 2006.210.07:48:40.28#ibcon#about to read 6, iclass 38, count 2 2006.210.07:48:40.28#ibcon#read 6, iclass 38, count 2 2006.210.07:48:40.28#ibcon#end of sib2, iclass 38, count 2 2006.210.07:48:40.28#ibcon#*after write, iclass 38, count 2 2006.210.07:48:40.28#ibcon#*before return 0, iclass 38, count 2 2006.210.07:48:40.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:48:40.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:48:40.28#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:48:40.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:40.28#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:48:40.40#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:48:40.40#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:48:40.40#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:48:40.40#ibcon#first serial, iclass 38, count 0 2006.210.07:48:40.40#ibcon#enter sib2, iclass 38, count 0 2006.210.07:48:40.40#ibcon#flushed, iclass 38, count 0 2006.210.07:48:40.40#ibcon#about to write, iclass 38, count 0 2006.210.07:48:40.40#ibcon#wrote, iclass 38, count 0 2006.210.07:48:40.40#ibcon#about to read 3, iclass 38, count 0 2006.210.07:48:40.42#ibcon#read 3, iclass 38, count 0 2006.210.07:48:40.42#ibcon#about to read 4, iclass 38, count 0 2006.210.07:48:40.42#ibcon#read 4, iclass 38, count 0 2006.210.07:48:40.42#ibcon#about to read 5, iclass 38, count 0 2006.210.07:48:40.42#ibcon#read 5, iclass 38, count 0 2006.210.07:48:40.42#ibcon#about to read 6, iclass 38, count 0 2006.210.07:48:40.42#ibcon#read 6, iclass 38, count 0 2006.210.07:48:40.42#ibcon#end of sib2, iclass 38, count 0 2006.210.07:48:40.42#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:48:40.42#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:48:40.42#ibcon#[27=USB\r\n] 2006.210.07:48:40.42#ibcon#*before write, iclass 38, count 0 2006.210.07:48:40.42#ibcon#enter sib2, iclass 38, count 0 2006.210.07:48:40.42#ibcon#flushed, iclass 38, count 0 2006.210.07:48:40.42#ibcon#about to write, iclass 38, count 0 2006.210.07:48:40.42#ibcon#wrote, iclass 38, count 0 2006.210.07:48:40.42#ibcon#about to read 3, iclass 38, count 0 2006.210.07:48:40.45#ibcon#read 3, iclass 38, count 0 2006.210.07:48:40.45#ibcon#about to read 4, iclass 38, count 0 2006.210.07:48:40.45#ibcon#read 4, iclass 38, count 0 2006.210.07:48:40.45#ibcon#about to read 5, iclass 38, count 0 2006.210.07:48:40.45#ibcon#read 5, iclass 38, count 0 2006.210.07:48:40.45#ibcon#about to read 6, iclass 38, count 0 2006.210.07:48:40.45#ibcon#read 6, iclass 38, count 0 2006.210.07:48:40.45#ibcon#end of sib2, iclass 38, count 0 2006.210.07:48:40.45#ibcon#*after write, iclass 38, count 0 2006.210.07:48:40.45#ibcon#*before return 0, iclass 38, count 0 2006.210.07:48:40.45#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:48:40.45#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:48:40.45#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:48:40.45#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:48:40.45$vc4f8/vblo=2,640.99 2006.210.07:48:40.45#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:48:40.45#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:48:40.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:40.45#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:40.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:40.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:40.45#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:48:40.45#ibcon#first serial, iclass 40, count 0 2006.210.07:48:40.45#ibcon#enter sib2, iclass 40, count 0 2006.210.07:48:40.45#ibcon#flushed, iclass 40, count 0 2006.210.07:48:40.45#ibcon#about to write, iclass 40, count 0 2006.210.07:48:40.45#ibcon#wrote, iclass 40, count 0 2006.210.07:48:40.45#ibcon#about to read 3, iclass 40, count 0 2006.210.07:48:40.47#ibcon#read 3, iclass 40, count 0 2006.210.07:48:40.47#ibcon#about to read 4, iclass 40, count 0 2006.210.07:48:40.47#ibcon#read 4, iclass 40, count 0 2006.210.07:48:40.47#ibcon#about to read 5, iclass 40, count 0 2006.210.07:48:40.47#ibcon#read 5, iclass 40, count 0 2006.210.07:48:40.47#ibcon#about to read 6, iclass 40, count 0 2006.210.07:48:40.47#ibcon#read 6, iclass 40, count 0 2006.210.07:48:40.47#ibcon#end of sib2, iclass 40, count 0 2006.210.07:48:40.47#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:48:40.47#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:48:40.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:48:40.47#ibcon#*before write, iclass 40, count 0 2006.210.07:48:40.47#ibcon#enter sib2, iclass 40, count 0 2006.210.07:48:40.47#ibcon#flushed, iclass 40, count 0 2006.210.07:48:40.47#ibcon#about to write, iclass 40, count 0 2006.210.07:48:40.47#ibcon#wrote, iclass 40, count 0 2006.210.07:48:40.47#ibcon#about to read 3, iclass 40, count 0 2006.210.07:48:40.51#ibcon#read 3, iclass 40, count 0 2006.210.07:48:40.51#ibcon#about to read 4, iclass 40, count 0 2006.210.07:48:40.51#ibcon#read 4, iclass 40, count 0 2006.210.07:48:40.51#ibcon#about to read 5, iclass 40, count 0 2006.210.07:48:40.51#ibcon#read 5, iclass 40, count 0 2006.210.07:48:40.51#ibcon#about to read 6, iclass 40, count 0 2006.210.07:48:40.51#ibcon#read 6, iclass 40, count 0 2006.210.07:48:40.51#ibcon#end of sib2, iclass 40, count 0 2006.210.07:48:40.51#ibcon#*after write, iclass 40, count 0 2006.210.07:48:40.51#ibcon#*before return 0, iclass 40, count 0 2006.210.07:48:40.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:40.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:48:40.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:48:40.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:48:40.51$vc4f8/vb=2,4 2006.210.07:48:40.51#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:48:40.51#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:48:40.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:40.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:40.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:40.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:40.57#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:48:40.57#ibcon#first serial, iclass 4, count 2 2006.210.07:48:40.57#ibcon#enter sib2, iclass 4, count 2 2006.210.07:48:40.57#ibcon#flushed, iclass 4, count 2 2006.210.07:48:40.57#ibcon#about to write, iclass 4, count 2 2006.210.07:48:40.57#ibcon#wrote, iclass 4, count 2 2006.210.07:48:40.57#ibcon#about to read 3, iclass 4, count 2 2006.210.07:48:40.59#ibcon#read 3, iclass 4, count 2 2006.210.07:48:40.59#ibcon#about to read 4, iclass 4, count 2 2006.210.07:48:40.59#ibcon#read 4, iclass 4, count 2 2006.210.07:48:40.59#ibcon#about to read 5, iclass 4, count 2 2006.210.07:48:40.59#ibcon#read 5, iclass 4, count 2 2006.210.07:48:40.59#ibcon#about to read 6, iclass 4, count 2 2006.210.07:48:40.59#ibcon#read 6, iclass 4, count 2 2006.210.07:48:40.59#ibcon#end of sib2, iclass 4, count 2 2006.210.07:48:40.59#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:48:40.59#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:48:40.59#ibcon#[27=AT02-04\r\n] 2006.210.07:48:40.59#ibcon#*before write, iclass 4, count 2 2006.210.07:48:40.59#ibcon#enter sib2, iclass 4, count 2 2006.210.07:48:40.59#ibcon#flushed, iclass 4, count 2 2006.210.07:48:40.59#ibcon#about to write, iclass 4, count 2 2006.210.07:48:40.59#ibcon#wrote, iclass 4, count 2 2006.210.07:48:40.59#ibcon#about to read 3, iclass 4, count 2 2006.210.07:48:40.62#ibcon#read 3, iclass 4, count 2 2006.210.07:48:40.62#ibcon#about to read 4, iclass 4, count 2 2006.210.07:48:40.62#ibcon#read 4, iclass 4, count 2 2006.210.07:48:40.62#ibcon#about to read 5, iclass 4, count 2 2006.210.07:48:40.62#ibcon#read 5, iclass 4, count 2 2006.210.07:48:40.62#ibcon#about to read 6, iclass 4, count 2 2006.210.07:48:40.62#ibcon#read 6, iclass 4, count 2 2006.210.07:48:40.62#ibcon#end of sib2, iclass 4, count 2 2006.210.07:48:40.62#ibcon#*after write, iclass 4, count 2 2006.210.07:48:40.62#ibcon#*before return 0, iclass 4, count 2 2006.210.07:48:40.62#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:40.62#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:48:40.62#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:48:40.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:40.62#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:40.74#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:40.74#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:40.74#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:48:40.74#ibcon#first serial, iclass 4, count 0 2006.210.07:48:40.74#ibcon#enter sib2, iclass 4, count 0 2006.210.07:48:40.74#ibcon#flushed, iclass 4, count 0 2006.210.07:48:40.74#ibcon#about to write, iclass 4, count 0 2006.210.07:48:40.74#ibcon#wrote, iclass 4, count 0 2006.210.07:48:40.74#ibcon#about to read 3, iclass 4, count 0 2006.210.07:48:40.76#ibcon#read 3, iclass 4, count 0 2006.210.07:48:40.76#ibcon#about to read 4, iclass 4, count 0 2006.210.07:48:40.76#ibcon#read 4, iclass 4, count 0 2006.210.07:48:40.76#ibcon#about to read 5, iclass 4, count 0 2006.210.07:48:40.76#ibcon#read 5, iclass 4, count 0 2006.210.07:48:40.76#ibcon#about to read 6, iclass 4, count 0 2006.210.07:48:40.76#ibcon#read 6, iclass 4, count 0 2006.210.07:48:40.76#ibcon#end of sib2, iclass 4, count 0 2006.210.07:48:40.76#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:48:40.76#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:48:40.76#ibcon#[27=USB\r\n] 2006.210.07:48:40.76#ibcon#*before write, iclass 4, count 0 2006.210.07:48:40.76#ibcon#enter sib2, iclass 4, count 0 2006.210.07:48:40.76#ibcon#flushed, iclass 4, count 0 2006.210.07:48:40.76#ibcon#about to write, iclass 4, count 0 2006.210.07:48:40.76#ibcon#wrote, iclass 4, count 0 2006.210.07:48:40.76#ibcon#about to read 3, iclass 4, count 0 2006.210.07:48:40.79#ibcon#read 3, iclass 4, count 0 2006.210.07:48:40.79#ibcon#about to read 4, iclass 4, count 0 2006.210.07:48:40.79#ibcon#read 4, iclass 4, count 0 2006.210.07:48:40.79#ibcon#about to read 5, iclass 4, count 0 2006.210.07:48:40.79#ibcon#read 5, iclass 4, count 0 2006.210.07:48:40.79#ibcon#about to read 6, iclass 4, count 0 2006.210.07:48:40.79#ibcon#read 6, iclass 4, count 0 2006.210.07:48:40.79#ibcon#end of sib2, iclass 4, count 0 2006.210.07:48:40.79#ibcon#*after write, iclass 4, count 0 2006.210.07:48:40.79#ibcon#*before return 0, iclass 4, count 0 2006.210.07:48:40.79#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:40.79#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:48:40.79#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:48:40.79#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:48:40.79$vc4f8/vblo=3,656.99 2006.210.07:48:40.79#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:48:40.79#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:48:40.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:40.79#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:40.79#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:40.79#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:40.79#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:48:40.79#ibcon#first serial, iclass 6, count 0 2006.210.07:48:40.79#ibcon#enter sib2, iclass 6, count 0 2006.210.07:48:40.79#ibcon#flushed, iclass 6, count 0 2006.210.07:48:40.79#ibcon#about to write, iclass 6, count 0 2006.210.07:48:40.79#ibcon#wrote, iclass 6, count 0 2006.210.07:48:40.79#ibcon#about to read 3, iclass 6, count 0 2006.210.07:48:40.81#ibcon#read 3, iclass 6, count 0 2006.210.07:48:40.81#ibcon#about to read 4, iclass 6, count 0 2006.210.07:48:40.81#ibcon#read 4, iclass 6, count 0 2006.210.07:48:40.81#ibcon#about to read 5, iclass 6, count 0 2006.210.07:48:40.81#ibcon#read 5, iclass 6, count 0 2006.210.07:48:40.81#ibcon#about to read 6, iclass 6, count 0 2006.210.07:48:40.81#ibcon#read 6, iclass 6, count 0 2006.210.07:48:40.81#ibcon#end of sib2, iclass 6, count 0 2006.210.07:48:40.81#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:48:40.81#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:48:40.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:48:40.81#ibcon#*before write, iclass 6, count 0 2006.210.07:48:40.81#ibcon#enter sib2, iclass 6, count 0 2006.210.07:48:40.81#ibcon#flushed, iclass 6, count 0 2006.210.07:48:40.81#ibcon#about to write, iclass 6, count 0 2006.210.07:48:40.81#ibcon#wrote, iclass 6, count 0 2006.210.07:48:40.81#ibcon#about to read 3, iclass 6, count 0 2006.210.07:48:40.85#ibcon#read 3, iclass 6, count 0 2006.210.07:48:40.85#ibcon#about to read 4, iclass 6, count 0 2006.210.07:48:40.85#ibcon#read 4, iclass 6, count 0 2006.210.07:48:40.85#ibcon#about to read 5, iclass 6, count 0 2006.210.07:48:40.85#ibcon#read 5, iclass 6, count 0 2006.210.07:48:40.85#ibcon#about to read 6, iclass 6, count 0 2006.210.07:48:40.85#ibcon#read 6, iclass 6, count 0 2006.210.07:48:40.85#ibcon#end of sib2, iclass 6, count 0 2006.210.07:48:40.85#ibcon#*after write, iclass 6, count 0 2006.210.07:48:40.85#ibcon#*before return 0, iclass 6, count 0 2006.210.07:48:40.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:40.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:48:40.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:48:40.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:48:40.85$vc4f8/vb=3,3 2006.210.07:48:40.85#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:48:40.85#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:48:40.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:40.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:40.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:40.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:40.91#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:48:40.91#ibcon#first serial, iclass 10, count 2 2006.210.07:48:40.91#ibcon#enter sib2, iclass 10, count 2 2006.210.07:48:40.91#ibcon#flushed, iclass 10, count 2 2006.210.07:48:40.91#ibcon#about to write, iclass 10, count 2 2006.210.07:48:40.91#ibcon#wrote, iclass 10, count 2 2006.210.07:48:40.91#ibcon#about to read 3, iclass 10, count 2 2006.210.07:48:40.93#ibcon#read 3, iclass 10, count 2 2006.210.07:48:40.93#ibcon#about to read 4, iclass 10, count 2 2006.210.07:48:40.93#ibcon#read 4, iclass 10, count 2 2006.210.07:48:40.93#ibcon#about to read 5, iclass 10, count 2 2006.210.07:48:40.93#ibcon#read 5, iclass 10, count 2 2006.210.07:48:40.93#ibcon#about to read 6, iclass 10, count 2 2006.210.07:48:40.93#ibcon#read 6, iclass 10, count 2 2006.210.07:48:40.93#ibcon#end of sib2, iclass 10, count 2 2006.210.07:48:40.93#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:48:40.93#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:48:40.93#ibcon#[27=AT03-03\r\n] 2006.210.07:48:40.93#ibcon#*before write, iclass 10, count 2 2006.210.07:48:40.93#ibcon#enter sib2, iclass 10, count 2 2006.210.07:48:40.93#ibcon#flushed, iclass 10, count 2 2006.210.07:48:40.93#ibcon#about to write, iclass 10, count 2 2006.210.07:48:40.93#ibcon#wrote, iclass 10, count 2 2006.210.07:48:40.93#ibcon#about to read 3, iclass 10, count 2 2006.210.07:48:40.96#ibcon#read 3, iclass 10, count 2 2006.210.07:48:40.96#ibcon#about to read 4, iclass 10, count 2 2006.210.07:48:40.96#ibcon#read 4, iclass 10, count 2 2006.210.07:48:40.96#ibcon#about to read 5, iclass 10, count 2 2006.210.07:48:40.96#ibcon#read 5, iclass 10, count 2 2006.210.07:48:40.96#ibcon#about to read 6, iclass 10, count 2 2006.210.07:48:40.96#ibcon#read 6, iclass 10, count 2 2006.210.07:48:40.96#ibcon#end of sib2, iclass 10, count 2 2006.210.07:48:40.96#ibcon#*after write, iclass 10, count 2 2006.210.07:48:40.96#ibcon#*before return 0, iclass 10, count 2 2006.210.07:48:40.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:40.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:48:40.96#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:48:40.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:40.96#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:41.08#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:41.08#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:41.08#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:48:41.08#ibcon#first serial, iclass 10, count 0 2006.210.07:48:41.08#ibcon#enter sib2, iclass 10, count 0 2006.210.07:48:41.08#ibcon#flushed, iclass 10, count 0 2006.210.07:48:41.08#ibcon#about to write, iclass 10, count 0 2006.210.07:48:41.08#ibcon#wrote, iclass 10, count 0 2006.210.07:48:41.08#ibcon#about to read 3, iclass 10, count 0 2006.210.07:48:41.10#ibcon#read 3, iclass 10, count 0 2006.210.07:48:41.10#ibcon#about to read 4, iclass 10, count 0 2006.210.07:48:41.10#ibcon#read 4, iclass 10, count 0 2006.210.07:48:41.10#ibcon#about to read 5, iclass 10, count 0 2006.210.07:48:41.10#ibcon#read 5, iclass 10, count 0 2006.210.07:48:41.10#ibcon#about to read 6, iclass 10, count 0 2006.210.07:48:41.10#ibcon#read 6, iclass 10, count 0 2006.210.07:48:41.10#ibcon#end of sib2, iclass 10, count 0 2006.210.07:48:41.10#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:48:41.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:48:41.10#ibcon#[27=USB\r\n] 2006.210.07:48:41.10#ibcon#*before write, iclass 10, count 0 2006.210.07:48:41.10#ibcon#enter sib2, iclass 10, count 0 2006.210.07:48:41.10#ibcon#flushed, iclass 10, count 0 2006.210.07:48:41.10#ibcon#about to write, iclass 10, count 0 2006.210.07:48:41.10#ibcon#wrote, iclass 10, count 0 2006.210.07:48:41.10#ibcon#about to read 3, iclass 10, count 0 2006.210.07:48:41.13#ibcon#read 3, iclass 10, count 0 2006.210.07:48:41.13#ibcon#about to read 4, iclass 10, count 0 2006.210.07:48:41.13#ibcon#read 4, iclass 10, count 0 2006.210.07:48:41.13#ibcon#about to read 5, iclass 10, count 0 2006.210.07:48:41.13#ibcon#read 5, iclass 10, count 0 2006.210.07:48:41.13#ibcon#about to read 6, iclass 10, count 0 2006.210.07:48:41.13#ibcon#read 6, iclass 10, count 0 2006.210.07:48:41.13#ibcon#end of sib2, iclass 10, count 0 2006.210.07:48:41.13#ibcon#*after write, iclass 10, count 0 2006.210.07:48:41.13#ibcon#*before return 0, iclass 10, count 0 2006.210.07:48:41.13#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:41.13#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:48:41.13#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:48:41.13#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:48:41.13$vc4f8/vblo=4,712.99 2006.210.07:48:41.13#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:48:41.13#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:48:41.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:41.13#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:41.13#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:41.13#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:41.13#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:48:41.13#ibcon#first serial, iclass 12, count 0 2006.210.07:48:41.13#ibcon#enter sib2, iclass 12, count 0 2006.210.07:48:41.13#ibcon#flushed, iclass 12, count 0 2006.210.07:48:41.13#ibcon#about to write, iclass 12, count 0 2006.210.07:48:41.13#ibcon#wrote, iclass 12, count 0 2006.210.07:48:41.13#ibcon#about to read 3, iclass 12, count 0 2006.210.07:48:41.15#ibcon#read 3, iclass 12, count 0 2006.210.07:48:41.15#ibcon#about to read 4, iclass 12, count 0 2006.210.07:48:41.15#ibcon#read 4, iclass 12, count 0 2006.210.07:48:41.15#ibcon#about to read 5, iclass 12, count 0 2006.210.07:48:41.15#ibcon#read 5, iclass 12, count 0 2006.210.07:48:41.15#ibcon#about to read 6, iclass 12, count 0 2006.210.07:48:41.15#ibcon#read 6, iclass 12, count 0 2006.210.07:48:41.15#ibcon#end of sib2, iclass 12, count 0 2006.210.07:48:41.15#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:48:41.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:48:41.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:48:41.15#ibcon#*before write, iclass 12, count 0 2006.210.07:48:41.15#ibcon#enter sib2, iclass 12, count 0 2006.210.07:48:41.15#ibcon#flushed, iclass 12, count 0 2006.210.07:48:41.15#ibcon#about to write, iclass 12, count 0 2006.210.07:48:41.15#ibcon#wrote, iclass 12, count 0 2006.210.07:48:41.15#ibcon#about to read 3, iclass 12, count 0 2006.210.07:48:41.19#ibcon#read 3, iclass 12, count 0 2006.210.07:48:41.19#ibcon#about to read 4, iclass 12, count 0 2006.210.07:48:41.19#ibcon#read 4, iclass 12, count 0 2006.210.07:48:41.19#ibcon#about to read 5, iclass 12, count 0 2006.210.07:48:41.19#ibcon#read 5, iclass 12, count 0 2006.210.07:48:41.19#ibcon#about to read 6, iclass 12, count 0 2006.210.07:48:41.19#ibcon#read 6, iclass 12, count 0 2006.210.07:48:41.19#ibcon#end of sib2, iclass 12, count 0 2006.210.07:48:41.19#ibcon#*after write, iclass 12, count 0 2006.210.07:48:41.19#ibcon#*before return 0, iclass 12, count 0 2006.210.07:48:41.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:41.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:48:41.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:48:41.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:48:41.19$vc4f8/vb=4,3 2006.210.07:48:41.19#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:48:41.19#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:48:41.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:41.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:41.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:41.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:41.25#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:48:41.25#ibcon#first serial, iclass 14, count 2 2006.210.07:48:41.25#ibcon#enter sib2, iclass 14, count 2 2006.210.07:48:41.25#ibcon#flushed, iclass 14, count 2 2006.210.07:48:41.25#ibcon#about to write, iclass 14, count 2 2006.210.07:48:41.25#ibcon#wrote, iclass 14, count 2 2006.210.07:48:41.25#ibcon#about to read 3, iclass 14, count 2 2006.210.07:48:41.27#ibcon#read 3, iclass 14, count 2 2006.210.07:48:41.27#ibcon#about to read 4, iclass 14, count 2 2006.210.07:48:41.27#ibcon#read 4, iclass 14, count 2 2006.210.07:48:41.27#ibcon#about to read 5, iclass 14, count 2 2006.210.07:48:41.27#ibcon#read 5, iclass 14, count 2 2006.210.07:48:41.27#ibcon#about to read 6, iclass 14, count 2 2006.210.07:48:41.27#ibcon#read 6, iclass 14, count 2 2006.210.07:48:41.27#ibcon#end of sib2, iclass 14, count 2 2006.210.07:48:41.27#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:48:41.27#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:48:41.27#ibcon#[27=AT04-03\r\n] 2006.210.07:48:41.27#ibcon#*before write, iclass 14, count 2 2006.210.07:48:41.27#ibcon#enter sib2, iclass 14, count 2 2006.210.07:48:41.27#ibcon#flushed, iclass 14, count 2 2006.210.07:48:41.27#ibcon#about to write, iclass 14, count 2 2006.210.07:48:41.27#ibcon#wrote, iclass 14, count 2 2006.210.07:48:41.27#ibcon#about to read 3, iclass 14, count 2 2006.210.07:48:41.30#ibcon#read 3, iclass 14, count 2 2006.210.07:48:41.30#ibcon#about to read 4, iclass 14, count 2 2006.210.07:48:41.30#ibcon#read 4, iclass 14, count 2 2006.210.07:48:41.30#ibcon#about to read 5, iclass 14, count 2 2006.210.07:48:41.30#ibcon#read 5, iclass 14, count 2 2006.210.07:48:41.30#ibcon#about to read 6, iclass 14, count 2 2006.210.07:48:41.30#ibcon#read 6, iclass 14, count 2 2006.210.07:48:41.30#ibcon#end of sib2, iclass 14, count 2 2006.210.07:48:41.30#ibcon#*after write, iclass 14, count 2 2006.210.07:48:41.30#ibcon#*before return 0, iclass 14, count 2 2006.210.07:48:41.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:41.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:48:41.30#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:48:41.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:41.30#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:41.42#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:41.42#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:41.42#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:48:41.42#ibcon#first serial, iclass 14, count 0 2006.210.07:48:41.42#ibcon#enter sib2, iclass 14, count 0 2006.210.07:48:41.42#ibcon#flushed, iclass 14, count 0 2006.210.07:48:41.42#ibcon#about to write, iclass 14, count 0 2006.210.07:48:41.42#ibcon#wrote, iclass 14, count 0 2006.210.07:48:41.42#ibcon#about to read 3, iclass 14, count 0 2006.210.07:48:41.44#ibcon#read 3, iclass 14, count 0 2006.210.07:48:41.44#ibcon#about to read 4, iclass 14, count 0 2006.210.07:48:41.44#ibcon#read 4, iclass 14, count 0 2006.210.07:48:41.44#ibcon#about to read 5, iclass 14, count 0 2006.210.07:48:41.44#ibcon#read 5, iclass 14, count 0 2006.210.07:48:41.44#ibcon#about to read 6, iclass 14, count 0 2006.210.07:48:41.44#ibcon#read 6, iclass 14, count 0 2006.210.07:48:41.44#ibcon#end of sib2, iclass 14, count 0 2006.210.07:48:41.44#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:48:41.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:48:41.44#ibcon#[27=USB\r\n] 2006.210.07:48:41.44#ibcon#*before write, iclass 14, count 0 2006.210.07:48:41.44#ibcon#enter sib2, iclass 14, count 0 2006.210.07:48:41.44#ibcon#flushed, iclass 14, count 0 2006.210.07:48:41.44#ibcon#about to write, iclass 14, count 0 2006.210.07:48:41.44#ibcon#wrote, iclass 14, count 0 2006.210.07:48:41.44#ibcon#about to read 3, iclass 14, count 0 2006.210.07:48:41.47#ibcon#read 3, iclass 14, count 0 2006.210.07:48:41.47#ibcon#about to read 4, iclass 14, count 0 2006.210.07:48:41.47#ibcon#read 4, iclass 14, count 0 2006.210.07:48:41.47#ibcon#about to read 5, iclass 14, count 0 2006.210.07:48:41.47#ibcon#read 5, iclass 14, count 0 2006.210.07:48:41.47#ibcon#about to read 6, iclass 14, count 0 2006.210.07:48:41.47#ibcon#read 6, iclass 14, count 0 2006.210.07:48:41.47#ibcon#end of sib2, iclass 14, count 0 2006.210.07:48:41.47#ibcon#*after write, iclass 14, count 0 2006.210.07:48:41.47#ibcon#*before return 0, iclass 14, count 0 2006.210.07:48:41.47#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:41.47#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:48:41.47#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:48:41.47#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:48:41.47$vc4f8/vblo=5,744.99 2006.210.07:48:41.47#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:48:41.47#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:48:41.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:41.47#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:41.47#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:41.47#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:41.47#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:48:41.47#ibcon#first serial, iclass 16, count 0 2006.210.07:48:41.47#ibcon#enter sib2, iclass 16, count 0 2006.210.07:48:41.47#ibcon#flushed, iclass 16, count 0 2006.210.07:48:41.47#ibcon#about to write, iclass 16, count 0 2006.210.07:48:41.47#ibcon#wrote, iclass 16, count 0 2006.210.07:48:41.47#ibcon#about to read 3, iclass 16, count 0 2006.210.07:48:41.49#ibcon#read 3, iclass 16, count 0 2006.210.07:48:41.49#ibcon#about to read 4, iclass 16, count 0 2006.210.07:48:41.49#ibcon#read 4, iclass 16, count 0 2006.210.07:48:41.49#ibcon#about to read 5, iclass 16, count 0 2006.210.07:48:41.49#ibcon#read 5, iclass 16, count 0 2006.210.07:48:41.49#ibcon#about to read 6, iclass 16, count 0 2006.210.07:48:41.49#ibcon#read 6, iclass 16, count 0 2006.210.07:48:41.49#ibcon#end of sib2, iclass 16, count 0 2006.210.07:48:41.49#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:48:41.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:48:41.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:48:41.49#ibcon#*before write, iclass 16, count 0 2006.210.07:48:41.49#ibcon#enter sib2, iclass 16, count 0 2006.210.07:48:41.49#ibcon#flushed, iclass 16, count 0 2006.210.07:48:41.49#ibcon#about to write, iclass 16, count 0 2006.210.07:48:41.49#ibcon#wrote, iclass 16, count 0 2006.210.07:48:41.49#ibcon#about to read 3, iclass 16, count 0 2006.210.07:48:41.53#ibcon#read 3, iclass 16, count 0 2006.210.07:48:41.53#ibcon#about to read 4, iclass 16, count 0 2006.210.07:48:41.53#ibcon#read 4, iclass 16, count 0 2006.210.07:48:41.53#ibcon#about to read 5, iclass 16, count 0 2006.210.07:48:41.53#ibcon#read 5, iclass 16, count 0 2006.210.07:48:41.53#ibcon#about to read 6, iclass 16, count 0 2006.210.07:48:41.53#ibcon#read 6, iclass 16, count 0 2006.210.07:48:41.53#ibcon#end of sib2, iclass 16, count 0 2006.210.07:48:41.53#ibcon#*after write, iclass 16, count 0 2006.210.07:48:41.53#ibcon#*before return 0, iclass 16, count 0 2006.210.07:48:41.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:41.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:48:41.53#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:48:41.53#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:48:41.53$vc4f8/vb=5,3 2006.210.07:48:41.53#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:48:41.53#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:48:41.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:41.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:41.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:41.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:41.59#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:48:41.59#ibcon#first serial, iclass 18, count 2 2006.210.07:48:41.59#ibcon#enter sib2, iclass 18, count 2 2006.210.07:48:41.59#ibcon#flushed, iclass 18, count 2 2006.210.07:48:41.59#ibcon#about to write, iclass 18, count 2 2006.210.07:48:41.59#ibcon#wrote, iclass 18, count 2 2006.210.07:48:41.59#ibcon#about to read 3, iclass 18, count 2 2006.210.07:48:41.61#ibcon#read 3, iclass 18, count 2 2006.210.07:48:41.61#ibcon#about to read 4, iclass 18, count 2 2006.210.07:48:41.61#ibcon#read 4, iclass 18, count 2 2006.210.07:48:41.61#ibcon#about to read 5, iclass 18, count 2 2006.210.07:48:41.61#ibcon#read 5, iclass 18, count 2 2006.210.07:48:41.61#ibcon#about to read 6, iclass 18, count 2 2006.210.07:48:41.61#ibcon#read 6, iclass 18, count 2 2006.210.07:48:41.61#ibcon#end of sib2, iclass 18, count 2 2006.210.07:48:41.61#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:48:41.61#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:48:41.61#ibcon#[27=AT05-03\r\n] 2006.210.07:48:41.61#ibcon#*before write, iclass 18, count 2 2006.210.07:48:41.61#ibcon#enter sib2, iclass 18, count 2 2006.210.07:48:41.61#ibcon#flushed, iclass 18, count 2 2006.210.07:48:41.61#ibcon#about to write, iclass 18, count 2 2006.210.07:48:41.61#ibcon#wrote, iclass 18, count 2 2006.210.07:48:41.61#ibcon#about to read 3, iclass 18, count 2 2006.210.07:48:41.64#ibcon#read 3, iclass 18, count 2 2006.210.07:48:41.64#ibcon#about to read 4, iclass 18, count 2 2006.210.07:48:41.64#ibcon#read 4, iclass 18, count 2 2006.210.07:48:41.64#ibcon#about to read 5, iclass 18, count 2 2006.210.07:48:41.64#ibcon#read 5, iclass 18, count 2 2006.210.07:48:41.64#ibcon#about to read 6, iclass 18, count 2 2006.210.07:48:41.64#ibcon#read 6, iclass 18, count 2 2006.210.07:48:41.64#ibcon#end of sib2, iclass 18, count 2 2006.210.07:48:41.64#ibcon#*after write, iclass 18, count 2 2006.210.07:48:41.64#ibcon#*before return 0, iclass 18, count 2 2006.210.07:48:41.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:41.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:48:41.64#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:48:41.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:41.64#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:41.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:41.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:41.76#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:48:41.76#ibcon#first serial, iclass 18, count 0 2006.210.07:48:41.76#ibcon#enter sib2, iclass 18, count 0 2006.210.07:48:41.76#ibcon#flushed, iclass 18, count 0 2006.210.07:48:41.76#ibcon#about to write, iclass 18, count 0 2006.210.07:48:41.76#ibcon#wrote, iclass 18, count 0 2006.210.07:48:41.76#ibcon#about to read 3, iclass 18, count 0 2006.210.07:48:41.78#ibcon#read 3, iclass 18, count 0 2006.210.07:48:41.78#ibcon#about to read 4, iclass 18, count 0 2006.210.07:48:41.78#ibcon#read 4, iclass 18, count 0 2006.210.07:48:41.78#ibcon#about to read 5, iclass 18, count 0 2006.210.07:48:41.78#ibcon#read 5, iclass 18, count 0 2006.210.07:48:41.78#ibcon#about to read 6, iclass 18, count 0 2006.210.07:48:41.78#ibcon#read 6, iclass 18, count 0 2006.210.07:48:41.78#ibcon#end of sib2, iclass 18, count 0 2006.210.07:48:41.78#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:48:41.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:48:41.78#ibcon#[27=USB\r\n] 2006.210.07:48:41.78#ibcon#*before write, iclass 18, count 0 2006.210.07:48:41.78#ibcon#enter sib2, iclass 18, count 0 2006.210.07:48:41.78#ibcon#flushed, iclass 18, count 0 2006.210.07:48:41.78#ibcon#about to write, iclass 18, count 0 2006.210.07:48:41.78#ibcon#wrote, iclass 18, count 0 2006.210.07:48:41.78#ibcon#about to read 3, iclass 18, count 0 2006.210.07:48:41.81#ibcon#read 3, iclass 18, count 0 2006.210.07:48:41.81#ibcon#about to read 4, iclass 18, count 0 2006.210.07:48:41.81#ibcon#read 4, iclass 18, count 0 2006.210.07:48:41.81#ibcon#about to read 5, iclass 18, count 0 2006.210.07:48:41.81#ibcon#read 5, iclass 18, count 0 2006.210.07:48:41.81#ibcon#about to read 6, iclass 18, count 0 2006.210.07:48:41.81#ibcon#read 6, iclass 18, count 0 2006.210.07:48:41.81#ibcon#end of sib2, iclass 18, count 0 2006.210.07:48:41.81#ibcon#*after write, iclass 18, count 0 2006.210.07:48:41.81#ibcon#*before return 0, iclass 18, count 0 2006.210.07:48:41.81#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:41.81#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:48:41.81#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:48:41.81#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:48:41.81$vc4f8/vblo=6,752.99 2006.210.07:48:41.81#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:48:41.81#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:48:41.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:48:41.81#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:41.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:41.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:41.81#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:48:41.81#ibcon#first serial, iclass 20, count 0 2006.210.07:48:41.81#ibcon#enter sib2, iclass 20, count 0 2006.210.07:48:41.81#ibcon#flushed, iclass 20, count 0 2006.210.07:48:41.81#ibcon#about to write, iclass 20, count 0 2006.210.07:48:41.81#ibcon#wrote, iclass 20, count 0 2006.210.07:48:41.81#ibcon#about to read 3, iclass 20, count 0 2006.210.07:48:41.83#ibcon#read 3, iclass 20, count 0 2006.210.07:48:41.83#ibcon#about to read 4, iclass 20, count 0 2006.210.07:48:41.83#ibcon#read 4, iclass 20, count 0 2006.210.07:48:41.83#ibcon#about to read 5, iclass 20, count 0 2006.210.07:48:41.83#ibcon#read 5, iclass 20, count 0 2006.210.07:48:41.83#ibcon#about to read 6, iclass 20, count 0 2006.210.07:48:41.83#ibcon#read 6, iclass 20, count 0 2006.210.07:48:41.83#ibcon#end of sib2, iclass 20, count 0 2006.210.07:48:41.83#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:48:41.83#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:48:41.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:48:41.83#ibcon#*before write, iclass 20, count 0 2006.210.07:48:41.83#ibcon#enter sib2, iclass 20, count 0 2006.210.07:48:41.83#ibcon#flushed, iclass 20, count 0 2006.210.07:48:41.83#ibcon#about to write, iclass 20, count 0 2006.210.07:48:41.83#ibcon#wrote, iclass 20, count 0 2006.210.07:48:41.83#ibcon#about to read 3, iclass 20, count 0 2006.210.07:48:41.87#ibcon#read 3, iclass 20, count 0 2006.210.07:48:41.87#ibcon#about to read 4, iclass 20, count 0 2006.210.07:48:41.87#ibcon#read 4, iclass 20, count 0 2006.210.07:48:41.87#ibcon#about to read 5, iclass 20, count 0 2006.210.07:48:41.87#ibcon#read 5, iclass 20, count 0 2006.210.07:48:41.87#ibcon#about to read 6, iclass 20, count 0 2006.210.07:48:41.87#ibcon#read 6, iclass 20, count 0 2006.210.07:48:41.87#ibcon#end of sib2, iclass 20, count 0 2006.210.07:48:41.87#ibcon#*after write, iclass 20, count 0 2006.210.07:48:41.87#ibcon#*before return 0, iclass 20, count 0 2006.210.07:48:41.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:41.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:48:41.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:48:41.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:48:41.87$vc4f8/vb=6,3 2006.210.07:48:41.87#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:48:41.87#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:48:41.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:48:41.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:41.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:41.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:41.93#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:48:41.93#ibcon#first serial, iclass 22, count 2 2006.210.07:48:41.93#ibcon#enter sib2, iclass 22, count 2 2006.210.07:48:41.93#ibcon#flushed, iclass 22, count 2 2006.210.07:48:41.93#ibcon#about to write, iclass 22, count 2 2006.210.07:48:41.93#ibcon#wrote, iclass 22, count 2 2006.210.07:48:41.93#ibcon#about to read 3, iclass 22, count 2 2006.210.07:48:41.95#ibcon#read 3, iclass 22, count 2 2006.210.07:48:41.95#ibcon#about to read 4, iclass 22, count 2 2006.210.07:48:41.95#ibcon#read 4, iclass 22, count 2 2006.210.07:48:41.95#ibcon#about to read 5, iclass 22, count 2 2006.210.07:48:41.95#ibcon#read 5, iclass 22, count 2 2006.210.07:48:41.95#ibcon#about to read 6, iclass 22, count 2 2006.210.07:48:41.95#ibcon#read 6, iclass 22, count 2 2006.210.07:48:41.95#ibcon#end of sib2, iclass 22, count 2 2006.210.07:48:41.95#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:48:41.95#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:48:41.95#ibcon#[27=AT06-03\r\n] 2006.210.07:48:41.95#ibcon#*before write, iclass 22, count 2 2006.210.07:48:41.95#ibcon#enter sib2, iclass 22, count 2 2006.210.07:48:41.95#ibcon#flushed, iclass 22, count 2 2006.210.07:48:41.95#ibcon#about to write, iclass 22, count 2 2006.210.07:48:41.95#ibcon#wrote, iclass 22, count 2 2006.210.07:48:41.95#ibcon#about to read 3, iclass 22, count 2 2006.210.07:48:41.98#ibcon#read 3, iclass 22, count 2 2006.210.07:48:41.98#ibcon#about to read 4, iclass 22, count 2 2006.210.07:48:41.98#ibcon#read 4, iclass 22, count 2 2006.210.07:48:41.98#ibcon#about to read 5, iclass 22, count 2 2006.210.07:48:41.98#ibcon#read 5, iclass 22, count 2 2006.210.07:48:41.98#ibcon#about to read 6, iclass 22, count 2 2006.210.07:48:41.98#ibcon#read 6, iclass 22, count 2 2006.210.07:48:41.98#ibcon#end of sib2, iclass 22, count 2 2006.210.07:48:41.98#ibcon#*after write, iclass 22, count 2 2006.210.07:48:41.98#ibcon#*before return 0, iclass 22, count 2 2006.210.07:48:41.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:41.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:48:41.98#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:48:41.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:48:41.98#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:42.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:42.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:42.10#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:48:42.10#ibcon#first serial, iclass 22, count 0 2006.210.07:48:42.10#ibcon#enter sib2, iclass 22, count 0 2006.210.07:48:42.10#ibcon#flushed, iclass 22, count 0 2006.210.07:48:42.10#ibcon#about to write, iclass 22, count 0 2006.210.07:48:42.10#ibcon#wrote, iclass 22, count 0 2006.210.07:48:42.10#ibcon#about to read 3, iclass 22, count 0 2006.210.07:48:42.12#ibcon#read 3, iclass 22, count 0 2006.210.07:48:42.12#ibcon#about to read 4, iclass 22, count 0 2006.210.07:48:42.12#ibcon#read 4, iclass 22, count 0 2006.210.07:48:42.12#ibcon#about to read 5, iclass 22, count 0 2006.210.07:48:42.12#ibcon#read 5, iclass 22, count 0 2006.210.07:48:42.12#ibcon#about to read 6, iclass 22, count 0 2006.210.07:48:42.12#ibcon#read 6, iclass 22, count 0 2006.210.07:48:42.12#ibcon#end of sib2, iclass 22, count 0 2006.210.07:48:42.12#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:48:42.12#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:48:42.12#ibcon#[27=USB\r\n] 2006.210.07:48:42.12#ibcon#*before write, iclass 22, count 0 2006.210.07:48:42.12#ibcon#enter sib2, iclass 22, count 0 2006.210.07:48:42.12#ibcon#flushed, iclass 22, count 0 2006.210.07:48:42.12#ibcon#about to write, iclass 22, count 0 2006.210.07:48:42.12#ibcon#wrote, iclass 22, count 0 2006.210.07:48:42.12#ibcon#about to read 3, iclass 22, count 0 2006.210.07:48:42.15#ibcon#read 3, iclass 22, count 0 2006.210.07:48:42.15#ibcon#about to read 4, iclass 22, count 0 2006.210.07:48:42.15#ibcon#read 4, iclass 22, count 0 2006.210.07:48:42.15#ibcon#about to read 5, iclass 22, count 0 2006.210.07:48:42.15#ibcon#read 5, iclass 22, count 0 2006.210.07:48:42.15#ibcon#about to read 6, iclass 22, count 0 2006.210.07:48:42.15#ibcon#read 6, iclass 22, count 0 2006.210.07:48:42.15#ibcon#end of sib2, iclass 22, count 0 2006.210.07:48:42.15#ibcon#*after write, iclass 22, count 0 2006.210.07:48:42.15#ibcon#*before return 0, iclass 22, count 0 2006.210.07:48:42.15#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:42.15#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:48:42.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:48:42.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:48:42.15$vc4f8/vabw=wide 2006.210.07:48:42.15#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:48:42.15#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:48:42.15#ibcon#ireg 8 cls_cnt 0 2006.210.07:48:42.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:42.15#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:42.15#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:42.15#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:48:42.15#ibcon#first serial, iclass 24, count 0 2006.210.07:48:42.15#ibcon#enter sib2, iclass 24, count 0 2006.210.07:48:42.15#ibcon#flushed, iclass 24, count 0 2006.210.07:48:42.15#ibcon#about to write, iclass 24, count 0 2006.210.07:48:42.15#ibcon#wrote, iclass 24, count 0 2006.210.07:48:42.15#ibcon#about to read 3, iclass 24, count 0 2006.210.07:48:42.17#ibcon#read 3, iclass 24, count 0 2006.210.07:48:42.17#ibcon#about to read 4, iclass 24, count 0 2006.210.07:48:42.17#ibcon#read 4, iclass 24, count 0 2006.210.07:48:42.17#ibcon#about to read 5, iclass 24, count 0 2006.210.07:48:42.17#ibcon#read 5, iclass 24, count 0 2006.210.07:48:42.17#ibcon#about to read 6, iclass 24, count 0 2006.210.07:48:42.17#ibcon#read 6, iclass 24, count 0 2006.210.07:48:42.17#ibcon#end of sib2, iclass 24, count 0 2006.210.07:48:42.17#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:48:42.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:48:42.17#ibcon#[25=BW32\r\n] 2006.210.07:48:42.17#ibcon#*before write, iclass 24, count 0 2006.210.07:48:42.17#ibcon#enter sib2, iclass 24, count 0 2006.210.07:48:42.17#ibcon#flushed, iclass 24, count 0 2006.210.07:48:42.17#ibcon#about to write, iclass 24, count 0 2006.210.07:48:42.17#ibcon#wrote, iclass 24, count 0 2006.210.07:48:42.17#ibcon#about to read 3, iclass 24, count 0 2006.210.07:48:42.20#ibcon#read 3, iclass 24, count 0 2006.210.07:48:42.20#ibcon#about to read 4, iclass 24, count 0 2006.210.07:48:42.20#ibcon#read 4, iclass 24, count 0 2006.210.07:48:42.20#ibcon#about to read 5, iclass 24, count 0 2006.210.07:48:42.20#ibcon#read 5, iclass 24, count 0 2006.210.07:48:42.20#ibcon#about to read 6, iclass 24, count 0 2006.210.07:48:42.20#ibcon#read 6, iclass 24, count 0 2006.210.07:48:42.20#ibcon#end of sib2, iclass 24, count 0 2006.210.07:48:42.20#ibcon#*after write, iclass 24, count 0 2006.210.07:48:42.20#ibcon#*before return 0, iclass 24, count 0 2006.210.07:48:42.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:42.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:48:42.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:48:42.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:48:42.20$vc4f8/vbbw=wide 2006.210.07:48:42.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:48:42.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:48:42.20#ibcon#ireg 8 cls_cnt 0 2006.210.07:48:42.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:48:42.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:48:42.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:48:42.27#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:48:42.27#ibcon#first serial, iclass 26, count 0 2006.210.07:48:42.27#ibcon#enter sib2, iclass 26, count 0 2006.210.07:48:42.27#ibcon#flushed, iclass 26, count 0 2006.210.07:48:42.27#ibcon#about to write, iclass 26, count 0 2006.210.07:48:42.27#ibcon#wrote, iclass 26, count 0 2006.210.07:48:42.27#ibcon#about to read 3, iclass 26, count 0 2006.210.07:48:42.29#ibcon#read 3, iclass 26, count 0 2006.210.07:48:42.29#ibcon#about to read 4, iclass 26, count 0 2006.210.07:48:42.29#ibcon#read 4, iclass 26, count 0 2006.210.07:48:42.29#ibcon#about to read 5, iclass 26, count 0 2006.210.07:48:42.29#ibcon#read 5, iclass 26, count 0 2006.210.07:48:42.29#ibcon#about to read 6, iclass 26, count 0 2006.210.07:48:42.29#ibcon#read 6, iclass 26, count 0 2006.210.07:48:42.29#ibcon#end of sib2, iclass 26, count 0 2006.210.07:48:42.29#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:48:42.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:48:42.29#ibcon#[27=BW32\r\n] 2006.210.07:48:42.29#ibcon#*before write, iclass 26, count 0 2006.210.07:48:42.29#ibcon#enter sib2, iclass 26, count 0 2006.210.07:48:42.29#ibcon#flushed, iclass 26, count 0 2006.210.07:48:42.29#ibcon#about to write, iclass 26, count 0 2006.210.07:48:42.29#ibcon#wrote, iclass 26, count 0 2006.210.07:48:42.29#ibcon#about to read 3, iclass 26, count 0 2006.210.07:48:42.32#ibcon#read 3, iclass 26, count 0 2006.210.07:48:42.32#ibcon#about to read 4, iclass 26, count 0 2006.210.07:48:42.32#ibcon#read 4, iclass 26, count 0 2006.210.07:48:42.32#ibcon#about to read 5, iclass 26, count 0 2006.210.07:48:42.32#ibcon#read 5, iclass 26, count 0 2006.210.07:48:42.32#ibcon#about to read 6, iclass 26, count 0 2006.210.07:48:42.32#ibcon#read 6, iclass 26, count 0 2006.210.07:48:42.32#ibcon#end of sib2, iclass 26, count 0 2006.210.07:48:42.32#ibcon#*after write, iclass 26, count 0 2006.210.07:48:42.32#ibcon#*before return 0, iclass 26, count 0 2006.210.07:48:42.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:48:42.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:48:42.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:48:42.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:48:42.32$4f8m12a/ifd4f 2006.210.07:48:42.32$ifd4f/lo= 2006.210.07:48:42.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:48:42.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:48:42.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:48:42.32$ifd4f/patch= 2006.210.07:48:42.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:48:42.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:48:42.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:48:42.32$4f8m12a/"form=m,16.000,1:2 2006.210.07:48:42.32$4f8m12a/"tpicd 2006.210.07:48:42.32$4f8m12a/echo=off 2006.210.07:48:42.32$4f8m12a/xlog=off 2006.210.07:48:42.32:!2006.210.07:49:20 2006.210.07:48:58.13#trakl#Source acquired 2006.210.07:49:00.13#flagr#flagr/antenna,acquired 2006.210.07:49:20.00:preob 2006.210.07:49:20.13/onsource/TRACKING 2006.210.07:49:20.13:!2006.210.07:49:30 2006.210.07:49:30.00:data_valid=on 2006.210.07:49:30.00:midob 2006.210.07:49:30.13/onsource/TRACKING 2006.210.07:49:30.13/wx/30.56,1006.3,73 2006.210.07:49:30.22/cable/+6.3952E-03 2006.210.07:49:31.31/va/01,08,usb,yes,29,31 2006.210.07:49:31.31/va/02,07,usb,yes,29,31 2006.210.07:49:31.31/va/03,06,usb,yes,31,31 2006.210.07:49:31.31/va/04,07,usb,yes,30,32 2006.210.07:49:31.31/va/05,07,usb,yes,31,33 2006.210.07:49:31.31/va/06,06,usb,yes,31,30 2006.210.07:49:31.31/va/07,06,usb,yes,31,31 2006.210.07:49:31.31/va/08,07,usb,yes,29,29 2006.210.07:49:31.54/valo/01,532.99,yes,locked 2006.210.07:49:31.54/valo/02,572.99,yes,locked 2006.210.07:49:31.54/valo/03,672.99,yes,locked 2006.210.07:49:31.54/valo/04,832.99,yes,locked 2006.210.07:49:31.54/valo/05,652.99,yes,locked 2006.210.07:49:31.54/valo/06,772.99,yes,locked 2006.210.07:49:31.54/valo/07,832.99,yes,locked 2006.210.07:49:31.54/valo/08,852.99,yes,locked 2006.210.07:49:32.63/vb/01,04,usb,yes,29,28 2006.210.07:49:32.63/vb/02,04,usb,yes,31,32 2006.210.07:49:32.63/vb/03,03,usb,yes,34,38 2006.210.07:49:32.63/vb/04,03,usb,yes,35,35 2006.210.07:49:32.63/vb/05,03,usb,yes,33,38 2006.210.07:49:32.63/vb/06,03,usb,yes,34,37 2006.210.07:49:32.63/vb/07,04,usb,yes,29,29 2006.210.07:49:32.63/vb/08,03,usb,yes,34,37 2006.210.07:49:32.87/vblo/01,632.99,yes,locked 2006.210.07:49:32.87/vblo/02,640.99,yes,locked 2006.210.07:49:32.87/vblo/03,656.99,yes,locked 2006.210.07:49:32.87/vblo/04,712.99,yes,locked 2006.210.07:49:32.87/vblo/05,744.99,yes,locked 2006.210.07:49:32.87/vblo/06,752.99,yes,locked 2006.210.07:49:32.87/vblo/07,734.99,yes,locked 2006.210.07:49:32.87/vblo/08,744.99,yes,locked 2006.210.07:49:33.02/vabw/8 2006.210.07:49:33.17/vbbw/8 2006.210.07:49:33.26/xfe/off,on,12.2 2006.210.07:49:33.64/ifatt/23,28,28,28 2006.210.07:49:34.08/fmout-gps/S +4.60E-07 2006.210.07:49:34.12:!2006.210.07:50:30 2006.210.07:50:30.00:data_valid=off 2006.210.07:50:30.00:postob 2006.210.07:50:30.19/cable/+6.3957E-03 2006.210.07:50:30.19/wx/30.56,1006.3,71 2006.210.07:50:31.08/fmout-gps/S +4.63E-07 2006.210.07:50:31.08:scan_name=210-0751,k06210,60 2006.210.07:50:31.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.210.07:50:31.13#flagr#flagr/antenna,new-source 2006.210.07:50:32.14:checkk5 2006.210.07:50:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:50:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:50:33.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:50:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:50:33.84/chk_obsdata//k5ts1/T2100749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:50:34.18/chk_obsdata//k5ts2/T2100749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:50:34.52/chk_obsdata//k5ts3/T2100749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:50:34.85/chk_obsdata//k5ts4/T2100749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:50:35.50/k5log//k5ts1_log_newline 2006.210.07:50:36.16/k5log//k5ts2_log_newline 2006.210.07:50:36.82/k5log//k5ts3_log_newline 2006.210.07:50:37.48/k5log//k5ts4_log_newline 2006.210.07:50:37.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:50:37.50:4f8m12a=1 2006.210.07:50:37.50$4f8m12a/echo=on 2006.210.07:50:37.50$4f8m12a/pcalon 2006.210.07:50:37.50$pcalon/"no phase cal control is implemented here 2006.210.07:50:37.50$4f8m12a/"tpicd=stop 2006.210.07:50:37.51$4f8m12a/vc4f8 2006.210.07:50:37.51$vc4f8/valo=1,532.99 2006.210.07:50:37.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:50:37.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:50:37.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:37.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:37.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:37.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:37.51#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:50:37.51#ibcon#first serial, iclass 3, count 0 2006.210.07:50:37.51#ibcon#enter sib2, iclass 3, count 0 2006.210.07:50:37.51#ibcon#flushed, iclass 3, count 0 2006.210.07:50:37.51#ibcon#about to write, iclass 3, count 0 2006.210.07:50:37.51#ibcon#wrote, iclass 3, count 0 2006.210.07:50:37.51#ibcon#about to read 3, iclass 3, count 0 2006.210.07:50:37.53#ibcon#read 3, iclass 3, count 0 2006.210.07:50:37.53#ibcon#about to read 4, iclass 3, count 0 2006.210.07:50:37.53#ibcon#read 4, iclass 3, count 0 2006.210.07:50:37.53#ibcon#about to read 5, iclass 3, count 0 2006.210.07:50:37.53#ibcon#read 5, iclass 3, count 0 2006.210.07:50:37.53#ibcon#about to read 6, iclass 3, count 0 2006.210.07:50:37.53#ibcon#read 6, iclass 3, count 0 2006.210.07:50:37.53#ibcon#end of sib2, iclass 3, count 0 2006.210.07:50:37.53#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:50:37.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:50:37.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:50:37.53#ibcon#*before write, iclass 3, count 0 2006.210.07:50:37.53#ibcon#enter sib2, iclass 3, count 0 2006.210.07:50:37.53#ibcon#flushed, iclass 3, count 0 2006.210.07:50:37.53#ibcon#about to write, iclass 3, count 0 2006.210.07:50:37.53#ibcon#wrote, iclass 3, count 0 2006.210.07:50:37.53#ibcon#about to read 3, iclass 3, count 0 2006.210.07:50:37.58#ibcon#read 3, iclass 3, count 0 2006.210.07:50:37.58#ibcon#about to read 4, iclass 3, count 0 2006.210.07:50:37.58#ibcon#read 4, iclass 3, count 0 2006.210.07:50:37.58#ibcon#about to read 5, iclass 3, count 0 2006.210.07:50:37.58#ibcon#read 5, iclass 3, count 0 2006.210.07:50:37.58#ibcon#about to read 6, iclass 3, count 0 2006.210.07:50:37.58#ibcon#read 6, iclass 3, count 0 2006.210.07:50:37.58#ibcon#end of sib2, iclass 3, count 0 2006.210.07:50:37.58#ibcon#*after write, iclass 3, count 0 2006.210.07:50:37.58#ibcon#*before return 0, iclass 3, count 0 2006.210.07:50:37.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:37.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:37.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:50:37.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:50:37.58$vc4f8/va=1,8 2006.210.07:50:37.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:50:37.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:50:37.58#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:37.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:37.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:37.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:37.58#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:50:37.58#ibcon#first serial, iclass 5, count 2 2006.210.07:50:37.58#ibcon#enter sib2, iclass 5, count 2 2006.210.07:50:37.58#ibcon#flushed, iclass 5, count 2 2006.210.07:50:37.58#ibcon#about to write, iclass 5, count 2 2006.210.07:50:37.58#ibcon#wrote, iclass 5, count 2 2006.210.07:50:37.58#ibcon#about to read 3, iclass 5, count 2 2006.210.07:50:37.60#ibcon#read 3, iclass 5, count 2 2006.210.07:50:37.60#ibcon#about to read 4, iclass 5, count 2 2006.210.07:50:37.60#ibcon#read 4, iclass 5, count 2 2006.210.07:50:37.60#ibcon#about to read 5, iclass 5, count 2 2006.210.07:50:37.60#ibcon#read 5, iclass 5, count 2 2006.210.07:50:37.60#ibcon#about to read 6, iclass 5, count 2 2006.210.07:50:37.60#ibcon#read 6, iclass 5, count 2 2006.210.07:50:37.60#ibcon#end of sib2, iclass 5, count 2 2006.210.07:50:37.60#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:50:37.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:50:37.60#ibcon#[25=AT01-08\r\n] 2006.210.07:50:37.60#ibcon#*before write, iclass 5, count 2 2006.210.07:50:37.60#ibcon#enter sib2, iclass 5, count 2 2006.210.07:50:37.60#ibcon#flushed, iclass 5, count 2 2006.210.07:50:37.60#ibcon#about to write, iclass 5, count 2 2006.210.07:50:37.60#ibcon#wrote, iclass 5, count 2 2006.210.07:50:37.60#ibcon#about to read 3, iclass 5, count 2 2006.210.07:50:37.63#ibcon#read 3, iclass 5, count 2 2006.210.07:50:37.63#ibcon#about to read 4, iclass 5, count 2 2006.210.07:50:37.63#ibcon#read 4, iclass 5, count 2 2006.210.07:50:37.63#ibcon#about to read 5, iclass 5, count 2 2006.210.07:50:37.63#ibcon#read 5, iclass 5, count 2 2006.210.07:50:37.63#ibcon#about to read 6, iclass 5, count 2 2006.210.07:50:37.63#ibcon#read 6, iclass 5, count 2 2006.210.07:50:37.63#ibcon#end of sib2, iclass 5, count 2 2006.210.07:50:37.63#ibcon#*after write, iclass 5, count 2 2006.210.07:50:37.63#ibcon#*before return 0, iclass 5, count 2 2006.210.07:50:37.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:37.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:37.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:50:37.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:37.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:37.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:37.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:37.75#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:50:37.75#ibcon#first serial, iclass 5, count 0 2006.210.07:50:37.75#ibcon#enter sib2, iclass 5, count 0 2006.210.07:50:37.75#ibcon#flushed, iclass 5, count 0 2006.210.07:50:37.75#ibcon#about to write, iclass 5, count 0 2006.210.07:50:37.75#ibcon#wrote, iclass 5, count 0 2006.210.07:50:37.75#ibcon#about to read 3, iclass 5, count 0 2006.210.07:50:37.77#ibcon#read 3, iclass 5, count 0 2006.210.07:50:37.77#ibcon#about to read 4, iclass 5, count 0 2006.210.07:50:37.77#ibcon#read 4, iclass 5, count 0 2006.210.07:50:37.77#ibcon#about to read 5, iclass 5, count 0 2006.210.07:50:37.77#ibcon#read 5, iclass 5, count 0 2006.210.07:50:37.77#ibcon#about to read 6, iclass 5, count 0 2006.210.07:50:37.77#ibcon#read 6, iclass 5, count 0 2006.210.07:50:37.77#ibcon#end of sib2, iclass 5, count 0 2006.210.07:50:37.77#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:50:37.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:50:37.77#ibcon#[25=USB\r\n] 2006.210.07:50:37.77#ibcon#*before write, iclass 5, count 0 2006.210.07:50:37.77#ibcon#enter sib2, iclass 5, count 0 2006.210.07:50:37.77#ibcon#flushed, iclass 5, count 0 2006.210.07:50:37.77#ibcon#about to write, iclass 5, count 0 2006.210.07:50:37.77#ibcon#wrote, iclass 5, count 0 2006.210.07:50:37.77#ibcon#about to read 3, iclass 5, count 0 2006.210.07:50:37.80#ibcon#read 3, iclass 5, count 0 2006.210.07:50:37.80#ibcon#about to read 4, iclass 5, count 0 2006.210.07:50:37.80#ibcon#read 4, iclass 5, count 0 2006.210.07:50:37.80#ibcon#about to read 5, iclass 5, count 0 2006.210.07:50:37.80#ibcon#read 5, iclass 5, count 0 2006.210.07:50:37.80#ibcon#about to read 6, iclass 5, count 0 2006.210.07:50:37.80#ibcon#read 6, iclass 5, count 0 2006.210.07:50:37.80#ibcon#end of sib2, iclass 5, count 0 2006.210.07:50:37.80#ibcon#*after write, iclass 5, count 0 2006.210.07:50:37.80#ibcon#*before return 0, iclass 5, count 0 2006.210.07:50:37.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:37.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:37.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:50:37.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:50:37.80$vc4f8/valo=2,572.99 2006.210.07:50:37.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:50:37.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:50:37.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:37.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:37.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:37.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:37.80#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:50:37.80#ibcon#first serial, iclass 7, count 0 2006.210.07:50:37.80#ibcon#enter sib2, iclass 7, count 0 2006.210.07:50:37.80#ibcon#flushed, iclass 7, count 0 2006.210.07:50:37.80#ibcon#about to write, iclass 7, count 0 2006.210.07:50:37.80#ibcon#wrote, iclass 7, count 0 2006.210.07:50:37.80#ibcon#about to read 3, iclass 7, count 0 2006.210.07:50:37.82#ibcon#read 3, iclass 7, count 0 2006.210.07:50:37.82#ibcon#about to read 4, iclass 7, count 0 2006.210.07:50:37.82#ibcon#read 4, iclass 7, count 0 2006.210.07:50:37.82#ibcon#about to read 5, iclass 7, count 0 2006.210.07:50:37.82#ibcon#read 5, iclass 7, count 0 2006.210.07:50:37.82#ibcon#about to read 6, iclass 7, count 0 2006.210.07:50:37.82#ibcon#read 6, iclass 7, count 0 2006.210.07:50:37.82#ibcon#end of sib2, iclass 7, count 0 2006.210.07:50:37.82#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:50:37.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:50:37.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:50:37.82#ibcon#*before write, iclass 7, count 0 2006.210.07:50:37.82#ibcon#enter sib2, iclass 7, count 0 2006.210.07:50:37.82#ibcon#flushed, iclass 7, count 0 2006.210.07:50:37.82#ibcon#about to write, iclass 7, count 0 2006.210.07:50:37.82#ibcon#wrote, iclass 7, count 0 2006.210.07:50:37.82#ibcon#about to read 3, iclass 7, count 0 2006.210.07:50:37.86#ibcon#read 3, iclass 7, count 0 2006.210.07:50:37.86#ibcon#about to read 4, iclass 7, count 0 2006.210.07:50:37.86#ibcon#read 4, iclass 7, count 0 2006.210.07:50:37.86#ibcon#about to read 5, iclass 7, count 0 2006.210.07:50:37.86#ibcon#read 5, iclass 7, count 0 2006.210.07:50:37.86#ibcon#about to read 6, iclass 7, count 0 2006.210.07:50:37.86#ibcon#read 6, iclass 7, count 0 2006.210.07:50:37.86#ibcon#end of sib2, iclass 7, count 0 2006.210.07:50:37.86#ibcon#*after write, iclass 7, count 0 2006.210.07:50:37.86#ibcon#*before return 0, iclass 7, count 0 2006.210.07:50:37.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:37.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:37.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:50:37.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:50:37.86$vc4f8/va=2,7 2006.210.07:50:37.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:50:37.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:50:37.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:37.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:37.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:37.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:37.92#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:50:37.92#ibcon#first serial, iclass 11, count 2 2006.210.07:50:37.92#ibcon#enter sib2, iclass 11, count 2 2006.210.07:50:37.92#ibcon#flushed, iclass 11, count 2 2006.210.07:50:37.92#ibcon#about to write, iclass 11, count 2 2006.210.07:50:37.92#ibcon#wrote, iclass 11, count 2 2006.210.07:50:37.92#ibcon#about to read 3, iclass 11, count 2 2006.210.07:50:37.94#ibcon#read 3, iclass 11, count 2 2006.210.07:50:37.94#ibcon#about to read 4, iclass 11, count 2 2006.210.07:50:37.94#ibcon#read 4, iclass 11, count 2 2006.210.07:50:37.94#ibcon#about to read 5, iclass 11, count 2 2006.210.07:50:37.94#ibcon#read 5, iclass 11, count 2 2006.210.07:50:37.94#ibcon#about to read 6, iclass 11, count 2 2006.210.07:50:37.94#ibcon#read 6, iclass 11, count 2 2006.210.07:50:37.94#ibcon#end of sib2, iclass 11, count 2 2006.210.07:50:37.94#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:50:37.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:50:37.94#ibcon#[25=AT02-07\r\n] 2006.210.07:50:37.94#ibcon#*before write, iclass 11, count 2 2006.210.07:50:37.94#ibcon#enter sib2, iclass 11, count 2 2006.210.07:50:37.94#ibcon#flushed, iclass 11, count 2 2006.210.07:50:37.94#ibcon#about to write, iclass 11, count 2 2006.210.07:50:37.94#ibcon#wrote, iclass 11, count 2 2006.210.07:50:37.94#ibcon#about to read 3, iclass 11, count 2 2006.210.07:50:37.97#ibcon#read 3, iclass 11, count 2 2006.210.07:50:37.97#ibcon#about to read 4, iclass 11, count 2 2006.210.07:50:37.97#ibcon#read 4, iclass 11, count 2 2006.210.07:50:37.97#ibcon#about to read 5, iclass 11, count 2 2006.210.07:50:37.97#ibcon#read 5, iclass 11, count 2 2006.210.07:50:37.97#ibcon#about to read 6, iclass 11, count 2 2006.210.07:50:37.97#ibcon#read 6, iclass 11, count 2 2006.210.07:50:37.97#ibcon#end of sib2, iclass 11, count 2 2006.210.07:50:37.97#ibcon#*after write, iclass 11, count 2 2006.210.07:50:37.97#ibcon#*before return 0, iclass 11, count 2 2006.210.07:50:37.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:37.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:37.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:50:37.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:37.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:38.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:38.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:38.09#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:50:38.09#ibcon#first serial, iclass 11, count 0 2006.210.07:50:38.09#ibcon#enter sib2, iclass 11, count 0 2006.210.07:50:38.09#ibcon#flushed, iclass 11, count 0 2006.210.07:50:38.09#ibcon#about to write, iclass 11, count 0 2006.210.07:50:38.09#ibcon#wrote, iclass 11, count 0 2006.210.07:50:38.09#ibcon#about to read 3, iclass 11, count 0 2006.210.07:50:38.11#ibcon#read 3, iclass 11, count 0 2006.210.07:50:38.11#ibcon#about to read 4, iclass 11, count 0 2006.210.07:50:38.11#ibcon#read 4, iclass 11, count 0 2006.210.07:50:38.11#ibcon#about to read 5, iclass 11, count 0 2006.210.07:50:38.11#ibcon#read 5, iclass 11, count 0 2006.210.07:50:38.11#ibcon#about to read 6, iclass 11, count 0 2006.210.07:50:38.11#ibcon#read 6, iclass 11, count 0 2006.210.07:50:38.11#ibcon#end of sib2, iclass 11, count 0 2006.210.07:50:38.11#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:50:38.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:50:38.11#ibcon#[25=USB\r\n] 2006.210.07:50:38.11#ibcon#*before write, iclass 11, count 0 2006.210.07:50:38.11#ibcon#enter sib2, iclass 11, count 0 2006.210.07:50:38.11#ibcon#flushed, iclass 11, count 0 2006.210.07:50:38.11#ibcon#about to write, iclass 11, count 0 2006.210.07:50:38.11#ibcon#wrote, iclass 11, count 0 2006.210.07:50:38.11#ibcon#about to read 3, iclass 11, count 0 2006.210.07:50:38.14#ibcon#read 3, iclass 11, count 0 2006.210.07:50:38.14#ibcon#about to read 4, iclass 11, count 0 2006.210.07:50:38.14#ibcon#read 4, iclass 11, count 0 2006.210.07:50:38.14#ibcon#about to read 5, iclass 11, count 0 2006.210.07:50:38.14#ibcon#read 5, iclass 11, count 0 2006.210.07:50:38.14#ibcon#about to read 6, iclass 11, count 0 2006.210.07:50:38.14#ibcon#read 6, iclass 11, count 0 2006.210.07:50:38.14#ibcon#end of sib2, iclass 11, count 0 2006.210.07:50:38.14#ibcon#*after write, iclass 11, count 0 2006.210.07:50:38.14#ibcon#*before return 0, iclass 11, count 0 2006.210.07:50:38.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:38.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:38.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:50:38.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:50:38.14$vc4f8/valo=3,672.99 2006.210.07:50:38.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:50:38.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:50:38.14#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:38.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:38.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:38.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:38.14#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:50:38.14#ibcon#first serial, iclass 13, count 0 2006.210.07:50:38.14#ibcon#enter sib2, iclass 13, count 0 2006.210.07:50:38.14#ibcon#flushed, iclass 13, count 0 2006.210.07:50:38.14#ibcon#about to write, iclass 13, count 0 2006.210.07:50:38.14#ibcon#wrote, iclass 13, count 0 2006.210.07:50:38.14#ibcon#about to read 3, iclass 13, count 0 2006.210.07:50:38.16#ibcon#read 3, iclass 13, count 0 2006.210.07:50:38.16#ibcon#about to read 4, iclass 13, count 0 2006.210.07:50:38.16#ibcon#read 4, iclass 13, count 0 2006.210.07:50:38.16#ibcon#about to read 5, iclass 13, count 0 2006.210.07:50:38.16#ibcon#read 5, iclass 13, count 0 2006.210.07:50:38.16#ibcon#about to read 6, iclass 13, count 0 2006.210.07:50:38.16#ibcon#read 6, iclass 13, count 0 2006.210.07:50:38.16#ibcon#end of sib2, iclass 13, count 0 2006.210.07:50:38.16#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:50:38.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:50:38.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:50:38.16#ibcon#*before write, iclass 13, count 0 2006.210.07:50:38.16#ibcon#enter sib2, iclass 13, count 0 2006.210.07:50:38.16#ibcon#flushed, iclass 13, count 0 2006.210.07:50:38.16#ibcon#about to write, iclass 13, count 0 2006.210.07:50:38.16#ibcon#wrote, iclass 13, count 0 2006.210.07:50:38.16#ibcon#about to read 3, iclass 13, count 0 2006.210.07:50:38.20#ibcon#read 3, iclass 13, count 0 2006.210.07:50:38.20#ibcon#about to read 4, iclass 13, count 0 2006.210.07:50:38.20#ibcon#read 4, iclass 13, count 0 2006.210.07:50:38.20#ibcon#about to read 5, iclass 13, count 0 2006.210.07:50:38.20#ibcon#read 5, iclass 13, count 0 2006.210.07:50:38.20#ibcon#about to read 6, iclass 13, count 0 2006.210.07:50:38.20#ibcon#read 6, iclass 13, count 0 2006.210.07:50:38.20#ibcon#end of sib2, iclass 13, count 0 2006.210.07:50:38.20#ibcon#*after write, iclass 13, count 0 2006.210.07:50:38.20#ibcon#*before return 0, iclass 13, count 0 2006.210.07:50:38.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:38.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:38.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:50:38.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:50:38.20$vc4f8/va=3,6 2006.210.07:50:38.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:50:38.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:50:38.20#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:38.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:38.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:38.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:38.26#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:50:38.26#ibcon#first serial, iclass 15, count 2 2006.210.07:50:38.26#ibcon#enter sib2, iclass 15, count 2 2006.210.07:50:38.26#ibcon#flushed, iclass 15, count 2 2006.210.07:50:38.26#ibcon#about to write, iclass 15, count 2 2006.210.07:50:38.26#ibcon#wrote, iclass 15, count 2 2006.210.07:50:38.26#ibcon#about to read 3, iclass 15, count 2 2006.210.07:50:38.28#ibcon#read 3, iclass 15, count 2 2006.210.07:50:38.28#ibcon#about to read 4, iclass 15, count 2 2006.210.07:50:38.28#ibcon#read 4, iclass 15, count 2 2006.210.07:50:38.28#ibcon#about to read 5, iclass 15, count 2 2006.210.07:50:38.28#ibcon#read 5, iclass 15, count 2 2006.210.07:50:38.28#ibcon#about to read 6, iclass 15, count 2 2006.210.07:50:38.28#ibcon#read 6, iclass 15, count 2 2006.210.07:50:38.28#ibcon#end of sib2, iclass 15, count 2 2006.210.07:50:38.28#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:50:38.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:50:38.28#ibcon#[25=AT03-06\r\n] 2006.210.07:50:38.28#ibcon#*before write, iclass 15, count 2 2006.210.07:50:38.28#ibcon#enter sib2, iclass 15, count 2 2006.210.07:50:38.28#ibcon#flushed, iclass 15, count 2 2006.210.07:50:38.28#ibcon#about to write, iclass 15, count 2 2006.210.07:50:38.28#ibcon#wrote, iclass 15, count 2 2006.210.07:50:38.28#ibcon#about to read 3, iclass 15, count 2 2006.210.07:50:38.31#ibcon#read 3, iclass 15, count 2 2006.210.07:50:38.31#ibcon#about to read 4, iclass 15, count 2 2006.210.07:50:38.31#ibcon#read 4, iclass 15, count 2 2006.210.07:50:38.31#ibcon#about to read 5, iclass 15, count 2 2006.210.07:50:38.31#ibcon#read 5, iclass 15, count 2 2006.210.07:50:38.31#ibcon#about to read 6, iclass 15, count 2 2006.210.07:50:38.31#ibcon#read 6, iclass 15, count 2 2006.210.07:50:38.31#ibcon#end of sib2, iclass 15, count 2 2006.210.07:50:38.31#ibcon#*after write, iclass 15, count 2 2006.210.07:50:38.31#ibcon#*before return 0, iclass 15, count 2 2006.210.07:50:38.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:38.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:38.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:50:38.31#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:38.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:38.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:38.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:38.43#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:50:38.43#ibcon#first serial, iclass 15, count 0 2006.210.07:50:38.43#ibcon#enter sib2, iclass 15, count 0 2006.210.07:50:38.43#ibcon#flushed, iclass 15, count 0 2006.210.07:50:38.43#ibcon#about to write, iclass 15, count 0 2006.210.07:50:38.43#ibcon#wrote, iclass 15, count 0 2006.210.07:50:38.43#ibcon#about to read 3, iclass 15, count 0 2006.210.07:50:38.45#ibcon#read 3, iclass 15, count 0 2006.210.07:50:38.45#ibcon#about to read 4, iclass 15, count 0 2006.210.07:50:38.45#ibcon#read 4, iclass 15, count 0 2006.210.07:50:38.45#ibcon#about to read 5, iclass 15, count 0 2006.210.07:50:38.45#ibcon#read 5, iclass 15, count 0 2006.210.07:50:38.45#ibcon#about to read 6, iclass 15, count 0 2006.210.07:50:38.45#ibcon#read 6, iclass 15, count 0 2006.210.07:50:38.45#ibcon#end of sib2, iclass 15, count 0 2006.210.07:50:38.45#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:50:38.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:50:38.45#ibcon#[25=USB\r\n] 2006.210.07:50:38.45#ibcon#*before write, iclass 15, count 0 2006.210.07:50:38.45#ibcon#enter sib2, iclass 15, count 0 2006.210.07:50:38.45#ibcon#flushed, iclass 15, count 0 2006.210.07:50:38.45#ibcon#about to write, iclass 15, count 0 2006.210.07:50:38.45#ibcon#wrote, iclass 15, count 0 2006.210.07:50:38.45#ibcon#about to read 3, iclass 15, count 0 2006.210.07:50:38.48#ibcon#read 3, iclass 15, count 0 2006.210.07:50:38.48#ibcon#about to read 4, iclass 15, count 0 2006.210.07:50:38.48#ibcon#read 4, iclass 15, count 0 2006.210.07:50:38.48#ibcon#about to read 5, iclass 15, count 0 2006.210.07:50:38.48#ibcon#read 5, iclass 15, count 0 2006.210.07:50:38.48#ibcon#about to read 6, iclass 15, count 0 2006.210.07:50:38.48#ibcon#read 6, iclass 15, count 0 2006.210.07:50:38.48#ibcon#end of sib2, iclass 15, count 0 2006.210.07:50:38.48#ibcon#*after write, iclass 15, count 0 2006.210.07:50:38.48#ibcon#*before return 0, iclass 15, count 0 2006.210.07:50:38.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:38.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:38.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:50:38.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:50:38.48$vc4f8/valo=4,832.99 2006.210.07:50:38.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:50:38.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:50:38.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:38.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:38.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:38.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:38.48#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:50:38.48#ibcon#first serial, iclass 17, count 0 2006.210.07:50:38.48#ibcon#enter sib2, iclass 17, count 0 2006.210.07:50:38.48#ibcon#flushed, iclass 17, count 0 2006.210.07:50:38.48#ibcon#about to write, iclass 17, count 0 2006.210.07:50:38.48#ibcon#wrote, iclass 17, count 0 2006.210.07:50:38.48#ibcon#about to read 3, iclass 17, count 0 2006.210.07:50:38.50#ibcon#read 3, iclass 17, count 0 2006.210.07:50:38.50#ibcon#about to read 4, iclass 17, count 0 2006.210.07:50:38.50#ibcon#read 4, iclass 17, count 0 2006.210.07:50:38.50#ibcon#about to read 5, iclass 17, count 0 2006.210.07:50:38.50#ibcon#read 5, iclass 17, count 0 2006.210.07:50:38.50#ibcon#about to read 6, iclass 17, count 0 2006.210.07:50:38.50#ibcon#read 6, iclass 17, count 0 2006.210.07:50:38.50#ibcon#end of sib2, iclass 17, count 0 2006.210.07:50:38.50#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:50:38.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:50:38.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:50:38.50#ibcon#*before write, iclass 17, count 0 2006.210.07:50:38.50#ibcon#enter sib2, iclass 17, count 0 2006.210.07:50:38.50#ibcon#flushed, iclass 17, count 0 2006.210.07:50:38.50#ibcon#about to write, iclass 17, count 0 2006.210.07:50:38.50#ibcon#wrote, iclass 17, count 0 2006.210.07:50:38.50#ibcon#about to read 3, iclass 17, count 0 2006.210.07:50:38.54#ibcon#read 3, iclass 17, count 0 2006.210.07:50:38.54#ibcon#about to read 4, iclass 17, count 0 2006.210.07:50:38.54#ibcon#read 4, iclass 17, count 0 2006.210.07:50:38.54#ibcon#about to read 5, iclass 17, count 0 2006.210.07:50:38.54#ibcon#read 5, iclass 17, count 0 2006.210.07:50:38.54#ibcon#about to read 6, iclass 17, count 0 2006.210.07:50:38.54#ibcon#read 6, iclass 17, count 0 2006.210.07:50:38.54#ibcon#end of sib2, iclass 17, count 0 2006.210.07:50:38.54#ibcon#*after write, iclass 17, count 0 2006.210.07:50:38.54#ibcon#*before return 0, iclass 17, count 0 2006.210.07:50:38.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:38.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:38.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:50:38.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:50:38.54$vc4f8/va=4,7 2006.210.07:50:38.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:50:38.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:50:38.54#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:38.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:38.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:38.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:38.60#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:50:38.60#ibcon#first serial, iclass 19, count 2 2006.210.07:50:38.60#ibcon#enter sib2, iclass 19, count 2 2006.210.07:50:38.60#ibcon#flushed, iclass 19, count 2 2006.210.07:50:38.60#ibcon#about to write, iclass 19, count 2 2006.210.07:50:38.60#ibcon#wrote, iclass 19, count 2 2006.210.07:50:38.60#ibcon#about to read 3, iclass 19, count 2 2006.210.07:50:38.62#ibcon#read 3, iclass 19, count 2 2006.210.07:50:38.62#ibcon#about to read 4, iclass 19, count 2 2006.210.07:50:38.62#ibcon#read 4, iclass 19, count 2 2006.210.07:50:38.62#ibcon#about to read 5, iclass 19, count 2 2006.210.07:50:38.62#ibcon#read 5, iclass 19, count 2 2006.210.07:50:38.62#ibcon#about to read 6, iclass 19, count 2 2006.210.07:50:38.62#ibcon#read 6, iclass 19, count 2 2006.210.07:50:38.62#ibcon#end of sib2, iclass 19, count 2 2006.210.07:50:38.62#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:50:38.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:50:38.62#ibcon#[25=AT04-07\r\n] 2006.210.07:50:38.62#ibcon#*before write, iclass 19, count 2 2006.210.07:50:38.62#ibcon#enter sib2, iclass 19, count 2 2006.210.07:50:38.62#ibcon#flushed, iclass 19, count 2 2006.210.07:50:38.62#ibcon#about to write, iclass 19, count 2 2006.210.07:50:38.62#ibcon#wrote, iclass 19, count 2 2006.210.07:50:38.62#ibcon#about to read 3, iclass 19, count 2 2006.210.07:50:38.65#ibcon#read 3, iclass 19, count 2 2006.210.07:50:38.65#ibcon#about to read 4, iclass 19, count 2 2006.210.07:50:38.65#ibcon#read 4, iclass 19, count 2 2006.210.07:50:38.65#ibcon#about to read 5, iclass 19, count 2 2006.210.07:50:38.65#ibcon#read 5, iclass 19, count 2 2006.210.07:50:38.65#ibcon#about to read 6, iclass 19, count 2 2006.210.07:50:38.65#ibcon#read 6, iclass 19, count 2 2006.210.07:50:38.65#ibcon#end of sib2, iclass 19, count 2 2006.210.07:50:38.65#ibcon#*after write, iclass 19, count 2 2006.210.07:50:38.65#ibcon#*before return 0, iclass 19, count 2 2006.210.07:50:38.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:38.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:38.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:50:38.65#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:38.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:38.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:38.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:38.77#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:50:38.77#ibcon#first serial, iclass 19, count 0 2006.210.07:50:38.77#ibcon#enter sib2, iclass 19, count 0 2006.210.07:50:38.77#ibcon#flushed, iclass 19, count 0 2006.210.07:50:38.77#ibcon#about to write, iclass 19, count 0 2006.210.07:50:38.77#ibcon#wrote, iclass 19, count 0 2006.210.07:50:38.77#ibcon#about to read 3, iclass 19, count 0 2006.210.07:50:38.79#ibcon#read 3, iclass 19, count 0 2006.210.07:50:38.79#ibcon#about to read 4, iclass 19, count 0 2006.210.07:50:38.79#ibcon#read 4, iclass 19, count 0 2006.210.07:50:38.79#ibcon#about to read 5, iclass 19, count 0 2006.210.07:50:38.79#ibcon#read 5, iclass 19, count 0 2006.210.07:50:38.79#ibcon#about to read 6, iclass 19, count 0 2006.210.07:50:38.79#ibcon#read 6, iclass 19, count 0 2006.210.07:50:38.79#ibcon#end of sib2, iclass 19, count 0 2006.210.07:50:38.79#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:50:38.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:50:38.79#ibcon#[25=USB\r\n] 2006.210.07:50:38.79#ibcon#*before write, iclass 19, count 0 2006.210.07:50:38.79#ibcon#enter sib2, iclass 19, count 0 2006.210.07:50:38.79#ibcon#flushed, iclass 19, count 0 2006.210.07:50:38.79#ibcon#about to write, iclass 19, count 0 2006.210.07:50:38.79#ibcon#wrote, iclass 19, count 0 2006.210.07:50:38.79#ibcon#about to read 3, iclass 19, count 0 2006.210.07:50:38.82#ibcon#read 3, iclass 19, count 0 2006.210.07:50:38.82#ibcon#about to read 4, iclass 19, count 0 2006.210.07:50:38.82#ibcon#read 4, iclass 19, count 0 2006.210.07:50:38.82#ibcon#about to read 5, iclass 19, count 0 2006.210.07:50:38.82#ibcon#read 5, iclass 19, count 0 2006.210.07:50:38.82#ibcon#about to read 6, iclass 19, count 0 2006.210.07:50:38.82#ibcon#read 6, iclass 19, count 0 2006.210.07:50:38.82#ibcon#end of sib2, iclass 19, count 0 2006.210.07:50:38.82#ibcon#*after write, iclass 19, count 0 2006.210.07:50:38.82#ibcon#*before return 0, iclass 19, count 0 2006.210.07:50:38.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:38.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:38.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:50:38.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:50:38.82$vc4f8/valo=5,652.99 2006.210.07:50:38.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:50:38.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:50:38.82#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:38.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:38.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:38.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:38.82#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:50:38.82#ibcon#first serial, iclass 21, count 0 2006.210.07:50:38.82#ibcon#enter sib2, iclass 21, count 0 2006.210.07:50:38.82#ibcon#flushed, iclass 21, count 0 2006.210.07:50:38.82#ibcon#about to write, iclass 21, count 0 2006.210.07:50:38.82#ibcon#wrote, iclass 21, count 0 2006.210.07:50:38.82#ibcon#about to read 3, iclass 21, count 0 2006.210.07:50:38.84#ibcon#read 3, iclass 21, count 0 2006.210.07:50:38.84#ibcon#about to read 4, iclass 21, count 0 2006.210.07:50:38.84#ibcon#read 4, iclass 21, count 0 2006.210.07:50:38.84#ibcon#about to read 5, iclass 21, count 0 2006.210.07:50:38.84#ibcon#read 5, iclass 21, count 0 2006.210.07:50:38.84#ibcon#about to read 6, iclass 21, count 0 2006.210.07:50:38.84#ibcon#read 6, iclass 21, count 0 2006.210.07:50:38.84#ibcon#end of sib2, iclass 21, count 0 2006.210.07:50:38.84#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:50:38.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:50:38.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:50:38.84#ibcon#*before write, iclass 21, count 0 2006.210.07:50:38.84#ibcon#enter sib2, iclass 21, count 0 2006.210.07:50:38.84#ibcon#flushed, iclass 21, count 0 2006.210.07:50:38.84#ibcon#about to write, iclass 21, count 0 2006.210.07:50:38.84#ibcon#wrote, iclass 21, count 0 2006.210.07:50:38.84#ibcon#about to read 3, iclass 21, count 0 2006.210.07:50:38.88#ibcon#read 3, iclass 21, count 0 2006.210.07:50:38.88#ibcon#about to read 4, iclass 21, count 0 2006.210.07:50:38.88#ibcon#read 4, iclass 21, count 0 2006.210.07:50:38.88#ibcon#about to read 5, iclass 21, count 0 2006.210.07:50:38.88#ibcon#read 5, iclass 21, count 0 2006.210.07:50:38.88#ibcon#about to read 6, iclass 21, count 0 2006.210.07:50:38.88#ibcon#read 6, iclass 21, count 0 2006.210.07:50:38.88#ibcon#end of sib2, iclass 21, count 0 2006.210.07:50:38.88#ibcon#*after write, iclass 21, count 0 2006.210.07:50:38.88#ibcon#*before return 0, iclass 21, count 0 2006.210.07:50:38.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:38.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:38.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:50:38.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:50:38.88$vc4f8/va=5,7 2006.210.07:50:38.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.07:50:38.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.07:50:38.88#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:38.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:38.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:38.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:38.94#ibcon#enter wrdev, iclass 23, count 2 2006.210.07:50:38.94#ibcon#first serial, iclass 23, count 2 2006.210.07:50:38.94#ibcon#enter sib2, iclass 23, count 2 2006.210.07:50:38.94#ibcon#flushed, iclass 23, count 2 2006.210.07:50:38.94#ibcon#about to write, iclass 23, count 2 2006.210.07:50:38.94#ibcon#wrote, iclass 23, count 2 2006.210.07:50:38.94#ibcon#about to read 3, iclass 23, count 2 2006.210.07:50:38.96#ibcon#read 3, iclass 23, count 2 2006.210.07:50:38.96#ibcon#about to read 4, iclass 23, count 2 2006.210.07:50:38.96#ibcon#read 4, iclass 23, count 2 2006.210.07:50:38.96#ibcon#about to read 5, iclass 23, count 2 2006.210.07:50:38.96#ibcon#read 5, iclass 23, count 2 2006.210.07:50:38.96#ibcon#about to read 6, iclass 23, count 2 2006.210.07:50:38.96#ibcon#read 6, iclass 23, count 2 2006.210.07:50:38.96#ibcon#end of sib2, iclass 23, count 2 2006.210.07:50:38.96#ibcon#*mode == 0, iclass 23, count 2 2006.210.07:50:38.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.07:50:38.96#ibcon#[25=AT05-07\r\n] 2006.210.07:50:38.96#ibcon#*before write, iclass 23, count 2 2006.210.07:50:38.96#ibcon#enter sib2, iclass 23, count 2 2006.210.07:50:38.96#ibcon#flushed, iclass 23, count 2 2006.210.07:50:38.96#ibcon#about to write, iclass 23, count 2 2006.210.07:50:38.96#ibcon#wrote, iclass 23, count 2 2006.210.07:50:38.96#ibcon#about to read 3, iclass 23, count 2 2006.210.07:50:38.99#ibcon#read 3, iclass 23, count 2 2006.210.07:50:38.99#ibcon#about to read 4, iclass 23, count 2 2006.210.07:50:38.99#ibcon#read 4, iclass 23, count 2 2006.210.07:50:38.99#ibcon#about to read 5, iclass 23, count 2 2006.210.07:50:38.99#ibcon#read 5, iclass 23, count 2 2006.210.07:50:38.99#ibcon#about to read 6, iclass 23, count 2 2006.210.07:50:38.99#ibcon#read 6, iclass 23, count 2 2006.210.07:50:38.99#ibcon#end of sib2, iclass 23, count 2 2006.210.07:50:38.99#ibcon#*after write, iclass 23, count 2 2006.210.07:50:38.99#ibcon#*before return 0, iclass 23, count 2 2006.210.07:50:38.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:38.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:38.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.07:50:38.99#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:38.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:39.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:39.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:39.11#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:50:39.11#ibcon#first serial, iclass 23, count 0 2006.210.07:50:39.11#ibcon#enter sib2, iclass 23, count 0 2006.210.07:50:39.11#ibcon#flushed, iclass 23, count 0 2006.210.07:50:39.11#ibcon#about to write, iclass 23, count 0 2006.210.07:50:39.11#ibcon#wrote, iclass 23, count 0 2006.210.07:50:39.11#ibcon#about to read 3, iclass 23, count 0 2006.210.07:50:39.13#ibcon#read 3, iclass 23, count 0 2006.210.07:50:39.13#ibcon#about to read 4, iclass 23, count 0 2006.210.07:50:39.13#ibcon#read 4, iclass 23, count 0 2006.210.07:50:39.13#ibcon#about to read 5, iclass 23, count 0 2006.210.07:50:39.13#ibcon#read 5, iclass 23, count 0 2006.210.07:50:39.13#ibcon#about to read 6, iclass 23, count 0 2006.210.07:50:39.13#ibcon#read 6, iclass 23, count 0 2006.210.07:50:39.13#ibcon#end of sib2, iclass 23, count 0 2006.210.07:50:39.13#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:50:39.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:50:39.13#ibcon#[25=USB\r\n] 2006.210.07:50:39.13#ibcon#*before write, iclass 23, count 0 2006.210.07:50:39.13#ibcon#enter sib2, iclass 23, count 0 2006.210.07:50:39.13#ibcon#flushed, iclass 23, count 0 2006.210.07:50:39.13#ibcon#about to write, iclass 23, count 0 2006.210.07:50:39.13#ibcon#wrote, iclass 23, count 0 2006.210.07:50:39.13#ibcon#about to read 3, iclass 23, count 0 2006.210.07:50:39.16#ibcon#read 3, iclass 23, count 0 2006.210.07:50:39.16#ibcon#about to read 4, iclass 23, count 0 2006.210.07:50:39.16#ibcon#read 4, iclass 23, count 0 2006.210.07:50:39.16#ibcon#about to read 5, iclass 23, count 0 2006.210.07:50:39.16#ibcon#read 5, iclass 23, count 0 2006.210.07:50:39.16#ibcon#about to read 6, iclass 23, count 0 2006.210.07:50:39.16#ibcon#read 6, iclass 23, count 0 2006.210.07:50:39.16#ibcon#end of sib2, iclass 23, count 0 2006.210.07:50:39.16#ibcon#*after write, iclass 23, count 0 2006.210.07:50:39.16#ibcon#*before return 0, iclass 23, count 0 2006.210.07:50:39.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:39.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:39.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:50:39.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:50:39.16$vc4f8/valo=6,772.99 2006.210.07:50:39.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.07:50:39.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.07:50:39.16#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:39.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:39.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:39.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:39.16#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:50:39.16#ibcon#first serial, iclass 25, count 0 2006.210.07:50:39.16#ibcon#enter sib2, iclass 25, count 0 2006.210.07:50:39.16#ibcon#flushed, iclass 25, count 0 2006.210.07:50:39.16#ibcon#about to write, iclass 25, count 0 2006.210.07:50:39.16#ibcon#wrote, iclass 25, count 0 2006.210.07:50:39.16#ibcon#about to read 3, iclass 25, count 0 2006.210.07:50:39.18#ibcon#read 3, iclass 25, count 0 2006.210.07:50:39.18#ibcon#about to read 4, iclass 25, count 0 2006.210.07:50:39.18#ibcon#read 4, iclass 25, count 0 2006.210.07:50:39.18#ibcon#about to read 5, iclass 25, count 0 2006.210.07:50:39.18#ibcon#read 5, iclass 25, count 0 2006.210.07:50:39.18#ibcon#about to read 6, iclass 25, count 0 2006.210.07:50:39.18#ibcon#read 6, iclass 25, count 0 2006.210.07:50:39.18#ibcon#end of sib2, iclass 25, count 0 2006.210.07:50:39.18#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:50:39.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:50:39.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:50:39.18#ibcon#*before write, iclass 25, count 0 2006.210.07:50:39.18#ibcon#enter sib2, iclass 25, count 0 2006.210.07:50:39.18#ibcon#flushed, iclass 25, count 0 2006.210.07:50:39.18#ibcon#about to write, iclass 25, count 0 2006.210.07:50:39.18#ibcon#wrote, iclass 25, count 0 2006.210.07:50:39.18#ibcon#about to read 3, iclass 25, count 0 2006.210.07:50:39.22#ibcon#read 3, iclass 25, count 0 2006.210.07:50:39.22#ibcon#about to read 4, iclass 25, count 0 2006.210.07:50:39.22#ibcon#read 4, iclass 25, count 0 2006.210.07:50:39.22#ibcon#about to read 5, iclass 25, count 0 2006.210.07:50:39.22#ibcon#read 5, iclass 25, count 0 2006.210.07:50:39.22#ibcon#about to read 6, iclass 25, count 0 2006.210.07:50:39.22#ibcon#read 6, iclass 25, count 0 2006.210.07:50:39.22#ibcon#end of sib2, iclass 25, count 0 2006.210.07:50:39.22#ibcon#*after write, iclass 25, count 0 2006.210.07:50:39.22#ibcon#*before return 0, iclass 25, count 0 2006.210.07:50:39.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:39.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:39.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:50:39.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:50:39.22$vc4f8/va=6,6 2006.210.07:50:39.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.07:50:39.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.07:50:39.22#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:39.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:50:39.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:50:39.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:50:39.28#ibcon#enter wrdev, iclass 27, count 2 2006.210.07:50:39.28#ibcon#first serial, iclass 27, count 2 2006.210.07:50:39.28#ibcon#enter sib2, iclass 27, count 2 2006.210.07:50:39.28#ibcon#flushed, iclass 27, count 2 2006.210.07:50:39.28#ibcon#about to write, iclass 27, count 2 2006.210.07:50:39.28#ibcon#wrote, iclass 27, count 2 2006.210.07:50:39.28#ibcon#about to read 3, iclass 27, count 2 2006.210.07:50:39.30#ibcon#read 3, iclass 27, count 2 2006.210.07:50:39.30#ibcon#about to read 4, iclass 27, count 2 2006.210.07:50:39.30#ibcon#read 4, iclass 27, count 2 2006.210.07:50:39.30#ibcon#about to read 5, iclass 27, count 2 2006.210.07:50:39.30#ibcon#read 5, iclass 27, count 2 2006.210.07:50:39.30#ibcon#about to read 6, iclass 27, count 2 2006.210.07:50:39.30#ibcon#read 6, iclass 27, count 2 2006.210.07:50:39.30#ibcon#end of sib2, iclass 27, count 2 2006.210.07:50:39.30#ibcon#*mode == 0, iclass 27, count 2 2006.210.07:50:39.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.07:50:39.30#ibcon#[25=AT06-06\r\n] 2006.210.07:50:39.30#ibcon#*before write, iclass 27, count 2 2006.210.07:50:39.30#ibcon#enter sib2, iclass 27, count 2 2006.210.07:50:39.30#ibcon#flushed, iclass 27, count 2 2006.210.07:50:39.30#ibcon#about to write, iclass 27, count 2 2006.210.07:50:39.30#ibcon#wrote, iclass 27, count 2 2006.210.07:50:39.30#ibcon#about to read 3, iclass 27, count 2 2006.210.07:50:39.33#ibcon#read 3, iclass 27, count 2 2006.210.07:50:39.33#ibcon#about to read 4, iclass 27, count 2 2006.210.07:50:39.33#ibcon#read 4, iclass 27, count 2 2006.210.07:50:39.33#ibcon#about to read 5, iclass 27, count 2 2006.210.07:50:39.33#ibcon#read 5, iclass 27, count 2 2006.210.07:50:39.33#ibcon#about to read 6, iclass 27, count 2 2006.210.07:50:39.33#ibcon#read 6, iclass 27, count 2 2006.210.07:50:39.33#ibcon#end of sib2, iclass 27, count 2 2006.210.07:50:39.33#ibcon#*after write, iclass 27, count 2 2006.210.07:50:39.33#ibcon#*before return 0, iclass 27, count 2 2006.210.07:50:39.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:50:39.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.07:50:39.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.07:50:39.33#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:39.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:50:39.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:50:39.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:50:39.45#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:50:39.45#ibcon#first serial, iclass 27, count 0 2006.210.07:50:39.45#ibcon#enter sib2, iclass 27, count 0 2006.210.07:50:39.45#ibcon#flushed, iclass 27, count 0 2006.210.07:50:39.45#ibcon#about to write, iclass 27, count 0 2006.210.07:50:39.45#ibcon#wrote, iclass 27, count 0 2006.210.07:50:39.45#ibcon#about to read 3, iclass 27, count 0 2006.210.07:50:39.47#ibcon#read 3, iclass 27, count 0 2006.210.07:50:39.47#ibcon#about to read 4, iclass 27, count 0 2006.210.07:50:39.47#ibcon#read 4, iclass 27, count 0 2006.210.07:50:39.47#ibcon#about to read 5, iclass 27, count 0 2006.210.07:50:39.47#ibcon#read 5, iclass 27, count 0 2006.210.07:50:39.47#ibcon#about to read 6, iclass 27, count 0 2006.210.07:50:39.47#ibcon#read 6, iclass 27, count 0 2006.210.07:50:39.47#ibcon#end of sib2, iclass 27, count 0 2006.210.07:50:39.47#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:50:39.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:50:39.47#ibcon#[25=USB\r\n] 2006.210.07:50:39.47#ibcon#*before write, iclass 27, count 0 2006.210.07:50:39.47#ibcon#enter sib2, iclass 27, count 0 2006.210.07:50:39.47#ibcon#flushed, iclass 27, count 0 2006.210.07:50:39.47#ibcon#about to write, iclass 27, count 0 2006.210.07:50:39.47#ibcon#wrote, iclass 27, count 0 2006.210.07:50:39.47#ibcon#about to read 3, iclass 27, count 0 2006.210.07:50:39.50#ibcon#read 3, iclass 27, count 0 2006.210.07:50:39.50#ibcon#about to read 4, iclass 27, count 0 2006.210.07:50:39.50#ibcon#read 4, iclass 27, count 0 2006.210.07:50:39.50#ibcon#about to read 5, iclass 27, count 0 2006.210.07:50:39.50#ibcon#read 5, iclass 27, count 0 2006.210.07:50:39.50#ibcon#about to read 6, iclass 27, count 0 2006.210.07:50:39.50#ibcon#read 6, iclass 27, count 0 2006.210.07:50:39.50#ibcon#end of sib2, iclass 27, count 0 2006.210.07:50:39.50#ibcon#*after write, iclass 27, count 0 2006.210.07:50:39.50#ibcon#*before return 0, iclass 27, count 0 2006.210.07:50:39.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:50:39.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.07:50:39.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:50:39.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:50:39.50$vc4f8/valo=7,832.99 2006.210.07:50:39.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.07:50:39.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.07:50:39.50#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:39.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:50:39.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:50:39.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:50:39.50#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:50:39.50#ibcon#first serial, iclass 29, count 0 2006.210.07:50:39.50#ibcon#enter sib2, iclass 29, count 0 2006.210.07:50:39.50#ibcon#flushed, iclass 29, count 0 2006.210.07:50:39.50#ibcon#about to write, iclass 29, count 0 2006.210.07:50:39.50#ibcon#wrote, iclass 29, count 0 2006.210.07:50:39.50#ibcon#about to read 3, iclass 29, count 0 2006.210.07:50:39.52#ibcon#read 3, iclass 29, count 0 2006.210.07:50:39.52#ibcon#about to read 4, iclass 29, count 0 2006.210.07:50:39.52#ibcon#read 4, iclass 29, count 0 2006.210.07:50:39.52#ibcon#about to read 5, iclass 29, count 0 2006.210.07:50:39.52#ibcon#read 5, iclass 29, count 0 2006.210.07:50:39.52#ibcon#about to read 6, iclass 29, count 0 2006.210.07:50:39.52#ibcon#read 6, iclass 29, count 0 2006.210.07:50:39.52#ibcon#end of sib2, iclass 29, count 0 2006.210.07:50:39.52#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:50:39.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:50:39.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:50:39.52#ibcon#*before write, iclass 29, count 0 2006.210.07:50:39.52#ibcon#enter sib2, iclass 29, count 0 2006.210.07:50:39.52#ibcon#flushed, iclass 29, count 0 2006.210.07:50:39.52#ibcon#about to write, iclass 29, count 0 2006.210.07:50:39.52#ibcon#wrote, iclass 29, count 0 2006.210.07:50:39.52#ibcon#about to read 3, iclass 29, count 0 2006.210.07:50:39.56#ibcon#read 3, iclass 29, count 0 2006.210.07:50:39.56#ibcon#about to read 4, iclass 29, count 0 2006.210.07:50:39.56#ibcon#read 4, iclass 29, count 0 2006.210.07:50:39.56#ibcon#about to read 5, iclass 29, count 0 2006.210.07:50:39.56#ibcon#read 5, iclass 29, count 0 2006.210.07:50:39.56#ibcon#about to read 6, iclass 29, count 0 2006.210.07:50:39.56#ibcon#read 6, iclass 29, count 0 2006.210.07:50:39.56#ibcon#end of sib2, iclass 29, count 0 2006.210.07:50:39.56#ibcon#*after write, iclass 29, count 0 2006.210.07:50:39.56#ibcon#*before return 0, iclass 29, count 0 2006.210.07:50:39.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:50:39.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.07:50:39.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:50:39.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:50:39.56$vc4f8/va=7,6 2006.210.07:50:39.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.07:50:39.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.07:50:39.56#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:39.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:50:39.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:50:39.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:50:39.62#ibcon#enter wrdev, iclass 31, count 2 2006.210.07:50:39.62#ibcon#first serial, iclass 31, count 2 2006.210.07:50:39.62#ibcon#enter sib2, iclass 31, count 2 2006.210.07:50:39.62#ibcon#flushed, iclass 31, count 2 2006.210.07:50:39.62#ibcon#about to write, iclass 31, count 2 2006.210.07:50:39.62#ibcon#wrote, iclass 31, count 2 2006.210.07:50:39.62#ibcon#about to read 3, iclass 31, count 2 2006.210.07:50:39.64#ibcon#read 3, iclass 31, count 2 2006.210.07:50:39.64#ibcon#about to read 4, iclass 31, count 2 2006.210.07:50:39.64#ibcon#read 4, iclass 31, count 2 2006.210.07:50:39.64#ibcon#about to read 5, iclass 31, count 2 2006.210.07:50:39.64#ibcon#read 5, iclass 31, count 2 2006.210.07:50:39.64#ibcon#about to read 6, iclass 31, count 2 2006.210.07:50:39.64#ibcon#read 6, iclass 31, count 2 2006.210.07:50:39.64#ibcon#end of sib2, iclass 31, count 2 2006.210.07:50:39.64#ibcon#*mode == 0, iclass 31, count 2 2006.210.07:50:39.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.07:50:39.64#ibcon#[25=AT07-06\r\n] 2006.210.07:50:39.64#ibcon#*before write, iclass 31, count 2 2006.210.07:50:39.64#ibcon#enter sib2, iclass 31, count 2 2006.210.07:50:39.64#ibcon#flushed, iclass 31, count 2 2006.210.07:50:39.64#ibcon#about to write, iclass 31, count 2 2006.210.07:50:39.64#ibcon#wrote, iclass 31, count 2 2006.210.07:50:39.64#ibcon#about to read 3, iclass 31, count 2 2006.210.07:50:39.67#ibcon#read 3, iclass 31, count 2 2006.210.07:50:39.67#ibcon#about to read 4, iclass 31, count 2 2006.210.07:50:39.67#ibcon#read 4, iclass 31, count 2 2006.210.07:50:39.67#ibcon#about to read 5, iclass 31, count 2 2006.210.07:50:39.67#ibcon#read 5, iclass 31, count 2 2006.210.07:50:39.67#ibcon#about to read 6, iclass 31, count 2 2006.210.07:50:39.67#ibcon#read 6, iclass 31, count 2 2006.210.07:50:39.67#ibcon#end of sib2, iclass 31, count 2 2006.210.07:50:39.67#ibcon#*after write, iclass 31, count 2 2006.210.07:50:39.67#ibcon#*before return 0, iclass 31, count 2 2006.210.07:50:39.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:50:39.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.07:50:39.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.07:50:39.67#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:39.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:50:39.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:50:39.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:50:39.79#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:50:39.79#ibcon#first serial, iclass 31, count 0 2006.210.07:50:39.79#ibcon#enter sib2, iclass 31, count 0 2006.210.07:50:39.79#ibcon#flushed, iclass 31, count 0 2006.210.07:50:39.79#ibcon#about to write, iclass 31, count 0 2006.210.07:50:39.79#ibcon#wrote, iclass 31, count 0 2006.210.07:50:39.79#ibcon#about to read 3, iclass 31, count 0 2006.210.07:50:39.81#ibcon#read 3, iclass 31, count 0 2006.210.07:50:39.81#ibcon#about to read 4, iclass 31, count 0 2006.210.07:50:39.81#ibcon#read 4, iclass 31, count 0 2006.210.07:50:39.81#ibcon#about to read 5, iclass 31, count 0 2006.210.07:50:39.81#ibcon#read 5, iclass 31, count 0 2006.210.07:50:39.81#ibcon#about to read 6, iclass 31, count 0 2006.210.07:50:39.81#ibcon#read 6, iclass 31, count 0 2006.210.07:50:39.81#ibcon#end of sib2, iclass 31, count 0 2006.210.07:50:39.81#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:50:39.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:50:39.81#ibcon#[25=USB\r\n] 2006.210.07:50:39.81#ibcon#*before write, iclass 31, count 0 2006.210.07:50:39.81#ibcon#enter sib2, iclass 31, count 0 2006.210.07:50:39.81#ibcon#flushed, iclass 31, count 0 2006.210.07:50:39.81#ibcon#about to write, iclass 31, count 0 2006.210.07:50:39.81#ibcon#wrote, iclass 31, count 0 2006.210.07:50:39.81#ibcon#about to read 3, iclass 31, count 0 2006.210.07:50:39.84#ibcon#read 3, iclass 31, count 0 2006.210.07:50:39.84#ibcon#about to read 4, iclass 31, count 0 2006.210.07:50:39.84#ibcon#read 4, iclass 31, count 0 2006.210.07:50:39.84#ibcon#about to read 5, iclass 31, count 0 2006.210.07:50:39.84#ibcon#read 5, iclass 31, count 0 2006.210.07:50:39.84#ibcon#about to read 6, iclass 31, count 0 2006.210.07:50:39.84#ibcon#read 6, iclass 31, count 0 2006.210.07:50:39.84#ibcon#end of sib2, iclass 31, count 0 2006.210.07:50:39.84#ibcon#*after write, iclass 31, count 0 2006.210.07:50:39.84#ibcon#*before return 0, iclass 31, count 0 2006.210.07:50:39.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:50:39.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.07:50:39.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:50:39.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:50:39.84$vc4f8/valo=8,852.99 2006.210.07:50:39.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.07:50:39.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.07:50:39.84#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:39.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:50:39.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:50:39.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:50:39.84#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:50:39.84#ibcon#first serial, iclass 33, count 0 2006.210.07:50:39.84#ibcon#enter sib2, iclass 33, count 0 2006.210.07:50:39.84#ibcon#flushed, iclass 33, count 0 2006.210.07:50:39.84#ibcon#about to write, iclass 33, count 0 2006.210.07:50:39.84#ibcon#wrote, iclass 33, count 0 2006.210.07:50:39.84#ibcon#about to read 3, iclass 33, count 0 2006.210.07:50:39.86#ibcon#read 3, iclass 33, count 0 2006.210.07:50:39.86#ibcon#about to read 4, iclass 33, count 0 2006.210.07:50:39.86#ibcon#read 4, iclass 33, count 0 2006.210.07:50:39.86#ibcon#about to read 5, iclass 33, count 0 2006.210.07:50:39.86#ibcon#read 5, iclass 33, count 0 2006.210.07:50:39.86#ibcon#about to read 6, iclass 33, count 0 2006.210.07:50:39.86#ibcon#read 6, iclass 33, count 0 2006.210.07:50:39.86#ibcon#end of sib2, iclass 33, count 0 2006.210.07:50:39.86#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:50:39.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:50:39.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:50:39.86#ibcon#*before write, iclass 33, count 0 2006.210.07:50:39.86#ibcon#enter sib2, iclass 33, count 0 2006.210.07:50:39.86#ibcon#flushed, iclass 33, count 0 2006.210.07:50:39.86#ibcon#about to write, iclass 33, count 0 2006.210.07:50:39.86#ibcon#wrote, iclass 33, count 0 2006.210.07:50:39.86#ibcon#about to read 3, iclass 33, count 0 2006.210.07:50:39.90#ibcon#read 3, iclass 33, count 0 2006.210.07:50:39.90#ibcon#about to read 4, iclass 33, count 0 2006.210.07:50:39.90#ibcon#read 4, iclass 33, count 0 2006.210.07:50:39.90#ibcon#about to read 5, iclass 33, count 0 2006.210.07:50:39.90#ibcon#read 5, iclass 33, count 0 2006.210.07:50:39.90#ibcon#about to read 6, iclass 33, count 0 2006.210.07:50:39.90#ibcon#read 6, iclass 33, count 0 2006.210.07:50:39.90#ibcon#end of sib2, iclass 33, count 0 2006.210.07:50:39.90#ibcon#*after write, iclass 33, count 0 2006.210.07:50:39.90#ibcon#*before return 0, iclass 33, count 0 2006.210.07:50:39.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:50:39.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.07:50:39.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:50:39.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:50:39.90$vc4f8/va=8,7 2006.210.07:50:39.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.07:50:39.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.07:50:39.90#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:39.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:50:39.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:50:39.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:50:39.96#ibcon#enter wrdev, iclass 35, count 2 2006.210.07:50:39.96#ibcon#first serial, iclass 35, count 2 2006.210.07:50:39.96#ibcon#enter sib2, iclass 35, count 2 2006.210.07:50:39.96#ibcon#flushed, iclass 35, count 2 2006.210.07:50:39.96#ibcon#about to write, iclass 35, count 2 2006.210.07:50:39.96#ibcon#wrote, iclass 35, count 2 2006.210.07:50:39.96#ibcon#about to read 3, iclass 35, count 2 2006.210.07:50:39.98#ibcon#read 3, iclass 35, count 2 2006.210.07:50:39.98#ibcon#about to read 4, iclass 35, count 2 2006.210.07:50:39.98#ibcon#read 4, iclass 35, count 2 2006.210.07:50:39.98#ibcon#about to read 5, iclass 35, count 2 2006.210.07:50:39.98#ibcon#read 5, iclass 35, count 2 2006.210.07:50:39.98#ibcon#about to read 6, iclass 35, count 2 2006.210.07:50:39.98#ibcon#read 6, iclass 35, count 2 2006.210.07:50:39.98#ibcon#end of sib2, iclass 35, count 2 2006.210.07:50:39.98#ibcon#*mode == 0, iclass 35, count 2 2006.210.07:50:39.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.07:50:39.98#ibcon#[25=AT08-07\r\n] 2006.210.07:50:39.98#ibcon#*before write, iclass 35, count 2 2006.210.07:50:39.98#ibcon#enter sib2, iclass 35, count 2 2006.210.07:50:39.98#ibcon#flushed, iclass 35, count 2 2006.210.07:50:39.98#ibcon#about to write, iclass 35, count 2 2006.210.07:50:39.98#ibcon#wrote, iclass 35, count 2 2006.210.07:50:39.98#ibcon#about to read 3, iclass 35, count 2 2006.210.07:50:40.01#ibcon#read 3, iclass 35, count 2 2006.210.07:50:40.01#ibcon#about to read 4, iclass 35, count 2 2006.210.07:50:40.01#ibcon#read 4, iclass 35, count 2 2006.210.07:50:40.01#ibcon#about to read 5, iclass 35, count 2 2006.210.07:50:40.01#ibcon#read 5, iclass 35, count 2 2006.210.07:50:40.01#ibcon#about to read 6, iclass 35, count 2 2006.210.07:50:40.01#ibcon#read 6, iclass 35, count 2 2006.210.07:50:40.01#ibcon#end of sib2, iclass 35, count 2 2006.210.07:50:40.01#ibcon#*after write, iclass 35, count 2 2006.210.07:50:40.01#ibcon#*before return 0, iclass 35, count 2 2006.210.07:50:40.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:50:40.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.07:50:40.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.07:50:40.01#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:40.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:50:40.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:50:40.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:50:40.13#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:50:40.13#ibcon#first serial, iclass 35, count 0 2006.210.07:50:40.13#ibcon#enter sib2, iclass 35, count 0 2006.210.07:50:40.13#ibcon#flushed, iclass 35, count 0 2006.210.07:50:40.13#ibcon#about to write, iclass 35, count 0 2006.210.07:50:40.13#ibcon#wrote, iclass 35, count 0 2006.210.07:50:40.13#ibcon#about to read 3, iclass 35, count 0 2006.210.07:50:40.15#ibcon#read 3, iclass 35, count 0 2006.210.07:50:40.15#ibcon#about to read 4, iclass 35, count 0 2006.210.07:50:40.15#ibcon#read 4, iclass 35, count 0 2006.210.07:50:40.15#ibcon#about to read 5, iclass 35, count 0 2006.210.07:50:40.15#ibcon#read 5, iclass 35, count 0 2006.210.07:50:40.15#ibcon#about to read 6, iclass 35, count 0 2006.210.07:50:40.15#ibcon#read 6, iclass 35, count 0 2006.210.07:50:40.15#ibcon#end of sib2, iclass 35, count 0 2006.210.07:50:40.15#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:50:40.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:50:40.15#ibcon#[25=USB\r\n] 2006.210.07:50:40.15#ibcon#*before write, iclass 35, count 0 2006.210.07:50:40.15#ibcon#enter sib2, iclass 35, count 0 2006.210.07:50:40.15#ibcon#flushed, iclass 35, count 0 2006.210.07:50:40.15#ibcon#about to write, iclass 35, count 0 2006.210.07:50:40.15#ibcon#wrote, iclass 35, count 0 2006.210.07:50:40.15#ibcon#about to read 3, iclass 35, count 0 2006.210.07:50:40.18#ibcon#read 3, iclass 35, count 0 2006.210.07:50:40.18#ibcon#about to read 4, iclass 35, count 0 2006.210.07:50:40.18#ibcon#read 4, iclass 35, count 0 2006.210.07:50:40.18#ibcon#about to read 5, iclass 35, count 0 2006.210.07:50:40.18#ibcon#read 5, iclass 35, count 0 2006.210.07:50:40.18#ibcon#about to read 6, iclass 35, count 0 2006.210.07:50:40.18#ibcon#read 6, iclass 35, count 0 2006.210.07:50:40.18#ibcon#end of sib2, iclass 35, count 0 2006.210.07:50:40.18#ibcon#*after write, iclass 35, count 0 2006.210.07:50:40.18#ibcon#*before return 0, iclass 35, count 0 2006.210.07:50:40.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:50:40.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.07:50:40.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:50:40.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:50:40.18$vc4f8/vblo=1,632.99 2006.210.07:50:40.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.07:50:40.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.07:50:40.18#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:40.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:50:40.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:50:40.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:50:40.18#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:50:40.18#ibcon#first serial, iclass 37, count 0 2006.210.07:50:40.18#ibcon#enter sib2, iclass 37, count 0 2006.210.07:50:40.18#ibcon#flushed, iclass 37, count 0 2006.210.07:50:40.18#ibcon#about to write, iclass 37, count 0 2006.210.07:50:40.18#ibcon#wrote, iclass 37, count 0 2006.210.07:50:40.18#ibcon#about to read 3, iclass 37, count 0 2006.210.07:50:40.20#ibcon#read 3, iclass 37, count 0 2006.210.07:50:40.20#ibcon#about to read 4, iclass 37, count 0 2006.210.07:50:40.20#ibcon#read 4, iclass 37, count 0 2006.210.07:50:40.20#ibcon#about to read 5, iclass 37, count 0 2006.210.07:50:40.20#ibcon#read 5, iclass 37, count 0 2006.210.07:50:40.20#ibcon#about to read 6, iclass 37, count 0 2006.210.07:50:40.20#ibcon#read 6, iclass 37, count 0 2006.210.07:50:40.20#ibcon#end of sib2, iclass 37, count 0 2006.210.07:50:40.20#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:50:40.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:50:40.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:50:40.20#ibcon#*before write, iclass 37, count 0 2006.210.07:50:40.20#ibcon#enter sib2, iclass 37, count 0 2006.210.07:50:40.20#ibcon#flushed, iclass 37, count 0 2006.210.07:50:40.20#ibcon#about to write, iclass 37, count 0 2006.210.07:50:40.20#ibcon#wrote, iclass 37, count 0 2006.210.07:50:40.20#ibcon#about to read 3, iclass 37, count 0 2006.210.07:50:40.24#ibcon#read 3, iclass 37, count 0 2006.210.07:50:40.24#ibcon#about to read 4, iclass 37, count 0 2006.210.07:50:40.24#ibcon#read 4, iclass 37, count 0 2006.210.07:50:40.24#ibcon#about to read 5, iclass 37, count 0 2006.210.07:50:40.24#ibcon#read 5, iclass 37, count 0 2006.210.07:50:40.24#ibcon#about to read 6, iclass 37, count 0 2006.210.07:50:40.24#ibcon#read 6, iclass 37, count 0 2006.210.07:50:40.24#ibcon#end of sib2, iclass 37, count 0 2006.210.07:50:40.24#ibcon#*after write, iclass 37, count 0 2006.210.07:50:40.24#ibcon#*before return 0, iclass 37, count 0 2006.210.07:50:40.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:50:40.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.07:50:40.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:50:40.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:50:40.24$vc4f8/vb=1,4 2006.210.07:50:40.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.07:50:40.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.07:50:40.24#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:40.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:50:40.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:50:40.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:50:40.24#ibcon#enter wrdev, iclass 39, count 2 2006.210.07:50:40.24#ibcon#first serial, iclass 39, count 2 2006.210.07:50:40.24#ibcon#enter sib2, iclass 39, count 2 2006.210.07:50:40.24#ibcon#flushed, iclass 39, count 2 2006.210.07:50:40.24#ibcon#about to write, iclass 39, count 2 2006.210.07:50:40.24#ibcon#wrote, iclass 39, count 2 2006.210.07:50:40.24#ibcon#about to read 3, iclass 39, count 2 2006.210.07:50:40.26#ibcon#read 3, iclass 39, count 2 2006.210.07:50:40.26#ibcon#about to read 4, iclass 39, count 2 2006.210.07:50:40.26#ibcon#read 4, iclass 39, count 2 2006.210.07:50:40.26#ibcon#about to read 5, iclass 39, count 2 2006.210.07:50:40.26#ibcon#read 5, iclass 39, count 2 2006.210.07:50:40.26#ibcon#about to read 6, iclass 39, count 2 2006.210.07:50:40.26#ibcon#read 6, iclass 39, count 2 2006.210.07:50:40.26#ibcon#end of sib2, iclass 39, count 2 2006.210.07:50:40.26#ibcon#*mode == 0, iclass 39, count 2 2006.210.07:50:40.26#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.07:50:40.26#ibcon#[27=AT01-04\r\n] 2006.210.07:50:40.26#ibcon#*before write, iclass 39, count 2 2006.210.07:50:40.26#ibcon#enter sib2, iclass 39, count 2 2006.210.07:50:40.26#ibcon#flushed, iclass 39, count 2 2006.210.07:50:40.26#ibcon#about to write, iclass 39, count 2 2006.210.07:50:40.26#ibcon#wrote, iclass 39, count 2 2006.210.07:50:40.26#ibcon#about to read 3, iclass 39, count 2 2006.210.07:50:40.29#ibcon#read 3, iclass 39, count 2 2006.210.07:50:40.29#ibcon#about to read 4, iclass 39, count 2 2006.210.07:50:40.29#ibcon#read 4, iclass 39, count 2 2006.210.07:50:40.29#ibcon#about to read 5, iclass 39, count 2 2006.210.07:50:40.29#ibcon#read 5, iclass 39, count 2 2006.210.07:50:40.29#ibcon#about to read 6, iclass 39, count 2 2006.210.07:50:40.29#ibcon#read 6, iclass 39, count 2 2006.210.07:50:40.29#ibcon#end of sib2, iclass 39, count 2 2006.210.07:50:40.29#ibcon#*after write, iclass 39, count 2 2006.210.07:50:40.29#ibcon#*before return 0, iclass 39, count 2 2006.210.07:50:40.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:50:40.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.07:50:40.29#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.07:50:40.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:40.29#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:50:40.41#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:50:40.41#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:50:40.41#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:50:40.41#ibcon#first serial, iclass 39, count 0 2006.210.07:50:40.41#ibcon#enter sib2, iclass 39, count 0 2006.210.07:50:40.41#ibcon#flushed, iclass 39, count 0 2006.210.07:50:40.41#ibcon#about to write, iclass 39, count 0 2006.210.07:50:40.41#ibcon#wrote, iclass 39, count 0 2006.210.07:50:40.41#ibcon#about to read 3, iclass 39, count 0 2006.210.07:50:40.43#ibcon#read 3, iclass 39, count 0 2006.210.07:50:40.43#ibcon#about to read 4, iclass 39, count 0 2006.210.07:50:40.43#ibcon#read 4, iclass 39, count 0 2006.210.07:50:40.43#ibcon#about to read 5, iclass 39, count 0 2006.210.07:50:40.43#ibcon#read 5, iclass 39, count 0 2006.210.07:50:40.43#ibcon#about to read 6, iclass 39, count 0 2006.210.07:50:40.43#ibcon#read 6, iclass 39, count 0 2006.210.07:50:40.43#ibcon#end of sib2, iclass 39, count 0 2006.210.07:50:40.43#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:50:40.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:50:40.43#ibcon#[27=USB\r\n] 2006.210.07:50:40.43#ibcon#*before write, iclass 39, count 0 2006.210.07:50:40.43#ibcon#enter sib2, iclass 39, count 0 2006.210.07:50:40.43#ibcon#flushed, iclass 39, count 0 2006.210.07:50:40.43#ibcon#about to write, iclass 39, count 0 2006.210.07:50:40.43#ibcon#wrote, iclass 39, count 0 2006.210.07:50:40.43#ibcon#about to read 3, iclass 39, count 0 2006.210.07:50:40.46#ibcon#read 3, iclass 39, count 0 2006.210.07:50:40.46#ibcon#about to read 4, iclass 39, count 0 2006.210.07:50:40.46#ibcon#read 4, iclass 39, count 0 2006.210.07:50:40.46#ibcon#about to read 5, iclass 39, count 0 2006.210.07:50:40.46#ibcon#read 5, iclass 39, count 0 2006.210.07:50:40.46#ibcon#about to read 6, iclass 39, count 0 2006.210.07:50:40.46#ibcon#read 6, iclass 39, count 0 2006.210.07:50:40.46#ibcon#end of sib2, iclass 39, count 0 2006.210.07:50:40.46#ibcon#*after write, iclass 39, count 0 2006.210.07:50:40.46#ibcon#*before return 0, iclass 39, count 0 2006.210.07:50:40.46#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:50:40.46#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.07:50:40.46#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:50:40.46#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:50:40.46$vc4f8/vblo=2,640.99 2006.210.07:50:40.46#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.07:50:40.46#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.07:50:40.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:40.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:40.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:40.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:40.46#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:50:40.46#ibcon#first serial, iclass 3, count 0 2006.210.07:50:40.46#ibcon#enter sib2, iclass 3, count 0 2006.210.07:50:40.46#ibcon#flushed, iclass 3, count 0 2006.210.07:50:40.46#ibcon#about to write, iclass 3, count 0 2006.210.07:50:40.46#ibcon#wrote, iclass 3, count 0 2006.210.07:50:40.46#ibcon#about to read 3, iclass 3, count 0 2006.210.07:50:40.48#ibcon#read 3, iclass 3, count 0 2006.210.07:50:40.48#ibcon#about to read 4, iclass 3, count 0 2006.210.07:50:40.48#ibcon#read 4, iclass 3, count 0 2006.210.07:50:40.48#ibcon#about to read 5, iclass 3, count 0 2006.210.07:50:40.48#ibcon#read 5, iclass 3, count 0 2006.210.07:50:40.48#ibcon#about to read 6, iclass 3, count 0 2006.210.07:50:40.48#ibcon#read 6, iclass 3, count 0 2006.210.07:50:40.48#ibcon#end of sib2, iclass 3, count 0 2006.210.07:50:40.48#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:50:40.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:50:40.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:50:40.48#ibcon#*before write, iclass 3, count 0 2006.210.07:50:40.48#ibcon#enter sib2, iclass 3, count 0 2006.210.07:50:40.48#ibcon#flushed, iclass 3, count 0 2006.210.07:50:40.48#ibcon#about to write, iclass 3, count 0 2006.210.07:50:40.48#ibcon#wrote, iclass 3, count 0 2006.210.07:50:40.48#ibcon#about to read 3, iclass 3, count 0 2006.210.07:50:40.52#ibcon#read 3, iclass 3, count 0 2006.210.07:50:40.52#ibcon#about to read 4, iclass 3, count 0 2006.210.07:50:40.52#ibcon#read 4, iclass 3, count 0 2006.210.07:50:40.52#ibcon#about to read 5, iclass 3, count 0 2006.210.07:50:40.52#ibcon#read 5, iclass 3, count 0 2006.210.07:50:40.52#ibcon#about to read 6, iclass 3, count 0 2006.210.07:50:40.52#ibcon#read 6, iclass 3, count 0 2006.210.07:50:40.52#ibcon#end of sib2, iclass 3, count 0 2006.210.07:50:40.52#ibcon#*after write, iclass 3, count 0 2006.210.07:50:40.52#ibcon#*before return 0, iclass 3, count 0 2006.210.07:50:40.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:40.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.07:50:40.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:50:40.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:50:40.52$vc4f8/vb=2,4 2006.210.07:50:40.52#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.07:50:40.52#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.07:50:40.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:40.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:40.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:40.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:40.58#ibcon#enter wrdev, iclass 5, count 2 2006.210.07:50:40.58#ibcon#first serial, iclass 5, count 2 2006.210.07:50:40.58#ibcon#enter sib2, iclass 5, count 2 2006.210.07:50:40.58#ibcon#flushed, iclass 5, count 2 2006.210.07:50:40.58#ibcon#about to write, iclass 5, count 2 2006.210.07:50:40.58#ibcon#wrote, iclass 5, count 2 2006.210.07:50:40.58#ibcon#about to read 3, iclass 5, count 2 2006.210.07:50:40.60#ibcon#read 3, iclass 5, count 2 2006.210.07:50:40.60#ibcon#about to read 4, iclass 5, count 2 2006.210.07:50:40.60#ibcon#read 4, iclass 5, count 2 2006.210.07:50:40.60#ibcon#about to read 5, iclass 5, count 2 2006.210.07:50:40.60#ibcon#read 5, iclass 5, count 2 2006.210.07:50:40.60#ibcon#about to read 6, iclass 5, count 2 2006.210.07:50:40.60#ibcon#read 6, iclass 5, count 2 2006.210.07:50:40.60#ibcon#end of sib2, iclass 5, count 2 2006.210.07:50:40.60#ibcon#*mode == 0, iclass 5, count 2 2006.210.07:50:40.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.07:50:40.60#ibcon#[27=AT02-04\r\n] 2006.210.07:50:40.60#ibcon#*before write, iclass 5, count 2 2006.210.07:50:40.60#ibcon#enter sib2, iclass 5, count 2 2006.210.07:50:40.60#ibcon#flushed, iclass 5, count 2 2006.210.07:50:40.60#ibcon#about to write, iclass 5, count 2 2006.210.07:50:40.60#ibcon#wrote, iclass 5, count 2 2006.210.07:50:40.60#ibcon#about to read 3, iclass 5, count 2 2006.210.07:50:40.63#ibcon#read 3, iclass 5, count 2 2006.210.07:50:40.63#ibcon#about to read 4, iclass 5, count 2 2006.210.07:50:40.63#ibcon#read 4, iclass 5, count 2 2006.210.07:50:40.63#ibcon#about to read 5, iclass 5, count 2 2006.210.07:50:40.63#ibcon#read 5, iclass 5, count 2 2006.210.07:50:40.63#ibcon#about to read 6, iclass 5, count 2 2006.210.07:50:40.63#ibcon#read 6, iclass 5, count 2 2006.210.07:50:40.63#ibcon#end of sib2, iclass 5, count 2 2006.210.07:50:40.63#ibcon#*after write, iclass 5, count 2 2006.210.07:50:40.63#ibcon#*before return 0, iclass 5, count 2 2006.210.07:50:40.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:40.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.07:50:40.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.07:50:40.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:40.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:40.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:40.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:40.75#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:50:40.75#ibcon#first serial, iclass 5, count 0 2006.210.07:50:40.75#ibcon#enter sib2, iclass 5, count 0 2006.210.07:50:40.75#ibcon#flushed, iclass 5, count 0 2006.210.07:50:40.75#ibcon#about to write, iclass 5, count 0 2006.210.07:50:40.75#ibcon#wrote, iclass 5, count 0 2006.210.07:50:40.75#ibcon#about to read 3, iclass 5, count 0 2006.210.07:50:40.77#ibcon#read 3, iclass 5, count 0 2006.210.07:50:40.77#ibcon#about to read 4, iclass 5, count 0 2006.210.07:50:40.77#ibcon#read 4, iclass 5, count 0 2006.210.07:50:40.77#ibcon#about to read 5, iclass 5, count 0 2006.210.07:50:40.77#ibcon#read 5, iclass 5, count 0 2006.210.07:50:40.77#ibcon#about to read 6, iclass 5, count 0 2006.210.07:50:40.77#ibcon#read 6, iclass 5, count 0 2006.210.07:50:40.77#ibcon#end of sib2, iclass 5, count 0 2006.210.07:50:40.77#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:50:40.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:50:40.77#ibcon#[27=USB\r\n] 2006.210.07:50:40.77#ibcon#*before write, iclass 5, count 0 2006.210.07:50:40.77#ibcon#enter sib2, iclass 5, count 0 2006.210.07:50:40.77#ibcon#flushed, iclass 5, count 0 2006.210.07:50:40.77#ibcon#about to write, iclass 5, count 0 2006.210.07:50:40.77#ibcon#wrote, iclass 5, count 0 2006.210.07:50:40.77#ibcon#about to read 3, iclass 5, count 0 2006.210.07:50:40.80#ibcon#read 3, iclass 5, count 0 2006.210.07:50:40.80#ibcon#about to read 4, iclass 5, count 0 2006.210.07:50:40.80#ibcon#read 4, iclass 5, count 0 2006.210.07:50:40.80#ibcon#about to read 5, iclass 5, count 0 2006.210.07:50:40.80#ibcon#read 5, iclass 5, count 0 2006.210.07:50:40.80#ibcon#about to read 6, iclass 5, count 0 2006.210.07:50:40.80#ibcon#read 6, iclass 5, count 0 2006.210.07:50:40.80#ibcon#end of sib2, iclass 5, count 0 2006.210.07:50:40.80#ibcon#*after write, iclass 5, count 0 2006.210.07:50:40.80#ibcon#*before return 0, iclass 5, count 0 2006.210.07:50:40.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:40.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.07:50:40.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:50:40.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:50:40.80$vc4f8/vblo=3,656.99 2006.210.07:50:40.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.07:50:40.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.07:50:40.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:40.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:40.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:40.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:40.80#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:50:40.80#ibcon#first serial, iclass 7, count 0 2006.210.07:50:40.80#ibcon#enter sib2, iclass 7, count 0 2006.210.07:50:40.80#ibcon#flushed, iclass 7, count 0 2006.210.07:50:40.80#ibcon#about to write, iclass 7, count 0 2006.210.07:50:40.80#ibcon#wrote, iclass 7, count 0 2006.210.07:50:40.80#ibcon#about to read 3, iclass 7, count 0 2006.210.07:50:40.82#ibcon#read 3, iclass 7, count 0 2006.210.07:50:40.82#ibcon#about to read 4, iclass 7, count 0 2006.210.07:50:40.82#ibcon#read 4, iclass 7, count 0 2006.210.07:50:40.82#ibcon#about to read 5, iclass 7, count 0 2006.210.07:50:40.82#ibcon#read 5, iclass 7, count 0 2006.210.07:50:40.82#ibcon#about to read 6, iclass 7, count 0 2006.210.07:50:40.82#ibcon#read 6, iclass 7, count 0 2006.210.07:50:40.82#ibcon#end of sib2, iclass 7, count 0 2006.210.07:50:40.82#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:50:40.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:50:40.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:50:40.82#ibcon#*before write, iclass 7, count 0 2006.210.07:50:40.82#ibcon#enter sib2, iclass 7, count 0 2006.210.07:50:40.82#ibcon#flushed, iclass 7, count 0 2006.210.07:50:40.82#ibcon#about to write, iclass 7, count 0 2006.210.07:50:40.82#ibcon#wrote, iclass 7, count 0 2006.210.07:50:40.82#ibcon#about to read 3, iclass 7, count 0 2006.210.07:50:40.86#ibcon#read 3, iclass 7, count 0 2006.210.07:50:40.86#ibcon#about to read 4, iclass 7, count 0 2006.210.07:50:40.86#ibcon#read 4, iclass 7, count 0 2006.210.07:50:40.86#ibcon#about to read 5, iclass 7, count 0 2006.210.07:50:40.86#ibcon#read 5, iclass 7, count 0 2006.210.07:50:40.86#ibcon#about to read 6, iclass 7, count 0 2006.210.07:50:40.86#ibcon#read 6, iclass 7, count 0 2006.210.07:50:40.86#ibcon#end of sib2, iclass 7, count 0 2006.210.07:50:40.86#ibcon#*after write, iclass 7, count 0 2006.210.07:50:40.86#ibcon#*before return 0, iclass 7, count 0 2006.210.07:50:40.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:40.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.07:50:40.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:50:40.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:50:40.86$vc4f8/vb=3,3 2006.210.07:50:40.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.07:50:40.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.07:50:40.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:40.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:40.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:40.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:40.92#ibcon#enter wrdev, iclass 11, count 2 2006.210.07:50:40.92#ibcon#first serial, iclass 11, count 2 2006.210.07:50:40.92#ibcon#enter sib2, iclass 11, count 2 2006.210.07:50:40.92#ibcon#flushed, iclass 11, count 2 2006.210.07:50:40.92#ibcon#about to write, iclass 11, count 2 2006.210.07:50:40.92#ibcon#wrote, iclass 11, count 2 2006.210.07:50:40.92#ibcon#about to read 3, iclass 11, count 2 2006.210.07:50:40.94#ibcon#read 3, iclass 11, count 2 2006.210.07:50:40.94#ibcon#about to read 4, iclass 11, count 2 2006.210.07:50:40.94#ibcon#read 4, iclass 11, count 2 2006.210.07:50:40.94#ibcon#about to read 5, iclass 11, count 2 2006.210.07:50:40.94#ibcon#read 5, iclass 11, count 2 2006.210.07:50:40.94#ibcon#about to read 6, iclass 11, count 2 2006.210.07:50:40.94#ibcon#read 6, iclass 11, count 2 2006.210.07:50:40.94#ibcon#end of sib2, iclass 11, count 2 2006.210.07:50:40.94#ibcon#*mode == 0, iclass 11, count 2 2006.210.07:50:40.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.07:50:40.94#ibcon#[27=AT03-03\r\n] 2006.210.07:50:40.94#ibcon#*before write, iclass 11, count 2 2006.210.07:50:40.94#ibcon#enter sib2, iclass 11, count 2 2006.210.07:50:40.94#ibcon#flushed, iclass 11, count 2 2006.210.07:50:40.94#ibcon#about to write, iclass 11, count 2 2006.210.07:50:40.94#ibcon#wrote, iclass 11, count 2 2006.210.07:50:40.94#ibcon#about to read 3, iclass 11, count 2 2006.210.07:50:40.97#ibcon#read 3, iclass 11, count 2 2006.210.07:50:40.97#ibcon#about to read 4, iclass 11, count 2 2006.210.07:50:40.97#ibcon#read 4, iclass 11, count 2 2006.210.07:50:40.97#ibcon#about to read 5, iclass 11, count 2 2006.210.07:50:40.97#ibcon#read 5, iclass 11, count 2 2006.210.07:50:40.97#ibcon#about to read 6, iclass 11, count 2 2006.210.07:50:40.97#ibcon#read 6, iclass 11, count 2 2006.210.07:50:40.97#ibcon#end of sib2, iclass 11, count 2 2006.210.07:50:40.97#ibcon#*after write, iclass 11, count 2 2006.210.07:50:40.97#ibcon#*before return 0, iclass 11, count 2 2006.210.07:50:40.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:40.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.07:50:40.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.07:50:40.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:40.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:41.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:41.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:41.09#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:50:41.09#ibcon#first serial, iclass 11, count 0 2006.210.07:50:41.09#ibcon#enter sib2, iclass 11, count 0 2006.210.07:50:41.09#ibcon#flushed, iclass 11, count 0 2006.210.07:50:41.09#ibcon#about to write, iclass 11, count 0 2006.210.07:50:41.09#ibcon#wrote, iclass 11, count 0 2006.210.07:50:41.09#ibcon#about to read 3, iclass 11, count 0 2006.210.07:50:41.11#ibcon#read 3, iclass 11, count 0 2006.210.07:50:41.11#ibcon#about to read 4, iclass 11, count 0 2006.210.07:50:41.11#ibcon#read 4, iclass 11, count 0 2006.210.07:50:41.11#ibcon#about to read 5, iclass 11, count 0 2006.210.07:50:41.11#ibcon#read 5, iclass 11, count 0 2006.210.07:50:41.11#ibcon#about to read 6, iclass 11, count 0 2006.210.07:50:41.11#ibcon#read 6, iclass 11, count 0 2006.210.07:50:41.11#ibcon#end of sib2, iclass 11, count 0 2006.210.07:50:41.11#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:50:41.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:50:41.11#ibcon#[27=USB\r\n] 2006.210.07:50:41.11#ibcon#*before write, iclass 11, count 0 2006.210.07:50:41.11#ibcon#enter sib2, iclass 11, count 0 2006.210.07:50:41.11#ibcon#flushed, iclass 11, count 0 2006.210.07:50:41.11#ibcon#about to write, iclass 11, count 0 2006.210.07:50:41.11#ibcon#wrote, iclass 11, count 0 2006.210.07:50:41.11#ibcon#about to read 3, iclass 11, count 0 2006.210.07:50:41.14#ibcon#read 3, iclass 11, count 0 2006.210.07:50:41.14#ibcon#about to read 4, iclass 11, count 0 2006.210.07:50:41.14#ibcon#read 4, iclass 11, count 0 2006.210.07:50:41.14#ibcon#about to read 5, iclass 11, count 0 2006.210.07:50:41.14#ibcon#read 5, iclass 11, count 0 2006.210.07:50:41.14#ibcon#about to read 6, iclass 11, count 0 2006.210.07:50:41.14#ibcon#read 6, iclass 11, count 0 2006.210.07:50:41.14#ibcon#end of sib2, iclass 11, count 0 2006.210.07:50:41.14#ibcon#*after write, iclass 11, count 0 2006.210.07:50:41.14#ibcon#*before return 0, iclass 11, count 0 2006.210.07:50:41.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:41.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.07:50:41.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:50:41.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:50:41.14$vc4f8/vblo=4,712.99 2006.210.07:50:41.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.07:50:41.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.07:50:41.14#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:41.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:41.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:41.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:41.14#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:50:41.14#ibcon#first serial, iclass 13, count 0 2006.210.07:50:41.14#ibcon#enter sib2, iclass 13, count 0 2006.210.07:50:41.14#ibcon#flushed, iclass 13, count 0 2006.210.07:50:41.14#ibcon#about to write, iclass 13, count 0 2006.210.07:50:41.14#ibcon#wrote, iclass 13, count 0 2006.210.07:50:41.14#ibcon#about to read 3, iclass 13, count 0 2006.210.07:50:41.16#ibcon#read 3, iclass 13, count 0 2006.210.07:50:41.16#ibcon#about to read 4, iclass 13, count 0 2006.210.07:50:41.16#ibcon#read 4, iclass 13, count 0 2006.210.07:50:41.16#ibcon#about to read 5, iclass 13, count 0 2006.210.07:50:41.16#ibcon#read 5, iclass 13, count 0 2006.210.07:50:41.16#ibcon#about to read 6, iclass 13, count 0 2006.210.07:50:41.16#ibcon#read 6, iclass 13, count 0 2006.210.07:50:41.16#ibcon#end of sib2, iclass 13, count 0 2006.210.07:50:41.16#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:50:41.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:50:41.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:50:41.16#ibcon#*before write, iclass 13, count 0 2006.210.07:50:41.16#ibcon#enter sib2, iclass 13, count 0 2006.210.07:50:41.16#ibcon#flushed, iclass 13, count 0 2006.210.07:50:41.16#ibcon#about to write, iclass 13, count 0 2006.210.07:50:41.16#ibcon#wrote, iclass 13, count 0 2006.210.07:50:41.16#ibcon#about to read 3, iclass 13, count 0 2006.210.07:50:41.20#ibcon#read 3, iclass 13, count 0 2006.210.07:50:41.20#ibcon#about to read 4, iclass 13, count 0 2006.210.07:50:41.20#ibcon#read 4, iclass 13, count 0 2006.210.07:50:41.20#ibcon#about to read 5, iclass 13, count 0 2006.210.07:50:41.20#ibcon#read 5, iclass 13, count 0 2006.210.07:50:41.20#ibcon#about to read 6, iclass 13, count 0 2006.210.07:50:41.20#ibcon#read 6, iclass 13, count 0 2006.210.07:50:41.20#ibcon#end of sib2, iclass 13, count 0 2006.210.07:50:41.20#ibcon#*after write, iclass 13, count 0 2006.210.07:50:41.20#ibcon#*before return 0, iclass 13, count 0 2006.210.07:50:41.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:41.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.07:50:41.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:50:41.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:50:41.20$vc4f8/vb=4,3 2006.210.07:50:41.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.07:50:41.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.07:50:41.20#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:41.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:41.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:41.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:41.26#ibcon#enter wrdev, iclass 15, count 2 2006.210.07:50:41.26#ibcon#first serial, iclass 15, count 2 2006.210.07:50:41.26#ibcon#enter sib2, iclass 15, count 2 2006.210.07:50:41.26#ibcon#flushed, iclass 15, count 2 2006.210.07:50:41.26#ibcon#about to write, iclass 15, count 2 2006.210.07:50:41.26#ibcon#wrote, iclass 15, count 2 2006.210.07:50:41.26#ibcon#about to read 3, iclass 15, count 2 2006.210.07:50:41.28#ibcon#read 3, iclass 15, count 2 2006.210.07:50:41.28#ibcon#about to read 4, iclass 15, count 2 2006.210.07:50:41.28#ibcon#read 4, iclass 15, count 2 2006.210.07:50:41.28#ibcon#about to read 5, iclass 15, count 2 2006.210.07:50:41.28#ibcon#read 5, iclass 15, count 2 2006.210.07:50:41.28#ibcon#about to read 6, iclass 15, count 2 2006.210.07:50:41.28#ibcon#read 6, iclass 15, count 2 2006.210.07:50:41.28#ibcon#end of sib2, iclass 15, count 2 2006.210.07:50:41.28#ibcon#*mode == 0, iclass 15, count 2 2006.210.07:50:41.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.07:50:41.28#ibcon#[27=AT04-03\r\n] 2006.210.07:50:41.28#ibcon#*before write, iclass 15, count 2 2006.210.07:50:41.28#ibcon#enter sib2, iclass 15, count 2 2006.210.07:50:41.28#ibcon#flushed, iclass 15, count 2 2006.210.07:50:41.28#ibcon#about to write, iclass 15, count 2 2006.210.07:50:41.28#ibcon#wrote, iclass 15, count 2 2006.210.07:50:41.28#ibcon#about to read 3, iclass 15, count 2 2006.210.07:50:41.31#ibcon#read 3, iclass 15, count 2 2006.210.07:50:41.31#ibcon#about to read 4, iclass 15, count 2 2006.210.07:50:41.31#ibcon#read 4, iclass 15, count 2 2006.210.07:50:41.31#ibcon#about to read 5, iclass 15, count 2 2006.210.07:50:41.31#ibcon#read 5, iclass 15, count 2 2006.210.07:50:41.31#ibcon#about to read 6, iclass 15, count 2 2006.210.07:50:41.31#ibcon#read 6, iclass 15, count 2 2006.210.07:50:41.31#ibcon#end of sib2, iclass 15, count 2 2006.210.07:50:41.31#ibcon#*after write, iclass 15, count 2 2006.210.07:50:41.31#ibcon#*before return 0, iclass 15, count 2 2006.210.07:50:41.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:41.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.07:50:41.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.07:50:41.31#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:41.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:41.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:41.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:41.43#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:50:41.43#ibcon#first serial, iclass 15, count 0 2006.210.07:50:41.43#ibcon#enter sib2, iclass 15, count 0 2006.210.07:50:41.43#ibcon#flushed, iclass 15, count 0 2006.210.07:50:41.43#ibcon#about to write, iclass 15, count 0 2006.210.07:50:41.43#ibcon#wrote, iclass 15, count 0 2006.210.07:50:41.43#ibcon#about to read 3, iclass 15, count 0 2006.210.07:50:41.45#ibcon#read 3, iclass 15, count 0 2006.210.07:50:41.45#ibcon#about to read 4, iclass 15, count 0 2006.210.07:50:41.45#ibcon#read 4, iclass 15, count 0 2006.210.07:50:41.45#ibcon#about to read 5, iclass 15, count 0 2006.210.07:50:41.45#ibcon#read 5, iclass 15, count 0 2006.210.07:50:41.45#ibcon#about to read 6, iclass 15, count 0 2006.210.07:50:41.45#ibcon#read 6, iclass 15, count 0 2006.210.07:50:41.45#ibcon#end of sib2, iclass 15, count 0 2006.210.07:50:41.45#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:50:41.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:50:41.45#ibcon#[27=USB\r\n] 2006.210.07:50:41.45#ibcon#*before write, iclass 15, count 0 2006.210.07:50:41.45#ibcon#enter sib2, iclass 15, count 0 2006.210.07:50:41.45#ibcon#flushed, iclass 15, count 0 2006.210.07:50:41.45#ibcon#about to write, iclass 15, count 0 2006.210.07:50:41.45#ibcon#wrote, iclass 15, count 0 2006.210.07:50:41.45#ibcon#about to read 3, iclass 15, count 0 2006.210.07:50:41.48#ibcon#read 3, iclass 15, count 0 2006.210.07:50:41.48#ibcon#about to read 4, iclass 15, count 0 2006.210.07:50:41.48#ibcon#read 4, iclass 15, count 0 2006.210.07:50:41.48#ibcon#about to read 5, iclass 15, count 0 2006.210.07:50:41.48#ibcon#read 5, iclass 15, count 0 2006.210.07:50:41.48#ibcon#about to read 6, iclass 15, count 0 2006.210.07:50:41.48#ibcon#read 6, iclass 15, count 0 2006.210.07:50:41.48#ibcon#end of sib2, iclass 15, count 0 2006.210.07:50:41.48#ibcon#*after write, iclass 15, count 0 2006.210.07:50:41.48#ibcon#*before return 0, iclass 15, count 0 2006.210.07:50:41.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:41.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.07:50:41.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:50:41.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:50:41.48$vc4f8/vblo=5,744.99 2006.210.07:50:41.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.07:50:41.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.07:50:41.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:41.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:41.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:41.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:41.48#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:50:41.48#ibcon#first serial, iclass 17, count 0 2006.210.07:50:41.48#ibcon#enter sib2, iclass 17, count 0 2006.210.07:50:41.48#ibcon#flushed, iclass 17, count 0 2006.210.07:50:41.48#ibcon#about to write, iclass 17, count 0 2006.210.07:50:41.48#ibcon#wrote, iclass 17, count 0 2006.210.07:50:41.48#ibcon#about to read 3, iclass 17, count 0 2006.210.07:50:41.50#ibcon#read 3, iclass 17, count 0 2006.210.07:50:41.50#ibcon#about to read 4, iclass 17, count 0 2006.210.07:50:41.50#ibcon#read 4, iclass 17, count 0 2006.210.07:50:41.50#ibcon#about to read 5, iclass 17, count 0 2006.210.07:50:41.50#ibcon#read 5, iclass 17, count 0 2006.210.07:50:41.50#ibcon#about to read 6, iclass 17, count 0 2006.210.07:50:41.50#ibcon#read 6, iclass 17, count 0 2006.210.07:50:41.50#ibcon#end of sib2, iclass 17, count 0 2006.210.07:50:41.50#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:50:41.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:50:41.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:50:41.50#ibcon#*before write, iclass 17, count 0 2006.210.07:50:41.50#ibcon#enter sib2, iclass 17, count 0 2006.210.07:50:41.50#ibcon#flushed, iclass 17, count 0 2006.210.07:50:41.50#ibcon#about to write, iclass 17, count 0 2006.210.07:50:41.50#ibcon#wrote, iclass 17, count 0 2006.210.07:50:41.50#ibcon#about to read 3, iclass 17, count 0 2006.210.07:50:41.54#ibcon#read 3, iclass 17, count 0 2006.210.07:50:41.54#ibcon#about to read 4, iclass 17, count 0 2006.210.07:50:41.54#ibcon#read 4, iclass 17, count 0 2006.210.07:50:41.54#ibcon#about to read 5, iclass 17, count 0 2006.210.07:50:41.54#ibcon#read 5, iclass 17, count 0 2006.210.07:50:41.54#ibcon#about to read 6, iclass 17, count 0 2006.210.07:50:41.54#ibcon#read 6, iclass 17, count 0 2006.210.07:50:41.54#ibcon#end of sib2, iclass 17, count 0 2006.210.07:50:41.54#ibcon#*after write, iclass 17, count 0 2006.210.07:50:41.54#ibcon#*before return 0, iclass 17, count 0 2006.210.07:50:41.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:41.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.07:50:41.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:50:41.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:50:41.54$vc4f8/vb=5,3 2006.210.07:50:41.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.07:50:41.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.07:50:41.54#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:41.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:41.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:41.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:41.60#ibcon#enter wrdev, iclass 19, count 2 2006.210.07:50:41.60#ibcon#first serial, iclass 19, count 2 2006.210.07:50:41.60#ibcon#enter sib2, iclass 19, count 2 2006.210.07:50:41.60#ibcon#flushed, iclass 19, count 2 2006.210.07:50:41.60#ibcon#about to write, iclass 19, count 2 2006.210.07:50:41.60#ibcon#wrote, iclass 19, count 2 2006.210.07:50:41.60#ibcon#about to read 3, iclass 19, count 2 2006.210.07:50:41.62#ibcon#read 3, iclass 19, count 2 2006.210.07:50:41.62#ibcon#about to read 4, iclass 19, count 2 2006.210.07:50:41.62#ibcon#read 4, iclass 19, count 2 2006.210.07:50:41.62#ibcon#about to read 5, iclass 19, count 2 2006.210.07:50:41.62#ibcon#read 5, iclass 19, count 2 2006.210.07:50:41.62#ibcon#about to read 6, iclass 19, count 2 2006.210.07:50:41.62#ibcon#read 6, iclass 19, count 2 2006.210.07:50:41.62#ibcon#end of sib2, iclass 19, count 2 2006.210.07:50:41.62#ibcon#*mode == 0, iclass 19, count 2 2006.210.07:50:41.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.07:50:41.62#ibcon#[27=AT05-03\r\n] 2006.210.07:50:41.62#ibcon#*before write, iclass 19, count 2 2006.210.07:50:41.62#ibcon#enter sib2, iclass 19, count 2 2006.210.07:50:41.62#ibcon#flushed, iclass 19, count 2 2006.210.07:50:41.62#ibcon#about to write, iclass 19, count 2 2006.210.07:50:41.62#ibcon#wrote, iclass 19, count 2 2006.210.07:50:41.62#ibcon#about to read 3, iclass 19, count 2 2006.210.07:50:41.65#ibcon#read 3, iclass 19, count 2 2006.210.07:50:41.65#ibcon#about to read 4, iclass 19, count 2 2006.210.07:50:41.65#ibcon#read 4, iclass 19, count 2 2006.210.07:50:41.65#ibcon#about to read 5, iclass 19, count 2 2006.210.07:50:41.65#ibcon#read 5, iclass 19, count 2 2006.210.07:50:41.65#ibcon#about to read 6, iclass 19, count 2 2006.210.07:50:41.65#ibcon#read 6, iclass 19, count 2 2006.210.07:50:41.65#ibcon#end of sib2, iclass 19, count 2 2006.210.07:50:41.65#ibcon#*after write, iclass 19, count 2 2006.210.07:50:41.65#ibcon#*before return 0, iclass 19, count 2 2006.210.07:50:41.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:41.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.07:50:41.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.07:50:41.65#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:41.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:41.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:41.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:41.77#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:50:41.77#ibcon#first serial, iclass 19, count 0 2006.210.07:50:41.77#ibcon#enter sib2, iclass 19, count 0 2006.210.07:50:41.77#ibcon#flushed, iclass 19, count 0 2006.210.07:50:41.77#ibcon#about to write, iclass 19, count 0 2006.210.07:50:41.77#ibcon#wrote, iclass 19, count 0 2006.210.07:50:41.77#ibcon#about to read 3, iclass 19, count 0 2006.210.07:50:41.79#ibcon#read 3, iclass 19, count 0 2006.210.07:50:41.79#ibcon#about to read 4, iclass 19, count 0 2006.210.07:50:41.79#ibcon#read 4, iclass 19, count 0 2006.210.07:50:41.79#ibcon#about to read 5, iclass 19, count 0 2006.210.07:50:41.79#ibcon#read 5, iclass 19, count 0 2006.210.07:50:41.79#ibcon#about to read 6, iclass 19, count 0 2006.210.07:50:41.79#ibcon#read 6, iclass 19, count 0 2006.210.07:50:41.79#ibcon#end of sib2, iclass 19, count 0 2006.210.07:50:41.79#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:50:41.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:50:41.79#ibcon#[27=USB\r\n] 2006.210.07:50:41.79#ibcon#*before write, iclass 19, count 0 2006.210.07:50:41.79#ibcon#enter sib2, iclass 19, count 0 2006.210.07:50:41.79#ibcon#flushed, iclass 19, count 0 2006.210.07:50:41.79#ibcon#about to write, iclass 19, count 0 2006.210.07:50:41.79#ibcon#wrote, iclass 19, count 0 2006.210.07:50:41.79#ibcon#about to read 3, iclass 19, count 0 2006.210.07:50:41.82#ibcon#read 3, iclass 19, count 0 2006.210.07:50:41.82#ibcon#about to read 4, iclass 19, count 0 2006.210.07:50:41.82#ibcon#read 4, iclass 19, count 0 2006.210.07:50:41.82#ibcon#about to read 5, iclass 19, count 0 2006.210.07:50:41.82#ibcon#read 5, iclass 19, count 0 2006.210.07:50:41.82#ibcon#about to read 6, iclass 19, count 0 2006.210.07:50:41.82#ibcon#read 6, iclass 19, count 0 2006.210.07:50:41.82#ibcon#end of sib2, iclass 19, count 0 2006.210.07:50:41.82#ibcon#*after write, iclass 19, count 0 2006.210.07:50:41.82#ibcon#*before return 0, iclass 19, count 0 2006.210.07:50:41.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:41.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.07:50:41.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:50:41.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:50:41.82$vc4f8/vblo=6,752.99 2006.210.07:50:41.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:50:41.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:50:41.82#ibcon#ireg 17 cls_cnt 0 2006.210.07:50:41.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:41.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:41.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:41.82#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:50:41.82#ibcon#first serial, iclass 21, count 0 2006.210.07:50:41.82#ibcon#enter sib2, iclass 21, count 0 2006.210.07:50:41.82#ibcon#flushed, iclass 21, count 0 2006.210.07:50:41.82#ibcon#about to write, iclass 21, count 0 2006.210.07:50:41.82#ibcon#wrote, iclass 21, count 0 2006.210.07:50:41.82#ibcon#about to read 3, iclass 21, count 0 2006.210.07:50:41.84#ibcon#read 3, iclass 21, count 0 2006.210.07:50:41.84#ibcon#about to read 4, iclass 21, count 0 2006.210.07:50:41.84#ibcon#read 4, iclass 21, count 0 2006.210.07:50:41.84#ibcon#about to read 5, iclass 21, count 0 2006.210.07:50:41.84#ibcon#read 5, iclass 21, count 0 2006.210.07:50:41.84#ibcon#about to read 6, iclass 21, count 0 2006.210.07:50:41.84#ibcon#read 6, iclass 21, count 0 2006.210.07:50:41.84#ibcon#end of sib2, iclass 21, count 0 2006.210.07:50:41.84#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:50:41.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:50:41.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:50:41.84#ibcon#*before write, iclass 21, count 0 2006.210.07:50:41.84#ibcon#enter sib2, iclass 21, count 0 2006.210.07:50:41.84#ibcon#flushed, iclass 21, count 0 2006.210.07:50:41.84#ibcon#about to write, iclass 21, count 0 2006.210.07:50:41.84#ibcon#wrote, iclass 21, count 0 2006.210.07:50:41.84#ibcon#about to read 3, iclass 21, count 0 2006.210.07:50:41.88#ibcon#read 3, iclass 21, count 0 2006.210.07:50:41.88#ibcon#about to read 4, iclass 21, count 0 2006.210.07:50:41.88#ibcon#read 4, iclass 21, count 0 2006.210.07:50:41.88#ibcon#about to read 5, iclass 21, count 0 2006.210.07:50:41.88#ibcon#read 5, iclass 21, count 0 2006.210.07:50:41.88#ibcon#about to read 6, iclass 21, count 0 2006.210.07:50:41.88#ibcon#read 6, iclass 21, count 0 2006.210.07:50:41.88#ibcon#end of sib2, iclass 21, count 0 2006.210.07:50:41.88#ibcon#*after write, iclass 21, count 0 2006.210.07:50:41.88#ibcon#*before return 0, iclass 21, count 0 2006.210.07:50:41.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:41.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:50:41.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:50:41.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:50:41.88$vc4f8/vb=6,3 2006.210.07:50:41.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.07:50:41.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.07:50:41.88#ibcon#ireg 11 cls_cnt 2 2006.210.07:50:41.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:41.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:41.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:41.94#ibcon#enter wrdev, iclass 23, count 2 2006.210.07:50:41.94#ibcon#first serial, iclass 23, count 2 2006.210.07:50:41.94#ibcon#enter sib2, iclass 23, count 2 2006.210.07:50:41.94#ibcon#flushed, iclass 23, count 2 2006.210.07:50:41.94#ibcon#about to write, iclass 23, count 2 2006.210.07:50:41.94#ibcon#wrote, iclass 23, count 2 2006.210.07:50:41.94#ibcon#about to read 3, iclass 23, count 2 2006.210.07:50:41.96#ibcon#read 3, iclass 23, count 2 2006.210.07:50:41.96#ibcon#about to read 4, iclass 23, count 2 2006.210.07:50:41.96#ibcon#read 4, iclass 23, count 2 2006.210.07:50:41.96#ibcon#about to read 5, iclass 23, count 2 2006.210.07:50:41.96#ibcon#read 5, iclass 23, count 2 2006.210.07:50:41.96#ibcon#about to read 6, iclass 23, count 2 2006.210.07:50:41.96#ibcon#read 6, iclass 23, count 2 2006.210.07:50:41.96#ibcon#end of sib2, iclass 23, count 2 2006.210.07:50:41.96#ibcon#*mode == 0, iclass 23, count 2 2006.210.07:50:41.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.07:50:41.96#ibcon#[27=AT06-03\r\n] 2006.210.07:50:41.96#ibcon#*before write, iclass 23, count 2 2006.210.07:50:41.96#ibcon#enter sib2, iclass 23, count 2 2006.210.07:50:41.96#ibcon#flushed, iclass 23, count 2 2006.210.07:50:41.96#ibcon#about to write, iclass 23, count 2 2006.210.07:50:41.96#ibcon#wrote, iclass 23, count 2 2006.210.07:50:41.96#ibcon#about to read 3, iclass 23, count 2 2006.210.07:50:41.99#ibcon#read 3, iclass 23, count 2 2006.210.07:50:41.99#ibcon#about to read 4, iclass 23, count 2 2006.210.07:50:41.99#ibcon#read 4, iclass 23, count 2 2006.210.07:50:41.99#ibcon#about to read 5, iclass 23, count 2 2006.210.07:50:41.99#ibcon#read 5, iclass 23, count 2 2006.210.07:50:41.99#ibcon#about to read 6, iclass 23, count 2 2006.210.07:50:41.99#ibcon#read 6, iclass 23, count 2 2006.210.07:50:41.99#ibcon#end of sib2, iclass 23, count 2 2006.210.07:50:41.99#ibcon#*after write, iclass 23, count 2 2006.210.07:50:41.99#ibcon#*before return 0, iclass 23, count 2 2006.210.07:50:41.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:41.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.07:50:41.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.07:50:41.99#ibcon#ireg 7 cls_cnt 0 2006.210.07:50:41.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:42.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:42.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:42.11#ibcon#enter wrdev, iclass 23, count 0 2006.210.07:50:42.11#ibcon#first serial, iclass 23, count 0 2006.210.07:50:42.11#ibcon#enter sib2, iclass 23, count 0 2006.210.07:50:42.11#ibcon#flushed, iclass 23, count 0 2006.210.07:50:42.11#ibcon#about to write, iclass 23, count 0 2006.210.07:50:42.11#ibcon#wrote, iclass 23, count 0 2006.210.07:50:42.11#ibcon#about to read 3, iclass 23, count 0 2006.210.07:50:42.13#ibcon#read 3, iclass 23, count 0 2006.210.07:50:42.13#ibcon#about to read 4, iclass 23, count 0 2006.210.07:50:42.13#ibcon#read 4, iclass 23, count 0 2006.210.07:50:42.13#ibcon#about to read 5, iclass 23, count 0 2006.210.07:50:42.13#ibcon#read 5, iclass 23, count 0 2006.210.07:50:42.13#ibcon#about to read 6, iclass 23, count 0 2006.210.07:50:42.13#ibcon#read 6, iclass 23, count 0 2006.210.07:50:42.13#ibcon#end of sib2, iclass 23, count 0 2006.210.07:50:42.13#ibcon#*mode == 0, iclass 23, count 0 2006.210.07:50:42.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.07:50:42.13#ibcon#[27=USB\r\n] 2006.210.07:50:42.13#ibcon#*before write, iclass 23, count 0 2006.210.07:50:42.13#ibcon#enter sib2, iclass 23, count 0 2006.210.07:50:42.13#ibcon#flushed, iclass 23, count 0 2006.210.07:50:42.13#ibcon#about to write, iclass 23, count 0 2006.210.07:50:42.13#ibcon#wrote, iclass 23, count 0 2006.210.07:50:42.13#ibcon#about to read 3, iclass 23, count 0 2006.210.07:50:42.16#ibcon#read 3, iclass 23, count 0 2006.210.07:50:42.16#ibcon#about to read 4, iclass 23, count 0 2006.210.07:50:42.16#ibcon#read 4, iclass 23, count 0 2006.210.07:50:42.16#ibcon#about to read 5, iclass 23, count 0 2006.210.07:50:42.16#ibcon#read 5, iclass 23, count 0 2006.210.07:50:42.16#ibcon#about to read 6, iclass 23, count 0 2006.210.07:50:42.16#ibcon#read 6, iclass 23, count 0 2006.210.07:50:42.16#ibcon#end of sib2, iclass 23, count 0 2006.210.07:50:42.16#ibcon#*after write, iclass 23, count 0 2006.210.07:50:42.16#ibcon#*before return 0, iclass 23, count 0 2006.210.07:50:42.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:42.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.07:50:42.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.07:50:42.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.07:50:42.16$vc4f8/vabw=wide 2006.210.07:50:42.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.07:50:42.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.07:50:42.16#ibcon#ireg 8 cls_cnt 0 2006.210.07:50:42.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:42.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:42.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:42.16#ibcon#enter wrdev, iclass 25, count 0 2006.210.07:50:42.16#ibcon#first serial, iclass 25, count 0 2006.210.07:50:42.16#ibcon#enter sib2, iclass 25, count 0 2006.210.07:50:42.16#ibcon#flushed, iclass 25, count 0 2006.210.07:50:42.16#ibcon#about to write, iclass 25, count 0 2006.210.07:50:42.16#ibcon#wrote, iclass 25, count 0 2006.210.07:50:42.16#ibcon#about to read 3, iclass 25, count 0 2006.210.07:50:42.18#ibcon#read 3, iclass 25, count 0 2006.210.07:50:42.18#ibcon#about to read 4, iclass 25, count 0 2006.210.07:50:42.18#ibcon#read 4, iclass 25, count 0 2006.210.07:50:42.18#ibcon#about to read 5, iclass 25, count 0 2006.210.07:50:42.18#ibcon#read 5, iclass 25, count 0 2006.210.07:50:42.18#ibcon#about to read 6, iclass 25, count 0 2006.210.07:50:42.18#ibcon#read 6, iclass 25, count 0 2006.210.07:50:42.18#ibcon#end of sib2, iclass 25, count 0 2006.210.07:50:42.18#ibcon#*mode == 0, iclass 25, count 0 2006.210.07:50:42.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.07:50:42.18#ibcon#[25=BW32\r\n] 2006.210.07:50:42.18#ibcon#*before write, iclass 25, count 0 2006.210.07:50:42.18#ibcon#enter sib2, iclass 25, count 0 2006.210.07:50:42.18#ibcon#flushed, iclass 25, count 0 2006.210.07:50:42.18#ibcon#about to write, iclass 25, count 0 2006.210.07:50:42.18#ibcon#wrote, iclass 25, count 0 2006.210.07:50:42.18#ibcon#about to read 3, iclass 25, count 0 2006.210.07:50:42.21#ibcon#read 3, iclass 25, count 0 2006.210.07:50:42.21#ibcon#about to read 4, iclass 25, count 0 2006.210.07:50:42.21#ibcon#read 4, iclass 25, count 0 2006.210.07:50:42.21#ibcon#about to read 5, iclass 25, count 0 2006.210.07:50:42.21#ibcon#read 5, iclass 25, count 0 2006.210.07:50:42.21#ibcon#about to read 6, iclass 25, count 0 2006.210.07:50:42.21#ibcon#read 6, iclass 25, count 0 2006.210.07:50:42.21#ibcon#end of sib2, iclass 25, count 0 2006.210.07:50:42.21#ibcon#*after write, iclass 25, count 0 2006.210.07:50:42.21#ibcon#*before return 0, iclass 25, count 0 2006.210.07:50:42.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:42.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.07:50:42.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.07:50:42.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.07:50:42.21$vc4f8/vbbw=wide 2006.210.07:50:42.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.07:50:42.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.07:50:42.21#ibcon#ireg 8 cls_cnt 0 2006.210.07:50:42.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:50:42.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:50:42.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:50:42.28#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:50:42.28#ibcon#first serial, iclass 27, count 0 2006.210.07:50:42.28#ibcon#enter sib2, iclass 27, count 0 2006.210.07:50:42.28#ibcon#flushed, iclass 27, count 0 2006.210.07:50:42.28#ibcon#about to write, iclass 27, count 0 2006.210.07:50:42.28#ibcon#wrote, iclass 27, count 0 2006.210.07:50:42.28#ibcon#about to read 3, iclass 27, count 0 2006.210.07:50:42.30#ibcon#read 3, iclass 27, count 0 2006.210.07:50:42.30#ibcon#about to read 4, iclass 27, count 0 2006.210.07:50:42.30#ibcon#read 4, iclass 27, count 0 2006.210.07:50:42.30#ibcon#about to read 5, iclass 27, count 0 2006.210.07:50:42.30#ibcon#read 5, iclass 27, count 0 2006.210.07:50:42.30#ibcon#about to read 6, iclass 27, count 0 2006.210.07:50:42.30#ibcon#read 6, iclass 27, count 0 2006.210.07:50:42.30#ibcon#end of sib2, iclass 27, count 0 2006.210.07:50:42.30#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:50:42.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:50:42.30#ibcon#[27=BW32\r\n] 2006.210.07:50:42.30#ibcon#*before write, iclass 27, count 0 2006.210.07:50:42.30#ibcon#enter sib2, iclass 27, count 0 2006.210.07:50:42.30#ibcon#flushed, iclass 27, count 0 2006.210.07:50:42.30#ibcon#about to write, iclass 27, count 0 2006.210.07:50:42.30#ibcon#wrote, iclass 27, count 0 2006.210.07:50:42.30#ibcon#about to read 3, iclass 27, count 0 2006.210.07:50:42.33#ibcon#read 3, iclass 27, count 0 2006.210.07:50:42.33#ibcon#about to read 4, iclass 27, count 0 2006.210.07:50:42.33#ibcon#read 4, iclass 27, count 0 2006.210.07:50:42.33#ibcon#about to read 5, iclass 27, count 0 2006.210.07:50:42.33#ibcon#read 5, iclass 27, count 0 2006.210.07:50:42.33#ibcon#about to read 6, iclass 27, count 0 2006.210.07:50:42.33#ibcon#read 6, iclass 27, count 0 2006.210.07:50:42.33#ibcon#end of sib2, iclass 27, count 0 2006.210.07:50:42.33#ibcon#*after write, iclass 27, count 0 2006.210.07:50:42.33#ibcon#*before return 0, iclass 27, count 0 2006.210.07:50:42.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:50:42.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:50:42.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:50:42.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:50:42.33$4f8m12a/ifd4f 2006.210.07:50:42.33$ifd4f/lo= 2006.210.07:50:42.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:50:42.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:50:42.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:50:42.33$ifd4f/patch= 2006.210.07:50:42.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:50:42.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:50:42.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:50:42.33$4f8m12a/"form=m,16.000,1:2 2006.210.07:50:42.33$4f8m12a/"tpicd 2006.210.07:50:42.33$4f8m12a/echo=off 2006.210.07:50:42.33$4f8m12a/xlog=off 2006.210.07:50:42.33:!2006.210.07:51:10 2006.210.07:50:53.14#trakl#Source acquired 2006.210.07:50:55.14#flagr#flagr/antenna,acquired 2006.210.07:51:10.00:preob 2006.210.07:51:11.14/onsource/TRACKING 2006.210.07:51:11.14:!2006.210.07:51:20 2006.210.07:51:20.00:data_valid=on 2006.210.07:51:20.00:midob 2006.210.07:51:20.14/onsource/TRACKING 2006.210.07:51:20.14/wx/30.57,1006.3,72 2006.210.07:51:20.26/cable/+6.3933E-03 2006.210.07:51:21.35/va/01,08,usb,yes,28,30 2006.210.07:51:21.35/va/02,07,usb,yes,28,30 2006.210.07:51:21.35/va/03,06,usb,yes,30,30 2006.210.07:51:21.35/va/04,07,usb,yes,29,31 2006.210.07:51:21.35/va/05,07,usb,yes,30,32 2006.210.07:51:21.35/va/06,06,usb,yes,29,29 2006.210.07:51:21.35/va/07,06,usb,yes,30,29 2006.210.07:51:21.35/va/08,07,usb,yes,28,27 2006.210.07:51:21.58/valo/01,532.99,yes,locked 2006.210.07:51:21.58/valo/02,572.99,yes,locked 2006.210.07:51:21.58/valo/03,672.99,yes,locked 2006.210.07:51:21.58/valo/04,832.99,yes,locked 2006.210.07:51:21.58/valo/05,652.99,yes,locked 2006.210.07:51:21.58/valo/06,772.99,yes,locked 2006.210.07:51:21.58/valo/07,832.99,yes,locked 2006.210.07:51:21.58/valo/08,852.99,yes,locked 2006.210.07:51:22.67/vb/01,04,usb,yes,28,27 2006.210.07:51:22.67/vb/02,04,usb,yes,30,31 2006.210.07:51:22.67/vb/03,03,usb,yes,33,37 2006.210.07:51:22.67/vb/04,03,usb,yes,34,34 2006.210.07:51:22.67/vb/05,03,usb,yes,32,36 2006.210.07:51:22.67/vb/06,03,usb,yes,33,36 2006.210.07:51:22.67/vb/07,04,usb,yes,28,28 2006.210.07:51:22.67/vb/08,03,usb,yes,33,36 2006.210.07:51:22.90/vblo/01,632.99,yes,locked 2006.210.07:51:22.90/vblo/02,640.99,yes,locked 2006.210.07:51:22.90/vblo/03,656.99,yes,locked 2006.210.07:51:22.90/vblo/04,712.99,yes,locked 2006.210.07:51:22.90/vblo/05,744.99,yes,locked 2006.210.07:51:22.90/vblo/06,752.99,yes,locked 2006.210.07:51:22.90/vblo/07,734.99,yes,locked 2006.210.07:51:22.90/vblo/08,744.99,yes,locked 2006.210.07:51:23.05/vabw/8 2006.210.07:51:23.20/vbbw/8 2006.210.07:51:23.37/xfe/off,on,12.5 2006.210.07:51:23.76/ifatt/23,28,28,28 2006.210.07:51:24.07/fmout-gps/S +4.63E-07 2006.210.07:51:24.11:!2006.210.07:52:20 2006.210.07:52:20.00:data_valid=off 2006.210.07:52:20.00:postob 2006.210.07:52:20.10/cable/+6.3959E-03 2006.210.07:52:20.10/wx/30.57,1006.3,75 2006.210.07:52:21.08/fmout-gps/S +4.65E-07 2006.210.07:52:21.08:scan_name=210-0753,k06210,60 2006.210.07:52:21.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.210.07:52:21.14#flagr#flagr/antenna,new-source 2006.210.07:52:22.14:checkk5 2006.210.07:52:22.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:52:22.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:52:23.16/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:52:23.50/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:52:23.84/chk_obsdata//k5ts1/T2100751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:52:24.18/chk_obsdata//k5ts2/T2100751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:52:24.50/chk_obsdata//k5ts3/T2100751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:52:24.84/chk_obsdata//k5ts4/T2100751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:52:25.49/k5log//k5ts1_log_newline 2006.210.07:52:26.14/k5log//k5ts2_log_newline 2006.210.07:52:26.79/k5log//k5ts3_log_newline 2006.210.07:52:27.45/k5log//k5ts4_log_newline 2006.210.07:52:27.47/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:52:27.47:4f8m12a=1 2006.210.07:52:27.47$4f8m12a/echo=on 2006.210.07:52:27.48$4f8m12a/pcalon 2006.210.07:52:27.48$pcalon/"no phase cal control is implemented here 2006.210.07:52:27.48$4f8m12a/"tpicd=stop 2006.210.07:52:27.48$4f8m12a/vc4f8 2006.210.07:52:27.48$vc4f8/valo=1,532.99 2006.210.07:52:27.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.07:52:27.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.07:52:27.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:27.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:27.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:27.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:27.48#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:52:27.48#ibcon#first serial, iclass 34, count 0 2006.210.07:52:27.48#ibcon#enter sib2, iclass 34, count 0 2006.210.07:52:27.48#ibcon#flushed, iclass 34, count 0 2006.210.07:52:27.48#ibcon#about to write, iclass 34, count 0 2006.210.07:52:27.48#ibcon#wrote, iclass 34, count 0 2006.210.07:52:27.48#ibcon#about to read 3, iclass 34, count 0 2006.210.07:52:27.50#ibcon#read 3, iclass 34, count 0 2006.210.07:52:27.50#ibcon#about to read 4, iclass 34, count 0 2006.210.07:52:27.50#ibcon#read 4, iclass 34, count 0 2006.210.07:52:27.50#ibcon#about to read 5, iclass 34, count 0 2006.210.07:52:27.50#ibcon#read 5, iclass 34, count 0 2006.210.07:52:27.50#ibcon#about to read 6, iclass 34, count 0 2006.210.07:52:27.50#ibcon#read 6, iclass 34, count 0 2006.210.07:52:27.50#ibcon#end of sib2, iclass 34, count 0 2006.210.07:52:27.50#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:52:27.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:52:27.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:52:27.50#ibcon#*before write, iclass 34, count 0 2006.210.07:52:27.50#ibcon#enter sib2, iclass 34, count 0 2006.210.07:52:27.50#ibcon#flushed, iclass 34, count 0 2006.210.07:52:27.50#ibcon#about to write, iclass 34, count 0 2006.210.07:52:27.50#ibcon#wrote, iclass 34, count 0 2006.210.07:52:27.50#ibcon#about to read 3, iclass 34, count 0 2006.210.07:52:27.55#ibcon#read 3, iclass 34, count 0 2006.210.07:52:27.55#ibcon#about to read 4, iclass 34, count 0 2006.210.07:52:27.55#ibcon#read 4, iclass 34, count 0 2006.210.07:52:27.55#ibcon#about to read 5, iclass 34, count 0 2006.210.07:52:27.55#ibcon#read 5, iclass 34, count 0 2006.210.07:52:27.55#ibcon#about to read 6, iclass 34, count 0 2006.210.07:52:27.55#ibcon#read 6, iclass 34, count 0 2006.210.07:52:27.55#ibcon#end of sib2, iclass 34, count 0 2006.210.07:52:27.55#ibcon#*after write, iclass 34, count 0 2006.210.07:52:27.55#ibcon#*before return 0, iclass 34, count 0 2006.210.07:52:27.55#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:27.55#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:27.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:52:27.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:52:27.55$vc4f8/va=1,8 2006.210.07:52:27.55#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.07:52:27.55#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.07:52:27.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:27.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:27.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:27.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:27.55#ibcon#enter wrdev, iclass 36, count 2 2006.210.07:52:27.55#ibcon#first serial, iclass 36, count 2 2006.210.07:52:27.55#ibcon#enter sib2, iclass 36, count 2 2006.210.07:52:27.55#ibcon#flushed, iclass 36, count 2 2006.210.07:52:27.55#ibcon#about to write, iclass 36, count 2 2006.210.07:52:27.55#ibcon#wrote, iclass 36, count 2 2006.210.07:52:27.55#ibcon#about to read 3, iclass 36, count 2 2006.210.07:52:27.57#ibcon#read 3, iclass 36, count 2 2006.210.07:52:27.57#ibcon#about to read 4, iclass 36, count 2 2006.210.07:52:27.57#ibcon#read 4, iclass 36, count 2 2006.210.07:52:27.57#ibcon#about to read 5, iclass 36, count 2 2006.210.07:52:27.57#ibcon#read 5, iclass 36, count 2 2006.210.07:52:27.57#ibcon#about to read 6, iclass 36, count 2 2006.210.07:52:27.57#ibcon#read 6, iclass 36, count 2 2006.210.07:52:27.57#ibcon#end of sib2, iclass 36, count 2 2006.210.07:52:27.57#ibcon#*mode == 0, iclass 36, count 2 2006.210.07:52:27.57#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.07:52:27.57#ibcon#[25=AT01-08\r\n] 2006.210.07:52:27.57#ibcon#*before write, iclass 36, count 2 2006.210.07:52:27.57#ibcon#enter sib2, iclass 36, count 2 2006.210.07:52:27.57#ibcon#flushed, iclass 36, count 2 2006.210.07:52:27.57#ibcon#about to write, iclass 36, count 2 2006.210.07:52:27.57#ibcon#wrote, iclass 36, count 2 2006.210.07:52:27.57#ibcon#about to read 3, iclass 36, count 2 2006.210.07:52:27.60#ibcon#read 3, iclass 36, count 2 2006.210.07:52:27.60#ibcon#about to read 4, iclass 36, count 2 2006.210.07:52:27.60#ibcon#read 4, iclass 36, count 2 2006.210.07:52:27.60#ibcon#about to read 5, iclass 36, count 2 2006.210.07:52:27.60#ibcon#read 5, iclass 36, count 2 2006.210.07:52:27.60#ibcon#about to read 6, iclass 36, count 2 2006.210.07:52:27.60#ibcon#read 6, iclass 36, count 2 2006.210.07:52:27.60#ibcon#end of sib2, iclass 36, count 2 2006.210.07:52:27.60#ibcon#*after write, iclass 36, count 2 2006.210.07:52:27.60#ibcon#*before return 0, iclass 36, count 2 2006.210.07:52:27.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:27.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:27.60#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.07:52:27.60#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:27.60#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:27.72#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:27.72#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:27.72#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:52:27.72#ibcon#first serial, iclass 36, count 0 2006.210.07:52:27.72#ibcon#enter sib2, iclass 36, count 0 2006.210.07:52:27.72#ibcon#flushed, iclass 36, count 0 2006.210.07:52:27.72#ibcon#about to write, iclass 36, count 0 2006.210.07:52:27.72#ibcon#wrote, iclass 36, count 0 2006.210.07:52:27.72#ibcon#about to read 3, iclass 36, count 0 2006.210.07:52:27.74#ibcon#read 3, iclass 36, count 0 2006.210.07:52:27.74#ibcon#about to read 4, iclass 36, count 0 2006.210.07:52:27.74#ibcon#read 4, iclass 36, count 0 2006.210.07:52:27.74#ibcon#about to read 5, iclass 36, count 0 2006.210.07:52:27.74#ibcon#read 5, iclass 36, count 0 2006.210.07:52:27.74#ibcon#about to read 6, iclass 36, count 0 2006.210.07:52:27.74#ibcon#read 6, iclass 36, count 0 2006.210.07:52:27.74#ibcon#end of sib2, iclass 36, count 0 2006.210.07:52:27.74#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:52:27.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:52:27.74#ibcon#[25=USB\r\n] 2006.210.07:52:27.74#ibcon#*before write, iclass 36, count 0 2006.210.07:52:27.74#ibcon#enter sib2, iclass 36, count 0 2006.210.07:52:27.74#ibcon#flushed, iclass 36, count 0 2006.210.07:52:27.74#ibcon#about to write, iclass 36, count 0 2006.210.07:52:27.74#ibcon#wrote, iclass 36, count 0 2006.210.07:52:27.74#ibcon#about to read 3, iclass 36, count 0 2006.210.07:52:27.77#ibcon#read 3, iclass 36, count 0 2006.210.07:52:27.77#ibcon#about to read 4, iclass 36, count 0 2006.210.07:52:27.77#ibcon#read 4, iclass 36, count 0 2006.210.07:52:27.77#ibcon#about to read 5, iclass 36, count 0 2006.210.07:52:27.77#ibcon#read 5, iclass 36, count 0 2006.210.07:52:27.77#ibcon#about to read 6, iclass 36, count 0 2006.210.07:52:27.77#ibcon#read 6, iclass 36, count 0 2006.210.07:52:27.77#ibcon#end of sib2, iclass 36, count 0 2006.210.07:52:27.77#ibcon#*after write, iclass 36, count 0 2006.210.07:52:27.77#ibcon#*before return 0, iclass 36, count 0 2006.210.07:52:27.77#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:27.77#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:27.77#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:52:27.77#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:52:27.77$vc4f8/valo=2,572.99 2006.210.07:52:27.77#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.07:52:27.77#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.07:52:27.77#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:27.77#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:27.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:27.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:27.77#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:52:27.77#ibcon#first serial, iclass 38, count 0 2006.210.07:52:27.77#ibcon#enter sib2, iclass 38, count 0 2006.210.07:52:27.77#ibcon#flushed, iclass 38, count 0 2006.210.07:52:27.77#ibcon#about to write, iclass 38, count 0 2006.210.07:52:27.77#ibcon#wrote, iclass 38, count 0 2006.210.07:52:27.77#ibcon#about to read 3, iclass 38, count 0 2006.210.07:52:27.79#ibcon#read 3, iclass 38, count 0 2006.210.07:52:27.79#ibcon#about to read 4, iclass 38, count 0 2006.210.07:52:27.79#ibcon#read 4, iclass 38, count 0 2006.210.07:52:27.79#ibcon#about to read 5, iclass 38, count 0 2006.210.07:52:27.79#ibcon#read 5, iclass 38, count 0 2006.210.07:52:27.79#ibcon#about to read 6, iclass 38, count 0 2006.210.07:52:27.79#ibcon#read 6, iclass 38, count 0 2006.210.07:52:27.79#ibcon#end of sib2, iclass 38, count 0 2006.210.07:52:27.79#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:52:27.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:52:27.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:52:27.79#ibcon#*before write, iclass 38, count 0 2006.210.07:52:27.79#ibcon#enter sib2, iclass 38, count 0 2006.210.07:52:27.79#ibcon#flushed, iclass 38, count 0 2006.210.07:52:27.79#ibcon#about to write, iclass 38, count 0 2006.210.07:52:27.79#ibcon#wrote, iclass 38, count 0 2006.210.07:52:27.79#ibcon#about to read 3, iclass 38, count 0 2006.210.07:52:27.83#ibcon#read 3, iclass 38, count 0 2006.210.07:52:27.83#ibcon#about to read 4, iclass 38, count 0 2006.210.07:52:27.83#ibcon#read 4, iclass 38, count 0 2006.210.07:52:27.83#ibcon#about to read 5, iclass 38, count 0 2006.210.07:52:27.83#ibcon#read 5, iclass 38, count 0 2006.210.07:52:27.83#ibcon#about to read 6, iclass 38, count 0 2006.210.07:52:27.83#ibcon#read 6, iclass 38, count 0 2006.210.07:52:27.83#ibcon#end of sib2, iclass 38, count 0 2006.210.07:52:27.83#ibcon#*after write, iclass 38, count 0 2006.210.07:52:27.83#ibcon#*before return 0, iclass 38, count 0 2006.210.07:52:27.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:27.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:27.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:52:27.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:52:27.83$vc4f8/va=2,7 2006.210.07:52:27.83#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.07:52:27.83#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.07:52:27.83#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:27.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:27.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:27.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:27.89#ibcon#enter wrdev, iclass 40, count 2 2006.210.07:52:27.89#ibcon#first serial, iclass 40, count 2 2006.210.07:52:27.89#ibcon#enter sib2, iclass 40, count 2 2006.210.07:52:27.89#ibcon#flushed, iclass 40, count 2 2006.210.07:52:27.89#ibcon#about to write, iclass 40, count 2 2006.210.07:52:27.89#ibcon#wrote, iclass 40, count 2 2006.210.07:52:27.89#ibcon#about to read 3, iclass 40, count 2 2006.210.07:52:27.90#abcon#<5=/07 1.4 4.1 30.58 751006.3\r\n> 2006.210.07:52:27.91#ibcon#read 3, iclass 40, count 2 2006.210.07:52:27.91#ibcon#about to read 4, iclass 40, count 2 2006.210.07:52:27.91#ibcon#read 4, iclass 40, count 2 2006.210.07:52:27.91#ibcon#about to read 5, iclass 40, count 2 2006.210.07:52:27.91#ibcon#read 5, iclass 40, count 2 2006.210.07:52:27.91#ibcon#about to read 6, iclass 40, count 2 2006.210.07:52:27.91#ibcon#read 6, iclass 40, count 2 2006.210.07:52:27.91#ibcon#end of sib2, iclass 40, count 2 2006.210.07:52:27.91#ibcon#*mode == 0, iclass 40, count 2 2006.210.07:52:27.91#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.07:52:27.91#ibcon#[25=AT02-07\r\n] 2006.210.07:52:27.91#ibcon#*before write, iclass 40, count 2 2006.210.07:52:27.91#ibcon#enter sib2, iclass 40, count 2 2006.210.07:52:27.91#ibcon#flushed, iclass 40, count 2 2006.210.07:52:27.91#ibcon#about to write, iclass 40, count 2 2006.210.07:52:27.91#ibcon#wrote, iclass 40, count 2 2006.210.07:52:27.91#ibcon#about to read 3, iclass 40, count 2 2006.210.07:52:27.92#abcon#{5=INTERFACE CLEAR} 2006.210.07:52:27.94#ibcon#read 3, iclass 40, count 2 2006.210.07:52:27.94#ibcon#about to read 4, iclass 40, count 2 2006.210.07:52:27.94#ibcon#read 4, iclass 40, count 2 2006.210.07:52:27.94#ibcon#about to read 5, iclass 40, count 2 2006.210.07:52:27.94#ibcon#read 5, iclass 40, count 2 2006.210.07:52:27.94#ibcon#about to read 6, iclass 40, count 2 2006.210.07:52:27.94#ibcon#read 6, iclass 40, count 2 2006.210.07:52:27.94#ibcon#end of sib2, iclass 40, count 2 2006.210.07:52:27.94#ibcon#*after write, iclass 40, count 2 2006.210.07:52:27.94#ibcon#*before return 0, iclass 40, count 2 2006.210.07:52:27.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:27.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:27.94#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.07:52:27.94#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:27.94#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:27.98#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:52:28.06#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:28.06#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:28.06#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:52:28.06#ibcon#first serial, iclass 40, count 0 2006.210.07:52:28.06#ibcon#enter sib2, iclass 40, count 0 2006.210.07:52:28.06#ibcon#flushed, iclass 40, count 0 2006.210.07:52:28.06#ibcon#about to write, iclass 40, count 0 2006.210.07:52:28.06#ibcon#wrote, iclass 40, count 0 2006.210.07:52:28.06#ibcon#about to read 3, iclass 40, count 0 2006.210.07:52:28.08#ibcon#read 3, iclass 40, count 0 2006.210.07:52:28.08#ibcon#about to read 4, iclass 40, count 0 2006.210.07:52:28.08#ibcon#read 4, iclass 40, count 0 2006.210.07:52:28.08#ibcon#about to read 5, iclass 40, count 0 2006.210.07:52:28.08#ibcon#read 5, iclass 40, count 0 2006.210.07:52:28.08#ibcon#about to read 6, iclass 40, count 0 2006.210.07:52:28.08#ibcon#read 6, iclass 40, count 0 2006.210.07:52:28.08#ibcon#end of sib2, iclass 40, count 0 2006.210.07:52:28.08#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:52:28.08#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:52:28.08#ibcon#[25=USB\r\n] 2006.210.07:52:28.08#ibcon#*before write, iclass 40, count 0 2006.210.07:52:28.08#ibcon#enter sib2, iclass 40, count 0 2006.210.07:52:28.08#ibcon#flushed, iclass 40, count 0 2006.210.07:52:28.08#ibcon#about to write, iclass 40, count 0 2006.210.07:52:28.08#ibcon#wrote, iclass 40, count 0 2006.210.07:52:28.08#ibcon#about to read 3, iclass 40, count 0 2006.210.07:52:28.11#ibcon#read 3, iclass 40, count 0 2006.210.07:52:28.11#ibcon#about to read 4, iclass 40, count 0 2006.210.07:52:28.11#ibcon#read 4, iclass 40, count 0 2006.210.07:52:28.11#ibcon#about to read 5, iclass 40, count 0 2006.210.07:52:28.11#ibcon#read 5, iclass 40, count 0 2006.210.07:52:28.11#ibcon#about to read 6, iclass 40, count 0 2006.210.07:52:28.11#ibcon#read 6, iclass 40, count 0 2006.210.07:52:28.11#ibcon#end of sib2, iclass 40, count 0 2006.210.07:52:28.11#ibcon#*after write, iclass 40, count 0 2006.210.07:52:28.11#ibcon#*before return 0, iclass 40, count 0 2006.210.07:52:28.11#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:28.11#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:28.11#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:52:28.11#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:52:28.11$vc4f8/valo=3,672.99 2006.210.07:52:28.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.07:52:28.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.07:52:28.11#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:28.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:28.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:28.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:28.11#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:52:28.11#ibcon#first serial, iclass 10, count 0 2006.210.07:52:28.11#ibcon#enter sib2, iclass 10, count 0 2006.210.07:52:28.11#ibcon#flushed, iclass 10, count 0 2006.210.07:52:28.11#ibcon#about to write, iclass 10, count 0 2006.210.07:52:28.11#ibcon#wrote, iclass 10, count 0 2006.210.07:52:28.11#ibcon#about to read 3, iclass 10, count 0 2006.210.07:52:28.13#ibcon#read 3, iclass 10, count 0 2006.210.07:52:28.13#ibcon#about to read 4, iclass 10, count 0 2006.210.07:52:28.13#ibcon#read 4, iclass 10, count 0 2006.210.07:52:28.13#ibcon#about to read 5, iclass 10, count 0 2006.210.07:52:28.13#ibcon#read 5, iclass 10, count 0 2006.210.07:52:28.13#ibcon#about to read 6, iclass 10, count 0 2006.210.07:52:28.13#ibcon#read 6, iclass 10, count 0 2006.210.07:52:28.13#ibcon#end of sib2, iclass 10, count 0 2006.210.07:52:28.13#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:52:28.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:52:28.13#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:52:28.13#ibcon#*before write, iclass 10, count 0 2006.210.07:52:28.13#ibcon#enter sib2, iclass 10, count 0 2006.210.07:52:28.13#ibcon#flushed, iclass 10, count 0 2006.210.07:52:28.13#ibcon#about to write, iclass 10, count 0 2006.210.07:52:28.13#ibcon#wrote, iclass 10, count 0 2006.210.07:52:28.13#ibcon#about to read 3, iclass 10, count 0 2006.210.07:52:28.17#ibcon#read 3, iclass 10, count 0 2006.210.07:52:28.17#ibcon#about to read 4, iclass 10, count 0 2006.210.07:52:28.17#ibcon#read 4, iclass 10, count 0 2006.210.07:52:28.17#ibcon#about to read 5, iclass 10, count 0 2006.210.07:52:28.17#ibcon#read 5, iclass 10, count 0 2006.210.07:52:28.17#ibcon#about to read 6, iclass 10, count 0 2006.210.07:52:28.17#ibcon#read 6, iclass 10, count 0 2006.210.07:52:28.17#ibcon#end of sib2, iclass 10, count 0 2006.210.07:52:28.17#ibcon#*after write, iclass 10, count 0 2006.210.07:52:28.17#ibcon#*before return 0, iclass 10, count 0 2006.210.07:52:28.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:28.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:28.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:52:28.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:52:28.17$vc4f8/va=3,6 2006.210.07:52:28.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.07:52:28.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.07:52:28.17#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:28.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:28.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:28.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:28.23#ibcon#enter wrdev, iclass 12, count 2 2006.210.07:52:28.23#ibcon#first serial, iclass 12, count 2 2006.210.07:52:28.23#ibcon#enter sib2, iclass 12, count 2 2006.210.07:52:28.23#ibcon#flushed, iclass 12, count 2 2006.210.07:52:28.23#ibcon#about to write, iclass 12, count 2 2006.210.07:52:28.23#ibcon#wrote, iclass 12, count 2 2006.210.07:52:28.23#ibcon#about to read 3, iclass 12, count 2 2006.210.07:52:28.25#ibcon#read 3, iclass 12, count 2 2006.210.07:52:28.25#ibcon#about to read 4, iclass 12, count 2 2006.210.07:52:28.25#ibcon#read 4, iclass 12, count 2 2006.210.07:52:28.25#ibcon#about to read 5, iclass 12, count 2 2006.210.07:52:28.25#ibcon#read 5, iclass 12, count 2 2006.210.07:52:28.25#ibcon#about to read 6, iclass 12, count 2 2006.210.07:52:28.25#ibcon#read 6, iclass 12, count 2 2006.210.07:52:28.25#ibcon#end of sib2, iclass 12, count 2 2006.210.07:52:28.25#ibcon#*mode == 0, iclass 12, count 2 2006.210.07:52:28.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.07:52:28.25#ibcon#[25=AT03-06\r\n] 2006.210.07:52:28.25#ibcon#*before write, iclass 12, count 2 2006.210.07:52:28.25#ibcon#enter sib2, iclass 12, count 2 2006.210.07:52:28.25#ibcon#flushed, iclass 12, count 2 2006.210.07:52:28.25#ibcon#about to write, iclass 12, count 2 2006.210.07:52:28.25#ibcon#wrote, iclass 12, count 2 2006.210.07:52:28.25#ibcon#about to read 3, iclass 12, count 2 2006.210.07:52:28.28#ibcon#read 3, iclass 12, count 2 2006.210.07:52:28.28#ibcon#about to read 4, iclass 12, count 2 2006.210.07:52:28.28#ibcon#read 4, iclass 12, count 2 2006.210.07:52:28.28#ibcon#about to read 5, iclass 12, count 2 2006.210.07:52:28.28#ibcon#read 5, iclass 12, count 2 2006.210.07:52:28.28#ibcon#about to read 6, iclass 12, count 2 2006.210.07:52:28.28#ibcon#read 6, iclass 12, count 2 2006.210.07:52:28.28#ibcon#end of sib2, iclass 12, count 2 2006.210.07:52:28.28#ibcon#*after write, iclass 12, count 2 2006.210.07:52:28.28#ibcon#*before return 0, iclass 12, count 2 2006.210.07:52:28.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:28.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:28.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.07:52:28.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:28.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:28.40#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:28.40#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:28.40#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:52:28.40#ibcon#first serial, iclass 12, count 0 2006.210.07:52:28.40#ibcon#enter sib2, iclass 12, count 0 2006.210.07:52:28.40#ibcon#flushed, iclass 12, count 0 2006.210.07:52:28.40#ibcon#about to write, iclass 12, count 0 2006.210.07:52:28.40#ibcon#wrote, iclass 12, count 0 2006.210.07:52:28.40#ibcon#about to read 3, iclass 12, count 0 2006.210.07:52:28.42#ibcon#read 3, iclass 12, count 0 2006.210.07:52:28.42#ibcon#about to read 4, iclass 12, count 0 2006.210.07:52:28.42#ibcon#read 4, iclass 12, count 0 2006.210.07:52:28.42#ibcon#about to read 5, iclass 12, count 0 2006.210.07:52:28.42#ibcon#read 5, iclass 12, count 0 2006.210.07:52:28.42#ibcon#about to read 6, iclass 12, count 0 2006.210.07:52:28.42#ibcon#read 6, iclass 12, count 0 2006.210.07:52:28.42#ibcon#end of sib2, iclass 12, count 0 2006.210.07:52:28.42#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:52:28.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:52:28.42#ibcon#[25=USB\r\n] 2006.210.07:52:28.42#ibcon#*before write, iclass 12, count 0 2006.210.07:52:28.42#ibcon#enter sib2, iclass 12, count 0 2006.210.07:52:28.42#ibcon#flushed, iclass 12, count 0 2006.210.07:52:28.42#ibcon#about to write, iclass 12, count 0 2006.210.07:52:28.42#ibcon#wrote, iclass 12, count 0 2006.210.07:52:28.42#ibcon#about to read 3, iclass 12, count 0 2006.210.07:52:28.45#ibcon#read 3, iclass 12, count 0 2006.210.07:52:28.45#ibcon#about to read 4, iclass 12, count 0 2006.210.07:52:28.45#ibcon#read 4, iclass 12, count 0 2006.210.07:52:28.45#ibcon#about to read 5, iclass 12, count 0 2006.210.07:52:28.45#ibcon#read 5, iclass 12, count 0 2006.210.07:52:28.45#ibcon#about to read 6, iclass 12, count 0 2006.210.07:52:28.45#ibcon#read 6, iclass 12, count 0 2006.210.07:52:28.45#ibcon#end of sib2, iclass 12, count 0 2006.210.07:52:28.45#ibcon#*after write, iclass 12, count 0 2006.210.07:52:28.45#ibcon#*before return 0, iclass 12, count 0 2006.210.07:52:28.45#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:28.45#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:28.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:52:28.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:52:28.45$vc4f8/valo=4,832.99 2006.210.07:52:28.45#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.07:52:28.45#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.07:52:28.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:28.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:28.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:28.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:28.45#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:52:28.45#ibcon#first serial, iclass 14, count 0 2006.210.07:52:28.45#ibcon#enter sib2, iclass 14, count 0 2006.210.07:52:28.45#ibcon#flushed, iclass 14, count 0 2006.210.07:52:28.45#ibcon#about to write, iclass 14, count 0 2006.210.07:52:28.45#ibcon#wrote, iclass 14, count 0 2006.210.07:52:28.45#ibcon#about to read 3, iclass 14, count 0 2006.210.07:52:28.47#ibcon#read 3, iclass 14, count 0 2006.210.07:52:28.47#ibcon#about to read 4, iclass 14, count 0 2006.210.07:52:28.47#ibcon#read 4, iclass 14, count 0 2006.210.07:52:28.47#ibcon#about to read 5, iclass 14, count 0 2006.210.07:52:28.47#ibcon#read 5, iclass 14, count 0 2006.210.07:52:28.47#ibcon#about to read 6, iclass 14, count 0 2006.210.07:52:28.47#ibcon#read 6, iclass 14, count 0 2006.210.07:52:28.47#ibcon#end of sib2, iclass 14, count 0 2006.210.07:52:28.47#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:52:28.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:52:28.47#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:52:28.47#ibcon#*before write, iclass 14, count 0 2006.210.07:52:28.47#ibcon#enter sib2, iclass 14, count 0 2006.210.07:52:28.47#ibcon#flushed, iclass 14, count 0 2006.210.07:52:28.47#ibcon#about to write, iclass 14, count 0 2006.210.07:52:28.47#ibcon#wrote, iclass 14, count 0 2006.210.07:52:28.47#ibcon#about to read 3, iclass 14, count 0 2006.210.07:52:28.51#ibcon#read 3, iclass 14, count 0 2006.210.07:52:28.51#ibcon#about to read 4, iclass 14, count 0 2006.210.07:52:28.51#ibcon#read 4, iclass 14, count 0 2006.210.07:52:28.51#ibcon#about to read 5, iclass 14, count 0 2006.210.07:52:28.51#ibcon#read 5, iclass 14, count 0 2006.210.07:52:28.51#ibcon#about to read 6, iclass 14, count 0 2006.210.07:52:28.51#ibcon#read 6, iclass 14, count 0 2006.210.07:52:28.51#ibcon#end of sib2, iclass 14, count 0 2006.210.07:52:28.51#ibcon#*after write, iclass 14, count 0 2006.210.07:52:28.51#ibcon#*before return 0, iclass 14, count 0 2006.210.07:52:28.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:28.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:28.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:52:28.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:52:28.51$vc4f8/va=4,7 2006.210.07:52:28.51#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.07:52:28.51#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.07:52:28.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:28.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:28.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:28.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:28.57#ibcon#enter wrdev, iclass 16, count 2 2006.210.07:52:28.57#ibcon#first serial, iclass 16, count 2 2006.210.07:52:28.57#ibcon#enter sib2, iclass 16, count 2 2006.210.07:52:28.57#ibcon#flushed, iclass 16, count 2 2006.210.07:52:28.57#ibcon#about to write, iclass 16, count 2 2006.210.07:52:28.57#ibcon#wrote, iclass 16, count 2 2006.210.07:52:28.57#ibcon#about to read 3, iclass 16, count 2 2006.210.07:52:28.59#ibcon#read 3, iclass 16, count 2 2006.210.07:52:28.59#ibcon#about to read 4, iclass 16, count 2 2006.210.07:52:28.59#ibcon#read 4, iclass 16, count 2 2006.210.07:52:28.59#ibcon#about to read 5, iclass 16, count 2 2006.210.07:52:28.59#ibcon#read 5, iclass 16, count 2 2006.210.07:52:28.59#ibcon#about to read 6, iclass 16, count 2 2006.210.07:52:28.59#ibcon#read 6, iclass 16, count 2 2006.210.07:52:28.59#ibcon#end of sib2, iclass 16, count 2 2006.210.07:52:28.59#ibcon#*mode == 0, iclass 16, count 2 2006.210.07:52:28.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.07:52:28.59#ibcon#[25=AT04-07\r\n] 2006.210.07:52:28.59#ibcon#*before write, iclass 16, count 2 2006.210.07:52:28.59#ibcon#enter sib2, iclass 16, count 2 2006.210.07:52:28.59#ibcon#flushed, iclass 16, count 2 2006.210.07:52:28.59#ibcon#about to write, iclass 16, count 2 2006.210.07:52:28.59#ibcon#wrote, iclass 16, count 2 2006.210.07:52:28.59#ibcon#about to read 3, iclass 16, count 2 2006.210.07:52:28.62#ibcon#read 3, iclass 16, count 2 2006.210.07:52:28.62#ibcon#about to read 4, iclass 16, count 2 2006.210.07:52:28.62#ibcon#read 4, iclass 16, count 2 2006.210.07:52:28.62#ibcon#about to read 5, iclass 16, count 2 2006.210.07:52:28.62#ibcon#read 5, iclass 16, count 2 2006.210.07:52:28.62#ibcon#about to read 6, iclass 16, count 2 2006.210.07:52:28.62#ibcon#read 6, iclass 16, count 2 2006.210.07:52:28.62#ibcon#end of sib2, iclass 16, count 2 2006.210.07:52:28.62#ibcon#*after write, iclass 16, count 2 2006.210.07:52:28.62#ibcon#*before return 0, iclass 16, count 2 2006.210.07:52:28.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:28.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:28.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.07:52:28.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:28.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:28.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:28.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:28.74#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:52:28.74#ibcon#first serial, iclass 16, count 0 2006.210.07:52:28.74#ibcon#enter sib2, iclass 16, count 0 2006.210.07:52:28.74#ibcon#flushed, iclass 16, count 0 2006.210.07:52:28.74#ibcon#about to write, iclass 16, count 0 2006.210.07:52:28.74#ibcon#wrote, iclass 16, count 0 2006.210.07:52:28.74#ibcon#about to read 3, iclass 16, count 0 2006.210.07:52:28.76#ibcon#read 3, iclass 16, count 0 2006.210.07:52:28.76#ibcon#about to read 4, iclass 16, count 0 2006.210.07:52:28.76#ibcon#read 4, iclass 16, count 0 2006.210.07:52:28.76#ibcon#about to read 5, iclass 16, count 0 2006.210.07:52:28.76#ibcon#read 5, iclass 16, count 0 2006.210.07:52:28.76#ibcon#about to read 6, iclass 16, count 0 2006.210.07:52:28.76#ibcon#read 6, iclass 16, count 0 2006.210.07:52:28.76#ibcon#end of sib2, iclass 16, count 0 2006.210.07:52:28.76#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:52:28.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:52:28.76#ibcon#[25=USB\r\n] 2006.210.07:52:28.76#ibcon#*before write, iclass 16, count 0 2006.210.07:52:28.76#ibcon#enter sib2, iclass 16, count 0 2006.210.07:52:28.76#ibcon#flushed, iclass 16, count 0 2006.210.07:52:28.76#ibcon#about to write, iclass 16, count 0 2006.210.07:52:28.76#ibcon#wrote, iclass 16, count 0 2006.210.07:52:28.76#ibcon#about to read 3, iclass 16, count 0 2006.210.07:52:28.79#ibcon#read 3, iclass 16, count 0 2006.210.07:52:28.79#ibcon#about to read 4, iclass 16, count 0 2006.210.07:52:28.79#ibcon#read 4, iclass 16, count 0 2006.210.07:52:28.79#ibcon#about to read 5, iclass 16, count 0 2006.210.07:52:28.79#ibcon#read 5, iclass 16, count 0 2006.210.07:52:28.79#ibcon#about to read 6, iclass 16, count 0 2006.210.07:52:28.79#ibcon#read 6, iclass 16, count 0 2006.210.07:52:28.79#ibcon#end of sib2, iclass 16, count 0 2006.210.07:52:28.79#ibcon#*after write, iclass 16, count 0 2006.210.07:52:28.79#ibcon#*before return 0, iclass 16, count 0 2006.210.07:52:28.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:28.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:28.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:52:28.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:52:28.79$vc4f8/valo=5,652.99 2006.210.07:52:28.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.07:52:28.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.07:52:28.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:28.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:28.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:28.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:28.79#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:52:28.79#ibcon#first serial, iclass 18, count 0 2006.210.07:52:28.79#ibcon#enter sib2, iclass 18, count 0 2006.210.07:52:28.79#ibcon#flushed, iclass 18, count 0 2006.210.07:52:28.79#ibcon#about to write, iclass 18, count 0 2006.210.07:52:28.79#ibcon#wrote, iclass 18, count 0 2006.210.07:52:28.79#ibcon#about to read 3, iclass 18, count 0 2006.210.07:52:28.81#ibcon#read 3, iclass 18, count 0 2006.210.07:52:28.81#ibcon#about to read 4, iclass 18, count 0 2006.210.07:52:28.81#ibcon#read 4, iclass 18, count 0 2006.210.07:52:28.81#ibcon#about to read 5, iclass 18, count 0 2006.210.07:52:28.81#ibcon#read 5, iclass 18, count 0 2006.210.07:52:28.81#ibcon#about to read 6, iclass 18, count 0 2006.210.07:52:28.81#ibcon#read 6, iclass 18, count 0 2006.210.07:52:28.81#ibcon#end of sib2, iclass 18, count 0 2006.210.07:52:28.81#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:52:28.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:52:28.81#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:52:28.81#ibcon#*before write, iclass 18, count 0 2006.210.07:52:28.81#ibcon#enter sib2, iclass 18, count 0 2006.210.07:52:28.81#ibcon#flushed, iclass 18, count 0 2006.210.07:52:28.81#ibcon#about to write, iclass 18, count 0 2006.210.07:52:28.81#ibcon#wrote, iclass 18, count 0 2006.210.07:52:28.81#ibcon#about to read 3, iclass 18, count 0 2006.210.07:52:28.85#ibcon#read 3, iclass 18, count 0 2006.210.07:52:28.85#ibcon#about to read 4, iclass 18, count 0 2006.210.07:52:28.85#ibcon#read 4, iclass 18, count 0 2006.210.07:52:28.85#ibcon#about to read 5, iclass 18, count 0 2006.210.07:52:28.85#ibcon#read 5, iclass 18, count 0 2006.210.07:52:28.85#ibcon#about to read 6, iclass 18, count 0 2006.210.07:52:28.85#ibcon#read 6, iclass 18, count 0 2006.210.07:52:28.85#ibcon#end of sib2, iclass 18, count 0 2006.210.07:52:28.85#ibcon#*after write, iclass 18, count 0 2006.210.07:52:28.85#ibcon#*before return 0, iclass 18, count 0 2006.210.07:52:28.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:28.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:28.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:52:28.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:52:28.85$vc4f8/va=5,7 2006.210.07:52:28.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.07:52:28.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.07:52:28.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:28.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:28.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:28.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:28.91#ibcon#enter wrdev, iclass 20, count 2 2006.210.07:52:28.91#ibcon#first serial, iclass 20, count 2 2006.210.07:52:28.91#ibcon#enter sib2, iclass 20, count 2 2006.210.07:52:28.91#ibcon#flushed, iclass 20, count 2 2006.210.07:52:28.91#ibcon#about to write, iclass 20, count 2 2006.210.07:52:28.91#ibcon#wrote, iclass 20, count 2 2006.210.07:52:28.91#ibcon#about to read 3, iclass 20, count 2 2006.210.07:52:28.93#ibcon#read 3, iclass 20, count 2 2006.210.07:52:28.93#ibcon#about to read 4, iclass 20, count 2 2006.210.07:52:28.93#ibcon#read 4, iclass 20, count 2 2006.210.07:52:28.93#ibcon#about to read 5, iclass 20, count 2 2006.210.07:52:28.93#ibcon#read 5, iclass 20, count 2 2006.210.07:52:28.93#ibcon#about to read 6, iclass 20, count 2 2006.210.07:52:28.93#ibcon#read 6, iclass 20, count 2 2006.210.07:52:28.93#ibcon#end of sib2, iclass 20, count 2 2006.210.07:52:28.93#ibcon#*mode == 0, iclass 20, count 2 2006.210.07:52:28.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.07:52:28.93#ibcon#[25=AT05-07\r\n] 2006.210.07:52:28.93#ibcon#*before write, iclass 20, count 2 2006.210.07:52:28.93#ibcon#enter sib2, iclass 20, count 2 2006.210.07:52:28.93#ibcon#flushed, iclass 20, count 2 2006.210.07:52:28.93#ibcon#about to write, iclass 20, count 2 2006.210.07:52:28.93#ibcon#wrote, iclass 20, count 2 2006.210.07:52:28.93#ibcon#about to read 3, iclass 20, count 2 2006.210.07:52:28.96#ibcon#read 3, iclass 20, count 2 2006.210.07:52:28.96#ibcon#about to read 4, iclass 20, count 2 2006.210.07:52:28.96#ibcon#read 4, iclass 20, count 2 2006.210.07:52:28.96#ibcon#about to read 5, iclass 20, count 2 2006.210.07:52:28.96#ibcon#read 5, iclass 20, count 2 2006.210.07:52:28.96#ibcon#about to read 6, iclass 20, count 2 2006.210.07:52:28.96#ibcon#read 6, iclass 20, count 2 2006.210.07:52:28.96#ibcon#end of sib2, iclass 20, count 2 2006.210.07:52:28.96#ibcon#*after write, iclass 20, count 2 2006.210.07:52:28.96#ibcon#*before return 0, iclass 20, count 2 2006.210.07:52:28.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:28.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:28.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.07:52:28.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:28.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:29.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:29.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:29.08#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:52:29.08#ibcon#first serial, iclass 20, count 0 2006.210.07:52:29.08#ibcon#enter sib2, iclass 20, count 0 2006.210.07:52:29.08#ibcon#flushed, iclass 20, count 0 2006.210.07:52:29.08#ibcon#about to write, iclass 20, count 0 2006.210.07:52:29.08#ibcon#wrote, iclass 20, count 0 2006.210.07:52:29.08#ibcon#about to read 3, iclass 20, count 0 2006.210.07:52:29.10#ibcon#read 3, iclass 20, count 0 2006.210.07:52:29.10#ibcon#about to read 4, iclass 20, count 0 2006.210.07:52:29.10#ibcon#read 4, iclass 20, count 0 2006.210.07:52:29.10#ibcon#about to read 5, iclass 20, count 0 2006.210.07:52:29.10#ibcon#read 5, iclass 20, count 0 2006.210.07:52:29.10#ibcon#about to read 6, iclass 20, count 0 2006.210.07:52:29.10#ibcon#read 6, iclass 20, count 0 2006.210.07:52:29.10#ibcon#end of sib2, iclass 20, count 0 2006.210.07:52:29.10#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:52:29.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:52:29.10#ibcon#[25=USB\r\n] 2006.210.07:52:29.10#ibcon#*before write, iclass 20, count 0 2006.210.07:52:29.10#ibcon#enter sib2, iclass 20, count 0 2006.210.07:52:29.10#ibcon#flushed, iclass 20, count 0 2006.210.07:52:29.10#ibcon#about to write, iclass 20, count 0 2006.210.07:52:29.10#ibcon#wrote, iclass 20, count 0 2006.210.07:52:29.10#ibcon#about to read 3, iclass 20, count 0 2006.210.07:52:29.13#ibcon#read 3, iclass 20, count 0 2006.210.07:52:29.13#ibcon#about to read 4, iclass 20, count 0 2006.210.07:52:29.13#ibcon#read 4, iclass 20, count 0 2006.210.07:52:29.13#ibcon#about to read 5, iclass 20, count 0 2006.210.07:52:29.13#ibcon#read 5, iclass 20, count 0 2006.210.07:52:29.13#ibcon#about to read 6, iclass 20, count 0 2006.210.07:52:29.13#ibcon#read 6, iclass 20, count 0 2006.210.07:52:29.13#ibcon#end of sib2, iclass 20, count 0 2006.210.07:52:29.13#ibcon#*after write, iclass 20, count 0 2006.210.07:52:29.13#ibcon#*before return 0, iclass 20, count 0 2006.210.07:52:29.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:29.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:29.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:52:29.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:52:29.13$vc4f8/valo=6,772.99 2006.210.07:52:29.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:52:29.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:52:29.13#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:29.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:29.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:29.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:29.13#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:52:29.13#ibcon#first serial, iclass 22, count 0 2006.210.07:52:29.13#ibcon#enter sib2, iclass 22, count 0 2006.210.07:52:29.13#ibcon#flushed, iclass 22, count 0 2006.210.07:52:29.13#ibcon#about to write, iclass 22, count 0 2006.210.07:52:29.13#ibcon#wrote, iclass 22, count 0 2006.210.07:52:29.13#ibcon#about to read 3, iclass 22, count 0 2006.210.07:52:29.15#ibcon#read 3, iclass 22, count 0 2006.210.07:52:29.15#ibcon#about to read 4, iclass 22, count 0 2006.210.07:52:29.15#ibcon#read 4, iclass 22, count 0 2006.210.07:52:29.15#ibcon#about to read 5, iclass 22, count 0 2006.210.07:52:29.15#ibcon#read 5, iclass 22, count 0 2006.210.07:52:29.15#ibcon#about to read 6, iclass 22, count 0 2006.210.07:52:29.15#ibcon#read 6, iclass 22, count 0 2006.210.07:52:29.15#ibcon#end of sib2, iclass 22, count 0 2006.210.07:52:29.15#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:52:29.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:52:29.15#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:52:29.15#ibcon#*before write, iclass 22, count 0 2006.210.07:52:29.15#ibcon#enter sib2, iclass 22, count 0 2006.210.07:52:29.15#ibcon#flushed, iclass 22, count 0 2006.210.07:52:29.15#ibcon#about to write, iclass 22, count 0 2006.210.07:52:29.15#ibcon#wrote, iclass 22, count 0 2006.210.07:52:29.15#ibcon#about to read 3, iclass 22, count 0 2006.210.07:52:29.19#ibcon#read 3, iclass 22, count 0 2006.210.07:52:29.19#ibcon#about to read 4, iclass 22, count 0 2006.210.07:52:29.19#ibcon#read 4, iclass 22, count 0 2006.210.07:52:29.19#ibcon#about to read 5, iclass 22, count 0 2006.210.07:52:29.19#ibcon#read 5, iclass 22, count 0 2006.210.07:52:29.19#ibcon#about to read 6, iclass 22, count 0 2006.210.07:52:29.19#ibcon#read 6, iclass 22, count 0 2006.210.07:52:29.19#ibcon#end of sib2, iclass 22, count 0 2006.210.07:52:29.19#ibcon#*after write, iclass 22, count 0 2006.210.07:52:29.19#ibcon#*before return 0, iclass 22, count 0 2006.210.07:52:29.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:29.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:29.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:52:29.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:52:29.19$vc4f8/va=6,6 2006.210.07:52:29.19#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.07:52:29.19#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.07:52:29.19#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:29.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:52:29.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:52:29.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:52:29.25#ibcon#enter wrdev, iclass 24, count 2 2006.210.07:52:29.25#ibcon#first serial, iclass 24, count 2 2006.210.07:52:29.25#ibcon#enter sib2, iclass 24, count 2 2006.210.07:52:29.25#ibcon#flushed, iclass 24, count 2 2006.210.07:52:29.25#ibcon#about to write, iclass 24, count 2 2006.210.07:52:29.25#ibcon#wrote, iclass 24, count 2 2006.210.07:52:29.25#ibcon#about to read 3, iclass 24, count 2 2006.210.07:52:29.27#ibcon#read 3, iclass 24, count 2 2006.210.07:52:29.27#ibcon#about to read 4, iclass 24, count 2 2006.210.07:52:29.27#ibcon#read 4, iclass 24, count 2 2006.210.07:52:29.27#ibcon#about to read 5, iclass 24, count 2 2006.210.07:52:29.27#ibcon#read 5, iclass 24, count 2 2006.210.07:52:29.27#ibcon#about to read 6, iclass 24, count 2 2006.210.07:52:29.27#ibcon#read 6, iclass 24, count 2 2006.210.07:52:29.27#ibcon#end of sib2, iclass 24, count 2 2006.210.07:52:29.27#ibcon#*mode == 0, iclass 24, count 2 2006.210.07:52:29.27#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.07:52:29.27#ibcon#[25=AT06-06\r\n] 2006.210.07:52:29.27#ibcon#*before write, iclass 24, count 2 2006.210.07:52:29.27#ibcon#enter sib2, iclass 24, count 2 2006.210.07:52:29.27#ibcon#flushed, iclass 24, count 2 2006.210.07:52:29.27#ibcon#about to write, iclass 24, count 2 2006.210.07:52:29.27#ibcon#wrote, iclass 24, count 2 2006.210.07:52:29.27#ibcon#about to read 3, iclass 24, count 2 2006.210.07:52:29.30#ibcon#read 3, iclass 24, count 2 2006.210.07:52:29.30#ibcon#about to read 4, iclass 24, count 2 2006.210.07:52:29.30#ibcon#read 4, iclass 24, count 2 2006.210.07:52:29.30#ibcon#about to read 5, iclass 24, count 2 2006.210.07:52:29.30#ibcon#read 5, iclass 24, count 2 2006.210.07:52:29.30#ibcon#about to read 6, iclass 24, count 2 2006.210.07:52:29.30#ibcon#read 6, iclass 24, count 2 2006.210.07:52:29.30#ibcon#end of sib2, iclass 24, count 2 2006.210.07:52:29.30#ibcon#*after write, iclass 24, count 2 2006.210.07:52:29.30#ibcon#*before return 0, iclass 24, count 2 2006.210.07:52:29.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:52:29.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.07:52:29.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.07:52:29.30#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:29.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:52:29.42#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:52:29.42#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:52:29.42#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:52:29.42#ibcon#first serial, iclass 24, count 0 2006.210.07:52:29.42#ibcon#enter sib2, iclass 24, count 0 2006.210.07:52:29.42#ibcon#flushed, iclass 24, count 0 2006.210.07:52:29.42#ibcon#about to write, iclass 24, count 0 2006.210.07:52:29.42#ibcon#wrote, iclass 24, count 0 2006.210.07:52:29.42#ibcon#about to read 3, iclass 24, count 0 2006.210.07:52:29.44#ibcon#read 3, iclass 24, count 0 2006.210.07:52:29.44#ibcon#about to read 4, iclass 24, count 0 2006.210.07:52:29.44#ibcon#read 4, iclass 24, count 0 2006.210.07:52:29.44#ibcon#about to read 5, iclass 24, count 0 2006.210.07:52:29.44#ibcon#read 5, iclass 24, count 0 2006.210.07:52:29.44#ibcon#about to read 6, iclass 24, count 0 2006.210.07:52:29.44#ibcon#read 6, iclass 24, count 0 2006.210.07:52:29.44#ibcon#end of sib2, iclass 24, count 0 2006.210.07:52:29.44#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:52:29.44#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:52:29.44#ibcon#[25=USB\r\n] 2006.210.07:52:29.44#ibcon#*before write, iclass 24, count 0 2006.210.07:52:29.44#ibcon#enter sib2, iclass 24, count 0 2006.210.07:52:29.44#ibcon#flushed, iclass 24, count 0 2006.210.07:52:29.44#ibcon#about to write, iclass 24, count 0 2006.210.07:52:29.44#ibcon#wrote, iclass 24, count 0 2006.210.07:52:29.44#ibcon#about to read 3, iclass 24, count 0 2006.210.07:52:29.47#ibcon#read 3, iclass 24, count 0 2006.210.07:52:29.47#ibcon#about to read 4, iclass 24, count 0 2006.210.07:52:29.47#ibcon#read 4, iclass 24, count 0 2006.210.07:52:29.47#ibcon#about to read 5, iclass 24, count 0 2006.210.07:52:29.47#ibcon#read 5, iclass 24, count 0 2006.210.07:52:29.47#ibcon#about to read 6, iclass 24, count 0 2006.210.07:52:29.47#ibcon#read 6, iclass 24, count 0 2006.210.07:52:29.47#ibcon#end of sib2, iclass 24, count 0 2006.210.07:52:29.47#ibcon#*after write, iclass 24, count 0 2006.210.07:52:29.47#ibcon#*before return 0, iclass 24, count 0 2006.210.07:52:29.47#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:52:29.47#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.07:52:29.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:52:29.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:52:29.47$vc4f8/valo=7,832.99 2006.210.07:52:29.47#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:52:29.47#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:52:29.47#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:29.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:52:29.47#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:52:29.47#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:52:29.47#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:52:29.47#ibcon#first serial, iclass 26, count 0 2006.210.07:52:29.47#ibcon#enter sib2, iclass 26, count 0 2006.210.07:52:29.47#ibcon#flushed, iclass 26, count 0 2006.210.07:52:29.47#ibcon#about to write, iclass 26, count 0 2006.210.07:52:29.47#ibcon#wrote, iclass 26, count 0 2006.210.07:52:29.47#ibcon#about to read 3, iclass 26, count 0 2006.210.07:52:29.49#ibcon#read 3, iclass 26, count 0 2006.210.07:52:29.49#ibcon#about to read 4, iclass 26, count 0 2006.210.07:52:29.49#ibcon#read 4, iclass 26, count 0 2006.210.07:52:29.49#ibcon#about to read 5, iclass 26, count 0 2006.210.07:52:29.49#ibcon#read 5, iclass 26, count 0 2006.210.07:52:29.49#ibcon#about to read 6, iclass 26, count 0 2006.210.07:52:29.49#ibcon#read 6, iclass 26, count 0 2006.210.07:52:29.49#ibcon#end of sib2, iclass 26, count 0 2006.210.07:52:29.49#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:52:29.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:52:29.49#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:52:29.49#ibcon#*before write, iclass 26, count 0 2006.210.07:52:29.49#ibcon#enter sib2, iclass 26, count 0 2006.210.07:52:29.49#ibcon#flushed, iclass 26, count 0 2006.210.07:52:29.49#ibcon#about to write, iclass 26, count 0 2006.210.07:52:29.49#ibcon#wrote, iclass 26, count 0 2006.210.07:52:29.49#ibcon#about to read 3, iclass 26, count 0 2006.210.07:52:29.53#ibcon#read 3, iclass 26, count 0 2006.210.07:52:29.53#ibcon#about to read 4, iclass 26, count 0 2006.210.07:52:29.53#ibcon#read 4, iclass 26, count 0 2006.210.07:52:29.53#ibcon#about to read 5, iclass 26, count 0 2006.210.07:52:29.53#ibcon#read 5, iclass 26, count 0 2006.210.07:52:29.53#ibcon#about to read 6, iclass 26, count 0 2006.210.07:52:29.53#ibcon#read 6, iclass 26, count 0 2006.210.07:52:29.53#ibcon#end of sib2, iclass 26, count 0 2006.210.07:52:29.53#ibcon#*after write, iclass 26, count 0 2006.210.07:52:29.53#ibcon#*before return 0, iclass 26, count 0 2006.210.07:52:29.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:52:29.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:52:29.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:52:29.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:52:29.53$vc4f8/va=7,6 2006.210.07:52:29.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.07:52:29.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.07:52:29.53#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:29.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:52:29.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:52:29.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:52:29.59#ibcon#enter wrdev, iclass 28, count 2 2006.210.07:52:29.59#ibcon#first serial, iclass 28, count 2 2006.210.07:52:29.59#ibcon#enter sib2, iclass 28, count 2 2006.210.07:52:29.59#ibcon#flushed, iclass 28, count 2 2006.210.07:52:29.59#ibcon#about to write, iclass 28, count 2 2006.210.07:52:29.59#ibcon#wrote, iclass 28, count 2 2006.210.07:52:29.59#ibcon#about to read 3, iclass 28, count 2 2006.210.07:52:29.61#ibcon#read 3, iclass 28, count 2 2006.210.07:52:29.61#ibcon#about to read 4, iclass 28, count 2 2006.210.07:52:29.61#ibcon#read 4, iclass 28, count 2 2006.210.07:52:29.61#ibcon#about to read 5, iclass 28, count 2 2006.210.07:52:29.61#ibcon#read 5, iclass 28, count 2 2006.210.07:52:29.61#ibcon#about to read 6, iclass 28, count 2 2006.210.07:52:29.61#ibcon#read 6, iclass 28, count 2 2006.210.07:52:29.61#ibcon#end of sib2, iclass 28, count 2 2006.210.07:52:29.61#ibcon#*mode == 0, iclass 28, count 2 2006.210.07:52:29.61#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.07:52:29.61#ibcon#[25=AT07-06\r\n] 2006.210.07:52:29.61#ibcon#*before write, iclass 28, count 2 2006.210.07:52:29.61#ibcon#enter sib2, iclass 28, count 2 2006.210.07:52:29.61#ibcon#flushed, iclass 28, count 2 2006.210.07:52:29.61#ibcon#about to write, iclass 28, count 2 2006.210.07:52:29.61#ibcon#wrote, iclass 28, count 2 2006.210.07:52:29.61#ibcon#about to read 3, iclass 28, count 2 2006.210.07:52:29.64#ibcon#read 3, iclass 28, count 2 2006.210.07:52:29.64#ibcon#about to read 4, iclass 28, count 2 2006.210.07:52:29.64#ibcon#read 4, iclass 28, count 2 2006.210.07:52:29.64#ibcon#about to read 5, iclass 28, count 2 2006.210.07:52:29.64#ibcon#read 5, iclass 28, count 2 2006.210.07:52:29.64#ibcon#about to read 6, iclass 28, count 2 2006.210.07:52:29.64#ibcon#read 6, iclass 28, count 2 2006.210.07:52:29.64#ibcon#end of sib2, iclass 28, count 2 2006.210.07:52:29.64#ibcon#*after write, iclass 28, count 2 2006.210.07:52:29.64#ibcon#*before return 0, iclass 28, count 2 2006.210.07:52:29.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:52:29.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.07:52:29.64#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.07:52:29.64#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:29.64#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:52:29.76#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:52:29.76#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:52:29.76#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:52:29.76#ibcon#first serial, iclass 28, count 0 2006.210.07:52:29.76#ibcon#enter sib2, iclass 28, count 0 2006.210.07:52:29.76#ibcon#flushed, iclass 28, count 0 2006.210.07:52:29.76#ibcon#about to write, iclass 28, count 0 2006.210.07:52:29.76#ibcon#wrote, iclass 28, count 0 2006.210.07:52:29.76#ibcon#about to read 3, iclass 28, count 0 2006.210.07:52:29.78#ibcon#read 3, iclass 28, count 0 2006.210.07:52:29.78#ibcon#about to read 4, iclass 28, count 0 2006.210.07:52:29.78#ibcon#read 4, iclass 28, count 0 2006.210.07:52:29.78#ibcon#about to read 5, iclass 28, count 0 2006.210.07:52:29.78#ibcon#read 5, iclass 28, count 0 2006.210.07:52:29.78#ibcon#about to read 6, iclass 28, count 0 2006.210.07:52:29.78#ibcon#read 6, iclass 28, count 0 2006.210.07:52:29.78#ibcon#end of sib2, iclass 28, count 0 2006.210.07:52:29.78#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:52:29.78#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:52:29.78#ibcon#[25=USB\r\n] 2006.210.07:52:29.78#ibcon#*before write, iclass 28, count 0 2006.210.07:52:29.78#ibcon#enter sib2, iclass 28, count 0 2006.210.07:52:29.78#ibcon#flushed, iclass 28, count 0 2006.210.07:52:29.78#ibcon#about to write, iclass 28, count 0 2006.210.07:52:29.78#ibcon#wrote, iclass 28, count 0 2006.210.07:52:29.78#ibcon#about to read 3, iclass 28, count 0 2006.210.07:52:29.81#ibcon#read 3, iclass 28, count 0 2006.210.07:52:29.81#ibcon#about to read 4, iclass 28, count 0 2006.210.07:52:29.81#ibcon#read 4, iclass 28, count 0 2006.210.07:52:29.81#ibcon#about to read 5, iclass 28, count 0 2006.210.07:52:29.81#ibcon#read 5, iclass 28, count 0 2006.210.07:52:29.81#ibcon#about to read 6, iclass 28, count 0 2006.210.07:52:29.81#ibcon#read 6, iclass 28, count 0 2006.210.07:52:29.81#ibcon#end of sib2, iclass 28, count 0 2006.210.07:52:29.81#ibcon#*after write, iclass 28, count 0 2006.210.07:52:29.81#ibcon#*before return 0, iclass 28, count 0 2006.210.07:52:29.81#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:52:29.81#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.07:52:29.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:52:29.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:52:29.81$vc4f8/valo=8,852.99 2006.210.07:52:29.81#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.07:52:29.81#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.07:52:29.81#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:29.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:52:29.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:52:29.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:52:29.81#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:52:29.81#ibcon#first serial, iclass 30, count 0 2006.210.07:52:29.81#ibcon#enter sib2, iclass 30, count 0 2006.210.07:52:29.81#ibcon#flushed, iclass 30, count 0 2006.210.07:52:29.81#ibcon#about to write, iclass 30, count 0 2006.210.07:52:29.81#ibcon#wrote, iclass 30, count 0 2006.210.07:52:29.81#ibcon#about to read 3, iclass 30, count 0 2006.210.07:52:29.83#ibcon#read 3, iclass 30, count 0 2006.210.07:52:29.83#ibcon#about to read 4, iclass 30, count 0 2006.210.07:52:29.83#ibcon#read 4, iclass 30, count 0 2006.210.07:52:29.83#ibcon#about to read 5, iclass 30, count 0 2006.210.07:52:29.83#ibcon#read 5, iclass 30, count 0 2006.210.07:52:29.83#ibcon#about to read 6, iclass 30, count 0 2006.210.07:52:29.83#ibcon#read 6, iclass 30, count 0 2006.210.07:52:29.83#ibcon#end of sib2, iclass 30, count 0 2006.210.07:52:29.83#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:52:29.83#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:52:29.83#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:52:29.83#ibcon#*before write, iclass 30, count 0 2006.210.07:52:29.83#ibcon#enter sib2, iclass 30, count 0 2006.210.07:52:29.83#ibcon#flushed, iclass 30, count 0 2006.210.07:52:29.83#ibcon#about to write, iclass 30, count 0 2006.210.07:52:29.83#ibcon#wrote, iclass 30, count 0 2006.210.07:52:29.83#ibcon#about to read 3, iclass 30, count 0 2006.210.07:52:29.87#ibcon#read 3, iclass 30, count 0 2006.210.07:52:29.87#ibcon#about to read 4, iclass 30, count 0 2006.210.07:52:29.87#ibcon#read 4, iclass 30, count 0 2006.210.07:52:29.87#ibcon#about to read 5, iclass 30, count 0 2006.210.07:52:29.87#ibcon#read 5, iclass 30, count 0 2006.210.07:52:29.87#ibcon#about to read 6, iclass 30, count 0 2006.210.07:52:29.87#ibcon#read 6, iclass 30, count 0 2006.210.07:52:29.87#ibcon#end of sib2, iclass 30, count 0 2006.210.07:52:29.87#ibcon#*after write, iclass 30, count 0 2006.210.07:52:29.87#ibcon#*before return 0, iclass 30, count 0 2006.210.07:52:29.87#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:52:29.87#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:52:29.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:52:29.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:52:29.87$vc4f8/va=8,7 2006.210.07:52:29.87#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.07:52:29.87#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.07:52:29.87#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:29.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:52:29.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:52:29.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:52:29.93#ibcon#enter wrdev, iclass 32, count 2 2006.210.07:52:29.93#ibcon#first serial, iclass 32, count 2 2006.210.07:52:29.93#ibcon#enter sib2, iclass 32, count 2 2006.210.07:52:29.93#ibcon#flushed, iclass 32, count 2 2006.210.07:52:29.93#ibcon#about to write, iclass 32, count 2 2006.210.07:52:29.93#ibcon#wrote, iclass 32, count 2 2006.210.07:52:29.93#ibcon#about to read 3, iclass 32, count 2 2006.210.07:52:29.95#ibcon#read 3, iclass 32, count 2 2006.210.07:52:29.95#ibcon#about to read 4, iclass 32, count 2 2006.210.07:52:29.95#ibcon#read 4, iclass 32, count 2 2006.210.07:52:29.95#ibcon#about to read 5, iclass 32, count 2 2006.210.07:52:29.95#ibcon#read 5, iclass 32, count 2 2006.210.07:52:29.95#ibcon#about to read 6, iclass 32, count 2 2006.210.07:52:29.95#ibcon#read 6, iclass 32, count 2 2006.210.07:52:29.95#ibcon#end of sib2, iclass 32, count 2 2006.210.07:52:29.95#ibcon#*mode == 0, iclass 32, count 2 2006.210.07:52:29.95#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.07:52:29.95#ibcon#[25=AT08-07\r\n] 2006.210.07:52:29.95#ibcon#*before write, iclass 32, count 2 2006.210.07:52:29.95#ibcon#enter sib2, iclass 32, count 2 2006.210.07:52:29.95#ibcon#flushed, iclass 32, count 2 2006.210.07:52:29.95#ibcon#about to write, iclass 32, count 2 2006.210.07:52:29.95#ibcon#wrote, iclass 32, count 2 2006.210.07:52:29.95#ibcon#about to read 3, iclass 32, count 2 2006.210.07:52:29.98#ibcon#read 3, iclass 32, count 2 2006.210.07:52:29.98#ibcon#about to read 4, iclass 32, count 2 2006.210.07:52:29.98#ibcon#read 4, iclass 32, count 2 2006.210.07:52:29.98#ibcon#about to read 5, iclass 32, count 2 2006.210.07:52:29.98#ibcon#read 5, iclass 32, count 2 2006.210.07:52:29.98#ibcon#about to read 6, iclass 32, count 2 2006.210.07:52:29.98#ibcon#read 6, iclass 32, count 2 2006.210.07:52:29.98#ibcon#end of sib2, iclass 32, count 2 2006.210.07:52:29.98#ibcon#*after write, iclass 32, count 2 2006.210.07:52:29.98#ibcon#*before return 0, iclass 32, count 2 2006.210.07:52:29.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:52:29.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.07:52:29.98#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.07:52:29.98#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:29.98#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:52:30.10#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:52:30.10#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:52:30.10#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:52:30.10#ibcon#first serial, iclass 32, count 0 2006.210.07:52:30.10#ibcon#enter sib2, iclass 32, count 0 2006.210.07:52:30.10#ibcon#flushed, iclass 32, count 0 2006.210.07:52:30.10#ibcon#about to write, iclass 32, count 0 2006.210.07:52:30.10#ibcon#wrote, iclass 32, count 0 2006.210.07:52:30.10#ibcon#about to read 3, iclass 32, count 0 2006.210.07:52:30.12#ibcon#read 3, iclass 32, count 0 2006.210.07:52:30.12#ibcon#about to read 4, iclass 32, count 0 2006.210.07:52:30.12#ibcon#read 4, iclass 32, count 0 2006.210.07:52:30.12#ibcon#about to read 5, iclass 32, count 0 2006.210.07:52:30.12#ibcon#read 5, iclass 32, count 0 2006.210.07:52:30.12#ibcon#about to read 6, iclass 32, count 0 2006.210.07:52:30.12#ibcon#read 6, iclass 32, count 0 2006.210.07:52:30.12#ibcon#end of sib2, iclass 32, count 0 2006.210.07:52:30.12#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:52:30.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:52:30.12#ibcon#[25=USB\r\n] 2006.210.07:52:30.12#ibcon#*before write, iclass 32, count 0 2006.210.07:52:30.12#ibcon#enter sib2, iclass 32, count 0 2006.210.07:52:30.12#ibcon#flushed, iclass 32, count 0 2006.210.07:52:30.12#ibcon#about to write, iclass 32, count 0 2006.210.07:52:30.12#ibcon#wrote, iclass 32, count 0 2006.210.07:52:30.12#ibcon#about to read 3, iclass 32, count 0 2006.210.07:52:30.15#ibcon#read 3, iclass 32, count 0 2006.210.07:52:30.15#ibcon#about to read 4, iclass 32, count 0 2006.210.07:52:30.15#ibcon#read 4, iclass 32, count 0 2006.210.07:52:30.15#ibcon#about to read 5, iclass 32, count 0 2006.210.07:52:30.15#ibcon#read 5, iclass 32, count 0 2006.210.07:52:30.15#ibcon#about to read 6, iclass 32, count 0 2006.210.07:52:30.15#ibcon#read 6, iclass 32, count 0 2006.210.07:52:30.15#ibcon#end of sib2, iclass 32, count 0 2006.210.07:52:30.15#ibcon#*after write, iclass 32, count 0 2006.210.07:52:30.15#ibcon#*before return 0, iclass 32, count 0 2006.210.07:52:30.15#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:52:30.15#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.07:52:30.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:52:30.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:52:30.15$vc4f8/vblo=1,632.99 2006.210.07:52:30.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.07:52:30.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.07:52:30.15#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:30.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:30.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:30.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:30.15#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:52:30.15#ibcon#first serial, iclass 34, count 0 2006.210.07:52:30.15#ibcon#enter sib2, iclass 34, count 0 2006.210.07:52:30.15#ibcon#flushed, iclass 34, count 0 2006.210.07:52:30.15#ibcon#about to write, iclass 34, count 0 2006.210.07:52:30.15#ibcon#wrote, iclass 34, count 0 2006.210.07:52:30.15#ibcon#about to read 3, iclass 34, count 0 2006.210.07:52:30.17#ibcon#read 3, iclass 34, count 0 2006.210.07:52:30.17#ibcon#about to read 4, iclass 34, count 0 2006.210.07:52:30.17#ibcon#read 4, iclass 34, count 0 2006.210.07:52:30.17#ibcon#about to read 5, iclass 34, count 0 2006.210.07:52:30.17#ibcon#read 5, iclass 34, count 0 2006.210.07:52:30.17#ibcon#about to read 6, iclass 34, count 0 2006.210.07:52:30.17#ibcon#read 6, iclass 34, count 0 2006.210.07:52:30.17#ibcon#end of sib2, iclass 34, count 0 2006.210.07:52:30.17#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:52:30.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:52:30.17#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:52:30.17#ibcon#*before write, iclass 34, count 0 2006.210.07:52:30.17#ibcon#enter sib2, iclass 34, count 0 2006.210.07:52:30.17#ibcon#flushed, iclass 34, count 0 2006.210.07:52:30.17#ibcon#about to write, iclass 34, count 0 2006.210.07:52:30.17#ibcon#wrote, iclass 34, count 0 2006.210.07:52:30.17#ibcon#about to read 3, iclass 34, count 0 2006.210.07:52:30.21#ibcon#read 3, iclass 34, count 0 2006.210.07:52:30.21#ibcon#about to read 4, iclass 34, count 0 2006.210.07:52:30.21#ibcon#read 4, iclass 34, count 0 2006.210.07:52:30.21#ibcon#about to read 5, iclass 34, count 0 2006.210.07:52:30.21#ibcon#read 5, iclass 34, count 0 2006.210.07:52:30.21#ibcon#about to read 6, iclass 34, count 0 2006.210.07:52:30.21#ibcon#read 6, iclass 34, count 0 2006.210.07:52:30.21#ibcon#end of sib2, iclass 34, count 0 2006.210.07:52:30.21#ibcon#*after write, iclass 34, count 0 2006.210.07:52:30.21#ibcon#*before return 0, iclass 34, count 0 2006.210.07:52:30.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:30.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.07:52:30.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:52:30.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:52:30.21$vc4f8/vb=1,4 2006.210.07:52:30.21#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.07:52:30.21#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.07:52:30.21#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:30.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:30.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:30.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:30.21#ibcon#enter wrdev, iclass 36, count 2 2006.210.07:52:30.21#ibcon#first serial, iclass 36, count 2 2006.210.07:52:30.21#ibcon#enter sib2, iclass 36, count 2 2006.210.07:52:30.21#ibcon#flushed, iclass 36, count 2 2006.210.07:52:30.21#ibcon#about to write, iclass 36, count 2 2006.210.07:52:30.21#ibcon#wrote, iclass 36, count 2 2006.210.07:52:30.21#ibcon#about to read 3, iclass 36, count 2 2006.210.07:52:30.23#ibcon#read 3, iclass 36, count 2 2006.210.07:52:30.23#ibcon#about to read 4, iclass 36, count 2 2006.210.07:52:30.23#ibcon#read 4, iclass 36, count 2 2006.210.07:52:30.23#ibcon#about to read 5, iclass 36, count 2 2006.210.07:52:30.23#ibcon#read 5, iclass 36, count 2 2006.210.07:52:30.23#ibcon#about to read 6, iclass 36, count 2 2006.210.07:52:30.23#ibcon#read 6, iclass 36, count 2 2006.210.07:52:30.23#ibcon#end of sib2, iclass 36, count 2 2006.210.07:52:30.23#ibcon#*mode == 0, iclass 36, count 2 2006.210.07:52:30.23#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.07:52:30.23#ibcon#[27=AT01-04\r\n] 2006.210.07:52:30.23#ibcon#*before write, iclass 36, count 2 2006.210.07:52:30.23#ibcon#enter sib2, iclass 36, count 2 2006.210.07:52:30.23#ibcon#flushed, iclass 36, count 2 2006.210.07:52:30.23#ibcon#about to write, iclass 36, count 2 2006.210.07:52:30.23#ibcon#wrote, iclass 36, count 2 2006.210.07:52:30.23#ibcon#about to read 3, iclass 36, count 2 2006.210.07:52:30.26#ibcon#read 3, iclass 36, count 2 2006.210.07:52:30.26#ibcon#about to read 4, iclass 36, count 2 2006.210.07:52:30.26#ibcon#read 4, iclass 36, count 2 2006.210.07:52:30.26#ibcon#about to read 5, iclass 36, count 2 2006.210.07:52:30.26#ibcon#read 5, iclass 36, count 2 2006.210.07:52:30.26#ibcon#about to read 6, iclass 36, count 2 2006.210.07:52:30.26#ibcon#read 6, iclass 36, count 2 2006.210.07:52:30.26#ibcon#end of sib2, iclass 36, count 2 2006.210.07:52:30.26#ibcon#*after write, iclass 36, count 2 2006.210.07:52:30.26#ibcon#*before return 0, iclass 36, count 2 2006.210.07:52:30.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:30.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.07:52:30.26#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.07:52:30.26#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:30.26#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:30.38#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:30.38#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:30.38#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:52:30.38#ibcon#first serial, iclass 36, count 0 2006.210.07:52:30.38#ibcon#enter sib2, iclass 36, count 0 2006.210.07:52:30.38#ibcon#flushed, iclass 36, count 0 2006.210.07:52:30.38#ibcon#about to write, iclass 36, count 0 2006.210.07:52:30.38#ibcon#wrote, iclass 36, count 0 2006.210.07:52:30.38#ibcon#about to read 3, iclass 36, count 0 2006.210.07:52:30.40#ibcon#read 3, iclass 36, count 0 2006.210.07:52:30.40#ibcon#about to read 4, iclass 36, count 0 2006.210.07:52:30.40#ibcon#read 4, iclass 36, count 0 2006.210.07:52:30.40#ibcon#about to read 5, iclass 36, count 0 2006.210.07:52:30.40#ibcon#read 5, iclass 36, count 0 2006.210.07:52:30.40#ibcon#about to read 6, iclass 36, count 0 2006.210.07:52:30.40#ibcon#read 6, iclass 36, count 0 2006.210.07:52:30.40#ibcon#end of sib2, iclass 36, count 0 2006.210.07:52:30.40#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:52:30.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:52:30.40#ibcon#[27=USB\r\n] 2006.210.07:52:30.40#ibcon#*before write, iclass 36, count 0 2006.210.07:52:30.40#ibcon#enter sib2, iclass 36, count 0 2006.210.07:52:30.40#ibcon#flushed, iclass 36, count 0 2006.210.07:52:30.40#ibcon#about to write, iclass 36, count 0 2006.210.07:52:30.40#ibcon#wrote, iclass 36, count 0 2006.210.07:52:30.40#ibcon#about to read 3, iclass 36, count 0 2006.210.07:52:30.43#ibcon#read 3, iclass 36, count 0 2006.210.07:52:30.43#ibcon#about to read 4, iclass 36, count 0 2006.210.07:52:30.43#ibcon#read 4, iclass 36, count 0 2006.210.07:52:30.43#ibcon#about to read 5, iclass 36, count 0 2006.210.07:52:30.43#ibcon#read 5, iclass 36, count 0 2006.210.07:52:30.43#ibcon#about to read 6, iclass 36, count 0 2006.210.07:52:30.43#ibcon#read 6, iclass 36, count 0 2006.210.07:52:30.43#ibcon#end of sib2, iclass 36, count 0 2006.210.07:52:30.43#ibcon#*after write, iclass 36, count 0 2006.210.07:52:30.43#ibcon#*before return 0, iclass 36, count 0 2006.210.07:52:30.43#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:30.43#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.07:52:30.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:52:30.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:52:30.43$vc4f8/vblo=2,640.99 2006.210.07:52:30.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.07:52:30.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.07:52:30.43#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:30.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:30.43#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:30.43#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:30.43#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:52:30.43#ibcon#first serial, iclass 38, count 0 2006.210.07:52:30.43#ibcon#enter sib2, iclass 38, count 0 2006.210.07:52:30.43#ibcon#flushed, iclass 38, count 0 2006.210.07:52:30.43#ibcon#about to write, iclass 38, count 0 2006.210.07:52:30.43#ibcon#wrote, iclass 38, count 0 2006.210.07:52:30.43#ibcon#about to read 3, iclass 38, count 0 2006.210.07:52:30.45#ibcon#read 3, iclass 38, count 0 2006.210.07:52:30.45#ibcon#about to read 4, iclass 38, count 0 2006.210.07:52:30.45#ibcon#read 4, iclass 38, count 0 2006.210.07:52:30.45#ibcon#about to read 5, iclass 38, count 0 2006.210.07:52:30.45#ibcon#read 5, iclass 38, count 0 2006.210.07:52:30.45#ibcon#about to read 6, iclass 38, count 0 2006.210.07:52:30.45#ibcon#read 6, iclass 38, count 0 2006.210.07:52:30.45#ibcon#end of sib2, iclass 38, count 0 2006.210.07:52:30.45#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:52:30.45#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:52:30.45#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:52:30.45#ibcon#*before write, iclass 38, count 0 2006.210.07:52:30.45#ibcon#enter sib2, iclass 38, count 0 2006.210.07:52:30.45#ibcon#flushed, iclass 38, count 0 2006.210.07:52:30.45#ibcon#about to write, iclass 38, count 0 2006.210.07:52:30.45#ibcon#wrote, iclass 38, count 0 2006.210.07:52:30.45#ibcon#about to read 3, iclass 38, count 0 2006.210.07:52:30.49#ibcon#read 3, iclass 38, count 0 2006.210.07:52:30.49#ibcon#about to read 4, iclass 38, count 0 2006.210.07:52:30.49#ibcon#read 4, iclass 38, count 0 2006.210.07:52:30.49#ibcon#about to read 5, iclass 38, count 0 2006.210.07:52:30.49#ibcon#read 5, iclass 38, count 0 2006.210.07:52:30.49#ibcon#about to read 6, iclass 38, count 0 2006.210.07:52:30.49#ibcon#read 6, iclass 38, count 0 2006.210.07:52:30.49#ibcon#end of sib2, iclass 38, count 0 2006.210.07:52:30.49#ibcon#*after write, iclass 38, count 0 2006.210.07:52:30.49#ibcon#*before return 0, iclass 38, count 0 2006.210.07:52:30.49#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:30.49#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.07:52:30.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:52:30.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:52:30.49$vc4f8/vb=2,4 2006.210.07:52:30.49#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.07:52:30.49#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.07:52:30.49#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:30.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:30.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:30.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:30.55#ibcon#enter wrdev, iclass 40, count 2 2006.210.07:52:30.55#ibcon#first serial, iclass 40, count 2 2006.210.07:52:30.55#ibcon#enter sib2, iclass 40, count 2 2006.210.07:52:30.55#ibcon#flushed, iclass 40, count 2 2006.210.07:52:30.55#ibcon#about to write, iclass 40, count 2 2006.210.07:52:30.55#ibcon#wrote, iclass 40, count 2 2006.210.07:52:30.55#ibcon#about to read 3, iclass 40, count 2 2006.210.07:52:30.57#ibcon#read 3, iclass 40, count 2 2006.210.07:52:30.57#ibcon#about to read 4, iclass 40, count 2 2006.210.07:52:30.57#ibcon#read 4, iclass 40, count 2 2006.210.07:52:30.57#ibcon#about to read 5, iclass 40, count 2 2006.210.07:52:30.57#ibcon#read 5, iclass 40, count 2 2006.210.07:52:30.57#ibcon#about to read 6, iclass 40, count 2 2006.210.07:52:30.57#ibcon#read 6, iclass 40, count 2 2006.210.07:52:30.57#ibcon#end of sib2, iclass 40, count 2 2006.210.07:52:30.57#ibcon#*mode == 0, iclass 40, count 2 2006.210.07:52:30.57#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.07:52:30.57#ibcon#[27=AT02-04\r\n] 2006.210.07:52:30.57#ibcon#*before write, iclass 40, count 2 2006.210.07:52:30.57#ibcon#enter sib2, iclass 40, count 2 2006.210.07:52:30.57#ibcon#flushed, iclass 40, count 2 2006.210.07:52:30.57#ibcon#about to write, iclass 40, count 2 2006.210.07:52:30.57#ibcon#wrote, iclass 40, count 2 2006.210.07:52:30.57#ibcon#about to read 3, iclass 40, count 2 2006.210.07:52:30.60#ibcon#read 3, iclass 40, count 2 2006.210.07:52:30.60#ibcon#about to read 4, iclass 40, count 2 2006.210.07:52:30.60#ibcon#read 4, iclass 40, count 2 2006.210.07:52:30.60#ibcon#about to read 5, iclass 40, count 2 2006.210.07:52:30.60#ibcon#read 5, iclass 40, count 2 2006.210.07:52:30.60#ibcon#about to read 6, iclass 40, count 2 2006.210.07:52:30.60#ibcon#read 6, iclass 40, count 2 2006.210.07:52:30.60#ibcon#end of sib2, iclass 40, count 2 2006.210.07:52:30.60#ibcon#*after write, iclass 40, count 2 2006.210.07:52:30.60#ibcon#*before return 0, iclass 40, count 2 2006.210.07:52:30.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:30.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.07:52:30.60#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.07:52:30.60#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:30.60#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:30.72#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:30.72#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:30.72#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:52:30.72#ibcon#first serial, iclass 40, count 0 2006.210.07:52:30.72#ibcon#enter sib2, iclass 40, count 0 2006.210.07:52:30.72#ibcon#flushed, iclass 40, count 0 2006.210.07:52:30.72#ibcon#about to write, iclass 40, count 0 2006.210.07:52:30.72#ibcon#wrote, iclass 40, count 0 2006.210.07:52:30.72#ibcon#about to read 3, iclass 40, count 0 2006.210.07:52:30.74#ibcon#read 3, iclass 40, count 0 2006.210.07:52:30.74#ibcon#about to read 4, iclass 40, count 0 2006.210.07:52:30.74#ibcon#read 4, iclass 40, count 0 2006.210.07:52:30.74#ibcon#about to read 5, iclass 40, count 0 2006.210.07:52:30.74#ibcon#read 5, iclass 40, count 0 2006.210.07:52:30.74#ibcon#about to read 6, iclass 40, count 0 2006.210.07:52:30.74#ibcon#read 6, iclass 40, count 0 2006.210.07:52:30.74#ibcon#end of sib2, iclass 40, count 0 2006.210.07:52:30.74#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:52:30.74#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:52:30.74#ibcon#[27=USB\r\n] 2006.210.07:52:30.74#ibcon#*before write, iclass 40, count 0 2006.210.07:52:30.74#ibcon#enter sib2, iclass 40, count 0 2006.210.07:52:30.74#ibcon#flushed, iclass 40, count 0 2006.210.07:52:30.74#ibcon#about to write, iclass 40, count 0 2006.210.07:52:30.74#ibcon#wrote, iclass 40, count 0 2006.210.07:52:30.74#ibcon#about to read 3, iclass 40, count 0 2006.210.07:52:30.77#ibcon#read 3, iclass 40, count 0 2006.210.07:52:30.77#ibcon#about to read 4, iclass 40, count 0 2006.210.07:52:30.77#ibcon#read 4, iclass 40, count 0 2006.210.07:52:30.77#ibcon#about to read 5, iclass 40, count 0 2006.210.07:52:30.77#ibcon#read 5, iclass 40, count 0 2006.210.07:52:30.77#ibcon#about to read 6, iclass 40, count 0 2006.210.07:52:30.77#ibcon#read 6, iclass 40, count 0 2006.210.07:52:30.77#ibcon#end of sib2, iclass 40, count 0 2006.210.07:52:30.77#ibcon#*after write, iclass 40, count 0 2006.210.07:52:30.77#ibcon#*before return 0, iclass 40, count 0 2006.210.07:52:30.77#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:30.77#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.07:52:30.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:52:30.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:52:30.77$vc4f8/vblo=3,656.99 2006.210.07:52:30.77#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.07:52:30.77#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.07:52:30.77#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:30.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:52:30.77#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:52:30.77#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:52:30.77#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:52:30.77#ibcon#first serial, iclass 4, count 0 2006.210.07:52:30.77#ibcon#enter sib2, iclass 4, count 0 2006.210.07:52:30.77#ibcon#flushed, iclass 4, count 0 2006.210.07:52:30.77#ibcon#about to write, iclass 4, count 0 2006.210.07:52:30.77#ibcon#wrote, iclass 4, count 0 2006.210.07:52:30.77#ibcon#about to read 3, iclass 4, count 0 2006.210.07:52:30.79#ibcon#read 3, iclass 4, count 0 2006.210.07:52:30.79#ibcon#about to read 4, iclass 4, count 0 2006.210.07:52:30.79#ibcon#read 4, iclass 4, count 0 2006.210.07:52:30.79#ibcon#about to read 5, iclass 4, count 0 2006.210.07:52:30.79#ibcon#read 5, iclass 4, count 0 2006.210.07:52:30.79#ibcon#about to read 6, iclass 4, count 0 2006.210.07:52:30.79#ibcon#read 6, iclass 4, count 0 2006.210.07:52:30.79#ibcon#end of sib2, iclass 4, count 0 2006.210.07:52:30.79#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:52:30.79#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:52:30.79#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:52:30.79#ibcon#*before write, iclass 4, count 0 2006.210.07:52:30.79#ibcon#enter sib2, iclass 4, count 0 2006.210.07:52:30.79#ibcon#flushed, iclass 4, count 0 2006.210.07:52:30.79#ibcon#about to write, iclass 4, count 0 2006.210.07:52:30.79#ibcon#wrote, iclass 4, count 0 2006.210.07:52:30.79#ibcon#about to read 3, iclass 4, count 0 2006.210.07:52:30.83#ibcon#read 3, iclass 4, count 0 2006.210.07:52:30.83#ibcon#about to read 4, iclass 4, count 0 2006.210.07:52:30.83#ibcon#read 4, iclass 4, count 0 2006.210.07:52:30.83#ibcon#about to read 5, iclass 4, count 0 2006.210.07:52:30.83#ibcon#read 5, iclass 4, count 0 2006.210.07:52:30.83#ibcon#about to read 6, iclass 4, count 0 2006.210.07:52:30.83#ibcon#read 6, iclass 4, count 0 2006.210.07:52:30.83#ibcon#end of sib2, iclass 4, count 0 2006.210.07:52:30.83#ibcon#*after write, iclass 4, count 0 2006.210.07:52:30.83#ibcon#*before return 0, iclass 4, count 0 2006.210.07:52:30.83#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:52:30.83#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.07:52:30.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:52:30.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:52:30.83$vc4f8/vb=3,3 2006.210.07:52:30.83#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.07:52:30.83#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.07:52:30.83#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:30.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:52:30.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:52:30.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:52:30.89#ibcon#enter wrdev, iclass 6, count 2 2006.210.07:52:30.89#ibcon#first serial, iclass 6, count 2 2006.210.07:52:30.89#ibcon#enter sib2, iclass 6, count 2 2006.210.07:52:30.89#ibcon#flushed, iclass 6, count 2 2006.210.07:52:30.89#ibcon#about to write, iclass 6, count 2 2006.210.07:52:30.89#ibcon#wrote, iclass 6, count 2 2006.210.07:52:30.89#ibcon#about to read 3, iclass 6, count 2 2006.210.07:52:30.91#ibcon#read 3, iclass 6, count 2 2006.210.07:52:30.91#ibcon#about to read 4, iclass 6, count 2 2006.210.07:52:30.91#ibcon#read 4, iclass 6, count 2 2006.210.07:52:30.91#ibcon#about to read 5, iclass 6, count 2 2006.210.07:52:30.91#ibcon#read 5, iclass 6, count 2 2006.210.07:52:30.91#ibcon#about to read 6, iclass 6, count 2 2006.210.07:52:30.91#ibcon#read 6, iclass 6, count 2 2006.210.07:52:30.91#ibcon#end of sib2, iclass 6, count 2 2006.210.07:52:30.91#ibcon#*mode == 0, iclass 6, count 2 2006.210.07:52:30.91#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.07:52:30.91#ibcon#[27=AT03-03\r\n] 2006.210.07:52:30.91#ibcon#*before write, iclass 6, count 2 2006.210.07:52:30.91#ibcon#enter sib2, iclass 6, count 2 2006.210.07:52:30.91#ibcon#flushed, iclass 6, count 2 2006.210.07:52:30.91#ibcon#about to write, iclass 6, count 2 2006.210.07:52:30.91#ibcon#wrote, iclass 6, count 2 2006.210.07:52:30.91#ibcon#about to read 3, iclass 6, count 2 2006.210.07:52:30.94#ibcon#read 3, iclass 6, count 2 2006.210.07:52:30.94#ibcon#about to read 4, iclass 6, count 2 2006.210.07:52:30.94#ibcon#read 4, iclass 6, count 2 2006.210.07:52:30.94#ibcon#about to read 5, iclass 6, count 2 2006.210.07:52:30.94#ibcon#read 5, iclass 6, count 2 2006.210.07:52:30.94#ibcon#about to read 6, iclass 6, count 2 2006.210.07:52:30.94#ibcon#read 6, iclass 6, count 2 2006.210.07:52:30.94#ibcon#end of sib2, iclass 6, count 2 2006.210.07:52:30.94#ibcon#*after write, iclass 6, count 2 2006.210.07:52:30.94#ibcon#*before return 0, iclass 6, count 2 2006.210.07:52:30.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:52:30.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.07:52:30.94#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.07:52:30.94#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:30.94#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:52:31.06#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:52:31.06#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:52:31.06#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:52:31.06#ibcon#first serial, iclass 6, count 0 2006.210.07:52:31.06#ibcon#enter sib2, iclass 6, count 0 2006.210.07:52:31.06#ibcon#flushed, iclass 6, count 0 2006.210.07:52:31.06#ibcon#about to write, iclass 6, count 0 2006.210.07:52:31.06#ibcon#wrote, iclass 6, count 0 2006.210.07:52:31.06#ibcon#about to read 3, iclass 6, count 0 2006.210.07:52:31.08#ibcon#read 3, iclass 6, count 0 2006.210.07:52:31.08#ibcon#about to read 4, iclass 6, count 0 2006.210.07:52:31.08#ibcon#read 4, iclass 6, count 0 2006.210.07:52:31.08#ibcon#about to read 5, iclass 6, count 0 2006.210.07:52:31.08#ibcon#read 5, iclass 6, count 0 2006.210.07:52:31.08#ibcon#about to read 6, iclass 6, count 0 2006.210.07:52:31.08#ibcon#read 6, iclass 6, count 0 2006.210.07:52:31.08#ibcon#end of sib2, iclass 6, count 0 2006.210.07:52:31.08#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:52:31.08#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:52:31.08#ibcon#[27=USB\r\n] 2006.210.07:52:31.08#ibcon#*before write, iclass 6, count 0 2006.210.07:52:31.08#ibcon#enter sib2, iclass 6, count 0 2006.210.07:52:31.08#ibcon#flushed, iclass 6, count 0 2006.210.07:52:31.08#ibcon#about to write, iclass 6, count 0 2006.210.07:52:31.08#ibcon#wrote, iclass 6, count 0 2006.210.07:52:31.08#ibcon#about to read 3, iclass 6, count 0 2006.210.07:52:31.11#ibcon#read 3, iclass 6, count 0 2006.210.07:52:31.11#ibcon#about to read 4, iclass 6, count 0 2006.210.07:52:31.11#ibcon#read 4, iclass 6, count 0 2006.210.07:52:31.11#ibcon#about to read 5, iclass 6, count 0 2006.210.07:52:31.11#ibcon#read 5, iclass 6, count 0 2006.210.07:52:31.11#ibcon#about to read 6, iclass 6, count 0 2006.210.07:52:31.11#ibcon#read 6, iclass 6, count 0 2006.210.07:52:31.11#ibcon#end of sib2, iclass 6, count 0 2006.210.07:52:31.11#ibcon#*after write, iclass 6, count 0 2006.210.07:52:31.11#ibcon#*before return 0, iclass 6, count 0 2006.210.07:52:31.11#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:52:31.11#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.07:52:31.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:52:31.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:52:31.11$vc4f8/vblo=4,712.99 2006.210.07:52:31.11#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.07:52:31.11#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.07:52:31.11#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:31.11#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:31.11#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:31.11#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:31.11#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:52:31.11#ibcon#first serial, iclass 10, count 0 2006.210.07:52:31.11#ibcon#enter sib2, iclass 10, count 0 2006.210.07:52:31.11#ibcon#flushed, iclass 10, count 0 2006.210.07:52:31.11#ibcon#about to write, iclass 10, count 0 2006.210.07:52:31.11#ibcon#wrote, iclass 10, count 0 2006.210.07:52:31.11#ibcon#about to read 3, iclass 10, count 0 2006.210.07:52:31.13#ibcon#read 3, iclass 10, count 0 2006.210.07:52:31.13#ibcon#about to read 4, iclass 10, count 0 2006.210.07:52:31.13#ibcon#read 4, iclass 10, count 0 2006.210.07:52:31.13#ibcon#about to read 5, iclass 10, count 0 2006.210.07:52:31.13#ibcon#read 5, iclass 10, count 0 2006.210.07:52:31.13#ibcon#about to read 6, iclass 10, count 0 2006.210.07:52:31.13#ibcon#read 6, iclass 10, count 0 2006.210.07:52:31.13#ibcon#end of sib2, iclass 10, count 0 2006.210.07:52:31.13#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:52:31.13#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:52:31.13#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:52:31.13#ibcon#*before write, iclass 10, count 0 2006.210.07:52:31.13#ibcon#enter sib2, iclass 10, count 0 2006.210.07:52:31.13#ibcon#flushed, iclass 10, count 0 2006.210.07:52:31.13#ibcon#about to write, iclass 10, count 0 2006.210.07:52:31.13#ibcon#wrote, iclass 10, count 0 2006.210.07:52:31.13#ibcon#about to read 3, iclass 10, count 0 2006.210.07:52:31.17#ibcon#read 3, iclass 10, count 0 2006.210.07:52:31.17#ibcon#about to read 4, iclass 10, count 0 2006.210.07:52:31.17#ibcon#read 4, iclass 10, count 0 2006.210.07:52:31.17#ibcon#about to read 5, iclass 10, count 0 2006.210.07:52:31.17#ibcon#read 5, iclass 10, count 0 2006.210.07:52:31.17#ibcon#about to read 6, iclass 10, count 0 2006.210.07:52:31.17#ibcon#read 6, iclass 10, count 0 2006.210.07:52:31.17#ibcon#end of sib2, iclass 10, count 0 2006.210.07:52:31.17#ibcon#*after write, iclass 10, count 0 2006.210.07:52:31.17#ibcon#*before return 0, iclass 10, count 0 2006.210.07:52:31.17#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:31.17#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.07:52:31.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:52:31.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:52:31.17$vc4f8/vb=4,3 2006.210.07:52:31.17#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.07:52:31.17#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.07:52:31.17#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:31.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:31.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:31.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:31.23#ibcon#enter wrdev, iclass 12, count 2 2006.210.07:52:31.23#ibcon#first serial, iclass 12, count 2 2006.210.07:52:31.23#ibcon#enter sib2, iclass 12, count 2 2006.210.07:52:31.23#ibcon#flushed, iclass 12, count 2 2006.210.07:52:31.23#ibcon#about to write, iclass 12, count 2 2006.210.07:52:31.23#ibcon#wrote, iclass 12, count 2 2006.210.07:52:31.23#ibcon#about to read 3, iclass 12, count 2 2006.210.07:52:31.25#ibcon#read 3, iclass 12, count 2 2006.210.07:52:31.25#ibcon#about to read 4, iclass 12, count 2 2006.210.07:52:31.25#ibcon#read 4, iclass 12, count 2 2006.210.07:52:31.25#ibcon#about to read 5, iclass 12, count 2 2006.210.07:52:31.25#ibcon#read 5, iclass 12, count 2 2006.210.07:52:31.25#ibcon#about to read 6, iclass 12, count 2 2006.210.07:52:31.25#ibcon#read 6, iclass 12, count 2 2006.210.07:52:31.25#ibcon#end of sib2, iclass 12, count 2 2006.210.07:52:31.25#ibcon#*mode == 0, iclass 12, count 2 2006.210.07:52:31.25#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.07:52:31.25#ibcon#[27=AT04-03\r\n] 2006.210.07:52:31.25#ibcon#*before write, iclass 12, count 2 2006.210.07:52:31.25#ibcon#enter sib2, iclass 12, count 2 2006.210.07:52:31.25#ibcon#flushed, iclass 12, count 2 2006.210.07:52:31.25#ibcon#about to write, iclass 12, count 2 2006.210.07:52:31.25#ibcon#wrote, iclass 12, count 2 2006.210.07:52:31.25#ibcon#about to read 3, iclass 12, count 2 2006.210.07:52:31.28#ibcon#read 3, iclass 12, count 2 2006.210.07:52:31.28#ibcon#about to read 4, iclass 12, count 2 2006.210.07:52:31.28#ibcon#read 4, iclass 12, count 2 2006.210.07:52:31.28#ibcon#about to read 5, iclass 12, count 2 2006.210.07:52:31.28#ibcon#read 5, iclass 12, count 2 2006.210.07:52:31.28#ibcon#about to read 6, iclass 12, count 2 2006.210.07:52:31.28#ibcon#read 6, iclass 12, count 2 2006.210.07:52:31.28#ibcon#end of sib2, iclass 12, count 2 2006.210.07:52:31.28#ibcon#*after write, iclass 12, count 2 2006.210.07:52:31.28#ibcon#*before return 0, iclass 12, count 2 2006.210.07:52:31.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:31.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.07:52:31.28#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.07:52:31.28#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:31.28#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:31.40#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:31.40#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:31.40#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:52:31.40#ibcon#first serial, iclass 12, count 0 2006.210.07:52:31.40#ibcon#enter sib2, iclass 12, count 0 2006.210.07:52:31.40#ibcon#flushed, iclass 12, count 0 2006.210.07:52:31.40#ibcon#about to write, iclass 12, count 0 2006.210.07:52:31.40#ibcon#wrote, iclass 12, count 0 2006.210.07:52:31.40#ibcon#about to read 3, iclass 12, count 0 2006.210.07:52:31.42#ibcon#read 3, iclass 12, count 0 2006.210.07:52:31.42#ibcon#about to read 4, iclass 12, count 0 2006.210.07:52:31.42#ibcon#read 4, iclass 12, count 0 2006.210.07:52:31.42#ibcon#about to read 5, iclass 12, count 0 2006.210.07:52:31.42#ibcon#read 5, iclass 12, count 0 2006.210.07:52:31.42#ibcon#about to read 6, iclass 12, count 0 2006.210.07:52:31.42#ibcon#read 6, iclass 12, count 0 2006.210.07:52:31.42#ibcon#end of sib2, iclass 12, count 0 2006.210.07:52:31.42#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:52:31.42#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:52:31.42#ibcon#[27=USB\r\n] 2006.210.07:52:31.42#ibcon#*before write, iclass 12, count 0 2006.210.07:52:31.42#ibcon#enter sib2, iclass 12, count 0 2006.210.07:52:31.42#ibcon#flushed, iclass 12, count 0 2006.210.07:52:31.42#ibcon#about to write, iclass 12, count 0 2006.210.07:52:31.42#ibcon#wrote, iclass 12, count 0 2006.210.07:52:31.42#ibcon#about to read 3, iclass 12, count 0 2006.210.07:52:31.45#ibcon#read 3, iclass 12, count 0 2006.210.07:52:31.45#ibcon#about to read 4, iclass 12, count 0 2006.210.07:52:31.45#ibcon#read 4, iclass 12, count 0 2006.210.07:52:31.45#ibcon#about to read 5, iclass 12, count 0 2006.210.07:52:31.45#ibcon#read 5, iclass 12, count 0 2006.210.07:52:31.45#ibcon#about to read 6, iclass 12, count 0 2006.210.07:52:31.45#ibcon#read 6, iclass 12, count 0 2006.210.07:52:31.45#ibcon#end of sib2, iclass 12, count 0 2006.210.07:52:31.45#ibcon#*after write, iclass 12, count 0 2006.210.07:52:31.45#ibcon#*before return 0, iclass 12, count 0 2006.210.07:52:31.45#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:31.45#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.07:52:31.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:52:31.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:52:31.45$vc4f8/vblo=5,744.99 2006.210.07:52:31.45#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.07:52:31.45#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.07:52:31.45#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:31.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:31.45#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:31.45#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:31.45#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:52:31.45#ibcon#first serial, iclass 14, count 0 2006.210.07:52:31.45#ibcon#enter sib2, iclass 14, count 0 2006.210.07:52:31.45#ibcon#flushed, iclass 14, count 0 2006.210.07:52:31.45#ibcon#about to write, iclass 14, count 0 2006.210.07:52:31.45#ibcon#wrote, iclass 14, count 0 2006.210.07:52:31.45#ibcon#about to read 3, iclass 14, count 0 2006.210.07:52:31.47#ibcon#read 3, iclass 14, count 0 2006.210.07:52:31.47#ibcon#about to read 4, iclass 14, count 0 2006.210.07:52:31.47#ibcon#read 4, iclass 14, count 0 2006.210.07:52:31.47#ibcon#about to read 5, iclass 14, count 0 2006.210.07:52:31.47#ibcon#read 5, iclass 14, count 0 2006.210.07:52:31.47#ibcon#about to read 6, iclass 14, count 0 2006.210.07:52:31.47#ibcon#read 6, iclass 14, count 0 2006.210.07:52:31.47#ibcon#end of sib2, iclass 14, count 0 2006.210.07:52:31.47#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:52:31.47#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:52:31.47#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:52:31.47#ibcon#*before write, iclass 14, count 0 2006.210.07:52:31.47#ibcon#enter sib2, iclass 14, count 0 2006.210.07:52:31.47#ibcon#flushed, iclass 14, count 0 2006.210.07:52:31.47#ibcon#about to write, iclass 14, count 0 2006.210.07:52:31.47#ibcon#wrote, iclass 14, count 0 2006.210.07:52:31.47#ibcon#about to read 3, iclass 14, count 0 2006.210.07:52:31.51#ibcon#read 3, iclass 14, count 0 2006.210.07:52:31.51#ibcon#about to read 4, iclass 14, count 0 2006.210.07:52:31.51#ibcon#read 4, iclass 14, count 0 2006.210.07:52:31.51#ibcon#about to read 5, iclass 14, count 0 2006.210.07:52:31.51#ibcon#read 5, iclass 14, count 0 2006.210.07:52:31.51#ibcon#about to read 6, iclass 14, count 0 2006.210.07:52:31.51#ibcon#read 6, iclass 14, count 0 2006.210.07:52:31.51#ibcon#end of sib2, iclass 14, count 0 2006.210.07:52:31.51#ibcon#*after write, iclass 14, count 0 2006.210.07:52:31.51#ibcon#*before return 0, iclass 14, count 0 2006.210.07:52:31.51#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:31.51#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.07:52:31.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:52:31.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:52:31.51$vc4f8/vb=5,3 2006.210.07:52:31.51#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.07:52:31.51#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.07:52:31.51#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:31.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:31.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:31.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:31.57#ibcon#enter wrdev, iclass 16, count 2 2006.210.07:52:31.57#ibcon#first serial, iclass 16, count 2 2006.210.07:52:31.57#ibcon#enter sib2, iclass 16, count 2 2006.210.07:52:31.57#ibcon#flushed, iclass 16, count 2 2006.210.07:52:31.57#ibcon#about to write, iclass 16, count 2 2006.210.07:52:31.57#ibcon#wrote, iclass 16, count 2 2006.210.07:52:31.57#ibcon#about to read 3, iclass 16, count 2 2006.210.07:52:31.59#ibcon#read 3, iclass 16, count 2 2006.210.07:52:31.59#ibcon#about to read 4, iclass 16, count 2 2006.210.07:52:31.59#ibcon#read 4, iclass 16, count 2 2006.210.07:52:31.59#ibcon#about to read 5, iclass 16, count 2 2006.210.07:52:31.59#ibcon#read 5, iclass 16, count 2 2006.210.07:52:31.59#ibcon#about to read 6, iclass 16, count 2 2006.210.07:52:31.59#ibcon#read 6, iclass 16, count 2 2006.210.07:52:31.59#ibcon#end of sib2, iclass 16, count 2 2006.210.07:52:31.59#ibcon#*mode == 0, iclass 16, count 2 2006.210.07:52:31.59#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.07:52:31.59#ibcon#[27=AT05-03\r\n] 2006.210.07:52:31.59#ibcon#*before write, iclass 16, count 2 2006.210.07:52:31.59#ibcon#enter sib2, iclass 16, count 2 2006.210.07:52:31.59#ibcon#flushed, iclass 16, count 2 2006.210.07:52:31.59#ibcon#about to write, iclass 16, count 2 2006.210.07:52:31.59#ibcon#wrote, iclass 16, count 2 2006.210.07:52:31.59#ibcon#about to read 3, iclass 16, count 2 2006.210.07:52:31.62#ibcon#read 3, iclass 16, count 2 2006.210.07:52:31.62#ibcon#about to read 4, iclass 16, count 2 2006.210.07:52:31.62#ibcon#read 4, iclass 16, count 2 2006.210.07:52:31.62#ibcon#about to read 5, iclass 16, count 2 2006.210.07:52:31.62#ibcon#read 5, iclass 16, count 2 2006.210.07:52:31.62#ibcon#about to read 6, iclass 16, count 2 2006.210.07:52:31.62#ibcon#read 6, iclass 16, count 2 2006.210.07:52:31.62#ibcon#end of sib2, iclass 16, count 2 2006.210.07:52:31.62#ibcon#*after write, iclass 16, count 2 2006.210.07:52:31.62#ibcon#*before return 0, iclass 16, count 2 2006.210.07:52:31.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:31.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.07:52:31.62#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.07:52:31.62#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:31.62#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:31.74#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:31.74#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:31.74#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:52:31.74#ibcon#first serial, iclass 16, count 0 2006.210.07:52:31.74#ibcon#enter sib2, iclass 16, count 0 2006.210.07:52:31.74#ibcon#flushed, iclass 16, count 0 2006.210.07:52:31.74#ibcon#about to write, iclass 16, count 0 2006.210.07:52:31.74#ibcon#wrote, iclass 16, count 0 2006.210.07:52:31.74#ibcon#about to read 3, iclass 16, count 0 2006.210.07:52:31.76#ibcon#read 3, iclass 16, count 0 2006.210.07:52:31.76#ibcon#about to read 4, iclass 16, count 0 2006.210.07:52:31.76#ibcon#read 4, iclass 16, count 0 2006.210.07:52:31.76#ibcon#about to read 5, iclass 16, count 0 2006.210.07:52:31.76#ibcon#read 5, iclass 16, count 0 2006.210.07:52:31.76#ibcon#about to read 6, iclass 16, count 0 2006.210.07:52:31.76#ibcon#read 6, iclass 16, count 0 2006.210.07:52:31.76#ibcon#end of sib2, iclass 16, count 0 2006.210.07:52:31.76#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:52:31.76#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:52:31.76#ibcon#[27=USB\r\n] 2006.210.07:52:31.76#ibcon#*before write, iclass 16, count 0 2006.210.07:52:31.76#ibcon#enter sib2, iclass 16, count 0 2006.210.07:52:31.76#ibcon#flushed, iclass 16, count 0 2006.210.07:52:31.76#ibcon#about to write, iclass 16, count 0 2006.210.07:52:31.76#ibcon#wrote, iclass 16, count 0 2006.210.07:52:31.76#ibcon#about to read 3, iclass 16, count 0 2006.210.07:52:31.79#ibcon#read 3, iclass 16, count 0 2006.210.07:52:31.79#ibcon#about to read 4, iclass 16, count 0 2006.210.07:52:31.79#ibcon#read 4, iclass 16, count 0 2006.210.07:52:31.79#ibcon#about to read 5, iclass 16, count 0 2006.210.07:52:31.79#ibcon#read 5, iclass 16, count 0 2006.210.07:52:31.79#ibcon#about to read 6, iclass 16, count 0 2006.210.07:52:31.79#ibcon#read 6, iclass 16, count 0 2006.210.07:52:31.79#ibcon#end of sib2, iclass 16, count 0 2006.210.07:52:31.79#ibcon#*after write, iclass 16, count 0 2006.210.07:52:31.79#ibcon#*before return 0, iclass 16, count 0 2006.210.07:52:31.79#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:31.79#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.07:52:31.79#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:52:31.79#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:52:31.79$vc4f8/vblo=6,752.99 2006.210.07:52:31.79#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.07:52:31.79#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.07:52:31.79#ibcon#ireg 17 cls_cnt 0 2006.210.07:52:31.79#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:31.79#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:31.79#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:31.79#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:52:31.79#ibcon#first serial, iclass 18, count 0 2006.210.07:52:31.79#ibcon#enter sib2, iclass 18, count 0 2006.210.07:52:31.79#ibcon#flushed, iclass 18, count 0 2006.210.07:52:31.79#ibcon#about to write, iclass 18, count 0 2006.210.07:52:31.79#ibcon#wrote, iclass 18, count 0 2006.210.07:52:31.79#ibcon#about to read 3, iclass 18, count 0 2006.210.07:52:31.81#ibcon#read 3, iclass 18, count 0 2006.210.07:52:31.81#ibcon#about to read 4, iclass 18, count 0 2006.210.07:52:31.81#ibcon#read 4, iclass 18, count 0 2006.210.07:52:31.81#ibcon#about to read 5, iclass 18, count 0 2006.210.07:52:31.81#ibcon#read 5, iclass 18, count 0 2006.210.07:52:31.81#ibcon#about to read 6, iclass 18, count 0 2006.210.07:52:31.81#ibcon#read 6, iclass 18, count 0 2006.210.07:52:31.81#ibcon#end of sib2, iclass 18, count 0 2006.210.07:52:31.81#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:52:31.81#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:52:31.81#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:52:31.81#ibcon#*before write, iclass 18, count 0 2006.210.07:52:31.81#ibcon#enter sib2, iclass 18, count 0 2006.210.07:52:31.81#ibcon#flushed, iclass 18, count 0 2006.210.07:52:31.81#ibcon#about to write, iclass 18, count 0 2006.210.07:52:31.81#ibcon#wrote, iclass 18, count 0 2006.210.07:52:31.81#ibcon#about to read 3, iclass 18, count 0 2006.210.07:52:31.85#ibcon#read 3, iclass 18, count 0 2006.210.07:52:31.85#ibcon#about to read 4, iclass 18, count 0 2006.210.07:52:31.85#ibcon#read 4, iclass 18, count 0 2006.210.07:52:31.85#ibcon#about to read 5, iclass 18, count 0 2006.210.07:52:31.85#ibcon#read 5, iclass 18, count 0 2006.210.07:52:31.85#ibcon#about to read 6, iclass 18, count 0 2006.210.07:52:31.85#ibcon#read 6, iclass 18, count 0 2006.210.07:52:31.85#ibcon#end of sib2, iclass 18, count 0 2006.210.07:52:31.85#ibcon#*after write, iclass 18, count 0 2006.210.07:52:31.85#ibcon#*before return 0, iclass 18, count 0 2006.210.07:52:31.85#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:31.85#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.07:52:31.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:52:31.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:52:31.85$vc4f8/vb=6,3 2006.210.07:52:31.85#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.07:52:31.85#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.07:52:31.85#ibcon#ireg 11 cls_cnt 2 2006.210.07:52:31.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:31.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:31.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:31.91#ibcon#enter wrdev, iclass 20, count 2 2006.210.07:52:31.91#ibcon#first serial, iclass 20, count 2 2006.210.07:52:31.91#ibcon#enter sib2, iclass 20, count 2 2006.210.07:52:31.91#ibcon#flushed, iclass 20, count 2 2006.210.07:52:31.91#ibcon#about to write, iclass 20, count 2 2006.210.07:52:31.91#ibcon#wrote, iclass 20, count 2 2006.210.07:52:31.91#ibcon#about to read 3, iclass 20, count 2 2006.210.07:52:31.93#ibcon#read 3, iclass 20, count 2 2006.210.07:52:31.93#ibcon#about to read 4, iclass 20, count 2 2006.210.07:52:31.93#ibcon#read 4, iclass 20, count 2 2006.210.07:52:31.93#ibcon#about to read 5, iclass 20, count 2 2006.210.07:52:31.93#ibcon#read 5, iclass 20, count 2 2006.210.07:52:31.93#ibcon#about to read 6, iclass 20, count 2 2006.210.07:52:31.93#ibcon#read 6, iclass 20, count 2 2006.210.07:52:31.93#ibcon#end of sib2, iclass 20, count 2 2006.210.07:52:31.93#ibcon#*mode == 0, iclass 20, count 2 2006.210.07:52:31.93#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.07:52:31.93#ibcon#[27=AT06-03\r\n] 2006.210.07:52:31.93#ibcon#*before write, iclass 20, count 2 2006.210.07:52:31.93#ibcon#enter sib2, iclass 20, count 2 2006.210.07:52:31.93#ibcon#flushed, iclass 20, count 2 2006.210.07:52:31.93#ibcon#about to write, iclass 20, count 2 2006.210.07:52:31.93#ibcon#wrote, iclass 20, count 2 2006.210.07:52:31.93#ibcon#about to read 3, iclass 20, count 2 2006.210.07:52:31.96#ibcon#read 3, iclass 20, count 2 2006.210.07:52:31.96#ibcon#about to read 4, iclass 20, count 2 2006.210.07:52:31.96#ibcon#read 4, iclass 20, count 2 2006.210.07:52:31.96#ibcon#about to read 5, iclass 20, count 2 2006.210.07:52:31.96#ibcon#read 5, iclass 20, count 2 2006.210.07:52:31.96#ibcon#about to read 6, iclass 20, count 2 2006.210.07:52:31.96#ibcon#read 6, iclass 20, count 2 2006.210.07:52:31.96#ibcon#end of sib2, iclass 20, count 2 2006.210.07:52:31.96#ibcon#*after write, iclass 20, count 2 2006.210.07:52:31.96#ibcon#*before return 0, iclass 20, count 2 2006.210.07:52:31.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:31.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.07:52:31.96#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.07:52:31.96#ibcon#ireg 7 cls_cnt 0 2006.210.07:52:31.96#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:32.08#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:32.08#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:32.08#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:52:32.08#ibcon#first serial, iclass 20, count 0 2006.210.07:52:32.08#ibcon#enter sib2, iclass 20, count 0 2006.210.07:52:32.08#ibcon#flushed, iclass 20, count 0 2006.210.07:52:32.08#ibcon#about to write, iclass 20, count 0 2006.210.07:52:32.08#ibcon#wrote, iclass 20, count 0 2006.210.07:52:32.08#ibcon#about to read 3, iclass 20, count 0 2006.210.07:52:32.10#ibcon#read 3, iclass 20, count 0 2006.210.07:52:32.10#ibcon#about to read 4, iclass 20, count 0 2006.210.07:52:32.10#ibcon#read 4, iclass 20, count 0 2006.210.07:52:32.10#ibcon#about to read 5, iclass 20, count 0 2006.210.07:52:32.10#ibcon#read 5, iclass 20, count 0 2006.210.07:52:32.10#ibcon#about to read 6, iclass 20, count 0 2006.210.07:52:32.10#ibcon#read 6, iclass 20, count 0 2006.210.07:52:32.10#ibcon#end of sib2, iclass 20, count 0 2006.210.07:52:32.10#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:52:32.10#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:52:32.10#ibcon#[27=USB\r\n] 2006.210.07:52:32.10#ibcon#*before write, iclass 20, count 0 2006.210.07:52:32.10#ibcon#enter sib2, iclass 20, count 0 2006.210.07:52:32.10#ibcon#flushed, iclass 20, count 0 2006.210.07:52:32.10#ibcon#about to write, iclass 20, count 0 2006.210.07:52:32.10#ibcon#wrote, iclass 20, count 0 2006.210.07:52:32.10#ibcon#about to read 3, iclass 20, count 0 2006.210.07:52:32.13#ibcon#read 3, iclass 20, count 0 2006.210.07:52:32.13#ibcon#about to read 4, iclass 20, count 0 2006.210.07:52:32.13#ibcon#read 4, iclass 20, count 0 2006.210.07:52:32.13#ibcon#about to read 5, iclass 20, count 0 2006.210.07:52:32.13#ibcon#read 5, iclass 20, count 0 2006.210.07:52:32.13#ibcon#about to read 6, iclass 20, count 0 2006.210.07:52:32.13#ibcon#read 6, iclass 20, count 0 2006.210.07:52:32.13#ibcon#end of sib2, iclass 20, count 0 2006.210.07:52:32.13#ibcon#*after write, iclass 20, count 0 2006.210.07:52:32.13#ibcon#*before return 0, iclass 20, count 0 2006.210.07:52:32.13#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:32.13#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.07:52:32.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:52:32.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:52:32.13$vc4f8/vabw=wide 2006.210.07:52:32.13#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.07:52:32.13#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.07:52:32.13#ibcon#ireg 8 cls_cnt 0 2006.210.07:52:32.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:32.13#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:32.13#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:32.13#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:52:32.13#ibcon#first serial, iclass 22, count 0 2006.210.07:52:32.13#ibcon#enter sib2, iclass 22, count 0 2006.210.07:52:32.13#ibcon#flushed, iclass 22, count 0 2006.210.07:52:32.13#ibcon#about to write, iclass 22, count 0 2006.210.07:52:32.13#ibcon#wrote, iclass 22, count 0 2006.210.07:52:32.13#ibcon#about to read 3, iclass 22, count 0 2006.210.07:52:32.15#ibcon#read 3, iclass 22, count 0 2006.210.07:52:32.15#ibcon#about to read 4, iclass 22, count 0 2006.210.07:52:32.15#ibcon#read 4, iclass 22, count 0 2006.210.07:52:32.15#ibcon#about to read 5, iclass 22, count 0 2006.210.07:52:32.15#ibcon#read 5, iclass 22, count 0 2006.210.07:52:32.15#ibcon#about to read 6, iclass 22, count 0 2006.210.07:52:32.15#ibcon#read 6, iclass 22, count 0 2006.210.07:52:32.15#ibcon#end of sib2, iclass 22, count 0 2006.210.07:52:32.15#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:52:32.15#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:52:32.15#ibcon#[25=BW32\r\n] 2006.210.07:52:32.15#ibcon#*before write, iclass 22, count 0 2006.210.07:52:32.15#ibcon#enter sib2, iclass 22, count 0 2006.210.07:52:32.15#ibcon#flushed, iclass 22, count 0 2006.210.07:52:32.15#ibcon#about to write, iclass 22, count 0 2006.210.07:52:32.15#ibcon#wrote, iclass 22, count 0 2006.210.07:52:32.15#ibcon#about to read 3, iclass 22, count 0 2006.210.07:52:32.18#ibcon#read 3, iclass 22, count 0 2006.210.07:52:32.18#ibcon#about to read 4, iclass 22, count 0 2006.210.07:52:32.18#ibcon#read 4, iclass 22, count 0 2006.210.07:52:32.18#ibcon#about to read 5, iclass 22, count 0 2006.210.07:52:32.18#ibcon#read 5, iclass 22, count 0 2006.210.07:52:32.18#ibcon#about to read 6, iclass 22, count 0 2006.210.07:52:32.18#ibcon#read 6, iclass 22, count 0 2006.210.07:52:32.18#ibcon#end of sib2, iclass 22, count 0 2006.210.07:52:32.18#ibcon#*after write, iclass 22, count 0 2006.210.07:52:32.18#ibcon#*before return 0, iclass 22, count 0 2006.210.07:52:32.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:32.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.07:52:32.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:52:32.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:52:32.18$vc4f8/vbbw=wide 2006.210.07:52:32.18#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:52:32.18#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:52:32.18#ibcon#ireg 8 cls_cnt 0 2006.210.07:52:32.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:52:32.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:52:32.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:52:32.25#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:52:32.25#ibcon#first serial, iclass 24, count 0 2006.210.07:52:32.25#ibcon#enter sib2, iclass 24, count 0 2006.210.07:52:32.25#ibcon#flushed, iclass 24, count 0 2006.210.07:52:32.25#ibcon#about to write, iclass 24, count 0 2006.210.07:52:32.25#ibcon#wrote, iclass 24, count 0 2006.210.07:52:32.25#ibcon#about to read 3, iclass 24, count 0 2006.210.07:52:32.27#ibcon#read 3, iclass 24, count 0 2006.210.07:52:32.27#ibcon#about to read 4, iclass 24, count 0 2006.210.07:52:32.27#ibcon#read 4, iclass 24, count 0 2006.210.07:52:32.27#ibcon#about to read 5, iclass 24, count 0 2006.210.07:52:32.27#ibcon#read 5, iclass 24, count 0 2006.210.07:52:32.27#ibcon#about to read 6, iclass 24, count 0 2006.210.07:52:32.27#ibcon#read 6, iclass 24, count 0 2006.210.07:52:32.27#ibcon#end of sib2, iclass 24, count 0 2006.210.07:52:32.27#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:52:32.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:52:32.27#ibcon#[27=BW32\r\n] 2006.210.07:52:32.27#ibcon#*before write, iclass 24, count 0 2006.210.07:52:32.27#ibcon#enter sib2, iclass 24, count 0 2006.210.07:52:32.27#ibcon#flushed, iclass 24, count 0 2006.210.07:52:32.27#ibcon#about to write, iclass 24, count 0 2006.210.07:52:32.27#ibcon#wrote, iclass 24, count 0 2006.210.07:52:32.27#ibcon#about to read 3, iclass 24, count 0 2006.210.07:52:32.30#ibcon#read 3, iclass 24, count 0 2006.210.07:52:32.30#ibcon#about to read 4, iclass 24, count 0 2006.210.07:52:32.30#ibcon#read 4, iclass 24, count 0 2006.210.07:52:32.30#ibcon#about to read 5, iclass 24, count 0 2006.210.07:52:32.30#ibcon#read 5, iclass 24, count 0 2006.210.07:52:32.30#ibcon#about to read 6, iclass 24, count 0 2006.210.07:52:32.30#ibcon#read 6, iclass 24, count 0 2006.210.07:52:32.30#ibcon#end of sib2, iclass 24, count 0 2006.210.07:52:32.30#ibcon#*after write, iclass 24, count 0 2006.210.07:52:32.30#ibcon#*before return 0, iclass 24, count 0 2006.210.07:52:32.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:52:32.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:52:32.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:52:32.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:52:32.30$4f8m12a/ifd4f 2006.210.07:52:32.30$ifd4f/lo= 2006.210.07:52:32.30$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:52:32.30$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:52:32.30$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:52:32.30$ifd4f/patch= 2006.210.07:52:32.30$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:52:32.30$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:52:32.30$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:52:32.30$4f8m12a/"form=m,16.000,1:2 2006.210.07:52:32.30$4f8m12a/"tpicd 2006.210.07:52:32.30$4f8m12a/echo=off 2006.210.07:52:32.30$4f8m12a/xlog=off 2006.210.07:52:32.30:!2006.210.07:53:00 2006.210.07:52:41.14#trakl#Source acquired 2006.210.07:52:42.14#flagr#flagr/antenna,acquired 2006.210.07:53:00.00:preob 2006.210.07:53:01.14/onsource/TRACKING 2006.210.07:53:01.14:!2006.210.07:53:10 2006.210.07:53:10.00:data_valid=on 2006.210.07:53:10.00:midob 2006.210.07:53:10.14/onsource/TRACKING 2006.210.07:53:10.14/wx/30.58,1006.3,75 2006.210.07:53:10.27/cable/+6.3949E-03 2006.210.07:53:11.36/va/01,08,usb,yes,29,31 2006.210.07:53:11.36/va/02,07,usb,yes,29,31 2006.210.07:53:11.36/va/03,06,usb,yes,31,31 2006.210.07:53:11.36/va/04,07,usb,yes,30,33 2006.210.07:53:11.36/va/05,07,usb,yes,31,33 2006.210.07:53:11.36/va/06,06,usb,yes,31,30 2006.210.07:53:11.36/va/07,06,usb,yes,31,31 2006.210.07:53:11.36/va/08,07,usb,yes,29,29 2006.210.07:53:11.59/valo/01,532.99,yes,locked 2006.210.07:53:11.59/valo/02,572.99,yes,locked 2006.210.07:53:11.59/valo/03,672.99,yes,locked 2006.210.07:53:11.59/valo/04,832.99,yes,locked 2006.210.07:53:11.59/valo/05,652.99,yes,locked 2006.210.07:53:11.59/valo/06,772.99,yes,locked 2006.210.07:53:11.59/valo/07,832.99,yes,locked 2006.210.07:53:11.59/valo/08,852.99,yes,locked 2006.210.07:53:12.68/vb/01,04,usb,yes,29,27 2006.210.07:53:12.68/vb/02,04,usb,yes,30,32 2006.210.07:53:12.68/vb/03,03,usb,yes,34,38 2006.210.07:53:12.68/vb/04,03,usb,yes,35,35 2006.210.07:53:12.68/vb/05,03,usb,yes,33,37 2006.210.07:53:12.68/vb/06,03,usb,yes,34,37 2006.210.07:53:12.68/vb/07,04,usb,yes,29,29 2006.210.07:53:12.68/vb/08,03,usb,yes,34,37 2006.210.07:53:12.91/vblo/01,632.99,yes,locked 2006.210.07:53:12.91/vblo/02,640.99,yes,locked 2006.210.07:53:12.91/vblo/03,656.99,yes,locked 2006.210.07:53:12.91/vblo/04,712.99,yes,locked 2006.210.07:53:12.91/vblo/05,744.99,yes,locked 2006.210.07:53:12.91/vblo/06,752.99,yes,locked 2006.210.07:53:12.91/vblo/07,734.99,yes,locked 2006.210.07:53:12.91/vblo/08,744.99,yes,locked 2006.210.07:53:13.06/vabw/8 2006.210.07:53:13.21/vbbw/8 2006.210.07:53:13.30/xfe/off,on,12.5 2006.210.07:53:13.68/ifatt/23,28,28,28 2006.210.07:53:14.08/fmout-gps/S +4.65E-07 2006.210.07:53:14.12:!2006.210.07:54:10 2006.210.07:54:10.00:data_valid=off 2006.210.07:54:10.00:postob 2006.210.07:54:10.10/cable/+6.3947E-03 2006.210.07:54:10.10/wx/30.59,1006.3,76 2006.210.07:54:11.08/fmout-gps/S +4.65E-07 2006.210.07:54:11.08:scan_name=210-0755,k06210,60 2006.210.07:54:11.09:source=3c418,203837.03,511912.7,2000.0,cw 2006.210.07:54:11.14#flagr#flagr/antenna,new-source 2006.210.07:54:12.14:checkk5 2006.210.07:54:12.47/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:54:12.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:54:13.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:54:13.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:54:13.84/chk_obsdata//k5ts1/T2100753??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:54:14.17/chk_obsdata//k5ts2/T2100753??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:54:14.51/chk_obsdata//k5ts3/T2100753??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:54:14.84/chk_obsdata//k5ts4/T2100753??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:54:15.50/k5log//k5ts1_log_newline 2006.210.07:54:16.15/k5log//k5ts2_log_newline 2006.210.07:54:16.81/k5log//k5ts3_log_newline 2006.210.07:54:17.46/k5log//k5ts4_log_newline 2006.210.07:54:17.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:54:17.48:4f8m12a=2 2006.210.07:54:17.48$4f8m12a/echo=on 2006.210.07:54:17.48$4f8m12a/pcalon 2006.210.07:54:17.48$pcalon/"no phase cal control is implemented here 2006.210.07:54:17.49$4f8m12a/"tpicd=stop 2006.210.07:54:17.49$4f8m12a/vc4f8 2006.210.07:54:17.49$vc4f8/valo=1,532.99 2006.210.07:54:17.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.07:54:17.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.07:54:17.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:17.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:17.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:17.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:17.49#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:54:17.49#ibcon#first serial, iclass 31, count 0 2006.210.07:54:17.49#ibcon#enter sib2, iclass 31, count 0 2006.210.07:54:17.49#ibcon#flushed, iclass 31, count 0 2006.210.07:54:17.49#ibcon#about to write, iclass 31, count 0 2006.210.07:54:17.49#ibcon#wrote, iclass 31, count 0 2006.210.07:54:17.49#ibcon#about to read 3, iclass 31, count 0 2006.210.07:54:17.51#ibcon#read 3, iclass 31, count 0 2006.210.07:54:17.51#ibcon#about to read 4, iclass 31, count 0 2006.210.07:54:17.51#ibcon#read 4, iclass 31, count 0 2006.210.07:54:17.51#ibcon#about to read 5, iclass 31, count 0 2006.210.07:54:17.51#ibcon#read 5, iclass 31, count 0 2006.210.07:54:17.51#ibcon#about to read 6, iclass 31, count 0 2006.210.07:54:17.51#ibcon#read 6, iclass 31, count 0 2006.210.07:54:17.51#ibcon#end of sib2, iclass 31, count 0 2006.210.07:54:17.51#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:54:17.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:54:17.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:54:17.51#ibcon#*before write, iclass 31, count 0 2006.210.07:54:17.51#ibcon#enter sib2, iclass 31, count 0 2006.210.07:54:17.51#ibcon#flushed, iclass 31, count 0 2006.210.07:54:17.51#ibcon#about to write, iclass 31, count 0 2006.210.07:54:17.51#ibcon#wrote, iclass 31, count 0 2006.210.07:54:17.51#ibcon#about to read 3, iclass 31, count 0 2006.210.07:54:17.56#ibcon#read 3, iclass 31, count 0 2006.210.07:54:17.56#ibcon#about to read 4, iclass 31, count 0 2006.210.07:54:17.56#ibcon#read 4, iclass 31, count 0 2006.210.07:54:17.56#ibcon#about to read 5, iclass 31, count 0 2006.210.07:54:17.56#ibcon#read 5, iclass 31, count 0 2006.210.07:54:17.56#ibcon#about to read 6, iclass 31, count 0 2006.210.07:54:17.56#ibcon#read 6, iclass 31, count 0 2006.210.07:54:17.56#ibcon#end of sib2, iclass 31, count 0 2006.210.07:54:17.56#ibcon#*after write, iclass 31, count 0 2006.210.07:54:17.56#ibcon#*before return 0, iclass 31, count 0 2006.210.07:54:17.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:17.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:17.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:54:17.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:54:17.56$vc4f8/va=1,8 2006.210.07:54:17.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.07:54:17.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.07:54:17.56#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:17.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:17.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:17.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:17.56#ibcon#enter wrdev, iclass 33, count 2 2006.210.07:54:17.56#ibcon#first serial, iclass 33, count 2 2006.210.07:54:17.56#ibcon#enter sib2, iclass 33, count 2 2006.210.07:54:17.56#ibcon#flushed, iclass 33, count 2 2006.210.07:54:17.56#ibcon#about to write, iclass 33, count 2 2006.210.07:54:17.56#ibcon#wrote, iclass 33, count 2 2006.210.07:54:17.56#ibcon#about to read 3, iclass 33, count 2 2006.210.07:54:17.58#ibcon#read 3, iclass 33, count 2 2006.210.07:54:17.58#ibcon#about to read 4, iclass 33, count 2 2006.210.07:54:17.58#ibcon#read 4, iclass 33, count 2 2006.210.07:54:17.58#ibcon#about to read 5, iclass 33, count 2 2006.210.07:54:17.58#ibcon#read 5, iclass 33, count 2 2006.210.07:54:17.58#ibcon#about to read 6, iclass 33, count 2 2006.210.07:54:17.58#ibcon#read 6, iclass 33, count 2 2006.210.07:54:17.58#ibcon#end of sib2, iclass 33, count 2 2006.210.07:54:17.58#ibcon#*mode == 0, iclass 33, count 2 2006.210.07:54:17.58#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.07:54:17.58#ibcon#[25=AT01-08\r\n] 2006.210.07:54:17.58#ibcon#*before write, iclass 33, count 2 2006.210.07:54:17.58#ibcon#enter sib2, iclass 33, count 2 2006.210.07:54:17.58#ibcon#flushed, iclass 33, count 2 2006.210.07:54:17.58#ibcon#about to write, iclass 33, count 2 2006.210.07:54:17.58#ibcon#wrote, iclass 33, count 2 2006.210.07:54:17.58#ibcon#about to read 3, iclass 33, count 2 2006.210.07:54:17.61#ibcon#read 3, iclass 33, count 2 2006.210.07:54:17.61#ibcon#about to read 4, iclass 33, count 2 2006.210.07:54:17.61#ibcon#read 4, iclass 33, count 2 2006.210.07:54:17.61#ibcon#about to read 5, iclass 33, count 2 2006.210.07:54:17.61#ibcon#read 5, iclass 33, count 2 2006.210.07:54:17.61#ibcon#about to read 6, iclass 33, count 2 2006.210.07:54:17.61#ibcon#read 6, iclass 33, count 2 2006.210.07:54:17.61#ibcon#end of sib2, iclass 33, count 2 2006.210.07:54:17.61#ibcon#*after write, iclass 33, count 2 2006.210.07:54:17.61#ibcon#*before return 0, iclass 33, count 2 2006.210.07:54:17.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:17.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:17.61#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.07:54:17.61#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:17.61#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:17.73#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:17.73#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:17.73#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:54:17.73#ibcon#first serial, iclass 33, count 0 2006.210.07:54:17.73#ibcon#enter sib2, iclass 33, count 0 2006.210.07:54:17.73#ibcon#flushed, iclass 33, count 0 2006.210.07:54:17.73#ibcon#about to write, iclass 33, count 0 2006.210.07:54:17.73#ibcon#wrote, iclass 33, count 0 2006.210.07:54:17.73#ibcon#about to read 3, iclass 33, count 0 2006.210.07:54:17.75#ibcon#read 3, iclass 33, count 0 2006.210.07:54:17.75#ibcon#about to read 4, iclass 33, count 0 2006.210.07:54:17.75#ibcon#read 4, iclass 33, count 0 2006.210.07:54:17.75#ibcon#about to read 5, iclass 33, count 0 2006.210.07:54:17.75#ibcon#read 5, iclass 33, count 0 2006.210.07:54:17.75#ibcon#about to read 6, iclass 33, count 0 2006.210.07:54:17.75#ibcon#read 6, iclass 33, count 0 2006.210.07:54:17.75#ibcon#end of sib2, iclass 33, count 0 2006.210.07:54:17.75#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:54:17.75#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:54:17.75#ibcon#[25=USB\r\n] 2006.210.07:54:17.75#ibcon#*before write, iclass 33, count 0 2006.210.07:54:17.75#ibcon#enter sib2, iclass 33, count 0 2006.210.07:54:17.75#ibcon#flushed, iclass 33, count 0 2006.210.07:54:17.75#ibcon#about to write, iclass 33, count 0 2006.210.07:54:17.75#ibcon#wrote, iclass 33, count 0 2006.210.07:54:17.75#ibcon#about to read 3, iclass 33, count 0 2006.210.07:54:17.78#ibcon#read 3, iclass 33, count 0 2006.210.07:54:17.78#ibcon#about to read 4, iclass 33, count 0 2006.210.07:54:17.78#ibcon#read 4, iclass 33, count 0 2006.210.07:54:17.78#ibcon#about to read 5, iclass 33, count 0 2006.210.07:54:17.78#ibcon#read 5, iclass 33, count 0 2006.210.07:54:17.78#ibcon#about to read 6, iclass 33, count 0 2006.210.07:54:17.78#ibcon#read 6, iclass 33, count 0 2006.210.07:54:17.78#ibcon#end of sib2, iclass 33, count 0 2006.210.07:54:17.78#ibcon#*after write, iclass 33, count 0 2006.210.07:54:17.78#ibcon#*before return 0, iclass 33, count 0 2006.210.07:54:17.78#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:17.78#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:17.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:54:17.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:54:17.78$vc4f8/valo=2,572.99 2006.210.07:54:17.78#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.07:54:17.78#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.07:54:17.78#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:17.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:17.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:17.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:17.78#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:54:17.78#ibcon#first serial, iclass 35, count 0 2006.210.07:54:17.78#ibcon#enter sib2, iclass 35, count 0 2006.210.07:54:17.78#ibcon#flushed, iclass 35, count 0 2006.210.07:54:17.78#ibcon#about to write, iclass 35, count 0 2006.210.07:54:17.78#ibcon#wrote, iclass 35, count 0 2006.210.07:54:17.78#ibcon#about to read 3, iclass 35, count 0 2006.210.07:54:17.80#ibcon#read 3, iclass 35, count 0 2006.210.07:54:17.80#ibcon#about to read 4, iclass 35, count 0 2006.210.07:54:17.80#ibcon#read 4, iclass 35, count 0 2006.210.07:54:17.80#ibcon#about to read 5, iclass 35, count 0 2006.210.07:54:17.80#ibcon#read 5, iclass 35, count 0 2006.210.07:54:17.80#ibcon#about to read 6, iclass 35, count 0 2006.210.07:54:17.80#ibcon#read 6, iclass 35, count 0 2006.210.07:54:17.80#ibcon#end of sib2, iclass 35, count 0 2006.210.07:54:17.80#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:54:17.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:54:17.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:54:17.80#ibcon#*before write, iclass 35, count 0 2006.210.07:54:17.80#ibcon#enter sib2, iclass 35, count 0 2006.210.07:54:17.80#ibcon#flushed, iclass 35, count 0 2006.210.07:54:17.80#ibcon#about to write, iclass 35, count 0 2006.210.07:54:17.80#ibcon#wrote, iclass 35, count 0 2006.210.07:54:17.80#ibcon#about to read 3, iclass 35, count 0 2006.210.07:54:17.84#ibcon#read 3, iclass 35, count 0 2006.210.07:54:17.84#ibcon#about to read 4, iclass 35, count 0 2006.210.07:54:17.84#ibcon#read 4, iclass 35, count 0 2006.210.07:54:17.84#ibcon#about to read 5, iclass 35, count 0 2006.210.07:54:17.84#ibcon#read 5, iclass 35, count 0 2006.210.07:54:17.84#ibcon#about to read 6, iclass 35, count 0 2006.210.07:54:17.84#ibcon#read 6, iclass 35, count 0 2006.210.07:54:17.84#ibcon#end of sib2, iclass 35, count 0 2006.210.07:54:17.84#ibcon#*after write, iclass 35, count 0 2006.210.07:54:17.84#ibcon#*before return 0, iclass 35, count 0 2006.210.07:54:17.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:17.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:17.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:54:17.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:54:17.84$vc4f8/va=2,7 2006.210.07:54:17.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:54:17.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:54:17.84#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:17.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:17.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:17.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:17.90#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:54:17.90#ibcon#first serial, iclass 37, count 2 2006.210.07:54:17.90#ibcon#enter sib2, iclass 37, count 2 2006.210.07:54:17.90#ibcon#flushed, iclass 37, count 2 2006.210.07:54:17.90#ibcon#about to write, iclass 37, count 2 2006.210.07:54:17.90#ibcon#wrote, iclass 37, count 2 2006.210.07:54:17.90#ibcon#about to read 3, iclass 37, count 2 2006.210.07:54:17.92#ibcon#read 3, iclass 37, count 2 2006.210.07:54:17.92#ibcon#about to read 4, iclass 37, count 2 2006.210.07:54:17.92#ibcon#read 4, iclass 37, count 2 2006.210.07:54:17.92#ibcon#about to read 5, iclass 37, count 2 2006.210.07:54:17.92#ibcon#read 5, iclass 37, count 2 2006.210.07:54:17.92#ibcon#about to read 6, iclass 37, count 2 2006.210.07:54:17.92#ibcon#read 6, iclass 37, count 2 2006.210.07:54:17.92#ibcon#end of sib2, iclass 37, count 2 2006.210.07:54:17.92#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:54:17.92#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:54:17.92#ibcon#[25=AT02-07\r\n] 2006.210.07:54:17.92#ibcon#*before write, iclass 37, count 2 2006.210.07:54:17.92#ibcon#enter sib2, iclass 37, count 2 2006.210.07:54:17.92#ibcon#flushed, iclass 37, count 2 2006.210.07:54:17.92#ibcon#about to write, iclass 37, count 2 2006.210.07:54:17.92#ibcon#wrote, iclass 37, count 2 2006.210.07:54:17.92#ibcon#about to read 3, iclass 37, count 2 2006.210.07:54:17.95#ibcon#read 3, iclass 37, count 2 2006.210.07:54:17.95#ibcon#about to read 4, iclass 37, count 2 2006.210.07:54:17.95#ibcon#read 4, iclass 37, count 2 2006.210.07:54:17.95#ibcon#about to read 5, iclass 37, count 2 2006.210.07:54:17.95#ibcon#read 5, iclass 37, count 2 2006.210.07:54:17.95#ibcon#about to read 6, iclass 37, count 2 2006.210.07:54:17.95#ibcon#read 6, iclass 37, count 2 2006.210.07:54:17.95#ibcon#end of sib2, iclass 37, count 2 2006.210.07:54:17.95#ibcon#*after write, iclass 37, count 2 2006.210.07:54:17.95#ibcon#*before return 0, iclass 37, count 2 2006.210.07:54:17.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:17.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:17.95#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:54:17.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:17.95#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:18.07#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:18.07#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:18.07#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:54:18.07#ibcon#first serial, iclass 37, count 0 2006.210.07:54:18.07#ibcon#enter sib2, iclass 37, count 0 2006.210.07:54:18.07#ibcon#flushed, iclass 37, count 0 2006.210.07:54:18.07#ibcon#about to write, iclass 37, count 0 2006.210.07:54:18.07#ibcon#wrote, iclass 37, count 0 2006.210.07:54:18.07#ibcon#about to read 3, iclass 37, count 0 2006.210.07:54:18.09#ibcon#read 3, iclass 37, count 0 2006.210.07:54:18.09#ibcon#about to read 4, iclass 37, count 0 2006.210.07:54:18.09#ibcon#read 4, iclass 37, count 0 2006.210.07:54:18.09#ibcon#about to read 5, iclass 37, count 0 2006.210.07:54:18.09#ibcon#read 5, iclass 37, count 0 2006.210.07:54:18.09#ibcon#about to read 6, iclass 37, count 0 2006.210.07:54:18.09#ibcon#read 6, iclass 37, count 0 2006.210.07:54:18.09#ibcon#end of sib2, iclass 37, count 0 2006.210.07:54:18.09#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:54:18.09#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:54:18.09#ibcon#[25=USB\r\n] 2006.210.07:54:18.09#ibcon#*before write, iclass 37, count 0 2006.210.07:54:18.09#ibcon#enter sib2, iclass 37, count 0 2006.210.07:54:18.09#ibcon#flushed, iclass 37, count 0 2006.210.07:54:18.09#ibcon#about to write, iclass 37, count 0 2006.210.07:54:18.09#ibcon#wrote, iclass 37, count 0 2006.210.07:54:18.09#ibcon#about to read 3, iclass 37, count 0 2006.210.07:54:18.12#ibcon#read 3, iclass 37, count 0 2006.210.07:54:18.12#ibcon#about to read 4, iclass 37, count 0 2006.210.07:54:18.12#ibcon#read 4, iclass 37, count 0 2006.210.07:54:18.12#ibcon#about to read 5, iclass 37, count 0 2006.210.07:54:18.12#ibcon#read 5, iclass 37, count 0 2006.210.07:54:18.12#ibcon#about to read 6, iclass 37, count 0 2006.210.07:54:18.12#ibcon#read 6, iclass 37, count 0 2006.210.07:54:18.12#ibcon#end of sib2, iclass 37, count 0 2006.210.07:54:18.12#ibcon#*after write, iclass 37, count 0 2006.210.07:54:18.12#ibcon#*before return 0, iclass 37, count 0 2006.210.07:54:18.12#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:18.12#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:18.12#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:54:18.12#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:54:18.12$vc4f8/valo=3,672.99 2006.210.07:54:18.12#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.07:54:18.12#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.07:54:18.12#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:18.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:18.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:18.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:18.12#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:54:18.12#ibcon#first serial, iclass 39, count 0 2006.210.07:54:18.12#ibcon#enter sib2, iclass 39, count 0 2006.210.07:54:18.12#ibcon#flushed, iclass 39, count 0 2006.210.07:54:18.12#ibcon#about to write, iclass 39, count 0 2006.210.07:54:18.12#ibcon#wrote, iclass 39, count 0 2006.210.07:54:18.12#ibcon#about to read 3, iclass 39, count 0 2006.210.07:54:18.14#ibcon#read 3, iclass 39, count 0 2006.210.07:54:18.14#ibcon#about to read 4, iclass 39, count 0 2006.210.07:54:18.14#ibcon#read 4, iclass 39, count 0 2006.210.07:54:18.14#ibcon#about to read 5, iclass 39, count 0 2006.210.07:54:18.14#ibcon#read 5, iclass 39, count 0 2006.210.07:54:18.14#ibcon#about to read 6, iclass 39, count 0 2006.210.07:54:18.14#ibcon#read 6, iclass 39, count 0 2006.210.07:54:18.14#ibcon#end of sib2, iclass 39, count 0 2006.210.07:54:18.14#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:54:18.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:54:18.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:54:18.14#ibcon#*before write, iclass 39, count 0 2006.210.07:54:18.14#ibcon#enter sib2, iclass 39, count 0 2006.210.07:54:18.14#ibcon#flushed, iclass 39, count 0 2006.210.07:54:18.14#ibcon#about to write, iclass 39, count 0 2006.210.07:54:18.14#ibcon#wrote, iclass 39, count 0 2006.210.07:54:18.14#ibcon#about to read 3, iclass 39, count 0 2006.210.07:54:18.18#ibcon#read 3, iclass 39, count 0 2006.210.07:54:18.18#ibcon#about to read 4, iclass 39, count 0 2006.210.07:54:18.18#ibcon#read 4, iclass 39, count 0 2006.210.07:54:18.18#ibcon#about to read 5, iclass 39, count 0 2006.210.07:54:18.18#ibcon#read 5, iclass 39, count 0 2006.210.07:54:18.18#ibcon#about to read 6, iclass 39, count 0 2006.210.07:54:18.18#ibcon#read 6, iclass 39, count 0 2006.210.07:54:18.18#ibcon#end of sib2, iclass 39, count 0 2006.210.07:54:18.18#ibcon#*after write, iclass 39, count 0 2006.210.07:54:18.18#ibcon#*before return 0, iclass 39, count 0 2006.210.07:54:18.18#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:18.18#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:18.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:54:18.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:54:18.18$vc4f8/va=3,6 2006.210.07:54:18.18#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.07:54:18.18#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.07:54:18.18#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:18.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:18.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:18.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:18.24#ibcon#enter wrdev, iclass 3, count 2 2006.210.07:54:18.24#ibcon#first serial, iclass 3, count 2 2006.210.07:54:18.24#ibcon#enter sib2, iclass 3, count 2 2006.210.07:54:18.24#ibcon#flushed, iclass 3, count 2 2006.210.07:54:18.24#ibcon#about to write, iclass 3, count 2 2006.210.07:54:18.24#ibcon#wrote, iclass 3, count 2 2006.210.07:54:18.24#ibcon#about to read 3, iclass 3, count 2 2006.210.07:54:18.26#ibcon#read 3, iclass 3, count 2 2006.210.07:54:18.26#ibcon#about to read 4, iclass 3, count 2 2006.210.07:54:18.26#ibcon#read 4, iclass 3, count 2 2006.210.07:54:18.26#ibcon#about to read 5, iclass 3, count 2 2006.210.07:54:18.26#ibcon#read 5, iclass 3, count 2 2006.210.07:54:18.26#ibcon#about to read 6, iclass 3, count 2 2006.210.07:54:18.26#ibcon#read 6, iclass 3, count 2 2006.210.07:54:18.26#ibcon#end of sib2, iclass 3, count 2 2006.210.07:54:18.26#ibcon#*mode == 0, iclass 3, count 2 2006.210.07:54:18.26#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.07:54:18.26#ibcon#[25=AT03-06\r\n] 2006.210.07:54:18.26#ibcon#*before write, iclass 3, count 2 2006.210.07:54:18.26#ibcon#enter sib2, iclass 3, count 2 2006.210.07:54:18.26#ibcon#flushed, iclass 3, count 2 2006.210.07:54:18.26#ibcon#about to write, iclass 3, count 2 2006.210.07:54:18.26#ibcon#wrote, iclass 3, count 2 2006.210.07:54:18.26#ibcon#about to read 3, iclass 3, count 2 2006.210.07:54:18.29#ibcon#read 3, iclass 3, count 2 2006.210.07:54:18.29#ibcon#about to read 4, iclass 3, count 2 2006.210.07:54:18.29#ibcon#read 4, iclass 3, count 2 2006.210.07:54:18.29#ibcon#about to read 5, iclass 3, count 2 2006.210.07:54:18.29#ibcon#read 5, iclass 3, count 2 2006.210.07:54:18.29#ibcon#about to read 6, iclass 3, count 2 2006.210.07:54:18.29#ibcon#read 6, iclass 3, count 2 2006.210.07:54:18.29#ibcon#end of sib2, iclass 3, count 2 2006.210.07:54:18.29#ibcon#*after write, iclass 3, count 2 2006.210.07:54:18.29#ibcon#*before return 0, iclass 3, count 2 2006.210.07:54:18.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:18.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:18.29#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.07:54:18.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:18.29#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:18.41#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:18.41#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:18.41#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:54:18.41#ibcon#first serial, iclass 3, count 0 2006.210.07:54:18.41#ibcon#enter sib2, iclass 3, count 0 2006.210.07:54:18.41#ibcon#flushed, iclass 3, count 0 2006.210.07:54:18.41#ibcon#about to write, iclass 3, count 0 2006.210.07:54:18.41#ibcon#wrote, iclass 3, count 0 2006.210.07:54:18.41#ibcon#about to read 3, iclass 3, count 0 2006.210.07:54:18.43#ibcon#read 3, iclass 3, count 0 2006.210.07:54:18.43#ibcon#about to read 4, iclass 3, count 0 2006.210.07:54:18.43#ibcon#read 4, iclass 3, count 0 2006.210.07:54:18.43#ibcon#about to read 5, iclass 3, count 0 2006.210.07:54:18.43#ibcon#read 5, iclass 3, count 0 2006.210.07:54:18.43#ibcon#about to read 6, iclass 3, count 0 2006.210.07:54:18.43#ibcon#read 6, iclass 3, count 0 2006.210.07:54:18.43#ibcon#end of sib2, iclass 3, count 0 2006.210.07:54:18.43#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:54:18.43#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:54:18.43#ibcon#[25=USB\r\n] 2006.210.07:54:18.43#ibcon#*before write, iclass 3, count 0 2006.210.07:54:18.43#ibcon#enter sib2, iclass 3, count 0 2006.210.07:54:18.43#ibcon#flushed, iclass 3, count 0 2006.210.07:54:18.43#ibcon#about to write, iclass 3, count 0 2006.210.07:54:18.43#ibcon#wrote, iclass 3, count 0 2006.210.07:54:18.43#ibcon#about to read 3, iclass 3, count 0 2006.210.07:54:18.46#ibcon#read 3, iclass 3, count 0 2006.210.07:54:18.46#ibcon#about to read 4, iclass 3, count 0 2006.210.07:54:18.46#ibcon#read 4, iclass 3, count 0 2006.210.07:54:18.46#ibcon#about to read 5, iclass 3, count 0 2006.210.07:54:18.46#ibcon#read 5, iclass 3, count 0 2006.210.07:54:18.46#ibcon#about to read 6, iclass 3, count 0 2006.210.07:54:18.46#ibcon#read 6, iclass 3, count 0 2006.210.07:54:18.46#ibcon#end of sib2, iclass 3, count 0 2006.210.07:54:18.46#ibcon#*after write, iclass 3, count 0 2006.210.07:54:18.46#ibcon#*before return 0, iclass 3, count 0 2006.210.07:54:18.46#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:18.46#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:18.46#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:54:18.46#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:54:18.46$vc4f8/valo=4,832.99 2006.210.07:54:18.46#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.07:54:18.46#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.07:54:18.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:18.46#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:18.46#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:18.46#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:18.46#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:54:18.46#ibcon#first serial, iclass 5, count 0 2006.210.07:54:18.46#ibcon#enter sib2, iclass 5, count 0 2006.210.07:54:18.46#ibcon#flushed, iclass 5, count 0 2006.210.07:54:18.46#ibcon#about to write, iclass 5, count 0 2006.210.07:54:18.46#ibcon#wrote, iclass 5, count 0 2006.210.07:54:18.46#ibcon#about to read 3, iclass 5, count 0 2006.210.07:54:18.48#ibcon#read 3, iclass 5, count 0 2006.210.07:54:18.48#ibcon#about to read 4, iclass 5, count 0 2006.210.07:54:18.48#ibcon#read 4, iclass 5, count 0 2006.210.07:54:18.48#ibcon#about to read 5, iclass 5, count 0 2006.210.07:54:18.48#ibcon#read 5, iclass 5, count 0 2006.210.07:54:18.48#ibcon#about to read 6, iclass 5, count 0 2006.210.07:54:18.48#ibcon#read 6, iclass 5, count 0 2006.210.07:54:18.48#ibcon#end of sib2, iclass 5, count 0 2006.210.07:54:18.48#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:54:18.48#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:54:18.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:54:18.48#ibcon#*before write, iclass 5, count 0 2006.210.07:54:18.48#ibcon#enter sib2, iclass 5, count 0 2006.210.07:54:18.48#ibcon#flushed, iclass 5, count 0 2006.210.07:54:18.48#ibcon#about to write, iclass 5, count 0 2006.210.07:54:18.48#ibcon#wrote, iclass 5, count 0 2006.210.07:54:18.48#ibcon#about to read 3, iclass 5, count 0 2006.210.07:54:18.52#ibcon#read 3, iclass 5, count 0 2006.210.07:54:18.52#ibcon#about to read 4, iclass 5, count 0 2006.210.07:54:18.52#ibcon#read 4, iclass 5, count 0 2006.210.07:54:18.52#ibcon#about to read 5, iclass 5, count 0 2006.210.07:54:18.52#ibcon#read 5, iclass 5, count 0 2006.210.07:54:18.52#ibcon#about to read 6, iclass 5, count 0 2006.210.07:54:18.52#ibcon#read 6, iclass 5, count 0 2006.210.07:54:18.52#ibcon#end of sib2, iclass 5, count 0 2006.210.07:54:18.52#ibcon#*after write, iclass 5, count 0 2006.210.07:54:18.52#ibcon#*before return 0, iclass 5, count 0 2006.210.07:54:18.52#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:18.52#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:18.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:54:18.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:54:18.52$vc4f8/va=4,7 2006.210.07:54:18.52#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.07:54:18.52#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.07:54:18.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:18.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:18.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:18.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:18.58#ibcon#enter wrdev, iclass 7, count 2 2006.210.07:54:18.58#ibcon#first serial, iclass 7, count 2 2006.210.07:54:18.58#ibcon#enter sib2, iclass 7, count 2 2006.210.07:54:18.58#ibcon#flushed, iclass 7, count 2 2006.210.07:54:18.58#ibcon#about to write, iclass 7, count 2 2006.210.07:54:18.58#ibcon#wrote, iclass 7, count 2 2006.210.07:54:18.58#ibcon#about to read 3, iclass 7, count 2 2006.210.07:54:18.60#ibcon#read 3, iclass 7, count 2 2006.210.07:54:18.60#ibcon#about to read 4, iclass 7, count 2 2006.210.07:54:18.60#ibcon#read 4, iclass 7, count 2 2006.210.07:54:18.60#ibcon#about to read 5, iclass 7, count 2 2006.210.07:54:18.60#ibcon#read 5, iclass 7, count 2 2006.210.07:54:18.60#ibcon#about to read 6, iclass 7, count 2 2006.210.07:54:18.60#ibcon#read 6, iclass 7, count 2 2006.210.07:54:18.60#ibcon#end of sib2, iclass 7, count 2 2006.210.07:54:18.60#ibcon#*mode == 0, iclass 7, count 2 2006.210.07:54:18.60#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.07:54:18.60#ibcon#[25=AT04-07\r\n] 2006.210.07:54:18.60#ibcon#*before write, iclass 7, count 2 2006.210.07:54:18.60#ibcon#enter sib2, iclass 7, count 2 2006.210.07:54:18.60#ibcon#flushed, iclass 7, count 2 2006.210.07:54:18.60#ibcon#about to write, iclass 7, count 2 2006.210.07:54:18.60#ibcon#wrote, iclass 7, count 2 2006.210.07:54:18.60#ibcon#about to read 3, iclass 7, count 2 2006.210.07:54:18.63#ibcon#read 3, iclass 7, count 2 2006.210.07:54:18.63#ibcon#about to read 4, iclass 7, count 2 2006.210.07:54:18.63#ibcon#read 4, iclass 7, count 2 2006.210.07:54:18.63#ibcon#about to read 5, iclass 7, count 2 2006.210.07:54:18.63#ibcon#read 5, iclass 7, count 2 2006.210.07:54:18.63#ibcon#about to read 6, iclass 7, count 2 2006.210.07:54:18.63#ibcon#read 6, iclass 7, count 2 2006.210.07:54:18.63#ibcon#end of sib2, iclass 7, count 2 2006.210.07:54:18.63#ibcon#*after write, iclass 7, count 2 2006.210.07:54:18.63#ibcon#*before return 0, iclass 7, count 2 2006.210.07:54:18.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:18.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:18.63#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.07:54:18.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:18.63#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:18.75#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:18.75#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:18.75#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:54:18.75#ibcon#first serial, iclass 7, count 0 2006.210.07:54:18.75#ibcon#enter sib2, iclass 7, count 0 2006.210.07:54:18.75#ibcon#flushed, iclass 7, count 0 2006.210.07:54:18.75#ibcon#about to write, iclass 7, count 0 2006.210.07:54:18.75#ibcon#wrote, iclass 7, count 0 2006.210.07:54:18.75#ibcon#about to read 3, iclass 7, count 0 2006.210.07:54:18.77#ibcon#read 3, iclass 7, count 0 2006.210.07:54:18.77#ibcon#about to read 4, iclass 7, count 0 2006.210.07:54:18.77#ibcon#read 4, iclass 7, count 0 2006.210.07:54:18.77#ibcon#about to read 5, iclass 7, count 0 2006.210.07:54:18.77#ibcon#read 5, iclass 7, count 0 2006.210.07:54:18.77#ibcon#about to read 6, iclass 7, count 0 2006.210.07:54:18.77#ibcon#read 6, iclass 7, count 0 2006.210.07:54:18.77#ibcon#end of sib2, iclass 7, count 0 2006.210.07:54:18.77#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:54:18.77#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:54:18.77#ibcon#[25=USB\r\n] 2006.210.07:54:18.77#ibcon#*before write, iclass 7, count 0 2006.210.07:54:18.77#ibcon#enter sib2, iclass 7, count 0 2006.210.07:54:18.77#ibcon#flushed, iclass 7, count 0 2006.210.07:54:18.77#ibcon#about to write, iclass 7, count 0 2006.210.07:54:18.77#ibcon#wrote, iclass 7, count 0 2006.210.07:54:18.77#ibcon#about to read 3, iclass 7, count 0 2006.210.07:54:18.80#ibcon#read 3, iclass 7, count 0 2006.210.07:54:18.80#ibcon#about to read 4, iclass 7, count 0 2006.210.07:54:18.80#ibcon#read 4, iclass 7, count 0 2006.210.07:54:18.80#ibcon#about to read 5, iclass 7, count 0 2006.210.07:54:18.80#ibcon#read 5, iclass 7, count 0 2006.210.07:54:18.80#ibcon#about to read 6, iclass 7, count 0 2006.210.07:54:18.80#ibcon#read 6, iclass 7, count 0 2006.210.07:54:18.80#ibcon#end of sib2, iclass 7, count 0 2006.210.07:54:18.80#ibcon#*after write, iclass 7, count 0 2006.210.07:54:18.80#ibcon#*before return 0, iclass 7, count 0 2006.210.07:54:18.80#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:18.80#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:18.80#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:54:18.80#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:54:18.80$vc4f8/valo=5,652.99 2006.210.07:54:18.80#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.07:54:18.80#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.07:54:18.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:18.80#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:18.80#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:18.80#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:18.80#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:54:18.80#ibcon#first serial, iclass 11, count 0 2006.210.07:54:18.80#ibcon#enter sib2, iclass 11, count 0 2006.210.07:54:18.80#ibcon#flushed, iclass 11, count 0 2006.210.07:54:18.80#ibcon#about to write, iclass 11, count 0 2006.210.07:54:18.80#ibcon#wrote, iclass 11, count 0 2006.210.07:54:18.80#ibcon#about to read 3, iclass 11, count 0 2006.210.07:54:18.82#ibcon#read 3, iclass 11, count 0 2006.210.07:54:18.82#ibcon#about to read 4, iclass 11, count 0 2006.210.07:54:18.82#ibcon#read 4, iclass 11, count 0 2006.210.07:54:18.82#ibcon#about to read 5, iclass 11, count 0 2006.210.07:54:18.82#ibcon#read 5, iclass 11, count 0 2006.210.07:54:18.82#ibcon#about to read 6, iclass 11, count 0 2006.210.07:54:18.82#ibcon#read 6, iclass 11, count 0 2006.210.07:54:18.82#ibcon#end of sib2, iclass 11, count 0 2006.210.07:54:18.82#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:54:18.82#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:54:18.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:54:18.82#ibcon#*before write, iclass 11, count 0 2006.210.07:54:18.82#ibcon#enter sib2, iclass 11, count 0 2006.210.07:54:18.82#ibcon#flushed, iclass 11, count 0 2006.210.07:54:18.82#ibcon#about to write, iclass 11, count 0 2006.210.07:54:18.82#ibcon#wrote, iclass 11, count 0 2006.210.07:54:18.82#ibcon#about to read 3, iclass 11, count 0 2006.210.07:54:18.86#ibcon#read 3, iclass 11, count 0 2006.210.07:54:18.86#ibcon#about to read 4, iclass 11, count 0 2006.210.07:54:18.86#ibcon#read 4, iclass 11, count 0 2006.210.07:54:18.86#ibcon#about to read 5, iclass 11, count 0 2006.210.07:54:18.86#ibcon#read 5, iclass 11, count 0 2006.210.07:54:18.86#ibcon#about to read 6, iclass 11, count 0 2006.210.07:54:18.86#ibcon#read 6, iclass 11, count 0 2006.210.07:54:18.86#ibcon#end of sib2, iclass 11, count 0 2006.210.07:54:18.86#ibcon#*after write, iclass 11, count 0 2006.210.07:54:18.86#ibcon#*before return 0, iclass 11, count 0 2006.210.07:54:18.86#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:18.86#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:18.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:54:18.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:54:18.86$vc4f8/va=5,7 2006.210.07:54:18.86#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.07:54:18.86#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.07:54:18.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:18.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:18.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:18.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:18.92#ibcon#enter wrdev, iclass 13, count 2 2006.210.07:54:18.92#ibcon#first serial, iclass 13, count 2 2006.210.07:54:18.92#ibcon#enter sib2, iclass 13, count 2 2006.210.07:54:18.92#ibcon#flushed, iclass 13, count 2 2006.210.07:54:18.92#ibcon#about to write, iclass 13, count 2 2006.210.07:54:18.92#ibcon#wrote, iclass 13, count 2 2006.210.07:54:18.92#ibcon#about to read 3, iclass 13, count 2 2006.210.07:54:18.94#ibcon#read 3, iclass 13, count 2 2006.210.07:54:18.94#ibcon#about to read 4, iclass 13, count 2 2006.210.07:54:18.94#ibcon#read 4, iclass 13, count 2 2006.210.07:54:18.94#ibcon#about to read 5, iclass 13, count 2 2006.210.07:54:18.94#ibcon#read 5, iclass 13, count 2 2006.210.07:54:18.94#ibcon#about to read 6, iclass 13, count 2 2006.210.07:54:18.94#ibcon#read 6, iclass 13, count 2 2006.210.07:54:18.94#ibcon#end of sib2, iclass 13, count 2 2006.210.07:54:18.94#ibcon#*mode == 0, iclass 13, count 2 2006.210.07:54:18.94#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.07:54:18.94#ibcon#[25=AT05-07\r\n] 2006.210.07:54:18.94#ibcon#*before write, iclass 13, count 2 2006.210.07:54:18.94#ibcon#enter sib2, iclass 13, count 2 2006.210.07:54:18.94#ibcon#flushed, iclass 13, count 2 2006.210.07:54:18.94#ibcon#about to write, iclass 13, count 2 2006.210.07:54:18.94#ibcon#wrote, iclass 13, count 2 2006.210.07:54:18.94#ibcon#about to read 3, iclass 13, count 2 2006.210.07:54:18.97#ibcon#read 3, iclass 13, count 2 2006.210.07:54:18.97#ibcon#about to read 4, iclass 13, count 2 2006.210.07:54:18.97#ibcon#read 4, iclass 13, count 2 2006.210.07:54:18.97#ibcon#about to read 5, iclass 13, count 2 2006.210.07:54:18.97#ibcon#read 5, iclass 13, count 2 2006.210.07:54:18.97#ibcon#about to read 6, iclass 13, count 2 2006.210.07:54:18.97#ibcon#read 6, iclass 13, count 2 2006.210.07:54:18.97#ibcon#end of sib2, iclass 13, count 2 2006.210.07:54:18.97#ibcon#*after write, iclass 13, count 2 2006.210.07:54:18.97#ibcon#*before return 0, iclass 13, count 2 2006.210.07:54:18.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:18.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:18.97#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.07:54:18.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:18.97#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:19.09#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:19.09#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:19.09#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:54:19.09#ibcon#first serial, iclass 13, count 0 2006.210.07:54:19.09#ibcon#enter sib2, iclass 13, count 0 2006.210.07:54:19.09#ibcon#flushed, iclass 13, count 0 2006.210.07:54:19.09#ibcon#about to write, iclass 13, count 0 2006.210.07:54:19.09#ibcon#wrote, iclass 13, count 0 2006.210.07:54:19.09#ibcon#about to read 3, iclass 13, count 0 2006.210.07:54:19.11#ibcon#read 3, iclass 13, count 0 2006.210.07:54:19.11#ibcon#about to read 4, iclass 13, count 0 2006.210.07:54:19.11#ibcon#read 4, iclass 13, count 0 2006.210.07:54:19.11#ibcon#about to read 5, iclass 13, count 0 2006.210.07:54:19.11#ibcon#read 5, iclass 13, count 0 2006.210.07:54:19.11#ibcon#about to read 6, iclass 13, count 0 2006.210.07:54:19.11#ibcon#read 6, iclass 13, count 0 2006.210.07:54:19.11#ibcon#end of sib2, iclass 13, count 0 2006.210.07:54:19.11#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:54:19.11#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:54:19.11#ibcon#[25=USB\r\n] 2006.210.07:54:19.11#ibcon#*before write, iclass 13, count 0 2006.210.07:54:19.11#ibcon#enter sib2, iclass 13, count 0 2006.210.07:54:19.11#ibcon#flushed, iclass 13, count 0 2006.210.07:54:19.11#ibcon#about to write, iclass 13, count 0 2006.210.07:54:19.11#ibcon#wrote, iclass 13, count 0 2006.210.07:54:19.11#ibcon#about to read 3, iclass 13, count 0 2006.210.07:54:19.14#ibcon#read 3, iclass 13, count 0 2006.210.07:54:19.14#ibcon#about to read 4, iclass 13, count 0 2006.210.07:54:19.14#ibcon#read 4, iclass 13, count 0 2006.210.07:54:19.14#ibcon#about to read 5, iclass 13, count 0 2006.210.07:54:19.14#ibcon#read 5, iclass 13, count 0 2006.210.07:54:19.14#ibcon#about to read 6, iclass 13, count 0 2006.210.07:54:19.14#ibcon#read 6, iclass 13, count 0 2006.210.07:54:19.14#ibcon#end of sib2, iclass 13, count 0 2006.210.07:54:19.14#ibcon#*after write, iclass 13, count 0 2006.210.07:54:19.14#ibcon#*before return 0, iclass 13, count 0 2006.210.07:54:19.14#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:19.14#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:19.14#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:54:19.14#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:54:19.14$vc4f8/valo=6,772.99 2006.210.07:54:19.14#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.07:54:19.14#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.07:54:19.14#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:19.14#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:19.14#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:19.14#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:19.14#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:54:19.14#ibcon#first serial, iclass 15, count 0 2006.210.07:54:19.14#ibcon#enter sib2, iclass 15, count 0 2006.210.07:54:19.14#ibcon#flushed, iclass 15, count 0 2006.210.07:54:19.14#ibcon#about to write, iclass 15, count 0 2006.210.07:54:19.14#ibcon#wrote, iclass 15, count 0 2006.210.07:54:19.14#ibcon#about to read 3, iclass 15, count 0 2006.210.07:54:19.16#ibcon#read 3, iclass 15, count 0 2006.210.07:54:19.16#ibcon#about to read 4, iclass 15, count 0 2006.210.07:54:19.16#ibcon#read 4, iclass 15, count 0 2006.210.07:54:19.16#ibcon#about to read 5, iclass 15, count 0 2006.210.07:54:19.16#ibcon#read 5, iclass 15, count 0 2006.210.07:54:19.16#ibcon#about to read 6, iclass 15, count 0 2006.210.07:54:19.16#ibcon#read 6, iclass 15, count 0 2006.210.07:54:19.16#ibcon#end of sib2, iclass 15, count 0 2006.210.07:54:19.16#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:54:19.16#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:54:19.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:54:19.16#ibcon#*before write, iclass 15, count 0 2006.210.07:54:19.16#ibcon#enter sib2, iclass 15, count 0 2006.210.07:54:19.16#ibcon#flushed, iclass 15, count 0 2006.210.07:54:19.16#ibcon#about to write, iclass 15, count 0 2006.210.07:54:19.16#ibcon#wrote, iclass 15, count 0 2006.210.07:54:19.16#ibcon#about to read 3, iclass 15, count 0 2006.210.07:54:19.20#ibcon#read 3, iclass 15, count 0 2006.210.07:54:19.20#ibcon#about to read 4, iclass 15, count 0 2006.210.07:54:19.20#ibcon#read 4, iclass 15, count 0 2006.210.07:54:19.20#ibcon#about to read 5, iclass 15, count 0 2006.210.07:54:19.20#ibcon#read 5, iclass 15, count 0 2006.210.07:54:19.20#ibcon#about to read 6, iclass 15, count 0 2006.210.07:54:19.20#ibcon#read 6, iclass 15, count 0 2006.210.07:54:19.20#ibcon#end of sib2, iclass 15, count 0 2006.210.07:54:19.20#ibcon#*after write, iclass 15, count 0 2006.210.07:54:19.20#ibcon#*before return 0, iclass 15, count 0 2006.210.07:54:19.20#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:19.20#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:19.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:54:19.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:54:19.20$vc4f8/va=6,6 2006.210.07:54:19.20#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.07:54:19.20#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.07:54:19.20#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:19.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:19.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:19.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:19.26#ibcon#enter wrdev, iclass 17, count 2 2006.210.07:54:19.26#ibcon#first serial, iclass 17, count 2 2006.210.07:54:19.26#ibcon#enter sib2, iclass 17, count 2 2006.210.07:54:19.26#ibcon#flushed, iclass 17, count 2 2006.210.07:54:19.26#ibcon#about to write, iclass 17, count 2 2006.210.07:54:19.26#ibcon#wrote, iclass 17, count 2 2006.210.07:54:19.26#ibcon#about to read 3, iclass 17, count 2 2006.210.07:54:19.28#ibcon#read 3, iclass 17, count 2 2006.210.07:54:19.28#ibcon#about to read 4, iclass 17, count 2 2006.210.07:54:19.28#ibcon#read 4, iclass 17, count 2 2006.210.07:54:19.28#ibcon#about to read 5, iclass 17, count 2 2006.210.07:54:19.28#ibcon#read 5, iclass 17, count 2 2006.210.07:54:19.28#ibcon#about to read 6, iclass 17, count 2 2006.210.07:54:19.28#ibcon#read 6, iclass 17, count 2 2006.210.07:54:19.28#ibcon#end of sib2, iclass 17, count 2 2006.210.07:54:19.28#ibcon#*mode == 0, iclass 17, count 2 2006.210.07:54:19.28#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.07:54:19.28#ibcon#[25=AT06-06\r\n] 2006.210.07:54:19.28#ibcon#*before write, iclass 17, count 2 2006.210.07:54:19.28#ibcon#enter sib2, iclass 17, count 2 2006.210.07:54:19.28#ibcon#flushed, iclass 17, count 2 2006.210.07:54:19.28#ibcon#about to write, iclass 17, count 2 2006.210.07:54:19.28#ibcon#wrote, iclass 17, count 2 2006.210.07:54:19.28#ibcon#about to read 3, iclass 17, count 2 2006.210.07:54:19.31#ibcon#read 3, iclass 17, count 2 2006.210.07:54:19.31#ibcon#about to read 4, iclass 17, count 2 2006.210.07:54:19.31#ibcon#read 4, iclass 17, count 2 2006.210.07:54:19.31#ibcon#about to read 5, iclass 17, count 2 2006.210.07:54:19.31#ibcon#read 5, iclass 17, count 2 2006.210.07:54:19.31#ibcon#about to read 6, iclass 17, count 2 2006.210.07:54:19.31#ibcon#read 6, iclass 17, count 2 2006.210.07:54:19.31#ibcon#end of sib2, iclass 17, count 2 2006.210.07:54:19.31#ibcon#*after write, iclass 17, count 2 2006.210.07:54:19.31#ibcon#*before return 0, iclass 17, count 2 2006.210.07:54:19.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:19.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:19.31#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.07:54:19.31#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:19.31#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:19.43#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:19.43#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:19.43#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:54:19.43#ibcon#first serial, iclass 17, count 0 2006.210.07:54:19.43#ibcon#enter sib2, iclass 17, count 0 2006.210.07:54:19.43#ibcon#flushed, iclass 17, count 0 2006.210.07:54:19.43#ibcon#about to write, iclass 17, count 0 2006.210.07:54:19.43#ibcon#wrote, iclass 17, count 0 2006.210.07:54:19.43#ibcon#about to read 3, iclass 17, count 0 2006.210.07:54:19.45#ibcon#read 3, iclass 17, count 0 2006.210.07:54:19.45#ibcon#about to read 4, iclass 17, count 0 2006.210.07:54:19.45#ibcon#read 4, iclass 17, count 0 2006.210.07:54:19.45#ibcon#about to read 5, iclass 17, count 0 2006.210.07:54:19.45#ibcon#read 5, iclass 17, count 0 2006.210.07:54:19.45#ibcon#about to read 6, iclass 17, count 0 2006.210.07:54:19.45#ibcon#read 6, iclass 17, count 0 2006.210.07:54:19.45#ibcon#end of sib2, iclass 17, count 0 2006.210.07:54:19.45#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:54:19.45#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:54:19.45#ibcon#[25=USB\r\n] 2006.210.07:54:19.45#ibcon#*before write, iclass 17, count 0 2006.210.07:54:19.45#ibcon#enter sib2, iclass 17, count 0 2006.210.07:54:19.45#ibcon#flushed, iclass 17, count 0 2006.210.07:54:19.45#ibcon#about to write, iclass 17, count 0 2006.210.07:54:19.45#ibcon#wrote, iclass 17, count 0 2006.210.07:54:19.45#ibcon#about to read 3, iclass 17, count 0 2006.210.07:54:19.48#ibcon#read 3, iclass 17, count 0 2006.210.07:54:19.48#ibcon#about to read 4, iclass 17, count 0 2006.210.07:54:19.48#ibcon#read 4, iclass 17, count 0 2006.210.07:54:19.48#ibcon#about to read 5, iclass 17, count 0 2006.210.07:54:19.48#ibcon#read 5, iclass 17, count 0 2006.210.07:54:19.48#ibcon#about to read 6, iclass 17, count 0 2006.210.07:54:19.48#ibcon#read 6, iclass 17, count 0 2006.210.07:54:19.48#ibcon#end of sib2, iclass 17, count 0 2006.210.07:54:19.48#ibcon#*after write, iclass 17, count 0 2006.210.07:54:19.48#ibcon#*before return 0, iclass 17, count 0 2006.210.07:54:19.48#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:19.48#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:19.48#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:54:19.48#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:54:19.48$vc4f8/valo=7,832.99 2006.210.07:54:19.48#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.07:54:19.48#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.07:54:19.48#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:19.48#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:19.48#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:19.48#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:19.48#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:54:19.48#ibcon#first serial, iclass 19, count 0 2006.210.07:54:19.48#ibcon#enter sib2, iclass 19, count 0 2006.210.07:54:19.48#ibcon#flushed, iclass 19, count 0 2006.210.07:54:19.48#ibcon#about to write, iclass 19, count 0 2006.210.07:54:19.48#ibcon#wrote, iclass 19, count 0 2006.210.07:54:19.48#ibcon#about to read 3, iclass 19, count 0 2006.210.07:54:19.50#ibcon#read 3, iclass 19, count 0 2006.210.07:54:19.50#ibcon#about to read 4, iclass 19, count 0 2006.210.07:54:19.50#ibcon#read 4, iclass 19, count 0 2006.210.07:54:19.50#ibcon#about to read 5, iclass 19, count 0 2006.210.07:54:19.50#ibcon#read 5, iclass 19, count 0 2006.210.07:54:19.50#ibcon#about to read 6, iclass 19, count 0 2006.210.07:54:19.50#ibcon#read 6, iclass 19, count 0 2006.210.07:54:19.50#ibcon#end of sib2, iclass 19, count 0 2006.210.07:54:19.50#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:54:19.50#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:54:19.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:54:19.50#ibcon#*before write, iclass 19, count 0 2006.210.07:54:19.50#ibcon#enter sib2, iclass 19, count 0 2006.210.07:54:19.50#ibcon#flushed, iclass 19, count 0 2006.210.07:54:19.50#ibcon#about to write, iclass 19, count 0 2006.210.07:54:19.50#ibcon#wrote, iclass 19, count 0 2006.210.07:54:19.50#ibcon#about to read 3, iclass 19, count 0 2006.210.07:54:19.54#ibcon#read 3, iclass 19, count 0 2006.210.07:54:19.54#ibcon#about to read 4, iclass 19, count 0 2006.210.07:54:19.54#ibcon#read 4, iclass 19, count 0 2006.210.07:54:19.54#ibcon#about to read 5, iclass 19, count 0 2006.210.07:54:19.54#ibcon#read 5, iclass 19, count 0 2006.210.07:54:19.54#ibcon#about to read 6, iclass 19, count 0 2006.210.07:54:19.54#ibcon#read 6, iclass 19, count 0 2006.210.07:54:19.54#ibcon#end of sib2, iclass 19, count 0 2006.210.07:54:19.54#ibcon#*after write, iclass 19, count 0 2006.210.07:54:19.54#ibcon#*before return 0, iclass 19, count 0 2006.210.07:54:19.54#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:19.54#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:19.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:54:19.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:54:19.54$vc4f8/va=7,6 2006.210.07:54:19.54#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.07:54:19.54#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.07:54:19.54#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:19.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:54:19.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:54:19.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:54:19.60#ibcon#enter wrdev, iclass 21, count 2 2006.210.07:54:19.60#ibcon#first serial, iclass 21, count 2 2006.210.07:54:19.60#ibcon#enter sib2, iclass 21, count 2 2006.210.07:54:19.60#ibcon#flushed, iclass 21, count 2 2006.210.07:54:19.60#ibcon#about to write, iclass 21, count 2 2006.210.07:54:19.60#ibcon#wrote, iclass 21, count 2 2006.210.07:54:19.60#ibcon#about to read 3, iclass 21, count 2 2006.210.07:54:19.62#ibcon#read 3, iclass 21, count 2 2006.210.07:54:19.62#ibcon#about to read 4, iclass 21, count 2 2006.210.07:54:19.62#ibcon#read 4, iclass 21, count 2 2006.210.07:54:19.62#ibcon#about to read 5, iclass 21, count 2 2006.210.07:54:19.62#ibcon#read 5, iclass 21, count 2 2006.210.07:54:19.62#ibcon#about to read 6, iclass 21, count 2 2006.210.07:54:19.62#ibcon#read 6, iclass 21, count 2 2006.210.07:54:19.62#ibcon#end of sib2, iclass 21, count 2 2006.210.07:54:19.62#ibcon#*mode == 0, iclass 21, count 2 2006.210.07:54:19.62#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.07:54:19.62#ibcon#[25=AT07-06\r\n] 2006.210.07:54:19.62#ibcon#*before write, iclass 21, count 2 2006.210.07:54:19.62#ibcon#enter sib2, iclass 21, count 2 2006.210.07:54:19.62#ibcon#flushed, iclass 21, count 2 2006.210.07:54:19.62#ibcon#about to write, iclass 21, count 2 2006.210.07:54:19.62#ibcon#wrote, iclass 21, count 2 2006.210.07:54:19.62#ibcon#about to read 3, iclass 21, count 2 2006.210.07:54:19.65#ibcon#read 3, iclass 21, count 2 2006.210.07:54:19.65#ibcon#about to read 4, iclass 21, count 2 2006.210.07:54:19.65#ibcon#read 4, iclass 21, count 2 2006.210.07:54:19.65#ibcon#about to read 5, iclass 21, count 2 2006.210.07:54:19.65#ibcon#read 5, iclass 21, count 2 2006.210.07:54:19.65#ibcon#about to read 6, iclass 21, count 2 2006.210.07:54:19.65#ibcon#read 6, iclass 21, count 2 2006.210.07:54:19.65#ibcon#end of sib2, iclass 21, count 2 2006.210.07:54:19.65#ibcon#*after write, iclass 21, count 2 2006.210.07:54:19.65#ibcon#*before return 0, iclass 21, count 2 2006.210.07:54:19.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:54:19.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.07:54:19.65#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.07:54:19.65#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:19.65#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:54:19.77#abcon#<5=/06 2.2 6.5 30.59 761006.3\r\n> 2006.210.07:54:19.77#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:54:19.77#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:54:19.77#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:54:19.77#ibcon#first serial, iclass 21, count 0 2006.210.07:54:19.77#ibcon#enter sib2, iclass 21, count 0 2006.210.07:54:19.77#ibcon#flushed, iclass 21, count 0 2006.210.07:54:19.77#ibcon#about to write, iclass 21, count 0 2006.210.07:54:19.77#ibcon#wrote, iclass 21, count 0 2006.210.07:54:19.77#ibcon#about to read 3, iclass 21, count 0 2006.210.07:54:19.79#ibcon#read 3, iclass 21, count 0 2006.210.07:54:19.79#ibcon#about to read 4, iclass 21, count 0 2006.210.07:54:19.79#ibcon#read 4, iclass 21, count 0 2006.210.07:54:19.79#ibcon#about to read 5, iclass 21, count 0 2006.210.07:54:19.79#ibcon#read 5, iclass 21, count 0 2006.210.07:54:19.79#ibcon#about to read 6, iclass 21, count 0 2006.210.07:54:19.79#ibcon#read 6, iclass 21, count 0 2006.210.07:54:19.79#ibcon#end of sib2, iclass 21, count 0 2006.210.07:54:19.79#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:54:19.79#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:54:19.79#ibcon#[25=USB\r\n] 2006.210.07:54:19.79#ibcon#*before write, iclass 21, count 0 2006.210.07:54:19.79#ibcon#enter sib2, iclass 21, count 0 2006.210.07:54:19.79#ibcon#flushed, iclass 21, count 0 2006.210.07:54:19.79#ibcon#about to write, iclass 21, count 0 2006.210.07:54:19.79#ibcon#wrote, iclass 21, count 0 2006.210.07:54:19.79#ibcon#about to read 3, iclass 21, count 0 2006.210.07:54:19.79#abcon#{5=INTERFACE CLEAR} 2006.210.07:54:19.82#ibcon#read 3, iclass 21, count 0 2006.210.07:54:19.82#ibcon#about to read 4, iclass 21, count 0 2006.210.07:54:19.82#ibcon#read 4, iclass 21, count 0 2006.210.07:54:19.82#ibcon#about to read 5, iclass 21, count 0 2006.210.07:54:19.82#ibcon#read 5, iclass 21, count 0 2006.210.07:54:19.82#ibcon#about to read 6, iclass 21, count 0 2006.210.07:54:19.82#ibcon#read 6, iclass 21, count 0 2006.210.07:54:19.82#ibcon#end of sib2, iclass 21, count 0 2006.210.07:54:19.82#ibcon#*after write, iclass 21, count 0 2006.210.07:54:19.82#ibcon#*before return 0, iclass 21, count 0 2006.210.07:54:19.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:54:19.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.07:54:19.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:54:19.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:54:19.82$vc4f8/valo=8,852.99 2006.210.07:54:19.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.07:54:19.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.07:54:19.82#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:19.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:54:19.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:54:19.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:54:19.82#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:54:19.82#ibcon#first serial, iclass 26, count 0 2006.210.07:54:19.82#ibcon#enter sib2, iclass 26, count 0 2006.210.07:54:19.82#ibcon#flushed, iclass 26, count 0 2006.210.07:54:19.82#ibcon#about to write, iclass 26, count 0 2006.210.07:54:19.82#ibcon#wrote, iclass 26, count 0 2006.210.07:54:19.82#ibcon#about to read 3, iclass 26, count 0 2006.210.07:54:19.84#ibcon#read 3, iclass 26, count 0 2006.210.07:54:19.84#ibcon#about to read 4, iclass 26, count 0 2006.210.07:54:19.84#ibcon#read 4, iclass 26, count 0 2006.210.07:54:19.84#ibcon#about to read 5, iclass 26, count 0 2006.210.07:54:19.84#ibcon#read 5, iclass 26, count 0 2006.210.07:54:19.84#ibcon#about to read 6, iclass 26, count 0 2006.210.07:54:19.84#ibcon#read 6, iclass 26, count 0 2006.210.07:54:19.84#ibcon#end of sib2, iclass 26, count 0 2006.210.07:54:19.84#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:54:19.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:54:19.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:54:19.84#ibcon#*before write, iclass 26, count 0 2006.210.07:54:19.84#ibcon#enter sib2, iclass 26, count 0 2006.210.07:54:19.84#ibcon#flushed, iclass 26, count 0 2006.210.07:54:19.84#ibcon#about to write, iclass 26, count 0 2006.210.07:54:19.84#ibcon#wrote, iclass 26, count 0 2006.210.07:54:19.84#ibcon#about to read 3, iclass 26, count 0 2006.210.07:54:19.85#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:54:19.88#ibcon#read 3, iclass 26, count 0 2006.210.07:54:19.88#ibcon#about to read 4, iclass 26, count 0 2006.210.07:54:19.88#ibcon#read 4, iclass 26, count 0 2006.210.07:54:19.88#ibcon#about to read 5, iclass 26, count 0 2006.210.07:54:19.88#ibcon#read 5, iclass 26, count 0 2006.210.07:54:19.88#ibcon#about to read 6, iclass 26, count 0 2006.210.07:54:19.88#ibcon#read 6, iclass 26, count 0 2006.210.07:54:19.88#ibcon#end of sib2, iclass 26, count 0 2006.210.07:54:19.88#ibcon#*after write, iclass 26, count 0 2006.210.07:54:19.88#ibcon#*before return 0, iclass 26, count 0 2006.210.07:54:19.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:54:19.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.07:54:19.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:54:19.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:54:19.88$vc4f8/va=8,7 2006.210.07:54:19.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.07:54:19.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.07:54:19.88#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:19.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:54:19.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:54:19.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:54:19.94#ibcon#enter wrdev, iclass 29, count 2 2006.210.07:54:19.94#ibcon#first serial, iclass 29, count 2 2006.210.07:54:19.94#ibcon#enter sib2, iclass 29, count 2 2006.210.07:54:19.94#ibcon#flushed, iclass 29, count 2 2006.210.07:54:19.94#ibcon#about to write, iclass 29, count 2 2006.210.07:54:19.94#ibcon#wrote, iclass 29, count 2 2006.210.07:54:19.94#ibcon#about to read 3, iclass 29, count 2 2006.210.07:54:19.96#ibcon#read 3, iclass 29, count 2 2006.210.07:54:19.96#ibcon#about to read 4, iclass 29, count 2 2006.210.07:54:19.96#ibcon#read 4, iclass 29, count 2 2006.210.07:54:19.96#ibcon#about to read 5, iclass 29, count 2 2006.210.07:54:19.96#ibcon#read 5, iclass 29, count 2 2006.210.07:54:19.96#ibcon#about to read 6, iclass 29, count 2 2006.210.07:54:19.96#ibcon#read 6, iclass 29, count 2 2006.210.07:54:19.96#ibcon#end of sib2, iclass 29, count 2 2006.210.07:54:19.96#ibcon#*mode == 0, iclass 29, count 2 2006.210.07:54:19.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.07:54:19.96#ibcon#[25=AT08-07\r\n] 2006.210.07:54:19.96#ibcon#*before write, iclass 29, count 2 2006.210.07:54:19.96#ibcon#enter sib2, iclass 29, count 2 2006.210.07:54:19.96#ibcon#flushed, iclass 29, count 2 2006.210.07:54:19.96#ibcon#about to write, iclass 29, count 2 2006.210.07:54:19.96#ibcon#wrote, iclass 29, count 2 2006.210.07:54:19.96#ibcon#about to read 3, iclass 29, count 2 2006.210.07:54:19.99#ibcon#read 3, iclass 29, count 2 2006.210.07:54:19.99#ibcon#about to read 4, iclass 29, count 2 2006.210.07:54:19.99#ibcon#read 4, iclass 29, count 2 2006.210.07:54:19.99#ibcon#about to read 5, iclass 29, count 2 2006.210.07:54:19.99#ibcon#read 5, iclass 29, count 2 2006.210.07:54:19.99#ibcon#about to read 6, iclass 29, count 2 2006.210.07:54:19.99#ibcon#read 6, iclass 29, count 2 2006.210.07:54:19.99#ibcon#end of sib2, iclass 29, count 2 2006.210.07:54:19.99#ibcon#*after write, iclass 29, count 2 2006.210.07:54:19.99#ibcon#*before return 0, iclass 29, count 2 2006.210.07:54:19.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:54:19.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.07:54:19.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.07:54:19.99#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:19.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:54:20.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:54:20.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:54:20.11#ibcon#enter wrdev, iclass 29, count 0 2006.210.07:54:20.11#ibcon#first serial, iclass 29, count 0 2006.210.07:54:20.11#ibcon#enter sib2, iclass 29, count 0 2006.210.07:54:20.11#ibcon#flushed, iclass 29, count 0 2006.210.07:54:20.11#ibcon#about to write, iclass 29, count 0 2006.210.07:54:20.11#ibcon#wrote, iclass 29, count 0 2006.210.07:54:20.11#ibcon#about to read 3, iclass 29, count 0 2006.210.07:54:20.13#ibcon#read 3, iclass 29, count 0 2006.210.07:54:20.13#ibcon#about to read 4, iclass 29, count 0 2006.210.07:54:20.13#ibcon#read 4, iclass 29, count 0 2006.210.07:54:20.13#ibcon#about to read 5, iclass 29, count 0 2006.210.07:54:20.13#ibcon#read 5, iclass 29, count 0 2006.210.07:54:20.13#ibcon#about to read 6, iclass 29, count 0 2006.210.07:54:20.13#ibcon#read 6, iclass 29, count 0 2006.210.07:54:20.13#ibcon#end of sib2, iclass 29, count 0 2006.210.07:54:20.13#ibcon#*mode == 0, iclass 29, count 0 2006.210.07:54:20.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.07:54:20.13#ibcon#[25=USB\r\n] 2006.210.07:54:20.13#ibcon#*before write, iclass 29, count 0 2006.210.07:54:20.13#ibcon#enter sib2, iclass 29, count 0 2006.210.07:54:20.13#ibcon#flushed, iclass 29, count 0 2006.210.07:54:20.13#ibcon#about to write, iclass 29, count 0 2006.210.07:54:20.13#ibcon#wrote, iclass 29, count 0 2006.210.07:54:20.13#ibcon#about to read 3, iclass 29, count 0 2006.210.07:54:20.16#ibcon#read 3, iclass 29, count 0 2006.210.07:54:20.16#ibcon#about to read 4, iclass 29, count 0 2006.210.07:54:20.16#ibcon#read 4, iclass 29, count 0 2006.210.07:54:20.16#ibcon#about to read 5, iclass 29, count 0 2006.210.07:54:20.16#ibcon#read 5, iclass 29, count 0 2006.210.07:54:20.16#ibcon#about to read 6, iclass 29, count 0 2006.210.07:54:20.16#ibcon#read 6, iclass 29, count 0 2006.210.07:54:20.16#ibcon#end of sib2, iclass 29, count 0 2006.210.07:54:20.16#ibcon#*after write, iclass 29, count 0 2006.210.07:54:20.16#ibcon#*before return 0, iclass 29, count 0 2006.210.07:54:20.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:54:20.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.07:54:20.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.07:54:20.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.07:54:20.16$vc4f8/vblo=1,632.99 2006.210.07:54:20.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.07:54:20.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.07:54:20.16#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:20.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:20.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:20.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:20.16#ibcon#enter wrdev, iclass 31, count 0 2006.210.07:54:20.16#ibcon#first serial, iclass 31, count 0 2006.210.07:54:20.16#ibcon#enter sib2, iclass 31, count 0 2006.210.07:54:20.16#ibcon#flushed, iclass 31, count 0 2006.210.07:54:20.16#ibcon#about to write, iclass 31, count 0 2006.210.07:54:20.16#ibcon#wrote, iclass 31, count 0 2006.210.07:54:20.16#ibcon#about to read 3, iclass 31, count 0 2006.210.07:54:20.18#ibcon#read 3, iclass 31, count 0 2006.210.07:54:20.18#ibcon#about to read 4, iclass 31, count 0 2006.210.07:54:20.18#ibcon#read 4, iclass 31, count 0 2006.210.07:54:20.18#ibcon#about to read 5, iclass 31, count 0 2006.210.07:54:20.18#ibcon#read 5, iclass 31, count 0 2006.210.07:54:20.18#ibcon#about to read 6, iclass 31, count 0 2006.210.07:54:20.18#ibcon#read 6, iclass 31, count 0 2006.210.07:54:20.18#ibcon#end of sib2, iclass 31, count 0 2006.210.07:54:20.18#ibcon#*mode == 0, iclass 31, count 0 2006.210.07:54:20.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.07:54:20.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:54:20.18#ibcon#*before write, iclass 31, count 0 2006.210.07:54:20.18#ibcon#enter sib2, iclass 31, count 0 2006.210.07:54:20.18#ibcon#flushed, iclass 31, count 0 2006.210.07:54:20.18#ibcon#about to write, iclass 31, count 0 2006.210.07:54:20.18#ibcon#wrote, iclass 31, count 0 2006.210.07:54:20.18#ibcon#about to read 3, iclass 31, count 0 2006.210.07:54:20.22#ibcon#read 3, iclass 31, count 0 2006.210.07:54:20.22#ibcon#about to read 4, iclass 31, count 0 2006.210.07:54:20.22#ibcon#read 4, iclass 31, count 0 2006.210.07:54:20.22#ibcon#about to read 5, iclass 31, count 0 2006.210.07:54:20.22#ibcon#read 5, iclass 31, count 0 2006.210.07:54:20.22#ibcon#about to read 6, iclass 31, count 0 2006.210.07:54:20.22#ibcon#read 6, iclass 31, count 0 2006.210.07:54:20.22#ibcon#end of sib2, iclass 31, count 0 2006.210.07:54:20.22#ibcon#*after write, iclass 31, count 0 2006.210.07:54:20.22#ibcon#*before return 0, iclass 31, count 0 2006.210.07:54:20.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:20.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.07:54:20.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.07:54:20.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.07:54:20.22$vc4f8/vb=1,4 2006.210.07:54:20.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.07:54:20.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.07:54:20.22#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:20.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:20.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:20.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:20.22#ibcon#enter wrdev, iclass 33, count 2 2006.210.07:54:20.22#ibcon#first serial, iclass 33, count 2 2006.210.07:54:20.22#ibcon#enter sib2, iclass 33, count 2 2006.210.07:54:20.22#ibcon#flushed, iclass 33, count 2 2006.210.07:54:20.22#ibcon#about to write, iclass 33, count 2 2006.210.07:54:20.22#ibcon#wrote, iclass 33, count 2 2006.210.07:54:20.22#ibcon#about to read 3, iclass 33, count 2 2006.210.07:54:20.24#ibcon#read 3, iclass 33, count 2 2006.210.07:54:20.24#ibcon#about to read 4, iclass 33, count 2 2006.210.07:54:20.24#ibcon#read 4, iclass 33, count 2 2006.210.07:54:20.24#ibcon#about to read 5, iclass 33, count 2 2006.210.07:54:20.24#ibcon#read 5, iclass 33, count 2 2006.210.07:54:20.24#ibcon#about to read 6, iclass 33, count 2 2006.210.07:54:20.24#ibcon#read 6, iclass 33, count 2 2006.210.07:54:20.24#ibcon#end of sib2, iclass 33, count 2 2006.210.07:54:20.24#ibcon#*mode == 0, iclass 33, count 2 2006.210.07:54:20.24#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.07:54:20.24#ibcon#[27=AT01-04\r\n] 2006.210.07:54:20.24#ibcon#*before write, iclass 33, count 2 2006.210.07:54:20.24#ibcon#enter sib2, iclass 33, count 2 2006.210.07:54:20.24#ibcon#flushed, iclass 33, count 2 2006.210.07:54:20.24#ibcon#about to write, iclass 33, count 2 2006.210.07:54:20.24#ibcon#wrote, iclass 33, count 2 2006.210.07:54:20.24#ibcon#about to read 3, iclass 33, count 2 2006.210.07:54:20.27#ibcon#read 3, iclass 33, count 2 2006.210.07:54:20.27#ibcon#about to read 4, iclass 33, count 2 2006.210.07:54:20.27#ibcon#read 4, iclass 33, count 2 2006.210.07:54:20.27#ibcon#about to read 5, iclass 33, count 2 2006.210.07:54:20.27#ibcon#read 5, iclass 33, count 2 2006.210.07:54:20.27#ibcon#about to read 6, iclass 33, count 2 2006.210.07:54:20.27#ibcon#read 6, iclass 33, count 2 2006.210.07:54:20.27#ibcon#end of sib2, iclass 33, count 2 2006.210.07:54:20.27#ibcon#*after write, iclass 33, count 2 2006.210.07:54:20.27#ibcon#*before return 0, iclass 33, count 2 2006.210.07:54:20.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:20.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.07:54:20.27#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.07:54:20.27#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:20.27#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:20.39#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:20.39#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:20.39#ibcon#enter wrdev, iclass 33, count 0 2006.210.07:54:20.39#ibcon#first serial, iclass 33, count 0 2006.210.07:54:20.39#ibcon#enter sib2, iclass 33, count 0 2006.210.07:54:20.39#ibcon#flushed, iclass 33, count 0 2006.210.07:54:20.39#ibcon#about to write, iclass 33, count 0 2006.210.07:54:20.39#ibcon#wrote, iclass 33, count 0 2006.210.07:54:20.39#ibcon#about to read 3, iclass 33, count 0 2006.210.07:54:20.41#ibcon#read 3, iclass 33, count 0 2006.210.07:54:20.41#ibcon#about to read 4, iclass 33, count 0 2006.210.07:54:20.41#ibcon#read 4, iclass 33, count 0 2006.210.07:54:20.41#ibcon#about to read 5, iclass 33, count 0 2006.210.07:54:20.41#ibcon#read 5, iclass 33, count 0 2006.210.07:54:20.41#ibcon#about to read 6, iclass 33, count 0 2006.210.07:54:20.41#ibcon#read 6, iclass 33, count 0 2006.210.07:54:20.41#ibcon#end of sib2, iclass 33, count 0 2006.210.07:54:20.41#ibcon#*mode == 0, iclass 33, count 0 2006.210.07:54:20.41#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.07:54:20.41#ibcon#[27=USB\r\n] 2006.210.07:54:20.41#ibcon#*before write, iclass 33, count 0 2006.210.07:54:20.41#ibcon#enter sib2, iclass 33, count 0 2006.210.07:54:20.41#ibcon#flushed, iclass 33, count 0 2006.210.07:54:20.41#ibcon#about to write, iclass 33, count 0 2006.210.07:54:20.41#ibcon#wrote, iclass 33, count 0 2006.210.07:54:20.41#ibcon#about to read 3, iclass 33, count 0 2006.210.07:54:20.44#ibcon#read 3, iclass 33, count 0 2006.210.07:54:20.44#ibcon#about to read 4, iclass 33, count 0 2006.210.07:54:20.44#ibcon#read 4, iclass 33, count 0 2006.210.07:54:20.44#ibcon#about to read 5, iclass 33, count 0 2006.210.07:54:20.44#ibcon#read 5, iclass 33, count 0 2006.210.07:54:20.44#ibcon#about to read 6, iclass 33, count 0 2006.210.07:54:20.44#ibcon#read 6, iclass 33, count 0 2006.210.07:54:20.44#ibcon#end of sib2, iclass 33, count 0 2006.210.07:54:20.44#ibcon#*after write, iclass 33, count 0 2006.210.07:54:20.44#ibcon#*before return 0, iclass 33, count 0 2006.210.07:54:20.44#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:20.44#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.07:54:20.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.07:54:20.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.07:54:20.44$vc4f8/vblo=2,640.99 2006.210.07:54:20.44#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.07:54:20.44#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.07:54:20.44#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:20.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:20.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:20.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:20.44#ibcon#enter wrdev, iclass 35, count 0 2006.210.07:54:20.44#ibcon#first serial, iclass 35, count 0 2006.210.07:54:20.44#ibcon#enter sib2, iclass 35, count 0 2006.210.07:54:20.44#ibcon#flushed, iclass 35, count 0 2006.210.07:54:20.44#ibcon#about to write, iclass 35, count 0 2006.210.07:54:20.44#ibcon#wrote, iclass 35, count 0 2006.210.07:54:20.44#ibcon#about to read 3, iclass 35, count 0 2006.210.07:54:20.46#ibcon#read 3, iclass 35, count 0 2006.210.07:54:20.46#ibcon#about to read 4, iclass 35, count 0 2006.210.07:54:20.46#ibcon#read 4, iclass 35, count 0 2006.210.07:54:20.46#ibcon#about to read 5, iclass 35, count 0 2006.210.07:54:20.46#ibcon#read 5, iclass 35, count 0 2006.210.07:54:20.46#ibcon#about to read 6, iclass 35, count 0 2006.210.07:54:20.46#ibcon#read 6, iclass 35, count 0 2006.210.07:54:20.46#ibcon#end of sib2, iclass 35, count 0 2006.210.07:54:20.46#ibcon#*mode == 0, iclass 35, count 0 2006.210.07:54:20.46#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.07:54:20.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:54:20.46#ibcon#*before write, iclass 35, count 0 2006.210.07:54:20.46#ibcon#enter sib2, iclass 35, count 0 2006.210.07:54:20.46#ibcon#flushed, iclass 35, count 0 2006.210.07:54:20.46#ibcon#about to write, iclass 35, count 0 2006.210.07:54:20.46#ibcon#wrote, iclass 35, count 0 2006.210.07:54:20.46#ibcon#about to read 3, iclass 35, count 0 2006.210.07:54:20.50#ibcon#read 3, iclass 35, count 0 2006.210.07:54:20.50#ibcon#about to read 4, iclass 35, count 0 2006.210.07:54:20.50#ibcon#read 4, iclass 35, count 0 2006.210.07:54:20.50#ibcon#about to read 5, iclass 35, count 0 2006.210.07:54:20.50#ibcon#read 5, iclass 35, count 0 2006.210.07:54:20.50#ibcon#about to read 6, iclass 35, count 0 2006.210.07:54:20.50#ibcon#read 6, iclass 35, count 0 2006.210.07:54:20.50#ibcon#end of sib2, iclass 35, count 0 2006.210.07:54:20.50#ibcon#*after write, iclass 35, count 0 2006.210.07:54:20.50#ibcon#*before return 0, iclass 35, count 0 2006.210.07:54:20.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:20.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.07:54:20.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.07:54:20.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.07:54:20.50$vc4f8/vb=2,4 2006.210.07:54:20.50#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.07:54:20.50#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.07:54:20.50#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:20.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:20.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:20.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:20.56#ibcon#enter wrdev, iclass 37, count 2 2006.210.07:54:20.56#ibcon#first serial, iclass 37, count 2 2006.210.07:54:20.56#ibcon#enter sib2, iclass 37, count 2 2006.210.07:54:20.56#ibcon#flushed, iclass 37, count 2 2006.210.07:54:20.56#ibcon#about to write, iclass 37, count 2 2006.210.07:54:20.56#ibcon#wrote, iclass 37, count 2 2006.210.07:54:20.56#ibcon#about to read 3, iclass 37, count 2 2006.210.07:54:20.58#ibcon#read 3, iclass 37, count 2 2006.210.07:54:20.58#ibcon#about to read 4, iclass 37, count 2 2006.210.07:54:20.58#ibcon#read 4, iclass 37, count 2 2006.210.07:54:20.58#ibcon#about to read 5, iclass 37, count 2 2006.210.07:54:20.58#ibcon#read 5, iclass 37, count 2 2006.210.07:54:20.58#ibcon#about to read 6, iclass 37, count 2 2006.210.07:54:20.58#ibcon#read 6, iclass 37, count 2 2006.210.07:54:20.58#ibcon#end of sib2, iclass 37, count 2 2006.210.07:54:20.58#ibcon#*mode == 0, iclass 37, count 2 2006.210.07:54:20.58#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.07:54:20.58#ibcon#[27=AT02-04\r\n] 2006.210.07:54:20.58#ibcon#*before write, iclass 37, count 2 2006.210.07:54:20.58#ibcon#enter sib2, iclass 37, count 2 2006.210.07:54:20.58#ibcon#flushed, iclass 37, count 2 2006.210.07:54:20.58#ibcon#about to write, iclass 37, count 2 2006.210.07:54:20.58#ibcon#wrote, iclass 37, count 2 2006.210.07:54:20.58#ibcon#about to read 3, iclass 37, count 2 2006.210.07:54:20.61#ibcon#read 3, iclass 37, count 2 2006.210.07:54:20.61#ibcon#about to read 4, iclass 37, count 2 2006.210.07:54:20.61#ibcon#read 4, iclass 37, count 2 2006.210.07:54:20.61#ibcon#about to read 5, iclass 37, count 2 2006.210.07:54:20.61#ibcon#read 5, iclass 37, count 2 2006.210.07:54:20.61#ibcon#about to read 6, iclass 37, count 2 2006.210.07:54:20.61#ibcon#read 6, iclass 37, count 2 2006.210.07:54:20.61#ibcon#end of sib2, iclass 37, count 2 2006.210.07:54:20.61#ibcon#*after write, iclass 37, count 2 2006.210.07:54:20.61#ibcon#*before return 0, iclass 37, count 2 2006.210.07:54:20.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:20.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.07:54:20.61#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.07:54:20.61#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:20.61#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:20.73#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:20.73#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:20.73#ibcon#enter wrdev, iclass 37, count 0 2006.210.07:54:20.73#ibcon#first serial, iclass 37, count 0 2006.210.07:54:20.73#ibcon#enter sib2, iclass 37, count 0 2006.210.07:54:20.73#ibcon#flushed, iclass 37, count 0 2006.210.07:54:20.73#ibcon#about to write, iclass 37, count 0 2006.210.07:54:20.73#ibcon#wrote, iclass 37, count 0 2006.210.07:54:20.73#ibcon#about to read 3, iclass 37, count 0 2006.210.07:54:20.75#ibcon#read 3, iclass 37, count 0 2006.210.07:54:20.75#ibcon#about to read 4, iclass 37, count 0 2006.210.07:54:20.75#ibcon#read 4, iclass 37, count 0 2006.210.07:54:20.75#ibcon#about to read 5, iclass 37, count 0 2006.210.07:54:20.75#ibcon#read 5, iclass 37, count 0 2006.210.07:54:20.75#ibcon#about to read 6, iclass 37, count 0 2006.210.07:54:20.75#ibcon#read 6, iclass 37, count 0 2006.210.07:54:20.75#ibcon#end of sib2, iclass 37, count 0 2006.210.07:54:20.75#ibcon#*mode == 0, iclass 37, count 0 2006.210.07:54:20.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.07:54:20.75#ibcon#[27=USB\r\n] 2006.210.07:54:20.75#ibcon#*before write, iclass 37, count 0 2006.210.07:54:20.75#ibcon#enter sib2, iclass 37, count 0 2006.210.07:54:20.75#ibcon#flushed, iclass 37, count 0 2006.210.07:54:20.75#ibcon#about to write, iclass 37, count 0 2006.210.07:54:20.75#ibcon#wrote, iclass 37, count 0 2006.210.07:54:20.75#ibcon#about to read 3, iclass 37, count 0 2006.210.07:54:20.78#ibcon#read 3, iclass 37, count 0 2006.210.07:54:20.78#ibcon#about to read 4, iclass 37, count 0 2006.210.07:54:20.78#ibcon#read 4, iclass 37, count 0 2006.210.07:54:20.78#ibcon#about to read 5, iclass 37, count 0 2006.210.07:54:20.78#ibcon#read 5, iclass 37, count 0 2006.210.07:54:20.78#ibcon#about to read 6, iclass 37, count 0 2006.210.07:54:20.78#ibcon#read 6, iclass 37, count 0 2006.210.07:54:20.78#ibcon#end of sib2, iclass 37, count 0 2006.210.07:54:20.78#ibcon#*after write, iclass 37, count 0 2006.210.07:54:20.78#ibcon#*before return 0, iclass 37, count 0 2006.210.07:54:20.78#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:20.78#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.07:54:20.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.07:54:20.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.07:54:20.78$vc4f8/vblo=3,656.99 2006.210.07:54:20.78#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.07:54:20.78#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.07:54:20.78#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:20.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:20.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:20.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:20.78#ibcon#enter wrdev, iclass 39, count 0 2006.210.07:54:20.78#ibcon#first serial, iclass 39, count 0 2006.210.07:54:20.78#ibcon#enter sib2, iclass 39, count 0 2006.210.07:54:20.78#ibcon#flushed, iclass 39, count 0 2006.210.07:54:20.78#ibcon#about to write, iclass 39, count 0 2006.210.07:54:20.78#ibcon#wrote, iclass 39, count 0 2006.210.07:54:20.78#ibcon#about to read 3, iclass 39, count 0 2006.210.07:54:20.80#ibcon#read 3, iclass 39, count 0 2006.210.07:54:20.80#ibcon#about to read 4, iclass 39, count 0 2006.210.07:54:20.80#ibcon#read 4, iclass 39, count 0 2006.210.07:54:20.80#ibcon#about to read 5, iclass 39, count 0 2006.210.07:54:20.80#ibcon#read 5, iclass 39, count 0 2006.210.07:54:20.80#ibcon#about to read 6, iclass 39, count 0 2006.210.07:54:20.80#ibcon#read 6, iclass 39, count 0 2006.210.07:54:20.80#ibcon#end of sib2, iclass 39, count 0 2006.210.07:54:20.80#ibcon#*mode == 0, iclass 39, count 0 2006.210.07:54:20.80#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.07:54:20.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:54:20.80#ibcon#*before write, iclass 39, count 0 2006.210.07:54:20.80#ibcon#enter sib2, iclass 39, count 0 2006.210.07:54:20.80#ibcon#flushed, iclass 39, count 0 2006.210.07:54:20.80#ibcon#about to write, iclass 39, count 0 2006.210.07:54:20.80#ibcon#wrote, iclass 39, count 0 2006.210.07:54:20.80#ibcon#about to read 3, iclass 39, count 0 2006.210.07:54:20.84#ibcon#read 3, iclass 39, count 0 2006.210.07:54:20.84#ibcon#about to read 4, iclass 39, count 0 2006.210.07:54:20.84#ibcon#read 4, iclass 39, count 0 2006.210.07:54:20.84#ibcon#about to read 5, iclass 39, count 0 2006.210.07:54:20.84#ibcon#read 5, iclass 39, count 0 2006.210.07:54:20.84#ibcon#about to read 6, iclass 39, count 0 2006.210.07:54:20.84#ibcon#read 6, iclass 39, count 0 2006.210.07:54:20.84#ibcon#end of sib2, iclass 39, count 0 2006.210.07:54:20.84#ibcon#*after write, iclass 39, count 0 2006.210.07:54:20.84#ibcon#*before return 0, iclass 39, count 0 2006.210.07:54:20.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:20.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.07:54:20.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.07:54:20.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.07:54:20.84$vc4f8/vb=3,3 2006.210.07:54:20.84#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.07:54:20.84#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.07:54:20.84#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:20.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:20.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:20.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:20.90#ibcon#enter wrdev, iclass 3, count 2 2006.210.07:54:20.90#ibcon#first serial, iclass 3, count 2 2006.210.07:54:20.90#ibcon#enter sib2, iclass 3, count 2 2006.210.07:54:20.90#ibcon#flushed, iclass 3, count 2 2006.210.07:54:20.90#ibcon#about to write, iclass 3, count 2 2006.210.07:54:20.90#ibcon#wrote, iclass 3, count 2 2006.210.07:54:20.90#ibcon#about to read 3, iclass 3, count 2 2006.210.07:54:20.92#ibcon#read 3, iclass 3, count 2 2006.210.07:54:20.92#ibcon#about to read 4, iclass 3, count 2 2006.210.07:54:20.92#ibcon#read 4, iclass 3, count 2 2006.210.07:54:20.92#ibcon#about to read 5, iclass 3, count 2 2006.210.07:54:20.92#ibcon#read 5, iclass 3, count 2 2006.210.07:54:20.92#ibcon#about to read 6, iclass 3, count 2 2006.210.07:54:20.92#ibcon#read 6, iclass 3, count 2 2006.210.07:54:20.92#ibcon#end of sib2, iclass 3, count 2 2006.210.07:54:20.92#ibcon#*mode == 0, iclass 3, count 2 2006.210.07:54:20.92#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.07:54:20.92#ibcon#[27=AT03-03\r\n] 2006.210.07:54:20.92#ibcon#*before write, iclass 3, count 2 2006.210.07:54:20.92#ibcon#enter sib2, iclass 3, count 2 2006.210.07:54:20.92#ibcon#flushed, iclass 3, count 2 2006.210.07:54:20.92#ibcon#about to write, iclass 3, count 2 2006.210.07:54:20.92#ibcon#wrote, iclass 3, count 2 2006.210.07:54:20.92#ibcon#about to read 3, iclass 3, count 2 2006.210.07:54:20.95#ibcon#read 3, iclass 3, count 2 2006.210.07:54:20.95#ibcon#about to read 4, iclass 3, count 2 2006.210.07:54:20.95#ibcon#read 4, iclass 3, count 2 2006.210.07:54:20.95#ibcon#about to read 5, iclass 3, count 2 2006.210.07:54:20.95#ibcon#read 5, iclass 3, count 2 2006.210.07:54:20.95#ibcon#about to read 6, iclass 3, count 2 2006.210.07:54:20.95#ibcon#read 6, iclass 3, count 2 2006.210.07:54:20.95#ibcon#end of sib2, iclass 3, count 2 2006.210.07:54:20.95#ibcon#*after write, iclass 3, count 2 2006.210.07:54:20.95#ibcon#*before return 0, iclass 3, count 2 2006.210.07:54:20.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:20.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.07:54:20.95#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.07:54:20.95#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:20.95#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:21.07#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:21.07#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:21.07#ibcon#enter wrdev, iclass 3, count 0 2006.210.07:54:21.07#ibcon#first serial, iclass 3, count 0 2006.210.07:54:21.07#ibcon#enter sib2, iclass 3, count 0 2006.210.07:54:21.07#ibcon#flushed, iclass 3, count 0 2006.210.07:54:21.07#ibcon#about to write, iclass 3, count 0 2006.210.07:54:21.07#ibcon#wrote, iclass 3, count 0 2006.210.07:54:21.07#ibcon#about to read 3, iclass 3, count 0 2006.210.07:54:21.09#ibcon#read 3, iclass 3, count 0 2006.210.07:54:21.09#ibcon#about to read 4, iclass 3, count 0 2006.210.07:54:21.09#ibcon#read 4, iclass 3, count 0 2006.210.07:54:21.09#ibcon#about to read 5, iclass 3, count 0 2006.210.07:54:21.09#ibcon#read 5, iclass 3, count 0 2006.210.07:54:21.09#ibcon#about to read 6, iclass 3, count 0 2006.210.07:54:21.09#ibcon#read 6, iclass 3, count 0 2006.210.07:54:21.09#ibcon#end of sib2, iclass 3, count 0 2006.210.07:54:21.09#ibcon#*mode == 0, iclass 3, count 0 2006.210.07:54:21.09#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.07:54:21.09#ibcon#[27=USB\r\n] 2006.210.07:54:21.09#ibcon#*before write, iclass 3, count 0 2006.210.07:54:21.09#ibcon#enter sib2, iclass 3, count 0 2006.210.07:54:21.09#ibcon#flushed, iclass 3, count 0 2006.210.07:54:21.09#ibcon#about to write, iclass 3, count 0 2006.210.07:54:21.09#ibcon#wrote, iclass 3, count 0 2006.210.07:54:21.09#ibcon#about to read 3, iclass 3, count 0 2006.210.07:54:21.12#ibcon#read 3, iclass 3, count 0 2006.210.07:54:21.12#ibcon#about to read 4, iclass 3, count 0 2006.210.07:54:21.12#ibcon#read 4, iclass 3, count 0 2006.210.07:54:21.12#ibcon#about to read 5, iclass 3, count 0 2006.210.07:54:21.12#ibcon#read 5, iclass 3, count 0 2006.210.07:54:21.12#ibcon#about to read 6, iclass 3, count 0 2006.210.07:54:21.12#ibcon#read 6, iclass 3, count 0 2006.210.07:54:21.12#ibcon#end of sib2, iclass 3, count 0 2006.210.07:54:21.12#ibcon#*after write, iclass 3, count 0 2006.210.07:54:21.12#ibcon#*before return 0, iclass 3, count 0 2006.210.07:54:21.12#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:21.12#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.07:54:21.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.07:54:21.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.07:54:21.12$vc4f8/vblo=4,712.99 2006.210.07:54:21.12#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.07:54:21.12#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.07:54:21.12#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:21.12#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:21.12#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:21.12#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:21.12#ibcon#enter wrdev, iclass 5, count 0 2006.210.07:54:21.12#ibcon#first serial, iclass 5, count 0 2006.210.07:54:21.12#ibcon#enter sib2, iclass 5, count 0 2006.210.07:54:21.12#ibcon#flushed, iclass 5, count 0 2006.210.07:54:21.12#ibcon#about to write, iclass 5, count 0 2006.210.07:54:21.12#ibcon#wrote, iclass 5, count 0 2006.210.07:54:21.12#ibcon#about to read 3, iclass 5, count 0 2006.210.07:54:21.14#ibcon#read 3, iclass 5, count 0 2006.210.07:54:21.14#ibcon#about to read 4, iclass 5, count 0 2006.210.07:54:21.14#ibcon#read 4, iclass 5, count 0 2006.210.07:54:21.14#ibcon#about to read 5, iclass 5, count 0 2006.210.07:54:21.14#ibcon#read 5, iclass 5, count 0 2006.210.07:54:21.14#ibcon#about to read 6, iclass 5, count 0 2006.210.07:54:21.14#ibcon#read 6, iclass 5, count 0 2006.210.07:54:21.14#ibcon#end of sib2, iclass 5, count 0 2006.210.07:54:21.14#ibcon#*mode == 0, iclass 5, count 0 2006.210.07:54:21.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.07:54:21.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:54:21.14#ibcon#*before write, iclass 5, count 0 2006.210.07:54:21.14#ibcon#enter sib2, iclass 5, count 0 2006.210.07:54:21.14#ibcon#flushed, iclass 5, count 0 2006.210.07:54:21.14#ibcon#about to write, iclass 5, count 0 2006.210.07:54:21.14#ibcon#wrote, iclass 5, count 0 2006.210.07:54:21.14#ibcon#about to read 3, iclass 5, count 0 2006.210.07:54:21.18#ibcon#read 3, iclass 5, count 0 2006.210.07:54:21.18#ibcon#about to read 4, iclass 5, count 0 2006.210.07:54:21.18#ibcon#read 4, iclass 5, count 0 2006.210.07:54:21.18#ibcon#about to read 5, iclass 5, count 0 2006.210.07:54:21.18#ibcon#read 5, iclass 5, count 0 2006.210.07:54:21.18#ibcon#about to read 6, iclass 5, count 0 2006.210.07:54:21.18#ibcon#read 6, iclass 5, count 0 2006.210.07:54:21.18#ibcon#end of sib2, iclass 5, count 0 2006.210.07:54:21.18#ibcon#*after write, iclass 5, count 0 2006.210.07:54:21.18#ibcon#*before return 0, iclass 5, count 0 2006.210.07:54:21.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:21.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.07:54:21.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.07:54:21.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.07:54:21.18$vc4f8/vb=4,3 2006.210.07:54:21.18#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.07:54:21.18#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.07:54:21.18#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:21.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:21.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:21.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:21.24#ibcon#enter wrdev, iclass 7, count 2 2006.210.07:54:21.24#ibcon#first serial, iclass 7, count 2 2006.210.07:54:21.24#ibcon#enter sib2, iclass 7, count 2 2006.210.07:54:21.24#ibcon#flushed, iclass 7, count 2 2006.210.07:54:21.24#ibcon#about to write, iclass 7, count 2 2006.210.07:54:21.24#ibcon#wrote, iclass 7, count 2 2006.210.07:54:21.24#ibcon#about to read 3, iclass 7, count 2 2006.210.07:54:21.26#ibcon#read 3, iclass 7, count 2 2006.210.07:54:21.26#ibcon#about to read 4, iclass 7, count 2 2006.210.07:54:21.26#ibcon#read 4, iclass 7, count 2 2006.210.07:54:21.26#ibcon#about to read 5, iclass 7, count 2 2006.210.07:54:21.26#ibcon#read 5, iclass 7, count 2 2006.210.07:54:21.26#ibcon#about to read 6, iclass 7, count 2 2006.210.07:54:21.26#ibcon#read 6, iclass 7, count 2 2006.210.07:54:21.26#ibcon#end of sib2, iclass 7, count 2 2006.210.07:54:21.26#ibcon#*mode == 0, iclass 7, count 2 2006.210.07:54:21.26#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.07:54:21.26#ibcon#[27=AT04-03\r\n] 2006.210.07:54:21.26#ibcon#*before write, iclass 7, count 2 2006.210.07:54:21.26#ibcon#enter sib2, iclass 7, count 2 2006.210.07:54:21.26#ibcon#flushed, iclass 7, count 2 2006.210.07:54:21.26#ibcon#about to write, iclass 7, count 2 2006.210.07:54:21.26#ibcon#wrote, iclass 7, count 2 2006.210.07:54:21.26#ibcon#about to read 3, iclass 7, count 2 2006.210.07:54:21.29#ibcon#read 3, iclass 7, count 2 2006.210.07:54:21.29#ibcon#about to read 4, iclass 7, count 2 2006.210.07:54:21.29#ibcon#read 4, iclass 7, count 2 2006.210.07:54:21.29#ibcon#about to read 5, iclass 7, count 2 2006.210.07:54:21.29#ibcon#read 5, iclass 7, count 2 2006.210.07:54:21.29#ibcon#about to read 6, iclass 7, count 2 2006.210.07:54:21.29#ibcon#read 6, iclass 7, count 2 2006.210.07:54:21.29#ibcon#end of sib2, iclass 7, count 2 2006.210.07:54:21.29#ibcon#*after write, iclass 7, count 2 2006.210.07:54:21.29#ibcon#*before return 0, iclass 7, count 2 2006.210.07:54:21.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:21.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.07:54:21.29#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.07:54:21.29#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:21.29#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:21.41#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:21.41#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:21.41#ibcon#enter wrdev, iclass 7, count 0 2006.210.07:54:21.41#ibcon#first serial, iclass 7, count 0 2006.210.07:54:21.41#ibcon#enter sib2, iclass 7, count 0 2006.210.07:54:21.41#ibcon#flushed, iclass 7, count 0 2006.210.07:54:21.41#ibcon#about to write, iclass 7, count 0 2006.210.07:54:21.41#ibcon#wrote, iclass 7, count 0 2006.210.07:54:21.41#ibcon#about to read 3, iclass 7, count 0 2006.210.07:54:21.43#ibcon#read 3, iclass 7, count 0 2006.210.07:54:21.43#ibcon#about to read 4, iclass 7, count 0 2006.210.07:54:21.43#ibcon#read 4, iclass 7, count 0 2006.210.07:54:21.43#ibcon#about to read 5, iclass 7, count 0 2006.210.07:54:21.43#ibcon#read 5, iclass 7, count 0 2006.210.07:54:21.43#ibcon#about to read 6, iclass 7, count 0 2006.210.07:54:21.43#ibcon#read 6, iclass 7, count 0 2006.210.07:54:21.43#ibcon#end of sib2, iclass 7, count 0 2006.210.07:54:21.43#ibcon#*mode == 0, iclass 7, count 0 2006.210.07:54:21.43#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.07:54:21.43#ibcon#[27=USB\r\n] 2006.210.07:54:21.43#ibcon#*before write, iclass 7, count 0 2006.210.07:54:21.43#ibcon#enter sib2, iclass 7, count 0 2006.210.07:54:21.43#ibcon#flushed, iclass 7, count 0 2006.210.07:54:21.43#ibcon#about to write, iclass 7, count 0 2006.210.07:54:21.43#ibcon#wrote, iclass 7, count 0 2006.210.07:54:21.43#ibcon#about to read 3, iclass 7, count 0 2006.210.07:54:21.46#ibcon#read 3, iclass 7, count 0 2006.210.07:54:21.46#ibcon#about to read 4, iclass 7, count 0 2006.210.07:54:21.46#ibcon#read 4, iclass 7, count 0 2006.210.07:54:21.46#ibcon#about to read 5, iclass 7, count 0 2006.210.07:54:21.46#ibcon#read 5, iclass 7, count 0 2006.210.07:54:21.46#ibcon#about to read 6, iclass 7, count 0 2006.210.07:54:21.46#ibcon#read 6, iclass 7, count 0 2006.210.07:54:21.46#ibcon#end of sib2, iclass 7, count 0 2006.210.07:54:21.46#ibcon#*after write, iclass 7, count 0 2006.210.07:54:21.46#ibcon#*before return 0, iclass 7, count 0 2006.210.07:54:21.46#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:21.46#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.07:54:21.46#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.07:54:21.46#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.07:54:21.46$vc4f8/vblo=5,744.99 2006.210.07:54:21.46#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.07:54:21.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.07:54:21.46#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:21.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:21.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:21.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:21.46#ibcon#enter wrdev, iclass 11, count 0 2006.210.07:54:21.46#ibcon#first serial, iclass 11, count 0 2006.210.07:54:21.46#ibcon#enter sib2, iclass 11, count 0 2006.210.07:54:21.46#ibcon#flushed, iclass 11, count 0 2006.210.07:54:21.46#ibcon#about to write, iclass 11, count 0 2006.210.07:54:21.46#ibcon#wrote, iclass 11, count 0 2006.210.07:54:21.46#ibcon#about to read 3, iclass 11, count 0 2006.210.07:54:21.48#ibcon#read 3, iclass 11, count 0 2006.210.07:54:21.48#ibcon#about to read 4, iclass 11, count 0 2006.210.07:54:21.48#ibcon#read 4, iclass 11, count 0 2006.210.07:54:21.48#ibcon#about to read 5, iclass 11, count 0 2006.210.07:54:21.48#ibcon#read 5, iclass 11, count 0 2006.210.07:54:21.48#ibcon#about to read 6, iclass 11, count 0 2006.210.07:54:21.48#ibcon#read 6, iclass 11, count 0 2006.210.07:54:21.48#ibcon#end of sib2, iclass 11, count 0 2006.210.07:54:21.48#ibcon#*mode == 0, iclass 11, count 0 2006.210.07:54:21.48#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.07:54:21.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:54:21.48#ibcon#*before write, iclass 11, count 0 2006.210.07:54:21.48#ibcon#enter sib2, iclass 11, count 0 2006.210.07:54:21.48#ibcon#flushed, iclass 11, count 0 2006.210.07:54:21.48#ibcon#about to write, iclass 11, count 0 2006.210.07:54:21.48#ibcon#wrote, iclass 11, count 0 2006.210.07:54:21.48#ibcon#about to read 3, iclass 11, count 0 2006.210.07:54:21.52#ibcon#read 3, iclass 11, count 0 2006.210.07:54:21.52#ibcon#about to read 4, iclass 11, count 0 2006.210.07:54:21.52#ibcon#read 4, iclass 11, count 0 2006.210.07:54:21.52#ibcon#about to read 5, iclass 11, count 0 2006.210.07:54:21.52#ibcon#read 5, iclass 11, count 0 2006.210.07:54:21.52#ibcon#about to read 6, iclass 11, count 0 2006.210.07:54:21.52#ibcon#read 6, iclass 11, count 0 2006.210.07:54:21.52#ibcon#end of sib2, iclass 11, count 0 2006.210.07:54:21.52#ibcon#*after write, iclass 11, count 0 2006.210.07:54:21.52#ibcon#*before return 0, iclass 11, count 0 2006.210.07:54:21.52#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:21.52#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.07:54:21.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.07:54:21.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.07:54:21.52$vc4f8/vb=5,3 2006.210.07:54:21.52#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.07:54:21.52#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.07:54:21.52#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:21.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:21.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:21.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:21.58#ibcon#enter wrdev, iclass 13, count 2 2006.210.07:54:21.58#ibcon#first serial, iclass 13, count 2 2006.210.07:54:21.58#ibcon#enter sib2, iclass 13, count 2 2006.210.07:54:21.58#ibcon#flushed, iclass 13, count 2 2006.210.07:54:21.58#ibcon#about to write, iclass 13, count 2 2006.210.07:54:21.58#ibcon#wrote, iclass 13, count 2 2006.210.07:54:21.58#ibcon#about to read 3, iclass 13, count 2 2006.210.07:54:21.60#ibcon#read 3, iclass 13, count 2 2006.210.07:54:21.60#ibcon#about to read 4, iclass 13, count 2 2006.210.07:54:21.60#ibcon#read 4, iclass 13, count 2 2006.210.07:54:21.60#ibcon#about to read 5, iclass 13, count 2 2006.210.07:54:21.60#ibcon#read 5, iclass 13, count 2 2006.210.07:54:21.60#ibcon#about to read 6, iclass 13, count 2 2006.210.07:54:21.60#ibcon#read 6, iclass 13, count 2 2006.210.07:54:21.60#ibcon#end of sib2, iclass 13, count 2 2006.210.07:54:21.60#ibcon#*mode == 0, iclass 13, count 2 2006.210.07:54:21.60#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.07:54:21.60#ibcon#[27=AT05-03\r\n] 2006.210.07:54:21.60#ibcon#*before write, iclass 13, count 2 2006.210.07:54:21.60#ibcon#enter sib2, iclass 13, count 2 2006.210.07:54:21.60#ibcon#flushed, iclass 13, count 2 2006.210.07:54:21.60#ibcon#about to write, iclass 13, count 2 2006.210.07:54:21.60#ibcon#wrote, iclass 13, count 2 2006.210.07:54:21.60#ibcon#about to read 3, iclass 13, count 2 2006.210.07:54:21.63#ibcon#read 3, iclass 13, count 2 2006.210.07:54:21.63#ibcon#about to read 4, iclass 13, count 2 2006.210.07:54:21.63#ibcon#read 4, iclass 13, count 2 2006.210.07:54:21.63#ibcon#about to read 5, iclass 13, count 2 2006.210.07:54:21.63#ibcon#read 5, iclass 13, count 2 2006.210.07:54:21.63#ibcon#about to read 6, iclass 13, count 2 2006.210.07:54:21.63#ibcon#read 6, iclass 13, count 2 2006.210.07:54:21.63#ibcon#end of sib2, iclass 13, count 2 2006.210.07:54:21.63#ibcon#*after write, iclass 13, count 2 2006.210.07:54:21.63#ibcon#*before return 0, iclass 13, count 2 2006.210.07:54:21.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:21.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.07:54:21.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.07:54:21.63#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:21.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:21.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:21.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:21.75#ibcon#enter wrdev, iclass 13, count 0 2006.210.07:54:21.75#ibcon#first serial, iclass 13, count 0 2006.210.07:54:21.75#ibcon#enter sib2, iclass 13, count 0 2006.210.07:54:21.75#ibcon#flushed, iclass 13, count 0 2006.210.07:54:21.75#ibcon#about to write, iclass 13, count 0 2006.210.07:54:21.75#ibcon#wrote, iclass 13, count 0 2006.210.07:54:21.75#ibcon#about to read 3, iclass 13, count 0 2006.210.07:54:21.77#ibcon#read 3, iclass 13, count 0 2006.210.07:54:21.77#ibcon#about to read 4, iclass 13, count 0 2006.210.07:54:21.77#ibcon#read 4, iclass 13, count 0 2006.210.07:54:21.77#ibcon#about to read 5, iclass 13, count 0 2006.210.07:54:21.77#ibcon#read 5, iclass 13, count 0 2006.210.07:54:21.77#ibcon#about to read 6, iclass 13, count 0 2006.210.07:54:21.77#ibcon#read 6, iclass 13, count 0 2006.210.07:54:21.77#ibcon#end of sib2, iclass 13, count 0 2006.210.07:54:21.77#ibcon#*mode == 0, iclass 13, count 0 2006.210.07:54:21.77#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.07:54:21.77#ibcon#[27=USB\r\n] 2006.210.07:54:21.77#ibcon#*before write, iclass 13, count 0 2006.210.07:54:21.77#ibcon#enter sib2, iclass 13, count 0 2006.210.07:54:21.77#ibcon#flushed, iclass 13, count 0 2006.210.07:54:21.77#ibcon#about to write, iclass 13, count 0 2006.210.07:54:21.77#ibcon#wrote, iclass 13, count 0 2006.210.07:54:21.77#ibcon#about to read 3, iclass 13, count 0 2006.210.07:54:21.80#ibcon#read 3, iclass 13, count 0 2006.210.07:54:21.80#ibcon#about to read 4, iclass 13, count 0 2006.210.07:54:21.80#ibcon#read 4, iclass 13, count 0 2006.210.07:54:21.80#ibcon#about to read 5, iclass 13, count 0 2006.210.07:54:21.80#ibcon#read 5, iclass 13, count 0 2006.210.07:54:21.80#ibcon#about to read 6, iclass 13, count 0 2006.210.07:54:21.80#ibcon#read 6, iclass 13, count 0 2006.210.07:54:21.80#ibcon#end of sib2, iclass 13, count 0 2006.210.07:54:21.80#ibcon#*after write, iclass 13, count 0 2006.210.07:54:21.80#ibcon#*before return 0, iclass 13, count 0 2006.210.07:54:21.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:21.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.07:54:21.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.07:54:21.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.07:54:21.80$vc4f8/vblo=6,752.99 2006.210.07:54:21.80#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.07:54:21.80#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.07:54:21.80#ibcon#ireg 17 cls_cnt 0 2006.210.07:54:21.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:21.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:21.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:21.80#ibcon#enter wrdev, iclass 15, count 0 2006.210.07:54:21.80#ibcon#first serial, iclass 15, count 0 2006.210.07:54:21.80#ibcon#enter sib2, iclass 15, count 0 2006.210.07:54:21.80#ibcon#flushed, iclass 15, count 0 2006.210.07:54:21.80#ibcon#about to write, iclass 15, count 0 2006.210.07:54:21.80#ibcon#wrote, iclass 15, count 0 2006.210.07:54:21.80#ibcon#about to read 3, iclass 15, count 0 2006.210.07:54:21.82#ibcon#read 3, iclass 15, count 0 2006.210.07:54:21.82#ibcon#about to read 4, iclass 15, count 0 2006.210.07:54:21.82#ibcon#read 4, iclass 15, count 0 2006.210.07:54:21.82#ibcon#about to read 5, iclass 15, count 0 2006.210.07:54:21.82#ibcon#read 5, iclass 15, count 0 2006.210.07:54:21.82#ibcon#about to read 6, iclass 15, count 0 2006.210.07:54:21.82#ibcon#read 6, iclass 15, count 0 2006.210.07:54:21.82#ibcon#end of sib2, iclass 15, count 0 2006.210.07:54:21.82#ibcon#*mode == 0, iclass 15, count 0 2006.210.07:54:21.82#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.07:54:21.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:54:21.82#ibcon#*before write, iclass 15, count 0 2006.210.07:54:21.82#ibcon#enter sib2, iclass 15, count 0 2006.210.07:54:21.82#ibcon#flushed, iclass 15, count 0 2006.210.07:54:21.82#ibcon#about to write, iclass 15, count 0 2006.210.07:54:21.82#ibcon#wrote, iclass 15, count 0 2006.210.07:54:21.82#ibcon#about to read 3, iclass 15, count 0 2006.210.07:54:21.86#ibcon#read 3, iclass 15, count 0 2006.210.07:54:21.86#ibcon#about to read 4, iclass 15, count 0 2006.210.07:54:21.86#ibcon#read 4, iclass 15, count 0 2006.210.07:54:21.86#ibcon#about to read 5, iclass 15, count 0 2006.210.07:54:21.86#ibcon#read 5, iclass 15, count 0 2006.210.07:54:21.86#ibcon#about to read 6, iclass 15, count 0 2006.210.07:54:21.86#ibcon#read 6, iclass 15, count 0 2006.210.07:54:21.86#ibcon#end of sib2, iclass 15, count 0 2006.210.07:54:21.86#ibcon#*after write, iclass 15, count 0 2006.210.07:54:21.86#ibcon#*before return 0, iclass 15, count 0 2006.210.07:54:21.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:21.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.07:54:21.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.07:54:21.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.07:54:21.86$vc4f8/vb=6,3 2006.210.07:54:21.86#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.07:54:21.86#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.07:54:21.86#ibcon#ireg 11 cls_cnt 2 2006.210.07:54:21.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:21.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:21.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:21.92#ibcon#enter wrdev, iclass 17, count 2 2006.210.07:54:21.92#ibcon#first serial, iclass 17, count 2 2006.210.07:54:21.92#ibcon#enter sib2, iclass 17, count 2 2006.210.07:54:21.92#ibcon#flushed, iclass 17, count 2 2006.210.07:54:21.92#ibcon#about to write, iclass 17, count 2 2006.210.07:54:21.92#ibcon#wrote, iclass 17, count 2 2006.210.07:54:21.92#ibcon#about to read 3, iclass 17, count 2 2006.210.07:54:21.94#ibcon#read 3, iclass 17, count 2 2006.210.07:54:21.94#ibcon#about to read 4, iclass 17, count 2 2006.210.07:54:21.94#ibcon#read 4, iclass 17, count 2 2006.210.07:54:21.94#ibcon#about to read 5, iclass 17, count 2 2006.210.07:54:21.94#ibcon#read 5, iclass 17, count 2 2006.210.07:54:21.94#ibcon#about to read 6, iclass 17, count 2 2006.210.07:54:21.94#ibcon#read 6, iclass 17, count 2 2006.210.07:54:21.94#ibcon#end of sib2, iclass 17, count 2 2006.210.07:54:21.94#ibcon#*mode == 0, iclass 17, count 2 2006.210.07:54:21.94#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.07:54:21.94#ibcon#[27=AT06-03\r\n] 2006.210.07:54:21.94#ibcon#*before write, iclass 17, count 2 2006.210.07:54:21.94#ibcon#enter sib2, iclass 17, count 2 2006.210.07:54:21.94#ibcon#flushed, iclass 17, count 2 2006.210.07:54:21.94#ibcon#about to write, iclass 17, count 2 2006.210.07:54:21.94#ibcon#wrote, iclass 17, count 2 2006.210.07:54:21.94#ibcon#about to read 3, iclass 17, count 2 2006.210.07:54:21.97#ibcon#read 3, iclass 17, count 2 2006.210.07:54:21.97#ibcon#about to read 4, iclass 17, count 2 2006.210.07:54:21.97#ibcon#read 4, iclass 17, count 2 2006.210.07:54:21.97#ibcon#about to read 5, iclass 17, count 2 2006.210.07:54:21.97#ibcon#read 5, iclass 17, count 2 2006.210.07:54:21.97#ibcon#about to read 6, iclass 17, count 2 2006.210.07:54:21.97#ibcon#read 6, iclass 17, count 2 2006.210.07:54:21.97#ibcon#end of sib2, iclass 17, count 2 2006.210.07:54:21.97#ibcon#*after write, iclass 17, count 2 2006.210.07:54:21.97#ibcon#*before return 0, iclass 17, count 2 2006.210.07:54:21.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:21.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.07:54:21.97#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.07:54:21.97#ibcon#ireg 7 cls_cnt 0 2006.210.07:54:21.97#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:22.09#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:22.09#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:22.09#ibcon#enter wrdev, iclass 17, count 0 2006.210.07:54:22.09#ibcon#first serial, iclass 17, count 0 2006.210.07:54:22.09#ibcon#enter sib2, iclass 17, count 0 2006.210.07:54:22.09#ibcon#flushed, iclass 17, count 0 2006.210.07:54:22.09#ibcon#about to write, iclass 17, count 0 2006.210.07:54:22.09#ibcon#wrote, iclass 17, count 0 2006.210.07:54:22.09#ibcon#about to read 3, iclass 17, count 0 2006.210.07:54:22.11#ibcon#read 3, iclass 17, count 0 2006.210.07:54:22.11#ibcon#about to read 4, iclass 17, count 0 2006.210.07:54:22.11#ibcon#read 4, iclass 17, count 0 2006.210.07:54:22.11#ibcon#about to read 5, iclass 17, count 0 2006.210.07:54:22.11#ibcon#read 5, iclass 17, count 0 2006.210.07:54:22.11#ibcon#about to read 6, iclass 17, count 0 2006.210.07:54:22.11#ibcon#read 6, iclass 17, count 0 2006.210.07:54:22.11#ibcon#end of sib2, iclass 17, count 0 2006.210.07:54:22.11#ibcon#*mode == 0, iclass 17, count 0 2006.210.07:54:22.11#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.07:54:22.11#ibcon#[27=USB\r\n] 2006.210.07:54:22.11#ibcon#*before write, iclass 17, count 0 2006.210.07:54:22.11#ibcon#enter sib2, iclass 17, count 0 2006.210.07:54:22.11#ibcon#flushed, iclass 17, count 0 2006.210.07:54:22.11#ibcon#about to write, iclass 17, count 0 2006.210.07:54:22.11#ibcon#wrote, iclass 17, count 0 2006.210.07:54:22.11#ibcon#about to read 3, iclass 17, count 0 2006.210.07:54:22.14#ibcon#read 3, iclass 17, count 0 2006.210.07:54:22.14#ibcon#about to read 4, iclass 17, count 0 2006.210.07:54:22.14#ibcon#read 4, iclass 17, count 0 2006.210.07:54:22.14#ibcon#about to read 5, iclass 17, count 0 2006.210.07:54:22.14#ibcon#read 5, iclass 17, count 0 2006.210.07:54:22.14#ibcon#about to read 6, iclass 17, count 0 2006.210.07:54:22.14#ibcon#read 6, iclass 17, count 0 2006.210.07:54:22.14#ibcon#end of sib2, iclass 17, count 0 2006.210.07:54:22.14#ibcon#*after write, iclass 17, count 0 2006.210.07:54:22.14#ibcon#*before return 0, iclass 17, count 0 2006.210.07:54:22.14#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:22.14#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.07:54:22.14#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.07:54:22.14#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.07:54:22.14$vc4f8/vabw=wide 2006.210.07:54:22.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.07:54:22.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.07:54:22.14#ibcon#ireg 8 cls_cnt 0 2006.210.07:54:22.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:22.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:22.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:22.14#ibcon#enter wrdev, iclass 19, count 0 2006.210.07:54:22.14#ibcon#first serial, iclass 19, count 0 2006.210.07:54:22.14#ibcon#enter sib2, iclass 19, count 0 2006.210.07:54:22.14#ibcon#flushed, iclass 19, count 0 2006.210.07:54:22.14#ibcon#about to write, iclass 19, count 0 2006.210.07:54:22.14#ibcon#wrote, iclass 19, count 0 2006.210.07:54:22.14#ibcon#about to read 3, iclass 19, count 0 2006.210.07:54:22.16#ibcon#read 3, iclass 19, count 0 2006.210.07:54:22.16#ibcon#about to read 4, iclass 19, count 0 2006.210.07:54:22.16#ibcon#read 4, iclass 19, count 0 2006.210.07:54:22.16#ibcon#about to read 5, iclass 19, count 0 2006.210.07:54:22.16#ibcon#read 5, iclass 19, count 0 2006.210.07:54:22.16#ibcon#about to read 6, iclass 19, count 0 2006.210.07:54:22.16#ibcon#read 6, iclass 19, count 0 2006.210.07:54:22.16#ibcon#end of sib2, iclass 19, count 0 2006.210.07:54:22.16#ibcon#*mode == 0, iclass 19, count 0 2006.210.07:54:22.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.07:54:22.16#ibcon#[25=BW32\r\n] 2006.210.07:54:22.16#ibcon#*before write, iclass 19, count 0 2006.210.07:54:22.16#ibcon#enter sib2, iclass 19, count 0 2006.210.07:54:22.16#ibcon#flushed, iclass 19, count 0 2006.210.07:54:22.16#ibcon#about to write, iclass 19, count 0 2006.210.07:54:22.16#ibcon#wrote, iclass 19, count 0 2006.210.07:54:22.16#ibcon#about to read 3, iclass 19, count 0 2006.210.07:54:22.19#ibcon#read 3, iclass 19, count 0 2006.210.07:54:22.19#ibcon#about to read 4, iclass 19, count 0 2006.210.07:54:22.19#ibcon#read 4, iclass 19, count 0 2006.210.07:54:22.19#ibcon#about to read 5, iclass 19, count 0 2006.210.07:54:22.19#ibcon#read 5, iclass 19, count 0 2006.210.07:54:22.19#ibcon#about to read 6, iclass 19, count 0 2006.210.07:54:22.19#ibcon#read 6, iclass 19, count 0 2006.210.07:54:22.19#ibcon#end of sib2, iclass 19, count 0 2006.210.07:54:22.19#ibcon#*after write, iclass 19, count 0 2006.210.07:54:22.19#ibcon#*before return 0, iclass 19, count 0 2006.210.07:54:22.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:22.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.07:54:22.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.07:54:22.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.07:54:22.19$vc4f8/vbbw=wide 2006.210.07:54:22.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.07:54:22.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.07:54:22.19#ibcon#ireg 8 cls_cnt 0 2006.210.07:54:22.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:54:22.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:54:22.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:54:22.26#ibcon#enter wrdev, iclass 21, count 0 2006.210.07:54:22.26#ibcon#first serial, iclass 21, count 0 2006.210.07:54:22.26#ibcon#enter sib2, iclass 21, count 0 2006.210.07:54:22.26#ibcon#flushed, iclass 21, count 0 2006.210.07:54:22.26#ibcon#about to write, iclass 21, count 0 2006.210.07:54:22.26#ibcon#wrote, iclass 21, count 0 2006.210.07:54:22.26#ibcon#about to read 3, iclass 21, count 0 2006.210.07:54:22.28#ibcon#read 3, iclass 21, count 0 2006.210.07:54:22.28#ibcon#about to read 4, iclass 21, count 0 2006.210.07:54:22.28#ibcon#read 4, iclass 21, count 0 2006.210.07:54:22.28#ibcon#about to read 5, iclass 21, count 0 2006.210.07:54:22.28#ibcon#read 5, iclass 21, count 0 2006.210.07:54:22.28#ibcon#about to read 6, iclass 21, count 0 2006.210.07:54:22.28#ibcon#read 6, iclass 21, count 0 2006.210.07:54:22.28#ibcon#end of sib2, iclass 21, count 0 2006.210.07:54:22.28#ibcon#*mode == 0, iclass 21, count 0 2006.210.07:54:22.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.07:54:22.28#ibcon#[27=BW32\r\n] 2006.210.07:54:22.28#ibcon#*before write, iclass 21, count 0 2006.210.07:54:22.28#ibcon#enter sib2, iclass 21, count 0 2006.210.07:54:22.28#ibcon#flushed, iclass 21, count 0 2006.210.07:54:22.28#ibcon#about to write, iclass 21, count 0 2006.210.07:54:22.28#ibcon#wrote, iclass 21, count 0 2006.210.07:54:22.28#ibcon#about to read 3, iclass 21, count 0 2006.210.07:54:22.31#ibcon#read 3, iclass 21, count 0 2006.210.07:54:22.31#ibcon#about to read 4, iclass 21, count 0 2006.210.07:54:22.31#ibcon#read 4, iclass 21, count 0 2006.210.07:54:22.31#ibcon#about to read 5, iclass 21, count 0 2006.210.07:54:22.31#ibcon#read 5, iclass 21, count 0 2006.210.07:54:22.31#ibcon#about to read 6, iclass 21, count 0 2006.210.07:54:22.31#ibcon#read 6, iclass 21, count 0 2006.210.07:54:22.31#ibcon#end of sib2, iclass 21, count 0 2006.210.07:54:22.31#ibcon#*after write, iclass 21, count 0 2006.210.07:54:22.31#ibcon#*before return 0, iclass 21, count 0 2006.210.07:54:22.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:54:22.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.07:54:22.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.07:54:22.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.07:54:22.31$4f8m12a/ifd4f 2006.210.07:54:22.31$ifd4f/lo= 2006.210.07:54:22.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:54:22.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:54:22.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:54:22.31$ifd4f/patch= 2006.210.07:54:22.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:54:22.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:54:22.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:54:22.31$4f8m12a/"form=m,16.000,1:2 2006.210.07:54:22.31$4f8m12a/"tpicd 2006.210.07:54:22.31$4f8m12a/echo=off 2006.210.07:54:22.31$4f8m12a/xlog=off 2006.210.07:54:22.31:!2006.210.07:55:20 2006.210.07:54:56.14#trakl#Source acquired 2006.210.07:54:56.14#flagr#flagr/antenna,acquired 2006.210.07:55:20.00:preob 2006.210.07:55:21.14/onsource/TRACKING 2006.210.07:55:21.14:!2006.210.07:55:30 2006.210.07:55:30.00:data_valid=on 2006.210.07:55:30.00:midob 2006.210.07:55:30.14/onsource/TRACKING 2006.210.07:55:30.14/wx/30.59,1006.3,78 2006.210.07:55:30.31/cable/+6.3941E-03 2006.210.07:55:31.40/va/01,08,usb,yes,35,36 2006.210.07:55:31.40/va/02,07,usb,yes,35,36 2006.210.07:55:31.40/va/03,06,usb,yes,37,37 2006.210.07:55:31.40/va/04,07,usb,yes,36,39 2006.210.07:55:31.40/va/05,07,usb,yes,38,40 2006.210.07:55:31.40/va/06,06,usb,yes,37,37 2006.210.07:55:31.40/va/07,06,usb,yes,38,38 2006.210.07:55:31.40/va/08,07,usb,yes,36,35 2006.210.07:55:31.63/valo/01,532.99,yes,locked 2006.210.07:55:31.63/valo/02,572.99,yes,locked 2006.210.07:55:31.63/valo/03,672.99,yes,locked 2006.210.07:55:31.63/valo/04,832.99,yes,locked 2006.210.07:55:31.63/valo/05,652.99,yes,locked 2006.210.07:55:31.63/valo/06,772.99,yes,locked 2006.210.07:55:31.63/valo/07,832.99,yes,locked 2006.210.07:55:31.63/valo/08,852.99,yes,locked 2006.210.07:55:32.72/vb/01,04,usb,yes,30,29 2006.210.07:55:32.72/vb/02,04,usb,yes,32,33 2006.210.07:55:32.72/vb/03,03,usb,yes,35,40 2006.210.07:55:32.72/vb/04,03,usb,yes,36,36 2006.210.07:55:32.72/vb/05,03,usb,yes,35,39 2006.210.07:55:32.72/vb/06,03,usb,yes,35,39 2006.210.07:55:32.72/vb/07,04,usb,yes,31,31 2006.210.07:55:32.72/vb/08,03,usb,yes,35,39 2006.210.07:55:32.95/vblo/01,632.99,yes,locked 2006.210.07:55:32.95/vblo/02,640.99,yes,locked 2006.210.07:55:32.95/vblo/03,656.99,yes,locked 2006.210.07:55:32.95/vblo/04,712.99,yes,locked 2006.210.07:55:32.95/vblo/05,744.99,yes,locked 2006.210.07:55:32.95/vblo/06,752.99,yes,locked 2006.210.07:55:32.95/vblo/07,734.99,yes,locked 2006.210.07:55:32.95/vblo/08,744.99,yes,locked 2006.210.07:55:33.10/vabw/8 2006.210.07:55:33.25/vbbw/8 2006.210.07:55:33.34/xfe/off,on,12.5 2006.210.07:55:33.73/ifatt/23,28,28,28 2006.210.07:55:34.08/fmout-gps/S +4.66E-07 2006.210.07:55:34.12:!2006.210.07:56:30 2006.210.07:56:30.00:data_valid=off 2006.210.07:56:30.00:postob 2006.210.07:56:30.14/cable/+6.3926E-03 2006.210.07:56:30.14/wx/30.59,1006.3,79 2006.210.07:56:31.08/fmout-gps/S +4.67E-07 2006.210.07:56:31.08:scan_name=210-0759,k06210,60 2006.210.07:56:31.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.210.07:56:31.14#flagr#flagr/antenna,new-source 2006.210.07:56:32.14:checkk5 2006.210.07:56:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.07:56:32.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.07:56:33.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.07:56:33.52/chk_autoobs//k5ts4/ autoobs is running! 2006.210.07:56:33.86/chk_obsdata//k5ts1/T2100755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:56:34.19/chk_obsdata//k5ts2/T2100755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:56:34.53/chk_obsdata//k5ts3/T2100755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:56:34.87/chk_obsdata//k5ts4/T2100755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.07:56:35.54/k5log//k5ts1_log_newline 2006.210.07:56:36.20/k5log//k5ts2_log_newline 2006.210.07:56:36.86/k5log//k5ts3_log_newline 2006.210.07:56:37.51/k5log//k5ts4_log_newline 2006.210.07:56:37.54/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.07:56:37.54:4f8m12a=2 2006.210.07:56:37.54$4f8m12a/echo=on 2006.210.07:56:37.54$4f8m12a/pcalon 2006.210.07:56:37.54$pcalon/"no phase cal control is implemented here 2006.210.07:56:37.54$4f8m12a/"tpicd=stop 2006.210.07:56:37.54$4f8m12a/vc4f8 2006.210.07:56:37.54$vc4f8/valo=1,532.99 2006.210.07:56:37.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:56:37.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:56:37.54#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:37.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:37.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:37.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:37.54#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:56:37.54#ibcon#first serial, iclass 40, count 0 2006.210.07:56:37.54#ibcon#enter sib2, iclass 40, count 0 2006.210.07:56:37.54#ibcon#flushed, iclass 40, count 0 2006.210.07:56:37.54#ibcon#about to write, iclass 40, count 0 2006.210.07:56:37.54#ibcon#wrote, iclass 40, count 0 2006.210.07:56:37.54#ibcon#about to read 3, iclass 40, count 0 2006.210.07:56:37.56#ibcon#read 3, iclass 40, count 0 2006.210.07:56:37.56#ibcon#about to read 4, iclass 40, count 0 2006.210.07:56:37.56#ibcon#read 4, iclass 40, count 0 2006.210.07:56:37.56#ibcon#about to read 5, iclass 40, count 0 2006.210.07:56:37.56#ibcon#read 5, iclass 40, count 0 2006.210.07:56:37.56#ibcon#about to read 6, iclass 40, count 0 2006.210.07:56:37.56#ibcon#read 6, iclass 40, count 0 2006.210.07:56:37.56#ibcon#end of sib2, iclass 40, count 0 2006.210.07:56:37.56#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:56:37.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:56:37.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.07:56:37.56#ibcon#*before write, iclass 40, count 0 2006.210.07:56:37.56#ibcon#enter sib2, iclass 40, count 0 2006.210.07:56:37.56#ibcon#flushed, iclass 40, count 0 2006.210.07:56:37.56#ibcon#about to write, iclass 40, count 0 2006.210.07:56:37.56#ibcon#wrote, iclass 40, count 0 2006.210.07:56:37.56#ibcon#about to read 3, iclass 40, count 0 2006.210.07:56:37.61#ibcon#read 3, iclass 40, count 0 2006.210.07:56:37.61#ibcon#about to read 4, iclass 40, count 0 2006.210.07:56:37.61#ibcon#read 4, iclass 40, count 0 2006.210.07:56:37.61#ibcon#about to read 5, iclass 40, count 0 2006.210.07:56:37.61#ibcon#read 5, iclass 40, count 0 2006.210.07:56:37.61#ibcon#about to read 6, iclass 40, count 0 2006.210.07:56:37.61#ibcon#read 6, iclass 40, count 0 2006.210.07:56:37.61#ibcon#end of sib2, iclass 40, count 0 2006.210.07:56:37.61#ibcon#*after write, iclass 40, count 0 2006.210.07:56:37.61#ibcon#*before return 0, iclass 40, count 0 2006.210.07:56:37.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:37.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:37.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:56:37.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:56:37.61$vc4f8/va=1,8 2006.210.07:56:37.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:56:37.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:56:37.61#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:37.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:37.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:37.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:37.61#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:56:37.61#ibcon#first serial, iclass 4, count 2 2006.210.07:56:37.61#ibcon#enter sib2, iclass 4, count 2 2006.210.07:56:37.61#ibcon#flushed, iclass 4, count 2 2006.210.07:56:37.61#ibcon#about to write, iclass 4, count 2 2006.210.07:56:37.61#ibcon#wrote, iclass 4, count 2 2006.210.07:56:37.61#ibcon#about to read 3, iclass 4, count 2 2006.210.07:56:37.63#ibcon#read 3, iclass 4, count 2 2006.210.07:56:37.63#ibcon#about to read 4, iclass 4, count 2 2006.210.07:56:37.63#ibcon#read 4, iclass 4, count 2 2006.210.07:56:37.63#ibcon#about to read 5, iclass 4, count 2 2006.210.07:56:37.63#ibcon#read 5, iclass 4, count 2 2006.210.07:56:37.63#ibcon#about to read 6, iclass 4, count 2 2006.210.07:56:37.63#ibcon#read 6, iclass 4, count 2 2006.210.07:56:37.63#ibcon#end of sib2, iclass 4, count 2 2006.210.07:56:37.63#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:56:37.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:56:37.63#ibcon#[25=AT01-08\r\n] 2006.210.07:56:37.63#ibcon#*before write, iclass 4, count 2 2006.210.07:56:37.63#ibcon#enter sib2, iclass 4, count 2 2006.210.07:56:37.63#ibcon#flushed, iclass 4, count 2 2006.210.07:56:37.63#ibcon#about to write, iclass 4, count 2 2006.210.07:56:37.63#ibcon#wrote, iclass 4, count 2 2006.210.07:56:37.63#ibcon#about to read 3, iclass 4, count 2 2006.210.07:56:37.66#ibcon#read 3, iclass 4, count 2 2006.210.07:56:37.66#ibcon#about to read 4, iclass 4, count 2 2006.210.07:56:37.66#ibcon#read 4, iclass 4, count 2 2006.210.07:56:37.66#ibcon#about to read 5, iclass 4, count 2 2006.210.07:56:37.66#ibcon#read 5, iclass 4, count 2 2006.210.07:56:37.66#ibcon#about to read 6, iclass 4, count 2 2006.210.07:56:37.66#ibcon#read 6, iclass 4, count 2 2006.210.07:56:37.66#ibcon#end of sib2, iclass 4, count 2 2006.210.07:56:37.66#ibcon#*after write, iclass 4, count 2 2006.210.07:56:37.66#ibcon#*before return 0, iclass 4, count 2 2006.210.07:56:37.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:37.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:37.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:56:37.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:37.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:37.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:37.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:37.78#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:56:37.78#ibcon#first serial, iclass 4, count 0 2006.210.07:56:37.78#ibcon#enter sib2, iclass 4, count 0 2006.210.07:56:37.78#ibcon#flushed, iclass 4, count 0 2006.210.07:56:37.78#ibcon#about to write, iclass 4, count 0 2006.210.07:56:37.78#ibcon#wrote, iclass 4, count 0 2006.210.07:56:37.78#ibcon#about to read 3, iclass 4, count 0 2006.210.07:56:37.80#ibcon#read 3, iclass 4, count 0 2006.210.07:56:37.80#ibcon#about to read 4, iclass 4, count 0 2006.210.07:56:37.80#ibcon#read 4, iclass 4, count 0 2006.210.07:56:37.80#ibcon#about to read 5, iclass 4, count 0 2006.210.07:56:37.80#ibcon#read 5, iclass 4, count 0 2006.210.07:56:37.80#ibcon#about to read 6, iclass 4, count 0 2006.210.07:56:37.80#ibcon#read 6, iclass 4, count 0 2006.210.07:56:37.80#ibcon#end of sib2, iclass 4, count 0 2006.210.07:56:37.80#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:56:37.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:56:37.80#ibcon#[25=USB\r\n] 2006.210.07:56:37.80#ibcon#*before write, iclass 4, count 0 2006.210.07:56:37.80#ibcon#enter sib2, iclass 4, count 0 2006.210.07:56:37.80#ibcon#flushed, iclass 4, count 0 2006.210.07:56:37.80#ibcon#about to write, iclass 4, count 0 2006.210.07:56:37.80#ibcon#wrote, iclass 4, count 0 2006.210.07:56:37.80#ibcon#about to read 3, iclass 4, count 0 2006.210.07:56:37.83#ibcon#read 3, iclass 4, count 0 2006.210.07:56:37.83#ibcon#about to read 4, iclass 4, count 0 2006.210.07:56:37.83#ibcon#read 4, iclass 4, count 0 2006.210.07:56:37.83#ibcon#about to read 5, iclass 4, count 0 2006.210.07:56:37.83#ibcon#read 5, iclass 4, count 0 2006.210.07:56:37.83#ibcon#about to read 6, iclass 4, count 0 2006.210.07:56:37.83#ibcon#read 6, iclass 4, count 0 2006.210.07:56:37.83#ibcon#end of sib2, iclass 4, count 0 2006.210.07:56:37.83#ibcon#*after write, iclass 4, count 0 2006.210.07:56:37.83#ibcon#*before return 0, iclass 4, count 0 2006.210.07:56:37.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:37.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:37.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:56:37.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:56:37.83$vc4f8/valo=2,572.99 2006.210.07:56:37.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:56:37.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:56:37.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:37.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:37.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:37.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:37.83#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:56:37.83#ibcon#first serial, iclass 6, count 0 2006.210.07:56:37.83#ibcon#enter sib2, iclass 6, count 0 2006.210.07:56:37.83#ibcon#flushed, iclass 6, count 0 2006.210.07:56:37.83#ibcon#about to write, iclass 6, count 0 2006.210.07:56:37.83#ibcon#wrote, iclass 6, count 0 2006.210.07:56:37.83#ibcon#about to read 3, iclass 6, count 0 2006.210.07:56:37.85#ibcon#read 3, iclass 6, count 0 2006.210.07:56:37.85#ibcon#about to read 4, iclass 6, count 0 2006.210.07:56:37.85#ibcon#read 4, iclass 6, count 0 2006.210.07:56:37.85#ibcon#about to read 5, iclass 6, count 0 2006.210.07:56:37.85#ibcon#read 5, iclass 6, count 0 2006.210.07:56:37.85#ibcon#about to read 6, iclass 6, count 0 2006.210.07:56:37.85#ibcon#read 6, iclass 6, count 0 2006.210.07:56:37.85#ibcon#end of sib2, iclass 6, count 0 2006.210.07:56:37.85#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:56:37.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:56:37.85#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.07:56:37.85#ibcon#*before write, iclass 6, count 0 2006.210.07:56:37.85#ibcon#enter sib2, iclass 6, count 0 2006.210.07:56:37.85#ibcon#flushed, iclass 6, count 0 2006.210.07:56:37.85#ibcon#about to write, iclass 6, count 0 2006.210.07:56:37.85#ibcon#wrote, iclass 6, count 0 2006.210.07:56:37.85#ibcon#about to read 3, iclass 6, count 0 2006.210.07:56:37.89#ibcon#read 3, iclass 6, count 0 2006.210.07:56:37.89#ibcon#about to read 4, iclass 6, count 0 2006.210.07:56:37.89#ibcon#read 4, iclass 6, count 0 2006.210.07:56:37.89#ibcon#about to read 5, iclass 6, count 0 2006.210.07:56:37.89#ibcon#read 5, iclass 6, count 0 2006.210.07:56:37.89#ibcon#about to read 6, iclass 6, count 0 2006.210.07:56:37.89#ibcon#read 6, iclass 6, count 0 2006.210.07:56:37.89#ibcon#end of sib2, iclass 6, count 0 2006.210.07:56:37.89#ibcon#*after write, iclass 6, count 0 2006.210.07:56:37.89#ibcon#*before return 0, iclass 6, count 0 2006.210.07:56:37.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:37.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:37.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:56:37.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:56:37.89$vc4f8/va=2,7 2006.210.07:56:37.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:56:37.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:56:37.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:37.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:37.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:37.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:37.95#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:56:37.95#ibcon#first serial, iclass 10, count 2 2006.210.07:56:37.95#ibcon#enter sib2, iclass 10, count 2 2006.210.07:56:37.95#ibcon#flushed, iclass 10, count 2 2006.210.07:56:37.95#ibcon#about to write, iclass 10, count 2 2006.210.07:56:37.95#ibcon#wrote, iclass 10, count 2 2006.210.07:56:37.95#ibcon#about to read 3, iclass 10, count 2 2006.210.07:56:37.97#ibcon#read 3, iclass 10, count 2 2006.210.07:56:37.97#ibcon#about to read 4, iclass 10, count 2 2006.210.07:56:37.97#ibcon#read 4, iclass 10, count 2 2006.210.07:56:37.97#ibcon#about to read 5, iclass 10, count 2 2006.210.07:56:37.97#ibcon#read 5, iclass 10, count 2 2006.210.07:56:37.97#ibcon#about to read 6, iclass 10, count 2 2006.210.07:56:37.97#ibcon#read 6, iclass 10, count 2 2006.210.07:56:37.97#ibcon#end of sib2, iclass 10, count 2 2006.210.07:56:37.97#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:56:37.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:56:37.97#ibcon#[25=AT02-07\r\n] 2006.210.07:56:37.97#ibcon#*before write, iclass 10, count 2 2006.210.07:56:37.97#ibcon#enter sib2, iclass 10, count 2 2006.210.07:56:37.97#ibcon#flushed, iclass 10, count 2 2006.210.07:56:37.97#ibcon#about to write, iclass 10, count 2 2006.210.07:56:37.97#ibcon#wrote, iclass 10, count 2 2006.210.07:56:37.97#ibcon#about to read 3, iclass 10, count 2 2006.210.07:56:38.00#ibcon#read 3, iclass 10, count 2 2006.210.07:56:38.00#ibcon#about to read 4, iclass 10, count 2 2006.210.07:56:38.00#ibcon#read 4, iclass 10, count 2 2006.210.07:56:38.00#ibcon#about to read 5, iclass 10, count 2 2006.210.07:56:38.00#ibcon#read 5, iclass 10, count 2 2006.210.07:56:38.00#ibcon#about to read 6, iclass 10, count 2 2006.210.07:56:38.00#ibcon#read 6, iclass 10, count 2 2006.210.07:56:38.00#ibcon#end of sib2, iclass 10, count 2 2006.210.07:56:38.00#ibcon#*after write, iclass 10, count 2 2006.210.07:56:38.00#ibcon#*before return 0, iclass 10, count 2 2006.210.07:56:38.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:38.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:38.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:56:38.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:38.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:38.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:38.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:38.12#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:56:38.12#ibcon#first serial, iclass 10, count 0 2006.210.07:56:38.12#ibcon#enter sib2, iclass 10, count 0 2006.210.07:56:38.12#ibcon#flushed, iclass 10, count 0 2006.210.07:56:38.12#ibcon#about to write, iclass 10, count 0 2006.210.07:56:38.12#ibcon#wrote, iclass 10, count 0 2006.210.07:56:38.12#ibcon#about to read 3, iclass 10, count 0 2006.210.07:56:38.14#ibcon#read 3, iclass 10, count 0 2006.210.07:56:38.14#ibcon#about to read 4, iclass 10, count 0 2006.210.07:56:38.14#ibcon#read 4, iclass 10, count 0 2006.210.07:56:38.14#ibcon#about to read 5, iclass 10, count 0 2006.210.07:56:38.14#ibcon#read 5, iclass 10, count 0 2006.210.07:56:38.14#ibcon#about to read 6, iclass 10, count 0 2006.210.07:56:38.14#ibcon#read 6, iclass 10, count 0 2006.210.07:56:38.14#ibcon#end of sib2, iclass 10, count 0 2006.210.07:56:38.14#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:56:38.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:56:38.14#ibcon#[25=USB\r\n] 2006.210.07:56:38.14#ibcon#*before write, iclass 10, count 0 2006.210.07:56:38.14#ibcon#enter sib2, iclass 10, count 0 2006.210.07:56:38.14#ibcon#flushed, iclass 10, count 0 2006.210.07:56:38.14#ibcon#about to write, iclass 10, count 0 2006.210.07:56:38.14#ibcon#wrote, iclass 10, count 0 2006.210.07:56:38.14#ibcon#about to read 3, iclass 10, count 0 2006.210.07:56:38.17#ibcon#read 3, iclass 10, count 0 2006.210.07:56:38.17#ibcon#about to read 4, iclass 10, count 0 2006.210.07:56:38.17#ibcon#read 4, iclass 10, count 0 2006.210.07:56:38.17#ibcon#about to read 5, iclass 10, count 0 2006.210.07:56:38.17#ibcon#read 5, iclass 10, count 0 2006.210.07:56:38.17#ibcon#about to read 6, iclass 10, count 0 2006.210.07:56:38.17#ibcon#read 6, iclass 10, count 0 2006.210.07:56:38.17#ibcon#end of sib2, iclass 10, count 0 2006.210.07:56:38.17#ibcon#*after write, iclass 10, count 0 2006.210.07:56:38.17#ibcon#*before return 0, iclass 10, count 0 2006.210.07:56:38.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:38.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:38.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:56:38.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:56:38.17$vc4f8/valo=3,672.99 2006.210.07:56:38.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:56:38.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:56:38.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:38.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:38.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:38.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:38.17#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:56:38.17#ibcon#first serial, iclass 12, count 0 2006.210.07:56:38.17#ibcon#enter sib2, iclass 12, count 0 2006.210.07:56:38.17#ibcon#flushed, iclass 12, count 0 2006.210.07:56:38.17#ibcon#about to write, iclass 12, count 0 2006.210.07:56:38.17#ibcon#wrote, iclass 12, count 0 2006.210.07:56:38.17#ibcon#about to read 3, iclass 12, count 0 2006.210.07:56:38.19#ibcon#read 3, iclass 12, count 0 2006.210.07:56:38.19#ibcon#about to read 4, iclass 12, count 0 2006.210.07:56:38.19#ibcon#read 4, iclass 12, count 0 2006.210.07:56:38.19#ibcon#about to read 5, iclass 12, count 0 2006.210.07:56:38.19#ibcon#read 5, iclass 12, count 0 2006.210.07:56:38.19#ibcon#about to read 6, iclass 12, count 0 2006.210.07:56:38.19#ibcon#read 6, iclass 12, count 0 2006.210.07:56:38.19#ibcon#end of sib2, iclass 12, count 0 2006.210.07:56:38.19#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:56:38.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:56:38.19#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.07:56:38.19#ibcon#*before write, iclass 12, count 0 2006.210.07:56:38.19#ibcon#enter sib2, iclass 12, count 0 2006.210.07:56:38.19#ibcon#flushed, iclass 12, count 0 2006.210.07:56:38.19#ibcon#about to write, iclass 12, count 0 2006.210.07:56:38.19#ibcon#wrote, iclass 12, count 0 2006.210.07:56:38.19#ibcon#about to read 3, iclass 12, count 0 2006.210.07:56:38.23#ibcon#read 3, iclass 12, count 0 2006.210.07:56:38.23#ibcon#about to read 4, iclass 12, count 0 2006.210.07:56:38.23#ibcon#read 4, iclass 12, count 0 2006.210.07:56:38.23#ibcon#about to read 5, iclass 12, count 0 2006.210.07:56:38.23#ibcon#read 5, iclass 12, count 0 2006.210.07:56:38.23#ibcon#about to read 6, iclass 12, count 0 2006.210.07:56:38.23#ibcon#read 6, iclass 12, count 0 2006.210.07:56:38.23#ibcon#end of sib2, iclass 12, count 0 2006.210.07:56:38.23#ibcon#*after write, iclass 12, count 0 2006.210.07:56:38.23#ibcon#*before return 0, iclass 12, count 0 2006.210.07:56:38.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:38.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:38.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:56:38.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:56:38.23$vc4f8/va=3,6 2006.210.07:56:38.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:56:38.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:56:38.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:38.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:38.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:38.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:38.29#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:56:38.29#ibcon#first serial, iclass 14, count 2 2006.210.07:56:38.29#ibcon#enter sib2, iclass 14, count 2 2006.210.07:56:38.29#ibcon#flushed, iclass 14, count 2 2006.210.07:56:38.29#ibcon#about to write, iclass 14, count 2 2006.210.07:56:38.29#ibcon#wrote, iclass 14, count 2 2006.210.07:56:38.29#ibcon#about to read 3, iclass 14, count 2 2006.210.07:56:38.31#ibcon#read 3, iclass 14, count 2 2006.210.07:56:38.31#ibcon#about to read 4, iclass 14, count 2 2006.210.07:56:38.31#ibcon#read 4, iclass 14, count 2 2006.210.07:56:38.31#ibcon#about to read 5, iclass 14, count 2 2006.210.07:56:38.31#ibcon#read 5, iclass 14, count 2 2006.210.07:56:38.31#ibcon#about to read 6, iclass 14, count 2 2006.210.07:56:38.31#ibcon#read 6, iclass 14, count 2 2006.210.07:56:38.31#ibcon#end of sib2, iclass 14, count 2 2006.210.07:56:38.31#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:56:38.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:56:38.31#ibcon#[25=AT03-06\r\n] 2006.210.07:56:38.31#ibcon#*before write, iclass 14, count 2 2006.210.07:56:38.31#ibcon#enter sib2, iclass 14, count 2 2006.210.07:56:38.31#ibcon#flushed, iclass 14, count 2 2006.210.07:56:38.31#ibcon#about to write, iclass 14, count 2 2006.210.07:56:38.31#ibcon#wrote, iclass 14, count 2 2006.210.07:56:38.31#ibcon#about to read 3, iclass 14, count 2 2006.210.07:56:38.34#ibcon#read 3, iclass 14, count 2 2006.210.07:56:38.34#ibcon#about to read 4, iclass 14, count 2 2006.210.07:56:38.34#ibcon#read 4, iclass 14, count 2 2006.210.07:56:38.34#ibcon#about to read 5, iclass 14, count 2 2006.210.07:56:38.34#ibcon#read 5, iclass 14, count 2 2006.210.07:56:38.34#ibcon#about to read 6, iclass 14, count 2 2006.210.07:56:38.34#ibcon#read 6, iclass 14, count 2 2006.210.07:56:38.34#ibcon#end of sib2, iclass 14, count 2 2006.210.07:56:38.34#ibcon#*after write, iclass 14, count 2 2006.210.07:56:38.34#ibcon#*before return 0, iclass 14, count 2 2006.210.07:56:38.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:38.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:38.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:56:38.34#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:38.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:38.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:38.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:38.46#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:56:38.46#ibcon#first serial, iclass 14, count 0 2006.210.07:56:38.46#ibcon#enter sib2, iclass 14, count 0 2006.210.07:56:38.46#ibcon#flushed, iclass 14, count 0 2006.210.07:56:38.46#ibcon#about to write, iclass 14, count 0 2006.210.07:56:38.46#ibcon#wrote, iclass 14, count 0 2006.210.07:56:38.46#ibcon#about to read 3, iclass 14, count 0 2006.210.07:56:38.48#ibcon#read 3, iclass 14, count 0 2006.210.07:56:38.48#ibcon#about to read 4, iclass 14, count 0 2006.210.07:56:38.48#ibcon#read 4, iclass 14, count 0 2006.210.07:56:38.48#ibcon#about to read 5, iclass 14, count 0 2006.210.07:56:38.48#ibcon#read 5, iclass 14, count 0 2006.210.07:56:38.48#ibcon#about to read 6, iclass 14, count 0 2006.210.07:56:38.48#ibcon#read 6, iclass 14, count 0 2006.210.07:56:38.48#ibcon#end of sib2, iclass 14, count 0 2006.210.07:56:38.48#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:56:38.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:56:38.48#ibcon#[25=USB\r\n] 2006.210.07:56:38.48#ibcon#*before write, iclass 14, count 0 2006.210.07:56:38.48#ibcon#enter sib2, iclass 14, count 0 2006.210.07:56:38.48#ibcon#flushed, iclass 14, count 0 2006.210.07:56:38.48#ibcon#about to write, iclass 14, count 0 2006.210.07:56:38.48#ibcon#wrote, iclass 14, count 0 2006.210.07:56:38.48#ibcon#about to read 3, iclass 14, count 0 2006.210.07:56:38.51#ibcon#read 3, iclass 14, count 0 2006.210.07:56:38.51#ibcon#about to read 4, iclass 14, count 0 2006.210.07:56:38.51#ibcon#read 4, iclass 14, count 0 2006.210.07:56:38.51#ibcon#about to read 5, iclass 14, count 0 2006.210.07:56:38.51#ibcon#read 5, iclass 14, count 0 2006.210.07:56:38.51#ibcon#about to read 6, iclass 14, count 0 2006.210.07:56:38.51#ibcon#read 6, iclass 14, count 0 2006.210.07:56:38.51#ibcon#end of sib2, iclass 14, count 0 2006.210.07:56:38.51#ibcon#*after write, iclass 14, count 0 2006.210.07:56:38.51#ibcon#*before return 0, iclass 14, count 0 2006.210.07:56:38.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:38.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:38.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:56:38.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:56:38.51$vc4f8/valo=4,832.99 2006.210.07:56:38.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:56:38.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:56:38.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:38.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:38.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:38.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:38.51#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:56:38.51#ibcon#first serial, iclass 16, count 0 2006.210.07:56:38.51#ibcon#enter sib2, iclass 16, count 0 2006.210.07:56:38.51#ibcon#flushed, iclass 16, count 0 2006.210.07:56:38.51#ibcon#about to write, iclass 16, count 0 2006.210.07:56:38.51#ibcon#wrote, iclass 16, count 0 2006.210.07:56:38.51#ibcon#about to read 3, iclass 16, count 0 2006.210.07:56:38.53#ibcon#read 3, iclass 16, count 0 2006.210.07:56:38.53#ibcon#about to read 4, iclass 16, count 0 2006.210.07:56:38.53#ibcon#read 4, iclass 16, count 0 2006.210.07:56:38.53#ibcon#about to read 5, iclass 16, count 0 2006.210.07:56:38.53#ibcon#read 5, iclass 16, count 0 2006.210.07:56:38.53#ibcon#about to read 6, iclass 16, count 0 2006.210.07:56:38.53#ibcon#read 6, iclass 16, count 0 2006.210.07:56:38.53#ibcon#end of sib2, iclass 16, count 0 2006.210.07:56:38.53#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:56:38.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:56:38.53#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.07:56:38.53#ibcon#*before write, iclass 16, count 0 2006.210.07:56:38.53#ibcon#enter sib2, iclass 16, count 0 2006.210.07:56:38.53#ibcon#flushed, iclass 16, count 0 2006.210.07:56:38.53#ibcon#about to write, iclass 16, count 0 2006.210.07:56:38.53#ibcon#wrote, iclass 16, count 0 2006.210.07:56:38.53#ibcon#about to read 3, iclass 16, count 0 2006.210.07:56:38.57#ibcon#read 3, iclass 16, count 0 2006.210.07:56:38.57#ibcon#about to read 4, iclass 16, count 0 2006.210.07:56:38.57#ibcon#read 4, iclass 16, count 0 2006.210.07:56:38.57#ibcon#about to read 5, iclass 16, count 0 2006.210.07:56:38.57#ibcon#read 5, iclass 16, count 0 2006.210.07:56:38.57#ibcon#about to read 6, iclass 16, count 0 2006.210.07:56:38.57#ibcon#read 6, iclass 16, count 0 2006.210.07:56:38.57#ibcon#end of sib2, iclass 16, count 0 2006.210.07:56:38.57#ibcon#*after write, iclass 16, count 0 2006.210.07:56:38.57#ibcon#*before return 0, iclass 16, count 0 2006.210.07:56:38.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:38.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:38.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:56:38.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:56:38.57$vc4f8/va=4,7 2006.210.07:56:38.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:56:38.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:56:38.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:38.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:38.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:38.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:38.63#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:56:38.63#ibcon#first serial, iclass 18, count 2 2006.210.07:56:38.63#ibcon#enter sib2, iclass 18, count 2 2006.210.07:56:38.63#ibcon#flushed, iclass 18, count 2 2006.210.07:56:38.63#ibcon#about to write, iclass 18, count 2 2006.210.07:56:38.63#ibcon#wrote, iclass 18, count 2 2006.210.07:56:38.63#ibcon#about to read 3, iclass 18, count 2 2006.210.07:56:38.65#ibcon#read 3, iclass 18, count 2 2006.210.07:56:38.65#ibcon#about to read 4, iclass 18, count 2 2006.210.07:56:38.65#ibcon#read 4, iclass 18, count 2 2006.210.07:56:38.65#ibcon#about to read 5, iclass 18, count 2 2006.210.07:56:38.65#ibcon#read 5, iclass 18, count 2 2006.210.07:56:38.65#ibcon#about to read 6, iclass 18, count 2 2006.210.07:56:38.65#ibcon#read 6, iclass 18, count 2 2006.210.07:56:38.65#ibcon#end of sib2, iclass 18, count 2 2006.210.07:56:38.65#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:56:38.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:56:38.65#ibcon#[25=AT04-07\r\n] 2006.210.07:56:38.65#ibcon#*before write, iclass 18, count 2 2006.210.07:56:38.65#ibcon#enter sib2, iclass 18, count 2 2006.210.07:56:38.65#ibcon#flushed, iclass 18, count 2 2006.210.07:56:38.65#ibcon#about to write, iclass 18, count 2 2006.210.07:56:38.65#ibcon#wrote, iclass 18, count 2 2006.210.07:56:38.65#ibcon#about to read 3, iclass 18, count 2 2006.210.07:56:38.68#ibcon#read 3, iclass 18, count 2 2006.210.07:56:38.68#ibcon#about to read 4, iclass 18, count 2 2006.210.07:56:38.68#ibcon#read 4, iclass 18, count 2 2006.210.07:56:38.68#ibcon#about to read 5, iclass 18, count 2 2006.210.07:56:38.68#ibcon#read 5, iclass 18, count 2 2006.210.07:56:38.68#ibcon#about to read 6, iclass 18, count 2 2006.210.07:56:38.68#ibcon#read 6, iclass 18, count 2 2006.210.07:56:38.68#ibcon#end of sib2, iclass 18, count 2 2006.210.07:56:38.68#ibcon#*after write, iclass 18, count 2 2006.210.07:56:38.68#ibcon#*before return 0, iclass 18, count 2 2006.210.07:56:38.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:38.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:38.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:56:38.68#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:38.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:38.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:38.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:38.80#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:56:38.80#ibcon#first serial, iclass 18, count 0 2006.210.07:56:38.80#ibcon#enter sib2, iclass 18, count 0 2006.210.07:56:38.80#ibcon#flushed, iclass 18, count 0 2006.210.07:56:38.80#ibcon#about to write, iclass 18, count 0 2006.210.07:56:38.80#ibcon#wrote, iclass 18, count 0 2006.210.07:56:38.80#ibcon#about to read 3, iclass 18, count 0 2006.210.07:56:38.82#ibcon#read 3, iclass 18, count 0 2006.210.07:56:38.82#ibcon#about to read 4, iclass 18, count 0 2006.210.07:56:38.82#ibcon#read 4, iclass 18, count 0 2006.210.07:56:38.82#ibcon#about to read 5, iclass 18, count 0 2006.210.07:56:38.82#ibcon#read 5, iclass 18, count 0 2006.210.07:56:38.82#ibcon#about to read 6, iclass 18, count 0 2006.210.07:56:38.82#ibcon#read 6, iclass 18, count 0 2006.210.07:56:38.82#ibcon#end of sib2, iclass 18, count 0 2006.210.07:56:38.82#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:56:38.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:56:38.82#ibcon#[25=USB\r\n] 2006.210.07:56:38.82#ibcon#*before write, iclass 18, count 0 2006.210.07:56:38.82#ibcon#enter sib2, iclass 18, count 0 2006.210.07:56:38.82#ibcon#flushed, iclass 18, count 0 2006.210.07:56:38.82#ibcon#about to write, iclass 18, count 0 2006.210.07:56:38.82#ibcon#wrote, iclass 18, count 0 2006.210.07:56:38.82#ibcon#about to read 3, iclass 18, count 0 2006.210.07:56:38.85#ibcon#read 3, iclass 18, count 0 2006.210.07:56:38.85#ibcon#about to read 4, iclass 18, count 0 2006.210.07:56:38.85#ibcon#read 4, iclass 18, count 0 2006.210.07:56:38.85#ibcon#about to read 5, iclass 18, count 0 2006.210.07:56:38.85#ibcon#read 5, iclass 18, count 0 2006.210.07:56:38.85#ibcon#about to read 6, iclass 18, count 0 2006.210.07:56:38.85#ibcon#read 6, iclass 18, count 0 2006.210.07:56:38.85#ibcon#end of sib2, iclass 18, count 0 2006.210.07:56:38.85#ibcon#*after write, iclass 18, count 0 2006.210.07:56:38.85#ibcon#*before return 0, iclass 18, count 0 2006.210.07:56:38.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:38.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:38.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:56:38.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:56:38.85$vc4f8/valo=5,652.99 2006.210.07:56:38.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:56:38.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:56:38.85#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:38.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:38.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:38.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:38.85#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:56:38.85#ibcon#first serial, iclass 20, count 0 2006.210.07:56:38.85#ibcon#enter sib2, iclass 20, count 0 2006.210.07:56:38.85#ibcon#flushed, iclass 20, count 0 2006.210.07:56:38.85#ibcon#about to write, iclass 20, count 0 2006.210.07:56:38.85#ibcon#wrote, iclass 20, count 0 2006.210.07:56:38.85#ibcon#about to read 3, iclass 20, count 0 2006.210.07:56:38.87#ibcon#read 3, iclass 20, count 0 2006.210.07:56:38.87#ibcon#about to read 4, iclass 20, count 0 2006.210.07:56:38.87#ibcon#read 4, iclass 20, count 0 2006.210.07:56:38.87#ibcon#about to read 5, iclass 20, count 0 2006.210.07:56:38.87#ibcon#read 5, iclass 20, count 0 2006.210.07:56:38.87#ibcon#about to read 6, iclass 20, count 0 2006.210.07:56:38.87#ibcon#read 6, iclass 20, count 0 2006.210.07:56:38.87#ibcon#end of sib2, iclass 20, count 0 2006.210.07:56:38.87#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:56:38.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:56:38.87#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.07:56:38.87#ibcon#*before write, iclass 20, count 0 2006.210.07:56:38.87#ibcon#enter sib2, iclass 20, count 0 2006.210.07:56:38.87#ibcon#flushed, iclass 20, count 0 2006.210.07:56:38.87#ibcon#about to write, iclass 20, count 0 2006.210.07:56:38.87#ibcon#wrote, iclass 20, count 0 2006.210.07:56:38.87#ibcon#about to read 3, iclass 20, count 0 2006.210.07:56:38.91#ibcon#read 3, iclass 20, count 0 2006.210.07:56:38.91#ibcon#about to read 4, iclass 20, count 0 2006.210.07:56:38.91#ibcon#read 4, iclass 20, count 0 2006.210.07:56:38.91#ibcon#about to read 5, iclass 20, count 0 2006.210.07:56:38.91#ibcon#read 5, iclass 20, count 0 2006.210.07:56:38.91#ibcon#about to read 6, iclass 20, count 0 2006.210.07:56:38.91#ibcon#read 6, iclass 20, count 0 2006.210.07:56:38.91#ibcon#end of sib2, iclass 20, count 0 2006.210.07:56:38.91#ibcon#*after write, iclass 20, count 0 2006.210.07:56:38.91#ibcon#*before return 0, iclass 20, count 0 2006.210.07:56:38.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:38.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:38.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:56:38.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:56:38.91$vc4f8/va=5,7 2006.210.07:56:38.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:56:38.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:56:38.91#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:38.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:38.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:38.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:38.97#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:56:38.97#ibcon#first serial, iclass 22, count 2 2006.210.07:56:38.97#ibcon#enter sib2, iclass 22, count 2 2006.210.07:56:38.97#ibcon#flushed, iclass 22, count 2 2006.210.07:56:38.97#ibcon#about to write, iclass 22, count 2 2006.210.07:56:38.97#ibcon#wrote, iclass 22, count 2 2006.210.07:56:38.97#ibcon#about to read 3, iclass 22, count 2 2006.210.07:56:38.99#ibcon#read 3, iclass 22, count 2 2006.210.07:56:38.99#ibcon#about to read 4, iclass 22, count 2 2006.210.07:56:38.99#ibcon#read 4, iclass 22, count 2 2006.210.07:56:38.99#ibcon#about to read 5, iclass 22, count 2 2006.210.07:56:38.99#ibcon#read 5, iclass 22, count 2 2006.210.07:56:38.99#ibcon#about to read 6, iclass 22, count 2 2006.210.07:56:38.99#ibcon#read 6, iclass 22, count 2 2006.210.07:56:38.99#ibcon#end of sib2, iclass 22, count 2 2006.210.07:56:38.99#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:56:38.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:56:38.99#ibcon#[25=AT05-07\r\n] 2006.210.07:56:38.99#ibcon#*before write, iclass 22, count 2 2006.210.07:56:38.99#ibcon#enter sib2, iclass 22, count 2 2006.210.07:56:38.99#ibcon#flushed, iclass 22, count 2 2006.210.07:56:38.99#ibcon#about to write, iclass 22, count 2 2006.210.07:56:38.99#ibcon#wrote, iclass 22, count 2 2006.210.07:56:38.99#ibcon#about to read 3, iclass 22, count 2 2006.210.07:56:39.02#ibcon#read 3, iclass 22, count 2 2006.210.07:56:39.02#ibcon#about to read 4, iclass 22, count 2 2006.210.07:56:39.02#ibcon#read 4, iclass 22, count 2 2006.210.07:56:39.02#ibcon#about to read 5, iclass 22, count 2 2006.210.07:56:39.02#ibcon#read 5, iclass 22, count 2 2006.210.07:56:39.02#ibcon#about to read 6, iclass 22, count 2 2006.210.07:56:39.02#ibcon#read 6, iclass 22, count 2 2006.210.07:56:39.02#ibcon#end of sib2, iclass 22, count 2 2006.210.07:56:39.02#ibcon#*after write, iclass 22, count 2 2006.210.07:56:39.02#ibcon#*before return 0, iclass 22, count 2 2006.210.07:56:39.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:39.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:39.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:56:39.02#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:39.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:39.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:39.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:39.14#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:56:39.14#ibcon#first serial, iclass 22, count 0 2006.210.07:56:39.14#ibcon#enter sib2, iclass 22, count 0 2006.210.07:56:39.14#ibcon#flushed, iclass 22, count 0 2006.210.07:56:39.14#ibcon#about to write, iclass 22, count 0 2006.210.07:56:39.14#ibcon#wrote, iclass 22, count 0 2006.210.07:56:39.14#ibcon#about to read 3, iclass 22, count 0 2006.210.07:56:39.16#ibcon#read 3, iclass 22, count 0 2006.210.07:56:39.16#ibcon#about to read 4, iclass 22, count 0 2006.210.07:56:39.16#ibcon#read 4, iclass 22, count 0 2006.210.07:56:39.16#ibcon#about to read 5, iclass 22, count 0 2006.210.07:56:39.16#ibcon#read 5, iclass 22, count 0 2006.210.07:56:39.16#ibcon#about to read 6, iclass 22, count 0 2006.210.07:56:39.16#ibcon#read 6, iclass 22, count 0 2006.210.07:56:39.16#ibcon#end of sib2, iclass 22, count 0 2006.210.07:56:39.16#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:56:39.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:56:39.16#ibcon#[25=USB\r\n] 2006.210.07:56:39.16#ibcon#*before write, iclass 22, count 0 2006.210.07:56:39.16#ibcon#enter sib2, iclass 22, count 0 2006.210.07:56:39.16#ibcon#flushed, iclass 22, count 0 2006.210.07:56:39.16#ibcon#about to write, iclass 22, count 0 2006.210.07:56:39.16#ibcon#wrote, iclass 22, count 0 2006.210.07:56:39.16#ibcon#about to read 3, iclass 22, count 0 2006.210.07:56:39.19#ibcon#read 3, iclass 22, count 0 2006.210.07:56:39.19#ibcon#about to read 4, iclass 22, count 0 2006.210.07:56:39.19#ibcon#read 4, iclass 22, count 0 2006.210.07:56:39.19#ibcon#about to read 5, iclass 22, count 0 2006.210.07:56:39.19#ibcon#read 5, iclass 22, count 0 2006.210.07:56:39.19#ibcon#about to read 6, iclass 22, count 0 2006.210.07:56:39.19#ibcon#read 6, iclass 22, count 0 2006.210.07:56:39.19#ibcon#end of sib2, iclass 22, count 0 2006.210.07:56:39.19#ibcon#*after write, iclass 22, count 0 2006.210.07:56:39.19#ibcon#*before return 0, iclass 22, count 0 2006.210.07:56:39.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:39.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:39.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:56:39.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:56:39.19$vc4f8/valo=6,772.99 2006.210.07:56:39.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.07:56:39.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.07:56:39.19#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:39.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:56:39.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:56:39.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:56:39.19#ibcon#enter wrdev, iclass 24, count 0 2006.210.07:56:39.19#ibcon#first serial, iclass 24, count 0 2006.210.07:56:39.19#ibcon#enter sib2, iclass 24, count 0 2006.210.07:56:39.19#ibcon#flushed, iclass 24, count 0 2006.210.07:56:39.19#ibcon#about to write, iclass 24, count 0 2006.210.07:56:39.19#ibcon#wrote, iclass 24, count 0 2006.210.07:56:39.19#ibcon#about to read 3, iclass 24, count 0 2006.210.07:56:39.21#ibcon#read 3, iclass 24, count 0 2006.210.07:56:39.21#ibcon#about to read 4, iclass 24, count 0 2006.210.07:56:39.21#ibcon#read 4, iclass 24, count 0 2006.210.07:56:39.21#ibcon#about to read 5, iclass 24, count 0 2006.210.07:56:39.21#ibcon#read 5, iclass 24, count 0 2006.210.07:56:39.21#ibcon#about to read 6, iclass 24, count 0 2006.210.07:56:39.21#ibcon#read 6, iclass 24, count 0 2006.210.07:56:39.21#ibcon#end of sib2, iclass 24, count 0 2006.210.07:56:39.21#ibcon#*mode == 0, iclass 24, count 0 2006.210.07:56:39.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.07:56:39.21#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.07:56:39.21#ibcon#*before write, iclass 24, count 0 2006.210.07:56:39.21#ibcon#enter sib2, iclass 24, count 0 2006.210.07:56:39.21#ibcon#flushed, iclass 24, count 0 2006.210.07:56:39.21#ibcon#about to write, iclass 24, count 0 2006.210.07:56:39.21#ibcon#wrote, iclass 24, count 0 2006.210.07:56:39.21#ibcon#about to read 3, iclass 24, count 0 2006.210.07:56:39.25#ibcon#read 3, iclass 24, count 0 2006.210.07:56:39.25#ibcon#about to read 4, iclass 24, count 0 2006.210.07:56:39.25#ibcon#read 4, iclass 24, count 0 2006.210.07:56:39.25#ibcon#about to read 5, iclass 24, count 0 2006.210.07:56:39.25#ibcon#read 5, iclass 24, count 0 2006.210.07:56:39.25#ibcon#about to read 6, iclass 24, count 0 2006.210.07:56:39.25#ibcon#read 6, iclass 24, count 0 2006.210.07:56:39.25#ibcon#end of sib2, iclass 24, count 0 2006.210.07:56:39.25#ibcon#*after write, iclass 24, count 0 2006.210.07:56:39.25#ibcon#*before return 0, iclass 24, count 0 2006.210.07:56:39.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:56:39.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.07:56:39.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.07:56:39.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.07:56:39.25$vc4f8/va=6,6 2006.210.07:56:39.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.07:56:39.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.07:56:39.25#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:39.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:56:39.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:56:39.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:56:39.31#ibcon#enter wrdev, iclass 26, count 2 2006.210.07:56:39.31#ibcon#first serial, iclass 26, count 2 2006.210.07:56:39.31#ibcon#enter sib2, iclass 26, count 2 2006.210.07:56:39.31#ibcon#flushed, iclass 26, count 2 2006.210.07:56:39.31#ibcon#about to write, iclass 26, count 2 2006.210.07:56:39.31#ibcon#wrote, iclass 26, count 2 2006.210.07:56:39.31#ibcon#about to read 3, iclass 26, count 2 2006.210.07:56:39.33#ibcon#read 3, iclass 26, count 2 2006.210.07:56:39.33#ibcon#about to read 4, iclass 26, count 2 2006.210.07:56:39.33#ibcon#read 4, iclass 26, count 2 2006.210.07:56:39.33#ibcon#about to read 5, iclass 26, count 2 2006.210.07:56:39.33#ibcon#read 5, iclass 26, count 2 2006.210.07:56:39.33#ibcon#about to read 6, iclass 26, count 2 2006.210.07:56:39.33#ibcon#read 6, iclass 26, count 2 2006.210.07:56:39.33#ibcon#end of sib2, iclass 26, count 2 2006.210.07:56:39.33#ibcon#*mode == 0, iclass 26, count 2 2006.210.07:56:39.33#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.07:56:39.33#ibcon#[25=AT06-06\r\n] 2006.210.07:56:39.33#ibcon#*before write, iclass 26, count 2 2006.210.07:56:39.33#ibcon#enter sib2, iclass 26, count 2 2006.210.07:56:39.33#ibcon#flushed, iclass 26, count 2 2006.210.07:56:39.33#ibcon#about to write, iclass 26, count 2 2006.210.07:56:39.33#ibcon#wrote, iclass 26, count 2 2006.210.07:56:39.33#ibcon#about to read 3, iclass 26, count 2 2006.210.07:56:39.36#ibcon#read 3, iclass 26, count 2 2006.210.07:56:39.36#ibcon#about to read 4, iclass 26, count 2 2006.210.07:56:39.36#ibcon#read 4, iclass 26, count 2 2006.210.07:56:39.36#ibcon#about to read 5, iclass 26, count 2 2006.210.07:56:39.36#ibcon#read 5, iclass 26, count 2 2006.210.07:56:39.36#ibcon#about to read 6, iclass 26, count 2 2006.210.07:56:39.36#ibcon#read 6, iclass 26, count 2 2006.210.07:56:39.36#ibcon#end of sib2, iclass 26, count 2 2006.210.07:56:39.36#ibcon#*after write, iclass 26, count 2 2006.210.07:56:39.36#ibcon#*before return 0, iclass 26, count 2 2006.210.07:56:39.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:56:39.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.07:56:39.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.07:56:39.36#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:39.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:56:39.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:56:39.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:56:39.48#ibcon#enter wrdev, iclass 26, count 0 2006.210.07:56:39.48#ibcon#first serial, iclass 26, count 0 2006.210.07:56:39.48#ibcon#enter sib2, iclass 26, count 0 2006.210.07:56:39.48#ibcon#flushed, iclass 26, count 0 2006.210.07:56:39.48#ibcon#about to write, iclass 26, count 0 2006.210.07:56:39.48#ibcon#wrote, iclass 26, count 0 2006.210.07:56:39.48#ibcon#about to read 3, iclass 26, count 0 2006.210.07:56:39.50#ibcon#read 3, iclass 26, count 0 2006.210.07:56:39.50#ibcon#about to read 4, iclass 26, count 0 2006.210.07:56:39.50#ibcon#read 4, iclass 26, count 0 2006.210.07:56:39.50#ibcon#about to read 5, iclass 26, count 0 2006.210.07:56:39.50#ibcon#read 5, iclass 26, count 0 2006.210.07:56:39.50#ibcon#about to read 6, iclass 26, count 0 2006.210.07:56:39.50#ibcon#read 6, iclass 26, count 0 2006.210.07:56:39.50#ibcon#end of sib2, iclass 26, count 0 2006.210.07:56:39.50#ibcon#*mode == 0, iclass 26, count 0 2006.210.07:56:39.50#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.07:56:39.50#ibcon#[25=USB\r\n] 2006.210.07:56:39.50#ibcon#*before write, iclass 26, count 0 2006.210.07:56:39.50#ibcon#enter sib2, iclass 26, count 0 2006.210.07:56:39.50#ibcon#flushed, iclass 26, count 0 2006.210.07:56:39.50#ibcon#about to write, iclass 26, count 0 2006.210.07:56:39.50#ibcon#wrote, iclass 26, count 0 2006.210.07:56:39.50#ibcon#about to read 3, iclass 26, count 0 2006.210.07:56:39.53#ibcon#read 3, iclass 26, count 0 2006.210.07:56:39.53#ibcon#about to read 4, iclass 26, count 0 2006.210.07:56:39.53#ibcon#read 4, iclass 26, count 0 2006.210.07:56:39.53#ibcon#about to read 5, iclass 26, count 0 2006.210.07:56:39.53#ibcon#read 5, iclass 26, count 0 2006.210.07:56:39.53#ibcon#about to read 6, iclass 26, count 0 2006.210.07:56:39.53#ibcon#read 6, iclass 26, count 0 2006.210.07:56:39.53#ibcon#end of sib2, iclass 26, count 0 2006.210.07:56:39.53#ibcon#*after write, iclass 26, count 0 2006.210.07:56:39.53#ibcon#*before return 0, iclass 26, count 0 2006.210.07:56:39.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:56:39.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.07:56:39.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.07:56:39.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.07:56:39.53$vc4f8/valo=7,832.99 2006.210.07:56:39.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.07:56:39.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.07:56:39.53#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:39.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:56:39.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:56:39.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:56:39.53#ibcon#enter wrdev, iclass 28, count 0 2006.210.07:56:39.53#ibcon#first serial, iclass 28, count 0 2006.210.07:56:39.53#ibcon#enter sib2, iclass 28, count 0 2006.210.07:56:39.53#ibcon#flushed, iclass 28, count 0 2006.210.07:56:39.53#ibcon#about to write, iclass 28, count 0 2006.210.07:56:39.53#ibcon#wrote, iclass 28, count 0 2006.210.07:56:39.53#ibcon#about to read 3, iclass 28, count 0 2006.210.07:56:39.55#ibcon#read 3, iclass 28, count 0 2006.210.07:56:39.55#ibcon#about to read 4, iclass 28, count 0 2006.210.07:56:39.55#ibcon#read 4, iclass 28, count 0 2006.210.07:56:39.55#ibcon#about to read 5, iclass 28, count 0 2006.210.07:56:39.55#ibcon#read 5, iclass 28, count 0 2006.210.07:56:39.55#ibcon#about to read 6, iclass 28, count 0 2006.210.07:56:39.55#ibcon#read 6, iclass 28, count 0 2006.210.07:56:39.55#ibcon#end of sib2, iclass 28, count 0 2006.210.07:56:39.55#ibcon#*mode == 0, iclass 28, count 0 2006.210.07:56:39.55#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.07:56:39.55#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.07:56:39.55#ibcon#*before write, iclass 28, count 0 2006.210.07:56:39.55#ibcon#enter sib2, iclass 28, count 0 2006.210.07:56:39.55#ibcon#flushed, iclass 28, count 0 2006.210.07:56:39.55#ibcon#about to write, iclass 28, count 0 2006.210.07:56:39.55#ibcon#wrote, iclass 28, count 0 2006.210.07:56:39.55#ibcon#about to read 3, iclass 28, count 0 2006.210.07:56:39.59#ibcon#read 3, iclass 28, count 0 2006.210.07:56:39.59#ibcon#about to read 4, iclass 28, count 0 2006.210.07:56:39.59#ibcon#read 4, iclass 28, count 0 2006.210.07:56:39.59#ibcon#about to read 5, iclass 28, count 0 2006.210.07:56:39.59#ibcon#read 5, iclass 28, count 0 2006.210.07:56:39.59#ibcon#about to read 6, iclass 28, count 0 2006.210.07:56:39.59#ibcon#read 6, iclass 28, count 0 2006.210.07:56:39.59#ibcon#end of sib2, iclass 28, count 0 2006.210.07:56:39.59#ibcon#*after write, iclass 28, count 0 2006.210.07:56:39.59#ibcon#*before return 0, iclass 28, count 0 2006.210.07:56:39.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:56:39.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.07:56:39.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.07:56:39.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.07:56:39.59$vc4f8/va=7,6 2006.210.07:56:39.59#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.07:56:39.59#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.07:56:39.59#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:39.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:56:39.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:56:39.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:56:39.65#ibcon#enter wrdev, iclass 30, count 2 2006.210.07:56:39.65#ibcon#first serial, iclass 30, count 2 2006.210.07:56:39.65#ibcon#enter sib2, iclass 30, count 2 2006.210.07:56:39.65#ibcon#flushed, iclass 30, count 2 2006.210.07:56:39.65#ibcon#about to write, iclass 30, count 2 2006.210.07:56:39.65#ibcon#wrote, iclass 30, count 2 2006.210.07:56:39.65#ibcon#about to read 3, iclass 30, count 2 2006.210.07:56:39.67#ibcon#read 3, iclass 30, count 2 2006.210.07:56:39.67#ibcon#about to read 4, iclass 30, count 2 2006.210.07:56:39.67#ibcon#read 4, iclass 30, count 2 2006.210.07:56:39.67#ibcon#about to read 5, iclass 30, count 2 2006.210.07:56:39.67#ibcon#read 5, iclass 30, count 2 2006.210.07:56:39.67#ibcon#about to read 6, iclass 30, count 2 2006.210.07:56:39.67#ibcon#read 6, iclass 30, count 2 2006.210.07:56:39.67#ibcon#end of sib2, iclass 30, count 2 2006.210.07:56:39.67#ibcon#*mode == 0, iclass 30, count 2 2006.210.07:56:39.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.07:56:39.67#ibcon#[25=AT07-06\r\n] 2006.210.07:56:39.67#ibcon#*before write, iclass 30, count 2 2006.210.07:56:39.67#ibcon#enter sib2, iclass 30, count 2 2006.210.07:56:39.67#ibcon#flushed, iclass 30, count 2 2006.210.07:56:39.67#ibcon#about to write, iclass 30, count 2 2006.210.07:56:39.67#ibcon#wrote, iclass 30, count 2 2006.210.07:56:39.67#ibcon#about to read 3, iclass 30, count 2 2006.210.07:56:39.70#ibcon#read 3, iclass 30, count 2 2006.210.07:56:39.70#ibcon#about to read 4, iclass 30, count 2 2006.210.07:56:39.70#ibcon#read 4, iclass 30, count 2 2006.210.07:56:39.70#ibcon#about to read 5, iclass 30, count 2 2006.210.07:56:39.70#ibcon#read 5, iclass 30, count 2 2006.210.07:56:39.70#ibcon#about to read 6, iclass 30, count 2 2006.210.07:56:39.70#ibcon#read 6, iclass 30, count 2 2006.210.07:56:39.70#ibcon#end of sib2, iclass 30, count 2 2006.210.07:56:39.70#ibcon#*after write, iclass 30, count 2 2006.210.07:56:39.70#ibcon#*before return 0, iclass 30, count 2 2006.210.07:56:39.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:56:39.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.07:56:39.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.07:56:39.70#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:39.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:56:39.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:56:39.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:56:39.82#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:56:39.82#ibcon#first serial, iclass 30, count 0 2006.210.07:56:39.82#ibcon#enter sib2, iclass 30, count 0 2006.210.07:56:39.82#ibcon#flushed, iclass 30, count 0 2006.210.07:56:39.82#ibcon#about to write, iclass 30, count 0 2006.210.07:56:39.82#ibcon#wrote, iclass 30, count 0 2006.210.07:56:39.82#ibcon#about to read 3, iclass 30, count 0 2006.210.07:56:39.84#ibcon#read 3, iclass 30, count 0 2006.210.07:56:39.84#ibcon#about to read 4, iclass 30, count 0 2006.210.07:56:39.84#ibcon#read 4, iclass 30, count 0 2006.210.07:56:39.84#ibcon#about to read 5, iclass 30, count 0 2006.210.07:56:39.84#ibcon#read 5, iclass 30, count 0 2006.210.07:56:39.84#ibcon#about to read 6, iclass 30, count 0 2006.210.07:56:39.84#ibcon#read 6, iclass 30, count 0 2006.210.07:56:39.84#ibcon#end of sib2, iclass 30, count 0 2006.210.07:56:39.84#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:56:39.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:56:39.84#ibcon#[25=USB\r\n] 2006.210.07:56:39.84#ibcon#*before write, iclass 30, count 0 2006.210.07:56:39.84#ibcon#enter sib2, iclass 30, count 0 2006.210.07:56:39.84#ibcon#flushed, iclass 30, count 0 2006.210.07:56:39.84#ibcon#about to write, iclass 30, count 0 2006.210.07:56:39.84#ibcon#wrote, iclass 30, count 0 2006.210.07:56:39.84#ibcon#about to read 3, iclass 30, count 0 2006.210.07:56:39.87#ibcon#read 3, iclass 30, count 0 2006.210.07:56:39.87#ibcon#about to read 4, iclass 30, count 0 2006.210.07:56:39.87#ibcon#read 4, iclass 30, count 0 2006.210.07:56:39.87#ibcon#about to read 5, iclass 30, count 0 2006.210.07:56:39.87#ibcon#read 5, iclass 30, count 0 2006.210.07:56:39.87#ibcon#about to read 6, iclass 30, count 0 2006.210.07:56:39.87#ibcon#read 6, iclass 30, count 0 2006.210.07:56:39.87#ibcon#end of sib2, iclass 30, count 0 2006.210.07:56:39.87#ibcon#*after write, iclass 30, count 0 2006.210.07:56:39.87#ibcon#*before return 0, iclass 30, count 0 2006.210.07:56:39.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:56:39.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.07:56:39.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:56:39.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:56:39.87$vc4f8/valo=8,852.99 2006.210.07:56:39.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.07:56:39.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.07:56:39.87#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:39.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:56:39.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:56:39.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:56:39.87#ibcon#enter wrdev, iclass 32, count 0 2006.210.07:56:39.87#ibcon#first serial, iclass 32, count 0 2006.210.07:56:39.87#ibcon#enter sib2, iclass 32, count 0 2006.210.07:56:39.87#ibcon#flushed, iclass 32, count 0 2006.210.07:56:39.87#ibcon#about to write, iclass 32, count 0 2006.210.07:56:39.87#ibcon#wrote, iclass 32, count 0 2006.210.07:56:39.87#ibcon#about to read 3, iclass 32, count 0 2006.210.07:56:39.89#ibcon#read 3, iclass 32, count 0 2006.210.07:56:39.89#ibcon#about to read 4, iclass 32, count 0 2006.210.07:56:39.89#ibcon#read 4, iclass 32, count 0 2006.210.07:56:39.89#ibcon#about to read 5, iclass 32, count 0 2006.210.07:56:39.89#ibcon#read 5, iclass 32, count 0 2006.210.07:56:39.89#ibcon#about to read 6, iclass 32, count 0 2006.210.07:56:39.89#ibcon#read 6, iclass 32, count 0 2006.210.07:56:39.89#ibcon#end of sib2, iclass 32, count 0 2006.210.07:56:39.89#ibcon#*mode == 0, iclass 32, count 0 2006.210.07:56:39.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.07:56:39.89#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.07:56:39.89#ibcon#*before write, iclass 32, count 0 2006.210.07:56:39.89#ibcon#enter sib2, iclass 32, count 0 2006.210.07:56:39.89#ibcon#flushed, iclass 32, count 0 2006.210.07:56:39.89#ibcon#about to write, iclass 32, count 0 2006.210.07:56:39.89#ibcon#wrote, iclass 32, count 0 2006.210.07:56:39.89#ibcon#about to read 3, iclass 32, count 0 2006.210.07:56:39.93#ibcon#read 3, iclass 32, count 0 2006.210.07:56:39.93#ibcon#about to read 4, iclass 32, count 0 2006.210.07:56:39.93#ibcon#read 4, iclass 32, count 0 2006.210.07:56:39.93#ibcon#about to read 5, iclass 32, count 0 2006.210.07:56:39.93#ibcon#read 5, iclass 32, count 0 2006.210.07:56:39.93#ibcon#about to read 6, iclass 32, count 0 2006.210.07:56:39.93#ibcon#read 6, iclass 32, count 0 2006.210.07:56:39.93#ibcon#end of sib2, iclass 32, count 0 2006.210.07:56:39.93#ibcon#*after write, iclass 32, count 0 2006.210.07:56:39.93#ibcon#*before return 0, iclass 32, count 0 2006.210.07:56:39.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:56:39.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.07:56:39.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.07:56:39.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.07:56:39.93$vc4f8/va=8,7 2006.210.07:56:39.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.07:56:39.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.07:56:39.93#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:39.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:56:39.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:56:39.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:56:39.99#ibcon#enter wrdev, iclass 34, count 2 2006.210.07:56:39.99#ibcon#first serial, iclass 34, count 2 2006.210.07:56:39.99#ibcon#enter sib2, iclass 34, count 2 2006.210.07:56:39.99#ibcon#flushed, iclass 34, count 2 2006.210.07:56:39.99#ibcon#about to write, iclass 34, count 2 2006.210.07:56:39.99#ibcon#wrote, iclass 34, count 2 2006.210.07:56:39.99#ibcon#about to read 3, iclass 34, count 2 2006.210.07:56:40.01#ibcon#read 3, iclass 34, count 2 2006.210.07:56:40.01#ibcon#about to read 4, iclass 34, count 2 2006.210.07:56:40.01#ibcon#read 4, iclass 34, count 2 2006.210.07:56:40.01#ibcon#about to read 5, iclass 34, count 2 2006.210.07:56:40.01#ibcon#read 5, iclass 34, count 2 2006.210.07:56:40.01#ibcon#about to read 6, iclass 34, count 2 2006.210.07:56:40.01#ibcon#read 6, iclass 34, count 2 2006.210.07:56:40.01#ibcon#end of sib2, iclass 34, count 2 2006.210.07:56:40.01#ibcon#*mode == 0, iclass 34, count 2 2006.210.07:56:40.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.07:56:40.01#ibcon#[25=AT08-07\r\n] 2006.210.07:56:40.01#ibcon#*before write, iclass 34, count 2 2006.210.07:56:40.01#ibcon#enter sib2, iclass 34, count 2 2006.210.07:56:40.01#ibcon#flushed, iclass 34, count 2 2006.210.07:56:40.01#ibcon#about to write, iclass 34, count 2 2006.210.07:56:40.01#ibcon#wrote, iclass 34, count 2 2006.210.07:56:40.01#ibcon#about to read 3, iclass 34, count 2 2006.210.07:56:40.04#ibcon#read 3, iclass 34, count 2 2006.210.07:56:40.04#ibcon#about to read 4, iclass 34, count 2 2006.210.07:56:40.04#ibcon#read 4, iclass 34, count 2 2006.210.07:56:40.04#ibcon#about to read 5, iclass 34, count 2 2006.210.07:56:40.04#ibcon#read 5, iclass 34, count 2 2006.210.07:56:40.04#ibcon#about to read 6, iclass 34, count 2 2006.210.07:56:40.04#ibcon#read 6, iclass 34, count 2 2006.210.07:56:40.04#ibcon#end of sib2, iclass 34, count 2 2006.210.07:56:40.04#ibcon#*after write, iclass 34, count 2 2006.210.07:56:40.04#ibcon#*before return 0, iclass 34, count 2 2006.210.07:56:40.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:56:40.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.07:56:40.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.07:56:40.04#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:40.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:56:40.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:56:40.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:56:40.16#ibcon#enter wrdev, iclass 34, count 0 2006.210.07:56:40.16#ibcon#first serial, iclass 34, count 0 2006.210.07:56:40.16#ibcon#enter sib2, iclass 34, count 0 2006.210.07:56:40.16#ibcon#flushed, iclass 34, count 0 2006.210.07:56:40.16#ibcon#about to write, iclass 34, count 0 2006.210.07:56:40.16#ibcon#wrote, iclass 34, count 0 2006.210.07:56:40.16#ibcon#about to read 3, iclass 34, count 0 2006.210.07:56:40.18#ibcon#read 3, iclass 34, count 0 2006.210.07:56:40.18#ibcon#about to read 4, iclass 34, count 0 2006.210.07:56:40.18#ibcon#read 4, iclass 34, count 0 2006.210.07:56:40.18#ibcon#about to read 5, iclass 34, count 0 2006.210.07:56:40.18#ibcon#read 5, iclass 34, count 0 2006.210.07:56:40.18#ibcon#about to read 6, iclass 34, count 0 2006.210.07:56:40.18#ibcon#read 6, iclass 34, count 0 2006.210.07:56:40.18#ibcon#end of sib2, iclass 34, count 0 2006.210.07:56:40.18#ibcon#*mode == 0, iclass 34, count 0 2006.210.07:56:40.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.07:56:40.18#ibcon#[25=USB\r\n] 2006.210.07:56:40.18#ibcon#*before write, iclass 34, count 0 2006.210.07:56:40.18#ibcon#enter sib2, iclass 34, count 0 2006.210.07:56:40.18#ibcon#flushed, iclass 34, count 0 2006.210.07:56:40.18#ibcon#about to write, iclass 34, count 0 2006.210.07:56:40.18#ibcon#wrote, iclass 34, count 0 2006.210.07:56:40.18#ibcon#about to read 3, iclass 34, count 0 2006.210.07:56:40.21#ibcon#read 3, iclass 34, count 0 2006.210.07:56:40.21#ibcon#about to read 4, iclass 34, count 0 2006.210.07:56:40.21#ibcon#read 4, iclass 34, count 0 2006.210.07:56:40.21#ibcon#about to read 5, iclass 34, count 0 2006.210.07:56:40.21#ibcon#read 5, iclass 34, count 0 2006.210.07:56:40.21#ibcon#about to read 6, iclass 34, count 0 2006.210.07:56:40.21#ibcon#read 6, iclass 34, count 0 2006.210.07:56:40.21#ibcon#end of sib2, iclass 34, count 0 2006.210.07:56:40.21#ibcon#*after write, iclass 34, count 0 2006.210.07:56:40.21#ibcon#*before return 0, iclass 34, count 0 2006.210.07:56:40.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:56:40.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.07:56:40.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.07:56:40.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.07:56:40.21$vc4f8/vblo=1,632.99 2006.210.07:56:40.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.07:56:40.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.07:56:40.21#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:40.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:56:40.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:56:40.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:56:40.21#ibcon#enter wrdev, iclass 36, count 0 2006.210.07:56:40.21#ibcon#first serial, iclass 36, count 0 2006.210.07:56:40.21#ibcon#enter sib2, iclass 36, count 0 2006.210.07:56:40.21#ibcon#flushed, iclass 36, count 0 2006.210.07:56:40.21#ibcon#about to write, iclass 36, count 0 2006.210.07:56:40.21#ibcon#wrote, iclass 36, count 0 2006.210.07:56:40.21#ibcon#about to read 3, iclass 36, count 0 2006.210.07:56:40.23#ibcon#read 3, iclass 36, count 0 2006.210.07:56:40.23#ibcon#about to read 4, iclass 36, count 0 2006.210.07:56:40.23#ibcon#read 4, iclass 36, count 0 2006.210.07:56:40.23#ibcon#about to read 5, iclass 36, count 0 2006.210.07:56:40.23#ibcon#read 5, iclass 36, count 0 2006.210.07:56:40.23#ibcon#about to read 6, iclass 36, count 0 2006.210.07:56:40.23#ibcon#read 6, iclass 36, count 0 2006.210.07:56:40.23#ibcon#end of sib2, iclass 36, count 0 2006.210.07:56:40.23#ibcon#*mode == 0, iclass 36, count 0 2006.210.07:56:40.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.07:56:40.23#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.07:56:40.23#ibcon#*before write, iclass 36, count 0 2006.210.07:56:40.23#ibcon#enter sib2, iclass 36, count 0 2006.210.07:56:40.23#ibcon#flushed, iclass 36, count 0 2006.210.07:56:40.23#ibcon#about to write, iclass 36, count 0 2006.210.07:56:40.23#ibcon#wrote, iclass 36, count 0 2006.210.07:56:40.23#ibcon#about to read 3, iclass 36, count 0 2006.210.07:56:40.27#ibcon#read 3, iclass 36, count 0 2006.210.07:56:40.27#ibcon#about to read 4, iclass 36, count 0 2006.210.07:56:40.27#ibcon#read 4, iclass 36, count 0 2006.210.07:56:40.27#ibcon#about to read 5, iclass 36, count 0 2006.210.07:56:40.27#ibcon#read 5, iclass 36, count 0 2006.210.07:56:40.27#ibcon#about to read 6, iclass 36, count 0 2006.210.07:56:40.27#ibcon#read 6, iclass 36, count 0 2006.210.07:56:40.27#ibcon#end of sib2, iclass 36, count 0 2006.210.07:56:40.27#ibcon#*after write, iclass 36, count 0 2006.210.07:56:40.27#ibcon#*before return 0, iclass 36, count 0 2006.210.07:56:40.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:56:40.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.07:56:40.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.07:56:40.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.07:56:40.27$vc4f8/vb=1,4 2006.210.07:56:40.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.07:56:40.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.07:56:40.27#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:40.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:56:40.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:56:40.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:56:40.27#ibcon#enter wrdev, iclass 38, count 2 2006.210.07:56:40.27#ibcon#first serial, iclass 38, count 2 2006.210.07:56:40.27#ibcon#enter sib2, iclass 38, count 2 2006.210.07:56:40.27#ibcon#flushed, iclass 38, count 2 2006.210.07:56:40.27#ibcon#about to write, iclass 38, count 2 2006.210.07:56:40.27#ibcon#wrote, iclass 38, count 2 2006.210.07:56:40.27#ibcon#about to read 3, iclass 38, count 2 2006.210.07:56:40.29#ibcon#read 3, iclass 38, count 2 2006.210.07:56:40.29#ibcon#about to read 4, iclass 38, count 2 2006.210.07:56:40.29#ibcon#read 4, iclass 38, count 2 2006.210.07:56:40.29#ibcon#about to read 5, iclass 38, count 2 2006.210.07:56:40.29#ibcon#read 5, iclass 38, count 2 2006.210.07:56:40.29#ibcon#about to read 6, iclass 38, count 2 2006.210.07:56:40.29#ibcon#read 6, iclass 38, count 2 2006.210.07:56:40.29#ibcon#end of sib2, iclass 38, count 2 2006.210.07:56:40.29#ibcon#*mode == 0, iclass 38, count 2 2006.210.07:56:40.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.07:56:40.29#ibcon#[27=AT01-04\r\n] 2006.210.07:56:40.29#ibcon#*before write, iclass 38, count 2 2006.210.07:56:40.29#ibcon#enter sib2, iclass 38, count 2 2006.210.07:56:40.29#ibcon#flushed, iclass 38, count 2 2006.210.07:56:40.29#ibcon#about to write, iclass 38, count 2 2006.210.07:56:40.29#ibcon#wrote, iclass 38, count 2 2006.210.07:56:40.29#ibcon#about to read 3, iclass 38, count 2 2006.210.07:56:40.32#ibcon#read 3, iclass 38, count 2 2006.210.07:56:40.32#ibcon#about to read 4, iclass 38, count 2 2006.210.07:56:40.32#ibcon#read 4, iclass 38, count 2 2006.210.07:56:40.32#ibcon#about to read 5, iclass 38, count 2 2006.210.07:56:40.32#ibcon#read 5, iclass 38, count 2 2006.210.07:56:40.32#ibcon#about to read 6, iclass 38, count 2 2006.210.07:56:40.32#ibcon#read 6, iclass 38, count 2 2006.210.07:56:40.32#ibcon#end of sib2, iclass 38, count 2 2006.210.07:56:40.32#ibcon#*after write, iclass 38, count 2 2006.210.07:56:40.32#ibcon#*before return 0, iclass 38, count 2 2006.210.07:56:40.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:56:40.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.07:56:40.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.07:56:40.32#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:40.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:56:40.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:56:40.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:56:40.44#ibcon#enter wrdev, iclass 38, count 0 2006.210.07:56:40.44#ibcon#first serial, iclass 38, count 0 2006.210.07:56:40.44#ibcon#enter sib2, iclass 38, count 0 2006.210.07:56:40.44#ibcon#flushed, iclass 38, count 0 2006.210.07:56:40.44#ibcon#about to write, iclass 38, count 0 2006.210.07:56:40.44#ibcon#wrote, iclass 38, count 0 2006.210.07:56:40.44#ibcon#about to read 3, iclass 38, count 0 2006.210.07:56:40.46#ibcon#read 3, iclass 38, count 0 2006.210.07:56:40.46#ibcon#about to read 4, iclass 38, count 0 2006.210.07:56:40.46#ibcon#read 4, iclass 38, count 0 2006.210.07:56:40.46#ibcon#about to read 5, iclass 38, count 0 2006.210.07:56:40.46#ibcon#read 5, iclass 38, count 0 2006.210.07:56:40.46#ibcon#about to read 6, iclass 38, count 0 2006.210.07:56:40.46#ibcon#read 6, iclass 38, count 0 2006.210.07:56:40.46#ibcon#end of sib2, iclass 38, count 0 2006.210.07:56:40.46#ibcon#*mode == 0, iclass 38, count 0 2006.210.07:56:40.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.07:56:40.46#ibcon#[27=USB\r\n] 2006.210.07:56:40.46#ibcon#*before write, iclass 38, count 0 2006.210.07:56:40.46#ibcon#enter sib2, iclass 38, count 0 2006.210.07:56:40.46#ibcon#flushed, iclass 38, count 0 2006.210.07:56:40.46#ibcon#about to write, iclass 38, count 0 2006.210.07:56:40.46#ibcon#wrote, iclass 38, count 0 2006.210.07:56:40.46#ibcon#about to read 3, iclass 38, count 0 2006.210.07:56:40.49#ibcon#read 3, iclass 38, count 0 2006.210.07:56:40.49#ibcon#about to read 4, iclass 38, count 0 2006.210.07:56:40.49#ibcon#read 4, iclass 38, count 0 2006.210.07:56:40.49#ibcon#about to read 5, iclass 38, count 0 2006.210.07:56:40.49#ibcon#read 5, iclass 38, count 0 2006.210.07:56:40.49#ibcon#about to read 6, iclass 38, count 0 2006.210.07:56:40.49#ibcon#read 6, iclass 38, count 0 2006.210.07:56:40.49#ibcon#end of sib2, iclass 38, count 0 2006.210.07:56:40.49#ibcon#*after write, iclass 38, count 0 2006.210.07:56:40.49#ibcon#*before return 0, iclass 38, count 0 2006.210.07:56:40.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:56:40.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.07:56:40.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.07:56:40.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.07:56:40.49$vc4f8/vblo=2,640.99 2006.210.07:56:40.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.07:56:40.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.07:56:40.49#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:40.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:40.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:40.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:40.49#ibcon#enter wrdev, iclass 40, count 0 2006.210.07:56:40.49#ibcon#first serial, iclass 40, count 0 2006.210.07:56:40.49#ibcon#enter sib2, iclass 40, count 0 2006.210.07:56:40.49#ibcon#flushed, iclass 40, count 0 2006.210.07:56:40.49#ibcon#about to write, iclass 40, count 0 2006.210.07:56:40.49#ibcon#wrote, iclass 40, count 0 2006.210.07:56:40.49#ibcon#about to read 3, iclass 40, count 0 2006.210.07:56:40.51#ibcon#read 3, iclass 40, count 0 2006.210.07:56:40.51#ibcon#about to read 4, iclass 40, count 0 2006.210.07:56:40.51#ibcon#read 4, iclass 40, count 0 2006.210.07:56:40.51#ibcon#about to read 5, iclass 40, count 0 2006.210.07:56:40.51#ibcon#read 5, iclass 40, count 0 2006.210.07:56:40.51#ibcon#about to read 6, iclass 40, count 0 2006.210.07:56:40.51#ibcon#read 6, iclass 40, count 0 2006.210.07:56:40.51#ibcon#end of sib2, iclass 40, count 0 2006.210.07:56:40.51#ibcon#*mode == 0, iclass 40, count 0 2006.210.07:56:40.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.07:56:40.51#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.07:56:40.51#ibcon#*before write, iclass 40, count 0 2006.210.07:56:40.51#ibcon#enter sib2, iclass 40, count 0 2006.210.07:56:40.51#ibcon#flushed, iclass 40, count 0 2006.210.07:56:40.51#ibcon#about to write, iclass 40, count 0 2006.210.07:56:40.51#ibcon#wrote, iclass 40, count 0 2006.210.07:56:40.51#ibcon#about to read 3, iclass 40, count 0 2006.210.07:56:40.55#ibcon#read 3, iclass 40, count 0 2006.210.07:56:40.55#ibcon#about to read 4, iclass 40, count 0 2006.210.07:56:40.55#ibcon#read 4, iclass 40, count 0 2006.210.07:56:40.55#ibcon#about to read 5, iclass 40, count 0 2006.210.07:56:40.55#ibcon#read 5, iclass 40, count 0 2006.210.07:56:40.55#ibcon#about to read 6, iclass 40, count 0 2006.210.07:56:40.55#ibcon#read 6, iclass 40, count 0 2006.210.07:56:40.55#ibcon#end of sib2, iclass 40, count 0 2006.210.07:56:40.55#ibcon#*after write, iclass 40, count 0 2006.210.07:56:40.55#ibcon#*before return 0, iclass 40, count 0 2006.210.07:56:40.55#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:40.55#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.07:56:40.55#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.07:56:40.55#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.07:56:40.55$vc4f8/vb=2,4 2006.210.07:56:40.55#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.07:56:40.55#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.07:56:40.55#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:40.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:40.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:40.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:40.61#ibcon#enter wrdev, iclass 4, count 2 2006.210.07:56:40.61#ibcon#first serial, iclass 4, count 2 2006.210.07:56:40.61#ibcon#enter sib2, iclass 4, count 2 2006.210.07:56:40.61#ibcon#flushed, iclass 4, count 2 2006.210.07:56:40.61#ibcon#about to write, iclass 4, count 2 2006.210.07:56:40.61#ibcon#wrote, iclass 4, count 2 2006.210.07:56:40.61#ibcon#about to read 3, iclass 4, count 2 2006.210.07:56:40.63#ibcon#read 3, iclass 4, count 2 2006.210.07:56:40.63#ibcon#about to read 4, iclass 4, count 2 2006.210.07:56:40.63#ibcon#read 4, iclass 4, count 2 2006.210.07:56:40.63#ibcon#about to read 5, iclass 4, count 2 2006.210.07:56:40.63#ibcon#read 5, iclass 4, count 2 2006.210.07:56:40.63#ibcon#about to read 6, iclass 4, count 2 2006.210.07:56:40.63#ibcon#read 6, iclass 4, count 2 2006.210.07:56:40.63#ibcon#end of sib2, iclass 4, count 2 2006.210.07:56:40.63#ibcon#*mode == 0, iclass 4, count 2 2006.210.07:56:40.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.07:56:40.63#ibcon#[27=AT02-04\r\n] 2006.210.07:56:40.63#ibcon#*before write, iclass 4, count 2 2006.210.07:56:40.63#ibcon#enter sib2, iclass 4, count 2 2006.210.07:56:40.63#ibcon#flushed, iclass 4, count 2 2006.210.07:56:40.63#ibcon#about to write, iclass 4, count 2 2006.210.07:56:40.63#ibcon#wrote, iclass 4, count 2 2006.210.07:56:40.63#ibcon#about to read 3, iclass 4, count 2 2006.210.07:56:40.66#ibcon#read 3, iclass 4, count 2 2006.210.07:56:40.66#ibcon#about to read 4, iclass 4, count 2 2006.210.07:56:40.66#ibcon#read 4, iclass 4, count 2 2006.210.07:56:40.66#ibcon#about to read 5, iclass 4, count 2 2006.210.07:56:40.66#ibcon#read 5, iclass 4, count 2 2006.210.07:56:40.66#ibcon#about to read 6, iclass 4, count 2 2006.210.07:56:40.66#ibcon#read 6, iclass 4, count 2 2006.210.07:56:40.66#ibcon#end of sib2, iclass 4, count 2 2006.210.07:56:40.66#ibcon#*after write, iclass 4, count 2 2006.210.07:56:40.66#ibcon#*before return 0, iclass 4, count 2 2006.210.07:56:40.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:40.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.07:56:40.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.07:56:40.66#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:40.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:40.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:40.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:40.78#ibcon#enter wrdev, iclass 4, count 0 2006.210.07:56:40.78#ibcon#first serial, iclass 4, count 0 2006.210.07:56:40.78#ibcon#enter sib2, iclass 4, count 0 2006.210.07:56:40.78#ibcon#flushed, iclass 4, count 0 2006.210.07:56:40.78#ibcon#about to write, iclass 4, count 0 2006.210.07:56:40.78#ibcon#wrote, iclass 4, count 0 2006.210.07:56:40.78#ibcon#about to read 3, iclass 4, count 0 2006.210.07:56:40.80#ibcon#read 3, iclass 4, count 0 2006.210.07:56:40.80#ibcon#about to read 4, iclass 4, count 0 2006.210.07:56:40.80#ibcon#read 4, iclass 4, count 0 2006.210.07:56:40.80#ibcon#about to read 5, iclass 4, count 0 2006.210.07:56:40.80#ibcon#read 5, iclass 4, count 0 2006.210.07:56:40.80#ibcon#about to read 6, iclass 4, count 0 2006.210.07:56:40.80#ibcon#read 6, iclass 4, count 0 2006.210.07:56:40.80#ibcon#end of sib2, iclass 4, count 0 2006.210.07:56:40.80#ibcon#*mode == 0, iclass 4, count 0 2006.210.07:56:40.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.07:56:40.80#ibcon#[27=USB\r\n] 2006.210.07:56:40.80#ibcon#*before write, iclass 4, count 0 2006.210.07:56:40.80#ibcon#enter sib2, iclass 4, count 0 2006.210.07:56:40.80#ibcon#flushed, iclass 4, count 0 2006.210.07:56:40.80#ibcon#about to write, iclass 4, count 0 2006.210.07:56:40.80#ibcon#wrote, iclass 4, count 0 2006.210.07:56:40.80#ibcon#about to read 3, iclass 4, count 0 2006.210.07:56:40.83#ibcon#read 3, iclass 4, count 0 2006.210.07:56:40.83#ibcon#about to read 4, iclass 4, count 0 2006.210.07:56:40.83#ibcon#read 4, iclass 4, count 0 2006.210.07:56:40.83#ibcon#about to read 5, iclass 4, count 0 2006.210.07:56:40.83#ibcon#read 5, iclass 4, count 0 2006.210.07:56:40.83#ibcon#about to read 6, iclass 4, count 0 2006.210.07:56:40.83#ibcon#read 6, iclass 4, count 0 2006.210.07:56:40.83#ibcon#end of sib2, iclass 4, count 0 2006.210.07:56:40.83#ibcon#*after write, iclass 4, count 0 2006.210.07:56:40.83#ibcon#*before return 0, iclass 4, count 0 2006.210.07:56:40.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:40.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.07:56:40.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.07:56:40.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.07:56:40.83$vc4f8/vblo=3,656.99 2006.210.07:56:40.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.07:56:40.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.07:56:40.83#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:40.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:40.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:40.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:40.83#ibcon#enter wrdev, iclass 6, count 0 2006.210.07:56:40.83#ibcon#first serial, iclass 6, count 0 2006.210.07:56:40.83#ibcon#enter sib2, iclass 6, count 0 2006.210.07:56:40.83#ibcon#flushed, iclass 6, count 0 2006.210.07:56:40.83#ibcon#about to write, iclass 6, count 0 2006.210.07:56:40.83#ibcon#wrote, iclass 6, count 0 2006.210.07:56:40.83#ibcon#about to read 3, iclass 6, count 0 2006.210.07:56:40.85#ibcon#read 3, iclass 6, count 0 2006.210.07:56:40.85#ibcon#about to read 4, iclass 6, count 0 2006.210.07:56:40.85#ibcon#read 4, iclass 6, count 0 2006.210.07:56:40.85#ibcon#about to read 5, iclass 6, count 0 2006.210.07:56:40.85#ibcon#read 5, iclass 6, count 0 2006.210.07:56:40.85#ibcon#about to read 6, iclass 6, count 0 2006.210.07:56:40.85#ibcon#read 6, iclass 6, count 0 2006.210.07:56:40.85#ibcon#end of sib2, iclass 6, count 0 2006.210.07:56:40.85#ibcon#*mode == 0, iclass 6, count 0 2006.210.07:56:40.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.07:56:40.85#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.07:56:40.85#ibcon#*before write, iclass 6, count 0 2006.210.07:56:40.85#ibcon#enter sib2, iclass 6, count 0 2006.210.07:56:40.85#ibcon#flushed, iclass 6, count 0 2006.210.07:56:40.85#ibcon#about to write, iclass 6, count 0 2006.210.07:56:40.85#ibcon#wrote, iclass 6, count 0 2006.210.07:56:40.85#ibcon#about to read 3, iclass 6, count 0 2006.210.07:56:40.89#ibcon#read 3, iclass 6, count 0 2006.210.07:56:40.89#ibcon#about to read 4, iclass 6, count 0 2006.210.07:56:40.89#ibcon#read 4, iclass 6, count 0 2006.210.07:56:40.89#ibcon#about to read 5, iclass 6, count 0 2006.210.07:56:40.89#ibcon#read 5, iclass 6, count 0 2006.210.07:56:40.89#ibcon#about to read 6, iclass 6, count 0 2006.210.07:56:40.89#ibcon#read 6, iclass 6, count 0 2006.210.07:56:40.89#ibcon#end of sib2, iclass 6, count 0 2006.210.07:56:40.89#ibcon#*after write, iclass 6, count 0 2006.210.07:56:40.89#ibcon#*before return 0, iclass 6, count 0 2006.210.07:56:40.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:40.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.07:56:40.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.07:56:40.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.07:56:40.89$vc4f8/vb=3,3 2006.210.07:56:40.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.07:56:40.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.07:56:40.89#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:40.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:40.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:40.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:40.95#ibcon#enter wrdev, iclass 10, count 2 2006.210.07:56:40.95#ibcon#first serial, iclass 10, count 2 2006.210.07:56:40.95#ibcon#enter sib2, iclass 10, count 2 2006.210.07:56:40.95#ibcon#flushed, iclass 10, count 2 2006.210.07:56:40.95#ibcon#about to write, iclass 10, count 2 2006.210.07:56:40.95#ibcon#wrote, iclass 10, count 2 2006.210.07:56:40.95#ibcon#about to read 3, iclass 10, count 2 2006.210.07:56:40.97#ibcon#read 3, iclass 10, count 2 2006.210.07:56:40.97#ibcon#about to read 4, iclass 10, count 2 2006.210.07:56:40.97#ibcon#read 4, iclass 10, count 2 2006.210.07:56:40.97#ibcon#about to read 5, iclass 10, count 2 2006.210.07:56:40.97#ibcon#read 5, iclass 10, count 2 2006.210.07:56:40.97#ibcon#about to read 6, iclass 10, count 2 2006.210.07:56:40.97#ibcon#read 6, iclass 10, count 2 2006.210.07:56:40.97#ibcon#end of sib2, iclass 10, count 2 2006.210.07:56:40.97#ibcon#*mode == 0, iclass 10, count 2 2006.210.07:56:40.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.07:56:40.97#ibcon#[27=AT03-03\r\n] 2006.210.07:56:40.97#ibcon#*before write, iclass 10, count 2 2006.210.07:56:40.97#ibcon#enter sib2, iclass 10, count 2 2006.210.07:56:40.97#ibcon#flushed, iclass 10, count 2 2006.210.07:56:40.97#ibcon#about to write, iclass 10, count 2 2006.210.07:56:40.97#ibcon#wrote, iclass 10, count 2 2006.210.07:56:40.97#ibcon#about to read 3, iclass 10, count 2 2006.210.07:56:41.00#ibcon#read 3, iclass 10, count 2 2006.210.07:56:41.00#ibcon#about to read 4, iclass 10, count 2 2006.210.07:56:41.00#ibcon#read 4, iclass 10, count 2 2006.210.07:56:41.00#ibcon#about to read 5, iclass 10, count 2 2006.210.07:56:41.00#ibcon#read 5, iclass 10, count 2 2006.210.07:56:41.00#ibcon#about to read 6, iclass 10, count 2 2006.210.07:56:41.00#ibcon#read 6, iclass 10, count 2 2006.210.07:56:41.00#ibcon#end of sib2, iclass 10, count 2 2006.210.07:56:41.00#ibcon#*after write, iclass 10, count 2 2006.210.07:56:41.00#ibcon#*before return 0, iclass 10, count 2 2006.210.07:56:41.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:41.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.07:56:41.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.07:56:41.00#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:41.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:41.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:41.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:41.12#ibcon#enter wrdev, iclass 10, count 0 2006.210.07:56:41.12#ibcon#first serial, iclass 10, count 0 2006.210.07:56:41.12#ibcon#enter sib2, iclass 10, count 0 2006.210.07:56:41.12#ibcon#flushed, iclass 10, count 0 2006.210.07:56:41.12#ibcon#about to write, iclass 10, count 0 2006.210.07:56:41.12#ibcon#wrote, iclass 10, count 0 2006.210.07:56:41.12#ibcon#about to read 3, iclass 10, count 0 2006.210.07:56:41.14#ibcon#read 3, iclass 10, count 0 2006.210.07:56:41.14#ibcon#about to read 4, iclass 10, count 0 2006.210.07:56:41.14#ibcon#read 4, iclass 10, count 0 2006.210.07:56:41.14#ibcon#about to read 5, iclass 10, count 0 2006.210.07:56:41.14#ibcon#read 5, iclass 10, count 0 2006.210.07:56:41.14#ibcon#about to read 6, iclass 10, count 0 2006.210.07:56:41.14#ibcon#read 6, iclass 10, count 0 2006.210.07:56:41.14#ibcon#end of sib2, iclass 10, count 0 2006.210.07:56:41.14#ibcon#*mode == 0, iclass 10, count 0 2006.210.07:56:41.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.07:56:41.14#ibcon#[27=USB\r\n] 2006.210.07:56:41.14#ibcon#*before write, iclass 10, count 0 2006.210.07:56:41.14#ibcon#enter sib2, iclass 10, count 0 2006.210.07:56:41.14#ibcon#flushed, iclass 10, count 0 2006.210.07:56:41.14#ibcon#about to write, iclass 10, count 0 2006.210.07:56:41.14#ibcon#wrote, iclass 10, count 0 2006.210.07:56:41.14#ibcon#about to read 3, iclass 10, count 0 2006.210.07:56:41.17#ibcon#read 3, iclass 10, count 0 2006.210.07:56:41.17#ibcon#about to read 4, iclass 10, count 0 2006.210.07:56:41.17#ibcon#read 4, iclass 10, count 0 2006.210.07:56:41.17#ibcon#about to read 5, iclass 10, count 0 2006.210.07:56:41.17#ibcon#read 5, iclass 10, count 0 2006.210.07:56:41.17#ibcon#about to read 6, iclass 10, count 0 2006.210.07:56:41.17#ibcon#read 6, iclass 10, count 0 2006.210.07:56:41.17#ibcon#end of sib2, iclass 10, count 0 2006.210.07:56:41.17#ibcon#*after write, iclass 10, count 0 2006.210.07:56:41.17#ibcon#*before return 0, iclass 10, count 0 2006.210.07:56:41.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:41.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.07:56:41.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.07:56:41.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.07:56:41.17$vc4f8/vblo=4,712.99 2006.210.07:56:41.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.07:56:41.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.07:56:41.17#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:41.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:41.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:41.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:41.17#ibcon#enter wrdev, iclass 12, count 0 2006.210.07:56:41.17#ibcon#first serial, iclass 12, count 0 2006.210.07:56:41.17#ibcon#enter sib2, iclass 12, count 0 2006.210.07:56:41.17#ibcon#flushed, iclass 12, count 0 2006.210.07:56:41.17#ibcon#about to write, iclass 12, count 0 2006.210.07:56:41.17#ibcon#wrote, iclass 12, count 0 2006.210.07:56:41.17#ibcon#about to read 3, iclass 12, count 0 2006.210.07:56:41.19#ibcon#read 3, iclass 12, count 0 2006.210.07:56:41.19#ibcon#about to read 4, iclass 12, count 0 2006.210.07:56:41.19#ibcon#read 4, iclass 12, count 0 2006.210.07:56:41.19#ibcon#about to read 5, iclass 12, count 0 2006.210.07:56:41.19#ibcon#read 5, iclass 12, count 0 2006.210.07:56:41.19#ibcon#about to read 6, iclass 12, count 0 2006.210.07:56:41.19#ibcon#read 6, iclass 12, count 0 2006.210.07:56:41.19#ibcon#end of sib2, iclass 12, count 0 2006.210.07:56:41.19#ibcon#*mode == 0, iclass 12, count 0 2006.210.07:56:41.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.07:56:41.19#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.07:56:41.19#ibcon#*before write, iclass 12, count 0 2006.210.07:56:41.19#ibcon#enter sib2, iclass 12, count 0 2006.210.07:56:41.19#ibcon#flushed, iclass 12, count 0 2006.210.07:56:41.19#ibcon#about to write, iclass 12, count 0 2006.210.07:56:41.19#ibcon#wrote, iclass 12, count 0 2006.210.07:56:41.19#ibcon#about to read 3, iclass 12, count 0 2006.210.07:56:41.23#ibcon#read 3, iclass 12, count 0 2006.210.07:56:41.23#ibcon#about to read 4, iclass 12, count 0 2006.210.07:56:41.23#ibcon#read 4, iclass 12, count 0 2006.210.07:56:41.23#ibcon#about to read 5, iclass 12, count 0 2006.210.07:56:41.23#ibcon#read 5, iclass 12, count 0 2006.210.07:56:41.23#ibcon#about to read 6, iclass 12, count 0 2006.210.07:56:41.23#ibcon#read 6, iclass 12, count 0 2006.210.07:56:41.23#ibcon#end of sib2, iclass 12, count 0 2006.210.07:56:41.23#ibcon#*after write, iclass 12, count 0 2006.210.07:56:41.23#ibcon#*before return 0, iclass 12, count 0 2006.210.07:56:41.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:41.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.07:56:41.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.07:56:41.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.07:56:41.23$vc4f8/vb=4,3 2006.210.07:56:41.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.07:56:41.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.07:56:41.23#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:41.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:41.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:41.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:41.29#ibcon#enter wrdev, iclass 14, count 2 2006.210.07:56:41.29#ibcon#first serial, iclass 14, count 2 2006.210.07:56:41.29#ibcon#enter sib2, iclass 14, count 2 2006.210.07:56:41.29#ibcon#flushed, iclass 14, count 2 2006.210.07:56:41.29#ibcon#about to write, iclass 14, count 2 2006.210.07:56:41.29#ibcon#wrote, iclass 14, count 2 2006.210.07:56:41.29#ibcon#about to read 3, iclass 14, count 2 2006.210.07:56:41.31#ibcon#read 3, iclass 14, count 2 2006.210.07:56:41.31#ibcon#about to read 4, iclass 14, count 2 2006.210.07:56:41.31#ibcon#read 4, iclass 14, count 2 2006.210.07:56:41.31#ibcon#about to read 5, iclass 14, count 2 2006.210.07:56:41.31#ibcon#read 5, iclass 14, count 2 2006.210.07:56:41.31#ibcon#about to read 6, iclass 14, count 2 2006.210.07:56:41.31#ibcon#read 6, iclass 14, count 2 2006.210.07:56:41.31#ibcon#end of sib2, iclass 14, count 2 2006.210.07:56:41.31#ibcon#*mode == 0, iclass 14, count 2 2006.210.07:56:41.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.07:56:41.31#ibcon#[27=AT04-03\r\n] 2006.210.07:56:41.31#ibcon#*before write, iclass 14, count 2 2006.210.07:56:41.31#ibcon#enter sib2, iclass 14, count 2 2006.210.07:56:41.31#ibcon#flushed, iclass 14, count 2 2006.210.07:56:41.31#ibcon#about to write, iclass 14, count 2 2006.210.07:56:41.31#ibcon#wrote, iclass 14, count 2 2006.210.07:56:41.31#ibcon#about to read 3, iclass 14, count 2 2006.210.07:56:41.34#ibcon#read 3, iclass 14, count 2 2006.210.07:56:41.34#ibcon#about to read 4, iclass 14, count 2 2006.210.07:56:41.34#ibcon#read 4, iclass 14, count 2 2006.210.07:56:41.34#ibcon#about to read 5, iclass 14, count 2 2006.210.07:56:41.34#ibcon#read 5, iclass 14, count 2 2006.210.07:56:41.34#ibcon#about to read 6, iclass 14, count 2 2006.210.07:56:41.34#ibcon#read 6, iclass 14, count 2 2006.210.07:56:41.34#ibcon#end of sib2, iclass 14, count 2 2006.210.07:56:41.34#ibcon#*after write, iclass 14, count 2 2006.210.07:56:41.34#ibcon#*before return 0, iclass 14, count 2 2006.210.07:56:41.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:41.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.07:56:41.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.07:56:41.34#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:41.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:41.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:41.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:41.46#ibcon#enter wrdev, iclass 14, count 0 2006.210.07:56:41.46#ibcon#first serial, iclass 14, count 0 2006.210.07:56:41.46#ibcon#enter sib2, iclass 14, count 0 2006.210.07:56:41.46#ibcon#flushed, iclass 14, count 0 2006.210.07:56:41.46#ibcon#about to write, iclass 14, count 0 2006.210.07:56:41.46#ibcon#wrote, iclass 14, count 0 2006.210.07:56:41.46#ibcon#about to read 3, iclass 14, count 0 2006.210.07:56:41.48#ibcon#read 3, iclass 14, count 0 2006.210.07:56:41.48#ibcon#about to read 4, iclass 14, count 0 2006.210.07:56:41.48#ibcon#read 4, iclass 14, count 0 2006.210.07:56:41.48#ibcon#about to read 5, iclass 14, count 0 2006.210.07:56:41.48#ibcon#read 5, iclass 14, count 0 2006.210.07:56:41.48#ibcon#about to read 6, iclass 14, count 0 2006.210.07:56:41.48#ibcon#read 6, iclass 14, count 0 2006.210.07:56:41.48#ibcon#end of sib2, iclass 14, count 0 2006.210.07:56:41.48#ibcon#*mode == 0, iclass 14, count 0 2006.210.07:56:41.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.07:56:41.48#ibcon#[27=USB\r\n] 2006.210.07:56:41.48#ibcon#*before write, iclass 14, count 0 2006.210.07:56:41.48#ibcon#enter sib2, iclass 14, count 0 2006.210.07:56:41.48#ibcon#flushed, iclass 14, count 0 2006.210.07:56:41.48#ibcon#about to write, iclass 14, count 0 2006.210.07:56:41.48#ibcon#wrote, iclass 14, count 0 2006.210.07:56:41.48#ibcon#about to read 3, iclass 14, count 0 2006.210.07:56:41.51#ibcon#read 3, iclass 14, count 0 2006.210.07:56:41.51#ibcon#about to read 4, iclass 14, count 0 2006.210.07:56:41.51#ibcon#read 4, iclass 14, count 0 2006.210.07:56:41.51#ibcon#about to read 5, iclass 14, count 0 2006.210.07:56:41.51#ibcon#read 5, iclass 14, count 0 2006.210.07:56:41.51#ibcon#about to read 6, iclass 14, count 0 2006.210.07:56:41.51#ibcon#read 6, iclass 14, count 0 2006.210.07:56:41.51#ibcon#end of sib2, iclass 14, count 0 2006.210.07:56:41.51#ibcon#*after write, iclass 14, count 0 2006.210.07:56:41.51#ibcon#*before return 0, iclass 14, count 0 2006.210.07:56:41.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:41.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.07:56:41.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.07:56:41.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.07:56:41.51$vc4f8/vblo=5,744.99 2006.210.07:56:41.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.07:56:41.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.07:56:41.51#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:41.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:41.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:41.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:41.51#ibcon#enter wrdev, iclass 16, count 0 2006.210.07:56:41.51#ibcon#first serial, iclass 16, count 0 2006.210.07:56:41.51#ibcon#enter sib2, iclass 16, count 0 2006.210.07:56:41.51#ibcon#flushed, iclass 16, count 0 2006.210.07:56:41.51#ibcon#about to write, iclass 16, count 0 2006.210.07:56:41.51#ibcon#wrote, iclass 16, count 0 2006.210.07:56:41.51#ibcon#about to read 3, iclass 16, count 0 2006.210.07:56:41.53#ibcon#read 3, iclass 16, count 0 2006.210.07:56:41.53#ibcon#about to read 4, iclass 16, count 0 2006.210.07:56:41.53#ibcon#read 4, iclass 16, count 0 2006.210.07:56:41.53#ibcon#about to read 5, iclass 16, count 0 2006.210.07:56:41.53#ibcon#read 5, iclass 16, count 0 2006.210.07:56:41.53#ibcon#about to read 6, iclass 16, count 0 2006.210.07:56:41.53#ibcon#read 6, iclass 16, count 0 2006.210.07:56:41.53#ibcon#end of sib2, iclass 16, count 0 2006.210.07:56:41.53#ibcon#*mode == 0, iclass 16, count 0 2006.210.07:56:41.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.07:56:41.53#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.07:56:41.53#ibcon#*before write, iclass 16, count 0 2006.210.07:56:41.53#ibcon#enter sib2, iclass 16, count 0 2006.210.07:56:41.53#ibcon#flushed, iclass 16, count 0 2006.210.07:56:41.53#ibcon#about to write, iclass 16, count 0 2006.210.07:56:41.53#ibcon#wrote, iclass 16, count 0 2006.210.07:56:41.53#ibcon#about to read 3, iclass 16, count 0 2006.210.07:56:41.57#ibcon#read 3, iclass 16, count 0 2006.210.07:56:41.57#ibcon#about to read 4, iclass 16, count 0 2006.210.07:56:41.57#ibcon#read 4, iclass 16, count 0 2006.210.07:56:41.57#ibcon#about to read 5, iclass 16, count 0 2006.210.07:56:41.57#ibcon#read 5, iclass 16, count 0 2006.210.07:56:41.57#ibcon#about to read 6, iclass 16, count 0 2006.210.07:56:41.57#ibcon#read 6, iclass 16, count 0 2006.210.07:56:41.57#ibcon#end of sib2, iclass 16, count 0 2006.210.07:56:41.57#ibcon#*after write, iclass 16, count 0 2006.210.07:56:41.57#ibcon#*before return 0, iclass 16, count 0 2006.210.07:56:41.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:41.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.07:56:41.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.07:56:41.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.07:56:41.57$vc4f8/vb=5,3 2006.210.07:56:41.57#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.07:56:41.57#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.07:56:41.57#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:41.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:41.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:41.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:41.63#ibcon#enter wrdev, iclass 18, count 2 2006.210.07:56:41.63#ibcon#first serial, iclass 18, count 2 2006.210.07:56:41.63#ibcon#enter sib2, iclass 18, count 2 2006.210.07:56:41.63#ibcon#flushed, iclass 18, count 2 2006.210.07:56:41.63#ibcon#about to write, iclass 18, count 2 2006.210.07:56:41.63#ibcon#wrote, iclass 18, count 2 2006.210.07:56:41.63#ibcon#about to read 3, iclass 18, count 2 2006.210.07:56:41.65#ibcon#read 3, iclass 18, count 2 2006.210.07:56:41.65#ibcon#about to read 4, iclass 18, count 2 2006.210.07:56:41.65#ibcon#read 4, iclass 18, count 2 2006.210.07:56:41.65#ibcon#about to read 5, iclass 18, count 2 2006.210.07:56:41.65#ibcon#read 5, iclass 18, count 2 2006.210.07:56:41.65#ibcon#about to read 6, iclass 18, count 2 2006.210.07:56:41.65#ibcon#read 6, iclass 18, count 2 2006.210.07:56:41.65#ibcon#end of sib2, iclass 18, count 2 2006.210.07:56:41.65#ibcon#*mode == 0, iclass 18, count 2 2006.210.07:56:41.65#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.07:56:41.65#ibcon#[27=AT05-03\r\n] 2006.210.07:56:41.65#ibcon#*before write, iclass 18, count 2 2006.210.07:56:41.65#ibcon#enter sib2, iclass 18, count 2 2006.210.07:56:41.65#ibcon#flushed, iclass 18, count 2 2006.210.07:56:41.65#ibcon#about to write, iclass 18, count 2 2006.210.07:56:41.65#ibcon#wrote, iclass 18, count 2 2006.210.07:56:41.65#ibcon#about to read 3, iclass 18, count 2 2006.210.07:56:41.68#ibcon#read 3, iclass 18, count 2 2006.210.07:56:41.68#ibcon#about to read 4, iclass 18, count 2 2006.210.07:56:41.68#ibcon#read 4, iclass 18, count 2 2006.210.07:56:41.68#ibcon#about to read 5, iclass 18, count 2 2006.210.07:56:41.68#ibcon#read 5, iclass 18, count 2 2006.210.07:56:41.68#ibcon#about to read 6, iclass 18, count 2 2006.210.07:56:41.68#ibcon#read 6, iclass 18, count 2 2006.210.07:56:41.68#ibcon#end of sib2, iclass 18, count 2 2006.210.07:56:41.68#ibcon#*after write, iclass 18, count 2 2006.210.07:56:41.68#ibcon#*before return 0, iclass 18, count 2 2006.210.07:56:41.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:41.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.07:56:41.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.07:56:41.68#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:41.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:41.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:41.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:41.80#ibcon#enter wrdev, iclass 18, count 0 2006.210.07:56:41.80#ibcon#first serial, iclass 18, count 0 2006.210.07:56:41.80#ibcon#enter sib2, iclass 18, count 0 2006.210.07:56:41.80#ibcon#flushed, iclass 18, count 0 2006.210.07:56:41.80#ibcon#about to write, iclass 18, count 0 2006.210.07:56:41.80#ibcon#wrote, iclass 18, count 0 2006.210.07:56:41.80#ibcon#about to read 3, iclass 18, count 0 2006.210.07:56:41.82#ibcon#read 3, iclass 18, count 0 2006.210.07:56:41.82#ibcon#about to read 4, iclass 18, count 0 2006.210.07:56:41.82#ibcon#read 4, iclass 18, count 0 2006.210.07:56:41.82#ibcon#about to read 5, iclass 18, count 0 2006.210.07:56:41.82#ibcon#read 5, iclass 18, count 0 2006.210.07:56:41.82#ibcon#about to read 6, iclass 18, count 0 2006.210.07:56:41.82#ibcon#read 6, iclass 18, count 0 2006.210.07:56:41.82#ibcon#end of sib2, iclass 18, count 0 2006.210.07:56:41.82#ibcon#*mode == 0, iclass 18, count 0 2006.210.07:56:41.82#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.07:56:41.82#ibcon#[27=USB\r\n] 2006.210.07:56:41.82#ibcon#*before write, iclass 18, count 0 2006.210.07:56:41.82#ibcon#enter sib2, iclass 18, count 0 2006.210.07:56:41.82#ibcon#flushed, iclass 18, count 0 2006.210.07:56:41.82#ibcon#about to write, iclass 18, count 0 2006.210.07:56:41.82#ibcon#wrote, iclass 18, count 0 2006.210.07:56:41.82#ibcon#about to read 3, iclass 18, count 0 2006.210.07:56:41.85#ibcon#read 3, iclass 18, count 0 2006.210.07:56:41.85#ibcon#about to read 4, iclass 18, count 0 2006.210.07:56:41.85#ibcon#read 4, iclass 18, count 0 2006.210.07:56:41.85#ibcon#about to read 5, iclass 18, count 0 2006.210.07:56:41.85#ibcon#read 5, iclass 18, count 0 2006.210.07:56:41.85#ibcon#about to read 6, iclass 18, count 0 2006.210.07:56:41.85#ibcon#read 6, iclass 18, count 0 2006.210.07:56:41.85#ibcon#end of sib2, iclass 18, count 0 2006.210.07:56:41.85#ibcon#*after write, iclass 18, count 0 2006.210.07:56:41.85#ibcon#*before return 0, iclass 18, count 0 2006.210.07:56:41.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:41.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.07:56:41.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.07:56:41.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.07:56:41.85$vc4f8/vblo=6,752.99 2006.210.07:56:41.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.07:56:41.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.07:56:41.85#ibcon#ireg 17 cls_cnt 0 2006.210.07:56:41.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:41.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:41.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:41.85#ibcon#enter wrdev, iclass 20, count 0 2006.210.07:56:41.85#ibcon#first serial, iclass 20, count 0 2006.210.07:56:41.85#ibcon#enter sib2, iclass 20, count 0 2006.210.07:56:41.85#ibcon#flushed, iclass 20, count 0 2006.210.07:56:41.85#ibcon#about to write, iclass 20, count 0 2006.210.07:56:41.85#ibcon#wrote, iclass 20, count 0 2006.210.07:56:41.85#ibcon#about to read 3, iclass 20, count 0 2006.210.07:56:41.87#ibcon#read 3, iclass 20, count 0 2006.210.07:56:41.87#ibcon#about to read 4, iclass 20, count 0 2006.210.07:56:41.87#ibcon#read 4, iclass 20, count 0 2006.210.07:56:41.87#ibcon#about to read 5, iclass 20, count 0 2006.210.07:56:41.87#ibcon#read 5, iclass 20, count 0 2006.210.07:56:41.87#ibcon#about to read 6, iclass 20, count 0 2006.210.07:56:41.87#ibcon#read 6, iclass 20, count 0 2006.210.07:56:41.87#ibcon#end of sib2, iclass 20, count 0 2006.210.07:56:41.87#ibcon#*mode == 0, iclass 20, count 0 2006.210.07:56:41.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.07:56:41.87#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.07:56:41.87#ibcon#*before write, iclass 20, count 0 2006.210.07:56:41.87#ibcon#enter sib2, iclass 20, count 0 2006.210.07:56:41.87#ibcon#flushed, iclass 20, count 0 2006.210.07:56:41.87#ibcon#about to write, iclass 20, count 0 2006.210.07:56:41.87#ibcon#wrote, iclass 20, count 0 2006.210.07:56:41.87#ibcon#about to read 3, iclass 20, count 0 2006.210.07:56:41.91#ibcon#read 3, iclass 20, count 0 2006.210.07:56:41.91#ibcon#about to read 4, iclass 20, count 0 2006.210.07:56:41.91#ibcon#read 4, iclass 20, count 0 2006.210.07:56:41.91#ibcon#about to read 5, iclass 20, count 0 2006.210.07:56:41.91#ibcon#read 5, iclass 20, count 0 2006.210.07:56:41.91#ibcon#about to read 6, iclass 20, count 0 2006.210.07:56:41.91#ibcon#read 6, iclass 20, count 0 2006.210.07:56:41.91#ibcon#end of sib2, iclass 20, count 0 2006.210.07:56:41.91#ibcon#*after write, iclass 20, count 0 2006.210.07:56:41.91#ibcon#*before return 0, iclass 20, count 0 2006.210.07:56:41.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:41.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.07:56:41.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.07:56:41.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.07:56:41.91$vc4f8/vb=6,3 2006.210.07:56:41.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.07:56:41.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.07:56:41.91#ibcon#ireg 11 cls_cnt 2 2006.210.07:56:41.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:41.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:41.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:41.97#ibcon#enter wrdev, iclass 22, count 2 2006.210.07:56:41.97#ibcon#first serial, iclass 22, count 2 2006.210.07:56:41.97#ibcon#enter sib2, iclass 22, count 2 2006.210.07:56:41.97#ibcon#flushed, iclass 22, count 2 2006.210.07:56:41.97#ibcon#about to write, iclass 22, count 2 2006.210.07:56:41.97#ibcon#wrote, iclass 22, count 2 2006.210.07:56:41.97#ibcon#about to read 3, iclass 22, count 2 2006.210.07:56:41.99#ibcon#read 3, iclass 22, count 2 2006.210.07:56:41.99#ibcon#about to read 4, iclass 22, count 2 2006.210.07:56:41.99#ibcon#read 4, iclass 22, count 2 2006.210.07:56:41.99#ibcon#about to read 5, iclass 22, count 2 2006.210.07:56:41.99#ibcon#read 5, iclass 22, count 2 2006.210.07:56:41.99#ibcon#about to read 6, iclass 22, count 2 2006.210.07:56:41.99#ibcon#read 6, iclass 22, count 2 2006.210.07:56:41.99#ibcon#end of sib2, iclass 22, count 2 2006.210.07:56:41.99#ibcon#*mode == 0, iclass 22, count 2 2006.210.07:56:41.99#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.07:56:41.99#ibcon#[27=AT06-03\r\n] 2006.210.07:56:41.99#ibcon#*before write, iclass 22, count 2 2006.210.07:56:41.99#ibcon#enter sib2, iclass 22, count 2 2006.210.07:56:41.99#ibcon#flushed, iclass 22, count 2 2006.210.07:56:41.99#ibcon#about to write, iclass 22, count 2 2006.210.07:56:41.99#ibcon#wrote, iclass 22, count 2 2006.210.07:56:41.99#ibcon#about to read 3, iclass 22, count 2 2006.210.07:56:42.02#ibcon#read 3, iclass 22, count 2 2006.210.07:56:42.02#ibcon#about to read 4, iclass 22, count 2 2006.210.07:56:42.02#ibcon#read 4, iclass 22, count 2 2006.210.07:56:42.02#ibcon#about to read 5, iclass 22, count 2 2006.210.07:56:42.02#ibcon#read 5, iclass 22, count 2 2006.210.07:56:42.02#ibcon#about to read 6, iclass 22, count 2 2006.210.07:56:42.02#ibcon#read 6, iclass 22, count 2 2006.210.07:56:42.02#ibcon#end of sib2, iclass 22, count 2 2006.210.07:56:42.02#ibcon#*after write, iclass 22, count 2 2006.210.07:56:42.02#ibcon#*before return 0, iclass 22, count 2 2006.210.07:56:42.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:42.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.07:56:42.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.07:56:42.02#ibcon#ireg 7 cls_cnt 0 2006.210.07:56:42.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:42.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:42.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:42.14#ibcon#enter wrdev, iclass 22, count 0 2006.210.07:56:42.14#ibcon#first serial, iclass 22, count 0 2006.210.07:56:42.14#ibcon#enter sib2, iclass 22, count 0 2006.210.07:56:42.14#ibcon#flushed, iclass 22, count 0 2006.210.07:56:42.14#ibcon#about to write, iclass 22, count 0 2006.210.07:56:42.14#ibcon#wrote, iclass 22, count 0 2006.210.07:56:42.14#ibcon#about to read 3, iclass 22, count 0 2006.210.07:56:42.15#abcon#<5=/06 2.7 6.5 30.58 791006.3\r\n> 2006.210.07:56:42.16#ibcon#read 3, iclass 22, count 0 2006.210.07:56:42.16#ibcon#about to read 4, iclass 22, count 0 2006.210.07:56:42.16#ibcon#read 4, iclass 22, count 0 2006.210.07:56:42.16#ibcon#about to read 5, iclass 22, count 0 2006.210.07:56:42.16#ibcon#read 5, iclass 22, count 0 2006.210.07:56:42.16#ibcon#about to read 6, iclass 22, count 0 2006.210.07:56:42.16#ibcon#read 6, iclass 22, count 0 2006.210.07:56:42.16#ibcon#end of sib2, iclass 22, count 0 2006.210.07:56:42.16#ibcon#*mode == 0, iclass 22, count 0 2006.210.07:56:42.16#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.07:56:42.16#ibcon#[27=USB\r\n] 2006.210.07:56:42.16#ibcon#*before write, iclass 22, count 0 2006.210.07:56:42.16#ibcon#enter sib2, iclass 22, count 0 2006.210.07:56:42.16#ibcon#flushed, iclass 22, count 0 2006.210.07:56:42.16#ibcon#about to write, iclass 22, count 0 2006.210.07:56:42.16#ibcon#wrote, iclass 22, count 0 2006.210.07:56:42.16#ibcon#about to read 3, iclass 22, count 0 2006.210.07:56:42.17#abcon#{5=INTERFACE CLEAR} 2006.210.07:56:42.19#ibcon#read 3, iclass 22, count 0 2006.210.07:56:42.19#ibcon#about to read 4, iclass 22, count 0 2006.210.07:56:42.19#ibcon#read 4, iclass 22, count 0 2006.210.07:56:42.19#ibcon#about to read 5, iclass 22, count 0 2006.210.07:56:42.19#ibcon#read 5, iclass 22, count 0 2006.210.07:56:42.19#ibcon#about to read 6, iclass 22, count 0 2006.210.07:56:42.19#ibcon#read 6, iclass 22, count 0 2006.210.07:56:42.19#ibcon#end of sib2, iclass 22, count 0 2006.210.07:56:42.19#ibcon#*after write, iclass 22, count 0 2006.210.07:56:42.19#ibcon#*before return 0, iclass 22, count 0 2006.210.07:56:42.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:42.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.07:56:42.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.07:56:42.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.07:56:42.19$vc4f8/vabw=wide 2006.210.07:56:42.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.07:56:42.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.07:56:42.19#ibcon#ireg 8 cls_cnt 0 2006.210.07:56:42.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:56:42.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:56:42.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:56:42.19#ibcon#enter wrdev, iclass 27, count 0 2006.210.07:56:42.19#ibcon#first serial, iclass 27, count 0 2006.210.07:56:42.19#ibcon#enter sib2, iclass 27, count 0 2006.210.07:56:42.19#ibcon#flushed, iclass 27, count 0 2006.210.07:56:42.19#ibcon#about to write, iclass 27, count 0 2006.210.07:56:42.19#ibcon#wrote, iclass 27, count 0 2006.210.07:56:42.19#ibcon#about to read 3, iclass 27, count 0 2006.210.07:56:42.21#ibcon#read 3, iclass 27, count 0 2006.210.07:56:42.21#ibcon#about to read 4, iclass 27, count 0 2006.210.07:56:42.21#ibcon#read 4, iclass 27, count 0 2006.210.07:56:42.21#ibcon#about to read 5, iclass 27, count 0 2006.210.07:56:42.21#ibcon#read 5, iclass 27, count 0 2006.210.07:56:42.21#ibcon#about to read 6, iclass 27, count 0 2006.210.07:56:42.21#ibcon#read 6, iclass 27, count 0 2006.210.07:56:42.21#ibcon#end of sib2, iclass 27, count 0 2006.210.07:56:42.21#ibcon#*mode == 0, iclass 27, count 0 2006.210.07:56:42.21#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.07:56:42.21#ibcon#[25=BW32\r\n] 2006.210.07:56:42.21#ibcon#*before write, iclass 27, count 0 2006.210.07:56:42.21#ibcon#enter sib2, iclass 27, count 0 2006.210.07:56:42.21#ibcon#flushed, iclass 27, count 0 2006.210.07:56:42.21#ibcon#about to write, iclass 27, count 0 2006.210.07:56:42.21#ibcon#wrote, iclass 27, count 0 2006.210.07:56:42.21#ibcon#about to read 3, iclass 27, count 0 2006.210.07:56:42.23#abcon#[5=S1D000X0/0*\r\n] 2006.210.07:56:42.24#ibcon#read 3, iclass 27, count 0 2006.210.07:56:42.24#ibcon#about to read 4, iclass 27, count 0 2006.210.07:56:42.24#ibcon#read 4, iclass 27, count 0 2006.210.07:56:42.24#ibcon#about to read 5, iclass 27, count 0 2006.210.07:56:42.24#ibcon#read 5, iclass 27, count 0 2006.210.07:56:42.24#ibcon#about to read 6, iclass 27, count 0 2006.210.07:56:42.24#ibcon#read 6, iclass 27, count 0 2006.210.07:56:42.24#ibcon#end of sib2, iclass 27, count 0 2006.210.07:56:42.24#ibcon#*after write, iclass 27, count 0 2006.210.07:56:42.24#ibcon#*before return 0, iclass 27, count 0 2006.210.07:56:42.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:56:42.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.07:56:42.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.07:56:42.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.07:56:42.24$vc4f8/vbbw=wide 2006.210.07:56:42.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.07:56:42.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.07:56:42.24#ibcon#ireg 8 cls_cnt 0 2006.210.07:56:42.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:56:42.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:56:42.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:56:42.31#ibcon#enter wrdev, iclass 30, count 0 2006.210.07:56:42.31#ibcon#first serial, iclass 30, count 0 2006.210.07:56:42.31#ibcon#enter sib2, iclass 30, count 0 2006.210.07:56:42.31#ibcon#flushed, iclass 30, count 0 2006.210.07:56:42.31#ibcon#about to write, iclass 30, count 0 2006.210.07:56:42.31#ibcon#wrote, iclass 30, count 0 2006.210.07:56:42.31#ibcon#about to read 3, iclass 30, count 0 2006.210.07:56:42.33#ibcon#read 3, iclass 30, count 0 2006.210.07:56:42.33#ibcon#about to read 4, iclass 30, count 0 2006.210.07:56:42.33#ibcon#read 4, iclass 30, count 0 2006.210.07:56:42.33#ibcon#about to read 5, iclass 30, count 0 2006.210.07:56:42.33#ibcon#read 5, iclass 30, count 0 2006.210.07:56:42.33#ibcon#about to read 6, iclass 30, count 0 2006.210.07:56:42.33#ibcon#read 6, iclass 30, count 0 2006.210.07:56:42.33#ibcon#end of sib2, iclass 30, count 0 2006.210.07:56:42.33#ibcon#*mode == 0, iclass 30, count 0 2006.210.07:56:42.33#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.07:56:42.33#ibcon#[27=BW32\r\n] 2006.210.07:56:42.33#ibcon#*before write, iclass 30, count 0 2006.210.07:56:42.33#ibcon#enter sib2, iclass 30, count 0 2006.210.07:56:42.33#ibcon#flushed, iclass 30, count 0 2006.210.07:56:42.33#ibcon#about to write, iclass 30, count 0 2006.210.07:56:42.33#ibcon#wrote, iclass 30, count 0 2006.210.07:56:42.33#ibcon#about to read 3, iclass 30, count 0 2006.210.07:56:42.36#ibcon#read 3, iclass 30, count 0 2006.210.07:56:42.36#ibcon#about to read 4, iclass 30, count 0 2006.210.07:56:42.36#ibcon#read 4, iclass 30, count 0 2006.210.07:56:42.36#ibcon#about to read 5, iclass 30, count 0 2006.210.07:56:42.36#ibcon#read 5, iclass 30, count 0 2006.210.07:56:42.36#ibcon#about to read 6, iclass 30, count 0 2006.210.07:56:42.36#ibcon#read 6, iclass 30, count 0 2006.210.07:56:42.36#ibcon#end of sib2, iclass 30, count 0 2006.210.07:56:42.36#ibcon#*after write, iclass 30, count 0 2006.210.07:56:42.36#ibcon#*before return 0, iclass 30, count 0 2006.210.07:56:42.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:56:42.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.07:56:42.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.07:56:42.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.07:56:42.36$4f8m12a/ifd4f 2006.210.07:56:42.36$ifd4f/lo= 2006.210.07:56:42.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.07:56:42.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.07:56:42.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.07:56:42.36$ifd4f/patch= 2006.210.07:56:42.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.07:56:42.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.07:56:42.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.07:56:42.36$4f8m12a/"form=m,16.000,1:2 2006.210.07:56:42.36$4f8m12a/"tpicd 2006.210.07:56:42.36$4f8m12a/echo=off 2006.210.07:56:42.36$4f8m12a/xlog=off 2006.210.07:56:42.36:!2006.210.07:58:50 2006.210.07:57:12.13#trakl#Source acquired 2006.210.07:57:13.13#flagr#flagr/antenna,acquired 2006.210.07:58:50.00:preob 2006.210.07:58:50.13/onsource/TRACKING 2006.210.07:58:50.13:!2006.210.07:59:00 2006.210.07:59:00.00:data_valid=on 2006.210.07:59:00.00:midob 2006.210.07:59:01.13/onsource/TRACKING 2006.210.07:59:01.13/wx/30.55,1006.3,79 2006.210.07:59:01.23/cable/+6.3937E-03 2006.210.07:59:02.32/va/01,08,usb,yes,28,30 2006.210.07:59:02.32/va/02,07,usb,yes,29,30 2006.210.07:59:02.32/va/03,06,usb,yes,30,30 2006.210.07:59:02.32/va/04,07,usb,yes,29,32 2006.210.07:59:02.32/va/05,07,usb,yes,31,32 2006.210.07:59:02.32/va/06,06,usb,yes,30,30 2006.210.07:59:02.32/va/07,06,usb,yes,30,30 2006.210.07:59:02.32/va/08,07,usb,yes,29,28 2006.210.07:59:02.55/valo/01,532.99,yes,locked 2006.210.07:59:02.55/valo/02,572.99,yes,locked 2006.210.07:59:02.55/valo/03,672.99,yes,locked 2006.210.07:59:02.55/valo/04,832.99,yes,locked 2006.210.07:59:02.55/valo/05,652.99,yes,locked 2006.210.07:59:02.55/valo/06,772.99,yes,locked 2006.210.07:59:02.55/valo/07,832.99,yes,locked 2006.210.07:59:02.55/valo/08,852.99,yes,locked 2006.210.07:59:03.64/vb/01,04,usb,yes,28,27 2006.210.07:59:03.64/vb/02,04,usb,yes,30,31 2006.210.07:59:03.64/vb/03,03,usb,yes,33,37 2006.210.07:59:03.64/vb/04,03,usb,yes,34,34 2006.210.07:59:03.64/vb/05,03,usb,yes,32,37 2006.210.07:59:03.64/vb/06,03,usb,yes,33,36 2006.210.07:59:03.64/vb/07,04,usb,yes,29,29 2006.210.07:59:03.64/vb/08,03,usb,yes,33,37 2006.210.07:59:03.88/vblo/01,632.99,yes,locked 2006.210.07:59:03.88/vblo/02,640.99,yes,locked 2006.210.07:59:03.88/vblo/03,656.99,yes,locked 2006.210.07:59:03.88/vblo/04,712.99,yes,locked 2006.210.07:59:03.88/vblo/05,744.99,yes,locked 2006.210.07:59:03.88/vblo/06,752.99,yes,locked 2006.210.07:59:03.88/vblo/07,734.99,yes,locked 2006.210.07:59:03.88/vblo/08,744.99,yes,locked 2006.210.07:59:04.03/vabw/8 2006.210.07:59:04.18/vbbw/8 2006.210.07:59:04.27/xfe/off,on,12.7 2006.210.07:59:04.66/ifatt/23,28,28,28 2006.210.07:59:05.08/fmout-gps/S +4.65E-07 2006.210.07:59:05.12:!2006.210.08:00:00 2006.210.08:00:00.00:data_valid=off 2006.210.08:00:00.00:postob 2006.210.08:00:00.13/cable/+6.3934E-03 2006.210.08:00:00.13/wx/30.53,1006.3,80 2006.210.08:00:01.08/fmout-gps/S +4.64E-07 2006.210.08:00:01.08:scan_name=210-0800,k06210,60 2006.210.08:00:01.08:source=0823+033,082550.34,030924.5,2000.0,ccw 2006.210.08:00:01.14#flagr#flagr/antenna,new-source 2006.210.08:00:02.14:checkk5 2006.210.08:00:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:00:02.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:00:03.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:00:03.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:00:03.85/chk_obsdata//k5ts1/T2100759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:00:04.19/chk_obsdata//k5ts2/T2100759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:00:04.52/chk_obsdata//k5ts3/T2100759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:00:04.86/chk_obsdata//k5ts4/T2100759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:00:05.51/k5log//k5ts1_log_newline 2006.210.08:00:06.17/k5log//k5ts2_log_newline 2006.210.08:00:06.82/k5log//k5ts3_log_newline 2006.210.08:00:07.48/k5log//k5ts4_log_newline 2006.210.08:00:07.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:00:07.50:4f8m12a=2 2006.210.08:00:07.50$4f8m12a/echo=on 2006.210.08:00:07.50$4f8m12a/pcalon 2006.210.08:00:07.51$pcalon/"no phase cal control is implemented here 2006.210.08:00:07.51$4f8m12a/"tpicd=stop 2006.210.08:00:07.51$4f8m12a/vc4f8 2006.210.08:00:07.51$vc4f8/valo=1,532.99 2006.210.08:00:07.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:00:07.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:00:07.51#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:07.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:07.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:07.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:07.51#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:00:07.51#ibcon#first serial, iclass 3, count 0 2006.210.08:00:07.51#ibcon#enter sib2, iclass 3, count 0 2006.210.08:00:07.51#ibcon#flushed, iclass 3, count 0 2006.210.08:00:07.51#ibcon#about to write, iclass 3, count 0 2006.210.08:00:07.51#ibcon#wrote, iclass 3, count 0 2006.210.08:00:07.51#ibcon#about to read 3, iclass 3, count 0 2006.210.08:00:07.53#ibcon#read 3, iclass 3, count 0 2006.210.08:00:07.53#ibcon#about to read 4, iclass 3, count 0 2006.210.08:00:07.53#ibcon#read 4, iclass 3, count 0 2006.210.08:00:07.53#ibcon#about to read 5, iclass 3, count 0 2006.210.08:00:07.53#ibcon#read 5, iclass 3, count 0 2006.210.08:00:07.53#ibcon#about to read 6, iclass 3, count 0 2006.210.08:00:07.53#ibcon#read 6, iclass 3, count 0 2006.210.08:00:07.53#ibcon#end of sib2, iclass 3, count 0 2006.210.08:00:07.53#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:00:07.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:00:07.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:00:07.53#ibcon#*before write, iclass 3, count 0 2006.210.08:00:07.53#ibcon#enter sib2, iclass 3, count 0 2006.210.08:00:07.53#ibcon#flushed, iclass 3, count 0 2006.210.08:00:07.53#ibcon#about to write, iclass 3, count 0 2006.210.08:00:07.53#ibcon#wrote, iclass 3, count 0 2006.210.08:00:07.53#ibcon#about to read 3, iclass 3, count 0 2006.210.08:00:07.58#ibcon#read 3, iclass 3, count 0 2006.210.08:00:07.58#ibcon#about to read 4, iclass 3, count 0 2006.210.08:00:07.58#ibcon#read 4, iclass 3, count 0 2006.210.08:00:07.58#ibcon#about to read 5, iclass 3, count 0 2006.210.08:00:07.58#ibcon#read 5, iclass 3, count 0 2006.210.08:00:07.58#ibcon#about to read 6, iclass 3, count 0 2006.210.08:00:07.58#ibcon#read 6, iclass 3, count 0 2006.210.08:00:07.58#ibcon#end of sib2, iclass 3, count 0 2006.210.08:00:07.58#ibcon#*after write, iclass 3, count 0 2006.210.08:00:07.58#ibcon#*before return 0, iclass 3, count 0 2006.210.08:00:07.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:07.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:07.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:00:07.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:00:07.58$vc4f8/va=1,8 2006.210.08:00:07.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:00:07.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:00:07.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:07.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:07.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:07.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:07.58#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:00:07.58#ibcon#first serial, iclass 5, count 2 2006.210.08:00:07.58#ibcon#enter sib2, iclass 5, count 2 2006.210.08:00:07.58#ibcon#flushed, iclass 5, count 2 2006.210.08:00:07.58#ibcon#about to write, iclass 5, count 2 2006.210.08:00:07.58#ibcon#wrote, iclass 5, count 2 2006.210.08:00:07.58#ibcon#about to read 3, iclass 5, count 2 2006.210.08:00:07.60#ibcon#read 3, iclass 5, count 2 2006.210.08:00:07.60#ibcon#about to read 4, iclass 5, count 2 2006.210.08:00:07.60#ibcon#read 4, iclass 5, count 2 2006.210.08:00:07.60#ibcon#about to read 5, iclass 5, count 2 2006.210.08:00:07.60#ibcon#read 5, iclass 5, count 2 2006.210.08:00:07.60#ibcon#about to read 6, iclass 5, count 2 2006.210.08:00:07.60#ibcon#read 6, iclass 5, count 2 2006.210.08:00:07.60#ibcon#end of sib2, iclass 5, count 2 2006.210.08:00:07.60#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:00:07.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:00:07.60#ibcon#[25=AT01-08\r\n] 2006.210.08:00:07.60#ibcon#*before write, iclass 5, count 2 2006.210.08:00:07.60#ibcon#enter sib2, iclass 5, count 2 2006.210.08:00:07.60#ibcon#flushed, iclass 5, count 2 2006.210.08:00:07.60#ibcon#about to write, iclass 5, count 2 2006.210.08:00:07.60#ibcon#wrote, iclass 5, count 2 2006.210.08:00:07.60#ibcon#about to read 3, iclass 5, count 2 2006.210.08:00:07.63#ibcon#read 3, iclass 5, count 2 2006.210.08:00:07.63#ibcon#about to read 4, iclass 5, count 2 2006.210.08:00:07.63#ibcon#read 4, iclass 5, count 2 2006.210.08:00:07.63#ibcon#about to read 5, iclass 5, count 2 2006.210.08:00:07.63#ibcon#read 5, iclass 5, count 2 2006.210.08:00:07.63#ibcon#about to read 6, iclass 5, count 2 2006.210.08:00:07.63#ibcon#read 6, iclass 5, count 2 2006.210.08:00:07.63#ibcon#end of sib2, iclass 5, count 2 2006.210.08:00:07.63#ibcon#*after write, iclass 5, count 2 2006.210.08:00:07.63#ibcon#*before return 0, iclass 5, count 2 2006.210.08:00:07.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:07.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:07.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:00:07.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:07.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:07.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:07.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:07.75#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:00:07.75#ibcon#first serial, iclass 5, count 0 2006.210.08:00:07.75#ibcon#enter sib2, iclass 5, count 0 2006.210.08:00:07.75#ibcon#flushed, iclass 5, count 0 2006.210.08:00:07.75#ibcon#about to write, iclass 5, count 0 2006.210.08:00:07.75#ibcon#wrote, iclass 5, count 0 2006.210.08:00:07.75#ibcon#about to read 3, iclass 5, count 0 2006.210.08:00:07.77#ibcon#read 3, iclass 5, count 0 2006.210.08:00:07.77#ibcon#about to read 4, iclass 5, count 0 2006.210.08:00:07.77#ibcon#read 4, iclass 5, count 0 2006.210.08:00:07.77#ibcon#about to read 5, iclass 5, count 0 2006.210.08:00:07.77#ibcon#read 5, iclass 5, count 0 2006.210.08:00:07.77#ibcon#about to read 6, iclass 5, count 0 2006.210.08:00:07.77#ibcon#read 6, iclass 5, count 0 2006.210.08:00:07.77#ibcon#end of sib2, iclass 5, count 0 2006.210.08:00:07.77#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:00:07.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:00:07.77#ibcon#[25=USB\r\n] 2006.210.08:00:07.77#ibcon#*before write, iclass 5, count 0 2006.210.08:00:07.77#ibcon#enter sib2, iclass 5, count 0 2006.210.08:00:07.77#ibcon#flushed, iclass 5, count 0 2006.210.08:00:07.77#ibcon#about to write, iclass 5, count 0 2006.210.08:00:07.77#ibcon#wrote, iclass 5, count 0 2006.210.08:00:07.77#ibcon#about to read 3, iclass 5, count 0 2006.210.08:00:07.80#ibcon#read 3, iclass 5, count 0 2006.210.08:00:07.80#ibcon#about to read 4, iclass 5, count 0 2006.210.08:00:07.80#ibcon#read 4, iclass 5, count 0 2006.210.08:00:07.80#ibcon#about to read 5, iclass 5, count 0 2006.210.08:00:07.80#ibcon#read 5, iclass 5, count 0 2006.210.08:00:07.80#ibcon#about to read 6, iclass 5, count 0 2006.210.08:00:07.80#ibcon#read 6, iclass 5, count 0 2006.210.08:00:07.80#ibcon#end of sib2, iclass 5, count 0 2006.210.08:00:07.80#ibcon#*after write, iclass 5, count 0 2006.210.08:00:07.80#ibcon#*before return 0, iclass 5, count 0 2006.210.08:00:07.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:07.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:07.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:00:07.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:00:07.80$vc4f8/valo=2,572.99 2006.210.08:00:07.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:00:07.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:00:07.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:07.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:07.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:07.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:07.80#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:00:07.80#ibcon#first serial, iclass 7, count 0 2006.210.08:00:07.80#ibcon#enter sib2, iclass 7, count 0 2006.210.08:00:07.80#ibcon#flushed, iclass 7, count 0 2006.210.08:00:07.80#ibcon#about to write, iclass 7, count 0 2006.210.08:00:07.80#ibcon#wrote, iclass 7, count 0 2006.210.08:00:07.80#ibcon#about to read 3, iclass 7, count 0 2006.210.08:00:07.82#ibcon#read 3, iclass 7, count 0 2006.210.08:00:07.82#ibcon#about to read 4, iclass 7, count 0 2006.210.08:00:07.82#ibcon#read 4, iclass 7, count 0 2006.210.08:00:07.82#ibcon#about to read 5, iclass 7, count 0 2006.210.08:00:07.82#ibcon#read 5, iclass 7, count 0 2006.210.08:00:07.82#ibcon#about to read 6, iclass 7, count 0 2006.210.08:00:07.82#ibcon#read 6, iclass 7, count 0 2006.210.08:00:07.82#ibcon#end of sib2, iclass 7, count 0 2006.210.08:00:07.82#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:00:07.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:00:07.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:00:07.82#ibcon#*before write, iclass 7, count 0 2006.210.08:00:07.82#ibcon#enter sib2, iclass 7, count 0 2006.210.08:00:07.82#ibcon#flushed, iclass 7, count 0 2006.210.08:00:07.82#ibcon#about to write, iclass 7, count 0 2006.210.08:00:07.82#ibcon#wrote, iclass 7, count 0 2006.210.08:00:07.82#ibcon#about to read 3, iclass 7, count 0 2006.210.08:00:07.86#ibcon#read 3, iclass 7, count 0 2006.210.08:00:07.86#ibcon#about to read 4, iclass 7, count 0 2006.210.08:00:07.86#ibcon#read 4, iclass 7, count 0 2006.210.08:00:07.86#ibcon#about to read 5, iclass 7, count 0 2006.210.08:00:07.86#ibcon#read 5, iclass 7, count 0 2006.210.08:00:07.86#ibcon#about to read 6, iclass 7, count 0 2006.210.08:00:07.86#ibcon#read 6, iclass 7, count 0 2006.210.08:00:07.86#ibcon#end of sib2, iclass 7, count 0 2006.210.08:00:07.86#ibcon#*after write, iclass 7, count 0 2006.210.08:00:07.86#ibcon#*before return 0, iclass 7, count 0 2006.210.08:00:07.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:07.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:07.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:00:07.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:00:07.86$vc4f8/va=2,7 2006.210.08:00:07.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:00:07.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:00:07.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:07.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:07.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:07.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:07.92#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:00:07.92#ibcon#first serial, iclass 11, count 2 2006.210.08:00:07.92#ibcon#enter sib2, iclass 11, count 2 2006.210.08:00:07.92#ibcon#flushed, iclass 11, count 2 2006.210.08:00:07.92#ibcon#about to write, iclass 11, count 2 2006.210.08:00:07.92#ibcon#wrote, iclass 11, count 2 2006.210.08:00:07.92#ibcon#about to read 3, iclass 11, count 2 2006.210.08:00:07.94#ibcon#read 3, iclass 11, count 2 2006.210.08:00:07.94#ibcon#about to read 4, iclass 11, count 2 2006.210.08:00:07.94#ibcon#read 4, iclass 11, count 2 2006.210.08:00:07.94#ibcon#about to read 5, iclass 11, count 2 2006.210.08:00:07.94#ibcon#read 5, iclass 11, count 2 2006.210.08:00:07.94#ibcon#about to read 6, iclass 11, count 2 2006.210.08:00:07.94#ibcon#read 6, iclass 11, count 2 2006.210.08:00:07.94#ibcon#end of sib2, iclass 11, count 2 2006.210.08:00:07.94#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:00:07.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:00:07.94#ibcon#[25=AT02-07\r\n] 2006.210.08:00:07.94#ibcon#*before write, iclass 11, count 2 2006.210.08:00:07.94#ibcon#enter sib2, iclass 11, count 2 2006.210.08:00:07.94#ibcon#flushed, iclass 11, count 2 2006.210.08:00:07.94#ibcon#about to write, iclass 11, count 2 2006.210.08:00:07.94#ibcon#wrote, iclass 11, count 2 2006.210.08:00:07.94#ibcon#about to read 3, iclass 11, count 2 2006.210.08:00:07.97#ibcon#read 3, iclass 11, count 2 2006.210.08:00:07.97#ibcon#about to read 4, iclass 11, count 2 2006.210.08:00:07.97#ibcon#read 4, iclass 11, count 2 2006.210.08:00:07.97#ibcon#about to read 5, iclass 11, count 2 2006.210.08:00:07.97#ibcon#read 5, iclass 11, count 2 2006.210.08:00:07.97#ibcon#about to read 6, iclass 11, count 2 2006.210.08:00:07.97#ibcon#read 6, iclass 11, count 2 2006.210.08:00:07.97#ibcon#end of sib2, iclass 11, count 2 2006.210.08:00:07.97#ibcon#*after write, iclass 11, count 2 2006.210.08:00:07.97#ibcon#*before return 0, iclass 11, count 2 2006.210.08:00:07.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:07.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:07.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:00:07.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:07.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:08.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:08.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:08.09#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:00:08.09#ibcon#first serial, iclass 11, count 0 2006.210.08:00:08.09#ibcon#enter sib2, iclass 11, count 0 2006.210.08:00:08.09#ibcon#flushed, iclass 11, count 0 2006.210.08:00:08.09#ibcon#about to write, iclass 11, count 0 2006.210.08:00:08.09#ibcon#wrote, iclass 11, count 0 2006.210.08:00:08.09#ibcon#about to read 3, iclass 11, count 0 2006.210.08:00:08.11#ibcon#read 3, iclass 11, count 0 2006.210.08:00:08.11#ibcon#about to read 4, iclass 11, count 0 2006.210.08:00:08.11#ibcon#read 4, iclass 11, count 0 2006.210.08:00:08.11#ibcon#about to read 5, iclass 11, count 0 2006.210.08:00:08.11#ibcon#read 5, iclass 11, count 0 2006.210.08:00:08.11#ibcon#about to read 6, iclass 11, count 0 2006.210.08:00:08.11#ibcon#read 6, iclass 11, count 0 2006.210.08:00:08.11#ibcon#end of sib2, iclass 11, count 0 2006.210.08:00:08.11#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:00:08.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:00:08.11#ibcon#[25=USB\r\n] 2006.210.08:00:08.11#ibcon#*before write, iclass 11, count 0 2006.210.08:00:08.11#ibcon#enter sib2, iclass 11, count 0 2006.210.08:00:08.11#ibcon#flushed, iclass 11, count 0 2006.210.08:00:08.11#ibcon#about to write, iclass 11, count 0 2006.210.08:00:08.11#ibcon#wrote, iclass 11, count 0 2006.210.08:00:08.11#ibcon#about to read 3, iclass 11, count 0 2006.210.08:00:08.14#ibcon#read 3, iclass 11, count 0 2006.210.08:00:08.14#ibcon#about to read 4, iclass 11, count 0 2006.210.08:00:08.14#ibcon#read 4, iclass 11, count 0 2006.210.08:00:08.14#ibcon#about to read 5, iclass 11, count 0 2006.210.08:00:08.14#ibcon#read 5, iclass 11, count 0 2006.210.08:00:08.14#ibcon#about to read 6, iclass 11, count 0 2006.210.08:00:08.14#ibcon#read 6, iclass 11, count 0 2006.210.08:00:08.14#ibcon#end of sib2, iclass 11, count 0 2006.210.08:00:08.14#ibcon#*after write, iclass 11, count 0 2006.210.08:00:08.14#ibcon#*before return 0, iclass 11, count 0 2006.210.08:00:08.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:08.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:08.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:00:08.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:00:08.14$vc4f8/valo=3,672.99 2006.210.08:00:08.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:00:08.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:00:08.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:08.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:08.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:08.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:08.14#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:00:08.14#ibcon#first serial, iclass 13, count 0 2006.210.08:00:08.14#ibcon#enter sib2, iclass 13, count 0 2006.210.08:00:08.14#ibcon#flushed, iclass 13, count 0 2006.210.08:00:08.14#ibcon#about to write, iclass 13, count 0 2006.210.08:00:08.14#ibcon#wrote, iclass 13, count 0 2006.210.08:00:08.14#ibcon#about to read 3, iclass 13, count 0 2006.210.08:00:08.16#ibcon#read 3, iclass 13, count 0 2006.210.08:00:08.16#ibcon#about to read 4, iclass 13, count 0 2006.210.08:00:08.16#ibcon#read 4, iclass 13, count 0 2006.210.08:00:08.16#ibcon#about to read 5, iclass 13, count 0 2006.210.08:00:08.16#ibcon#read 5, iclass 13, count 0 2006.210.08:00:08.16#ibcon#about to read 6, iclass 13, count 0 2006.210.08:00:08.16#ibcon#read 6, iclass 13, count 0 2006.210.08:00:08.16#ibcon#end of sib2, iclass 13, count 0 2006.210.08:00:08.16#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:00:08.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:00:08.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:00:08.16#ibcon#*before write, iclass 13, count 0 2006.210.08:00:08.16#ibcon#enter sib2, iclass 13, count 0 2006.210.08:00:08.16#ibcon#flushed, iclass 13, count 0 2006.210.08:00:08.16#ibcon#about to write, iclass 13, count 0 2006.210.08:00:08.16#ibcon#wrote, iclass 13, count 0 2006.210.08:00:08.16#ibcon#about to read 3, iclass 13, count 0 2006.210.08:00:08.20#ibcon#read 3, iclass 13, count 0 2006.210.08:00:08.20#ibcon#about to read 4, iclass 13, count 0 2006.210.08:00:08.20#ibcon#read 4, iclass 13, count 0 2006.210.08:00:08.20#ibcon#about to read 5, iclass 13, count 0 2006.210.08:00:08.20#ibcon#read 5, iclass 13, count 0 2006.210.08:00:08.20#ibcon#about to read 6, iclass 13, count 0 2006.210.08:00:08.20#ibcon#read 6, iclass 13, count 0 2006.210.08:00:08.20#ibcon#end of sib2, iclass 13, count 0 2006.210.08:00:08.20#ibcon#*after write, iclass 13, count 0 2006.210.08:00:08.20#ibcon#*before return 0, iclass 13, count 0 2006.210.08:00:08.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:08.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:08.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:00:08.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:00:08.20$vc4f8/va=3,6 2006.210.08:00:08.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:00:08.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:00:08.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:08.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:08.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:08.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:08.26#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:00:08.26#ibcon#first serial, iclass 15, count 2 2006.210.08:00:08.26#ibcon#enter sib2, iclass 15, count 2 2006.210.08:00:08.26#ibcon#flushed, iclass 15, count 2 2006.210.08:00:08.26#ibcon#about to write, iclass 15, count 2 2006.210.08:00:08.26#ibcon#wrote, iclass 15, count 2 2006.210.08:00:08.26#ibcon#about to read 3, iclass 15, count 2 2006.210.08:00:08.28#ibcon#read 3, iclass 15, count 2 2006.210.08:00:08.28#ibcon#about to read 4, iclass 15, count 2 2006.210.08:00:08.28#ibcon#read 4, iclass 15, count 2 2006.210.08:00:08.28#ibcon#about to read 5, iclass 15, count 2 2006.210.08:00:08.28#ibcon#read 5, iclass 15, count 2 2006.210.08:00:08.28#ibcon#about to read 6, iclass 15, count 2 2006.210.08:00:08.28#ibcon#read 6, iclass 15, count 2 2006.210.08:00:08.28#ibcon#end of sib2, iclass 15, count 2 2006.210.08:00:08.28#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:00:08.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:00:08.28#ibcon#[25=AT03-06\r\n] 2006.210.08:00:08.28#ibcon#*before write, iclass 15, count 2 2006.210.08:00:08.28#ibcon#enter sib2, iclass 15, count 2 2006.210.08:00:08.28#ibcon#flushed, iclass 15, count 2 2006.210.08:00:08.28#ibcon#about to write, iclass 15, count 2 2006.210.08:00:08.28#ibcon#wrote, iclass 15, count 2 2006.210.08:00:08.28#ibcon#about to read 3, iclass 15, count 2 2006.210.08:00:08.31#ibcon#read 3, iclass 15, count 2 2006.210.08:00:08.31#ibcon#about to read 4, iclass 15, count 2 2006.210.08:00:08.31#ibcon#read 4, iclass 15, count 2 2006.210.08:00:08.31#ibcon#about to read 5, iclass 15, count 2 2006.210.08:00:08.31#ibcon#read 5, iclass 15, count 2 2006.210.08:00:08.31#ibcon#about to read 6, iclass 15, count 2 2006.210.08:00:08.31#ibcon#read 6, iclass 15, count 2 2006.210.08:00:08.31#ibcon#end of sib2, iclass 15, count 2 2006.210.08:00:08.31#ibcon#*after write, iclass 15, count 2 2006.210.08:00:08.31#ibcon#*before return 0, iclass 15, count 2 2006.210.08:00:08.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:08.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:08.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:00:08.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:08.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:08.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:08.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:08.43#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:00:08.43#ibcon#first serial, iclass 15, count 0 2006.210.08:00:08.43#ibcon#enter sib2, iclass 15, count 0 2006.210.08:00:08.43#ibcon#flushed, iclass 15, count 0 2006.210.08:00:08.43#ibcon#about to write, iclass 15, count 0 2006.210.08:00:08.43#ibcon#wrote, iclass 15, count 0 2006.210.08:00:08.43#ibcon#about to read 3, iclass 15, count 0 2006.210.08:00:08.45#ibcon#read 3, iclass 15, count 0 2006.210.08:00:08.45#ibcon#about to read 4, iclass 15, count 0 2006.210.08:00:08.45#ibcon#read 4, iclass 15, count 0 2006.210.08:00:08.45#ibcon#about to read 5, iclass 15, count 0 2006.210.08:00:08.45#ibcon#read 5, iclass 15, count 0 2006.210.08:00:08.45#ibcon#about to read 6, iclass 15, count 0 2006.210.08:00:08.45#ibcon#read 6, iclass 15, count 0 2006.210.08:00:08.45#ibcon#end of sib2, iclass 15, count 0 2006.210.08:00:08.45#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:00:08.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:00:08.45#ibcon#[25=USB\r\n] 2006.210.08:00:08.45#ibcon#*before write, iclass 15, count 0 2006.210.08:00:08.45#ibcon#enter sib2, iclass 15, count 0 2006.210.08:00:08.45#ibcon#flushed, iclass 15, count 0 2006.210.08:00:08.45#ibcon#about to write, iclass 15, count 0 2006.210.08:00:08.45#ibcon#wrote, iclass 15, count 0 2006.210.08:00:08.45#ibcon#about to read 3, iclass 15, count 0 2006.210.08:00:08.48#ibcon#read 3, iclass 15, count 0 2006.210.08:00:08.48#ibcon#about to read 4, iclass 15, count 0 2006.210.08:00:08.48#ibcon#read 4, iclass 15, count 0 2006.210.08:00:08.48#ibcon#about to read 5, iclass 15, count 0 2006.210.08:00:08.48#ibcon#read 5, iclass 15, count 0 2006.210.08:00:08.48#ibcon#about to read 6, iclass 15, count 0 2006.210.08:00:08.48#ibcon#read 6, iclass 15, count 0 2006.210.08:00:08.48#ibcon#end of sib2, iclass 15, count 0 2006.210.08:00:08.48#ibcon#*after write, iclass 15, count 0 2006.210.08:00:08.48#ibcon#*before return 0, iclass 15, count 0 2006.210.08:00:08.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:08.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:08.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:00:08.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:00:08.48$vc4f8/valo=4,832.99 2006.210.08:00:08.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:00:08.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:00:08.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:08.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:08.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:08.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:08.48#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:00:08.48#ibcon#first serial, iclass 17, count 0 2006.210.08:00:08.48#ibcon#enter sib2, iclass 17, count 0 2006.210.08:00:08.48#ibcon#flushed, iclass 17, count 0 2006.210.08:00:08.48#ibcon#about to write, iclass 17, count 0 2006.210.08:00:08.48#ibcon#wrote, iclass 17, count 0 2006.210.08:00:08.48#ibcon#about to read 3, iclass 17, count 0 2006.210.08:00:08.50#ibcon#read 3, iclass 17, count 0 2006.210.08:00:08.50#ibcon#about to read 4, iclass 17, count 0 2006.210.08:00:08.50#ibcon#read 4, iclass 17, count 0 2006.210.08:00:08.50#ibcon#about to read 5, iclass 17, count 0 2006.210.08:00:08.50#ibcon#read 5, iclass 17, count 0 2006.210.08:00:08.50#ibcon#about to read 6, iclass 17, count 0 2006.210.08:00:08.50#ibcon#read 6, iclass 17, count 0 2006.210.08:00:08.50#ibcon#end of sib2, iclass 17, count 0 2006.210.08:00:08.50#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:00:08.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:00:08.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:00:08.50#ibcon#*before write, iclass 17, count 0 2006.210.08:00:08.50#ibcon#enter sib2, iclass 17, count 0 2006.210.08:00:08.50#ibcon#flushed, iclass 17, count 0 2006.210.08:00:08.50#ibcon#about to write, iclass 17, count 0 2006.210.08:00:08.50#ibcon#wrote, iclass 17, count 0 2006.210.08:00:08.50#ibcon#about to read 3, iclass 17, count 0 2006.210.08:00:08.54#ibcon#read 3, iclass 17, count 0 2006.210.08:00:08.54#ibcon#about to read 4, iclass 17, count 0 2006.210.08:00:08.54#ibcon#read 4, iclass 17, count 0 2006.210.08:00:08.54#ibcon#about to read 5, iclass 17, count 0 2006.210.08:00:08.54#ibcon#read 5, iclass 17, count 0 2006.210.08:00:08.54#ibcon#about to read 6, iclass 17, count 0 2006.210.08:00:08.54#ibcon#read 6, iclass 17, count 0 2006.210.08:00:08.54#ibcon#end of sib2, iclass 17, count 0 2006.210.08:00:08.54#ibcon#*after write, iclass 17, count 0 2006.210.08:00:08.54#ibcon#*before return 0, iclass 17, count 0 2006.210.08:00:08.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:08.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:08.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:00:08.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:00:08.54$vc4f8/va=4,7 2006.210.08:00:08.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:00:08.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:00:08.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:08.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:08.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:08.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:08.60#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:00:08.60#ibcon#first serial, iclass 19, count 2 2006.210.08:00:08.60#ibcon#enter sib2, iclass 19, count 2 2006.210.08:00:08.60#ibcon#flushed, iclass 19, count 2 2006.210.08:00:08.60#ibcon#about to write, iclass 19, count 2 2006.210.08:00:08.60#ibcon#wrote, iclass 19, count 2 2006.210.08:00:08.60#ibcon#about to read 3, iclass 19, count 2 2006.210.08:00:08.62#ibcon#read 3, iclass 19, count 2 2006.210.08:00:08.62#ibcon#about to read 4, iclass 19, count 2 2006.210.08:00:08.62#ibcon#read 4, iclass 19, count 2 2006.210.08:00:08.62#ibcon#about to read 5, iclass 19, count 2 2006.210.08:00:08.62#ibcon#read 5, iclass 19, count 2 2006.210.08:00:08.62#ibcon#about to read 6, iclass 19, count 2 2006.210.08:00:08.62#ibcon#read 6, iclass 19, count 2 2006.210.08:00:08.62#ibcon#end of sib2, iclass 19, count 2 2006.210.08:00:08.62#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:00:08.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:00:08.62#ibcon#[25=AT04-07\r\n] 2006.210.08:00:08.62#ibcon#*before write, iclass 19, count 2 2006.210.08:00:08.62#ibcon#enter sib2, iclass 19, count 2 2006.210.08:00:08.62#ibcon#flushed, iclass 19, count 2 2006.210.08:00:08.62#ibcon#about to write, iclass 19, count 2 2006.210.08:00:08.62#ibcon#wrote, iclass 19, count 2 2006.210.08:00:08.62#ibcon#about to read 3, iclass 19, count 2 2006.210.08:00:08.65#ibcon#read 3, iclass 19, count 2 2006.210.08:00:08.65#ibcon#about to read 4, iclass 19, count 2 2006.210.08:00:08.65#ibcon#read 4, iclass 19, count 2 2006.210.08:00:08.65#ibcon#about to read 5, iclass 19, count 2 2006.210.08:00:08.65#ibcon#read 5, iclass 19, count 2 2006.210.08:00:08.65#ibcon#about to read 6, iclass 19, count 2 2006.210.08:00:08.65#ibcon#read 6, iclass 19, count 2 2006.210.08:00:08.65#ibcon#end of sib2, iclass 19, count 2 2006.210.08:00:08.65#ibcon#*after write, iclass 19, count 2 2006.210.08:00:08.65#ibcon#*before return 0, iclass 19, count 2 2006.210.08:00:08.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:08.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:08.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:00:08.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:08.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:08.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:08.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:08.77#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:00:08.77#ibcon#first serial, iclass 19, count 0 2006.210.08:00:08.77#ibcon#enter sib2, iclass 19, count 0 2006.210.08:00:08.77#ibcon#flushed, iclass 19, count 0 2006.210.08:00:08.77#ibcon#about to write, iclass 19, count 0 2006.210.08:00:08.77#ibcon#wrote, iclass 19, count 0 2006.210.08:00:08.77#ibcon#about to read 3, iclass 19, count 0 2006.210.08:00:08.79#ibcon#read 3, iclass 19, count 0 2006.210.08:00:08.79#ibcon#about to read 4, iclass 19, count 0 2006.210.08:00:08.79#ibcon#read 4, iclass 19, count 0 2006.210.08:00:08.79#ibcon#about to read 5, iclass 19, count 0 2006.210.08:00:08.79#ibcon#read 5, iclass 19, count 0 2006.210.08:00:08.79#ibcon#about to read 6, iclass 19, count 0 2006.210.08:00:08.79#ibcon#read 6, iclass 19, count 0 2006.210.08:00:08.79#ibcon#end of sib2, iclass 19, count 0 2006.210.08:00:08.79#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:00:08.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:00:08.79#ibcon#[25=USB\r\n] 2006.210.08:00:08.79#ibcon#*before write, iclass 19, count 0 2006.210.08:00:08.79#ibcon#enter sib2, iclass 19, count 0 2006.210.08:00:08.79#ibcon#flushed, iclass 19, count 0 2006.210.08:00:08.79#ibcon#about to write, iclass 19, count 0 2006.210.08:00:08.79#ibcon#wrote, iclass 19, count 0 2006.210.08:00:08.79#ibcon#about to read 3, iclass 19, count 0 2006.210.08:00:08.82#ibcon#read 3, iclass 19, count 0 2006.210.08:00:08.82#ibcon#about to read 4, iclass 19, count 0 2006.210.08:00:08.82#ibcon#read 4, iclass 19, count 0 2006.210.08:00:08.82#ibcon#about to read 5, iclass 19, count 0 2006.210.08:00:08.82#ibcon#read 5, iclass 19, count 0 2006.210.08:00:08.82#ibcon#about to read 6, iclass 19, count 0 2006.210.08:00:08.82#ibcon#read 6, iclass 19, count 0 2006.210.08:00:08.82#ibcon#end of sib2, iclass 19, count 0 2006.210.08:00:08.82#ibcon#*after write, iclass 19, count 0 2006.210.08:00:08.82#ibcon#*before return 0, iclass 19, count 0 2006.210.08:00:08.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:08.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:08.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:00:08.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:00:08.82$vc4f8/valo=5,652.99 2006.210.08:00:08.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:00:08.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:00:08.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:08.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:08.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:08.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:08.82#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:00:08.82#ibcon#first serial, iclass 21, count 0 2006.210.08:00:08.82#ibcon#enter sib2, iclass 21, count 0 2006.210.08:00:08.82#ibcon#flushed, iclass 21, count 0 2006.210.08:00:08.82#ibcon#about to write, iclass 21, count 0 2006.210.08:00:08.82#ibcon#wrote, iclass 21, count 0 2006.210.08:00:08.82#ibcon#about to read 3, iclass 21, count 0 2006.210.08:00:08.84#ibcon#read 3, iclass 21, count 0 2006.210.08:00:08.84#ibcon#about to read 4, iclass 21, count 0 2006.210.08:00:08.84#ibcon#read 4, iclass 21, count 0 2006.210.08:00:08.84#ibcon#about to read 5, iclass 21, count 0 2006.210.08:00:08.84#ibcon#read 5, iclass 21, count 0 2006.210.08:00:08.84#ibcon#about to read 6, iclass 21, count 0 2006.210.08:00:08.84#ibcon#read 6, iclass 21, count 0 2006.210.08:00:08.84#ibcon#end of sib2, iclass 21, count 0 2006.210.08:00:08.84#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:00:08.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:00:08.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:00:08.84#ibcon#*before write, iclass 21, count 0 2006.210.08:00:08.84#ibcon#enter sib2, iclass 21, count 0 2006.210.08:00:08.84#ibcon#flushed, iclass 21, count 0 2006.210.08:00:08.84#ibcon#about to write, iclass 21, count 0 2006.210.08:00:08.84#ibcon#wrote, iclass 21, count 0 2006.210.08:00:08.84#ibcon#about to read 3, iclass 21, count 0 2006.210.08:00:08.88#ibcon#read 3, iclass 21, count 0 2006.210.08:00:08.88#ibcon#about to read 4, iclass 21, count 0 2006.210.08:00:08.88#ibcon#read 4, iclass 21, count 0 2006.210.08:00:08.88#ibcon#about to read 5, iclass 21, count 0 2006.210.08:00:08.88#ibcon#read 5, iclass 21, count 0 2006.210.08:00:08.88#ibcon#about to read 6, iclass 21, count 0 2006.210.08:00:08.88#ibcon#read 6, iclass 21, count 0 2006.210.08:00:08.88#ibcon#end of sib2, iclass 21, count 0 2006.210.08:00:08.88#ibcon#*after write, iclass 21, count 0 2006.210.08:00:08.88#ibcon#*before return 0, iclass 21, count 0 2006.210.08:00:08.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:08.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:08.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:00:08.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:00:08.88$vc4f8/va=5,7 2006.210.08:00:08.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:00:08.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:00:08.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:08.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:08.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:08.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:08.94#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:00:08.94#ibcon#first serial, iclass 23, count 2 2006.210.08:00:08.94#ibcon#enter sib2, iclass 23, count 2 2006.210.08:00:08.94#ibcon#flushed, iclass 23, count 2 2006.210.08:00:08.94#ibcon#about to write, iclass 23, count 2 2006.210.08:00:08.94#ibcon#wrote, iclass 23, count 2 2006.210.08:00:08.94#ibcon#about to read 3, iclass 23, count 2 2006.210.08:00:08.96#ibcon#read 3, iclass 23, count 2 2006.210.08:00:08.96#ibcon#about to read 4, iclass 23, count 2 2006.210.08:00:08.96#ibcon#read 4, iclass 23, count 2 2006.210.08:00:08.96#ibcon#about to read 5, iclass 23, count 2 2006.210.08:00:08.96#ibcon#read 5, iclass 23, count 2 2006.210.08:00:08.96#ibcon#about to read 6, iclass 23, count 2 2006.210.08:00:08.96#ibcon#read 6, iclass 23, count 2 2006.210.08:00:08.96#ibcon#end of sib2, iclass 23, count 2 2006.210.08:00:08.96#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:00:08.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:00:08.96#ibcon#[25=AT05-07\r\n] 2006.210.08:00:08.96#ibcon#*before write, iclass 23, count 2 2006.210.08:00:08.96#ibcon#enter sib2, iclass 23, count 2 2006.210.08:00:08.96#ibcon#flushed, iclass 23, count 2 2006.210.08:00:08.96#ibcon#about to write, iclass 23, count 2 2006.210.08:00:08.96#ibcon#wrote, iclass 23, count 2 2006.210.08:00:08.96#ibcon#about to read 3, iclass 23, count 2 2006.210.08:00:08.99#ibcon#read 3, iclass 23, count 2 2006.210.08:00:08.99#ibcon#about to read 4, iclass 23, count 2 2006.210.08:00:08.99#ibcon#read 4, iclass 23, count 2 2006.210.08:00:08.99#ibcon#about to read 5, iclass 23, count 2 2006.210.08:00:08.99#ibcon#read 5, iclass 23, count 2 2006.210.08:00:08.99#ibcon#about to read 6, iclass 23, count 2 2006.210.08:00:08.99#ibcon#read 6, iclass 23, count 2 2006.210.08:00:08.99#ibcon#end of sib2, iclass 23, count 2 2006.210.08:00:08.99#ibcon#*after write, iclass 23, count 2 2006.210.08:00:08.99#ibcon#*before return 0, iclass 23, count 2 2006.210.08:00:08.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:08.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:08.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:00:08.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:08.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:09.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:09.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:09.11#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:00:09.11#ibcon#first serial, iclass 23, count 0 2006.210.08:00:09.11#ibcon#enter sib2, iclass 23, count 0 2006.210.08:00:09.11#ibcon#flushed, iclass 23, count 0 2006.210.08:00:09.11#ibcon#about to write, iclass 23, count 0 2006.210.08:00:09.11#ibcon#wrote, iclass 23, count 0 2006.210.08:00:09.11#ibcon#about to read 3, iclass 23, count 0 2006.210.08:00:09.13#ibcon#read 3, iclass 23, count 0 2006.210.08:00:09.13#ibcon#about to read 4, iclass 23, count 0 2006.210.08:00:09.13#ibcon#read 4, iclass 23, count 0 2006.210.08:00:09.13#ibcon#about to read 5, iclass 23, count 0 2006.210.08:00:09.13#ibcon#read 5, iclass 23, count 0 2006.210.08:00:09.13#ibcon#about to read 6, iclass 23, count 0 2006.210.08:00:09.13#ibcon#read 6, iclass 23, count 0 2006.210.08:00:09.13#ibcon#end of sib2, iclass 23, count 0 2006.210.08:00:09.13#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:00:09.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:00:09.13#ibcon#[25=USB\r\n] 2006.210.08:00:09.13#ibcon#*before write, iclass 23, count 0 2006.210.08:00:09.13#ibcon#enter sib2, iclass 23, count 0 2006.210.08:00:09.13#ibcon#flushed, iclass 23, count 0 2006.210.08:00:09.13#ibcon#about to write, iclass 23, count 0 2006.210.08:00:09.13#ibcon#wrote, iclass 23, count 0 2006.210.08:00:09.13#ibcon#about to read 3, iclass 23, count 0 2006.210.08:00:09.16#ibcon#read 3, iclass 23, count 0 2006.210.08:00:09.16#ibcon#about to read 4, iclass 23, count 0 2006.210.08:00:09.16#ibcon#read 4, iclass 23, count 0 2006.210.08:00:09.16#ibcon#about to read 5, iclass 23, count 0 2006.210.08:00:09.16#ibcon#read 5, iclass 23, count 0 2006.210.08:00:09.16#ibcon#about to read 6, iclass 23, count 0 2006.210.08:00:09.16#ibcon#read 6, iclass 23, count 0 2006.210.08:00:09.16#ibcon#end of sib2, iclass 23, count 0 2006.210.08:00:09.16#ibcon#*after write, iclass 23, count 0 2006.210.08:00:09.16#ibcon#*before return 0, iclass 23, count 0 2006.210.08:00:09.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:09.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:09.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:00:09.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:00:09.16$vc4f8/valo=6,772.99 2006.210.08:00:09.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:00:09.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:00:09.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:09.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:09.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:09.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:09.16#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:00:09.16#ibcon#first serial, iclass 25, count 0 2006.210.08:00:09.16#ibcon#enter sib2, iclass 25, count 0 2006.210.08:00:09.16#ibcon#flushed, iclass 25, count 0 2006.210.08:00:09.16#ibcon#about to write, iclass 25, count 0 2006.210.08:00:09.16#ibcon#wrote, iclass 25, count 0 2006.210.08:00:09.16#ibcon#about to read 3, iclass 25, count 0 2006.210.08:00:09.18#ibcon#read 3, iclass 25, count 0 2006.210.08:00:09.18#ibcon#about to read 4, iclass 25, count 0 2006.210.08:00:09.18#ibcon#read 4, iclass 25, count 0 2006.210.08:00:09.18#ibcon#about to read 5, iclass 25, count 0 2006.210.08:00:09.18#ibcon#read 5, iclass 25, count 0 2006.210.08:00:09.18#ibcon#about to read 6, iclass 25, count 0 2006.210.08:00:09.18#ibcon#read 6, iclass 25, count 0 2006.210.08:00:09.18#ibcon#end of sib2, iclass 25, count 0 2006.210.08:00:09.18#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:00:09.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:00:09.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:00:09.18#ibcon#*before write, iclass 25, count 0 2006.210.08:00:09.18#ibcon#enter sib2, iclass 25, count 0 2006.210.08:00:09.18#ibcon#flushed, iclass 25, count 0 2006.210.08:00:09.18#ibcon#about to write, iclass 25, count 0 2006.210.08:00:09.18#ibcon#wrote, iclass 25, count 0 2006.210.08:00:09.18#ibcon#about to read 3, iclass 25, count 0 2006.210.08:00:09.22#ibcon#read 3, iclass 25, count 0 2006.210.08:00:09.22#ibcon#about to read 4, iclass 25, count 0 2006.210.08:00:09.22#ibcon#read 4, iclass 25, count 0 2006.210.08:00:09.22#ibcon#about to read 5, iclass 25, count 0 2006.210.08:00:09.22#ibcon#read 5, iclass 25, count 0 2006.210.08:00:09.22#ibcon#about to read 6, iclass 25, count 0 2006.210.08:00:09.22#ibcon#read 6, iclass 25, count 0 2006.210.08:00:09.22#ibcon#end of sib2, iclass 25, count 0 2006.210.08:00:09.22#ibcon#*after write, iclass 25, count 0 2006.210.08:00:09.22#ibcon#*before return 0, iclass 25, count 0 2006.210.08:00:09.22#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:09.22#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:09.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:00:09.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:00:09.22$vc4f8/va=6,6 2006.210.08:00:09.22#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:00:09.22#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:00:09.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:09.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:00:09.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:00:09.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:00:09.28#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:00:09.28#ibcon#first serial, iclass 27, count 2 2006.210.08:00:09.28#ibcon#enter sib2, iclass 27, count 2 2006.210.08:00:09.28#ibcon#flushed, iclass 27, count 2 2006.210.08:00:09.28#ibcon#about to write, iclass 27, count 2 2006.210.08:00:09.28#ibcon#wrote, iclass 27, count 2 2006.210.08:00:09.28#ibcon#about to read 3, iclass 27, count 2 2006.210.08:00:09.30#ibcon#read 3, iclass 27, count 2 2006.210.08:00:09.30#ibcon#about to read 4, iclass 27, count 2 2006.210.08:00:09.30#ibcon#read 4, iclass 27, count 2 2006.210.08:00:09.30#ibcon#about to read 5, iclass 27, count 2 2006.210.08:00:09.30#ibcon#read 5, iclass 27, count 2 2006.210.08:00:09.30#ibcon#about to read 6, iclass 27, count 2 2006.210.08:00:09.30#ibcon#read 6, iclass 27, count 2 2006.210.08:00:09.30#ibcon#end of sib2, iclass 27, count 2 2006.210.08:00:09.30#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:00:09.30#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:00:09.30#ibcon#[25=AT06-06\r\n] 2006.210.08:00:09.30#ibcon#*before write, iclass 27, count 2 2006.210.08:00:09.30#ibcon#enter sib2, iclass 27, count 2 2006.210.08:00:09.30#ibcon#flushed, iclass 27, count 2 2006.210.08:00:09.30#ibcon#about to write, iclass 27, count 2 2006.210.08:00:09.30#ibcon#wrote, iclass 27, count 2 2006.210.08:00:09.30#ibcon#about to read 3, iclass 27, count 2 2006.210.08:00:09.33#ibcon#read 3, iclass 27, count 2 2006.210.08:00:09.33#ibcon#about to read 4, iclass 27, count 2 2006.210.08:00:09.33#ibcon#read 4, iclass 27, count 2 2006.210.08:00:09.33#ibcon#about to read 5, iclass 27, count 2 2006.210.08:00:09.33#ibcon#read 5, iclass 27, count 2 2006.210.08:00:09.33#ibcon#about to read 6, iclass 27, count 2 2006.210.08:00:09.33#ibcon#read 6, iclass 27, count 2 2006.210.08:00:09.33#ibcon#end of sib2, iclass 27, count 2 2006.210.08:00:09.33#ibcon#*after write, iclass 27, count 2 2006.210.08:00:09.33#ibcon#*before return 0, iclass 27, count 2 2006.210.08:00:09.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:00:09.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:00:09.33#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:00:09.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:09.33#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:00:09.45#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:00:09.45#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:00:09.45#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:00:09.45#ibcon#first serial, iclass 27, count 0 2006.210.08:00:09.45#ibcon#enter sib2, iclass 27, count 0 2006.210.08:00:09.45#ibcon#flushed, iclass 27, count 0 2006.210.08:00:09.45#ibcon#about to write, iclass 27, count 0 2006.210.08:00:09.45#ibcon#wrote, iclass 27, count 0 2006.210.08:00:09.45#ibcon#about to read 3, iclass 27, count 0 2006.210.08:00:09.47#ibcon#read 3, iclass 27, count 0 2006.210.08:00:09.47#ibcon#about to read 4, iclass 27, count 0 2006.210.08:00:09.47#ibcon#read 4, iclass 27, count 0 2006.210.08:00:09.47#ibcon#about to read 5, iclass 27, count 0 2006.210.08:00:09.47#ibcon#read 5, iclass 27, count 0 2006.210.08:00:09.47#ibcon#about to read 6, iclass 27, count 0 2006.210.08:00:09.47#ibcon#read 6, iclass 27, count 0 2006.210.08:00:09.47#ibcon#end of sib2, iclass 27, count 0 2006.210.08:00:09.47#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:00:09.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:00:09.47#ibcon#[25=USB\r\n] 2006.210.08:00:09.47#ibcon#*before write, iclass 27, count 0 2006.210.08:00:09.47#ibcon#enter sib2, iclass 27, count 0 2006.210.08:00:09.47#ibcon#flushed, iclass 27, count 0 2006.210.08:00:09.47#ibcon#about to write, iclass 27, count 0 2006.210.08:00:09.47#ibcon#wrote, iclass 27, count 0 2006.210.08:00:09.47#ibcon#about to read 3, iclass 27, count 0 2006.210.08:00:09.50#ibcon#read 3, iclass 27, count 0 2006.210.08:00:09.50#ibcon#about to read 4, iclass 27, count 0 2006.210.08:00:09.50#ibcon#read 4, iclass 27, count 0 2006.210.08:00:09.50#ibcon#about to read 5, iclass 27, count 0 2006.210.08:00:09.50#ibcon#read 5, iclass 27, count 0 2006.210.08:00:09.50#ibcon#about to read 6, iclass 27, count 0 2006.210.08:00:09.50#ibcon#read 6, iclass 27, count 0 2006.210.08:00:09.50#ibcon#end of sib2, iclass 27, count 0 2006.210.08:00:09.50#ibcon#*after write, iclass 27, count 0 2006.210.08:00:09.50#ibcon#*before return 0, iclass 27, count 0 2006.210.08:00:09.50#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:00:09.50#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:00:09.50#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:00:09.50#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:00:09.50$vc4f8/valo=7,832.99 2006.210.08:00:09.50#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:00:09.50#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:00:09.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:09.50#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:00:09.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:00:09.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:00:09.50#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:00:09.50#ibcon#first serial, iclass 29, count 0 2006.210.08:00:09.50#ibcon#enter sib2, iclass 29, count 0 2006.210.08:00:09.50#ibcon#flushed, iclass 29, count 0 2006.210.08:00:09.50#ibcon#about to write, iclass 29, count 0 2006.210.08:00:09.50#ibcon#wrote, iclass 29, count 0 2006.210.08:00:09.50#ibcon#about to read 3, iclass 29, count 0 2006.210.08:00:09.52#ibcon#read 3, iclass 29, count 0 2006.210.08:00:09.52#ibcon#about to read 4, iclass 29, count 0 2006.210.08:00:09.52#ibcon#read 4, iclass 29, count 0 2006.210.08:00:09.52#ibcon#about to read 5, iclass 29, count 0 2006.210.08:00:09.52#ibcon#read 5, iclass 29, count 0 2006.210.08:00:09.52#ibcon#about to read 6, iclass 29, count 0 2006.210.08:00:09.52#ibcon#read 6, iclass 29, count 0 2006.210.08:00:09.52#ibcon#end of sib2, iclass 29, count 0 2006.210.08:00:09.52#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:00:09.52#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:00:09.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:00:09.52#ibcon#*before write, iclass 29, count 0 2006.210.08:00:09.52#ibcon#enter sib2, iclass 29, count 0 2006.210.08:00:09.52#ibcon#flushed, iclass 29, count 0 2006.210.08:00:09.52#ibcon#about to write, iclass 29, count 0 2006.210.08:00:09.52#ibcon#wrote, iclass 29, count 0 2006.210.08:00:09.52#ibcon#about to read 3, iclass 29, count 0 2006.210.08:00:09.56#ibcon#read 3, iclass 29, count 0 2006.210.08:00:09.56#ibcon#about to read 4, iclass 29, count 0 2006.210.08:00:09.56#ibcon#read 4, iclass 29, count 0 2006.210.08:00:09.56#ibcon#about to read 5, iclass 29, count 0 2006.210.08:00:09.56#ibcon#read 5, iclass 29, count 0 2006.210.08:00:09.56#ibcon#about to read 6, iclass 29, count 0 2006.210.08:00:09.56#ibcon#read 6, iclass 29, count 0 2006.210.08:00:09.56#ibcon#end of sib2, iclass 29, count 0 2006.210.08:00:09.56#ibcon#*after write, iclass 29, count 0 2006.210.08:00:09.56#ibcon#*before return 0, iclass 29, count 0 2006.210.08:00:09.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:00:09.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:00:09.56#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:00:09.56#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:00:09.56$vc4f8/va=7,6 2006.210.08:00:09.56#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.08:00:09.56#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.08:00:09.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:09.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:00:09.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:00:09.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:00:09.62#ibcon#enter wrdev, iclass 31, count 2 2006.210.08:00:09.62#ibcon#first serial, iclass 31, count 2 2006.210.08:00:09.62#ibcon#enter sib2, iclass 31, count 2 2006.210.08:00:09.62#ibcon#flushed, iclass 31, count 2 2006.210.08:00:09.62#ibcon#about to write, iclass 31, count 2 2006.210.08:00:09.62#ibcon#wrote, iclass 31, count 2 2006.210.08:00:09.62#ibcon#about to read 3, iclass 31, count 2 2006.210.08:00:09.64#ibcon#read 3, iclass 31, count 2 2006.210.08:00:09.64#ibcon#about to read 4, iclass 31, count 2 2006.210.08:00:09.64#ibcon#read 4, iclass 31, count 2 2006.210.08:00:09.64#ibcon#about to read 5, iclass 31, count 2 2006.210.08:00:09.64#ibcon#read 5, iclass 31, count 2 2006.210.08:00:09.64#ibcon#about to read 6, iclass 31, count 2 2006.210.08:00:09.64#ibcon#read 6, iclass 31, count 2 2006.210.08:00:09.64#ibcon#end of sib2, iclass 31, count 2 2006.210.08:00:09.64#ibcon#*mode == 0, iclass 31, count 2 2006.210.08:00:09.64#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.08:00:09.64#ibcon#[25=AT07-06\r\n] 2006.210.08:00:09.64#ibcon#*before write, iclass 31, count 2 2006.210.08:00:09.64#ibcon#enter sib2, iclass 31, count 2 2006.210.08:00:09.64#ibcon#flushed, iclass 31, count 2 2006.210.08:00:09.64#ibcon#about to write, iclass 31, count 2 2006.210.08:00:09.64#ibcon#wrote, iclass 31, count 2 2006.210.08:00:09.64#ibcon#about to read 3, iclass 31, count 2 2006.210.08:00:09.67#ibcon#read 3, iclass 31, count 2 2006.210.08:00:09.67#ibcon#about to read 4, iclass 31, count 2 2006.210.08:00:09.67#ibcon#read 4, iclass 31, count 2 2006.210.08:00:09.67#ibcon#about to read 5, iclass 31, count 2 2006.210.08:00:09.67#ibcon#read 5, iclass 31, count 2 2006.210.08:00:09.67#ibcon#about to read 6, iclass 31, count 2 2006.210.08:00:09.67#ibcon#read 6, iclass 31, count 2 2006.210.08:00:09.67#ibcon#end of sib2, iclass 31, count 2 2006.210.08:00:09.67#ibcon#*after write, iclass 31, count 2 2006.210.08:00:09.67#ibcon#*before return 0, iclass 31, count 2 2006.210.08:00:09.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:00:09.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:00:09.67#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.08:00:09.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:09.67#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:00:09.79#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:00:09.79#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:00:09.79#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:00:09.79#ibcon#first serial, iclass 31, count 0 2006.210.08:00:09.79#ibcon#enter sib2, iclass 31, count 0 2006.210.08:00:09.79#ibcon#flushed, iclass 31, count 0 2006.210.08:00:09.79#ibcon#about to write, iclass 31, count 0 2006.210.08:00:09.79#ibcon#wrote, iclass 31, count 0 2006.210.08:00:09.79#ibcon#about to read 3, iclass 31, count 0 2006.210.08:00:09.81#ibcon#read 3, iclass 31, count 0 2006.210.08:00:09.81#ibcon#about to read 4, iclass 31, count 0 2006.210.08:00:09.81#ibcon#read 4, iclass 31, count 0 2006.210.08:00:09.81#ibcon#about to read 5, iclass 31, count 0 2006.210.08:00:09.81#ibcon#read 5, iclass 31, count 0 2006.210.08:00:09.81#ibcon#about to read 6, iclass 31, count 0 2006.210.08:00:09.81#ibcon#read 6, iclass 31, count 0 2006.210.08:00:09.81#ibcon#end of sib2, iclass 31, count 0 2006.210.08:00:09.81#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:00:09.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:00:09.81#ibcon#[25=USB\r\n] 2006.210.08:00:09.81#ibcon#*before write, iclass 31, count 0 2006.210.08:00:09.81#ibcon#enter sib2, iclass 31, count 0 2006.210.08:00:09.81#ibcon#flushed, iclass 31, count 0 2006.210.08:00:09.81#ibcon#about to write, iclass 31, count 0 2006.210.08:00:09.81#ibcon#wrote, iclass 31, count 0 2006.210.08:00:09.81#ibcon#about to read 3, iclass 31, count 0 2006.210.08:00:09.84#ibcon#read 3, iclass 31, count 0 2006.210.08:00:09.84#ibcon#about to read 4, iclass 31, count 0 2006.210.08:00:09.84#ibcon#read 4, iclass 31, count 0 2006.210.08:00:09.84#ibcon#about to read 5, iclass 31, count 0 2006.210.08:00:09.84#ibcon#read 5, iclass 31, count 0 2006.210.08:00:09.84#ibcon#about to read 6, iclass 31, count 0 2006.210.08:00:09.84#ibcon#read 6, iclass 31, count 0 2006.210.08:00:09.84#ibcon#end of sib2, iclass 31, count 0 2006.210.08:00:09.84#ibcon#*after write, iclass 31, count 0 2006.210.08:00:09.84#ibcon#*before return 0, iclass 31, count 0 2006.210.08:00:09.84#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:00:09.84#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:00:09.84#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:00:09.84#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:00:09.84$vc4f8/valo=8,852.99 2006.210.08:00:09.84#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:00:09.84#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:00:09.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:09.84#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:00:09.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:00:09.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:00:09.84#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:00:09.84#ibcon#first serial, iclass 33, count 0 2006.210.08:00:09.84#ibcon#enter sib2, iclass 33, count 0 2006.210.08:00:09.84#ibcon#flushed, iclass 33, count 0 2006.210.08:00:09.84#ibcon#about to write, iclass 33, count 0 2006.210.08:00:09.84#ibcon#wrote, iclass 33, count 0 2006.210.08:00:09.84#ibcon#about to read 3, iclass 33, count 0 2006.210.08:00:09.86#ibcon#read 3, iclass 33, count 0 2006.210.08:00:09.86#ibcon#about to read 4, iclass 33, count 0 2006.210.08:00:09.86#ibcon#read 4, iclass 33, count 0 2006.210.08:00:09.86#ibcon#about to read 5, iclass 33, count 0 2006.210.08:00:09.86#ibcon#read 5, iclass 33, count 0 2006.210.08:00:09.86#ibcon#about to read 6, iclass 33, count 0 2006.210.08:00:09.86#ibcon#read 6, iclass 33, count 0 2006.210.08:00:09.86#ibcon#end of sib2, iclass 33, count 0 2006.210.08:00:09.86#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:00:09.86#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:00:09.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:00:09.86#ibcon#*before write, iclass 33, count 0 2006.210.08:00:09.86#ibcon#enter sib2, iclass 33, count 0 2006.210.08:00:09.86#ibcon#flushed, iclass 33, count 0 2006.210.08:00:09.86#ibcon#about to write, iclass 33, count 0 2006.210.08:00:09.86#ibcon#wrote, iclass 33, count 0 2006.210.08:00:09.86#ibcon#about to read 3, iclass 33, count 0 2006.210.08:00:09.90#ibcon#read 3, iclass 33, count 0 2006.210.08:00:09.90#ibcon#about to read 4, iclass 33, count 0 2006.210.08:00:09.90#ibcon#read 4, iclass 33, count 0 2006.210.08:00:09.90#ibcon#about to read 5, iclass 33, count 0 2006.210.08:00:09.90#ibcon#read 5, iclass 33, count 0 2006.210.08:00:09.90#ibcon#about to read 6, iclass 33, count 0 2006.210.08:00:09.90#ibcon#read 6, iclass 33, count 0 2006.210.08:00:09.90#ibcon#end of sib2, iclass 33, count 0 2006.210.08:00:09.90#ibcon#*after write, iclass 33, count 0 2006.210.08:00:09.90#ibcon#*before return 0, iclass 33, count 0 2006.210.08:00:09.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:00:09.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:00:09.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:00:09.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:00:09.90$vc4f8/va=8,7 2006.210.08:00:09.90#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:00:09.90#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:00:09.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:09.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:00:09.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:00:09.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:00:09.96#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:00:09.96#ibcon#first serial, iclass 35, count 2 2006.210.08:00:09.96#ibcon#enter sib2, iclass 35, count 2 2006.210.08:00:09.96#ibcon#flushed, iclass 35, count 2 2006.210.08:00:09.96#ibcon#about to write, iclass 35, count 2 2006.210.08:00:09.96#ibcon#wrote, iclass 35, count 2 2006.210.08:00:09.96#ibcon#about to read 3, iclass 35, count 2 2006.210.08:00:09.98#ibcon#read 3, iclass 35, count 2 2006.210.08:00:09.98#ibcon#about to read 4, iclass 35, count 2 2006.210.08:00:09.98#ibcon#read 4, iclass 35, count 2 2006.210.08:00:09.98#ibcon#about to read 5, iclass 35, count 2 2006.210.08:00:09.98#ibcon#read 5, iclass 35, count 2 2006.210.08:00:09.98#ibcon#about to read 6, iclass 35, count 2 2006.210.08:00:09.98#ibcon#read 6, iclass 35, count 2 2006.210.08:00:09.98#ibcon#end of sib2, iclass 35, count 2 2006.210.08:00:09.98#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:00:09.98#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:00:09.98#ibcon#[25=AT08-07\r\n] 2006.210.08:00:09.98#ibcon#*before write, iclass 35, count 2 2006.210.08:00:09.98#ibcon#enter sib2, iclass 35, count 2 2006.210.08:00:09.98#ibcon#flushed, iclass 35, count 2 2006.210.08:00:09.98#ibcon#about to write, iclass 35, count 2 2006.210.08:00:09.98#ibcon#wrote, iclass 35, count 2 2006.210.08:00:09.98#ibcon#about to read 3, iclass 35, count 2 2006.210.08:00:10.01#ibcon#read 3, iclass 35, count 2 2006.210.08:00:10.01#ibcon#about to read 4, iclass 35, count 2 2006.210.08:00:10.01#ibcon#read 4, iclass 35, count 2 2006.210.08:00:10.01#ibcon#about to read 5, iclass 35, count 2 2006.210.08:00:10.01#ibcon#read 5, iclass 35, count 2 2006.210.08:00:10.01#ibcon#about to read 6, iclass 35, count 2 2006.210.08:00:10.01#ibcon#read 6, iclass 35, count 2 2006.210.08:00:10.01#ibcon#end of sib2, iclass 35, count 2 2006.210.08:00:10.01#ibcon#*after write, iclass 35, count 2 2006.210.08:00:10.01#ibcon#*before return 0, iclass 35, count 2 2006.210.08:00:10.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:00:10.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:00:10.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:00:10.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:10.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:00:10.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:00:10.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:00:10.13#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:00:10.13#ibcon#first serial, iclass 35, count 0 2006.210.08:00:10.13#ibcon#enter sib2, iclass 35, count 0 2006.210.08:00:10.13#ibcon#flushed, iclass 35, count 0 2006.210.08:00:10.13#ibcon#about to write, iclass 35, count 0 2006.210.08:00:10.13#ibcon#wrote, iclass 35, count 0 2006.210.08:00:10.13#ibcon#about to read 3, iclass 35, count 0 2006.210.08:00:10.15#ibcon#read 3, iclass 35, count 0 2006.210.08:00:10.15#ibcon#about to read 4, iclass 35, count 0 2006.210.08:00:10.15#ibcon#read 4, iclass 35, count 0 2006.210.08:00:10.15#ibcon#about to read 5, iclass 35, count 0 2006.210.08:00:10.15#ibcon#read 5, iclass 35, count 0 2006.210.08:00:10.15#ibcon#about to read 6, iclass 35, count 0 2006.210.08:00:10.15#ibcon#read 6, iclass 35, count 0 2006.210.08:00:10.15#ibcon#end of sib2, iclass 35, count 0 2006.210.08:00:10.15#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:00:10.15#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:00:10.15#ibcon#[25=USB\r\n] 2006.210.08:00:10.15#ibcon#*before write, iclass 35, count 0 2006.210.08:00:10.15#ibcon#enter sib2, iclass 35, count 0 2006.210.08:00:10.15#ibcon#flushed, iclass 35, count 0 2006.210.08:00:10.15#ibcon#about to write, iclass 35, count 0 2006.210.08:00:10.15#ibcon#wrote, iclass 35, count 0 2006.210.08:00:10.15#ibcon#about to read 3, iclass 35, count 0 2006.210.08:00:10.18#ibcon#read 3, iclass 35, count 0 2006.210.08:00:10.18#ibcon#about to read 4, iclass 35, count 0 2006.210.08:00:10.18#ibcon#read 4, iclass 35, count 0 2006.210.08:00:10.18#ibcon#about to read 5, iclass 35, count 0 2006.210.08:00:10.18#ibcon#read 5, iclass 35, count 0 2006.210.08:00:10.18#ibcon#about to read 6, iclass 35, count 0 2006.210.08:00:10.18#ibcon#read 6, iclass 35, count 0 2006.210.08:00:10.18#ibcon#end of sib2, iclass 35, count 0 2006.210.08:00:10.18#ibcon#*after write, iclass 35, count 0 2006.210.08:00:10.18#ibcon#*before return 0, iclass 35, count 0 2006.210.08:00:10.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:00:10.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:00:10.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:00:10.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:00:10.18$vc4f8/vblo=1,632.99 2006.210.08:00:10.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:00:10.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:00:10.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:10.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:00:10.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:00:10.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:00:10.18#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:00:10.18#ibcon#first serial, iclass 37, count 0 2006.210.08:00:10.18#ibcon#enter sib2, iclass 37, count 0 2006.210.08:00:10.18#ibcon#flushed, iclass 37, count 0 2006.210.08:00:10.18#ibcon#about to write, iclass 37, count 0 2006.210.08:00:10.18#ibcon#wrote, iclass 37, count 0 2006.210.08:00:10.18#ibcon#about to read 3, iclass 37, count 0 2006.210.08:00:10.20#ibcon#read 3, iclass 37, count 0 2006.210.08:00:10.20#ibcon#about to read 4, iclass 37, count 0 2006.210.08:00:10.20#ibcon#read 4, iclass 37, count 0 2006.210.08:00:10.20#ibcon#about to read 5, iclass 37, count 0 2006.210.08:00:10.20#ibcon#read 5, iclass 37, count 0 2006.210.08:00:10.20#ibcon#about to read 6, iclass 37, count 0 2006.210.08:00:10.20#ibcon#read 6, iclass 37, count 0 2006.210.08:00:10.20#ibcon#end of sib2, iclass 37, count 0 2006.210.08:00:10.20#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:00:10.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:00:10.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:00:10.20#ibcon#*before write, iclass 37, count 0 2006.210.08:00:10.20#ibcon#enter sib2, iclass 37, count 0 2006.210.08:00:10.20#ibcon#flushed, iclass 37, count 0 2006.210.08:00:10.20#ibcon#about to write, iclass 37, count 0 2006.210.08:00:10.20#ibcon#wrote, iclass 37, count 0 2006.210.08:00:10.20#ibcon#about to read 3, iclass 37, count 0 2006.210.08:00:10.24#ibcon#read 3, iclass 37, count 0 2006.210.08:00:10.24#ibcon#about to read 4, iclass 37, count 0 2006.210.08:00:10.24#ibcon#read 4, iclass 37, count 0 2006.210.08:00:10.24#ibcon#about to read 5, iclass 37, count 0 2006.210.08:00:10.24#ibcon#read 5, iclass 37, count 0 2006.210.08:00:10.24#ibcon#about to read 6, iclass 37, count 0 2006.210.08:00:10.24#ibcon#read 6, iclass 37, count 0 2006.210.08:00:10.24#ibcon#end of sib2, iclass 37, count 0 2006.210.08:00:10.24#ibcon#*after write, iclass 37, count 0 2006.210.08:00:10.24#ibcon#*before return 0, iclass 37, count 0 2006.210.08:00:10.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:00:10.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:00:10.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:00:10.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:00:10.24$vc4f8/vb=1,4 2006.210.08:00:10.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:00:10.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:00:10.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:10.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:00:10.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:00:10.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:00:10.24#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:00:10.24#ibcon#first serial, iclass 39, count 2 2006.210.08:00:10.24#ibcon#enter sib2, iclass 39, count 2 2006.210.08:00:10.24#ibcon#flushed, iclass 39, count 2 2006.210.08:00:10.24#ibcon#about to write, iclass 39, count 2 2006.210.08:00:10.24#ibcon#wrote, iclass 39, count 2 2006.210.08:00:10.24#ibcon#about to read 3, iclass 39, count 2 2006.210.08:00:10.26#ibcon#read 3, iclass 39, count 2 2006.210.08:00:10.26#ibcon#about to read 4, iclass 39, count 2 2006.210.08:00:10.26#ibcon#read 4, iclass 39, count 2 2006.210.08:00:10.26#ibcon#about to read 5, iclass 39, count 2 2006.210.08:00:10.26#ibcon#read 5, iclass 39, count 2 2006.210.08:00:10.26#ibcon#about to read 6, iclass 39, count 2 2006.210.08:00:10.26#ibcon#read 6, iclass 39, count 2 2006.210.08:00:10.26#ibcon#end of sib2, iclass 39, count 2 2006.210.08:00:10.26#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:00:10.26#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:00:10.26#ibcon#[27=AT01-04\r\n] 2006.210.08:00:10.26#ibcon#*before write, iclass 39, count 2 2006.210.08:00:10.26#ibcon#enter sib2, iclass 39, count 2 2006.210.08:00:10.26#ibcon#flushed, iclass 39, count 2 2006.210.08:00:10.26#ibcon#about to write, iclass 39, count 2 2006.210.08:00:10.26#ibcon#wrote, iclass 39, count 2 2006.210.08:00:10.26#ibcon#about to read 3, iclass 39, count 2 2006.210.08:00:10.29#ibcon#read 3, iclass 39, count 2 2006.210.08:00:10.29#ibcon#about to read 4, iclass 39, count 2 2006.210.08:00:10.29#ibcon#read 4, iclass 39, count 2 2006.210.08:00:10.29#ibcon#about to read 5, iclass 39, count 2 2006.210.08:00:10.29#ibcon#read 5, iclass 39, count 2 2006.210.08:00:10.29#ibcon#about to read 6, iclass 39, count 2 2006.210.08:00:10.29#ibcon#read 6, iclass 39, count 2 2006.210.08:00:10.29#ibcon#end of sib2, iclass 39, count 2 2006.210.08:00:10.29#ibcon#*after write, iclass 39, count 2 2006.210.08:00:10.29#ibcon#*before return 0, iclass 39, count 2 2006.210.08:00:10.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:00:10.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:00:10.29#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:00:10.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:10.29#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:00:10.41#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:00:10.41#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:00:10.41#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:00:10.41#ibcon#first serial, iclass 39, count 0 2006.210.08:00:10.41#ibcon#enter sib2, iclass 39, count 0 2006.210.08:00:10.41#ibcon#flushed, iclass 39, count 0 2006.210.08:00:10.41#ibcon#about to write, iclass 39, count 0 2006.210.08:00:10.41#ibcon#wrote, iclass 39, count 0 2006.210.08:00:10.41#ibcon#about to read 3, iclass 39, count 0 2006.210.08:00:10.43#ibcon#read 3, iclass 39, count 0 2006.210.08:00:10.43#ibcon#about to read 4, iclass 39, count 0 2006.210.08:00:10.43#ibcon#read 4, iclass 39, count 0 2006.210.08:00:10.43#ibcon#about to read 5, iclass 39, count 0 2006.210.08:00:10.43#ibcon#read 5, iclass 39, count 0 2006.210.08:00:10.43#ibcon#about to read 6, iclass 39, count 0 2006.210.08:00:10.43#ibcon#read 6, iclass 39, count 0 2006.210.08:00:10.43#ibcon#end of sib2, iclass 39, count 0 2006.210.08:00:10.43#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:00:10.43#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:00:10.43#ibcon#[27=USB\r\n] 2006.210.08:00:10.43#ibcon#*before write, iclass 39, count 0 2006.210.08:00:10.43#ibcon#enter sib2, iclass 39, count 0 2006.210.08:00:10.43#ibcon#flushed, iclass 39, count 0 2006.210.08:00:10.43#ibcon#about to write, iclass 39, count 0 2006.210.08:00:10.43#ibcon#wrote, iclass 39, count 0 2006.210.08:00:10.43#ibcon#about to read 3, iclass 39, count 0 2006.210.08:00:10.46#ibcon#read 3, iclass 39, count 0 2006.210.08:00:10.46#ibcon#about to read 4, iclass 39, count 0 2006.210.08:00:10.46#ibcon#read 4, iclass 39, count 0 2006.210.08:00:10.46#ibcon#about to read 5, iclass 39, count 0 2006.210.08:00:10.46#ibcon#read 5, iclass 39, count 0 2006.210.08:00:10.46#ibcon#about to read 6, iclass 39, count 0 2006.210.08:00:10.46#ibcon#read 6, iclass 39, count 0 2006.210.08:00:10.46#ibcon#end of sib2, iclass 39, count 0 2006.210.08:00:10.46#ibcon#*after write, iclass 39, count 0 2006.210.08:00:10.46#ibcon#*before return 0, iclass 39, count 0 2006.210.08:00:10.46#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:00:10.46#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:00:10.46#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:00:10.46#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:00:10.46$vc4f8/vblo=2,640.99 2006.210.08:00:10.46#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:00:10.46#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:00:10.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:10.46#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:10.46#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:10.46#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:10.46#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:00:10.46#ibcon#first serial, iclass 3, count 0 2006.210.08:00:10.46#ibcon#enter sib2, iclass 3, count 0 2006.210.08:00:10.46#ibcon#flushed, iclass 3, count 0 2006.210.08:00:10.46#ibcon#about to write, iclass 3, count 0 2006.210.08:00:10.46#ibcon#wrote, iclass 3, count 0 2006.210.08:00:10.46#ibcon#about to read 3, iclass 3, count 0 2006.210.08:00:10.48#ibcon#read 3, iclass 3, count 0 2006.210.08:00:10.48#ibcon#about to read 4, iclass 3, count 0 2006.210.08:00:10.48#ibcon#read 4, iclass 3, count 0 2006.210.08:00:10.48#ibcon#about to read 5, iclass 3, count 0 2006.210.08:00:10.48#ibcon#read 5, iclass 3, count 0 2006.210.08:00:10.48#ibcon#about to read 6, iclass 3, count 0 2006.210.08:00:10.48#ibcon#read 6, iclass 3, count 0 2006.210.08:00:10.48#ibcon#end of sib2, iclass 3, count 0 2006.210.08:00:10.48#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:00:10.48#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:00:10.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:00:10.48#ibcon#*before write, iclass 3, count 0 2006.210.08:00:10.48#ibcon#enter sib2, iclass 3, count 0 2006.210.08:00:10.48#ibcon#flushed, iclass 3, count 0 2006.210.08:00:10.48#ibcon#about to write, iclass 3, count 0 2006.210.08:00:10.48#ibcon#wrote, iclass 3, count 0 2006.210.08:00:10.48#ibcon#about to read 3, iclass 3, count 0 2006.210.08:00:10.52#ibcon#read 3, iclass 3, count 0 2006.210.08:00:10.52#ibcon#about to read 4, iclass 3, count 0 2006.210.08:00:10.52#ibcon#read 4, iclass 3, count 0 2006.210.08:00:10.52#ibcon#about to read 5, iclass 3, count 0 2006.210.08:00:10.52#ibcon#read 5, iclass 3, count 0 2006.210.08:00:10.52#ibcon#about to read 6, iclass 3, count 0 2006.210.08:00:10.52#ibcon#read 6, iclass 3, count 0 2006.210.08:00:10.52#ibcon#end of sib2, iclass 3, count 0 2006.210.08:00:10.52#ibcon#*after write, iclass 3, count 0 2006.210.08:00:10.52#ibcon#*before return 0, iclass 3, count 0 2006.210.08:00:10.52#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:10.52#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:00:10.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:00:10.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:00:10.52$vc4f8/vb=2,4 2006.210.08:00:10.52#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:00:10.52#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:00:10.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:10.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:10.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:10.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:10.58#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:00:10.58#ibcon#first serial, iclass 5, count 2 2006.210.08:00:10.58#ibcon#enter sib2, iclass 5, count 2 2006.210.08:00:10.58#ibcon#flushed, iclass 5, count 2 2006.210.08:00:10.58#ibcon#about to write, iclass 5, count 2 2006.210.08:00:10.58#ibcon#wrote, iclass 5, count 2 2006.210.08:00:10.58#ibcon#about to read 3, iclass 5, count 2 2006.210.08:00:10.60#ibcon#read 3, iclass 5, count 2 2006.210.08:00:10.60#ibcon#about to read 4, iclass 5, count 2 2006.210.08:00:10.60#ibcon#read 4, iclass 5, count 2 2006.210.08:00:10.60#ibcon#about to read 5, iclass 5, count 2 2006.210.08:00:10.60#ibcon#read 5, iclass 5, count 2 2006.210.08:00:10.60#ibcon#about to read 6, iclass 5, count 2 2006.210.08:00:10.60#ibcon#read 6, iclass 5, count 2 2006.210.08:00:10.60#ibcon#end of sib2, iclass 5, count 2 2006.210.08:00:10.60#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:00:10.60#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:00:10.60#ibcon#[27=AT02-04\r\n] 2006.210.08:00:10.60#ibcon#*before write, iclass 5, count 2 2006.210.08:00:10.60#ibcon#enter sib2, iclass 5, count 2 2006.210.08:00:10.60#ibcon#flushed, iclass 5, count 2 2006.210.08:00:10.60#ibcon#about to write, iclass 5, count 2 2006.210.08:00:10.60#ibcon#wrote, iclass 5, count 2 2006.210.08:00:10.60#ibcon#about to read 3, iclass 5, count 2 2006.210.08:00:10.63#ibcon#read 3, iclass 5, count 2 2006.210.08:00:10.63#ibcon#about to read 4, iclass 5, count 2 2006.210.08:00:10.63#ibcon#read 4, iclass 5, count 2 2006.210.08:00:10.63#ibcon#about to read 5, iclass 5, count 2 2006.210.08:00:10.63#ibcon#read 5, iclass 5, count 2 2006.210.08:00:10.63#ibcon#about to read 6, iclass 5, count 2 2006.210.08:00:10.63#ibcon#read 6, iclass 5, count 2 2006.210.08:00:10.63#ibcon#end of sib2, iclass 5, count 2 2006.210.08:00:10.63#ibcon#*after write, iclass 5, count 2 2006.210.08:00:10.63#ibcon#*before return 0, iclass 5, count 2 2006.210.08:00:10.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:10.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:00:10.63#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:00:10.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:10.63#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:10.75#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:10.75#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:10.75#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:00:10.75#ibcon#first serial, iclass 5, count 0 2006.210.08:00:10.75#ibcon#enter sib2, iclass 5, count 0 2006.210.08:00:10.75#ibcon#flushed, iclass 5, count 0 2006.210.08:00:10.75#ibcon#about to write, iclass 5, count 0 2006.210.08:00:10.75#ibcon#wrote, iclass 5, count 0 2006.210.08:00:10.75#ibcon#about to read 3, iclass 5, count 0 2006.210.08:00:10.77#ibcon#read 3, iclass 5, count 0 2006.210.08:00:10.77#ibcon#about to read 4, iclass 5, count 0 2006.210.08:00:10.77#ibcon#read 4, iclass 5, count 0 2006.210.08:00:10.77#ibcon#about to read 5, iclass 5, count 0 2006.210.08:00:10.77#ibcon#read 5, iclass 5, count 0 2006.210.08:00:10.77#ibcon#about to read 6, iclass 5, count 0 2006.210.08:00:10.77#ibcon#read 6, iclass 5, count 0 2006.210.08:00:10.77#ibcon#end of sib2, iclass 5, count 0 2006.210.08:00:10.77#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:00:10.77#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:00:10.77#ibcon#[27=USB\r\n] 2006.210.08:00:10.77#ibcon#*before write, iclass 5, count 0 2006.210.08:00:10.77#ibcon#enter sib2, iclass 5, count 0 2006.210.08:00:10.77#ibcon#flushed, iclass 5, count 0 2006.210.08:00:10.77#ibcon#about to write, iclass 5, count 0 2006.210.08:00:10.77#ibcon#wrote, iclass 5, count 0 2006.210.08:00:10.77#ibcon#about to read 3, iclass 5, count 0 2006.210.08:00:10.80#ibcon#read 3, iclass 5, count 0 2006.210.08:00:10.80#ibcon#about to read 4, iclass 5, count 0 2006.210.08:00:10.80#ibcon#read 4, iclass 5, count 0 2006.210.08:00:10.80#ibcon#about to read 5, iclass 5, count 0 2006.210.08:00:10.80#ibcon#read 5, iclass 5, count 0 2006.210.08:00:10.80#ibcon#about to read 6, iclass 5, count 0 2006.210.08:00:10.80#ibcon#read 6, iclass 5, count 0 2006.210.08:00:10.80#ibcon#end of sib2, iclass 5, count 0 2006.210.08:00:10.80#ibcon#*after write, iclass 5, count 0 2006.210.08:00:10.80#ibcon#*before return 0, iclass 5, count 0 2006.210.08:00:10.80#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:10.80#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:00:10.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:00:10.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:00:10.80$vc4f8/vblo=3,656.99 2006.210.08:00:10.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:00:10.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:00:10.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:10.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:10.80#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:10.80#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:10.80#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:00:10.80#ibcon#first serial, iclass 7, count 0 2006.210.08:00:10.80#ibcon#enter sib2, iclass 7, count 0 2006.210.08:00:10.80#ibcon#flushed, iclass 7, count 0 2006.210.08:00:10.80#ibcon#about to write, iclass 7, count 0 2006.210.08:00:10.80#ibcon#wrote, iclass 7, count 0 2006.210.08:00:10.80#ibcon#about to read 3, iclass 7, count 0 2006.210.08:00:10.82#ibcon#read 3, iclass 7, count 0 2006.210.08:00:10.82#ibcon#about to read 4, iclass 7, count 0 2006.210.08:00:10.82#ibcon#read 4, iclass 7, count 0 2006.210.08:00:10.82#ibcon#about to read 5, iclass 7, count 0 2006.210.08:00:10.82#ibcon#read 5, iclass 7, count 0 2006.210.08:00:10.82#ibcon#about to read 6, iclass 7, count 0 2006.210.08:00:10.82#ibcon#read 6, iclass 7, count 0 2006.210.08:00:10.82#ibcon#end of sib2, iclass 7, count 0 2006.210.08:00:10.82#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:00:10.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:00:10.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:00:10.82#ibcon#*before write, iclass 7, count 0 2006.210.08:00:10.82#ibcon#enter sib2, iclass 7, count 0 2006.210.08:00:10.82#ibcon#flushed, iclass 7, count 0 2006.210.08:00:10.82#ibcon#about to write, iclass 7, count 0 2006.210.08:00:10.82#ibcon#wrote, iclass 7, count 0 2006.210.08:00:10.82#ibcon#about to read 3, iclass 7, count 0 2006.210.08:00:10.86#ibcon#read 3, iclass 7, count 0 2006.210.08:00:10.86#ibcon#about to read 4, iclass 7, count 0 2006.210.08:00:10.86#ibcon#read 4, iclass 7, count 0 2006.210.08:00:10.86#ibcon#about to read 5, iclass 7, count 0 2006.210.08:00:10.86#ibcon#read 5, iclass 7, count 0 2006.210.08:00:10.86#ibcon#about to read 6, iclass 7, count 0 2006.210.08:00:10.86#ibcon#read 6, iclass 7, count 0 2006.210.08:00:10.86#ibcon#end of sib2, iclass 7, count 0 2006.210.08:00:10.86#ibcon#*after write, iclass 7, count 0 2006.210.08:00:10.86#ibcon#*before return 0, iclass 7, count 0 2006.210.08:00:10.86#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:10.86#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:00:10.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:00:10.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:00:10.86$vc4f8/vb=3,3 2006.210.08:00:10.86#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:00:10.86#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:00:10.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:10.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:10.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:10.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:10.92#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:00:10.92#ibcon#first serial, iclass 11, count 2 2006.210.08:00:10.92#ibcon#enter sib2, iclass 11, count 2 2006.210.08:00:10.92#ibcon#flushed, iclass 11, count 2 2006.210.08:00:10.92#ibcon#about to write, iclass 11, count 2 2006.210.08:00:10.92#ibcon#wrote, iclass 11, count 2 2006.210.08:00:10.92#ibcon#about to read 3, iclass 11, count 2 2006.210.08:00:10.94#ibcon#read 3, iclass 11, count 2 2006.210.08:00:10.94#ibcon#about to read 4, iclass 11, count 2 2006.210.08:00:10.94#ibcon#read 4, iclass 11, count 2 2006.210.08:00:10.94#ibcon#about to read 5, iclass 11, count 2 2006.210.08:00:10.94#ibcon#read 5, iclass 11, count 2 2006.210.08:00:10.94#ibcon#about to read 6, iclass 11, count 2 2006.210.08:00:10.94#ibcon#read 6, iclass 11, count 2 2006.210.08:00:10.94#ibcon#end of sib2, iclass 11, count 2 2006.210.08:00:10.94#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:00:10.94#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:00:10.94#ibcon#[27=AT03-03\r\n] 2006.210.08:00:10.94#ibcon#*before write, iclass 11, count 2 2006.210.08:00:10.94#ibcon#enter sib2, iclass 11, count 2 2006.210.08:00:10.94#ibcon#flushed, iclass 11, count 2 2006.210.08:00:10.94#ibcon#about to write, iclass 11, count 2 2006.210.08:00:10.94#ibcon#wrote, iclass 11, count 2 2006.210.08:00:10.94#ibcon#about to read 3, iclass 11, count 2 2006.210.08:00:10.97#ibcon#read 3, iclass 11, count 2 2006.210.08:00:10.97#ibcon#about to read 4, iclass 11, count 2 2006.210.08:00:10.97#ibcon#read 4, iclass 11, count 2 2006.210.08:00:10.97#ibcon#about to read 5, iclass 11, count 2 2006.210.08:00:10.97#ibcon#read 5, iclass 11, count 2 2006.210.08:00:10.97#ibcon#about to read 6, iclass 11, count 2 2006.210.08:00:10.97#ibcon#read 6, iclass 11, count 2 2006.210.08:00:10.97#ibcon#end of sib2, iclass 11, count 2 2006.210.08:00:10.97#ibcon#*after write, iclass 11, count 2 2006.210.08:00:10.97#ibcon#*before return 0, iclass 11, count 2 2006.210.08:00:10.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:10.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:00:10.97#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:00:10.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:10.97#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:11.09#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:11.09#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:11.09#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:00:11.09#ibcon#first serial, iclass 11, count 0 2006.210.08:00:11.09#ibcon#enter sib2, iclass 11, count 0 2006.210.08:00:11.09#ibcon#flushed, iclass 11, count 0 2006.210.08:00:11.09#ibcon#about to write, iclass 11, count 0 2006.210.08:00:11.09#ibcon#wrote, iclass 11, count 0 2006.210.08:00:11.09#ibcon#about to read 3, iclass 11, count 0 2006.210.08:00:11.11#ibcon#read 3, iclass 11, count 0 2006.210.08:00:11.11#ibcon#about to read 4, iclass 11, count 0 2006.210.08:00:11.11#ibcon#read 4, iclass 11, count 0 2006.210.08:00:11.11#ibcon#about to read 5, iclass 11, count 0 2006.210.08:00:11.11#ibcon#read 5, iclass 11, count 0 2006.210.08:00:11.11#ibcon#about to read 6, iclass 11, count 0 2006.210.08:00:11.11#ibcon#read 6, iclass 11, count 0 2006.210.08:00:11.11#ibcon#end of sib2, iclass 11, count 0 2006.210.08:00:11.11#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:00:11.11#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:00:11.11#ibcon#[27=USB\r\n] 2006.210.08:00:11.11#ibcon#*before write, iclass 11, count 0 2006.210.08:00:11.11#ibcon#enter sib2, iclass 11, count 0 2006.210.08:00:11.11#ibcon#flushed, iclass 11, count 0 2006.210.08:00:11.11#ibcon#about to write, iclass 11, count 0 2006.210.08:00:11.11#ibcon#wrote, iclass 11, count 0 2006.210.08:00:11.11#ibcon#about to read 3, iclass 11, count 0 2006.210.08:00:11.14#ibcon#read 3, iclass 11, count 0 2006.210.08:00:11.14#ibcon#about to read 4, iclass 11, count 0 2006.210.08:00:11.14#ibcon#read 4, iclass 11, count 0 2006.210.08:00:11.14#ibcon#about to read 5, iclass 11, count 0 2006.210.08:00:11.14#ibcon#read 5, iclass 11, count 0 2006.210.08:00:11.14#ibcon#about to read 6, iclass 11, count 0 2006.210.08:00:11.14#ibcon#read 6, iclass 11, count 0 2006.210.08:00:11.14#ibcon#end of sib2, iclass 11, count 0 2006.210.08:00:11.14#ibcon#*after write, iclass 11, count 0 2006.210.08:00:11.14#ibcon#*before return 0, iclass 11, count 0 2006.210.08:00:11.14#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:11.14#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:00:11.14#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:00:11.14#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:00:11.14$vc4f8/vblo=4,712.99 2006.210.08:00:11.14#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:00:11.14#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:00:11.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:11.14#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:11.14#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:11.14#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:11.14#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:00:11.14#ibcon#first serial, iclass 13, count 0 2006.210.08:00:11.14#ibcon#enter sib2, iclass 13, count 0 2006.210.08:00:11.14#ibcon#flushed, iclass 13, count 0 2006.210.08:00:11.14#ibcon#about to write, iclass 13, count 0 2006.210.08:00:11.14#ibcon#wrote, iclass 13, count 0 2006.210.08:00:11.14#ibcon#about to read 3, iclass 13, count 0 2006.210.08:00:11.16#ibcon#read 3, iclass 13, count 0 2006.210.08:00:11.16#ibcon#about to read 4, iclass 13, count 0 2006.210.08:00:11.16#ibcon#read 4, iclass 13, count 0 2006.210.08:00:11.16#ibcon#about to read 5, iclass 13, count 0 2006.210.08:00:11.16#ibcon#read 5, iclass 13, count 0 2006.210.08:00:11.16#ibcon#about to read 6, iclass 13, count 0 2006.210.08:00:11.16#ibcon#read 6, iclass 13, count 0 2006.210.08:00:11.16#ibcon#end of sib2, iclass 13, count 0 2006.210.08:00:11.16#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:00:11.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:00:11.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:00:11.16#ibcon#*before write, iclass 13, count 0 2006.210.08:00:11.16#ibcon#enter sib2, iclass 13, count 0 2006.210.08:00:11.16#ibcon#flushed, iclass 13, count 0 2006.210.08:00:11.16#ibcon#about to write, iclass 13, count 0 2006.210.08:00:11.16#ibcon#wrote, iclass 13, count 0 2006.210.08:00:11.16#ibcon#about to read 3, iclass 13, count 0 2006.210.08:00:11.20#ibcon#read 3, iclass 13, count 0 2006.210.08:00:11.20#ibcon#about to read 4, iclass 13, count 0 2006.210.08:00:11.20#ibcon#read 4, iclass 13, count 0 2006.210.08:00:11.20#ibcon#about to read 5, iclass 13, count 0 2006.210.08:00:11.20#ibcon#read 5, iclass 13, count 0 2006.210.08:00:11.20#ibcon#about to read 6, iclass 13, count 0 2006.210.08:00:11.20#ibcon#read 6, iclass 13, count 0 2006.210.08:00:11.20#ibcon#end of sib2, iclass 13, count 0 2006.210.08:00:11.20#ibcon#*after write, iclass 13, count 0 2006.210.08:00:11.20#ibcon#*before return 0, iclass 13, count 0 2006.210.08:00:11.20#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:11.20#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:00:11.20#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:00:11.20#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:00:11.20$vc4f8/vb=4,3 2006.210.08:00:11.20#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:00:11.20#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:00:11.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:11.20#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:11.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:11.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:11.26#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:00:11.26#ibcon#first serial, iclass 15, count 2 2006.210.08:00:11.26#ibcon#enter sib2, iclass 15, count 2 2006.210.08:00:11.26#ibcon#flushed, iclass 15, count 2 2006.210.08:00:11.26#ibcon#about to write, iclass 15, count 2 2006.210.08:00:11.26#ibcon#wrote, iclass 15, count 2 2006.210.08:00:11.26#ibcon#about to read 3, iclass 15, count 2 2006.210.08:00:11.28#ibcon#read 3, iclass 15, count 2 2006.210.08:00:11.28#ibcon#about to read 4, iclass 15, count 2 2006.210.08:00:11.28#ibcon#read 4, iclass 15, count 2 2006.210.08:00:11.28#ibcon#about to read 5, iclass 15, count 2 2006.210.08:00:11.28#ibcon#read 5, iclass 15, count 2 2006.210.08:00:11.28#ibcon#about to read 6, iclass 15, count 2 2006.210.08:00:11.28#ibcon#read 6, iclass 15, count 2 2006.210.08:00:11.28#ibcon#end of sib2, iclass 15, count 2 2006.210.08:00:11.28#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:00:11.28#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:00:11.28#ibcon#[27=AT04-03\r\n] 2006.210.08:00:11.28#ibcon#*before write, iclass 15, count 2 2006.210.08:00:11.28#ibcon#enter sib2, iclass 15, count 2 2006.210.08:00:11.28#ibcon#flushed, iclass 15, count 2 2006.210.08:00:11.28#ibcon#about to write, iclass 15, count 2 2006.210.08:00:11.28#ibcon#wrote, iclass 15, count 2 2006.210.08:00:11.28#ibcon#about to read 3, iclass 15, count 2 2006.210.08:00:11.31#ibcon#read 3, iclass 15, count 2 2006.210.08:00:11.31#ibcon#about to read 4, iclass 15, count 2 2006.210.08:00:11.31#ibcon#read 4, iclass 15, count 2 2006.210.08:00:11.31#ibcon#about to read 5, iclass 15, count 2 2006.210.08:00:11.31#ibcon#read 5, iclass 15, count 2 2006.210.08:00:11.31#ibcon#about to read 6, iclass 15, count 2 2006.210.08:00:11.31#ibcon#read 6, iclass 15, count 2 2006.210.08:00:11.31#ibcon#end of sib2, iclass 15, count 2 2006.210.08:00:11.31#ibcon#*after write, iclass 15, count 2 2006.210.08:00:11.31#ibcon#*before return 0, iclass 15, count 2 2006.210.08:00:11.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:11.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:00:11.31#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:00:11.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:11.31#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:11.43#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:11.43#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:11.43#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:00:11.43#ibcon#first serial, iclass 15, count 0 2006.210.08:00:11.43#ibcon#enter sib2, iclass 15, count 0 2006.210.08:00:11.43#ibcon#flushed, iclass 15, count 0 2006.210.08:00:11.43#ibcon#about to write, iclass 15, count 0 2006.210.08:00:11.43#ibcon#wrote, iclass 15, count 0 2006.210.08:00:11.43#ibcon#about to read 3, iclass 15, count 0 2006.210.08:00:11.45#ibcon#read 3, iclass 15, count 0 2006.210.08:00:11.45#ibcon#about to read 4, iclass 15, count 0 2006.210.08:00:11.45#ibcon#read 4, iclass 15, count 0 2006.210.08:00:11.45#ibcon#about to read 5, iclass 15, count 0 2006.210.08:00:11.45#ibcon#read 5, iclass 15, count 0 2006.210.08:00:11.45#ibcon#about to read 6, iclass 15, count 0 2006.210.08:00:11.45#ibcon#read 6, iclass 15, count 0 2006.210.08:00:11.45#ibcon#end of sib2, iclass 15, count 0 2006.210.08:00:11.45#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:00:11.45#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:00:11.45#ibcon#[27=USB\r\n] 2006.210.08:00:11.45#ibcon#*before write, iclass 15, count 0 2006.210.08:00:11.45#ibcon#enter sib2, iclass 15, count 0 2006.210.08:00:11.45#ibcon#flushed, iclass 15, count 0 2006.210.08:00:11.45#ibcon#about to write, iclass 15, count 0 2006.210.08:00:11.45#ibcon#wrote, iclass 15, count 0 2006.210.08:00:11.45#ibcon#about to read 3, iclass 15, count 0 2006.210.08:00:11.48#ibcon#read 3, iclass 15, count 0 2006.210.08:00:11.48#ibcon#about to read 4, iclass 15, count 0 2006.210.08:00:11.48#ibcon#read 4, iclass 15, count 0 2006.210.08:00:11.48#ibcon#about to read 5, iclass 15, count 0 2006.210.08:00:11.48#ibcon#read 5, iclass 15, count 0 2006.210.08:00:11.48#ibcon#about to read 6, iclass 15, count 0 2006.210.08:00:11.48#ibcon#read 6, iclass 15, count 0 2006.210.08:00:11.48#ibcon#end of sib2, iclass 15, count 0 2006.210.08:00:11.48#ibcon#*after write, iclass 15, count 0 2006.210.08:00:11.48#ibcon#*before return 0, iclass 15, count 0 2006.210.08:00:11.48#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:11.48#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:00:11.48#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:00:11.48#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:00:11.48$vc4f8/vblo=5,744.99 2006.210.08:00:11.48#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:00:11.48#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:00:11.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:11.48#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:11.48#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:11.48#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:11.48#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:00:11.48#ibcon#first serial, iclass 17, count 0 2006.210.08:00:11.48#ibcon#enter sib2, iclass 17, count 0 2006.210.08:00:11.48#ibcon#flushed, iclass 17, count 0 2006.210.08:00:11.48#ibcon#about to write, iclass 17, count 0 2006.210.08:00:11.48#ibcon#wrote, iclass 17, count 0 2006.210.08:00:11.48#ibcon#about to read 3, iclass 17, count 0 2006.210.08:00:11.50#ibcon#read 3, iclass 17, count 0 2006.210.08:00:11.50#ibcon#about to read 4, iclass 17, count 0 2006.210.08:00:11.50#ibcon#read 4, iclass 17, count 0 2006.210.08:00:11.50#ibcon#about to read 5, iclass 17, count 0 2006.210.08:00:11.50#ibcon#read 5, iclass 17, count 0 2006.210.08:00:11.50#ibcon#about to read 6, iclass 17, count 0 2006.210.08:00:11.50#ibcon#read 6, iclass 17, count 0 2006.210.08:00:11.50#ibcon#end of sib2, iclass 17, count 0 2006.210.08:00:11.50#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:00:11.50#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:00:11.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:00:11.50#ibcon#*before write, iclass 17, count 0 2006.210.08:00:11.50#ibcon#enter sib2, iclass 17, count 0 2006.210.08:00:11.50#ibcon#flushed, iclass 17, count 0 2006.210.08:00:11.50#ibcon#about to write, iclass 17, count 0 2006.210.08:00:11.50#ibcon#wrote, iclass 17, count 0 2006.210.08:00:11.50#ibcon#about to read 3, iclass 17, count 0 2006.210.08:00:11.54#ibcon#read 3, iclass 17, count 0 2006.210.08:00:11.54#ibcon#about to read 4, iclass 17, count 0 2006.210.08:00:11.54#ibcon#read 4, iclass 17, count 0 2006.210.08:00:11.54#ibcon#about to read 5, iclass 17, count 0 2006.210.08:00:11.54#ibcon#read 5, iclass 17, count 0 2006.210.08:00:11.54#ibcon#about to read 6, iclass 17, count 0 2006.210.08:00:11.54#ibcon#read 6, iclass 17, count 0 2006.210.08:00:11.54#ibcon#end of sib2, iclass 17, count 0 2006.210.08:00:11.54#ibcon#*after write, iclass 17, count 0 2006.210.08:00:11.54#ibcon#*before return 0, iclass 17, count 0 2006.210.08:00:11.54#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:11.54#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:00:11.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:00:11.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:00:11.54$vc4f8/vb=5,3 2006.210.08:00:11.54#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:00:11.54#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:00:11.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:11.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:11.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:11.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:11.60#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:00:11.60#ibcon#first serial, iclass 19, count 2 2006.210.08:00:11.60#ibcon#enter sib2, iclass 19, count 2 2006.210.08:00:11.60#ibcon#flushed, iclass 19, count 2 2006.210.08:00:11.60#ibcon#about to write, iclass 19, count 2 2006.210.08:00:11.60#ibcon#wrote, iclass 19, count 2 2006.210.08:00:11.60#ibcon#about to read 3, iclass 19, count 2 2006.210.08:00:11.62#ibcon#read 3, iclass 19, count 2 2006.210.08:00:11.62#ibcon#about to read 4, iclass 19, count 2 2006.210.08:00:11.62#ibcon#read 4, iclass 19, count 2 2006.210.08:00:11.62#ibcon#about to read 5, iclass 19, count 2 2006.210.08:00:11.62#ibcon#read 5, iclass 19, count 2 2006.210.08:00:11.62#ibcon#about to read 6, iclass 19, count 2 2006.210.08:00:11.62#ibcon#read 6, iclass 19, count 2 2006.210.08:00:11.62#ibcon#end of sib2, iclass 19, count 2 2006.210.08:00:11.62#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:00:11.62#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:00:11.62#ibcon#[27=AT05-03\r\n] 2006.210.08:00:11.62#ibcon#*before write, iclass 19, count 2 2006.210.08:00:11.62#ibcon#enter sib2, iclass 19, count 2 2006.210.08:00:11.62#ibcon#flushed, iclass 19, count 2 2006.210.08:00:11.62#ibcon#about to write, iclass 19, count 2 2006.210.08:00:11.62#ibcon#wrote, iclass 19, count 2 2006.210.08:00:11.62#ibcon#about to read 3, iclass 19, count 2 2006.210.08:00:11.65#ibcon#read 3, iclass 19, count 2 2006.210.08:00:11.65#ibcon#about to read 4, iclass 19, count 2 2006.210.08:00:11.65#ibcon#read 4, iclass 19, count 2 2006.210.08:00:11.65#ibcon#about to read 5, iclass 19, count 2 2006.210.08:00:11.65#ibcon#read 5, iclass 19, count 2 2006.210.08:00:11.65#ibcon#about to read 6, iclass 19, count 2 2006.210.08:00:11.65#ibcon#read 6, iclass 19, count 2 2006.210.08:00:11.65#ibcon#end of sib2, iclass 19, count 2 2006.210.08:00:11.65#ibcon#*after write, iclass 19, count 2 2006.210.08:00:11.65#ibcon#*before return 0, iclass 19, count 2 2006.210.08:00:11.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:11.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:00:11.65#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:00:11.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:11.65#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:11.77#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:11.77#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:11.77#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:00:11.77#ibcon#first serial, iclass 19, count 0 2006.210.08:00:11.77#ibcon#enter sib2, iclass 19, count 0 2006.210.08:00:11.77#ibcon#flushed, iclass 19, count 0 2006.210.08:00:11.77#ibcon#about to write, iclass 19, count 0 2006.210.08:00:11.77#ibcon#wrote, iclass 19, count 0 2006.210.08:00:11.77#ibcon#about to read 3, iclass 19, count 0 2006.210.08:00:11.79#ibcon#read 3, iclass 19, count 0 2006.210.08:00:11.79#ibcon#about to read 4, iclass 19, count 0 2006.210.08:00:11.79#ibcon#read 4, iclass 19, count 0 2006.210.08:00:11.79#ibcon#about to read 5, iclass 19, count 0 2006.210.08:00:11.79#ibcon#read 5, iclass 19, count 0 2006.210.08:00:11.79#ibcon#about to read 6, iclass 19, count 0 2006.210.08:00:11.79#ibcon#read 6, iclass 19, count 0 2006.210.08:00:11.79#ibcon#end of sib2, iclass 19, count 0 2006.210.08:00:11.79#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:00:11.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:00:11.79#ibcon#[27=USB\r\n] 2006.210.08:00:11.79#ibcon#*before write, iclass 19, count 0 2006.210.08:00:11.79#ibcon#enter sib2, iclass 19, count 0 2006.210.08:00:11.79#ibcon#flushed, iclass 19, count 0 2006.210.08:00:11.79#ibcon#about to write, iclass 19, count 0 2006.210.08:00:11.79#ibcon#wrote, iclass 19, count 0 2006.210.08:00:11.79#ibcon#about to read 3, iclass 19, count 0 2006.210.08:00:11.82#ibcon#read 3, iclass 19, count 0 2006.210.08:00:11.82#ibcon#about to read 4, iclass 19, count 0 2006.210.08:00:11.82#ibcon#read 4, iclass 19, count 0 2006.210.08:00:11.82#ibcon#about to read 5, iclass 19, count 0 2006.210.08:00:11.82#ibcon#read 5, iclass 19, count 0 2006.210.08:00:11.82#ibcon#about to read 6, iclass 19, count 0 2006.210.08:00:11.82#ibcon#read 6, iclass 19, count 0 2006.210.08:00:11.82#ibcon#end of sib2, iclass 19, count 0 2006.210.08:00:11.82#ibcon#*after write, iclass 19, count 0 2006.210.08:00:11.82#ibcon#*before return 0, iclass 19, count 0 2006.210.08:00:11.82#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:11.82#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:00:11.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:00:11.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:00:11.82$vc4f8/vblo=6,752.99 2006.210.08:00:11.82#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:00:11.82#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:00:11.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:00:11.82#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:11.82#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:11.82#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:11.82#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:00:11.82#ibcon#first serial, iclass 21, count 0 2006.210.08:00:11.82#ibcon#enter sib2, iclass 21, count 0 2006.210.08:00:11.82#ibcon#flushed, iclass 21, count 0 2006.210.08:00:11.82#ibcon#about to write, iclass 21, count 0 2006.210.08:00:11.82#ibcon#wrote, iclass 21, count 0 2006.210.08:00:11.82#ibcon#about to read 3, iclass 21, count 0 2006.210.08:00:11.84#ibcon#read 3, iclass 21, count 0 2006.210.08:00:11.84#ibcon#about to read 4, iclass 21, count 0 2006.210.08:00:11.84#ibcon#read 4, iclass 21, count 0 2006.210.08:00:11.84#ibcon#about to read 5, iclass 21, count 0 2006.210.08:00:11.84#ibcon#read 5, iclass 21, count 0 2006.210.08:00:11.84#ibcon#about to read 6, iclass 21, count 0 2006.210.08:00:11.84#ibcon#read 6, iclass 21, count 0 2006.210.08:00:11.84#ibcon#end of sib2, iclass 21, count 0 2006.210.08:00:11.84#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:00:11.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:00:11.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:00:11.84#ibcon#*before write, iclass 21, count 0 2006.210.08:00:11.84#ibcon#enter sib2, iclass 21, count 0 2006.210.08:00:11.84#ibcon#flushed, iclass 21, count 0 2006.210.08:00:11.84#ibcon#about to write, iclass 21, count 0 2006.210.08:00:11.84#ibcon#wrote, iclass 21, count 0 2006.210.08:00:11.84#ibcon#about to read 3, iclass 21, count 0 2006.210.08:00:11.88#ibcon#read 3, iclass 21, count 0 2006.210.08:00:11.88#ibcon#about to read 4, iclass 21, count 0 2006.210.08:00:11.88#ibcon#read 4, iclass 21, count 0 2006.210.08:00:11.88#ibcon#about to read 5, iclass 21, count 0 2006.210.08:00:11.88#ibcon#read 5, iclass 21, count 0 2006.210.08:00:11.88#ibcon#about to read 6, iclass 21, count 0 2006.210.08:00:11.88#ibcon#read 6, iclass 21, count 0 2006.210.08:00:11.88#ibcon#end of sib2, iclass 21, count 0 2006.210.08:00:11.88#ibcon#*after write, iclass 21, count 0 2006.210.08:00:11.88#ibcon#*before return 0, iclass 21, count 0 2006.210.08:00:11.88#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:11.88#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:00:11.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:00:11.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:00:11.88$vc4f8/vb=6,3 2006.210.08:00:11.88#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:00:11.88#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:00:11.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:00:11.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:11.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:11.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:11.94#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:00:11.94#ibcon#first serial, iclass 23, count 2 2006.210.08:00:11.94#ibcon#enter sib2, iclass 23, count 2 2006.210.08:00:11.94#ibcon#flushed, iclass 23, count 2 2006.210.08:00:11.94#ibcon#about to write, iclass 23, count 2 2006.210.08:00:11.94#ibcon#wrote, iclass 23, count 2 2006.210.08:00:11.94#ibcon#about to read 3, iclass 23, count 2 2006.210.08:00:11.96#ibcon#read 3, iclass 23, count 2 2006.210.08:00:11.96#ibcon#about to read 4, iclass 23, count 2 2006.210.08:00:11.96#ibcon#read 4, iclass 23, count 2 2006.210.08:00:11.96#ibcon#about to read 5, iclass 23, count 2 2006.210.08:00:11.96#ibcon#read 5, iclass 23, count 2 2006.210.08:00:11.96#ibcon#about to read 6, iclass 23, count 2 2006.210.08:00:11.96#ibcon#read 6, iclass 23, count 2 2006.210.08:00:11.96#ibcon#end of sib2, iclass 23, count 2 2006.210.08:00:11.96#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:00:11.96#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:00:11.96#ibcon#[27=AT06-03\r\n] 2006.210.08:00:11.96#ibcon#*before write, iclass 23, count 2 2006.210.08:00:11.96#ibcon#enter sib2, iclass 23, count 2 2006.210.08:00:11.96#ibcon#flushed, iclass 23, count 2 2006.210.08:00:11.96#ibcon#about to write, iclass 23, count 2 2006.210.08:00:11.96#ibcon#wrote, iclass 23, count 2 2006.210.08:00:11.96#ibcon#about to read 3, iclass 23, count 2 2006.210.08:00:11.99#ibcon#read 3, iclass 23, count 2 2006.210.08:00:11.99#ibcon#about to read 4, iclass 23, count 2 2006.210.08:00:11.99#ibcon#read 4, iclass 23, count 2 2006.210.08:00:11.99#ibcon#about to read 5, iclass 23, count 2 2006.210.08:00:11.99#ibcon#read 5, iclass 23, count 2 2006.210.08:00:11.99#ibcon#about to read 6, iclass 23, count 2 2006.210.08:00:11.99#ibcon#read 6, iclass 23, count 2 2006.210.08:00:11.99#ibcon#end of sib2, iclass 23, count 2 2006.210.08:00:11.99#ibcon#*after write, iclass 23, count 2 2006.210.08:00:11.99#ibcon#*before return 0, iclass 23, count 2 2006.210.08:00:11.99#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:11.99#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:00:11.99#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:00:11.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:00:11.99#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:12.11#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:12.11#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:12.11#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:00:12.11#ibcon#first serial, iclass 23, count 0 2006.210.08:00:12.11#ibcon#enter sib2, iclass 23, count 0 2006.210.08:00:12.11#ibcon#flushed, iclass 23, count 0 2006.210.08:00:12.11#ibcon#about to write, iclass 23, count 0 2006.210.08:00:12.11#ibcon#wrote, iclass 23, count 0 2006.210.08:00:12.11#ibcon#about to read 3, iclass 23, count 0 2006.210.08:00:12.13#ibcon#read 3, iclass 23, count 0 2006.210.08:00:12.13#ibcon#about to read 4, iclass 23, count 0 2006.210.08:00:12.13#ibcon#read 4, iclass 23, count 0 2006.210.08:00:12.13#ibcon#about to read 5, iclass 23, count 0 2006.210.08:00:12.13#ibcon#read 5, iclass 23, count 0 2006.210.08:00:12.13#ibcon#about to read 6, iclass 23, count 0 2006.210.08:00:12.13#ibcon#read 6, iclass 23, count 0 2006.210.08:00:12.13#ibcon#end of sib2, iclass 23, count 0 2006.210.08:00:12.13#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:00:12.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:00:12.13#ibcon#[27=USB\r\n] 2006.210.08:00:12.13#ibcon#*before write, iclass 23, count 0 2006.210.08:00:12.13#ibcon#enter sib2, iclass 23, count 0 2006.210.08:00:12.13#ibcon#flushed, iclass 23, count 0 2006.210.08:00:12.13#ibcon#about to write, iclass 23, count 0 2006.210.08:00:12.13#ibcon#wrote, iclass 23, count 0 2006.210.08:00:12.13#ibcon#about to read 3, iclass 23, count 0 2006.210.08:00:12.16#ibcon#read 3, iclass 23, count 0 2006.210.08:00:12.16#ibcon#about to read 4, iclass 23, count 0 2006.210.08:00:12.16#ibcon#read 4, iclass 23, count 0 2006.210.08:00:12.16#ibcon#about to read 5, iclass 23, count 0 2006.210.08:00:12.16#ibcon#read 5, iclass 23, count 0 2006.210.08:00:12.16#ibcon#about to read 6, iclass 23, count 0 2006.210.08:00:12.16#ibcon#read 6, iclass 23, count 0 2006.210.08:00:12.16#ibcon#end of sib2, iclass 23, count 0 2006.210.08:00:12.16#ibcon#*after write, iclass 23, count 0 2006.210.08:00:12.16#ibcon#*before return 0, iclass 23, count 0 2006.210.08:00:12.16#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:12.16#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:00:12.16#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:00:12.16#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:00:12.16$vc4f8/vabw=wide 2006.210.08:00:12.16#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:00:12.16#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:00:12.16#ibcon#ireg 8 cls_cnt 0 2006.210.08:00:12.16#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:12.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:12.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:12.16#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:00:12.16#ibcon#first serial, iclass 25, count 0 2006.210.08:00:12.16#ibcon#enter sib2, iclass 25, count 0 2006.210.08:00:12.16#ibcon#flushed, iclass 25, count 0 2006.210.08:00:12.16#ibcon#about to write, iclass 25, count 0 2006.210.08:00:12.16#ibcon#wrote, iclass 25, count 0 2006.210.08:00:12.16#ibcon#about to read 3, iclass 25, count 0 2006.210.08:00:12.18#ibcon#read 3, iclass 25, count 0 2006.210.08:00:12.18#ibcon#about to read 4, iclass 25, count 0 2006.210.08:00:12.18#ibcon#read 4, iclass 25, count 0 2006.210.08:00:12.18#ibcon#about to read 5, iclass 25, count 0 2006.210.08:00:12.18#ibcon#read 5, iclass 25, count 0 2006.210.08:00:12.18#ibcon#about to read 6, iclass 25, count 0 2006.210.08:00:12.18#ibcon#read 6, iclass 25, count 0 2006.210.08:00:12.18#ibcon#end of sib2, iclass 25, count 0 2006.210.08:00:12.18#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:00:12.18#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:00:12.18#ibcon#[25=BW32\r\n] 2006.210.08:00:12.18#ibcon#*before write, iclass 25, count 0 2006.210.08:00:12.18#ibcon#enter sib2, iclass 25, count 0 2006.210.08:00:12.18#ibcon#flushed, iclass 25, count 0 2006.210.08:00:12.18#ibcon#about to write, iclass 25, count 0 2006.210.08:00:12.18#ibcon#wrote, iclass 25, count 0 2006.210.08:00:12.18#ibcon#about to read 3, iclass 25, count 0 2006.210.08:00:12.21#ibcon#read 3, iclass 25, count 0 2006.210.08:00:12.21#ibcon#about to read 4, iclass 25, count 0 2006.210.08:00:12.21#ibcon#read 4, iclass 25, count 0 2006.210.08:00:12.21#ibcon#about to read 5, iclass 25, count 0 2006.210.08:00:12.21#ibcon#read 5, iclass 25, count 0 2006.210.08:00:12.21#ibcon#about to read 6, iclass 25, count 0 2006.210.08:00:12.21#ibcon#read 6, iclass 25, count 0 2006.210.08:00:12.21#ibcon#end of sib2, iclass 25, count 0 2006.210.08:00:12.21#ibcon#*after write, iclass 25, count 0 2006.210.08:00:12.21#ibcon#*before return 0, iclass 25, count 0 2006.210.08:00:12.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:12.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:00:12.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:00:12.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:00:12.21$vc4f8/vbbw=wide 2006.210.08:00:12.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.08:00:12.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.08:00:12.21#ibcon#ireg 8 cls_cnt 0 2006.210.08:00:12.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:00:12.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:00:12.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:00:12.28#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:00:12.28#ibcon#first serial, iclass 27, count 0 2006.210.08:00:12.28#ibcon#enter sib2, iclass 27, count 0 2006.210.08:00:12.28#ibcon#flushed, iclass 27, count 0 2006.210.08:00:12.28#ibcon#about to write, iclass 27, count 0 2006.210.08:00:12.28#ibcon#wrote, iclass 27, count 0 2006.210.08:00:12.28#ibcon#about to read 3, iclass 27, count 0 2006.210.08:00:12.30#ibcon#read 3, iclass 27, count 0 2006.210.08:00:12.30#ibcon#about to read 4, iclass 27, count 0 2006.210.08:00:12.30#ibcon#read 4, iclass 27, count 0 2006.210.08:00:12.30#ibcon#about to read 5, iclass 27, count 0 2006.210.08:00:12.30#ibcon#read 5, iclass 27, count 0 2006.210.08:00:12.30#ibcon#about to read 6, iclass 27, count 0 2006.210.08:00:12.30#ibcon#read 6, iclass 27, count 0 2006.210.08:00:12.30#ibcon#end of sib2, iclass 27, count 0 2006.210.08:00:12.30#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:00:12.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:00:12.30#ibcon#[27=BW32\r\n] 2006.210.08:00:12.30#ibcon#*before write, iclass 27, count 0 2006.210.08:00:12.30#ibcon#enter sib2, iclass 27, count 0 2006.210.08:00:12.30#ibcon#flushed, iclass 27, count 0 2006.210.08:00:12.30#ibcon#about to write, iclass 27, count 0 2006.210.08:00:12.30#ibcon#wrote, iclass 27, count 0 2006.210.08:00:12.30#ibcon#about to read 3, iclass 27, count 0 2006.210.08:00:12.33#ibcon#read 3, iclass 27, count 0 2006.210.08:00:12.33#ibcon#about to read 4, iclass 27, count 0 2006.210.08:00:12.33#ibcon#read 4, iclass 27, count 0 2006.210.08:00:12.33#ibcon#about to read 5, iclass 27, count 0 2006.210.08:00:12.33#ibcon#read 5, iclass 27, count 0 2006.210.08:00:12.33#ibcon#about to read 6, iclass 27, count 0 2006.210.08:00:12.33#ibcon#read 6, iclass 27, count 0 2006.210.08:00:12.33#ibcon#end of sib2, iclass 27, count 0 2006.210.08:00:12.33#ibcon#*after write, iclass 27, count 0 2006.210.08:00:12.33#ibcon#*before return 0, iclass 27, count 0 2006.210.08:00:12.33#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:00:12.33#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:00:12.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:00:12.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:00:12.33$4f8m12a/ifd4f 2006.210.08:00:12.33$ifd4f/lo= 2006.210.08:00:12.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:00:12.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:00:12.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:00:12.33$ifd4f/patch= 2006.210.08:00:12.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:00:12.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:00:12.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:00:12.33$4f8m12a/"form=m,16.000,1:2 2006.210.08:00:12.33$4f8m12a/"tpicd 2006.210.08:00:12.33$4f8m12a/echo=off 2006.210.08:00:12.33$4f8m12a/xlog=off 2006.210.08:00:12.33:!2006.210.08:00:40 2006.210.08:00:26.14#trakl#Source acquired 2006.210.08:00:28.14#flagr#flagr/antenna,acquired 2006.210.08:00:40.00:preob 2006.210.08:00:41.14/onsource/TRACKING 2006.210.08:00:41.14:!2006.210.08:00:50 2006.210.08:00:50.00:data_valid=on 2006.210.08:00:50.00:midob 2006.210.08:00:50.14/onsource/TRACKING 2006.210.08:00:50.14/wx/30.50,1006.3,81 2006.210.08:00:50.30/cable/+6.3954E-03 2006.210.08:00:51.39/va/01,08,usb,yes,35,37 2006.210.08:00:51.39/va/02,07,usb,yes,35,37 2006.210.08:00:51.39/va/03,06,usb,yes,37,38 2006.210.08:00:51.39/va/04,07,usb,yes,36,39 2006.210.08:00:51.39/va/05,07,usb,yes,38,40 2006.210.08:00:51.39/va/06,06,usb,yes,37,37 2006.210.08:00:51.39/va/07,06,usb,yes,37,37 2006.210.08:00:51.39/va/08,07,usb,yes,36,35 2006.210.08:00:51.62/valo/01,532.99,yes,locked 2006.210.08:00:51.62/valo/02,572.99,yes,locked 2006.210.08:00:51.62/valo/03,672.99,yes,locked 2006.210.08:00:51.62/valo/04,832.99,yes,locked 2006.210.08:00:51.62/valo/05,652.99,yes,locked 2006.210.08:00:51.62/valo/06,772.99,yes,locked 2006.210.08:00:51.62/valo/07,832.99,yes,locked 2006.210.08:00:51.62/valo/08,852.99,yes,locked 2006.210.08:00:52.71/vb/01,04,usb,yes,30,29 2006.210.08:00:52.71/vb/02,04,usb,yes,32,33 2006.210.08:00:52.71/vb/03,03,usb,yes,35,40 2006.210.08:00:52.71/vb/04,03,usb,yes,36,36 2006.210.08:00:52.71/vb/05,03,usb,yes,35,39 2006.210.08:00:52.71/vb/06,03,usb,yes,35,39 2006.210.08:00:52.71/vb/07,04,usb,yes,31,31 2006.210.08:00:52.71/vb/08,03,usb,yes,35,39 2006.210.08:00:52.95/vblo/01,632.99,yes,locked 2006.210.08:00:52.95/vblo/02,640.99,yes,locked 2006.210.08:00:52.95/vblo/03,656.99,yes,locked 2006.210.08:00:52.95/vblo/04,712.99,yes,locked 2006.210.08:00:52.95/vblo/05,744.99,yes,locked 2006.210.08:00:52.95/vblo/06,752.99,yes,locked 2006.210.08:00:52.95/vblo/07,734.99,yes,locked 2006.210.08:00:52.95/vblo/08,744.99,yes,locked 2006.210.08:00:53.10/vabw/8 2006.210.08:00:53.25/vbbw/8 2006.210.08:00:53.34/xfe/off,on,14.0 2006.210.08:00:53.74/ifatt/23,28,28,28 2006.210.08:00:54.08/fmout-gps/S +4.65E-07 2006.210.08:00:54.12:!2006.210.08:01:50 2006.210.08:01:50.00:data_valid=off 2006.210.08:01:50.00:postob 2006.210.08:01:50.18/cable/+6.3926E-03 2006.210.08:01:50.18/wx/30.47,1006.3,81 2006.210.08:01:51.08/fmout-gps/S +4.66E-07 2006.210.08:01:51.08:scan_name=210-0802,k06210,60 2006.210.08:01:51.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.210.08:01:51.14#flagr#flagr/antenna,new-source 2006.210.08:01:52.14:checkk5 2006.210.08:01:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:01:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:01:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:01:53.52/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:01:53.86/chk_obsdata//k5ts1/T2100800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:01:54.19/chk_obsdata//k5ts2/T2100800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:01:54.52/chk_obsdata//k5ts3/T2100800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:01:54.85/chk_obsdata//k5ts4/T2100800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:01:55.51/k5log//k5ts1_log_newline 2006.210.08:01:56.17/k5log//k5ts2_log_newline 2006.210.08:01:56.82/k5log//k5ts3_log_newline 2006.210.08:01:57.48/k5log//k5ts4_log_newline 2006.210.08:01:57.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:01:57.51:4f8m12a=2 2006.210.08:01:57.51$4f8m12a/echo=on 2006.210.08:01:57.51$4f8m12a/pcalon 2006.210.08:01:57.51$pcalon/"no phase cal control is implemented here 2006.210.08:01:57.51$4f8m12a/"tpicd=stop 2006.210.08:01:57.51$4f8m12a/vc4f8 2006.210.08:01:57.51$vc4f8/valo=1,532.99 2006.210.08:01:57.51#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:01:57.51#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:01:57.51#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:57.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:01:57.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:01:57.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:01:57.51#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:01:57.51#ibcon#first serial, iclass 29, count 0 2006.210.08:01:57.51#ibcon#enter sib2, iclass 29, count 0 2006.210.08:01:57.51#ibcon#flushed, iclass 29, count 0 2006.210.08:01:57.51#ibcon#about to write, iclass 29, count 0 2006.210.08:01:57.51#ibcon#wrote, iclass 29, count 0 2006.210.08:01:57.51#ibcon#about to read 3, iclass 29, count 0 2006.210.08:01:57.53#ibcon#read 3, iclass 29, count 0 2006.210.08:01:57.53#ibcon#about to read 4, iclass 29, count 0 2006.210.08:01:57.53#ibcon#read 4, iclass 29, count 0 2006.210.08:01:57.53#ibcon#about to read 5, iclass 29, count 0 2006.210.08:01:57.53#ibcon#read 5, iclass 29, count 0 2006.210.08:01:57.53#ibcon#about to read 6, iclass 29, count 0 2006.210.08:01:57.53#ibcon#read 6, iclass 29, count 0 2006.210.08:01:57.53#ibcon#end of sib2, iclass 29, count 0 2006.210.08:01:57.53#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:01:57.53#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:01:57.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:01:57.53#ibcon#*before write, iclass 29, count 0 2006.210.08:01:57.53#ibcon#enter sib2, iclass 29, count 0 2006.210.08:01:57.53#ibcon#flushed, iclass 29, count 0 2006.210.08:01:57.53#ibcon#about to write, iclass 29, count 0 2006.210.08:01:57.53#ibcon#wrote, iclass 29, count 0 2006.210.08:01:57.53#ibcon#about to read 3, iclass 29, count 0 2006.210.08:01:57.58#ibcon#read 3, iclass 29, count 0 2006.210.08:01:57.58#ibcon#about to read 4, iclass 29, count 0 2006.210.08:01:57.58#ibcon#read 4, iclass 29, count 0 2006.210.08:01:57.58#ibcon#about to read 5, iclass 29, count 0 2006.210.08:01:57.58#ibcon#read 5, iclass 29, count 0 2006.210.08:01:57.58#ibcon#about to read 6, iclass 29, count 0 2006.210.08:01:57.58#ibcon#read 6, iclass 29, count 0 2006.210.08:01:57.58#ibcon#end of sib2, iclass 29, count 0 2006.210.08:01:57.58#ibcon#*after write, iclass 29, count 0 2006.210.08:01:57.58#ibcon#*before return 0, iclass 29, count 0 2006.210.08:01:57.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:01:57.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:01:57.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:01:57.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:01:57.58$vc4f8/va=1,8 2006.210.08:01:57.58#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.08:01:57.58#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.08:01:57.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:57.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:01:57.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:01:57.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:01:57.58#ibcon#enter wrdev, iclass 31, count 2 2006.210.08:01:57.58#ibcon#first serial, iclass 31, count 2 2006.210.08:01:57.58#ibcon#enter sib2, iclass 31, count 2 2006.210.08:01:57.58#ibcon#flushed, iclass 31, count 2 2006.210.08:01:57.58#ibcon#about to write, iclass 31, count 2 2006.210.08:01:57.58#ibcon#wrote, iclass 31, count 2 2006.210.08:01:57.58#ibcon#about to read 3, iclass 31, count 2 2006.210.08:01:57.60#ibcon#read 3, iclass 31, count 2 2006.210.08:01:57.60#ibcon#about to read 4, iclass 31, count 2 2006.210.08:01:57.60#ibcon#read 4, iclass 31, count 2 2006.210.08:01:57.60#ibcon#about to read 5, iclass 31, count 2 2006.210.08:01:57.60#ibcon#read 5, iclass 31, count 2 2006.210.08:01:57.60#ibcon#about to read 6, iclass 31, count 2 2006.210.08:01:57.60#ibcon#read 6, iclass 31, count 2 2006.210.08:01:57.60#ibcon#end of sib2, iclass 31, count 2 2006.210.08:01:57.60#ibcon#*mode == 0, iclass 31, count 2 2006.210.08:01:57.60#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.08:01:57.60#ibcon#[25=AT01-08\r\n] 2006.210.08:01:57.60#ibcon#*before write, iclass 31, count 2 2006.210.08:01:57.60#ibcon#enter sib2, iclass 31, count 2 2006.210.08:01:57.60#ibcon#flushed, iclass 31, count 2 2006.210.08:01:57.60#ibcon#about to write, iclass 31, count 2 2006.210.08:01:57.60#ibcon#wrote, iclass 31, count 2 2006.210.08:01:57.60#ibcon#about to read 3, iclass 31, count 2 2006.210.08:01:57.63#ibcon#read 3, iclass 31, count 2 2006.210.08:01:57.63#ibcon#about to read 4, iclass 31, count 2 2006.210.08:01:57.63#ibcon#read 4, iclass 31, count 2 2006.210.08:01:57.63#ibcon#about to read 5, iclass 31, count 2 2006.210.08:01:57.63#ibcon#read 5, iclass 31, count 2 2006.210.08:01:57.63#ibcon#about to read 6, iclass 31, count 2 2006.210.08:01:57.63#ibcon#read 6, iclass 31, count 2 2006.210.08:01:57.63#ibcon#end of sib2, iclass 31, count 2 2006.210.08:01:57.63#ibcon#*after write, iclass 31, count 2 2006.210.08:01:57.63#ibcon#*before return 0, iclass 31, count 2 2006.210.08:01:57.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:01:57.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:01:57.63#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.08:01:57.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:57.63#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:01:57.75#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:01:57.75#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:01:57.75#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:01:57.75#ibcon#first serial, iclass 31, count 0 2006.210.08:01:57.75#ibcon#enter sib2, iclass 31, count 0 2006.210.08:01:57.75#ibcon#flushed, iclass 31, count 0 2006.210.08:01:57.75#ibcon#about to write, iclass 31, count 0 2006.210.08:01:57.75#ibcon#wrote, iclass 31, count 0 2006.210.08:01:57.75#ibcon#about to read 3, iclass 31, count 0 2006.210.08:01:57.77#ibcon#read 3, iclass 31, count 0 2006.210.08:01:57.77#ibcon#about to read 4, iclass 31, count 0 2006.210.08:01:57.77#ibcon#read 4, iclass 31, count 0 2006.210.08:01:57.77#ibcon#about to read 5, iclass 31, count 0 2006.210.08:01:57.77#ibcon#read 5, iclass 31, count 0 2006.210.08:01:57.77#ibcon#about to read 6, iclass 31, count 0 2006.210.08:01:57.77#ibcon#read 6, iclass 31, count 0 2006.210.08:01:57.77#ibcon#end of sib2, iclass 31, count 0 2006.210.08:01:57.77#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:01:57.77#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:01:57.77#ibcon#[25=USB\r\n] 2006.210.08:01:57.77#ibcon#*before write, iclass 31, count 0 2006.210.08:01:57.77#ibcon#enter sib2, iclass 31, count 0 2006.210.08:01:57.77#ibcon#flushed, iclass 31, count 0 2006.210.08:01:57.77#ibcon#about to write, iclass 31, count 0 2006.210.08:01:57.77#ibcon#wrote, iclass 31, count 0 2006.210.08:01:57.77#ibcon#about to read 3, iclass 31, count 0 2006.210.08:01:57.80#ibcon#read 3, iclass 31, count 0 2006.210.08:01:57.80#ibcon#about to read 4, iclass 31, count 0 2006.210.08:01:57.80#ibcon#read 4, iclass 31, count 0 2006.210.08:01:57.80#ibcon#about to read 5, iclass 31, count 0 2006.210.08:01:57.80#ibcon#read 5, iclass 31, count 0 2006.210.08:01:57.80#ibcon#about to read 6, iclass 31, count 0 2006.210.08:01:57.80#ibcon#read 6, iclass 31, count 0 2006.210.08:01:57.80#ibcon#end of sib2, iclass 31, count 0 2006.210.08:01:57.80#ibcon#*after write, iclass 31, count 0 2006.210.08:01:57.80#ibcon#*before return 0, iclass 31, count 0 2006.210.08:01:57.80#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:01:57.80#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:01:57.80#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:01:57.80#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:01:57.80$vc4f8/valo=2,572.99 2006.210.08:01:57.80#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:01:57.80#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:01:57.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:57.80#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:01:57.80#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:01:57.80#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:01:57.80#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:01:57.80#ibcon#first serial, iclass 33, count 0 2006.210.08:01:57.80#ibcon#enter sib2, iclass 33, count 0 2006.210.08:01:57.80#ibcon#flushed, iclass 33, count 0 2006.210.08:01:57.80#ibcon#about to write, iclass 33, count 0 2006.210.08:01:57.80#ibcon#wrote, iclass 33, count 0 2006.210.08:01:57.80#ibcon#about to read 3, iclass 33, count 0 2006.210.08:01:57.82#ibcon#read 3, iclass 33, count 0 2006.210.08:01:57.82#ibcon#about to read 4, iclass 33, count 0 2006.210.08:01:57.82#ibcon#read 4, iclass 33, count 0 2006.210.08:01:57.82#ibcon#about to read 5, iclass 33, count 0 2006.210.08:01:57.82#ibcon#read 5, iclass 33, count 0 2006.210.08:01:57.82#ibcon#about to read 6, iclass 33, count 0 2006.210.08:01:57.82#ibcon#read 6, iclass 33, count 0 2006.210.08:01:57.82#ibcon#end of sib2, iclass 33, count 0 2006.210.08:01:57.82#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:01:57.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:01:57.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:01:57.82#ibcon#*before write, iclass 33, count 0 2006.210.08:01:57.82#ibcon#enter sib2, iclass 33, count 0 2006.210.08:01:57.82#ibcon#flushed, iclass 33, count 0 2006.210.08:01:57.82#ibcon#about to write, iclass 33, count 0 2006.210.08:01:57.82#ibcon#wrote, iclass 33, count 0 2006.210.08:01:57.82#ibcon#about to read 3, iclass 33, count 0 2006.210.08:01:57.86#ibcon#read 3, iclass 33, count 0 2006.210.08:01:57.86#ibcon#about to read 4, iclass 33, count 0 2006.210.08:01:57.86#ibcon#read 4, iclass 33, count 0 2006.210.08:01:57.86#ibcon#about to read 5, iclass 33, count 0 2006.210.08:01:57.86#ibcon#read 5, iclass 33, count 0 2006.210.08:01:57.86#ibcon#about to read 6, iclass 33, count 0 2006.210.08:01:57.86#ibcon#read 6, iclass 33, count 0 2006.210.08:01:57.86#ibcon#end of sib2, iclass 33, count 0 2006.210.08:01:57.86#ibcon#*after write, iclass 33, count 0 2006.210.08:01:57.86#ibcon#*before return 0, iclass 33, count 0 2006.210.08:01:57.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:01:57.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:01:57.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:01:57.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:01:57.86$vc4f8/va=2,7 2006.210.08:01:57.86#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:01:57.86#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:01:57.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:57.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:01:57.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:01:57.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:01:57.92#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:01:57.92#ibcon#first serial, iclass 35, count 2 2006.210.08:01:57.92#ibcon#enter sib2, iclass 35, count 2 2006.210.08:01:57.92#ibcon#flushed, iclass 35, count 2 2006.210.08:01:57.92#ibcon#about to write, iclass 35, count 2 2006.210.08:01:57.92#ibcon#wrote, iclass 35, count 2 2006.210.08:01:57.92#ibcon#about to read 3, iclass 35, count 2 2006.210.08:01:57.94#ibcon#read 3, iclass 35, count 2 2006.210.08:01:57.94#ibcon#about to read 4, iclass 35, count 2 2006.210.08:01:57.94#ibcon#read 4, iclass 35, count 2 2006.210.08:01:57.94#ibcon#about to read 5, iclass 35, count 2 2006.210.08:01:57.94#ibcon#read 5, iclass 35, count 2 2006.210.08:01:57.94#ibcon#about to read 6, iclass 35, count 2 2006.210.08:01:57.94#ibcon#read 6, iclass 35, count 2 2006.210.08:01:57.94#ibcon#end of sib2, iclass 35, count 2 2006.210.08:01:57.94#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:01:57.94#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:01:57.94#ibcon#[25=AT02-07\r\n] 2006.210.08:01:57.94#ibcon#*before write, iclass 35, count 2 2006.210.08:01:57.94#ibcon#enter sib2, iclass 35, count 2 2006.210.08:01:57.94#ibcon#flushed, iclass 35, count 2 2006.210.08:01:57.94#ibcon#about to write, iclass 35, count 2 2006.210.08:01:57.94#ibcon#wrote, iclass 35, count 2 2006.210.08:01:57.94#ibcon#about to read 3, iclass 35, count 2 2006.210.08:01:57.97#ibcon#read 3, iclass 35, count 2 2006.210.08:01:57.97#ibcon#about to read 4, iclass 35, count 2 2006.210.08:01:57.97#ibcon#read 4, iclass 35, count 2 2006.210.08:01:57.97#ibcon#about to read 5, iclass 35, count 2 2006.210.08:01:57.97#ibcon#read 5, iclass 35, count 2 2006.210.08:01:57.97#ibcon#about to read 6, iclass 35, count 2 2006.210.08:01:57.97#ibcon#read 6, iclass 35, count 2 2006.210.08:01:57.97#ibcon#end of sib2, iclass 35, count 2 2006.210.08:01:57.97#ibcon#*after write, iclass 35, count 2 2006.210.08:01:57.97#ibcon#*before return 0, iclass 35, count 2 2006.210.08:01:57.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:01:57.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:01:57.97#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:01:57.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:57.97#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:01:58.09#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:01:58.09#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:01:58.09#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:01:58.09#ibcon#first serial, iclass 35, count 0 2006.210.08:01:58.09#ibcon#enter sib2, iclass 35, count 0 2006.210.08:01:58.09#ibcon#flushed, iclass 35, count 0 2006.210.08:01:58.09#ibcon#about to write, iclass 35, count 0 2006.210.08:01:58.09#ibcon#wrote, iclass 35, count 0 2006.210.08:01:58.09#ibcon#about to read 3, iclass 35, count 0 2006.210.08:01:58.11#ibcon#read 3, iclass 35, count 0 2006.210.08:01:58.11#ibcon#about to read 4, iclass 35, count 0 2006.210.08:01:58.11#ibcon#read 4, iclass 35, count 0 2006.210.08:01:58.11#ibcon#about to read 5, iclass 35, count 0 2006.210.08:01:58.11#ibcon#read 5, iclass 35, count 0 2006.210.08:01:58.11#ibcon#about to read 6, iclass 35, count 0 2006.210.08:01:58.11#ibcon#read 6, iclass 35, count 0 2006.210.08:01:58.11#ibcon#end of sib2, iclass 35, count 0 2006.210.08:01:58.11#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:01:58.11#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:01:58.11#ibcon#[25=USB\r\n] 2006.210.08:01:58.11#ibcon#*before write, iclass 35, count 0 2006.210.08:01:58.11#ibcon#enter sib2, iclass 35, count 0 2006.210.08:01:58.11#ibcon#flushed, iclass 35, count 0 2006.210.08:01:58.11#ibcon#about to write, iclass 35, count 0 2006.210.08:01:58.11#ibcon#wrote, iclass 35, count 0 2006.210.08:01:58.11#ibcon#about to read 3, iclass 35, count 0 2006.210.08:01:58.14#ibcon#read 3, iclass 35, count 0 2006.210.08:01:58.14#ibcon#about to read 4, iclass 35, count 0 2006.210.08:01:58.14#ibcon#read 4, iclass 35, count 0 2006.210.08:01:58.14#ibcon#about to read 5, iclass 35, count 0 2006.210.08:01:58.14#ibcon#read 5, iclass 35, count 0 2006.210.08:01:58.14#ibcon#about to read 6, iclass 35, count 0 2006.210.08:01:58.14#ibcon#read 6, iclass 35, count 0 2006.210.08:01:58.14#ibcon#end of sib2, iclass 35, count 0 2006.210.08:01:58.14#ibcon#*after write, iclass 35, count 0 2006.210.08:01:58.14#ibcon#*before return 0, iclass 35, count 0 2006.210.08:01:58.14#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:01:58.14#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:01:58.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:01:58.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:01:58.14$vc4f8/valo=3,672.99 2006.210.08:01:58.14#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:01:58.14#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:01:58.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:58.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:01:58.14#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:01:58.14#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:01:58.14#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:01:58.14#ibcon#first serial, iclass 37, count 0 2006.210.08:01:58.14#ibcon#enter sib2, iclass 37, count 0 2006.210.08:01:58.14#ibcon#flushed, iclass 37, count 0 2006.210.08:01:58.14#ibcon#about to write, iclass 37, count 0 2006.210.08:01:58.14#ibcon#wrote, iclass 37, count 0 2006.210.08:01:58.14#ibcon#about to read 3, iclass 37, count 0 2006.210.08:01:58.16#ibcon#read 3, iclass 37, count 0 2006.210.08:01:58.16#ibcon#about to read 4, iclass 37, count 0 2006.210.08:01:58.16#ibcon#read 4, iclass 37, count 0 2006.210.08:01:58.16#ibcon#about to read 5, iclass 37, count 0 2006.210.08:01:58.16#ibcon#read 5, iclass 37, count 0 2006.210.08:01:58.16#ibcon#about to read 6, iclass 37, count 0 2006.210.08:01:58.16#ibcon#read 6, iclass 37, count 0 2006.210.08:01:58.16#ibcon#end of sib2, iclass 37, count 0 2006.210.08:01:58.16#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:01:58.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:01:58.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:01:58.16#ibcon#*before write, iclass 37, count 0 2006.210.08:01:58.16#ibcon#enter sib2, iclass 37, count 0 2006.210.08:01:58.16#ibcon#flushed, iclass 37, count 0 2006.210.08:01:58.16#ibcon#about to write, iclass 37, count 0 2006.210.08:01:58.16#ibcon#wrote, iclass 37, count 0 2006.210.08:01:58.16#ibcon#about to read 3, iclass 37, count 0 2006.210.08:01:58.20#ibcon#read 3, iclass 37, count 0 2006.210.08:01:58.20#ibcon#about to read 4, iclass 37, count 0 2006.210.08:01:58.20#ibcon#read 4, iclass 37, count 0 2006.210.08:01:58.20#ibcon#about to read 5, iclass 37, count 0 2006.210.08:01:58.20#ibcon#read 5, iclass 37, count 0 2006.210.08:01:58.20#ibcon#about to read 6, iclass 37, count 0 2006.210.08:01:58.20#ibcon#read 6, iclass 37, count 0 2006.210.08:01:58.20#ibcon#end of sib2, iclass 37, count 0 2006.210.08:01:58.20#ibcon#*after write, iclass 37, count 0 2006.210.08:01:58.20#ibcon#*before return 0, iclass 37, count 0 2006.210.08:01:58.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:01:58.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:01:58.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:01:58.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:01:58.20$vc4f8/va=3,6 2006.210.08:01:58.20#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:01:58.20#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:01:58.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:58.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:01:58.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:01:58.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:01:58.26#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:01:58.26#ibcon#first serial, iclass 39, count 2 2006.210.08:01:58.26#ibcon#enter sib2, iclass 39, count 2 2006.210.08:01:58.26#ibcon#flushed, iclass 39, count 2 2006.210.08:01:58.26#ibcon#about to write, iclass 39, count 2 2006.210.08:01:58.26#ibcon#wrote, iclass 39, count 2 2006.210.08:01:58.26#ibcon#about to read 3, iclass 39, count 2 2006.210.08:01:58.28#ibcon#read 3, iclass 39, count 2 2006.210.08:01:58.28#ibcon#about to read 4, iclass 39, count 2 2006.210.08:01:58.28#ibcon#read 4, iclass 39, count 2 2006.210.08:01:58.28#ibcon#about to read 5, iclass 39, count 2 2006.210.08:01:58.28#ibcon#read 5, iclass 39, count 2 2006.210.08:01:58.28#ibcon#about to read 6, iclass 39, count 2 2006.210.08:01:58.28#ibcon#read 6, iclass 39, count 2 2006.210.08:01:58.28#ibcon#end of sib2, iclass 39, count 2 2006.210.08:01:58.28#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:01:58.28#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:01:58.28#ibcon#[25=AT03-06\r\n] 2006.210.08:01:58.28#ibcon#*before write, iclass 39, count 2 2006.210.08:01:58.28#ibcon#enter sib2, iclass 39, count 2 2006.210.08:01:58.28#ibcon#flushed, iclass 39, count 2 2006.210.08:01:58.28#ibcon#about to write, iclass 39, count 2 2006.210.08:01:58.28#ibcon#wrote, iclass 39, count 2 2006.210.08:01:58.28#ibcon#about to read 3, iclass 39, count 2 2006.210.08:01:58.31#ibcon#read 3, iclass 39, count 2 2006.210.08:01:58.31#ibcon#about to read 4, iclass 39, count 2 2006.210.08:01:58.31#ibcon#read 4, iclass 39, count 2 2006.210.08:01:58.31#ibcon#about to read 5, iclass 39, count 2 2006.210.08:01:58.31#ibcon#read 5, iclass 39, count 2 2006.210.08:01:58.31#ibcon#about to read 6, iclass 39, count 2 2006.210.08:01:58.31#ibcon#read 6, iclass 39, count 2 2006.210.08:01:58.31#ibcon#end of sib2, iclass 39, count 2 2006.210.08:01:58.31#ibcon#*after write, iclass 39, count 2 2006.210.08:01:58.31#ibcon#*before return 0, iclass 39, count 2 2006.210.08:01:58.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:01:58.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:01:58.31#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:01:58.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:58.31#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:01:58.43#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:01:58.43#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:01:58.43#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:01:58.43#ibcon#first serial, iclass 39, count 0 2006.210.08:01:58.43#ibcon#enter sib2, iclass 39, count 0 2006.210.08:01:58.43#ibcon#flushed, iclass 39, count 0 2006.210.08:01:58.43#ibcon#about to write, iclass 39, count 0 2006.210.08:01:58.43#ibcon#wrote, iclass 39, count 0 2006.210.08:01:58.43#ibcon#about to read 3, iclass 39, count 0 2006.210.08:01:58.45#ibcon#read 3, iclass 39, count 0 2006.210.08:01:58.45#ibcon#about to read 4, iclass 39, count 0 2006.210.08:01:58.45#ibcon#read 4, iclass 39, count 0 2006.210.08:01:58.45#ibcon#about to read 5, iclass 39, count 0 2006.210.08:01:58.45#ibcon#read 5, iclass 39, count 0 2006.210.08:01:58.45#ibcon#about to read 6, iclass 39, count 0 2006.210.08:01:58.45#ibcon#read 6, iclass 39, count 0 2006.210.08:01:58.45#ibcon#end of sib2, iclass 39, count 0 2006.210.08:01:58.45#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:01:58.45#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:01:58.45#ibcon#[25=USB\r\n] 2006.210.08:01:58.45#ibcon#*before write, iclass 39, count 0 2006.210.08:01:58.45#ibcon#enter sib2, iclass 39, count 0 2006.210.08:01:58.45#ibcon#flushed, iclass 39, count 0 2006.210.08:01:58.45#ibcon#about to write, iclass 39, count 0 2006.210.08:01:58.45#ibcon#wrote, iclass 39, count 0 2006.210.08:01:58.45#ibcon#about to read 3, iclass 39, count 0 2006.210.08:01:58.48#ibcon#read 3, iclass 39, count 0 2006.210.08:01:58.48#ibcon#about to read 4, iclass 39, count 0 2006.210.08:01:58.48#ibcon#read 4, iclass 39, count 0 2006.210.08:01:58.48#ibcon#about to read 5, iclass 39, count 0 2006.210.08:01:58.48#ibcon#read 5, iclass 39, count 0 2006.210.08:01:58.48#ibcon#about to read 6, iclass 39, count 0 2006.210.08:01:58.48#ibcon#read 6, iclass 39, count 0 2006.210.08:01:58.48#ibcon#end of sib2, iclass 39, count 0 2006.210.08:01:58.48#ibcon#*after write, iclass 39, count 0 2006.210.08:01:58.48#ibcon#*before return 0, iclass 39, count 0 2006.210.08:01:58.48#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:01:58.48#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:01:58.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:01:58.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:01:58.48$vc4f8/valo=4,832.99 2006.210.08:01:58.48#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:01:58.48#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:01:58.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:58.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:01:58.48#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:01:58.48#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:01:58.48#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:01:58.48#ibcon#first serial, iclass 3, count 0 2006.210.08:01:58.48#ibcon#enter sib2, iclass 3, count 0 2006.210.08:01:58.48#ibcon#flushed, iclass 3, count 0 2006.210.08:01:58.48#ibcon#about to write, iclass 3, count 0 2006.210.08:01:58.48#ibcon#wrote, iclass 3, count 0 2006.210.08:01:58.48#ibcon#about to read 3, iclass 3, count 0 2006.210.08:01:58.50#ibcon#read 3, iclass 3, count 0 2006.210.08:01:58.50#ibcon#about to read 4, iclass 3, count 0 2006.210.08:01:58.50#ibcon#read 4, iclass 3, count 0 2006.210.08:01:58.50#ibcon#about to read 5, iclass 3, count 0 2006.210.08:01:58.50#ibcon#read 5, iclass 3, count 0 2006.210.08:01:58.50#ibcon#about to read 6, iclass 3, count 0 2006.210.08:01:58.50#ibcon#read 6, iclass 3, count 0 2006.210.08:01:58.50#ibcon#end of sib2, iclass 3, count 0 2006.210.08:01:58.50#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:01:58.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:01:58.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:01:58.50#ibcon#*before write, iclass 3, count 0 2006.210.08:01:58.50#ibcon#enter sib2, iclass 3, count 0 2006.210.08:01:58.50#ibcon#flushed, iclass 3, count 0 2006.210.08:01:58.50#ibcon#about to write, iclass 3, count 0 2006.210.08:01:58.50#ibcon#wrote, iclass 3, count 0 2006.210.08:01:58.50#ibcon#about to read 3, iclass 3, count 0 2006.210.08:01:58.54#ibcon#read 3, iclass 3, count 0 2006.210.08:01:58.54#ibcon#about to read 4, iclass 3, count 0 2006.210.08:01:58.54#ibcon#read 4, iclass 3, count 0 2006.210.08:01:58.54#ibcon#about to read 5, iclass 3, count 0 2006.210.08:01:58.54#ibcon#read 5, iclass 3, count 0 2006.210.08:01:58.54#ibcon#about to read 6, iclass 3, count 0 2006.210.08:01:58.54#ibcon#read 6, iclass 3, count 0 2006.210.08:01:58.54#ibcon#end of sib2, iclass 3, count 0 2006.210.08:01:58.54#ibcon#*after write, iclass 3, count 0 2006.210.08:01:58.54#ibcon#*before return 0, iclass 3, count 0 2006.210.08:01:58.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:01:58.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:01:58.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:01:58.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:01:58.54$vc4f8/va=4,7 2006.210.08:01:58.54#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:01:58.54#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:01:58.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:58.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:01:58.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:01:58.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:01:58.60#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:01:58.60#ibcon#first serial, iclass 5, count 2 2006.210.08:01:58.60#ibcon#enter sib2, iclass 5, count 2 2006.210.08:01:58.60#ibcon#flushed, iclass 5, count 2 2006.210.08:01:58.60#ibcon#about to write, iclass 5, count 2 2006.210.08:01:58.60#ibcon#wrote, iclass 5, count 2 2006.210.08:01:58.60#ibcon#about to read 3, iclass 5, count 2 2006.210.08:01:58.62#ibcon#read 3, iclass 5, count 2 2006.210.08:01:58.62#ibcon#about to read 4, iclass 5, count 2 2006.210.08:01:58.62#ibcon#read 4, iclass 5, count 2 2006.210.08:01:58.62#ibcon#about to read 5, iclass 5, count 2 2006.210.08:01:58.62#ibcon#read 5, iclass 5, count 2 2006.210.08:01:58.62#ibcon#about to read 6, iclass 5, count 2 2006.210.08:01:58.62#ibcon#read 6, iclass 5, count 2 2006.210.08:01:58.62#ibcon#end of sib2, iclass 5, count 2 2006.210.08:01:58.62#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:01:58.62#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:01:58.62#ibcon#[25=AT04-07\r\n] 2006.210.08:01:58.62#ibcon#*before write, iclass 5, count 2 2006.210.08:01:58.62#ibcon#enter sib2, iclass 5, count 2 2006.210.08:01:58.62#ibcon#flushed, iclass 5, count 2 2006.210.08:01:58.62#ibcon#about to write, iclass 5, count 2 2006.210.08:01:58.62#ibcon#wrote, iclass 5, count 2 2006.210.08:01:58.62#ibcon#about to read 3, iclass 5, count 2 2006.210.08:01:58.65#ibcon#read 3, iclass 5, count 2 2006.210.08:01:58.65#ibcon#about to read 4, iclass 5, count 2 2006.210.08:01:58.65#ibcon#read 4, iclass 5, count 2 2006.210.08:01:58.65#ibcon#about to read 5, iclass 5, count 2 2006.210.08:01:58.65#ibcon#read 5, iclass 5, count 2 2006.210.08:01:58.65#ibcon#about to read 6, iclass 5, count 2 2006.210.08:01:58.65#ibcon#read 6, iclass 5, count 2 2006.210.08:01:58.65#ibcon#end of sib2, iclass 5, count 2 2006.210.08:01:58.65#ibcon#*after write, iclass 5, count 2 2006.210.08:01:58.65#ibcon#*before return 0, iclass 5, count 2 2006.210.08:01:58.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:01:58.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:01:58.65#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:01:58.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:58.65#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:01:58.77#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:01:58.77#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:01:58.77#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:01:58.77#ibcon#first serial, iclass 5, count 0 2006.210.08:01:58.77#ibcon#enter sib2, iclass 5, count 0 2006.210.08:01:58.77#ibcon#flushed, iclass 5, count 0 2006.210.08:01:58.77#ibcon#about to write, iclass 5, count 0 2006.210.08:01:58.77#ibcon#wrote, iclass 5, count 0 2006.210.08:01:58.77#ibcon#about to read 3, iclass 5, count 0 2006.210.08:01:58.79#ibcon#read 3, iclass 5, count 0 2006.210.08:01:58.79#ibcon#about to read 4, iclass 5, count 0 2006.210.08:01:58.79#ibcon#read 4, iclass 5, count 0 2006.210.08:01:58.79#ibcon#about to read 5, iclass 5, count 0 2006.210.08:01:58.79#ibcon#read 5, iclass 5, count 0 2006.210.08:01:58.79#ibcon#about to read 6, iclass 5, count 0 2006.210.08:01:58.79#ibcon#read 6, iclass 5, count 0 2006.210.08:01:58.79#ibcon#end of sib2, iclass 5, count 0 2006.210.08:01:58.79#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:01:58.79#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:01:58.79#ibcon#[25=USB\r\n] 2006.210.08:01:58.79#ibcon#*before write, iclass 5, count 0 2006.210.08:01:58.79#ibcon#enter sib2, iclass 5, count 0 2006.210.08:01:58.79#ibcon#flushed, iclass 5, count 0 2006.210.08:01:58.79#ibcon#about to write, iclass 5, count 0 2006.210.08:01:58.79#ibcon#wrote, iclass 5, count 0 2006.210.08:01:58.79#ibcon#about to read 3, iclass 5, count 0 2006.210.08:01:58.82#ibcon#read 3, iclass 5, count 0 2006.210.08:01:58.82#ibcon#about to read 4, iclass 5, count 0 2006.210.08:01:58.82#ibcon#read 4, iclass 5, count 0 2006.210.08:01:58.82#ibcon#about to read 5, iclass 5, count 0 2006.210.08:01:58.82#ibcon#read 5, iclass 5, count 0 2006.210.08:01:58.82#ibcon#about to read 6, iclass 5, count 0 2006.210.08:01:58.82#ibcon#read 6, iclass 5, count 0 2006.210.08:01:58.82#ibcon#end of sib2, iclass 5, count 0 2006.210.08:01:58.82#ibcon#*after write, iclass 5, count 0 2006.210.08:01:58.82#ibcon#*before return 0, iclass 5, count 0 2006.210.08:01:58.82#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:01:58.82#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:01:58.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:01:58.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:01:58.82$vc4f8/valo=5,652.99 2006.210.08:01:58.82#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:01:58.82#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:01:58.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:58.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:01:58.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:01:58.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:01:58.82#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:01:58.82#ibcon#first serial, iclass 7, count 0 2006.210.08:01:58.82#ibcon#enter sib2, iclass 7, count 0 2006.210.08:01:58.82#ibcon#flushed, iclass 7, count 0 2006.210.08:01:58.82#ibcon#about to write, iclass 7, count 0 2006.210.08:01:58.82#ibcon#wrote, iclass 7, count 0 2006.210.08:01:58.82#ibcon#about to read 3, iclass 7, count 0 2006.210.08:01:58.84#ibcon#read 3, iclass 7, count 0 2006.210.08:01:58.84#ibcon#about to read 4, iclass 7, count 0 2006.210.08:01:58.84#ibcon#read 4, iclass 7, count 0 2006.210.08:01:58.84#ibcon#about to read 5, iclass 7, count 0 2006.210.08:01:58.84#ibcon#read 5, iclass 7, count 0 2006.210.08:01:58.84#ibcon#about to read 6, iclass 7, count 0 2006.210.08:01:58.84#ibcon#read 6, iclass 7, count 0 2006.210.08:01:58.84#ibcon#end of sib2, iclass 7, count 0 2006.210.08:01:58.84#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:01:58.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:01:58.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:01:58.84#ibcon#*before write, iclass 7, count 0 2006.210.08:01:58.84#ibcon#enter sib2, iclass 7, count 0 2006.210.08:01:58.84#ibcon#flushed, iclass 7, count 0 2006.210.08:01:58.84#ibcon#about to write, iclass 7, count 0 2006.210.08:01:58.84#ibcon#wrote, iclass 7, count 0 2006.210.08:01:58.84#ibcon#about to read 3, iclass 7, count 0 2006.210.08:01:58.88#ibcon#read 3, iclass 7, count 0 2006.210.08:01:58.88#ibcon#about to read 4, iclass 7, count 0 2006.210.08:01:58.88#ibcon#read 4, iclass 7, count 0 2006.210.08:01:58.88#ibcon#about to read 5, iclass 7, count 0 2006.210.08:01:58.88#ibcon#read 5, iclass 7, count 0 2006.210.08:01:58.88#ibcon#about to read 6, iclass 7, count 0 2006.210.08:01:58.88#ibcon#read 6, iclass 7, count 0 2006.210.08:01:58.88#ibcon#end of sib2, iclass 7, count 0 2006.210.08:01:58.88#ibcon#*after write, iclass 7, count 0 2006.210.08:01:58.88#ibcon#*before return 0, iclass 7, count 0 2006.210.08:01:58.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:01:58.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:01:58.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:01:58.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:01:58.88$vc4f8/va=5,7 2006.210.08:01:58.88#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:01:58.88#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:01:58.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:58.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:01:58.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:01:58.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:01:58.94#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:01:58.94#ibcon#first serial, iclass 11, count 2 2006.210.08:01:58.94#ibcon#enter sib2, iclass 11, count 2 2006.210.08:01:58.94#ibcon#flushed, iclass 11, count 2 2006.210.08:01:58.94#ibcon#about to write, iclass 11, count 2 2006.210.08:01:58.94#ibcon#wrote, iclass 11, count 2 2006.210.08:01:58.94#ibcon#about to read 3, iclass 11, count 2 2006.210.08:01:58.96#ibcon#read 3, iclass 11, count 2 2006.210.08:01:58.96#ibcon#about to read 4, iclass 11, count 2 2006.210.08:01:58.96#ibcon#read 4, iclass 11, count 2 2006.210.08:01:58.96#ibcon#about to read 5, iclass 11, count 2 2006.210.08:01:58.96#ibcon#read 5, iclass 11, count 2 2006.210.08:01:58.96#ibcon#about to read 6, iclass 11, count 2 2006.210.08:01:58.96#ibcon#read 6, iclass 11, count 2 2006.210.08:01:58.96#ibcon#end of sib2, iclass 11, count 2 2006.210.08:01:58.96#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:01:58.96#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:01:58.96#ibcon#[25=AT05-07\r\n] 2006.210.08:01:58.96#ibcon#*before write, iclass 11, count 2 2006.210.08:01:58.96#ibcon#enter sib2, iclass 11, count 2 2006.210.08:01:58.96#ibcon#flushed, iclass 11, count 2 2006.210.08:01:58.96#ibcon#about to write, iclass 11, count 2 2006.210.08:01:58.96#ibcon#wrote, iclass 11, count 2 2006.210.08:01:58.96#ibcon#about to read 3, iclass 11, count 2 2006.210.08:01:58.99#ibcon#read 3, iclass 11, count 2 2006.210.08:01:58.99#ibcon#about to read 4, iclass 11, count 2 2006.210.08:01:58.99#ibcon#read 4, iclass 11, count 2 2006.210.08:01:58.99#ibcon#about to read 5, iclass 11, count 2 2006.210.08:01:58.99#ibcon#read 5, iclass 11, count 2 2006.210.08:01:58.99#ibcon#about to read 6, iclass 11, count 2 2006.210.08:01:58.99#ibcon#read 6, iclass 11, count 2 2006.210.08:01:58.99#ibcon#end of sib2, iclass 11, count 2 2006.210.08:01:58.99#ibcon#*after write, iclass 11, count 2 2006.210.08:01:58.99#ibcon#*before return 0, iclass 11, count 2 2006.210.08:01:58.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:01:58.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:01:58.99#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:01:58.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:58.99#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:01:59.11#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:01:59.11#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:01:59.11#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:01:59.11#ibcon#first serial, iclass 11, count 0 2006.210.08:01:59.11#ibcon#enter sib2, iclass 11, count 0 2006.210.08:01:59.11#ibcon#flushed, iclass 11, count 0 2006.210.08:01:59.11#ibcon#about to write, iclass 11, count 0 2006.210.08:01:59.11#ibcon#wrote, iclass 11, count 0 2006.210.08:01:59.11#ibcon#about to read 3, iclass 11, count 0 2006.210.08:01:59.13#ibcon#read 3, iclass 11, count 0 2006.210.08:01:59.13#ibcon#about to read 4, iclass 11, count 0 2006.210.08:01:59.13#ibcon#read 4, iclass 11, count 0 2006.210.08:01:59.13#ibcon#about to read 5, iclass 11, count 0 2006.210.08:01:59.13#ibcon#read 5, iclass 11, count 0 2006.210.08:01:59.13#ibcon#about to read 6, iclass 11, count 0 2006.210.08:01:59.13#ibcon#read 6, iclass 11, count 0 2006.210.08:01:59.13#ibcon#end of sib2, iclass 11, count 0 2006.210.08:01:59.13#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:01:59.13#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:01:59.13#ibcon#[25=USB\r\n] 2006.210.08:01:59.13#ibcon#*before write, iclass 11, count 0 2006.210.08:01:59.13#ibcon#enter sib2, iclass 11, count 0 2006.210.08:01:59.13#ibcon#flushed, iclass 11, count 0 2006.210.08:01:59.13#ibcon#about to write, iclass 11, count 0 2006.210.08:01:59.13#ibcon#wrote, iclass 11, count 0 2006.210.08:01:59.13#ibcon#about to read 3, iclass 11, count 0 2006.210.08:01:59.16#ibcon#read 3, iclass 11, count 0 2006.210.08:01:59.16#ibcon#about to read 4, iclass 11, count 0 2006.210.08:01:59.16#ibcon#read 4, iclass 11, count 0 2006.210.08:01:59.16#ibcon#about to read 5, iclass 11, count 0 2006.210.08:01:59.16#ibcon#read 5, iclass 11, count 0 2006.210.08:01:59.16#ibcon#about to read 6, iclass 11, count 0 2006.210.08:01:59.16#ibcon#read 6, iclass 11, count 0 2006.210.08:01:59.16#ibcon#end of sib2, iclass 11, count 0 2006.210.08:01:59.16#ibcon#*after write, iclass 11, count 0 2006.210.08:01:59.16#ibcon#*before return 0, iclass 11, count 0 2006.210.08:01:59.16#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:01:59.16#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:01:59.16#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:01:59.16#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:01:59.16$vc4f8/valo=6,772.99 2006.210.08:01:59.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:01:59.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:01:59.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:59.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:01:59.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:01:59.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:01:59.16#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:01:59.16#ibcon#first serial, iclass 13, count 0 2006.210.08:01:59.16#ibcon#enter sib2, iclass 13, count 0 2006.210.08:01:59.16#ibcon#flushed, iclass 13, count 0 2006.210.08:01:59.16#ibcon#about to write, iclass 13, count 0 2006.210.08:01:59.16#ibcon#wrote, iclass 13, count 0 2006.210.08:01:59.16#ibcon#about to read 3, iclass 13, count 0 2006.210.08:01:59.18#ibcon#read 3, iclass 13, count 0 2006.210.08:01:59.18#ibcon#about to read 4, iclass 13, count 0 2006.210.08:01:59.18#ibcon#read 4, iclass 13, count 0 2006.210.08:01:59.18#ibcon#about to read 5, iclass 13, count 0 2006.210.08:01:59.18#ibcon#read 5, iclass 13, count 0 2006.210.08:01:59.18#ibcon#about to read 6, iclass 13, count 0 2006.210.08:01:59.18#ibcon#read 6, iclass 13, count 0 2006.210.08:01:59.18#ibcon#end of sib2, iclass 13, count 0 2006.210.08:01:59.18#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:01:59.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:01:59.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:01:59.18#ibcon#*before write, iclass 13, count 0 2006.210.08:01:59.18#ibcon#enter sib2, iclass 13, count 0 2006.210.08:01:59.18#ibcon#flushed, iclass 13, count 0 2006.210.08:01:59.18#ibcon#about to write, iclass 13, count 0 2006.210.08:01:59.18#ibcon#wrote, iclass 13, count 0 2006.210.08:01:59.18#ibcon#about to read 3, iclass 13, count 0 2006.210.08:01:59.22#ibcon#read 3, iclass 13, count 0 2006.210.08:01:59.22#ibcon#about to read 4, iclass 13, count 0 2006.210.08:01:59.22#ibcon#read 4, iclass 13, count 0 2006.210.08:01:59.22#ibcon#about to read 5, iclass 13, count 0 2006.210.08:01:59.22#ibcon#read 5, iclass 13, count 0 2006.210.08:01:59.22#ibcon#about to read 6, iclass 13, count 0 2006.210.08:01:59.22#ibcon#read 6, iclass 13, count 0 2006.210.08:01:59.22#ibcon#end of sib2, iclass 13, count 0 2006.210.08:01:59.22#ibcon#*after write, iclass 13, count 0 2006.210.08:01:59.22#ibcon#*before return 0, iclass 13, count 0 2006.210.08:01:59.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:01:59.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:01:59.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:01:59.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:01:59.22$vc4f8/va=6,6 2006.210.08:01:59.22#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:01:59.22#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:01:59.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:59.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:01:59.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:01:59.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:01:59.28#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:01:59.28#ibcon#first serial, iclass 15, count 2 2006.210.08:01:59.28#ibcon#enter sib2, iclass 15, count 2 2006.210.08:01:59.28#ibcon#flushed, iclass 15, count 2 2006.210.08:01:59.28#ibcon#about to write, iclass 15, count 2 2006.210.08:01:59.28#ibcon#wrote, iclass 15, count 2 2006.210.08:01:59.28#ibcon#about to read 3, iclass 15, count 2 2006.210.08:01:59.30#ibcon#read 3, iclass 15, count 2 2006.210.08:01:59.30#ibcon#about to read 4, iclass 15, count 2 2006.210.08:01:59.30#ibcon#read 4, iclass 15, count 2 2006.210.08:01:59.30#ibcon#about to read 5, iclass 15, count 2 2006.210.08:01:59.30#ibcon#read 5, iclass 15, count 2 2006.210.08:01:59.30#ibcon#about to read 6, iclass 15, count 2 2006.210.08:01:59.30#ibcon#read 6, iclass 15, count 2 2006.210.08:01:59.30#ibcon#end of sib2, iclass 15, count 2 2006.210.08:01:59.30#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:01:59.30#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:01:59.30#ibcon#[25=AT06-06\r\n] 2006.210.08:01:59.30#ibcon#*before write, iclass 15, count 2 2006.210.08:01:59.30#ibcon#enter sib2, iclass 15, count 2 2006.210.08:01:59.30#ibcon#flushed, iclass 15, count 2 2006.210.08:01:59.30#ibcon#about to write, iclass 15, count 2 2006.210.08:01:59.30#ibcon#wrote, iclass 15, count 2 2006.210.08:01:59.30#ibcon#about to read 3, iclass 15, count 2 2006.210.08:01:59.33#ibcon#read 3, iclass 15, count 2 2006.210.08:01:59.33#ibcon#about to read 4, iclass 15, count 2 2006.210.08:01:59.33#ibcon#read 4, iclass 15, count 2 2006.210.08:01:59.33#ibcon#about to read 5, iclass 15, count 2 2006.210.08:01:59.33#ibcon#read 5, iclass 15, count 2 2006.210.08:01:59.33#ibcon#about to read 6, iclass 15, count 2 2006.210.08:01:59.33#ibcon#read 6, iclass 15, count 2 2006.210.08:01:59.33#ibcon#end of sib2, iclass 15, count 2 2006.210.08:01:59.33#ibcon#*after write, iclass 15, count 2 2006.210.08:01:59.33#ibcon#*before return 0, iclass 15, count 2 2006.210.08:01:59.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:01:59.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:01:59.33#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:01:59.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:59.33#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:01:59.45#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:01:59.45#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:01:59.45#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:01:59.45#ibcon#first serial, iclass 15, count 0 2006.210.08:01:59.45#ibcon#enter sib2, iclass 15, count 0 2006.210.08:01:59.45#ibcon#flushed, iclass 15, count 0 2006.210.08:01:59.45#ibcon#about to write, iclass 15, count 0 2006.210.08:01:59.45#ibcon#wrote, iclass 15, count 0 2006.210.08:01:59.45#ibcon#about to read 3, iclass 15, count 0 2006.210.08:01:59.47#ibcon#read 3, iclass 15, count 0 2006.210.08:01:59.47#ibcon#about to read 4, iclass 15, count 0 2006.210.08:01:59.47#ibcon#read 4, iclass 15, count 0 2006.210.08:01:59.47#ibcon#about to read 5, iclass 15, count 0 2006.210.08:01:59.47#ibcon#read 5, iclass 15, count 0 2006.210.08:01:59.47#ibcon#about to read 6, iclass 15, count 0 2006.210.08:01:59.47#ibcon#read 6, iclass 15, count 0 2006.210.08:01:59.47#ibcon#end of sib2, iclass 15, count 0 2006.210.08:01:59.47#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:01:59.47#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:01:59.47#ibcon#[25=USB\r\n] 2006.210.08:01:59.47#ibcon#*before write, iclass 15, count 0 2006.210.08:01:59.47#ibcon#enter sib2, iclass 15, count 0 2006.210.08:01:59.47#ibcon#flushed, iclass 15, count 0 2006.210.08:01:59.47#ibcon#about to write, iclass 15, count 0 2006.210.08:01:59.47#ibcon#wrote, iclass 15, count 0 2006.210.08:01:59.47#ibcon#about to read 3, iclass 15, count 0 2006.210.08:01:59.50#ibcon#read 3, iclass 15, count 0 2006.210.08:01:59.50#ibcon#about to read 4, iclass 15, count 0 2006.210.08:01:59.50#ibcon#read 4, iclass 15, count 0 2006.210.08:01:59.50#ibcon#about to read 5, iclass 15, count 0 2006.210.08:01:59.50#ibcon#read 5, iclass 15, count 0 2006.210.08:01:59.50#ibcon#about to read 6, iclass 15, count 0 2006.210.08:01:59.50#ibcon#read 6, iclass 15, count 0 2006.210.08:01:59.50#ibcon#end of sib2, iclass 15, count 0 2006.210.08:01:59.50#ibcon#*after write, iclass 15, count 0 2006.210.08:01:59.50#ibcon#*before return 0, iclass 15, count 0 2006.210.08:01:59.50#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:01:59.50#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:01:59.50#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:01:59.50#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:01:59.50$vc4f8/valo=7,832.99 2006.210.08:01:59.50#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:01:59.50#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:01:59.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:59.50#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:01:59.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:01:59.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:01:59.50#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:01:59.50#ibcon#first serial, iclass 17, count 0 2006.210.08:01:59.50#ibcon#enter sib2, iclass 17, count 0 2006.210.08:01:59.50#ibcon#flushed, iclass 17, count 0 2006.210.08:01:59.50#ibcon#about to write, iclass 17, count 0 2006.210.08:01:59.50#ibcon#wrote, iclass 17, count 0 2006.210.08:01:59.50#ibcon#about to read 3, iclass 17, count 0 2006.210.08:01:59.52#ibcon#read 3, iclass 17, count 0 2006.210.08:01:59.52#ibcon#about to read 4, iclass 17, count 0 2006.210.08:01:59.52#ibcon#read 4, iclass 17, count 0 2006.210.08:01:59.52#ibcon#about to read 5, iclass 17, count 0 2006.210.08:01:59.52#ibcon#read 5, iclass 17, count 0 2006.210.08:01:59.52#ibcon#about to read 6, iclass 17, count 0 2006.210.08:01:59.52#ibcon#read 6, iclass 17, count 0 2006.210.08:01:59.52#ibcon#end of sib2, iclass 17, count 0 2006.210.08:01:59.52#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:01:59.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:01:59.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:01:59.52#ibcon#*before write, iclass 17, count 0 2006.210.08:01:59.52#ibcon#enter sib2, iclass 17, count 0 2006.210.08:01:59.52#ibcon#flushed, iclass 17, count 0 2006.210.08:01:59.52#ibcon#about to write, iclass 17, count 0 2006.210.08:01:59.52#ibcon#wrote, iclass 17, count 0 2006.210.08:01:59.52#ibcon#about to read 3, iclass 17, count 0 2006.210.08:01:59.56#ibcon#read 3, iclass 17, count 0 2006.210.08:01:59.56#ibcon#about to read 4, iclass 17, count 0 2006.210.08:01:59.56#ibcon#read 4, iclass 17, count 0 2006.210.08:01:59.56#ibcon#about to read 5, iclass 17, count 0 2006.210.08:01:59.56#ibcon#read 5, iclass 17, count 0 2006.210.08:01:59.56#ibcon#about to read 6, iclass 17, count 0 2006.210.08:01:59.56#ibcon#read 6, iclass 17, count 0 2006.210.08:01:59.56#ibcon#end of sib2, iclass 17, count 0 2006.210.08:01:59.56#ibcon#*after write, iclass 17, count 0 2006.210.08:01:59.56#ibcon#*before return 0, iclass 17, count 0 2006.210.08:01:59.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:01:59.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:01:59.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:01:59.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:01:59.56$vc4f8/va=7,6 2006.210.08:01:59.56#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:01:59.56#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:01:59.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:59.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:01:59.62#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:01:59.62#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:01:59.62#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:01:59.62#ibcon#first serial, iclass 19, count 2 2006.210.08:01:59.62#ibcon#enter sib2, iclass 19, count 2 2006.210.08:01:59.62#ibcon#flushed, iclass 19, count 2 2006.210.08:01:59.62#ibcon#about to write, iclass 19, count 2 2006.210.08:01:59.62#ibcon#wrote, iclass 19, count 2 2006.210.08:01:59.62#ibcon#about to read 3, iclass 19, count 2 2006.210.08:01:59.64#ibcon#read 3, iclass 19, count 2 2006.210.08:01:59.64#ibcon#about to read 4, iclass 19, count 2 2006.210.08:01:59.64#ibcon#read 4, iclass 19, count 2 2006.210.08:01:59.64#ibcon#about to read 5, iclass 19, count 2 2006.210.08:01:59.64#ibcon#read 5, iclass 19, count 2 2006.210.08:01:59.64#ibcon#about to read 6, iclass 19, count 2 2006.210.08:01:59.64#ibcon#read 6, iclass 19, count 2 2006.210.08:01:59.64#ibcon#end of sib2, iclass 19, count 2 2006.210.08:01:59.64#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:01:59.64#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:01:59.64#ibcon#[25=AT07-06\r\n] 2006.210.08:01:59.64#ibcon#*before write, iclass 19, count 2 2006.210.08:01:59.64#ibcon#enter sib2, iclass 19, count 2 2006.210.08:01:59.64#ibcon#flushed, iclass 19, count 2 2006.210.08:01:59.64#ibcon#about to write, iclass 19, count 2 2006.210.08:01:59.64#ibcon#wrote, iclass 19, count 2 2006.210.08:01:59.64#ibcon#about to read 3, iclass 19, count 2 2006.210.08:01:59.67#ibcon#read 3, iclass 19, count 2 2006.210.08:01:59.67#ibcon#about to read 4, iclass 19, count 2 2006.210.08:01:59.67#ibcon#read 4, iclass 19, count 2 2006.210.08:01:59.67#ibcon#about to read 5, iclass 19, count 2 2006.210.08:01:59.67#ibcon#read 5, iclass 19, count 2 2006.210.08:01:59.67#ibcon#about to read 6, iclass 19, count 2 2006.210.08:01:59.67#ibcon#read 6, iclass 19, count 2 2006.210.08:01:59.67#ibcon#end of sib2, iclass 19, count 2 2006.210.08:01:59.67#ibcon#*after write, iclass 19, count 2 2006.210.08:01:59.67#ibcon#*before return 0, iclass 19, count 2 2006.210.08:01:59.67#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:01:59.67#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:01:59.67#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:01:59.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:01:59.67#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:01:59.79#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:01:59.79#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:01:59.79#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:01:59.79#ibcon#first serial, iclass 19, count 0 2006.210.08:01:59.79#ibcon#enter sib2, iclass 19, count 0 2006.210.08:01:59.79#ibcon#flushed, iclass 19, count 0 2006.210.08:01:59.79#ibcon#about to write, iclass 19, count 0 2006.210.08:01:59.79#ibcon#wrote, iclass 19, count 0 2006.210.08:01:59.79#ibcon#about to read 3, iclass 19, count 0 2006.210.08:01:59.81#ibcon#read 3, iclass 19, count 0 2006.210.08:01:59.81#ibcon#about to read 4, iclass 19, count 0 2006.210.08:01:59.81#ibcon#read 4, iclass 19, count 0 2006.210.08:01:59.81#ibcon#about to read 5, iclass 19, count 0 2006.210.08:01:59.81#ibcon#read 5, iclass 19, count 0 2006.210.08:01:59.81#ibcon#about to read 6, iclass 19, count 0 2006.210.08:01:59.81#ibcon#read 6, iclass 19, count 0 2006.210.08:01:59.81#ibcon#end of sib2, iclass 19, count 0 2006.210.08:01:59.81#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:01:59.81#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:01:59.81#ibcon#[25=USB\r\n] 2006.210.08:01:59.81#ibcon#*before write, iclass 19, count 0 2006.210.08:01:59.81#ibcon#enter sib2, iclass 19, count 0 2006.210.08:01:59.81#ibcon#flushed, iclass 19, count 0 2006.210.08:01:59.81#ibcon#about to write, iclass 19, count 0 2006.210.08:01:59.81#ibcon#wrote, iclass 19, count 0 2006.210.08:01:59.81#ibcon#about to read 3, iclass 19, count 0 2006.210.08:01:59.84#ibcon#read 3, iclass 19, count 0 2006.210.08:01:59.84#ibcon#about to read 4, iclass 19, count 0 2006.210.08:01:59.84#ibcon#read 4, iclass 19, count 0 2006.210.08:01:59.84#ibcon#about to read 5, iclass 19, count 0 2006.210.08:01:59.84#ibcon#read 5, iclass 19, count 0 2006.210.08:01:59.84#ibcon#about to read 6, iclass 19, count 0 2006.210.08:01:59.84#ibcon#read 6, iclass 19, count 0 2006.210.08:01:59.84#ibcon#end of sib2, iclass 19, count 0 2006.210.08:01:59.84#ibcon#*after write, iclass 19, count 0 2006.210.08:01:59.84#ibcon#*before return 0, iclass 19, count 0 2006.210.08:01:59.84#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:01:59.84#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:01:59.84#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:01:59.84#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:01:59.84$vc4f8/valo=8,852.99 2006.210.08:01:59.84#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:01:59.84#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:01:59.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:01:59.84#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:01:59.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:01:59.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:01:59.84#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:01:59.84#ibcon#first serial, iclass 21, count 0 2006.210.08:01:59.84#ibcon#enter sib2, iclass 21, count 0 2006.210.08:01:59.84#ibcon#flushed, iclass 21, count 0 2006.210.08:01:59.84#ibcon#about to write, iclass 21, count 0 2006.210.08:01:59.84#ibcon#wrote, iclass 21, count 0 2006.210.08:01:59.84#ibcon#about to read 3, iclass 21, count 0 2006.210.08:01:59.86#ibcon#read 3, iclass 21, count 0 2006.210.08:01:59.86#ibcon#about to read 4, iclass 21, count 0 2006.210.08:01:59.86#ibcon#read 4, iclass 21, count 0 2006.210.08:01:59.86#ibcon#about to read 5, iclass 21, count 0 2006.210.08:01:59.86#ibcon#read 5, iclass 21, count 0 2006.210.08:01:59.86#ibcon#about to read 6, iclass 21, count 0 2006.210.08:01:59.86#ibcon#read 6, iclass 21, count 0 2006.210.08:01:59.86#ibcon#end of sib2, iclass 21, count 0 2006.210.08:01:59.86#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:01:59.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:01:59.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:01:59.86#ibcon#*before write, iclass 21, count 0 2006.210.08:01:59.86#ibcon#enter sib2, iclass 21, count 0 2006.210.08:01:59.86#ibcon#flushed, iclass 21, count 0 2006.210.08:01:59.86#ibcon#about to write, iclass 21, count 0 2006.210.08:01:59.86#ibcon#wrote, iclass 21, count 0 2006.210.08:01:59.86#ibcon#about to read 3, iclass 21, count 0 2006.210.08:01:59.90#ibcon#read 3, iclass 21, count 0 2006.210.08:01:59.90#ibcon#about to read 4, iclass 21, count 0 2006.210.08:01:59.90#ibcon#read 4, iclass 21, count 0 2006.210.08:01:59.90#ibcon#about to read 5, iclass 21, count 0 2006.210.08:01:59.90#ibcon#read 5, iclass 21, count 0 2006.210.08:01:59.90#ibcon#about to read 6, iclass 21, count 0 2006.210.08:01:59.90#ibcon#read 6, iclass 21, count 0 2006.210.08:01:59.90#ibcon#end of sib2, iclass 21, count 0 2006.210.08:01:59.90#ibcon#*after write, iclass 21, count 0 2006.210.08:01:59.90#ibcon#*before return 0, iclass 21, count 0 2006.210.08:01:59.90#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:01:59.90#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:01:59.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:01:59.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:01:59.90$vc4f8/va=8,7 2006.210.08:01:59.90#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:01:59.90#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:01:59.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:01:59.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:01:59.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:01:59.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:01:59.96#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:01:59.96#ibcon#first serial, iclass 23, count 2 2006.210.08:01:59.96#ibcon#enter sib2, iclass 23, count 2 2006.210.08:01:59.96#ibcon#flushed, iclass 23, count 2 2006.210.08:01:59.96#ibcon#about to write, iclass 23, count 2 2006.210.08:01:59.96#ibcon#wrote, iclass 23, count 2 2006.210.08:01:59.96#ibcon#about to read 3, iclass 23, count 2 2006.210.08:01:59.98#ibcon#read 3, iclass 23, count 2 2006.210.08:01:59.98#ibcon#about to read 4, iclass 23, count 2 2006.210.08:01:59.98#ibcon#read 4, iclass 23, count 2 2006.210.08:01:59.98#ibcon#about to read 5, iclass 23, count 2 2006.210.08:01:59.98#ibcon#read 5, iclass 23, count 2 2006.210.08:01:59.98#ibcon#about to read 6, iclass 23, count 2 2006.210.08:01:59.98#ibcon#read 6, iclass 23, count 2 2006.210.08:01:59.98#ibcon#end of sib2, iclass 23, count 2 2006.210.08:01:59.98#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:01:59.98#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:01:59.98#ibcon#[25=AT08-07\r\n] 2006.210.08:01:59.98#ibcon#*before write, iclass 23, count 2 2006.210.08:01:59.98#ibcon#enter sib2, iclass 23, count 2 2006.210.08:01:59.98#ibcon#flushed, iclass 23, count 2 2006.210.08:01:59.98#ibcon#about to write, iclass 23, count 2 2006.210.08:01:59.98#ibcon#wrote, iclass 23, count 2 2006.210.08:01:59.98#ibcon#about to read 3, iclass 23, count 2 2006.210.08:02:00.01#ibcon#read 3, iclass 23, count 2 2006.210.08:02:00.01#ibcon#about to read 4, iclass 23, count 2 2006.210.08:02:00.01#ibcon#read 4, iclass 23, count 2 2006.210.08:02:00.01#ibcon#about to read 5, iclass 23, count 2 2006.210.08:02:00.01#ibcon#read 5, iclass 23, count 2 2006.210.08:02:00.01#ibcon#about to read 6, iclass 23, count 2 2006.210.08:02:00.01#ibcon#read 6, iclass 23, count 2 2006.210.08:02:00.01#ibcon#end of sib2, iclass 23, count 2 2006.210.08:02:00.01#ibcon#*after write, iclass 23, count 2 2006.210.08:02:00.01#ibcon#*before return 0, iclass 23, count 2 2006.210.08:02:00.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:02:00.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:02:00.01#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:02:00.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:00.01#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:02:00.13#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:02:00.13#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:02:00.13#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:02:00.13#ibcon#first serial, iclass 23, count 0 2006.210.08:02:00.13#ibcon#enter sib2, iclass 23, count 0 2006.210.08:02:00.13#ibcon#flushed, iclass 23, count 0 2006.210.08:02:00.13#ibcon#about to write, iclass 23, count 0 2006.210.08:02:00.13#ibcon#wrote, iclass 23, count 0 2006.210.08:02:00.13#ibcon#about to read 3, iclass 23, count 0 2006.210.08:02:00.15#ibcon#read 3, iclass 23, count 0 2006.210.08:02:00.15#ibcon#about to read 4, iclass 23, count 0 2006.210.08:02:00.15#ibcon#read 4, iclass 23, count 0 2006.210.08:02:00.15#ibcon#about to read 5, iclass 23, count 0 2006.210.08:02:00.15#ibcon#read 5, iclass 23, count 0 2006.210.08:02:00.15#ibcon#about to read 6, iclass 23, count 0 2006.210.08:02:00.15#ibcon#read 6, iclass 23, count 0 2006.210.08:02:00.15#ibcon#end of sib2, iclass 23, count 0 2006.210.08:02:00.15#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:02:00.15#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:02:00.15#ibcon#[25=USB\r\n] 2006.210.08:02:00.15#ibcon#*before write, iclass 23, count 0 2006.210.08:02:00.15#ibcon#enter sib2, iclass 23, count 0 2006.210.08:02:00.15#ibcon#flushed, iclass 23, count 0 2006.210.08:02:00.15#ibcon#about to write, iclass 23, count 0 2006.210.08:02:00.15#ibcon#wrote, iclass 23, count 0 2006.210.08:02:00.15#ibcon#about to read 3, iclass 23, count 0 2006.210.08:02:00.18#ibcon#read 3, iclass 23, count 0 2006.210.08:02:00.18#ibcon#about to read 4, iclass 23, count 0 2006.210.08:02:00.18#ibcon#read 4, iclass 23, count 0 2006.210.08:02:00.18#ibcon#about to read 5, iclass 23, count 0 2006.210.08:02:00.18#ibcon#read 5, iclass 23, count 0 2006.210.08:02:00.18#ibcon#about to read 6, iclass 23, count 0 2006.210.08:02:00.18#ibcon#read 6, iclass 23, count 0 2006.210.08:02:00.18#ibcon#end of sib2, iclass 23, count 0 2006.210.08:02:00.18#ibcon#*after write, iclass 23, count 0 2006.210.08:02:00.18#ibcon#*before return 0, iclass 23, count 0 2006.210.08:02:00.18#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:02:00.18#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:02:00.18#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:02:00.18#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:02:00.18$vc4f8/vblo=1,632.99 2006.210.08:02:00.18#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:02:00.18#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:02:00.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:02:00.18#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:02:00.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:02:00.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:02:00.18#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:02:00.18#ibcon#first serial, iclass 25, count 0 2006.210.08:02:00.18#ibcon#enter sib2, iclass 25, count 0 2006.210.08:02:00.18#ibcon#flushed, iclass 25, count 0 2006.210.08:02:00.18#ibcon#about to write, iclass 25, count 0 2006.210.08:02:00.18#ibcon#wrote, iclass 25, count 0 2006.210.08:02:00.18#ibcon#about to read 3, iclass 25, count 0 2006.210.08:02:00.20#ibcon#read 3, iclass 25, count 0 2006.210.08:02:00.20#ibcon#about to read 4, iclass 25, count 0 2006.210.08:02:00.20#ibcon#read 4, iclass 25, count 0 2006.210.08:02:00.20#ibcon#about to read 5, iclass 25, count 0 2006.210.08:02:00.20#ibcon#read 5, iclass 25, count 0 2006.210.08:02:00.20#ibcon#about to read 6, iclass 25, count 0 2006.210.08:02:00.20#ibcon#read 6, iclass 25, count 0 2006.210.08:02:00.20#ibcon#end of sib2, iclass 25, count 0 2006.210.08:02:00.20#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:02:00.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:02:00.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:02:00.20#ibcon#*before write, iclass 25, count 0 2006.210.08:02:00.20#ibcon#enter sib2, iclass 25, count 0 2006.210.08:02:00.20#ibcon#flushed, iclass 25, count 0 2006.210.08:02:00.20#ibcon#about to write, iclass 25, count 0 2006.210.08:02:00.20#ibcon#wrote, iclass 25, count 0 2006.210.08:02:00.20#ibcon#about to read 3, iclass 25, count 0 2006.210.08:02:00.24#ibcon#read 3, iclass 25, count 0 2006.210.08:02:00.24#ibcon#about to read 4, iclass 25, count 0 2006.210.08:02:00.24#ibcon#read 4, iclass 25, count 0 2006.210.08:02:00.24#ibcon#about to read 5, iclass 25, count 0 2006.210.08:02:00.24#ibcon#read 5, iclass 25, count 0 2006.210.08:02:00.24#ibcon#about to read 6, iclass 25, count 0 2006.210.08:02:00.24#ibcon#read 6, iclass 25, count 0 2006.210.08:02:00.24#ibcon#end of sib2, iclass 25, count 0 2006.210.08:02:00.24#ibcon#*after write, iclass 25, count 0 2006.210.08:02:00.24#ibcon#*before return 0, iclass 25, count 0 2006.210.08:02:00.24#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:02:00.24#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:02:00.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:02:00.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:02:00.24$vc4f8/vb=1,4 2006.210.08:02:00.24#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:02:00.24#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:02:00.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:02:00.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:02:00.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:02:00.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:02:00.24#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:02:00.24#ibcon#first serial, iclass 27, count 2 2006.210.08:02:00.24#ibcon#enter sib2, iclass 27, count 2 2006.210.08:02:00.24#ibcon#flushed, iclass 27, count 2 2006.210.08:02:00.24#ibcon#about to write, iclass 27, count 2 2006.210.08:02:00.24#ibcon#wrote, iclass 27, count 2 2006.210.08:02:00.24#ibcon#about to read 3, iclass 27, count 2 2006.210.08:02:00.26#ibcon#read 3, iclass 27, count 2 2006.210.08:02:00.26#ibcon#about to read 4, iclass 27, count 2 2006.210.08:02:00.26#ibcon#read 4, iclass 27, count 2 2006.210.08:02:00.26#ibcon#about to read 5, iclass 27, count 2 2006.210.08:02:00.26#ibcon#read 5, iclass 27, count 2 2006.210.08:02:00.26#ibcon#about to read 6, iclass 27, count 2 2006.210.08:02:00.26#ibcon#read 6, iclass 27, count 2 2006.210.08:02:00.26#ibcon#end of sib2, iclass 27, count 2 2006.210.08:02:00.26#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:02:00.26#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:02:00.26#ibcon#[27=AT01-04\r\n] 2006.210.08:02:00.26#ibcon#*before write, iclass 27, count 2 2006.210.08:02:00.26#ibcon#enter sib2, iclass 27, count 2 2006.210.08:02:00.26#ibcon#flushed, iclass 27, count 2 2006.210.08:02:00.26#ibcon#about to write, iclass 27, count 2 2006.210.08:02:00.26#ibcon#wrote, iclass 27, count 2 2006.210.08:02:00.26#ibcon#about to read 3, iclass 27, count 2 2006.210.08:02:00.29#ibcon#read 3, iclass 27, count 2 2006.210.08:02:00.29#ibcon#about to read 4, iclass 27, count 2 2006.210.08:02:00.29#ibcon#read 4, iclass 27, count 2 2006.210.08:02:00.29#ibcon#about to read 5, iclass 27, count 2 2006.210.08:02:00.29#ibcon#read 5, iclass 27, count 2 2006.210.08:02:00.29#ibcon#about to read 6, iclass 27, count 2 2006.210.08:02:00.29#ibcon#read 6, iclass 27, count 2 2006.210.08:02:00.29#ibcon#end of sib2, iclass 27, count 2 2006.210.08:02:00.29#ibcon#*after write, iclass 27, count 2 2006.210.08:02:00.29#ibcon#*before return 0, iclass 27, count 2 2006.210.08:02:00.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:02:00.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:02:00.29#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:02:00.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:00.29#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:02:00.41#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:02:00.41#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:02:00.41#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:02:00.41#ibcon#first serial, iclass 27, count 0 2006.210.08:02:00.41#ibcon#enter sib2, iclass 27, count 0 2006.210.08:02:00.41#ibcon#flushed, iclass 27, count 0 2006.210.08:02:00.41#ibcon#about to write, iclass 27, count 0 2006.210.08:02:00.41#ibcon#wrote, iclass 27, count 0 2006.210.08:02:00.41#ibcon#about to read 3, iclass 27, count 0 2006.210.08:02:00.43#ibcon#read 3, iclass 27, count 0 2006.210.08:02:00.43#ibcon#about to read 4, iclass 27, count 0 2006.210.08:02:00.43#ibcon#read 4, iclass 27, count 0 2006.210.08:02:00.43#ibcon#about to read 5, iclass 27, count 0 2006.210.08:02:00.43#ibcon#read 5, iclass 27, count 0 2006.210.08:02:00.43#ibcon#about to read 6, iclass 27, count 0 2006.210.08:02:00.43#ibcon#read 6, iclass 27, count 0 2006.210.08:02:00.43#ibcon#end of sib2, iclass 27, count 0 2006.210.08:02:00.43#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:02:00.43#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:02:00.43#ibcon#[27=USB\r\n] 2006.210.08:02:00.43#ibcon#*before write, iclass 27, count 0 2006.210.08:02:00.43#ibcon#enter sib2, iclass 27, count 0 2006.210.08:02:00.43#ibcon#flushed, iclass 27, count 0 2006.210.08:02:00.43#ibcon#about to write, iclass 27, count 0 2006.210.08:02:00.43#ibcon#wrote, iclass 27, count 0 2006.210.08:02:00.43#ibcon#about to read 3, iclass 27, count 0 2006.210.08:02:00.43#abcon#<5=/05 4.1 7.6 30.46 811006.3\r\n> 2006.210.08:02:00.45#abcon#{5=INTERFACE CLEAR} 2006.210.08:02:00.46#ibcon#read 3, iclass 27, count 0 2006.210.08:02:00.46#ibcon#about to read 4, iclass 27, count 0 2006.210.08:02:00.46#ibcon#read 4, iclass 27, count 0 2006.210.08:02:00.46#ibcon#about to read 5, iclass 27, count 0 2006.210.08:02:00.46#ibcon#read 5, iclass 27, count 0 2006.210.08:02:00.46#ibcon#about to read 6, iclass 27, count 0 2006.210.08:02:00.46#ibcon#read 6, iclass 27, count 0 2006.210.08:02:00.46#ibcon#end of sib2, iclass 27, count 0 2006.210.08:02:00.46#ibcon#*after write, iclass 27, count 0 2006.210.08:02:00.46#ibcon#*before return 0, iclass 27, count 0 2006.210.08:02:00.46#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:02:00.46#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:02:00.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:02:00.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:02:00.46$vc4f8/vblo=2,640.99 2006.210.08:02:00.46#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.08:02:00.46#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.08:02:00.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:02:00.46#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:02:00.46#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:02:00.46#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:02:00.46#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:02:00.46#ibcon#first serial, iclass 32, count 0 2006.210.08:02:00.46#ibcon#enter sib2, iclass 32, count 0 2006.210.08:02:00.46#ibcon#flushed, iclass 32, count 0 2006.210.08:02:00.46#ibcon#about to write, iclass 32, count 0 2006.210.08:02:00.46#ibcon#wrote, iclass 32, count 0 2006.210.08:02:00.46#ibcon#about to read 3, iclass 32, count 0 2006.210.08:02:00.48#ibcon#read 3, iclass 32, count 0 2006.210.08:02:00.48#ibcon#about to read 4, iclass 32, count 0 2006.210.08:02:00.48#ibcon#read 4, iclass 32, count 0 2006.210.08:02:00.48#ibcon#about to read 5, iclass 32, count 0 2006.210.08:02:00.48#ibcon#read 5, iclass 32, count 0 2006.210.08:02:00.48#ibcon#about to read 6, iclass 32, count 0 2006.210.08:02:00.48#ibcon#read 6, iclass 32, count 0 2006.210.08:02:00.48#ibcon#end of sib2, iclass 32, count 0 2006.210.08:02:00.48#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:02:00.48#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:02:00.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:02:00.48#ibcon#*before write, iclass 32, count 0 2006.210.08:02:00.48#ibcon#enter sib2, iclass 32, count 0 2006.210.08:02:00.48#ibcon#flushed, iclass 32, count 0 2006.210.08:02:00.48#ibcon#about to write, iclass 32, count 0 2006.210.08:02:00.48#ibcon#wrote, iclass 32, count 0 2006.210.08:02:00.48#ibcon#about to read 3, iclass 32, count 0 2006.210.08:02:00.51#abcon#[5=S1D000X0/0*\r\n] 2006.210.08:02:00.52#ibcon#read 3, iclass 32, count 0 2006.210.08:02:00.52#ibcon#about to read 4, iclass 32, count 0 2006.210.08:02:00.52#ibcon#read 4, iclass 32, count 0 2006.210.08:02:00.52#ibcon#about to read 5, iclass 32, count 0 2006.210.08:02:00.52#ibcon#read 5, iclass 32, count 0 2006.210.08:02:00.52#ibcon#about to read 6, iclass 32, count 0 2006.210.08:02:00.52#ibcon#read 6, iclass 32, count 0 2006.210.08:02:00.52#ibcon#end of sib2, iclass 32, count 0 2006.210.08:02:00.52#ibcon#*after write, iclass 32, count 0 2006.210.08:02:00.52#ibcon#*before return 0, iclass 32, count 0 2006.210.08:02:00.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:02:00.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:02:00.52#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:02:00.52#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:02:00.52$vc4f8/vb=2,4 2006.210.08:02:00.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:02:00.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:02:00.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:02:00.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:02:00.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:02:00.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:02:00.58#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:02:00.58#ibcon#first serial, iclass 35, count 2 2006.210.08:02:00.58#ibcon#enter sib2, iclass 35, count 2 2006.210.08:02:00.58#ibcon#flushed, iclass 35, count 2 2006.210.08:02:00.58#ibcon#about to write, iclass 35, count 2 2006.210.08:02:00.58#ibcon#wrote, iclass 35, count 2 2006.210.08:02:00.58#ibcon#about to read 3, iclass 35, count 2 2006.210.08:02:00.60#ibcon#read 3, iclass 35, count 2 2006.210.08:02:00.60#ibcon#about to read 4, iclass 35, count 2 2006.210.08:02:00.60#ibcon#read 4, iclass 35, count 2 2006.210.08:02:00.60#ibcon#about to read 5, iclass 35, count 2 2006.210.08:02:00.60#ibcon#read 5, iclass 35, count 2 2006.210.08:02:00.60#ibcon#about to read 6, iclass 35, count 2 2006.210.08:02:00.60#ibcon#read 6, iclass 35, count 2 2006.210.08:02:00.60#ibcon#end of sib2, iclass 35, count 2 2006.210.08:02:00.60#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:02:00.60#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:02:00.60#ibcon#[27=AT02-04\r\n] 2006.210.08:02:00.60#ibcon#*before write, iclass 35, count 2 2006.210.08:02:00.60#ibcon#enter sib2, iclass 35, count 2 2006.210.08:02:00.60#ibcon#flushed, iclass 35, count 2 2006.210.08:02:00.60#ibcon#about to write, iclass 35, count 2 2006.210.08:02:00.60#ibcon#wrote, iclass 35, count 2 2006.210.08:02:00.60#ibcon#about to read 3, iclass 35, count 2 2006.210.08:02:00.63#ibcon#read 3, iclass 35, count 2 2006.210.08:02:00.63#ibcon#about to read 4, iclass 35, count 2 2006.210.08:02:00.63#ibcon#read 4, iclass 35, count 2 2006.210.08:02:00.63#ibcon#about to read 5, iclass 35, count 2 2006.210.08:02:00.63#ibcon#read 5, iclass 35, count 2 2006.210.08:02:00.63#ibcon#about to read 6, iclass 35, count 2 2006.210.08:02:00.63#ibcon#read 6, iclass 35, count 2 2006.210.08:02:00.63#ibcon#end of sib2, iclass 35, count 2 2006.210.08:02:00.63#ibcon#*after write, iclass 35, count 2 2006.210.08:02:00.63#ibcon#*before return 0, iclass 35, count 2 2006.210.08:02:00.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:02:00.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:02:00.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:02:00.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:00.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:02:00.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:02:00.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:02:00.75#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:02:00.75#ibcon#first serial, iclass 35, count 0 2006.210.08:02:00.75#ibcon#enter sib2, iclass 35, count 0 2006.210.08:02:00.75#ibcon#flushed, iclass 35, count 0 2006.210.08:02:00.75#ibcon#about to write, iclass 35, count 0 2006.210.08:02:00.75#ibcon#wrote, iclass 35, count 0 2006.210.08:02:00.75#ibcon#about to read 3, iclass 35, count 0 2006.210.08:02:00.77#ibcon#read 3, iclass 35, count 0 2006.210.08:02:00.77#ibcon#about to read 4, iclass 35, count 0 2006.210.08:02:00.77#ibcon#read 4, iclass 35, count 0 2006.210.08:02:00.77#ibcon#about to read 5, iclass 35, count 0 2006.210.08:02:00.77#ibcon#read 5, iclass 35, count 0 2006.210.08:02:00.77#ibcon#about to read 6, iclass 35, count 0 2006.210.08:02:00.77#ibcon#read 6, iclass 35, count 0 2006.210.08:02:00.77#ibcon#end of sib2, iclass 35, count 0 2006.210.08:02:00.77#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:02:00.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:02:00.77#ibcon#[27=USB\r\n] 2006.210.08:02:00.77#ibcon#*before write, iclass 35, count 0 2006.210.08:02:00.77#ibcon#enter sib2, iclass 35, count 0 2006.210.08:02:00.77#ibcon#flushed, iclass 35, count 0 2006.210.08:02:00.77#ibcon#about to write, iclass 35, count 0 2006.210.08:02:00.77#ibcon#wrote, iclass 35, count 0 2006.210.08:02:00.77#ibcon#about to read 3, iclass 35, count 0 2006.210.08:02:00.80#ibcon#read 3, iclass 35, count 0 2006.210.08:02:00.80#ibcon#about to read 4, iclass 35, count 0 2006.210.08:02:00.80#ibcon#read 4, iclass 35, count 0 2006.210.08:02:00.80#ibcon#about to read 5, iclass 35, count 0 2006.210.08:02:00.80#ibcon#read 5, iclass 35, count 0 2006.210.08:02:00.80#ibcon#about to read 6, iclass 35, count 0 2006.210.08:02:00.80#ibcon#read 6, iclass 35, count 0 2006.210.08:02:00.80#ibcon#end of sib2, iclass 35, count 0 2006.210.08:02:00.80#ibcon#*after write, iclass 35, count 0 2006.210.08:02:00.80#ibcon#*before return 0, iclass 35, count 0 2006.210.08:02:00.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:02:00.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:02:00.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:02:00.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:02:00.80$vc4f8/vblo=3,656.99 2006.210.08:02:00.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:02:00.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:02:00.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:02:00.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:02:00.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:02:00.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:02:00.80#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:02:00.80#ibcon#first serial, iclass 37, count 0 2006.210.08:02:00.80#ibcon#enter sib2, iclass 37, count 0 2006.210.08:02:00.80#ibcon#flushed, iclass 37, count 0 2006.210.08:02:00.80#ibcon#about to write, iclass 37, count 0 2006.210.08:02:00.80#ibcon#wrote, iclass 37, count 0 2006.210.08:02:00.80#ibcon#about to read 3, iclass 37, count 0 2006.210.08:02:00.82#ibcon#read 3, iclass 37, count 0 2006.210.08:02:00.82#ibcon#about to read 4, iclass 37, count 0 2006.210.08:02:00.82#ibcon#read 4, iclass 37, count 0 2006.210.08:02:00.82#ibcon#about to read 5, iclass 37, count 0 2006.210.08:02:00.82#ibcon#read 5, iclass 37, count 0 2006.210.08:02:00.82#ibcon#about to read 6, iclass 37, count 0 2006.210.08:02:00.82#ibcon#read 6, iclass 37, count 0 2006.210.08:02:00.82#ibcon#end of sib2, iclass 37, count 0 2006.210.08:02:00.82#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:02:00.82#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:02:00.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:02:00.82#ibcon#*before write, iclass 37, count 0 2006.210.08:02:00.82#ibcon#enter sib2, iclass 37, count 0 2006.210.08:02:00.82#ibcon#flushed, iclass 37, count 0 2006.210.08:02:00.82#ibcon#about to write, iclass 37, count 0 2006.210.08:02:00.82#ibcon#wrote, iclass 37, count 0 2006.210.08:02:00.82#ibcon#about to read 3, iclass 37, count 0 2006.210.08:02:00.86#ibcon#read 3, iclass 37, count 0 2006.210.08:02:00.86#ibcon#about to read 4, iclass 37, count 0 2006.210.08:02:00.86#ibcon#read 4, iclass 37, count 0 2006.210.08:02:00.86#ibcon#about to read 5, iclass 37, count 0 2006.210.08:02:00.86#ibcon#read 5, iclass 37, count 0 2006.210.08:02:00.86#ibcon#about to read 6, iclass 37, count 0 2006.210.08:02:00.86#ibcon#read 6, iclass 37, count 0 2006.210.08:02:00.86#ibcon#end of sib2, iclass 37, count 0 2006.210.08:02:00.86#ibcon#*after write, iclass 37, count 0 2006.210.08:02:00.86#ibcon#*before return 0, iclass 37, count 0 2006.210.08:02:00.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:02:00.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:02:00.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:02:00.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:02:00.86$vc4f8/vb=3,3 2006.210.08:02:00.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:02:00.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:02:00.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:02:00.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:02:00.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:02:00.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:02:00.92#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:02:00.92#ibcon#first serial, iclass 39, count 2 2006.210.08:02:00.92#ibcon#enter sib2, iclass 39, count 2 2006.210.08:02:00.92#ibcon#flushed, iclass 39, count 2 2006.210.08:02:00.92#ibcon#about to write, iclass 39, count 2 2006.210.08:02:00.92#ibcon#wrote, iclass 39, count 2 2006.210.08:02:00.92#ibcon#about to read 3, iclass 39, count 2 2006.210.08:02:00.94#ibcon#read 3, iclass 39, count 2 2006.210.08:02:00.94#ibcon#about to read 4, iclass 39, count 2 2006.210.08:02:00.94#ibcon#read 4, iclass 39, count 2 2006.210.08:02:00.94#ibcon#about to read 5, iclass 39, count 2 2006.210.08:02:00.94#ibcon#read 5, iclass 39, count 2 2006.210.08:02:00.94#ibcon#about to read 6, iclass 39, count 2 2006.210.08:02:00.94#ibcon#read 6, iclass 39, count 2 2006.210.08:02:00.94#ibcon#end of sib2, iclass 39, count 2 2006.210.08:02:00.94#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:02:00.94#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:02:00.94#ibcon#[27=AT03-03\r\n] 2006.210.08:02:00.94#ibcon#*before write, iclass 39, count 2 2006.210.08:02:00.94#ibcon#enter sib2, iclass 39, count 2 2006.210.08:02:00.94#ibcon#flushed, iclass 39, count 2 2006.210.08:02:00.94#ibcon#about to write, iclass 39, count 2 2006.210.08:02:00.94#ibcon#wrote, iclass 39, count 2 2006.210.08:02:00.94#ibcon#about to read 3, iclass 39, count 2 2006.210.08:02:00.97#ibcon#read 3, iclass 39, count 2 2006.210.08:02:00.97#ibcon#about to read 4, iclass 39, count 2 2006.210.08:02:00.97#ibcon#read 4, iclass 39, count 2 2006.210.08:02:00.97#ibcon#about to read 5, iclass 39, count 2 2006.210.08:02:00.97#ibcon#read 5, iclass 39, count 2 2006.210.08:02:00.97#ibcon#about to read 6, iclass 39, count 2 2006.210.08:02:00.97#ibcon#read 6, iclass 39, count 2 2006.210.08:02:00.97#ibcon#end of sib2, iclass 39, count 2 2006.210.08:02:00.97#ibcon#*after write, iclass 39, count 2 2006.210.08:02:00.97#ibcon#*before return 0, iclass 39, count 2 2006.210.08:02:00.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:02:00.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:02:00.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:02:00.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:00.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:02:01.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:02:01.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:02:01.09#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:02:01.09#ibcon#first serial, iclass 39, count 0 2006.210.08:02:01.09#ibcon#enter sib2, iclass 39, count 0 2006.210.08:02:01.09#ibcon#flushed, iclass 39, count 0 2006.210.08:02:01.09#ibcon#about to write, iclass 39, count 0 2006.210.08:02:01.09#ibcon#wrote, iclass 39, count 0 2006.210.08:02:01.09#ibcon#about to read 3, iclass 39, count 0 2006.210.08:02:01.11#ibcon#read 3, iclass 39, count 0 2006.210.08:02:01.11#ibcon#about to read 4, iclass 39, count 0 2006.210.08:02:01.11#ibcon#read 4, iclass 39, count 0 2006.210.08:02:01.11#ibcon#about to read 5, iclass 39, count 0 2006.210.08:02:01.11#ibcon#read 5, iclass 39, count 0 2006.210.08:02:01.11#ibcon#about to read 6, iclass 39, count 0 2006.210.08:02:01.11#ibcon#read 6, iclass 39, count 0 2006.210.08:02:01.11#ibcon#end of sib2, iclass 39, count 0 2006.210.08:02:01.11#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:02:01.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:02:01.11#ibcon#[27=USB\r\n] 2006.210.08:02:01.11#ibcon#*before write, iclass 39, count 0 2006.210.08:02:01.11#ibcon#enter sib2, iclass 39, count 0 2006.210.08:02:01.11#ibcon#flushed, iclass 39, count 0 2006.210.08:02:01.11#ibcon#about to write, iclass 39, count 0 2006.210.08:02:01.11#ibcon#wrote, iclass 39, count 0 2006.210.08:02:01.11#ibcon#about to read 3, iclass 39, count 0 2006.210.08:02:01.14#ibcon#read 3, iclass 39, count 0 2006.210.08:02:01.14#ibcon#about to read 4, iclass 39, count 0 2006.210.08:02:01.14#ibcon#read 4, iclass 39, count 0 2006.210.08:02:01.14#ibcon#about to read 5, iclass 39, count 0 2006.210.08:02:01.14#ibcon#read 5, iclass 39, count 0 2006.210.08:02:01.14#ibcon#about to read 6, iclass 39, count 0 2006.210.08:02:01.14#ibcon#read 6, iclass 39, count 0 2006.210.08:02:01.14#ibcon#end of sib2, iclass 39, count 0 2006.210.08:02:01.14#ibcon#*after write, iclass 39, count 0 2006.210.08:02:01.14#ibcon#*before return 0, iclass 39, count 0 2006.210.08:02:01.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:02:01.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:02:01.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:02:01.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:02:01.14$vc4f8/vblo=4,712.99 2006.210.08:02:01.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:02:01.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:02:01.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:02:01.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:02:01.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:02:01.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:02:01.14#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:02:01.14#ibcon#first serial, iclass 3, count 0 2006.210.08:02:01.14#ibcon#enter sib2, iclass 3, count 0 2006.210.08:02:01.14#ibcon#flushed, iclass 3, count 0 2006.210.08:02:01.14#ibcon#about to write, iclass 3, count 0 2006.210.08:02:01.14#ibcon#wrote, iclass 3, count 0 2006.210.08:02:01.14#ibcon#about to read 3, iclass 3, count 0 2006.210.08:02:01.16#ibcon#read 3, iclass 3, count 0 2006.210.08:02:01.16#ibcon#about to read 4, iclass 3, count 0 2006.210.08:02:01.16#ibcon#read 4, iclass 3, count 0 2006.210.08:02:01.16#ibcon#about to read 5, iclass 3, count 0 2006.210.08:02:01.16#ibcon#read 5, iclass 3, count 0 2006.210.08:02:01.16#ibcon#about to read 6, iclass 3, count 0 2006.210.08:02:01.16#ibcon#read 6, iclass 3, count 0 2006.210.08:02:01.16#ibcon#end of sib2, iclass 3, count 0 2006.210.08:02:01.16#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:02:01.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:02:01.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:02:01.16#ibcon#*before write, iclass 3, count 0 2006.210.08:02:01.16#ibcon#enter sib2, iclass 3, count 0 2006.210.08:02:01.16#ibcon#flushed, iclass 3, count 0 2006.210.08:02:01.16#ibcon#about to write, iclass 3, count 0 2006.210.08:02:01.16#ibcon#wrote, iclass 3, count 0 2006.210.08:02:01.16#ibcon#about to read 3, iclass 3, count 0 2006.210.08:02:01.20#ibcon#read 3, iclass 3, count 0 2006.210.08:02:01.20#ibcon#about to read 4, iclass 3, count 0 2006.210.08:02:01.20#ibcon#read 4, iclass 3, count 0 2006.210.08:02:01.20#ibcon#about to read 5, iclass 3, count 0 2006.210.08:02:01.20#ibcon#read 5, iclass 3, count 0 2006.210.08:02:01.20#ibcon#about to read 6, iclass 3, count 0 2006.210.08:02:01.20#ibcon#read 6, iclass 3, count 0 2006.210.08:02:01.20#ibcon#end of sib2, iclass 3, count 0 2006.210.08:02:01.20#ibcon#*after write, iclass 3, count 0 2006.210.08:02:01.20#ibcon#*before return 0, iclass 3, count 0 2006.210.08:02:01.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:02:01.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:02:01.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:02:01.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:02:01.20$vc4f8/vb=4,3 2006.210.08:02:01.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:02:01.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:02:01.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:02:01.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:02:01.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:02:01.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:02:01.26#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:02:01.26#ibcon#first serial, iclass 5, count 2 2006.210.08:02:01.26#ibcon#enter sib2, iclass 5, count 2 2006.210.08:02:01.26#ibcon#flushed, iclass 5, count 2 2006.210.08:02:01.26#ibcon#about to write, iclass 5, count 2 2006.210.08:02:01.26#ibcon#wrote, iclass 5, count 2 2006.210.08:02:01.26#ibcon#about to read 3, iclass 5, count 2 2006.210.08:02:01.28#ibcon#read 3, iclass 5, count 2 2006.210.08:02:01.28#ibcon#about to read 4, iclass 5, count 2 2006.210.08:02:01.28#ibcon#read 4, iclass 5, count 2 2006.210.08:02:01.28#ibcon#about to read 5, iclass 5, count 2 2006.210.08:02:01.28#ibcon#read 5, iclass 5, count 2 2006.210.08:02:01.28#ibcon#about to read 6, iclass 5, count 2 2006.210.08:02:01.28#ibcon#read 6, iclass 5, count 2 2006.210.08:02:01.28#ibcon#end of sib2, iclass 5, count 2 2006.210.08:02:01.28#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:02:01.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:02:01.28#ibcon#[27=AT04-03\r\n] 2006.210.08:02:01.28#ibcon#*before write, iclass 5, count 2 2006.210.08:02:01.28#ibcon#enter sib2, iclass 5, count 2 2006.210.08:02:01.28#ibcon#flushed, iclass 5, count 2 2006.210.08:02:01.28#ibcon#about to write, iclass 5, count 2 2006.210.08:02:01.28#ibcon#wrote, iclass 5, count 2 2006.210.08:02:01.28#ibcon#about to read 3, iclass 5, count 2 2006.210.08:02:01.31#ibcon#read 3, iclass 5, count 2 2006.210.08:02:01.31#ibcon#about to read 4, iclass 5, count 2 2006.210.08:02:01.31#ibcon#read 4, iclass 5, count 2 2006.210.08:02:01.31#ibcon#about to read 5, iclass 5, count 2 2006.210.08:02:01.31#ibcon#read 5, iclass 5, count 2 2006.210.08:02:01.31#ibcon#about to read 6, iclass 5, count 2 2006.210.08:02:01.31#ibcon#read 6, iclass 5, count 2 2006.210.08:02:01.31#ibcon#end of sib2, iclass 5, count 2 2006.210.08:02:01.31#ibcon#*after write, iclass 5, count 2 2006.210.08:02:01.31#ibcon#*before return 0, iclass 5, count 2 2006.210.08:02:01.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:02:01.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:02:01.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:02:01.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:01.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:02:01.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:02:01.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:02:01.43#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:02:01.43#ibcon#first serial, iclass 5, count 0 2006.210.08:02:01.43#ibcon#enter sib2, iclass 5, count 0 2006.210.08:02:01.43#ibcon#flushed, iclass 5, count 0 2006.210.08:02:01.43#ibcon#about to write, iclass 5, count 0 2006.210.08:02:01.43#ibcon#wrote, iclass 5, count 0 2006.210.08:02:01.43#ibcon#about to read 3, iclass 5, count 0 2006.210.08:02:01.45#ibcon#read 3, iclass 5, count 0 2006.210.08:02:01.45#ibcon#about to read 4, iclass 5, count 0 2006.210.08:02:01.45#ibcon#read 4, iclass 5, count 0 2006.210.08:02:01.45#ibcon#about to read 5, iclass 5, count 0 2006.210.08:02:01.45#ibcon#read 5, iclass 5, count 0 2006.210.08:02:01.45#ibcon#about to read 6, iclass 5, count 0 2006.210.08:02:01.45#ibcon#read 6, iclass 5, count 0 2006.210.08:02:01.45#ibcon#end of sib2, iclass 5, count 0 2006.210.08:02:01.45#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:02:01.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:02:01.45#ibcon#[27=USB\r\n] 2006.210.08:02:01.45#ibcon#*before write, iclass 5, count 0 2006.210.08:02:01.45#ibcon#enter sib2, iclass 5, count 0 2006.210.08:02:01.45#ibcon#flushed, iclass 5, count 0 2006.210.08:02:01.45#ibcon#about to write, iclass 5, count 0 2006.210.08:02:01.45#ibcon#wrote, iclass 5, count 0 2006.210.08:02:01.45#ibcon#about to read 3, iclass 5, count 0 2006.210.08:02:01.48#ibcon#read 3, iclass 5, count 0 2006.210.08:02:01.48#ibcon#about to read 4, iclass 5, count 0 2006.210.08:02:01.48#ibcon#read 4, iclass 5, count 0 2006.210.08:02:01.48#ibcon#about to read 5, iclass 5, count 0 2006.210.08:02:01.48#ibcon#read 5, iclass 5, count 0 2006.210.08:02:01.48#ibcon#about to read 6, iclass 5, count 0 2006.210.08:02:01.48#ibcon#read 6, iclass 5, count 0 2006.210.08:02:01.48#ibcon#end of sib2, iclass 5, count 0 2006.210.08:02:01.48#ibcon#*after write, iclass 5, count 0 2006.210.08:02:01.48#ibcon#*before return 0, iclass 5, count 0 2006.210.08:02:01.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:02:01.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:02:01.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:02:01.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:02:01.48$vc4f8/vblo=5,744.99 2006.210.08:02:01.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:02:01.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:02:01.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:02:01.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:02:01.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:02:01.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:02:01.48#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:02:01.48#ibcon#first serial, iclass 7, count 0 2006.210.08:02:01.48#ibcon#enter sib2, iclass 7, count 0 2006.210.08:02:01.48#ibcon#flushed, iclass 7, count 0 2006.210.08:02:01.48#ibcon#about to write, iclass 7, count 0 2006.210.08:02:01.48#ibcon#wrote, iclass 7, count 0 2006.210.08:02:01.48#ibcon#about to read 3, iclass 7, count 0 2006.210.08:02:01.50#ibcon#read 3, iclass 7, count 0 2006.210.08:02:01.50#ibcon#about to read 4, iclass 7, count 0 2006.210.08:02:01.50#ibcon#read 4, iclass 7, count 0 2006.210.08:02:01.50#ibcon#about to read 5, iclass 7, count 0 2006.210.08:02:01.50#ibcon#read 5, iclass 7, count 0 2006.210.08:02:01.50#ibcon#about to read 6, iclass 7, count 0 2006.210.08:02:01.50#ibcon#read 6, iclass 7, count 0 2006.210.08:02:01.50#ibcon#end of sib2, iclass 7, count 0 2006.210.08:02:01.50#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:02:01.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:02:01.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:02:01.50#ibcon#*before write, iclass 7, count 0 2006.210.08:02:01.50#ibcon#enter sib2, iclass 7, count 0 2006.210.08:02:01.50#ibcon#flushed, iclass 7, count 0 2006.210.08:02:01.50#ibcon#about to write, iclass 7, count 0 2006.210.08:02:01.50#ibcon#wrote, iclass 7, count 0 2006.210.08:02:01.50#ibcon#about to read 3, iclass 7, count 0 2006.210.08:02:01.54#ibcon#read 3, iclass 7, count 0 2006.210.08:02:01.54#ibcon#about to read 4, iclass 7, count 0 2006.210.08:02:01.54#ibcon#read 4, iclass 7, count 0 2006.210.08:02:01.54#ibcon#about to read 5, iclass 7, count 0 2006.210.08:02:01.54#ibcon#read 5, iclass 7, count 0 2006.210.08:02:01.54#ibcon#about to read 6, iclass 7, count 0 2006.210.08:02:01.54#ibcon#read 6, iclass 7, count 0 2006.210.08:02:01.54#ibcon#end of sib2, iclass 7, count 0 2006.210.08:02:01.54#ibcon#*after write, iclass 7, count 0 2006.210.08:02:01.54#ibcon#*before return 0, iclass 7, count 0 2006.210.08:02:01.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:02:01.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:02:01.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:02:01.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:02:01.54$vc4f8/vb=5,3 2006.210.08:02:01.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:02:01.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:02:01.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:02:01.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:02:01.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:02:01.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:02:01.60#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:02:01.60#ibcon#first serial, iclass 11, count 2 2006.210.08:02:01.60#ibcon#enter sib2, iclass 11, count 2 2006.210.08:02:01.60#ibcon#flushed, iclass 11, count 2 2006.210.08:02:01.60#ibcon#about to write, iclass 11, count 2 2006.210.08:02:01.60#ibcon#wrote, iclass 11, count 2 2006.210.08:02:01.60#ibcon#about to read 3, iclass 11, count 2 2006.210.08:02:01.62#ibcon#read 3, iclass 11, count 2 2006.210.08:02:01.62#ibcon#about to read 4, iclass 11, count 2 2006.210.08:02:01.62#ibcon#read 4, iclass 11, count 2 2006.210.08:02:01.62#ibcon#about to read 5, iclass 11, count 2 2006.210.08:02:01.62#ibcon#read 5, iclass 11, count 2 2006.210.08:02:01.62#ibcon#about to read 6, iclass 11, count 2 2006.210.08:02:01.62#ibcon#read 6, iclass 11, count 2 2006.210.08:02:01.62#ibcon#end of sib2, iclass 11, count 2 2006.210.08:02:01.62#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:02:01.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:02:01.62#ibcon#[27=AT05-03\r\n] 2006.210.08:02:01.62#ibcon#*before write, iclass 11, count 2 2006.210.08:02:01.62#ibcon#enter sib2, iclass 11, count 2 2006.210.08:02:01.62#ibcon#flushed, iclass 11, count 2 2006.210.08:02:01.62#ibcon#about to write, iclass 11, count 2 2006.210.08:02:01.62#ibcon#wrote, iclass 11, count 2 2006.210.08:02:01.62#ibcon#about to read 3, iclass 11, count 2 2006.210.08:02:01.65#ibcon#read 3, iclass 11, count 2 2006.210.08:02:01.65#ibcon#about to read 4, iclass 11, count 2 2006.210.08:02:01.65#ibcon#read 4, iclass 11, count 2 2006.210.08:02:01.65#ibcon#about to read 5, iclass 11, count 2 2006.210.08:02:01.65#ibcon#read 5, iclass 11, count 2 2006.210.08:02:01.65#ibcon#about to read 6, iclass 11, count 2 2006.210.08:02:01.65#ibcon#read 6, iclass 11, count 2 2006.210.08:02:01.65#ibcon#end of sib2, iclass 11, count 2 2006.210.08:02:01.65#ibcon#*after write, iclass 11, count 2 2006.210.08:02:01.65#ibcon#*before return 0, iclass 11, count 2 2006.210.08:02:01.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:02:01.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:02:01.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:02:01.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:01.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:02:01.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:02:01.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:02:01.77#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:02:01.77#ibcon#first serial, iclass 11, count 0 2006.210.08:02:01.77#ibcon#enter sib2, iclass 11, count 0 2006.210.08:02:01.77#ibcon#flushed, iclass 11, count 0 2006.210.08:02:01.77#ibcon#about to write, iclass 11, count 0 2006.210.08:02:01.77#ibcon#wrote, iclass 11, count 0 2006.210.08:02:01.77#ibcon#about to read 3, iclass 11, count 0 2006.210.08:02:01.79#ibcon#read 3, iclass 11, count 0 2006.210.08:02:01.79#ibcon#about to read 4, iclass 11, count 0 2006.210.08:02:01.79#ibcon#read 4, iclass 11, count 0 2006.210.08:02:01.79#ibcon#about to read 5, iclass 11, count 0 2006.210.08:02:01.79#ibcon#read 5, iclass 11, count 0 2006.210.08:02:01.79#ibcon#about to read 6, iclass 11, count 0 2006.210.08:02:01.79#ibcon#read 6, iclass 11, count 0 2006.210.08:02:01.79#ibcon#end of sib2, iclass 11, count 0 2006.210.08:02:01.79#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:02:01.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:02:01.79#ibcon#[27=USB\r\n] 2006.210.08:02:01.79#ibcon#*before write, iclass 11, count 0 2006.210.08:02:01.79#ibcon#enter sib2, iclass 11, count 0 2006.210.08:02:01.79#ibcon#flushed, iclass 11, count 0 2006.210.08:02:01.79#ibcon#about to write, iclass 11, count 0 2006.210.08:02:01.79#ibcon#wrote, iclass 11, count 0 2006.210.08:02:01.79#ibcon#about to read 3, iclass 11, count 0 2006.210.08:02:01.82#ibcon#read 3, iclass 11, count 0 2006.210.08:02:01.82#ibcon#about to read 4, iclass 11, count 0 2006.210.08:02:01.82#ibcon#read 4, iclass 11, count 0 2006.210.08:02:01.82#ibcon#about to read 5, iclass 11, count 0 2006.210.08:02:01.82#ibcon#read 5, iclass 11, count 0 2006.210.08:02:01.82#ibcon#about to read 6, iclass 11, count 0 2006.210.08:02:01.82#ibcon#read 6, iclass 11, count 0 2006.210.08:02:01.82#ibcon#end of sib2, iclass 11, count 0 2006.210.08:02:01.82#ibcon#*after write, iclass 11, count 0 2006.210.08:02:01.82#ibcon#*before return 0, iclass 11, count 0 2006.210.08:02:01.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:02:01.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:02:01.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:02:01.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:02:01.82$vc4f8/vblo=6,752.99 2006.210.08:02:01.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:02:01.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:02:01.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:02:01.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:02:01.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:02:01.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:02:01.82#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:02:01.82#ibcon#first serial, iclass 13, count 0 2006.210.08:02:01.82#ibcon#enter sib2, iclass 13, count 0 2006.210.08:02:01.82#ibcon#flushed, iclass 13, count 0 2006.210.08:02:01.82#ibcon#about to write, iclass 13, count 0 2006.210.08:02:01.82#ibcon#wrote, iclass 13, count 0 2006.210.08:02:01.82#ibcon#about to read 3, iclass 13, count 0 2006.210.08:02:01.84#ibcon#read 3, iclass 13, count 0 2006.210.08:02:01.84#ibcon#about to read 4, iclass 13, count 0 2006.210.08:02:01.84#ibcon#read 4, iclass 13, count 0 2006.210.08:02:01.84#ibcon#about to read 5, iclass 13, count 0 2006.210.08:02:01.84#ibcon#read 5, iclass 13, count 0 2006.210.08:02:01.84#ibcon#about to read 6, iclass 13, count 0 2006.210.08:02:01.84#ibcon#read 6, iclass 13, count 0 2006.210.08:02:01.84#ibcon#end of sib2, iclass 13, count 0 2006.210.08:02:01.84#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:02:01.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:02:01.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:02:01.84#ibcon#*before write, iclass 13, count 0 2006.210.08:02:01.84#ibcon#enter sib2, iclass 13, count 0 2006.210.08:02:01.84#ibcon#flushed, iclass 13, count 0 2006.210.08:02:01.84#ibcon#about to write, iclass 13, count 0 2006.210.08:02:01.84#ibcon#wrote, iclass 13, count 0 2006.210.08:02:01.84#ibcon#about to read 3, iclass 13, count 0 2006.210.08:02:01.88#ibcon#read 3, iclass 13, count 0 2006.210.08:02:01.88#ibcon#about to read 4, iclass 13, count 0 2006.210.08:02:01.88#ibcon#read 4, iclass 13, count 0 2006.210.08:02:01.88#ibcon#about to read 5, iclass 13, count 0 2006.210.08:02:01.88#ibcon#read 5, iclass 13, count 0 2006.210.08:02:01.88#ibcon#about to read 6, iclass 13, count 0 2006.210.08:02:01.88#ibcon#read 6, iclass 13, count 0 2006.210.08:02:01.88#ibcon#end of sib2, iclass 13, count 0 2006.210.08:02:01.88#ibcon#*after write, iclass 13, count 0 2006.210.08:02:01.88#ibcon#*before return 0, iclass 13, count 0 2006.210.08:02:01.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:02:01.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:02:01.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:02:01.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:02:01.88$vc4f8/vb=6,3 2006.210.08:02:01.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:02:01.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:02:01.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:02:01.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:02:01.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:02:01.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:02:01.94#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:02:01.94#ibcon#first serial, iclass 15, count 2 2006.210.08:02:01.94#ibcon#enter sib2, iclass 15, count 2 2006.210.08:02:01.94#ibcon#flushed, iclass 15, count 2 2006.210.08:02:01.94#ibcon#about to write, iclass 15, count 2 2006.210.08:02:01.94#ibcon#wrote, iclass 15, count 2 2006.210.08:02:01.94#ibcon#about to read 3, iclass 15, count 2 2006.210.08:02:01.96#ibcon#read 3, iclass 15, count 2 2006.210.08:02:01.96#ibcon#about to read 4, iclass 15, count 2 2006.210.08:02:01.96#ibcon#read 4, iclass 15, count 2 2006.210.08:02:01.96#ibcon#about to read 5, iclass 15, count 2 2006.210.08:02:01.96#ibcon#read 5, iclass 15, count 2 2006.210.08:02:01.96#ibcon#about to read 6, iclass 15, count 2 2006.210.08:02:01.96#ibcon#read 6, iclass 15, count 2 2006.210.08:02:01.96#ibcon#end of sib2, iclass 15, count 2 2006.210.08:02:01.96#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:02:01.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:02:01.96#ibcon#[27=AT06-03\r\n] 2006.210.08:02:01.96#ibcon#*before write, iclass 15, count 2 2006.210.08:02:01.96#ibcon#enter sib2, iclass 15, count 2 2006.210.08:02:01.96#ibcon#flushed, iclass 15, count 2 2006.210.08:02:01.96#ibcon#about to write, iclass 15, count 2 2006.210.08:02:01.96#ibcon#wrote, iclass 15, count 2 2006.210.08:02:01.96#ibcon#about to read 3, iclass 15, count 2 2006.210.08:02:01.99#ibcon#read 3, iclass 15, count 2 2006.210.08:02:01.99#ibcon#about to read 4, iclass 15, count 2 2006.210.08:02:01.99#ibcon#read 4, iclass 15, count 2 2006.210.08:02:01.99#ibcon#about to read 5, iclass 15, count 2 2006.210.08:02:01.99#ibcon#read 5, iclass 15, count 2 2006.210.08:02:01.99#ibcon#about to read 6, iclass 15, count 2 2006.210.08:02:01.99#ibcon#read 6, iclass 15, count 2 2006.210.08:02:01.99#ibcon#end of sib2, iclass 15, count 2 2006.210.08:02:01.99#ibcon#*after write, iclass 15, count 2 2006.210.08:02:01.99#ibcon#*before return 0, iclass 15, count 2 2006.210.08:02:01.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:02:01.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:02:01.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:02:01.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:02:01.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:02:02.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:02:02.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:02:02.11#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:02:02.11#ibcon#first serial, iclass 15, count 0 2006.210.08:02:02.11#ibcon#enter sib2, iclass 15, count 0 2006.210.08:02:02.11#ibcon#flushed, iclass 15, count 0 2006.210.08:02:02.11#ibcon#about to write, iclass 15, count 0 2006.210.08:02:02.11#ibcon#wrote, iclass 15, count 0 2006.210.08:02:02.11#ibcon#about to read 3, iclass 15, count 0 2006.210.08:02:02.13#ibcon#read 3, iclass 15, count 0 2006.210.08:02:02.13#ibcon#about to read 4, iclass 15, count 0 2006.210.08:02:02.13#ibcon#read 4, iclass 15, count 0 2006.210.08:02:02.13#ibcon#about to read 5, iclass 15, count 0 2006.210.08:02:02.13#ibcon#read 5, iclass 15, count 0 2006.210.08:02:02.13#ibcon#about to read 6, iclass 15, count 0 2006.210.08:02:02.13#ibcon#read 6, iclass 15, count 0 2006.210.08:02:02.13#ibcon#end of sib2, iclass 15, count 0 2006.210.08:02:02.13#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:02:02.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:02:02.13#ibcon#[27=USB\r\n] 2006.210.08:02:02.13#ibcon#*before write, iclass 15, count 0 2006.210.08:02:02.13#ibcon#enter sib2, iclass 15, count 0 2006.210.08:02:02.13#ibcon#flushed, iclass 15, count 0 2006.210.08:02:02.13#ibcon#about to write, iclass 15, count 0 2006.210.08:02:02.13#ibcon#wrote, iclass 15, count 0 2006.210.08:02:02.13#ibcon#about to read 3, iclass 15, count 0 2006.210.08:02:02.16#ibcon#read 3, iclass 15, count 0 2006.210.08:02:02.16#ibcon#about to read 4, iclass 15, count 0 2006.210.08:02:02.16#ibcon#read 4, iclass 15, count 0 2006.210.08:02:02.16#ibcon#about to read 5, iclass 15, count 0 2006.210.08:02:02.16#ibcon#read 5, iclass 15, count 0 2006.210.08:02:02.16#ibcon#about to read 6, iclass 15, count 0 2006.210.08:02:02.16#ibcon#read 6, iclass 15, count 0 2006.210.08:02:02.16#ibcon#end of sib2, iclass 15, count 0 2006.210.08:02:02.16#ibcon#*after write, iclass 15, count 0 2006.210.08:02:02.16#ibcon#*before return 0, iclass 15, count 0 2006.210.08:02:02.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:02:02.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:02:02.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:02:02.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:02:02.16$vc4f8/vabw=wide 2006.210.08:02:02.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:02:02.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:02:02.16#ibcon#ireg 8 cls_cnt 0 2006.210.08:02:02.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:02:02.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:02:02.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:02:02.16#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:02:02.16#ibcon#first serial, iclass 17, count 0 2006.210.08:02:02.16#ibcon#enter sib2, iclass 17, count 0 2006.210.08:02:02.16#ibcon#flushed, iclass 17, count 0 2006.210.08:02:02.16#ibcon#about to write, iclass 17, count 0 2006.210.08:02:02.16#ibcon#wrote, iclass 17, count 0 2006.210.08:02:02.16#ibcon#about to read 3, iclass 17, count 0 2006.210.08:02:02.18#ibcon#read 3, iclass 17, count 0 2006.210.08:02:02.18#ibcon#about to read 4, iclass 17, count 0 2006.210.08:02:02.18#ibcon#read 4, iclass 17, count 0 2006.210.08:02:02.18#ibcon#about to read 5, iclass 17, count 0 2006.210.08:02:02.18#ibcon#read 5, iclass 17, count 0 2006.210.08:02:02.18#ibcon#about to read 6, iclass 17, count 0 2006.210.08:02:02.18#ibcon#read 6, iclass 17, count 0 2006.210.08:02:02.18#ibcon#end of sib2, iclass 17, count 0 2006.210.08:02:02.18#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:02:02.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:02:02.18#ibcon#[25=BW32\r\n] 2006.210.08:02:02.18#ibcon#*before write, iclass 17, count 0 2006.210.08:02:02.18#ibcon#enter sib2, iclass 17, count 0 2006.210.08:02:02.18#ibcon#flushed, iclass 17, count 0 2006.210.08:02:02.18#ibcon#about to write, iclass 17, count 0 2006.210.08:02:02.18#ibcon#wrote, iclass 17, count 0 2006.210.08:02:02.18#ibcon#about to read 3, iclass 17, count 0 2006.210.08:02:02.21#ibcon#read 3, iclass 17, count 0 2006.210.08:02:02.21#ibcon#about to read 4, iclass 17, count 0 2006.210.08:02:02.21#ibcon#read 4, iclass 17, count 0 2006.210.08:02:02.21#ibcon#about to read 5, iclass 17, count 0 2006.210.08:02:02.21#ibcon#read 5, iclass 17, count 0 2006.210.08:02:02.21#ibcon#about to read 6, iclass 17, count 0 2006.210.08:02:02.21#ibcon#read 6, iclass 17, count 0 2006.210.08:02:02.21#ibcon#end of sib2, iclass 17, count 0 2006.210.08:02:02.21#ibcon#*after write, iclass 17, count 0 2006.210.08:02:02.21#ibcon#*before return 0, iclass 17, count 0 2006.210.08:02:02.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:02:02.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:02:02.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:02:02.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:02:02.21$vc4f8/vbbw=wide 2006.210.08:02:02.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.08:02:02.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.08:02:02.21#ibcon#ireg 8 cls_cnt 0 2006.210.08:02:02.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:02:02.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:02:02.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:02:02.28#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:02:02.28#ibcon#first serial, iclass 19, count 0 2006.210.08:02:02.28#ibcon#enter sib2, iclass 19, count 0 2006.210.08:02:02.28#ibcon#flushed, iclass 19, count 0 2006.210.08:02:02.28#ibcon#about to write, iclass 19, count 0 2006.210.08:02:02.28#ibcon#wrote, iclass 19, count 0 2006.210.08:02:02.28#ibcon#about to read 3, iclass 19, count 0 2006.210.08:02:02.30#ibcon#read 3, iclass 19, count 0 2006.210.08:02:02.30#ibcon#about to read 4, iclass 19, count 0 2006.210.08:02:02.30#ibcon#read 4, iclass 19, count 0 2006.210.08:02:02.30#ibcon#about to read 5, iclass 19, count 0 2006.210.08:02:02.30#ibcon#read 5, iclass 19, count 0 2006.210.08:02:02.30#ibcon#about to read 6, iclass 19, count 0 2006.210.08:02:02.30#ibcon#read 6, iclass 19, count 0 2006.210.08:02:02.30#ibcon#end of sib2, iclass 19, count 0 2006.210.08:02:02.30#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:02:02.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:02:02.30#ibcon#[27=BW32\r\n] 2006.210.08:02:02.30#ibcon#*before write, iclass 19, count 0 2006.210.08:02:02.30#ibcon#enter sib2, iclass 19, count 0 2006.210.08:02:02.30#ibcon#flushed, iclass 19, count 0 2006.210.08:02:02.30#ibcon#about to write, iclass 19, count 0 2006.210.08:02:02.30#ibcon#wrote, iclass 19, count 0 2006.210.08:02:02.30#ibcon#about to read 3, iclass 19, count 0 2006.210.08:02:02.33#ibcon#read 3, iclass 19, count 0 2006.210.08:02:02.33#ibcon#about to read 4, iclass 19, count 0 2006.210.08:02:02.33#ibcon#read 4, iclass 19, count 0 2006.210.08:02:02.33#ibcon#about to read 5, iclass 19, count 0 2006.210.08:02:02.33#ibcon#read 5, iclass 19, count 0 2006.210.08:02:02.33#ibcon#about to read 6, iclass 19, count 0 2006.210.08:02:02.33#ibcon#read 6, iclass 19, count 0 2006.210.08:02:02.33#ibcon#end of sib2, iclass 19, count 0 2006.210.08:02:02.33#ibcon#*after write, iclass 19, count 0 2006.210.08:02:02.33#ibcon#*before return 0, iclass 19, count 0 2006.210.08:02:02.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:02:02.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:02:02.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:02:02.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:02:02.33$4f8m12a/ifd4f 2006.210.08:02:02.33$ifd4f/lo= 2006.210.08:02:02.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:02:02.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:02:02.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:02:02.33$ifd4f/patch= 2006.210.08:02:02.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:02:02.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:02:02.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:02:02.33$4f8m12a/"form=m,16.000,1:2 2006.210.08:02:02.33$4f8m12a/"tpicd 2006.210.08:02:02.33$4f8m12a/echo=off 2006.210.08:02:02.33$4f8m12a/xlog=off 2006.210.08:02:02.33:!2006.210.08:02:40 2006.210.08:02:20.14#trakl#Source acquired 2006.210.08:02:21.14#flagr#flagr/antenna,acquired 2006.210.08:02:40.00:preob 2006.210.08:02:40.14/onsource/TRACKING 2006.210.08:02:40.14:!2006.210.08:02:50 2006.210.08:02:50.00:data_valid=on 2006.210.08:02:50.00:midob 2006.210.08:02:51.14/onsource/TRACKING 2006.210.08:02:51.14/wx/30.44,1006.4,81 2006.210.08:02:51.31/cable/+6.3944E-03 2006.210.08:02:52.40/va/01,08,usb,yes,28,30 2006.210.08:02:52.40/va/02,07,usb,yes,28,30 2006.210.08:02:52.40/va/03,06,usb,yes,30,30 2006.210.08:02:52.40/va/04,07,usb,yes,29,31 2006.210.08:02:52.40/va/05,07,usb,yes,30,32 2006.210.08:02:52.40/va/06,06,usb,yes,29,29 2006.210.08:02:52.40/va/07,06,usb,yes,30,30 2006.210.08:02:52.40/va/08,07,usb,yes,28,28 2006.210.08:02:52.63/valo/01,532.99,yes,locked 2006.210.08:02:52.63/valo/02,572.99,yes,locked 2006.210.08:02:52.63/valo/03,672.99,yes,locked 2006.210.08:02:52.63/valo/04,832.99,yes,locked 2006.210.08:02:52.63/valo/05,652.99,yes,locked 2006.210.08:02:52.63/valo/06,772.99,yes,locked 2006.210.08:02:52.63/valo/07,832.99,yes,locked 2006.210.08:02:52.63/valo/08,852.99,yes,locked 2006.210.08:02:53.72/vb/01,04,usb,yes,28,27 2006.210.08:02:53.72/vb/02,04,usb,yes,30,31 2006.210.08:02:53.72/vb/03,03,usb,yes,33,37 2006.210.08:02:53.72/vb/04,03,usb,yes,34,34 2006.210.08:02:53.72/vb/05,03,usb,yes,32,36 2006.210.08:02:53.72/vb/06,03,usb,yes,33,36 2006.210.08:02:53.72/vb/07,04,usb,yes,28,28 2006.210.08:02:53.72/vb/08,03,usb,yes,33,36 2006.210.08:02:53.96/vblo/01,632.99,yes,locked 2006.210.08:02:53.96/vblo/02,640.99,yes,locked 2006.210.08:02:53.96/vblo/03,656.99,yes,locked 2006.210.08:02:53.96/vblo/04,712.99,yes,locked 2006.210.08:02:53.96/vblo/05,744.99,yes,locked 2006.210.08:02:53.96/vblo/06,752.99,yes,locked 2006.210.08:02:53.96/vblo/07,734.99,yes,locked 2006.210.08:02:53.96/vblo/08,744.99,yes,locked 2006.210.08:02:54.11/vabw/8 2006.210.08:02:54.26/vbbw/8 2006.210.08:02:54.35/xfe/off,on,13.7 2006.210.08:02:54.74/ifatt/23,28,28,28 2006.210.08:02:55.08/fmout-gps/S +4.64E-07 2006.210.08:02:55.12:!2006.210.08:03:50 2006.210.08:03:50.00:data_valid=off 2006.210.08:03:50.00:postob 2006.210.08:03:50.18/cable/+6.3922E-03 2006.210.08:03:50.18/wx/30.41,1006.4,81 2006.210.08:03:51.08/fmout-gps/S +4.63E-07 2006.210.08:03:51.08:scan_name=210-0804,k06210,60 2006.210.08:03:51.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.210.08:03:51.14#flagr#flagr/antenna,new-source 2006.210.08:03:52.14:checkk5 2006.210.08:03:52.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:03:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:03:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:03:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:03:53.84/chk_obsdata//k5ts1/T2100802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:03:54.17/chk_obsdata//k5ts2/T2100802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:03:54.51/chk_obsdata//k5ts3/T2100802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:03:54.84/chk_obsdata//k5ts4/T2100802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:03:55.51/k5log//k5ts1_log_newline 2006.210.08:03:56.17/k5log//k5ts2_log_newline 2006.210.08:03:56.82/k5log//k5ts3_log_newline 2006.210.08:03:57.47/k5log//k5ts4_log_newline 2006.210.08:03:57.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:03:57.50:4f8m12a=2 2006.210.08:03:57.50$4f8m12a/echo=on 2006.210.08:03:57.50$4f8m12a/pcalon 2006.210.08:03:57.50$pcalon/"no phase cal control is implemented here 2006.210.08:03:57.50$4f8m12a/"tpicd=stop 2006.210.08:03:57.50$4f8m12a/vc4f8 2006.210.08:03:57.50$vc4f8/valo=1,532.99 2006.210.08:03:57.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.08:03:57.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.08:03:57.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:57.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:03:57.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:03:57.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:03:57.50#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:03:57.50#ibcon#first serial, iclass 30, count 0 2006.210.08:03:57.50#ibcon#enter sib2, iclass 30, count 0 2006.210.08:03:57.50#ibcon#flushed, iclass 30, count 0 2006.210.08:03:57.50#ibcon#about to write, iclass 30, count 0 2006.210.08:03:57.50#ibcon#wrote, iclass 30, count 0 2006.210.08:03:57.50#ibcon#about to read 3, iclass 30, count 0 2006.210.08:03:57.52#ibcon#read 3, iclass 30, count 0 2006.210.08:03:57.52#ibcon#about to read 4, iclass 30, count 0 2006.210.08:03:57.52#ibcon#read 4, iclass 30, count 0 2006.210.08:03:57.52#ibcon#about to read 5, iclass 30, count 0 2006.210.08:03:57.52#ibcon#read 5, iclass 30, count 0 2006.210.08:03:57.52#ibcon#about to read 6, iclass 30, count 0 2006.210.08:03:57.52#ibcon#read 6, iclass 30, count 0 2006.210.08:03:57.52#ibcon#end of sib2, iclass 30, count 0 2006.210.08:03:57.52#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:03:57.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:03:57.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:03:57.52#ibcon#*before write, iclass 30, count 0 2006.210.08:03:57.52#ibcon#enter sib2, iclass 30, count 0 2006.210.08:03:57.52#ibcon#flushed, iclass 30, count 0 2006.210.08:03:57.52#ibcon#about to write, iclass 30, count 0 2006.210.08:03:57.52#ibcon#wrote, iclass 30, count 0 2006.210.08:03:57.52#ibcon#about to read 3, iclass 30, count 0 2006.210.08:03:57.57#ibcon#read 3, iclass 30, count 0 2006.210.08:03:57.57#ibcon#about to read 4, iclass 30, count 0 2006.210.08:03:57.57#ibcon#read 4, iclass 30, count 0 2006.210.08:03:57.57#ibcon#about to read 5, iclass 30, count 0 2006.210.08:03:57.57#ibcon#read 5, iclass 30, count 0 2006.210.08:03:57.57#ibcon#about to read 6, iclass 30, count 0 2006.210.08:03:57.57#ibcon#read 6, iclass 30, count 0 2006.210.08:03:57.57#ibcon#end of sib2, iclass 30, count 0 2006.210.08:03:57.57#ibcon#*after write, iclass 30, count 0 2006.210.08:03:57.57#ibcon#*before return 0, iclass 30, count 0 2006.210.08:03:57.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:03:57.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:03:57.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:03:57.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:03:57.57$vc4f8/va=1,8 2006.210.08:03:57.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.08:03:57.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.08:03:57.57#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:57.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:03:57.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:03:57.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:03:57.57#ibcon#enter wrdev, iclass 32, count 2 2006.210.08:03:57.57#ibcon#first serial, iclass 32, count 2 2006.210.08:03:57.57#ibcon#enter sib2, iclass 32, count 2 2006.210.08:03:57.57#ibcon#flushed, iclass 32, count 2 2006.210.08:03:57.57#ibcon#about to write, iclass 32, count 2 2006.210.08:03:57.57#ibcon#wrote, iclass 32, count 2 2006.210.08:03:57.57#ibcon#about to read 3, iclass 32, count 2 2006.210.08:03:57.59#ibcon#read 3, iclass 32, count 2 2006.210.08:03:57.59#ibcon#about to read 4, iclass 32, count 2 2006.210.08:03:57.59#ibcon#read 4, iclass 32, count 2 2006.210.08:03:57.59#ibcon#about to read 5, iclass 32, count 2 2006.210.08:03:57.59#ibcon#read 5, iclass 32, count 2 2006.210.08:03:57.59#ibcon#about to read 6, iclass 32, count 2 2006.210.08:03:57.59#ibcon#read 6, iclass 32, count 2 2006.210.08:03:57.59#ibcon#end of sib2, iclass 32, count 2 2006.210.08:03:57.59#ibcon#*mode == 0, iclass 32, count 2 2006.210.08:03:57.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.08:03:57.59#ibcon#[25=AT01-08\r\n] 2006.210.08:03:57.59#ibcon#*before write, iclass 32, count 2 2006.210.08:03:57.59#ibcon#enter sib2, iclass 32, count 2 2006.210.08:03:57.59#ibcon#flushed, iclass 32, count 2 2006.210.08:03:57.59#ibcon#about to write, iclass 32, count 2 2006.210.08:03:57.59#ibcon#wrote, iclass 32, count 2 2006.210.08:03:57.59#ibcon#about to read 3, iclass 32, count 2 2006.210.08:03:57.62#ibcon#read 3, iclass 32, count 2 2006.210.08:03:57.62#ibcon#about to read 4, iclass 32, count 2 2006.210.08:03:57.62#ibcon#read 4, iclass 32, count 2 2006.210.08:03:57.62#ibcon#about to read 5, iclass 32, count 2 2006.210.08:03:57.62#ibcon#read 5, iclass 32, count 2 2006.210.08:03:57.62#ibcon#about to read 6, iclass 32, count 2 2006.210.08:03:57.62#ibcon#read 6, iclass 32, count 2 2006.210.08:03:57.62#ibcon#end of sib2, iclass 32, count 2 2006.210.08:03:57.62#ibcon#*after write, iclass 32, count 2 2006.210.08:03:57.62#ibcon#*before return 0, iclass 32, count 2 2006.210.08:03:57.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:03:57.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:03:57.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.08:03:57.62#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:57.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:03:57.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:03:57.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:03:57.74#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:03:57.74#ibcon#first serial, iclass 32, count 0 2006.210.08:03:57.74#ibcon#enter sib2, iclass 32, count 0 2006.210.08:03:57.74#ibcon#flushed, iclass 32, count 0 2006.210.08:03:57.74#ibcon#about to write, iclass 32, count 0 2006.210.08:03:57.74#ibcon#wrote, iclass 32, count 0 2006.210.08:03:57.74#ibcon#about to read 3, iclass 32, count 0 2006.210.08:03:57.76#ibcon#read 3, iclass 32, count 0 2006.210.08:03:57.76#ibcon#about to read 4, iclass 32, count 0 2006.210.08:03:57.76#ibcon#read 4, iclass 32, count 0 2006.210.08:03:57.76#ibcon#about to read 5, iclass 32, count 0 2006.210.08:03:57.76#ibcon#read 5, iclass 32, count 0 2006.210.08:03:57.76#ibcon#about to read 6, iclass 32, count 0 2006.210.08:03:57.76#ibcon#read 6, iclass 32, count 0 2006.210.08:03:57.76#ibcon#end of sib2, iclass 32, count 0 2006.210.08:03:57.76#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:03:57.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:03:57.76#ibcon#[25=USB\r\n] 2006.210.08:03:57.76#ibcon#*before write, iclass 32, count 0 2006.210.08:03:57.76#ibcon#enter sib2, iclass 32, count 0 2006.210.08:03:57.76#ibcon#flushed, iclass 32, count 0 2006.210.08:03:57.76#ibcon#about to write, iclass 32, count 0 2006.210.08:03:57.76#ibcon#wrote, iclass 32, count 0 2006.210.08:03:57.76#ibcon#about to read 3, iclass 32, count 0 2006.210.08:03:57.79#ibcon#read 3, iclass 32, count 0 2006.210.08:03:57.79#ibcon#about to read 4, iclass 32, count 0 2006.210.08:03:57.79#ibcon#read 4, iclass 32, count 0 2006.210.08:03:57.79#ibcon#about to read 5, iclass 32, count 0 2006.210.08:03:57.79#ibcon#read 5, iclass 32, count 0 2006.210.08:03:57.79#ibcon#about to read 6, iclass 32, count 0 2006.210.08:03:57.79#ibcon#read 6, iclass 32, count 0 2006.210.08:03:57.79#ibcon#end of sib2, iclass 32, count 0 2006.210.08:03:57.79#ibcon#*after write, iclass 32, count 0 2006.210.08:03:57.79#ibcon#*before return 0, iclass 32, count 0 2006.210.08:03:57.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:03:57.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:03:57.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:03:57.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:03:57.79$vc4f8/valo=2,572.99 2006.210.08:03:57.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:03:57.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:03:57.79#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:57.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:03:57.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:03:57.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:03:57.79#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:03:57.79#ibcon#first serial, iclass 34, count 0 2006.210.08:03:57.79#ibcon#enter sib2, iclass 34, count 0 2006.210.08:03:57.79#ibcon#flushed, iclass 34, count 0 2006.210.08:03:57.79#ibcon#about to write, iclass 34, count 0 2006.210.08:03:57.79#ibcon#wrote, iclass 34, count 0 2006.210.08:03:57.79#ibcon#about to read 3, iclass 34, count 0 2006.210.08:03:57.81#ibcon#read 3, iclass 34, count 0 2006.210.08:03:57.81#ibcon#about to read 4, iclass 34, count 0 2006.210.08:03:57.81#ibcon#read 4, iclass 34, count 0 2006.210.08:03:57.81#ibcon#about to read 5, iclass 34, count 0 2006.210.08:03:57.81#ibcon#read 5, iclass 34, count 0 2006.210.08:03:57.81#ibcon#about to read 6, iclass 34, count 0 2006.210.08:03:57.81#ibcon#read 6, iclass 34, count 0 2006.210.08:03:57.81#ibcon#end of sib2, iclass 34, count 0 2006.210.08:03:57.81#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:03:57.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:03:57.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:03:57.81#ibcon#*before write, iclass 34, count 0 2006.210.08:03:57.81#ibcon#enter sib2, iclass 34, count 0 2006.210.08:03:57.81#ibcon#flushed, iclass 34, count 0 2006.210.08:03:57.81#ibcon#about to write, iclass 34, count 0 2006.210.08:03:57.81#ibcon#wrote, iclass 34, count 0 2006.210.08:03:57.81#ibcon#about to read 3, iclass 34, count 0 2006.210.08:03:57.85#ibcon#read 3, iclass 34, count 0 2006.210.08:03:57.85#ibcon#about to read 4, iclass 34, count 0 2006.210.08:03:57.85#ibcon#read 4, iclass 34, count 0 2006.210.08:03:57.85#ibcon#about to read 5, iclass 34, count 0 2006.210.08:03:57.85#ibcon#read 5, iclass 34, count 0 2006.210.08:03:57.85#ibcon#about to read 6, iclass 34, count 0 2006.210.08:03:57.85#ibcon#read 6, iclass 34, count 0 2006.210.08:03:57.85#ibcon#end of sib2, iclass 34, count 0 2006.210.08:03:57.85#ibcon#*after write, iclass 34, count 0 2006.210.08:03:57.85#ibcon#*before return 0, iclass 34, count 0 2006.210.08:03:57.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:03:57.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:03:57.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:03:57.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:03:57.85$vc4f8/va=2,7 2006.210.08:03:57.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.08:03:57.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.08:03:57.85#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:57.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:03:57.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:03:57.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:03:57.91#ibcon#enter wrdev, iclass 36, count 2 2006.210.08:03:57.91#ibcon#first serial, iclass 36, count 2 2006.210.08:03:57.91#ibcon#enter sib2, iclass 36, count 2 2006.210.08:03:57.91#ibcon#flushed, iclass 36, count 2 2006.210.08:03:57.91#ibcon#about to write, iclass 36, count 2 2006.210.08:03:57.91#ibcon#wrote, iclass 36, count 2 2006.210.08:03:57.91#ibcon#about to read 3, iclass 36, count 2 2006.210.08:03:57.93#ibcon#read 3, iclass 36, count 2 2006.210.08:03:57.93#ibcon#about to read 4, iclass 36, count 2 2006.210.08:03:57.93#ibcon#read 4, iclass 36, count 2 2006.210.08:03:57.93#ibcon#about to read 5, iclass 36, count 2 2006.210.08:03:57.93#ibcon#read 5, iclass 36, count 2 2006.210.08:03:57.93#ibcon#about to read 6, iclass 36, count 2 2006.210.08:03:57.93#ibcon#read 6, iclass 36, count 2 2006.210.08:03:57.93#ibcon#end of sib2, iclass 36, count 2 2006.210.08:03:57.93#ibcon#*mode == 0, iclass 36, count 2 2006.210.08:03:57.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.08:03:57.93#ibcon#[25=AT02-07\r\n] 2006.210.08:03:57.93#ibcon#*before write, iclass 36, count 2 2006.210.08:03:57.93#ibcon#enter sib2, iclass 36, count 2 2006.210.08:03:57.93#ibcon#flushed, iclass 36, count 2 2006.210.08:03:57.93#ibcon#about to write, iclass 36, count 2 2006.210.08:03:57.93#ibcon#wrote, iclass 36, count 2 2006.210.08:03:57.93#ibcon#about to read 3, iclass 36, count 2 2006.210.08:03:57.96#ibcon#read 3, iclass 36, count 2 2006.210.08:03:57.96#ibcon#about to read 4, iclass 36, count 2 2006.210.08:03:57.96#ibcon#read 4, iclass 36, count 2 2006.210.08:03:57.96#ibcon#about to read 5, iclass 36, count 2 2006.210.08:03:57.96#ibcon#read 5, iclass 36, count 2 2006.210.08:03:57.96#ibcon#about to read 6, iclass 36, count 2 2006.210.08:03:57.96#ibcon#read 6, iclass 36, count 2 2006.210.08:03:57.96#ibcon#end of sib2, iclass 36, count 2 2006.210.08:03:57.96#ibcon#*after write, iclass 36, count 2 2006.210.08:03:57.96#ibcon#*before return 0, iclass 36, count 2 2006.210.08:03:57.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:03:57.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:03:57.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.08:03:57.96#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:57.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:03:58.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:03:58.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:03:58.08#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:03:58.08#ibcon#first serial, iclass 36, count 0 2006.210.08:03:58.08#ibcon#enter sib2, iclass 36, count 0 2006.210.08:03:58.08#ibcon#flushed, iclass 36, count 0 2006.210.08:03:58.08#ibcon#about to write, iclass 36, count 0 2006.210.08:03:58.08#ibcon#wrote, iclass 36, count 0 2006.210.08:03:58.08#ibcon#about to read 3, iclass 36, count 0 2006.210.08:03:58.10#ibcon#read 3, iclass 36, count 0 2006.210.08:03:58.10#ibcon#about to read 4, iclass 36, count 0 2006.210.08:03:58.10#ibcon#read 4, iclass 36, count 0 2006.210.08:03:58.10#ibcon#about to read 5, iclass 36, count 0 2006.210.08:03:58.10#ibcon#read 5, iclass 36, count 0 2006.210.08:03:58.10#ibcon#about to read 6, iclass 36, count 0 2006.210.08:03:58.10#ibcon#read 6, iclass 36, count 0 2006.210.08:03:58.10#ibcon#end of sib2, iclass 36, count 0 2006.210.08:03:58.10#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:03:58.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:03:58.10#ibcon#[25=USB\r\n] 2006.210.08:03:58.10#ibcon#*before write, iclass 36, count 0 2006.210.08:03:58.10#ibcon#enter sib2, iclass 36, count 0 2006.210.08:03:58.10#ibcon#flushed, iclass 36, count 0 2006.210.08:03:58.10#ibcon#about to write, iclass 36, count 0 2006.210.08:03:58.10#ibcon#wrote, iclass 36, count 0 2006.210.08:03:58.10#ibcon#about to read 3, iclass 36, count 0 2006.210.08:03:58.13#ibcon#read 3, iclass 36, count 0 2006.210.08:03:58.13#ibcon#about to read 4, iclass 36, count 0 2006.210.08:03:58.13#ibcon#read 4, iclass 36, count 0 2006.210.08:03:58.13#ibcon#about to read 5, iclass 36, count 0 2006.210.08:03:58.13#ibcon#read 5, iclass 36, count 0 2006.210.08:03:58.13#ibcon#about to read 6, iclass 36, count 0 2006.210.08:03:58.13#ibcon#read 6, iclass 36, count 0 2006.210.08:03:58.13#ibcon#end of sib2, iclass 36, count 0 2006.210.08:03:58.13#ibcon#*after write, iclass 36, count 0 2006.210.08:03:58.13#ibcon#*before return 0, iclass 36, count 0 2006.210.08:03:58.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:03:58.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:03:58.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:03:58.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:03:58.13$vc4f8/valo=3,672.99 2006.210.08:03:58.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.08:03:58.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.08:03:58.13#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:58.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:03:58.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:03:58.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:03:58.13#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:03:58.13#ibcon#first serial, iclass 38, count 0 2006.210.08:03:58.13#ibcon#enter sib2, iclass 38, count 0 2006.210.08:03:58.13#ibcon#flushed, iclass 38, count 0 2006.210.08:03:58.13#ibcon#about to write, iclass 38, count 0 2006.210.08:03:58.13#ibcon#wrote, iclass 38, count 0 2006.210.08:03:58.13#ibcon#about to read 3, iclass 38, count 0 2006.210.08:03:58.15#ibcon#read 3, iclass 38, count 0 2006.210.08:03:58.15#ibcon#about to read 4, iclass 38, count 0 2006.210.08:03:58.15#ibcon#read 4, iclass 38, count 0 2006.210.08:03:58.15#ibcon#about to read 5, iclass 38, count 0 2006.210.08:03:58.15#ibcon#read 5, iclass 38, count 0 2006.210.08:03:58.15#ibcon#about to read 6, iclass 38, count 0 2006.210.08:03:58.15#ibcon#read 6, iclass 38, count 0 2006.210.08:03:58.15#ibcon#end of sib2, iclass 38, count 0 2006.210.08:03:58.15#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:03:58.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:03:58.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:03:58.15#ibcon#*before write, iclass 38, count 0 2006.210.08:03:58.15#ibcon#enter sib2, iclass 38, count 0 2006.210.08:03:58.15#ibcon#flushed, iclass 38, count 0 2006.210.08:03:58.15#ibcon#about to write, iclass 38, count 0 2006.210.08:03:58.15#ibcon#wrote, iclass 38, count 0 2006.210.08:03:58.15#ibcon#about to read 3, iclass 38, count 0 2006.210.08:03:58.19#ibcon#read 3, iclass 38, count 0 2006.210.08:03:58.19#ibcon#about to read 4, iclass 38, count 0 2006.210.08:03:58.19#ibcon#read 4, iclass 38, count 0 2006.210.08:03:58.19#ibcon#about to read 5, iclass 38, count 0 2006.210.08:03:58.19#ibcon#read 5, iclass 38, count 0 2006.210.08:03:58.19#ibcon#about to read 6, iclass 38, count 0 2006.210.08:03:58.19#ibcon#read 6, iclass 38, count 0 2006.210.08:03:58.19#ibcon#end of sib2, iclass 38, count 0 2006.210.08:03:58.19#ibcon#*after write, iclass 38, count 0 2006.210.08:03:58.19#ibcon#*before return 0, iclass 38, count 0 2006.210.08:03:58.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:03:58.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:03:58.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:03:58.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:03:58.19$vc4f8/va=3,6 2006.210.08:03:58.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.08:03:58.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.08:03:58.19#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:58.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:03:58.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:03:58.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:03:58.25#ibcon#enter wrdev, iclass 40, count 2 2006.210.08:03:58.25#ibcon#first serial, iclass 40, count 2 2006.210.08:03:58.25#ibcon#enter sib2, iclass 40, count 2 2006.210.08:03:58.25#ibcon#flushed, iclass 40, count 2 2006.210.08:03:58.25#ibcon#about to write, iclass 40, count 2 2006.210.08:03:58.25#ibcon#wrote, iclass 40, count 2 2006.210.08:03:58.25#ibcon#about to read 3, iclass 40, count 2 2006.210.08:03:58.27#ibcon#read 3, iclass 40, count 2 2006.210.08:03:58.27#ibcon#about to read 4, iclass 40, count 2 2006.210.08:03:58.27#ibcon#read 4, iclass 40, count 2 2006.210.08:03:58.27#ibcon#about to read 5, iclass 40, count 2 2006.210.08:03:58.27#ibcon#read 5, iclass 40, count 2 2006.210.08:03:58.27#ibcon#about to read 6, iclass 40, count 2 2006.210.08:03:58.27#ibcon#read 6, iclass 40, count 2 2006.210.08:03:58.27#ibcon#end of sib2, iclass 40, count 2 2006.210.08:03:58.27#ibcon#*mode == 0, iclass 40, count 2 2006.210.08:03:58.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.08:03:58.27#ibcon#[25=AT03-06\r\n] 2006.210.08:03:58.27#ibcon#*before write, iclass 40, count 2 2006.210.08:03:58.27#ibcon#enter sib2, iclass 40, count 2 2006.210.08:03:58.27#ibcon#flushed, iclass 40, count 2 2006.210.08:03:58.27#ibcon#about to write, iclass 40, count 2 2006.210.08:03:58.27#ibcon#wrote, iclass 40, count 2 2006.210.08:03:58.27#ibcon#about to read 3, iclass 40, count 2 2006.210.08:03:58.30#ibcon#read 3, iclass 40, count 2 2006.210.08:03:58.30#ibcon#about to read 4, iclass 40, count 2 2006.210.08:03:58.30#ibcon#read 4, iclass 40, count 2 2006.210.08:03:58.30#ibcon#about to read 5, iclass 40, count 2 2006.210.08:03:58.30#ibcon#read 5, iclass 40, count 2 2006.210.08:03:58.30#ibcon#about to read 6, iclass 40, count 2 2006.210.08:03:58.30#ibcon#read 6, iclass 40, count 2 2006.210.08:03:58.30#ibcon#end of sib2, iclass 40, count 2 2006.210.08:03:58.30#ibcon#*after write, iclass 40, count 2 2006.210.08:03:58.30#ibcon#*before return 0, iclass 40, count 2 2006.210.08:03:58.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:03:58.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:03:58.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.08:03:58.30#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:58.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:03:58.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:03:58.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:03:58.42#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:03:58.42#ibcon#first serial, iclass 40, count 0 2006.210.08:03:58.42#ibcon#enter sib2, iclass 40, count 0 2006.210.08:03:58.42#ibcon#flushed, iclass 40, count 0 2006.210.08:03:58.42#ibcon#about to write, iclass 40, count 0 2006.210.08:03:58.42#ibcon#wrote, iclass 40, count 0 2006.210.08:03:58.42#ibcon#about to read 3, iclass 40, count 0 2006.210.08:03:58.44#ibcon#read 3, iclass 40, count 0 2006.210.08:03:58.44#ibcon#about to read 4, iclass 40, count 0 2006.210.08:03:58.44#ibcon#read 4, iclass 40, count 0 2006.210.08:03:58.44#ibcon#about to read 5, iclass 40, count 0 2006.210.08:03:58.44#ibcon#read 5, iclass 40, count 0 2006.210.08:03:58.44#ibcon#about to read 6, iclass 40, count 0 2006.210.08:03:58.44#ibcon#read 6, iclass 40, count 0 2006.210.08:03:58.44#ibcon#end of sib2, iclass 40, count 0 2006.210.08:03:58.44#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:03:58.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:03:58.44#ibcon#[25=USB\r\n] 2006.210.08:03:58.44#ibcon#*before write, iclass 40, count 0 2006.210.08:03:58.44#ibcon#enter sib2, iclass 40, count 0 2006.210.08:03:58.44#ibcon#flushed, iclass 40, count 0 2006.210.08:03:58.44#ibcon#about to write, iclass 40, count 0 2006.210.08:03:58.44#ibcon#wrote, iclass 40, count 0 2006.210.08:03:58.44#ibcon#about to read 3, iclass 40, count 0 2006.210.08:03:58.47#ibcon#read 3, iclass 40, count 0 2006.210.08:03:58.47#ibcon#about to read 4, iclass 40, count 0 2006.210.08:03:58.47#ibcon#read 4, iclass 40, count 0 2006.210.08:03:58.47#ibcon#about to read 5, iclass 40, count 0 2006.210.08:03:58.47#ibcon#read 5, iclass 40, count 0 2006.210.08:03:58.47#ibcon#about to read 6, iclass 40, count 0 2006.210.08:03:58.47#ibcon#read 6, iclass 40, count 0 2006.210.08:03:58.47#ibcon#end of sib2, iclass 40, count 0 2006.210.08:03:58.47#ibcon#*after write, iclass 40, count 0 2006.210.08:03:58.47#ibcon#*before return 0, iclass 40, count 0 2006.210.08:03:58.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:03:58.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:03:58.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:03:58.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:03:58.47$vc4f8/valo=4,832.99 2006.210.08:03:58.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.08:03:58.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.08:03:58.47#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:58.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:03:58.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:03:58.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:03:58.47#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:03:58.47#ibcon#first serial, iclass 4, count 0 2006.210.08:03:58.47#ibcon#enter sib2, iclass 4, count 0 2006.210.08:03:58.47#ibcon#flushed, iclass 4, count 0 2006.210.08:03:58.47#ibcon#about to write, iclass 4, count 0 2006.210.08:03:58.47#ibcon#wrote, iclass 4, count 0 2006.210.08:03:58.47#ibcon#about to read 3, iclass 4, count 0 2006.210.08:03:58.49#ibcon#read 3, iclass 4, count 0 2006.210.08:03:58.49#ibcon#about to read 4, iclass 4, count 0 2006.210.08:03:58.49#ibcon#read 4, iclass 4, count 0 2006.210.08:03:58.49#ibcon#about to read 5, iclass 4, count 0 2006.210.08:03:58.49#ibcon#read 5, iclass 4, count 0 2006.210.08:03:58.49#ibcon#about to read 6, iclass 4, count 0 2006.210.08:03:58.49#ibcon#read 6, iclass 4, count 0 2006.210.08:03:58.49#ibcon#end of sib2, iclass 4, count 0 2006.210.08:03:58.49#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:03:58.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:03:58.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:03:58.49#ibcon#*before write, iclass 4, count 0 2006.210.08:03:58.49#ibcon#enter sib2, iclass 4, count 0 2006.210.08:03:58.49#ibcon#flushed, iclass 4, count 0 2006.210.08:03:58.49#ibcon#about to write, iclass 4, count 0 2006.210.08:03:58.49#ibcon#wrote, iclass 4, count 0 2006.210.08:03:58.49#ibcon#about to read 3, iclass 4, count 0 2006.210.08:03:58.53#ibcon#read 3, iclass 4, count 0 2006.210.08:03:58.53#ibcon#about to read 4, iclass 4, count 0 2006.210.08:03:58.53#ibcon#read 4, iclass 4, count 0 2006.210.08:03:58.53#ibcon#about to read 5, iclass 4, count 0 2006.210.08:03:58.53#ibcon#read 5, iclass 4, count 0 2006.210.08:03:58.53#ibcon#about to read 6, iclass 4, count 0 2006.210.08:03:58.53#ibcon#read 6, iclass 4, count 0 2006.210.08:03:58.53#ibcon#end of sib2, iclass 4, count 0 2006.210.08:03:58.53#ibcon#*after write, iclass 4, count 0 2006.210.08:03:58.53#ibcon#*before return 0, iclass 4, count 0 2006.210.08:03:58.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:03:58.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:03:58.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:03:58.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:03:58.53$vc4f8/va=4,7 2006.210.08:03:58.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.08:03:58.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.08:03:58.53#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:58.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:03:58.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:03:58.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:03:58.59#ibcon#enter wrdev, iclass 6, count 2 2006.210.08:03:58.59#ibcon#first serial, iclass 6, count 2 2006.210.08:03:58.59#ibcon#enter sib2, iclass 6, count 2 2006.210.08:03:58.59#ibcon#flushed, iclass 6, count 2 2006.210.08:03:58.59#ibcon#about to write, iclass 6, count 2 2006.210.08:03:58.59#ibcon#wrote, iclass 6, count 2 2006.210.08:03:58.59#ibcon#about to read 3, iclass 6, count 2 2006.210.08:03:58.61#ibcon#read 3, iclass 6, count 2 2006.210.08:03:58.61#ibcon#about to read 4, iclass 6, count 2 2006.210.08:03:58.61#ibcon#read 4, iclass 6, count 2 2006.210.08:03:58.61#ibcon#about to read 5, iclass 6, count 2 2006.210.08:03:58.61#ibcon#read 5, iclass 6, count 2 2006.210.08:03:58.61#ibcon#about to read 6, iclass 6, count 2 2006.210.08:03:58.61#ibcon#read 6, iclass 6, count 2 2006.210.08:03:58.61#ibcon#end of sib2, iclass 6, count 2 2006.210.08:03:58.61#ibcon#*mode == 0, iclass 6, count 2 2006.210.08:03:58.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.08:03:58.61#ibcon#[25=AT04-07\r\n] 2006.210.08:03:58.61#ibcon#*before write, iclass 6, count 2 2006.210.08:03:58.61#ibcon#enter sib2, iclass 6, count 2 2006.210.08:03:58.61#ibcon#flushed, iclass 6, count 2 2006.210.08:03:58.61#ibcon#about to write, iclass 6, count 2 2006.210.08:03:58.61#ibcon#wrote, iclass 6, count 2 2006.210.08:03:58.61#ibcon#about to read 3, iclass 6, count 2 2006.210.08:03:58.64#ibcon#read 3, iclass 6, count 2 2006.210.08:03:58.64#ibcon#about to read 4, iclass 6, count 2 2006.210.08:03:58.64#ibcon#read 4, iclass 6, count 2 2006.210.08:03:58.64#ibcon#about to read 5, iclass 6, count 2 2006.210.08:03:58.64#ibcon#read 5, iclass 6, count 2 2006.210.08:03:58.64#ibcon#about to read 6, iclass 6, count 2 2006.210.08:03:58.64#ibcon#read 6, iclass 6, count 2 2006.210.08:03:58.64#ibcon#end of sib2, iclass 6, count 2 2006.210.08:03:58.64#ibcon#*after write, iclass 6, count 2 2006.210.08:03:58.64#ibcon#*before return 0, iclass 6, count 2 2006.210.08:03:58.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:03:58.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:03:58.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.08:03:58.64#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:58.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:03:58.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:03:58.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:03:58.76#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:03:58.76#ibcon#first serial, iclass 6, count 0 2006.210.08:03:58.76#ibcon#enter sib2, iclass 6, count 0 2006.210.08:03:58.76#ibcon#flushed, iclass 6, count 0 2006.210.08:03:58.76#ibcon#about to write, iclass 6, count 0 2006.210.08:03:58.76#ibcon#wrote, iclass 6, count 0 2006.210.08:03:58.76#ibcon#about to read 3, iclass 6, count 0 2006.210.08:03:58.78#ibcon#read 3, iclass 6, count 0 2006.210.08:03:58.78#ibcon#about to read 4, iclass 6, count 0 2006.210.08:03:58.78#ibcon#read 4, iclass 6, count 0 2006.210.08:03:58.78#ibcon#about to read 5, iclass 6, count 0 2006.210.08:03:58.78#ibcon#read 5, iclass 6, count 0 2006.210.08:03:58.78#ibcon#about to read 6, iclass 6, count 0 2006.210.08:03:58.78#ibcon#read 6, iclass 6, count 0 2006.210.08:03:58.78#ibcon#end of sib2, iclass 6, count 0 2006.210.08:03:58.78#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:03:58.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:03:58.78#ibcon#[25=USB\r\n] 2006.210.08:03:58.78#ibcon#*before write, iclass 6, count 0 2006.210.08:03:58.78#ibcon#enter sib2, iclass 6, count 0 2006.210.08:03:58.78#ibcon#flushed, iclass 6, count 0 2006.210.08:03:58.78#ibcon#about to write, iclass 6, count 0 2006.210.08:03:58.78#ibcon#wrote, iclass 6, count 0 2006.210.08:03:58.78#ibcon#about to read 3, iclass 6, count 0 2006.210.08:03:58.81#ibcon#read 3, iclass 6, count 0 2006.210.08:03:58.81#ibcon#about to read 4, iclass 6, count 0 2006.210.08:03:58.81#ibcon#read 4, iclass 6, count 0 2006.210.08:03:58.81#ibcon#about to read 5, iclass 6, count 0 2006.210.08:03:58.81#ibcon#read 5, iclass 6, count 0 2006.210.08:03:58.81#ibcon#about to read 6, iclass 6, count 0 2006.210.08:03:58.81#ibcon#read 6, iclass 6, count 0 2006.210.08:03:58.81#ibcon#end of sib2, iclass 6, count 0 2006.210.08:03:58.81#ibcon#*after write, iclass 6, count 0 2006.210.08:03:58.81#ibcon#*before return 0, iclass 6, count 0 2006.210.08:03:58.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:03:58.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:03:58.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:03:58.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:03:58.81$vc4f8/valo=5,652.99 2006.210.08:03:58.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.08:03:58.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.08:03:58.81#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:58.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:03:58.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:03:58.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:03:58.81#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:03:58.81#ibcon#first serial, iclass 10, count 0 2006.210.08:03:58.81#ibcon#enter sib2, iclass 10, count 0 2006.210.08:03:58.81#ibcon#flushed, iclass 10, count 0 2006.210.08:03:58.81#ibcon#about to write, iclass 10, count 0 2006.210.08:03:58.81#ibcon#wrote, iclass 10, count 0 2006.210.08:03:58.81#ibcon#about to read 3, iclass 10, count 0 2006.210.08:03:58.83#ibcon#read 3, iclass 10, count 0 2006.210.08:03:58.83#ibcon#about to read 4, iclass 10, count 0 2006.210.08:03:58.83#ibcon#read 4, iclass 10, count 0 2006.210.08:03:58.83#ibcon#about to read 5, iclass 10, count 0 2006.210.08:03:58.83#ibcon#read 5, iclass 10, count 0 2006.210.08:03:58.83#ibcon#about to read 6, iclass 10, count 0 2006.210.08:03:58.83#ibcon#read 6, iclass 10, count 0 2006.210.08:03:58.83#ibcon#end of sib2, iclass 10, count 0 2006.210.08:03:58.83#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:03:58.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:03:58.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:03:58.83#ibcon#*before write, iclass 10, count 0 2006.210.08:03:58.83#ibcon#enter sib2, iclass 10, count 0 2006.210.08:03:58.83#ibcon#flushed, iclass 10, count 0 2006.210.08:03:58.83#ibcon#about to write, iclass 10, count 0 2006.210.08:03:58.83#ibcon#wrote, iclass 10, count 0 2006.210.08:03:58.83#ibcon#about to read 3, iclass 10, count 0 2006.210.08:03:58.87#ibcon#read 3, iclass 10, count 0 2006.210.08:03:58.87#ibcon#about to read 4, iclass 10, count 0 2006.210.08:03:58.87#ibcon#read 4, iclass 10, count 0 2006.210.08:03:58.87#ibcon#about to read 5, iclass 10, count 0 2006.210.08:03:58.87#ibcon#read 5, iclass 10, count 0 2006.210.08:03:58.87#ibcon#about to read 6, iclass 10, count 0 2006.210.08:03:58.87#ibcon#read 6, iclass 10, count 0 2006.210.08:03:58.87#ibcon#end of sib2, iclass 10, count 0 2006.210.08:03:58.87#ibcon#*after write, iclass 10, count 0 2006.210.08:03:58.87#ibcon#*before return 0, iclass 10, count 0 2006.210.08:03:58.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:03:58.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:03:58.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:03:58.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:03:58.87$vc4f8/va=5,7 2006.210.08:03:58.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.08:03:58.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.08:03:58.87#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:58.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:03:58.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:03:58.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:03:58.93#ibcon#enter wrdev, iclass 12, count 2 2006.210.08:03:58.93#ibcon#first serial, iclass 12, count 2 2006.210.08:03:58.93#ibcon#enter sib2, iclass 12, count 2 2006.210.08:03:58.93#ibcon#flushed, iclass 12, count 2 2006.210.08:03:58.93#ibcon#about to write, iclass 12, count 2 2006.210.08:03:58.93#ibcon#wrote, iclass 12, count 2 2006.210.08:03:58.93#ibcon#about to read 3, iclass 12, count 2 2006.210.08:03:58.95#ibcon#read 3, iclass 12, count 2 2006.210.08:03:58.95#ibcon#about to read 4, iclass 12, count 2 2006.210.08:03:58.95#ibcon#read 4, iclass 12, count 2 2006.210.08:03:58.95#ibcon#about to read 5, iclass 12, count 2 2006.210.08:03:58.95#ibcon#read 5, iclass 12, count 2 2006.210.08:03:58.95#ibcon#about to read 6, iclass 12, count 2 2006.210.08:03:58.95#ibcon#read 6, iclass 12, count 2 2006.210.08:03:58.95#ibcon#end of sib2, iclass 12, count 2 2006.210.08:03:58.95#ibcon#*mode == 0, iclass 12, count 2 2006.210.08:03:58.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.08:03:58.95#ibcon#[25=AT05-07\r\n] 2006.210.08:03:58.95#ibcon#*before write, iclass 12, count 2 2006.210.08:03:58.95#ibcon#enter sib2, iclass 12, count 2 2006.210.08:03:58.95#ibcon#flushed, iclass 12, count 2 2006.210.08:03:58.95#ibcon#about to write, iclass 12, count 2 2006.210.08:03:58.95#ibcon#wrote, iclass 12, count 2 2006.210.08:03:58.95#ibcon#about to read 3, iclass 12, count 2 2006.210.08:03:58.98#ibcon#read 3, iclass 12, count 2 2006.210.08:03:58.98#ibcon#about to read 4, iclass 12, count 2 2006.210.08:03:58.98#ibcon#read 4, iclass 12, count 2 2006.210.08:03:58.98#ibcon#about to read 5, iclass 12, count 2 2006.210.08:03:58.98#ibcon#read 5, iclass 12, count 2 2006.210.08:03:58.98#ibcon#about to read 6, iclass 12, count 2 2006.210.08:03:58.98#ibcon#read 6, iclass 12, count 2 2006.210.08:03:58.98#ibcon#end of sib2, iclass 12, count 2 2006.210.08:03:58.98#ibcon#*after write, iclass 12, count 2 2006.210.08:03:58.98#ibcon#*before return 0, iclass 12, count 2 2006.210.08:03:58.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:03:58.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:03:58.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.08:03:58.98#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:58.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:03:59.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:03:59.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:03:59.10#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:03:59.10#ibcon#first serial, iclass 12, count 0 2006.210.08:03:59.10#ibcon#enter sib2, iclass 12, count 0 2006.210.08:03:59.10#ibcon#flushed, iclass 12, count 0 2006.210.08:03:59.10#ibcon#about to write, iclass 12, count 0 2006.210.08:03:59.10#ibcon#wrote, iclass 12, count 0 2006.210.08:03:59.10#ibcon#about to read 3, iclass 12, count 0 2006.210.08:03:59.12#ibcon#read 3, iclass 12, count 0 2006.210.08:03:59.12#ibcon#about to read 4, iclass 12, count 0 2006.210.08:03:59.12#ibcon#read 4, iclass 12, count 0 2006.210.08:03:59.12#ibcon#about to read 5, iclass 12, count 0 2006.210.08:03:59.12#ibcon#read 5, iclass 12, count 0 2006.210.08:03:59.12#ibcon#about to read 6, iclass 12, count 0 2006.210.08:03:59.12#ibcon#read 6, iclass 12, count 0 2006.210.08:03:59.12#ibcon#end of sib2, iclass 12, count 0 2006.210.08:03:59.12#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:03:59.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:03:59.12#ibcon#[25=USB\r\n] 2006.210.08:03:59.12#ibcon#*before write, iclass 12, count 0 2006.210.08:03:59.12#ibcon#enter sib2, iclass 12, count 0 2006.210.08:03:59.12#ibcon#flushed, iclass 12, count 0 2006.210.08:03:59.12#ibcon#about to write, iclass 12, count 0 2006.210.08:03:59.12#ibcon#wrote, iclass 12, count 0 2006.210.08:03:59.12#ibcon#about to read 3, iclass 12, count 0 2006.210.08:03:59.15#ibcon#read 3, iclass 12, count 0 2006.210.08:03:59.15#ibcon#about to read 4, iclass 12, count 0 2006.210.08:03:59.15#ibcon#read 4, iclass 12, count 0 2006.210.08:03:59.15#ibcon#about to read 5, iclass 12, count 0 2006.210.08:03:59.15#ibcon#read 5, iclass 12, count 0 2006.210.08:03:59.15#ibcon#about to read 6, iclass 12, count 0 2006.210.08:03:59.15#ibcon#read 6, iclass 12, count 0 2006.210.08:03:59.15#ibcon#end of sib2, iclass 12, count 0 2006.210.08:03:59.15#ibcon#*after write, iclass 12, count 0 2006.210.08:03:59.15#ibcon#*before return 0, iclass 12, count 0 2006.210.08:03:59.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:03:59.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:03:59.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:03:59.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:03:59.15$vc4f8/valo=6,772.99 2006.210.08:03:59.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.08:03:59.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.08:03:59.15#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:59.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:03:59.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:03:59.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:03:59.15#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:03:59.15#ibcon#first serial, iclass 14, count 0 2006.210.08:03:59.15#ibcon#enter sib2, iclass 14, count 0 2006.210.08:03:59.15#ibcon#flushed, iclass 14, count 0 2006.210.08:03:59.15#ibcon#about to write, iclass 14, count 0 2006.210.08:03:59.15#ibcon#wrote, iclass 14, count 0 2006.210.08:03:59.15#ibcon#about to read 3, iclass 14, count 0 2006.210.08:03:59.17#ibcon#read 3, iclass 14, count 0 2006.210.08:03:59.17#ibcon#about to read 4, iclass 14, count 0 2006.210.08:03:59.17#ibcon#read 4, iclass 14, count 0 2006.210.08:03:59.17#ibcon#about to read 5, iclass 14, count 0 2006.210.08:03:59.17#ibcon#read 5, iclass 14, count 0 2006.210.08:03:59.17#ibcon#about to read 6, iclass 14, count 0 2006.210.08:03:59.17#ibcon#read 6, iclass 14, count 0 2006.210.08:03:59.17#ibcon#end of sib2, iclass 14, count 0 2006.210.08:03:59.17#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:03:59.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:03:59.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:03:59.17#ibcon#*before write, iclass 14, count 0 2006.210.08:03:59.17#ibcon#enter sib2, iclass 14, count 0 2006.210.08:03:59.17#ibcon#flushed, iclass 14, count 0 2006.210.08:03:59.17#ibcon#about to write, iclass 14, count 0 2006.210.08:03:59.17#ibcon#wrote, iclass 14, count 0 2006.210.08:03:59.17#ibcon#about to read 3, iclass 14, count 0 2006.210.08:03:59.21#ibcon#read 3, iclass 14, count 0 2006.210.08:03:59.21#ibcon#about to read 4, iclass 14, count 0 2006.210.08:03:59.21#ibcon#read 4, iclass 14, count 0 2006.210.08:03:59.21#ibcon#about to read 5, iclass 14, count 0 2006.210.08:03:59.21#ibcon#read 5, iclass 14, count 0 2006.210.08:03:59.21#ibcon#about to read 6, iclass 14, count 0 2006.210.08:03:59.21#ibcon#read 6, iclass 14, count 0 2006.210.08:03:59.21#ibcon#end of sib2, iclass 14, count 0 2006.210.08:03:59.21#ibcon#*after write, iclass 14, count 0 2006.210.08:03:59.21#ibcon#*before return 0, iclass 14, count 0 2006.210.08:03:59.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:03:59.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:03:59.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:03:59.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:03:59.21$vc4f8/va=6,6 2006.210.08:03:59.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.08:03:59.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.08:03:59.21#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:59.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:03:59.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:03:59.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:03:59.27#ibcon#enter wrdev, iclass 16, count 2 2006.210.08:03:59.27#ibcon#first serial, iclass 16, count 2 2006.210.08:03:59.27#ibcon#enter sib2, iclass 16, count 2 2006.210.08:03:59.27#ibcon#flushed, iclass 16, count 2 2006.210.08:03:59.27#ibcon#about to write, iclass 16, count 2 2006.210.08:03:59.27#ibcon#wrote, iclass 16, count 2 2006.210.08:03:59.27#ibcon#about to read 3, iclass 16, count 2 2006.210.08:03:59.29#ibcon#read 3, iclass 16, count 2 2006.210.08:03:59.29#ibcon#about to read 4, iclass 16, count 2 2006.210.08:03:59.29#ibcon#read 4, iclass 16, count 2 2006.210.08:03:59.29#ibcon#about to read 5, iclass 16, count 2 2006.210.08:03:59.29#ibcon#read 5, iclass 16, count 2 2006.210.08:03:59.29#ibcon#about to read 6, iclass 16, count 2 2006.210.08:03:59.29#ibcon#read 6, iclass 16, count 2 2006.210.08:03:59.29#ibcon#end of sib2, iclass 16, count 2 2006.210.08:03:59.29#ibcon#*mode == 0, iclass 16, count 2 2006.210.08:03:59.29#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.08:03:59.29#ibcon#[25=AT06-06\r\n] 2006.210.08:03:59.29#ibcon#*before write, iclass 16, count 2 2006.210.08:03:59.29#ibcon#enter sib2, iclass 16, count 2 2006.210.08:03:59.29#ibcon#flushed, iclass 16, count 2 2006.210.08:03:59.29#ibcon#about to write, iclass 16, count 2 2006.210.08:03:59.29#ibcon#wrote, iclass 16, count 2 2006.210.08:03:59.29#ibcon#about to read 3, iclass 16, count 2 2006.210.08:03:59.32#ibcon#read 3, iclass 16, count 2 2006.210.08:03:59.32#ibcon#about to read 4, iclass 16, count 2 2006.210.08:03:59.32#ibcon#read 4, iclass 16, count 2 2006.210.08:03:59.32#ibcon#about to read 5, iclass 16, count 2 2006.210.08:03:59.32#ibcon#read 5, iclass 16, count 2 2006.210.08:03:59.32#ibcon#about to read 6, iclass 16, count 2 2006.210.08:03:59.32#ibcon#read 6, iclass 16, count 2 2006.210.08:03:59.32#ibcon#end of sib2, iclass 16, count 2 2006.210.08:03:59.32#ibcon#*after write, iclass 16, count 2 2006.210.08:03:59.32#ibcon#*before return 0, iclass 16, count 2 2006.210.08:03:59.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:03:59.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:03:59.32#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.08:03:59.32#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:59.32#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:03:59.44#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:03:59.44#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:03:59.44#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:03:59.44#ibcon#first serial, iclass 16, count 0 2006.210.08:03:59.44#ibcon#enter sib2, iclass 16, count 0 2006.210.08:03:59.44#ibcon#flushed, iclass 16, count 0 2006.210.08:03:59.44#ibcon#about to write, iclass 16, count 0 2006.210.08:03:59.44#ibcon#wrote, iclass 16, count 0 2006.210.08:03:59.44#ibcon#about to read 3, iclass 16, count 0 2006.210.08:03:59.46#ibcon#read 3, iclass 16, count 0 2006.210.08:03:59.46#ibcon#about to read 4, iclass 16, count 0 2006.210.08:03:59.46#ibcon#read 4, iclass 16, count 0 2006.210.08:03:59.46#ibcon#about to read 5, iclass 16, count 0 2006.210.08:03:59.46#ibcon#read 5, iclass 16, count 0 2006.210.08:03:59.46#ibcon#about to read 6, iclass 16, count 0 2006.210.08:03:59.46#ibcon#read 6, iclass 16, count 0 2006.210.08:03:59.46#ibcon#end of sib2, iclass 16, count 0 2006.210.08:03:59.46#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:03:59.46#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:03:59.46#ibcon#[25=USB\r\n] 2006.210.08:03:59.46#ibcon#*before write, iclass 16, count 0 2006.210.08:03:59.46#ibcon#enter sib2, iclass 16, count 0 2006.210.08:03:59.46#ibcon#flushed, iclass 16, count 0 2006.210.08:03:59.46#ibcon#about to write, iclass 16, count 0 2006.210.08:03:59.46#ibcon#wrote, iclass 16, count 0 2006.210.08:03:59.46#ibcon#about to read 3, iclass 16, count 0 2006.210.08:03:59.49#ibcon#read 3, iclass 16, count 0 2006.210.08:03:59.49#ibcon#about to read 4, iclass 16, count 0 2006.210.08:03:59.49#ibcon#read 4, iclass 16, count 0 2006.210.08:03:59.49#ibcon#about to read 5, iclass 16, count 0 2006.210.08:03:59.49#ibcon#read 5, iclass 16, count 0 2006.210.08:03:59.49#ibcon#about to read 6, iclass 16, count 0 2006.210.08:03:59.49#ibcon#read 6, iclass 16, count 0 2006.210.08:03:59.49#ibcon#end of sib2, iclass 16, count 0 2006.210.08:03:59.49#ibcon#*after write, iclass 16, count 0 2006.210.08:03:59.49#ibcon#*before return 0, iclass 16, count 0 2006.210.08:03:59.49#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:03:59.49#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:03:59.49#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:03:59.49#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:03:59.49$vc4f8/valo=7,832.99 2006.210.08:03:59.49#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.08:03:59.49#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.08:03:59.49#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:59.49#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:03:59.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:03:59.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:03:59.49#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:03:59.49#ibcon#first serial, iclass 18, count 0 2006.210.08:03:59.49#ibcon#enter sib2, iclass 18, count 0 2006.210.08:03:59.49#ibcon#flushed, iclass 18, count 0 2006.210.08:03:59.49#ibcon#about to write, iclass 18, count 0 2006.210.08:03:59.49#ibcon#wrote, iclass 18, count 0 2006.210.08:03:59.49#ibcon#about to read 3, iclass 18, count 0 2006.210.08:03:59.51#ibcon#read 3, iclass 18, count 0 2006.210.08:03:59.51#ibcon#about to read 4, iclass 18, count 0 2006.210.08:03:59.51#ibcon#read 4, iclass 18, count 0 2006.210.08:03:59.51#ibcon#about to read 5, iclass 18, count 0 2006.210.08:03:59.51#ibcon#read 5, iclass 18, count 0 2006.210.08:03:59.51#ibcon#about to read 6, iclass 18, count 0 2006.210.08:03:59.51#ibcon#read 6, iclass 18, count 0 2006.210.08:03:59.51#ibcon#end of sib2, iclass 18, count 0 2006.210.08:03:59.51#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:03:59.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:03:59.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:03:59.51#ibcon#*before write, iclass 18, count 0 2006.210.08:03:59.51#ibcon#enter sib2, iclass 18, count 0 2006.210.08:03:59.51#ibcon#flushed, iclass 18, count 0 2006.210.08:03:59.51#ibcon#about to write, iclass 18, count 0 2006.210.08:03:59.51#ibcon#wrote, iclass 18, count 0 2006.210.08:03:59.51#ibcon#about to read 3, iclass 18, count 0 2006.210.08:03:59.55#ibcon#read 3, iclass 18, count 0 2006.210.08:03:59.55#ibcon#about to read 4, iclass 18, count 0 2006.210.08:03:59.55#ibcon#read 4, iclass 18, count 0 2006.210.08:03:59.55#ibcon#about to read 5, iclass 18, count 0 2006.210.08:03:59.55#ibcon#read 5, iclass 18, count 0 2006.210.08:03:59.55#ibcon#about to read 6, iclass 18, count 0 2006.210.08:03:59.55#ibcon#read 6, iclass 18, count 0 2006.210.08:03:59.55#ibcon#end of sib2, iclass 18, count 0 2006.210.08:03:59.55#ibcon#*after write, iclass 18, count 0 2006.210.08:03:59.55#ibcon#*before return 0, iclass 18, count 0 2006.210.08:03:59.55#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:03:59.55#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:03:59.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:03:59.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:03:59.55$vc4f8/va=7,6 2006.210.08:03:59.55#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.08:03:59.55#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.08:03:59.55#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:59.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:03:59.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:03:59.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:03:59.61#ibcon#enter wrdev, iclass 20, count 2 2006.210.08:03:59.61#ibcon#first serial, iclass 20, count 2 2006.210.08:03:59.61#ibcon#enter sib2, iclass 20, count 2 2006.210.08:03:59.61#ibcon#flushed, iclass 20, count 2 2006.210.08:03:59.61#ibcon#about to write, iclass 20, count 2 2006.210.08:03:59.61#ibcon#wrote, iclass 20, count 2 2006.210.08:03:59.61#ibcon#about to read 3, iclass 20, count 2 2006.210.08:03:59.63#ibcon#read 3, iclass 20, count 2 2006.210.08:03:59.63#ibcon#about to read 4, iclass 20, count 2 2006.210.08:03:59.63#ibcon#read 4, iclass 20, count 2 2006.210.08:03:59.63#ibcon#about to read 5, iclass 20, count 2 2006.210.08:03:59.63#ibcon#read 5, iclass 20, count 2 2006.210.08:03:59.63#ibcon#about to read 6, iclass 20, count 2 2006.210.08:03:59.63#ibcon#read 6, iclass 20, count 2 2006.210.08:03:59.63#ibcon#end of sib2, iclass 20, count 2 2006.210.08:03:59.63#ibcon#*mode == 0, iclass 20, count 2 2006.210.08:03:59.63#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.08:03:59.63#ibcon#[25=AT07-06\r\n] 2006.210.08:03:59.63#ibcon#*before write, iclass 20, count 2 2006.210.08:03:59.63#ibcon#enter sib2, iclass 20, count 2 2006.210.08:03:59.63#ibcon#flushed, iclass 20, count 2 2006.210.08:03:59.63#ibcon#about to write, iclass 20, count 2 2006.210.08:03:59.63#ibcon#wrote, iclass 20, count 2 2006.210.08:03:59.63#ibcon#about to read 3, iclass 20, count 2 2006.210.08:03:59.66#ibcon#read 3, iclass 20, count 2 2006.210.08:03:59.66#ibcon#about to read 4, iclass 20, count 2 2006.210.08:03:59.66#ibcon#read 4, iclass 20, count 2 2006.210.08:03:59.66#ibcon#about to read 5, iclass 20, count 2 2006.210.08:03:59.66#ibcon#read 5, iclass 20, count 2 2006.210.08:03:59.66#ibcon#about to read 6, iclass 20, count 2 2006.210.08:03:59.66#ibcon#read 6, iclass 20, count 2 2006.210.08:03:59.66#ibcon#end of sib2, iclass 20, count 2 2006.210.08:03:59.66#ibcon#*after write, iclass 20, count 2 2006.210.08:03:59.66#ibcon#*before return 0, iclass 20, count 2 2006.210.08:03:59.66#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:03:59.66#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:03:59.66#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.08:03:59.66#ibcon#ireg 7 cls_cnt 0 2006.210.08:03:59.66#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:03:59.78#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:03:59.78#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:03:59.78#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:03:59.78#ibcon#first serial, iclass 20, count 0 2006.210.08:03:59.78#ibcon#enter sib2, iclass 20, count 0 2006.210.08:03:59.78#ibcon#flushed, iclass 20, count 0 2006.210.08:03:59.78#ibcon#about to write, iclass 20, count 0 2006.210.08:03:59.78#ibcon#wrote, iclass 20, count 0 2006.210.08:03:59.78#ibcon#about to read 3, iclass 20, count 0 2006.210.08:03:59.80#ibcon#read 3, iclass 20, count 0 2006.210.08:03:59.80#ibcon#about to read 4, iclass 20, count 0 2006.210.08:03:59.80#ibcon#read 4, iclass 20, count 0 2006.210.08:03:59.80#ibcon#about to read 5, iclass 20, count 0 2006.210.08:03:59.80#ibcon#read 5, iclass 20, count 0 2006.210.08:03:59.80#ibcon#about to read 6, iclass 20, count 0 2006.210.08:03:59.80#ibcon#read 6, iclass 20, count 0 2006.210.08:03:59.80#ibcon#end of sib2, iclass 20, count 0 2006.210.08:03:59.80#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:03:59.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:03:59.80#ibcon#[25=USB\r\n] 2006.210.08:03:59.80#ibcon#*before write, iclass 20, count 0 2006.210.08:03:59.80#ibcon#enter sib2, iclass 20, count 0 2006.210.08:03:59.80#ibcon#flushed, iclass 20, count 0 2006.210.08:03:59.80#ibcon#about to write, iclass 20, count 0 2006.210.08:03:59.80#ibcon#wrote, iclass 20, count 0 2006.210.08:03:59.80#ibcon#about to read 3, iclass 20, count 0 2006.210.08:03:59.83#ibcon#read 3, iclass 20, count 0 2006.210.08:03:59.83#ibcon#about to read 4, iclass 20, count 0 2006.210.08:03:59.83#ibcon#read 4, iclass 20, count 0 2006.210.08:03:59.83#ibcon#about to read 5, iclass 20, count 0 2006.210.08:03:59.83#ibcon#read 5, iclass 20, count 0 2006.210.08:03:59.83#ibcon#about to read 6, iclass 20, count 0 2006.210.08:03:59.83#ibcon#read 6, iclass 20, count 0 2006.210.08:03:59.83#ibcon#end of sib2, iclass 20, count 0 2006.210.08:03:59.83#ibcon#*after write, iclass 20, count 0 2006.210.08:03:59.83#ibcon#*before return 0, iclass 20, count 0 2006.210.08:03:59.83#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:03:59.83#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:03:59.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:03:59.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:03:59.83$vc4f8/valo=8,852.99 2006.210.08:03:59.83#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.08:03:59.83#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.08:03:59.83#ibcon#ireg 17 cls_cnt 0 2006.210.08:03:59.83#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:03:59.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:03:59.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:03:59.83#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:03:59.83#ibcon#first serial, iclass 22, count 0 2006.210.08:03:59.83#ibcon#enter sib2, iclass 22, count 0 2006.210.08:03:59.83#ibcon#flushed, iclass 22, count 0 2006.210.08:03:59.83#ibcon#about to write, iclass 22, count 0 2006.210.08:03:59.83#ibcon#wrote, iclass 22, count 0 2006.210.08:03:59.83#ibcon#about to read 3, iclass 22, count 0 2006.210.08:03:59.85#ibcon#read 3, iclass 22, count 0 2006.210.08:03:59.85#ibcon#about to read 4, iclass 22, count 0 2006.210.08:03:59.85#ibcon#read 4, iclass 22, count 0 2006.210.08:03:59.85#ibcon#about to read 5, iclass 22, count 0 2006.210.08:03:59.85#ibcon#read 5, iclass 22, count 0 2006.210.08:03:59.85#ibcon#about to read 6, iclass 22, count 0 2006.210.08:03:59.85#ibcon#read 6, iclass 22, count 0 2006.210.08:03:59.85#ibcon#end of sib2, iclass 22, count 0 2006.210.08:03:59.85#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:03:59.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:03:59.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:03:59.85#ibcon#*before write, iclass 22, count 0 2006.210.08:03:59.85#ibcon#enter sib2, iclass 22, count 0 2006.210.08:03:59.85#ibcon#flushed, iclass 22, count 0 2006.210.08:03:59.85#ibcon#about to write, iclass 22, count 0 2006.210.08:03:59.85#ibcon#wrote, iclass 22, count 0 2006.210.08:03:59.85#ibcon#about to read 3, iclass 22, count 0 2006.210.08:03:59.89#ibcon#read 3, iclass 22, count 0 2006.210.08:03:59.89#ibcon#about to read 4, iclass 22, count 0 2006.210.08:03:59.89#ibcon#read 4, iclass 22, count 0 2006.210.08:03:59.89#ibcon#about to read 5, iclass 22, count 0 2006.210.08:03:59.89#ibcon#read 5, iclass 22, count 0 2006.210.08:03:59.89#ibcon#about to read 6, iclass 22, count 0 2006.210.08:03:59.89#ibcon#read 6, iclass 22, count 0 2006.210.08:03:59.89#ibcon#end of sib2, iclass 22, count 0 2006.210.08:03:59.89#ibcon#*after write, iclass 22, count 0 2006.210.08:03:59.89#ibcon#*before return 0, iclass 22, count 0 2006.210.08:03:59.89#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:03:59.89#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:03:59.89#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:03:59.89#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:03:59.89$vc4f8/va=8,7 2006.210.08:03:59.89#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.08:03:59.89#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.08:03:59.89#ibcon#ireg 11 cls_cnt 2 2006.210.08:03:59.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:03:59.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:03:59.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:03:59.95#ibcon#enter wrdev, iclass 24, count 2 2006.210.08:03:59.95#ibcon#first serial, iclass 24, count 2 2006.210.08:03:59.95#ibcon#enter sib2, iclass 24, count 2 2006.210.08:03:59.95#ibcon#flushed, iclass 24, count 2 2006.210.08:03:59.95#ibcon#about to write, iclass 24, count 2 2006.210.08:03:59.95#ibcon#wrote, iclass 24, count 2 2006.210.08:03:59.95#ibcon#about to read 3, iclass 24, count 2 2006.210.08:03:59.97#ibcon#read 3, iclass 24, count 2 2006.210.08:03:59.97#ibcon#about to read 4, iclass 24, count 2 2006.210.08:03:59.97#ibcon#read 4, iclass 24, count 2 2006.210.08:03:59.97#ibcon#about to read 5, iclass 24, count 2 2006.210.08:03:59.97#ibcon#read 5, iclass 24, count 2 2006.210.08:03:59.97#ibcon#about to read 6, iclass 24, count 2 2006.210.08:03:59.97#ibcon#read 6, iclass 24, count 2 2006.210.08:03:59.97#ibcon#end of sib2, iclass 24, count 2 2006.210.08:03:59.97#ibcon#*mode == 0, iclass 24, count 2 2006.210.08:03:59.97#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.08:03:59.97#ibcon#[25=AT08-07\r\n] 2006.210.08:03:59.97#ibcon#*before write, iclass 24, count 2 2006.210.08:03:59.97#ibcon#enter sib2, iclass 24, count 2 2006.210.08:03:59.97#ibcon#flushed, iclass 24, count 2 2006.210.08:03:59.97#ibcon#about to write, iclass 24, count 2 2006.210.08:03:59.97#ibcon#wrote, iclass 24, count 2 2006.210.08:03:59.97#ibcon#about to read 3, iclass 24, count 2 2006.210.08:04:00.00#ibcon#read 3, iclass 24, count 2 2006.210.08:04:00.00#ibcon#about to read 4, iclass 24, count 2 2006.210.08:04:00.00#ibcon#read 4, iclass 24, count 2 2006.210.08:04:00.00#ibcon#about to read 5, iclass 24, count 2 2006.210.08:04:00.00#ibcon#read 5, iclass 24, count 2 2006.210.08:04:00.00#ibcon#about to read 6, iclass 24, count 2 2006.210.08:04:00.00#ibcon#read 6, iclass 24, count 2 2006.210.08:04:00.00#ibcon#end of sib2, iclass 24, count 2 2006.210.08:04:00.00#ibcon#*after write, iclass 24, count 2 2006.210.08:04:00.00#ibcon#*before return 0, iclass 24, count 2 2006.210.08:04:00.00#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:04:00.00#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:04:00.00#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.08:04:00.00#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:00.00#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:04:00.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:04:00.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:04:00.12#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:04:00.12#ibcon#first serial, iclass 24, count 0 2006.210.08:04:00.12#ibcon#enter sib2, iclass 24, count 0 2006.210.08:04:00.12#ibcon#flushed, iclass 24, count 0 2006.210.08:04:00.12#ibcon#about to write, iclass 24, count 0 2006.210.08:04:00.12#ibcon#wrote, iclass 24, count 0 2006.210.08:04:00.12#ibcon#about to read 3, iclass 24, count 0 2006.210.08:04:00.14#ibcon#read 3, iclass 24, count 0 2006.210.08:04:00.14#ibcon#about to read 4, iclass 24, count 0 2006.210.08:04:00.14#ibcon#read 4, iclass 24, count 0 2006.210.08:04:00.14#ibcon#about to read 5, iclass 24, count 0 2006.210.08:04:00.14#ibcon#read 5, iclass 24, count 0 2006.210.08:04:00.14#ibcon#about to read 6, iclass 24, count 0 2006.210.08:04:00.14#ibcon#read 6, iclass 24, count 0 2006.210.08:04:00.14#ibcon#end of sib2, iclass 24, count 0 2006.210.08:04:00.14#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:04:00.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:04:00.14#ibcon#[25=USB\r\n] 2006.210.08:04:00.14#ibcon#*before write, iclass 24, count 0 2006.210.08:04:00.14#ibcon#enter sib2, iclass 24, count 0 2006.210.08:04:00.14#ibcon#flushed, iclass 24, count 0 2006.210.08:04:00.14#ibcon#about to write, iclass 24, count 0 2006.210.08:04:00.14#ibcon#wrote, iclass 24, count 0 2006.210.08:04:00.14#ibcon#about to read 3, iclass 24, count 0 2006.210.08:04:00.17#ibcon#read 3, iclass 24, count 0 2006.210.08:04:00.17#ibcon#about to read 4, iclass 24, count 0 2006.210.08:04:00.17#ibcon#read 4, iclass 24, count 0 2006.210.08:04:00.17#ibcon#about to read 5, iclass 24, count 0 2006.210.08:04:00.17#ibcon#read 5, iclass 24, count 0 2006.210.08:04:00.17#ibcon#about to read 6, iclass 24, count 0 2006.210.08:04:00.17#ibcon#read 6, iclass 24, count 0 2006.210.08:04:00.17#ibcon#end of sib2, iclass 24, count 0 2006.210.08:04:00.17#ibcon#*after write, iclass 24, count 0 2006.210.08:04:00.17#ibcon#*before return 0, iclass 24, count 0 2006.210.08:04:00.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:04:00.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:04:00.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:04:00.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:04:00.17$vc4f8/vblo=1,632.99 2006.210.08:04:00.17#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.08:04:00.17#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.08:04:00.17#ibcon#ireg 17 cls_cnt 0 2006.210.08:04:00.17#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:04:00.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:04:00.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:04:00.17#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:04:00.17#ibcon#first serial, iclass 26, count 0 2006.210.08:04:00.17#ibcon#enter sib2, iclass 26, count 0 2006.210.08:04:00.17#ibcon#flushed, iclass 26, count 0 2006.210.08:04:00.17#ibcon#about to write, iclass 26, count 0 2006.210.08:04:00.17#ibcon#wrote, iclass 26, count 0 2006.210.08:04:00.17#ibcon#about to read 3, iclass 26, count 0 2006.210.08:04:00.19#ibcon#read 3, iclass 26, count 0 2006.210.08:04:00.19#ibcon#about to read 4, iclass 26, count 0 2006.210.08:04:00.19#ibcon#read 4, iclass 26, count 0 2006.210.08:04:00.19#ibcon#about to read 5, iclass 26, count 0 2006.210.08:04:00.19#ibcon#read 5, iclass 26, count 0 2006.210.08:04:00.19#ibcon#about to read 6, iclass 26, count 0 2006.210.08:04:00.19#ibcon#read 6, iclass 26, count 0 2006.210.08:04:00.19#ibcon#end of sib2, iclass 26, count 0 2006.210.08:04:00.19#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:04:00.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:04:00.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:04:00.19#ibcon#*before write, iclass 26, count 0 2006.210.08:04:00.19#ibcon#enter sib2, iclass 26, count 0 2006.210.08:04:00.19#ibcon#flushed, iclass 26, count 0 2006.210.08:04:00.19#ibcon#about to write, iclass 26, count 0 2006.210.08:04:00.19#ibcon#wrote, iclass 26, count 0 2006.210.08:04:00.19#ibcon#about to read 3, iclass 26, count 0 2006.210.08:04:00.23#ibcon#read 3, iclass 26, count 0 2006.210.08:04:00.23#ibcon#about to read 4, iclass 26, count 0 2006.210.08:04:00.23#ibcon#read 4, iclass 26, count 0 2006.210.08:04:00.23#ibcon#about to read 5, iclass 26, count 0 2006.210.08:04:00.23#ibcon#read 5, iclass 26, count 0 2006.210.08:04:00.23#ibcon#about to read 6, iclass 26, count 0 2006.210.08:04:00.23#ibcon#read 6, iclass 26, count 0 2006.210.08:04:00.23#ibcon#end of sib2, iclass 26, count 0 2006.210.08:04:00.23#ibcon#*after write, iclass 26, count 0 2006.210.08:04:00.23#ibcon#*before return 0, iclass 26, count 0 2006.210.08:04:00.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:04:00.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:04:00.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:04:00.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:04:00.23$vc4f8/vb=1,4 2006.210.08:04:00.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.08:04:00.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.08:04:00.23#ibcon#ireg 11 cls_cnt 2 2006.210.08:04:00.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:04:00.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:04:00.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:04:00.23#ibcon#enter wrdev, iclass 28, count 2 2006.210.08:04:00.23#ibcon#first serial, iclass 28, count 2 2006.210.08:04:00.23#ibcon#enter sib2, iclass 28, count 2 2006.210.08:04:00.23#ibcon#flushed, iclass 28, count 2 2006.210.08:04:00.23#ibcon#about to write, iclass 28, count 2 2006.210.08:04:00.23#ibcon#wrote, iclass 28, count 2 2006.210.08:04:00.23#ibcon#about to read 3, iclass 28, count 2 2006.210.08:04:00.25#ibcon#read 3, iclass 28, count 2 2006.210.08:04:00.25#ibcon#about to read 4, iclass 28, count 2 2006.210.08:04:00.25#ibcon#read 4, iclass 28, count 2 2006.210.08:04:00.25#ibcon#about to read 5, iclass 28, count 2 2006.210.08:04:00.25#ibcon#read 5, iclass 28, count 2 2006.210.08:04:00.25#ibcon#about to read 6, iclass 28, count 2 2006.210.08:04:00.25#ibcon#read 6, iclass 28, count 2 2006.210.08:04:00.25#ibcon#end of sib2, iclass 28, count 2 2006.210.08:04:00.25#ibcon#*mode == 0, iclass 28, count 2 2006.210.08:04:00.25#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.08:04:00.25#ibcon#[27=AT01-04\r\n] 2006.210.08:04:00.25#ibcon#*before write, iclass 28, count 2 2006.210.08:04:00.25#ibcon#enter sib2, iclass 28, count 2 2006.210.08:04:00.25#ibcon#flushed, iclass 28, count 2 2006.210.08:04:00.25#ibcon#about to write, iclass 28, count 2 2006.210.08:04:00.25#ibcon#wrote, iclass 28, count 2 2006.210.08:04:00.25#ibcon#about to read 3, iclass 28, count 2 2006.210.08:04:00.28#ibcon#read 3, iclass 28, count 2 2006.210.08:04:00.28#ibcon#about to read 4, iclass 28, count 2 2006.210.08:04:00.28#ibcon#read 4, iclass 28, count 2 2006.210.08:04:00.28#ibcon#about to read 5, iclass 28, count 2 2006.210.08:04:00.28#ibcon#read 5, iclass 28, count 2 2006.210.08:04:00.28#ibcon#about to read 6, iclass 28, count 2 2006.210.08:04:00.28#ibcon#read 6, iclass 28, count 2 2006.210.08:04:00.28#ibcon#end of sib2, iclass 28, count 2 2006.210.08:04:00.28#ibcon#*after write, iclass 28, count 2 2006.210.08:04:00.28#ibcon#*before return 0, iclass 28, count 2 2006.210.08:04:00.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:04:00.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:04:00.28#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.08:04:00.28#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:00.28#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:04:00.40#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:04:00.40#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:04:00.40#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:04:00.40#ibcon#first serial, iclass 28, count 0 2006.210.08:04:00.40#ibcon#enter sib2, iclass 28, count 0 2006.210.08:04:00.40#ibcon#flushed, iclass 28, count 0 2006.210.08:04:00.40#ibcon#about to write, iclass 28, count 0 2006.210.08:04:00.40#ibcon#wrote, iclass 28, count 0 2006.210.08:04:00.40#ibcon#about to read 3, iclass 28, count 0 2006.210.08:04:00.42#ibcon#read 3, iclass 28, count 0 2006.210.08:04:00.42#ibcon#about to read 4, iclass 28, count 0 2006.210.08:04:00.42#ibcon#read 4, iclass 28, count 0 2006.210.08:04:00.42#ibcon#about to read 5, iclass 28, count 0 2006.210.08:04:00.42#ibcon#read 5, iclass 28, count 0 2006.210.08:04:00.42#ibcon#about to read 6, iclass 28, count 0 2006.210.08:04:00.42#ibcon#read 6, iclass 28, count 0 2006.210.08:04:00.42#ibcon#end of sib2, iclass 28, count 0 2006.210.08:04:00.42#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:04:00.42#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:04:00.42#ibcon#[27=USB\r\n] 2006.210.08:04:00.42#ibcon#*before write, iclass 28, count 0 2006.210.08:04:00.42#ibcon#enter sib2, iclass 28, count 0 2006.210.08:04:00.42#ibcon#flushed, iclass 28, count 0 2006.210.08:04:00.42#ibcon#about to write, iclass 28, count 0 2006.210.08:04:00.42#ibcon#wrote, iclass 28, count 0 2006.210.08:04:00.42#ibcon#about to read 3, iclass 28, count 0 2006.210.08:04:00.45#ibcon#read 3, iclass 28, count 0 2006.210.08:04:00.45#ibcon#about to read 4, iclass 28, count 0 2006.210.08:04:00.45#ibcon#read 4, iclass 28, count 0 2006.210.08:04:00.45#ibcon#about to read 5, iclass 28, count 0 2006.210.08:04:00.45#ibcon#read 5, iclass 28, count 0 2006.210.08:04:00.45#ibcon#about to read 6, iclass 28, count 0 2006.210.08:04:00.45#ibcon#read 6, iclass 28, count 0 2006.210.08:04:00.45#ibcon#end of sib2, iclass 28, count 0 2006.210.08:04:00.45#ibcon#*after write, iclass 28, count 0 2006.210.08:04:00.45#ibcon#*before return 0, iclass 28, count 0 2006.210.08:04:00.45#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:04:00.45#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:04:00.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:04:00.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:04:00.45$vc4f8/vblo=2,640.99 2006.210.08:04:00.45#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.08:04:00.45#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.08:04:00.45#ibcon#ireg 17 cls_cnt 0 2006.210.08:04:00.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:04:00.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:04:00.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:04:00.45#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:04:00.45#ibcon#first serial, iclass 30, count 0 2006.210.08:04:00.45#ibcon#enter sib2, iclass 30, count 0 2006.210.08:04:00.45#ibcon#flushed, iclass 30, count 0 2006.210.08:04:00.45#ibcon#about to write, iclass 30, count 0 2006.210.08:04:00.45#ibcon#wrote, iclass 30, count 0 2006.210.08:04:00.45#ibcon#about to read 3, iclass 30, count 0 2006.210.08:04:00.47#ibcon#read 3, iclass 30, count 0 2006.210.08:04:00.47#ibcon#about to read 4, iclass 30, count 0 2006.210.08:04:00.47#ibcon#read 4, iclass 30, count 0 2006.210.08:04:00.47#ibcon#about to read 5, iclass 30, count 0 2006.210.08:04:00.47#ibcon#read 5, iclass 30, count 0 2006.210.08:04:00.47#ibcon#about to read 6, iclass 30, count 0 2006.210.08:04:00.47#ibcon#read 6, iclass 30, count 0 2006.210.08:04:00.47#ibcon#end of sib2, iclass 30, count 0 2006.210.08:04:00.47#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:04:00.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:04:00.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:04:00.47#ibcon#*before write, iclass 30, count 0 2006.210.08:04:00.47#ibcon#enter sib2, iclass 30, count 0 2006.210.08:04:00.47#ibcon#flushed, iclass 30, count 0 2006.210.08:04:00.47#ibcon#about to write, iclass 30, count 0 2006.210.08:04:00.47#ibcon#wrote, iclass 30, count 0 2006.210.08:04:00.47#ibcon#about to read 3, iclass 30, count 0 2006.210.08:04:00.51#ibcon#read 3, iclass 30, count 0 2006.210.08:04:00.51#ibcon#about to read 4, iclass 30, count 0 2006.210.08:04:00.51#ibcon#read 4, iclass 30, count 0 2006.210.08:04:00.51#ibcon#about to read 5, iclass 30, count 0 2006.210.08:04:00.51#ibcon#read 5, iclass 30, count 0 2006.210.08:04:00.51#ibcon#about to read 6, iclass 30, count 0 2006.210.08:04:00.51#ibcon#read 6, iclass 30, count 0 2006.210.08:04:00.51#ibcon#end of sib2, iclass 30, count 0 2006.210.08:04:00.51#ibcon#*after write, iclass 30, count 0 2006.210.08:04:00.51#ibcon#*before return 0, iclass 30, count 0 2006.210.08:04:00.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:04:00.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:04:00.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:04:00.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:04:00.51$vc4f8/vb=2,4 2006.210.08:04:00.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.08:04:00.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.08:04:00.51#ibcon#ireg 11 cls_cnt 2 2006.210.08:04:00.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:04:00.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:04:00.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:04:00.57#ibcon#enter wrdev, iclass 32, count 2 2006.210.08:04:00.57#ibcon#first serial, iclass 32, count 2 2006.210.08:04:00.57#ibcon#enter sib2, iclass 32, count 2 2006.210.08:04:00.57#ibcon#flushed, iclass 32, count 2 2006.210.08:04:00.57#ibcon#about to write, iclass 32, count 2 2006.210.08:04:00.57#ibcon#wrote, iclass 32, count 2 2006.210.08:04:00.57#ibcon#about to read 3, iclass 32, count 2 2006.210.08:04:00.59#ibcon#read 3, iclass 32, count 2 2006.210.08:04:00.59#ibcon#about to read 4, iclass 32, count 2 2006.210.08:04:00.59#ibcon#read 4, iclass 32, count 2 2006.210.08:04:00.59#ibcon#about to read 5, iclass 32, count 2 2006.210.08:04:00.59#ibcon#read 5, iclass 32, count 2 2006.210.08:04:00.59#ibcon#about to read 6, iclass 32, count 2 2006.210.08:04:00.59#ibcon#read 6, iclass 32, count 2 2006.210.08:04:00.59#ibcon#end of sib2, iclass 32, count 2 2006.210.08:04:00.59#ibcon#*mode == 0, iclass 32, count 2 2006.210.08:04:00.59#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.08:04:00.59#ibcon#[27=AT02-04\r\n] 2006.210.08:04:00.59#ibcon#*before write, iclass 32, count 2 2006.210.08:04:00.59#ibcon#enter sib2, iclass 32, count 2 2006.210.08:04:00.59#ibcon#flushed, iclass 32, count 2 2006.210.08:04:00.59#ibcon#about to write, iclass 32, count 2 2006.210.08:04:00.59#ibcon#wrote, iclass 32, count 2 2006.210.08:04:00.59#ibcon#about to read 3, iclass 32, count 2 2006.210.08:04:00.62#ibcon#read 3, iclass 32, count 2 2006.210.08:04:00.62#ibcon#about to read 4, iclass 32, count 2 2006.210.08:04:00.62#ibcon#read 4, iclass 32, count 2 2006.210.08:04:00.62#ibcon#about to read 5, iclass 32, count 2 2006.210.08:04:00.62#ibcon#read 5, iclass 32, count 2 2006.210.08:04:00.62#ibcon#about to read 6, iclass 32, count 2 2006.210.08:04:00.62#ibcon#read 6, iclass 32, count 2 2006.210.08:04:00.62#ibcon#end of sib2, iclass 32, count 2 2006.210.08:04:00.62#ibcon#*after write, iclass 32, count 2 2006.210.08:04:00.62#ibcon#*before return 0, iclass 32, count 2 2006.210.08:04:00.62#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:04:00.62#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:04:00.62#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.08:04:00.62#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:00.62#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:04:00.74#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:04:00.74#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:04:00.74#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:04:00.74#ibcon#first serial, iclass 32, count 0 2006.210.08:04:00.74#ibcon#enter sib2, iclass 32, count 0 2006.210.08:04:00.74#ibcon#flushed, iclass 32, count 0 2006.210.08:04:00.74#ibcon#about to write, iclass 32, count 0 2006.210.08:04:00.74#ibcon#wrote, iclass 32, count 0 2006.210.08:04:00.74#ibcon#about to read 3, iclass 32, count 0 2006.210.08:04:00.76#ibcon#read 3, iclass 32, count 0 2006.210.08:04:00.76#ibcon#about to read 4, iclass 32, count 0 2006.210.08:04:00.76#ibcon#read 4, iclass 32, count 0 2006.210.08:04:00.76#ibcon#about to read 5, iclass 32, count 0 2006.210.08:04:00.76#ibcon#read 5, iclass 32, count 0 2006.210.08:04:00.76#ibcon#about to read 6, iclass 32, count 0 2006.210.08:04:00.76#ibcon#read 6, iclass 32, count 0 2006.210.08:04:00.76#ibcon#end of sib2, iclass 32, count 0 2006.210.08:04:00.76#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:04:00.76#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:04:00.76#ibcon#[27=USB\r\n] 2006.210.08:04:00.76#ibcon#*before write, iclass 32, count 0 2006.210.08:04:00.76#ibcon#enter sib2, iclass 32, count 0 2006.210.08:04:00.76#ibcon#flushed, iclass 32, count 0 2006.210.08:04:00.76#ibcon#about to write, iclass 32, count 0 2006.210.08:04:00.76#ibcon#wrote, iclass 32, count 0 2006.210.08:04:00.76#ibcon#about to read 3, iclass 32, count 0 2006.210.08:04:00.79#ibcon#read 3, iclass 32, count 0 2006.210.08:04:00.79#ibcon#about to read 4, iclass 32, count 0 2006.210.08:04:00.79#ibcon#read 4, iclass 32, count 0 2006.210.08:04:00.79#ibcon#about to read 5, iclass 32, count 0 2006.210.08:04:00.79#ibcon#read 5, iclass 32, count 0 2006.210.08:04:00.79#ibcon#about to read 6, iclass 32, count 0 2006.210.08:04:00.79#ibcon#read 6, iclass 32, count 0 2006.210.08:04:00.79#ibcon#end of sib2, iclass 32, count 0 2006.210.08:04:00.79#ibcon#*after write, iclass 32, count 0 2006.210.08:04:00.79#ibcon#*before return 0, iclass 32, count 0 2006.210.08:04:00.79#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:04:00.79#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:04:00.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:04:00.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:04:00.79$vc4f8/vblo=3,656.99 2006.210.08:04:00.79#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:04:00.79#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:04:00.79#ibcon#ireg 17 cls_cnt 0 2006.210.08:04:00.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:04:00.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:04:00.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:04:00.79#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:04:00.79#ibcon#first serial, iclass 34, count 0 2006.210.08:04:00.79#ibcon#enter sib2, iclass 34, count 0 2006.210.08:04:00.79#ibcon#flushed, iclass 34, count 0 2006.210.08:04:00.79#ibcon#about to write, iclass 34, count 0 2006.210.08:04:00.79#ibcon#wrote, iclass 34, count 0 2006.210.08:04:00.79#ibcon#about to read 3, iclass 34, count 0 2006.210.08:04:00.81#ibcon#read 3, iclass 34, count 0 2006.210.08:04:00.81#ibcon#about to read 4, iclass 34, count 0 2006.210.08:04:00.81#ibcon#read 4, iclass 34, count 0 2006.210.08:04:00.81#ibcon#about to read 5, iclass 34, count 0 2006.210.08:04:00.81#ibcon#read 5, iclass 34, count 0 2006.210.08:04:00.81#ibcon#about to read 6, iclass 34, count 0 2006.210.08:04:00.81#ibcon#read 6, iclass 34, count 0 2006.210.08:04:00.81#ibcon#end of sib2, iclass 34, count 0 2006.210.08:04:00.81#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:04:00.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:04:00.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:04:00.81#ibcon#*before write, iclass 34, count 0 2006.210.08:04:00.81#ibcon#enter sib2, iclass 34, count 0 2006.210.08:04:00.81#ibcon#flushed, iclass 34, count 0 2006.210.08:04:00.81#ibcon#about to write, iclass 34, count 0 2006.210.08:04:00.81#ibcon#wrote, iclass 34, count 0 2006.210.08:04:00.81#ibcon#about to read 3, iclass 34, count 0 2006.210.08:04:00.85#ibcon#read 3, iclass 34, count 0 2006.210.08:04:00.85#ibcon#about to read 4, iclass 34, count 0 2006.210.08:04:00.85#ibcon#read 4, iclass 34, count 0 2006.210.08:04:00.85#ibcon#about to read 5, iclass 34, count 0 2006.210.08:04:00.85#ibcon#read 5, iclass 34, count 0 2006.210.08:04:00.85#ibcon#about to read 6, iclass 34, count 0 2006.210.08:04:00.85#ibcon#read 6, iclass 34, count 0 2006.210.08:04:00.85#ibcon#end of sib2, iclass 34, count 0 2006.210.08:04:00.85#ibcon#*after write, iclass 34, count 0 2006.210.08:04:00.85#ibcon#*before return 0, iclass 34, count 0 2006.210.08:04:00.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:04:00.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:04:00.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:04:00.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:04:00.85$vc4f8/vb=3,3 2006.210.08:04:00.85#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.08:04:00.85#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.08:04:00.85#ibcon#ireg 11 cls_cnt 2 2006.210.08:04:00.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:04:00.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:04:00.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:04:00.91#ibcon#enter wrdev, iclass 36, count 2 2006.210.08:04:00.91#ibcon#first serial, iclass 36, count 2 2006.210.08:04:00.91#ibcon#enter sib2, iclass 36, count 2 2006.210.08:04:00.91#ibcon#flushed, iclass 36, count 2 2006.210.08:04:00.91#ibcon#about to write, iclass 36, count 2 2006.210.08:04:00.91#ibcon#wrote, iclass 36, count 2 2006.210.08:04:00.91#ibcon#about to read 3, iclass 36, count 2 2006.210.08:04:00.93#ibcon#read 3, iclass 36, count 2 2006.210.08:04:00.93#ibcon#about to read 4, iclass 36, count 2 2006.210.08:04:00.93#ibcon#read 4, iclass 36, count 2 2006.210.08:04:00.93#ibcon#about to read 5, iclass 36, count 2 2006.210.08:04:00.93#ibcon#read 5, iclass 36, count 2 2006.210.08:04:00.93#ibcon#about to read 6, iclass 36, count 2 2006.210.08:04:00.93#ibcon#read 6, iclass 36, count 2 2006.210.08:04:00.93#ibcon#end of sib2, iclass 36, count 2 2006.210.08:04:00.93#ibcon#*mode == 0, iclass 36, count 2 2006.210.08:04:00.93#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.08:04:00.93#ibcon#[27=AT03-03\r\n] 2006.210.08:04:00.93#ibcon#*before write, iclass 36, count 2 2006.210.08:04:00.93#ibcon#enter sib2, iclass 36, count 2 2006.210.08:04:00.93#ibcon#flushed, iclass 36, count 2 2006.210.08:04:00.93#ibcon#about to write, iclass 36, count 2 2006.210.08:04:00.93#ibcon#wrote, iclass 36, count 2 2006.210.08:04:00.93#ibcon#about to read 3, iclass 36, count 2 2006.210.08:04:00.96#ibcon#read 3, iclass 36, count 2 2006.210.08:04:00.96#ibcon#about to read 4, iclass 36, count 2 2006.210.08:04:00.96#ibcon#read 4, iclass 36, count 2 2006.210.08:04:00.96#ibcon#about to read 5, iclass 36, count 2 2006.210.08:04:00.96#ibcon#read 5, iclass 36, count 2 2006.210.08:04:00.96#ibcon#about to read 6, iclass 36, count 2 2006.210.08:04:00.96#ibcon#read 6, iclass 36, count 2 2006.210.08:04:00.96#ibcon#end of sib2, iclass 36, count 2 2006.210.08:04:00.96#ibcon#*after write, iclass 36, count 2 2006.210.08:04:00.96#ibcon#*before return 0, iclass 36, count 2 2006.210.08:04:00.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:04:00.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:04:00.96#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.08:04:00.96#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:00.96#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:04:01.08#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:04:01.08#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:04:01.08#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:04:01.08#ibcon#first serial, iclass 36, count 0 2006.210.08:04:01.08#ibcon#enter sib2, iclass 36, count 0 2006.210.08:04:01.08#ibcon#flushed, iclass 36, count 0 2006.210.08:04:01.08#ibcon#about to write, iclass 36, count 0 2006.210.08:04:01.08#ibcon#wrote, iclass 36, count 0 2006.210.08:04:01.08#ibcon#about to read 3, iclass 36, count 0 2006.210.08:04:01.10#ibcon#read 3, iclass 36, count 0 2006.210.08:04:01.10#ibcon#about to read 4, iclass 36, count 0 2006.210.08:04:01.10#ibcon#read 4, iclass 36, count 0 2006.210.08:04:01.10#ibcon#about to read 5, iclass 36, count 0 2006.210.08:04:01.10#ibcon#read 5, iclass 36, count 0 2006.210.08:04:01.10#ibcon#about to read 6, iclass 36, count 0 2006.210.08:04:01.10#ibcon#read 6, iclass 36, count 0 2006.210.08:04:01.10#ibcon#end of sib2, iclass 36, count 0 2006.210.08:04:01.10#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:04:01.10#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:04:01.10#ibcon#[27=USB\r\n] 2006.210.08:04:01.10#ibcon#*before write, iclass 36, count 0 2006.210.08:04:01.10#ibcon#enter sib2, iclass 36, count 0 2006.210.08:04:01.10#ibcon#flushed, iclass 36, count 0 2006.210.08:04:01.10#ibcon#about to write, iclass 36, count 0 2006.210.08:04:01.10#ibcon#wrote, iclass 36, count 0 2006.210.08:04:01.10#ibcon#about to read 3, iclass 36, count 0 2006.210.08:04:01.13#ibcon#read 3, iclass 36, count 0 2006.210.08:04:01.13#ibcon#about to read 4, iclass 36, count 0 2006.210.08:04:01.13#ibcon#read 4, iclass 36, count 0 2006.210.08:04:01.13#ibcon#about to read 5, iclass 36, count 0 2006.210.08:04:01.13#ibcon#read 5, iclass 36, count 0 2006.210.08:04:01.13#ibcon#about to read 6, iclass 36, count 0 2006.210.08:04:01.13#ibcon#read 6, iclass 36, count 0 2006.210.08:04:01.13#ibcon#end of sib2, iclass 36, count 0 2006.210.08:04:01.13#ibcon#*after write, iclass 36, count 0 2006.210.08:04:01.13#ibcon#*before return 0, iclass 36, count 0 2006.210.08:04:01.13#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:04:01.13#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:04:01.13#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:04:01.13#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:04:01.13$vc4f8/vblo=4,712.99 2006.210.08:04:01.13#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.08:04:01.13#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.08:04:01.13#ibcon#ireg 17 cls_cnt 0 2006.210.08:04:01.13#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:04:01.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:04:01.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:04:01.13#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:04:01.13#ibcon#first serial, iclass 38, count 0 2006.210.08:04:01.13#ibcon#enter sib2, iclass 38, count 0 2006.210.08:04:01.13#ibcon#flushed, iclass 38, count 0 2006.210.08:04:01.13#ibcon#about to write, iclass 38, count 0 2006.210.08:04:01.13#ibcon#wrote, iclass 38, count 0 2006.210.08:04:01.13#ibcon#about to read 3, iclass 38, count 0 2006.210.08:04:01.15#ibcon#read 3, iclass 38, count 0 2006.210.08:04:01.15#ibcon#about to read 4, iclass 38, count 0 2006.210.08:04:01.15#ibcon#read 4, iclass 38, count 0 2006.210.08:04:01.15#ibcon#about to read 5, iclass 38, count 0 2006.210.08:04:01.15#ibcon#read 5, iclass 38, count 0 2006.210.08:04:01.15#ibcon#about to read 6, iclass 38, count 0 2006.210.08:04:01.15#ibcon#read 6, iclass 38, count 0 2006.210.08:04:01.15#ibcon#end of sib2, iclass 38, count 0 2006.210.08:04:01.15#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:04:01.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:04:01.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:04:01.15#ibcon#*before write, iclass 38, count 0 2006.210.08:04:01.15#ibcon#enter sib2, iclass 38, count 0 2006.210.08:04:01.15#ibcon#flushed, iclass 38, count 0 2006.210.08:04:01.15#ibcon#about to write, iclass 38, count 0 2006.210.08:04:01.15#ibcon#wrote, iclass 38, count 0 2006.210.08:04:01.15#ibcon#about to read 3, iclass 38, count 0 2006.210.08:04:01.19#ibcon#read 3, iclass 38, count 0 2006.210.08:04:01.19#ibcon#about to read 4, iclass 38, count 0 2006.210.08:04:01.19#ibcon#read 4, iclass 38, count 0 2006.210.08:04:01.19#ibcon#about to read 5, iclass 38, count 0 2006.210.08:04:01.19#ibcon#read 5, iclass 38, count 0 2006.210.08:04:01.19#ibcon#about to read 6, iclass 38, count 0 2006.210.08:04:01.19#ibcon#read 6, iclass 38, count 0 2006.210.08:04:01.19#ibcon#end of sib2, iclass 38, count 0 2006.210.08:04:01.19#ibcon#*after write, iclass 38, count 0 2006.210.08:04:01.19#ibcon#*before return 0, iclass 38, count 0 2006.210.08:04:01.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:04:01.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:04:01.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:04:01.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:04:01.19$vc4f8/vb=4,3 2006.210.08:04:01.19#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.08:04:01.19#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.08:04:01.19#ibcon#ireg 11 cls_cnt 2 2006.210.08:04:01.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:04:01.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:04:01.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:04:01.25#ibcon#enter wrdev, iclass 40, count 2 2006.210.08:04:01.25#ibcon#first serial, iclass 40, count 2 2006.210.08:04:01.25#ibcon#enter sib2, iclass 40, count 2 2006.210.08:04:01.25#ibcon#flushed, iclass 40, count 2 2006.210.08:04:01.25#ibcon#about to write, iclass 40, count 2 2006.210.08:04:01.25#ibcon#wrote, iclass 40, count 2 2006.210.08:04:01.25#ibcon#about to read 3, iclass 40, count 2 2006.210.08:04:01.27#ibcon#read 3, iclass 40, count 2 2006.210.08:04:01.27#ibcon#about to read 4, iclass 40, count 2 2006.210.08:04:01.27#ibcon#read 4, iclass 40, count 2 2006.210.08:04:01.27#ibcon#about to read 5, iclass 40, count 2 2006.210.08:04:01.27#ibcon#read 5, iclass 40, count 2 2006.210.08:04:01.27#ibcon#about to read 6, iclass 40, count 2 2006.210.08:04:01.27#ibcon#read 6, iclass 40, count 2 2006.210.08:04:01.27#ibcon#end of sib2, iclass 40, count 2 2006.210.08:04:01.27#ibcon#*mode == 0, iclass 40, count 2 2006.210.08:04:01.27#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.08:04:01.27#ibcon#[27=AT04-03\r\n] 2006.210.08:04:01.27#ibcon#*before write, iclass 40, count 2 2006.210.08:04:01.27#ibcon#enter sib2, iclass 40, count 2 2006.210.08:04:01.27#ibcon#flushed, iclass 40, count 2 2006.210.08:04:01.27#ibcon#about to write, iclass 40, count 2 2006.210.08:04:01.27#ibcon#wrote, iclass 40, count 2 2006.210.08:04:01.27#ibcon#about to read 3, iclass 40, count 2 2006.210.08:04:01.30#ibcon#read 3, iclass 40, count 2 2006.210.08:04:01.30#ibcon#about to read 4, iclass 40, count 2 2006.210.08:04:01.30#ibcon#read 4, iclass 40, count 2 2006.210.08:04:01.30#ibcon#about to read 5, iclass 40, count 2 2006.210.08:04:01.30#ibcon#read 5, iclass 40, count 2 2006.210.08:04:01.30#ibcon#about to read 6, iclass 40, count 2 2006.210.08:04:01.30#ibcon#read 6, iclass 40, count 2 2006.210.08:04:01.30#ibcon#end of sib2, iclass 40, count 2 2006.210.08:04:01.30#ibcon#*after write, iclass 40, count 2 2006.210.08:04:01.30#ibcon#*before return 0, iclass 40, count 2 2006.210.08:04:01.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:04:01.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:04:01.30#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.08:04:01.30#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:01.30#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:04:01.42#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:04:01.42#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:04:01.42#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:04:01.42#ibcon#first serial, iclass 40, count 0 2006.210.08:04:01.42#ibcon#enter sib2, iclass 40, count 0 2006.210.08:04:01.42#ibcon#flushed, iclass 40, count 0 2006.210.08:04:01.42#ibcon#about to write, iclass 40, count 0 2006.210.08:04:01.42#ibcon#wrote, iclass 40, count 0 2006.210.08:04:01.42#ibcon#about to read 3, iclass 40, count 0 2006.210.08:04:01.44#ibcon#read 3, iclass 40, count 0 2006.210.08:04:01.44#ibcon#about to read 4, iclass 40, count 0 2006.210.08:04:01.44#ibcon#read 4, iclass 40, count 0 2006.210.08:04:01.44#ibcon#about to read 5, iclass 40, count 0 2006.210.08:04:01.44#ibcon#read 5, iclass 40, count 0 2006.210.08:04:01.44#ibcon#about to read 6, iclass 40, count 0 2006.210.08:04:01.44#ibcon#read 6, iclass 40, count 0 2006.210.08:04:01.44#ibcon#end of sib2, iclass 40, count 0 2006.210.08:04:01.44#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:04:01.44#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:04:01.44#ibcon#[27=USB\r\n] 2006.210.08:04:01.44#ibcon#*before write, iclass 40, count 0 2006.210.08:04:01.44#ibcon#enter sib2, iclass 40, count 0 2006.210.08:04:01.44#ibcon#flushed, iclass 40, count 0 2006.210.08:04:01.44#ibcon#about to write, iclass 40, count 0 2006.210.08:04:01.44#ibcon#wrote, iclass 40, count 0 2006.210.08:04:01.44#ibcon#about to read 3, iclass 40, count 0 2006.210.08:04:01.47#ibcon#read 3, iclass 40, count 0 2006.210.08:04:01.47#ibcon#about to read 4, iclass 40, count 0 2006.210.08:04:01.47#ibcon#read 4, iclass 40, count 0 2006.210.08:04:01.47#ibcon#about to read 5, iclass 40, count 0 2006.210.08:04:01.47#ibcon#read 5, iclass 40, count 0 2006.210.08:04:01.47#ibcon#about to read 6, iclass 40, count 0 2006.210.08:04:01.47#ibcon#read 6, iclass 40, count 0 2006.210.08:04:01.47#ibcon#end of sib2, iclass 40, count 0 2006.210.08:04:01.47#ibcon#*after write, iclass 40, count 0 2006.210.08:04:01.47#ibcon#*before return 0, iclass 40, count 0 2006.210.08:04:01.47#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:04:01.47#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:04:01.47#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:04:01.47#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:04:01.47$vc4f8/vblo=5,744.99 2006.210.08:04:01.47#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.08:04:01.47#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.08:04:01.47#ibcon#ireg 17 cls_cnt 0 2006.210.08:04:01.47#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:04:01.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:04:01.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:04:01.47#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:04:01.47#ibcon#first serial, iclass 4, count 0 2006.210.08:04:01.47#ibcon#enter sib2, iclass 4, count 0 2006.210.08:04:01.47#ibcon#flushed, iclass 4, count 0 2006.210.08:04:01.47#ibcon#about to write, iclass 4, count 0 2006.210.08:04:01.47#ibcon#wrote, iclass 4, count 0 2006.210.08:04:01.47#ibcon#about to read 3, iclass 4, count 0 2006.210.08:04:01.49#ibcon#read 3, iclass 4, count 0 2006.210.08:04:01.49#ibcon#about to read 4, iclass 4, count 0 2006.210.08:04:01.49#ibcon#read 4, iclass 4, count 0 2006.210.08:04:01.49#ibcon#about to read 5, iclass 4, count 0 2006.210.08:04:01.49#ibcon#read 5, iclass 4, count 0 2006.210.08:04:01.49#ibcon#about to read 6, iclass 4, count 0 2006.210.08:04:01.49#ibcon#read 6, iclass 4, count 0 2006.210.08:04:01.49#ibcon#end of sib2, iclass 4, count 0 2006.210.08:04:01.49#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:04:01.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:04:01.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:04:01.49#ibcon#*before write, iclass 4, count 0 2006.210.08:04:01.49#ibcon#enter sib2, iclass 4, count 0 2006.210.08:04:01.49#ibcon#flushed, iclass 4, count 0 2006.210.08:04:01.49#ibcon#about to write, iclass 4, count 0 2006.210.08:04:01.49#ibcon#wrote, iclass 4, count 0 2006.210.08:04:01.49#ibcon#about to read 3, iclass 4, count 0 2006.210.08:04:01.53#ibcon#read 3, iclass 4, count 0 2006.210.08:04:01.53#ibcon#about to read 4, iclass 4, count 0 2006.210.08:04:01.53#ibcon#read 4, iclass 4, count 0 2006.210.08:04:01.53#ibcon#about to read 5, iclass 4, count 0 2006.210.08:04:01.53#ibcon#read 5, iclass 4, count 0 2006.210.08:04:01.53#ibcon#about to read 6, iclass 4, count 0 2006.210.08:04:01.53#ibcon#read 6, iclass 4, count 0 2006.210.08:04:01.53#ibcon#end of sib2, iclass 4, count 0 2006.210.08:04:01.53#ibcon#*after write, iclass 4, count 0 2006.210.08:04:01.53#ibcon#*before return 0, iclass 4, count 0 2006.210.08:04:01.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:04:01.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:04:01.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:04:01.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:04:01.53$vc4f8/vb=5,3 2006.210.08:04:01.53#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.08:04:01.53#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.08:04:01.53#ibcon#ireg 11 cls_cnt 2 2006.210.08:04:01.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:04:01.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:04:01.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:04:01.59#ibcon#enter wrdev, iclass 6, count 2 2006.210.08:04:01.59#ibcon#first serial, iclass 6, count 2 2006.210.08:04:01.59#ibcon#enter sib2, iclass 6, count 2 2006.210.08:04:01.59#ibcon#flushed, iclass 6, count 2 2006.210.08:04:01.59#ibcon#about to write, iclass 6, count 2 2006.210.08:04:01.59#ibcon#wrote, iclass 6, count 2 2006.210.08:04:01.59#ibcon#about to read 3, iclass 6, count 2 2006.210.08:04:01.61#ibcon#read 3, iclass 6, count 2 2006.210.08:04:01.61#ibcon#about to read 4, iclass 6, count 2 2006.210.08:04:01.61#ibcon#read 4, iclass 6, count 2 2006.210.08:04:01.61#ibcon#about to read 5, iclass 6, count 2 2006.210.08:04:01.61#ibcon#read 5, iclass 6, count 2 2006.210.08:04:01.61#ibcon#about to read 6, iclass 6, count 2 2006.210.08:04:01.61#ibcon#read 6, iclass 6, count 2 2006.210.08:04:01.61#ibcon#end of sib2, iclass 6, count 2 2006.210.08:04:01.61#ibcon#*mode == 0, iclass 6, count 2 2006.210.08:04:01.61#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.08:04:01.61#ibcon#[27=AT05-03\r\n] 2006.210.08:04:01.61#ibcon#*before write, iclass 6, count 2 2006.210.08:04:01.61#ibcon#enter sib2, iclass 6, count 2 2006.210.08:04:01.61#ibcon#flushed, iclass 6, count 2 2006.210.08:04:01.61#ibcon#about to write, iclass 6, count 2 2006.210.08:04:01.61#ibcon#wrote, iclass 6, count 2 2006.210.08:04:01.61#ibcon#about to read 3, iclass 6, count 2 2006.210.08:04:01.64#ibcon#read 3, iclass 6, count 2 2006.210.08:04:01.64#ibcon#about to read 4, iclass 6, count 2 2006.210.08:04:01.64#ibcon#read 4, iclass 6, count 2 2006.210.08:04:01.64#ibcon#about to read 5, iclass 6, count 2 2006.210.08:04:01.64#ibcon#read 5, iclass 6, count 2 2006.210.08:04:01.64#ibcon#about to read 6, iclass 6, count 2 2006.210.08:04:01.64#ibcon#read 6, iclass 6, count 2 2006.210.08:04:01.64#ibcon#end of sib2, iclass 6, count 2 2006.210.08:04:01.64#ibcon#*after write, iclass 6, count 2 2006.210.08:04:01.64#ibcon#*before return 0, iclass 6, count 2 2006.210.08:04:01.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:04:01.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:04:01.64#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.08:04:01.64#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:01.64#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:04:01.76#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:04:01.76#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:04:01.76#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:04:01.76#ibcon#first serial, iclass 6, count 0 2006.210.08:04:01.76#ibcon#enter sib2, iclass 6, count 0 2006.210.08:04:01.76#ibcon#flushed, iclass 6, count 0 2006.210.08:04:01.76#ibcon#about to write, iclass 6, count 0 2006.210.08:04:01.76#ibcon#wrote, iclass 6, count 0 2006.210.08:04:01.76#ibcon#about to read 3, iclass 6, count 0 2006.210.08:04:01.78#ibcon#read 3, iclass 6, count 0 2006.210.08:04:01.78#ibcon#about to read 4, iclass 6, count 0 2006.210.08:04:01.78#ibcon#read 4, iclass 6, count 0 2006.210.08:04:01.78#ibcon#about to read 5, iclass 6, count 0 2006.210.08:04:01.78#ibcon#read 5, iclass 6, count 0 2006.210.08:04:01.78#ibcon#about to read 6, iclass 6, count 0 2006.210.08:04:01.78#ibcon#read 6, iclass 6, count 0 2006.210.08:04:01.78#ibcon#end of sib2, iclass 6, count 0 2006.210.08:04:01.78#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:04:01.78#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:04:01.78#ibcon#[27=USB\r\n] 2006.210.08:04:01.78#ibcon#*before write, iclass 6, count 0 2006.210.08:04:01.78#ibcon#enter sib2, iclass 6, count 0 2006.210.08:04:01.78#ibcon#flushed, iclass 6, count 0 2006.210.08:04:01.78#ibcon#about to write, iclass 6, count 0 2006.210.08:04:01.78#ibcon#wrote, iclass 6, count 0 2006.210.08:04:01.78#ibcon#about to read 3, iclass 6, count 0 2006.210.08:04:01.81#ibcon#read 3, iclass 6, count 0 2006.210.08:04:01.81#ibcon#about to read 4, iclass 6, count 0 2006.210.08:04:01.81#ibcon#read 4, iclass 6, count 0 2006.210.08:04:01.81#ibcon#about to read 5, iclass 6, count 0 2006.210.08:04:01.81#ibcon#read 5, iclass 6, count 0 2006.210.08:04:01.81#ibcon#about to read 6, iclass 6, count 0 2006.210.08:04:01.81#ibcon#read 6, iclass 6, count 0 2006.210.08:04:01.81#ibcon#end of sib2, iclass 6, count 0 2006.210.08:04:01.81#ibcon#*after write, iclass 6, count 0 2006.210.08:04:01.81#ibcon#*before return 0, iclass 6, count 0 2006.210.08:04:01.81#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:04:01.81#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:04:01.81#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:04:01.81#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:04:01.81$vc4f8/vblo=6,752.99 2006.210.08:04:01.81#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.08:04:01.81#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.08:04:01.81#ibcon#ireg 17 cls_cnt 0 2006.210.08:04:01.81#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:04:01.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:04:01.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:04:01.81#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:04:01.81#ibcon#first serial, iclass 10, count 0 2006.210.08:04:01.81#ibcon#enter sib2, iclass 10, count 0 2006.210.08:04:01.81#ibcon#flushed, iclass 10, count 0 2006.210.08:04:01.81#ibcon#about to write, iclass 10, count 0 2006.210.08:04:01.81#ibcon#wrote, iclass 10, count 0 2006.210.08:04:01.81#ibcon#about to read 3, iclass 10, count 0 2006.210.08:04:01.83#ibcon#read 3, iclass 10, count 0 2006.210.08:04:01.83#ibcon#about to read 4, iclass 10, count 0 2006.210.08:04:01.83#ibcon#read 4, iclass 10, count 0 2006.210.08:04:01.83#ibcon#about to read 5, iclass 10, count 0 2006.210.08:04:01.83#ibcon#read 5, iclass 10, count 0 2006.210.08:04:01.83#ibcon#about to read 6, iclass 10, count 0 2006.210.08:04:01.83#ibcon#read 6, iclass 10, count 0 2006.210.08:04:01.83#ibcon#end of sib2, iclass 10, count 0 2006.210.08:04:01.83#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:04:01.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:04:01.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:04:01.83#ibcon#*before write, iclass 10, count 0 2006.210.08:04:01.83#ibcon#enter sib2, iclass 10, count 0 2006.210.08:04:01.83#ibcon#flushed, iclass 10, count 0 2006.210.08:04:01.83#ibcon#about to write, iclass 10, count 0 2006.210.08:04:01.83#ibcon#wrote, iclass 10, count 0 2006.210.08:04:01.83#ibcon#about to read 3, iclass 10, count 0 2006.210.08:04:01.87#ibcon#read 3, iclass 10, count 0 2006.210.08:04:01.87#ibcon#about to read 4, iclass 10, count 0 2006.210.08:04:01.87#ibcon#read 4, iclass 10, count 0 2006.210.08:04:01.87#ibcon#about to read 5, iclass 10, count 0 2006.210.08:04:01.87#ibcon#read 5, iclass 10, count 0 2006.210.08:04:01.87#ibcon#about to read 6, iclass 10, count 0 2006.210.08:04:01.87#ibcon#read 6, iclass 10, count 0 2006.210.08:04:01.87#ibcon#end of sib2, iclass 10, count 0 2006.210.08:04:01.87#ibcon#*after write, iclass 10, count 0 2006.210.08:04:01.87#ibcon#*before return 0, iclass 10, count 0 2006.210.08:04:01.87#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:04:01.87#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:04:01.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:04:01.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:04:01.87$vc4f8/vb=6,3 2006.210.08:04:01.87#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.08:04:01.87#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.08:04:01.87#ibcon#ireg 11 cls_cnt 2 2006.210.08:04:01.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:04:01.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:04:01.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:04:01.93#ibcon#enter wrdev, iclass 12, count 2 2006.210.08:04:01.93#ibcon#first serial, iclass 12, count 2 2006.210.08:04:01.93#ibcon#enter sib2, iclass 12, count 2 2006.210.08:04:01.93#ibcon#flushed, iclass 12, count 2 2006.210.08:04:01.93#ibcon#about to write, iclass 12, count 2 2006.210.08:04:01.93#ibcon#wrote, iclass 12, count 2 2006.210.08:04:01.93#ibcon#about to read 3, iclass 12, count 2 2006.210.08:04:01.95#ibcon#read 3, iclass 12, count 2 2006.210.08:04:01.95#ibcon#about to read 4, iclass 12, count 2 2006.210.08:04:01.95#ibcon#read 4, iclass 12, count 2 2006.210.08:04:01.95#ibcon#about to read 5, iclass 12, count 2 2006.210.08:04:01.95#ibcon#read 5, iclass 12, count 2 2006.210.08:04:01.95#ibcon#about to read 6, iclass 12, count 2 2006.210.08:04:01.95#ibcon#read 6, iclass 12, count 2 2006.210.08:04:01.95#ibcon#end of sib2, iclass 12, count 2 2006.210.08:04:01.95#ibcon#*mode == 0, iclass 12, count 2 2006.210.08:04:01.95#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.08:04:01.95#ibcon#[27=AT06-03\r\n] 2006.210.08:04:01.95#ibcon#*before write, iclass 12, count 2 2006.210.08:04:01.95#ibcon#enter sib2, iclass 12, count 2 2006.210.08:04:01.95#ibcon#flushed, iclass 12, count 2 2006.210.08:04:01.95#ibcon#about to write, iclass 12, count 2 2006.210.08:04:01.95#ibcon#wrote, iclass 12, count 2 2006.210.08:04:01.95#ibcon#about to read 3, iclass 12, count 2 2006.210.08:04:01.98#ibcon#read 3, iclass 12, count 2 2006.210.08:04:01.98#ibcon#about to read 4, iclass 12, count 2 2006.210.08:04:01.98#ibcon#read 4, iclass 12, count 2 2006.210.08:04:01.98#ibcon#about to read 5, iclass 12, count 2 2006.210.08:04:01.98#ibcon#read 5, iclass 12, count 2 2006.210.08:04:01.98#ibcon#about to read 6, iclass 12, count 2 2006.210.08:04:01.98#ibcon#read 6, iclass 12, count 2 2006.210.08:04:01.98#ibcon#end of sib2, iclass 12, count 2 2006.210.08:04:01.98#ibcon#*after write, iclass 12, count 2 2006.210.08:04:01.98#ibcon#*before return 0, iclass 12, count 2 2006.210.08:04:01.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:04:01.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:04:01.98#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.08:04:01.98#ibcon#ireg 7 cls_cnt 0 2006.210.08:04:01.98#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:04:02.10#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:04:02.10#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:04:02.10#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:04:02.10#ibcon#first serial, iclass 12, count 0 2006.210.08:04:02.10#ibcon#enter sib2, iclass 12, count 0 2006.210.08:04:02.10#ibcon#flushed, iclass 12, count 0 2006.210.08:04:02.10#ibcon#about to write, iclass 12, count 0 2006.210.08:04:02.10#ibcon#wrote, iclass 12, count 0 2006.210.08:04:02.10#ibcon#about to read 3, iclass 12, count 0 2006.210.08:04:02.12#ibcon#read 3, iclass 12, count 0 2006.210.08:04:02.12#ibcon#about to read 4, iclass 12, count 0 2006.210.08:04:02.12#ibcon#read 4, iclass 12, count 0 2006.210.08:04:02.12#ibcon#about to read 5, iclass 12, count 0 2006.210.08:04:02.12#ibcon#read 5, iclass 12, count 0 2006.210.08:04:02.12#ibcon#about to read 6, iclass 12, count 0 2006.210.08:04:02.12#ibcon#read 6, iclass 12, count 0 2006.210.08:04:02.12#ibcon#end of sib2, iclass 12, count 0 2006.210.08:04:02.12#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:04:02.12#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:04:02.12#ibcon#[27=USB\r\n] 2006.210.08:04:02.12#ibcon#*before write, iclass 12, count 0 2006.210.08:04:02.12#ibcon#enter sib2, iclass 12, count 0 2006.210.08:04:02.12#ibcon#flushed, iclass 12, count 0 2006.210.08:04:02.12#ibcon#about to write, iclass 12, count 0 2006.210.08:04:02.12#ibcon#wrote, iclass 12, count 0 2006.210.08:04:02.12#ibcon#about to read 3, iclass 12, count 0 2006.210.08:04:02.15#ibcon#read 3, iclass 12, count 0 2006.210.08:04:02.15#ibcon#about to read 4, iclass 12, count 0 2006.210.08:04:02.15#ibcon#read 4, iclass 12, count 0 2006.210.08:04:02.15#ibcon#about to read 5, iclass 12, count 0 2006.210.08:04:02.15#ibcon#read 5, iclass 12, count 0 2006.210.08:04:02.15#ibcon#about to read 6, iclass 12, count 0 2006.210.08:04:02.15#ibcon#read 6, iclass 12, count 0 2006.210.08:04:02.15#ibcon#end of sib2, iclass 12, count 0 2006.210.08:04:02.15#ibcon#*after write, iclass 12, count 0 2006.210.08:04:02.15#ibcon#*before return 0, iclass 12, count 0 2006.210.08:04:02.15#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:04:02.15#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:04:02.15#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:04:02.15#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:04:02.15$vc4f8/vabw=wide 2006.210.08:04:02.15#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.08:04:02.15#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.08:04:02.15#ibcon#ireg 8 cls_cnt 0 2006.210.08:04:02.15#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:04:02.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:04:02.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:04:02.15#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:04:02.15#ibcon#first serial, iclass 14, count 0 2006.210.08:04:02.15#ibcon#enter sib2, iclass 14, count 0 2006.210.08:04:02.15#ibcon#flushed, iclass 14, count 0 2006.210.08:04:02.15#ibcon#about to write, iclass 14, count 0 2006.210.08:04:02.15#ibcon#wrote, iclass 14, count 0 2006.210.08:04:02.15#ibcon#about to read 3, iclass 14, count 0 2006.210.08:04:02.17#ibcon#read 3, iclass 14, count 0 2006.210.08:04:02.17#ibcon#about to read 4, iclass 14, count 0 2006.210.08:04:02.17#ibcon#read 4, iclass 14, count 0 2006.210.08:04:02.17#ibcon#about to read 5, iclass 14, count 0 2006.210.08:04:02.17#ibcon#read 5, iclass 14, count 0 2006.210.08:04:02.17#ibcon#about to read 6, iclass 14, count 0 2006.210.08:04:02.17#ibcon#read 6, iclass 14, count 0 2006.210.08:04:02.17#ibcon#end of sib2, iclass 14, count 0 2006.210.08:04:02.17#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:04:02.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:04:02.17#ibcon#[25=BW32\r\n] 2006.210.08:04:02.17#ibcon#*before write, iclass 14, count 0 2006.210.08:04:02.17#ibcon#enter sib2, iclass 14, count 0 2006.210.08:04:02.17#ibcon#flushed, iclass 14, count 0 2006.210.08:04:02.17#ibcon#about to write, iclass 14, count 0 2006.210.08:04:02.17#ibcon#wrote, iclass 14, count 0 2006.210.08:04:02.17#ibcon#about to read 3, iclass 14, count 0 2006.210.08:04:02.20#ibcon#read 3, iclass 14, count 0 2006.210.08:04:02.20#ibcon#about to read 4, iclass 14, count 0 2006.210.08:04:02.20#ibcon#read 4, iclass 14, count 0 2006.210.08:04:02.20#ibcon#about to read 5, iclass 14, count 0 2006.210.08:04:02.20#ibcon#read 5, iclass 14, count 0 2006.210.08:04:02.20#ibcon#about to read 6, iclass 14, count 0 2006.210.08:04:02.20#ibcon#read 6, iclass 14, count 0 2006.210.08:04:02.20#ibcon#end of sib2, iclass 14, count 0 2006.210.08:04:02.20#ibcon#*after write, iclass 14, count 0 2006.210.08:04:02.20#ibcon#*before return 0, iclass 14, count 0 2006.210.08:04:02.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:04:02.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:04:02.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:04:02.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:04:02.20$vc4f8/vbbw=wide 2006.210.08:04:02.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.08:04:02.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.08:04:02.20#ibcon#ireg 8 cls_cnt 0 2006.210.08:04:02.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:04:02.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:04:02.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:04:02.27#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:04:02.27#ibcon#first serial, iclass 16, count 0 2006.210.08:04:02.27#ibcon#enter sib2, iclass 16, count 0 2006.210.08:04:02.27#ibcon#flushed, iclass 16, count 0 2006.210.08:04:02.27#ibcon#about to write, iclass 16, count 0 2006.210.08:04:02.27#ibcon#wrote, iclass 16, count 0 2006.210.08:04:02.27#ibcon#about to read 3, iclass 16, count 0 2006.210.08:04:02.29#ibcon#read 3, iclass 16, count 0 2006.210.08:04:02.29#ibcon#about to read 4, iclass 16, count 0 2006.210.08:04:02.29#ibcon#read 4, iclass 16, count 0 2006.210.08:04:02.29#ibcon#about to read 5, iclass 16, count 0 2006.210.08:04:02.29#ibcon#read 5, iclass 16, count 0 2006.210.08:04:02.29#ibcon#about to read 6, iclass 16, count 0 2006.210.08:04:02.29#ibcon#read 6, iclass 16, count 0 2006.210.08:04:02.29#ibcon#end of sib2, iclass 16, count 0 2006.210.08:04:02.29#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:04:02.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:04:02.29#ibcon#[27=BW32\r\n] 2006.210.08:04:02.29#ibcon#*before write, iclass 16, count 0 2006.210.08:04:02.29#ibcon#enter sib2, iclass 16, count 0 2006.210.08:04:02.29#ibcon#flushed, iclass 16, count 0 2006.210.08:04:02.29#ibcon#about to write, iclass 16, count 0 2006.210.08:04:02.29#ibcon#wrote, iclass 16, count 0 2006.210.08:04:02.29#ibcon#about to read 3, iclass 16, count 0 2006.210.08:04:02.32#ibcon#read 3, iclass 16, count 0 2006.210.08:04:02.32#ibcon#about to read 4, iclass 16, count 0 2006.210.08:04:02.32#ibcon#read 4, iclass 16, count 0 2006.210.08:04:02.32#ibcon#about to read 5, iclass 16, count 0 2006.210.08:04:02.32#ibcon#read 5, iclass 16, count 0 2006.210.08:04:02.32#ibcon#about to read 6, iclass 16, count 0 2006.210.08:04:02.32#ibcon#read 6, iclass 16, count 0 2006.210.08:04:02.32#ibcon#end of sib2, iclass 16, count 0 2006.210.08:04:02.32#ibcon#*after write, iclass 16, count 0 2006.210.08:04:02.32#ibcon#*before return 0, iclass 16, count 0 2006.210.08:04:02.32#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:04:02.32#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:04:02.32#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:04:02.32#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:04:02.32$4f8m12a/ifd4f 2006.210.08:04:02.32$ifd4f/lo= 2006.210.08:04:02.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:04:02.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:04:02.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:04:02.32$ifd4f/patch= 2006.210.08:04:02.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:04:02.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:04:02.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:04:02.32$4f8m12a/"form=m,16.000,1:2 2006.210.08:04:02.32$4f8m12a/"tpicd 2006.210.08:04:02.32$4f8m12a/echo=off 2006.210.08:04:02.32$4f8m12a/xlog=off 2006.210.08:04:02.32:!2006.210.08:04:30 2006.210.08:04:15.14#trakl#Source acquired 2006.210.08:04:15.14#flagr#flagr/antenna,acquired 2006.210.08:04:30.00:preob 2006.210.08:04:31.14/onsource/TRACKING 2006.210.08:04:31.14:!2006.210.08:04:40 2006.210.08:04:40.00:data_valid=on 2006.210.08:04:40.00:midob 2006.210.08:04:40.14/onsource/TRACKING 2006.210.08:04:40.14/wx/30.38,1006.3,81 2006.210.08:04:40.35/cable/+6.3935E-03 2006.210.08:04:41.44/va/01,08,usb,yes,30,31 2006.210.08:04:41.44/va/02,07,usb,yes,30,31 2006.210.08:04:41.44/va/03,06,usb,yes,31,32 2006.210.08:04:41.44/va/04,07,usb,yes,31,33 2006.210.08:04:41.44/va/05,07,usb,yes,32,34 2006.210.08:04:41.44/va/06,06,usb,yes,31,31 2006.210.08:04:41.44/va/07,06,usb,yes,32,31 2006.210.08:04:41.44/va/08,07,usb,yes,30,29 2006.210.08:04:41.67/valo/01,532.99,yes,locked 2006.210.08:04:41.67/valo/02,572.99,yes,locked 2006.210.08:04:41.67/valo/03,672.99,yes,locked 2006.210.08:04:41.67/valo/04,832.99,yes,locked 2006.210.08:04:41.67/valo/05,652.99,yes,locked 2006.210.08:04:41.67/valo/06,772.99,yes,locked 2006.210.08:04:41.67/valo/07,832.99,yes,locked 2006.210.08:04:41.67/valo/08,852.99,yes,locked 2006.210.08:04:42.76/vb/01,04,usb,yes,29,28 2006.210.08:04:42.76/vb/02,04,usb,yes,31,32 2006.210.08:04:42.76/vb/03,03,usb,yes,34,38 2006.210.08:04:42.76/vb/04,03,usb,yes,35,35 2006.210.08:04:42.76/vb/05,03,usb,yes,33,38 2006.210.08:04:42.76/vb/06,03,usb,yes,34,37 2006.210.08:04:42.76/vb/07,04,usb,yes,30,29 2006.210.08:04:42.76/vb/08,03,usb,yes,34,38 2006.210.08:04:43.00/vblo/01,632.99,yes,locked 2006.210.08:04:43.00/vblo/02,640.99,yes,locked 2006.210.08:04:43.00/vblo/03,656.99,yes,locked 2006.210.08:04:43.00/vblo/04,712.99,yes,locked 2006.210.08:04:43.00/vblo/05,744.99,yes,locked 2006.210.08:04:43.00/vblo/06,752.99,yes,locked 2006.210.08:04:43.00/vblo/07,734.99,yes,locked 2006.210.08:04:43.00/vblo/08,744.99,yes,locked 2006.210.08:04:43.15/vabw/8 2006.210.08:04:43.30/vbbw/8 2006.210.08:04:43.39/xfe/off,on,13.2 2006.210.08:04:43.82/ifatt/23,28,28,28 2006.210.08:04:44.08/fmout-gps/S +4.63E-07 2006.210.08:04:44.12:!2006.210.08:05:40 2006.210.08:05:40.00:data_valid=off 2006.210.08:05:40.00:postob 2006.210.08:05:40.15/cable/+6.3931E-03 2006.210.08:05:40.15/wx/30.34,1006.4,81 2006.210.08:05:41.08/fmout-gps/S +4.63E-07 2006.210.08:05:41.08:scan_name=210-0806,k06210,60 2006.210.08:05:41.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.210.08:05:41.13#flagr#flagr/antenna,new-source 2006.210.08:05:42.13:checkk5 2006.210.08:05:42.47/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:05:42.81/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:05:43.15/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:05:43.49/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:05:43.87/chk_obsdata//k5ts1/T2100804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:05:44.20/chk_obsdata//k5ts2/T2100804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:05:44.53/chk_obsdata//k5ts3/T2100804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:05:44.86/chk_obsdata//k5ts4/T2100804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:05:45.52/k5log//k5ts1_log_newline 2006.210.08:05:46.18/k5log//k5ts2_log_newline 2006.210.08:05:46.83/k5log//k5ts3_log_newline 2006.210.08:05:47.49/k5log//k5ts4_log_newline 2006.210.08:05:47.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:05:47.52:4f8m12a=2 2006.210.08:05:47.52$4f8m12a/echo=on 2006.210.08:05:47.52$4f8m12a/pcalon 2006.210.08:05:47.52$pcalon/"no phase cal control is implemented here 2006.210.08:05:47.52$4f8m12a/"tpicd=stop 2006.210.08:05:47.52$4f8m12a/vc4f8 2006.210.08:05:47.52$vc4f8/valo=1,532.99 2006.210.08:05:47.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.08:05:47.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.08:05:47.52#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:47.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:47.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:47.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:47.52#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:05:47.52#ibcon#first serial, iclass 27, count 0 2006.210.08:05:47.52#ibcon#enter sib2, iclass 27, count 0 2006.210.08:05:47.52#ibcon#flushed, iclass 27, count 0 2006.210.08:05:47.52#ibcon#about to write, iclass 27, count 0 2006.210.08:05:47.52#ibcon#wrote, iclass 27, count 0 2006.210.08:05:47.52#ibcon#about to read 3, iclass 27, count 0 2006.210.08:05:47.54#ibcon#read 3, iclass 27, count 0 2006.210.08:05:47.54#ibcon#about to read 4, iclass 27, count 0 2006.210.08:05:47.54#ibcon#read 4, iclass 27, count 0 2006.210.08:05:47.54#ibcon#about to read 5, iclass 27, count 0 2006.210.08:05:47.54#ibcon#read 5, iclass 27, count 0 2006.210.08:05:47.54#ibcon#about to read 6, iclass 27, count 0 2006.210.08:05:47.54#ibcon#read 6, iclass 27, count 0 2006.210.08:05:47.54#ibcon#end of sib2, iclass 27, count 0 2006.210.08:05:47.54#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:05:47.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:05:47.54#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:05:47.54#ibcon#*before write, iclass 27, count 0 2006.210.08:05:47.54#ibcon#enter sib2, iclass 27, count 0 2006.210.08:05:47.54#ibcon#flushed, iclass 27, count 0 2006.210.08:05:47.54#ibcon#about to write, iclass 27, count 0 2006.210.08:05:47.54#ibcon#wrote, iclass 27, count 0 2006.210.08:05:47.54#ibcon#about to read 3, iclass 27, count 0 2006.210.08:05:47.59#ibcon#read 3, iclass 27, count 0 2006.210.08:05:47.59#ibcon#about to read 4, iclass 27, count 0 2006.210.08:05:47.59#ibcon#read 4, iclass 27, count 0 2006.210.08:05:47.59#ibcon#about to read 5, iclass 27, count 0 2006.210.08:05:47.59#ibcon#read 5, iclass 27, count 0 2006.210.08:05:47.59#ibcon#about to read 6, iclass 27, count 0 2006.210.08:05:47.59#ibcon#read 6, iclass 27, count 0 2006.210.08:05:47.59#ibcon#end of sib2, iclass 27, count 0 2006.210.08:05:47.59#ibcon#*after write, iclass 27, count 0 2006.210.08:05:47.59#ibcon#*before return 0, iclass 27, count 0 2006.210.08:05:47.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:47.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:47.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:05:47.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:05:47.59$vc4f8/va=1,8 2006.210.08:05:47.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.08:05:47.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.08:05:47.59#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:47.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:47.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:47.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:47.59#ibcon#enter wrdev, iclass 29, count 2 2006.210.08:05:47.59#ibcon#first serial, iclass 29, count 2 2006.210.08:05:47.59#ibcon#enter sib2, iclass 29, count 2 2006.210.08:05:47.59#ibcon#flushed, iclass 29, count 2 2006.210.08:05:47.59#ibcon#about to write, iclass 29, count 2 2006.210.08:05:47.59#ibcon#wrote, iclass 29, count 2 2006.210.08:05:47.59#ibcon#about to read 3, iclass 29, count 2 2006.210.08:05:47.61#ibcon#read 3, iclass 29, count 2 2006.210.08:05:47.61#ibcon#about to read 4, iclass 29, count 2 2006.210.08:05:47.61#ibcon#read 4, iclass 29, count 2 2006.210.08:05:47.61#ibcon#about to read 5, iclass 29, count 2 2006.210.08:05:47.61#ibcon#read 5, iclass 29, count 2 2006.210.08:05:47.61#ibcon#about to read 6, iclass 29, count 2 2006.210.08:05:47.61#ibcon#read 6, iclass 29, count 2 2006.210.08:05:47.61#ibcon#end of sib2, iclass 29, count 2 2006.210.08:05:47.61#ibcon#*mode == 0, iclass 29, count 2 2006.210.08:05:47.61#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.08:05:47.61#ibcon#[25=AT01-08\r\n] 2006.210.08:05:47.61#ibcon#*before write, iclass 29, count 2 2006.210.08:05:47.61#ibcon#enter sib2, iclass 29, count 2 2006.210.08:05:47.61#ibcon#flushed, iclass 29, count 2 2006.210.08:05:47.61#ibcon#about to write, iclass 29, count 2 2006.210.08:05:47.61#ibcon#wrote, iclass 29, count 2 2006.210.08:05:47.61#ibcon#about to read 3, iclass 29, count 2 2006.210.08:05:47.64#ibcon#read 3, iclass 29, count 2 2006.210.08:05:47.64#ibcon#about to read 4, iclass 29, count 2 2006.210.08:05:47.64#ibcon#read 4, iclass 29, count 2 2006.210.08:05:47.64#ibcon#about to read 5, iclass 29, count 2 2006.210.08:05:47.64#ibcon#read 5, iclass 29, count 2 2006.210.08:05:47.64#ibcon#about to read 6, iclass 29, count 2 2006.210.08:05:47.64#ibcon#read 6, iclass 29, count 2 2006.210.08:05:47.64#ibcon#end of sib2, iclass 29, count 2 2006.210.08:05:47.64#ibcon#*after write, iclass 29, count 2 2006.210.08:05:47.64#ibcon#*before return 0, iclass 29, count 2 2006.210.08:05:47.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:47.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:47.64#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.08:05:47.64#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:47.64#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:47.76#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:47.76#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:47.76#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:05:47.76#ibcon#first serial, iclass 29, count 0 2006.210.08:05:47.76#ibcon#enter sib2, iclass 29, count 0 2006.210.08:05:47.76#ibcon#flushed, iclass 29, count 0 2006.210.08:05:47.76#ibcon#about to write, iclass 29, count 0 2006.210.08:05:47.76#ibcon#wrote, iclass 29, count 0 2006.210.08:05:47.76#ibcon#about to read 3, iclass 29, count 0 2006.210.08:05:47.78#ibcon#read 3, iclass 29, count 0 2006.210.08:05:47.78#ibcon#about to read 4, iclass 29, count 0 2006.210.08:05:47.78#ibcon#read 4, iclass 29, count 0 2006.210.08:05:47.78#ibcon#about to read 5, iclass 29, count 0 2006.210.08:05:47.78#ibcon#read 5, iclass 29, count 0 2006.210.08:05:47.78#ibcon#about to read 6, iclass 29, count 0 2006.210.08:05:47.78#ibcon#read 6, iclass 29, count 0 2006.210.08:05:47.78#ibcon#end of sib2, iclass 29, count 0 2006.210.08:05:47.78#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:05:47.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:05:47.78#ibcon#[25=USB\r\n] 2006.210.08:05:47.78#ibcon#*before write, iclass 29, count 0 2006.210.08:05:47.78#ibcon#enter sib2, iclass 29, count 0 2006.210.08:05:47.78#ibcon#flushed, iclass 29, count 0 2006.210.08:05:47.78#ibcon#about to write, iclass 29, count 0 2006.210.08:05:47.78#ibcon#wrote, iclass 29, count 0 2006.210.08:05:47.78#ibcon#about to read 3, iclass 29, count 0 2006.210.08:05:47.81#ibcon#read 3, iclass 29, count 0 2006.210.08:05:47.81#ibcon#about to read 4, iclass 29, count 0 2006.210.08:05:47.81#ibcon#read 4, iclass 29, count 0 2006.210.08:05:47.81#ibcon#about to read 5, iclass 29, count 0 2006.210.08:05:47.81#ibcon#read 5, iclass 29, count 0 2006.210.08:05:47.81#ibcon#about to read 6, iclass 29, count 0 2006.210.08:05:47.81#ibcon#read 6, iclass 29, count 0 2006.210.08:05:47.81#ibcon#end of sib2, iclass 29, count 0 2006.210.08:05:47.81#ibcon#*after write, iclass 29, count 0 2006.210.08:05:47.81#ibcon#*before return 0, iclass 29, count 0 2006.210.08:05:47.81#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:47.81#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:47.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:05:47.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:05:47.81$vc4f8/valo=2,572.99 2006.210.08:05:47.81#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.08:05:47.81#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.08:05:47.81#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:47.81#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:47.81#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:47.81#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:47.81#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:05:47.81#ibcon#first serial, iclass 31, count 0 2006.210.08:05:47.81#ibcon#enter sib2, iclass 31, count 0 2006.210.08:05:47.81#ibcon#flushed, iclass 31, count 0 2006.210.08:05:47.81#ibcon#about to write, iclass 31, count 0 2006.210.08:05:47.81#ibcon#wrote, iclass 31, count 0 2006.210.08:05:47.81#ibcon#about to read 3, iclass 31, count 0 2006.210.08:05:47.83#ibcon#read 3, iclass 31, count 0 2006.210.08:05:47.83#ibcon#about to read 4, iclass 31, count 0 2006.210.08:05:47.83#ibcon#read 4, iclass 31, count 0 2006.210.08:05:47.83#ibcon#about to read 5, iclass 31, count 0 2006.210.08:05:47.83#ibcon#read 5, iclass 31, count 0 2006.210.08:05:47.83#ibcon#about to read 6, iclass 31, count 0 2006.210.08:05:47.83#ibcon#read 6, iclass 31, count 0 2006.210.08:05:47.83#ibcon#end of sib2, iclass 31, count 0 2006.210.08:05:47.83#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:05:47.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:05:47.83#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:05:47.83#ibcon#*before write, iclass 31, count 0 2006.210.08:05:47.83#ibcon#enter sib2, iclass 31, count 0 2006.210.08:05:47.83#ibcon#flushed, iclass 31, count 0 2006.210.08:05:47.83#ibcon#about to write, iclass 31, count 0 2006.210.08:05:47.83#ibcon#wrote, iclass 31, count 0 2006.210.08:05:47.83#ibcon#about to read 3, iclass 31, count 0 2006.210.08:05:47.87#ibcon#read 3, iclass 31, count 0 2006.210.08:05:47.87#ibcon#about to read 4, iclass 31, count 0 2006.210.08:05:47.87#ibcon#read 4, iclass 31, count 0 2006.210.08:05:47.87#ibcon#about to read 5, iclass 31, count 0 2006.210.08:05:47.87#ibcon#read 5, iclass 31, count 0 2006.210.08:05:47.87#ibcon#about to read 6, iclass 31, count 0 2006.210.08:05:47.87#ibcon#read 6, iclass 31, count 0 2006.210.08:05:47.87#ibcon#end of sib2, iclass 31, count 0 2006.210.08:05:47.87#ibcon#*after write, iclass 31, count 0 2006.210.08:05:47.87#ibcon#*before return 0, iclass 31, count 0 2006.210.08:05:47.87#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:47.87#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:47.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:05:47.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:05:47.87$vc4f8/va=2,7 2006.210.08:05:47.87#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.08:05:47.87#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.08:05:47.87#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:47.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:47.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:47.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:47.93#ibcon#enter wrdev, iclass 33, count 2 2006.210.08:05:47.93#ibcon#first serial, iclass 33, count 2 2006.210.08:05:47.93#ibcon#enter sib2, iclass 33, count 2 2006.210.08:05:47.93#ibcon#flushed, iclass 33, count 2 2006.210.08:05:47.93#ibcon#about to write, iclass 33, count 2 2006.210.08:05:47.93#ibcon#wrote, iclass 33, count 2 2006.210.08:05:47.93#ibcon#about to read 3, iclass 33, count 2 2006.210.08:05:47.95#ibcon#read 3, iclass 33, count 2 2006.210.08:05:47.95#ibcon#about to read 4, iclass 33, count 2 2006.210.08:05:47.95#ibcon#read 4, iclass 33, count 2 2006.210.08:05:47.95#ibcon#about to read 5, iclass 33, count 2 2006.210.08:05:47.95#ibcon#read 5, iclass 33, count 2 2006.210.08:05:47.95#ibcon#about to read 6, iclass 33, count 2 2006.210.08:05:47.95#ibcon#read 6, iclass 33, count 2 2006.210.08:05:47.95#ibcon#end of sib2, iclass 33, count 2 2006.210.08:05:47.95#ibcon#*mode == 0, iclass 33, count 2 2006.210.08:05:47.95#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.08:05:47.95#ibcon#[25=AT02-07\r\n] 2006.210.08:05:47.95#ibcon#*before write, iclass 33, count 2 2006.210.08:05:47.95#ibcon#enter sib2, iclass 33, count 2 2006.210.08:05:47.95#ibcon#flushed, iclass 33, count 2 2006.210.08:05:47.95#ibcon#about to write, iclass 33, count 2 2006.210.08:05:47.95#ibcon#wrote, iclass 33, count 2 2006.210.08:05:47.95#ibcon#about to read 3, iclass 33, count 2 2006.210.08:05:47.98#ibcon#read 3, iclass 33, count 2 2006.210.08:05:47.98#ibcon#about to read 4, iclass 33, count 2 2006.210.08:05:47.98#ibcon#read 4, iclass 33, count 2 2006.210.08:05:47.98#ibcon#about to read 5, iclass 33, count 2 2006.210.08:05:47.98#ibcon#read 5, iclass 33, count 2 2006.210.08:05:47.98#ibcon#about to read 6, iclass 33, count 2 2006.210.08:05:47.98#ibcon#read 6, iclass 33, count 2 2006.210.08:05:47.98#ibcon#end of sib2, iclass 33, count 2 2006.210.08:05:47.98#ibcon#*after write, iclass 33, count 2 2006.210.08:05:47.98#ibcon#*before return 0, iclass 33, count 2 2006.210.08:05:47.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:47.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:47.98#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.08:05:47.98#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:47.98#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:48.10#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:48.10#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:48.10#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:05:48.10#ibcon#first serial, iclass 33, count 0 2006.210.08:05:48.10#ibcon#enter sib2, iclass 33, count 0 2006.210.08:05:48.10#ibcon#flushed, iclass 33, count 0 2006.210.08:05:48.10#ibcon#about to write, iclass 33, count 0 2006.210.08:05:48.10#ibcon#wrote, iclass 33, count 0 2006.210.08:05:48.10#ibcon#about to read 3, iclass 33, count 0 2006.210.08:05:48.12#ibcon#read 3, iclass 33, count 0 2006.210.08:05:48.12#ibcon#about to read 4, iclass 33, count 0 2006.210.08:05:48.12#ibcon#read 4, iclass 33, count 0 2006.210.08:05:48.12#ibcon#about to read 5, iclass 33, count 0 2006.210.08:05:48.12#ibcon#read 5, iclass 33, count 0 2006.210.08:05:48.12#ibcon#about to read 6, iclass 33, count 0 2006.210.08:05:48.12#ibcon#read 6, iclass 33, count 0 2006.210.08:05:48.12#ibcon#end of sib2, iclass 33, count 0 2006.210.08:05:48.12#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:05:48.12#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:05:48.12#ibcon#[25=USB\r\n] 2006.210.08:05:48.12#ibcon#*before write, iclass 33, count 0 2006.210.08:05:48.12#ibcon#enter sib2, iclass 33, count 0 2006.210.08:05:48.12#ibcon#flushed, iclass 33, count 0 2006.210.08:05:48.12#ibcon#about to write, iclass 33, count 0 2006.210.08:05:48.12#ibcon#wrote, iclass 33, count 0 2006.210.08:05:48.12#ibcon#about to read 3, iclass 33, count 0 2006.210.08:05:48.15#ibcon#read 3, iclass 33, count 0 2006.210.08:05:48.15#ibcon#about to read 4, iclass 33, count 0 2006.210.08:05:48.15#ibcon#read 4, iclass 33, count 0 2006.210.08:05:48.15#ibcon#about to read 5, iclass 33, count 0 2006.210.08:05:48.15#ibcon#read 5, iclass 33, count 0 2006.210.08:05:48.15#ibcon#about to read 6, iclass 33, count 0 2006.210.08:05:48.15#ibcon#read 6, iclass 33, count 0 2006.210.08:05:48.15#ibcon#end of sib2, iclass 33, count 0 2006.210.08:05:48.15#ibcon#*after write, iclass 33, count 0 2006.210.08:05:48.15#ibcon#*before return 0, iclass 33, count 0 2006.210.08:05:48.15#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:48.15#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:48.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:05:48.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:05:48.15$vc4f8/valo=3,672.99 2006.210.08:05:48.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:05:48.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:05:48.15#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:48.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:48.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:48.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:48.15#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:05:48.15#ibcon#first serial, iclass 35, count 0 2006.210.08:05:48.15#ibcon#enter sib2, iclass 35, count 0 2006.210.08:05:48.15#ibcon#flushed, iclass 35, count 0 2006.210.08:05:48.15#ibcon#about to write, iclass 35, count 0 2006.210.08:05:48.15#ibcon#wrote, iclass 35, count 0 2006.210.08:05:48.15#ibcon#about to read 3, iclass 35, count 0 2006.210.08:05:48.17#ibcon#read 3, iclass 35, count 0 2006.210.08:05:48.17#ibcon#about to read 4, iclass 35, count 0 2006.210.08:05:48.17#ibcon#read 4, iclass 35, count 0 2006.210.08:05:48.17#ibcon#about to read 5, iclass 35, count 0 2006.210.08:05:48.17#ibcon#read 5, iclass 35, count 0 2006.210.08:05:48.17#ibcon#about to read 6, iclass 35, count 0 2006.210.08:05:48.17#ibcon#read 6, iclass 35, count 0 2006.210.08:05:48.17#ibcon#end of sib2, iclass 35, count 0 2006.210.08:05:48.17#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:05:48.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:05:48.17#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:05:48.17#ibcon#*before write, iclass 35, count 0 2006.210.08:05:48.17#ibcon#enter sib2, iclass 35, count 0 2006.210.08:05:48.17#ibcon#flushed, iclass 35, count 0 2006.210.08:05:48.17#ibcon#about to write, iclass 35, count 0 2006.210.08:05:48.17#ibcon#wrote, iclass 35, count 0 2006.210.08:05:48.17#ibcon#about to read 3, iclass 35, count 0 2006.210.08:05:48.21#ibcon#read 3, iclass 35, count 0 2006.210.08:05:48.21#ibcon#about to read 4, iclass 35, count 0 2006.210.08:05:48.21#ibcon#read 4, iclass 35, count 0 2006.210.08:05:48.21#ibcon#about to read 5, iclass 35, count 0 2006.210.08:05:48.21#ibcon#read 5, iclass 35, count 0 2006.210.08:05:48.21#ibcon#about to read 6, iclass 35, count 0 2006.210.08:05:48.21#ibcon#read 6, iclass 35, count 0 2006.210.08:05:48.21#ibcon#end of sib2, iclass 35, count 0 2006.210.08:05:48.21#ibcon#*after write, iclass 35, count 0 2006.210.08:05:48.21#ibcon#*before return 0, iclass 35, count 0 2006.210.08:05:48.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:48.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:48.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:05:48.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:05:48.21$vc4f8/va=3,6 2006.210.08:05:48.21#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.08:05:48.21#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.08:05:48.21#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:48.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:48.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:48.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:48.27#ibcon#enter wrdev, iclass 37, count 2 2006.210.08:05:48.27#ibcon#first serial, iclass 37, count 2 2006.210.08:05:48.27#ibcon#enter sib2, iclass 37, count 2 2006.210.08:05:48.27#ibcon#flushed, iclass 37, count 2 2006.210.08:05:48.27#ibcon#about to write, iclass 37, count 2 2006.210.08:05:48.27#ibcon#wrote, iclass 37, count 2 2006.210.08:05:48.27#ibcon#about to read 3, iclass 37, count 2 2006.210.08:05:48.29#ibcon#read 3, iclass 37, count 2 2006.210.08:05:48.29#ibcon#about to read 4, iclass 37, count 2 2006.210.08:05:48.29#ibcon#read 4, iclass 37, count 2 2006.210.08:05:48.29#ibcon#about to read 5, iclass 37, count 2 2006.210.08:05:48.29#ibcon#read 5, iclass 37, count 2 2006.210.08:05:48.29#ibcon#about to read 6, iclass 37, count 2 2006.210.08:05:48.29#ibcon#read 6, iclass 37, count 2 2006.210.08:05:48.29#ibcon#end of sib2, iclass 37, count 2 2006.210.08:05:48.29#ibcon#*mode == 0, iclass 37, count 2 2006.210.08:05:48.29#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.08:05:48.29#ibcon#[25=AT03-06\r\n] 2006.210.08:05:48.29#ibcon#*before write, iclass 37, count 2 2006.210.08:05:48.29#ibcon#enter sib2, iclass 37, count 2 2006.210.08:05:48.29#ibcon#flushed, iclass 37, count 2 2006.210.08:05:48.29#ibcon#about to write, iclass 37, count 2 2006.210.08:05:48.29#ibcon#wrote, iclass 37, count 2 2006.210.08:05:48.29#ibcon#about to read 3, iclass 37, count 2 2006.210.08:05:48.32#ibcon#read 3, iclass 37, count 2 2006.210.08:05:48.32#ibcon#about to read 4, iclass 37, count 2 2006.210.08:05:48.32#ibcon#read 4, iclass 37, count 2 2006.210.08:05:48.32#ibcon#about to read 5, iclass 37, count 2 2006.210.08:05:48.32#ibcon#read 5, iclass 37, count 2 2006.210.08:05:48.32#ibcon#about to read 6, iclass 37, count 2 2006.210.08:05:48.32#ibcon#read 6, iclass 37, count 2 2006.210.08:05:48.32#ibcon#end of sib2, iclass 37, count 2 2006.210.08:05:48.32#ibcon#*after write, iclass 37, count 2 2006.210.08:05:48.32#ibcon#*before return 0, iclass 37, count 2 2006.210.08:05:48.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:48.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:48.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.08:05:48.32#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:48.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:48.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:48.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:48.44#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:05:48.44#ibcon#first serial, iclass 37, count 0 2006.210.08:05:48.44#ibcon#enter sib2, iclass 37, count 0 2006.210.08:05:48.44#ibcon#flushed, iclass 37, count 0 2006.210.08:05:48.44#ibcon#about to write, iclass 37, count 0 2006.210.08:05:48.44#ibcon#wrote, iclass 37, count 0 2006.210.08:05:48.44#ibcon#about to read 3, iclass 37, count 0 2006.210.08:05:48.46#ibcon#read 3, iclass 37, count 0 2006.210.08:05:48.46#ibcon#about to read 4, iclass 37, count 0 2006.210.08:05:48.46#ibcon#read 4, iclass 37, count 0 2006.210.08:05:48.46#ibcon#about to read 5, iclass 37, count 0 2006.210.08:05:48.46#ibcon#read 5, iclass 37, count 0 2006.210.08:05:48.46#ibcon#about to read 6, iclass 37, count 0 2006.210.08:05:48.46#ibcon#read 6, iclass 37, count 0 2006.210.08:05:48.46#ibcon#end of sib2, iclass 37, count 0 2006.210.08:05:48.46#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:05:48.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:05:48.46#ibcon#[25=USB\r\n] 2006.210.08:05:48.46#ibcon#*before write, iclass 37, count 0 2006.210.08:05:48.46#ibcon#enter sib2, iclass 37, count 0 2006.210.08:05:48.46#ibcon#flushed, iclass 37, count 0 2006.210.08:05:48.46#ibcon#about to write, iclass 37, count 0 2006.210.08:05:48.46#ibcon#wrote, iclass 37, count 0 2006.210.08:05:48.46#ibcon#about to read 3, iclass 37, count 0 2006.210.08:05:48.49#ibcon#read 3, iclass 37, count 0 2006.210.08:05:48.49#ibcon#about to read 4, iclass 37, count 0 2006.210.08:05:48.49#ibcon#read 4, iclass 37, count 0 2006.210.08:05:48.49#ibcon#about to read 5, iclass 37, count 0 2006.210.08:05:48.49#ibcon#read 5, iclass 37, count 0 2006.210.08:05:48.49#ibcon#about to read 6, iclass 37, count 0 2006.210.08:05:48.49#ibcon#read 6, iclass 37, count 0 2006.210.08:05:48.49#ibcon#end of sib2, iclass 37, count 0 2006.210.08:05:48.49#ibcon#*after write, iclass 37, count 0 2006.210.08:05:48.49#ibcon#*before return 0, iclass 37, count 0 2006.210.08:05:48.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:48.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:48.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:05:48.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:05:48.49$vc4f8/valo=4,832.99 2006.210.08:05:48.49#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.08:05:48.49#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.08:05:48.49#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:48.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:48.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:48.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:48.49#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:05:48.49#ibcon#first serial, iclass 39, count 0 2006.210.08:05:48.49#ibcon#enter sib2, iclass 39, count 0 2006.210.08:05:48.49#ibcon#flushed, iclass 39, count 0 2006.210.08:05:48.49#ibcon#about to write, iclass 39, count 0 2006.210.08:05:48.49#ibcon#wrote, iclass 39, count 0 2006.210.08:05:48.49#ibcon#about to read 3, iclass 39, count 0 2006.210.08:05:48.51#ibcon#read 3, iclass 39, count 0 2006.210.08:05:48.51#ibcon#about to read 4, iclass 39, count 0 2006.210.08:05:48.51#ibcon#read 4, iclass 39, count 0 2006.210.08:05:48.51#ibcon#about to read 5, iclass 39, count 0 2006.210.08:05:48.51#ibcon#read 5, iclass 39, count 0 2006.210.08:05:48.51#ibcon#about to read 6, iclass 39, count 0 2006.210.08:05:48.51#ibcon#read 6, iclass 39, count 0 2006.210.08:05:48.51#ibcon#end of sib2, iclass 39, count 0 2006.210.08:05:48.51#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:05:48.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:05:48.51#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:05:48.51#ibcon#*before write, iclass 39, count 0 2006.210.08:05:48.51#ibcon#enter sib2, iclass 39, count 0 2006.210.08:05:48.51#ibcon#flushed, iclass 39, count 0 2006.210.08:05:48.51#ibcon#about to write, iclass 39, count 0 2006.210.08:05:48.51#ibcon#wrote, iclass 39, count 0 2006.210.08:05:48.51#ibcon#about to read 3, iclass 39, count 0 2006.210.08:05:48.55#ibcon#read 3, iclass 39, count 0 2006.210.08:05:48.55#ibcon#about to read 4, iclass 39, count 0 2006.210.08:05:48.55#ibcon#read 4, iclass 39, count 0 2006.210.08:05:48.55#ibcon#about to read 5, iclass 39, count 0 2006.210.08:05:48.55#ibcon#read 5, iclass 39, count 0 2006.210.08:05:48.55#ibcon#about to read 6, iclass 39, count 0 2006.210.08:05:48.55#ibcon#read 6, iclass 39, count 0 2006.210.08:05:48.55#ibcon#end of sib2, iclass 39, count 0 2006.210.08:05:48.55#ibcon#*after write, iclass 39, count 0 2006.210.08:05:48.55#ibcon#*before return 0, iclass 39, count 0 2006.210.08:05:48.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:48.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:48.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:05:48.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:05:48.55$vc4f8/va=4,7 2006.210.08:05:48.55#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.08:05:48.55#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.08:05:48.55#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:48.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:48.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:48.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:48.61#ibcon#enter wrdev, iclass 3, count 2 2006.210.08:05:48.61#ibcon#first serial, iclass 3, count 2 2006.210.08:05:48.61#ibcon#enter sib2, iclass 3, count 2 2006.210.08:05:48.61#ibcon#flushed, iclass 3, count 2 2006.210.08:05:48.61#ibcon#about to write, iclass 3, count 2 2006.210.08:05:48.61#ibcon#wrote, iclass 3, count 2 2006.210.08:05:48.61#ibcon#about to read 3, iclass 3, count 2 2006.210.08:05:48.63#ibcon#read 3, iclass 3, count 2 2006.210.08:05:48.63#ibcon#about to read 4, iclass 3, count 2 2006.210.08:05:48.63#ibcon#read 4, iclass 3, count 2 2006.210.08:05:48.63#ibcon#about to read 5, iclass 3, count 2 2006.210.08:05:48.63#ibcon#read 5, iclass 3, count 2 2006.210.08:05:48.63#ibcon#about to read 6, iclass 3, count 2 2006.210.08:05:48.63#ibcon#read 6, iclass 3, count 2 2006.210.08:05:48.63#ibcon#end of sib2, iclass 3, count 2 2006.210.08:05:48.63#ibcon#*mode == 0, iclass 3, count 2 2006.210.08:05:48.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.08:05:48.63#ibcon#[25=AT04-07\r\n] 2006.210.08:05:48.63#ibcon#*before write, iclass 3, count 2 2006.210.08:05:48.63#ibcon#enter sib2, iclass 3, count 2 2006.210.08:05:48.63#ibcon#flushed, iclass 3, count 2 2006.210.08:05:48.63#ibcon#about to write, iclass 3, count 2 2006.210.08:05:48.63#ibcon#wrote, iclass 3, count 2 2006.210.08:05:48.63#ibcon#about to read 3, iclass 3, count 2 2006.210.08:05:48.66#ibcon#read 3, iclass 3, count 2 2006.210.08:05:48.66#ibcon#about to read 4, iclass 3, count 2 2006.210.08:05:48.66#ibcon#read 4, iclass 3, count 2 2006.210.08:05:48.66#ibcon#about to read 5, iclass 3, count 2 2006.210.08:05:48.66#ibcon#read 5, iclass 3, count 2 2006.210.08:05:48.66#ibcon#about to read 6, iclass 3, count 2 2006.210.08:05:48.66#ibcon#read 6, iclass 3, count 2 2006.210.08:05:48.66#ibcon#end of sib2, iclass 3, count 2 2006.210.08:05:48.66#ibcon#*after write, iclass 3, count 2 2006.210.08:05:48.66#ibcon#*before return 0, iclass 3, count 2 2006.210.08:05:48.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:48.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:48.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.08:05:48.66#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:48.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:48.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:48.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:48.78#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:05:48.78#ibcon#first serial, iclass 3, count 0 2006.210.08:05:48.78#ibcon#enter sib2, iclass 3, count 0 2006.210.08:05:48.78#ibcon#flushed, iclass 3, count 0 2006.210.08:05:48.78#ibcon#about to write, iclass 3, count 0 2006.210.08:05:48.78#ibcon#wrote, iclass 3, count 0 2006.210.08:05:48.78#ibcon#about to read 3, iclass 3, count 0 2006.210.08:05:48.80#ibcon#read 3, iclass 3, count 0 2006.210.08:05:48.80#ibcon#about to read 4, iclass 3, count 0 2006.210.08:05:48.80#ibcon#read 4, iclass 3, count 0 2006.210.08:05:48.80#ibcon#about to read 5, iclass 3, count 0 2006.210.08:05:48.80#ibcon#read 5, iclass 3, count 0 2006.210.08:05:48.80#ibcon#about to read 6, iclass 3, count 0 2006.210.08:05:48.80#ibcon#read 6, iclass 3, count 0 2006.210.08:05:48.80#ibcon#end of sib2, iclass 3, count 0 2006.210.08:05:48.80#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:05:48.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:05:48.80#ibcon#[25=USB\r\n] 2006.210.08:05:48.80#ibcon#*before write, iclass 3, count 0 2006.210.08:05:48.80#ibcon#enter sib2, iclass 3, count 0 2006.210.08:05:48.80#ibcon#flushed, iclass 3, count 0 2006.210.08:05:48.80#ibcon#about to write, iclass 3, count 0 2006.210.08:05:48.80#ibcon#wrote, iclass 3, count 0 2006.210.08:05:48.80#ibcon#about to read 3, iclass 3, count 0 2006.210.08:05:48.83#ibcon#read 3, iclass 3, count 0 2006.210.08:05:48.83#ibcon#about to read 4, iclass 3, count 0 2006.210.08:05:48.83#ibcon#read 4, iclass 3, count 0 2006.210.08:05:48.83#ibcon#about to read 5, iclass 3, count 0 2006.210.08:05:48.83#ibcon#read 5, iclass 3, count 0 2006.210.08:05:48.83#ibcon#about to read 6, iclass 3, count 0 2006.210.08:05:48.83#ibcon#read 6, iclass 3, count 0 2006.210.08:05:48.83#ibcon#end of sib2, iclass 3, count 0 2006.210.08:05:48.83#ibcon#*after write, iclass 3, count 0 2006.210.08:05:48.83#ibcon#*before return 0, iclass 3, count 0 2006.210.08:05:48.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:48.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:48.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:05:48.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:05:48.83$vc4f8/valo=5,652.99 2006.210.08:05:48.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.08:05:48.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.08:05:48.83#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:48.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:48.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:48.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:48.83#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:05:48.83#ibcon#first serial, iclass 5, count 0 2006.210.08:05:48.83#ibcon#enter sib2, iclass 5, count 0 2006.210.08:05:48.83#ibcon#flushed, iclass 5, count 0 2006.210.08:05:48.83#ibcon#about to write, iclass 5, count 0 2006.210.08:05:48.83#ibcon#wrote, iclass 5, count 0 2006.210.08:05:48.83#ibcon#about to read 3, iclass 5, count 0 2006.210.08:05:48.85#ibcon#read 3, iclass 5, count 0 2006.210.08:05:48.85#ibcon#about to read 4, iclass 5, count 0 2006.210.08:05:48.85#ibcon#read 4, iclass 5, count 0 2006.210.08:05:48.85#ibcon#about to read 5, iclass 5, count 0 2006.210.08:05:48.85#ibcon#read 5, iclass 5, count 0 2006.210.08:05:48.85#ibcon#about to read 6, iclass 5, count 0 2006.210.08:05:48.85#ibcon#read 6, iclass 5, count 0 2006.210.08:05:48.85#ibcon#end of sib2, iclass 5, count 0 2006.210.08:05:48.85#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:05:48.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:05:48.85#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:05:48.85#ibcon#*before write, iclass 5, count 0 2006.210.08:05:48.85#ibcon#enter sib2, iclass 5, count 0 2006.210.08:05:48.85#ibcon#flushed, iclass 5, count 0 2006.210.08:05:48.85#ibcon#about to write, iclass 5, count 0 2006.210.08:05:48.85#ibcon#wrote, iclass 5, count 0 2006.210.08:05:48.85#ibcon#about to read 3, iclass 5, count 0 2006.210.08:05:48.89#ibcon#read 3, iclass 5, count 0 2006.210.08:05:48.89#ibcon#about to read 4, iclass 5, count 0 2006.210.08:05:48.89#ibcon#read 4, iclass 5, count 0 2006.210.08:05:48.89#ibcon#about to read 5, iclass 5, count 0 2006.210.08:05:48.89#ibcon#read 5, iclass 5, count 0 2006.210.08:05:48.89#ibcon#about to read 6, iclass 5, count 0 2006.210.08:05:48.89#ibcon#read 6, iclass 5, count 0 2006.210.08:05:48.89#ibcon#end of sib2, iclass 5, count 0 2006.210.08:05:48.89#ibcon#*after write, iclass 5, count 0 2006.210.08:05:48.89#ibcon#*before return 0, iclass 5, count 0 2006.210.08:05:48.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:48.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:48.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:05:48.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:05:48.89$vc4f8/va=5,7 2006.210.08:05:48.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.08:05:48.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.08:05:48.89#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:48.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:48.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:48.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:48.95#ibcon#enter wrdev, iclass 7, count 2 2006.210.08:05:48.95#ibcon#first serial, iclass 7, count 2 2006.210.08:05:48.95#ibcon#enter sib2, iclass 7, count 2 2006.210.08:05:48.95#ibcon#flushed, iclass 7, count 2 2006.210.08:05:48.95#ibcon#about to write, iclass 7, count 2 2006.210.08:05:48.95#ibcon#wrote, iclass 7, count 2 2006.210.08:05:48.95#ibcon#about to read 3, iclass 7, count 2 2006.210.08:05:48.97#ibcon#read 3, iclass 7, count 2 2006.210.08:05:48.97#ibcon#about to read 4, iclass 7, count 2 2006.210.08:05:48.97#ibcon#read 4, iclass 7, count 2 2006.210.08:05:48.97#ibcon#about to read 5, iclass 7, count 2 2006.210.08:05:48.97#ibcon#read 5, iclass 7, count 2 2006.210.08:05:48.97#ibcon#about to read 6, iclass 7, count 2 2006.210.08:05:48.97#ibcon#read 6, iclass 7, count 2 2006.210.08:05:48.97#ibcon#end of sib2, iclass 7, count 2 2006.210.08:05:48.97#ibcon#*mode == 0, iclass 7, count 2 2006.210.08:05:48.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.08:05:48.97#ibcon#[25=AT05-07\r\n] 2006.210.08:05:48.97#ibcon#*before write, iclass 7, count 2 2006.210.08:05:48.97#ibcon#enter sib2, iclass 7, count 2 2006.210.08:05:48.97#ibcon#flushed, iclass 7, count 2 2006.210.08:05:48.97#ibcon#about to write, iclass 7, count 2 2006.210.08:05:48.97#ibcon#wrote, iclass 7, count 2 2006.210.08:05:48.97#ibcon#about to read 3, iclass 7, count 2 2006.210.08:05:49.00#ibcon#read 3, iclass 7, count 2 2006.210.08:05:49.00#ibcon#about to read 4, iclass 7, count 2 2006.210.08:05:49.00#ibcon#read 4, iclass 7, count 2 2006.210.08:05:49.00#ibcon#about to read 5, iclass 7, count 2 2006.210.08:05:49.00#ibcon#read 5, iclass 7, count 2 2006.210.08:05:49.00#ibcon#about to read 6, iclass 7, count 2 2006.210.08:05:49.00#ibcon#read 6, iclass 7, count 2 2006.210.08:05:49.00#ibcon#end of sib2, iclass 7, count 2 2006.210.08:05:49.00#ibcon#*after write, iclass 7, count 2 2006.210.08:05:49.00#ibcon#*before return 0, iclass 7, count 2 2006.210.08:05:49.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:49.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:49.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.08:05:49.00#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:49.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:49.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:49.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:49.12#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:05:49.12#ibcon#first serial, iclass 7, count 0 2006.210.08:05:49.12#ibcon#enter sib2, iclass 7, count 0 2006.210.08:05:49.12#ibcon#flushed, iclass 7, count 0 2006.210.08:05:49.12#ibcon#about to write, iclass 7, count 0 2006.210.08:05:49.12#ibcon#wrote, iclass 7, count 0 2006.210.08:05:49.12#ibcon#about to read 3, iclass 7, count 0 2006.210.08:05:49.14#ibcon#read 3, iclass 7, count 0 2006.210.08:05:49.14#ibcon#about to read 4, iclass 7, count 0 2006.210.08:05:49.14#ibcon#read 4, iclass 7, count 0 2006.210.08:05:49.14#ibcon#about to read 5, iclass 7, count 0 2006.210.08:05:49.14#ibcon#read 5, iclass 7, count 0 2006.210.08:05:49.14#ibcon#about to read 6, iclass 7, count 0 2006.210.08:05:49.14#ibcon#read 6, iclass 7, count 0 2006.210.08:05:49.14#ibcon#end of sib2, iclass 7, count 0 2006.210.08:05:49.14#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:05:49.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:05:49.14#ibcon#[25=USB\r\n] 2006.210.08:05:49.14#ibcon#*before write, iclass 7, count 0 2006.210.08:05:49.14#ibcon#enter sib2, iclass 7, count 0 2006.210.08:05:49.14#ibcon#flushed, iclass 7, count 0 2006.210.08:05:49.14#ibcon#about to write, iclass 7, count 0 2006.210.08:05:49.14#ibcon#wrote, iclass 7, count 0 2006.210.08:05:49.14#ibcon#about to read 3, iclass 7, count 0 2006.210.08:05:49.17#ibcon#read 3, iclass 7, count 0 2006.210.08:05:49.17#ibcon#about to read 4, iclass 7, count 0 2006.210.08:05:49.17#ibcon#read 4, iclass 7, count 0 2006.210.08:05:49.17#ibcon#about to read 5, iclass 7, count 0 2006.210.08:05:49.17#ibcon#read 5, iclass 7, count 0 2006.210.08:05:49.17#ibcon#about to read 6, iclass 7, count 0 2006.210.08:05:49.17#ibcon#read 6, iclass 7, count 0 2006.210.08:05:49.17#ibcon#end of sib2, iclass 7, count 0 2006.210.08:05:49.17#ibcon#*after write, iclass 7, count 0 2006.210.08:05:49.17#ibcon#*before return 0, iclass 7, count 0 2006.210.08:05:49.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:49.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:49.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:05:49.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:05:49.17$vc4f8/valo=6,772.99 2006.210.08:05:49.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.08:05:49.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.08:05:49.17#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:49.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:49.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:49.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:49.17#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:05:49.17#ibcon#first serial, iclass 11, count 0 2006.210.08:05:49.17#ibcon#enter sib2, iclass 11, count 0 2006.210.08:05:49.17#ibcon#flushed, iclass 11, count 0 2006.210.08:05:49.17#ibcon#about to write, iclass 11, count 0 2006.210.08:05:49.17#ibcon#wrote, iclass 11, count 0 2006.210.08:05:49.17#ibcon#about to read 3, iclass 11, count 0 2006.210.08:05:49.19#ibcon#read 3, iclass 11, count 0 2006.210.08:05:49.19#ibcon#about to read 4, iclass 11, count 0 2006.210.08:05:49.19#ibcon#read 4, iclass 11, count 0 2006.210.08:05:49.19#ibcon#about to read 5, iclass 11, count 0 2006.210.08:05:49.19#ibcon#read 5, iclass 11, count 0 2006.210.08:05:49.19#ibcon#about to read 6, iclass 11, count 0 2006.210.08:05:49.19#ibcon#read 6, iclass 11, count 0 2006.210.08:05:49.19#ibcon#end of sib2, iclass 11, count 0 2006.210.08:05:49.19#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:05:49.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:05:49.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:05:49.19#ibcon#*before write, iclass 11, count 0 2006.210.08:05:49.19#ibcon#enter sib2, iclass 11, count 0 2006.210.08:05:49.19#ibcon#flushed, iclass 11, count 0 2006.210.08:05:49.19#ibcon#about to write, iclass 11, count 0 2006.210.08:05:49.19#ibcon#wrote, iclass 11, count 0 2006.210.08:05:49.19#ibcon#about to read 3, iclass 11, count 0 2006.210.08:05:49.23#ibcon#read 3, iclass 11, count 0 2006.210.08:05:49.23#ibcon#about to read 4, iclass 11, count 0 2006.210.08:05:49.23#ibcon#read 4, iclass 11, count 0 2006.210.08:05:49.23#ibcon#about to read 5, iclass 11, count 0 2006.210.08:05:49.23#ibcon#read 5, iclass 11, count 0 2006.210.08:05:49.23#ibcon#about to read 6, iclass 11, count 0 2006.210.08:05:49.23#ibcon#read 6, iclass 11, count 0 2006.210.08:05:49.23#ibcon#end of sib2, iclass 11, count 0 2006.210.08:05:49.23#ibcon#*after write, iclass 11, count 0 2006.210.08:05:49.23#ibcon#*before return 0, iclass 11, count 0 2006.210.08:05:49.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:49.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:49.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:05:49.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:05:49.23$vc4f8/va=6,6 2006.210.08:05:49.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.08:05:49.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.08:05:49.23#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:49.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:05:49.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:05:49.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:05:49.29#ibcon#enter wrdev, iclass 13, count 2 2006.210.08:05:49.29#ibcon#first serial, iclass 13, count 2 2006.210.08:05:49.29#ibcon#enter sib2, iclass 13, count 2 2006.210.08:05:49.29#ibcon#flushed, iclass 13, count 2 2006.210.08:05:49.29#ibcon#about to write, iclass 13, count 2 2006.210.08:05:49.29#ibcon#wrote, iclass 13, count 2 2006.210.08:05:49.29#ibcon#about to read 3, iclass 13, count 2 2006.210.08:05:49.31#ibcon#read 3, iclass 13, count 2 2006.210.08:05:49.31#ibcon#about to read 4, iclass 13, count 2 2006.210.08:05:49.31#ibcon#read 4, iclass 13, count 2 2006.210.08:05:49.31#ibcon#about to read 5, iclass 13, count 2 2006.210.08:05:49.31#ibcon#read 5, iclass 13, count 2 2006.210.08:05:49.31#ibcon#about to read 6, iclass 13, count 2 2006.210.08:05:49.31#ibcon#read 6, iclass 13, count 2 2006.210.08:05:49.31#ibcon#end of sib2, iclass 13, count 2 2006.210.08:05:49.31#ibcon#*mode == 0, iclass 13, count 2 2006.210.08:05:49.31#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.08:05:49.31#ibcon#[25=AT06-06\r\n] 2006.210.08:05:49.31#ibcon#*before write, iclass 13, count 2 2006.210.08:05:49.31#ibcon#enter sib2, iclass 13, count 2 2006.210.08:05:49.31#ibcon#flushed, iclass 13, count 2 2006.210.08:05:49.31#ibcon#about to write, iclass 13, count 2 2006.210.08:05:49.31#ibcon#wrote, iclass 13, count 2 2006.210.08:05:49.31#ibcon#about to read 3, iclass 13, count 2 2006.210.08:05:49.34#ibcon#read 3, iclass 13, count 2 2006.210.08:05:49.34#ibcon#about to read 4, iclass 13, count 2 2006.210.08:05:49.34#ibcon#read 4, iclass 13, count 2 2006.210.08:05:49.34#ibcon#about to read 5, iclass 13, count 2 2006.210.08:05:49.34#ibcon#read 5, iclass 13, count 2 2006.210.08:05:49.34#ibcon#about to read 6, iclass 13, count 2 2006.210.08:05:49.34#ibcon#read 6, iclass 13, count 2 2006.210.08:05:49.34#ibcon#end of sib2, iclass 13, count 2 2006.210.08:05:49.34#ibcon#*after write, iclass 13, count 2 2006.210.08:05:49.34#ibcon#*before return 0, iclass 13, count 2 2006.210.08:05:49.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:05:49.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:05:49.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.08:05:49.34#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:49.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:05:49.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:05:49.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:05:49.46#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:05:49.46#ibcon#first serial, iclass 13, count 0 2006.210.08:05:49.46#ibcon#enter sib2, iclass 13, count 0 2006.210.08:05:49.46#ibcon#flushed, iclass 13, count 0 2006.210.08:05:49.46#ibcon#about to write, iclass 13, count 0 2006.210.08:05:49.46#ibcon#wrote, iclass 13, count 0 2006.210.08:05:49.46#ibcon#about to read 3, iclass 13, count 0 2006.210.08:05:49.48#ibcon#read 3, iclass 13, count 0 2006.210.08:05:49.48#ibcon#about to read 4, iclass 13, count 0 2006.210.08:05:49.48#ibcon#read 4, iclass 13, count 0 2006.210.08:05:49.48#ibcon#about to read 5, iclass 13, count 0 2006.210.08:05:49.48#ibcon#read 5, iclass 13, count 0 2006.210.08:05:49.48#ibcon#about to read 6, iclass 13, count 0 2006.210.08:05:49.48#ibcon#read 6, iclass 13, count 0 2006.210.08:05:49.48#ibcon#end of sib2, iclass 13, count 0 2006.210.08:05:49.48#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:05:49.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:05:49.48#ibcon#[25=USB\r\n] 2006.210.08:05:49.48#ibcon#*before write, iclass 13, count 0 2006.210.08:05:49.48#ibcon#enter sib2, iclass 13, count 0 2006.210.08:05:49.48#ibcon#flushed, iclass 13, count 0 2006.210.08:05:49.48#ibcon#about to write, iclass 13, count 0 2006.210.08:05:49.48#ibcon#wrote, iclass 13, count 0 2006.210.08:05:49.48#ibcon#about to read 3, iclass 13, count 0 2006.210.08:05:49.51#ibcon#read 3, iclass 13, count 0 2006.210.08:05:49.51#ibcon#about to read 4, iclass 13, count 0 2006.210.08:05:49.51#ibcon#read 4, iclass 13, count 0 2006.210.08:05:49.51#ibcon#about to read 5, iclass 13, count 0 2006.210.08:05:49.51#ibcon#read 5, iclass 13, count 0 2006.210.08:05:49.51#ibcon#about to read 6, iclass 13, count 0 2006.210.08:05:49.51#ibcon#read 6, iclass 13, count 0 2006.210.08:05:49.51#ibcon#end of sib2, iclass 13, count 0 2006.210.08:05:49.51#ibcon#*after write, iclass 13, count 0 2006.210.08:05:49.51#ibcon#*before return 0, iclass 13, count 0 2006.210.08:05:49.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:05:49.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:05:49.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:05:49.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:05:49.51$vc4f8/valo=7,832.99 2006.210.08:05:49.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.08:05:49.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.08:05:49.51#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:49.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:05:49.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:05:49.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:05:49.51#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:05:49.51#ibcon#first serial, iclass 15, count 0 2006.210.08:05:49.51#ibcon#enter sib2, iclass 15, count 0 2006.210.08:05:49.51#ibcon#flushed, iclass 15, count 0 2006.210.08:05:49.51#ibcon#about to write, iclass 15, count 0 2006.210.08:05:49.51#ibcon#wrote, iclass 15, count 0 2006.210.08:05:49.51#ibcon#about to read 3, iclass 15, count 0 2006.210.08:05:49.53#ibcon#read 3, iclass 15, count 0 2006.210.08:05:49.53#ibcon#about to read 4, iclass 15, count 0 2006.210.08:05:49.53#ibcon#read 4, iclass 15, count 0 2006.210.08:05:49.53#ibcon#about to read 5, iclass 15, count 0 2006.210.08:05:49.53#ibcon#read 5, iclass 15, count 0 2006.210.08:05:49.53#ibcon#about to read 6, iclass 15, count 0 2006.210.08:05:49.53#ibcon#read 6, iclass 15, count 0 2006.210.08:05:49.53#ibcon#end of sib2, iclass 15, count 0 2006.210.08:05:49.53#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:05:49.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:05:49.53#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:05:49.53#ibcon#*before write, iclass 15, count 0 2006.210.08:05:49.53#ibcon#enter sib2, iclass 15, count 0 2006.210.08:05:49.53#ibcon#flushed, iclass 15, count 0 2006.210.08:05:49.53#ibcon#about to write, iclass 15, count 0 2006.210.08:05:49.53#ibcon#wrote, iclass 15, count 0 2006.210.08:05:49.53#ibcon#about to read 3, iclass 15, count 0 2006.210.08:05:49.57#ibcon#read 3, iclass 15, count 0 2006.210.08:05:49.57#ibcon#about to read 4, iclass 15, count 0 2006.210.08:05:49.57#ibcon#read 4, iclass 15, count 0 2006.210.08:05:49.57#ibcon#about to read 5, iclass 15, count 0 2006.210.08:05:49.57#ibcon#read 5, iclass 15, count 0 2006.210.08:05:49.57#ibcon#about to read 6, iclass 15, count 0 2006.210.08:05:49.57#ibcon#read 6, iclass 15, count 0 2006.210.08:05:49.57#ibcon#end of sib2, iclass 15, count 0 2006.210.08:05:49.57#ibcon#*after write, iclass 15, count 0 2006.210.08:05:49.57#ibcon#*before return 0, iclass 15, count 0 2006.210.08:05:49.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:05:49.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:05:49.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:05:49.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:05:49.57$vc4f8/va=7,6 2006.210.08:05:49.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.08:05:49.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.08:05:49.57#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:49.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:05:49.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:05:49.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:05:49.63#ibcon#enter wrdev, iclass 17, count 2 2006.210.08:05:49.63#ibcon#first serial, iclass 17, count 2 2006.210.08:05:49.63#ibcon#enter sib2, iclass 17, count 2 2006.210.08:05:49.63#ibcon#flushed, iclass 17, count 2 2006.210.08:05:49.63#ibcon#about to write, iclass 17, count 2 2006.210.08:05:49.63#ibcon#wrote, iclass 17, count 2 2006.210.08:05:49.63#ibcon#about to read 3, iclass 17, count 2 2006.210.08:05:49.65#ibcon#read 3, iclass 17, count 2 2006.210.08:05:49.65#ibcon#about to read 4, iclass 17, count 2 2006.210.08:05:49.65#ibcon#read 4, iclass 17, count 2 2006.210.08:05:49.65#ibcon#about to read 5, iclass 17, count 2 2006.210.08:05:49.65#ibcon#read 5, iclass 17, count 2 2006.210.08:05:49.65#ibcon#about to read 6, iclass 17, count 2 2006.210.08:05:49.65#ibcon#read 6, iclass 17, count 2 2006.210.08:05:49.65#ibcon#end of sib2, iclass 17, count 2 2006.210.08:05:49.65#ibcon#*mode == 0, iclass 17, count 2 2006.210.08:05:49.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.08:05:49.65#ibcon#[25=AT07-06\r\n] 2006.210.08:05:49.65#ibcon#*before write, iclass 17, count 2 2006.210.08:05:49.65#ibcon#enter sib2, iclass 17, count 2 2006.210.08:05:49.65#ibcon#flushed, iclass 17, count 2 2006.210.08:05:49.65#ibcon#about to write, iclass 17, count 2 2006.210.08:05:49.65#ibcon#wrote, iclass 17, count 2 2006.210.08:05:49.65#ibcon#about to read 3, iclass 17, count 2 2006.210.08:05:49.68#ibcon#read 3, iclass 17, count 2 2006.210.08:05:49.68#ibcon#about to read 4, iclass 17, count 2 2006.210.08:05:49.68#ibcon#read 4, iclass 17, count 2 2006.210.08:05:49.68#ibcon#about to read 5, iclass 17, count 2 2006.210.08:05:49.68#ibcon#read 5, iclass 17, count 2 2006.210.08:05:49.68#ibcon#about to read 6, iclass 17, count 2 2006.210.08:05:49.68#ibcon#read 6, iclass 17, count 2 2006.210.08:05:49.68#ibcon#end of sib2, iclass 17, count 2 2006.210.08:05:49.68#ibcon#*after write, iclass 17, count 2 2006.210.08:05:49.68#ibcon#*before return 0, iclass 17, count 2 2006.210.08:05:49.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:05:49.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:05:49.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.08:05:49.68#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:49.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:05:49.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:05:49.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:05:49.80#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:05:49.80#ibcon#first serial, iclass 17, count 0 2006.210.08:05:49.80#ibcon#enter sib2, iclass 17, count 0 2006.210.08:05:49.80#ibcon#flushed, iclass 17, count 0 2006.210.08:05:49.80#ibcon#about to write, iclass 17, count 0 2006.210.08:05:49.80#ibcon#wrote, iclass 17, count 0 2006.210.08:05:49.80#ibcon#about to read 3, iclass 17, count 0 2006.210.08:05:49.82#ibcon#read 3, iclass 17, count 0 2006.210.08:05:49.82#ibcon#about to read 4, iclass 17, count 0 2006.210.08:05:49.82#ibcon#read 4, iclass 17, count 0 2006.210.08:05:49.82#ibcon#about to read 5, iclass 17, count 0 2006.210.08:05:49.82#ibcon#read 5, iclass 17, count 0 2006.210.08:05:49.82#ibcon#about to read 6, iclass 17, count 0 2006.210.08:05:49.82#ibcon#read 6, iclass 17, count 0 2006.210.08:05:49.82#ibcon#end of sib2, iclass 17, count 0 2006.210.08:05:49.82#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:05:49.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:05:49.82#ibcon#[25=USB\r\n] 2006.210.08:05:49.82#ibcon#*before write, iclass 17, count 0 2006.210.08:05:49.82#ibcon#enter sib2, iclass 17, count 0 2006.210.08:05:49.82#ibcon#flushed, iclass 17, count 0 2006.210.08:05:49.82#ibcon#about to write, iclass 17, count 0 2006.210.08:05:49.82#ibcon#wrote, iclass 17, count 0 2006.210.08:05:49.82#ibcon#about to read 3, iclass 17, count 0 2006.210.08:05:49.85#ibcon#read 3, iclass 17, count 0 2006.210.08:05:49.85#ibcon#about to read 4, iclass 17, count 0 2006.210.08:05:49.85#ibcon#read 4, iclass 17, count 0 2006.210.08:05:49.85#ibcon#about to read 5, iclass 17, count 0 2006.210.08:05:49.85#ibcon#read 5, iclass 17, count 0 2006.210.08:05:49.85#ibcon#about to read 6, iclass 17, count 0 2006.210.08:05:49.85#ibcon#read 6, iclass 17, count 0 2006.210.08:05:49.85#ibcon#end of sib2, iclass 17, count 0 2006.210.08:05:49.85#ibcon#*after write, iclass 17, count 0 2006.210.08:05:49.85#ibcon#*before return 0, iclass 17, count 0 2006.210.08:05:49.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:05:49.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:05:49.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:05:49.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:05:49.85$vc4f8/valo=8,852.99 2006.210.08:05:49.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.08:05:49.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.08:05:49.85#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:49.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:05:49.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:05:49.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:05:49.85#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:05:49.85#ibcon#first serial, iclass 19, count 0 2006.210.08:05:49.85#ibcon#enter sib2, iclass 19, count 0 2006.210.08:05:49.85#ibcon#flushed, iclass 19, count 0 2006.210.08:05:49.85#ibcon#about to write, iclass 19, count 0 2006.210.08:05:49.85#ibcon#wrote, iclass 19, count 0 2006.210.08:05:49.85#ibcon#about to read 3, iclass 19, count 0 2006.210.08:05:49.87#ibcon#read 3, iclass 19, count 0 2006.210.08:05:49.87#ibcon#about to read 4, iclass 19, count 0 2006.210.08:05:49.87#ibcon#read 4, iclass 19, count 0 2006.210.08:05:49.87#ibcon#about to read 5, iclass 19, count 0 2006.210.08:05:49.87#ibcon#read 5, iclass 19, count 0 2006.210.08:05:49.87#ibcon#about to read 6, iclass 19, count 0 2006.210.08:05:49.87#ibcon#read 6, iclass 19, count 0 2006.210.08:05:49.87#ibcon#end of sib2, iclass 19, count 0 2006.210.08:05:49.87#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:05:49.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:05:49.87#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:05:49.87#ibcon#*before write, iclass 19, count 0 2006.210.08:05:49.87#ibcon#enter sib2, iclass 19, count 0 2006.210.08:05:49.87#ibcon#flushed, iclass 19, count 0 2006.210.08:05:49.87#ibcon#about to write, iclass 19, count 0 2006.210.08:05:49.87#ibcon#wrote, iclass 19, count 0 2006.210.08:05:49.87#ibcon#about to read 3, iclass 19, count 0 2006.210.08:05:49.91#ibcon#read 3, iclass 19, count 0 2006.210.08:05:49.91#ibcon#about to read 4, iclass 19, count 0 2006.210.08:05:49.91#ibcon#read 4, iclass 19, count 0 2006.210.08:05:49.91#ibcon#about to read 5, iclass 19, count 0 2006.210.08:05:49.91#ibcon#read 5, iclass 19, count 0 2006.210.08:05:49.91#ibcon#about to read 6, iclass 19, count 0 2006.210.08:05:49.91#ibcon#read 6, iclass 19, count 0 2006.210.08:05:49.91#ibcon#end of sib2, iclass 19, count 0 2006.210.08:05:49.91#ibcon#*after write, iclass 19, count 0 2006.210.08:05:49.91#ibcon#*before return 0, iclass 19, count 0 2006.210.08:05:49.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:05:49.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:05:49.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:05:49.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:05:49.91$vc4f8/va=8,7 2006.210.08:05:49.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.08:05:49.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.08:05:49.91#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:49.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:05:49.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:05:49.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:05:49.97#ibcon#enter wrdev, iclass 21, count 2 2006.210.08:05:49.97#ibcon#first serial, iclass 21, count 2 2006.210.08:05:49.97#ibcon#enter sib2, iclass 21, count 2 2006.210.08:05:49.97#ibcon#flushed, iclass 21, count 2 2006.210.08:05:49.97#ibcon#about to write, iclass 21, count 2 2006.210.08:05:49.97#ibcon#wrote, iclass 21, count 2 2006.210.08:05:49.97#ibcon#about to read 3, iclass 21, count 2 2006.210.08:05:49.99#ibcon#read 3, iclass 21, count 2 2006.210.08:05:49.99#ibcon#about to read 4, iclass 21, count 2 2006.210.08:05:49.99#ibcon#read 4, iclass 21, count 2 2006.210.08:05:49.99#ibcon#about to read 5, iclass 21, count 2 2006.210.08:05:49.99#ibcon#read 5, iclass 21, count 2 2006.210.08:05:49.99#ibcon#about to read 6, iclass 21, count 2 2006.210.08:05:49.99#ibcon#read 6, iclass 21, count 2 2006.210.08:05:49.99#ibcon#end of sib2, iclass 21, count 2 2006.210.08:05:49.99#ibcon#*mode == 0, iclass 21, count 2 2006.210.08:05:49.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.08:05:49.99#ibcon#[25=AT08-07\r\n] 2006.210.08:05:49.99#ibcon#*before write, iclass 21, count 2 2006.210.08:05:49.99#ibcon#enter sib2, iclass 21, count 2 2006.210.08:05:49.99#ibcon#flushed, iclass 21, count 2 2006.210.08:05:49.99#ibcon#about to write, iclass 21, count 2 2006.210.08:05:49.99#ibcon#wrote, iclass 21, count 2 2006.210.08:05:49.99#ibcon#about to read 3, iclass 21, count 2 2006.210.08:05:50.02#ibcon#read 3, iclass 21, count 2 2006.210.08:05:50.02#ibcon#about to read 4, iclass 21, count 2 2006.210.08:05:50.02#ibcon#read 4, iclass 21, count 2 2006.210.08:05:50.02#ibcon#about to read 5, iclass 21, count 2 2006.210.08:05:50.02#ibcon#read 5, iclass 21, count 2 2006.210.08:05:50.02#ibcon#about to read 6, iclass 21, count 2 2006.210.08:05:50.02#ibcon#read 6, iclass 21, count 2 2006.210.08:05:50.02#ibcon#end of sib2, iclass 21, count 2 2006.210.08:05:50.02#ibcon#*after write, iclass 21, count 2 2006.210.08:05:50.02#ibcon#*before return 0, iclass 21, count 2 2006.210.08:05:50.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:05:50.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:05:50.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.08:05:50.02#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:50.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:05:50.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:05:50.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:05:50.14#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:05:50.14#ibcon#first serial, iclass 21, count 0 2006.210.08:05:50.14#ibcon#enter sib2, iclass 21, count 0 2006.210.08:05:50.14#ibcon#flushed, iclass 21, count 0 2006.210.08:05:50.14#ibcon#about to write, iclass 21, count 0 2006.210.08:05:50.14#ibcon#wrote, iclass 21, count 0 2006.210.08:05:50.14#ibcon#about to read 3, iclass 21, count 0 2006.210.08:05:50.16#ibcon#read 3, iclass 21, count 0 2006.210.08:05:50.16#ibcon#about to read 4, iclass 21, count 0 2006.210.08:05:50.16#ibcon#read 4, iclass 21, count 0 2006.210.08:05:50.16#ibcon#about to read 5, iclass 21, count 0 2006.210.08:05:50.16#ibcon#read 5, iclass 21, count 0 2006.210.08:05:50.16#ibcon#about to read 6, iclass 21, count 0 2006.210.08:05:50.16#ibcon#read 6, iclass 21, count 0 2006.210.08:05:50.16#ibcon#end of sib2, iclass 21, count 0 2006.210.08:05:50.16#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:05:50.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:05:50.16#ibcon#[25=USB\r\n] 2006.210.08:05:50.16#ibcon#*before write, iclass 21, count 0 2006.210.08:05:50.16#ibcon#enter sib2, iclass 21, count 0 2006.210.08:05:50.16#ibcon#flushed, iclass 21, count 0 2006.210.08:05:50.16#ibcon#about to write, iclass 21, count 0 2006.210.08:05:50.16#ibcon#wrote, iclass 21, count 0 2006.210.08:05:50.16#ibcon#about to read 3, iclass 21, count 0 2006.210.08:05:50.19#ibcon#read 3, iclass 21, count 0 2006.210.08:05:50.19#ibcon#about to read 4, iclass 21, count 0 2006.210.08:05:50.19#ibcon#read 4, iclass 21, count 0 2006.210.08:05:50.19#ibcon#about to read 5, iclass 21, count 0 2006.210.08:05:50.19#ibcon#read 5, iclass 21, count 0 2006.210.08:05:50.19#ibcon#about to read 6, iclass 21, count 0 2006.210.08:05:50.19#ibcon#read 6, iclass 21, count 0 2006.210.08:05:50.19#ibcon#end of sib2, iclass 21, count 0 2006.210.08:05:50.19#ibcon#*after write, iclass 21, count 0 2006.210.08:05:50.19#ibcon#*before return 0, iclass 21, count 0 2006.210.08:05:50.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:05:50.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:05:50.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:05:50.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:05:50.19$vc4f8/vblo=1,632.99 2006.210.08:05:50.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.08:05:50.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.08:05:50.19#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:50.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:05:50.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:05:50.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:05:50.19#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:05:50.19#ibcon#first serial, iclass 23, count 0 2006.210.08:05:50.19#ibcon#enter sib2, iclass 23, count 0 2006.210.08:05:50.19#ibcon#flushed, iclass 23, count 0 2006.210.08:05:50.19#ibcon#about to write, iclass 23, count 0 2006.210.08:05:50.19#ibcon#wrote, iclass 23, count 0 2006.210.08:05:50.19#ibcon#about to read 3, iclass 23, count 0 2006.210.08:05:50.21#ibcon#read 3, iclass 23, count 0 2006.210.08:05:50.21#ibcon#about to read 4, iclass 23, count 0 2006.210.08:05:50.21#ibcon#read 4, iclass 23, count 0 2006.210.08:05:50.21#ibcon#about to read 5, iclass 23, count 0 2006.210.08:05:50.21#ibcon#read 5, iclass 23, count 0 2006.210.08:05:50.21#ibcon#about to read 6, iclass 23, count 0 2006.210.08:05:50.21#ibcon#read 6, iclass 23, count 0 2006.210.08:05:50.21#ibcon#end of sib2, iclass 23, count 0 2006.210.08:05:50.21#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:05:50.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:05:50.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:05:50.21#ibcon#*before write, iclass 23, count 0 2006.210.08:05:50.21#ibcon#enter sib2, iclass 23, count 0 2006.210.08:05:50.21#ibcon#flushed, iclass 23, count 0 2006.210.08:05:50.21#ibcon#about to write, iclass 23, count 0 2006.210.08:05:50.21#ibcon#wrote, iclass 23, count 0 2006.210.08:05:50.21#ibcon#about to read 3, iclass 23, count 0 2006.210.08:05:50.25#ibcon#read 3, iclass 23, count 0 2006.210.08:05:50.25#ibcon#about to read 4, iclass 23, count 0 2006.210.08:05:50.25#ibcon#read 4, iclass 23, count 0 2006.210.08:05:50.25#ibcon#about to read 5, iclass 23, count 0 2006.210.08:05:50.25#ibcon#read 5, iclass 23, count 0 2006.210.08:05:50.25#ibcon#about to read 6, iclass 23, count 0 2006.210.08:05:50.25#ibcon#read 6, iclass 23, count 0 2006.210.08:05:50.25#ibcon#end of sib2, iclass 23, count 0 2006.210.08:05:50.25#ibcon#*after write, iclass 23, count 0 2006.210.08:05:50.25#ibcon#*before return 0, iclass 23, count 0 2006.210.08:05:50.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:05:50.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:05:50.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:05:50.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:05:50.25$vc4f8/vb=1,4 2006.210.08:05:50.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.08:05:50.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.08:05:50.25#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:50.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:05:50.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:05:50.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:05:50.25#ibcon#enter wrdev, iclass 25, count 2 2006.210.08:05:50.25#ibcon#first serial, iclass 25, count 2 2006.210.08:05:50.25#ibcon#enter sib2, iclass 25, count 2 2006.210.08:05:50.25#ibcon#flushed, iclass 25, count 2 2006.210.08:05:50.25#ibcon#about to write, iclass 25, count 2 2006.210.08:05:50.25#ibcon#wrote, iclass 25, count 2 2006.210.08:05:50.25#ibcon#about to read 3, iclass 25, count 2 2006.210.08:05:50.27#ibcon#read 3, iclass 25, count 2 2006.210.08:05:50.27#ibcon#about to read 4, iclass 25, count 2 2006.210.08:05:50.27#ibcon#read 4, iclass 25, count 2 2006.210.08:05:50.27#ibcon#about to read 5, iclass 25, count 2 2006.210.08:05:50.27#ibcon#read 5, iclass 25, count 2 2006.210.08:05:50.27#ibcon#about to read 6, iclass 25, count 2 2006.210.08:05:50.27#ibcon#read 6, iclass 25, count 2 2006.210.08:05:50.27#ibcon#end of sib2, iclass 25, count 2 2006.210.08:05:50.27#ibcon#*mode == 0, iclass 25, count 2 2006.210.08:05:50.27#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.08:05:50.27#ibcon#[27=AT01-04\r\n] 2006.210.08:05:50.27#ibcon#*before write, iclass 25, count 2 2006.210.08:05:50.27#ibcon#enter sib2, iclass 25, count 2 2006.210.08:05:50.27#ibcon#flushed, iclass 25, count 2 2006.210.08:05:50.27#ibcon#about to write, iclass 25, count 2 2006.210.08:05:50.27#ibcon#wrote, iclass 25, count 2 2006.210.08:05:50.27#ibcon#about to read 3, iclass 25, count 2 2006.210.08:05:50.30#ibcon#read 3, iclass 25, count 2 2006.210.08:05:50.30#ibcon#about to read 4, iclass 25, count 2 2006.210.08:05:50.30#ibcon#read 4, iclass 25, count 2 2006.210.08:05:50.30#ibcon#about to read 5, iclass 25, count 2 2006.210.08:05:50.30#ibcon#read 5, iclass 25, count 2 2006.210.08:05:50.30#ibcon#about to read 6, iclass 25, count 2 2006.210.08:05:50.30#ibcon#read 6, iclass 25, count 2 2006.210.08:05:50.30#ibcon#end of sib2, iclass 25, count 2 2006.210.08:05:50.30#ibcon#*after write, iclass 25, count 2 2006.210.08:05:50.30#ibcon#*before return 0, iclass 25, count 2 2006.210.08:05:50.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:05:50.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:05:50.30#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.08:05:50.30#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:50.30#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:05:50.42#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:05:50.42#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:05:50.42#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:05:50.42#ibcon#first serial, iclass 25, count 0 2006.210.08:05:50.42#ibcon#enter sib2, iclass 25, count 0 2006.210.08:05:50.42#ibcon#flushed, iclass 25, count 0 2006.210.08:05:50.42#ibcon#about to write, iclass 25, count 0 2006.210.08:05:50.42#ibcon#wrote, iclass 25, count 0 2006.210.08:05:50.42#ibcon#about to read 3, iclass 25, count 0 2006.210.08:05:50.44#ibcon#read 3, iclass 25, count 0 2006.210.08:05:50.44#ibcon#about to read 4, iclass 25, count 0 2006.210.08:05:50.44#ibcon#read 4, iclass 25, count 0 2006.210.08:05:50.44#ibcon#about to read 5, iclass 25, count 0 2006.210.08:05:50.44#ibcon#read 5, iclass 25, count 0 2006.210.08:05:50.44#ibcon#about to read 6, iclass 25, count 0 2006.210.08:05:50.44#ibcon#read 6, iclass 25, count 0 2006.210.08:05:50.44#ibcon#end of sib2, iclass 25, count 0 2006.210.08:05:50.44#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:05:50.44#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:05:50.44#ibcon#[27=USB\r\n] 2006.210.08:05:50.44#ibcon#*before write, iclass 25, count 0 2006.210.08:05:50.44#ibcon#enter sib2, iclass 25, count 0 2006.210.08:05:50.44#ibcon#flushed, iclass 25, count 0 2006.210.08:05:50.44#ibcon#about to write, iclass 25, count 0 2006.210.08:05:50.44#ibcon#wrote, iclass 25, count 0 2006.210.08:05:50.44#ibcon#about to read 3, iclass 25, count 0 2006.210.08:05:50.47#ibcon#read 3, iclass 25, count 0 2006.210.08:05:50.47#ibcon#about to read 4, iclass 25, count 0 2006.210.08:05:50.47#ibcon#read 4, iclass 25, count 0 2006.210.08:05:50.47#ibcon#about to read 5, iclass 25, count 0 2006.210.08:05:50.47#ibcon#read 5, iclass 25, count 0 2006.210.08:05:50.47#ibcon#about to read 6, iclass 25, count 0 2006.210.08:05:50.47#ibcon#read 6, iclass 25, count 0 2006.210.08:05:50.47#ibcon#end of sib2, iclass 25, count 0 2006.210.08:05:50.47#ibcon#*after write, iclass 25, count 0 2006.210.08:05:50.47#ibcon#*before return 0, iclass 25, count 0 2006.210.08:05:50.47#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:05:50.47#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:05:50.47#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:05:50.47#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:05:50.47$vc4f8/vblo=2,640.99 2006.210.08:05:50.47#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.08:05:50.47#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.08:05:50.47#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:50.47#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:50.47#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:50.47#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:50.47#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:05:50.47#ibcon#first serial, iclass 27, count 0 2006.210.08:05:50.47#ibcon#enter sib2, iclass 27, count 0 2006.210.08:05:50.47#ibcon#flushed, iclass 27, count 0 2006.210.08:05:50.47#ibcon#about to write, iclass 27, count 0 2006.210.08:05:50.47#ibcon#wrote, iclass 27, count 0 2006.210.08:05:50.47#ibcon#about to read 3, iclass 27, count 0 2006.210.08:05:50.49#ibcon#read 3, iclass 27, count 0 2006.210.08:05:50.49#ibcon#about to read 4, iclass 27, count 0 2006.210.08:05:50.49#ibcon#read 4, iclass 27, count 0 2006.210.08:05:50.49#ibcon#about to read 5, iclass 27, count 0 2006.210.08:05:50.49#ibcon#read 5, iclass 27, count 0 2006.210.08:05:50.49#ibcon#about to read 6, iclass 27, count 0 2006.210.08:05:50.49#ibcon#read 6, iclass 27, count 0 2006.210.08:05:50.49#ibcon#end of sib2, iclass 27, count 0 2006.210.08:05:50.49#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:05:50.49#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:05:50.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:05:50.49#ibcon#*before write, iclass 27, count 0 2006.210.08:05:50.49#ibcon#enter sib2, iclass 27, count 0 2006.210.08:05:50.49#ibcon#flushed, iclass 27, count 0 2006.210.08:05:50.49#ibcon#about to write, iclass 27, count 0 2006.210.08:05:50.49#ibcon#wrote, iclass 27, count 0 2006.210.08:05:50.49#ibcon#about to read 3, iclass 27, count 0 2006.210.08:05:50.53#ibcon#read 3, iclass 27, count 0 2006.210.08:05:50.53#ibcon#about to read 4, iclass 27, count 0 2006.210.08:05:50.53#ibcon#read 4, iclass 27, count 0 2006.210.08:05:50.53#ibcon#about to read 5, iclass 27, count 0 2006.210.08:05:50.53#ibcon#read 5, iclass 27, count 0 2006.210.08:05:50.53#ibcon#about to read 6, iclass 27, count 0 2006.210.08:05:50.53#ibcon#read 6, iclass 27, count 0 2006.210.08:05:50.53#ibcon#end of sib2, iclass 27, count 0 2006.210.08:05:50.53#ibcon#*after write, iclass 27, count 0 2006.210.08:05:50.53#ibcon#*before return 0, iclass 27, count 0 2006.210.08:05:50.53#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:50.53#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:05:50.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:05:50.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:05:50.53$vc4f8/vb=2,4 2006.210.08:05:50.53#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.08:05:50.53#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.08:05:50.53#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:50.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:50.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:50.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:50.59#ibcon#enter wrdev, iclass 29, count 2 2006.210.08:05:50.59#ibcon#first serial, iclass 29, count 2 2006.210.08:05:50.59#ibcon#enter sib2, iclass 29, count 2 2006.210.08:05:50.59#ibcon#flushed, iclass 29, count 2 2006.210.08:05:50.59#ibcon#about to write, iclass 29, count 2 2006.210.08:05:50.59#ibcon#wrote, iclass 29, count 2 2006.210.08:05:50.59#ibcon#about to read 3, iclass 29, count 2 2006.210.08:05:50.61#ibcon#read 3, iclass 29, count 2 2006.210.08:05:50.61#ibcon#about to read 4, iclass 29, count 2 2006.210.08:05:50.61#ibcon#read 4, iclass 29, count 2 2006.210.08:05:50.61#ibcon#about to read 5, iclass 29, count 2 2006.210.08:05:50.61#ibcon#read 5, iclass 29, count 2 2006.210.08:05:50.61#ibcon#about to read 6, iclass 29, count 2 2006.210.08:05:50.61#ibcon#read 6, iclass 29, count 2 2006.210.08:05:50.61#ibcon#end of sib2, iclass 29, count 2 2006.210.08:05:50.61#ibcon#*mode == 0, iclass 29, count 2 2006.210.08:05:50.61#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.08:05:50.61#ibcon#[27=AT02-04\r\n] 2006.210.08:05:50.61#ibcon#*before write, iclass 29, count 2 2006.210.08:05:50.61#ibcon#enter sib2, iclass 29, count 2 2006.210.08:05:50.61#ibcon#flushed, iclass 29, count 2 2006.210.08:05:50.61#ibcon#about to write, iclass 29, count 2 2006.210.08:05:50.61#ibcon#wrote, iclass 29, count 2 2006.210.08:05:50.61#ibcon#about to read 3, iclass 29, count 2 2006.210.08:05:50.64#ibcon#read 3, iclass 29, count 2 2006.210.08:05:50.64#ibcon#about to read 4, iclass 29, count 2 2006.210.08:05:50.64#ibcon#read 4, iclass 29, count 2 2006.210.08:05:50.64#ibcon#about to read 5, iclass 29, count 2 2006.210.08:05:50.64#ibcon#read 5, iclass 29, count 2 2006.210.08:05:50.64#ibcon#about to read 6, iclass 29, count 2 2006.210.08:05:50.64#ibcon#read 6, iclass 29, count 2 2006.210.08:05:50.64#ibcon#end of sib2, iclass 29, count 2 2006.210.08:05:50.64#ibcon#*after write, iclass 29, count 2 2006.210.08:05:50.64#ibcon#*before return 0, iclass 29, count 2 2006.210.08:05:50.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:50.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:05:50.64#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.08:05:50.64#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:50.64#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:50.76#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:50.76#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:50.76#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:05:50.76#ibcon#first serial, iclass 29, count 0 2006.210.08:05:50.76#ibcon#enter sib2, iclass 29, count 0 2006.210.08:05:50.76#ibcon#flushed, iclass 29, count 0 2006.210.08:05:50.76#ibcon#about to write, iclass 29, count 0 2006.210.08:05:50.76#ibcon#wrote, iclass 29, count 0 2006.210.08:05:50.76#ibcon#about to read 3, iclass 29, count 0 2006.210.08:05:50.78#ibcon#read 3, iclass 29, count 0 2006.210.08:05:50.78#ibcon#about to read 4, iclass 29, count 0 2006.210.08:05:50.78#ibcon#read 4, iclass 29, count 0 2006.210.08:05:50.78#ibcon#about to read 5, iclass 29, count 0 2006.210.08:05:50.78#ibcon#read 5, iclass 29, count 0 2006.210.08:05:50.78#ibcon#about to read 6, iclass 29, count 0 2006.210.08:05:50.78#ibcon#read 6, iclass 29, count 0 2006.210.08:05:50.78#ibcon#end of sib2, iclass 29, count 0 2006.210.08:05:50.78#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:05:50.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:05:50.78#ibcon#[27=USB\r\n] 2006.210.08:05:50.78#ibcon#*before write, iclass 29, count 0 2006.210.08:05:50.78#ibcon#enter sib2, iclass 29, count 0 2006.210.08:05:50.78#ibcon#flushed, iclass 29, count 0 2006.210.08:05:50.78#ibcon#about to write, iclass 29, count 0 2006.210.08:05:50.78#ibcon#wrote, iclass 29, count 0 2006.210.08:05:50.78#ibcon#about to read 3, iclass 29, count 0 2006.210.08:05:50.81#ibcon#read 3, iclass 29, count 0 2006.210.08:05:50.81#ibcon#about to read 4, iclass 29, count 0 2006.210.08:05:50.81#ibcon#read 4, iclass 29, count 0 2006.210.08:05:50.81#ibcon#about to read 5, iclass 29, count 0 2006.210.08:05:50.81#ibcon#read 5, iclass 29, count 0 2006.210.08:05:50.81#ibcon#about to read 6, iclass 29, count 0 2006.210.08:05:50.81#ibcon#read 6, iclass 29, count 0 2006.210.08:05:50.81#ibcon#end of sib2, iclass 29, count 0 2006.210.08:05:50.81#ibcon#*after write, iclass 29, count 0 2006.210.08:05:50.81#ibcon#*before return 0, iclass 29, count 0 2006.210.08:05:50.81#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:50.81#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:05:50.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:05:50.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:05:50.81$vc4f8/vblo=3,656.99 2006.210.08:05:50.81#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.08:05:50.81#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.08:05:50.81#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:50.81#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:50.81#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:50.81#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:50.81#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:05:50.81#ibcon#first serial, iclass 31, count 0 2006.210.08:05:50.81#ibcon#enter sib2, iclass 31, count 0 2006.210.08:05:50.81#ibcon#flushed, iclass 31, count 0 2006.210.08:05:50.81#ibcon#about to write, iclass 31, count 0 2006.210.08:05:50.81#ibcon#wrote, iclass 31, count 0 2006.210.08:05:50.81#ibcon#about to read 3, iclass 31, count 0 2006.210.08:05:50.83#ibcon#read 3, iclass 31, count 0 2006.210.08:05:50.83#ibcon#about to read 4, iclass 31, count 0 2006.210.08:05:50.83#ibcon#read 4, iclass 31, count 0 2006.210.08:05:50.83#ibcon#about to read 5, iclass 31, count 0 2006.210.08:05:50.83#ibcon#read 5, iclass 31, count 0 2006.210.08:05:50.83#ibcon#about to read 6, iclass 31, count 0 2006.210.08:05:50.83#ibcon#read 6, iclass 31, count 0 2006.210.08:05:50.83#ibcon#end of sib2, iclass 31, count 0 2006.210.08:05:50.83#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:05:50.83#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:05:50.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:05:50.83#ibcon#*before write, iclass 31, count 0 2006.210.08:05:50.83#ibcon#enter sib2, iclass 31, count 0 2006.210.08:05:50.83#ibcon#flushed, iclass 31, count 0 2006.210.08:05:50.83#ibcon#about to write, iclass 31, count 0 2006.210.08:05:50.83#ibcon#wrote, iclass 31, count 0 2006.210.08:05:50.83#ibcon#about to read 3, iclass 31, count 0 2006.210.08:05:50.87#ibcon#read 3, iclass 31, count 0 2006.210.08:05:50.87#ibcon#about to read 4, iclass 31, count 0 2006.210.08:05:50.87#ibcon#read 4, iclass 31, count 0 2006.210.08:05:50.87#ibcon#about to read 5, iclass 31, count 0 2006.210.08:05:50.87#ibcon#read 5, iclass 31, count 0 2006.210.08:05:50.87#ibcon#about to read 6, iclass 31, count 0 2006.210.08:05:50.87#ibcon#read 6, iclass 31, count 0 2006.210.08:05:50.87#ibcon#end of sib2, iclass 31, count 0 2006.210.08:05:50.87#ibcon#*after write, iclass 31, count 0 2006.210.08:05:50.87#ibcon#*before return 0, iclass 31, count 0 2006.210.08:05:50.87#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:50.87#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:05:50.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:05:50.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:05:50.87$vc4f8/vb=3,3 2006.210.08:05:50.87#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.08:05:50.87#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.08:05:50.87#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:50.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:50.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:50.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:50.93#ibcon#enter wrdev, iclass 33, count 2 2006.210.08:05:50.93#ibcon#first serial, iclass 33, count 2 2006.210.08:05:50.93#ibcon#enter sib2, iclass 33, count 2 2006.210.08:05:50.93#ibcon#flushed, iclass 33, count 2 2006.210.08:05:50.93#ibcon#about to write, iclass 33, count 2 2006.210.08:05:50.93#ibcon#wrote, iclass 33, count 2 2006.210.08:05:50.93#ibcon#about to read 3, iclass 33, count 2 2006.210.08:05:50.95#ibcon#read 3, iclass 33, count 2 2006.210.08:05:50.95#ibcon#about to read 4, iclass 33, count 2 2006.210.08:05:50.95#ibcon#read 4, iclass 33, count 2 2006.210.08:05:50.95#ibcon#about to read 5, iclass 33, count 2 2006.210.08:05:50.95#ibcon#read 5, iclass 33, count 2 2006.210.08:05:50.95#ibcon#about to read 6, iclass 33, count 2 2006.210.08:05:50.95#ibcon#read 6, iclass 33, count 2 2006.210.08:05:50.95#ibcon#end of sib2, iclass 33, count 2 2006.210.08:05:50.95#ibcon#*mode == 0, iclass 33, count 2 2006.210.08:05:50.95#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.08:05:50.95#ibcon#[27=AT03-03\r\n] 2006.210.08:05:50.95#ibcon#*before write, iclass 33, count 2 2006.210.08:05:50.95#ibcon#enter sib2, iclass 33, count 2 2006.210.08:05:50.95#ibcon#flushed, iclass 33, count 2 2006.210.08:05:50.95#ibcon#about to write, iclass 33, count 2 2006.210.08:05:50.95#ibcon#wrote, iclass 33, count 2 2006.210.08:05:50.95#ibcon#about to read 3, iclass 33, count 2 2006.210.08:05:50.98#ibcon#read 3, iclass 33, count 2 2006.210.08:05:50.98#ibcon#about to read 4, iclass 33, count 2 2006.210.08:05:50.98#ibcon#read 4, iclass 33, count 2 2006.210.08:05:50.98#ibcon#about to read 5, iclass 33, count 2 2006.210.08:05:50.98#ibcon#read 5, iclass 33, count 2 2006.210.08:05:50.98#ibcon#about to read 6, iclass 33, count 2 2006.210.08:05:50.98#ibcon#read 6, iclass 33, count 2 2006.210.08:05:50.98#ibcon#end of sib2, iclass 33, count 2 2006.210.08:05:50.98#ibcon#*after write, iclass 33, count 2 2006.210.08:05:50.98#ibcon#*before return 0, iclass 33, count 2 2006.210.08:05:50.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:50.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:05:50.98#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.08:05:50.98#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:50.98#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:51.10#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:51.10#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:51.10#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:05:51.10#ibcon#first serial, iclass 33, count 0 2006.210.08:05:51.10#ibcon#enter sib2, iclass 33, count 0 2006.210.08:05:51.10#ibcon#flushed, iclass 33, count 0 2006.210.08:05:51.10#ibcon#about to write, iclass 33, count 0 2006.210.08:05:51.10#ibcon#wrote, iclass 33, count 0 2006.210.08:05:51.10#ibcon#about to read 3, iclass 33, count 0 2006.210.08:05:51.12#ibcon#read 3, iclass 33, count 0 2006.210.08:05:51.12#ibcon#about to read 4, iclass 33, count 0 2006.210.08:05:51.12#ibcon#read 4, iclass 33, count 0 2006.210.08:05:51.12#ibcon#about to read 5, iclass 33, count 0 2006.210.08:05:51.12#ibcon#read 5, iclass 33, count 0 2006.210.08:05:51.12#ibcon#about to read 6, iclass 33, count 0 2006.210.08:05:51.12#ibcon#read 6, iclass 33, count 0 2006.210.08:05:51.12#ibcon#end of sib2, iclass 33, count 0 2006.210.08:05:51.12#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:05:51.12#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:05:51.12#ibcon#[27=USB\r\n] 2006.210.08:05:51.12#ibcon#*before write, iclass 33, count 0 2006.210.08:05:51.12#ibcon#enter sib2, iclass 33, count 0 2006.210.08:05:51.12#ibcon#flushed, iclass 33, count 0 2006.210.08:05:51.12#ibcon#about to write, iclass 33, count 0 2006.210.08:05:51.12#ibcon#wrote, iclass 33, count 0 2006.210.08:05:51.12#ibcon#about to read 3, iclass 33, count 0 2006.210.08:05:51.15#ibcon#read 3, iclass 33, count 0 2006.210.08:05:51.15#ibcon#about to read 4, iclass 33, count 0 2006.210.08:05:51.15#ibcon#read 4, iclass 33, count 0 2006.210.08:05:51.15#ibcon#about to read 5, iclass 33, count 0 2006.210.08:05:51.15#ibcon#read 5, iclass 33, count 0 2006.210.08:05:51.15#ibcon#about to read 6, iclass 33, count 0 2006.210.08:05:51.15#ibcon#read 6, iclass 33, count 0 2006.210.08:05:51.15#ibcon#end of sib2, iclass 33, count 0 2006.210.08:05:51.15#ibcon#*after write, iclass 33, count 0 2006.210.08:05:51.15#ibcon#*before return 0, iclass 33, count 0 2006.210.08:05:51.15#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:51.15#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:05:51.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:05:51.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:05:51.15$vc4f8/vblo=4,712.99 2006.210.08:05:51.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:05:51.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:05:51.15#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:51.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:51.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:51.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:51.15#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:05:51.15#ibcon#first serial, iclass 35, count 0 2006.210.08:05:51.15#ibcon#enter sib2, iclass 35, count 0 2006.210.08:05:51.15#ibcon#flushed, iclass 35, count 0 2006.210.08:05:51.15#ibcon#about to write, iclass 35, count 0 2006.210.08:05:51.15#ibcon#wrote, iclass 35, count 0 2006.210.08:05:51.15#ibcon#about to read 3, iclass 35, count 0 2006.210.08:05:51.17#ibcon#read 3, iclass 35, count 0 2006.210.08:05:51.17#ibcon#about to read 4, iclass 35, count 0 2006.210.08:05:51.17#ibcon#read 4, iclass 35, count 0 2006.210.08:05:51.17#ibcon#about to read 5, iclass 35, count 0 2006.210.08:05:51.17#ibcon#read 5, iclass 35, count 0 2006.210.08:05:51.17#ibcon#about to read 6, iclass 35, count 0 2006.210.08:05:51.17#ibcon#read 6, iclass 35, count 0 2006.210.08:05:51.17#ibcon#end of sib2, iclass 35, count 0 2006.210.08:05:51.17#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:05:51.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:05:51.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:05:51.17#ibcon#*before write, iclass 35, count 0 2006.210.08:05:51.17#ibcon#enter sib2, iclass 35, count 0 2006.210.08:05:51.17#ibcon#flushed, iclass 35, count 0 2006.210.08:05:51.17#ibcon#about to write, iclass 35, count 0 2006.210.08:05:51.17#ibcon#wrote, iclass 35, count 0 2006.210.08:05:51.17#ibcon#about to read 3, iclass 35, count 0 2006.210.08:05:51.21#ibcon#read 3, iclass 35, count 0 2006.210.08:05:51.21#ibcon#about to read 4, iclass 35, count 0 2006.210.08:05:51.21#ibcon#read 4, iclass 35, count 0 2006.210.08:05:51.21#ibcon#about to read 5, iclass 35, count 0 2006.210.08:05:51.21#ibcon#read 5, iclass 35, count 0 2006.210.08:05:51.21#ibcon#about to read 6, iclass 35, count 0 2006.210.08:05:51.21#ibcon#read 6, iclass 35, count 0 2006.210.08:05:51.21#ibcon#end of sib2, iclass 35, count 0 2006.210.08:05:51.21#ibcon#*after write, iclass 35, count 0 2006.210.08:05:51.21#ibcon#*before return 0, iclass 35, count 0 2006.210.08:05:51.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:51.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:05:51.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:05:51.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:05:51.21$vc4f8/vb=4,3 2006.210.08:05:51.21#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.08:05:51.21#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.08:05:51.21#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:51.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:51.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:51.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:51.27#ibcon#enter wrdev, iclass 37, count 2 2006.210.08:05:51.27#ibcon#first serial, iclass 37, count 2 2006.210.08:05:51.27#ibcon#enter sib2, iclass 37, count 2 2006.210.08:05:51.27#ibcon#flushed, iclass 37, count 2 2006.210.08:05:51.27#ibcon#about to write, iclass 37, count 2 2006.210.08:05:51.27#ibcon#wrote, iclass 37, count 2 2006.210.08:05:51.27#ibcon#about to read 3, iclass 37, count 2 2006.210.08:05:51.29#ibcon#read 3, iclass 37, count 2 2006.210.08:05:51.29#ibcon#about to read 4, iclass 37, count 2 2006.210.08:05:51.29#ibcon#read 4, iclass 37, count 2 2006.210.08:05:51.29#ibcon#about to read 5, iclass 37, count 2 2006.210.08:05:51.29#ibcon#read 5, iclass 37, count 2 2006.210.08:05:51.29#ibcon#about to read 6, iclass 37, count 2 2006.210.08:05:51.29#ibcon#read 6, iclass 37, count 2 2006.210.08:05:51.29#ibcon#end of sib2, iclass 37, count 2 2006.210.08:05:51.29#ibcon#*mode == 0, iclass 37, count 2 2006.210.08:05:51.29#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.08:05:51.29#ibcon#[27=AT04-03\r\n] 2006.210.08:05:51.29#ibcon#*before write, iclass 37, count 2 2006.210.08:05:51.29#ibcon#enter sib2, iclass 37, count 2 2006.210.08:05:51.29#ibcon#flushed, iclass 37, count 2 2006.210.08:05:51.29#ibcon#about to write, iclass 37, count 2 2006.210.08:05:51.29#ibcon#wrote, iclass 37, count 2 2006.210.08:05:51.29#ibcon#about to read 3, iclass 37, count 2 2006.210.08:05:51.32#ibcon#read 3, iclass 37, count 2 2006.210.08:05:51.32#ibcon#about to read 4, iclass 37, count 2 2006.210.08:05:51.32#ibcon#read 4, iclass 37, count 2 2006.210.08:05:51.32#ibcon#about to read 5, iclass 37, count 2 2006.210.08:05:51.32#ibcon#read 5, iclass 37, count 2 2006.210.08:05:51.32#ibcon#about to read 6, iclass 37, count 2 2006.210.08:05:51.32#ibcon#read 6, iclass 37, count 2 2006.210.08:05:51.32#ibcon#end of sib2, iclass 37, count 2 2006.210.08:05:51.32#ibcon#*after write, iclass 37, count 2 2006.210.08:05:51.32#ibcon#*before return 0, iclass 37, count 2 2006.210.08:05:51.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:51.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:05:51.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.08:05:51.32#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:51.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:51.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:51.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:51.44#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:05:51.44#ibcon#first serial, iclass 37, count 0 2006.210.08:05:51.44#ibcon#enter sib2, iclass 37, count 0 2006.210.08:05:51.44#ibcon#flushed, iclass 37, count 0 2006.210.08:05:51.44#ibcon#about to write, iclass 37, count 0 2006.210.08:05:51.44#ibcon#wrote, iclass 37, count 0 2006.210.08:05:51.44#ibcon#about to read 3, iclass 37, count 0 2006.210.08:05:51.46#ibcon#read 3, iclass 37, count 0 2006.210.08:05:51.46#ibcon#about to read 4, iclass 37, count 0 2006.210.08:05:51.46#ibcon#read 4, iclass 37, count 0 2006.210.08:05:51.46#ibcon#about to read 5, iclass 37, count 0 2006.210.08:05:51.46#ibcon#read 5, iclass 37, count 0 2006.210.08:05:51.46#ibcon#about to read 6, iclass 37, count 0 2006.210.08:05:51.46#ibcon#read 6, iclass 37, count 0 2006.210.08:05:51.46#ibcon#end of sib2, iclass 37, count 0 2006.210.08:05:51.46#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:05:51.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:05:51.46#ibcon#[27=USB\r\n] 2006.210.08:05:51.46#ibcon#*before write, iclass 37, count 0 2006.210.08:05:51.46#ibcon#enter sib2, iclass 37, count 0 2006.210.08:05:51.46#ibcon#flushed, iclass 37, count 0 2006.210.08:05:51.46#ibcon#about to write, iclass 37, count 0 2006.210.08:05:51.46#ibcon#wrote, iclass 37, count 0 2006.210.08:05:51.46#ibcon#about to read 3, iclass 37, count 0 2006.210.08:05:51.49#ibcon#read 3, iclass 37, count 0 2006.210.08:05:51.49#ibcon#about to read 4, iclass 37, count 0 2006.210.08:05:51.49#ibcon#read 4, iclass 37, count 0 2006.210.08:05:51.49#ibcon#about to read 5, iclass 37, count 0 2006.210.08:05:51.49#ibcon#read 5, iclass 37, count 0 2006.210.08:05:51.49#ibcon#about to read 6, iclass 37, count 0 2006.210.08:05:51.49#ibcon#read 6, iclass 37, count 0 2006.210.08:05:51.49#ibcon#end of sib2, iclass 37, count 0 2006.210.08:05:51.49#ibcon#*after write, iclass 37, count 0 2006.210.08:05:51.49#ibcon#*before return 0, iclass 37, count 0 2006.210.08:05:51.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:51.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:05:51.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:05:51.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:05:51.49$vc4f8/vblo=5,744.99 2006.210.08:05:51.49#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.08:05:51.49#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.08:05:51.49#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:51.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:51.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:51.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:51.49#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:05:51.49#ibcon#first serial, iclass 39, count 0 2006.210.08:05:51.49#ibcon#enter sib2, iclass 39, count 0 2006.210.08:05:51.49#ibcon#flushed, iclass 39, count 0 2006.210.08:05:51.49#ibcon#about to write, iclass 39, count 0 2006.210.08:05:51.49#ibcon#wrote, iclass 39, count 0 2006.210.08:05:51.49#ibcon#about to read 3, iclass 39, count 0 2006.210.08:05:51.51#ibcon#read 3, iclass 39, count 0 2006.210.08:05:51.51#ibcon#about to read 4, iclass 39, count 0 2006.210.08:05:51.51#ibcon#read 4, iclass 39, count 0 2006.210.08:05:51.51#ibcon#about to read 5, iclass 39, count 0 2006.210.08:05:51.51#ibcon#read 5, iclass 39, count 0 2006.210.08:05:51.51#ibcon#about to read 6, iclass 39, count 0 2006.210.08:05:51.51#ibcon#read 6, iclass 39, count 0 2006.210.08:05:51.51#ibcon#end of sib2, iclass 39, count 0 2006.210.08:05:51.51#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:05:51.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:05:51.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:05:51.51#ibcon#*before write, iclass 39, count 0 2006.210.08:05:51.51#ibcon#enter sib2, iclass 39, count 0 2006.210.08:05:51.51#ibcon#flushed, iclass 39, count 0 2006.210.08:05:51.51#ibcon#about to write, iclass 39, count 0 2006.210.08:05:51.51#ibcon#wrote, iclass 39, count 0 2006.210.08:05:51.51#ibcon#about to read 3, iclass 39, count 0 2006.210.08:05:51.55#ibcon#read 3, iclass 39, count 0 2006.210.08:05:51.55#ibcon#about to read 4, iclass 39, count 0 2006.210.08:05:51.55#ibcon#read 4, iclass 39, count 0 2006.210.08:05:51.55#ibcon#about to read 5, iclass 39, count 0 2006.210.08:05:51.55#ibcon#read 5, iclass 39, count 0 2006.210.08:05:51.55#ibcon#about to read 6, iclass 39, count 0 2006.210.08:05:51.55#ibcon#read 6, iclass 39, count 0 2006.210.08:05:51.55#ibcon#end of sib2, iclass 39, count 0 2006.210.08:05:51.55#ibcon#*after write, iclass 39, count 0 2006.210.08:05:51.55#ibcon#*before return 0, iclass 39, count 0 2006.210.08:05:51.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:51.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:05:51.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:05:51.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:05:51.55$vc4f8/vb=5,3 2006.210.08:05:51.55#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.08:05:51.55#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.08:05:51.55#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:51.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:51.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:51.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:51.61#ibcon#enter wrdev, iclass 3, count 2 2006.210.08:05:51.61#ibcon#first serial, iclass 3, count 2 2006.210.08:05:51.61#ibcon#enter sib2, iclass 3, count 2 2006.210.08:05:51.61#ibcon#flushed, iclass 3, count 2 2006.210.08:05:51.61#ibcon#about to write, iclass 3, count 2 2006.210.08:05:51.61#ibcon#wrote, iclass 3, count 2 2006.210.08:05:51.61#ibcon#about to read 3, iclass 3, count 2 2006.210.08:05:51.63#ibcon#read 3, iclass 3, count 2 2006.210.08:05:51.63#ibcon#about to read 4, iclass 3, count 2 2006.210.08:05:51.63#ibcon#read 4, iclass 3, count 2 2006.210.08:05:51.63#ibcon#about to read 5, iclass 3, count 2 2006.210.08:05:51.63#ibcon#read 5, iclass 3, count 2 2006.210.08:05:51.63#ibcon#about to read 6, iclass 3, count 2 2006.210.08:05:51.63#ibcon#read 6, iclass 3, count 2 2006.210.08:05:51.63#ibcon#end of sib2, iclass 3, count 2 2006.210.08:05:51.63#ibcon#*mode == 0, iclass 3, count 2 2006.210.08:05:51.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.08:05:51.63#ibcon#[27=AT05-03\r\n] 2006.210.08:05:51.63#ibcon#*before write, iclass 3, count 2 2006.210.08:05:51.63#ibcon#enter sib2, iclass 3, count 2 2006.210.08:05:51.63#ibcon#flushed, iclass 3, count 2 2006.210.08:05:51.63#ibcon#about to write, iclass 3, count 2 2006.210.08:05:51.63#ibcon#wrote, iclass 3, count 2 2006.210.08:05:51.63#ibcon#about to read 3, iclass 3, count 2 2006.210.08:05:51.66#ibcon#read 3, iclass 3, count 2 2006.210.08:05:51.66#ibcon#about to read 4, iclass 3, count 2 2006.210.08:05:51.66#ibcon#read 4, iclass 3, count 2 2006.210.08:05:51.66#ibcon#about to read 5, iclass 3, count 2 2006.210.08:05:51.66#ibcon#read 5, iclass 3, count 2 2006.210.08:05:51.66#ibcon#about to read 6, iclass 3, count 2 2006.210.08:05:51.66#ibcon#read 6, iclass 3, count 2 2006.210.08:05:51.66#ibcon#end of sib2, iclass 3, count 2 2006.210.08:05:51.66#ibcon#*after write, iclass 3, count 2 2006.210.08:05:51.66#ibcon#*before return 0, iclass 3, count 2 2006.210.08:05:51.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:51.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:05:51.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.08:05:51.66#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:51.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:51.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:51.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:51.78#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:05:51.78#ibcon#first serial, iclass 3, count 0 2006.210.08:05:51.78#ibcon#enter sib2, iclass 3, count 0 2006.210.08:05:51.78#ibcon#flushed, iclass 3, count 0 2006.210.08:05:51.78#ibcon#about to write, iclass 3, count 0 2006.210.08:05:51.78#ibcon#wrote, iclass 3, count 0 2006.210.08:05:51.78#ibcon#about to read 3, iclass 3, count 0 2006.210.08:05:51.80#ibcon#read 3, iclass 3, count 0 2006.210.08:05:51.80#ibcon#about to read 4, iclass 3, count 0 2006.210.08:05:51.80#ibcon#read 4, iclass 3, count 0 2006.210.08:05:51.80#ibcon#about to read 5, iclass 3, count 0 2006.210.08:05:51.80#ibcon#read 5, iclass 3, count 0 2006.210.08:05:51.80#ibcon#about to read 6, iclass 3, count 0 2006.210.08:05:51.80#ibcon#read 6, iclass 3, count 0 2006.210.08:05:51.80#ibcon#end of sib2, iclass 3, count 0 2006.210.08:05:51.80#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:05:51.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:05:51.80#ibcon#[27=USB\r\n] 2006.210.08:05:51.80#ibcon#*before write, iclass 3, count 0 2006.210.08:05:51.80#ibcon#enter sib2, iclass 3, count 0 2006.210.08:05:51.80#ibcon#flushed, iclass 3, count 0 2006.210.08:05:51.80#ibcon#about to write, iclass 3, count 0 2006.210.08:05:51.80#ibcon#wrote, iclass 3, count 0 2006.210.08:05:51.80#ibcon#about to read 3, iclass 3, count 0 2006.210.08:05:51.83#ibcon#read 3, iclass 3, count 0 2006.210.08:05:51.83#ibcon#about to read 4, iclass 3, count 0 2006.210.08:05:51.83#ibcon#read 4, iclass 3, count 0 2006.210.08:05:51.83#ibcon#about to read 5, iclass 3, count 0 2006.210.08:05:51.83#ibcon#read 5, iclass 3, count 0 2006.210.08:05:51.83#ibcon#about to read 6, iclass 3, count 0 2006.210.08:05:51.83#ibcon#read 6, iclass 3, count 0 2006.210.08:05:51.83#ibcon#end of sib2, iclass 3, count 0 2006.210.08:05:51.83#ibcon#*after write, iclass 3, count 0 2006.210.08:05:51.83#ibcon#*before return 0, iclass 3, count 0 2006.210.08:05:51.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:51.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:05:51.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:05:51.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:05:51.83$vc4f8/vblo=6,752.99 2006.210.08:05:51.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.08:05:51.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.08:05:51.83#ibcon#ireg 17 cls_cnt 0 2006.210.08:05:51.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:51.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:51.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:51.83#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:05:51.83#ibcon#first serial, iclass 5, count 0 2006.210.08:05:51.83#ibcon#enter sib2, iclass 5, count 0 2006.210.08:05:51.83#ibcon#flushed, iclass 5, count 0 2006.210.08:05:51.83#ibcon#about to write, iclass 5, count 0 2006.210.08:05:51.83#ibcon#wrote, iclass 5, count 0 2006.210.08:05:51.83#ibcon#about to read 3, iclass 5, count 0 2006.210.08:05:51.85#ibcon#read 3, iclass 5, count 0 2006.210.08:05:51.85#ibcon#about to read 4, iclass 5, count 0 2006.210.08:05:51.85#ibcon#read 4, iclass 5, count 0 2006.210.08:05:51.85#ibcon#about to read 5, iclass 5, count 0 2006.210.08:05:51.85#ibcon#read 5, iclass 5, count 0 2006.210.08:05:51.85#ibcon#about to read 6, iclass 5, count 0 2006.210.08:05:51.85#ibcon#read 6, iclass 5, count 0 2006.210.08:05:51.85#ibcon#end of sib2, iclass 5, count 0 2006.210.08:05:51.85#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:05:51.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:05:51.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:05:51.85#ibcon#*before write, iclass 5, count 0 2006.210.08:05:51.85#ibcon#enter sib2, iclass 5, count 0 2006.210.08:05:51.85#ibcon#flushed, iclass 5, count 0 2006.210.08:05:51.85#ibcon#about to write, iclass 5, count 0 2006.210.08:05:51.85#ibcon#wrote, iclass 5, count 0 2006.210.08:05:51.85#ibcon#about to read 3, iclass 5, count 0 2006.210.08:05:51.89#ibcon#read 3, iclass 5, count 0 2006.210.08:05:51.89#ibcon#about to read 4, iclass 5, count 0 2006.210.08:05:51.89#ibcon#read 4, iclass 5, count 0 2006.210.08:05:51.89#ibcon#about to read 5, iclass 5, count 0 2006.210.08:05:51.89#ibcon#read 5, iclass 5, count 0 2006.210.08:05:51.89#ibcon#about to read 6, iclass 5, count 0 2006.210.08:05:51.89#ibcon#read 6, iclass 5, count 0 2006.210.08:05:51.89#ibcon#end of sib2, iclass 5, count 0 2006.210.08:05:51.89#ibcon#*after write, iclass 5, count 0 2006.210.08:05:51.89#ibcon#*before return 0, iclass 5, count 0 2006.210.08:05:51.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:51.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:05:51.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:05:51.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:05:51.89$vc4f8/vb=6,3 2006.210.08:05:51.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.08:05:51.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.08:05:51.89#ibcon#ireg 11 cls_cnt 2 2006.210.08:05:51.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:51.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:51.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:51.95#ibcon#enter wrdev, iclass 7, count 2 2006.210.08:05:51.95#ibcon#first serial, iclass 7, count 2 2006.210.08:05:51.95#ibcon#enter sib2, iclass 7, count 2 2006.210.08:05:51.95#ibcon#flushed, iclass 7, count 2 2006.210.08:05:51.95#ibcon#about to write, iclass 7, count 2 2006.210.08:05:51.95#ibcon#wrote, iclass 7, count 2 2006.210.08:05:51.95#ibcon#about to read 3, iclass 7, count 2 2006.210.08:05:51.97#ibcon#read 3, iclass 7, count 2 2006.210.08:05:51.97#ibcon#about to read 4, iclass 7, count 2 2006.210.08:05:51.97#ibcon#read 4, iclass 7, count 2 2006.210.08:05:51.97#ibcon#about to read 5, iclass 7, count 2 2006.210.08:05:51.97#ibcon#read 5, iclass 7, count 2 2006.210.08:05:51.97#ibcon#about to read 6, iclass 7, count 2 2006.210.08:05:51.97#ibcon#read 6, iclass 7, count 2 2006.210.08:05:51.97#ibcon#end of sib2, iclass 7, count 2 2006.210.08:05:51.97#ibcon#*mode == 0, iclass 7, count 2 2006.210.08:05:51.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.08:05:51.97#ibcon#[27=AT06-03\r\n] 2006.210.08:05:51.97#ibcon#*before write, iclass 7, count 2 2006.210.08:05:51.97#ibcon#enter sib2, iclass 7, count 2 2006.210.08:05:51.97#ibcon#flushed, iclass 7, count 2 2006.210.08:05:51.97#ibcon#about to write, iclass 7, count 2 2006.210.08:05:51.97#ibcon#wrote, iclass 7, count 2 2006.210.08:05:51.97#ibcon#about to read 3, iclass 7, count 2 2006.210.08:05:52.00#ibcon#read 3, iclass 7, count 2 2006.210.08:05:52.00#ibcon#about to read 4, iclass 7, count 2 2006.210.08:05:52.00#ibcon#read 4, iclass 7, count 2 2006.210.08:05:52.00#ibcon#about to read 5, iclass 7, count 2 2006.210.08:05:52.00#ibcon#read 5, iclass 7, count 2 2006.210.08:05:52.00#ibcon#about to read 6, iclass 7, count 2 2006.210.08:05:52.00#ibcon#read 6, iclass 7, count 2 2006.210.08:05:52.00#ibcon#end of sib2, iclass 7, count 2 2006.210.08:05:52.00#ibcon#*after write, iclass 7, count 2 2006.210.08:05:52.00#ibcon#*before return 0, iclass 7, count 2 2006.210.08:05:52.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:52.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:05:52.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.08:05:52.00#ibcon#ireg 7 cls_cnt 0 2006.210.08:05:52.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:52.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:52.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:52.12#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:05:52.12#ibcon#first serial, iclass 7, count 0 2006.210.08:05:52.12#ibcon#enter sib2, iclass 7, count 0 2006.210.08:05:52.12#ibcon#flushed, iclass 7, count 0 2006.210.08:05:52.12#ibcon#about to write, iclass 7, count 0 2006.210.08:05:52.12#ibcon#wrote, iclass 7, count 0 2006.210.08:05:52.12#ibcon#about to read 3, iclass 7, count 0 2006.210.08:05:52.14#ibcon#read 3, iclass 7, count 0 2006.210.08:05:52.14#ibcon#about to read 4, iclass 7, count 0 2006.210.08:05:52.14#ibcon#read 4, iclass 7, count 0 2006.210.08:05:52.14#ibcon#about to read 5, iclass 7, count 0 2006.210.08:05:52.14#ibcon#read 5, iclass 7, count 0 2006.210.08:05:52.14#ibcon#about to read 6, iclass 7, count 0 2006.210.08:05:52.14#ibcon#read 6, iclass 7, count 0 2006.210.08:05:52.14#ibcon#end of sib2, iclass 7, count 0 2006.210.08:05:52.14#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:05:52.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:05:52.14#ibcon#[27=USB\r\n] 2006.210.08:05:52.14#ibcon#*before write, iclass 7, count 0 2006.210.08:05:52.14#ibcon#enter sib2, iclass 7, count 0 2006.210.08:05:52.14#ibcon#flushed, iclass 7, count 0 2006.210.08:05:52.14#ibcon#about to write, iclass 7, count 0 2006.210.08:05:52.14#ibcon#wrote, iclass 7, count 0 2006.210.08:05:52.14#ibcon#about to read 3, iclass 7, count 0 2006.210.08:05:52.17#ibcon#read 3, iclass 7, count 0 2006.210.08:05:52.17#ibcon#about to read 4, iclass 7, count 0 2006.210.08:05:52.17#ibcon#read 4, iclass 7, count 0 2006.210.08:05:52.17#ibcon#about to read 5, iclass 7, count 0 2006.210.08:05:52.17#ibcon#read 5, iclass 7, count 0 2006.210.08:05:52.17#ibcon#about to read 6, iclass 7, count 0 2006.210.08:05:52.17#ibcon#read 6, iclass 7, count 0 2006.210.08:05:52.17#ibcon#end of sib2, iclass 7, count 0 2006.210.08:05:52.17#ibcon#*after write, iclass 7, count 0 2006.210.08:05:52.17#ibcon#*before return 0, iclass 7, count 0 2006.210.08:05:52.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:52.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:05:52.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:05:52.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:05:52.17$vc4f8/vabw=wide 2006.210.08:05:52.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.08:05:52.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.08:05:52.17#ibcon#ireg 8 cls_cnt 0 2006.210.08:05:52.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:52.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:52.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:52.17#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:05:52.17#ibcon#first serial, iclass 11, count 0 2006.210.08:05:52.17#ibcon#enter sib2, iclass 11, count 0 2006.210.08:05:52.17#ibcon#flushed, iclass 11, count 0 2006.210.08:05:52.17#ibcon#about to write, iclass 11, count 0 2006.210.08:05:52.17#ibcon#wrote, iclass 11, count 0 2006.210.08:05:52.17#ibcon#about to read 3, iclass 11, count 0 2006.210.08:05:52.19#ibcon#read 3, iclass 11, count 0 2006.210.08:05:52.19#ibcon#about to read 4, iclass 11, count 0 2006.210.08:05:52.19#ibcon#read 4, iclass 11, count 0 2006.210.08:05:52.19#ibcon#about to read 5, iclass 11, count 0 2006.210.08:05:52.19#ibcon#read 5, iclass 11, count 0 2006.210.08:05:52.19#ibcon#about to read 6, iclass 11, count 0 2006.210.08:05:52.19#ibcon#read 6, iclass 11, count 0 2006.210.08:05:52.19#ibcon#end of sib2, iclass 11, count 0 2006.210.08:05:52.19#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:05:52.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:05:52.19#ibcon#[25=BW32\r\n] 2006.210.08:05:52.19#ibcon#*before write, iclass 11, count 0 2006.210.08:05:52.19#ibcon#enter sib2, iclass 11, count 0 2006.210.08:05:52.19#ibcon#flushed, iclass 11, count 0 2006.210.08:05:52.19#ibcon#about to write, iclass 11, count 0 2006.210.08:05:52.19#ibcon#wrote, iclass 11, count 0 2006.210.08:05:52.19#ibcon#about to read 3, iclass 11, count 0 2006.210.08:05:52.22#ibcon#read 3, iclass 11, count 0 2006.210.08:05:52.22#ibcon#about to read 4, iclass 11, count 0 2006.210.08:05:52.22#ibcon#read 4, iclass 11, count 0 2006.210.08:05:52.22#ibcon#about to read 5, iclass 11, count 0 2006.210.08:05:52.22#ibcon#read 5, iclass 11, count 0 2006.210.08:05:52.22#ibcon#about to read 6, iclass 11, count 0 2006.210.08:05:52.22#ibcon#read 6, iclass 11, count 0 2006.210.08:05:52.22#ibcon#end of sib2, iclass 11, count 0 2006.210.08:05:52.22#ibcon#*after write, iclass 11, count 0 2006.210.08:05:52.22#ibcon#*before return 0, iclass 11, count 0 2006.210.08:05:52.22#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:52.22#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:05:52.22#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:05:52.22#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:05:52.22$vc4f8/vbbw=wide 2006.210.08:05:52.22#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:05:52.22#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:05:52.22#ibcon#ireg 8 cls_cnt 0 2006.210.08:05:52.22#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:05:52.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:05:52.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:05:52.29#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:05:52.29#ibcon#first serial, iclass 13, count 0 2006.210.08:05:52.29#ibcon#enter sib2, iclass 13, count 0 2006.210.08:05:52.29#ibcon#flushed, iclass 13, count 0 2006.210.08:05:52.29#ibcon#about to write, iclass 13, count 0 2006.210.08:05:52.29#ibcon#wrote, iclass 13, count 0 2006.210.08:05:52.29#ibcon#about to read 3, iclass 13, count 0 2006.210.08:05:52.31#ibcon#read 3, iclass 13, count 0 2006.210.08:05:52.31#ibcon#about to read 4, iclass 13, count 0 2006.210.08:05:52.31#ibcon#read 4, iclass 13, count 0 2006.210.08:05:52.31#ibcon#about to read 5, iclass 13, count 0 2006.210.08:05:52.31#ibcon#read 5, iclass 13, count 0 2006.210.08:05:52.31#ibcon#about to read 6, iclass 13, count 0 2006.210.08:05:52.31#ibcon#read 6, iclass 13, count 0 2006.210.08:05:52.31#ibcon#end of sib2, iclass 13, count 0 2006.210.08:05:52.31#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:05:52.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:05:52.31#ibcon#[27=BW32\r\n] 2006.210.08:05:52.31#ibcon#*before write, iclass 13, count 0 2006.210.08:05:52.31#ibcon#enter sib2, iclass 13, count 0 2006.210.08:05:52.31#ibcon#flushed, iclass 13, count 0 2006.210.08:05:52.31#ibcon#about to write, iclass 13, count 0 2006.210.08:05:52.31#ibcon#wrote, iclass 13, count 0 2006.210.08:05:52.31#ibcon#about to read 3, iclass 13, count 0 2006.210.08:05:52.34#ibcon#read 3, iclass 13, count 0 2006.210.08:05:52.34#ibcon#about to read 4, iclass 13, count 0 2006.210.08:05:52.34#ibcon#read 4, iclass 13, count 0 2006.210.08:05:52.34#ibcon#about to read 5, iclass 13, count 0 2006.210.08:05:52.34#ibcon#read 5, iclass 13, count 0 2006.210.08:05:52.34#ibcon#about to read 6, iclass 13, count 0 2006.210.08:05:52.34#ibcon#read 6, iclass 13, count 0 2006.210.08:05:52.34#ibcon#end of sib2, iclass 13, count 0 2006.210.08:05:52.34#ibcon#*after write, iclass 13, count 0 2006.210.08:05:52.34#ibcon#*before return 0, iclass 13, count 0 2006.210.08:05:52.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:05:52.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:05:52.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:05:52.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:05:52.34$4f8m12a/ifd4f 2006.210.08:05:52.34$ifd4f/lo= 2006.210.08:05:52.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:05:52.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:05:52.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:05:52.34$ifd4f/patch= 2006.210.08:05:52.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:05:52.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:05:52.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:05:52.34$4f8m12a/"form=m,16.000,1:2 2006.210.08:05:52.34$4f8m12a/"tpicd 2006.210.08:05:52.34$4f8m12a/echo=off 2006.210.08:05:52.34$4f8m12a/xlog=off 2006.210.08:05:52.34:!2006.210.08:06:20 2006.210.08:06:01.13#trakl#Source acquired 2006.210.08:06:02.13#flagr#flagr/antenna,acquired 2006.210.08:06:20.00:preob 2006.210.08:06:21.13/onsource/TRACKING 2006.210.08:06:21.13:!2006.210.08:06:30 2006.210.08:06:30.00:data_valid=on 2006.210.08:06:30.00:midob 2006.210.08:06:30.13/onsource/TRACKING 2006.210.08:06:30.13/wx/30.31,1006.4,82 2006.210.08:06:30.26/cable/+6.3934E-03 2006.210.08:06:31.35/va/01,08,usb,yes,30,32 2006.210.08:06:31.35/va/02,07,usb,yes,30,32 2006.210.08:06:31.35/va/03,06,usb,yes,32,32 2006.210.08:06:31.35/va/04,07,usb,yes,31,33 2006.210.08:06:31.35/va/05,07,usb,yes,32,34 2006.210.08:06:31.35/va/06,06,usb,yes,31,31 2006.210.08:06:31.35/va/07,06,usb,yes,32,32 2006.210.08:06:31.35/va/08,07,usb,yes,30,30 2006.210.08:06:31.58/valo/01,532.99,yes,locked 2006.210.08:06:31.58/valo/02,572.99,yes,locked 2006.210.08:06:31.58/valo/03,672.99,yes,locked 2006.210.08:06:31.58/valo/04,832.99,yes,locked 2006.210.08:06:31.58/valo/05,652.99,yes,locked 2006.210.08:06:31.58/valo/06,772.99,yes,locked 2006.210.08:06:31.58/valo/07,832.99,yes,locked 2006.210.08:06:31.58/valo/08,852.99,yes,locked 2006.210.08:06:32.67/vb/01,04,usb,yes,29,28 2006.210.08:06:32.67/vb/02,04,usb,yes,31,32 2006.210.08:06:32.67/vb/03,03,usb,yes,34,39 2006.210.08:06:32.67/vb/04,03,usb,yes,35,35 2006.210.08:06:32.67/vb/05,03,usb,yes,34,38 2006.210.08:06:32.67/vb/06,03,usb,yes,34,38 2006.210.08:06:32.67/vb/07,04,usb,yes,30,30 2006.210.08:06:32.67/vb/08,03,usb,yes,34,38 2006.210.08:06:32.90/vblo/01,632.99,yes,locked 2006.210.08:06:32.90/vblo/02,640.99,yes,locked 2006.210.08:06:32.90/vblo/03,656.99,yes,locked 2006.210.08:06:32.90/vblo/04,712.99,yes,locked 2006.210.08:06:32.90/vblo/05,744.99,yes,locked 2006.210.08:06:32.90/vblo/06,752.99,yes,locked 2006.210.08:06:32.90/vblo/07,734.99,yes,locked 2006.210.08:06:32.90/vblo/08,744.99,yes,locked 2006.210.08:06:33.05/vabw/8 2006.210.08:06:33.20/vbbw/8 2006.210.08:06:33.29/xfe/off,on,13.0 2006.210.08:06:33.67/ifatt/23,28,28,28 2006.210.08:06:34.08/fmout-gps/S +4.61E-07 2006.210.08:06:34.12:!2006.210.08:07:30 2006.210.08:07:30.02:data_valid=off 2006.210.08:07:30.02:postob 2006.210.08:07:30.18/cable/+6.3944E-03 2006.210.08:07:30.19/wx/30.27,1006.4,81 2006.210.08:07:31.07/fmout-gps/S +4.62E-07 2006.210.08:07:31.08:scan_name=210-0808,k06210,60 2006.210.08:07:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.210.08:07:31.13#flagr#flagr/antenna,new-source 2006.210.08:07:32.14:checkk5 2006.210.08:07:32.47/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:07:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:07:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:07:33.50/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:07:33.83/chk_obsdata//k5ts1/T2100806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:07:34.16/chk_obsdata//k5ts2/T2100806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:07:34.50/chk_obsdata//k5ts3/T2100806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:07:34.83/chk_obsdata//k5ts4/T2100806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:07:35.50/k5log//k5ts1_log_newline 2006.210.08:07:36.16/k5log//k5ts2_log_newline 2006.210.08:07:36.81/k5log//k5ts3_log_newline 2006.210.08:07:37.48/k5log//k5ts4_log_newline 2006.210.08:07:37.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:07:37.51:4f8m12a=2 2006.210.08:07:37.51$4f8m12a/echo=on 2006.210.08:07:37.51$4f8m12a/pcalon 2006.210.08:07:37.51$pcalon/"no phase cal control is implemented here 2006.210.08:07:37.51$4f8m12a/"tpicd=stop 2006.210.08:07:37.51$4f8m12a/vc4f8 2006.210.08:07:37.51$vc4f8/valo=1,532.99 2006.210.08:07:37.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.08:07:37.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.08:07:37.51#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:37.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:37.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:37.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:37.51#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:07:37.51#ibcon#first serial, iclass 24, count 0 2006.210.08:07:37.51#ibcon#enter sib2, iclass 24, count 0 2006.210.08:07:37.51#ibcon#flushed, iclass 24, count 0 2006.210.08:07:37.51#ibcon#about to write, iclass 24, count 0 2006.210.08:07:37.51#ibcon#wrote, iclass 24, count 0 2006.210.08:07:37.51#ibcon#about to read 3, iclass 24, count 0 2006.210.08:07:37.52#ibcon#read 3, iclass 24, count 0 2006.210.08:07:37.52#ibcon#about to read 4, iclass 24, count 0 2006.210.08:07:37.52#ibcon#read 4, iclass 24, count 0 2006.210.08:07:37.52#ibcon#about to read 5, iclass 24, count 0 2006.210.08:07:37.52#ibcon#read 5, iclass 24, count 0 2006.210.08:07:37.52#ibcon#about to read 6, iclass 24, count 0 2006.210.08:07:37.52#ibcon#read 6, iclass 24, count 0 2006.210.08:07:37.52#ibcon#end of sib2, iclass 24, count 0 2006.210.08:07:37.52#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:07:37.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:07:37.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:07:37.52#ibcon#*before write, iclass 24, count 0 2006.210.08:07:37.52#ibcon#enter sib2, iclass 24, count 0 2006.210.08:07:37.53#ibcon#flushed, iclass 24, count 0 2006.210.08:07:37.53#ibcon#about to write, iclass 24, count 0 2006.210.08:07:37.53#ibcon#wrote, iclass 24, count 0 2006.210.08:07:37.53#ibcon#about to read 3, iclass 24, count 0 2006.210.08:07:37.57#ibcon#read 3, iclass 24, count 0 2006.210.08:07:37.57#ibcon#about to read 4, iclass 24, count 0 2006.210.08:07:37.57#ibcon#read 4, iclass 24, count 0 2006.210.08:07:37.57#ibcon#about to read 5, iclass 24, count 0 2006.210.08:07:37.57#ibcon#read 5, iclass 24, count 0 2006.210.08:07:37.57#ibcon#about to read 6, iclass 24, count 0 2006.210.08:07:37.57#ibcon#read 6, iclass 24, count 0 2006.210.08:07:37.57#ibcon#end of sib2, iclass 24, count 0 2006.210.08:07:37.57#ibcon#*after write, iclass 24, count 0 2006.210.08:07:37.57#ibcon#*before return 0, iclass 24, count 0 2006.210.08:07:37.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:37.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:37.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:07:37.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:07:37.58$vc4f8/va=1,8 2006.210.08:07:37.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.08:07:37.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.08:07:37.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:37.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:37.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:37.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:37.58#ibcon#enter wrdev, iclass 26, count 2 2006.210.08:07:37.58#ibcon#first serial, iclass 26, count 2 2006.210.08:07:37.58#ibcon#enter sib2, iclass 26, count 2 2006.210.08:07:37.58#ibcon#flushed, iclass 26, count 2 2006.210.08:07:37.58#ibcon#about to write, iclass 26, count 2 2006.210.08:07:37.58#ibcon#wrote, iclass 26, count 2 2006.210.08:07:37.58#ibcon#about to read 3, iclass 26, count 2 2006.210.08:07:37.59#ibcon#read 3, iclass 26, count 2 2006.210.08:07:37.59#ibcon#about to read 4, iclass 26, count 2 2006.210.08:07:37.59#ibcon#read 4, iclass 26, count 2 2006.210.08:07:37.59#ibcon#about to read 5, iclass 26, count 2 2006.210.08:07:37.59#ibcon#read 5, iclass 26, count 2 2006.210.08:07:37.59#ibcon#about to read 6, iclass 26, count 2 2006.210.08:07:37.59#ibcon#read 6, iclass 26, count 2 2006.210.08:07:37.59#ibcon#end of sib2, iclass 26, count 2 2006.210.08:07:37.59#ibcon#*mode == 0, iclass 26, count 2 2006.210.08:07:37.59#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.08:07:37.59#ibcon#[25=AT01-08\r\n] 2006.210.08:07:37.59#ibcon#*before write, iclass 26, count 2 2006.210.08:07:37.59#ibcon#enter sib2, iclass 26, count 2 2006.210.08:07:37.59#ibcon#flushed, iclass 26, count 2 2006.210.08:07:37.60#ibcon#about to write, iclass 26, count 2 2006.210.08:07:37.60#ibcon#wrote, iclass 26, count 2 2006.210.08:07:37.60#ibcon#about to read 3, iclass 26, count 2 2006.210.08:07:37.62#ibcon#read 3, iclass 26, count 2 2006.210.08:07:37.62#ibcon#about to read 4, iclass 26, count 2 2006.210.08:07:37.62#ibcon#read 4, iclass 26, count 2 2006.210.08:07:37.62#ibcon#about to read 5, iclass 26, count 2 2006.210.08:07:37.62#ibcon#read 5, iclass 26, count 2 2006.210.08:07:37.62#ibcon#about to read 6, iclass 26, count 2 2006.210.08:07:37.62#ibcon#read 6, iclass 26, count 2 2006.210.08:07:37.62#ibcon#end of sib2, iclass 26, count 2 2006.210.08:07:37.62#ibcon#*after write, iclass 26, count 2 2006.210.08:07:37.62#ibcon#*before return 0, iclass 26, count 2 2006.210.08:07:37.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:37.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:37.62#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.08:07:37.62#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:37.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:37.73#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:37.73#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:37.73#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:07:37.73#ibcon#first serial, iclass 26, count 0 2006.210.08:07:37.73#ibcon#enter sib2, iclass 26, count 0 2006.210.08:07:37.73#ibcon#flushed, iclass 26, count 0 2006.210.08:07:37.73#ibcon#about to write, iclass 26, count 0 2006.210.08:07:37.73#ibcon#wrote, iclass 26, count 0 2006.210.08:07:37.73#ibcon#about to read 3, iclass 26, count 0 2006.210.08:07:37.75#ibcon#read 3, iclass 26, count 0 2006.210.08:07:37.75#ibcon#about to read 4, iclass 26, count 0 2006.210.08:07:37.75#ibcon#read 4, iclass 26, count 0 2006.210.08:07:37.75#ibcon#about to read 5, iclass 26, count 0 2006.210.08:07:37.75#ibcon#read 5, iclass 26, count 0 2006.210.08:07:37.75#ibcon#about to read 6, iclass 26, count 0 2006.210.08:07:37.75#ibcon#read 6, iclass 26, count 0 2006.210.08:07:37.75#ibcon#end of sib2, iclass 26, count 0 2006.210.08:07:37.75#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:07:37.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:07:37.75#ibcon#[25=USB\r\n] 2006.210.08:07:37.75#ibcon#*before write, iclass 26, count 0 2006.210.08:07:37.75#ibcon#enter sib2, iclass 26, count 0 2006.210.08:07:37.75#ibcon#flushed, iclass 26, count 0 2006.210.08:07:37.76#ibcon#about to write, iclass 26, count 0 2006.210.08:07:37.76#ibcon#wrote, iclass 26, count 0 2006.210.08:07:37.76#ibcon#about to read 3, iclass 26, count 0 2006.210.08:07:37.78#ibcon#read 3, iclass 26, count 0 2006.210.08:07:37.78#ibcon#about to read 4, iclass 26, count 0 2006.210.08:07:37.78#ibcon#read 4, iclass 26, count 0 2006.210.08:07:37.78#ibcon#about to read 5, iclass 26, count 0 2006.210.08:07:37.78#ibcon#read 5, iclass 26, count 0 2006.210.08:07:37.78#ibcon#about to read 6, iclass 26, count 0 2006.210.08:07:37.78#ibcon#read 6, iclass 26, count 0 2006.210.08:07:37.78#ibcon#end of sib2, iclass 26, count 0 2006.210.08:07:37.78#ibcon#*after write, iclass 26, count 0 2006.210.08:07:37.78#ibcon#*before return 0, iclass 26, count 0 2006.210.08:07:37.78#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:37.78#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:37.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:07:37.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:07:37.79$vc4f8/valo=2,572.99 2006.210.08:07:37.79#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.08:07:37.79#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.08:07:37.79#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:37.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:37.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:37.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:37.79#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:07:37.79#ibcon#first serial, iclass 28, count 0 2006.210.08:07:37.79#ibcon#enter sib2, iclass 28, count 0 2006.210.08:07:37.79#ibcon#flushed, iclass 28, count 0 2006.210.08:07:37.79#ibcon#about to write, iclass 28, count 0 2006.210.08:07:37.79#ibcon#wrote, iclass 28, count 0 2006.210.08:07:37.79#ibcon#about to read 3, iclass 28, count 0 2006.210.08:07:37.80#ibcon#read 3, iclass 28, count 0 2006.210.08:07:37.80#ibcon#about to read 4, iclass 28, count 0 2006.210.08:07:37.80#ibcon#read 4, iclass 28, count 0 2006.210.08:07:37.80#ibcon#about to read 5, iclass 28, count 0 2006.210.08:07:37.80#ibcon#read 5, iclass 28, count 0 2006.210.08:07:37.80#ibcon#about to read 6, iclass 28, count 0 2006.210.08:07:37.80#ibcon#read 6, iclass 28, count 0 2006.210.08:07:37.80#ibcon#end of sib2, iclass 28, count 0 2006.210.08:07:37.80#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:07:37.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:07:37.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:07:37.80#ibcon#*before write, iclass 28, count 0 2006.210.08:07:37.80#ibcon#enter sib2, iclass 28, count 0 2006.210.08:07:37.80#ibcon#flushed, iclass 28, count 0 2006.210.08:07:37.81#ibcon#about to write, iclass 28, count 0 2006.210.08:07:37.81#ibcon#wrote, iclass 28, count 0 2006.210.08:07:37.81#ibcon#about to read 3, iclass 28, count 0 2006.210.08:07:37.84#ibcon#read 3, iclass 28, count 0 2006.210.08:07:37.84#ibcon#about to read 4, iclass 28, count 0 2006.210.08:07:37.84#ibcon#read 4, iclass 28, count 0 2006.210.08:07:37.84#ibcon#about to read 5, iclass 28, count 0 2006.210.08:07:37.84#ibcon#read 5, iclass 28, count 0 2006.210.08:07:37.84#ibcon#about to read 6, iclass 28, count 0 2006.210.08:07:37.84#ibcon#read 6, iclass 28, count 0 2006.210.08:07:37.84#ibcon#end of sib2, iclass 28, count 0 2006.210.08:07:37.84#ibcon#*after write, iclass 28, count 0 2006.210.08:07:37.84#ibcon#*before return 0, iclass 28, count 0 2006.210.08:07:37.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:37.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:37.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:07:37.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:07:37.85$vc4f8/va=2,7 2006.210.08:07:37.85#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.08:07:37.85#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.08:07:37.85#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:37.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:37.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:37.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:37.89#ibcon#enter wrdev, iclass 30, count 2 2006.210.08:07:37.89#ibcon#first serial, iclass 30, count 2 2006.210.08:07:37.89#ibcon#enter sib2, iclass 30, count 2 2006.210.08:07:37.89#ibcon#flushed, iclass 30, count 2 2006.210.08:07:37.89#ibcon#about to write, iclass 30, count 2 2006.210.08:07:37.89#ibcon#wrote, iclass 30, count 2 2006.210.08:07:37.89#ibcon#about to read 3, iclass 30, count 2 2006.210.08:07:37.91#ibcon#read 3, iclass 30, count 2 2006.210.08:07:37.91#ibcon#about to read 4, iclass 30, count 2 2006.210.08:07:37.91#ibcon#read 4, iclass 30, count 2 2006.210.08:07:37.91#ibcon#about to read 5, iclass 30, count 2 2006.210.08:07:37.91#ibcon#read 5, iclass 30, count 2 2006.210.08:07:37.91#ibcon#about to read 6, iclass 30, count 2 2006.210.08:07:37.91#ibcon#read 6, iclass 30, count 2 2006.210.08:07:37.91#ibcon#end of sib2, iclass 30, count 2 2006.210.08:07:37.91#ibcon#*mode == 0, iclass 30, count 2 2006.210.08:07:37.91#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.08:07:37.91#ibcon#[25=AT02-07\r\n] 2006.210.08:07:37.91#ibcon#*before write, iclass 30, count 2 2006.210.08:07:37.91#ibcon#enter sib2, iclass 30, count 2 2006.210.08:07:37.91#ibcon#flushed, iclass 30, count 2 2006.210.08:07:37.91#ibcon#about to write, iclass 30, count 2 2006.210.08:07:37.92#ibcon#wrote, iclass 30, count 2 2006.210.08:07:37.92#ibcon#about to read 3, iclass 30, count 2 2006.210.08:07:37.94#ibcon#read 3, iclass 30, count 2 2006.210.08:07:37.94#ibcon#about to read 4, iclass 30, count 2 2006.210.08:07:37.94#ibcon#read 4, iclass 30, count 2 2006.210.08:07:37.94#ibcon#about to read 5, iclass 30, count 2 2006.210.08:07:37.94#ibcon#read 5, iclass 30, count 2 2006.210.08:07:37.94#ibcon#about to read 6, iclass 30, count 2 2006.210.08:07:37.94#ibcon#read 6, iclass 30, count 2 2006.210.08:07:37.94#ibcon#end of sib2, iclass 30, count 2 2006.210.08:07:37.94#ibcon#*after write, iclass 30, count 2 2006.210.08:07:37.94#ibcon#*before return 0, iclass 30, count 2 2006.210.08:07:37.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:37.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:37.94#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.08:07:37.94#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:37.95#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:38.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:38.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:38.05#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:07:38.05#ibcon#first serial, iclass 30, count 0 2006.210.08:07:38.05#ibcon#enter sib2, iclass 30, count 0 2006.210.08:07:38.05#ibcon#flushed, iclass 30, count 0 2006.210.08:07:38.05#ibcon#about to write, iclass 30, count 0 2006.210.08:07:38.05#ibcon#wrote, iclass 30, count 0 2006.210.08:07:38.05#ibcon#about to read 3, iclass 30, count 0 2006.210.08:07:38.07#ibcon#read 3, iclass 30, count 0 2006.210.08:07:38.07#ibcon#about to read 4, iclass 30, count 0 2006.210.08:07:38.07#ibcon#read 4, iclass 30, count 0 2006.210.08:07:38.07#ibcon#about to read 5, iclass 30, count 0 2006.210.08:07:38.07#ibcon#read 5, iclass 30, count 0 2006.210.08:07:38.07#ibcon#about to read 6, iclass 30, count 0 2006.210.08:07:38.07#ibcon#read 6, iclass 30, count 0 2006.210.08:07:38.07#ibcon#end of sib2, iclass 30, count 0 2006.210.08:07:38.07#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:07:38.07#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:07:38.07#ibcon#[25=USB\r\n] 2006.210.08:07:38.07#ibcon#*before write, iclass 30, count 0 2006.210.08:07:38.07#ibcon#enter sib2, iclass 30, count 0 2006.210.08:07:38.07#ibcon#flushed, iclass 30, count 0 2006.210.08:07:38.07#ibcon#about to write, iclass 30, count 0 2006.210.08:07:38.08#ibcon#wrote, iclass 30, count 0 2006.210.08:07:38.08#ibcon#about to read 3, iclass 30, count 0 2006.210.08:07:38.10#ibcon#read 3, iclass 30, count 0 2006.210.08:07:38.10#ibcon#about to read 4, iclass 30, count 0 2006.210.08:07:38.10#ibcon#read 4, iclass 30, count 0 2006.210.08:07:38.10#ibcon#about to read 5, iclass 30, count 0 2006.210.08:07:38.10#ibcon#read 5, iclass 30, count 0 2006.210.08:07:38.10#ibcon#about to read 6, iclass 30, count 0 2006.210.08:07:38.10#ibcon#read 6, iclass 30, count 0 2006.210.08:07:38.10#ibcon#end of sib2, iclass 30, count 0 2006.210.08:07:38.10#ibcon#*after write, iclass 30, count 0 2006.210.08:07:38.10#ibcon#*before return 0, iclass 30, count 0 2006.210.08:07:38.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:38.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:38.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:07:38.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:07:38.11$vc4f8/valo=3,672.99 2006.210.08:07:38.11#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.08:07:38.11#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.08:07:38.11#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:38.11#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:38.11#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:38.11#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:38.11#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:07:38.11#ibcon#first serial, iclass 32, count 0 2006.210.08:07:38.11#ibcon#enter sib2, iclass 32, count 0 2006.210.08:07:38.11#ibcon#flushed, iclass 32, count 0 2006.210.08:07:38.11#ibcon#about to write, iclass 32, count 0 2006.210.08:07:38.11#ibcon#wrote, iclass 32, count 0 2006.210.08:07:38.11#ibcon#about to read 3, iclass 32, count 0 2006.210.08:07:38.12#ibcon#read 3, iclass 32, count 0 2006.210.08:07:38.12#ibcon#about to read 4, iclass 32, count 0 2006.210.08:07:38.12#ibcon#read 4, iclass 32, count 0 2006.210.08:07:38.12#ibcon#about to read 5, iclass 32, count 0 2006.210.08:07:38.12#ibcon#read 5, iclass 32, count 0 2006.210.08:07:38.12#ibcon#about to read 6, iclass 32, count 0 2006.210.08:07:38.12#ibcon#read 6, iclass 32, count 0 2006.210.08:07:38.12#ibcon#end of sib2, iclass 32, count 0 2006.210.08:07:38.12#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:07:38.12#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:07:38.12#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:07:38.12#ibcon#*before write, iclass 32, count 0 2006.210.08:07:38.12#ibcon#enter sib2, iclass 32, count 0 2006.210.08:07:38.12#ibcon#flushed, iclass 32, count 0 2006.210.08:07:38.13#ibcon#about to write, iclass 32, count 0 2006.210.08:07:38.13#ibcon#wrote, iclass 32, count 0 2006.210.08:07:38.13#ibcon#about to read 3, iclass 32, count 0 2006.210.08:07:38.16#ibcon#read 3, iclass 32, count 0 2006.210.08:07:38.16#ibcon#about to read 4, iclass 32, count 0 2006.210.08:07:38.16#ibcon#read 4, iclass 32, count 0 2006.210.08:07:38.16#ibcon#about to read 5, iclass 32, count 0 2006.210.08:07:38.16#ibcon#read 5, iclass 32, count 0 2006.210.08:07:38.16#ibcon#about to read 6, iclass 32, count 0 2006.210.08:07:38.16#ibcon#read 6, iclass 32, count 0 2006.210.08:07:38.16#ibcon#end of sib2, iclass 32, count 0 2006.210.08:07:38.16#ibcon#*after write, iclass 32, count 0 2006.210.08:07:38.16#ibcon#*before return 0, iclass 32, count 0 2006.210.08:07:38.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:38.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:38.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:07:38.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:07:38.17$vc4f8/va=3,6 2006.210.08:07:38.17#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.08:07:38.17#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.08:07:38.17#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:38.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:38.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:38.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:38.21#ibcon#enter wrdev, iclass 34, count 2 2006.210.08:07:38.21#ibcon#first serial, iclass 34, count 2 2006.210.08:07:38.21#ibcon#enter sib2, iclass 34, count 2 2006.210.08:07:38.21#ibcon#flushed, iclass 34, count 2 2006.210.08:07:38.21#ibcon#about to write, iclass 34, count 2 2006.210.08:07:38.21#ibcon#wrote, iclass 34, count 2 2006.210.08:07:38.21#ibcon#about to read 3, iclass 34, count 2 2006.210.08:07:38.23#ibcon#read 3, iclass 34, count 2 2006.210.08:07:38.23#ibcon#about to read 4, iclass 34, count 2 2006.210.08:07:38.23#ibcon#read 4, iclass 34, count 2 2006.210.08:07:38.23#ibcon#about to read 5, iclass 34, count 2 2006.210.08:07:38.23#ibcon#read 5, iclass 34, count 2 2006.210.08:07:38.23#ibcon#about to read 6, iclass 34, count 2 2006.210.08:07:38.23#ibcon#read 6, iclass 34, count 2 2006.210.08:07:38.23#ibcon#end of sib2, iclass 34, count 2 2006.210.08:07:38.23#ibcon#*mode == 0, iclass 34, count 2 2006.210.08:07:38.23#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.08:07:38.23#ibcon#[25=AT03-06\r\n] 2006.210.08:07:38.23#ibcon#*before write, iclass 34, count 2 2006.210.08:07:38.23#ibcon#enter sib2, iclass 34, count 2 2006.210.08:07:38.23#ibcon#flushed, iclass 34, count 2 2006.210.08:07:38.23#ibcon#about to write, iclass 34, count 2 2006.210.08:07:38.24#ibcon#wrote, iclass 34, count 2 2006.210.08:07:38.24#ibcon#about to read 3, iclass 34, count 2 2006.210.08:07:38.26#ibcon#read 3, iclass 34, count 2 2006.210.08:07:38.26#ibcon#about to read 4, iclass 34, count 2 2006.210.08:07:38.26#ibcon#read 4, iclass 34, count 2 2006.210.08:07:38.26#ibcon#about to read 5, iclass 34, count 2 2006.210.08:07:38.26#ibcon#read 5, iclass 34, count 2 2006.210.08:07:38.26#ibcon#about to read 6, iclass 34, count 2 2006.210.08:07:38.26#ibcon#read 6, iclass 34, count 2 2006.210.08:07:38.26#ibcon#end of sib2, iclass 34, count 2 2006.210.08:07:38.26#ibcon#*after write, iclass 34, count 2 2006.210.08:07:38.26#ibcon#*before return 0, iclass 34, count 2 2006.210.08:07:38.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:38.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:38.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.08:07:38.26#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:38.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:38.37#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:38.37#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:38.37#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:07:38.37#ibcon#first serial, iclass 34, count 0 2006.210.08:07:38.37#ibcon#enter sib2, iclass 34, count 0 2006.210.08:07:38.37#ibcon#flushed, iclass 34, count 0 2006.210.08:07:38.37#ibcon#about to write, iclass 34, count 0 2006.210.08:07:38.37#ibcon#wrote, iclass 34, count 0 2006.210.08:07:38.37#ibcon#about to read 3, iclass 34, count 0 2006.210.08:07:38.39#ibcon#read 3, iclass 34, count 0 2006.210.08:07:38.39#ibcon#about to read 4, iclass 34, count 0 2006.210.08:07:38.39#ibcon#read 4, iclass 34, count 0 2006.210.08:07:38.39#ibcon#about to read 5, iclass 34, count 0 2006.210.08:07:38.39#ibcon#read 5, iclass 34, count 0 2006.210.08:07:38.39#ibcon#about to read 6, iclass 34, count 0 2006.210.08:07:38.39#ibcon#read 6, iclass 34, count 0 2006.210.08:07:38.39#ibcon#end of sib2, iclass 34, count 0 2006.210.08:07:38.39#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:07:38.39#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:07:38.39#ibcon#[25=USB\r\n] 2006.210.08:07:38.39#ibcon#*before write, iclass 34, count 0 2006.210.08:07:38.39#ibcon#enter sib2, iclass 34, count 0 2006.210.08:07:38.39#ibcon#flushed, iclass 34, count 0 2006.210.08:07:38.39#ibcon#about to write, iclass 34, count 0 2006.210.08:07:38.40#ibcon#wrote, iclass 34, count 0 2006.210.08:07:38.40#ibcon#about to read 3, iclass 34, count 0 2006.210.08:07:38.42#ibcon#read 3, iclass 34, count 0 2006.210.08:07:38.42#ibcon#about to read 4, iclass 34, count 0 2006.210.08:07:38.42#ibcon#read 4, iclass 34, count 0 2006.210.08:07:38.42#ibcon#about to read 5, iclass 34, count 0 2006.210.08:07:38.42#ibcon#read 5, iclass 34, count 0 2006.210.08:07:38.42#ibcon#about to read 6, iclass 34, count 0 2006.210.08:07:38.42#ibcon#read 6, iclass 34, count 0 2006.210.08:07:38.42#ibcon#end of sib2, iclass 34, count 0 2006.210.08:07:38.42#ibcon#*after write, iclass 34, count 0 2006.210.08:07:38.42#ibcon#*before return 0, iclass 34, count 0 2006.210.08:07:38.42#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:38.42#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:38.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:07:38.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:07:38.43$vc4f8/valo=4,832.99 2006.210.08:07:38.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.08:07:38.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.08:07:38.43#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:38.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:38.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:38.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:38.43#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:07:38.43#ibcon#first serial, iclass 36, count 0 2006.210.08:07:38.43#ibcon#enter sib2, iclass 36, count 0 2006.210.08:07:38.43#ibcon#flushed, iclass 36, count 0 2006.210.08:07:38.43#ibcon#about to write, iclass 36, count 0 2006.210.08:07:38.43#ibcon#wrote, iclass 36, count 0 2006.210.08:07:38.43#ibcon#about to read 3, iclass 36, count 0 2006.210.08:07:38.44#ibcon#read 3, iclass 36, count 0 2006.210.08:07:38.44#ibcon#about to read 4, iclass 36, count 0 2006.210.08:07:38.44#ibcon#read 4, iclass 36, count 0 2006.210.08:07:38.44#ibcon#about to read 5, iclass 36, count 0 2006.210.08:07:38.44#ibcon#read 5, iclass 36, count 0 2006.210.08:07:38.44#ibcon#about to read 6, iclass 36, count 0 2006.210.08:07:38.44#ibcon#read 6, iclass 36, count 0 2006.210.08:07:38.44#ibcon#end of sib2, iclass 36, count 0 2006.210.08:07:38.44#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:07:38.44#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:07:38.44#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:07:38.44#ibcon#*before write, iclass 36, count 0 2006.210.08:07:38.44#ibcon#enter sib2, iclass 36, count 0 2006.210.08:07:38.44#ibcon#flushed, iclass 36, count 0 2006.210.08:07:38.45#ibcon#about to write, iclass 36, count 0 2006.210.08:07:38.45#ibcon#wrote, iclass 36, count 0 2006.210.08:07:38.45#ibcon#about to read 3, iclass 36, count 0 2006.210.08:07:38.48#ibcon#read 3, iclass 36, count 0 2006.210.08:07:38.48#ibcon#about to read 4, iclass 36, count 0 2006.210.08:07:38.48#ibcon#read 4, iclass 36, count 0 2006.210.08:07:38.48#ibcon#about to read 5, iclass 36, count 0 2006.210.08:07:38.48#ibcon#read 5, iclass 36, count 0 2006.210.08:07:38.48#ibcon#about to read 6, iclass 36, count 0 2006.210.08:07:38.48#ibcon#read 6, iclass 36, count 0 2006.210.08:07:38.48#ibcon#end of sib2, iclass 36, count 0 2006.210.08:07:38.48#ibcon#*after write, iclass 36, count 0 2006.210.08:07:38.48#ibcon#*before return 0, iclass 36, count 0 2006.210.08:07:38.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:38.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:38.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:07:38.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:07:38.49$vc4f8/va=4,7 2006.210.08:07:38.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.08:07:38.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.08:07:38.49#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:38.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:38.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:38.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:38.53#ibcon#enter wrdev, iclass 38, count 2 2006.210.08:07:38.53#ibcon#first serial, iclass 38, count 2 2006.210.08:07:38.53#ibcon#enter sib2, iclass 38, count 2 2006.210.08:07:38.53#ibcon#flushed, iclass 38, count 2 2006.210.08:07:38.53#ibcon#about to write, iclass 38, count 2 2006.210.08:07:38.53#ibcon#wrote, iclass 38, count 2 2006.210.08:07:38.53#ibcon#about to read 3, iclass 38, count 2 2006.210.08:07:38.55#ibcon#read 3, iclass 38, count 2 2006.210.08:07:38.55#ibcon#about to read 4, iclass 38, count 2 2006.210.08:07:38.55#ibcon#read 4, iclass 38, count 2 2006.210.08:07:38.55#ibcon#about to read 5, iclass 38, count 2 2006.210.08:07:38.55#ibcon#read 5, iclass 38, count 2 2006.210.08:07:38.55#ibcon#about to read 6, iclass 38, count 2 2006.210.08:07:38.55#ibcon#read 6, iclass 38, count 2 2006.210.08:07:38.55#ibcon#end of sib2, iclass 38, count 2 2006.210.08:07:38.55#ibcon#*mode == 0, iclass 38, count 2 2006.210.08:07:38.55#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.08:07:38.55#ibcon#[25=AT04-07\r\n] 2006.210.08:07:38.55#ibcon#*before write, iclass 38, count 2 2006.210.08:07:38.55#ibcon#enter sib2, iclass 38, count 2 2006.210.08:07:38.55#ibcon#flushed, iclass 38, count 2 2006.210.08:07:38.55#ibcon#about to write, iclass 38, count 2 2006.210.08:07:38.56#ibcon#wrote, iclass 38, count 2 2006.210.08:07:38.56#ibcon#about to read 3, iclass 38, count 2 2006.210.08:07:38.58#ibcon#read 3, iclass 38, count 2 2006.210.08:07:38.58#ibcon#about to read 4, iclass 38, count 2 2006.210.08:07:38.58#ibcon#read 4, iclass 38, count 2 2006.210.08:07:38.58#ibcon#about to read 5, iclass 38, count 2 2006.210.08:07:38.58#ibcon#read 5, iclass 38, count 2 2006.210.08:07:38.58#ibcon#about to read 6, iclass 38, count 2 2006.210.08:07:38.58#ibcon#read 6, iclass 38, count 2 2006.210.08:07:38.58#ibcon#end of sib2, iclass 38, count 2 2006.210.08:07:38.58#ibcon#*after write, iclass 38, count 2 2006.210.08:07:38.58#ibcon#*before return 0, iclass 38, count 2 2006.210.08:07:38.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:38.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:38.58#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.08:07:38.58#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:38.59#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:38.70#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:38.70#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:38.70#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:07:38.70#ibcon#first serial, iclass 38, count 0 2006.210.08:07:38.70#ibcon#enter sib2, iclass 38, count 0 2006.210.08:07:38.70#ibcon#flushed, iclass 38, count 0 2006.210.08:07:38.70#ibcon#about to write, iclass 38, count 0 2006.210.08:07:38.70#ibcon#wrote, iclass 38, count 0 2006.210.08:07:38.70#ibcon#about to read 3, iclass 38, count 0 2006.210.08:07:38.72#ibcon#read 3, iclass 38, count 0 2006.210.08:07:38.72#ibcon#about to read 4, iclass 38, count 0 2006.210.08:07:38.72#ibcon#read 4, iclass 38, count 0 2006.210.08:07:38.72#ibcon#about to read 5, iclass 38, count 0 2006.210.08:07:38.72#ibcon#read 5, iclass 38, count 0 2006.210.08:07:38.72#ibcon#about to read 6, iclass 38, count 0 2006.210.08:07:38.72#ibcon#read 6, iclass 38, count 0 2006.210.08:07:38.72#ibcon#end of sib2, iclass 38, count 0 2006.210.08:07:38.72#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:07:38.72#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:07:38.72#ibcon#[25=USB\r\n] 2006.210.08:07:38.72#ibcon#*before write, iclass 38, count 0 2006.210.08:07:38.72#ibcon#enter sib2, iclass 38, count 0 2006.210.08:07:38.72#ibcon#flushed, iclass 38, count 0 2006.210.08:07:38.72#ibcon#about to write, iclass 38, count 0 2006.210.08:07:38.73#ibcon#wrote, iclass 38, count 0 2006.210.08:07:38.73#ibcon#about to read 3, iclass 38, count 0 2006.210.08:07:38.75#ibcon#read 3, iclass 38, count 0 2006.210.08:07:38.75#ibcon#about to read 4, iclass 38, count 0 2006.210.08:07:38.75#ibcon#read 4, iclass 38, count 0 2006.210.08:07:38.75#ibcon#about to read 5, iclass 38, count 0 2006.210.08:07:38.75#ibcon#read 5, iclass 38, count 0 2006.210.08:07:38.75#ibcon#about to read 6, iclass 38, count 0 2006.210.08:07:38.75#ibcon#read 6, iclass 38, count 0 2006.210.08:07:38.75#ibcon#end of sib2, iclass 38, count 0 2006.210.08:07:38.75#ibcon#*after write, iclass 38, count 0 2006.210.08:07:38.75#ibcon#*before return 0, iclass 38, count 0 2006.210.08:07:38.75#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:38.75#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:38.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:07:38.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:07:38.76$vc4f8/valo=5,652.99 2006.210.08:07:38.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.08:07:38.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.08:07:38.76#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:38.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:38.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:38.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:38.76#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:07:38.76#ibcon#first serial, iclass 40, count 0 2006.210.08:07:38.76#ibcon#enter sib2, iclass 40, count 0 2006.210.08:07:38.76#ibcon#flushed, iclass 40, count 0 2006.210.08:07:38.76#ibcon#about to write, iclass 40, count 0 2006.210.08:07:38.76#ibcon#wrote, iclass 40, count 0 2006.210.08:07:38.76#ibcon#about to read 3, iclass 40, count 0 2006.210.08:07:38.77#ibcon#read 3, iclass 40, count 0 2006.210.08:07:38.77#ibcon#about to read 4, iclass 40, count 0 2006.210.08:07:38.77#ibcon#read 4, iclass 40, count 0 2006.210.08:07:38.77#ibcon#about to read 5, iclass 40, count 0 2006.210.08:07:38.77#ibcon#read 5, iclass 40, count 0 2006.210.08:07:38.77#ibcon#about to read 6, iclass 40, count 0 2006.210.08:07:38.77#ibcon#read 6, iclass 40, count 0 2006.210.08:07:38.77#ibcon#end of sib2, iclass 40, count 0 2006.210.08:07:38.77#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:07:38.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:07:38.77#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:07:38.77#ibcon#*before write, iclass 40, count 0 2006.210.08:07:38.77#ibcon#enter sib2, iclass 40, count 0 2006.210.08:07:38.77#ibcon#flushed, iclass 40, count 0 2006.210.08:07:38.78#ibcon#about to write, iclass 40, count 0 2006.210.08:07:38.78#ibcon#wrote, iclass 40, count 0 2006.210.08:07:38.78#ibcon#about to read 3, iclass 40, count 0 2006.210.08:07:38.81#ibcon#read 3, iclass 40, count 0 2006.210.08:07:38.81#ibcon#about to read 4, iclass 40, count 0 2006.210.08:07:38.81#ibcon#read 4, iclass 40, count 0 2006.210.08:07:38.81#ibcon#about to read 5, iclass 40, count 0 2006.210.08:07:38.81#ibcon#read 5, iclass 40, count 0 2006.210.08:07:38.81#ibcon#about to read 6, iclass 40, count 0 2006.210.08:07:38.81#ibcon#read 6, iclass 40, count 0 2006.210.08:07:38.81#ibcon#end of sib2, iclass 40, count 0 2006.210.08:07:38.81#ibcon#*after write, iclass 40, count 0 2006.210.08:07:38.81#ibcon#*before return 0, iclass 40, count 0 2006.210.08:07:38.81#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:38.81#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:38.81#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:07:38.81#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:07:38.82$vc4f8/va=5,7 2006.210.08:07:38.82#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.08:07:38.82#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.08:07:38.82#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:38.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:38.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:38.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:38.86#ibcon#enter wrdev, iclass 4, count 2 2006.210.08:07:38.86#ibcon#first serial, iclass 4, count 2 2006.210.08:07:38.86#ibcon#enter sib2, iclass 4, count 2 2006.210.08:07:38.86#ibcon#flushed, iclass 4, count 2 2006.210.08:07:38.86#ibcon#about to write, iclass 4, count 2 2006.210.08:07:38.86#ibcon#wrote, iclass 4, count 2 2006.210.08:07:38.86#ibcon#about to read 3, iclass 4, count 2 2006.210.08:07:38.88#ibcon#read 3, iclass 4, count 2 2006.210.08:07:38.88#ibcon#about to read 4, iclass 4, count 2 2006.210.08:07:38.88#ibcon#read 4, iclass 4, count 2 2006.210.08:07:38.88#ibcon#about to read 5, iclass 4, count 2 2006.210.08:07:38.88#ibcon#read 5, iclass 4, count 2 2006.210.08:07:38.88#ibcon#about to read 6, iclass 4, count 2 2006.210.08:07:38.88#ibcon#read 6, iclass 4, count 2 2006.210.08:07:38.88#ibcon#end of sib2, iclass 4, count 2 2006.210.08:07:38.88#ibcon#*mode == 0, iclass 4, count 2 2006.210.08:07:38.88#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.08:07:38.88#ibcon#[25=AT05-07\r\n] 2006.210.08:07:38.88#ibcon#*before write, iclass 4, count 2 2006.210.08:07:38.88#ibcon#enter sib2, iclass 4, count 2 2006.210.08:07:38.88#ibcon#flushed, iclass 4, count 2 2006.210.08:07:38.88#ibcon#about to write, iclass 4, count 2 2006.210.08:07:38.89#ibcon#wrote, iclass 4, count 2 2006.210.08:07:38.89#ibcon#about to read 3, iclass 4, count 2 2006.210.08:07:38.91#ibcon#read 3, iclass 4, count 2 2006.210.08:07:38.91#ibcon#about to read 4, iclass 4, count 2 2006.210.08:07:38.91#ibcon#read 4, iclass 4, count 2 2006.210.08:07:38.91#ibcon#about to read 5, iclass 4, count 2 2006.210.08:07:38.91#ibcon#read 5, iclass 4, count 2 2006.210.08:07:38.91#ibcon#about to read 6, iclass 4, count 2 2006.210.08:07:38.91#ibcon#read 6, iclass 4, count 2 2006.210.08:07:38.91#ibcon#end of sib2, iclass 4, count 2 2006.210.08:07:38.91#ibcon#*after write, iclass 4, count 2 2006.210.08:07:38.91#ibcon#*before return 0, iclass 4, count 2 2006.210.08:07:38.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:38.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:38.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.08:07:38.91#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:38.92#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:39.02#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:39.02#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:39.02#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:07:39.02#ibcon#first serial, iclass 4, count 0 2006.210.08:07:39.02#ibcon#enter sib2, iclass 4, count 0 2006.210.08:07:39.02#ibcon#flushed, iclass 4, count 0 2006.210.08:07:39.02#ibcon#about to write, iclass 4, count 0 2006.210.08:07:39.02#ibcon#wrote, iclass 4, count 0 2006.210.08:07:39.02#ibcon#about to read 3, iclass 4, count 0 2006.210.08:07:39.04#ibcon#read 3, iclass 4, count 0 2006.210.08:07:39.04#ibcon#about to read 4, iclass 4, count 0 2006.210.08:07:39.04#ibcon#read 4, iclass 4, count 0 2006.210.08:07:39.04#ibcon#about to read 5, iclass 4, count 0 2006.210.08:07:39.04#ibcon#read 5, iclass 4, count 0 2006.210.08:07:39.04#ibcon#about to read 6, iclass 4, count 0 2006.210.08:07:39.04#ibcon#read 6, iclass 4, count 0 2006.210.08:07:39.04#ibcon#end of sib2, iclass 4, count 0 2006.210.08:07:39.04#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:07:39.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:07:39.04#ibcon#[25=USB\r\n] 2006.210.08:07:39.04#ibcon#*before write, iclass 4, count 0 2006.210.08:07:39.04#ibcon#enter sib2, iclass 4, count 0 2006.210.08:07:39.04#ibcon#flushed, iclass 4, count 0 2006.210.08:07:39.04#ibcon#about to write, iclass 4, count 0 2006.210.08:07:39.05#ibcon#wrote, iclass 4, count 0 2006.210.08:07:39.05#ibcon#about to read 3, iclass 4, count 0 2006.210.08:07:39.07#ibcon#read 3, iclass 4, count 0 2006.210.08:07:39.07#ibcon#about to read 4, iclass 4, count 0 2006.210.08:07:39.07#ibcon#read 4, iclass 4, count 0 2006.210.08:07:39.07#ibcon#about to read 5, iclass 4, count 0 2006.210.08:07:39.07#ibcon#read 5, iclass 4, count 0 2006.210.08:07:39.07#ibcon#about to read 6, iclass 4, count 0 2006.210.08:07:39.07#ibcon#read 6, iclass 4, count 0 2006.210.08:07:39.07#ibcon#end of sib2, iclass 4, count 0 2006.210.08:07:39.07#ibcon#*after write, iclass 4, count 0 2006.210.08:07:39.07#ibcon#*before return 0, iclass 4, count 0 2006.210.08:07:39.07#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:39.07#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:39.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:07:39.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:07:39.08$vc4f8/valo=6,772.99 2006.210.08:07:39.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.08:07:39.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.08:07:39.08#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:39.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:39.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:39.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:39.08#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:07:39.08#ibcon#first serial, iclass 6, count 0 2006.210.08:07:39.08#ibcon#enter sib2, iclass 6, count 0 2006.210.08:07:39.08#ibcon#flushed, iclass 6, count 0 2006.210.08:07:39.08#ibcon#about to write, iclass 6, count 0 2006.210.08:07:39.08#ibcon#wrote, iclass 6, count 0 2006.210.08:07:39.08#ibcon#about to read 3, iclass 6, count 0 2006.210.08:07:39.09#ibcon#read 3, iclass 6, count 0 2006.210.08:07:39.09#ibcon#about to read 4, iclass 6, count 0 2006.210.08:07:39.09#ibcon#read 4, iclass 6, count 0 2006.210.08:07:39.09#ibcon#about to read 5, iclass 6, count 0 2006.210.08:07:39.09#ibcon#read 5, iclass 6, count 0 2006.210.08:07:39.09#ibcon#about to read 6, iclass 6, count 0 2006.210.08:07:39.09#ibcon#read 6, iclass 6, count 0 2006.210.08:07:39.09#ibcon#end of sib2, iclass 6, count 0 2006.210.08:07:39.09#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:07:39.09#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:07:39.09#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:07:39.09#ibcon#*before write, iclass 6, count 0 2006.210.08:07:39.09#ibcon#enter sib2, iclass 6, count 0 2006.210.08:07:39.09#ibcon#flushed, iclass 6, count 0 2006.210.08:07:39.10#ibcon#about to write, iclass 6, count 0 2006.210.08:07:39.10#ibcon#wrote, iclass 6, count 0 2006.210.08:07:39.10#ibcon#about to read 3, iclass 6, count 0 2006.210.08:07:39.13#ibcon#read 3, iclass 6, count 0 2006.210.08:07:39.13#ibcon#about to read 4, iclass 6, count 0 2006.210.08:07:39.13#ibcon#read 4, iclass 6, count 0 2006.210.08:07:39.13#ibcon#about to read 5, iclass 6, count 0 2006.210.08:07:39.13#ibcon#read 5, iclass 6, count 0 2006.210.08:07:39.13#ibcon#about to read 6, iclass 6, count 0 2006.210.08:07:39.13#ibcon#read 6, iclass 6, count 0 2006.210.08:07:39.13#ibcon#end of sib2, iclass 6, count 0 2006.210.08:07:39.13#ibcon#*after write, iclass 6, count 0 2006.210.08:07:39.13#ibcon#*before return 0, iclass 6, count 0 2006.210.08:07:39.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:39.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:39.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:07:39.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:07:39.14$vc4f8/va=6,6 2006.210.08:07:39.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.08:07:39.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.08:07:39.14#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:39.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:07:39.18#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:07:39.18#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:07:39.18#ibcon#enter wrdev, iclass 10, count 2 2006.210.08:07:39.18#ibcon#first serial, iclass 10, count 2 2006.210.08:07:39.18#ibcon#enter sib2, iclass 10, count 2 2006.210.08:07:39.18#ibcon#flushed, iclass 10, count 2 2006.210.08:07:39.18#ibcon#about to write, iclass 10, count 2 2006.210.08:07:39.18#ibcon#wrote, iclass 10, count 2 2006.210.08:07:39.18#ibcon#about to read 3, iclass 10, count 2 2006.210.08:07:39.20#ibcon#read 3, iclass 10, count 2 2006.210.08:07:39.20#ibcon#about to read 4, iclass 10, count 2 2006.210.08:07:39.20#ibcon#read 4, iclass 10, count 2 2006.210.08:07:39.20#ibcon#about to read 5, iclass 10, count 2 2006.210.08:07:39.20#ibcon#read 5, iclass 10, count 2 2006.210.08:07:39.20#ibcon#about to read 6, iclass 10, count 2 2006.210.08:07:39.20#ibcon#read 6, iclass 10, count 2 2006.210.08:07:39.20#ibcon#end of sib2, iclass 10, count 2 2006.210.08:07:39.20#ibcon#*mode == 0, iclass 10, count 2 2006.210.08:07:39.20#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.08:07:39.20#ibcon#[25=AT06-06\r\n] 2006.210.08:07:39.20#ibcon#*before write, iclass 10, count 2 2006.210.08:07:39.20#ibcon#enter sib2, iclass 10, count 2 2006.210.08:07:39.20#ibcon#flushed, iclass 10, count 2 2006.210.08:07:39.20#ibcon#about to write, iclass 10, count 2 2006.210.08:07:39.21#ibcon#wrote, iclass 10, count 2 2006.210.08:07:39.21#ibcon#about to read 3, iclass 10, count 2 2006.210.08:07:39.23#ibcon#read 3, iclass 10, count 2 2006.210.08:07:39.23#ibcon#about to read 4, iclass 10, count 2 2006.210.08:07:39.23#ibcon#read 4, iclass 10, count 2 2006.210.08:07:39.23#ibcon#about to read 5, iclass 10, count 2 2006.210.08:07:39.23#ibcon#read 5, iclass 10, count 2 2006.210.08:07:39.23#ibcon#about to read 6, iclass 10, count 2 2006.210.08:07:39.23#ibcon#read 6, iclass 10, count 2 2006.210.08:07:39.23#ibcon#end of sib2, iclass 10, count 2 2006.210.08:07:39.23#ibcon#*after write, iclass 10, count 2 2006.210.08:07:39.23#ibcon#*before return 0, iclass 10, count 2 2006.210.08:07:39.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:07:39.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:07:39.23#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.08:07:39.23#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:39.24#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:07:39.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:07:39.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:07:39.34#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:07:39.34#ibcon#first serial, iclass 10, count 0 2006.210.08:07:39.34#ibcon#enter sib2, iclass 10, count 0 2006.210.08:07:39.34#ibcon#flushed, iclass 10, count 0 2006.210.08:07:39.34#ibcon#about to write, iclass 10, count 0 2006.210.08:07:39.34#ibcon#wrote, iclass 10, count 0 2006.210.08:07:39.34#ibcon#about to read 3, iclass 10, count 0 2006.210.08:07:39.36#ibcon#read 3, iclass 10, count 0 2006.210.08:07:39.36#ibcon#about to read 4, iclass 10, count 0 2006.210.08:07:39.36#ibcon#read 4, iclass 10, count 0 2006.210.08:07:39.36#ibcon#about to read 5, iclass 10, count 0 2006.210.08:07:39.36#ibcon#read 5, iclass 10, count 0 2006.210.08:07:39.36#ibcon#about to read 6, iclass 10, count 0 2006.210.08:07:39.36#ibcon#read 6, iclass 10, count 0 2006.210.08:07:39.36#ibcon#end of sib2, iclass 10, count 0 2006.210.08:07:39.36#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:07:39.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:07:39.36#ibcon#[25=USB\r\n] 2006.210.08:07:39.36#ibcon#*before write, iclass 10, count 0 2006.210.08:07:39.36#ibcon#enter sib2, iclass 10, count 0 2006.210.08:07:39.36#ibcon#flushed, iclass 10, count 0 2006.210.08:07:39.36#ibcon#about to write, iclass 10, count 0 2006.210.08:07:39.37#ibcon#wrote, iclass 10, count 0 2006.210.08:07:39.37#ibcon#about to read 3, iclass 10, count 0 2006.210.08:07:39.39#ibcon#read 3, iclass 10, count 0 2006.210.08:07:39.39#ibcon#about to read 4, iclass 10, count 0 2006.210.08:07:39.39#ibcon#read 4, iclass 10, count 0 2006.210.08:07:39.39#ibcon#about to read 5, iclass 10, count 0 2006.210.08:07:39.39#ibcon#read 5, iclass 10, count 0 2006.210.08:07:39.39#ibcon#about to read 6, iclass 10, count 0 2006.210.08:07:39.39#ibcon#read 6, iclass 10, count 0 2006.210.08:07:39.39#ibcon#end of sib2, iclass 10, count 0 2006.210.08:07:39.39#ibcon#*after write, iclass 10, count 0 2006.210.08:07:39.39#ibcon#*before return 0, iclass 10, count 0 2006.210.08:07:39.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:07:39.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:07:39.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:07:39.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:07:39.40$vc4f8/valo=7,832.99 2006.210.08:07:39.40#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.08:07:39.40#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.08:07:39.40#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:39.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:07:39.40#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:07:39.40#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:07:39.40#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:07:39.40#ibcon#first serial, iclass 12, count 0 2006.210.08:07:39.40#ibcon#enter sib2, iclass 12, count 0 2006.210.08:07:39.40#ibcon#flushed, iclass 12, count 0 2006.210.08:07:39.40#ibcon#about to write, iclass 12, count 0 2006.210.08:07:39.40#ibcon#wrote, iclass 12, count 0 2006.210.08:07:39.40#ibcon#about to read 3, iclass 12, count 0 2006.210.08:07:39.41#ibcon#read 3, iclass 12, count 0 2006.210.08:07:39.41#ibcon#about to read 4, iclass 12, count 0 2006.210.08:07:39.41#ibcon#read 4, iclass 12, count 0 2006.210.08:07:39.41#ibcon#about to read 5, iclass 12, count 0 2006.210.08:07:39.41#ibcon#read 5, iclass 12, count 0 2006.210.08:07:39.41#ibcon#about to read 6, iclass 12, count 0 2006.210.08:07:39.41#ibcon#read 6, iclass 12, count 0 2006.210.08:07:39.41#ibcon#end of sib2, iclass 12, count 0 2006.210.08:07:39.41#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:07:39.41#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:07:39.41#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:07:39.41#ibcon#*before write, iclass 12, count 0 2006.210.08:07:39.41#ibcon#enter sib2, iclass 12, count 0 2006.210.08:07:39.41#ibcon#flushed, iclass 12, count 0 2006.210.08:07:39.41#ibcon#about to write, iclass 12, count 0 2006.210.08:07:39.42#ibcon#wrote, iclass 12, count 0 2006.210.08:07:39.42#ibcon#about to read 3, iclass 12, count 0 2006.210.08:07:39.45#ibcon#read 3, iclass 12, count 0 2006.210.08:07:39.45#ibcon#about to read 4, iclass 12, count 0 2006.210.08:07:39.45#ibcon#read 4, iclass 12, count 0 2006.210.08:07:39.45#ibcon#about to read 5, iclass 12, count 0 2006.210.08:07:39.45#ibcon#read 5, iclass 12, count 0 2006.210.08:07:39.45#ibcon#about to read 6, iclass 12, count 0 2006.210.08:07:39.45#ibcon#read 6, iclass 12, count 0 2006.210.08:07:39.45#ibcon#end of sib2, iclass 12, count 0 2006.210.08:07:39.45#ibcon#*after write, iclass 12, count 0 2006.210.08:07:39.45#ibcon#*before return 0, iclass 12, count 0 2006.210.08:07:39.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:07:39.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:07:39.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:07:39.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:07:39.46$vc4f8/va=7,6 2006.210.08:07:39.46#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.08:07:39.46#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.08:07:39.46#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:39.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:07:39.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:07:39.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:07:39.50#ibcon#enter wrdev, iclass 14, count 2 2006.210.08:07:39.50#ibcon#first serial, iclass 14, count 2 2006.210.08:07:39.50#ibcon#enter sib2, iclass 14, count 2 2006.210.08:07:39.50#ibcon#flushed, iclass 14, count 2 2006.210.08:07:39.50#ibcon#about to write, iclass 14, count 2 2006.210.08:07:39.50#ibcon#wrote, iclass 14, count 2 2006.210.08:07:39.50#ibcon#about to read 3, iclass 14, count 2 2006.210.08:07:39.52#ibcon#read 3, iclass 14, count 2 2006.210.08:07:39.52#ibcon#about to read 4, iclass 14, count 2 2006.210.08:07:39.52#ibcon#read 4, iclass 14, count 2 2006.210.08:07:39.52#ibcon#about to read 5, iclass 14, count 2 2006.210.08:07:39.52#ibcon#read 5, iclass 14, count 2 2006.210.08:07:39.52#ibcon#about to read 6, iclass 14, count 2 2006.210.08:07:39.52#ibcon#read 6, iclass 14, count 2 2006.210.08:07:39.52#ibcon#end of sib2, iclass 14, count 2 2006.210.08:07:39.52#ibcon#*mode == 0, iclass 14, count 2 2006.210.08:07:39.52#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.08:07:39.52#ibcon#[25=AT07-06\r\n] 2006.210.08:07:39.52#ibcon#*before write, iclass 14, count 2 2006.210.08:07:39.52#ibcon#enter sib2, iclass 14, count 2 2006.210.08:07:39.52#ibcon#flushed, iclass 14, count 2 2006.210.08:07:39.52#ibcon#about to write, iclass 14, count 2 2006.210.08:07:39.53#ibcon#wrote, iclass 14, count 2 2006.210.08:07:39.53#ibcon#about to read 3, iclass 14, count 2 2006.210.08:07:39.55#ibcon#read 3, iclass 14, count 2 2006.210.08:07:39.55#ibcon#about to read 4, iclass 14, count 2 2006.210.08:07:39.55#ibcon#read 4, iclass 14, count 2 2006.210.08:07:39.55#ibcon#about to read 5, iclass 14, count 2 2006.210.08:07:39.55#ibcon#read 5, iclass 14, count 2 2006.210.08:07:39.55#ibcon#about to read 6, iclass 14, count 2 2006.210.08:07:39.55#ibcon#read 6, iclass 14, count 2 2006.210.08:07:39.55#ibcon#end of sib2, iclass 14, count 2 2006.210.08:07:39.55#ibcon#*after write, iclass 14, count 2 2006.210.08:07:39.55#ibcon#*before return 0, iclass 14, count 2 2006.210.08:07:39.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:07:39.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:07:39.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.08:07:39.55#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:39.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:07:39.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:07:39.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:07:39.66#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:07:39.66#ibcon#first serial, iclass 14, count 0 2006.210.08:07:39.66#ibcon#enter sib2, iclass 14, count 0 2006.210.08:07:39.66#ibcon#flushed, iclass 14, count 0 2006.210.08:07:39.66#ibcon#about to write, iclass 14, count 0 2006.210.08:07:39.66#ibcon#wrote, iclass 14, count 0 2006.210.08:07:39.66#ibcon#about to read 3, iclass 14, count 0 2006.210.08:07:39.68#ibcon#read 3, iclass 14, count 0 2006.210.08:07:39.68#ibcon#about to read 4, iclass 14, count 0 2006.210.08:07:39.68#ibcon#read 4, iclass 14, count 0 2006.210.08:07:39.68#ibcon#about to read 5, iclass 14, count 0 2006.210.08:07:39.68#ibcon#read 5, iclass 14, count 0 2006.210.08:07:39.68#ibcon#about to read 6, iclass 14, count 0 2006.210.08:07:39.68#ibcon#read 6, iclass 14, count 0 2006.210.08:07:39.68#ibcon#end of sib2, iclass 14, count 0 2006.210.08:07:39.68#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:07:39.68#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:07:39.68#ibcon#[25=USB\r\n] 2006.210.08:07:39.68#ibcon#*before write, iclass 14, count 0 2006.210.08:07:39.68#ibcon#enter sib2, iclass 14, count 0 2006.210.08:07:39.68#ibcon#flushed, iclass 14, count 0 2006.210.08:07:39.68#ibcon#about to write, iclass 14, count 0 2006.210.08:07:39.69#ibcon#wrote, iclass 14, count 0 2006.210.08:07:39.69#ibcon#about to read 3, iclass 14, count 0 2006.210.08:07:39.71#ibcon#read 3, iclass 14, count 0 2006.210.08:07:39.71#ibcon#about to read 4, iclass 14, count 0 2006.210.08:07:39.71#ibcon#read 4, iclass 14, count 0 2006.210.08:07:39.71#ibcon#about to read 5, iclass 14, count 0 2006.210.08:07:39.71#ibcon#read 5, iclass 14, count 0 2006.210.08:07:39.71#ibcon#about to read 6, iclass 14, count 0 2006.210.08:07:39.71#ibcon#read 6, iclass 14, count 0 2006.210.08:07:39.71#ibcon#end of sib2, iclass 14, count 0 2006.210.08:07:39.71#ibcon#*after write, iclass 14, count 0 2006.210.08:07:39.71#ibcon#*before return 0, iclass 14, count 0 2006.210.08:07:39.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:07:39.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:07:39.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:07:39.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:07:39.72$vc4f8/valo=8,852.99 2006.210.08:07:39.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.08:07:39.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.08:07:39.72#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:39.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:07:39.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:07:39.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:07:39.72#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:07:39.72#ibcon#first serial, iclass 16, count 0 2006.210.08:07:39.72#ibcon#enter sib2, iclass 16, count 0 2006.210.08:07:39.72#ibcon#flushed, iclass 16, count 0 2006.210.08:07:39.72#ibcon#about to write, iclass 16, count 0 2006.210.08:07:39.72#ibcon#wrote, iclass 16, count 0 2006.210.08:07:39.72#ibcon#about to read 3, iclass 16, count 0 2006.210.08:07:39.73#ibcon#read 3, iclass 16, count 0 2006.210.08:07:39.73#ibcon#about to read 4, iclass 16, count 0 2006.210.08:07:39.73#ibcon#read 4, iclass 16, count 0 2006.210.08:07:39.73#ibcon#about to read 5, iclass 16, count 0 2006.210.08:07:39.73#ibcon#read 5, iclass 16, count 0 2006.210.08:07:39.73#ibcon#about to read 6, iclass 16, count 0 2006.210.08:07:39.73#ibcon#read 6, iclass 16, count 0 2006.210.08:07:39.73#ibcon#end of sib2, iclass 16, count 0 2006.210.08:07:39.73#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:07:39.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:07:39.73#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:07:39.73#ibcon#*before write, iclass 16, count 0 2006.210.08:07:39.73#ibcon#enter sib2, iclass 16, count 0 2006.210.08:07:39.73#ibcon#flushed, iclass 16, count 0 2006.210.08:07:39.74#ibcon#about to write, iclass 16, count 0 2006.210.08:07:39.74#ibcon#wrote, iclass 16, count 0 2006.210.08:07:39.74#ibcon#about to read 3, iclass 16, count 0 2006.210.08:07:39.77#ibcon#read 3, iclass 16, count 0 2006.210.08:07:39.77#ibcon#about to read 4, iclass 16, count 0 2006.210.08:07:39.77#ibcon#read 4, iclass 16, count 0 2006.210.08:07:39.77#ibcon#about to read 5, iclass 16, count 0 2006.210.08:07:39.77#ibcon#read 5, iclass 16, count 0 2006.210.08:07:39.77#ibcon#about to read 6, iclass 16, count 0 2006.210.08:07:39.77#ibcon#read 6, iclass 16, count 0 2006.210.08:07:39.77#ibcon#end of sib2, iclass 16, count 0 2006.210.08:07:39.77#ibcon#*after write, iclass 16, count 0 2006.210.08:07:39.77#ibcon#*before return 0, iclass 16, count 0 2006.210.08:07:39.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:07:39.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:07:39.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:07:39.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:07:39.78$vc4f8/va=8,7 2006.210.08:07:39.78#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.08:07:39.78#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.08:07:39.78#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:39.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:07:39.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:07:39.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:07:39.82#ibcon#enter wrdev, iclass 18, count 2 2006.210.08:07:39.82#ibcon#first serial, iclass 18, count 2 2006.210.08:07:39.82#ibcon#enter sib2, iclass 18, count 2 2006.210.08:07:39.82#ibcon#flushed, iclass 18, count 2 2006.210.08:07:39.82#ibcon#about to write, iclass 18, count 2 2006.210.08:07:39.82#ibcon#wrote, iclass 18, count 2 2006.210.08:07:39.82#ibcon#about to read 3, iclass 18, count 2 2006.210.08:07:39.84#ibcon#read 3, iclass 18, count 2 2006.210.08:07:39.84#ibcon#about to read 4, iclass 18, count 2 2006.210.08:07:39.84#ibcon#read 4, iclass 18, count 2 2006.210.08:07:39.84#ibcon#about to read 5, iclass 18, count 2 2006.210.08:07:39.84#ibcon#read 5, iclass 18, count 2 2006.210.08:07:39.84#ibcon#about to read 6, iclass 18, count 2 2006.210.08:07:39.84#ibcon#read 6, iclass 18, count 2 2006.210.08:07:39.84#ibcon#end of sib2, iclass 18, count 2 2006.210.08:07:39.84#ibcon#*mode == 0, iclass 18, count 2 2006.210.08:07:39.84#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.08:07:39.84#ibcon#[25=AT08-07\r\n] 2006.210.08:07:39.84#ibcon#*before write, iclass 18, count 2 2006.210.08:07:39.84#ibcon#enter sib2, iclass 18, count 2 2006.210.08:07:39.84#ibcon#flushed, iclass 18, count 2 2006.210.08:07:39.84#ibcon#about to write, iclass 18, count 2 2006.210.08:07:39.85#ibcon#wrote, iclass 18, count 2 2006.210.08:07:39.85#ibcon#about to read 3, iclass 18, count 2 2006.210.08:07:39.87#ibcon#read 3, iclass 18, count 2 2006.210.08:07:39.87#ibcon#about to read 4, iclass 18, count 2 2006.210.08:07:39.87#ibcon#read 4, iclass 18, count 2 2006.210.08:07:39.87#ibcon#about to read 5, iclass 18, count 2 2006.210.08:07:39.87#ibcon#read 5, iclass 18, count 2 2006.210.08:07:39.87#ibcon#about to read 6, iclass 18, count 2 2006.210.08:07:39.87#ibcon#read 6, iclass 18, count 2 2006.210.08:07:39.87#ibcon#end of sib2, iclass 18, count 2 2006.210.08:07:39.87#ibcon#*after write, iclass 18, count 2 2006.210.08:07:39.87#ibcon#*before return 0, iclass 18, count 2 2006.210.08:07:39.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:07:39.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:07:39.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.08:07:39.87#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:39.88#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:07:39.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:07:39.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:07:39.98#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:07:39.98#ibcon#first serial, iclass 18, count 0 2006.210.08:07:39.98#ibcon#enter sib2, iclass 18, count 0 2006.210.08:07:39.98#ibcon#flushed, iclass 18, count 0 2006.210.08:07:39.98#ibcon#about to write, iclass 18, count 0 2006.210.08:07:39.98#ibcon#wrote, iclass 18, count 0 2006.210.08:07:39.98#ibcon#about to read 3, iclass 18, count 0 2006.210.08:07:40.00#ibcon#read 3, iclass 18, count 0 2006.210.08:07:40.00#ibcon#about to read 4, iclass 18, count 0 2006.210.08:07:40.00#ibcon#read 4, iclass 18, count 0 2006.210.08:07:40.00#ibcon#about to read 5, iclass 18, count 0 2006.210.08:07:40.00#ibcon#read 5, iclass 18, count 0 2006.210.08:07:40.00#ibcon#about to read 6, iclass 18, count 0 2006.210.08:07:40.00#ibcon#read 6, iclass 18, count 0 2006.210.08:07:40.00#ibcon#end of sib2, iclass 18, count 0 2006.210.08:07:40.00#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:07:40.00#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:07:40.00#ibcon#[25=USB\r\n] 2006.210.08:07:40.00#ibcon#*before write, iclass 18, count 0 2006.210.08:07:40.00#ibcon#enter sib2, iclass 18, count 0 2006.210.08:07:40.00#ibcon#flushed, iclass 18, count 0 2006.210.08:07:40.00#ibcon#about to write, iclass 18, count 0 2006.210.08:07:40.01#ibcon#wrote, iclass 18, count 0 2006.210.08:07:40.01#ibcon#about to read 3, iclass 18, count 0 2006.210.08:07:40.03#ibcon#read 3, iclass 18, count 0 2006.210.08:07:40.03#ibcon#about to read 4, iclass 18, count 0 2006.210.08:07:40.03#ibcon#read 4, iclass 18, count 0 2006.210.08:07:40.03#ibcon#about to read 5, iclass 18, count 0 2006.210.08:07:40.03#ibcon#read 5, iclass 18, count 0 2006.210.08:07:40.03#ibcon#about to read 6, iclass 18, count 0 2006.210.08:07:40.03#ibcon#read 6, iclass 18, count 0 2006.210.08:07:40.03#ibcon#end of sib2, iclass 18, count 0 2006.210.08:07:40.03#ibcon#*after write, iclass 18, count 0 2006.210.08:07:40.03#ibcon#*before return 0, iclass 18, count 0 2006.210.08:07:40.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:07:40.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:07:40.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:07:40.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:07:40.04$vc4f8/vblo=1,632.99 2006.210.08:07:40.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.08:07:40.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.08:07:40.04#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:40.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:07:40.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:07:40.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:07:40.04#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:07:40.04#ibcon#first serial, iclass 20, count 0 2006.210.08:07:40.04#ibcon#enter sib2, iclass 20, count 0 2006.210.08:07:40.04#ibcon#flushed, iclass 20, count 0 2006.210.08:07:40.04#ibcon#about to write, iclass 20, count 0 2006.210.08:07:40.04#ibcon#wrote, iclass 20, count 0 2006.210.08:07:40.04#ibcon#about to read 3, iclass 20, count 0 2006.210.08:07:40.05#ibcon#read 3, iclass 20, count 0 2006.210.08:07:40.05#ibcon#about to read 4, iclass 20, count 0 2006.210.08:07:40.05#ibcon#read 4, iclass 20, count 0 2006.210.08:07:40.05#ibcon#about to read 5, iclass 20, count 0 2006.210.08:07:40.05#ibcon#read 5, iclass 20, count 0 2006.210.08:07:40.05#ibcon#about to read 6, iclass 20, count 0 2006.210.08:07:40.05#ibcon#read 6, iclass 20, count 0 2006.210.08:07:40.05#ibcon#end of sib2, iclass 20, count 0 2006.210.08:07:40.05#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:07:40.05#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:07:40.05#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:07:40.05#ibcon#*before write, iclass 20, count 0 2006.210.08:07:40.05#ibcon#enter sib2, iclass 20, count 0 2006.210.08:07:40.05#ibcon#flushed, iclass 20, count 0 2006.210.08:07:40.05#ibcon#about to write, iclass 20, count 0 2006.210.08:07:40.06#ibcon#wrote, iclass 20, count 0 2006.210.08:07:40.06#ibcon#about to read 3, iclass 20, count 0 2006.210.08:07:40.09#ibcon#read 3, iclass 20, count 0 2006.210.08:07:40.09#ibcon#about to read 4, iclass 20, count 0 2006.210.08:07:40.09#ibcon#read 4, iclass 20, count 0 2006.210.08:07:40.09#ibcon#about to read 5, iclass 20, count 0 2006.210.08:07:40.09#ibcon#read 5, iclass 20, count 0 2006.210.08:07:40.09#ibcon#about to read 6, iclass 20, count 0 2006.210.08:07:40.09#ibcon#read 6, iclass 20, count 0 2006.210.08:07:40.09#ibcon#end of sib2, iclass 20, count 0 2006.210.08:07:40.09#ibcon#*after write, iclass 20, count 0 2006.210.08:07:40.09#ibcon#*before return 0, iclass 20, count 0 2006.210.08:07:40.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:07:40.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:07:40.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:07:40.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:07:40.10$vc4f8/vb=1,4 2006.210.08:07:40.10#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.08:07:40.10#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.08:07:40.10#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:40.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:07:40.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:07:40.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:07:40.10#ibcon#enter wrdev, iclass 22, count 2 2006.210.08:07:40.10#ibcon#first serial, iclass 22, count 2 2006.210.08:07:40.10#ibcon#enter sib2, iclass 22, count 2 2006.210.08:07:40.10#ibcon#flushed, iclass 22, count 2 2006.210.08:07:40.10#ibcon#about to write, iclass 22, count 2 2006.210.08:07:40.10#ibcon#wrote, iclass 22, count 2 2006.210.08:07:40.10#ibcon#about to read 3, iclass 22, count 2 2006.210.08:07:40.11#ibcon#read 3, iclass 22, count 2 2006.210.08:07:40.11#ibcon#about to read 4, iclass 22, count 2 2006.210.08:07:40.11#ibcon#read 4, iclass 22, count 2 2006.210.08:07:40.11#ibcon#about to read 5, iclass 22, count 2 2006.210.08:07:40.11#ibcon#read 5, iclass 22, count 2 2006.210.08:07:40.11#ibcon#about to read 6, iclass 22, count 2 2006.210.08:07:40.11#ibcon#read 6, iclass 22, count 2 2006.210.08:07:40.11#ibcon#end of sib2, iclass 22, count 2 2006.210.08:07:40.11#ibcon#*mode == 0, iclass 22, count 2 2006.210.08:07:40.11#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.08:07:40.11#ibcon#[27=AT01-04\r\n] 2006.210.08:07:40.11#ibcon#*before write, iclass 22, count 2 2006.210.08:07:40.11#ibcon#enter sib2, iclass 22, count 2 2006.210.08:07:40.11#ibcon#flushed, iclass 22, count 2 2006.210.08:07:40.11#ibcon#about to write, iclass 22, count 2 2006.210.08:07:40.12#ibcon#wrote, iclass 22, count 2 2006.210.08:07:40.12#ibcon#about to read 3, iclass 22, count 2 2006.210.08:07:40.14#ibcon#read 3, iclass 22, count 2 2006.210.08:07:40.14#ibcon#about to read 4, iclass 22, count 2 2006.210.08:07:40.14#ibcon#read 4, iclass 22, count 2 2006.210.08:07:40.14#ibcon#about to read 5, iclass 22, count 2 2006.210.08:07:40.14#ibcon#read 5, iclass 22, count 2 2006.210.08:07:40.14#ibcon#about to read 6, iclass 22, count 2 2006.210.08:07:40.14#ibcon#read 6, iclass 22, count 2 2006.210.08:07:40.14#ibcon#end of sib2, iclass 22, count 2 2006.210.08:07:40.14#ibcon#*after write, iclass 22, count 2 2006.210.08:07:40.14#ibcon#*before return 0, iclass 22, count 2 2006.210.08:07:40.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:07:40.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:07:40.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.08:07:40.14#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:40.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:07:40.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:07:40.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:07:40.26#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:07:40.26#ibcon#first serial, iclass 22, count 0 2006.210.08:07:40.26#ibcon#enter sib2, iclass 22, count 0 2006.210.08:07:40.26#ibcon#flushed, iclass 22, count 0 2006.210.08:07:40.26#ibcon#about to write, iclass 22, count 0 2006.210.08:07:40.26#ibcon#wrote, iclass 22, count 0 2006.210.08:07:40.26#ibcon#about to read 3, iclass 22, count 0 2006.210.08:07:40.28#ibcon#read 3, iclass 22, count 0 2006.210.08:07:40.28#ibcon#about to read 4, iclass 22, count 0 2006.210.08:07:40.28#ibcon#read 4, iclass 22, count 0 2006.210.08:07:40.28#ibcon#about to read 5, iclass 22, count 0 2006.210.08:07:40.28#ibcon#read 5, iclass 22, count 0 2006.210.08:07:40.28#ibcon#about to read 6, iclass 22, count 0 2006.210.08:07:40.28#ibcon#read 6, iclass 22, count 0 2006.210.08:07:40.28#ibcon#end of sib2, iclass 22, count 0 2006.210.08:07:40.28#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:07:40.28#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:07:40.28#ibcon#[27=USB\r\n] 2006.210.08:07:40.28#ibcon#*before write, iclass 22, count 0 2006.210.08:07:40.28#ibcon#enter sib2, iclass 22, count 0 2006.210.08:07:40.28#ibcon#flushed, iclass 22, count 0 2006.210.08:07:40.28#ibcon#about to write, iclass 22, count 0 2006.210.08:07:40.29#ibcon#wrote, iclass 22, count 0 2006.210.08:07:40.29#ibcon#about to read 3, iclass 22, count 0 2006.210.08:07:40.31#ibcon#read 3, iclass 22, count 0 2006.210.08:07:40.31#ibcon#about to read 4, iclass 22, count 0 2006.210.08:07:40.31#ibcon#read 4, iclass 22, count 0 2006.210.08:07:40.31#ibcon#about to read 5, iclass 22, count 0 2006.210.08:07:40.31#ibcon#read 5, iclass 22, count 0 2006.210.08:07:40.31#ibcon#about to read 6, iclass 22, count 0 2006.210.08:07:40.31#ibcon#read 6, iclass 22, count 0 2006.210.08:07:40.31#ibcon#end of sib2, iclass 22, count 0 2006.210.08:07:40.31#ibcon#*after write, iclass 22, count 0 2006.210.08:07:40.31#ibcon#*before return 0, iclass 22, count 0 2006.210.08:07:40.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:07:40.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:07:40.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:07:40.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:07:40.32$vc4f8/vblo=2,640.99 2006.210.08:07:40.32#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.08:07:40.32#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.08:07:40.32#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:40.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:40.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:40.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:40.32#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:07:40.32#ibcon#first serial, iclass 24, count 0 2006.210.08:07:40.32#ibcon#enter sib2, iclass 24, count 0 2006.210.08:07:40.32#ibcon#flushed, iclass 24, count 0 2006.210.08:07:40.32#ibcon#about to write, iclass 24, count 0 2006.210.08:07:40.32#ibcon#wrote, iclass 24, count 0 2006.210.08:07:40.32#ibcon#about to read 3, iclass 24, count 0 2006.210.08:07:40.33#ibcon#read 3, iclass 24, count 0 2006.210.08:07:40.33#ibcon#about to read 4, iclass 24, count 0 2006.210.08:07:40.33#ibcon#read 4, iclass 24, count 0 2006.210.08:07:40.33#ibcon#about to read 5, iclass 24, count 0 2006.210.08:07:40.33#ibcon#read 5, iclass 24, count 0 2006.210.08:07:40.33#ibcon#about to read 6, iclass 24, count 0 2006.210.08:07:40.33#ibcon#read 6, iclass 24, count 0 2006.210.08:07:40.33#ibcon#end of sib2, iclass 24, count 0 2006.210.08:07:40.33#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:07:40.33#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:07:40.33#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:07:40.33#ibcon#*before write, iclass 24, count 0 2006.210.08:07:40.33#ibcon#enter sib2, iclass 24, count 0 2006.210.08:07:40.33#ibcon#flushed, iclass 24, count 0 2006.210.08:07:40.33#ibcon#about to write, iclass 24, count 0 2006.210.08:07:40.34#ibcon#wrote, iclass 24, count 0 2006.210.08:07:40.34#ibcon#about to read 3, iclass 24, count 0 2006.210.08:07:40.37#ibcon#read 3, iclass 24, count 0 2006.210.08:07:40.37#ibcon#about to read 4, iclass 24, count 0 2006.210.08:07:40.37#ibcon#read 4, iclass 24, count 0 2006.210.08:07:40.37#ibcon#about to read 5, iclass 24, count 0 2006.210.08:07:40.37#ibcon#read 5, iclass 24, count 0 2006.210.08:07:40.37#ibcon#about to read 6, iclass 24, count 0 2006.210.08:07:40.37#ibcon#read 6, iclass 24, count 0 2006.210.08:07:40.37#ibcon#end of sib2, iclass 24, count 0 2006.210.08:07:40.37#ibcon#*after write, iclass 24, count 0 2006.210.08:07:40.37#ibcon#*before return 0, iclass 24, count 0 2006.210.08:07:40.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:40.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:07:40.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:07:40.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:07:40.38$vc4f8/vb=2,4 2006.210.08:07:40.38#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.08:07:40.38#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.08:07:40.38#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:40.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:40.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:40.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:40.42#ibcon#enter wrdev, iclass 26, count 2 2006.210.08:07:40.42#ibcon#first serial, iclass 26, count 2 2006.210.08:07:40.42#ibcon#enter sib2, iclass 26, count 2 2006.210.08:07:40.42#ibcon#flushed, iclass 26, count 2 2006.210.08:07:40.42#ibcon#about to write, iclass 26, count 2 2006.210.08:07:40.42#ibcon#wrote, iclass 26, count 2 2006.210.08:07:40.42#ibcon#about to read 3, iclass 26, count 2 2006.210.08:07:40.44#ibcon#read 3, iclass 26, count 2 2006.210.08:07:40.44#ibcon#about to read 4, iclass 26, count 2 2006.210.08:07:40.44#ibcon#read 4, iclass 26, count 2 2006.210.08:07:40.44#ibcon#about to read 5, iclass 26, count 2 2006.210.08:07:40.44#ibcon#read 5, iclass 26, count 2 2006.210.08:07:40.44#ibcon#about to read 6, iclass 26, count 2 2006.210.08:07:40.44#ibcon#read 6, iclass 26, count 2 2006.210.08:07:40.44#ibcon#end of sib2, iclass 26, count 2 2006.210.08:07:40.44#ibcon#*mode == 0, iclass 26, count 2 2006.210.08:07:40.44#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.08:07:40.44#ibcon#[27=AT02-04\r\n] 2006.210.08:07:40.44#ibcon#*before write, iclass 26, count 2 2006.210.08:07:40.44#ibcon#enter sib2, iclass 26, count 2 2006.210.08:07:40.44#ibcon#flushed, iclass 26, count 2 2006.210.08:07:40.44#ibcon#about to write, iclass 26, count 2 2006.210.08:07:40.45#ibcon#wrote, iclass 26, count 2 2006.210.08:07:40.45#ibcon#about to read 3, iclass 26, count 2 2006.210.08:07:40.47#ibcon#read 3, iclass 26, count 2 2006.210.08:07:40.47#ibcon#about to read 4, iclass 26, count 2 2006.210.08:07:40.47#ibcon#read 4, iclass 26, count 2 2006.210.08:07:40.47#ibcon#about to read 5, iclass 26, count 2 2006.210.08:07:40.47#ibcon#read 5, iclass 26, count 2 2006.210.08:07:40.47#ibcon#about to read 6, iclass 26, count 2 2006.210.08:07:40.47#ibcon#read 6, iclass 26, count 2 2006.210.08:07:40.47#ibcon#end of sib2, iclass 26, count 2 2006.210.08:07:40.47#ibcon#*after write, iclass 26, count 2 2006.210.08:07:40.47#ibcon#*before return 0, iclass 26, count 2 2006.210.08:07:40.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:40.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:07:40.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.08:07:40.47#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:40.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:40.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:40.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:40.59#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:07:40.59#ibcon#first serial, iclass 26, count 0 2006.210.08:07:40.59#ibcon#enter sib2, iclass 26, count 0 2006.210.08:07:40.59#ibcon#flushed, iclass 26, count 0 2006.210.08:07:40.59#ibcon#about to write, iclass 26, count 0 2006.210.08:07:40.59#ibcon#wrote, iclass 26, count 0 2006.210.08:07:40.59#ibcon#about to read 3, iclass 26, count 0 2006.210.08:07:40.61#ibcon#read 3, iclass 26, count 0 2006.210.08:07:40.61#ibcon#about to read 4, iclass 26, count 0 2006.210.08:07:40.61#ibcon#read 4, iclass 26, count 0 2006.210.08:07:40.61#ibcon#about to read 5, iclass 26, count 0 2006.210.08:07:40.61#ibcon#read 5, iclass 26, count 0 2006.210.08:07:40.61#ibcon#about to read 6, iclass 26, count 0 2006.210.08:07:40.61#ibcon#read 6, iclass 26, count 0 2006.210.08:07:40.61#ibcon#end of sib2, iclass 26, count 0 2006.210.08:07:40.61#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:07:40.61#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:07:40.61#ibcon#[27=USB\r\n] 2006.210.08:07:40.61#ibcon#*before write, iclass 26, count 0 2006.210.08:07:40.61#ibcon#enter sib2, iclass 26, count 0 2006.210.08:07:40.61#ibcon#flushed, iclass 26, count 0 2006.210.08:07:40.61#ibcon#about to write, iclass 26, count 0 2006.210.08:07:40.62#ibcon#wrote, iclass 26, count 0 2006.210.08:07:40.62#ibcon#about to read 3, iclass 26, count 0 2006.210.08:07:40.64#ibcon#read 3, iclass 26, count 0 2006.210.08:07:40.64#ibcon#about to read 4, iclass 26, count 0 2006.210.08:07:40.64#ibcon#read 4, iclass 26, count 0 2006.210.08:07:40.64#ibcon#about to read 5, iclass 26, count 0 2006.210.08:07:40.64#ibcon#read 5, iclass 26, count 0 2006.210.08:07:40.64#ibcon#about to read 6, iclass 26, count 0 2006.210.08:07:40.64#ibcon#read 6, iclass 26, count 0 2006.210.08:07:40.64#ibcon#end of sib2, iclass 26, count 0 2006.210.08:07:40.64#ibcon#*after write, iclass 26, count 0 2006.210.08:07:40.64#ibcon#*before return 0, iclass 26, count 0 2006.210.08:07:40.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:40.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:07:40.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:07:40.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:07:40.65$vc4f8/vblo=3,656.99 2006.210.08:07:40.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.08:07:40.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.08:07:40.65#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:40.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:40.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:40.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:40.65#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:07:40.65#ibcon#first serial, iclass 28, count 0 2006.210.08:07:40.65#ibcon#enter sib2, iclass 28, count 0 2006.210.08:07:40.65#ibcon#flushed, iclass 28, count 0 2006.210.08:07:40.65#ibcon#about to write, iclass 28, count 0 2006.210.08:07:40.65#ibcon#wrote, iclass 28, count 0 2006.210.08:07:40.65#ibcon#about to read 3, iclass 28, count 0 2006.210.08:07:40.66#ibcon#read 3, iclass 28, count 0 2006.210.08:07:40.66#ibcon#about to read 4, iclass 28, count 0 2006.210.08:07:40.66#ibcon#read 4, iclass 28, count 0 2006.210.08:07:40.66#ibcon#about to read 5, iclass 28, count 0 2006.210.08:07:40.66#ibcon#read 5, iclass 28, count 0 2006.210.08:07:40.66#ibcon#about to read 6, iclass 28, count 0 2006.210.08:07:40.66#ibcon#read 6, iclass 28, count 0 2006.210.08:07:40.66#ibcon#end of sib2, iclass 28, count 0 2006.210.08:07:40.66#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:07:40.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:07:40.66#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:07:40.66#ibcon#*before write, iclass 28, count 0 2006.210.08:07:40.66#ibcon#enter sib2, iclass 28, count 0 2006.210.08:07:40.66#ibcon#flushed, iclass 28, count 0 2006.210.08:07:40.66#ibcon#about to write, iclass 28, count 0 2006.210.08:07:40.67#ibcon#wrote, iclass 28, count 0 2006.210.08:07:40.67#ibcon#about to read 3, iclass 28, count 0 2006.210.08:07:40.70#ibcon#read 3, iclass 28, count 0 2006.210.08:07:40.70#ibcon#about to read 4, iclass 28, count 0 2006.210.08:07:40.70#ibcon#read 4, iclass 28, count 0 2006.210.08:07:40.70#ibcon#about to read 5, iclass 28, count 0 2006.210.08:07:40.70#ibcon#read 5, iclass 28, count 0 2006.210.08:07:40.70#ibcon#about to read 6, iclass 28, count 0 2006.210.08:07:40.70#ibcon#read 6, iclass 28, count 0 2006.210.08:07:40.70#ibcon#end of sib2, iclass 28, count 0 2006.210.08:07:40.70#ibcon#*after write, iclass 28, count 0 2006.210.08:07:40.70#ibcon#*before return 0, iclass 28, count 0 2006.210.08:07:40.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:40.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:07:40.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:07:40.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:07:40.71$vc4f8/vb=3,3 2006.210.08:07:40.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.08:07:40.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.08:07:40.71#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:40.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:40.75#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:40.75#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:40.75#ibcon#enter wrdev, iclass 30, count 2 2006.210.08:07:40.75#ibcon#first serial, iclass 30, count 2 2006.210.08:07:40.75#ibcon#enter sib2, iclass 30, count 2 2006.210.08:07:40.75#ibcon#flushed, iclass 30, count 2 2006.210.08:07:40.75#ibcon#about to write, iclass 30, count 2 2006.210.08:07:40.75#ibcon#wrote, iclass 30, count 2 2006.210.08:07:40.75#ibcon#about to read 3, iclass 30, count 2 2006.210.08:07:40.77#ibcon#read 3, iclass 30, count 2 2006.210.08:07:40.77#ibcon#about to read 4, iclass 30, count 2 2006.210.08:07:40.77#ibcon#read 4, iclass 30, count 2 2006.210.08:07:40.77#ibcon#about to read 5, iclass 30, count 2 2006.210.08:07:40.77#ibcon#read 5, iclass 30, count 2 2006.210.08:07:40.77#ibcon#about to read 6, iclass 30, count 2 2006.210.08:07:40.77#ibcon#read 6, iclass 30, count 2 2006.210.08:07:40.77#ibcon#end of sib2, iclass 30, count 2 2006.210.08:07:40.77#ibcon#*mode == 0, iclass 30, count 2 2006.210.08:07:40.77#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.08:07:40.77#ibcon#[27=AT03-03\r\n] 2006.210.08:07:40.77#ibcon#*before write, iclass 30, count 2 2006.210.08:07:40.77#ibcon#enter sib2, iclass 30, count 2 2006.210.08:07:40.77#ibcon#flushed, iclass 30, count 2 2006.210.08:07:40.77#ibcon#about to write, iclass 30, count 2 2006.210.08:07:40.78#ibcon#wrote, iclass 30, count 2 2006.210.08:07:40.78#ibcon#about to read 3, iclass 30, count 2 2006.210.08:07:40.80#ibcon#read 3, iclass 30, count 2 2006.210.08:07:40.80#ibcon#about to read 4, iclass 30, count 2 2006.210.08:07:40.80#ibcon#read 4, iclass 30, count 2 2006.210.08:07:40.80#ibcon#about to read 5, iclass 30, count 2 2006.210.08:07:40.80#ibcon#read 5, iclass 30, count 2 2006.210.08:07:40.80#ibcon#about to read 6, iclass 30, count 2 2006.210.08:07:40.80#ibcon#read 6, iclass 30, count 2 2006.210.08:07:40.80#ibcon#end of sib2, iclass 30, count 2 2006.210.08:07:40.80#ibcon#*after write, iclass 30, count 2 2006.210.08:07:40.80#ibcon#*before return 0, iclass 30, count 2 2006.210.08:07:40.80#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:40.80#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:07:40.80#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.08:07:40.80#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:40.81#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:40.92#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:40.92#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:40.92#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:07:40.92#ibcon#first serial, iclass 30, count 0 2006.210.08:07:40.92#ibcon#enter sib2, iclass 30, count 0 2006.210.08:07:40.92#ibcon#flushed, iclass 30, count 0 2006.210.08:07:40.92#ibcon#about to write, iclass 30, count 0 2006.210.08:07:40.92#ibcon#wrote, iclass 30, count 0 2006.210.08:07:40.92#ibcon#about to read 3, iclass 30, count 0 2006.210.08:07:40.94#ibcon#read 3, iclass 30, count 0 2006.210.08:07:40.94#ibcon#about to read 4, iclass 30, count 0 2006.210.08:07:40.94#ibcon#read 4, iclass 30, count 0 2006.210.08:07:40.94#ibcon#about to read 5, iclass 30, count 0 2006.210.08:07:40.94#ibcon#read 5, iclass 30, count 0 2006.210.08:07:40.94#ibcon#about to read 6, iclass 30, count 0 2006.210.08:07:40.94#ibcon#read 6, iclass 30, count 0 2006.210.08:07:40.94#ibcon#end of sib2, iclass 30, count 0 2006.210.08:07:40.94#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:07:40.94#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:07:40.94#ibcon#[27=USB\r\n] 2006.210.08:07:40.94#ibcon#*before write, iclass 30, count 0 2006.210.08:07:40.94#ibcon#enter sib2, iclass 30, count 0 2006.210.08:07:40.94#ibcon#flushed, iclass 30, count 0 2006.210.08:07:40.94#ibcon#about to write, iclass 30, count 0 2006.210.08:07:40.95#ibcon#wrote, iclass 30, count 0 2006.210.08:07:40.95#ibcon#about to read 3, iclass 30, count 0 2006.210.08:07:40.97#ibcon#read 3, iclass 30, count 0 2006.210.08:07:40.97#ibcon#about to read 4, iclass 30, count 0 2006.210.08:07:40.97#ibcon#read 4, iclass 30, count 0 2006.210.08:07:40.97#ibcon#about to read 5, iclass 30, count 0 2006.210.08:07:40.97#ibcon#read 5, iclass 30, count 0 2006.210.08:07:40.97#ibcon#about to read 6, iclass 30, count 0 2006.210.08:07:40.97#ibcon#read 6, iclass 30, count 0 2006.210.08:07:40.97#ibcon#end of sib2, iclass 30, count 0 2006.210.08:07:40.97#ibcon#*after write, iclass 30, count 0 2006.210.08:07:40.97#ibcon#*before return 0, iclass 30, count 0 2006.210.08:07:40.97#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:40.97#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:07:40.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:07:40.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:07:40.98$vc4f8/vblo=4,712.99 2006.210.08:07:40.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.08:07:40.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.08:07:40.98#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:40.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:40.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:40.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:40.98#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:07:40.98#ibcon#first serial, iclass 32, count 0 2006.210.08:07:40.98#ibcon#enter sib2, iclass 32, count 0 2006.210.08:07:40.98#ibcon#flushed, iclass 32, count 0 2006.210.08:07:40.98#ibcon#about to write, iclass 32, count 0 2006.210.08:07:40.98#ibcon#wrote, iclass 32, count 0 2006.210.08:07:40.98#ibcon#about to read 3, iclass 32, count 0 2006.210.08:07:40.99#ibcon#read 3, iclass 32, count 0 2006.210.08:07:40.99#ibcon#about to read 4, iclass 32, count 0 2006.210.08:07:40.99#ibcon#read 4, iclass 32, count 0 2006.210.08:07:40.99#ibcon#about to read 5, iclass 32, count 0 2006.210.08:07:40.99#ibcon#read 5, iclass 32, count 0 2006.210.08:07:40.99#ibcon#about to read 6, iclass 32, count 0 2006.210.08:07:40.99#ibcon#read 6, iclass 32, count 0 2006.210.08:07:40.99#ibcon#end of sib2, iclass 32, count 0 2006.210.08:07:40.99#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:07:40.99#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:07:40.99#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:07:40.99#ibcon#*before write, iclass 32, count 0 2006.210.08:07:40.99#ibcon#enter sib2, iclass 32, count 0 2006.210.08:07:40.99#ibcon#flushed, iclass 32, count 0 2006.210.08:07:40.99#ibcon#about to write, iclass 32, count 0 2006.210.08:07:41.00#ibcon#wrote, iclass 32, count 0 2006.210.08:07:41.00#ibcon#about to read 3, iclass 32, count 0 2006.210.08:07:41.03#ibcon#read 3, iclass 32, count 0 2006.210.08:07:41.03#ibcon#about to read 4, iclass 32, count 0 2006.210.08:07:41.03#ibcon#read 4, iclass 32, count 0 2006.210.08:07:41.03#ibcon#about to read 5, iclass 32, count 0 2006.210.08:07:41.03#ibcon#read 5, iclass 32, count 0 2006.210.08:07:41.03#ibcon#about to read 6, iclass 32, count 0 2006.210.08:07:41.03#ibcon#read 6, iclass 32, count 0 2006.210.08:07:41.03#ibcon#end of sib2, iclass 32, count 0 2006.210.08:07:41.03#ibcon#*after write, iclass 32, count 0 2006.210.08:07:41.03#ibcon#*before return 0, iclass 32, count 0 2006.210.08:07:41.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:41.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:07:41.03#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:07:41.03#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:07:41.04$vc4f8/vb=4,3 2006.210.08:07:41.04#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.08:07:41.04#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.08:07:41.04#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:41.04#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:41.08#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:41.08#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:41.08#ibcon#enter wrdev, iclass 34, count 2 2006.210.08:07:41.08#ibcon#first serial, iclass 34, count 2 2006.210.08:07:41.08#ibcon#enter sib2, iclass 34, count 2 2006.210.08:07:41.08#ibcon#flushed, iclass 34, count 2 2006.210.08:07:41.08#ibcon#about to write, iclass 34, count 2 2006.210.08:07:41.08#ibcon#wrote, iclass 34, count 2 2006.210.08:07:41.08#ibcon#about to read 3, iclass 34, count 2 2006.210.08:07:41.10#ibcon#read 3, iclass 34, count 2 2006.210.08:07:41.10#ibcon#about to read 4, iclass 34, count 2 2006.210.08:07:41.10#ibcon#read 4, iclass 34, count 2 2006.210.08:07:41.10#ibcon#about to read 5, iclass 34, count 2 2006.210.08:07:41.10#ibcon#read 5, iclass 34, count 2 2006.210.08:07:41.10#ibcon#about to read 6, iclass 34, count 2 2006.210.08:07:41.10#ibcon#read 6, iclass 34, count 2 2006.210.08:07:41.10#ibcon#end of sib2, iclass 34, count 2 2006.210.08:07:41.10#ibcon#*mode == 0, iclass 34, count 2 2006.210.08:07:41.10#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.08:07:41.10#ibcon#[27=AT04-03\r\n] 2006.210.08:07:41.10#ibcon#*before write, iclass 34, count 2 2006.210.08:07:41.10#ibcon#enter sib2, iclass 34, count 2 2006.210.08:07:41.10#ibcon#flushed, iclass 34, count 2 2006.210.08:07:41.10#ibcon#about to write, iclass 34, count 2 2006.210.08:07:41.11#ibcon#wrote, iclass 34, count 2 2006.210.08:07:41.11#ibcon#about to read 3, iclass 34, count 2 2006.210.08:07:41.13#ibcon#read 3, iclass 34, count 2 2006.210.08:07:41.13#ibcon#about to read 4, iclass 34, count 2 2006.210.08:07:41.13#ibcon#read 4, iclass 34, count 2 2006.210.08:07:41.13#ibcon#about to read 5, iclass 34, count 2 2006.210.08:07:41.13#ibcon#read 5, iclass 34, count 2 2006.210.08:07:41.13#ibcon#about to read 6, iclass 34, count 2 2006.210.08:07:41.13#ibcon#read 6, iclass 34, count 2 2006.210.08:07:41.13#ibcon#end of sib2, iclass 34, count 2 2006.210.08:07:41.13#ibcon#*after write, iclass 34, count 2 2006.210.08:07:41.13#ibcon#*before return 0, iclass 34, count 2 2006.210.08:07:41.13#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:41.13#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:07:41.13#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.08:07:41.13#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:41.14#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:41.24#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:41.24#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:41.24#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:07:41.24#ibcon#first serial, iclass 34, count 0 2006.210.08:07:41.24#ibcon#enter sib2, iclass 34, count 0 2006.210.08:07:41.24#ibcon#flushed, iclass 34, count 0 2006.210.08:07:41.24#ibcon#about to write, iclass 34, count 0 2006.210.08:07:41.24#ibcon#wrote, iclass 34, count 0 2006.210.08:07:41.24#ibcon#about to read 3, iclass 34, count 0 2006.210.08:07:41.26#ibcon#read 3, iclass 34, count 0 2006.210.08:07:41.26#ibcon#about to read 4, iclass 34, count 0 2006.210.08:07:41.26#ibcon#read 4, iclass 34, count 0 2006.210.08:07:41.26#ibcon#about to read 5, iclass 34, count 0 2006.210.08:07:41.26#ibcon#read 5, iclass 34, count 0 2006.210.08:07:41.26#ibcon#about to read 6, iclass 34, count 0 2006.210.08:07:41.26#ibcon#read 6, iclass 34, count 0 2006.210.08:07:41.26#ibcon#end of sib2, iclass 34, count 0 2006.210.08:07:41.26#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:07:41.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:07:41.26#ibcon#[27=USB\r\n] 2006.210.08:07:41.26#ibcon#*before write, iclass 34, count 0 2006.210.08:07:41.26#ibcon#enter sib2, iclass 34, count 0 2006.210.08:07:41.26#ibcon#flushed, iclass 34, count 0 2006.210.08:07:41.26#ibcon#about to write, iclass 34, count 0 2006.210.08:07:41.27#ibcon#wrote, iclass 34, count 0 2006.210.08:07:41.27#ibcon#about to read 3, iclass 34, count 0 2006.210.08:07:41.29#ibcon#read 3, iclass 34, count 0 2006.210.08:07:41.29#ibcon#about to read 4, iclass 34, count 0 2006.210.08:07:41.29#ibcon#read 4, iclass 34, count 0 2006.210.08:07:41.29#ibcon#about to read 5, iclass 34, count 0 2006.210.08:07:41.29#ibcon#read 5, iclass 34, count 0 2006.210.08:07:41.29#ibcon#about to read 6, iclass 34, count 0 2006.210.08:07:41.29#ibcon#read 6, iclass 34, count 0 2006.210.08:07:41.29#ibcon#end of sib2, iclass 34, count 0 2006.210.08:07:41.29#ibcon#*after write, iclass 34, count 0 2006.210.08:07:41.29#ibcon#*before return 0, iclass 34, count 0 2006.210.08:07:41.29#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:41.29#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:07:41.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:07:41.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:07:41.30$vc4f8/vblo=5,744.99 2006.210.08:07:41.30#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.08:07:41.30#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.08:07:41.30#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:41.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:41.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:41.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:41.30#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:07:41.30#ibcon#first serial, iclass 36, count 0 2006.210.08:07:41.30#ibcon#enter sib2, iclass 36, count 0 2006.210.08:07:41.30#ibcon#flushed, iclass 36, count 0 2006.210.08:07:41.30#ibcon#about to write, iclass 36, count 0 2006.210.08:07:41.30#ibcon#wrote, iclass 36, count 0 2006.210.08:07:41.30#ibcon#about to read 3, iclass 36, count 0 2006.210.08:07:41.31#ibcon#read 3, iclass 36, count 0 2006.210.08:07:41.31#ibcon#about to read 4, iclass 36, count 0 2006.210.08:07:41.31#ibcon#read 4, iclass 36, count 0 2006.210.08:07:41.31#ibcon#about to read 5, iclass 36, count 0 2006.210.08:07:41.31#ibcon#read 5, iclass 36, count 0 2006.210.08:07:41.31#ibcon#about to read 6, iclass 36, count 0 2006.210.08:07:41.31#ibcon#read 6, iclass 36, count 0 2006.210.08:07:41.31#ibcon#end of sib2, iclass 36, count 0 2006.210.08:07:41.31#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:07:41.31#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:07:41.31#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:07:41.31#ibcon#*before write, iclass 36, count 0 2006.210.08:07:41.31#ibcon#enter sib2, iclass 36, count 0 2006.210.08:07:41.31#ibcon#flushed, iclass 36, count 0 2006.210.08:07:41.31#ibcon#about to write, iclass 36, count 0 2006.210.08:07:41.32#ibcon#wrote, iclass 36, count 0 2006.210.08:07:41.32#ibcon#about to read 3, iclass 36, count 0 2006.210.08:07:41.35#ibcon#read 3, iclass 36, count 0 2006.210.08:07:41.35#ibcon#about to read 4, iclass 36, count 0 2006.210.08:07:41.35#ibcon#read 4, iclass 36, count 0 2006.210.08:07:41.35#ibcon#about to read 5, iclass 36, count 0 2006.210.08:07:41.35#ibcon#read 5, iclass 36, count 0 2006.210.08:07:41.35#ibcon#about to read 6, iclass 36, count 0 2006.210.08:07:41.35#ibcon#read 6, iclass 36, count 0 2006.210.08:07:41.35#ibcon#end of sib2, iclass 36, count 0 2006.210.08:07:41.35#ibcon#*after write, iclass 36, count 0 2006.210.08:07:41.35#ibcon#*before return 0, iclass 36, count 0 2006.210.08:07:41.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:41.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:07:41.35#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:07:41.35#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:07:41.36$vc4f8/vb=5,3 2006.210.08:07:41.36#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.08:07:41.36#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.08:07:41.36#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:41.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:41.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:41.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:41.40#ibcon#enter wrdev, iclass 38, count 2 2006.210.08:07:41.40#ibcon#first serial, iclass 38, count 2 2006.210.08:07:41.40#ibcon#enter sib2, iclass 38, count 2 2006.210.08:07:41.40#ibcon#flushed, iclass 38, count 2 2006.210.08:07:41.40#ibcon#about to write, iclass 38, count 2 2006.210.08:07:41.40#ibcon#wrote, iclass 38, count 2 2006.210.08:07:41.40#ibcon#about to read 3, iclass 38, count 2 2006.210.08:07:41.42#ibcon#read 3, iclass 38, count 2 2006.210.08:07:41.42#ibcon#about to read 4, iclass 38, count 2 2006.210.08:07:41.42#ibcon#read 4, iclass 38, count 2 2006.210.08:07:41.42#ibcon#about to read 5, iclass 38, count 2 2006.210.08:07:41.42#ibcon#read 5, iclass 38, count 2 2006.210.08:07:41.42#ibcon#about to read 6, iclass 38, count 2 2006.210.08:07:41.42#ibcon#read 6, iclass 38, count 2 2006.210.08:07:41.42#ibcon#end of sib2, iclass 38, count 2 2006.210.08:07:41.42#ibcon#*mode == 0, iclass 38, count 2 2006.210.08:07:41.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.08:07:41.42#ibcon#[27=AT05-03\r\n] 2006.210.08:07:41.42#ibcon#*before write, iclass 38, count 2 2006.210.08:07:41.42#ibcon#enter sib2, iclass 38, count 2 2006.210.08:07:41.42#ibcon#flushed, iclass 38, count 2 2006.210.08:07:41.42#ibcon#about to write, iclass 38, count 2 2006.210.08:07:41.43#ibcon#wrote, iclass 38, count 2 2006.210.08:07:41.43#ibcon#about to read 3, iclass 38, count 2 2006.210.08:07:41.45#ibcon#read 3, iclass 38, count 2 2006.210.08:07:41.45#ibcon#about to read 4, iclass 38, count 2 2006.210.08:07:41.45#ibcon#read 4, iclass 38, count 2 2006.210.08:07:41.45#ibcon#about to read 5, iclass 38, count 2 2006.210.08:07:41.45#ibcon#read 5, iclass 38, count 2 2006.210.08:07:41.45#ibcon#about to read 6, iclass 38, count 2 2006.210.08:07:41.45#ibcon#read 6, iclass 38, count 2 2006.210.08:07:41.45#ibcon#end of sib2, iclass 38, count 2 2006.210.08:07:41.45#ibcon#*after write, iclass 38, count 2 2006.210.08:07:41.45#ibcon#*before return 0, iclass 38, count 2 2006.210.08:07:41.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:41.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:07:41.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.08:07:41.45#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:41.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:41.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:41.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:41.57#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:07:41.57#ibcon#first serial, iclass 38, count 0 2006.210.08:07:41.57#ibcon#enter sib2, iclass 38, count 0 2006.210.08:07:41.57#ibcon#flushed, iclass 38, count 0 2006.210.08:07:41.57#ibcon#about to write, iclass 38, count 0 2006.210.08:07:41.58#ibcon#wrote, iclass 38, count 0 2006.210.08:07:41.58#ibcon#about to read 3, iclass 38, count 0 2006.210.08:07:41.59#ibcon#read 3, iclass 38, count 0 2006.210.08:07:41.59#ibcon#about to read 4, iclass 38, count 0 2006.210.08:07:41.59#ibcon#read 4, iclass 38, count 0 2006.210.08:07:41.59#ibcon#about to read 5, iclass 38, count 0 2006.210.08:07:41.59#ibcon#read 5, iclass 38, count 0 2006.210.08:07:41.59#ibcon#about to read 6, iclass 38, count 0 2006.210.08:07:41.59#ibcon#read 6, iclass 38, count 0 2006.210.08:07:41.59#ibcon#end of sib2, iclass 38, count 0 2006.210.08:07:41.59#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:07:41.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:07:41.59#ibcon#[27=USB\r\n] 2006.210.08:07:41.59#ibcon#*before write, iclass 38, count 0 2006.210.08:07:41.59#ibcon#enter sib2, iclass 38, count 0 2006.210.08:07:41.59#ibcon#flushed, iclass 38, count 0 2006.210.08:07:41.59#ibcon#about to write, iclass 38, count 0 2006.210.08:07:41.60#ibcon#wrote, iclass 38, count 0 2006.210.08:07:41.60#ibcon#about to read 3, iclass 38, count 0 2006.210.08:07:41.62#ibcon#read 3, iclass 38, count 0 2006.210.08:07:41.62#ibcon#about to read 4, iclass 38, count 0 2006.210.08:07:41.62#ibcon#read 4, iclass 38, count 0 2006.210.08:07:41.62#ibcon#about to read 5, iclass 38, count 0 2006.210.08:07:41.62#ibcon#read 5, iclass 38, count 0 2006.210.08:07:41.62#ibcon#about to read 6, iclass 38, count 0 2006.210.08:07:41.62#ibcon#read 6, iclass 38, count 0 2006.210.08:07:41.62#ibcon#end of sib2, iclass 38, count 0 2006.210.08:07:41.62#ibcon#*after write, iclass 38, count 0 2006.210.08:07:41.62#ibcon#*before return 0, iclass 38, count 0 2006.210.08:07:41.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:41.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:07:41.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:07:41.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:07:41.63$vc4f8/vblo=6,752.99 2006.210.08:07:41.63#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.08:07:41.63#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.08:07:41.63#ibcon#ireg 17 cls_cnt 0 2006.210.08:07:41.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:41.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:41.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:41.63#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:07:41.63#ibcon#first serial, iclass 40, count 0 2006.210.08:07:41.63#ibcon#enter sib2, iclass 40, count 0 2006.210.08:07:41.63#ibcon#flushed, iclass 40, count 0 2006.210.08:07:41.63#ibcon#about to write, iclass 40, count 0 2006.210.08:07:41.63#ibcon#wrote, iclass 40, count 0 2006.210.08:07:41.63#ibcon#about to read 3, iclass 40, count 0 2006.210.08:07:41.64#ibcon#read 3, iclass 40, count 0 2006.210.08:07:41.64#ibcon#about to read 4, iclass 40, count 0 2006.210.08:07:41.64#ibcon#read 4, iclass 40, count 0 2006.210.08:07:41.64#ibcon#about to read 5, iclass 40, count 0 2006.210.08:07:41.64#ibcon#read 5, iclass 40, count 0 2006.210.08:07:41.64#ibcon#about to read 6, iclass 40, count 0 2006.210.08:07:41.64#ibcon#read 6, iclass 40, count 0 2006.210.08:07:41.64#ibcon#end of sib2, iclass 40, count 0 2006.210.08:07:41.64#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:07:41.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:07:41.64#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:07:41.64#ibcon#*before write, iclass 40, count 0 2006.210.08:07:41.64#ibcon#enter sib2, iclass 40, count 0 2006.210.08:07:41.64#ibcon#flushed, iclass 40, count 0 2006.210.08:07:41.64#ibcon#about to write, iclass 40, count 0 2006.210.08:07:41.65#ibcon#wrote, iclass 40, count 0 2006.210.08:07:41.65#ibcon#about to read 3, iclass 40, count 0 2006.210.08:07:41.68#ibcon#read 3, iclass 40, count 0 2006.210.08:07:41.68#ibcon#about to read 4, iclass 40, count 0 2006.210.08:07:41.68#ibcon#read 4, iclass 40, count 0 2006.210.08:07:41.68#ibcon#about to read 5, iclass 40, count 0 2006.210.08:07:41.68#ibcon#read 5, iclass 40, count 0 2006.210.08:07:41.68#ibcon#about to read 6, iclass 40, count 0 2006.210.08:07:41.68#ibcon#read 6, iclass 40, count 0 2006.210.08:07:41.68#ibcon#end of sib2, iclass 40, count 0 2006.210.08:07:41.68#ibcon#*after write, iclass 40, count 0 2006.210.08:07:41.68#ibcon#*before return 0, iclass 40, count 0 2006.210.08:07:41.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:41.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:07:41.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:07:41.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:07:41.69$vc4f8/vb=6,3 2006.210.08:07:41.69#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.08:07:41.69#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.08:07:41.69#ibcon#ireg 11 cls_cnt 2 2006.210.08:07:41.69#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:41.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:41.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:41.73#ibcon#enter wrdev, iclass 4, count 2 2006.210.08:07:41.73#ibcon#first serial, iclass 4, count 2 2006.210.08:07:41.73#ibcon#enter sib2, iclass 4, count 2 2006.210.08:07:41.73#ibcon#flushed, iclass 4, count 2 2006.210.08:07:41.73#ibcon#about to write, iclass 4, count 2 2006.210.08:07:41.73#ibcon#wrote, iclass 4, count 2 2006.210.08:07:41.73#ibcon#about to read 3, iclass 4, count 2 2006.210.08:07:41.75#ibcon#read 3, iclass 4, count 2 2006.210.08:07:41.75#ibcon#about to read 4, iclass 4, count 2 2006.210.08:07:41.75#ibcon#read 4, iclass 4, count 2 2006.210.08:07:41.75#ibcon#about to read 5, iclass 4, count 2 2006.210.08:07:41.75#ibcon#read 5, iclass 4, count 2 2006.210.08:07:41.75#ibcon#about to read 6, iclass 4, count 2 2006.210.08:07:41.75#ibcon#read 6, iclass 4, count 2 2006.210.08:07:41.75#ibcon#end of sib2, iclass 4, count 2 2006.210.08:07:41.75#ibcon#*mode == 0, iclass 4, count 2 2006.210.08:07:41.75#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.08:07:41.75#ibcon#[27=AT06-03\r\n] 2006.210.08:07:41.75#ibcon#*before write, iclass 4, count 2 2006.210.08:07:41.75#ibcon#enter sib2, iclass 4, count 2 2006.210.08:07:41.75#ibcon#flushed, iclass 4, count 2 2006.210.08:07:41.75#ibcon#about to write, iclass 4, count 2 2006.210.08:07:41.76#ibcon#wrote, iclass 4, count 2 2006.210.08:07:41.76#ibcon#about to read 3, iclass 4, count 2 2006.210.08:07:41.78#ibcon#read 3, iclass 4, count 2 2006.210.08:07:41.78#ibcon#about to read 4, iclass 4, count 2 2006.210.08:07:41.78#ibcon#read 4, iclass 4, count 2 2006.210.08:07:41.78#ibcon#about to read 5, iclass 4, count 2 2006.210.08:07:41.78#ibcon#read 5, iclass 4, count 2 2006.210.08:07:41.78#ibcon#about to read 6, iclass 4, count 2 2006.210.08:07:41.78#ibcon#read 6, iclass 4, count 2 2006.210.08:07:41.78#ibcon#end of sib2, iclass 4, count 2 2006.210.08:07:41.78#ibcon#*after write, iclass 4, count 2 2006.210.08:07:41.78#ibcon#*before return 0, iclass 4, count 2 2006.210.08:07:41.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:41.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:07:41.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.08:07:41.78#ibcon#ireg 7 cls_cnt 0 2006.210.08:07:41.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:41.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:41.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:41.90#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:07:41.90#ibcon#first serial, iclass 4, count 0 2006.210.08:07:41.90#ibcon#enter sib2, iclass 4, count 0 2006.210.08:07:41.90#ibcon#flushed, iclass 4, count 0 2006.210.08:07:41.90#ibcon#about to write, iclass 4, count 0 2006.210.08:07:41.90#ibcon#wrote, iclass 4, count 0 2006.210.08:07:41.90#ibcon#about to read 3, iclass 4, count 0 2006.210.08:07:41.92#ibcon#read 3, iclass 4, count 0 2006.210.08:07:41.92#ibcon#about to read 4, iclass 4, count 0 2006.210.08:07:41.92#ibcon#read 4, iclass 4, count 0 2006.210.08:07:41.92#ibcon#about to read 5, iclass 4, count 0 2006.210.08:07:41.92#ibcon#read 5, iclass 4, count 0 2006.210.08:07:41.92#ibcon#about to read 6, iclass 4, count 0 2006.210.08:07:41.92#ibcon#read 6, iclass 4, count 0 2006.210.08:07:41.92#ibcon#end of sib2, iclass 4, count 0 2006.210.08:07:41.92#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:07:41.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:07:41.92#ibcon#[27=USB\r\n] 2006.210.08:07:41.92#ibcon#*before write, iclass 4, count 0 2006.210.08:07:41.92#ibcon#enter sib2, iclass 4, count 0 2006.210.08:07:41.92#ibcon#flushed, iclass 4, count 0 2006.210.08:07:41.92#ibcon#about to write, iclass 4, count 0 2006.210.08:07:41.93#ibcon#wrote, iclass 4, count 0 2006.210.08:07:41.93#ibcon#about to read 3, iclass 4, count 0 2006.210.08:07:41.95#ibcon#read 3, iclass 4, count 0 2006.210.08:07:41.95#ibcon#about to read 4, iclass 4, count 0 2006.210.08:07:41.95#ibcon#read 4, iclass 4, count 0 2006.210.08:07:41.95#ibcon#about to read 5, iclass 4, count 0 2006.210.08:07:41.95#ibcon#read 5, iclass 4, count 0 2006.210.08:07:41.95#ibcon#about to read 6, iclass 4, count 0 2006.210.08:07:41.95#ibcon#read 6, iclass 4, count 0 2006.210.08:07:41.95#ibcon#end of sib2, iclass 4, count 0 2006.210.08:07:41.95#ibcon#*after write, iclass 4, count 0 2006.210.08:07:41.95#ibcon#*before return 0, iclass 4, count 0 2006.210.08:07:41.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:41.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:07:41.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:07:41.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:07:41.96$vc4f8/vabw=wide 2006.210.08:07:41.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.08:07:41.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.08:07:41.96#ibcon#ireg 8 cls_cnt 0 2006.210.08:07:41.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:41.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:41.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:41.96#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:07:41.96#ibcon#first serial, iclass 6, count 0 2006.210.08:07:41.96#ibcon#enter sib2, iclass 6, count 0 2006.210.08:07:41.96#ibcon#flushed, iclass 6, count 0 2006.210.08:07:41.96#ibcon#about to write, iclass 6, count 0 2006.210.08:07:41.96#ibcon#wrote, iclass 6, count 0 2006.210.08:07:41.96#ibcon#about to read 3, iclass 6, count 0 2006.210.08:07:41.97#ibcon#read 3, iclass 6, count 0 2006.210.08:07:41.97#ibcon#about to read 4, iclass 6, count 0 2006.210.08:07:41.97#ibcon#read 4, iclass 6, count 0 2006.210.08:07:41.97#ibcon#about to read 5, iclass 6, count 0 2006.210.08:07:41.97#ibcon#read 5, iclass 6, count 0 2006.210.08:07:41.97#ibcon#about to read 6, iclass 6, count 0 2006.210.08:07:41.97#ibcon#read 6, iclass 6, count 0 2006.210.08:07:41.97#ibcon#end of sib2, iclass 6, count 0 2006.210.08:07:41.97#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:07:41.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:07:41.97#ibcon#[25=BW32\r\n] 2006.210.08:07:41.97#ibcon#*before write, iclass 6, count 0 2006.210.08:07:41.97#ibcon#enter sib2, iclass 6, count 0 2006.210.08:07:41.97#ibcon#flushed, iclass 6, count 0 2006.210.08:07:41.97#ibcon#about to write, iclass 6, count 0 2006.210.08:07:41.98#ibcon#wrote, iclass 6, count 0 2006.210.08:07:41.98#ibcon#about to read 3, iclass 6, count 0 2006.210.08:07:42.00#ibcon#read 3, iclass 6, count 0 2006.210.08:07:42.00#ibcon#about to read 4, iclass 6, count 0 2006.210.08:07:42.00#ibcon#read 4, iclass 6, count 0 2006.210.08:07:42.00#ibcon#about to read 5, iclass 6, count 0 2006.210.08:07:42.00#ibcon#read 5, iclass 6, count 0 2006.210.08:07:42.00#ibcon#about to read 6, iclass 6, count 0 2006.210.08:07:42.00#ibcon#read 6, iclass 6, count 0 2006.210.08:07:42.00#ibcon#end of sib2, iclass 6, count 0 2006.210.08:07:42.00#ibcon#*after write, iclass 6, count 0 2006.210.08:07:42.00#ibcon#*before return 0, iclass 6, count 0 2006.210.08:07:42.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:42.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:07:42.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:07:42.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:07:42.01$vc4f8/vbbw=wide 2006.210.08:07:42.01#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.08:07:42.01#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.08:07:42.01#ibcon#ireg 8 cls_cnt 0 2006.210.08:07:42.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:07:42.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:07:42.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:07:42.06#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:07:42.06#ibcon#first serial, iclass 10, count 0 2006.210.08:07:42.06#ibcon#enter sib2, iclass 10, count 0 2006.210.08:07:42.06#ibcon#flushed, iclass 10, count 0 2006.210.08:07:42.06#ibcon#about to write, iclass 10, count 0 2006.210.08:07:42.06#ibcon#wrote, iclass 10, count 0 2006.210.08:07:42.06#ibcon#about to read 3, iclass 10, count 0 2006.210.08:07:42.08#ibcon#read 3, iclass 10, count 0 2006.210.08:07:42.08#ibcon#about to read 4, iclass 10, count 0 2006.210.08:07:42.08#ibcon#read 4, iclass 10, count 0 2006.210.08:07:42.08#ibcon#about to read 5, iclass 10, count 0 2006.210.08:07:42.08#ibcon#read 5, iclass 10, count 0 2006.210.08:07:42.08#ibcon#about to read 6, iclass 10, count 0 2006.210.08:07:42.08#ibcon#read 6, iclass 10, count 0 2006.210.08:07:42.08#ibcon#end of sib2, iclass 10, count 0 2006.210.08:07:42.08#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:07:42.08#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:07:42.08#ibcon#[27=BW32\r\n] 2006.210.08:07:42.08#ibcon#*before write, iclass 10, count 0 2006.210.08:07:42.08#ibcon#enter sib2, iclass 10, count 0 2006.210.08:07:42.08#ibcon#flushed, iclass 10, count 0 2006.210.08:07:42.08#ibcon#about to write, iclass 10, count 0 2006.210.08:07:42.09#ibcon#wrote, iclass 10, count 0 2006.210.08:07:42.09#ibcon#about to read 3, iclass 10, count 0 2006.210.08:07:42.11#ibcon#read 3, iclass 10, count 0 2006.210.08:07:42.11#ibcon#about to read 4, iclass 10, count 0 2006.210.08:07:42.11#ibcon#read 4, iclass 10, count 0 2006.210.08:07:42.11#ibcon#about to read 5, iclass 10, count 0 2006.210.08:07:42.11#ibcon#read 5, iclass 10, count 0 2006.210.08:07:42.11#ibcon#about to read 6, iclass 10, count 0 2006.210.08:07:42.11#ibcon#read 6, iclass 10, count 0 2006.210.08:07:42.11#ibcon#end of sib2, iclass 10, count 0 2006.210.08:07:42.11#ibcon#*after write, iclass 10, count 0 2006.210.08:07:42.11#ibcon#*before return 0, iclass 10, count 0 2006.210.08:07:42.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:07:42.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:07:42.11#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:07:42.11#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:07:42.12$4f8m12a/ifd4f 2006.210.08:07:42.12$ifd4f/lo= 2006.210.08:07:42.12$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:07:42.12$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:07:42.12$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:07:42.12$ifd4f/patch= 2006.210.08:07:42.12$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:07:42.12$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:07:42.12$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:07:42.12$4f8m12a/"form=m,16.000,1:2 2006.210.08:07:42.12$4f8m12a/"tpicd 2006.210.08:07:42.12$4f8m12a/echo=off 2006.210.08:07:42.12$4f8m12a/xlog=off 2006.210.08:07:42.12:!2006.210.08:08:10 2006.210.08:07:53.14#trakl#Source acquired 2006.210.08:07:55.15#flagr#flagr/antenna,acquired 2006.210.08:08:10.02:preob 2006.210.08:08:11.15/onsource/TRACKING 2006.210.08:08:11.15:!2006.210.08:08:20 2006.210.08:08:20.02:data_valid=on 2006.210.08:08:20.02:midob 2006.210.08:08:21.15/onsource/TRACKING 2006.210.08:08:21.15/wx/30.23,1006.4,82 2006.210.08:08:21.30/cable/+6.3947E-03 2006.210.08:08:22.39/va/01,08,usb,yes,29,31 2006.210.08:08:22.39/va/02,07,usb,yes,29,30 2006.210.08:08:22.39/va/03,06,usb,yes,31,31 2006.210.08:08:22.39/va/04,07,usb,yes,30,32 2006.210.08:08:22.39/va/05,07,usb,yes,31,33 2006.210.08:08:22.39/va/06,06,usb,yes,30,30 2006.210.08:08:22.39/va/07,06,usb,yes,31,30 2006.210.08:08:22.39/va/08,07,usb,yes,29,28 2006.210.08:08:22.62/valo/01,532.99,yes,locked 2006.210.08:08:22.62/valo/02,572.99,yes,locked 2006.210.08:08:22.62/valo/03,672.99,yes,locked 2006.210.08:08:22.62/valo/04,832.99,yes,locked 2006.210.08:08:22.62/valo/05,652.99,yes,locked 2006.210.08:08:22.62/valo/06,772.99,yes,locked 2006.210.08:08:22.62/valo/07,832.99,yes,locked 2006.210.08:08:22.62/valo/08,852.99,yes,locked 2006.210.08:08:23.71/vb/01,04,usb,yes,28,27 2006.210.08:08:23.71/vb/02,04,usb,yes,30,31 2006.210.08:08:23.71/vb/03,03,usb,yes,33,37 2006.210.08:08:23.71/vb/04,03,usb,yes,34,34 2006.210.08:08:23.71/vb/05,03,usb,yes,32,37 2006.210.08:08:23.71/vb/06,03,usb,yes,33,36 2006.210.08:08:23.71/vb/07,04,usb,yes,29,29 2006.210.08:08:23.71/vb/08,03,usb,yes,33,37 2006.210.08:08:23.94/vblo/01,632.99,yes,locked 2006.210.08:08:23.94/vblo/02,640.99,yes,locked 2006.210.08:08:23.94/vblo/03,656.99,yes,locked 2006.210.08:08:23.94/vblo/04,712.99,yes,locked 2006.210.08:08:23.94/vblo/05,744.99,yes,locked 2006.210.08:08:23.94/vblo/06,752.99,yes,locked 2006.210.08:08:23.94/vblo/07,734.99,yes,locked 2006.210.08:08:23.94/vblo/08,744.99,yes,locked 2006.210.08:08:24.09/vabw/8 2006.210.08:08:24.24/vbbw/8 2006.210.08:08:24.33/xfe/off,on,12.7 2006.210.08:08:24.70/ifatt/23,28,28,28 2006.210.08:08:25.07/fmout-gps/S +4.60E-07 2006.210.08:08:25.12:!2006.210.08:09:20 2006.210.08:09:20.02:data_valid=off 2006.210.08:09:20.02:postob 2006.210.08:09:20.15/cable/+6.3935E-03 2006.210.08:09:20.15/wx/30.20,1006.4,82 2006.210.08:09:21.07/fmout-gps/S +4.60E-07 2006.210.08:09:21.08:scan_name=210-0810,k06210,60 2006.210.08:09:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.210.08:09:22.14#flagr#flagr/antenna,new-source 2006.210.08:09:22.15:checkk5 2006.210.08:09:22.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:09:22.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:09:23.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:09:23.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:09:23.85/chk_obsdata//k5ts1/T2100808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:09:24.18/chk_obsdata//k5ts2/T2100808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:09:24.52/chk_obsdata//k5ts3/T2100808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:09:24.85/chk_obsdata//k5ts4/T2100808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:09:25.51/k5log//k5ts1_log_newline 2006.210.08:09:26.17/k5log//k5ts2_log_newline 2006.210.08:09:26.82/k5log//k5ts3_log_newline 2006.210.08:09:27.49/k5log//k5ts4_log_newline 2006.210.08:09:27.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:09:27.52:4f8m12a=2 2006.210.08:09:27.52$4f8m12a/echo=on 2006.210.08:09:27.52$4f8m12a/pcalon 2006.210.08:09:27.52$pcalon/"no phase cal control is implemented here 2006.210.08:09:27.52$4f8m12a/"tpicd=stop 2006.210.08:09:27.52$4f8m12a/vc4f8 2006.210.08:09:27.52$vc4f8/valo=1,532.99 2006.210.08:09:27.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:09:27.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:09:27.52#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:27.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:27.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:27.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:27.52#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:09:27.52#ibcon#first serial, iclass 17, count 0 2006.210.08:09:27.52#ibcon#enter sib2, iclass 17, count 0 2006.210.08:09:27.52#ibcon#flushed, iclass 17, count 0 2006.210.08:09:27.52#ibcon#about to write, iclass 17, count 0 2006.210.08:09:27.52#ibcon#wrote, iclass 17, count 0 2006.210.08:09:27.52#ibcon#about to read 3, iclass 17, count 0 2006.210.08:09:27.53#ibcon#read 3, iclass 17, count 0 2006.210.08:09:27.53#ibcon#about to read 4, iclass 17, count 0 2006.210.08:09:27.53#ibcon#read 4, iclass 17, count 0 2006.210.08:09:27.53#ibcon#about to read 5, iclass 17, count 0 2006.210.08:09:27.53#ibcon#read 5, iclass 17, count 0 2006.210.08:09:27.53#ibcon#about to read 6, iclass 17, count 0 2006.210.08:09:27.53#ibcon#read 6, iclass 17, count 0 2006.210.08:09:27.53#ibcon#end of sib2, iclass 17, count 0 2006.210.08:09:27.53#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:09:27.53#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:09:27.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:09:27.53#ibcon#*before write, iclass 17, count 0 2006.210.08:09:27.53#ibcon#enter sib2, iclass 17, count 0 2006.210.08:09:27.53#ibcon#flushed, iclass 17, count 0 2006.210.08:09:27.53#ibcon#about to write, iclass 17, count 0 2006.210.08:09:27.53#ibcon#wrote, iclass 17, count 0 2006.210.08:09:27.53#ibcon#about to read 3, iclass 17, count 0 2006.210.08:09:27.58#ibcon#read 3, iclass 17, count 0 2006.210.08:09:27.58#ibcon#about to read 4, iclass 17, count 0 2006.210.08:09:27.58#ibcon#read 4, iclass 17, count 0 2006.210.08:09:27.58#ibcon#about to read 5, iclass 17, count 0 2006.210.08:09:27.58#ibcon#read 5, iclass 17, count 0 2006.210.08:09:27.58#ibcon#about to read 6, iclass 17, count 0 2006.210.08:09:27.58#ibcon#read 6, iclass 17, count 0 2006.210.08:09:27.58#ibcon#end of sib2, iclass 17, count 0 2006.210.08:09:27.58#ibcon#*after write, iclass 17, count 0 2006.210.08:09:27.58#ibcon#*before return 0, iclass 17, count 0 2006.210.08:09:27.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:27.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:27.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:09:27.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:09:27.58$vc4f8/va=1,8 2006.210.08:09:27.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:09:27.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:09:27.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:27.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:27.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:27.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:27.58#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:09:27.58#ibcon#first serial, iclass 19, count 2 2006.210.08:09:27.58#ibcon#enter sib2, iclass 19, count 2 2006.210.08:09:27.58#ibcon#flushed, iclass 19, count 2 2006.210.08:09:27.58#ibcon#about to write, iclass 19, count 2 2006.210.08:09:27.59#ibcon#wrote, iclass 19, count 2 2006.210.08:09:27.59#ibcon#about to read 3, iclass 19, count 2 2006.210.08:09:27.60#ibcon#read 3, iclass 19, count 2 2006.210.08:09:27.60#ibcon#about to read 4, iclass 19, count 2 2006.210.08:09:27.60#ibcon#read 4, iclass 19, count 2 2006.210.08:09:27.60#ibcon#about to read 5, iclass 19, count 2 2006.210.08:09:27.60#ibcon#read 5, iclass 19, count 2 2006.210.08:09:27.60#ibcon#about to read 6, iclass 19, count 2 2006.210.08:09:27.60#ibcon#read 6, iclass 19, count 2 2006.210.08:09:27.60#ibcon#end of sib2, iclass 19, count 2 2006.210.08:09:27.60#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:09:27.60#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:09:27.60#ibcon#[25=AT01-08\r\n] 2006.210.08:09:27.60#ibcon#*before write, iclass 19, count 2 2006.210.08:09:27.60#ibcon#enter sib2, iclass 19, count 2 2006.210.08:09:27.60#ibcon#flushed, iclass 19, count 2 2006.210.08:09:27.60#ibcon#about to write, iclass 19, count 2 2006.210.08:09:27.60#ibcon#wrote, iclass 19, count 2 2006.210.08:09:27.60#ibcon#about to read 3, iclass 19, count 2 2006.210.08:09:27.63#ibcon#read 3, iclass 19, count 2 2006.210.08:09:27.63#ibcon#about to read 4, iclass 19, count 2 2006.210.08:09:27.63#ibcon#read 4, iclass 19, count 2 2006.210.08:09:27.63#ibcon#about to read 5, iclass 19, count 2 2006.210.08:09:27.63#ibcon#read 5, iclass 19, count 2 2006.210.08:09:27.63#ibcon#about to read 6, iclass 19, count 2 2006.210.08:09:27.63#ibcon#read 6, iclass 19, count 2 2006.210.08:09:27.63#ibcon#end of sib2, iclass 19, count 2 2006.210.08:09:27.63#ibcon#*after write, iclass 19, count 2 2006.210.08:09:27.63#ibcon#*before return 0, iclass 19, count 2 2006.210.08:09:27.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:27.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:27.63#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:09:27.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:27.63#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:27.75#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:27.75#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:27.75#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:09:27.75#ibcon#first serial, iclass 19, count 0 2006.210.08:09:27.75#ibcon#enter sib2, iclass 19, count 0 2006.210.08:09:27.75#ibcon#flushed, iclass 19, count 0 2006.210.08:09:27.75#ibcon#about to write, iclass 19, count 0 2006.210.08:09:27.75#ibcon#wrote, iclass 19, count 0 2006.210.08:09:27.75#ibcon#about to read 3, iclass 19, count 0 2006.210.08:09:27.77#ibcon#read 3, iclass 19, count 0 2006.210.08:09:27.77#ibcon#about to read 4, iclass 19, count 0 2006.210.08:09:27.77#ibcon#read 4, iclass 19, count 0 2006.210.08:09:27.77#ibcon#about to read 5, iclass 19, count 0 2006.210.08:09:27.77#ibcon#read 5, iclass 19, count 0 2006.210.08:09:27.77#ibcon#about to read 6, iclass 19, count 0 2006.210.08:09:27.77#ibcon#read 6, iclass 19, count 0 2006.210.08:09:27.77#ibcon#end of sib2, iclass 19, count 0 2006.210.08:09:27.77#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:09:27.77#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:09:27.77#ibcon#[25=USB\r\n] 2006.210.08:09:27.77#ibcon#*before write, iclass 19, count 0 2006.210.08:09:27.77#ibcon#enter sib2, iclass 19, count 0 2006.210.08:09:27.77#ibcon#flushed, iclass 19, count 0 2006.210.08:09:27.77#ibcon#about to write, iclass 19, count 0 2006.210.08:09:27.77#ibcon#wrote, iclass 19, count 0 2006.210.08:09:27.77#ibcon#about to read 3, iclass 19, count 0 2006.210.08:09:27.80#ibcon#read 3, iclass 19, count 0 2006.210.08:09:27.80#ibcon#about to read 4, iclass 19, count 0 2006.210.08:09:27.80#ibcon#read 4, iclass 19, count 0 2006.210.08:09:27.80#ibcon#about to read 5, iclass 19, count 0 2006.210.08:09:27.80#ibcon#read 5, iclass 19, count 0 2006.210.08:09:27.80#ibcon#about to read 6, iclass 19, count 0 2006.210.08:09:27.80#ibcon#read 6, iclass 19, count 0 2006.210.08:09:27.80#ibcon#end of sib2, iclass 19, count 0 2006.210.08:09:27.80#ibcon#*after write, iclass 19, count 0 2006.210.08:09:27.80#ibcon#*before return 0, iclass 19, count 0 2006.210.08:09:27.80#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:27.80#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:27.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:09:27.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:09:27.80$vc4f8/valo=2,572.99 2006.210.08:09:27.80#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:09:27.80#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:09:27.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:27.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:27.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:27.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:27.80#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:09:27.81#ibcon#first serial, iclass 21, count 0 2006.210.08:09:27.81#ibcon#enter sib2, iclass 21, count 0 2006.210.08:09:27.81#ibcon#flushed, iclass 21, count 0 2006.210.08:09:27.81#ibcon#about to write, iclass 21, count 0 2006.210.08:09:27.81#ibcon#wrote, iclass 21, count 0 2006.210.08:09:27.81#ibcon#about to read 3, iclass 21, count 0 2006.210.08:09:27.82#ibcon#read 3, iclass 21, count 0 2006.210.08:09:27.82#ibcon#about to read 4, iclass 21, count 0 2006.210.08:09:27.82#ibcon#read 4, iclass 21, count 0 2006.210.08:09:27.82#ibcon#about to read 5, iclass 21, count 0 2006.210.08:09:27.82#ibcon#read 5, iclass 21, count 0 2006.210.08:09:27.82#ibcon#about to read 6, iclass 21, count 0 2006.210.08:09:27.82#ibcon#read 6, iclass 21, count 0 2006.210.08:09:27.82#ibcon#end of sib2, iclass 21, count 0 2006.210.08:09:27.82#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:09:27.82#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:09:27.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:09:27.82#ibcon#*before write, iclass 21, count 0 2006.210.08:09:27.82#ibcon#enter sib2, iclass 21, count 0 2006.210.08:09:27.82#ibcon#flushed, iclass 21, count 0 2006.210.08:09:27.82#ibcon#about to write, iclass 21, count 0 2006.210.08:09:27.82#ibcon#wrote, iclass 21, count 0 2006.210.08:09:27.82#ibcon#about to read 3, iclass 21, count 0 2006.210.08:09:27.86#ibcon#read 3, iclass 21, count 0 2006.210.08:09:27.86#ibcon#about to read 4, iclass 21, count 0 2006.210.08:09:27.86#ibcon#read 4, iclass 21, count 0 2006.210.08:09:27.86#ibcon#about to read 5, iclass 21, count 0 2006.210.08:09:27.86#ibcon#read 5, iclass 21, count 0 2006.210.08:09:27.86#ibcon#about to read 6, iclass 21, count 0 2006.210.08:09:27.86#ibcon#read 6, iclass 21, count 0 2006.210.08:09:27.86#ibcon#end of sib2, iclass 21, count 0 2006.210.08:09:27.86#ibcon#*after write, iclass 21, count 0 2006.210.08:09:27.86#ibcon#*before return 0, iclass 21, count 0 2006.210.08:09:27.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:27.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:27.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:09:27.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:09:27.86$vc4f8/va=2,7 2006.210.08:09:27.86#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:09:27.86#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:09:27.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:27.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:27.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:27.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:27.92#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:09:27.92#ibcon#first serial, iclass 23, count 2 2006.210.08:09:27.92#ibcon#enter sib2, iclass 23, count 2 2006.210.08:09:27.92#ibcon#flushed, iclass 23, count 2 2006.210.08:09:27.92#ibcon#about to write, iclass 23, count 2 2006.210.08:09:27.92#ibcon#wrote, iclass 23, count 2 2006.210.08:09:27.92#ibcon#about to read 3, iclass 23, count 2 2006.210.08:09:27.94#ibcon#read 3, iclass 23, count 2 2006.210.08:09:27.94#ibcon#about to read 4, iclass 23, count 2 2006.210.08:09:27.94#ibcon#read 4, iclass 23, count 2 2006.210.08:09:27.94#ibcon#about to read 5, iclass 23, count 2 2006.210.08:09:27.94#ibcon#read 5, iclass 23, count 2 2006.210.08:09:27.94#ibcon#about to read 6, iclass 23, count 2 2006.210.08:09:27.94#ibcon#read 6, iclass 23, count 2 2006.210.08:09:27.94#ibcon#end of sib2, iclass 23, count 2 2006.210.08:09:27.94#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:09:27.94#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:09:27.94#ibcon#[25=AT02-07\r\n] 2006.210.08:09:27.94#ibcon#*before write, iclass 23, count 2 2006.210.08:09:27.94#ibcon#enter sib2, iclass 23, count 2 2006.210.08:09:27.94#ibcon#flushed, iclass 23, count 2 2006.210.08:09:27.94#ibcon#about to write, iclass 23, count 2 2006.210.08:09:27.94#ibcon#wrote, iclass 23, count 2 2006.210.08:09:27.94#ibcon#about to read 3, iclass 23, count 2 2006.210.08:09:27.97#ibcon#read 3, iclass 23, count 2 2006.210.08:09:27.97#ibcon#about to read 4, iclass 23, count 2 2006.210.08:09:27.97#ibcon#read 4, iclass 23, count 2 2006.210.08:09:27.97#ibcon#about to read 5, iclass 23, count 2 2006.210.08:09:27.97#ibcon#read 5, iclass 23, count 2 2006.210.08:09:27.97#ibcon#about to read 6, iclass 23, count 2 2006.210.08:09:27.97#ibcon#read 6, iclass 23, count 2 2006.210.08:09:27.97#ibcon#end of sib2, iclass 23, count 2 2006.210.08:09:27.97#ibcon#*after write, iclass 23, count 2 2006.210.08:09:27.97#ibcon#*before return 0, iclass 23, count 2 2006.210.08:09:27.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:27.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:27.97#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:09:27.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:27.97#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:28.09#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:28.09#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:28.09#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:09:28.09#ibcon#first serial, iclass 23, count 0 2006.210.08:09:28.09#ibcon#enter sib2, iclass 23, count 0 2006.210.08:09:28.09#ibcon#flushed, iclass 23, count 0 2006.210.08:09:28.09#ibcon#about to write, iclass 23, count 0 2006.210.08:09:28.09#ibcon#wrote, iclass 23, count 0 2006.210.08:09:28.09#ibcon#about to read 3, iclass 23, count 0 2006.210.08:09:28.11#ibcon#read 3, iclass 23, count 0 2006.210.08:09:28.11#ibcon#about to read 4, iclass 23, count 0 2006.210.08:09:28.11#ibcon#read 4, iclass 23, count 0 2006.210.08:09:28.11#ibcon#about to read 5, iclass 23, count 0 2006.210.08:09:28.11#ibcon#read 5, iclass 23, count 0 2006.210.08:09:28.11#ibcon#about to read 6, iclass 23, count 0 2006.210.08:09:28.11#ibcon#read 6, iclass 23, count 0 2006.210.08:09:28.11#ibcon#end of sib2, iclass 23, count 0 2006.210.08:09:28.11#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:09:28.11#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:09:28.11#ibcon#[25=USB\r\n] 2006.210.08:09:28.11#ibcon#*before write, iclass 23, count 0 2006.210.08:09:28.11#ibcon#enter sib2, iclass 23, count 0 2006.210.08:09:28.11#ibcon#flushed, iclass 23, count 0 2006.210.08:09:28.11#ibcon#about to write, iclass 23, count 0 2006.210.08:09:28.11#ibcon#wrote, iclass 23, count 0 2006.210.08:09:28.11#ibcon#about to read 3, iclass 23, count 0 2006.210.08:09:28.14#ibcon#read 3, iclass 23, count 0 2006.210.08:09:28.14#ibcon#about to read 4, iclass 23, count 0 2006.210.08:09:28.14#ibcon#read 4, iclass 23, count 0 2006.210.08:09:28.14#ibcon#about to read 5, iclass 23, count 0 2006.210.08:09:28.14#ibcon#read 5, iclass 23, count 0 2006.210.08:09:28.14#ibcon#about to read 6, iclass 23, count 0 2006.210.08:09:28.14#ibcon#read 6, iclass 23, count 0 2006.210.08:09:28.14#ibcon#end of sib2, iclass 23, count 0 2006.210.08:09:28.14#ibcon#*after write, iclass 23, count 0 2006.210.08:09:28.14#ibcon#*before return 0, iclass 23, count 0 2006.210.08:09:28.14#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:28.14#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:28.14#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:09:28.14#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:09:28.14$vc4f8/valo=3,672.99 2006.210.08:09:28.14#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:09:28.14#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:09:28.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:28.14#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:28.14#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:28.14#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:28.14#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:09:28.14#ibcon#first serial, iclass 25, count 0 2006.210.08:09:28.14#ibcon#enter sib2, iclass 25, count 0 2006.210.08:09:28.15#ibcon#flushed, iclass 25, count 0 2006.210.08:09:28.15#ibcon#about to write, iclass 25, count 0 2006.210.08:09:28.15#ibcon#wrote, iclass 25, count 0 2006.210.08:09:28.15#ibcon#about to read 3, iclass 25, count 0 2006.210.08:09:28.16#ibcon#read 3, iclass 25, count 0 2006.210.08:09:28.16#ibcon#about to read 4, iclass 25, count 0 2006.210.08:09:28.16#ibcon#read 4, iclass 25, count 0 2006.210.08:09:28.16#ibcon#about to read 5, iclass 25, count 0 2006.210.08:09:28.16#ibcon#read 5, iclass 25, count 0 2006.210.08:09:28.16#ibcon#about to read 6, iclass 25, count 0 2006.210.08:09:28.16#ibcon#read 6, iclass 25, count 0 2006.210.08:09:28.16#ibcon#end of sib2, iclass 25, count 0 2006.210.08:09:28.16#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:09:28.16#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:09:28.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:09:28.16#ibcon#*before write, iclass 25, count 0 2006.210.08:09:28.16#ibcon#enter sib2, iclass 25, count 0 2006.210.08:09:28.16#ibcon#flushed, iclass 25, count 0 2006.210.08:09:28.16#ibcon#about to write, iclass 25, count 0 2006.210.08:09:28.16#ibcon#wrote, iclass 25, count 0 2006.210.08:09:28.16#ibcon#about to read 3, iclass 25, count 0 2006.210.08:09:28.20#ibcon#read 3, iclass 25, count 0 2006.210.08:09:28.20#ibcon#about to read 4, iclass 25, count 0 2006.210.08:09:28.20#ibcon#read 4, iclass 25, count 0 2006.210.08:09:28.20#ibcon#about to read 5, iclass 25, count 0 2006.210.08:09:28.20#ibcon#read 5, iclass 25, count 0 2006.210.08:09:28.20#ibcon#about to read 6, iclass 25, count 0 2006.210.08:09:28.20#ibcon#read 6, iclass 25, count 0 2006.210.08:09:28.20#ibcon#end of sib2, iclass 25, count 0 2006.210.08:09:28.20#ibcon#*after write, iclass 25, count 0 2006.210.08:09:28.20#ibcon#*before return 0, iclass 25, count 0 2006.210.08:09:28.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:28.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:28.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:09:28.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:09:28.20$vc4f8/va=3,6 2006.210.08:09:28.20#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.08:09:28.20#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.08:09:28.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:28.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:09:28.23#abcon#<5=/06 3.7 6.0 30.19 821006.4\r\n> 2006.210.08:09:28.25#abcon#{5=INTERFACE CLEAR} 2006.210.08:09:28.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:09:28.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:09:28.26#ibcon#enter wrdev, iclass 28, count 2 2006.210.08:09:28.26#ibcon#first serial, iclass 28, count 2 2006.210.08:09:28.26#ibcon#enter sib2, iclass 28, count 2 2006.210.08:09:28.26#ibcon#flushed, iclass 28, count 2 2006.210.08:09:28.26#ibcon#about to write, iclass 28, count 2 2006.210.08:09:28.26#ibcon#wrote, iclass 28, count 2 2006.210.08:09:28.26#ibcon#about to read 3, iclass 28, count 2 2006.210.08:09:28.28#ibcon#read 3, iclass 28, count 2 2006.210.08:09:28.28#ibcon#about to read 4, iclass 28, count 2 2006.210.08:09:28.28#ibcon#read 4, iclass 28, count 2 2006.210.08:09:28.28#ibcon#about to read 5, iclass 28, count 2 2006.210.08:09:28.28#ibcon#read 5, iclass 28, count 2 2006.210.08:09:28.28#ibcon#about to read 6, iclass 28, count 2 2006.210.08:09:28.28#ibcon#read 6, iclass 28, count 2 2006.210.08:09:28.28#ibcon#end of sib2, iclass 28, count 2 2006.210.08:09:28.28#ibcon#*mode == 0, iclass 28, count 2 2006.210.08:09:28.28#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.08:09:28.28#ibcon#[25=AT03-06\r\n] 2006.210.08:09:28.28#ibcon#*before write, iclass 28, count 2 2006.210.08:09:28.28#ibcon#enter sib2, iclass 28, count 2 2006.210.08:09:28.28#ibcon#flushed, iclass 28, count 2 2006.210.08:09:28.28#ibcon#about to write, iclass 28, count 2 2006.210.08:09:28.28#ibcon#wrote, iclass 28, count 2 2006.210.08:09:28.28#ibcon#about to read 3, iclass 28, count 2 2006.210.08:09:28.31#abcon#[5=S1D000X0/0*\r\n] 2006.210.08:09:28.31#ibcon#read 3, iclass 28, count 2 2006.210.08:09:28.31#ibcon#about to read 4, iclass 28, count 2 2006.210.08:09:28.31#ibcon#read 4, iclass 28, count 2 2006.210.08:09:28.31#ibcon#about to read 5, iclass 28, count 2 2006.210.08:09:28.31#ibcon#read 5, iclass 28, count 2 2006.210.08:09:28.31#ibcon#about to read 6, iclass 28, count 2 2006.210.08:09:28.31#ibcon#read 6, iclass 28, count 2 2006.210.08:09:28.31#ibcon#end of sib2, iclass 28, count 2 2006.210.08:09:28.31#ibcon#*after write, iclass 28, count 2 2006.210.08:09:28.31#ibcon#*before return 0, iclass 28, count 2 2006.210.08:09:28.31#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:09:28.31#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:09:28.31#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.08:09:28.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:28.31#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:09:28.43#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:09:28.43#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:09:28.43#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:09:28.43#ibcon#first serial, iclass 28, count 0 2006.210.08:09:28.43#ibcon#enter sib2, iclass 28, count 0 2006.210.08:09:28.43#ibcon#flushed, iclass 28, count 0 2006.210.08:09:28.43#ibcon#about to write, iclass 28, count 0 2006.210.08:09:28.43#ibcon#wrote, iclass 28, count 0 2006.210.08:09:28.43#ibcon#about to read 3, iclass 28, count 0 2006.210.08:09:28.45#ibcon#read 3, iclass 28, count 0 2006.210.08:09:28.45#ibcon#about to read 4, iclass 28, count 0 2006.210.08:09:28.45#ibcon#read 4, iclass 28, count 0 2006.210.08:09:28.45#ibcon#about to read 5, iclass 28, count 0 2006.210.08:09:28.45#ibcon#read 5, iclass 28, count 0 2006.210.08:09:28.45#ibcon#about to read 6, iclass 28, count 0 2006.210.08:09:28.45#ibcon#read 6, iclass 28, count 0 2006.210.08:09:28.45#ibcon#end of sib2, iclass 28, count 0 2006.210.08:09:28.45#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:09:28.45#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:09:28.45#ibcon#[25=USB\r\n] 2006.210.08:09:28.45#ibcon#*before write, iclass 28, count 0 2006.210.08:09:28.45#ibcon#enter sib2, iclass 28, count 0 2006.210.08:09:28.45#ibcon#flushed, iclass 28, count 0 2006.210.08:09:28.45#ibcon#about to write, iclass 28, count 0 2006.210.08:09:28.45#ibcon#wrote, iclass 28, count 0 2006.210.08:09:28.45#ibcon#about to read 3, iclass 28, count 0 2006.210.08:09:28.48#ibcon#read 3, iclass 28, count 0 2006.210.08:09:28.48#ibcon#about to read 4, iclass 28, count 0 2006.210.08:09:28.48#ibcon#read 4, iclass 28, count 0 2006.210.08:09:28.48#ibcon#about to read 5, iclass 28, count 0 2006.210.08:09:28.48#ibcon#read 5, iclass 28, count 0 2006.210.08:09:28.48#ibcon#about to read 6, iclass 28, count 0 2006.210.08:09:28.48#ibcon#read 6, iclass 28, count 0 2006.210.08:09:28.48#ibcon#end of sib2, iclass 28, count 0 2006.210.08:09:28.48#ibcon#*after write, iclass 28, count 0 2006.210.08:09:28.48#ibcon#*before return 0, iclass 28, count 0 2006.210.08:09:28.48#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:09:28.48#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:09:28.48#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:09:28.48#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:09:28.48$vc4f8/valo=4,832.99 2006.210.08:09:28.48#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:09:28.48#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:09:28.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:28.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:28.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:28.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:28.48#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:09:28.49#ibcon#first serial, iclass 33, count 0 2006.210.08:09:28.49#ibcon#enter sib2, iclass 33, count 0 2006.210.08:09:28.49#ibcon#flushed, iclass 33, count 0 2006.210.08:09:28.49#ibcon#about to write, iclass 33, count 0 2006.210.08:09:28.49#ibcon#wrote, iclass 33, count 0 2006.210.08:09:28.49#ibcon#about to read 3, iclass 33, count 0 2006.210.08:09:28.50#ibcon#read 3, iclass 33, count 0 2006.210.08:09:28.50#ibcon#about to read 4, iclass 33, count 0 2006.210.08:09:28.50#ibcon#read 4, iclass 33, count 0 2006.210.08:09:28.50#ibcon#about to read 5, iclass 33, count 0 2006.210.08:09:28.50#ibcon#read 5, iclass 33, count 0 2006.210.08:09:28.50#ibcon#about to read 6, iclass 33, count 0 2006.210.08:09:28.50#ibcon#read 6, iclass 33, count 0 2006.210.08:09:28.50#ibcon#end of sib2, iclass 33, count 0 2006.210.08:09:28.50#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:09:28.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:09:28.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:09:28.50#ibcon#*before write, iclass 33, count 0 2006.210.08:09:28.50#ibcon#enter sib2, iclass 33, count 0 2006.210.08:09:28.50#ibcon#flushed, iclass 33, count 0 2006.210.08:09:28.50#ibcon#about to write, iclass 33, count 0 2006.210.08:09:28.50#ibcon#wrote, iclass 33, count 0 2006.210.08:09:28.50#ibcon#about to read 3, iclass 33, count 0 2006.210.08:09:28.54#ibcon#read 3, iclass 33, count 0 2006.210.08:09:28.54#ibcon#about to read 4, iclass 33, count 0 2006.210.08:09:28.54#ibcon#read 4, iclass 33, count 0 2006.210.08:09:28.54#ibcon#about to read 5, iclass 33, count 0 2006.210.08:09:28.54#ibcon#read 5, iclass 33, count 0 2006.210.08:09:28.54#ibcon#about to read 6, iclass 33, count 0 2006.210.08:09:28.54#ibcon#read 6, iclass 33, count 0 2006.210.08:09:28.54#ibcon#end of sib2, iclass 33, count 0 2006.210.08:09:28.54#ibcon#*after write, iclass 33, count 0 2006.210.08:09:28.54#ibcon#*before return 0, iclass 33, count 0 2006.210.08:09:28.54#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:28.54#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:28.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:09:28.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:09:28.54$vc4f8/va=4,7 2006.210.08:09:28.54#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:09:28.54#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:09:28.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:28.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:28.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:28.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:28.60#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:09:28.60#ibcon#first serial, iclass 35, count 2 2006.210.08:09:28.60#ibcon#enter sib2, iclass 35, count 2 2006.210.08:09:28.60#ibcon#flushed, iclass 35, count 2 2006.210.08:09:28.60#ibcon#about to write, iclass 35, count 2 2006.210.08:09:28.60#ibcon#wrote, iclass 35, count 2 2006.210.08:09:28.60#ibcon#about to read 3, iclass 35, count 2 2006.210.08:09:28.62#ibcon#read 3, iclass 35, count 2 2006.210.08:09:28.62#ibcon#about to read 4, iclass 35, count 2 2006.210.08:09:28.62#ibcon#read 4, iclass 35, count 2 2006.210.08:09:28.62#ibcon#about to read 5, iclass 35, count 2 2006.210.08:09:28.62#ibcon#read 5, iclass 35, count 2 2006.210.08:09:28.62#ibcon#about to read 6, iclass 35, count 2 2006.210.08:09:28.62#ibcon#read 6, iclass 35, count 2 2006.210.08:09:28.62#ibcon#end of sib2, iclass 35, count 2 2006.210.08:09:28.62#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:09:28.62#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:09:28.62#ibcon#[25=AT04-07\r\n] 2006.210.08:09:28.62#ibcon#*before write, iclass 35, count 2 2006.210.08:09:28.62#ibcon#enter sib2, iclass 35, count 2 2006.210.08:09:28.62#ibcon#flushed, iclass 35, count 2 2006.210.08:09:28.62#ibcon#about to write, iclass 35, count 2 2006.210.08:09:28.62#ibcon#wrote, iclass 35, count 2 2006.210.08:09:28.62#ibcon#about to read 3, iclass 35, count 2 2006.210.08:09:28.65#ibcon#read 3, iclass 35, count 2 2006.210.08:09:28.65#ibcon#about to read 4, iclass 35, count 2 2006.210.08:09:28.65#ibcon#read 4, iclass 35, count 2 2006.210.08:09:28.65#ibcon#about to read 5, iclass 35, count 2 2006.210.08:09:28.65#ibcon#read 5, iclass 35, count 2 2006.210.08:09:28.65#ibcon#about to read 6, iclass 35, count 2 2006.210.08:09:28.65#ibcon#read 6, iclass 35, count 2 2006.210.08:09:28.65#ibcon#end of sib2, iclass 35, count 2 2006.210.08:09:28.65#ibcon#*after write, iclass 35, count 2 2006.210.08:09:28.65#ibcon#*before return 0, iclass 35, count 2 2006.210.08:09:28.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:28.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:28.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:09:28.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:28.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:28.77#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:28.77#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:28.77#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:09:28.77#ibcon#first serial, iclass 35, count 0 2006.210.08:09:28.77#ibcon#enter sib2, iclass 35, count 0 2006.210.08:09:28.77#ibcon#flushed, iclass 35, count 0 2006.210.08:09:28.77#ibcon#about to write, iclass 35, count 0 2006.210.08:09:28.77#ibcon#wrote, iclass 35, count 0 2006.210.08:09:28.77#ibcon#about to read 3, iclass 35, count 0 2006.210.08:09:28.79#ibcon#read 3, iclass 35, count 0 2006.210.08:09:28.79#ibcon#about to read 4, iclass 35, count 0 2006.210.08:09:28.79#ibcon#read 4, iclass 35, count 0 2006.210.08:09:28.79#ibcon#about to read 5, iclass 35, count 0 2006.210.08:09:28.79#ibcon#read 5, iclass 35, count 0 2006.210.08:09:28.79#ibcon#about to read 6, iclass 35, count 0 2006.210.08:09:28.79#ibcon#read 6, iclass 35, count 0 2006.210.08:09:28.79#ibcon#end of sib2, iclass 35, count 0 2006.210.08:09:28.79#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:09:28.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:09:28.79#ibcon#[25=USB\r\n] 2006.210.08:09:28.79#ibcon#*before write, iclass 35, count 0 2006.210.08:09:28.79#ibcon#enter sib2, iclass 35, count 0 2006.210.08:09:28.79#ibcon#flushed, iclass 35, count 0 2006.210.08:09:28.79#ibcon#about to write, iclass 35, count 0 2006.210.08:09:28.79#ibcon#wrote, iclass 35, count 0 2006.210.08:09:28.79#ibcon#about to read 3, iclass 35, count 0 2006.210.08:09:28.82#ibcon#read 3, iclass 35, count 0 2006.210.08:09:28.82#ibcon#about to read 4, iclass 35, count 0 2006.210.08:09:28.82#ibcon#read 4, iclass 35, count 0 2006.210.08:09:28.82#ibcon#about to read 5, iclass 35, count 0 2006.210.08:09:28.82#ibcon#read 5, iclass 35, count 0 2006.210.08:09:28.82#ibcon#about to read 6, iclass 35, count 0 2006.210.08:09:28.82#ibcon#read 6, iclass 35, count 0 2006.210.08:09:28.82#ibcon#end of sib2, iclass 35, count 0 2006.210.08:09:28.82#ibcon#*after write, iclass 35, count 0 2006.210.08:09:28.82#ibcon#*before return 0, iclass 35, count 0 2006.210.08:09:28.82#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:28.82#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:28.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:09:28.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:09:28.82$vc4f8/valo=5,652.99 2006.210.08:09:28.82#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:09:28.82#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:09:28.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:28.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:28.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:28.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:28.82#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:09:28.83#ibcon#first serial, iclass 37, count 0 2006.210.08:09:28.83#ibcon#enter sib2, iclass 37, count 0 2006.210.08:09:28.83#ibcon#flushed, iclass 37, count 0 2006.210.08:09:28.83#ibcon#about to write, iclass 37, count 0 2006.210.08:09:28.83#ibcon#wrote, iclass 37, count 0 2006.210.08:09:28.83#ibcon#about to read 3, iclass 37, count 0 2006.210.08:09:28.84#ibcon#read 3, iclass 37, count 0 2006.210.08:09:28.84#ibcon#about to read 4, iclass 37, count 0 2006.210.08:09:28.84#ibcon#read 4, iclass 37, count 0 2006.210.08:09:28.84#ibcon#about to read 5, iclass 37, count 0 2006.210.08:09:28.84#ibcon#read 5, iclass 37, count 0 2006.210.08:09:28.84#ibcon#about to read 6, iclass 37, count 0 2006.210.08:09:28.84#ibcon#read 6, iclass 37, count 0 2006.210.08:09:28.84#ibcon#end of sib2, iclass 37, count 0 2006.210.08:09:28.84#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:09:28.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:09:28.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:09:28.84#ibcon#*before write, iclass 37, count 0 2006.210.08:09:28.84#ibcon#enter sib2, iclass 37, count 0 2006.210.08:09:28.84#ibcon#flushed, iclass 37, count 0 2006.210.08:09:28.84#ibcon#about to write, iclass 37, count 0 2006.210.08:09:28.84#ibcon#wrote, iclass 37, count 0 2006.210.08:09:28.84#ibcon#about to read 3, iclass 37, count 0 2006.210.08:09:28.88#ibcon#read 3, iclass 37, count 0 2006.210.08:09:28.88#ibcon#about to read 4, iclass 37, count 0 2006.210.08:09:28.88#ibcon#read 4, iclass 37, count 0 2006.210.08:09:28.88#ibcon#about to read 5, iclass 37, count 0 2006.210.08:09:28.88#ibcon#read 5, iclass 37, count 0 2006.210.08:09:28.88#ibcon#about to read 6, iclass 37, count 0 2006.210.08:09:28.88#ibcon#read 6, iclass 37, count 0 2006.210.08:09:28.88#ibcon#end of sib2, iclass 37, count 0 2006.210.08:09:28.88#ibcon#*after write, iclass 37, count 0 2006.210.08:09:28.88#ibcon#*before return 0, iclass 37, count 0 2006.210.08:09:28.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:28.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:28.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:09:28.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:09:28.88$vc4f8/va=5,7 2006.210.08:09:28.88#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:09:28.88#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:09:28.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:28.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:28.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:28.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:28.94#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:09:28.94#ibcon#first serial, iclass 39, count 2 2006.210.08:09:28.94#ibcon#enter sib2, iclass 39, count 2 2006.210.08:09:28.94#ibcon#flushed, iclass 39, count 2 2006.210.08:09:28.94#ibcon#about to write, iclass 39, count 2 2006.210.08:09:28.94#ibcon#wrote, iclass 39, count 2 2006.210.08:09:28.94#ibcon#about to read 3, iclass 39, count 2 2006.210.08:09:28.96#ibcon#read 3, iclass 39, count 2 2006.210.08:09:28.96#ibcon#about to read 4, iclass 39, count 2 2006.210.08:09:28.96#ibcon#read 4, iclass 39, count 2 2006.210.08:09:28.96#ibcon#about to read 5, iclass 39, count 2 2006.210.08:09:28.96#ibcon#read 5, iclass 39, count 2 2006.210.08:09:28.96#ibcon#about to read 6, iclass 39, count 2 2006.210.08:09:28.96#ibcon#read 6, iclass 39, count 2 2006.210.08:09:28.96#ibcon#end of sib2, iclass 39, count 2 2006.210.08:09:28.96#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:09:28.96#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:09:28.96#ibcon#[25=AT05-07\r\n] 2006.210.08:09:28.96#ibcon#*before write, iclass 39, count 2 2006.210.08:09:28.96#ibcon#enter sib2, iclass 39, count 2 2006.210.08:09:28.96#ibcon#flushed, iclass 39, count 2 2006.210.08:09:28.96#ibcon#about to write, iclass 39, count 2 2006.210.08:09:28.96#ibcon#wrote, iclass 39, count 2 2006.210.08:09:28.96#ibcon#about to read 3, iclass 39, count 2 2006.210.08:09:28.99#ibcon#read 3, iclass 39, count 2 2006.210.08:09:28.99#ibcon#about to read 4, iclass 39, count 2 2006.210.08:09:28.99#ibcon#read 4, iclass 39, count 2 2006.210.08:09:28.99#ibcon#about to read 5, iclass 39, count 2 2006.210.08:09:28.99#ibcon#read 5, iclass 39, count 2 2006.210.08:09:28.99#ibcon#about to read 6, iclass 39, count 2 2006.210.08:09:28.99#ibcon#read 6, iclass 39, count 2 2006.210.08:09:28.99#ibcon#end of sib2, iclass 39, count 2 2006.210.08:09:28.99#ibcon#*after write, iclass 39, count 2 2006.210.08:09:28.99#ibcon#*before return 0, iclass 39, count 2 2006.210.08:09:28.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:28.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:28.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:09:28.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:28.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:29.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:29.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:29.11#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:09:29.11#ibcon#first serial, iclass 39, count 0 2006.210.08:09:29.11#ibcon#enter sib2, iclass 39, count 0 2006.210.08:09:29.11#ibcon#flushed, iclass 39, count 0 2006.210.08:09:29.11#ibcon#about to write, iclass 39, count 0 2006.210.08:09:29.11#ibcon#wrote, iclass 39, count 0 2006.210.08:09:29.11#ibcon#about to read 3, iclass 39, count 0 2006.210.08:09:29.13#ibcon#read 3, iclass 39, count 0 2006.210.08:09:29.13#ibcon#about to read 4, iclass 39, count 0 2006.210.08:09:29.13#ibcon#read 4, iclass 39, count 0 2006.210.08:09:29.13#ibcon#about to read 5, iclass 39, count 0 2006.210.08:09:29.13#ibcon#read 5, iclass 39, count 0 2006.210.08:09:29.13#ibcon#about to read 6, iclass 39, count 0 2006.210.08:09:29.13#ibcon#read 6, iclass 39, count 0 2006.210.08:09:29.13#ibcon#end of sib2, iclass 39, count 0 2006.210.08:09:29.13#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:09:29.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:09:29.13#ibcon#[25=USB\r\n] 2006.210.08:09:29.13#ibcon#*before write, iclass 39, count 0 2006.210.08:09:29.13#ibcon#enter sib2, iclass 39, count 0 2006.210.08:09:29.13#ibcon#flushed, iclass 39, count 0 2006.210.08:09:29.13#ibcon#about to write, iclass 39, count 0 2006.210.08:09:29.13#ibcon#wrote, iclass 39, count 0 2006.210.08:09:29.13#ibcon#about to read 3, iclass 39, count 0 2006.210.08:09:29.16#ibcon#read 3, iclass 39, count 0 2006.210.08:09:29.16#ibcon#about to read 4, iclass 39, count 0 2006.210.08:09:29.16#ibcon#read 4, iclass 39, count 0 2006.210.08:09:29.16#ibcon#about to read 5, iclass 39, count 0 2006.210.08:09:29.16#ibcon#read 5, iclass 39, count 0 2006.210.08:09:29.16#ibcon#about to read 6, iclass 39, count 0 2006.210.08:09:29.16#ibcon#read 6, iclass 39, count 0 2006.210.08:09:29.16#ibcon#end of sib2, iclass 39, count 0 2006.210.08:09:29.16#ibcon#*after write, iclass 39, count 0 2006.210.08:09:29.16#ibcon#*before return 0, iclass 39, count 0 2006.210.08:09:29.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:29.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:29.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:09:29.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:09:29.16$vc4f8/valo=6,772.99 2006.210.08:09:29.16#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:09:29.16#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:09:29.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:29.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:29.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:29.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:29.17#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:09:29.17#ibcon#first serial, iclass 3, count 0 2006.210.08:09:29.17#ibcon#enter sib2, iclass 3, count 0 2006.210.08:09:29.17#ibcon#flushed, iclass 3, count 0 2006.210.08:09:29.17#ibcon#about to write, iclass 3, count 0 2006.210.08:09:29.17#ibcon#wrote, iclass 3, count 0 2006.210.08:09:29.17#ibcon#about to read 3, iclass 3, count 0 2006.210.08:09:29.18#ibcon#read 3, iclass 3, count 0 2006.210.08:09:29.18#ibcon#about to read 4, iclass 3, count 0 2006.210.08:09:29.18#ibcon#read 4, iclass 3, count 0 2006.210.08:09:29.18#ibcon#about to read 5, iclass 3, count 0 2006.210.08:09:29.18#ibcon#read 5, iclass 3, count 0 2006.210.08:09:29.18#ibcon#about to read 6, iclass 3, count 0 2006.210.08:09:29.18#ibcon#read 6, iclass 3, count 0 2006.210.08:09:29.18#ibcon#end of sib2, iclass 3, count 0 2006.210.08:09:29.18#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:09:29.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:09:29.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:09:29.18#ibcon#*before write, iclass 3, count 0 2006.210.08:09:29.18#ibcon#enter sib2, iclass 3, count 0 2006.210.08:09:29.18#ibcon#flushed, iclass 3, count 0 2006.210.08:09:29.18#ibcon#about to write, iclass 3, count 0 2006.210.08:09:29.18#ibcon#wrote, iclass 3, count 0 2006.210.08:09:29.18#ibcon#about to read 3, iclass 3, count 0 2006.210.08:09:29.22#ibcon#read 3, iclass 3, count 0 2006.210.08:09:29.22#ibcon#about to read 4, iclass 3, count 0 2006.210.08:09:29.22#ibcon#read 4, iclass 3, count 0 2006.210.08:09:29.22#ibcon#about to read 5, iclass 3, count 0 2006.210.08:09:29.22#ibcon#read 5, iclass 3, count 0 2006.210.08:09:29.22#ibcon#about to read 6, iclass 3, count 0 2006.210.08:09:29.22#ibcon#read 6, iclass 3, count 0 2006.210.08:09:29.22#ibcon#end of sib2, iclass 3, count 0 2006.210.08:09:29.22#ibcon#*after write, iclass 3, count 0 2006.210.08:09:29.22#ibcon#*before return 0, iclass 3, count 0 2006.210.08:09:29.22#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:29.22#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:29.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:09:29.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:09:29.22$vc4f8/va=6,6 2006.210.08:09:29.22#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:09:29.22#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:09:29.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:29.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:09:29.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:09:29.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:09:29.28#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:09:29.28#ibcon#first serial, iclass 5, count 2 2006.210.08:09:29.28#ibcon#enter sib2, iclass 5, count 2 2006.210.08:09:29.28#ibcon#flushed, iclass 5, count 2 2006.210.08:09:29.28#ibcon#about to write, iclass 5, count 2 2006.210.08:09:29.28#ibcon#wrote, iclass 5, count 2 2006.210.08:09:29.28#ibcon#about to read 3, iclass 5, count 2 2006.210.08:09:29.30#ibcon#read 3, iclass 5, count 2 2006.210.08:09:29.30#ibcon#about to read 4, iclass 5, count 2 2006.210.08:09:29.30#ibcon#read 4, iclass 5, count 2 2006.210.08:09:29.30#ibcon#about to read 5, iclass 5, count 2 2006.210.08:09:29.30#ibcon#read 5, iclass 5, count 2 2006.210.08:09:29.30#ibcon#about to read 6, iclass 5, count 2 2006.210.08:09:29.30#ibcon#read 6, iclass 5, count 2 2006.210.08:09:29.30#ibcon#end of sib2, iclass 5, count 2 2006.210.08:09:29.30#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:09:29.30#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:09:29.30#ibcon#[25=AT06-06\r\n] 2006.210.08:09:29.30#ibcon#*before write, iclass 5, count 2 2006.210.08:09:29.30#ibcon#enter sib2, iclass 5, count 2 2006.210.08:09:29.30#ibcon#flushed, iclass 5, count 2 2006.210.08:09:29.30#ibcon#about to write, iclass 5, count 2 2006.210.08:09:29.30#ibcon#wrote, iclass 5, count 2 2006.210.08:09:29.30#ibcon#about to read 3, iclass 5, count 2 2006.210.08:09:29.33#ibcon#read 3, iclass 5, count 2 2006.210.08:09:29.33#ibcon#about to read 4, iclass 5, count 2 2006.210.08:09:29.33#ibcon#read 4, iclass 5, count 2 2006.210.08:09:29.33#ibcon#about to read 5, iclass 5, count 2 2006.210.08:09:29.33#ibcon#read 5, iclass 5, count 2 2006.210.08:09:29.33#ibcon#about to read 6, iclass 5, count 2 2006.210.08:09:29.33#ibcon#read 6, iclass 5, count 2 2006.210.08:09:29.33#ibcon#end of sib2, iclass 5, count 2 2006.210.08:09:29.33#ibcon#*after write, iclass 5, count 2 2006.210.08:09:29.33#ibcon#*before return 0, iclass 5, count 2 2006.210.08:09:29.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:09:29.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:09:29.33#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:09:29.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:29.33#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:09:29.45#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:09:29.45#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:09:29.45#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:09:29.45#ibcon#first serial, iclass 5, count 0 2006.210.08:09:29.45#ibcon#enter sib2, iclass 5, count 0 2006.210.08:09:29.45#ibcon#flushed, iclass 5, count 0 2006.210.08:09:29.45#ibcon#about to write, iclass 5, count 0 2006.210.08:09:29.45#ibcon#wrote, iclass 5, count 0 2006.210.08:09:29.45#ibcon#about to read 3, iclass 5, count 0 2006.210.08:09:29.47#ibcon#read 3, iclass 5, count 0 2006.210.08:09:29.47#ibcon#about to read 4, iclass 5, count 0 2006.210.08:09:29.47#ibcon#read 4, iclass 5, count 0 2006.210.08:09:29.47#ibcon#about to read 5, iclass 5, count 0 2006.210.08:09:29.47#ibcon#read 5, iclass 5, count 0 2006.210.08:09:29.47#ibcon#about to read 6, iclass 5, count 0 2006.210.08:09:29.47#ibcon#read 6, iclass 5, count 0 2006.210.08:09:29.47#ibcon#end of sib2, iclass 5, count 0 2006.210.08:09:29.47#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:09:29.47#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:09:29.47#ibcon#[25=USB\r\n] 2006.210.08:09:29.47#ibcon#*before write, iclass 5, count 0 2006.210.08:09:29.47#ibcon#enter sib2, iclass 5, count 0 2006.210.08:09:29.47#ibcon#flushed, iclass 5, count 0 2006.210.08:09:29.47#ibcon#about to write, iclass 5, count 0 2006.210.08:09:29.47#ibcon#wrote, iclass 5, count 0 2006.210.08:09:29.47#ibcon#about to read 3, iclass 5, count 0 2006.210.08:09:29.50#ibcon#read 3, iclass 5, count 0 2006.210.08:09:29.50#ibcon#about to read 4, iclass 5, count 0 2006.210.08:09:29.50#ibcon#read 4, iclass 5, count 0 2006.210.08:09:29.50#ibcon#about to read 5, iclass 5, count 0 2006.210.08:09:29.50#ibcon#read 5, iclass 5, count 0 2006.210.08:09:29.50#ibcon#about to read 6, iclass 5, count 0 2006.210.08:09:29.50#ibcon#read 6, iclass 5, count 0 2006.210.08:09:29.50#ibcon#end of sib2, iclass 5, count 0 2006.210.08:09:29.50#ibcon#*after write, iclass 5, count 0 2006.210.08:09:29.50#ibcon#*before return 0, iclass 5, count 0 2006.210.08:09:29.50#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:09:29.50#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:09:29.50#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:09:29.50#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:09:29.50$vc4f8/valo=7,832.99 2006.210.08:09:29.50#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:09:29.50#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:09:29.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:29.50#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:09:29.50#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:09:29.50#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:09:29.50#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:09:29.51#ibcon#first serial, iclass 7, count 0 2006.210.08:09:29.51#ibcon#enter sib2, iclass 7, count 0 2006.210.08:09:29.51#ibcon#flushed, iclass 7, count 0 2006.210.08:09:29.51#ibcon#about to write, iclass 7, count 0 2006.210.08:09:29.51#ibcon#wrote, iclass 7, count 0 2006.210.08:09:29.51#ibcon#about to read 3, iclass 7, count 0 2006.210.08:09:29.52#ibcon#read 3, iclass 7, count 0 2006.210.08:09:29.52#ibcon#about to read 4, iclass 7, count 0 2006.210.08:09:29.52#ibcon#read 4, iclass 7, count 0 2006.210.08:09:29.52#ibcon#about to read 5, iclass 7, count 0 2006.210.08:09:29.52#ibcon#read 5, iclass 7, count 0 2006.210.08:09:29.52#ibcon#about to read 6, iclass 7, count 0 2006.210.08:09:29.52#ibcon#read 6, iclass 7, count 0 2006.210.08:09:29.52#ibcon#end of sib2, iclass 7, count 0 2006.210.08:09:29.52#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:09:29.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:09:29.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:09:29.52#ibcon#*before write, iclass 7, count 0 2006.210.08:09:29.52#ibcon#enter sib2, iclass 7, count 0 2006.210.08:09:29.52#ibcon#flushed, iclass 7, count 0 2006.210.08:09:29.52#ibcon#about to write, iclass 7, count 0 2006.210.08:09:29.52#ibcon#wrote, iclass 7, count 0 2006.210.08:09:29.52#ibcon#about to read 3, iclass 7, count 0 2006.210.08:09:29.56#ibcon#read 3, iclass 7, count 0 2006.210.08:09:29.56#ibcon#about to read 4, iclass 7, count 0 2006.210.08:09:29.56#ibcon#read 4, iclass 7, count 0 2006.210.08:09:29.56#ibcon#about to read 5, iclass 7, count 0 2006.210.08:09:29.56#ibcon#read 5, iclass 7, count 0 2006.210.08:09:29.56#ibcon#about to read 6, iclass 7, count 0 2006.210.08:09:29.56#ibcon#read 6, iclass 7, count 0 2006.210.08:09:29.56#ibcon#end of sib2, iclass 7, count 0 2006.210.08:09:29.56#ibcon#*after write, iclass 7, count 0 2006.210.08:09:29.56#ibcon#*before return 0, iclass 7, count 0 2006.210.08:09:29.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:09:29.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:09:29.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:09:29.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:09:29.56$vc4f8/va=7,6 2006.210.08:09:29.56#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:09:29.56#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:09:29.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:29.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:09:29.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:09:29.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:09:29.62#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:09:29.62#ibcon#first serial, iclass 11, count 2 2006.210.08:09:29.62#ibcon#enter sib2, iclass 11, count 2 2006.210.08:09:29.62#ibcon#flushed, iclass 11, count 2 2006.210.08:09:29.62#ibcon#about to write, iclass 11, count 2 2006.210.08:09:29.62#ibcon#wrote, iclass 11, count 2 2006.210.08:09:29.62#ibcon#about to read 3, iclass 11, count 2 2006.210.08:09:29.64#ibcon#read 3, iclass 11, count 2 2006.210.08:09:29.64#ibcon#about to read 4, iclass 11, count 2 2006.210.08:09:29.64#ibcon#read 4, iclass 11, count 2 2006.210.08:09:29.64#ibcon#about to read 5, iclass 11, count 2 2006.210.08:09:29.64#ibcon#read 5, iclass 11, count 2 2006.210.08:09:29.64#ibcon#about to read 6, iclass 11, count 2 2006.210.08:09:29.64#ibcon#read 6, iclass 11, count 2 2006.210.08:09:29.64#ibcon#end of sib2, iclass 11, count 2 2006.210.08:09:29.64#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:09:29.64#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:09:29.64#ibcon#[25=AT07-06\r\n] 2006.210.08:09:29.64#ibcon#*before write, iclass 11, count 2 2006.210.08:09:29.64#ibcon#enter sib2, iclass 11, count 2 2006.210.08:09:29.64#ibcon#flushed, iclass 11, count 2 2006.210.08:09:29.64#ibcon#about to write, iclass 11, count 2 2006.210.08:09:29.64#ibcon#wrote, iclass 11, count 2 2006.210.08:09:29.64#ibcon#about to read 3, iclass 11, count 2 2006.210.08:09:29.67#ibcon#read 3, iclass 11, count 2 2006.210.08:09:29.67#ibcon#about to read 4, iclass 11, count 2 2006.210.08:09:29.67#ibcon#read 4, iclass 11, count 2 2006.210.08:09:29.67#ibcon#about to read 5, iclass 11, count 2 2006.210.08:09:29.67#ibcon#read 5, iclass 11, count 2 2006.210.08:09:29.67#ibcon#about to read 6, iclass 11, count 2 2006.210.08:09:29.67#ibcon#read 6, iclass 11, count 2 2006.210.08:09:29.67#ibcon#end of sib2, iclass 11, count 2 2006.210.08:09:29.67#ibcon#*after write, iclass 11, count 2 2006.210.08:09:29.67#ibcon#*before return 0, iclass 11, count 2 2006.210.08:09:29.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:09:29.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:09:29.67#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:09:29.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:29.67#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:09:29.79#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:09:29.79#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:09:29.79#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:09:29.79#ibcon#first serial, iclass 11, count 0 2006.210.08:09:29.79#ibcon#enter sib2, iclass 11, count 0 2006.210.08:09:29.79#ibcon#flushed, iclass 11, count 0 2006.210.08:09:29.79#ibcon#about to write, iclass 11, count 0 2006.210.08:09:29.79#ibcon#wrote, iclass 11, count 0 2006.210.08:09:29.79#ibcon#about to read 3, iclass 11, count 0 2006.210.08:09:29.81#ibcon#read 3, iclass 11, count 0 2006.210.08:09:29.81#ibcon#about to read 4, iclass 11, count 0 2006.210.08:09:29.81#ibcon#read 4, iclass 11, count 0 2006.210.08:09:29.81#ibcon#about to read 5, iclass 11, count 0 2006.210.08:09:29.81#ibcon#read 5, iclass 11, count 0 2006.210.08:09:29.81#ibcon#about to read 6, iclass 11, count 0 2006.210.08:09:29.81#ibcon#read 6, iclass 11, count 0 2006.210.08:09:29.81#ibcon#end of sib2, iclass 11, count 0 2006.210.08:09:29.81#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:09:29.81#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:09:29.81#ibcon#[25=USB\r\n] 2006.210.08:09:29.81#ibcon#*before write, iclass 11, count 0 2006.210.08:09:29.81#ibcon#enter sib2, iclass 11, count 0 2006.210.08:09:29.81#ibcon#flushed, iclass 11, count 0 2006.210.08:09:29.81#ibcon#about to write, iclass 11, count 0 2006.210.08:09:29.81#ibcon#wrote, iclass 11, count 0 2006.210.08:09:29.81#ibcon#about to read 3, iclass 11, count 0 2006.210.08:09:29.84#ibcon#read 3, iclass 11, count 0 2006.210.08:09:29.84#ibcon#about to read 4, iclass 11, count 0 2006.210.08:09:29.84#ibcon#read 4, iclass 11, count 0 2006.210.08:09:29.84#ibcon#about to read 5, iclass 11, count 0 2006.210.08:09:29.84#ibcon#read 5, iclass 11, count 0 2006.210.08:09:29.84#ibcon#about to read 6, iclass 11, count 0 2006.210.08:09:29.84#ibcon#read 6, iclass 11, count 0 2006.210.08:09:29.84#ibcon#end of sib2, iclass 11, count 0 2006.210.08:09:29.84#ibcon#*after write, iclass 11, count 0 2006.210.08:09:29.84#ibcon#*before return 0, iclass 11, count 0 2006.210.08:09:29.84#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:09:29.84#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:09:29.84#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:09:29.84#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:09:29.84$vc4f8/valo=8,852.99 2006.210.08:09:29.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:09:29.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:09:29.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:29.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:09:29.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:09:29.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:09:29.84#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:09:29.85#ibcon#first serial, iclass 13, count 0 2006.210.08:09:29.85#ibcon#enter sib2, iclass 13, count 0 2006.210.08:09:29.85#ibcon#flushed, iclass 13, count 0 2006.210.08:09:29.85#ibcon#about to write, iclass 13, count 0 2006.210.08:09:29.85#ibcon#wrote, iclass 13, count 0 2006.210.08:09:29.85#ibcon#about to read 3, iclass 13, count 0 2006.210.08:09:29.86#ibcon#read 3, iclass 13, count 0 2006.210.08:09:29.86#ibcon#about to read 4, iclass 13, count 0 2006.210.08:09:29.86#ibcon#read 4, iclass 13, count 0 2006.210.08:09:29.86#ibcon#about to read 5, iclass 13, count 0 2006.210.08:09:29.86#ibcon#read 5, iclass 13, count 0 2006.210.08:09:29.86#ibcon#about to read 6, iclass 13, count 0 2006.210.08:09:29.86#ibcon#read 6, iclass 13, count 0 2006.210.08:09:29.86#ibcon#end of sib2, iclass 13, count 0 2006.210.08:09:29.86#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:09:29.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:09:29.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:09:29.86#ibcon#*before write, iclass 13, count 0 2006.210.08:09:29.86#ibcon#enter sib2, iclass 13, count 0 2006.210.08:09:29.86#ibcon#flushed, iclass 13, count 0 2006.210.08:09:29.86#ibcon#about to write, iclass 13, count 0 2006.210.08:09:29.86#ibcon#wrote, iclass 13, count 0 2006.210.08:09:29.86#ibcon#about to read 3, iclass 13, count 0 2006.210.08:09:29.90#ibcon#read 3, iclass 13, count 0 2006.210.08:09:29.90#ibcon#about to read 4, iclass 13, count 0 2006.210.08:09:29.90#ibcon#read 4, iclass 13, count 0 2006.210.08:09:29.90#ibcon#about to read 5, iclass 13, count 0 2006.210.08:09:29.90#ibcon#read 5, iclass 13, count 0 2006.210.08:09:29.90#ibcon#about to read 6, iclass 13, count 0 2006.210.08:09:29.90#ibcon#read 6, iclass 13, count 0 2006.210.08:09:29.90#ibcon#end of sib2, iclass 13, count 0 2006.210.08:09:29.90#ibcon#*after write, iclass 13, count 0 2006.210.08:09:29.90#ibcon#*before return 0, iclass 13, count 0 2006.210.08:09:29.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:09:29.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:09:29.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:09:29.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:09:29.90$vc4f8/va=8,7 2006.210.08:09:29.90#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:09:29.90#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:09:29.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:29.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:09:29.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:09:29.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:09:29.96#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:09:29.96#ibcon#first serial, iclass 15, count 2 2006.210.08:09:29.96#ibcon#enter sib2, iclass 15, count 2 2006.210.08:09:29.96#ibcon#flushed, iclass 15, count 2 2006.210.08:09:29.96#ibcon#about to write, iclass 15, count 2 2006.210.08:09:29.96#ibcon#wrote, iclass 15, count 2 2006.210.08:09:29.96#ibcon#about to read 3, iclass 15, count 2 2006.210.08:09:29.98#ibcon#read 3, iclass 15, count 2 2006.210.08:09:29.98#ibcon#about to read 4, iclass 15, count 2 2006.210.08:09:29.98#ibcon#read 4, iclass 15, count 2 2006.210.08:09:29.98#ibcon#about to read 5, iclass 15, count 2 2006.210.08:09:29.98#ibcon#read 5, iclass 15, count 2 2006.210.08:09:29.98#ibcon#about to read 6, iclass 15, count 2 2006.210.08:09:29.98#ibcon#read 6, iclass 15, count 2 2006.210.08:09:29.98#ibcon#end of sib2, iclass 15, count 2 2006.210.08:09:29.98#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:09:29.98#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:09:29.98#ibcon#[25=AT08-07\r\n] 2006.210.08:09:29.98#ibcon#*before write, iclass 15, count 2 2006.210.08:09:29.98#ibcon#enter sib2, iclass 15, count 2 2006.210.08:09:29.98#ibcon#flushed, iclass 15, count 2 2006.210.08:09:29.98#ibcon#about to write, iclass 15, count 2 2006.210.08:09:29.98#ibcon#wrote, iclass 15, count 2 2006.210.08:09:29.98#ibcon#about to read 3, iclass 15, count 2 2006.210.08:09:30.01#ibcon#read 3, iclass 15, count 2 2006.210.08:09:30.01#ibcon#about to read 4, iclass 15, count 2 2006.210.08:09:30.01#ibcon#read 4, iclass 15, count 2 2006.210.08:09:30.01#ibcon#about to read 5, iclass 15, count 2 2006.210.08:09:30.01#ibcon#read 5, iclass 15, count 2 2006.210.08:09:30.01#ibcon#about to read 6, iclass 15, count 2 2006.210.08:09:30.01#ibcon#read 6, iclass 15, count 2 2006.210.08:09:30.01#ibcon#end of sib2, iclass 15, count 2 2006.210.08:09:30.01#ibcon#*after write, iclass 15, count 2 2006.210.08:09:30.01#ibcon#*before return 0, iclass 15, count 2 2006.210.08:09:30.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:09:30.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:09:30.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:09:30.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:30.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:09:30.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:09:30.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:09:30.13#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:09:30.13#ibcon#first serial, iclass 15, count 0 2006.210.08:09:30.13#ibcon#enter sib2, iclass 15, count 0 2006.210.08:09:30.13#ibcon#flushed, iclass 15, count 0 2006.210.08:09:30.13#ibcon#about to write, iclass 15, count 0 2006.210.08:09:30.13#ibcon#wrote, iclass 15, count 0 2006.210.08:09:30.13#ibcon#about to read 3, iclass 15, count 0 2006.210.08:09:30.15#ibcon#read 3, iclass 15, count 0 2006.210.08:09:30.15#ibcon#about to read 4, iclass 15, count 0 2006.210.08:09:30.15#ibcon#read 4, iclass 15, count 0 2006.210.08:09:30.15#ibcon#about to read 5, iclass 15, count 0 2006.210.08:09:30.15#ibcon#read 5, iclass 15, count 0 2006.210.08:09:30.15#ibcon#about to read 6, iclass 15, count 0 2006.210.08:09:30.15#ibcon#read 6, iclass 15, count 0 2006.210.08:09:30.15#ibcon#end of sib2, iclass 15, count 0 2006.210.08:09:30.15#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:09:30.15#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:09:30.15#ibcon#[25=USB\r\n] 2006.210.08:09:30.15#ibcon#*before write, iclass 15, count 0 2006.210.08:09:30.15#ibcon#enter sib2, iclass 15, count 0 2006.210.08:09:30.15#ibcon#flushed, iclass 15, count 0 2006.210.08:09:30.15#ibcon#about to write, iclass 15, count 0 2006.210.08:09:30.15#ibcon#wrote, iclass 15, count 0 2006.210.08:09:30.15#ibcon#about to read 3, iclass 15, count 0 2006.210.08:09:30.18#ibcon#read 3, iclass 15, count 0 2006.210.08:09:30.18#ibcon#about to read 4, iclass 15, count 0 2006.210.08:09:30.18#ibcon#read 4, iclass 15, count 0 2006.210.08:09:30.18#ibcon#about to read 5, iclass 15, count 0 2006.210.08:09:30.18#ibcon#read 5, iclass 15, count 0 2006.210.08:09:30.18#ibcon#about to read 6, iclass 15, count 0 2006.210.08:09:30.18#ibcon#read 6, iclass 15, count 0 2006.210.08:09:30.18#ibcon#end of sib2, iclass 15, count 0 2006.210.08:09:30.18#ibcon#*after write, iclass 15, count 0 2006.210.08:09:30.18#ibcon#*before return 0, iclass 15, count 0 2006.210.08:09:30.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:09:30.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:09:30.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:09:30.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:09:30.18$vc4f8/vblo=1,632.99 2006.210.08:09:30.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:09:30.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:09:30.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:30.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:30.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:30.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:30.18#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:09:30.19#ibcon#first serial, iclass 17, count 0 2006.210.08:09:30.19#ibcon#enter sib2, iclass 17, count 0 2006.210.08:09:30.19#ibcon#flushed, iclass 17, count 0 2006.210.08:09:30.19#ibcon#about to write, iclass 17, count 0 2006.210.08:09:30.19#ibcon#wrote, iclass 17, count 0 2006.210.08:09:30.19#ibcon#about to read 3, iclass 17, count 0 2006.210.08:09:30.20#ibcon#read 3, iclass 17, count 0 2006.210.08:09:30.20#ibcon#about to read 4, iclass 17, count 0 2006.210.08:09:30.20#ibcon#read 4, iclass 17, count 0 2006.210.08:09:30.20#ibcon#about to read 5, iclass 17, count 0 2006.210.08:09:30.20#ibcon#read 5, iclass 17, count 0 2006.210.08:09:30.20#ibcon#about to read 6, iclass 17, count 0 2006.210.08:09:30.20#ibcon#read 6, iclass 17, count 0 2006.210.08:09:30.20#ibcon#end of sib2, iclass 17, count 0 2006.210.08:09:30.20#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:09:30.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:09:30.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:09:30.20#ibcon#*before write, iclass 17, count 0 2006.210.08:09:30.20#ibcon#enter sib2, iclass 17, count 0 2006.210.08:09:30.20#ibcon#flushed, iclass 17, count 0 2006.210.08:09:30.20#ibcon#about to write, iclass 17, count 0 2006.210.08:09:30.20#ibcon#wrote, iclass 17, count 0 2006.210.08:09:30.20#ibcon#about to read 3, iclass 17, count 0 2006.210.08:09:30.24#ibcon#read 3, iclass 17, count 0 2006.210.08:09:30.24#ibcon#about to read 4, iclass 17, count 0 2006.210.08:09:30.24#ibcon#read 4, iclass 17, count 0 2006.210.08:09:30.24#ibcon#about to read 5, iclass 17, count 0 2006.210.08:09:30.24#ibcon#read 5, iclass 17, count 0 2006.210.08:09:30.24#ibcon#about to read 6, iclass 17, count 0 2006.210.08:09:30.24#ibcon#read 6, iclass 17, count 0 2006.210.08:09:30.24#ibcon#end of sib2, iclass 17, count 0 2006.210.08:09:30.24#ibcon#*after write, iclass 17, count 0 2006.210.08:09:30.24#ibcon#*before return 0, iclass 17, count 0 2006.210.08:09:30.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:30.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:09:30.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:09:30.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:09:30.24$vc4f8/vb=1,4 2006.210.08:09:30.24#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:09:30.24#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:09:30.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:30.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:30.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:30.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:30.24#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:09:30.24#ibcon#first serial, iclass 19, count 2 2006.210.08:09:30.24#ibcon#enter sib2, iclass 19, count 2 2006.210.08:09:30.25#ibcon#flushed, iclass 19, count 2 2006.210.08:09:30.25#ibcon#about to write, iclass 19, count 2 2006.210.08:09:30.25#ibcon#wrote, iclass 19, count 2 2006.210.08:09:30.25#ibcon#about to read 3, iclass 19, count 2 2006.210.08:09:30.26#ibcon#read 3, iclass 19, count 2 2006.210.08:09:30.26#ibcon#about to read 4, iclass 19, count 2 2006.210.08:09:30.26#ibcon#read 4, iclass 19, count 2 2006.210.08:09:30.26#ibcon#about to read 5, iclass 19, count 2 2006.210.08:09:30.26#ibcon#read 5, iclass 19, count 2 2006.210.08:09:30.26#ibcon#about to read 6, iclass 19, count 2 2006.210.08:09:30.26#ibcon#read 6, iclass 19, count 2 2006.210.08:09:30.26#ibcon#end of sib2, iclass 19, count 2 2006.210.08:09:30.26#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:09:30.26#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:09:30.26#ibcon#[27=AT01-04\r\n] 2006.210.08:09:30.26#ibcon#*before write, iclass 19, count 2 2006.210.08:09:30.26#ibcon#enter sib2, iclass 19, count 2 2006.210.08:09:30.26#ibcon#flushed, iclass 19, count 2 2006.210.08:09:30.26#ibcon#about to write, iclass 19, count 2 2006.210.08:09:30.26#ibcon#wrote, iclass 19, count 2 2006.210.08:09:30.26#ibcon#about to read 3, iclass 19, count 2 2006.210.08:09:30.29#ibcon#read 3, iclass 19, count 2 2006.210.08:09:30.29#ibcon#about to read 4, iclass 19, count 2 2006.210.08:09:30.29#ibcon#read 4, iclass 19, count 2 2006.210.08:09:30.29#ibcon#about to read 5, iclass 19, count 2 2006.210.08:09:30.29#ibcon#read 5, iclass 19, count 2 2006.210.08:09:30.29#ibcon#about to read 6, iclass 19, count 2 2006.210.08:09:30.29#ibcon#read 6, iclass 19, count 2 2006.210.08:09:30.29#ibcon#end of sib2, iclass 19, count 2 2006.210.08:09:30.29#ibcon#*after write, iclass 19, count 2 2006.210.08:09:30.29#ibcon#*before return 0, iclass 19, count 2 2006.210.08:09:30.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:30.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:09:30.29#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:09:30.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:30.29#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:30.41#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:30.41#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:30.41#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:09:30.41#ibcon#first serial, iclass 19, count 0 2006.210.08:09:30.41#ibcon#enter sib2, iclass 19, count 0 2006.210.08:09:30.41#ibcon#flushed, iclass 19, count 0 2006.210.08:09:30.41#ibcon#about to write, iclass 19, count 0 2006.210.08:09:30.41#ibcon#wrote, iclass 19, count 0 2006.210.08:09:30.41#ibcon#about to read 3, iclass 19, count 0 2006.210.08:09:30.43#ibcon#read 3, iclass 19, count 0 2006.210.08:09:30.43#ibcon#about to read 4, iclass 19, count 0 2006.210.08:09:30.43#ibcon#read 4, iclass 19, count 0 2006.210.08:09:30.43#ibcon#about to read 5, iclass 19, count 0 2006.210.08:09:30.43#ibcon#read 5, iclass 19, count 0 2006.210.08:09:30.43#ibcon#about to read 6, iclass 19, count 0 2006.210.08:09:30.43#ibcon#read 6, iclass 19, count 0 2006.210.08:09:30.43#ibcon#end of sib2, iclass 19, count 0 2006.210.08:09:30.43#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:09:30.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:09:30.43#ibcon#[27=USB\r\n] 2006.210.08:09:30.43#ibcon#*before write, iclass 19, count 0 2006.210.08:09:30.43#ibcon#enter sib2, iclass 19, count 0 2006.210.08:09:30.43#ibcon#flushed, iclass 19, count 0 2006.210.08:09:30.43#ibcon#about to write, iclass 19, count 0 2006.210.08:09:30.43#ibcon#wrote, iclass 19, count 0 2006.210.08:09:30.43#ibcon#about to read 3, iclass 19, count 0 2006.210.08:09:30.46#ibcon#read 3, iclass 19, count 0 2006.210.08:09:30.46#ibcon#about to read 4, iclass 19, count 0 2006.210.08:09:30.46#ibcon#read 4, iclass 19, count 0 2006.210.08:09:30.46#ibcon#about to read 5, iclass 19, count 0 2006.210.08:09:30.46#ibcon#read 5, iclass 19, count 0 2006.210.08:09:30.46#ibcon#about to read 6, iclass 19, count 0 2006.210.08:09:30.46#ibcon#read 6, iclass 19, count 0 2006.210.08:09:30.46#ibcon#end of sib2, iclass 19, count 0 2006.210.08:09:30.46#ibcon#*after write, iclass 19, count 0 2006.210.08:09:30.46#ibcon#*before return 0, iclass 19, count 0 2006.210.08:09:30.46#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:30.46#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:09:30.46#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:09:30.46#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:09:30.46$vc4f8/vblo=2,640.99 2006.210.08:09:30.46#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:09:30.46#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:09:30.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:30.46#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:30.46#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:30.46#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:30.46#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:09:30.46#ibcon#first serial, iclass 21, count 0 2006.210.08:09:30.47#ibcon#enter sib2, iclass 21, count 0 2006.210.08:09:30.47#ibcon#flushed, iclass 21, count 0 2006.210.08:09:30.47#ibcon#about to write, iclass 21, count 0 2006.210.08:09:30.47#ibcon#wrote, iclass 21, count 0 2006.210.08:09:30.47#ibcon#about to read 3, iclass 21, count 0 2006.210.08:09:30.48#ibcon#read 3, iclass 21, count 0 2006.210.08:09:30.48#ibcon#about to read 4, iclass 21, count 0 2006.210.08:09:30.48#ibcon#read 4, iclass 21, count 0 2006.210.08:09:30.48#ibcon#about to read 5, iclass 21, count 0 2006.210.08:09:30.48#ibcon#read 5, iclass 21, count 0 2006.210.08:09:30.48#ibcon#about to read 6, iclass 21, count 0 2006.210.08:09:30.48#ibcon#read 6, iclass 21, count 0 2006.210.08:09:30.48#ibcon#end of sib2, iclass 21, count 0 2006.210.08:09:30.48#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:09:30.48#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:09:30.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:09:30.48#ibcon#*before write, iclass 21, count 0 2006.210.08:09:30.48#ibcon#enter sib2, iclass 21, count 0 2006.210.08:09:30.48#ibcon#flushed, iclass 21, count 0 2006.210.08:09:30.48#ibcon#about to write, iclass 21, count 0 2006.210.08:09:30.48#ibcon#wrote, iclass 21, count 0 2006.210.08:09:30.48#ibcon#about to read 3, iclass 21, count 0 2006.210.08:09:30.52#ibcon#read 3, iclass 21, count 0 2006.210.08:09:30.52#ibcon#about to read 4, iclass 21, count 0 2006.210.08:09:30.52#ibcon#read 4, iclass 21, count 0 2006.210.08:09:30.52#ibcon#about to read 5, iclass 21, count 0 2006.210.08:09:30.52#ibcon#read 5, iclass 21, count 0 2006.210.08:09:30.52#ibcon#about to read 6, iclass 21, count 0 2006.210.08:09:30.52#ibcon#read 6, iclass 21, count 0 2006.210.08:09:30.52#ibcon#end of sib2, iclass 21, count 0 2006.210.08:09:30.52#ibcon#*after write, iclass 21, count 0 2006.210.08:09:30.52#ibcon#*before return 0, iclass 21, count 0 2006.210.08:09:30.52#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:30.52#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:09:30.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:09:30.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:09:30.52$vc4f8/vb=2,4 2006.210.08:09:30.52#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:09:30.52#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:09:30.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:30.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:30.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:30.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:30.58#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:09:30.58#ibcon#first serial, iclass 23, count 2 2006.210.08:09:30.58#ibcon#enter sib2, iclass 23, count 2 2006.210.08:09:30.58#ibcon#flushed, iclass 23, count 2 2006.210.08:09:30.58#ibcon#about to write, iclass 23, count 2 2006.210.08:09:30.58#ibcon#wrote, iclass 23, count 2 2006.210.08:09:30.58#ibcon#about to read 3, iclass 23, count 2 2006.210.08:09:30.60#ibcon#read 3, iclass 23, count 2 2006.210.08:09:30.60#ibcon#about to read 4, iclass 23, count 2 2006.210.08:09:30.60#ibcon#read 4, iclass 23, count 2 2006.210.08:09:30.60#ibcon#about to read 5, iclass 23, count 2 2006.210.08:09:30.60#ibcon#read 5, iclass 23, count 2 2006.210.08:09:30.60#ibcon#about to read 6, iclass 23, count 2 2006.210.08:09:30.60#ibcon#read 6, iclass 23, count 2 2006.210.08:09:30.60#ibcon#end of sib2, iclass 23, count 2 2006.210.08:09:30.60#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:09:30.60#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:09:30.60#ibcon#[27=AT02-04\r\n] 2006.210.08:09:30.60#ibcon#*before write, iclass 23, count 2 2006.210.08:09:30.60#ibcon#enter sib2, iclass 23, count 2 2006.210.08:09:30.60#ibcon#flushed, iclass 23, count 2 2006.210.08:09:30.60#ibcon#about to write, iclass 23, count 2 2006.210.08:09:30.60#ibcon#wrote, iclass 23, count 2 2006.210.08:09:30.60#ibcon#about to read 3, iclass 23, count 2 2006.210.08:09:30.63#ibcon#read 3, iclass 23, count 2 2006.210.08:09:30.63#ibcon#about to read 4, iclass 23, count 2 2006.210.08:09:30.63#ibcon#read 4, iclass 23, count 2 2006.210.08:09:30.63#ibcon#about to read 5, iclass 23, count 2 2006.210.08:09:30.63#ibcon#read 5, iclass 23, count 2 2006.210.08:09:30.63#ibcon#about to read 6, iclass 23, count 2 2006.210.08:09:30.63#ibcon#read 6, iclass 23, count 2 2006.210.08:09:30.63#ibcon#end of sib2, iclass 23, count 2 2006.210.08:09:30.63#ibcon#*after write, iclass 23, count 2 2006.210.08:09:30.63#ibcon#*before return 0, iclass 23, count 2 2006.210.08:09:30.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:30.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:09:30.63#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:09:30.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:30.63#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:30.75#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:30.75#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:30.75#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:09:30.75#ibcon#first serial, iclass 23, count 0 2006.210.08:09:30.75#ibcon#enter sib2, iclass 23, count 0 2006.210.08:09:30.75#ibcon#flushed, iclass 23, count 0 2006.210.08:09:30.75#ibcon#about to write, iclass 23, count 0 2006.210.08:09:30.75#ibcon#wrote, iclass 23, count 0 2006.210.08:09:30.75#ibcon#about to read 3, iclass 23, count 0 2006.210.08:09:30.77#ibcon#read 3, iclass 23, count 0 2006.210.08:09:30.77#ibcon#about to read 4, iclass 23, count 0 2006.210.08:09:30.77#ibcon#read 4, iclass 23, count 0 2006.210.08:09:30.77#ibcon#about to read 5, iclass 23, count 0 2006.210.08:09:30.77#ibcon#read 5, iclass 23, count 0 2006.210.08:09:30.77#ibcon#about to read 6, iclass 23, count 0 2006.210.08:09:30.77#ibcon#read 6, iclass 23, count 0 2006.210.08:09:30.77#ibcon#end of sib2, iclass 23, count 0 2006.210.08:09:30.77#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:09:30.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:09:30.77#ibcon#[27=USB\r\n] 2006.210.08:09:30.77#ibcon#*before write, iclass 23, count 0 2006.210.08:09:30.77#ibcon#enter sib2, iclass 23, count 0 2006.210.08:09:30.77#ibcon#flushed, iclass 23, count 0 2006.210.08:09:30.77#ibcon#about to write, iclass 23, count 0 2006.210.08:09:30.77#ibcon#wrote, iclass 23, count 0 2006.210.08:09:30.77#ibcon#about to read 3, iclass 23, count 0 2006.210.08:09:30.80#ibcon#read 3, iclass 23, count 0 2006.210.08:09:30.80#ibcon#about to read 4, iclass 23, count 0 2006.210.08:09:30.80#ibcon#read 4, iclass 23, count 0 2006.210.08:09:30.80#ibcon#about to read 5, iclass 23, count 0 2006.210.08:09:30.80#ibcon#read 5, iclass 23, count 0 2006.210.08:09:30.80#ibcon#about to read 6, iclass 23, count 0 2006.210.08:09:30.80#ibcon#read 6, iclass 23, count 0 2006.210.08:09:30.80#ibcon#end of sib2, iclass 23, count 0 2006.210.08:09:30.80#ibcon#*after write, iclass 23, count 0 2006.210.08:09:30.80#ibcon#*before return 0, iclass 23, count 0 2006.210.08:09:30.80#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:30.80#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:09:30.80#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:09:30.80#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:09:30.80$vc4f8/vblo=3,656.99 2006.210.08:09:30.80#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:09:30.80#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:09:30.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:30.80#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:30.80#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:30.80#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:30.80#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:09:30.80#ibcon#first serial, iclass 25, count 0 2006.210.08:09:30.81#ibcon#enter sib2, iclass 25, count 0 2006.210.08:09:30.81#ibcon#flushed, iclass 25, count 0 2006.210.08:09:30.81#ibcon#about to write, iclass 25, count 0 2006.210.08:09:30.81#ibcon#wrote, iclass 25, count 0 2006.210.08:09:30.81#ibcon#about to read 3, iclass 25, count 0 2006.210.08:09:30.82#ibcon#read 3, iclass 25, count 0 2006.210.08:09:30.82#ibcon#about to read 4, iclass 25, count 0 2006.210.08:09:30.82#ibcon#read 4, iclass 25, count 0 2006.210.08:09:30.82#ibcon#about to read 5, iclass 25, count 0 2006.210.08:09:30.82#ibcon#read 5, iclass 25, count 0 2006.210.08:09:30.82#ibcon#about to read 6, iclass 25, count 0 2006.210.08:09:30.82#ibcon#read 6, iclass 25, count 0 2006.210.08:09:30.82#ibcon#end of sib2, iclass 25, count 0 2006.210.08:09:30.82#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:09:30.82#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:09:30.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:09:30.82#ibcon#*before write, iclass 25, count 0 2006.210.08:09:30.82#ibcon#enter sib2, iclass 25, count 0 2006.210.08:09:30.82#ibcon#flushed, iclass 25, count 0 2006.210.08:09:30.82#ibcon#about to write, iclass 25, count 0 2006.210.08:09:30.82#ibcon#wrote, iclass 25, count 0 2006.210.08:09:30.82#ibcon#about to read 3, iclass 25, count 0 2006.210.08:09:30.86#ibcon#read 3, iclass 25, count 0 2006.210.08:09:30.86#ibcon#about to read 4, iclass 25, count 0 2006.210.08:09:30.86#ibcon#read 4, iclass 25, count 0 2006.210.08:09:30.86#ibcon#about to read 5, iclass 25, count 0 2006.210.08:09:30.86#ibcon#read 5, iclass 25, count 0 2006.210.08:09:30.86#ibcon#about to read 6, iclass 25, count 0 2006.210.08:09:30.86#ibcon#read 6, iclass 25, count 0 2006.210.08:09:30.86#ibcon#end of sib2, iclass 25, count 0 2006.210.08:09:30.86#ibcon#*after write, iclass 25, count 0 2006.210.08:09:30.86#ibcon#*before return 0, iclass 25, count 0 2006.210.08:09:30.86#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:30.86#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:09:30.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:09:30.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:09:30.86$vc4f8/vb=3,3 2006.210.08:09:30.86#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:09:30.86#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:09:30.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:30.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:09:30.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:09:30.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:09:30.92#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:09:30.92#ibcon#first serial, iclass 27, count 2 2006.210.08:09:30.92#ibcon#enter sib2, iclass 27, count 2 2006.210.08:09:30.92#ibcon#flushed, iclass 27, count 2 2006.210.08:09:30.92#ibcon#about to write, iclass 27, count 2 2006.210.08:09:30.92#ibcon#wrote, iclass 27, count 2 2006.210.08:09:30.92#ibcon#about to read 3, iclass 27, count 2 2006.210.08:09:30.94#ibcon#read 3, iclass 27, count 2 2006.210.08:09:30.94#ibcon#about to read 4, iclass 27, count 2 2006.210.08:09:30.94#ibcon#read 4, iclass 27, count 2 2006.210.08:09:30.94#ibcon#about to read 5, iclass 27, count 2 2006.210.08:09:30.94#ibcon#read 5, iclass 27, count 2 2006.210.08:09:30.94#ibcon#about to read 6, iclass 27, count 2 2006.210.08:09:30.94#ibcon#read 6, iclass 27, count 2 2006.210.08:09:30.94#ibcon#end of sib2, iclass 27, count 2 2006.210.08:09:30.94#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:09:30.94#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:09:30.94#ibcon#[27=AT03-03\r\n] 2006.210.08:09:30.94#ibcon#*before write, iclass 27, count 2 2006.210.08:09:30.94#ibcon#enter sib2, iclass 27, count 2 2006.210.08:09:30.94#ibcon#flushed, iclass 27, count 2 2006.210.08:09:30.94#ibcon#about to write, iclass 27, count 2 2006.210.08:09:30.94#ibcon#wrote, iclass 27, count 2 2006.210.08:09:30.94#ibcon#about to read 3, iclass 27, count 2 2006.210.08:09:30.97#ibcon#read 3, iclass 27, count 2 2006.210.08:09:30.97#ibcon#about to read 4, iclass 27, count 2 2006.210.08:09:30.97#ibcon#read 4, iclass 27, count 2 2006.210.08:09:30.97#ibcon#about to read 5, iclass 27, count 2 2006.210.08:09:30.97#ibcon#read 5, iclass 27, count 2 2006.210.08:09:30.97#ibcon#about to read 6, iclass 27, count 2 2006.210.08:09:30.97#ibcon#read 6, iclass 27, count 2 2006.210.08:09:30.97#ibcon#end of sib2, iclass 27, count 2 2006.210.08:09:30.97#ibcon#*after write, iclass 27, count 2 2006.210.08:09:30.97#ibcon#*before return 0, iclass 27, count 2 2006.210.08:09:30.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:09:30.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:09:30.97#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:09:30.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:30.97#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:09:31.09#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:09:31.09#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:09:31.09#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:09:31.09#ibcon#first serial, iclass 27, count 0 2006.210.08:09:31.09#ibcon#enter sib2, iclass 27, count 0 2006.210.08:09:31.09#ibcon#flushed, iclass 27, count 0 2006.210.08:09:31.09#ibcon#about to write, iclass 27, count 0 2006.210.08:09:31.09#ibcon#wrote, iclass 27, count 0 2006.210.08:09:31.09#ibcon#about to read 3, iclass 27, count 0 2006.210.08:09:31.11#ibcon#read 3, iclass 27, count 0 2006.210.08:09:31.11#ibcon#about to read 4, iclass 27, count 0 2006.210.08:09:31.11#ibcon#read 4, iclass 27, count 0 2006.210.08:09:31.11#ibcon#about to read 5, iclass 27, count 0 2006.210.08:09:31.11#ibcon#read 5, iclass 27, count 0 2006.210.08:09:31.11#ibcon#about to read 6, iclass 27, count 0 2006.210.08:09:31.11#ibcon#read 6, iclass 27, count 0 2006.210.08:09:31.11#ibcon#end of sib2, iclass 27, count 0 2006.210.08:09:31.11#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:09:31.11#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:09:31.11#ibcon#[27=USB\r\n] 2006.210.08:09:31.11#ibcon#*before write, iclass 27, count 0 2006.210.08:09:31.11#ibcon#enter sib2, iclass 27, count 0 2006.210.08:09:31.11#ibcon#flushed, iclass 27, count 0 2006.210.08:09:31.11#ibcon#about to write, iclass 27, count 0 2006.210.08:09:31.11#ibcon#wrote, iclass 27, count 0 2006.210.08:09:31.11#ibcon#about to read 3, iclass 27, count 0 2006.210.08:09:31.14#ibcon#read 3, iclass 27, count 0 2006.210.08:09:31.14#ibcon#about to read 4, iclass 27, count 0 2006.210.08:09:31.14#ibcon#read 4, iclass 27, count 0 2006.210.08:09:31.14#ibcon#about to read 5, iclass 27, count 0 2006.210.08:09:31.14#ibcon#read 5, iclass 27, count 0 2006.210.08:09:31.14#ibcon#about to read 6, iclass 27, count 0 2006.210.08:09:31.14#ibcon#read 6, iclass 27, count 0 2006.210.08:09:31.14#ibcon#end of sib2, iclass 27, count 0 2006.210.08:09:31.14#ibcon#*after write, iclass 27, count 0 2006.210.08:09:31.14#ibcon#*before return 0, iclass 27, count 0 2006.210.08:09:31.14#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:09:31.14#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:09:31.14#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:09:31.14#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:09:31.14$vc4f8/vblo=4,712.99 2006.210.08:09:31.14#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:09:31.14#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:09:31.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:31.14#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:09:31.14#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:09:31.14#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:09:31.14#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:09:31.14#ibcon#first serial, iclass 29, count 0 2006.210.08:09:31.15#ibcon#enter sib2, iclass 29, count 0 2006.210.08:09:31.15#ibcon#flushed, iclass 29, count 0 2006.210.08:09:31.15#ibcon#about to write, iclass 29, count 0 2006.210.08:09:31.15#ibcon#wrote, iclass 29, count 0 2006.210.08:09:31.15#ibcon#about to read 3, iclass 29, count 0 2006.210.08:09:31.16#ibcon#read 3, iclass 29, count 0 2006.210.08:09:31.16#ibcon#about to read 4, iclass 29, count 0 2006.210.08:09:31.16#ibcon#read 4, iclass 29, count 0 2006.210.08:09:31.16#ibcon#about to read 5, iclass 29, count 0 2006.210.08:09:31.16#ibcon#read 5, iclass 29, count 0 2006.210.08:09:31.16#ibcon#about to read 6, iclass 29, count 0 2006.210.08:09:31.16#ibcon#read 6, iclass 29, count 0 2006.210.08:09:31.16#ibcon#end of sib2, iclass 29, count 0 2006.210.08:09:31.16#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:09:31.16#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:09:31.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:09:31.16#ibcon#*before write, iclass 29, count 0 2006.210.08:09:31.16#ibcon#enter sib2, iclass 29, count 0 2006.210.08:09:31.16#ibcon#flushed, iclass 29, count 0 2006.210.08:09:31.16#ibcon#about to write, iclass 29, count 0 2006.210.08:09:31.16#ibcon#wrote, iclass 29, count 0 2006.210.08:09:31.16#ibcon#about to read 3, iclass 29, count 0 2006.210.08:09:31.20#ibcon#read 3, iclass 29, count 0 2006.210.08:09:31.20#ibcon#about to read 4, iclass 29, count 0 2006.210.08:09:31.20#ibcon#read 4, iclass 29, count 0 2006.210.08:09:31.20#ibcon#about to read 5, iclass 29, count 0 2006.210.08:09:31.20#ibcon#read 5, iclass 29, count 0 2006.210.08:09:31.20#ibcon#about to read 6, iclass 29, count 0 2006.210.08:09:31.20#ibcon#read 6, iclass 29, count 0 2006.210.08:09:31.20#ibcon#end of sib2, iclass 29, count 0 2006.210.08:09:31.20#ibcon#*after write, iclass 29, count 0 2006.210.08:09:31.20#ibcon#*before return 0, iclass 29, count 0 2006.210.08:09:31.20#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:09:31.20#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:09:31.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:09:31.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:09:31.20$vc4f8/vb=4,3 2006.210.08:09:31.20#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.08:09:31.20#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.08:09:31.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:31.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:09:31.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:09:31.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:09:31.26#ibcon#enter wrdev, iclass 31, count 2 2006.210.08:09:31.26#ibcon#first serial, iclass 31, count 2 2006.210.08:09:31.26#ibcon#enter sib2, iclass 31, count 2 2006.210.08:09:31.26#ibcon#flushed, iclass 31, count 2 2006.210.08:09:31.26#ibcon#about to write, iclass 31, count 2 2006.210.08:09:31.26#ibcon#wrote, iclass 31, count 2 2006.210.08:09:31.26#ibcon#about to read 3, iclass 31, count 2 2006.210.08:09:31.28#ibcon#read 3, iclass 31, count 2 2006.210.08:09:31.28#ibcon#about to read 4, iclass 31, count 2 2006.210.08:09:31.28#ibcon#read 4, iclass 31, count 2 2006.210.08:09:31.28#ibcon#about to read 5, iclass 31, count 2 2006.210.08:09:31.28#ibcon#read 5, iclass 31, count 2 2006.210.08:09:31.28#ibcon#about to read 6, iclass 31, count 2 2006.210.08:09:31.28#ibcon#read 6, iclass 31, count 2 2006.210.08:09:31.28#ibcon#end of sib2, iclass 31, count 2 2006.210.08:09:31.28#ibcon#*mode == 0, iclass 31, count 2 2006.210.08:09:31.28#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.08:09:31.28#ibcon#[27=AT04-03\r\n] 2006.210.08:09:31.28#ibcon#*before write, iclass 31, count 2 2006.210.08:09:31.28#ibcon#enter sib2, iclass 31, count 2 2006.210.08:09:31.28#ibcon#flushed, iclass 31, count 2 2006.210.08:09:31.28#ibcon#about to write, iclass 31, count 2 2006.210.08:09:31.28#ibcon#wrote, iclass 31, count 2 2006.210.08:09:31.28#ibcon#about to read 3, iclass 31, count 2 2006.210.08:09:31.31#ibcon#read 3, iclass 31, count 2 2006.210.08:09:31.31#ibcon#about to read 4, iclass 31, count 2 2006.210.08:09:31.31#ibcon#read 4, iclass 31, count 2 2006.210.08:09:31.31#ibcon#about to read 5, iclass 31, count 2 2006.210.08:09:31.31#ibcon#read 5, iclass 31, count 2 2006.210.08:09:31.31#ibcon#about to read 6, iclass 31, count 2 2006.210.08:09:31.31#ibcon#read 6, iclass 31, count 2 2006.210.08:09:31.31#ibcon#end of sib2, iclass 31, count 2 2006.210.08:09:31.31#ibcon#*after write, iclass 31, count 2 2006.210.08:09:31.31#ibcon#*before return 0, iclass 31, count 2 2006.210.08:09:31.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:09:31.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:09:31.31#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.08:09:31.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:31.31#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:09:31.43#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:09:31.43#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:09:31.43#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:09:31.43#ibcon#first serial, iclass 31, count 0 2006.210.08:09:31.43#ibcon#enter sib2, iclass 31, count 0 2006.210.08:09:31.43#ibcon#flushed, iclass 31, count 0 2006.210.08:09:31.43#ibcon#about to write, iclass 31, count 0 2006.210.08:09:31.43#ibcon#wrote, iclass 31, count 0 2006.210.08:09:31.43#ibcon#about to read 3, iclass 31, count 0 2006.210.08:09:31.45#ibcon#read 3, iclass 31, count 0 2006.210.08:09:31.45#ibcon#about to read 4, iclass 31, count 0 2006.210.08:09:31.45#ibcon#read 4, iclass 31, count 0 2006.210.08:09:31.45#ibcon#about to read 5, iclass 31, count 0 2006.210.08:09:31.45#ibcon#read 5, iclass 31, count 0 2006.210.08:09:31.45#ibcon#about to read 6, iclass 31, count 0 2006.210.08:09:31.45#ibcon#read 6, iclass 31, count 0 2006.210.08:09:31.45#ibcon#end of sib2, iclass 31, count 0 2006.210.08:09:31.45#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:09:31.45#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:09:31.45#ibcon#[27=USB\r\n] 2006.210.08:09:31.45#ibcon#*before write, iclass 31, count 0 2006.210.08:09:31.45#ibcon#enter sib2, iclass 31, count 0 2006.210.08:09:31.45#ibcon#flushed, iclass 31, count 0 2006.210.08:09:31.45#ibcon#about to write, iclass 31, count 0 2006.210.08:09:31.45#ibcon#wrote, iclass 31, count 0 2006.210.08:09:31.45#ibcon#about to read 3, iclass 31, count 0 2006.210.08:09:31.48#ibcon#read 3, iclass 31, count 0 2006.210.08:09:31.48#ibcon#about to read 4, iclass 31, count 0 2006.210.08:09:31.48#ibcon#read 4, iclass 31, count 0 2006.210.08:09:31.48#ibcon#about to read 5, iclass 31, count 0 2006.210.08:09:31.48#ibcon#read 5, iclass 31, count 0 2006.210.08:09:31.48#ibcon#about to read 6, iclass 31, count 0 2006.210.08:09:31.48#ibcon#read 6, iclass 31, count 0 2006.210.08:09:31.48#ibcon#end of sib2, iclass 31, count 0 2006.210.08:09:31.48#ibcon#*after write, iclass 31, count 0 2006.210.08:09:31.48#ibcon#*before return 0, iclass 31, count 0 2006.210.08:09:31.48#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:09:31.48#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:09:31.48#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:09:31.48#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:09:31.48$vc4f8/vblo=5,744.99 2006.210.08:09:31.48#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:09:31.48#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:09:31.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:31.48#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:31.48#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:31.48#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:31.48#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:09:31.48#ibcon#first serial, iclass 33, count 0 2006.210.08:09:31.48#ibcon#enter sib2, iclass 33, count 0 2006.210.08:09:31.49#ibcon#flushed, iclass 33, count 0 2006.210.08:09:31.49#ibcon#about to write, iclass 33, count 0 2006.210.08:09:31.49#ibcon#wrote, iclass 33, count 0 2006.210.08:09:31.49#ibcon#about to read 3, iclass 33, count 0 2006.210.08:09:31.50#ibcon#read 3, iclass 33, count 0 2006.210.08:09:31.50#ibcon#about to read 4, iclass 33, count 0 2006.210.08:09:31.50#ibcon#read 4, iclass 33, count 0 2006.210.08:09:31.50#ibcon#about to read 5, iclass 33, count 0 2006.210.08:09:31.50#ibcon#read 5, iclass 33, count 0 2006.210.08:09:31.50#ibcon#about to read 6, iclass 33, count 0 2006.210.08:09:31.50#ibcon#read 6, iclass 33, count 0 2006.210.08:09:31.50#ibcon#end of sib2, iclass 33, count 0 2006.210.08:09:31.50#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:09:31.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:09:31.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:09:31.50#ibcon#*before write, iclass 33, count 0 2006.210.08:09:31.50#ibcon#enter sib2, iclass 33, count 0 2006.210.08:09:31.50#ibcon#flushed, iclass 33, count 0 2006.210.08:09:31.50#ibcon#about to write, iclass 33, count 0 2006.210.08:09:31.50#ibcon#wrote, iclass 33, count 0 2006.210.08:09:31.50#ibcon#about to read 3, iclass 33, count 0 2006.210.08:09:31.54#ibcon#read 3, iclass 33, count 0 2006.210.08:09:31.54#ibcon#about to read 4, iclass 33, count 0 2006.210.08:09:31.54#ibcon#read 4, iclass 33, count 0 2006.210.08:09:31.54#ibcon#about to read 5, iclass 33, count 0 2006.210.08:09:31.54#ibcon#read 5, iclass 33, count 0 2006.210.08:09:31.54#ibcon#about to read 6, iclass 33, count 0 2006.210.08:09:31.54#ibcon#read 6, iclass 33, count 0 2006.210.08:09:31.54#ibcon#end of sib2, iclass 33, count 0 2006.210.08:09:31.54#ibcon#*after write, iclass 33, count 0 2006.210.08:09:31.54#ibcon#*before return 0, iclass 33, count 0 2006.210.08:09:31.54#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:31.54#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:09:31.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:09:31.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:09:31.54$vc4f8/vb=5,3 2006.210.08:09:31.54#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:09:31.54#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:09:31.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:31.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:31.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:31.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:31.60#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:09:31.60#ibcon#first serial, iclass 35, count 2 2006.210.08:09:31.60#ibcon#enter sib2, iclass 35, count 2 2006.210.08:09:31.60#ibcon#flushed, iclass 35, count 2 2006.210.08:09:31.60#ibcon#about to write, iclass 35, count 2 2006.210.08:09:31.60#ibcon#wrote, iclass 35, count 2 2006.210.08:09:31.60#ibcon#about to read 3, iclass 35, count 2 2006.210.08:09:31.62#ibcon#read 3, iclass 35, count 2 2006.210.08:09:31.62#ibcon#about to read 4, iclass 35, count 2 2006.210.08:09:31.62#ibcon#read 4, iclass 35, count 2 2006.210.08:09:31.62#ibcon#about to read 5, iclass 35, count 2 2006.210.08:09:31.62#ibcon#read 5, iclass 35, count 2 2006.210.08:09:31.62#ibcon#about to read 6, iclass 35, count 2 2006.210.08:09:31.62#ibcon#read 6, iclass 35, count 2 2006.210.08:09:31.62#ibcon#end of sib2, iclass 35, count 2 2006.210.08:09:31.62#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:09:31.62#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:09:31.62#ibcon#[27=AT05-03\r\n] 2006.210.08:09:31.62#ibcon#*before write, iclass 35, count 2 2006.210.08:09:31.62#ibcon#enter sib2, iclass 35, count 2 2006.210.08:09:31.62#ibcon#flushed, iclass 35, count 2 2006.210.08:09:31.62#ibcon#about to write, iclass 35, count 2 2006.210.08:09:31.62#ibcon#wrote, iclass 35, count 2 2006.210.08:09:31.62#ibcon#about to read 3, iclass 35, count 2 2006.210.08:09:31.65#ibcon#read 3, iclass 35, count 2 2006.210.08:09:31.65#ibcon#about to read 4, iclass 35, count 2 2006.210.08:09:31.65#ibcon#read 4, iclass 35, count 2 2006.210.08:09:31.65#ibcon#about to read 5, iclass 35, count 2 2006.210.08:09:31.65#ibcon#read 5, iclass 35, count 2 2006.210.08:09:31.65#ibcon#about to read 6, iclass 35, count 2 2006.210.08:09:31.65#ibcon#read 6, iclass 35, count 2 2006.210.08:09:31.65#ibcon#end of sib2, iclass 35, count 2 2006.210.08:09:31.65#ibcon#*after write, iclass 35, count 2 2006.210.08:09:31.65#ibcon#*before return 0, iclass 35, count 2 2006.210.08:09:31.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:31.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:09:31.65#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:09:31.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:31.65#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:31.77#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:31.77#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:31.77#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:09:31.77#ibcon#first serial, iclass 35, count 0 2006.210.08:09:31.77#ibcon#enter sib2, iclass 35, count 0 2006.210.08:09:31.77#ibcon#flushed, iclass 35, count 0 2006.210.08:09:31.77#ibcon#about to write, iclass 35, count 0 2006.210.08:09:31.77#ibcon#wrote, iclass 35, count 0 2006.210.08:09:31.77#ibcon#about to read 3, iclass 35, count 0 2006.210.08:09:31.79#ibcon#read 3, iclass 35, count 0 2006.210.08:09:31.79#ibcon#about to read 4, iclass 35, count 0 2006.210.08:09:31.79#ibcon#read 4, iclass 35, count 0 2006.210.08:09:31.79#ibcon#about to read 5, iclass 35, count 0 2006.210.08:09:31.79#ibcon#read 5, iclass 35, count 0 2006.210.08:09:31.79#ibcon#about to read 6, iclass 35, count 0 2006.210.08:09:31.79#ibcon#read 6, iclass 35, count 0 2006.210.08:09:31.79#ibcon#end of sib2, iclass 35, count 0 2006.210.08:09:31.79#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:09:31.79#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:09:31.79#ibcon#[27=USB\r\n] 2006.210.08:09:31.79#ibcon#*before write, iclass 35, count 0 2006.210.08:09:31.79#ibcon#enter sib2, iclass 35, count 0 2006.210.08:09:31.79#ibcon#flushed, iclass 35, count 0 2006.210.08:09:31.79#ibcon#about to write, iclass 35, count 0 2006.210.08:09:31.79#ibcon#wrote, iclass 35, count 0 2006.210.08:09:31.79#ibcon#about to read 3, iclass 35, count 0 2006.210.08:09:31.82#ibcon#read 3, iclass 35, count 0 2006.210.08:09:31.82#ibcon#about to read 4, iclass 35, count 0 2006.210.08:09:31.82#ibcon#read 4, iclass 35, count 0 2006.210.08:09:31.82#ibcon#about to read 5, iclass 35, count 0 2006.210.08:09:31.82#ibcon#read 5, iclass 35, count 0 2006.210.08:09:31.82#ibcon#about to read 6, iclass 35, count 0 2006.210.08:09:31.82#ibcon#read 6, iclass 35, count 0 2006.210.08:09:31.82#ibcon#end of sib2, iclass 35, count 0 2006.210.08:09:31.82#ibcon#*after write, iclass 35, count 0 2006.210.08:09:31.82#ibcon#*before return 0, iclass 35, count 0 2006.210.08:09:31.82#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:31.82#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:09:31.82#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:09:31.82#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:09:31.82$vc4f8/vblo=6,752.99 2006.210.08:09:31.82#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:09:31.82#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:09:31.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:09:31.82#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:31.82#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:31.82#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:31.82#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:09:31.82#ibcon#first serial, iclass 37, count 0 2006.210.08:09:31.83#ibcon#enter sib2, iclass 37, count 0 2006.210.08:09:31.83#ibcon#flushed, iclass 37, count 0 2006.210.08:09:31.83#ibcon#about to write, iclass 37, count 0 2006.210.08:09:31.83#ibcon#wrote, iclass 37, count 0 2006.210.08:09:31.83#ibcon#about to read 3, iclass 37, count 0 2006.210.08:09:31.84#ibcon#read 3, iclass 37, count 0 2006.210.08:09:31.84#ibcon#about to read 4, iclass 37, count 0 2006.210.08:09:31.84#ibcon#read 4, iclass 37, count 0 2006.210.08:09:31.84#ibcon#about to read 5, iclass 37, count 0 2006.210.08:09:31.84#ibcon#read 5, iclass 37, count 0 2006.210.08:09:31.84#ibcon#about to read 6, iclass 37, count 0 2006.210.08:09:31.84#ibcon#read 6, iclass 37, count 0 2006.210.08:09:31.84#ibcon#end of sib2, iclass 37, count 0 2006.210.08:09:31.84#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:09:31.84#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:09:31.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:09:31.84#ibcon#*before write, iclass 37, count 0 2006.210.08:09:31.84#ibcon#enter sib2, iclass 37, count 0 2006.210.08:09:31.84#ibcon#flushed, iclass 37, count 0 2006.210.08:09:31.84#ibcon#about to write, iclass 37, count 0 2006.210.08:09:31.84#ibcon#wrote, iclass 37, count 0 2006.210.08:09:31.84#ibcon#about to read 3, iclass 37, count 0 2006.210.08:09:31.88#ibcon#read 3, iclass 37, count 0 2006.210.08:09:31.88#ibcon#about to read 4, iclass 37, count 0 2006.210.08:09:31.88#ibcon#read 4, iclass 37, count 0 2006.210.08:09:31.88#ibcon#about to read 5, iclass 37, count 0 2006.210.08:09:31.88#ibcon#read 5, iclass 37, count 0 2006.210.08:09:31.88#ibcon#about to read 6, iclass 37, count 0 2006.210.08:09:31.88#ibcon#read 6, iclass 37, count 0 2006.210.08:09:31.88#ibcon#end of sib2, iclass 37, count 0 2006.210.08:09:31.88#ibcon#*after write, iclass 37, count 0 2006.210.08:09:31.88#ibcon#*before return 0, iclass 37, count 0 2006.210.08:09:31.88#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:31.88#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:09:31.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:09:31.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:09:31.88$vc4f8/vb=6,3 2006.210.08:09:31.88#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:09:31.88#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:09:31.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:09:31.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:31.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:31.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:31.94#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:09:31.94#ibcon#first serial, iclass 39, count 2 2006.210.08:09:31.94#ibcon#enter sib2, iclass 39, count 2 2006.210.08:09:31.94#ibcon#flushed, iclass 39, count 2 2006.210.08:09:31.94#ibcon#about to write, iclass 39, count 2 2006.210.08:09:31.94#ibcon#wrote, iclass 39, count 2 2006.210.08:09:31.94#ibcon#about to read 3, iclass 39, count 2 2006.210.08:09:31.96#ibcon#read 3, iclass 39, count 2 2006.210.08:09:31.96#ibcon#about to read 4, iclass 39, count 2 2006.210.08:09:31.96#ibcon#read 4, iclass 39, count 2 2006.210.08:09:31.96#ibcon#about to read 5, iclass 39, count 2 2006.210.08:09:31.96#ibcon#read 5, iclass 39, count 2 2006.210.08:09:31.96#ibcon#about to read 6, iclass 39, count 2 2006.210.08:09:31.96#ibcon#read 6, iclass 39, count 2 2006.210.08:09:31.96#ibcon#end of sib2, iclass 39, count 2 2006.210.08:09:31.96#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:09:31.96#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:09:31.96#ibcon#[27=AT06-03\r\n] 2006.210.08:09:31.96#ibcon#*before write, iclass 39, count 2 2006.210.08:09:31.96#ibcon#enter sib2, iclass 39, count 2 2006.210.08:09:31.96#ibcon#flushed, iclass 39, count 2 2006.210.08:09:31.96#ibcon#about to write, iclass 39, count 2 2006.210.08:09:31.96#ibcon#wrote, iclass 39, count 2 2006.210.08:09:31.96#ibcon#about to read 3, iclass 39, count 2 2006.210.08:09:31.99#ibcon#read 3, iclass 39, count 2 2006.210.08:09:31.99#ibcon#about to read 4, iclass 39, count 2 2006.210.08:09:31.99#ibcon#read 4, iclass 39, count 2 2006.210.08:09:31.99#ibcon#about to read 5, iclass 39, count 2 2006.210.08:09:31.99#ibcon#read 5, iclass 39, count 2 2006.210.08:09:31.99#ibcon#about to read 6, iclass 39, count 2 2006.210.08:09:31.99#ibcon#read 6, iclass 39, count 2 2006.210.08:09:31.99#ibcon#end of sib2, iclass 39, count 2 2006.210.08:09:31.99#ibcon#*after write, iclass 39, count 2 2006.210.08:09:31.99#ibcon#*before return 0, iclass 39, count 2 2006.210.08:09:31.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:31.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:09:31.99#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:09:31.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:09:31.99#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:32.11#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:32.11#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:32.11#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:09:32.11#ibcon#first serial, iclass 39, count 0 2006.210.08:09:32.11#ibcon#enter sib2, iclass 39, count 0 2006.210.08:09:32.11#ibcon#flushed, iclass 39, count 0 2006.210.08:09:32.11#ibcon#about to write, iclass 39, count 0 2006.210.08:09:32.11#ibcon#wrote, iclass 39, count 0 2006.210.08:09:32.11#ibcon#about to read 3, iclass 39, count 0 2006.210.08:09:32.13#ibcon#read 3, iclass 39, count 0 2006.210.08:09:32.13#ibcon#about to read 4, iclass 39, count 0 2006.210.08:09:32.13#ibcon#read 4, iclass 39, count 0 2006.210.08:09:32.13#ibcon#about to read 5, iclass 39, count 0 2006.210.08:09:32.13#ibcon#read 5, iclass 39, count 0 2006.210.08:09:32.13#ibcon#about to read 6, iclass 39, count 0 2006.210.08:09:32.13#ibcon#read 6, iclass 39, count 0 2006.210.08:09:32.13#ibcon#end of sib2, iclass 39, count 0 2006.210.08:09:32.13#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:09:32.13#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:09:32.13#ibcon#[27=USB\r\n] 2006.210.08:09:32.13#ibcon#*before write, iclass 39, count 0 2006.210.08:09:32.13#ibcon#enter sib2, iclass 39, count 0 2006.210.08:09:32.13#ibcon#flushed, iclass 39, count 0 2006.210.08:09:32.13#ibcon#about to write, iclass 39, count 0 2006.210.08:09:32.13#ibcon#wrote, iclass 39, count 0 2006.210.08:09:32.13#ibcon#about to read 3, iclass 39, count 0 2006.210.08:09:32.16#ibcon#read 3, iclass 39, count 0 2006.210.08:09:32.16#ibcon#about to read 4, iclass 39, count 0 2006.210.08:09:32.16#ibcon#read 4, iclass 39, count 0 2006.210.08:09:32.16#ibcon#about to read 5, iclass 39, count 0 2006.210.08:09:32.16#ibcon#read 5, iclass 39, count 0 2006.210.08:09:32.16#ibcon#about to read 6, iclass 39, count 0 2006.210.08:09:32.16#ibcon#read 6, iclass 39, count 0 2006.210.08:09:32.16#ibcon#end of sib2, iclass 39, count 0 2006.210.08:09:32.16#ibcon#*after write, iclass 39, count 0 2006.210.08:09:32.16#ibcon#*before return 0, iclass 39, count 0 2006.210.08:09:32.16#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:32.16#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:09:32.16#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:09:32.16#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:09:32.16$vc4f8/vabw=wide 2006.210.08:09:32.16#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:09:32.16#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:09:32.16#ibcon#ireg 8 cls_cnt 0 2006.210.08:09:32.16#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:32.16#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:32.16#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:32.16#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:09:32.16#ibcon#first serial, iclass 3, count 0 2006.210.08:09:32.16#ibcon#enter sib2, iclass 3, count 0 2006.210.08:09:32.16#ibcon#flushed, iclass 3, count 0 2006.210.08:09:32.17#ibcon#about to write, iclass 3, count 0 2006.210.08:09:32.17#ibcon#wrote, iclass 3, count 0 2006.210.08:09:32.17#ibcon#about to read 3, iclass 3, count 0 2006.210.08:09:32.18#ibcon#read 3, iclass 3, count 0 2006.210.08:09:32.18#ibcon#about to read 4, iclass 3, count 0 2006.210.08:09:32.18#ibcon#read 4, iclass 3, count 0 2006.210.08:09:32.18#ibcon#about to read 5, iclass 3, count 0 2006.210.08:09:32.18#ibcon#read 5, iclass 3, count 0 2006.210.08:09:32.18#ibcon#about to read 6, iclass 3, count 0 2006.210.08:09:32.18#ibcon#read 6, iclass 3, count 0 2006.210.08:09:32.18#ibcon#end of sib2, iclass 3, count 0 2006.210.08:09:32.18#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:09:32.18#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:09:32.18#ibcon#[25=BW32\r\n] 2006.210.08:09:32.18#ibcon#*before write, iclass 3, count 0 2006.210.08:09:32.18#ibcon#enter sib2, iclass 3, count 0 2006.210.08:09:32.18#ibcon#flushed, iclass 3, count 0 2006.210.08:09:32.18#ibcon#about to write, iclass 3, count 0 2006.210.08:09:32.18#ibcon#wrote, iclass 3, count 0 2006.210.08:09:32.18#ibcon#about to read 3, iclass 3, count 0 2006.210.08:09:32.21#ibcon#read 3, iclass 3, count 0 2006.210.08:09:32.21#ibcon#about to read 4, iclass 3, count 0 2006.210.08:09:32.21#ibcon#read 4, iclass 3, count 0 2006.210.08:09:32.21#ibcon#about to read 5, iclass 3, count 0 2006.210.08:09:32.21#ibcon#read 5, iclass 3, count 0 2006.210.08:09:32.21#ibcon#about to read 6, iclass 3, count 0 2006.210.08:09:32.21#ibcon#read 6, iclass 3, count 0 2006.210.08:09:32.21#ibcon#end of sib2, iclass 3, count 0 2006.210.08:09:32.21#ibcon#*after write, iclass 3, count 0 2006.210.08:09:32.21#ibcon#*before return 0, iclass 3, count 0 2006.210.08:09:32.21#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:32.21#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:09:32.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:09:32.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:09:32.21$vc4f8/vbbw=wide 2006.210.08:09:32.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.08:09:32.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.08:09:32.21#ibcon#ireg 8 cls_cnt 0 2006.210.08:09:32.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:09:32.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:09:32.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:09:32.28#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:09:32.28#ibcon#first serial, iclass 5, count 0 2006.210.08:09:32.28#ibcon#enter sib2, iclass 5, count 0 2006.210.08:09:32.28#ibcon#flushed, iclass 5, count 0 2006.210.08:09:32.28#ibcon#about to write, iclass 5, count 0 2006.210.08:09:32.28#ibcon#wrote, iclass 5, count 0 2006.210.08:09:32.28#ibcon#about to read 3, iclass 5, count 0 2006.210.08:09:32.30#ibcon#read 3, iclass 5, count 0 2006.210.08:09:32.30#ibcon#about to read 4, iclass 5, count 0 2006.210.08:09:32.30#ibcon#read 4, iclass 5, count 0 2006.210.08:09:32.30#ibcon#about to read 5, iclass 5, count 0 2006.210.08:09:32.30#ibcon#read 5, iclass 5, count 0 2006.210.08:09:32.30#ibcon#about to read 6, iclass 5, count 0 2006.210.08:09:32.30#ibcon#read 6, iclass 5, count 0 2006.210.08:09:32.30#ibcon#end of sib2, iclass 5, count 0 2006.210.08:09:32.30#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:09:32.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:09:32.30#ibcon#[27=BW32\r\n] 2006.210.08:09:32.30#ibcon#*before write, iclass 5, count 0 2006.210.08:09:32.30#ibcon#enter sib2, iclass 5, count 0 2006.210.08:09:32.30#ibcon#flushed, iclass 5, count 0 2006.210.08:09:32.30#ibcon#about to write, iclass 5, count 0 2006.210.08:09:32.30#ibcon#wrote, iclass 5, count 0 2006.210.08:09:32.30#ibcon#about to read 3, iclass 5, count 0 2006.210.08:09:32.33#ibcon#read 3, iclass 5, count 0 2006.210.08:09:32.33#ibcon#about to read 4, iclass 5, count 0 2006.210.08:09:32.33#ibcon#read 4, iclass 5, count 0 2006.210.08:09:32.33#ibcon#about to read 5, iclass 5, count 0 2006.210.08:09:32.33#ibcon#read 5, iclass 5, count 0 2006.210.08:09:32.33#ibcon#about to read 6, iclass 5, count 0 2006.210.08:09:32.33#ibcon#read 6, iclass 5, count 0 2006.210.08:09:32.33#ibcon#end of sib2, iclass 5, count 0 2006.210.08:09:32.33#ibcon#*after write, iclass 5, count 0 2006.210.08:09:32.33#ibcon#*before return 0, iclass 5, count 0 2006.210.08:09:32.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:09:32.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:09:32.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:09:32.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:09:32.33$4f8m12a/ifd4f 2006.210.08:09:32.33$ifd4f/lo= 2006.210.08:09:32.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:09:32.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:09:32.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:09:32.34$ifd4f/patch= 2006.210.08:09:32.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:09:32.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:09:32.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:09:32.34$4f8m12a/"form=m,16.000,1:2 2006.210.08:09:32.34$4f8m12a/"tpicd 2006.210.08:09:32.34$4f8m12a/echo=off 2006.210.08:09:32.34$4f8m12a/xlog=off 2006.210.08:09:32.34:!2006.210.08:10:00 2006.210.08:09:44.14#trakl#Source acquired 2006.210.08:09:45.14#flagr#flagr/antenna,acquired 2006.210.08:10:00.01:preob 2006.210.08:10:01.14/onsource/TRACKING 2006.210.08:10:01.14:!2006.210.08:10:10 2006.210.08:10:10.00:data_valid=on 2006.210.08:10:10.00:midob 2006.210.08:10:10.14/onsource/TRACKING 2006.210.08:10:10.14/wx/30.17,1006.4,83 2006.210.08:10:10.21/cable/+6.3934E-03 2006.210.08:10:11.30/va/01,08,usb,yes,28,30 2006.210.08:10:11.30/va/02,07,usb,yes,29,30 2006.210.08:10:11.30/va/03,06,usb,yes,30,30 2006.210.08:10:11.30/va/04,07,usb,yes,29,32 2006.210.08:10:11.30/va/05,07,usb,yes,31,33 2006.210.08:10:11.30/va/06,06,usb,yes,30,30 2006.210.08:10:11.30/va/07,06,usb,yes,31,30 2006.210.08:10:11.30/va/08,07,usb,yes,29,28 2006.210.08:10:11.53/valo/01,532.99,yes,locked 2006.210.08:10:11.53/valo/02,572.99,yes,locked 2006.210.08:10:11.53/valo/03,672.99,yes,locked 2006.210.08:10:11.53/valo/04,832.99,yes,locked 2006.210.08:10:11.53/valo/05,652.99,yes,locked 2006.210.08:10:11.53/valo/06,772.99,yes,locked 2006.210.08:10:11.53/valo/07,832.99,yes,locked 2006.210.08:10:11.53/valo/08,852.99,yes,locked 2006.210.08:10:12.62/vb/01,04,usb,yes,28,27 2006.210.08:10:12.62/vb/02,04,usb,yes,30,31 2006.210.08:10:12.62/vb/03,03,usb,yes,33,37 2006.210.08:10:12.62/vb/04,03,usb,yes,34,34 2006.210.08:10:12.62/vb/05,03,usb,yes,32,37 2006.210.08:10:12.62/vb/06,03,usb,yes,33,36 2006.210.08:10:12.62/vb/07,04,usb,yes,29,29 2006.210.08:10:12.62/vb/08,03,usb,yes,33,37 2006.210.08:10:12.85/vblo/01,632.99,yes,locked 2006.210.08:10:12.85/vblo/02,640.99,yes,locked 2006.210.08:10:12.85/vblo/03,656.99,yes,locked 2006.210.08:10:12.85/vblo/04,712.99,yes,locked 2006.210.08:10:12.85/vblo/05,744.99,yes,locked 2006.210.08:10:12.85/vblo/06,752.99,yes,locked 2006.210.08:10:12.85/vblo/07,734.99,yes,locked 2006.210.08:10:12.85/vblo/08,744.99,yes,locked 2006.210.08:10:13.00/vabw/8 2006.210.08:10:13.15/vbbw/8 2006.210.08:10:13.24/xfe/off,on,12.7 2006.210.08:10:13.62/ifatt/23,28,28,28 2006.210.08:10:14.07/fmout-gps/S +4.61E-07 2006.210.08:10:14.11:!2006.210.08:11:10 2006.210.08:11:10.01:data_valid=off 2006.210.08:11:10.02:postob 2006.210.08:11:10.22/cable/+6.3914E-03 2006.210.08:11:10.22/wx/30.13,1006.4,82 2006.210.08:11:11.07/fmout-gps/S +4.59E-07 2006.210.08:11:11.07:scan_name=210-0812,k06210,60 2006.210.08:11:11.07:source=3c418,203837.03,511912.7,2000.0,cw 2006.210.08:11:11.14#flagr#flagr/antenna,new-source 2006.210.08:11:12.14:checkk5 2006.210.08:11:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:11:12.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:11:13.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:11:13.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:11:13.85/chk_obsdata//k5ts1/T2100810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:11:14.18/chk_obsdata//k5ts2/T2100810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:11:14.52/chk_obsdata//k5ts3/T2100810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:11:14.85/chk_obsdata//k5ts4/T2100810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:11:15.50/k5log//k5ts1_log_newline 2006.210.08:11:16.16/k5log//k5ts2_log_newline 2006.210.08:11:16.82/k5log//k5ts3_log_newline 2006.210.08:11:17.47/k5log//k5ts4_log_newline 2006.210.08:11:17.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:11:17.50:4f8m12a=2 2006.210.08:11:17.50$4f8m12a/echo=on 2006.210.08:11:17.50$4f8m12a/pcalon 2006.210.08:11:17.50$pcalon/"no phase cal control is implemented here 2006.210.08:11:17.50$4f8m12a/"tpicd=stop 2006.210.08:11:17.50$4f8m12a/vc4f8 2006.210.08:11:17.50$vc4f8/valo=1,532.99 2006.210.08:11:17.50#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.08:11:17.50#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.08:11:17.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:17.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:11:17.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:11:17.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:11:17.50#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:11:17.50#ibcon#first serial, iclass 14, count 0 2006.210.08:11:17.50#ibcon#enter sib2, iclass 14, count 0 2006.210.08:11:17.50#ibcon#flushed, iclass 14, count 0 2006.210.08:11:17.50#ibcon#about to write, iclass 14, count 0 2006.210.08:11:17.50#ibcon#wrote, iclass 14, count 0 2006.210.08:11:17.50#ibcon#about to read 3, iclass 14, count 0 2006.210.08:11:17.51#ibcon#read 3, iclass 14, count 0 2006.210.08:11:17.51#ibcon#about to read 4, iclass 14, count 0 2006.210.08:11:17.51#ibcon#read 4, iclass 14, count 0 2006.210.08:11:17.51#ibcon#about to read 5, iclass 14, count 0 2006.210.08:11:17.51#ibcon#read 5, iclass 14, count 0 2006.210.08:11:17.51#ibcon#about to read 6, iclass 14, count 0 2006.210.08:11:17.51#ibcon#read 6, iclass 14, count 0 2006.210.08:11:17.51#ibcon#end of sib2, iclass 14, count 0 2006.210.08:11:17.51#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:11:17.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:11:17.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:11:17.51#ibcon#*before write, iclass 14, count 0 2006.210.08:11:17.51#ibcon#enter sib2, iclass 14, count 0 2006.210.08:11:17.51#ibcon#flushed, iclass 14, count 0 2006.210.08:11:17.51#ibcon#about to write, iclass 14, count 0 2006.210.08:11:17.51#ibcon#wrote, iclass 14, count 0 2006.210.08:11:17.51#ibcon#about to read 3, iclass 14, count 0 2006.210.08:11:17.56#ibcon#read 3, iclass 14, count 0 2006.210.08:11:17.56#ibcon#about to read 4, iclass 14, count 0 2006.210.08:11:17.56#ibcon#read 4, iclass 14, count 0 2006.210.08:11:17.56#ibcon#about to read 5, iclass 14, count 0 2006.210.08:11:17.56#ibcon#read 5, iclass 14, count 0 2006.210.08:11:17.56#ibcon#about to read 6, iclass 14, count 0 2006.210.08:11:17.56#ibcon#read 6, iclass 14, count 0 2006.210.08:11:17.56#ibcon#end of sib2, iclass 14, count 0 2006.210.08:11:17.56#ibcon#*after write, iclass 14, count 0 2006.210.08:11:17.56#ibcon#*before return 0, iclass 14, count 0 2006.210.08:11:17.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:11:17.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:11:17.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:11:17.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:11:17.56$vc4f8/va=1,8 2006.210.08:11:17.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.08:11:17.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.08:11:17.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:17.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:17.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:17.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:17.56#ibcon#enter wrdev, iclass 16, count 2 2006.210.08:11:17.56#ibcon#first serial, iclass 16, count 2 2006.210.08:11:17.56#ibcon#enter sib2, iclass 16, count 2 2006.210.08:11:17.56#ibcon#flushed, iclass 16, count 2 2006.210.08:11:17.56#ibcon#about to write, iclass 16, count 2 2006.210.08:11:17.56#ibcon#wrote, iclass 16, count 2 2006.210.08:11:17.56#ibcon#about to read 3, iclass 16, count 2 2006.210.08:11:17.58#ibcon#read 3, iclass 16, count 2 2006.210.08:11:17.58#ibcon#about to read 4, iclass 16, count 2 2006.210.08:11:17.58#ibcon#read 4, iclass 16, count 2 2006.210.08:11:17.58#ibcon#about to read 5, iclass 16, count 2 2006.210.08:11:17.58#ibcon#read 5, iclass 16, count 2 2006.210.08:11:17.58#ibcon#about to read 6, iclass 16, count 2 2006.210.08:11:17.58#ibcon#read 6, iclass 16, count 2 2006.210.08:11:17.58#ibcon#end of sib2, iclass 16, count 2 2006.210.08:11:17.58#ibcon#*mode == 0, iclass 16, count 2 2006.210.08:11:17.58#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.08:11:17.58#ibcon#[25=AT01-08\r\n] 2006.210.08:11:17.58#ibcon#*before write, iclass 16, count 2 2006.210.08:11:17.58#ibcon#enter sib2, iclass 16, count 2 2006.210.08:11:17.58#ibcon#flushed, iclass 16, count 2 2006.210.08:11:17.58#ibcon#about to write, iclass 16, count 2 2006.210.08:11:17.58#ibcon#wrote, iclass 16, count 2 2006.210.08:11:17.58#ibcon#about to read 3, iclass 16, count 2 2006.210.08:11:17.61#ibcon#read 3, iclass 16, count 2 2006.210.08:11:17.61#ibcon#about to read 4, iclass 16, count 2 2006.210.08:11:17.61#ibcon#read 4, iclass 16, count 2 2006.210.08:11:17.61#ibcon#about to read 5, iclass 16, count 2 2006.210.08:11:17.61#ibcon#read 5, iclass 16, count 2 2006.210.08:11:17.61#ibcon#about to read 6, iclass 16, count 2 2006.210.08:11:17.61#ibcon#read 6, iclass 16, count 2 2006.210.08:11:17.61#ibcon#end of sib2, iclass 16, count 2 2006.210.08:11:17.61#ibcon#*after write, iclass 16, count 2 2006.210.08:11:17.61#ibcon#*before return 0, iclass 16, count 2 2006.210.08:11:17.61#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:17.61#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:17.61#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.08:11:17.61#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:17.61#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:17.73#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:17.73#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:17.73#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:11:17.73#ibcon#first serial, iclass 16, count 0 2006.210.08:11:17.73#ibcon#enter sib2, iclass 16, count 0 2006.210.08:11:17.73#ibcon#flushed, iclass 16, count 0 2006.210.08:11:17.73#ibcon#about to write, iclass 16, count 0 2006.210.08:11:17.73#ibcon#wrote, iclass 16, count 0 2006.210.08:11:17.73#ibcon#about to read 3, iclass 16, count 0 2006.210.08:11:17.75#ibcon#read 3, iclass 16, count 0 2006.210.08:11:17.75#ibcon#about to read 4, iclass 16, count 0 2006.210.08:11:17.75#ibcon#read 4, iclass 16, count 0 2006.210.08:11:17.75#ibcon#about to read 5, iclass 16, count 0 2006.210.08:11:17.75#ibcon#read 5, iclass 16, count 0 2006.210.08:11:17.75#ibcon#about to read 6, iclass 16, count 0 2006.210.08:11:17.75#ibcon#read 6, iclass 16, count 0 2006.210.08:11:17.75#ibcon#end of sib2, iclass 16, count 0 2006.210.08:11:17.75#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:11:17.75#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:11:17.75#ibcon#[25=USB\r\n] 2006.210.08:11:17.75#ibcon#*before write, iclass 16, count 0 2006.210.08:11:17.75#ibcon#enter sib2, iclass 16, count 0 2006.210.08:11:17.75#ibcon#flushed, iclass 16, count 0 2006.210.08:11:17.75#ibcon#about to write, iclass 16, count 0 2006.210.08:11:17.75#ibcon#wrote, iclass 16, count 0 2006.210.08:11:17.75#ibcon#about to read 3, iclass 16, count 0 2006.210.08:11:17.78#ibcon#read 3, iclass 16, count 0 2006.210.08:11:17.78#ibcon#about to read 4, iclass 16, count 0 2006.210.08:11:17.78#ibcon#read 4, iclass 16, count 0 2006.210.08:11:17.78#ibcon#about to read 5, iclass 16, count 0 2006.210.08:11:17.78#ibcon#read 5, iclass 16, count 0 2006.210.08:11:17.78#ibcon#about to read 6, iclass 16, count 0 2006.210.08:11:17.78#ibcon#read 6, iclass 16, count 0 2006.210.08:11:17.78#ibcon#end of sib2, iclass 16, count 0 2006.210.08:11:17.78#ibcon#*after write, iclass 16, count 0 2006.210.08:11:17.78#ibcon#*before return 0, iclass 16, count 0 2006.210.08:11:17.78#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:17.78#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:17.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:11:17.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:11:17.78$vc4f8/valo=2,572.99 2006.210.08:11:17.78#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.08:11:17.78#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.08:11:17.78#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:17.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:17.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:17.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:17.78#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:11:17.78#ibcon#first serial, iclass 18, count 0 2006.210.08:11:17.78#ibcon#enter sib2, iclass 18, count 0 2006.210.08:11:17.78#ibcon#flushed, iclass 18, count 0 2006.210.08:11:17.78#ibcon#about to write, iclass 18, count 0 2006.210.08:11:17.78#ibcon#wrote, iclass 18, count 0 2006.210.08:11:17.78#ibcon#about to read 3, iclass 18, count 0 2006.210.08:11:17.80#ibcon#read 3, iclass 18, count 0 2006.210.08:11:17.80#ibcon#about to read 4, iclass 18, count 0 2006.210.08:11:17.80#ibcon#read 4, iclass 18, count 0 2006.210.08:11:17.80#ibcon#about to read 5, iclass 18, count 0 2006.210.08:11:17.80#ibcon#read 5, iclass 18, count 0 2006.210.08:11:17.80#ibcon#about to read 6, iclass 18, count 0 2006.210.08:11:17.80#ibcon#read 6, iclass 18, count 0 2006.210.08:11:17.80#ibcon#end of sib2, iclass 18, count 0 2006.210.08:11:17.80#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:11:17.80#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:11:17.80#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:11:17.80#ibcon#*before write, iclass 18, count 0 2006.210.08:11:17.80#ibcon#enter sib2, iclass 18, count 0 2006.210.08:11:17.80#ibcon#flushed, iclass 18, count 0 2006.210.08:11:17.80#ibcon#about to write, iclass 18, count 0 2006.210.08:11:17.80#ibcon#wrote, iclass 18, count 0 2006.210.08:11:17.80#ibcon#about to read 3, iclass 18, count 0 2006.210.08:11:17.84#ibcon#read 3, iclass 18, count 0 2006.210.08:11:17.84#ibcon#about to read 4, iclass 18, count 0 2006.210.08:11:17.84#ibcon#read 4, iclass 18, count 0 2006.210.08:11:17.84#ibcon#about to read 5, iclass 18, count 0 2006.210.08:11:17.84#ibcon#read 5, iclass 18, count 0 2006.210.08:11:17.84#ibcon#about to read 6, iclass 18, count 0 2006.210.08:11:17.84#ibcon#read 6, iclass 18, count 0 2006.210.08:11:17.84#ibcon#end of sib2, iclass 18, count 0 2006.210.08:11:17.84#ibcon#*after write, iclass 18, count 0 2006.210.08:11:17.84#ibcon#*before return 0, iclass 18, count 0 2006.210.08:11:17.84#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:17.84#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:17.84#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:11:17.84#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:11:17.84$vc4f8/va=2,7 2006.210.08:11:17.84#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.08:11:17.84#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.08:11:17.84#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:17.84#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:17.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:17.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:17.90#ibcon#enter wrdev, iclass 20, count 2 2006.210.08:11:17.90#ibcon#first serial, iclass 20, count 2 2006.210.08:11:17.90#ibcon#enter sib2, iclass 20, count 2 2006.210.08:11:17.90#ibcon#flushed, iclass 20, count 2 2006.210.08:11:17.90#ibcon#about to write, iclass 20, count 2 2006.210.08:11:17.90#ibcon#wrote, iclass 20, count 2 2006.210.08:11:17.90#ibcon#about to read 3, iclass 20, count 2 2006.210.08:11:17.92#ibcon#read 3, iclass 20, count 2 2006.210.08:11:17.92#ibcon#about to read 4, iclass 20, count 2 2006.210.08:11:17.92#ibcon#read 4, iclass 20, count 2 2006.210.08:11:17.92#ibcon#about to read 5, iclass 20, count 2 2006.210.08:11:17.92#ibcon#read 5, iclass 20, count 2 2006.210.08:11:17.92#ibcon#about to read 6, iclass 20, count 2 2006.210.08:11:17.92#ibcon#read 6, iclass 20, count 2 2006.210.08:11:17.92#ibcon#end of sib2, iclass 20, count 2 2006.210.08:11:17.92#ibcon#*mode == 0, iclass 20, count 2 2006.210.08:11:17.92#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.08:11:17.92#ibcon#[25=AT02-07\r\n] 2006.210.08:11:17.92#ibcon#*before write, iclass 20, count 2 2006.210.08:11:17.92#ibcon#enter sib2, iclass 20, count 2 2006.210.08:11:17.92#ibcon#flushed, iclass 20, count 2 2006.210.08:11:17.92#ibcon#about to write, iclass 20, count 2 2006.210.08:11:17.92#ibcon#wrote, iclass 20, count 2 2006.210.08:11:17.92#ibcon#about to read 3, iclass 20, count 2 2006.210.08:11:17.95#ibcon#read 3, iclass 20, count 2 2006.210.08:11:17.95#ibcon#about to read 4, iclass 20, count 2 2006.210.08:11:17.95#ibcon#read 4, iclass 20, count 2 2006.210.08:11:17.95#ibcon#about to read 5, iclass 20, count 2 2006.210.08:11:17.95#ibcon#read 5, iclass 20, count 2 2006.210.08:11:17.95#ibcon#about to read 6, iclass 20, count 2 2006.210.08:11:17.95#ibcon#read 6, iclass 20, count 2 2006.210.08:11:17.95#ibcon#end of sib2, iclass 20, count 2 2006.210.08:11:17.95#ibcon#*after write, iclass 20, count 2 2006.210.08:11:17.95#ibcon#*before return 0, iclass 20, count 2 2006.210.08:11:17.95#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:17.95#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:17.95#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.08:11:17.95#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:17.95#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:18.07#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:18.07#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:18.07#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:11:18.07#ibcon#first serial, iclass 20, count 0 2006.210.08:11:18.07#ibcon#enter sib2, iclass 20, count 0 2006.210.08:11:18.07#ibcon#flushed, iclass 20, count 0 2006.210.08:11:18.07#ibcon#about to write, iclass 20, count 0 2006.210.08:11:18.07#ibcon#wrote, iclass 20, count 0 2006.210.08:11:18.07#ibcon#about to read 3, iclass 20, count 0 2006.210.08:11:18.09#ibcon#read 3, iclass 20, count 0 2006.210.08:11:18.09#ibcon#about to read 4, iclass 20, count 0 2006.210.08:11:18.09#ibcon#read 4, iclass 20, count 0 2006.210.08:11:18.09#ibcon#about to read 5, iclass 20, count 0 2006.210.08:11:18.09#ibcon#read 5, iclass 20, count 0 2006.210.08:11:18.09#ibcon#about to read 6, iclass 20, count 0 2006.210.08:11:18.09#ibcon#read 6, iclass 20, count 0 2006.210.08:11:18.09#ibcon#end of sib2, iclass 20, count 0 2006.210.08:11:18.09#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:11:18.09#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:11:18.09#ibcon#[25=USB\r\n] 2006.210.08:11:18.09#ibcon#*before write, iclass 20, count 0 2006.210.08:11:18.09#ibcon#enter sib2, iclass 20, count 0 2006.210.08:11:18.09#ibcon#flushed, iclass 20, count 0 2006.210.08:11:18.09#ibcon#about to write, iclass 20, count 0 2006.210.08:11:18.09#ibcon#wrote, iclass 20, count 0 2006.210.08:11:18.09#ibcon#about to read 3, iclass 20, count 0 2006.210.08:11:18.12#ibcon#read 3, iclass 20, count 0 2006.210.08:11:18.12#ibcon#about to read 4, iclass 20, count 0 2006.210.08:11:18.12#ibcon#read 4, iclass 20, count 0 2006.210.08:11:18.12#ibcon#about to read 5, iclass 20, count 0 2006.210.08:11:18.12#ibcon#read 5, iclass 20, count 0 2006.210.08:11:18.12#ibcon#about to read 6, iclass 20, count 0 2006.210.08:11:18.12#ibcon#read 6, iclass 20, count 0 2006.210.08:11:18.12#ibcon#end of sib2, iclass 20, count 0 2006.210.08:11:18.12#ibcon#*after write, iclass 20, count 0 2006.210.08:11:18.12#ibcon#*before return 0, iclass 20, count 0 2006.210.08:11:18.12#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:18.12#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:18.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:11:18.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:11:18.12$vc4f8/valo=3,672.99 2006.210.08:11:18.12#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.08:11:18.12#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.08:11:18.12#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:18.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:18.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:18.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:18.12#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:11:18.12#ibcon#first serial, iclass 22, count 0 2006.210.08:11:18.12#ibcon#enter sib2, iclass 22, count 0 2006.210.08:11:18.12#ibcon#flushed, iclass 22, count 0 2006.210.08:11:18.12#ibcon#about to write, iclass 22, count 0 2006.210.08:11:18.12#ibcon#wrote, iclass 22, count 0 2006.210.08:11:18.12#ibcon#about to read 3, iclass 22, count 0 2006.210.08:11:18.14#ibcon#read 3, iclass 22, count 0 2006.210.08:11:18.14#ibcon#about to read 4, iclass 22, count 0 2006.210.08:11:18.14#ibcon#read 4, iclass 22, count 0 2006.210.08:11:18.14#ibcon#about to read 5, iclass 22, count 0 2006.210.08:11:18.14#ibcon#read 5, iclass 22, count 0 2006.210.08:11:18.14#ibcon#about to read 6, iclass 22, count 0 2006.210.08:11:18.14#ibcon#read 6, iclass 22, count 0 2006.210.08:11:18.14#ibcon#end of sib2, iclass 22, count 0 2006.210.08:11:18.14#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:11:18.14#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:11:18.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:11:18.14#ibcon#*before write, iclass 22, count 0 2006.210.08:11:18.14#ibcon#enter sib2, iclass 22, count 0 2006.210.08:11:18.14#ibcon#flushed, iclass 22, count 0 2006.210.08:11:18.14#ibcon#about to write, iclass 22, count 0 2006.210.08:11:18.14#ibcon#wrote, iclass 22, count 0 2006.210.08:11:18.14#ibcon#about to read 3, iclass 22, count 0 2006.210.08:11:18.18#ibcon#read 3, iclass 22, count 0 2006.210.08:11:18.18#ibcon#about to read 4, iclass 22, count 0 2006.210.08:11:18.18#ibcon#read 4, iclass 22, count 0 2006.210.08:11:18.18#ibcon#about to read 5, iclass 22, count 0 2006.210.08:11:18.18#ibcon#read 5, iclass 22, count 0 2006.210.08:11:18.18#ibcon#about to read 6, iclass 22, count 0 2006.210.08:11:18.18#ibcon#read 6, iclass 22, count 0 2006.210.08:11:18.18#ibcon#end of sib2, iclass 22, count 0 2006.210.08:11:18.18#ibcon#*after write, iclass 22, count 0 2006.210.08:11:18.18#ibcon#*before return 0, iclass 22, count 0 2006.210.08:11:18.18#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:18.18#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:18.18#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:11:18.18#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:11:18.18$vc4f8/va=3,6 2006.210.08:11:18.18#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.08:11:18.18#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.08:11:18.18#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:18.18#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:18.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:18.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:18.24#ibcon#enter wrdev, iclass 24, count 2 2006.210.08:11:18.24#ibcon#first serial, iclass 24, count 2 2006.210.08:11:18.24#ibcon#enter sib2, iclass 24, count 2 2006.210.08:11:18.24#ibcon#flushed, iclass 24, count 2 2006.210.08:11:18.24#ibcon#about to write, iclass 24, count 2 2006.210.08:11:18.24#ibcon#wrote, iclass 24, count 2 2006.210.08:11:18.24#ibcon#about to read 3, iclass 24, count 2 2006.210.08:11:18.26#ibcon#read 3, iclass 24, count 2 2006.210.08:11:18.26#ibcon#about to read 4, iclass 24, count 2 2006.210.08:11:18.26#ibcon#read 4, iclass 24, count 2 2006.210.08:11:18.26#ibcon#about to read 5, iclass 24, count 2 2006.210.08:11:18.26#ibcon#read 5, iclass 24, count 2 2006.210.08:11:18.26#ibcon#about to read 6, iclass 24, count 2 2006.210.08:11:18.26#ibcon#read 6, iclass 24, count 2 2006.210.08:11:18.26#ibcon#end of sib2, iclass 24, count 2 2006.210.08:11:18.26#ibcon#*mode == 0, iclass 24, count 2 2006.210.08:11:18.26#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.08:11:18.26#ibcon#[25=AT03-06\r\n] 2006.210.08:11:18.26#ibcon#*before write, iclass 24, count 2 2006.210.08:11:18.26#ibcon#enter sib2, iclass 24, count 2 2006.210.08:11:18.26#ibcon#flushed, iclass 24, count 2 2006.210.08:11:18.26#ibcon#about to write, iclass 24, count 2 2006.210.08:11:18.26#ibcon#wrote, iclass 24, count 2 2006.210.08:11:18.26#ibcon#about to read 3, iclass 24, count 2 2006.210.08:11:18.29#ibcon#read 3, iclass 24, count 2 2006.210.08:11:18.29#ibcon#about to read 4, iclass 24, count 2 2006.210.08:11:18.29#ibcon#read 4, iclass 24, count 2 2006.210.08:11:18.29#ibcon#about to read 5, iclass 24, count 2 2006.210.08:11:18.29#ibcon#read 5, iclass 24, count 2 2006.210.08:11:18.29#ibcon#about to read 6, iclass 24, count 2 2006.210.08:11:18.29#ibcon#read 6, iclass 24, count 2 2006.210.08:11:18.29#ibcon#end of sib2, iclass 24, count 2 2006.210.08:11:18.29#ibcon#*after write, iclass 24, count 2 2006.210.08:11:18.29#ibcon#*before return 0, iclass 24, count 2 2006.210.08:11:18.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:18.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:18.29#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.08:11:18.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:18.29#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:18.41#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:18.41#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:18.41#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:11:18.41#ibcon#first serial, iclass 24, count 0 2006.210.08:11:18.41#ibcon#enter sib2, iclass 24, count 0 2006.210.08:11:18.41#ibcon#flushed, iclass 24, count 0 2006.210.08:11:18.41#ibcon#about to write, iclass 24, count 0 2006.210.08:11:18.41#ibcon#wrote, iclass 24, count 0 2006.210.08:11:18.41#ibcon#about to read 3, iclass 24, count 0 2006.210.08:11:18.43#ibcon#read 3, iclass 24, count 0 2006.210.08:11:18.43#ibcon#about to read 4, iclass 24, count 0 2006.210.08:11:18.43#ibcon#read 4, iclass 24, count 0 2006.210.08:11:18.43#ibcon#about to read 5, iclass 24, count 0 2006.210.08:11:18.43#ibcon#read 5, iclass 24, count 0 2006.210.08:11:18.43#ibcon#about to read 6, iclass 24, count 0 2006.210.08:11:18.43#ibcon#read 6, iclass 24, count 0 2006.210.08:11:18.43#ibcon#end of sib2, iclass 24, count 0 2006.210.08:11:18.43#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:11:18.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:11:18.43#ibcon#[25=USB\r\n] 2006.210.08:11:18.43#ibcon#*before write, iclass 24, count 0 2006.210.08:11:18.43#ibcon#enter sib2, iclass 24, count 0 2006.210.08:11:18.43#ibcon#flushed, iclass 24, count 0 2006.210.08:11:18.43#ibcon#about to write, iclass 24, count 0 2006.210.08:11:18.43#ibcon#wrote, iclass 24, count 0 2006.210.08:11:18.43#ibcon#about to read 3, iclass 24, count 0 2006.210.08:11:18.46#ibcon#read 3, iclass 24, count 0 2006.210.08:11:18.46#ibcon#about to read 4, iclass 24, count 0 2006.210.08:11:18.46#ibcon#read 4, iclass 24, count 0 2006.210.08:11:18.46#ibcon#about to read 5, iclass 24, count 0 2006.210.08:11:18.46#ibcon#read 5, iclass 24, count 0 2006.210.08:11:18.46#ibcon#about to read 6, iclass 24, count 0 2006.210.08:11:18.46#ibcon#read 6, iclass 24, count 0 2006.210.08:11:18.46#ibcon#end of sib2, iclass 24, count 0 2006.210.08:11:18.46#ibcon#*after write, iclass 24, count 0 2006.210.08:11:18.46#ibcon#*before return 0, iclass 24, count 0 2006.210.08:11:18.46#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:18.46#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:18.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:11:18.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:11:18.46$vc4f8/valo=4,832.99 2006.210.08:11:18.46#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.08:11:18.46#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.08:11:18.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:18.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:18.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:18.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:18.46#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:11:18.46#ibcon#first serial, iclass 26, count 0 2006.210.08:11:18.46#ibcon#enter sib2, iclass 26, count 0 2006.210.08:11:18.46#ibcon#flushed, iclass 26, count 0 2006.210.08:11:18.46#ibcon#about to write, iclass 26, count 0 2006.210.08:11:18.46#ibcon#wrote, iclass 26, count 0 2006.210.08:11:18.46#ibcon#about to read 3, iclass 26, count 0 2006.210.08:11:18.48#ibcon#read 3, iclass 26, count 0 2006.210.08:11:18.48#ibcon#about to read 4, iclass 26, count 0 2006.210.08:11:18.48#ibcon#read 4, iclass 26, count 0 2006.210.08:11:18.48#ibcon#about to read 5, iclass 26, count 0 2006.210.08:11:18.48#ibcon#read 5, iclass 26, count 0 2006.210.08:11:18.48#ibcon#about to read 6, iclass 26, count 0 2006.210.08:11:18.48#ibcon#read 6, iclass 26, count 0 2006.210.08:11:18.48#ibcon#end of sib2, iclass 26, count 0 2006.210.08:11:18.48#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:11:18.48#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:11:18.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:11:18.48#ibcon#*before write, iclass 26, count 0 2006.210.08:11:18.48#ibcon#enter sib2, iclass 26, count 0 2006.210.08:11:18.48#ibcon#flushed, iclass 26, count 0 2006.210.08:11:18.48#ibcon#about to write, iclass 26, count 0 2006.210.08:11:18.48#ibcon#wrote, iclass 26, count 0 2006.210.08:11:18.48#ibcon#about to read 3, iclass 26, count 0 2006.210.08:11:18.52#ibcon#read 3, iclass 26, count 0 2006.210.08:11:18.52#ibcon#about to read 4, iclass 26, count 0 2006.210.08:11:18.52#ibcon#read 4, iclass 26, count 0 2006.210.08:11:18.52#ibcon#about to read 5, iclass 26, count 0 2006.210.08:11:18.52#ibcon#read 5, iclass 26, count 0 2006.210.08:11:18.52#ibcon#about to read 6, iclass 26, count 0 2006.210.08:11:18.52#ibcon#read 6, iclass 26, count 0 2006.210.08:11:18.52#ibcon#end of sib2, iclass 26, count 0 2006.210.08:11:18.52#ibcon#*after write, iclass 26, count 0 2006.210.08:11:18.52#ibcon#*before return 0, iclass 26, count 0 2006.210.08:11:18.52#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:18.52#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:18.52#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:11:18.52#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:11:18.52$vc4f8/va=4,7 2006.210.08:11:18.52#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.08:11:18.52#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.08:11:18.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:18.52#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:18.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:18.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:18.58#ibcon#enter wrdev, iclass 28, count 2 2006.210.08:11:18.58#ibcon#first serial, iclass 28, count 2 2006.210.08:11:18.58#ibcon#enter sib2, iclass 28, count 2 2006.210.08:11:18.58#ibcon#flushed, iclass 28, count 2 2006.210.08:11:18.58#ibcon#about to write, iclass 28, count 2 2006.210.08:11:18.58#ibcon#wrote, iclass 28, count 2 2006.210.08:11:18.58#ibcon#about to read 3, iclass 28, count 2 2006.210.08:11:18.60#ibcon#read 3, iclass 28, count 2 2006.210.08:11:18.60#ibcon#about to read 4, iclass 28, count 2 2006.210.08:11:18.60#ibcon#read 4, iclass 28, count 2 2006.210.08:11:18.60#ibcon#about to read 5, iclass 28, count 2 2006.210.08:11:18.60#ibcon#read 5, iclass 28, count 2 2006.210.08:11:18.60#ibcon#about to read 6, iclass 28, count 2 2006.210.08:11:18.60#ibcon#read 6, iclass 28, count 2 2006.210.08:11:18.60#ibcon#end of sib2, iclass 28, count 2 2006.210.08:11:18.60#ibcon#*mode == 0, iclass 28, count 2 2006.210.08:11:18.60#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.08:11:18.60#ibcon#[25=AT04-07\r\n] 2006.210.08:11:18.60#ibcon#*before write, iclass 28, count 2 2006.210.08:11:18.60#ibcon#enter sib2, iclass 28, count 2 2006.210.08:11:18.60#ibcon#flushed, iclass 28, count 2 2006.210.08:11:18.60#ibcon#about to write, iclass 28, count 2 2006.210.08:11:18.60#ibcon#wrote, iclass 28, count 2 2006.210.08:11:18.60#ibcon#about to read 3, iclass 28, count 2 2006.210.08:11:18.63#ibcon#read 3, iclass 28, count 2 2006.210.08:11:18.63#ibcon#about to read 4, iclass 28, count 2 2006.210.08:11:18.63#ibcon#read 4, iclass 28, count 2 2006.210.08:11:18.63#ibcon#about to read 5, iclass 28, count 2 2006.210.08:11:18.63#ibcon#read 5, iclass 28, count 2 2006.210.08:11:18.63#ibcon#about to read 6, iclass 28, count 2 2006.210.08:11:18.63#ibcon#read 6, iclass 28, count 2 2006.210.08:11:18.63#ibcon#end of sib2, iclass 28, count 2 2006.210.08:11:18.63#ibcon#*after write, iclass 28, count 2 2006.210.08:11:18.63#ibcon#*before return 0, iclass 28, count 2 2006.210.08:11:18.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:18.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:18.63#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.08:11:18.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:18.63#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:18.75#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:18.75#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:18.75#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:11:18.75#ibcon#first serial, iclass 28, count 0 2006.210.08:11:18.75#ibcon#enter sib2, iclass 28, count 0 2006.210.08:11:18.75#ibcon#flushed, iclass 28, count 0 2006.210.08:11:18.75#ibcon#about to write, iclass 28, count 0 2006.210.08:11:18.75#ibcon#wrote, iclass 28, count 0 2006.210.08:11:18.75#ibcon#about to read 3, iclass 28, count 0 2006.210.08:11:18.77#ibcon#read 3, iclass 28, count 0 2006.210.08:11:18.77#ibcon#about to read 4, iclass 28, count 0 2006.210.08:11:18.77#ibcon#read 4, iclass 28, count 0 2006.210.08:11:18.77#ibcon#about to read 5, iclass 28, count 0 2006.210.08:11:18.77#ibcon#read 5, iclass 28, count 0 2006.210.08:11:18.77#ibcon#about to read 6, iclass 28, count 0 2006.210.08:11:18.77#ibcon#read 6, iclass 28, count 0 2006.210.08:11:18.77#ibcon#end of sib2, iclass 28, count 0 2006.210.08:11:18.77#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:11:18.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:11:18.77#ibcon#[25=USB\r\n] 2006.210.08:11:18.77#ibcon#*before write, iclass 28, count 0 2006.210.08:11:18.77#ibcon#enter sib2, iclass 28, count 0 2006.210.08:11:18.77#ibcon#flushed, iclass 28, count 0 2006.210.08:11:18.77#ibcon#about to write, iclass 28, count 0 2006.210.08:11:18.77#ibcon#wrote, iclass 28, count 0 2006.210.08:11:18.77#ibcon#about to read 3, iclass 28, count 0 2006.210.08:11:18.80#ibcon#read 3, iclass 28, count 0 2006.210.08:11:18.80#ibcon#about to read 4, iclass 28, count 0 2006.210.08:11:18.80#ibcon#read 4, iclass 28, count 0 2006.210.08:11:18.80#ibcon#about to read 5, iclass 28, count 0 2006.210.08:11:18.80#ibcon#read 5, iclass 28, count 0 2006.210.08:11:18.80#ibcon#about to read 6, iclass 28, count 0 2006.210.08:11:18.80#ibcon#read 6, iclass 28, count 0 2006.210.08:11:18.80#ibcon#end of sib2, iclass 28, count 0 2006.210.08:11:18.80#ibcon#*after write, iclass 28, count 0 2006.210.08:11:18.80#ibcon#*before return 0, iclass 28, count 0 2006.210.08:11:18.80#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:18.80#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:18.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:11:18.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:11:18.80$vc4f8/valo=5,652.99 2006.210.08:11:18.80#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.08:11:18.80#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.08:11:18.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:18.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:18.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:18.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:18.80#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:11:18.80#ibcon#first serial, iclass 30, count 0 2006.210.08:11:18.80#ibcon#enter sib2, iclass 30, count 0 2006.210.08:11:18.80#ibcon#flushed, iclass 30, count 0 2006.210.08:11:18.80#ibcon#about to write, iclass 30, count 0 2006.210.08:11:18.80#ibcon#wrote, iclass 30, count 0 2006.210.08:11:18.80#ibcon#about to read 3, iclass 30, count 0 2006.210.08:11:18.82#ibcon#read 3, iclass 30, count 0 2006.210.08:11:18.82#ibcon#about to read 4, iclass 30, count 0 2006.210.08:11:18.82#ibcon#read 4, iclass 30, count 0 2006.210.08:11:18.82#ibcon#about to read 5, iclass 30, count 0 2006.210.08:11:18.82#ibcon#read 5, iclass 30, count 0 2006.210.08:11:18.82#ibcon#about to read 6, iclass 30, count 0 2006.210.08:11:18.82#ibcon#read 6, iclass 30, count 0 2006.210.08:11:18.82#ibcon#end of sib2, iclass 30, count 0 2006.210.08:11:18.82#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:11:18.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:11:18.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:11:18.82#ibcon#*before write, iclass 30, count 0 2006.210.08:11:18.82#ibcon#enter sib2, iclass 30, count 0 2006.210.08:11:18.82#ibcon#flushed, iclass 30, count 0 2006.210.08:11:18.82#ibcon#about to write, iclass 30, count 0 2006.210.08:11:18.82#ibcon#wrote, iclass 30, count 0 2006.210.08:11:18.82#ibcon#about to read 3, iclass 30, count 0 2006.210.08:11:18.86#ibcon#read 3, iclass 30, count 0 2006.210.08:11:18.86#ibcon#about to read 4, iclass 30, count 0 2006.210.08:11:18.86#ibcon#read 4, iclass 30, count 0 2006.210.08:11:18.86#ibcon#about to read 5, iclass 30, count 0 2006.210.08:11:18.86#ibcon#read 5, iclass 30, count 0 2006.210.08:11:18.86#ibcon#about to read 6, iclass 30, count 0 2006.210.08:11:18.86#ibcon#read 6, iclass 30, count 0 2006.210.08:11:18.86#ibcon#end of sib2, iclass 30, count 0 2006.210.08:11:18.86#ibcon#*after write, iclass 30, count 0 2006.210.08:11:18.86#ibcon#*before return 0, iclass 30, count 0 2006.210.08:11:18.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:18.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:18.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:11:18.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:11:18.86$vc4f8/va=5,7 2006.210.08:11:18.86#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.08:11:18.86#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.08:11:18.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:18.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:18.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:18.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:18.92#ibcon#enter wrdev, iclass 32, count 2 2006.210.08:11:18.92#ibcon#first serial, iclass 32, count 2 2006.210.08:11:18.92#ibcon#enter sib2, iclass 32, count 2 2006.210.08:11:18.92#ibcon#flushed, iclass 32, count 2 2006.210.08:11:18.92#ibcon#about to write, iclass 32, count 2 2006.210.08:11:18.92#ibcon#wrote, iclass 32, count 2 2006.210.08:11:18.92#ibcon#about to read 3, iclass 32, count 2 2006.210.08:11:18.94#ibcon#read 3, iclass 32, count 2 2006.210.08:11:18.94#ibcon#about to read 4, iclass 32, count 2 2006.210.08:11:18.94#ibcon#read 4, iclass 32, count 2 2006.210.08:11:18.94#ibcon#about to read 5, iclass 32, count 2 2006.210.08:11:18.94#ibcon#read 5, iclass 32, count 2 2006.210.08:11:18.94#ibcon#about to read 6, iclass 32, count 2 2006.210.08:11:18.94#ibcon#read 6, iclass 32, count 2 2006.210.08:11:18.94#ibcon#end of sib2, iclass 32, count 2 2006.210.08:11:18.94#ibcon#*mode == 0, iclass 32, count 2 2006.210.08:11:18.94#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.08:11:18.94#ibcon#[25=AT05-07\r\n] 2006.210.08:11:18.94#ibcon#*before write, iclass 32, count 2 2006.210.08:11:18.94#ibcon#enter sib2, iclass 32, count 2 2006.210.08:11:18.94#ibcon#flushed, iclass 32, count 2 2006.210.08:11:18.94#ibcon#about to write, iclass 32, count 2 2006.210.08:11:18.94#ibcon#wrote, iclass 32, count 2 2006.210.08:11:18.94#ibcon#about to read 3, iclass 32, count 2 2006.210.08:11:18.97#ibcon#read 3, iclass 32, count 2 2006.210.08:11:18.97#ibcon#about to read 4, iclass 32, count 2 2006.210.08:11:18.97#ibcon#read 4, iclass 32, count 2 2006.210.08:11:18.97#ibcon#about to read 5, iclass 32, count 2 2006.210.08:11:18.97#ibcon#read 5, iclass 32, count 2 2006.210.08:11:18.97#ibcon#about to read 6, iclass 32, count 2 2006.210.08:11:18.97#ibcon#read 6, iclass 32, count 2 2006.210.08:11:18.97#ibcon#end of sib2, iclass 32, count 2 2006.210.08:11:18.97#ibcon#*after write, iclass 32, count 2 2006.210.08:11:18.97#ibcon#*before return 0, iclass 32, count 2 2006.210.08:11:18.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:18.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:18.97#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.08:11:18.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:18.97#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:19.09#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:19.09#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:19.09#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:11:19.09#ibcon#first serial, iclass 32, count 0 2006.210.08:11:19.09#ibcon#enter sib2, iclass 32, count 0 2006.210.08:11:19.09#ibcon#flushed, iclass 32, count 0 2006.210.08:11:19.09#ibcon#about to write, iclass 32, count 0 2006.210.08:11:19.09#ibcon#wrote, iclass 32, count 0 2006.210.08:11:19.09#ibcon#about to read 3, iclass 32, count 0 2006.210.08:11:19.11#ibcon#read 3, iclass 32, count 0 2006.210.08:11:19.11#ibcon#about to read 4, iclass 32, count 0 2006.210.08:11:19.11#ibcon#read 4, iclass 32, count 0 2006.210.08:11:19.11#ibcon#about to read 5, iclass 32, count 0 2006.210.08:11:19.11#ibcon#read 5, iclass 32, count 0 2006.210.08:11:19.11#ibcon#about to read 6, iclass 32, count 0 2006.210.08:11:19.11#ibcon#read 6, iclass 32, count 0 2006.210.08:11:19.11#ibcon#end of sib2, iclass 32, count 0 2006.210.08:11:19.11#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:11:19.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:11:19.11#ibcon#[25=USB\r\n] 2006.210.08:11:19.11#ibcon#*before write, iclass 32, count 0 2006.210.08:11:19.11#ibcon#enter sib2, iclass 32, count 0 2006.210.08:11:19.11#ibcon#flushed, iclass 32, count 0 2006.210.08:11:19.11#ibcon#about to write, iclass 32, count 0 2006.210.08:11:19.11#ibcon#wrote, iclass 32, count 0 2006.210.08:11:19.11#ibcon#about to read 3, iclass 32, count 0 2006.210.08:11:19.14#ibcon#read 3, iclass 32, count 0 2006.210.08:11:19.14#ibcon#about to read 4, iclass 32, count 0 2006.210.08:11:19.14#ibcon#read 4, iclass 32, count 0 2006.210.08:11:19.14#ibcon#about to read 5, iclass 32, count 0 2006.210.08:11:19.14#ibcon#read 5, iclass 32, count 0 2006.210.08:11:19.14#ibcon#about to read 6, iclass 32, count 0 2006.210.08:11:19.14#ibcon#read 6, iclass 32, count 0 2006.210.08:11:19.14#ibcon#end of sib2, iclass 32, count 0 2006.210.08:11:19.14#ibcon#*after write, iclass 32, count 0 2006.210.08:11:19.14#ibcon#*before return 0, iclass 32, count 0 2006.210.08:11:19.14#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:19.14#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:19.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:11:19.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:11:19.14$vc4f8/valo=6,772.99 2006.210.08:11:19.15#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:11:19.15#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:11:19.15#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:19.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:19.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:19.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:19.15#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:11:19.15#ibcon#first serial, iclass 34, count 0 2006.210.08:11:19.15#ibcon#enter sib2, iclass 34, count 0 2006.210.08:11:19.15#ibcon#flushed, iclass 34, count 0 2006.210.08:11:19.15#ibcon#about to write, iclass 34, count 0 2006.210.08:11:19.15#ibcon#wrote, iclass 34, count 0 2006.210.08:11:19.15#ibcon#about to read 3, iclass 34, count 0 2006.210.08:11:19.16#ibcon#read 3, iclass 34, count 0 2006.210.08:11:19.16#ibcon#about to read 4, iclass 34, count 0 2006.210.08:11:19.16#ibcon#read 4, iclass 34, count 0 2006.210.08:11:19.16#ibcon#about to read 5, iclass 34, count 0 2006.210.08:11:19.16#ibcon#read 5, iclass 34, count 0 2006.210.08:11:19.16#ibcon#about to read 6, iclass 34, count 0 2006.210.08:11:19.16#ibcon#read 6, iclass 34, count 0 2006.210.08:11:19.16#ibcon#end of sib2, iclass 34, count 0 2006.210.08:11:19.16#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:11:19.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:11:19.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:11:19.16#ibcon#*before write, iclass 34, count 0 2006.210.08:11:19.16#ibcon#enter sib2, iclass 34, count 0 2006.210.08:11:19.16#ibcon#flushed, iclass 34, count 0 2006.210.08:11:19.16#ibcon#about to write, iclass 34, count 0 2006.210.08:11:19.16#ibcon#wrote, iclass 34, count 0 2006.210.08:11:19.16#ibcon#about to read 3, iclass 34, count 0 2006.210.08:11:19.20#ibcon#read 3, iclass 34, count 0 2006.210.08:11:19.20#ibcon#about to read 4, iclass 34, count 0 2006.210.08:11:19.20#ibcon#read 4, iclass 34, count 0 2006.210.08:11:19.20#ibcon#about to read 5, iclass 34, count 0 2006.210.08:11:19.20#ibcon#read 5, iclass 34, count 0 2006.210.08:11:19.20#ibcon#about to read 6, iclass 34, count 0 2006.210.08:11:19.20#ibcon#read 6, iclass 34, count 0 2006.210.08:11:19.20#ibcon#end of sib2, iclass 34, count 0 2006.210.08:11:19.20#ibcon#*after write, iclass 34, count 0 2006.210.08:11:19.20#ibcon#*before return 0, iclass 34, count 0 2006.210.08:11:19.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:19.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:19.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:11:19.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:11:19.20$vc4f8/va=6,6 2006.210.08:11:19.20#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.08:11:19.20#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.08:11:19.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:19.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:19.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:19.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:19.26#ibcon#enter wrdev, iclass 36, count 2 2006.210.08:11:19.26#ibcon#first serial, iclass 36, count 2 2006.210.08:11:19.26#ibcon#enter sib2, iclass 36, count 2 2006.210.08:11:19.26#ibcon#flushed, iclass 36, count 2 2006.210.08:11:19.26#ibcon#about to write, iclass 36, count 2 2006.210.08:11:19.26#ibcon#wrote, iclass 36, count 2 2006.210.08:11:19.26#ibcon#about to read 3, iclass 36, count 2 2006.210.08:11:19.28#ibcon#read 3, iclass 36, count 2 2006.210.08:11:19.28#ibcon#about to read 4, iclass 36, count 2 2006.210.08:11:19.28#ibcon#read 4, iclass 36, count 2 2006.210.08:11:19.28#ibcon#about to read 5, iclass 36, count 2 2006.210.08:11:19.28#ibcon#read 5, iclass 36, count 2 2006.210.08:11:19.28#ibcon#about to read 6, iclass 36, count 2 2006.210.08:11:19.28#ibcon#read 6, iclass 36, count 2 2006.210.08:11:19.28#ibcon#end of sib2, iclass 36, count 2 2006.210.08:11:19.28#ibcon#*mode == 0, iclass 36, count 2 2006.210.08:11:19.28#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.08:11:19.28#ibcon#[25=AT06-06\r\n] 2006.210.08:11:19.28#ibcon#*before write, iclass 36, count 2 2006.210.08:11:19.28#ibcon#enter sib2, iclass 36, count 2 2006.210.08:11:19.28#ibcon#flushed, iclass 36, count 2 2006.210.08:11:19.28#ibcon#about to write, iclass 36, count 2 2006.210.08:11:19.28#ibcon#wrote, iclass 36, count 2 2006.210.08:11:19.28#ibcon#about to read 3, iclass 36, count 2 2006.210.08:11:19.31#ibcon#read 3, iclass 36, count 2 2006.210.08:11:19.31#ibcon#about to read 4, iclass 36, count 2 2006.210.08:11:19.31#ibcon#read 4, iclass 36, count 2 2006.210.08:11:19.31#ibcon#about to read 5, iclass 36, count 2 2006.210.08:11:19.31#ibcon#read 5, iclass 36, count 2 2006.210.08:11:19.31#ibcon#about to read 6, iclass 36, count 2 2006.210.08:11:19.31#ibcon#read 6, iclass 36, count 2 2006.210.08:11:19.31#ibcon#end of sib2, iclass 36, count 2 2006.210.08:11:19.31#ibcon#*after write, iclass 36, count 2 2006.210.08:11:19.31#ibcon#*before return 0, iclass 36, count 2 2006.210.08:11:19.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:19.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:19.31#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.08:11:19.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:19.31#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:19.43#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:19.43#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:19.43#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:11:19.43#ibcon#first serial, iclass 36, count 0 2006.210.08:11:19.43#ibcon#enter sib2, iclass 36, count 0 2006.210.08:11:19.43#ibcon#flushed, iclass 36, count 0 2006.210.08:11:19.43#ibcon#about to write, iclass 36, count 0 2006.210.08:11:19.43#ibcon#wrote, iclass 36, count 0 2006.210.08:11:19.43#ibcon#about to read 3, iclass 36, count 0 2006.210.08:11:19.45#ibcon#read 3, iclass 36, count 0 2006.210.08:11:19.45#ibcon#about to read 4, iclass 36, count 0 2006.210.08:11:19.45#ibcon#read 4, iclass 36, count 0 2006.210.08:11:19.45#ibcon#about to read 5, iclass 36, count 0 2006.210.08:11:19.45#ibcon#read 5, iclass 36, count 0 2006.210.08:11:19.45#ibcon#about to read 6, iclass 36, count 0 2006.210.08:11:19.45#ibcon#read 6, iclass 36, count 0 2006.210.08:11:19.45#ibcon#end of sib2, iclass 36, count 0 2006.210.08:11:19.45#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:11:19.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:11:19.45#ibcon#[25=USB\r\n] 2006.210.08:11:19.45#ibcon#*before write, iclass 36, count 0 2006.210.08:11:19.45#ibcon#enter sib2, iclass 36, count 0 2006.210.08:11:19.45#ibcon#flushed, iclass 36, count 0 2006.210.08:11:19.45#ibcon#about to write, iclass 36, count 0 2006.210.08:11:19.45#ibcon#wrote, iclass 36, count 0 2006.210.08:11:19.45#ibcon#about to read 3, iclass 36, count 0 2006.210.08:11:19.48#ibcon#read 3, iclass 36, count 0 2006.210.08:11:19.48#ibcon#about to read 4, iclass 36, count 0 2006.210.08:11:19.48#ibcon#read 4, iclass 36, count 0 2006.210.08:11:19.48#ibcon#about to read 5, iclass 36, count 0 2006.210.08:11:19.48#ibcon#read 5, iclass 36, count 0 2006.210.08:11:19.48#ibcon#about to read 6, iclass 36, count 0 2006.210.08:11:19.48#ibcon#read 6, iclass 36, count 0 2006.210.08:11:19.48#ibcon#end of sib2, iclass 36, count 0 2006.210.08:11:19.48#ibcon#*after write, iclass 36, count 0 2006.210.08:11:19.48#ibcon#*before return 0, iclass 36, count 0 2006.210.08:11:19.48#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:19.48#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:19.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:11:19.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:11:19.48$vc4f8/valo=7,832.99 2006.210.08:11:19.48#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.08:11:19.48#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.08:11:19.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:19.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:19.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:19.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:19.48#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:11:19.48#ibcon#first serial, iclass 38, count 0 2006.210.08:11:19.48#ibcon#enter sib2, iclass 38, count 0 2006.210.08:11:19.48#ibcon#flushed, iclass 38, count 0 2006.210.08:11:19.48#ibcon#about to write, iclass 38, count 0 2006.210.08:11:19.48#ibcon#wrote, iclass 38, count 0 2006.210.08:11:19.48#ibcon#about to read 3, iclass 38, count 0 2006.210.08:11:19.50#ibcon#read 3, iclass 38, count 0 2006.210.08:11:19.50#ibcon#about to read 4, iclass 38, count 0 2006.210.08:11:19.50#ibcon#read 4, iclass 38, count 0 2006.210.08:11:19.50#ibcon#about to read 5, iclass 38, count 0 2006.210.08:11:19.50#ibcon#read 5, iclass 38, count 0 2006.210.08:11:19.50#ibcon#about to read 6, iclass 38, count 0 2006.210.08:11:19.50#ibcon#read 6, iclass 38, count 0 2006.210.08:11:19.50#ibcon#end of sib2, iclass 38, count 0 2006.210.08:11:19.50#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:11:19.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:11:19.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:11:19.50#ibcon#*before write, iclass 38, count 0 2006.210.08:11:19.50#ibcon#enter sib2, iclass 38, count 0 2006.210.08:11:19.50#ibcon#flushed, iclass 38, count 0 2006.210.08:11:19.50#ibcon#about to write, iclass 38, count 0 2006.210.08:11:19.50#ibcon#wrote, iclass 38, count 0 2006.210.08:11:19.50#ibcon#about to read 3, iclass 38, count 0 2006.210.08:11:19.54#ibcon#read 3, iclass 38, count 0 2006.210.08:11:19.54#ibcon#about to read 4, iclass 38, count 0 2006.210.08:11:19.54#ibcon#read 4, iclass 38, count 0 2006.210.08:11:19.54#ibcon#about to read 5, iclass 38, count 0 2006.210.08:11:19.54#ibcon#read 5, iclass 38, count 0 2006.210.08:11:19.54#ibcon#about to read 6, iclass 38, count 0 2006.210.08:11:19.54#ibcon#read 6, iclass 38, count 0 2006.210.08:11:19.54#ibcon#end of sib2, iclass 38, count 0 2006.210.08:11:19.54#ibcon#*after write, iclass 38, count 0 2006.210.08:11:19.54#ibcon#*before return 0, iclass 38, count 0 2006.210.08:11:19.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:19.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:19.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:11:19.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:11:19.54$vc4f8/va=7,6 2006.210.08:11:19.54#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.08:11:19.54#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.08:11:19.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:19.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:11:19.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:11:19.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:11:19.60#ibcon#enter wrdev, iclass 40, count 2 2006.210.08:11:19.60#ibcon#first serial, iclass 40, count 2 2006.210.08:11:19.60#ibcon#enter sib2, iclass 40, count 2 2006.210.08:11:19.60#ibcon#flushed, iclass 40, count 2 2006.210.08:11:19.60#ibcon#about to write, iclass 40, count 2 2006.210.08:11:19.60#ibcon#wrote, iclass 40, count 2 2006.210.08:11:19.60#ibcon#about to read 3, iclass 40, count 2 2006.210.08:11:19.62#ibcon#read 3, iclass 40, count 2 2006.210.08:11:19.62#ibcon#about to read 4, iclass 40, count 2 2006.210.08:11:19.62#ibcon#read 4, iclass 40, count 2 2006.210.08:11:19.62#ibcon#about to read 5, iclass 40, count 2 2006.210.08:11:19.62#ibcon#read 5, iclass 40, count 2 2006.210.08:11:19.62#ibcon#about to read 6, iclass 40, count 2 2006.210.08:11:19.62#ibcon#read 6, iclass 40, count 2 2006.210.08:11:19.62#ibcon#end of sib2, iclass 40, count 2 2006.210.08:11:19.62#ibcon#*mode == 0, iclass 40, count 2 2006.210.08:11:19.62#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.08:11:19.62#ibcon#[25=AT07-06\r\n] 2006.210.08:11:19.62#ibcon#*before write, iclass 40, count 2 2006.210.08:11:19.62#ibcon#enter sib2, iclass 40, count 2 2006.210.08:11:19.62#ibcon#flushed, iclass 40, count 2 2006.210.08:11:19.62#ibcon#about to write, iclass 40, count 2 2006.210.08:11:19.62#ibcon#wrote, iclass 40, count 2 2006.210.08:11:19.62#ibcon#about to read 3, iclass 40, count 2 2006.210.08:11:19.65#ibcon#read 3, iclass 40, count 2 2006.210.08:11:19.65#ibcon#about to read 4, iclass 40, count 2 2006.210.08:11:19.65#ibcon#read 4, iclass 40, count 2 2006.210.08:11:19.65#ibcon#about to read 5, iclass 40, count 2 2006.210.08:11:19.65#ibcon#read 5, iclass 40, count 2 2006.210.08:11:19.65#ibcon#about to read 6, iclass 40, count 2 2006.210.08:11:19.65#ibcon#read 6, iclass 40, count 2 2006.210.08:11:19.65#ibcon#end of sib2, iclass 40, count 2 2006.210.08:11:19.65#ibcon#*after write, iclass 40, count 2 2006.210.08:11:19.65#ibcon#*before return 0, iclass 40, count 2 2006.210.08:11:19.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:11:19.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:11:19.65#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.08:11:19.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:19.65#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:11:19.77#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:11:19.77#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:11:19.77#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:11:19.77#ibcon#first serial, iclass 40, count 0 2006.210.08:11:19.77#ibcon#enter sib2, iclass 40, count 0 2006.210.08:11:19.77#ibcon#flushed, iclass 40, count 0 2006.210.08:11:19.77#ibcon#about to write, iclass 40, count 0 2006.210.08:11:19.77#ibcon#wrote, iclass 40, count 0 2006.210.08:11:19.77#ibcon#about to read 3, iclass 40, count 0 2006.210.08:11:19.79#ibcon#read 3, iclass 40, count 0 2006.210.08:11:19.79#ibcon#about to read 4, iclass 40, count 0 2006.210.08:11:19.79#ibcon#read 4, iclass 40, count 0 2006.210.08:11:19.79#ibcon#about to read 5, iclass 40, count 0 2006.210.08:11:19.79#ibcon#read 5, iclass 40, count 0 2006.210.08:11:19.79#ibcon#about to read 6, iclass 40, count 0 2006.210.08:11:19.79#ibcon#read 6, iclass 40, count 0 2006.210.08:11:19.79#ibcon#end of sib2, iclass 40, count 0 2006.210.08:11:19.79#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:11:19.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:11:19.79#ibcon#[25=USB\r\n] 2006.210.08:11:19.79#ibcon#*before write, iclass 40, count 0 2006.210.08:11:19.79#ibcon#enter sib2, iclass 40, count 0 2006.210.08:11:19.79#ibcon#flushed, iclass 40, count 0 2006.210.08:11:19.79#ibcon#about to write, iclass 40, count 0 2006.210.08:11:19.79#ibcon#wrote, iclass 40, count 0 2006.210.08:11:19.79#ibcon#about to read 3, iclass 40, count 0 2006.210.08:11:19.82#ibcon#read 3, iclass 40, count 0 2006.210.08:11:19.82#ibcon#about to read 4, iclass 40, count 0 2006.210.08:11:19.82#ibcon#read 4, iclass 40, count 0 2006.210.08:11:19.82#ibcon#about to read 5, iclass 40, count 0 2006.210.08:11:19.82#ibcon#read 5, iclass 40, count 0 2006.210.08:11:19.82#ibcon#about to read 6, iclass 40, count 0 2006.210.08:11:19.82#ibcon#read 6, iclass 40, count 0 2006.210.08:11:19.82#ibcon#end of sib2, iclass 40, count 0 2006.210.08:11:19.82#ibcon#*after write, iclass 40, count 0 2006.210.08:11:19.82#ibcon#*before return 0, iclass 40, count 0 2006.210.08:11:19.82#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:11:19.82#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:11:19.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:11:19.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:11:19.82$vc4f8/valo=8,852.99 2006.210.08:11:19.82#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.08:11:19.82#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.08:11:19.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:19.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:11:19.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:11:19.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:11:19.82#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:11:19.82#ibcon#first serial, iclass 4, count 0 2006.210.08:11:19.82#ibcon#enter sib2, iclass 4, count 0 2006.210.08:11:19.82#ibcon#flushed, iclass 4, count 0 2006.210.08:11:19.82#ibcon#about to write, iclass 4, count 0 2006.210.08:11:19.82#ibcon#wrote, iclass 4, count 0 2006.210.08:11:19.82#ibcon#about to read 3, iclass 4, count 0 2006.210.08:11:19.84#ibcon#read 3, iclass 4, count 0 2006.210.08:11:19.84#ibcon#about to read 4, iclass 4, count 0 2006.210.08:11:19.84#ibcon#read 4, iclass 4, count 0 2006.210.08:11:19.84#ibcon#about to read 5, iclass 4, count 0 2006.210.08:11:19.84#ibcon#read 5, iclass 4, count 0 2006.210.08:11:19.84#ibcon#about to read 6, iclass 4, count 0 2006.210.08:11:19.84#ibcon#read 6, iclass 4, count 0 2006.210.08:11:19.84#ibcon#end of sib2, iclass 4, count 0 2006.210.08:11:19.84#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:11:19.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:11:19.84#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:11:19.84#ibcon#*before write, iclass 4, count 0 2006.210.08:11:19.84#ibcon#enter sib2, iclass 4, count 0 2006.210.08:11:19.84#ibcon#flushed, iclass 4, count 0 2006.210.08:11:19.84#ibcon#about to write, iclass 4, count 0 2006.210.08:11:19.84#ibcon#wrote, iclass 4, count 0 2006.210.08:11:19.84#ibcon#about to read 3, iclass 4, count 0 2006.210.08:11:19.88#ibcon#read 3, iclass 4, count 0 2006.210.08:11:19.88#ibcon#about to read 4, iclass 4, count 0 2006.210.08:11:19.88#ibcon#read 4, iclass 4, count 0 2006.210.08:11:19.88#ibcon#about to read 5, iclass 4, count 0 2006.210.08:11:19.88#ibcon#read 5, iclass 4, count 0 2006.210.08:11:19.88#ibcon#about to read 6, iclass 4, count 0 2006.210.08:11:19.88#ibcon#read 6, iclass 4, count 0 2006.210.08:11:19.88#ibcon#end of sib2, iclass 4, count 0 2006.210.08:11:19.88#ibcon#*after write, iclass 4, count 0 2006.210.08:11:19.88#ibcon#*before return 0, iclass 4, count 0 2006.210.08:11:19.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:11:19.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:11:19.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:11:19.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:11:19.88$vc4f8/va=8,7 2006.210.08:11:19.88#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.08:11:19.88#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.08:11:19.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:19.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:11:19.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:11:19.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:11:19.94#ibcon#enter wrdev, iclass 6, count 2 2006.210.08:11:19.94#ibcon#first serial, iclass 6, count 2 2006.210.08:11:19.94#ibcon#enter sib2, iclass 6, count 2 2006.210.08:11:19.94#ibcon#flushed, iclass 6, count 2 2006.210.08:11:19.94#ibcon#about to write, iclass 6, count 2 2006.210.08:11:19.94#ibcon#wrote, iclass 6, count 2 2006.210.08:11:19.94#ibcon#about to read 3, iclass 6, count 2 2006.210.08:11:19.96#ibcon#read 3, iclass 6, count 2 2006.210.08:11:19.96#ibcon#about to read 4, iclass 6, count 2 2006.210.08:11:19.96#ibcon#read 4, iclass 6, count 2 2006.210.08:11:19.96#ibcon#about to read 5, iclass 6, count 2 2006.210.08:11:19.96#ibcon#read 5, iclass 6, count 2 2006.210.08:11:19.96#ibcon#about to read 6, iclass 6, count 2 2006.210.08:11:19.96#ibcon#read 6, iclass 6, count 2 2006.210.08:11:19.96#ibcon#end of sib2, iclass 6, count 2 2006.210.08:11:19.96#ibcon#*mode == 0, iclass 6, count 2 2006.210.08:11:19.96#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.08:11:19.96#ibcon#[25=AT08-07\r\n] 2006.210.08:11:19.96#ibcon#*before write, iclass 6, count 2 2006.210.08:11:19.96#ibcon#enter sib2, iclass 6, count 2 2006.210.08:11:19.96#ibcon#flushed, iclass 6, count 2 2006.210.08:11:19.96#ibcon#about to write, iclass 6, count 2 2006.210.08:11:19.96#ibcon#wrote, iclass 6, count 2 2006.210.08:11:19.96#ibcon#about to read 3, iclass 6, count 2 2006.210.08:11:19.99#ibcon#read 3, iclass 6, count 2 2006.210.08:11:19.99#ibcon#about to read 4, iclass 6, count 2 2006.210.08:11:19.99#ibcon#read 4, iclass 6, count 2 2006.210.08:11:19.99#ibcon#about to read 5, iclass 6, count 2 2006.210.08:11:19.99#ibcon#read 5, iclass 6, count 2 2006.210.08:11:19.99#ibcon#about to read 6, iclass 6, count 2 2006.210.08:11:19.99#ibcon#read 6, iclass 6, count 2 2006.210.08:11:19.99#ibcon#end of sib2, iclass 6, count 2 2006.210.08:11:19.99#ibcon#*after write, iclass 6, count 2 2006.210.08:11:19.99#ibcon#*before return 0, iclass 6, count 2 2006.210.08:11:19.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:11:19.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:11:19.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.08:11:19.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:19.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:11:20.10#abcon#<5=/06 3.5 5.7 30.13 821006.5\r\n> 2006.210.08:11:20.11#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:11:20.11#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:11:20.11#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:11:20.11#ibcon#first serial, iclass 6, count 0 2006.210.08:11:20.11#ibcon#enter sib2, iclass 6, count 0 2006.210.08:11:20.11#ibcon#flushed, iclass 6, count 0 2006.210.08:11:20.11#ibcon#about to write, iclass 6, count 0 2006.210.08:11:20.11#ibcon#wrote, iclass 6, count 0 2006.210.08:11:20.11#ibcon#about to read 3, iclass 6, count 0 2006.210.08:11:20.12#abcon#{5=INTERFACE CLEAR} 2006.210.08:11:20.13#ibcon#read 3, iclass 6, count 0 2006.210.08:11:20.13#ibcon#about to read 4, iclass 6, count 0 2006.210.08:11:20.13#ibcon#read 4, iclass 6, count 0 2006.210.08:11:20.13#ibcon#about to read 5, iclass 6, count 0 2006.210.08:11:20.13#ibcon#read 5, iclass 6, count 0 2006.210.08:11:20.13#ibcon#about to read 6, iclass 6, count 0 2006.210.08:11:20.13#ibcon#read 6, iclass 6, count 0 2006.210.08:11:20.13#ibcon#end of sib2, iclass 6, count 0 2006.210.08:11:20.13#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:11:20.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:11:20.13#ibcon#[25=USB\r\n] 2006.210.08:11:20.13#ibcon#*before write, iclass 6, count 0 2006.210.08:11:20.13#ibcon#enter sib2, iclass 6, count 0 2006.210.08:11:20.13#ibcon#flushed, iclass 6, count 0 2006.210.08:11:20.13#ibcon#about to write, iclass 6, count 0 2006.210.08:11:20.13#ibcon#wrote, iclass 6, count 0 2006.210.08:11:20.13#ibcon#about to read 3, iclass 6, count 0 2006.210.08:11:20.16#ibcon#read 3, iclass 6, count 0 2006.210.08:11:20.16#ibcon#about to read 4, iclass 6, count 0 2006.210.08:11:20.16#ibcon#read 4, iclass 6, count 0 2006.210.08:11:20.16#ibcon#about to read 5, iclass 6, count 0 2006.210.08:11:20.16#ibcon#read 5, iclass 6, count 0 2006.210.08:11:20.16#ibcon#about to read 6, iclass 6, count 0 2006.210.08:11:20.16#ibcon#read 6, iclass 6, count 0 2006.210.08:11:20.16#ibcon#end of sib2, iclass 6, count 0 2006.210.08:11:20.16#ibcon#*after write, iclass 6, count 0 2006.210.08:11:20.16#ibcon#*before return 0, iclass 6, count 0 2006.210.08:11:20.16#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:11:20.16#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:11:20.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:11:20.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:11:20.16$vc4f8/vblo=1,632.99 2006.210.08:11:20.16#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:11:20.16#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:11:20.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:20.16#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:11:20.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:11:20.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:11:20.16#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:11:20.16#ibcon#first serial, iclass 13, count 0 2006.210.08:11:20.16#ibcon#enter sib2, iclass 13, count 0 2006.210.08:11:20.16#ibcon#flushed, iclass 13, count 0 2006.210.08:11:20.16#ibcon#about to write, iclass 13, count 0 2006.210.08:11:20.16#ibcon#wrote, iclass 13, count 0 2006.210.08:11:20.16#ibcon#about to read 3, iclass 13, count 0 2006.210.08:11:20.18#ibcon#read 3, iclass 13, count 0 2006.210.08:11:20.18#ibcon#about to read 4, iclass 13, count 0 2006.210.08:11:20.18#ibcon#read 4, iclass 13, count 0 2006.210.08:11:20.18#ibcon#about to read 5, iclass 13, count 0 2006.210.08:11:20.18#ibcon#read 5, iclass 13, count 0 2006.210.08:11:20.18#ibcon#about to read 6, iclass 13, count 0 2006.210.08:11:20.18#ibcon#read 6, iclass 13, count 0 2006.210.08:11:20.18#ibcon#end of sib2, iclass 13, count 0 2006.210.08:11:20.18#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:11:20.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:11:20.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:11:20.18#ibcon#*before write, iclass 13, count 0 2006.210.08:11:20.18#ibcon#enter sib2, iclass 13, count 0 2006.210.08:11:20.18#ibcon#flushed, iclass 13, count 0 2006.210.08:11:20.18#ibcon#about to write, iclass 13, count 0 2006.210.08:11:20.18#ibcon#wrote, iclass 13, count 0 2006.210.08:11:20.18#ibcon#about to read 3, iclass 13, count 0 2006.210.08:11:20.18#abcon#[5=S1D000X0/0*\r\n] 2006.210.08:11:20.22#ibcon#read 3, iclass 13, count 0 2006.210.08:11:20.22#ibcon#about to read 4, iclass 13, count 0 2006.210.08:11:20.22#ibcon#read 4, iclass 13, count 0 2006.210.08:11:20.22#ibcon#about to read 5, iclass 13, count 0 2006.210.08:11:20.22#ibcon#read 5, iclass 13, count 0 2006.210.08:11:20.22#ibcon#about to read 6, iclass 13, count 0 2006.210.08:11:20.22#ibcon#read 6, iclass 13, count 0 2006.210.08:11:20.22#ibcon#end of sib2, iclass 13, count 0 2006.210.08:11:20.22#ibcon#*after write, iclass 13, count 0 2006.210.08:11:20.22#ibcon#*before return 0, iclass 13, count 0 2006.210.08:11:20.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:11:20.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:11:20.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:11:20.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:11:20.22$vc4f8/vb=1,4 2006.210.08:11:20.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.08:11:20.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.08:11:20.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:20.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:20.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:20.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:20.22#ibcon#enter wrdev, iclass 16, count 2 2006.210.08:11:20.22#ibcon#first serial, iclass 16, count 2 2006.210.08:11:20.22#ibcon#enter sib2, iclass 16, count 2 2006.210.08:11:20.22#ibcon#flushed, iclass 16, count 2 2006.210.08:11:20.22#ibcon#about to write, iclass 16, count 2 2006.210.08:11:20.22#ibcon#wrote, iclass 16, count 2 2006.210.08:11:20.22#ibcon#about to read 3, iclass 16, count 2 2006.210.08:11:20.24#ibcon#read 3, iclass 16, count 2 2006.210.08:11:20.24#ibcon#about to read 4, iclass 16, count 2 2006.210.08:11:20.24#ibcon#read 4, iclass 16, count 2 2006.210.08:11:20.24#ibcon#about to read 5, iclass 16, count 2 2006.210.08:11:20.24#ibcon#read 5, iclass 16, count 2 2006.210.08:11:20.24#ibcon#about to read 6, iclass 16, count 2 2006.210.08:11:20.24#ibcon#read 6, iclass 16, count 2 2006.210.08:11:20.24#ibcon#end of sib2, iclass 16, count 2 2006.210.08:11:20.24#ibcon#*mode == 0, iclass 16, count 2 2006.210.08:11:20.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.08:11:20.24#ibcon#[27=AT01-04\r\n] 2006.210.08:11:20.24#ibcon#*before write, iclass 16, count 2 2006.210.08:11:20.24#ibcon#enter sib2, iclass 16, count 2 2006.210.08:11:20.24#ibcon#flushed, iclass 16, count 2 2006.210.08:11:20.24#ibcon#about to write, iclass 16, count 2 2006.210.08:11:20.24#ibcon#wrote, iclass 16, count 2 2006.210.08:11:20.24#ibcon#about to read 3, iclass 16, count 2 2006.210.08:11:20.27#ibcon#read 3, iclass 16, count 2 2006.210.08:11:20.27#ibcon#about to read 4, iclass 16, count 2 2006.210.08:11:20.27#ibcon#read 4, iclass 16, count 2 2006.210.08:11:20.27#ibcon#about to read 5, iclass 16, count 2 2006.210.08:11:20.27#ibcon#read 5, iclass 16, count 2 2006.210.08:11:20.27#ibcon#about to read 6, iclass 16, count 2 2006.210.08:11:20.27#ibcon#read 6, iclass 16, count 2 2006.210.08:11:20.27#ibcon#end of sib2, iclass 16, count 2 2006.210.08:11:20.27#ibcon#*after write, iclass 16, count 2 2006.210.08:11:20.27#ibcon#*before return 0, iclass 16, count 2 2006.210.08:11:20.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:20.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:11:20.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.08:11:20.27#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:20.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:20.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:20.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:20.39#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:11:20.39#ibcon#first serial, iclass 16, count 0 2006.210.08:11:20.39#ibcon#enter sib2, iclass 16, count 0 2006.210.08:11:20.39#ibcon#flushed, iclass 16, count 0 2006.210.08:11:20.39#ibcon#about to write, iclass 16, count 0 2006.210.08:11:20.39#ibcon#wrote, iclass 16, count 0 2006.210.08:11:20.39#ibcon#about to read 3, iclass 16, count 0 2006.210.08:11:20.41#ibcon#read 3, iclass 16, count 0 2006.210.08:11:20.41#ibcon#about to read 4, iclass 16, count 0 2006.210.08:11:20.41#ibcon#read 4, iclass 16, count 0 2006.210.08:11:20.41#ibcon#about to read 5, iclass 16, count 0 2006.210.08:11:20.41#ibcon#read 5, iclass 16, count 0 2006.210.08:11:20.41#ibcon#about to read 6, iclass 16, count 0 2006.210.08:11:20.41#ibcon#read 6, iclass 16, count 0 2006.210.08:11:20.41#ibcon#end of sib2, iclass 16, count 0 2006.210.08:11:20.41#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:11:20.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:11:20.41#ibcon#[27=USB\r\n] 2006.210.08:11:20.41#ibcon#*before write, iclass 16, count 0 2006.210.08:11:20.41#ibcon#enter sib2, iclass 16, count 0 2006.210.08:11:20.41#ibcon#flushed, iclass 16, count 0 2006.210.08:11:20.41#ibcon#about to write, iclass 16, count 0 2006.210.08:11:20.41#ibcon#wrote, iclass 16, count 0 2006.210.08:11:20.41#ibcon#about to read 3, iclass 16, count 0 2006.210.08:11:20.44#ibcon#read 3, iclass 16, count 0 2006.210.08:11:20.44#ibcon#about to read 4, iclass 16, count 0 2006.210.08:11:20.44#ibcon#read 4, iclass 16, count 0 2006.210.08:11:20.44#ibcon#about to read 5, iclass 16, count 0 2006.210.08:11:20.44#ibcon#read 5, iclass 16, count 0 2006.210.08:11:20.44#ibcon#about to read 6, iclass 16, count 0 2006.210.08:11:20.44#ibcon#read 6, iclass 16, count 0 2006.210.08:11:20.44#ibcon#end of sib2, iclass 16, count 0 2006.210.08:11:20.44#ibcon#*after write, iclass 16, count 0 2006.210.08:11:20.44#ibcon#*before return 0, iclass 16, count 0 2006.210.08:11:20.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:20.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:11:20.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:11:20.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:11:20.44$vc4f8/vblo=2,640.99 2006.210.08:11:20.44#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.08:11:20.44#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.08:11:20.44#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:20.44#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:20.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:20.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:20.44#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:11:20.44#ibcon#first serial, iclass 18, count 0 2006.210.08:11:20.44#ibcon#enter sib2, iclass 18, count 0 2006.210.08:11:20.44#ibcon#flushed, iclass 18, count 0 2006.210.08:11:20.44#ibcon#about to write, iclass 18, count 0 2006.210.08:11:20.44#ibcon#wrote, iclass 18, count 0 2006.210.08:11:20.44#ibcon#about to read 3, iclass 18, count 0 2006.210.08:11:20.46#ibcon#read 3, iclass 18, count 0 2006.210.08:11:20.46#ibcon#about to read 4, iclass 18, count 0 2006.210.08:11:20.46#ibcon#read 4, iclass 18, count 0 2006.210.08:11:20.46#ibcon#about to read 5, iclass 18, count 0 2006.210.08:11:20.46#ibcon#read 5, iclass 18, count 0 2006.210.08:11:20.46#ibcon#about to read 6, iclass 18, count 0 2006.210.08:11:20.46#ibcon#read 6, iclass 18, count 0 2006.210.08:11:20.46#ibcon#end of sib2, iclass 18, count 0 2006.210.08:11:20.46#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:11:20.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:11:20.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:11:20.46#ibcon#*before write, iclass 18, count 0 2006.210.08:11:20.46#ibcon#enter sib2, iclass 18, count 0 2006.210.08:11:20.46#ibcon#flushed, iclass 18, count 0 2006.210.08:11:20.46#ibcon#about to write, iclass 18, count 0 2006.210.08:11:20.46#ibcon#wrote, iclass 18, count 0 2006.210.08:11:20.46#ibcon#about to read 3, iclass 18, count 0 2006.210.08:11:20.50#ibcon#read 3, iclass 18, count 0 2006.210.08:11:20.50#ibcon#about to read 4, iclass 18, count 0 2006.210.08:11:20.50#ibcon#read 4, iclass 18, count 0 2006.210.08:11:20.50#ibcon#about to read 5, iclass 18, count 0 2006.210.08:11:20.50#ibcon#read 5, iclass 18, count 0 2006.210.08:11:20.50#ibcon#about to read 6, iclass 18, count 0 2006.210.08:11:20.50#ibcon#read 6, iclass 18, count 0 2006.210.08:11:20.50#ibcon#end of sib2, iclass 18, count 0 2006.210.08:11:20.50#ibcon#*after write, iclass 18, count 0 2006.210.08:11:20.50#ibcon#*before return 0, iclass 18, count 0 2006.210.08:11:20.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:20.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:11:20.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:11:20.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:11:20.50$vc4f8/vb=2,4 2006.210.08:11:20.50#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.08:11:20.50#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.08:11:20.50#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:20.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:20.56#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:20.56#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:20.56#ibcon#enter wrdev, iclass 20, count 2 2006.210.08:11:20.56#ibcon#first serial, iclass 20, count 2 2006.210.08:11:20.56#ibcon#enter sib2, iclass 20, count 2 2006.210.08:11:20.56#ibcon#flushed, iclass 20, count 2 2006.210.08:11:20.56#ibcon#about to write, iclass 20, count 2 2006.210.08:11:20.56#ibcon#wrote, iclass 20, count 2 2006.210.08:11:20.56#ibcon#about to read 3, iclass 20, count 2 2006.210.08:11:20.58#ibcon#read 3, iclass 20, count 2 2006.210.08:11:20.58#ibcon#about to read 4, iclass 20, count 2 2006.210.08:11:20.58#ibcon#read 4, iclass 20, count 2 2006.210.08:11:20.58#ibcon#about to read 5, iclass 20, count 2 2006.210.08:11:20.58#ibcon#read 5, iclass 20, count 2 2006.210.08:11:20.58#ibcon#about to read 6, iclass 20, count 2 2006.210.08:11:20.58#ibcon#read 6, iclass 20, count 2 2006.210.08:11:20.58#ibcon#end of sib2, iclass 20, count 2 2006.210.08:11:20.58#ibcon#*mode == 0, iclass 20, count 2 2006.210.08:11:20.58#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.08:11:20.58#ibcon#[27=AT02-04\r\n] 2006.210.08:11:20.58#ibcon#*before write, iclass 20, count 2 2006.210.08:11:20.58#ibcon#enter sib2, iclass 20, count 2 2006.210.08:11:20.58#ibcon#flushed, iclass 20, count 2 2006.210.08:11:20.58#ibcon#about to write, iclass 20, count 2 2006.210.08:11:20.58#ibcon#wrote, iclass 20, count 2 2006.210.08:11:20.58#ibcon#about to read 3, iclass 20, count 2 2006.210.08:11:20.61#ibcon#read 3, iclass 20, count 2 2006.210.08:11:20.61#ibcon#about to read 4, iclass 20, count 2 2006.210.08:11:20.61#ibcon#read 4, iclass 20, count 2 2006.210.08:11:20.61#ibcon#about to read 5, iclass 20, count 2 2006.210.08:11:20.61#ibcon#read 5, iclass 20, count 2 2006.210.08:11:20.61#ibcon#about to read 6, iclass 20, count 2 2006.210.08:11:20.61#ibcon#read 6, iclass 20, count 2 2006.210.08:11:20.61#ibcon#end of sib2, iclass 20, count 2 2006.210.08:11:20.61#ibcon#*after write, iclass 20, count 2 2006.210.08:11:20.61#ibcon#*before return 0, iclass 20, count 2 2006.210.08:11:20.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:20.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:11:20.61#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.08:11:20.61#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:20.61#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:20.73#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:20.73#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:20.73#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:11:20.73#ibcon#first serial, iclass 20, count 0 2006.210.08:11:20.73#ibcon#enter sib2, iclass 20, count 0 2006.210.08:11:20.73#ibcon#flushed, iclass 20, count 0 2006.210.08:11:20.73#ibcon#about to write, iclass 20, count 0 2006.210.08:11:20.73#ibcon#wrote, iclass 20, count 0 2006.210.08:11:20.73#ibcon#about to read 3, iclass 20, count 0 2006.210.08:11:20.75#ibcon#read 3, iclass 20, count 0 2006.210.08:11:20.75#ibcon#about to read 4, iclass 20, count 0 2006.210.08:11:20.75#ibcon#read 4, iclass 20, count 0 2006.210.08:11:20.75#ibcon#about to read 5, iclass 20, count 0 2006.210.08:11:20.75#ibcon#read 5, iclass 20, count 0 2006.210.08:11:20.75#ibcon#about to read 6, iclass 20, count 0 2006.210.08:11:20.75#ibcon#read 6, iclass 20, count 0 2006.210.08:11:20.75#ibcon#end of sib2, iclass 20, count 0 2006.210.08:11:20.75#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:11:20.75#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:11:20.75#ibcon#[27=USB\r\n] 2006.210.08:11:20.75#ibcon#*before write, iclass 20, count 0 2006.210.08:11:20.75#ibcon#enter sib2, iclass 20, count 0 2006.210.08:11:20.75#ibcon#flushed, iclass 20, count 0 2006.210.08:11:20.75#ibcon#about to write, iclass 20, count 0 2006.210.08:11:20.75#ibcon#wrote, iclass 20, count 0 2006.210.08:11:20.75#ibcon#about to read 3, iclass 20, count 0 2006.210.08:11:20.78#ibcon#read 3, iclass 20, count 0 2006.210.08:11:20.78#ibcon#about to read 4, iclass 20, count 0 2006.210.08:11:20.78#ibcon#read 4, iclass 20, count 0 2006.210.08:11:20.78#ibcon#about to read 5, iclass 20, count 0 2006.210.08:11:20.78#ibcon#read 5, iclass 20, count 0 2006.210.08:11:20.78#ibcon#about to read 6, iclass 20, count 0 2006.210.08:11:20.78#ibcon#read 6, iclass 20, count 0 2006.210.08:11:20.78#ibcon#end of sib2, iclass 20, count 0 2006.210.08:11:20.78#ibcon#*after write, iclass 20, count 0 2006.210.08:11:20.78#ibcon#*before return 0, iclass 20, count 0 2006.210.08:11:20.78#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:20.78#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:11:20.78#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:11:20.78#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:11:20.78$vc4f8/vblo=3,656.99 2006.210.08:11:20.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.08:11:20.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.08:11:20.78#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:20.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:20.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:20.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:20.78#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:11:20.78#ibcon#first serial, iclass 22, count 0 2006.210.08:11:20.78#ibcon#enter sib2, iclass 22, count 0 2006.210.08:11:20.78#ibcon#flushed, iclass 22, count 0 2006.210.08:11:20.78#ibcon#about to write, iclass 22, count 0 2006.210.08:11:20.78#ibcon#wrote, iclass 22, count 0 2006.210.08:11:20.78#ibcon#about to read 3, iclass 22, count 0 2006.210.08:11:20.80#ibcon#read 3, iclass 22, count 0 2006.210.08:11:20.80#ibcon#about to read 4, iclass 22, count 0 2006.210.08:11:20.80#ibcon#read 4, iclass 22, count 0 2006.210.08:11:20.80#ibcon#about to read 5, iclass 22, count 0 2006.210.08:11:20.80#ibcon#read 5, iclass 22, count 0 2006.210.08:11:20.80#ibcon#about to read 6, iclass 22, count 0 2006.210.08:11:20.80#ibcon#read 6, iclass 22, count 0 2006.210.08:11:20.80#ibcon#end of sib2, iclass 22, count 0 2006.210.08:11:20.80#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:11:20.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:11:20.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:11:20.80#ibcon#*before write, iclass 22, count 0 2006.210.08:11:20.80#ibcon#enter sib2, iclass 22, count 0 2006.210.08:11:20.80#ibcon#flushed, iclass 22, count 0 2006.210.08:11:20.80#ibcon#about to write, iclass 22, count 0 2006.210.08:11:20.80#ibcon#wrote, iclass 22, count 0 2006.210.08:11:20.80#ibcon#about to read 3, iclass 22, count 0 2006.210.08:11:20.84#ibcon#read 3, iclass 22, count 0 2006.210.08:11:20.84#ibcon#about to read 4, iclass 22, count 0 2006.210.08:11:20.84#ibcon#read 4, iclass 22, count 0 2006.210.08:11:20.84#ibcon#about to read 5, iclass 22, count 0 2006.210.08:11:20.84#ibcon#read 5, iclass 22, count 0 2006.210.08:11:20.84#ibcon#about to read 6, iclass 22, count 0 2006.210.08:11:20.84#ibcon#read 6, iclass 22, count 0 2006.210.08:11:20.84#ibcon#end of sib2, iclass 22, count 0 2006.210.08:11:20.84#ibcon#*after write, iclass 22, count 0 2006.210.08:11:20.84#ibcon#*before return 0, iclass 22, count 0 2006.210.08:11:20.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:20.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:11:20.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:11:20.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:11:20.84$vc4f8/vb=3,3 2006.210.08:11:20.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.08:11:20.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.08:11:20.84#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:20.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:20.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:20.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:20.90#ibcon#enter wrdev, iclass 24, count 2 2006.210.08:11:20.90#ibcon#first serial, iclass 24, count 2 2006.210.08:11:20.90#ibcon#enter sib2, iclass 24, count 2 2006.210.08:11:20.90#ibcon#flushed, iclass 24, count 2 2006.210.08:11:20.90#ibcon#about to write, iclass 24, count 2 2006.210.08:11:20.90#ibcon#wrote, iclass 24, count 2 2006.210.08:11:20.90#ibcon#about to read 3, iclass 24, count 2 2006.210.08:11:20.92#ibcon#read 3, iclass 24, count 2 2006.210.08:11:20.92#ibcon#about to read 4, iclass 24, count 2 2006.210.08:11:20.92#ibcon#read 4, iclass 24, count 2 2006.210.08:11:20.92#ibcon#about to read 5, iclass 24, count 2 2006.210.08:11:20.92#ibcon#read 5, iclass 24, count 2 2006.210.08:11:20.92#ibcon#about to read 6, iclass 24, count 2 2006.210.08:11:20.92#ibcon#read 6, iclass 24, count 2 2006.210.08:11:20.92#ibcon#end of sib2, iclass 24, count 2 2006.210.08:11:20.92#ibcon#*mode == 0, iclass 24, count 2 2006.210.08:11:20.92#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.08:11:20.92#ibcon#[27=AT03-03\r\n] 2006.210.08:11:20.92#ibcon#*before write, iclass 24, count 2 2006.210.08:11:20.92#ibcon#enter sib2, iclass 24, count 2 2006.210.08:11:20.92#ibcon#flushed, iclass 24, count 2 2006.210.08:11:20.92#ibcon#about to write, iclass 24, count 2 2006.210.08:11:20.92#ibcon#wrote, iclass 24, count 2 2006.210.08:11:20.92#ibcon#about to read 3, iclass 24, count 2 2006.210.08:11:20.95#ibcon#read 3, iclass 24, count 2 2006.210.08:11:20.95#ibcon#about to read 4, iclass 24, count 2 2006.210.08:11:20.95#ibcon#read 4, iclass 24, count 2 2006.210.08:11:20.95#ibcon#about to read 5, iclass 24, count 2 2006.210.08:11:20.95#ibcon#read 5, iclass 24, count 2 2006.210.08:11:20.95#ibcon#about to read 6, iclass 24, count 2 2006.210.08:11:20.95#ibcon#read 6, iclass 24, count 2 2006.210.08:11:20.95#ibcon#end of sib2, iclass 24, count 2 2006.210.08:11:20.95#ibcon#*after write, iclass 24, count 2 2006.210.08:11:20.95#ibcon#*before return 0, iclass 24, count 2 2006.210.08:11:20.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:20.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:11:20.95#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.08:11:20.95#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:20.95#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:21.07#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:21.07#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:21.07#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:11:21.07#ibcon#first serial, iclass 24, count 0 2006.210.08:11:21.07#ibcon#enter sib2, iclass 24, count 0 2006.210.08:11:21.07#ibcon#flushed, iclass 24, count 0 2006.210.08:11:21.07#ibcon#about to write, iclass 24, count 0 2006.210.08:11:21.07#ibcon#wrote, iclass 24, count 0 2006.210.08:11:21.07#ibcon#about to read 3, iclass 24, count 0 2006.210.08:11:21.09#ibcon#read 3, iclass 24, count 0 2006.210.08:11:21.09#ibcon#about to read 4, iclass 24, count 0 2006.210.08:11:21.09#ibcon#read 4, iclass 24, count 0 2006.210.08:11:21.09#ibcon#about to read 5, iclass 24, count 0 2006.210.08:11:21.09#ibcon#read 5, iclass 24, count 0 2006.210.08:11:21.09#ibcon#about to read 6, iclass 24, count 0 2006.210.08:11:21.09#ibcon#read 6, iclass 24, count 0 2006.210.08:11:21.09#ibcon#end of sib2, iclass 24, count 0 2006.210.08:11:21.09#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:11:21.09#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:11:21.09#ibcon#[27=USB\r\n] 2006.210.08:11:21.09#ibcon#*before write, iclass 24, count 0 2006.210.08:11:21.09#ibcon#enter sib2, iclass 24, count 0 2006.210.08:11:21.09#ibcon#flushed, iclass 24, count 0 2006.210.08:11:21.09#ibcon#about to write, iclass 24, count 0 2006.210.08:11:21.09#ibcon#wrote, iclass 24, count 0 2006.210.08:11:21.09#ibcon#about to read 3, iclass 24, count 0 2006.210.08:11:21.12#ibcon#read 3, iclass 24, count 0 2006.210.08:11:21.12#ibcon#about to read 4, iclass 24, count 0 2006.210.08:11:21.12#ibcon#read 4, iclass 24, count 0 2006.210.08:11:21.12#ibcon#about to read 5, iclass 24, count 0 2006.210.08:11:21.12#ibcon#read 5, iclass 24, count 0 2006.210.08:11:21.12#ibcon#about to read 6, iclass 24, count 0 2006.210.08:11:21.12#ibcon#read 6, iclass 24, count 0 2006.210.08:11:21.12#ibcon#end of sib2, iclass 24, count 0 2006.210.08:11:21.12#ibcon#*after write, iclass 24, count 0 2006.210.08:11:21.12#ibcon#*before return 0, iclass 24, count 0 2006.210.08:11:21.12#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:21.12#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:11:21.12#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:11:21.12#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:11:21.12$vc4f8/vblo=4,712.99 2006.210.08:11:21.12#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.08:11:21.12#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.08:11:21.12#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:21.12#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:21.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:21.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:21.12#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:11:21.12#ibcon#first serial, iclass 26, count 0 2006.210.08:11:21.12#ibcon#enter sib2, iclass 26, count 0 2006.210.08:11:21.12#ibcon#flushed, iclass 26, count 0 2006.210.08:11:21.12#ibcon#about to write, iclass 26, count 0 2006.210.08:11:21.12#ibcon#wrote, iclass 26, count 0 2006.210.08:11:21.12#ibcon#about to read 3, iclass 26, count 0 2006.210.08:11:21.14#ibcon#read 3, iclass 26, count 0 2006.210.08:11:21.14#ibcon#about to read 4, iclass 26, count 0 2006.210.08:11:21.14#ibcon#read 4, iclass 26, count 0 2006.210.08:11:21.14#ibcon#about to read 5, iclass 26, count 0 2006.210.08:11:21.14#ibcon#read 5, iclass 26, count 0 2006.210.08:11:21.14#ibcon#about to read 6, iclass 26, count 0 2006.210.08:11:21.14#ibcon#read 6, iclass 26, count 0 2006.210.08:11:21.14#ibcon#end of sib2, iclass 26, count 0 2006.210.08:11:21.14#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:11:21.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:11:21.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:11:21.14#ibcon#*before write, iclass 26, count 0 2006.210.08:11:21.14#ibcon#enter sib2, iclass 26, count 0 2006.210.08:11:21.14#ibcon#flushed, iclass 26, count 0 2006.210.08:11:21.14#ibcon#about to write, iclass 26, count 0 2006.210.08:11:21.14#ibcon#wrote, iclass 26, count 0 2006.210.08:11:21.14#ibcon#about to read 3, iclass 26, count 0 2006.210.08:11:21.18#ibcon#read 3, iclass 26, count 0 2006.210.08:11:21.18#ibcon#about to read 4, iclass 26, count 0 2006.210.08:11:21.18#ibcon#read 4, iclass 26, count 0 2006.210.08:11:21.18#ibcon#about to read 5, iclass 26, count 0 2006.210.08:11:21.18#ibcon#read 5, iclass 26, count 0 2006.210.08:11:21.18#ibcon#about to read 6, iclass 26, count 0 2006.210.08:11:21.18#ibcon#read 6, iclass 26, count 0 2006.210.08:11:21.18#ibcon#end of sib2, iclass 26, count 0 2006.210.08:11:21.18#ibcon#*after write, iclass 26, count 0 2006.210.08:11:21.18#ibcon#*before return 0, iclass 26, count 0 2006.210.08:11:21.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:21.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:11:21.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:11:21.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:11:21.18$vc4f8/vb=4,3 2006.210.08:11:21.18#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.08:11:21.18#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.08:11:21.18#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:21.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:21.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:21.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:21.24#ibcon#enter wrdev, iclass 28, count 2 2006.210.08:11:21.24#ibcon#first serial, iclass 28, count 2 2006.210.08:11:21.24#ibcon#enter sib2, iclass 28, count 2 2006.210.08:11:21.24#ibcon#flushed, iclass 28, count 2 2006.210.08:11:21.24#ibcon#about to write, iclass 28, count 2 2006.210.08:11:21.24#ibcon#wrote, iclass 28, count 2 2006.210.08:11:21.24#ibcon#about to read 3, iclass 28, count 2 2006.210.08:11:21.26#ibcon#read 3, iclass 28, count 2 2006.210.08:11:21.26#ibcon#about to read 4, iclass 28, count 2 2006.210.08:11:21.26#ibcon#read 4, iclass 28, count 2 2006.210.08:11:21.26#ibcon#about to read 5, iclass 28, count 2 2006.210.08:11:21.26#ibcon#read 5, iclass 28, count 2 2006.210.08:11:21.26#ibcon#about to read 6, iclass 28, count 2 2006.210.08:11:21.26#ibcon#read 6, iclass 28, count 2 2006.210.08:11:21.26#ibcon#end of sib2, iclass 28, count 2 2006.210.08:11:21.26#ibcon#*mode == 0, iclass 28, count 2 2006.210.08:11:21.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.08:11:21.26#ibcon#[27=AT04-03\r\n] 2006.210.08:11:21.26#ibcon#*before write, iclass 28, count 2 2006.210.08:11:21.26#ibcon#enter sib2, iclass 28, count 2 2006.210.08:11:21.26#ibcon#flushed, iclass 28, count 2 2006.210.08:11:21.26#ibcon#about to write, iclass 28, count 2 2006.210.08:11:21.26#ibcon#wrote, iclass 28, count 2 2006.210.08:11:21.26#ibcon#about to read 3, iclass 28, count 2 2006.210.08:11:21.29#ibcon#read 3, iclass 28, count 2 2006.210.08:11:21.29#ibcon#about to read 4, iclass 28, count 2 2006.210.08:11:21.29#ibcon#read 4, iclass 28, count 2 2006.210.08:11:21.29#ibcon#about to read 5, iclass 28, count 2 2006.210.08:11:21.29#ibcon#read 5, iclass 28, count 2 2006.210.08:11:21.29#ibcon#about to read 6, iclass 28, count 2 2006.210.08:11:21.29#ibcon#read 6, iclass 28, count 2 2006.210.08:11:21.29#ibcon#end of sib2, iclass 28, count 2 2006.210.08:11:21.29#ibcon#*after write, iclass 28, count 2 2006.210.08:11:21.29#ibcon#*before return 0, iclass 28, count 2 2006.210.08:11:21.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:21.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:11:21.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.08:11:21.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:21.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:21.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:21.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:21.41#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:11:21.41#ibcon#first serial, iclass 28, count 0 2006.210.08:11:21.41#ibcon#enter sib2, iclass 28, count 0 2006.210.08:11:21.41#ibcon#flushed, iclass 28, count 0 2006.210.08:11:21.41#ibcon#about to write, iclass 28, count 0 2006.210.08:11:21.41#ibcon#wrote, iclass 28, count 0 2006.210.08:11:21.41#ibcon#about to read 3, iclass 28, count 0 2006.210.08:11:21.43#ibcon#read 3, iclass 28, count 0 2006.210.08:11:21.43#ibcon#about to read 4, iclass 28, count 0 2006.210.08:11:21.43#ibcon#read 4, iclass 28, count 0 2006.210.08:11:21.43#ibcon#about to read 5, iclass 28, count 0 2006.210.08:11:21.43#ibcon#read 5, iclass 28, count 0 2006.210.08:11:21.43#ibcon#about to read 6, iclass 28, count 0 2006.210.08:11:21.43#ibcon#read 6, iclass 28, count 0 2006.210.08:11:21.43#ibcon#end of sib2, iclass 28, count 0 2006.210.08:11:21.43#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:11:21.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:11:21.43#ibcon#[27=USB\r\n] 2006.210.08:11:21.43#ibcon#*before write, iclass 28, count 0 2006.210.08:11:21.43#ibcon#enter sib2, iclass 28, count 0 2006.210.08:11:21.43#ibcon#flushed, iclass 28, count 0 2006.210.08:11:21.43#ibcon#about to write, iclass 28, count 0 2006.210.08:11:21.43#ibcon#wrote, iclass 28, count 0 2006.210.08:11:21.43#ibcon#about to read 3, iclass 28, count 0 2006.210.08:11:21.46#ibcon#read 3, iclass 28, count 0 2006.210.08:11:21.46#ibcon#about to read 4, iclass 28, count 0 2006.210.08:11:21.46#ibcon#read 4, iclass 28, count 0 2006.210.08:11:21.46#ibcon#about to read 5, iclass 28, count 0 2006.210.08:11:21.46#ibcon#read 5, iclass 28, count 0 2006.210.08:11:21.46#ibcon#about to read 6, iclass 28, count 0 2006.210.08:11:21.46#ibcon#read 6, iclass 28, count 0 2006.210.08:11:21.46#ibcon#end of sib2, iclass 28, count 0 2006.210.08:11:21.46#ibcon#*after write, iclass 28, count 0 2006.210.08:11:21.46#ibcon#*before return 0, iclass 28, count 0 2006.210.08:11:21.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:21.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:11:21.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:11:21.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:11:21.46$vc4f8/vblo=5,744.99 2006.210.08:11:21.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.08:11:21.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.08:11:21.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:21.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:21.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:21.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:21.46#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:11:21.46#ibcon#first serial, iclass 30, count 0 2006.210.08:11:21.46#ibcon#enter sib2, iclass 30, count 0 2006.210.08:11:21.46#ibcon#flushed, iclass 30, count 0 2006.210.08:11:21.46#ibcon#about to write, iclass 30, count 0 2006.210.08:11:21.46#ibcon#wrote, iclass 30, count 0 2006.210.08:11:21.46#ibcon#about to read 3, iclass 30, count 0 2006.210.08:11:21.48#ibcon#read 3, iclass 30, count 0 2006.210.08:11:21.48#ibcon#about to read 4, iclass 30, count 0 2006.210.08:11:21.48#ibcon#read 4, iclass 30, count 0 2006.210.08:11:21.48#ibcon#about to read 5, iclass 30, count 0 2006.210.08:11:21.48#ibcon#read 5, iclass 30, count 0 2006.210.08:11:21.48#ibcon#about to read 6, iclass 30, count 0 2006.210.08:11:21.48#ibcon#read 6, iclass 30, count 0 2006.210.08:11:21.48#ibcon#end of sib2, iclass 30, count 0 2006.210.08:11:21.48#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:11:21.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:11:21.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:11:21.48#ibcon#*before write, iclass 30, count 0 2006.210.08:11:21.48#ibcon#enter sib2, iclass 30, count 0 2006.210.08:11:21.48#ibcon#flushed, iclass 30, count 0 2006.210.08:11:21.48#ibcon#about to write, iclass 30, count 0 2006.210.08:11:21.48#ibcon#wrote, iclass 30, count 0 2006.210.08:11:21.48#ibcon#about to read 3, iclass 30, count 0 2006.210.08:11:21.52#ibcon#read 3, iclass 30, count 0 2006.210.08:11:21.52#ibcon#about to read 4, iclass 30, count 0 2006.210.08:11:21.52#ibcon#read 4, iclass 30, count 0 2006.210.08:11:21.52#ibcon#about to read 5, iclass 30, count 0 2006.210.08:11:21.52#ibcon#read 5, iclass 30, count 0 2006.210.08:11:21.52#ibcon#about to read 6, iclass 30, count 0 2006.210.08:11:21.52#ibcon#read 6, iclass 30, count 0 2006.210.08:11:21.52#ibcon#end of sib2, iclass 30, count 0 2006.210.08:11:21.52#ibcon#*after write, iclass 30, count 0 2006.210.08:11:21.52#ibcon#*before return 0, iclass 30, count 0 2006.210.08:11:21.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:21.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:11:21.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:11:21.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:11:21.52$vc4f8/vb=5,3 2006.210.08:11:21.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.08:11:21.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.08:11:21.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:21.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:21.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:21.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:21.58#ibcon#enter wrdev, iclass 32, count 2 2006.210.08:11:21.58#ibcon#first serial, iclass 32, count 2 2006.210.08:11:21.58#ibcon#enter sib2, iclass 32, count 2 2006.210.08:11:21.58#ibcon#flushed, iclass 32, count 2 2006.210.08:11:21.58#ibcon#about to write, iclass 32, count 2 2006.210.08:11:21.58#ibcon#wrote, iclass 32, count 2 2006.210.08:11:21.58#ibcon#about to read 3, iclass 32, count 2 2006.210.08:11:21.60#ibcon#read 3, iclass 32, count 2 2006.210.08:11:21.60#ibcon#about to read 4, iclass 32, count 2 2006.210.08:11:21.60#ibcon#read 4, iclass 32, count 2 2006.210.08:11:21.60#ibcon#about to read 5, iclass 32, count 2 2006.210.08:11:21.60#ibcon#read 5, iclass 32, count 2 2006.210.08:11:21.60#ibcon#about to read 6, iclass 32, count 2 2006.210.08:11:21.60#ibcon#read 6, iclass 32, count 2 2006.210.08:11:21.60#ibcon#end of sib2, iclass 32, count 2 2006.210.08:11:21.60#ibcon#*mode == 0, iclass 32, count 2 2006.210.08:11:21.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.08:11:21.60#ibcon#[27=AT05-03\r\n] 2006.210.08:11:21.60#ibcon#*before write, iclass 32, count 2 2006.210.08:11:21.60#ibcon#enter sib2, iclass 32, count 2 2006.210.08:11:21.60#ibcon#flushed, iclass 32, count 2 2006.210.08:11:21.60#ibcon#about to write, iclass 32, count 2 2006.210.08:11:21.60#ibcon#wrote, iclass 32, count 2 2006.210.08:11:21.60#ibcon#about to read 3, iclass 32, count 2 2006.210.08:11:21.63#ibcon#read 3, iclass 32, count 2 2006.210.08:11:21.63#ibcon#about to read 4, iclass 32, count 2 2006.210.08:11:21.63#ibcon#read 4, iclass 32, count 2 2006.210.08:11:21.63#ibcon#about to read 5, iclass 32, count 2 2006.210.08:11:21.63#ibcon#read 5, iclass 32, count 2 2006.210.08:11:21.63#ibcon#about to read 6, iclass 32, count 2 2006.210.08:11:21.63#ibcon#read 6, iclass 32, count 2 2006.210.08:11:21.63#ibcon#end of sib2, iclass 32, count 2 2006.210.08:11:21.63#ibcon#*after write, iclass 32, count 2 2006.210.08:11:21.63#ibcon#*before return 0, iclass 32, count 2 2006.210.08:11:21.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:21.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:11:21.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.08:11:21.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:21.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:21.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:21.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:21.75#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:11:21.75#ibcon#first serial, iclass 32, count 0 2006.210.08:11:21.75#ibcon#enter sib2, iclass 32, count 0 2006.210.08:11:21.75#ibcon#flushed, iclass 32, count 0 2006.210.08:11:21.75#ibcon#about to write, iclass 32, count 0 2006.210.08:11:21.75#ibcon#wrote, iclass 32, count 0 2006.210.08:11:21.75#ibcon#about to read 3, iclass 32, count 0 2006.210.08:11:21.77#ibcon#read 3, iclass 32, count 0 2006.210.08:11:21.77#ibcon#about to read 4, iclass 32, count 0 2006.210.08:11:21.77#ibcon#read 4, iclass 32, count 0 2006.210.08:11:21.77#ibcon#about to read 5, iclass 32, count 0 2006.210.08:11:21.77#ibcon#read 5, iclass 32, count 0 2006.210.08:11:21.77#ibcon#about to read 6, iclass 32, count 0 2006.210.08:11:21.77#ibcon#read 6, iclass 32, count 0 2006.210.08:11:21.77#ibcon#end of sib2, iclass 32, count 0 2006.210.08:11:21.77#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:11:21.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:11:21.77#ibcon#[27=USB\r\n] 2006.210.08:11:21.77#ibcon#*before write, iclass 32, count 0 2006.210.08:11:21.77#ibcon#enter sib2, iclass 32, count 0 2006.210.08:11:21.77#ibcon#flushed, iclass 32, count 0 2006.210.08:11:21.77#ibcon#about to write, iclass 32, count 0 2006.210.08:11:21.77#ibcon#wrote, iclass 32, count 0 2006.210.08:11:21.77#ibcon#about to read 3, iclass 32, count 0 2006.210.08:11:21.80#ibcon#read 3, iclass 32, count 0 2006.210.08:11:21.80#ibcon#about to read 4, iclass 32, count 0 2006.210.08:11:21.80#ibcon#read 4, iclass 32, count 0 2006.210.08:11:21.80#ibcon#about to read 5, iclass 32, count 0 2006.210.08:11:21.80#ibcon#read 5, iclass 32, count 0 2006.210.08:11:21.80#ibcon#about to read 6, iclass 32, count 0 2006.210.08:11:21.80#ibcon#read 6, iclass 32, count 0 2006.210.08:11:21.80#ibcon#end of sib2, iclass 32, count 0 2006.210.08:11:21.80#ibcon#*after write, iclass 32, count 0 2006.210.08:11:21.80#ibcon#*before return 0, iclass 32, count 0 2006.210.08:11:21.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:21.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:11:21.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:11:21.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:11:21.80$vc4f8/vblo=6,752.99 2006.210.08:11:21.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:11:21.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:11:21.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:11:21.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:21.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:21.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:21.80#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:11:21.80#ibcon#first serial, iclass 34, count 0 2006.210.08:11:21.80#ibcon#enter sib2, iclass 34, count 0 2006.210.08:11:21.80#ibcon#flushed, iclass 34, count 0 2006.210.08:11:21.80#ibcon#about to write, iclass 34, count 0 2006.210.08:11:21.80#ibcon#wrote, iclass 34, count 0 2006.210.08:11:21.80#ibcon#about to read 3, iclass 34, count 0 2006.210.08:11:21.82#ibcon#read 3, iclass 34, count 0 2006.210.08:11:21.82#ibcon#about to read 4, iclass 34, count 0 2006.210.08:11:21.82#ibcon#read 4, iclass 34, count 0 2006.210.08:11:21.82#ibcon#about to read 5, iclass 34, count 0 2006.210.08:11:21.82#ibcon#read 5, iclass 34, count 0 2006.210.08:11:21.82#ibcon#about to read 6, iclass 34, count 0 2006.210.08:11:21.82#ibcon#read 6, iclass 34, count 0 2006.210.08:11:21.82#ibcon#end of sib2, iclass 34, count 0 2006.210.08:11:21.82#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:11:21.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:11:21.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:11:21.82#ibcon#*before write, iclass 34, count 0 2006.210.08:11:21.82#ibcon#enter sib2, iclass 34, count 0 2006.210.08:11:21.82#ibcon#flushed, iclass 34, count 0 2006.210.08:11:21.82#ibcon#about to write, iclass 34, count 0 2006.210.08:11:21.82#ibcon#wrote, iclass 34, count 0 2006.210.08:11:21.82#ibcon#about to read 3, iclass 34, count 0 2006.210.08:11:21.86#ibcon#read 3, iclass 34, count 0 2006.210.08:11:21.86#ibcon#about to read 4, iclass 34, count 0 2006.210.08:11:21.86#ibcon#read 4, iclass 34, count 0 2006.210.08:11:21.86#ibcon#about to read 5, iclass 34, count 0 2006.210.08:11:21.86#ibcon#read 5, iclass 34, count 0 2006.210.08:11:21.86#ibcon#about to read 6, iclass 34, count 0 2006.210.08:11:21.86#ibcon#read 6, iclass 34, count 0 2006.210.08:11:21.86#ibcon#end of sib2, iclass 34, count 0 2006.210.08:11:21.86#ibcon#*after write, iclass 34, count 0 2006.210.08:11:21.86#ibcon#*before return 0, iclass 34, count 0 2006.210.08:11:21.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:21.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:11:21.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:11:21.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:11:21.86$vc4f8/vb=6,3 2006.210.08:11:21.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.08:11:21.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.08:11:21.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:11:21.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:21.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:21.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:21.92#ibcon#enter wrdev, iclass 36, count 2 2006.210.08:11:21.92#ibcon#first serial, iclass 36, count 2 2006.210.08:11:21.92#ibcon#enter sib2, iclass 36, count 2 2006.210.08:11:21.92#ibcon#flushed, iclass 36, count 2 2006.210.08:11:21.92#ibcon#about to write, iclass 36, count 2 2006.210.08:11:21.92#ibcon#wrote, iclass 36, count 2 2006.210.08:11:21.92#ibcon#about to read 3, iclass 36, count 2 2006.210.08:11:21.94#ibcon#read 3, iclass 36, count 2 2006.210.08:11:21.94#ibcon#about to read 4, iclass 36, count 2 2006.210.08:11:21.94#ibcon#read 4, iclass 36, count 2 2006.210.08:11:21.94#ibcon#about to read 5, iclass 36, count 2 2006.210.08:11:21.94#ibcon#read 5, iclass 36, count 2 2006.210.08:11:21.94#ibcon#about to read 6, iclass 36, count 2 2006.210.08:11:21.94#ibcon#read 6, iclass 36, count 2 2006.210.08:11:21.94#ibcon#end of sib2, iclass 36, count 2 2006.210.08:11:21.94#ibcon#*mode == 0, iclass 36, count 2 2006.210.08:11:21.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.08:11:21.94#ibcon#[27=AT06-03\r\n] 2006.210.08:11:21.94#ibcon#*before write, iclass 36, count 2 2006.210.08:11:21.94#ibcon#enter sib2, iclass 36, count 2 2006.210.08:11:21.94#ibcon#flushed, iclass 36, count 2 2006.210.08:11:21.94#ibcon#about to write, iclass 36, count 2 2006.210.08:11:21.94#ibcon#wrote, iclass 36, count 2 2006.210.08:11:21.94#ibcon#about to read 3, iclass 36, count 2 2006.210.08:11:21.97#ibcon#read 3, iclass 36, count 2 2006.210.08:11:21.97#ibcon#about to read 4, iclass 36, count 2 2006.210.08:11:21.97#ibcon#read 4, iclass 36, count 2 2006.210.08:11:21.97#ibcon#about to read 5, iclass 36, count 2 2006.210.08:11:21.97#ibcon#read 5, iclass 36, count 2 2006.210.08:11:21.97#ibcon#about to read 6, iclass 36, count 2 2006.210.08:11:21.97#ibcon#read 6, iclass 36, count 2 2006.210.08:11:21.97#ibcon#end of sib2, iclass 36, count 2 2006.210.08:11:21.97#ibcon#*after write, iclass 36, count 2 2006.210.08:11:21.97#ibcon#*before return 0, iclass 36, count 2 2006.210.08:11:21.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:21.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:11:21.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.08:11:21.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:11:21.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:22.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:22.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:22.09#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:11:22.09#ibcon#first serial, iclass 36, count 0 2006.210.08:11:22.09#ibcon#enter sib2, iclass 36, count 0 2006.210.08:11:22.09#ibcon#flushed, iclass 36, count 0 2006.210.08:11:22.09#ibcon#about to write, iclass 36, count 0 2006.210.08:11:22.09#ibcon#wrote, iclass 36, count 0 2006.210.08:11:22.09#ibcon#about to read 3, iclass 36, count 0 2006.210.08:11:22.11#ibcon#read 3, iclass 36, count 0 2006.210.08:11:22.11#ibcon#about to read 4, iclass 36, count 0 2006.210.08:11:22.11#ibcon#read 4, iclass 36, count 0 2006.210.08:11:22.11#ibcon#about to read 5, iclass 36, count 0 2006.210.08:11:22.11#ibcon#read 5, iclass 36, count 0 2006.210.08:11:22.11#ibcon#about to read 6, iclass 36, count 0 2006.210.08:11:22.11#ibcon#read 6, iclass 36, count 0 2006.210.08:11:22.11#ibcon#end of sib2, iclass 36, count 0 2006.210.08:11:22.11#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:11:22.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:11:22.11#ibcon#[27=USB\r\n] 2006.210.08:11:22.11#ibcon#*before write, iclass 36, count 0 2006.210.08:11:22.11#ibcon#enter sib2, iclass 36, count 0 2006.210.08:11:22.11#ibcon#flushed, iclass 36, count 0 2006.210.08:11:22.11#ibcon#about to write, iclass 36, count 0 2006.210.08:11:22.11#ibcon#wrote, iclass 36, count 0 2006.210.08:11:22.11#ibcon#about to read 3, iclass 36, count 0 2006.210.08:11:22.14#ibcon#read 3, iclass 36, count 0 2006.210.08:11:22.14#ibcon#about to read 4, iclass 36, count 0 2006.210.08:11:22.14#ibcon#read 4, iclass 36, count 0 2006.210.08:11:22.14#ibcon#about to read 5, iclass 36, count 0 2006.210.08:11:22.14#ibcon#read 5, iclass 36, count 0 2006.210.08:11:22.14#ibcon#about to read 6, iclass 36, count 0 2006.210.08:11:22.14#ibcon#read 6, iclass 36, count 0 2006.210.08:11:22.14#ibcon#end of sib2, iclass 36, count 0 2006.210.08:11:22.14#ibcon#*after write, iclass 36, count 0 2006.210.08:11:22.14#ibcon#*before return 0, iclass 36, count 0 2006.210.08:11:22.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:22.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:11:22.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:11:22.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:11:22.14$vc4f8/vabw=wide 2006.210.08:11:22.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.08:11:22.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.08:11:22.15#ibcon#ireg 8 cls_cnt 0 2006.210.08:11:22.15#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:22.15#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:22.15#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:22.15#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:11:22.15#ibcon#first serial, iclass 38, count 0 2006.210.08:11:22.15#ibcon#enter sib2, iclass 38, count 0 2006.210.08:11:22.15#ibcon#flushed, iclass 38, count 0 2006.210.08:11:22.15#ibcon#about to write, iclass 38, count 0 2006.210.08:11:22.15#ibcon#wrote, iclass 38, count 0 2006.210.08:11:22.15#ibcon#about to read 3, iclass 38, count 0 2006.210.08:11:22.16#ibcon#read 3, iclass 38, count 0 2006.210.08:11:22.16#ibcon#about to read 4, iclass 38, count 0 2006.210.08:11:22.16#ibcon#read 4, iclass 38, count 0 2006.210.08:11:22.16#ibcon#about to read 5, iclass 38, count 0 2006.210.08:11:22.16#ibcon#read 5, iclass 38, count 0 2006.210.08:11:22.16#ibcon#about to read 6, iclass 38, count 0 2006.210.08:11:22.16#ibcon#read 6, iclass 38, count 0 2006.210.08:11:22.16#ibcon#end of sib2, iclass 38, count 0 2006.210.08:11:22.16#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:11:22.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:11:22.16#ibcon#[25=BW32\r\n] 2006.210.08:11:22.16#ibcon#*before write, iclass 38, count 0 2006.210.08:11:22.16#ibcon#enter sib2, iclass 38, count 0 2006.210.08:11:22.16#ibcon#flushed, iclass 38, count 0 2006.210.08:11:22.16#ibcon#about to write, iclass 38, count 0 2006.210.08:11:22.16#ibcon#wrote, iclass 38, count 0 2006.210.08:11:22.16#ibcon#about to read 3, iclass 38, count 0 2006.210.08:11:22.19#ibcon#read 3, iclass 38, count 0 2006.210.08:11:22.19#ibcon#about to read 4, iclass 38, count 0 2006.210.08:11:22.19#ibcon#read 4, iclass 38, count 0 2006.210.08:11:22.19#ibcon#about to read 5, iclass 38, count 0 2006.210.08:11:22.19#ibcon#read 5, iclass 38, count 0 2006.210.08:11:22.19#ibcon#about to read 6, iclass 38, count 0 2006.210.08:11:22.19#ibcon#read 6, iclass 38, count 0 2006.210.08:11:22.19#ibcon#end of sib2, iclass 38, count 0 2006.210.08:11:22.19#ibcon#*after write, iclass 38, count 0 2006.210.08:11:22.19#ibcon#*before return 0, iclass 38, count 0 2006.210.08:11:22.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:22.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:11:22.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:11:22.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:11:22.19$vc4f8/vbbw=wide 2006.210.08:11:22.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.08:11:22.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.08:11:22.19#ibcon#ireg 8 cls_cnt 0 2006.210.08:11:22.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:11:22.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:11:22.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:11:22.26#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:11:22.26#ibcon#first serial, iclass 40, count 0 2006.210.08:11:22.26#ibcon#enter sib2, iclass 40, count 0 2006.210.08:11:22.26#ibcon#flushed, iclass 40, count 0 2006.210.08:11:22.26#ibcon#about to write, iclass 40, count 0 2006.210.08:11:22.26#ibcon#wrote, iclass 40, count 0 2006.210.08:11:22.26#ibcon#about to read 3, iclass 40, count 0 2006.210.08:11:22.28#ibcon#read 3, iclass 40, count 0 2006.210.08:11:22.28#ibcon#about to read 4, iclass 40, count 0 2006.210.08:11:22.28#ibcon#read 4, iclass 40, count 0 2006.210.08:11:22.28#ibcon#about to read 5, iclass 40, count 0 2006.210.08:11:22.28#ibcon#read 5, iclass 40, count 0 2006.210.08:11:22.28#ibcon#about to read 6, iclass 40, count 0 2006.210.08:11:22.28#ibcon#read 6, iclass 40, count 0 2006.210.08:11:22.28#ibcon#end of sib2, iclass 40, count 0 2006.210.08:11:22.28#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:11:22.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:11:22.28#ibcon#[27=BW32\r\n] 2006.210.08:11:22.28#ibcon#*before write, iclass 40, count 0 2006.210.08:11:22.28#ibcon#enter sib2, iclass 40, count 0 2006.210.08:11:22.28#ibcon#flushed, iclass 40, count 0 2006.210.08:11:22.28#ibcon#about to write, iclass 40, count 0 2006.210.08:11:22.28#ibcon#wrote, iclass 40, count 0 2006.210.08:11:22.28#ibcon#about to read 3, iclass 40, count 0 2006.210.08:11:22.31#ibcon#read 3, iclass 40, count 0 2006.210.08:11:22.31#ibcon#about to read 4, iclass 40, count 0 2006.210.08:11:22.31#ibcon#read 4, iclass 40, count 0 2006.210.08:11:22.31#ibcon#about to read 5, iclass 40, count 0 2006.210.08:11:22.31#ibcon#read 5, iclass 40, count 0 2006.210.08:11:22.31#ibcon#about to read 6, iclass 40, count 0 2006.210.08:11:22.31#ibcon#read 6, iclass 40, count 0 2006.210.08:11:22.31#ibcon#end of sib2, iclass 40, count 0 2006.210.08:11:22.31#ibcon#*after write, iclass 40, count 0 2006.210.08:11:22.31#ibcon#*before return 0, iclass 40, count 0 2006.210.08:11:22.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:11:22.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:11:22.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:11:22.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:11:22.31$4f8m12a/ifd4f 2006.210.08:11:22.31$ifd4f/lo= 2006.210.08:11:22.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:11:22.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:11:22.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:11:22.32$ifd4f/patch= 2006.210.08:11:22.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:11:22.32$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:11:22.32$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:11:22.32$4f8m12a/"form=m,16.000,1:2 2006.210.08:11:22.32$4f8m12a/"tpicd 2006.210.08:11:22.32$4f8m12a/echo=off 2006.210.08:11:22.32$4f8m12a/xlog=off 2006.210.08:11:22.32:!2006.210.08:11:50 2006.210.08:11:33.14#trakl#Source acquired 2006.210.08:11:35.14#flagr#flagr/antenna,acquired 2006.210.08:11:50.01:preob 2006.210.08:11:51.14/onsource/TRACKING 2006.210.08:11:51.14:!2006.210.08:12:00 2006.210.08:12:00.00:data_valid=on 2006.210.08:12:00.00:midob 2006.210.08:12:00.14/onsource/TRACKING 2006.210.08:12:00.14/wx/30.11,1006.5,82 2006.210.08:12:00.25/cable/+6.3934E-03 2006.210.08:12:01.34/va/01,08,usb,yes,30,32 2006.210.08:12:01.34/va/02,07,usb,yes,31,32 2006.210.08:12:01.34/va/03,06,usb,yes,32,33 2006.210.08:12:01.34/va/04,07,usb,yes,32,34 2006.210.08:12:01.34/va/05,07,usb,yes,33,35 2006.210.08:12:01.34/va/06,06,usb,yes,32,32 2006.210.08:12:01.34/va/07,06,usb,yes,33,33 2006.210.08:12:01.34/va/08,07,usb,yes,31,31 2006.210.08:12:01.57/valo/01,532.99,yes,locked 2006.210.08:12:01.57/valo/02,572.99,yes,locked 2006.210.08:12:01.57/valo/03,672.99,yes,locked 2006.210.08:12:01.57/valo/04,832.99,yes,locked 2006.210.08:12:01.57/valo/05,652.99,yes,locked 2006.210.08:12:01.57/valo/06,772.99,yes,locked 2006.210.08:12:01.57/valo/07,832.99,yes,locked 2006.210.08:12:01.57/valo/08,852.99,yes,locked 2006.210.08:12:02.66/vb/01,04,usb,yes,30,28 2006.210.08:12:02.66/vb/02,04,usb,yes,31,33 2006.210.08:12:02.66/vb/03,03,usb,yes,35,39 2006.210.08:12:02.66/vb/04,03,usb,yes,36,36 2006.210.08:12:02.66/vb/05,03,usb,yes,34,39 2006.210.08:12:02.66/vb/06,03,usb,yes,35,38 2006.210.08:12:02.66/vb/07,04,usb,yes,30,31 2006.210.08:12:02.66/vb/08,03,usb,yes,35,39 2006.210.08:12:02.90/vblo/01,632.99,yes,locked 2006.210.08:12:02.90/vblo/02,640.99,yes,locked 2006.210.08:12:02.90/vblo/03,656.99,yes,locked 2006.210.08:12:02.90/vblo/04,712.99,yes,locked 2006.210.08:12:02.90/vblo/05,744.99,yes,locked 2006.210.08:12:02.90/vblo/06,752.99,yes,locked 2006.210.08:12:02.90/vblo/07,734.99,yes,locked 2006.210.08:12:02.90/vblo/08,744.99,yes,locked 2006.210.08:12:03.05/vabw/8 2006.210.08:12:03.20/vbbw/8 2006.210.08:12:03.29/xfe/off,on,12.5 2006.210.08:12:03.66/ifatt/23,28,28,28 2006.210.08:12:04.07/fmout-gps/S +4.59E-07 2006.210.08:12:04.11:!2006.210.08:13:00 2006.210.08:13:00.01:data_valid=off 2006.210.08:13:00.01:postob 2006.210.08:13:00.25/cable/+6.3922E-03 2006.210.08:13:00.25/wx/30.07,1006.5,82 2006.210.08:13:01.07/fmout-gps/S +4.58E-07 2006.210.08:13:01.07:scan_name=210-0814,k06210,60 2006.210.08:13:01.07:source=1418+546,141946.60,542314.8,2000.0,neutral 2006.210.08:13:01.14#flagr#flagr/antenna,new-source 2006.210.08:13:02.14:checkk5 2006.210.08:13:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:13:02.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:13:03.16/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:13:03.50/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:13:03.84/chk_obsdata//k5ts1/T2100812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:13:04.17/chk_obsdata//k5ts2/T2100812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:13:04.51/chk_obsdata//k5ts3/T2100812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:13:04.84/chk_obsdata//k5ts4/T2100812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:13:05.50/k5log//k5ts1_log_newline 2006.210.08:13:06.16/k5log//k5ts2_log_newline 2006.210.08:13:06.82/k5log//k5ts3_log_newline 2006.210.08:13:07.48/k5log//k5ts4_log_newline 2006.210.08:13:07.50/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:13:07.50:4f8m12a=2 2006.210.08:13:07.50$4f8m12a/echo=on 2006.210.08:13:07.50$4f8m12a/pcalon 2006.210.08:13:07.50$pcalon/"no phase cal control is implemented here 2006.210.08:13:07.50$4f8m12a/"tpicd=stop 2006.210.08:13:07.50$4f8m12a/vc4f8 2006.210.08:13:07.50$vc4f8/valo=1,532.99 2006.210.08:13:07.50#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.08:13:07.50#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.08:13:07.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:07.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:07.50#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:07.50#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:07.50#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:13:07.50#ibcon#first serial, iclass 11, count 0 2006.210.08:13:07.50#ibcon#enter sib2, iclass 11, count 0 2006.210.08:13:07.50#ibcon#flushed, iclass 11, count 0 2006.210.08:13:07.50#ibcon#about to write, iclass 11, count 0 2006.210.08:13:07.51#ibcon#wrote, iclass 11, count 0 2006.210.08:13:07.51#ibcon#about to read 3, iclass 11, count 0 2006.210.08:13:07.52#ibcon#read 3, iclass 11, count 0 2006.210.08:13:07.52#ibcon#about to read 4, iclass 11, count 0 2006.210.08:13:07.52#ibcon#read 4, iclass 11, count 0 2006.210.08:13:07.52#ibcon#about to read 5, iclass 11, count 0 2006.210.08:13:07.52#ibcon#read 5, iclass 11, count 0 2006.210.08:13:07.52#ibcon#about to read 6, iclass 11, count 0 2006.210.08:13:07.52#ibcon#read 6, iclass 11, count 0 2006.210.08:13:07.52#ibcon#end of sib2, iclass 11, count 0 2006.210.08:13:07.52#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:13:07.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:13:07.52#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:13:07.52#ibcon#*before write, iclass 11, count 0 2006.210.08:13:07.52#ibcon#enter sib2, iclass 11, count 0 2006.210.08:13:07.52#ibcon#flushed, iclass 11, count 0 2006.210.08:13:07.52#ibcon#about to write, iclass 11, count 0 2006.210.08:13:07.52#ibcon#wrote, iclass 11, count 0 2006.210.08:13:07.52#ibcon#about to read 3, iclass 11, count 0 2006.210.08:13:07.57#ibcon#read 3, iclass 11, count 0 2006.210.08:13:07.57#ibcon#about to read 4, iclass 11, count 0 2006.210.08:13:07.57#ibcon#read 4, iclass 11, count 0 2006.210.08:13:07.57#ibcon#about to read 5, iclass 11, count 0 2006.210.08:13:07.57#ibcon#read 5, iclass 11, count 0 2006.210.08:13:07.57#ibcon#about to read 6, iclass 11, count 0 2006.210.08:13:07.57#ibcon#read 6, iclass 11, count 0 2006.210.08:13:07.57#ibcon#end of sib2, iclass 11, count 0 2006.210.08:13:07.57#ibcon#*after write, iclass 11, count 0 2006.210.08:13:07.57#ibcon#*before return 0, iclass 11, count 0 2006.210.08:13:07.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:07.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:07.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:13:07.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:13:07.57$vc4f8/va=1,8 2006.210.08:13:07.57#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.08:13:07.57#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.08:13:07.57#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:07.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:07.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:07.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:07.57#ibcon#enter wrdev, iclass 13, count 2 2006.210.08:13:07.57#ibcon#first serial, iclass 13, count 2 2006.210.08:13:07.57#ibcon#enter sib2, iclass 13, count 2 2006.210.08:13:07.57#ibcon#flushed, iclass 13, count 2 2006.210.08:13:07.57#ibcon#about to write, iclass 13, count 2 2006.210.08:13:07.57#ibcon#wrote, iclass 13, count 2 2006.210.08:13:07.57#ibcon#about to read 3, iclass 13, count 2 2006.210.08:13:07.59#ibcon#read 3, iclass 13, count 2 2006.210.08:13:07.59#ibcon#about to read 4, iclass 13, count 2 2006.210.08:13:07.59#ibcon#read 4, iclass 13, count 2 2006.210.08:13:07.59#ibcon#about to read 5, iclass 13, count 2 2006.210.08:13:07.59#ibcon#read 5, iclass 13, count 2 2006.210.08:13:07.59#ibcon#about to read 6, iclass 13, count 2 2006.210.08:13:07.59#ibcon#read 6, iclass 13, count 2 2006.210.08:13:07.59#ibcon#end of sib2, iclass 13, count 2 2006.210.08:13:07.59#ibcon#*mode == 0, iclass 13, count 2 2006.210.08:13:07.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.08:13:07.59#ibcon#[25=AT01-08\r\n] 2006.210.08:13:07.59#ibcon#*before write, iclass 13, count 2 2006.210.08:13:07.59#ibcon#enter sib2, iclass 13, count 2 2006.210.08:13:07.59#ibcon#flushed, iclass 13, count 2 2006.210.08:13:07.59#ibcon#about to write, iclass 13, count 2 2006.210.08:13:07.59#ibcon#wrote, iclass 13, count 2 2006.210.08:13:07.59#ibcon#about to read 3, iclass 13, count 2 2006.210.08:13:07.62#ibcon#read 3, iclass 13, count 2 2006.210.08:13:07.62#ibcon#about to read 4, iclass 13, count 2 2006.210.08:13:07.62#ibcon#read 4, iclass 13, count 2 2006.210.08:13:07.62#ibcon#about to read 5, iclass 13, count 2 2006.210.08:13:07.62#ibcon#read 5, iclass 13, count 2 2006.210.08:13:07.62#ibcon#about to read 6, iclass 13, count 2 2006.210.08:13:07.62#ibcon#read 6, iclass 13, count 2 2006.210.08:13:07.62#ibcon#end of sib2, iclass 13, count 2 2006.210.08:13:07.62#ibcon#*after write, iclass 13, count 2 2006.210.08:13:07.62#ibcon#*before return 0, iclass 13, count 2 2006.210.08:13:07.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:07.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:07.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.08:13:07.62#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:07.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:07.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:07.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:07.74#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:13:07.74#ibcon#first serial, iclass 13, count 0 2006.210.08:13:07.74#ibcon#enter sib2, iclass 13, count 0 2006.210.08:13:07.74#ibcon#flushed, iclass 13, count 0 2006.210.08:13:07.74#ibcon#about to write, iclass 13, count 0 2006.210.08:13:07.74#ibcon#wrote, iclass 13, count 0 2006.210.08:13:07.74#ibcon#about to read 3, iclass 13, count 0 2006.210.08:13:07.76#ibcon#read 3, iclass 13, count 0 2006.210.08:13:07.76#ibcon#about to read 4, iclass 13, count 0 2006.210.08:13:07.76#ibcon#read 4, iclass 13, count 0 2006.210.08:13:07.76#ibcon#about to read 5, iclass 13, count 0 2006.210.08:13:07.76#ibcon#read 5, iclass 13, count 0 2006.210.08:13:07.76#ibcon#about to read 6, iclass 13, count 0 2006.210.08:13:07.76#ibcon#read 6, iclass 13, count 0 2006.210.08:13:07.76#ibcon#end of sib2, iclass 13, count 0 2006.210.08:13:07.76#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:13:07.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:13:07.76#ibcon#[25=USB\r\n] 2006.210.08:13:07.76#ibcon#*before write, iclass 13, count 0 2006.210.08:13:07.76#ibcon#enter sib2, iclass 13, count 0 2006.210.08:13:07.76#ibcon#flushed, iclass 13, count 0 2006.210.08:13:07.76#ibcon#about to write, iclass 13, count 0 2006.210.08:13:07.76#ibcon#wrote, iclass 13, count 0 2006.210.08:13:07.76#ibcon#about to read 3, iclass 13, count 0 2006.210.08:13:07.79#ibcon#read 3, iclass 13, count 0 2006.210.08:13:07.79#ibcon#about to read 4, iclass 13, count 0 2006.210.08:13:07.79#ibcon#read 4, iclass 13, count 0 2006.210.08:13:07.79#ibcon#about to read 5, iclass 13, count 0 2006.210.08:13:07.79#ibcon#read 5, iclass 13, count 0 2006.210.08:13:07.79#ibcon#about to read 6, iclass 13, count 0 2006.210.08:13:07.79#ibcon#read 6, iclass 13, count 0 2006.210.08:13:07.79#ibcon#end of sib2, iclass 13, count 0 2006.210.08:13:07.79#ibcon#*after write, iclass 13, count 0 2006.210.08:13:07.79#ibcon#*before return 0, iclass 13, count 0 2006.210.08:13:07.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:07.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:07.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:13:07.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:13:07.79$vc4f8/valo=2,572.99 2006.210.08:13:07.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.08:13:07.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.08:13:07.79#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:07.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:07.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:07.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:07.79#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:13:07.79#ibcon#first serial, iclass 15, count 0 2006.210.08:13:07.79#ibcon#enter sib2, iclass 15, count 0 2006.210.08:13:07.79#ibcon#flushed, iclass 15, count 0 2006.210.08:13:07.79#ibcon#about to write, iclass 15, count 0 2006.210.08:13:07.79#ibcon#wrote, iclass 15, count 0 2006.210.08:13:07.79#ibcon#about to read 3, iclass 15, count 0 2006.210.08:13:07.81#ibcon#read 3, iclass 15, count 0 2006.210.08:13:07.81#ibcon#about to read 4, iclass 15, count 0 2006.210.08:13:07.81#ibcon#read 4, iclass 15, count 0 2006.210.08:13:07.81#ibcon#about to read 5, iclass 15, count 0 2006.210.08:13:07.81#ibcon#read 5, iclass 15, count 0 2006.210.08:13:07.81#ibcon#about to read 6, iclass 15, count 0 2006.210.08:13:07.81#ibcon#read 6, iclass 15, count 0 2006.210.08:13:07.81#ibcon#end of sib2, iclass 15, count 0 2006.210.08:13:07.81#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:13:07.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:13:07.81#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:13:07.81#ibcon#*before write, iclass 15, count 0 2006.210.08:13:07.81#ibcon#enter sib2, iclass 15, count 0 2006.210.08:13:07.81#ibcon#flushed, iclass 15, count 0 2006.210.08:13:07.81#ibcon#about to write, iclass 15, count 0 2006.210.08:13:07.81#ibcon#wrote, iclass 15, count 0 2006.210.08:13:07.81#ibcon#about to read 3, iclass 15, count 0 2006.210.08:13:07.85#ibcon#read 3, iclass 15, count 0 2006.210.08:13:07.85#ibcon#about to read 4, iclass 15, count 0 2006.210.08:13:07.85#ibcon#read 4, iclass 15, count 0 2006.210.08:13:07.85#ibcon#about to read 5, iclass 15, count 0 2006.210.08:13:07.85#ibcon#read 5, iclass 15, count 0 2006.210.08:13:07.85#ibcon#about to read 6, iclass 15, count 0 2006.210.08:13:07.85#ibcon#read 6, iclass 15, count 0 2006.210.08:13:07.85#ibcon#end of sib2, iclass 15, count 0 2006.210.08:13:07.85#ibcon#*after write, iclass 15, count 0 2006.210.08:13:07.85#ibcon#*before return 0, iclass 15, count 0 2006.210.08:13:07.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:07.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:07.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:13:07.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:13:07.85$vc4f8/va=2,7 2006.210.08:13:07.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.08:13:07.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.08:13:07.85#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:07.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:07.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:07.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:07.91#ibcon#enter wrdev, iclass 17, count 2 2006.210.08:13:07.91#ibcon#first serial, iclass 17, count 2 2006.210.08:13:07.91#ibcon#enter sib2, iclass 17, count 2 2006.210.08:13:07.91#ibcon#flushed, iclass 17, count 2 2006.210.08:13:07.91#ibcon#about to write, iclass 17, count 2 2006.210.08:13:07.91#ibcon#wrote, iclass 17, count 2 2006.210.08:13:07.91#ibcon#about to read 3, iclass 17, count 2 2006.210.08:13:07.93#ibcon#read 3, iclass 17, count 2 2006.210.08:13:07.93#ibcon#about to read 4, iclass 17, count 2 2006.210.08:13:07.93#ibcon#read 4, iclass 17, count 2 2006.210.08:13:07.93#ibcon#about to read 5, iclass 17, count 2 2006.210.08:13:07.93#ibcon#read 5, iclass 17, count 2 2006.210.08:13:07.93#ibcon#about to read 6, iclass 17, count 2 2006.210.08:13:07.93#ibcon#read 6, iclass 17, count 2 2006.210.08:13:07.93#ibcon#end of sib2, iclass 17, count 2 2006.210.08:13:07.93#ibcon#*mode == 0, iclass 17, count 2 2006.210.08:13:07.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.08:13:07.93#ibcon#[25=AT02-07\r\n] 2006.210.08:13:07.93#ibcon#*before write, iclass 17, count 2 2006.210.08:13:07.93#ibcon#enter sib2, iclass 17, count 2 2006.210.08:13:07.93#ibcon#flushed, iclass 17, count 2 2006.210.08:13:07.93#ibcon#about to write, iclass 17, count 2 2006.210.08:13:07.93#ibcon#wrote, iclass 17, count 2 2006.210.08:13:07.93#ibcon#about to read 3, iclass 17, count 2 2006.210.08:13:07.96#ibcon#read 3, iclass 17, count 2 2006.210.08:13:07.96#ibcon#about to read 4, iclass 17, count 2 2006.210.08:13:07.96#ibcon#read 4, iclass 17, count 2 2006.210.08:13:07.96#ibcon#about to read 5, iclass 17, count 2 2006.210.08:13:07.96#ibcon#read 5, iclass 17, count 2 2006.210.08:13:07.96#ibcon#about to read 6, iclass 17, count 2 2006.210.08:13:07.96#ibcon#read 6, iclass 17, count 2 2006.210.08:13:07.96#ibcon#end of sib2, iclass 17, count 2 2006.210.08:13:07.96#ibcon#*after write, iclass 17, count 2 2006.210.08:13:07.96#ibcon#*before return 0, iclass 17, count 2 2006.210.08:13:07.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:07.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:07.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.08:13:07.96#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:07.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:08.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:08.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:08.08#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:13:08.08#ibcon#first serial, iclass 17, count 0 2006.210.08:13:08.08#ibcon#enter sib2, iclass 17, count 0 2006.210.08:13:08.08#ibcon#flushed, iclass 17, count 0 2006.210.08:13:08.08#ibcon#about to write, iclass 17, count 0 2006.210.08:13:08.08#ibcon#wrote, iclass 17, count 0 2006.210.08:13:08.08#ibcon#about to read 3, iclass 17, count 0 2006.210.08:13:08.10#ibcon#read 3, iclass 17, count 0 2006.210.08:13:08.10#ibcon#about to read 4, iclass 17, count 0 2006.210.08:13:08.10#ibcon#read 4, iclass 17, count 0 2006.210.08:13:08.10#ibcon#about to read 5, iclass 17, count 0 2006.210.08:13:08.10#ibcon#read 5, iclass 17, count 0 2006.210.08:13:08.10#ibcon#about to read 6, iclass 17, count 0 2006.210.08:13:08.10#ibcon#read 6, iclass 17, count 0 2006.210.08:13:08.10#ibcon#end of sib2, iclass 17, count 0 2006.210.08:13:08.10#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:13:08.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:13:08.10#ibcon#[25=USB\r\n] 2006.210.08:13:08.10#ibcon#*before write, iclass 17, count 0 2006.210.08:13:08.10#ibcon#enter sib2, iclass 17, count 0 2006.210.08:13:08.10#ibcon#flushed, iclass 17, count 0 2006.210.08:13:08.10#ibcon#about to write, iclass 17, count 0 2006.210.08:13:08.10#ibcon#wrote, iclass 17, count 0 2006.210.08:13:08.10#ibcon#about to read 3, iclass 17, count 0 2006.210.08:13:08.13#ibcon#read 3, iclass 17, count 0 2006.210.08:13:08.13#ibcon#about to read 4, iclass 17, count 0 2006.210.08:13:08.13#ibcon#read 4, iclass 17, count 0 2006.210.08:13:08.13#ibcon#about to read 5, iclass 17, count 0 2006.210.08:13:08.13#ibcon#read 5, iclass 17, count 0 2006.210.08:13:08.13#ibcon#about to read 6, iclass 17, count 0 2006.210.08:13:08.13#ibcon#read 6, iclass 17, count 0 2006.210.08:13:08.13#ibcon#end of sib2, iclass 17, count 0 2006.210.08:13:08.13#ibcon#*after write, iclass 17, count 0 2006.210.08:13:08.13#ibcon#*before return 0, iclass 17, count 0 2006.210.08:13:08.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:08.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:08.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:13:08.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:13:08.13$vc4f8/valo=3,672.99 2006.210.08:13:08.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.08:13:08.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.08:13:08.13#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:08.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:08.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:08.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:08.13#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:13:08.13#ibcon#first serial, iclass 19, count 0 2006.210.08:13:08.13#ibcon#enter sib2, iclass 19, count 0 2006.210.08:13:08.13#ibcon#flushed, iclass 19, count 0 2006.210.08:13:08.13#ibcon#about to write, iclass 19, count 0 2006.210.08:13:08.13#ibcon#wrote, iclass 19, count 0 2006.210.08:13:08.13#ibcon#about to read 3, iclass 19, count 0 2006.210.08:13:08.15#ibcon#read 3, iclass 19, count 0 2006.210.08:13:08.15#ibcon#about to read 4, iclass 19, count 0 2006.210.08:13:08.15#ibcon#read 4, iclass 19, count 0 2006.210.08:13:08.15#ibcon#about to read 5, iclass 19, count 0 2006.210.08:13:08.15#ibcon#read 5, iclass 19, count 0 2006.210.08:13:08.15#ibcon#about to read 6, iclass 19, count 0 2006.210.08:13:08.15#ibcon#read 6, iclass 19, count 0 2006.210.08:13:08.15#ibcon#end of sib2, iclass 19, count 0 2006.210.08:13:08.15#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:13:08.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:13:08.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:13:08.15#ibcon#*before write, iclass 19, count 0 2006.210.08:13:08.15#ibcon#enter sib2, iclass 19, count 0 2006.210.08:13:08.15#ibcon#flushed, iclass 19, count 0 2006.210.08:13:08.15#ibcon#about to write, iclass 19, count 0 2006.210.08:13:08.15#ibcon#wrote, iclass 19, count 0 2006.210.08:13:08.15#ibcon#about to read 3, iclass 19, count 0 2006.210.08:13:08.19#ibcon#read 3, iclass 19, count 0 2006.210.08:13:08.19#ibcon#about to read 4, iclass 19, count 0 2006.210.08:13:08.19#ibcon#read 4, iclass 19, count 0 2006.210.08:13:08.19#ibcon#about to read 5, iclass 19, count 0 2006.210.08:13:08.19#ibcon#read 5, iclass 19, count 0 2006.210.08:13:08.19#ibcon#about to read 6, iclass 19, count 0 2006.210.08:13:08.19#ibcon#read 6, iclass 19, count 0 2006.210.08:13:08.19#ibcon#end of sib2, iclass 19, count 0 2006.210.08:13:08.19#ibcon#*after write, iclass 19, count 0 2006.210.08:13:08.19#ibcon#*before return 0, iclass 19, count 0 2006.210.08:13:08.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:08.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:08.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:13:08.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:13:08.19$vc4f8/va=3,6 2006.210.08:13:08.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.08:13:08.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.08:13:08.19#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:08.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:08.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:08.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:08.25#ibcon#enter wrdev, iclass 21, count 2 2006.210.08:13:08.25#ibcon#first serial, iclass 21, count 2 2006.210.08:13:08.25#ibcon#enter sib2, iclass 21, count 2 2006.210.08:13:08.25#ibcon#flushed, iclass 21, count 2 2006.210.08:13:08.25#ibcon#about to write, iclass 21, count 2 2006.210.08:13:08.25#ibcon#wrote, iclass 21, count 2 2006.210.08:13:08.25#ibcon#about to read 3, iclass 21, count 2 2006.210.08:13:08.27#ibcon#read 3, iclass 21, count 2 2006.210.08:13:08.27#ibcon#about to read 4, iclass 21, count 2 2006.210.08:13:08.27#ibcon#read 4, iclass 21, count 2 2006.210.08:13:08.27#ibcon#about to read 5, iclass 21, count 2 2006.210.08:13:08.27#ibcon#read 5, iclass 21, count 2 2006.210.08:13:08.27#ibcon#about to read 6, iclass 21, count 2 2006.210.08:13:08.27#ibcon#read 6, iclass 21, count 2 2006.210.08:13:08.27#ibcon#end of sib2, iclass 21, count 2 2006.210.08:13:08.27#ibcon#*mode == 0, iclass 21, count 2 2006.210.08:13:08.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.08:13:08.27#ibcon#[25=AT03-06\r\n] 2006.210.08:13:08.27#ibcon#*before write, iclass 21, count 2 2006.210.08:13:08.27#ibcon#enter sib2, iclass 21, count 2 2006.210.08:13:08.27#ibcon#flushed, iclass 21, count 2 2006.210.08:13:08.27#ibcon#about to write, iclass 21, count 2 2006.210.08:13:08.27#ibcon#wrote, iclass 21, count 2 2006.210.08:13:08.27#ibcon#about to read 3, iclass 21, count 2 2006.210.08:13:08.30#ibcon#read 3, iclass 21, count 2 2006.210.08:13:08.30#ibcon#about to read 4, iclass 21, count 2 2006.210.08:13:08.30#ibcon#read 4, iclass 21, count 2 2006.210.08:13:08.30#ibcon#about to read 5, iclass 21, count 2 2006.210.08:13:08.30#ibcon#read 5, iclass 21, count 2 2006.210.08:13:08.30#ibcon#about to read 6, iclass 21, count 2 2006.210.08:13:08.30#ibcon#read 6, iclass 21, count 2 2006.210.08:13:08.30#ibcon#end of sib2, iclass 21, count 2 2006.210.08:13:08.30#ibcon#*after write, iclass 21, count 2 2006.210.08:13:08.30#ibcon#*before return 0, iclass 21, count 2 2006.210.08:13:08.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:08.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:08.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.08:13:08.30#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:08.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:08.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:08.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:08.42#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:13:08.42#ibcon#first serial, iclass 21, count 0 2006.210.08:13:08.42#ibcon#enter sib2, iclass 21, count 0 2006.210.08:13:08.42#ibcon#flushed, iclass 21, count 0 2006.210.08:13:08.42#ibcon#about to write, iclass 21, count 0 2006.210.08:13:08.42#ibcon#wrote, iclass 21, count 0 2006.210.08:13:08.42#ibcon#about to read 3, iclass 21, count 0 2006.210.08:13:08.44#ibcon#read 3, iclass 21, count 0 2006.210.08:13:08.44#ibcon#about to read 4, iclass 21, count 0 2006.210.08:13:08.44#ibcon#read 4, iclass 21, count 0 2006.210.08:13:08.44#ibcon#about to read 5, iclass 21, count 0 2006.210.08:13:08.44#ibcon#read 5, iclass 21, count 0 2006.210.08:13:08.44#ibcon#about to read 6, iclass 21, count 0 2006.210.08:13:08.44#ibcon#read 6, iclass 21, count 0 2006.210.08:13:08.44#ibcon#end of sib2, iclass 21, count 0 2006.210.08:13:08.44#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:13:08.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:13:08.44#ibcon#[25=USB\r\n] 2006.210.08:13:08.44#ibcon#*before write, iclass 21, count 0 2006.210.08:13:08.44#ibcon#enter sib2, iclass 21, count 0 2006.210.08:13:08.44#ibcon#flushed, iclass 21, count 0 2006.210.08:13:08.44#ibcon#about to write, iclass 21, count 0 2006.210.08:13:08.44#ibcon#wrote, iclass 21, count 0 2006.210.08:13:08.44#ibcon#about to read 3, iclass 21, count 0 2006.210.08:13:08.47#ibcon#read 3, iclass 21, count 0 2006.210.08:13:08.47#ibcon#about to read 4, iclass 21, count 0 2006.210.08:13:08.47#ibcon#read 4, iclass 21, count 0 2006.210.08:13:08.47#ibcon#about to read 5, iclass 21, count 0 2006.210.08:13:08.47#ibcon#read 5, iclass 21, count 0 2006.210.08:13:08.47#ibcon#about to read 6, iclass 21, count 0 2006.210.08:13:08.47#ibcon#read 6, iclass 21, count 0 2006.210.08:13:08.47#ibcon#end of sib2, iclass 21, count 0 2006.210.08:13:08.47#ibcon#*after write, iclass 21, count 0 2006.210.08:13:08.47#ibcon#*before return 0, iclass 21, count 0 2006.210.08:13:08.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:08.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:08.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:13:08.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:13:08.47$vc4f8/valo=4,832.99 2006.210.08:13:08.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.08:13:08.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.08:13:08.47#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:08.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:08.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:08.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:08.47#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:13:08.47#ibcon#first serial, iclass 23, count 0 2006.210.08:13:08.47#ibcon#enter sib2, iclass 23, count 0 2006.210.08:13:08.47#ibcon#flushed, iclass 23, count 0 2006.210.08:13:08.47#ibcon#about to write, iclass 23, count 0 2006.210.08:13:08.47#ibcon#wrote, iclass 23, count 0 2006.210.08:13:08.47#ibcon#about to read 3, iclass 23, count 0 2006.210.08:13:08.49#ibcon#read 3, iclass 23, count 0 2006.210.08:13:08.49#ibcon#about to read 4, iclass 23, count 0 2006.210.08:13:08.49#ibcon#read 4, iclass 23, count 0 2006.210.08:13:08.49#ibcon#about to read 5, iclass 23, count 0 2006.210.08:13:08.49#ibcon#read 5, iclass 23, count 0 2006.210.08:13:08.49#ibcon#about to read 6, iclass 23, count 0 2006.210.08:13:08.49#ibcon#read 6, iclass 23, count 0 2006.210.08:13:08.49#ibcon#end of sib2, iclass 23, count 0 2006.210.08:13:08.49#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:13:08.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:13:08.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:13:08.49#ibcon#*before write, iclass 23, count 0 2006.210.08:13:08.49#ibcon#enter sib2, iclass 23, count 0 2006.210.08:13:08.49#ibcon#flushed, iclass 23, count 0 2006.210.08:13:08.49#ibcon#about to write, iclass 23, count 0 2006.210.08:13:08.49#ibcon#wrote, iclass 23, count 0 2006.210.08:13:08.49#ibcon#about to read 3, iclass 23, count 0 2006.210.08:13:08.53#ibcon#read 3, iclass 23, count 0 2006.210.08:13:08.53#ibcon#about to read 4, iclass 23, count 0 2006.210.08:13:08.53#ibcon#read 4, iclass 23, count 0 2006.210.08:13:08.53#ibcon#about to read 5, iclass 23, count 0 2006.210.08:13:08.53#ibcon#read 5, iclass 23, count 0 2006.210.08:13:08.53#ibcon#about to read 6, iclass 23, count 0 2006.210.08:13:08.53#ibcon#read 6, iclass 23, count 0 2006.210.08:13:08.53#ibcon#end of sib2, iclass 23, count 0 2006.210.08:13:08.53#ibcon#*after write, iclass 23, count 0 2006.210.08:13:08.53#ibcon#*before return 0, iclass 23, count 0 2006.210.08:13:08.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:08.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:08.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:13:08.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:13:08.53$vc4f8/va=4,7 2006.210.08:13:08.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.08:13:08.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.08:13:08.53#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:08.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:08.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:08.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:08.59#ibcon#enter wrdev, iclass 25, count 2 2006.210.08:13:08.59#ibcon#first serial, iclass 25, count 2 2006.210.08:13:08.59#ibcon#enter sib2, iclass 25, count 2 2006.210.08:13:08.59#ibcon#flushed, iclass 25, count 2 2006.210.08:13:08.59#ibcon#about to write, iclass 25, count 2 2006.210.08:13:08.59#ibcon#wrote, iclass 25, count 2 2006.210.08:13:08.59#ibcon#about to read 3, iclass 25, count 2 2006.210.08:13:08.61#ibcon#read 3, iclass 25, count 2 2006.210.08:13:08.61#ibcon#about to read 4, iclass 25, count 2 2006.210.08:13:08.61#ibcon#read 4, iclass 25, count 2 2006.210.08:13:08.61#ibcon#about to read 5, iclass 25, count 2 2006.210.08:13:08.61#ibcon#read 5, iclass 25, count 2 2006.210.08:13:08.61#ibcon#about to read 6, iclass 25, count 2 2006.210.08:13:08.61#ibcon#read 6, iclass 25, count 2 2006.210.08:13:08.61#ibcon#end of sib2, iclass 25, count 2 2006.210.08:13:08.61#ibcon#*mode == 0, iclass 25, count 2 2006.210.08:13:08.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.08:13:08.61#ibcon#[25=AT04-07\r\n] 2006.210.08:13:08.61#ibcon#*before write, iclass 25, count 2 2006.210.08:13:08.61#ibcon#enter sib2, iclass 25, count 2 2006.210.08:13:08.61#ibcon#flushed, iclass 25, count 2 2006.210.08:13:08.61#ibcon#about to write, iclass 25, count 2 2006.210.08:13:08.61#ibcon#wrote, iclass 25, count 2 2006.210.08:13:08.61#ibcon#about to read 3, iclass 25, count 2 2006.210.08:13:08.64#ibcon#read 3, iclass 25, count 2 2006.210.08:13:08.64#ibcon#about to read 4, iclass 25, count 2 2006.210.08:13:08.64#ibcon#read 4, iclass 25, count 2 2006.210.08:13:08.64#ibcon#about to read 5, iclass 25, count 2 2006.210.08:13:08.64#ibcon#read 5, iclass 25, count 2 2006.210.08:13:08.64#ibcon#about to read 6, iclass 25, count 2 2006.210.08:13:08.64#ibcon#read 6, iclass 25, count 2 2006.210.08:13:08.64#ibcon#end of sib2, iclass 25, count 2 2006.210.08:13:08.64#ibcon#*after write, iclass 25, count 2 2006.210.08:13:08.64#ibcon#*before return 0, iclass 25, count 2 2006.210.08:13:08.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:08.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:08.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.08:13:08.64#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:08.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:08.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:08.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:08.76#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:13:08.76#ibcon#first serial, iclass 25, count 0 2006.210.08:13:08.76#ibcon#enter sib2, iclass 25, count 0 2006.210.08:13:08.76#ibcon#flushed, iclass 25, count 0 2006.210.08:13:08.76#ibcon#about to write, iclass 25, count 0 2006.210.08:13:08.76#ibcon#wrote, iclass 25, count 0 2006.210.08:13:08.76#ibcon#about to read 3, iclass 25, count 0 2006.210.08:13:08.78#ibcon#read 3, iclass 25, count 0 2006.210.08:13:08.78#ibcon#about to read 4, iclass 25, count 0 2006.210.08:13:08.78#ibcon#read 4, iclass 25, count 0 2006.210.08:13:08.78#ibcon#about to read 5, iclass 25, count 0 2006.210.08:13:08.78#ibcon#read 5, iclass 25, count 0 2006.210.08:13:08.78#ibcon#about to read 6, iclass 25, count 0 2006.210.08:13:08.78#ibcon#read 6, iclass 25, count 0 2006.210.08:13:08.78#ibcon#end of sib2, iclass 25, count 0 2006.210.08:13:08.78#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:13:08.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:13:08.78#ibcon#[25=USB\r\n] 2006.210.08:13:08.78#ibcon#*before write, iclass 25, count 0 2006.210.08:13:08.78#ibcon#enter sib2, iclass 25, count 0 2006.210.08:13:08.78#ibcon#flushed, iclass 25, count 0 2006.210.08:13:08.78#ibcon#about to write, iclass 25, count 0 2006.210.08:13:08.78#ibcon#wrote, iclass 25, count 0 2006.210.08:13:08.78#ibcon#about to read 3, iclass 25, count 0 2006.210.08:13:08.81#ibcon#read 3, iclass 25, count 0 2006.210.08:13:08.81#ibcon#about to read 4, iclass 25, count 0 2006.210.08:13:08.81#ibcon#read 4, iclass 25, count 0 2006.210.08:13:08.81#ibcon#about to read 5, iclass 25, count 0 2006.210.08:13:08.81#ibcon#read 5, iclass 25, count 0 2006.210.08:13:08.81#ibcon#about to read 6, iclass 25, count 0 2006.210.08:13:08.81#ibcon#read 6, iclass 25, count 0 2006.210.08:13:08.81#ibcon#end of sib2, iclass 25, count 0 2006.210.08:13:08.81#ibcon#*after write, iclass 25, count 0 2006.210.08:13:08.81#ibcon#*before return 0, iclass 25, count 0 2006.210.08:13:08.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:08.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:08.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:13:08.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:13:08.81$vc4f8/valo=5,652.99 2006.210.08:13:08.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.08:13:08.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.08:13:08.81#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:08.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:08.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:08.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:08.81#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:13:08.81#ibcon#first serial, iclass 27, count 0 2006.210.08:13:08.81#ibcon#enter sib2, iclass 27, count 0 2006.210.08:13:08.81#ibcon#flushed, iclass 27, count 0 2006.210.08:13:08.81#ibcon#about to write, iclass 27, count 0 2006.210.08:13:08.81#ibcon#wrote, iclass 27, count 0 2006.210.08:13:08.81#ibcon#about to read 3, iclass 27, count 0 2006.210.08:13:08.83#ibcon#read 3, iclass 27, count 0 2006.210.08:13:08.83#ibcon#about to read 4, iclass 27, count 0 2006.210.08:13:08.83#ibcon#read 4, iclass 27, count 0 2006.210.08:13:08.83#ibcon#about to read 5, iclass 27, count 0 2006.210.08:13:08.83#ibcon#read 5, iclass 27, count 0 2006.210.08:13:08.83#ibcon#about to read 6, iclass 27, count 0 2006.210.08:13:08.83#ibcon#read 6, iclass 27, count 0 2006.210.08:13:08.83#ibcon#end of sib2, iclass 27, count 0 2006.210.08:13:08.83#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:13:08.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:13:08.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:13:08.83#ibcon#*before write, iclass 27, count 0 2006.210.08:13:08.83#ibcon#enter sib2, iclass 27, count 0 2006.210.08:13:08.83#ibcon#flushed, iclass 27, count 0 2006.210.08:13:08.83#ibcon#about to write, iclass 27, count 0 2006.210.08:13:08.83#ibcon#wrote, iclass 27, count 0 2006.210.08:13:08.83#ibcon#about to read 3, iclass 27, count 0 2006.210.08:13:08.87#ibcon#read 3, iclass 27, count 0 2006.210.08:13:08.87#ibcon#about to read 4, iclass 27, count 0 2006.210.08:13:08.87#ibcon#read 4, iclass 27, count 0 2006.210.08:13:08.87#ibcon#about to read 5, iclass 27, count 0 2006.210.08:13:08.87#ibcon#read 5, iclass 27, count 0 2006.210.08:13:08.87#ibcon#about to read 6, iclass 27, count 0 2006.210.08:13:08.87#ibcon#read 6, iclass 27, count 0 2006.210.08:13:08.87#ibcon#end of sib2, iclass 27, count 0 2006.210.08:13:08.87#ibcon#*after write, iclass 27, count 0 2006.210.08:13:08.87#ibcon#*before return 0, iclass 27, count 0 2006.210.08:13:08.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:08.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:08.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:13:08.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:13:08.87$vc4f8/va=5,7 2006.210.08:13:08.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.08:13:08.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.08:13:08.87#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:08.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:08.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:08.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:08.93#ibcon#enter wrdev, iclass 29, count 2 2006.210.08:13:08.93#ibcon#first serial, iclass 29, count 2 2006.210.08:13:08.93#ibcon#enter sib2, iclass 29, count 2 2006.210.08:13:08.93#ibcon#flushed, iclass 29, count 2 2006.210.08:13:08.93#ibcon#about to write, iclass 29, count 2 2006.210.08:13:08.93#ibcon#wrote, iclass 29, count 2 2006.210.08:13:08.93#ibcon#about to read 3, iclass 29, count 2 2006.210.08:13:08.95#ibcon#read 3, iclass 29, count 2 2006.210.08:13:08.95#ibcon#about to read 4, iclass 29, count 2 2006.210.08:13:08.95#ibcon#read 4, iclass 29, count 2 2006.210.08:13:08.95#ibcon#about to read 5, iclass 29, count 2 2006.210.08:13:08.95#ibcon#read 5, iclass 29, count 2 2006.210.08:13:08.95#ibcon#about to read 6, iclass 29, count 2 2006.210.08:13:08.95#ibcon#read 6, iclass 29, count 2 2006.210.08:13:08.95#ibcon#end of sib2, iclass 29, count 2 2006.210.08:13:08.95#ibcon#*mode == 0, iclass 29, count 2 2006.210.08:13:08.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.08:13:08.95#ibcon#[25=AT05-07\r\n] 2006.210.08:13:08.95#ibcon#*before write, iclass 29, count 2 2006.210.08:13:08.95#ibcon#enter sib2, iclass 29, count 2 2006.210.08:13:08.95#ibcon#flushed, iclass 29, count 2 2006.210.08:13:08.95#ibcon#about to write, iclass 29, count 2 2006.210.08:13:08.95#ibcon#wrote, iclass 29, count 2 2006.210.08:13:08.95#ibcon#about to read 3, iclass 29, count 2 2006.210.08:13:08.98#ibcon#read 3, iclass 29, count 2 2006.210.08:13:08.98#ibcon#about to read 4, iclass 29, count 2 2006.210.08:13:08.98#ibcon#read 4, iclass 29, count 2 2006.210.08:13:08.98#ibcon#about to read 5, iclass 29, count 2 2006.210.08:13:08.98#ibcon#read 5, iclass 29, count 2 2006.210.08:13:08.98#ibcon#about to read 6, iclass 29, count 2 2006.210.08:13:08.98#ibcon#read 6, iclass 29, count 2 2006.210.08:13:08.98#ibcon#end of sib2, iclass 29, count 2 2006.210.08:13:08.98#ibcon#*after write, iclass 29, count 2 2006.210.08:13:08.98#ibcon#*before return 0, iclass 29, count 2 2006.210.08:13:08.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:08.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:08.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.08:13:08.98#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:08.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:09.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:09.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:09.10#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:13:09.10#ibcon#first serial, iclass 29, count 0 2006.210.08:13:09.10#ibcon#enter sib2, iclass 29, count 0 2006.210.08:13:09.10#ibcon#flushed, iclass 29, count 0 2006.210.08:13:09.10#ibcon#about to write, iclass 29, count 0 2006.210.08:13:09.10#ibcon#wrote, iclass 29, count 0 2006.210.08:13:09.10#ibcon#about to read 3, iclass 29, count 0 2006.210.08:13:09.12#ibcon#read 3, iclass 29, count 0 2006.210.08:13:09.12#ibcon#about to read 4, iclass 29, count 0 2006.210.08:13:09.12#ibcon#read 4, iclass 29, count 0 2006.210.08:13:09.12#ibcon#about to read 5, iclass 29, count 0 2006.210.08:13:09.12#ibcon#read 5, iclass 29, count 0 2006.210.08:13:09.12#ibcon#about to read 6, iclass 29, count 0 2006.210.08:13:09.12#ibcon#read 6, iclass 29, count 0 2006.210.08:13:09.12#ibcon#end of sib2, iclass 29, count 0 2006.210.08:13:09.12#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:13:09.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:13:09.12#ibcon#[25=USB\r\n] 2006.210.08:13:09.12#ibcon#*before write, iclass 29, count 0 2006.210.08:13:09.12#ibcon#enter sib2, iclass 29, count 0 2006.210.08:13:09.12#ibcon#flushed, iclass 29, count 0 2006.210.08:13:09.12#ibcon#about to write, iclass 29, count 0 2006.210.08:13:09.12#ibcon#wrote, iclass 29, count 0 2006.210.08:13:09.12#ibcon#about to read 3, iclass 29, count 0 2006.210.08:13:09.15#ibcon#read 3, iclass 29, count 0 2006.210.08:13:09.15#ibcon#about to read 4, iclass 29, count 0 2006.210.08:13:09.15#ibcon#read 4, iclass 29, count 0 2006.210.08:13:09.15#ibcon#about to read 5, iclass 29, count 0 2006.210.08:13:09.15#ibcon#read 5, iclass 29, count 0 2006.210.08:13:09.15#ibcon#about to read 6, iclass 29, count 0 2006.210.08:13:09.15#ibcon#read 6, iclass 29, count 0 2006.210.08:13:09.15#ibcon#end of sib2, iclass 29, count 0 2006.210.08:13:09.15#ibcon#*after write, iclass 29, count 0 2006.210.08:13:09.15#ibcon#*before return 0, iclass 29, count 0 2006.210.08:13:09.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:09.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:09.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:13:09.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:13:09.15$vc4f8/valo=6,772.99 2006.210.08:13:09.15#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.08:13:09.15#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.08:13:09.15#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:09.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:13:09.15#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:13:09.15#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:13:09.15#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:13:09.15#ibcon#first serial, iclass 31, count 0 2006.210.08:13:09.15#ibcon#enter sib2, iclass 31, count 0 2006.210.08:13:09.15#ibcon#flushed, iclass 31, count 0 2006.210.08:13:09.15#ibcon#about to write, iclass 31, count 0 2006.210.08:13:09.15#ibcon#wrote, iclass 31, count 0 2006.210.08:13:09.15#ibcon#about to read 3, iclass 31, count 0 2006.210.08:13:09.17#ibcon#read 3, iclass 31, count 0 2006.210.08:13:09.17#ibcon#about to read 4, iclass 31, count 0 2006.210.08:13:09.17#ibcon#read 4, iclass 31, count 0 2006.210.08:13:09.17#ibcon#about to read 5, iclass 31, count 0 2006.210.08:13:09.17#ibcon#read 5, iclass 31, count 0 2006.210.08:13:09.17#ibcon#about to read 6, iclass 31, count 0 2006.210.08:13:09.17#ibcon#read 6, iclass 31, count 0 2006.210.08:13:09.17#ibcon#end of sib2, iclass 31, count 0 2006.210.08:13:09.17#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:13:09.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:13:09.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:13:09.17#ibcon#*before write, iclass 31, count 0 2006.210.08:13:09.17#ibcon#enter sib2, iclass 31, count 0 2006.210.08:13:09.17#ibcon#flushed, iclass 31, count 0 2006.210.08:13:09.17#ibcon#about to write, iclass 31, count 0 2006.210.08:13:09.17#ibcon#wrote, iclass 31, count 0 2006.210.08:13:09.17#ibcon#about to read 3, iclass 31, count 0 2006.210.08:13:09.21#ibcon#read 3, iclass 31, count 0 2006.210.08:13:09.21#ibcon#about to read 4, iclass 31, count 0 2006.210.08:13:09.21#ibcon#read 4, iclass 31, count 0 2006.210.08:13:09.21#ibcon#about to read 5, iclass 31, count 0 2006.210.08:13:09.21#ibcon#read 5, iclass 31, count 0 2006.210.08:13:09.21#ibcon#about to read 6, iclass 31, count 0 2006.210.08:13:09.21#ibcon#read 6, iclass 31, count 0 2006.210.08:13:09.21#ibcon#end of sib2, iclass 31, count 0 2006.210.08:13:09.21#ibcon#*after write, iclass 31, count 0 2006.210.08:13:09.21#ibcon#*before return 0, iclass 31, count 0 2006.210.08:13:09.21#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:13:09.21#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:13:09.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:13:09.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:13:09.21$vc4f8/va=6,6 2006.210.08:13:09.21#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.08:13:09.21#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.08:13:09.21#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:09.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:13:09.27#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:13:09.27#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:13:09.27#ibcon#enter wrdev, iclass 33, count 2 2006.210.08:13:09.27#ibcon#first serial, iclass 33, count 2 2006.210.08:13:09.27#ibcon#enter sib2, iclass 33, count 2 2006.210.08:13:09.27#ibcon#flushed, iclass 33, count 2 2006.210.08:13:09.27#ibcon#about to write, iclass 33, count 2 2006.210.08:13:09.27#ibcon#wrote, iclass 33, count 2 2006.210.08:13:09.27#ibcon#about to read 3, iclass 33, count 2 2006.210.08:13:09.29#ibcon#read 3, iclass 33, count 2 2006.210.08:13:09.29#ibcon#about to read 4, iclass 33, count 2 2006.210.08:13:09.29#ibcon#read 4, iclass 33, count 2 2006.210.08:13:09.29#ibcon#about to read 5, iclass 33, count 2 2006.210.08:13:09.29#ibcon#read 5, iclass 33, count 2 2006.210.08:13:09.29#ibcon#about to read 6, iclass 33, count 2 2006.210.08:13:09.29#ibcon#read 6, iclass 33, count 2 2006.210.08:13:09.29#ibcon#end of sib2, iclass 33, count 2 2006.210.08:13:09.29#ibcon#*mode == 0, iclass 33, count 2 2006.210.08:13:09.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.08:13:09.29#ibcon#[25=AT06-06\r\n] 2006.210.08:13:09.29#ibcon#*before write, iclass 33, count 2 2006.210.08:13:09.29#ibcon#enter sib2, iclass 33, count 2 2006.210.08:13:09.29#ibcon#flushed, iclass 33, count 2 2006.210.08:13:09.29#ibcon#about to write, iclass 33, count 2 2006.210.08:13:09.29#ibcon#wrote, iclass 33, count 2 2006.210.08:13:09.29#ibcon#about to read 3, iclass 33, count 2 2006.210.08:13:09.32#ibcon#read 3, iclass 33, count 2 2006.210.08:13:09.32#ibcon#about to read 4, iclass 33, count 2 2006.210.08:13:09.32#ibcon#read 4, iclass 33, count 2 2006.210.08:13:09.32#ibcon#about to read 5, iclass 33, count 2 2006.210.08:13:09.32#ibcon#read 5, iclass 33, count 2 2006.210.08:13:09.32#ibcon#about to read 6, iclass 33, count 2 2006.210.08:13:09.32#ibcon#read 6, iclass 33, count 2 2006.210.08:13:09.32#ibcon#end of sib2, iclass 33, count 2 2006.210.08:13:09.32#ibcon#*after write, iclass 33, count 2 2006.210.08:13:09.32#ibcon#*before return 0, iclass 33, count 2 2006.210.08:13:09.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:13:09.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:13:09.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.08:13:09.32#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:09.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:13:09.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:13:09.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:13:09.44#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:13:09.44#ibcon#first serial, iclass 33, count 0 2006.210.08:13:09.44#ibcon#enter sib2, iclass 33, count 0 2006.210.08:13:09.44#ibcon#flushed, iclass 33, count 0 2006.210.08:13:09.44#ibcon#about to write, iclass 33, count 0 2006.210.08:13:09.44#ibcon#wrote, iclass 33, count 0 2006.210.08:13:09.44#ibcon#about to read 3, iclass 33, count 0 2006.210.08:13:09.46#ibcon#read 3, iclass 33, count 0 2006.210.08:13:09.46#ibcon#about to read 4, iclass 33, count 0 2006.210.08:13:09.46#ibcon#read 4, iclass 33, count 0 2006.210.08:13:09.46#ibcon#about to read 5, iclass 33, count 0 2006.210.08:13:09.46#ibcon#read 5, iclass 33, count 0 2006.210.08:13:09.46#ibcon#about to read 6, iclass 33, count 0 2006.210.08:13:09.46#ibcon#read 6, iclass 33, count 0 2006.210.08:13:09.46#ibcon#end of sib2, iclass 33, count 0 2006.210.08:13:09.46#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:13:09.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:13:09.46#ibcon#[25=USB\r\n] 2006.210.08:13:09.46#ibcon#*before write, iclass 33, count 0 2006.210.08:13:09.46#ibcon#enter sib2, iclass 33, count 0 2006.210.08:13:09.46#ibcon#flushed, iclass 33, count 0 2006.210.08:13:09.46#ibcon#about to write, iclass 33, count 0 2006.210.08:13:09.46#ibcon#wrote, iclass 33, count 0 2006.210.08:13:09.46#ibcon#about to read 3, iclass 33, count 0 2006.210.08:13:09.49#ibcon#read 3, iclass 33, count 0 2006.210.08:13:09.49#ibcon#about to read 4, iclass 33, count 0 2006.210.08:13:09.49#ibcon#read 4, iclass 33, count 0 2006.210.08:13:09.49#ibcon#about to read 5, iclass 33, count 0 2006.210.08:13:09.49#ibcon#read 5, iclass 33, count 0 2006.210.08:13:09.49#ibcon#about to read 6, iclass 33, count 0 2006.210.08:13:09.49#ibcon#read 6, iclass 33, count 0 2006.210.08:13:09.49#ibcon#end of sib2, iclass 33, count 0 2006.210.08:13:09.49#ibcon#*after write, iclass 33, count 0 2006.210.08:13:09.49#ibcon#*before return 0, iclass 33, count 0 2006.210.08:13:09.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:13:09.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:13:09.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:13:09.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:13:09.49$vc4f8/valo=7,832.99 2006.210.08:13:09.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:13:09.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:13:09.49#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:09.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:09.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:09.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:09.49#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:13:09.49#ibcon#first serial, iclass 35, count 0 2006.210.08:13:09.49#ibcon#enter sib2, iclass 35, count 0 2006.210.08:13:09.49#ibcon#flushed, iclass 35, count 0 2006.210.08:13:09.49#ibcon#about to write, iclass 35, count 0 2006.210.08:13:09.49#ibcon#wrote, iclass 35, count 0 2006.210.08:13:09.49#ibcon#about to read 3, iclass 35, count 0 2006.210.08:13:09.51#ibcon#read 3, iclass 35, count 0 2006.210.08:13:09.51#ibcon#about to read 4, iclass 35, count 0 2006.210.08:13:09.51#ibcon#read 4, iclass 35, count 0 2006.210.08:13:09.51#ibcon#about to read 5, iclass 35, count 0 2006.210.08:13:09.51#ibcon#read 5, iclass 35, count 0 2006.210.08:13:09.51#ibcon#about to read 6, iclass 35, count 0 2006.210.08:13:09.51#ibcon#read 6, iclass 35, count 0 2006.210.08:13:09.51#ibcon#end of sib2, iclass 35, count 0 2006.210.08:13:09.51#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:13:09.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:13:09.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:13:09.51#ibcon#*before write, iclass 35, count 0 2006.210.08:13:09.51#ibcon#enter sib2, iclass 35, count 0 2006.210.08:13:09.51#ibcon#flushed, iclass 35, count 0 2006.210.08:13:09.51#ibcon#about to write, iclass 35, count 0 2006.210.08:13:09.51#ibcon#wrote, iclass 35, count 0 2006.210.08:13:09.51#ibcon#about to read 3, iclass 35, count 0 2006.210.08:13:09.55#ibcon#read 3, iclass 35, count 0 2006.210.08:13:09.55#ibcon#about to read 4, iclass 35, count 0 2006.210.08:13:09.55#ibcon#read 4, iclass 35, count 0 2006.210.08:13:09.55#ibcon#about to read 5, iclass 35, count 0 2006.210.08:13:09.55#ibcon#read 5, iclass 35, count 0 2006.210.08:13:09.55#ibcon#about to read 6, iclass 35, count 0 2006.210.08:13:09.55#ibcon#read 6, iclass 35, count 0 2006.210.08:13:09.55#ibcon#end of sib2, iclass 35, count 0 2006.210.08:13:09.55#ibcon#*after write, iclass 35, count 0 2006.210.08:13:09.55#ibcon#*before return 0, iclass 35, count 0 2006.210.08:13:09.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:09.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:09.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:13:09.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:13:09.55$vc4f8/va=7,6 2006.210.08:13:09.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.08:13:09.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.08:13:09.55#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:09.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:13:09.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:13:09.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:13:09.61#ibcon#enter wrdev, iclass 37, count 2 2006.210.08:13:09.61#ibcon#first serial, iclass 37, count 2 2006.210.08:13:09.61#ibcon#enter sib2, iclass 37, count 2 2006.210.08:13:09.61#ibcon#flushed, iclass 37, count 2 2006.210.08:13:09.61#ibcon#about to write, iclass 37, count 2 2006.210.08:13:09.61#ibcon#wrote, iclass 37, count 2 2006.210.08:13:09.61#ibcon#about to read 3, iclass 37, count 2 2006.210.08:13:09.63#ibcon#read 3, iclass 37, count 2 2006.210.08:13:09.63#ibcon#about to read 4, iclass 37, count 2 2006.210.08:13:09.63#ibcon#read 4, iclass 37, count 2 2006.210.08:13:09.63#ibcon#about to read 5, iclass 37, count 2 2006.210.08:13:09.63#ibcon#read 5, iclass 37, count 2 2006.210.08:13:09.63#ibcon#about to read 6, iclass 37, count 2 2006.210.08:13:09.63#ibcon#read 6, iclass 37, count 2 2006.210.08:13:09.63#ibcon#end of sib2, iclass 37, count 2 2006.210.08:13:09.63#ibcon#*mode == 0, iclass 37, count 2 2006.210.08:13:09.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.08:13:09.63#ibcon#[25=AT07-06\r\n] 2006.210.08:13:09.63#ibcon#*before write, iclass 37, count 2 2006.210.08:13:09.63#ibcon#enter sib2, iclass 37, count 2 2006.210.08:13:09.63#ibcon#flushed, iclass 37, count 2 2006.210.08:13:09.63#ibcon#about to write, iclass 37, count 2 2006.210.08:13:09.63#ibcon#wrote, iclass 37, count 2 2006.210.08:13:09.63#ibcon#about to read 3, iclass 37, count 2 2006.210.08:13:09.66#ibcon#read 3, iclass 37, count 2 2006.210.08:13:09.66#ibcon#about to read 4, iclass 37, count 2 2006.210.08:13:09.66#ibcon#read 4, iclass 37, count 2 2006.210.08:13:09.66#ibcon#about to read 5, iclass 37, count 2 2006.210.08:13:09.66#ibcon#read 5, iclass 37, count 2 2006.210.08:13:09.66#ibcon#about to read 6, iclass 37, count 2 2006.210.08:13:09.66#ibcon#read 6, iclass 37, count 2 2006.210.08:13:09.66#ibcon#end of sib2, iclass 37, count 2 2006.210.08:13:09.66#ibcon#*after write, iclass 37, count 2 2006.210.08:13:09.66#ibcon#*before return 0, iclass 37, count 2 2006.210.08:13:09.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:13:09.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:13:09.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.08:13:09.66#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:09.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:13:09.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:13:09.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:13:09.78#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:13:09.78#ibcon#first serial, iclass 37, count 0 2006.210.08:13:09.78#ibcon#enter sib2, iclass 37, count 0 2006.210.08:13:09.78#ibcon#flushed, iclass 37, count 0 2006.210.08:13:09.78#ibcon#about to write, iclass 37, count 0 2006.210.08:13:09.78#ibcon#wrote, iclass 37, count 0 2006.210.08:13:09.78#ibcon#about to read 3, iclass 37, count 0 2006.210.08:13:09.80#ibcon#read 3, iclass 37, count 0 2006.210.08:13:09.80#ibcon#about to read 4, iclass 37, count 0 2006.210.08:13:09.80#ibcon#read 4, iclass 37, count 0 2006.210.08:13:09.80#ibcon#about to read 5, iclass 37, count 0 2006.210.08:13:09.80#ibcon#read 5, iclass 37, count 0 2006.210.08:13:09.80#ibcon#about to read 6, iclass 37, count 0 2006.210.08:13:09.80#ibcon#read 6, iclass 37, count 0 2006.210.08:13:09.80#ibcon#end of sib2, iclass 37, count 0 2006.210.08:13:09.80#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:13:09.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:13:09.80#ibcon#[25=USB\r\n] 2006.210.08:13:09.80#ibcon#*before write, iclass 37, count 0 2006.210.08:13:09.80#ibcon#enter sib2, iclass 37, count 0 2006.210.08:13:09.80#ibcon#flushed, iclass 37, count 0 2006.210.08:13:09.80#ibcon#about to write, iclass 37, count 0 2006.210.08:13:09.80#ibcon#wrote, iclass 37, count 0 2006.210.08:13:09.80#ibcon#about to read 3, iclass 37, count 0 2006.210.08:13:09.83#ibcon#read 3, iclass 37, count 0 2006.210.08:13:09.83#ibcon#about to read 4, iclass 37, count 0 2006.210.08:13:09.83#ibcon#read 4, iclass 37, count 0 2006.210.08:13:09.83#ibcon#about to read 5, iclass 37, count 0 2006.210.08:13:09.83#ibcon#read 5, iclass 37, count 0 2006.210.08:13:09.83#ibcon#about to read 6, iclass 37, count 0 2006.210.08:13:09.83#ibcon#read 6, iclass 37, count 0 2006.210.08:13:09.83#ibcon#end of sib2, iclass 37, count 0 2006.210.08:13:09.83#ibcon#*after write, iclass 37, count 0 2006.210.08:13:09.83#ibcon#*before return 0, iclass 37, count 0 2006.210.08:13:09.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:13:09.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:13:09.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:13:09.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:13:09.83$vc4f8/valo=8,852.99 2006.210.08:13:09.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.08:13:09.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.08:13:09.83#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:09.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:13:09.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:13:09.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:13:09.83#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:13:09.83#ibcon#first serial, iclass 39, count 0 2006.210.08:13:09.83#ibcon#enter sib2, iclass 39, count 0 2006.210.08:13:09.83#ibcon#flushed, iclass 39, count 0 2006.210.08:13:09.83#ibcon#about to write, iclass 39, count 0 2006.210.08:13:09.83#ibcon#wrote, iclass 39, count 0 2006.210.08:13:09.83#ibcon#about to read 3, iclass 39, count 0 2006.210.08:13:09.85#ibcon#read 3, iclass 39, count 0 2006.210.08:13:09.85#ibcon#about to read 4, iclass 39, count 0 2006.210.08:13:09.85#ibcon#read 4, iclass 39, count 0 2006.210.08:13:09.85#ibcon#about to read 5, iclass 39, count 0 2006.210.08:13:09.85#ibcon#read 5, iclass 39, count 0 2006.210.08:13:09.85#ibcon#about to read 6, iclass 39, count 0 2006.210.08:13:09.85#ibcon#read 6, iclass 39, count 0 2006.210.08:13:09.85#ibcon#end of sib2, iclass 39, count 0 2006.210.08:13:09.85#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:13:09.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:13:09.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:13:09.85#ibcon#*before write, iclass 39, count 0 2006.210.08:13:09.85#ibcon#enter sib2, iclass 39, count 0 2006.210.08:13:09.85#ibcon#flushed, iclass 39, count 0 2006.210.08:13:09.85#ibcon#about to write, iclass 39, count 0 2006.210.08:13:09.85#ibcon#wrote, iclass 39, count 0 2006.210.08:13:09.85#ibcon#about to read 3, iclass 39, count 0 2006.210.08:13:09.89#ibcon#read 3, iclass 39, count 0 2006.210.08:13:09.89#ibcon#about to read 4, iclass 39, count 0 2006.210.08:13:09.89#ibcon#read 4, iclass 39, count 0 2006.210.08:13:09.89#ibcon#about to read 5, iclass 39, count 0 2006.210.08:13:09.89#ibcon#read 5, iclass 39, count 0 2006.210.08:13:09.89#ibcon#about to read 6, iclass 39, count 0 2006.210.08:13:09.89#ibcon#read 6, iclass 39, count 0 2006.210.08:13:09.89#ibcon#end of sib2, iclass 39, count 0 2006.210.08:13:09.89#ibcon#*after write, iclass 39, count 0 2006.210.08:13:09.89#ibcon#*before return 0, iclass 39, count 0 2006.210.08:13:09.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:13:09.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:13:09.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:13:09.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:13:09.89$vc4f8/va=8,7 2006.210.08:13:09.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.08:13:09.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.08:13:09.89#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:09.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:13:09.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:13:09.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:13:09.95#ibcon#enter wrdev, iclass 3, count 2 2006.210.08:13:09.95#ibcon#first serial, iclass 3, count 2 2006.210.08:13:09.95#ibcon#enter sib2, iclass 3, count 2 2006.210.08:13:09.95#ibcon#flushed, iclass 3, count 2 2006.210.08:13:09.95#ibcon#about to write, iclass 3, count 2 2006.210.08:13:09.95#ibcon#wrote, iclass 3, count 2 2006.210.08:13:09.95#ibcon#about to read 3, iclass 3, count 2 2006.210.08:13:09.97#ibcon#read 3, iclass 3, count 2 2006.210.08:13:09.97#ibcon#about to read 4, iclass 3, count 2 2006.210.08:13:09.97#ibcon#read 4, iclass 3, count 2 2006.210.08:13:09.97#ibcon#about to read 5, iclass 3, count 2 2006.210.08:13:09.97#ibcon#read 5, iclass 3, count 2 2006.210.08:13:09.97#ibcon#about to read 6, iclass 3, count 2 2006.210.08:13:09.97#ibcon#read 6, iclass 3, count 2 2006.210.08:13:09.97#ibcon#end of sib2, iclass 3, count 2 2006.210.08:13:09.97#ibcon#*mode == 0, iclass 3, count 2 2006.210.08:13:09.97#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.08:13:09.97#ibcon#[25=AT08-07\r\n] 2006.210.08:13:09.97#ibcon#*before write, iclass 3, count 2 2006.210.08:13:09.97#ibcon#enter sib2, iclass 3, count 2 2006.210.08:13:09.97#ibcon#flushed, iclass 3, count 2 2006.210.08:13:09.97#ibcon#about to write, iclass 3, count 2 2006.210.08:13:09.97#ibcon#wrote, iclass 3, count 2 2006.210.08:13:09.97#ibcon#about to read 3, iclass 3, count 2 2006.210.08:13:10.00#ibcon#read 3, iclass 3, count 2 2006.210.08:13:10.00#ibcon#about to read 4, iclass 3, count 2 2006.210.08:13:10.00#ibcon#read 4, iclass 3, count 2 2006.210.08:13:10.00#ibcon#about to read 5, iclass 3, count 2 2006.210.08:13:10.00#ibcon#read 5, iclass 3, count 2 2006.210.08:13:10.00#ibcon#about to read 6, iclass 3, count 2 2006.210.08:13:10.00#ibcon#read 6, iclass 3, count 2 2006.210.08:13:10.00#ibcon#end of sib2, iclass 3, count 2 2006.210.08:13:10.00#ibcon#*after write, iclass 3, count 2 2006.210.08:13:10.00#ibcon#*before return 0, iclass 3, count 2 2006.210.08:13:10.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:13:10.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:13:10.00#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.08:13:10.00#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:10.00#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:13:10.12#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:13:10.12#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:13:10.12#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:13:10.12#ibcon#first serial, iclass 3, count 0 2006.210.08:13:10.12#ibcon#enter sib2, iclass 3, count 0 2006.210.08:13:10.12#ibcon#flushed, iclass 3, count 0 2006.210.08:13:10.12#ibcon#about to write, iclass 3, count 0 2006.210.08:13:10.12#ibcon#wrote, iclass 3, count 0 2006.210.08:13:10.12#ibcon#about to read 3, iclass 3, count 0 2006.210.08:13:10.14#ibcon#read 3, iclass 3, count 0 2006.210.08:13:10.14#ibcon#about to read 4, iclass 3, count 0 2006.210.08:13:10.14#ibcon#read 4, iclass 3, count 0 2006.210.08:13:10.14#ibcon#about to read 5, iclass 3, count 0 2006.210.08:13:10.14#ibcon#read 5, iclass 3, count 0 2006.210.08:13:10.14#ibcon#about to read 6, iclass 3, count 0 2006.210.08:13:10.14#ibcon#read 6, iclass 3, count 0 2006.210.08:13:10.14#ibcon#end of sib2, iclass 3, count 0 2006.210.08:13:10.14#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:13:10.14#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:13:10.14#ibcon#[25=USB\r\n] 2006.210.08:13:10.14#ibcon#*before write, iclass 3, count 0 2006.210.08:13:10.14#ibcon#enter sib2, iclass 3, count 0 2006.210.08:13:10.14#ibcon#flushed, iclass 3, count 0 2006.210.08:13:10.14#ibcon#about to write, iclass 3, count 0 2006.210.08:13:10.14#ibcon#wrote, iclass 3, count 0 2006.210.08:13:10.14#ibcon#about to read 3, iclass 3, count 0 2006.210.08:13:10.17#ibcon#read 3, iclass 3, count 0 2006.210.08:13:10.17#ibcon#about to read 4, iclass 3, count 0 2006.210.08:13:10.17#ibcon#read 4, iclass 3, count 0 2006.210.08:13:10.17#ibcon#about to read 5, iclass 3, count 0 2006.210.08:13:10.17#ibcon#read 5, iclass 3, count 0 2006.210.08:13:10.17#ibcon#about to read 6, iclass 3, count 0 2006.210.08:13:10.17#ibcon#read 6, iclass 3, count 0 2006.210.08:13:10.17#ibcon#end of sib2, iclass 3, count 0 2006.210.08:13:10.17#ibcon#*after write, iclass 3, count 0 2006.210.08:13:10.17#ibcon#*before return 0, iclass 3, count 0 2006.210.08:13:10.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:13:10.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:13:10.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:13:10.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:13:10.17$vc4f8/vblo=1,632.99 2006.210.08:13:10.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.08:13:10.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.08:13:10.17#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:10.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:13:10.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:13:10.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:13:10.17#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:13:10.17#ibcon#first serial, iclass 5, count 0 2006.210.08:13:10.17#ibcon#enter sib2, iclass 5, count 0 2006.210.08:13:10.17#ibcon#flushed, iclass 5, count 0 2006.210.08:13:10.17#ibcon#about to write, iclass 5, count 0 2006.210.08:13:10.17#ibcon#wrote, iclass 5, count 0 2006.210.08:13:10.17#ibcon#about to read 3, iclass 5, count 0 2006.210.08:13:10.19#ibcon#read 3, iclass 5, count 0 2006.210.08:13:10.19#ibcon#about to read 4, iclass 5, count 0 2006.210.08:13:10.19#ibcon#read 4, iclass 5, count 0 2006.210.08:13:10.19#ibcon#about to read 5, iclass 5, count 0 2006.210.08:13:10.19#ibcon#read 5, iclass 5, count 0 2006.210.08:13:10.19#ibcon#about to read 6, iclass 5, count 0 2006.210.08:13:10.19#ibcon#read 6, iclass 5, count 0 2006.210.08:13:10.19#ibcon#end of sib2, iclass 5, count 0 2006.210.08:13:10.19#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:13:10.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:13:10.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:13:10.19#ibcon#*before write, iclass 5, count 0 2006.210.08:13:10.19#ibcon#enter sib2, iclass 5, count 0 2006.210.08:13:10.19#ibcon#flushed, iclass 5, count 0 2006.210.08:13:10.19#ibcon#about to write, iclass 5, count 0 2006.210.08:13:10.19#ibcon#wrote, iclass 5, count 0 2006.210.08:13:10.19#ibcon#about to read 3, iclass 5, count 0 2006.210.08:13:10.23#ibcon#read 3, iclass 5, count 0 2006.210.08:13:10.23#ibcon#about to read 4, iclass 5, count 0 2006.210.08:13:10.23#ibcon#read 4, iclass 5, count 0 2006.210.08:13:10.23#ibcon#about to read 5, iclass 5, count 0 2006.210.08:13:10.23#ibcon#read 5, iclass 5, count 0 2006.210.08:13:10.23#ibcon#about to read 6, iclass 5, count 0 2006.210.08:13:10.23#ibcon#read 6, iclass 5, count 0 2006.210.08:13:10.23#ibcon#end of sib2, iclass 5, count 0 2006.210.08:13:10.23#ibcon#*after write, iclass 5, count 0 2006.210.08:13:10.23#ibcon#*before return 0, iclass 5, count 0 2006.210.08:13:10.23#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:13:10.23#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:13:10.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:13:10.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:13:10.23$vc4f8/vb=1,4 2006.210.08:13:10.23#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.08:13:10.23#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.08:13:10.23#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:10.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:13:10.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:13:10.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:13:10.23#ibcon#enter wrdev, iclass 7, count 2 2006.210.08:13:10.23#ibcon#first serial, iclass 7, count 2 2006.210.08:13:10.23#ibcon#enter sib2, iclass 7, count 2 2006.210.08:13:10.23#ibcon#flushed, iclass 7, count 2 2006.210.08:13:10.23#ibcon#about to write, iclass 7, count 2 2006.210.08:13:10.23#ibcon#wrote, iclass 7, count 2 2006.210.08:13:10.23#ibcon#about to read 3, iclass 7, count 2 2006.210.08:13:10.25#ibcon#read 3, iclass 7, count 2 2006.210.08:13:10.25#ibcon#about to read 4, iclass 7, count 2 2006.210.08:13:10.25#ibcon#read 4, iclass 7, count 2 2006.210.08:13:10.25#ibcon#about to read 5, iclass 7, count 2 2006.210.08:13:10.25#ibcon#read 5, iclass 7, count 2 2006.210.08:13:10.25#ibcon#about to read 6, iclass 7, count 2 2006.210.08:13:10.25#ibcon#read 6, iclass 7, count 2 2006.210.08:13:10.25#ibcon#end of sib2, iclass 7, count 2 2006.210.08:13:10.25#ibcon#*mode == 0, iclass 7, count 2 2006.210.08:13:10.25#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.08:13:10.25#ibcon#[27=AT01-04\r\n] 2006.210.08:13:10.25#ibcon#*before write, iclass 7, count 2 2006.210.08:13:10.25#ibcon#enter sib2, iclass 7, count 2 2006.210.08:13:10.25#ibcon#flushed, iclass 7, count 2 2006.210.08:13:10.25#ibcon#about to write, iclass 7, count 2 2006.210.08:13:10.25#ibcon#wrote, iclass 7, count 2 2006.210.08:13:10.25#ibcon#about to read 3, iclass 7, count 2 2006.210.08:13:10.28#ibcon#read 3, iclass 7, count 2 2006.210.08:13:10.28#ibcon#about to read 4, iclass 7, count 2 2006.210.08:13:10.28#ibcon#read 4, iclass 7, count 2 2006.210.08:13:10.28#ibcon#about to read 5, iclass 7, count 2 2006.210.08:13:10.28#ibcon#read 5, iclass 7, count 2 2006.210.08:13:10.28#ibcon#about to read 6, iclass 7, count 2 2006.210.08:13:10.28#ibcon#read 6, iclass 7, count 2 2006.210.08:13:10.28#ibcon#end of sib2, iclass 7, count 2 2006.210.08:13:10.28#ibcon#*after write, iclass 7, count 2 2006.210.08:13:10.28#ibcon#*before return 0, iclass 7, count 2 2006.210.08:13:10.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:13:10.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:13:10.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.08:13:10.28#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:10.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:13:10.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:13:10.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:13:10.40#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:13:10.40#ibcon#first serial, iclass 7, count 0 2006.210.08:13:10.40#ibcon#enter sib2, iclass 7, count 0 2006.210.08:13:10.40#ibcon#flushed, iclass 7, count 0 2006.210.08:13:10.40#ibcon#about to write, iclass 7, count 0 2006.210.08:13:10.40#ibcon#wrote, iclass 7, count 0 2006.210.08:13:10.40#ibcon#about to read 3, iclass 7, count 0 2006.210.08:13:10.42#ibcon#read 3, iclass 7, count 0 2006.210.08:13:10.42#ibcon#about to read 4, iclass 7, count 0 2006.210.08:13:10.42#ibcon#read 4, iclass 7, count 0 2006.210.08:13:10.42#ibcon#about to read 5, iclass 7, count 0 2006.210.08:13:10.42#ibcon#read 5, iclass 7, count 0 2006.210.08:13:10.42#ibcon#about to read 6, iclass 7, count 0 2006.210.08:13:10.42#ibcon#read 6, iclass 7, count 0 2006.210.08:13:10.42#ibcon#end of sib2, iclass 7, count 0 2006.210.08:13:10.42#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:13:10.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:13:10.42#ibcon#[27=USB\r\n] 2006.210.08:13:10.42#ibcon#*before write, iclass 7, count 0 2006.210.08:13:10.42#ibcon#enter sib2, iclass 7, count 0 2006.210.08:13:10.42#ibcon#flushed, iclass 7, count 0 2006.210.08:13:10.42#ibcon#about to write, iclass 7, count 0 2006.210.08:13:10.42#ibcon#wrote, iclass 7, count 0 2006.210.08:13:10.42#ibcon#about to read 3, iclass 7, count 0 2006.210.08:13:10.45#ibcon#read 3, iclass 7, count 0 2006.210.08:13:10.45#ibcon#about to read 4, iclass 7, count 0 2006.210.08:13:10.45#ibcon#read 4, iclass 7, count 0 2006.210.08:13:10.45#ibcon#about to read 5, iclass 7, count 0 2006.210.08:13:10.45#ibcon#read 5, iclass 7, count 0 2006.210.08:13:10.45#ibcon#about to read 6, iclass 7, count 0 2006.210.08:13:10.45#ibcon#read 6, iclass 7, count 0 2006.210.08:13:10.45#ibcon#end of sib2, iclass 7, count 0 2006.210.08:13:10.45#ibcon#*after write, iclass 7, count 0 2006.210.08:13:10.45#ibcon#*before return 0, iclass 7, count 0 2006.210.08:13:10.45#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:13:10.45#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:13:10.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:13:10.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:13:10.45$vc4f8/vblo=2,640.99 2006.210.08:13:10.45#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.08:13:10.45#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.08:13:10.45#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:10.45#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:10.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:10.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:10.45#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:13:10.45#ibcon#first serial, iclass 11, count 0 2006.210.08:13:10.45#ibcon#enter sib2, iclass 11, count 0 2006.210.08:13:10.45#ibcon#flushed, iclass 11, count 0 2006.210.08:13:10.45#ibcon#about to write, iclass 11, count 0 2006.210.08:13:10.45#ibcon#wrote, iclass 11, count 0 2006.210.08:13:10.45#ibcon#about to read 3, iclass 11, count 0 2006.210.08:13:10.47#ibcon#read 3, iclass 11, count 0 2006.210.08:13:10.47#ibcon#about to read 4, iclass 11, count 0 2006.210.08:13:10.47#ibcon#read 4, iclass 11, count 0 2006.210.08:13:10.47#ibcon#about to read 5, iclass 11, count 0 2006.210.08:13:10.47#ibcon#read 5, iclass 11, count 0 2006.210.08:13:10.47#ibcon#about to read 6, iclass 11, count 0 2006.210.08:13:10.47#ibcon#read 6, iclass 11, count 0 2006.210.08:13:10.47#ibcon#end of sib2, iclass 11, count 0 2006.210.08:13:10.47#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:13:10.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:13:10.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:13:10.47#ibcon#*before write, iclass 11, count 0 2006.210.08:13:10.47#ibcon#enter sib2, iclass 11, count 0 2006.210.08:13:10.47#ibcon#flushed, iclass 11, count 0 2006.210.08:13:10.47#ibcon#about to write, iclass 11, count 0 2006.210.08:13:10.47#ibcon#wrote, iclass 11, count 0 2006.210.08:13:10.47#ibcon#about to read 3, iclass 11, count 0 2006.210.08:13:10.51#ibcon#read 3, iclass 11, count 0 2006.210.08:13:10.51#ibcon#about to read 4, iclass 11, count 0 2006.210.08:13:10.51#ibcon#read 4, iclass 11, count 0 2006.210.08:13:10.51#ibcon#about to read 5, iclass 11, count 0 2006.210.08:13:10.51#ibcon#read 5, iclass 11, count 0 2006.210.08:13:10.51#ibcon#about to read 6, iclass 11, count 0 2006.210.08:13:10.51#ibcon#read 6, iclass 11, count 0 2006.210.08:13:10.51#ibcon#end of sib2, iclass 11, count 0 2006.210.08:13:10.51#ibcon#*after write, iclass 11, count 0 2006.210.08:13:10.51#ibcon#*before return 0, iclass 11, count 0 2006.210.08:13:10.51#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:10.51#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:13:10.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:13:10.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:13:10.51$vc4f8/vb=2,4 2006.210.08:13:10.51#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.08:13:10.51#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.08:13:10.51#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:10.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:10.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:10.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:10.57#ibcon#enter wrdev, iclass 13, count 2 2006.210.08:13:10.57#ibcon#first serial, iclass 13, count 2 2006.210.08:13:10.57#ibcon#enter sib2, iclass 13, count 2 2006.210.08:13:10.57#ibcon#flushed, iclass 13, count 2 2006.210.08:13:10.57#ibcon#about to write, iclass 13, count 2 2006.210.08:13:10.57#ibcon#wrote, iclass 13, count 2 2006.210.08:13:10.57#ibcon#about to read 3, iclass 13, count 2 2006.210.08:13:10.59#ibcon#read 3, iclass 13, count 2 2006.210.08:13:10.59#ibcon#about to read 4, iclass 13, count 2 2006.210.08:13:10.59#ibcon#read 4, iclass 13, count 2 2006.210.08:13:10.59#ibcon#about to read 5, iclass 13, count 2 2006.210.08:13:10.59#ibcon#read 5, iclass 13, count 2 2006.210.08:13:10.59#ibcon#about to read 6, iclass 13, count 2 2006.210.08:13:10.59#ibcon#read 6, iclass 13, count 2 2006.210.08:13:10.59#ibcon#end of sib2, iclass 13, count 2 2006.210.08:13:10.59#ibcon#*mode == 0, iclass 13, count 2 2006.210.08:13:10.59#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.08:13:10.59#ibcon#[27=AT02-04\r\n] 2006.210.08:13:10.59#ibcon#*before write, iclass 13, count 2 2006.210.08:13:10.59#ibcon#enter sib2, iclass 13, count 2 2006.210.08:13:10.59#ibcon#flushed, iclass 13, count 2 2006.210.08:13:10.59#ibcon#about to write, iclass 13, count 2 2006.210.08:13:10.59#ibcon#wrote, iclass 13, count 2 2006.210.08:13:10.59#ibcon#about to read 3, iclass 13, count 2 2006.210.08:13:10.62#ibcon#read 3, iclass 13, count 2 2006.210.08:13:10.62#ibcon#about to read 4, iclass 13, count 2 2006.210.08:13:10.62#ibcon#read 4, iclass 13, count 2 2006.210.08:13:10.62#ibcon#about to read 5, iclass 13, count 2 2006.210.08:13:10.62#ibcon#read 5, iclass 13, count 2 2006.210.08:13:10.62#ibcon#about to read 6, iclass 13, count 2 2006.210.08:13:10.62#ibcon#read 6, iclass 13, count 2 2006.210.08:13:10.62#ibcon#end of sib2, iclass 13, count 2 2006.210.08:13:10.62#ibcon#*after write, iclass 13, count 2 2006.210.08:13:10.62#ibcon#*before return 0, iclass 13, count 2 2006.210.08:13:10.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:10.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:13:10.62#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.08:13:10.62#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:10.62#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:10.74#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:10.74#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:10.74#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:13:10.74#ibcon#first serial, iclass 13, count 0 2006.210.08:13:10.74#ibcon#enter sib2, iclass 13, count 0 2006.210.08:13:10.74#ibcon#flushed, iclass 13, count 0 2006.210.08:13:10.74#ibcon#about to write, iclass 13, count 0 2006.210.08:13:10.74#ibcon#wrote, iclass 13, count 0 2006.210.08:13:10.74#ibcon#about to read 3, iclass 13, count 0 2006.210.08:13:10.76#ibcon#read 3, iclass 13, count 0 2006.210.08:13:10.76#ibcon#about to read 4, iclass 13, count 0 2006.210.08:13:10.76#ibcon#read 4, iclass 13, count 0 2006.210.08:13:10.76#ibcon#about to read 5, iclass 13, count 0 2006.210.08:13:10.76#ibcon#read 5, iclass 13, count 0 2006.210.08:13:10.76#ibcon#about to read 6, iclass 13, count 0 2006.210.08:13:10.76#ibcon#read 6, iclass 13, count 0 2006.210.08:13:10.76#ibcon#end of sib2, iclass 13, count 0 2006.210.08:13:10.76#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:13:10.76#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:13:10.76#ibcon#[27=USB\r\n] 2006.210.08:13:10.76#ibcon#*before write, iclass 13, count 0 2006.210.08:13:10.76#ibcon#enter sib2, iclass 13, count 0 2006.210.08:13:10.76#ibcon#flushed, iclass 13, count 0 2006.210.08:13:10.76#ibcon#about to write, iclass 13, count 0 2006.210.08:13:10.76#ibcon#wrote, iclass 13, count 0 2006.210.08:13:10.76#ibcon#about to read 3, iclass 13, count 0 2006.210.08:13:10.79#ibcon#read 3, iclass 13, count 0 2006.210.08:13:10.79#ibcon#about to read 4, iclass 13, count 0 2006.210.08:13:10.79#ibcon#read 4, iclass 13, count 0 2006.210.08:13:10.79#ibcon#about to read 5, iclass 13, count 0 2006.210.08:13:10.79#ibcon#read 5, iclass 13, count 0 2006.210.08:13:10.79#ibcon#about to read 6, iclass 13, count 0 2006.210.08:13:10.79#ibcon#read 6, iclass 13, count 0 2006.210.08:13:10.79#ibcon#end of sib2, iclass 13, count 0 2006.210.08:13:10.79#ibcon#*after write, iclass 13, count 0 2006.210.08:13:10.79#ibcon#*before return 0, iclass 13, count 0 2006.210.08:13:10.79#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:10.79#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:13:10.79#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:13:10.79#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:13:10.79$vc4f8/vblo=3,656.99 2006.210.08:13:10.79#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.08:13:10.79#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.08:13:10.79#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:10.79#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:10.79#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:10.79#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:10.79#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:13:10.79#ibcon#first serial, iclass 15, count 0 2006.210.08:13:10.79#ibcon#enter sib2, iclass 15, count 0 2006.210.08:13:10.79#ibcon#flushed, iclass 15, count 0 2006.210.08:13:10.79#ibcon#about to write, iclass 15, count 0 2006.210.08:13:10.79#ibcon#wrote, iclass 15, count 0 2006.210.08:13:10.79#ibcon#about to read 3, iclass 15, count 0 2006.210.08:13:10.81#ibcon#read 3, iclass 15, count 0 2006.210.08:13:10.81#ibcon#about to read 4, iclass 15, count 0 2006.210.08:13:10.81#ibcon#read 4, iclass 15, count 0 2006.210.08:13:10.81#ibcon#about to read 5, iclass 15, count 0 2006.210.08:13:10.81#ibcon#read 5, iclass 15, count 0 2006.210.08:13:10.81#ibcon#about to read 6, iclass 15, count 0 2006.210.08:13:10.81#ibcon#read 6, iclass 15, count 0 2006.210.08:13:10.81#ibcon#end of sib2, iclass 15, count 0 2006.210.08:13:10.81#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:13:10.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:13:10.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:13:10.81#ibcon#*before write, iclass 15, count 0 2006.210.08:13:10.81#ibcon#enter sib2, iclass 15, count 0 2006.210.08:13:10.81#ibcon#flushed, iclass 15, count 0 2006.210.08:13:10.81#ibcon#about to write, iclass 15, count 0 2006.210.08:13:10.81#ibcon#wrote, iclass 15, count 0 2006.210.08:13:10.81#ibcon#about to read 3, iclass 15, count 0 2006.210.08:13:10.85#ibcon#read 3, iclass 15, count 0 2006.210.08:13:10.85#ibcon#about to read 4, iclass 15, count 0 2006.210.08:13:10.85#ibcon#read 4, iclass 15, count 0 2006.210.08:13:10.85#ibcon#about to read 5, iclass 15, count 0 2006.210.08:13:10.85#ibcon#read 5, iclass 15, count 0 2006.210.08:13:10.85#ibcon#about to read 6, iclass 15, count 0 2006.210.08:13:10.85#ibcon#read 6, iclass 15, count 0 2006.210.08:13:10.85#ibcon#end of sib2, iclass 15, count 0 2006.210.08:13:10.85#ibcon#*after write, iclass 15, count 0 2006.210.08:13:10.85#ibcon#*before return 0, iclass 15, count 0 2006.210.08:13:10.85#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:10.85#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:13:10.85#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:13:10.85#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:13:10.85$vc4f8/vb=3,3 2006.210.08:13:10.85#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.08:13:10.85#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.08:13:10.85#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:10.85#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:10.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:10.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:10.91#ibcon#enter wrdev, iclass 17, count 2 2006.210.08:13:10.91#ibcon#first serial, iclass 17, count 2 2006.210.08:13:10.91#ibcon#enter sib2, iclass 17, count 2 2006.210.08:13:10.91#ibcon#flushed, iclass 17, count 2 2006.210.08:13:10.91#ibcon#about to write, iclass 17, count 2 2006.210.08:13:10.91#ibcon#wrote, iclass 17, count 2 2006.210.08:13:10.91#ibcon#about to read 3, iclass 17, count 2 2006.210.08:13:10.93#ibcon#read 3, iclass 17, count 2 2006.210.08:13:10.93#ibcon#about to read 4, iclass 17, count 2 2006.210.08:13:10.93#ibcon#read 4, iclass 17, count 2 2006.210.08:13:10.93#ibcon#about to read 5, iclass 17, count 2 2006.210.08:13:10.93#ibcon#read 5, iclass 17, count 2 2006.210.08:13:10.93#ibcon#about to read 6, iclass 17, count 2 2006.210.08:13:10.93#ibcon#read 6, iclass 17, count 2 2006.210.08:13:10.93#ibcon#end of sib2, iclass 17, count 2 2006.210.08:13:10.93#ibcon#*mode == 0, iclass 17, count 2 2006.210.08:13:10.93#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.08:13:10.93#ibcon#[27=AT03-03\r\n] 2006.210.08:13:10.93#ibcon#*before write, iclass 17, count 2 2006.210.08:13:10.93#ibcon#enter sib2, iclass 17, count 2 2006.210.08:13:10.93#ibcon#flushed, iclass 17, count 2 2006.210.08:13:10.93#ibcon#about to write, iclass 17, count 2 2006.210.08:13:10.93#ibcon#wrote, iclass 17, count 2 2006.210.08:13:10.93#ibcon#about to read 3, iclass 17, count 2 2006.210.08:13:10.96#ibcon#read 3, iclass 17, count 2 2006.210.08:13:10.96#ibcon#about to read 4, iclass 17, count 2 2006.210.08:13:10.96#ibcon#read 4, iclass 17, count 2 2006.210.08:13:10.96#ibcon#about to read 5, iclass 17, count 2 2006.210.08:13:10.96#ibcon#read 5, iclass 17, count 2 2006.210.08:13:10.96#ibcon#about to read 6, iclass 17, count 2 2006.210.08:13:10.96#ibcon#read 6, iclass 17, count 2 2006.210.08:13:10.96#ibcon#end of sib2, iclass 17, count 2 2006.210.08:13:10.96#ibcon#*after write, iclass 17, count 2 2006.210.08:13:10.96#ibcon#*before return 0, iclass 17, count 2 2006.210.08:13:10.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:10.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:13:10.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.08:13:10.96#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:10.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:11.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:11.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:11.08#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:13:11.08#ibcon#first serial, iclass 17, count 0 2006.210.08:13:11.08#ibcon#enter sib2, iclass 17, count 0 2006.210.08:13:11.08#ibcon#flushed, iclass 17, count 0 2006.210.08:13:11.08#ibcon#about to write, iclass 17, count 0 2006.210.08:13:11.08#ibcon#wrote, iclass 17, count 0 2006.210.08:13:11.08#ibcon#about to read 3, iclass 17, count 0 2006.210.08:13:11.10#ibcon#read 3, iclass 17, count 0 2006.210.08:13:11.10#ibcon#about to read 4, iclass 17, count 0 2006.210.08:13:11.10#ibcon#read 4, iclass 17, count 0 2006.210.08:13:11.10#ibcon#about to read 5, iclass 17, count 0 2006.210.08:13:11.10#ibcon#read 5, iclass 17, count 0 2006.210.08:13:11.10#ibcon#about to read 6, iclass 17, count 0 2006.210.08:13:11.10#ibcon#read 6, iclass 17, count 0 2006.210.08:13:11.10#ibcon#end of sib2, iclass 17, count 0 2006.210.08:13:11.10#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:13:11.10#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:13:11.10#ibcon#[27=USB\r\n] 2006.210.08:13:11.10#ibcon#*before write, iclass 17, count 0 2006.210.08:13:11.10#ibcon#enter sib2, iclass 17, count 0 2006.210.08:13:11.10#ibcon#flushed, iclass 17, count 0 2006.210.08:13:11.10#ibcon#about to write, iclass 17, count 0 2006.210.08:13:11.10#ibcon#wrote, iclass 17, count 0 2006.210.08:13:11.10#ibcon#about to read 3, iclass 17, count 0 2006.210.08:13:11.13#ibcon#read 3, iclass 17, count 0 2006.210.08:13:11.13#ibcon#about to read 4, iclass 17, count 0 2006.210.08:13:11.13#ibcon#read 4, iclass 17, count 0 2006.210.08:13:11.13#ibcon#about to read 5, iclass 17, count 0 2006.210.08:13:11.13#ibcon#read 5, iclass 17, count 0 2006.210.08:13:11.13#ibcon#about to read 6, iclass 17, count 0 2006.210.08:13:11.13#ibcon#read 6, iclass 17, count 0 2006.210.08:13:11.13#ibcon#end of sib2, iclass 17, count 0 2006.210.08:13:11.13#ibcon#*after write, iclass 17, count 0 2006.210.08:13:11.13#ibcon#*before return 0, iclass 17, count 0 2006.210.08:13:11.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:11.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:13:11.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:13:11.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:13:11.13$vc4f8/vblo=4,712.99 2006.210.08:13:11.13#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.08:13:11.13#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.08:13:11.13#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:11.13#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:11.13#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:11.13#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:11.13#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:13:11.13#ibcon#first serial, iclass 19, count 0 2006.210.08:13:11.13#ibcon#enter sib2, iclass 19, count 0 2006.210.08:13:11.13#ibcon#flushed, iclass 19, count 0 2006.210.08:13:11.13#ibcon#about to write, iclass 19, count 0 2006.210.08:13:11.13#ibcon#wrote, iclass 19, count 0 2006.210.08:13:11.13#ibcon#about to read 3, iclass 19, count 0 2006.210.08:13:11.15#ibcon#read 3, iclass 19, count 0 2006.210.08:13:11.15#ibcon#about to read 4, iclass 19, count 0 2006.210.08:13:11.15#ibcon#read 4, iclass 19, count 0 2006.210.08:13:11.15#ibcon#about to read 5, iclass 19, count 0 2006.210.08:13:11.15#ibcon#read 5, iclass 19, count 0 2006.210.08:13:11.15#ibcon#about to read 6, iclass 19, count 0 2006.210.08:13:11.15#ibcon#read 6, iclass 19, count 0 2006.210.08:13:11.15#ibcon#end of sib2, iclass 19, count 0 2006.210.08:13:11.15#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:13:11.15#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:13:11.15#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:13:11.15#ibcon#*before write, iclass 19, count 0 2006.210.08:13:11.15#ibcon#enter sib2, iclass 19, count 0 2006.210.08:13:11.15#ibcon#flushed, iclass 19, count 0 2006.210.08:13:11.15#ibcon#about to write, iclass 19, count 0 2006.210.08:13:11.15#ibcon#wrote, iclass 19, count 0 2006.210.08:13:11.15#ibcon#about to read 3, iclass 19, count 0 2006.210.08:13:11.19#ibcon#read 3, iclass 19, count 0 2006.210.08:13:11.19#ibcon#about to read 4, iclass 19, count 0 2006.210.08:13:11.19#ibcon#read 4, iclass 19, count 0 2006.210.08:13:11.19#ibcon#about to read 5, iclass 19, count 0 2006.210.08:13:11.19#ibcon#read 5, iclass 19, count 0 2006.210.08:13:11.19#ibcon#about to read 6, iclass 19, count 0 2006.210.08:13:11.19#ibcon#read 6, iclass 19, count 0 2006.210.08:13:11.19#ibcon#end of sib2, iclass 19, count 0 2006.210.08:13:11.19#ibcon#*after write, iclass 19, count 0 2006.210.08:13:11.19#ibcon#*before return 0, iclass 19, count 0 2006.210.08:13:11.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:11.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:13:11.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:13:11.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:13:11.19$vc4f8/vb=4,3 2006.210.08:13:11.19#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.08:13:11.19#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.08:13:11.19#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:11.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:11.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:11.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:11.25#ibcon#enter wrdev, iclass 21, count 2 2006.210.08:13:11.25#ibcon#first serial, iclass 21, count 2 2006.210.08:13:11.25#ibcon#enter sib2, iclass 21, count 2 2006.210.08:13:11.25#ibcon#flushed, iclass 21, count 2 2006.210.08:13:11.25#ibcon#about to write, iclass 21, count 2 2006.210.08:13:11.25#ibcon#wrote, iclass 21, count 2 2006.210.08:13:11.25#ibcon#about to read 3, iclass 21, count 2 2006.210.08:13:11.27#ibcon#read 3, iclass 21, count 2 2006.210.08:13:11.27#ibcon#about to read 4, iclass 21, count 2 2006.210.08:13:11.27#ibcon#read 4, iclass 21, count 2 2006.210.08:13:11.27#ibcon#about to read 5, iclass 21, count 2 2006.210.08:13:11.27#ibcon#read 5, iclass 21, count 2 2006.210.08:13:11.27#ibcon#about to read 6, iclass 21, count 2 2006.210.08:13:11.27#ibcon#read 6, iclass 21, count 2 2006.210.08:13:11.27#ibcon#end of sib2, iclass 21, count 2 2006.210.08:13:11.27#ibcon#*mode == 0, iclass 21, count 2 2006.210.08:13:11.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.08:13:11.27#ibcon#[27=AT04-03\r\n] 2006.210.08:13:11.27#ibcon#*before write, iclass 21, count 2 2006.210.08:13:11.27#ibcon#enter sib2, iclass 21, count 2 2006.210.08:13:11.27#ibcon#flushed, iclass 21, count 2 2006.210.08:13:11.27#ibcon#about to write, iclass 21, count 2 2006.210.08:13:11.27#ibcon#wrote, iclass 21, count 2 2006.210.08:13:11.27#ibcon#about to read 3, iclass 21, count 2 2006.210.08:13:11.30#ibcon#read 3, iclass 21, count 2 2006.210.08:13:11.30#ibcon#about to read 4, iclass 21, count 2 2006.210.08:13:11.30#ibcon#read 4, iclass 21, count 2 2006.210.08:13:11.30#ibcon#about to read 5, iclass 21, count 2 2006.210.08:13:11.30#ibcon#read 5, iclass 21, count 2 2006.210.08:13:11.30#ibcon#about to read 6, iclass 21, count 2 2006.210.08:13:11.30#ibcon#read 6, iclass 21, count 2 2006.210.08:13:11.30#ibcon#end of sib2, iclass 21, count 2 2006.210.08:13:11.30#ibcon#*after write, iclass 21, count 2 2006.210.08:13:11.30#ibcon#*before return 0, iclass 21, count 2 2006.210.08:13:11.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:11.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:13:11.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.08:13:11.30#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:11.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:11.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:11.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:11.42#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:13:11.42#ibcon#first serial, iclass 21, count 0 2006.210.08:13:11.42#ibcon#enter sib2, iclass 21, count 0 2006.210.08:13:11.42#ibcon#flushed, iclass 21, count 0 2006.210.08:13:11.42#ibcon#about to write, iclass 21, count 0 2006.210.08:13:11.42#ibcon#wrote, iclass 21, count 0 2006.210.08:13:11.42#ibcon#about to read 3, iclass 21, count 0 2006.210.08:13:11.44#ibcon#read 3, iclass 21, count 0 2006.210.08:13:11.44#ibcon#about to read 4, iclass 21, count 0 2006.210.08:13:11.44#ibcon#read 4, iclass 21, count 0 2006.210.08:13:11.44#ibcon#about to read 5, iclass 21, count 0 2006.210.08:13:11.44#ibcon#read 5, iclass 21, count 0 2006.210.08:13:11.44#ibcon#about to read 6, iclass 21, count 0 2006.210.08:13:11.44#ibcon#read 6, iclass 21, count 0 2006.210.08:13:11.44#ibcon#end of sib2, iclass 21, count 0 2006.210.08:13:11.44#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:13:11.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:13:11.44#ibcon#[27=USB\r\n] 2006.210.08:13:11.44#ibcon#*before write, iclass 21, count 0 2006.210.08:13:11.44#ibcon#enter sib2, iclass 21, count 0 2006.210.08:13:11.44#ibcon#flushed, iclass 21, count 0 2006.210.08:13:11.44#ibcon#about to write, iclass 21, count 0 2006.210.08:13:11.44#ibcon#wrote, iclass 21, count 0 2006.210.08:13:11.44#ibcon#about to read 3, iclass 21, count 0 2006.210.08:13:11.47#ibcon#read 3, iclass 21, count 0 2006.210.08:13:11.47#ibcon#about to read 4, iclass 21, count 0 2006.210.08:13:11.47#ibcon#read 4, iclass 21, count 0 2006.210.08:13:11.47#ibcon#about to read 5, iclass 21, count 0 2006.210.08:13:11.47#ibcon#read 5, iclass 21, count 0 2006.210.08:13:11.47#ibcon#about to read 6, iclass 21, count 0 2006.210.08:13:11.47#ibcon#read 6, iclass 21, count 0 2006.210.08:13:11.47#ibcon#end of sib2, iclass 21, count 0 2006.210.08:13:11.47#ibcon#*after write, iclass 21, count 0 2006.210.08:13:11.47#ibcon#*before return 0, iclass 21, count 0 2006.210.08:13:11.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:11.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:13:11.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:13:11.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:13:11.47$vc4f8/vblo=5,744.99 2006.210.08:13:11.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.08:13:11.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.08:13:11.47#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:11.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:11.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:11.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:11.47#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:13:11.47#ibcon#first serial, iclass 23, count 0 2006.210.08:13:11.47#ibcon#enter sib2, iclass 23, count 0 2006.210.08:13:11.47#ibcon#flushed, iclass 23, count 0 2006.210.08:13:11.47#ibcon#about to write, iclass 23, count 0 2006.210.08:13:11.47#ibcon#wrote, iclass 23, count 0 2006.210.08:13:11.47#ibcon#about to read 3, iclass 23, count 0 2006.210.08:13:11.49#ibcon#read 3, iclass 23, count 0 2006.210.08:13:11.49#ibcon#about to read 4, iclass 23, count 0 2006.210.08:13:11.49#ibcon#read 4, iclass 23, count 0 2006.210.08:13:11.49#ibcon#about to read 5, iclass 23, count 0 2006.210.08:13:11.49#ibcon#read 5, iclass 23, count 0 2006.210.08:13:11.49#ibcon#about to read 6, iclass 23, count 0 2006.210.08:13:11.49#ibcon#read 6, iclass 23, count 0 2006.210.08:13:11.49#ibcon#end of sib2, iclass 23, count 0 2006.210.08:13:11.49#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:13:11.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:13:11.49#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:13:11.49#ibcon#*before write, iclass 23, count 0 2006.210.08:13:11.49#ibcon#enter sib2, iclass 23, count 0 2006.210.08:13:11.49#ibcon#flushed, iclass 23, count 0 2006.210.08:13:11.49#ibcon#about to write, iclass 23, count 0 2006.210.08:13:11.49#ibcon#wrote, iclass 23, count 0 2006.210.08:13:11.49#ibcon#about to read 3, iclass 23, count 0 2006.210.08:13:11.53#ibcon#read 3, iclass 23, count 0 2006.210.08:13:11.53#ibcon#about to read 4, iclass 23, count 0 2006.210.08:13:11.53#ibcon#read 4, iclass 23, count 0 2006.210.08:13:11.53#ibcon#about to read 5, iclass 23, count 0 2006.210.08:13:11.53#ibcon#read 5, iclass 23, count 0 2006.210.08:13:11.53#ibcon#about to read 6, iclass 23, count 0 2006.210.08:13:11.53#ibcon#read 6, iclass 23, count 0 2006.210.08:13:11.53#ibcon#end of sib2, iclass 23, count 0 2006.210.08:13:11.53#ibcon#*after write, iclass 23, count 0 2006.210.08:13:11.53#ibcon#*before return 0, iclass 23, count 0 2006.210.08:13:11.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:11.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:13:11.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:13:11.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:13:11.53$vc4f8/vb=5,3 2006.210.08:13:11.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.08:13:11.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.08:13:11.53#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:11.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:11.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:11.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:11.59#ibcon#enter wrdev, iclass 25, count 2 2006.210.08:13:11.59#ibcon#first serial, iclass 25, count 2 2006.210.08:13:11.59#ibcon#enter sib2, iclass 25, count 2 2006.210.08:13:11.59#ibcon#flushed, iclass 25, count 2 2006.210.08:13:11.59#ibcon#about to write, iclass 25, count 2 2006.210.08:13:11.59#ibcon#wrote, iclass 25, count 2 2006.210.08:13:11.59#ibcon#about to read 3, iclass 25, count 2 2006.210.08:13:11.61#ibcon#read 3, iclass 25, count 2 2006.210.08:13:11.61#ibcon#about to read 4, iclass 25, count 2 2006.210.08:13:11.61#ibcon#read 4, iclass 25, count 2 2006.210.08:13:11.61#ibcon#about to read 5, iclass 25, count 2 2006.210.08:13:11.61#ibcon#read 5, iclass 25, count 2 2006.210.08:13:11.61#ibcon#about to read 6, iclass 25, count 2 2006.210.08:13:11.61#ibcon#read 6, iclass 25, count 2 2006.210.08:13:11.61#ibcon#end of sib2, iclass 25, count 2 2006.210.08:13:11.61#ibcon#*mode == 0, iclass 25, count 2 2006.210.08:13:11.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.08:13:11.61#ibcon#[27=AT05-03\r\n] 2006.210.08:13:11.61#ibcon#*before write, iclass 25, count 2 2006.210.08:13:11.61#ibcon#enter sib2, iclass 25, count 2 2006.210.08:13:11.61#ibcon#flushed, iclass 25, count 2 2006.210.08:13:11.61#ibcon#about to write, iclass 25, count 2 2006.210.08:13:11.61#ibcon#wrote, iclass 25, count 2 2006.210.08:13:11.61#ibcon#about to read 3, iclass 25, count 2 2006.210.08:13:11.64#ibcon#read 3, iclass 25, count 2 2006.210.08:13:11.64#ibcon#about to read 4, iclass 25, count 2 2006.210.08:13:11.64#ibcon#read 4, iclass 25, count 2 2006.210.08:13:11.64#ibcon#about to read 5, iclass 25, count 2 2006.210.08:13:11.64#ibcon#read 5, iclass 25, count 2 2006.210.08:13:11.64#ibcon#about to read 6, iclass 25, count 2 2006.210.08:13:11.64#ibcon#read 6, iclass 25, count 2 2006.210.08:13:11.64#ibcon#end of sib2, iclass 25, count 2 2006.210.08:13:11.64#ibcon#*after write, iclass 25, count 2 2006.210.08:13:11.64#ibcon#*before return 0, iclass 25, count 2 2006.210.08:13:11.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:11.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:13:11.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.08:13:11.64#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:11.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:11.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:11.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:11.76#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:13:11.76#ibcon#first serial, iclass 25, count 0 2006.210.08:13:11.76#ibcon#enter sib2, iclass 25, count 0 2006.210.08:13:11.76#ibcon#flushed, iclass 25, count 0 2006.210.08:13:11.76#ibcon#about to write, iclass 25, count 0 2006.210.08:13:11.76#ibcon#wrote, iclass 25, count 0 2006.210.08:13:11.76#ibcon#about to read 3, iclass 25, count 0 2006.210.08:13:11.78#ibcon#read 3, iclass 25, count 0 2006.210.08:13:11.78#ibcon#about to read 4, iclass 25, count 0 2006.210.08:13:11.78#ibcon#read 4, iclass 25, count 0 2006.210.08:13:11.78#ibcon#about to read 5, iclass 25, count 0 2006.210.08:13:11.78#ibcon#read 5, iclass 25, count 0 2006.210.08:13:11.78#ibcon#about to read 6, iclass 25, count 0 2006.210.08:13:11.78#ibcon#read 6, iclass 25, count 0 2006.210.08:13:11.78#ibcon#end of sib2, iclass 25, count 0 2006.210.08:13:11.78#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:13:11.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:13:11.78#ibcon#[27=USB\r\n] 2006.210.08:13:11.78#ibcon#*before write, iclass 25, count 0 2006.210.08:13:11.78#ibcon#enter sib2, iclass 25, count 0 2006.210.08:13:11.78#ibcon#flushed, iclass 25, count 0 2006.210.08:13:11.78#ibcon#about to write, iclass 25, count 0 2006.210.08:13:11.78#ibcon#wrote, iclass 25, count 0 2006.210.08:13:11.78#ibcon#about to read 3, iclass 25, count 0 2006.210.08:13:11.81#ibcon#read 3, iclass 25, count 0 2006.210.08:13:11.81#ibcon#about to read 4, iclass 25, count 0 2006.210.08:13:11.81#ibcon#read 4, iclass 25, count 0 2006.210.08:13:11.81#ibcon#about to read 5, iclass 25, count 0 2006.210.08:13:11.81#ibcon#read 5, iclass 25, count 0 2006.210.08:13:11.81#ibcon#about to read 6, iclass 25, count 0 2006.210.08:13:11.81#ibcon#read 6, iclass 25, count 0 2006.210.08:13:11.81#ibcon#end of sib2, iclass 25, count 0 2006.210.08:13:11.81#ibcon#*after write, iclass 25, count 0 2006.210.08:13:11.81#ibcon#*before return 0, iclass 25, count 0 2006.210.08:13:11.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:11.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:13:11.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:13:11.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:13:11.81$vc4f8/vblo=6,752.99 2006.210.08:13:11.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.08:13:11.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.08:13:11.81#ibcon#ireg 17 cls_cnt 0 2006.210.08:13:11.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:11.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:11.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:11.81#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:13:11.81#ibcon#first serial, iclass 27, count 0 2006.210.08:13:11.81#ibcon#enter sib2, iclass 27, count 0 2006.210.08:13:11.81#ibcon#flushed, iclass 27, count 0 2006.210.08:13:11.81#ibcon#about to write, iclass 27, count 0 2006.210.08:13:11.81#ibcon#wrote, iclass 27, count 0 2006.210.08:13:11.81#ibcon#about to read 3, iclass 27, count 0 2006.210.08:13:11.83#ibcon#read 3, iclass 27, count 0 2006.210.08:13:11.83#ibcon#about to read 4, iclass 27, count 0 2006.210.08:13:11.83#ibcon#read 4, iclass 27, count 0 2006.210.08:13:11.83#ibcon#about to read 5, iclass 27, count 0 2006.210.08:13:11.83#ibcon#read 5, iclass 27, count 0 2006.210.08:13:11.83#ibcon#about to read 6, iclass 27, count 0 2006.210.08:13:11.83#ibcon#read 6, iclass 27, count 0 2006.210.08:13:11.83#ibcon#end of sib2, iclass 27, count 0 2006.210.08:13:11.83#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:13:11.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:13:11.83#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:13:11.83#ibcon#*before write, iclass 27, count 0 2006.210.08:13:11.83#ibcon#enter sib2, iclass 27, count 0 2006.210.08:13:11.83#ibcon#flushed, iclass 27, count 0 2006.210.08:13:11.83#ibcon#about to write, iclass 27, count 0 2006.210.08:13:11.83#ibcon#wrote, iclass 27, count 0 2006.210.08:13:11.83#ibcon#about to read 3, iclass 27, count 0 2006.210.08:13:11.87#ibcon#read 3, iclass 27, count 0 2006.210.08:13:11.87#ibcon#about to read 4, iclass 27, count 0 2006.210.08:13:11.87#ibcon#read 4, iclass 27, count 0 2006.210.08:13:11.87#ibcon#about to read 5, iclass 27, count 0 2006.210.08:13:11.87#ibcon#read 5, iclass 27, count 0 2006.210.08:13:11.87#ibcon#about to read 6, iclass 27, count 0 2006.210.08:13:11.87#ibcon#read 6, iclass 27, count 0 2006.210.08:13:11.87#ibcon#end of sib2, iclass 27, count 0 2006.210.08:13:11.87#ibcon#*after write, iclass 27, count 0 2006.210.08:13:11.87#ibcon#*before return 0, iclass 27, count 0 2006.210.08:13:11.87#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:11.87#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:13:11.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:13:11.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:13:11.87$vc4f8/vb=6,3 2006.210.08:13:11.87#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.08:13:11.87#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.08:13:11.87#ibcon#ireg 11 cls_cnt 2 2006.210.08:13:11.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:11.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:11.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:11.93#ibcon#enter wrdev, iclass 29, count 2 2006.210.08:13:11.93#ibcon#first serial, iclass 29, count 2 2006.210.08:13:11.93#ibcon#enter sib2, iclass 29, count 2 2006.210.08:13:11.93#ibcon#flushed, iclass 29, count 2 2006.210.08:13:11.93#ibcon#about to write, iclass 29, count 2 2006.210.08:13:11.93#ibcon#wrote, iclass 29, count 2 2006.210.08:13:11.93#ibcon#about to read 3, iclass 29, count 2 2006.210.08:13:11.95#ibcon#read 3, iclass 29, count 2 2006.210.08:13:11.95#ibcon#about to read 4, iclass 29, count 2 2006.210.08:13:11.95#ibcon#read 4, iclass 29, count 2 2006.210.08:13:11.95#ibcon#about to read 5, iclass 29, count 2 2006.210.08:13:11.95#ibcon#read 5, iclass 29, count 2 2006.210.08:13:11.95#ibcon#about to read 6, iclass 29, count 2 2006.210.08:13:11.95#ibcon#read 6, iclass 29, count 2 2006.210.08:13:11.95#ibcon#end of sib2, iclass 29, count 2 2006.210.08:13:11.95#ibcon#*mode == 0, iclass 29, count 2 2006.210.08:13:11.95#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.08:13:11.95#ibcon#[27=AT06-03\r\n] 2006.210.08:13:11.95#ibcon#*before write, iclass 29, count 2 2006.210.08:13:11.95#ibcon#enter sib2, iclass 29, count 2 2006.210.08:13:11.95#ibcon#flushed, iclass 29, count 2 2006.210.08:13:11.95#ibcon#about to write, iclass 29, count 2 2006.210.08:13:11.95#ibcon#wrote, iclass 29, count 2 2006.210.08:13:11.95#ibcon#about to read 3, iclass 29, count 2 2006.210.08:13:11.97#abcon#<5=/05 3.5 6.4 30.06 821006.5\r\n> 2006.210.08:13:11.98#ibcon#read 3, iclass 29, count 2 2006.210.08:13:11.98#ibcon#about to read 4, iclass 29, count 2 2006.210.08:13:11.98#ibcon#read 4, iclass 29, count 2 2006.210.08:13:11.98#ibcon#about to read 5, iclass 29, count 2 2006.210.08:13:11.98#ibcon#read 5, iclass 29, count 2 2006.210.08:13:11.98#ibcon#about to read 6, iclass 29, count 2 2006.210.08:13:11.98#ibcon#read 6, iclass 29, count 2 2006.210.08:13:11.98#ibcon#end of sib2, iclass 29, count 2 2006.210.08:13:11.98#ibcon#*after write, iclass 29, count 2 2006.210.08:13:11.98#ibcon#*before return 0, iclass 29, count 2 2006.210.08:13:11.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:11.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:13:11.98#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.08:13:11.98#ibcon#ireg 7 cls_cnt 0 2006.210.08:13:11.98#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:11.99#abcon#{5=INTERFACE CLEAR} 2006.210.08:13:12.05#abcon#[5=S1D000X0/0*\r\n] 2006.210.08:13:12.10#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:12.10#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:12.10#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:13:12.10#ibcon#first serial, iclass 29, count 0 2006.210.08:13:12.10#ibcon#enter sib2, iclass 29, count 0 2006.210.08:13:12.10#ibcon#flushed, iclass 29, count 0 2006.210.08:13:12.10#ibcon#about to write, iclass 29, count 0 2006.210.08:13:12.10#ibcon#wrote, iclass 29, count 0 2006.210.08:13:12.10#ibcon#about to read 3, iclass 29, count 0 2006.210.08:13:12.12#ibcon#read 3, iclass 29, count 0 2006.210.08:13:12.12#ibcon#about to read 4, iclass 29, count 0 2006.210.08:13:12.12#ibcon#read 4, iclass 29, count 0 2006.210.08:13:12.12#ibcon#about to read 5, iclass 29, count 0 2006.210.08:13:12.12#ibcon#read 5, iclass 29, count 0 2006.210.08:13:12.12#ibcon#about to read 6, iclass 29, count 0 2006.210.08:13:12.12#ibcon#read 6, iclass 29, count 0 2006.210.08:13:12.12#ibcon#end of sib2, iclass 29, count 0 2006.210.08:13:12.12#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:13:12.12#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:13:12.12#ibcon#[27=USB\r\n] 2006.210.08:13:12.12#ibcon#*before write, iclass 29, count 0 2006.210.08:13:12.12#ibcon#enter sib2, iclass 29, count 0 2006.210.08:13:12.12#ibcon#flushed, iclass 29, count 0 2006.210.08:13:12.12#ibcon#about to write, iclass 29, count 0 2006.210.08:13:12.12#ibcon#wrote, iclass 29, count 0 2006.210.08:13:12.12#ibcon#about to read 3, iclass 29, count 0 2006.210.08:13:12.15#ibcon#read 3, iclass 29, count 0 2006.210.08:13:12.15#ibcon#about to read 4, iclass 29, count 0 2006.210.08:13:12.15#ibcon#read 4, iclass 29, count 0 2006.210.08:13:12.15#ibcon#about to read 5, iclass 29, count 0 2006.210.08:13:12.15#ibcon#read 5, iclass 29, count 0 2006.210.08:13:12.15#ibcon#about to read 6, iclass 29, count 0 2006.210.08:13:12.15#ibcon#read 6, iclass 29, count 0 2006.210.08:13:12.15#ibcon#end of sib2, iclass 29, count 0 2006.210.08:13:12.15#ibcon#*after write, iclass 29, count 0 2006.210.08:13:12.15#ibcon#*before return 0, iclass 29, count 0 2006.210.08:13:12.15#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:12.15#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:13:12.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:13:12.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:13:12.15$vc4f8/vabw=wide 2006.210.08:13:12.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:13:12.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:13:12.15#ibcon#ireg 8 cls_cnt 0 2006.210.08:13:12.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:12.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:12.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:12.15#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:13:12.15#ibcon#first serial, iclass 35, count 0 2006.210.08:13:12.15#ibcon#enter sib2, iclass 35, count 0 2006.210.08:13:12.15#ibcon#flushed, iclass 35, count 0 2006.210.08:13:12.15#ibcon#about to write, iclass 35, count 0 2006.210.08:13:12.15#ibcon#wrote, iclass 35, count 0 2006.210.08:13:12.15#ibcon#about to read 3, iclass 35, count 0 2006.210.08:13:12.17#ibcon#read 3, iclass 35, count 0 2006.210.08:13:12.17#ibcon#about to read 4, iclass 35, count 0 2006.210.08:13:12.17#ibcon#read 4, iclass 35, count 0 2006.210.08:13:12.17#ibcon#about to read 5, iclass 35, count 0 2006.210.08:13:12.17#ibcon#read 5, iclass 35, count 0 2006.210.08:13:12.17#ibcon#about to read 6, iclass 35, count 0 2006.210.08:13:12.17#ibcon#read 6, iclass 35, count 0 2006.210.08:13:12.17#ibcon#end of sib2, iclass 35, count 0 2006.210.08:13:12.17#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:13:12.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:13:12.17#ibcon#[25=BW32\r\n] 2006.210.08:13:12.17#ibcon#*before write, iclass 35, count 0 2006.210.08:13:12.17#ibcon#enter sib2, iclass 35, count 0 2006.210.08:13:12.17#ibcon#flushed, iclass 35, count 0 2006.210.08:13:12.17#ibcon#about to write, iclass 35, count 0 2006.210.08:13:12.17#ibcon#wrote, iclass 35, count 0 2006.210.08:13:12.17#ibcon#about to read 3, iclass 35, count 0 2006.210.08:13:12.20#ibcon#read 3, iclass 35, count 0 2006.210.08:13:12.20#ibcon#about to read 4, iclass 35, count 0 2006.210.08:13:12.20#ibcon#read 4, iclass 35, count 0 2006.210.08:13:12.20#ibcon#about to read 5, iclass 35, count 0 2006.210.08:13:12.20#ibcon#read 5, iclass 35, count 0 2006.210.08:13:12.20#ibcon#about to read 6, iclass 35, count 0 2006.210.08:13:12.20#ibcon#read 6, iclass 35, count 0 2006.210.08:13:12.20#ibcon#end of sib2, iclass 35, count 0 2006.210.08:13:12.20#ibcon#*after write, iclass 35, count 0 2006.210.08:13:12.20#ibcon#*before return 0, iclass 35, count 0 2006.210.08:13:12.20#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:12.20#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:13:12.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:13:12.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:13:12.20$vc4f8/vbbw=wide 2006.210.08:13:12.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:13:12.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:13:12.20#ibcon#ireg 8 cls_cnt 0 2006.210.08:13:12.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:13:12.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:13:12.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:13:12.27#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:13:12.27#ibcon#first serial, iclass 37, count 0 2006.210.08:13:12.27#ibcon#enter sib2, iclass 37, count 0 2006.210.08:13:12.27#ibcon#flushed, iclass 37, count 0 2006.210.08:13:12.27#ibcon#about to write, iclass 37, count 0 2006.210.08:13:12.27#ibcon#wrote, iclass 37, count 0 2006.210.08:13:12.27#ibcon#about to read 3, iclass 37, count 0 2006.210.08:13:12.29#ibcon#read 3, iclass 37, count 0 2006.210.08:13:12.29#ibcon#about to read 4, iclass 37, count 0 2006.210.08:13:12.29#ibcon#read 4, iclass 37, count 0 2006.210.08:13:12.29#ibcon#about to read 5, iclass 37, count 0 2006.210.08:13:12.29#ibcon#read 5, iclass 37, count 0 2006.210.08:13:12.29#ibcon#about to read 6, iclass 37, count 0 2006.210.08:13:12.29#ibcon#read 6, iclass 37, count 0 2006.210.08:13:12.29#ibcon#end of sib2, iclass 37, count 0 2006.210.08:13:12.29#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:13:12.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:13:12.29#ibcon#[27=BW32\r\n] 2006.210.08:13:12.29#ibcon#*before write, iclass 37, count 0 2006.210.08:13:12.29#ibcon#enter sib2, iclass 37, count 0 2006.210.08:13:12.29#ibcon#flushed, iclass 37, count 0 2006.210.08:13:12.29#ibcon#about to write, iclass 37, count 0 2006.210.08:13:12.29#ibcon#wrote, iclass 37, count 0 2006.210.08:13:12.29#ibcon#about to read 3, iclass 37, count 0 2006.210.08:13:12.32#ibcon#read 3, iclass 37, count 0 2006.210.08:13:12.32#ibcon#about to read 4, iclass 37, count 0 2006.210.08:13:12.32#ibcon#read 4, iclass 37, count 0 2006.210.08:13:12.32#ibcon#about to read 5, iclass 37, count 0 2006.210.08:13:12.32#ibcon#read 5, iclass 37, count 0 2006.210.08:13:12.32#ibcon#about to read 6, iclass 37, count 0 2006.210.08:13:12.32#ibcon#read 6, iclass 37, count 0 2006.210.08:13:12.32#ibcon#end of sib2, iclass 37, count 0 2006.210.08:13:12.32#ibcon#*after write, iclass 37, count 0 2006.210.08:13:12.32#ibcon#*before return 0, iclass 37, count 0 2006.210.08:13:12.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:13:12.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:13:12.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:13:12.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:13:12.32$4f8m12a/ifd4f 2006.210.08:13:12.32$ifd4f/lo= 2006.210.08:13:12.32$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:13:12.32$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:13:12.32$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:13:12.32$ifd4f/patch= 2006.210.08:13:12.32$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:13:12.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:13:12.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:13:12.33$4f8m12a/"form=m,16.000,1:2 2006.210.08:13:12.33$4f8m12a/"tpicd 2006.210.08:13:12.33$4f8m12a/echo=off 2006.210.08:13:12.33$4f8m12a/xlog=off 2006.210.08:13:12.33:!2006.210.08:13:50 2006.210.08:13:31.14#trakl#Source acquired 2006.210.08:13:31.14#flagr#flagr/antenna,acquired 2006.210.08:13:50.01:preob 2006.210.08:13:51.13/onsource/TRACKING 2006.210.08:13:51.13:!2006.210.08:14:00 2006.210.08:14:00.00:data_valid=on 2006.210.08:14:00.00:midob 2006.210.08:14:00.13/onsource/TRACKING 2006.210.08:14:00.13/wx/30.03,1006.5,83 2006.210.08:14:00.26/cable/+6.3935E-03 2006.210.08:14:01.35/va/01,08,usb,yes,28,30 2006.210.08:14:01.35/va/02,07,usb,yes,28,30 2006.210.08:14:01.35/va/03,06,usb,yes,30,30 2006.210.08:14:01.35/va/04,07,usb,yes,29,31 2006.210.08:14:01.35/va/05,07,usb,yes,30,32 2006.210.08:14:01.35/va/06,06,usb,yes,29,29 2006.210.08:14:01.35/va/07,06,usb,yes,30,30 2006.210.08:14:01.35/va/08,07,usb,yes,28,28 2006.210.08:14:01.58/valo/01,532.99,yes,locked 2006.210.08:14:01.58/valo/02,572.99,yes,locked 2006.210.08:14:01.58/valo/03,672.99,yes,locked 2006.210.08:14:01.58/valo/04,832.99,yes,locked 2006.210.08:14:01.58/valo/05,652.99,yes,locked 2006.210.08:14:01.58/valo/06,772.99,yes,locked 2006.210.08:14:01.58/valo/07,832.99,yes,locked 2006.210.08:14:01.58/valo/08,852.99,yes,locked 2006.210.08:14:02.67/vb/01,04,usb,yes,28,27 2006.210.08:14:02.67/vb/02,04,usb,yes,30,31 2006.210.08:14:02.67/vb/03,03,usb,yes,33,37 2006.210.08:14:02.67/vb/04,03,usb,yes,34,34 2006.210.08:14:02.67/vb/05,03,usb,yes,32,36 2006.210.08:14:02.67/vb/06,03,usb,yes,33,36 2006.210.08:14:02.67/vb/07,04,usb,yes,29,28 2006.210.08:14:02.67/vb/08,03,usb,yes,33,36 2006.210.08:14:02.90/vblo/01,632.99,yes,locked 2006.210.08:14:02.90/vblo/02,640.99,yes,locked 2006.210.08:14:02.90/vblo/03,656.99,yes,locked 2006.210.08:14:02.90/vblo/04,712.99,yes,locked 2006.210.08:14:02.90/vblo/05,744.99,yes,locked 2006.210.08:14:02.90/vblo/06,752.99,yes,locked 2006.210.08:14:02.90/vblo/07,734.99,yes,locked 2006.210.08:14:02.90/vblo/08,744.99,yes,locked 2006.210.08:14:03.05/vabw/8 2006.210.08:14:03.20/vbbw/8 2006.210.08:14:03.29/xfe/off,on,12.7 2006.210.08:14:03.66/ifatt/23,28,28,28 2006.210.08:14:04.07/fmout-gps/S +4.59E-07 2006.210.08:14:04.11:!2006.210.08:15:00 2006.210.08:15:00.01:data_valid=off 2006.210.08:15:00.01:postob 2006.210.08:15:00.22/cable/+6.3930E-03 2006.210.08:15:00.22/wx/29.99,1006.4,83 2006.210.08:15:01.07/fmout-gps/S +4.56E-07 2006.210.08:15:01.07:scan_name=210-0815,k06210,60 2006.210.08:15:01.07:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.210.08:15:02.13#flagr#flagr/antenna,new-source 2006.210.08:15:02.13:checkk5 2006.210.08:15:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:15:02.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:15:03.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:15:03.52/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:15:03.85/chk_obsdata//k5ts1/T2100814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:15:04.19/chk_obsdata//k5ts2/T2100814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:15:04.53/chk_obsdata//k5ts3/T2100814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:15:04.86/chk_obsdata//k5ts4/T2100814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:15:05.54/k5log//k5ts1_log_newline 2006.210.08:15:06.20/k5log//k5ts2_log_newline 2006.210.08:15:06.86/k5log//k5ts3_log_newline 2006.210.08:15:07.53/k5log//k5ts4_log_newline 2006.210.08:15:07.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:15:07.55:4f8m12a=2 2006.210.08:15:07.55$4f8m12a/echo=on 2006.210.08:15:07.55$4f8m12a/pcalon 2006.210.08:15:07.55$pcalon/"no phase cal control is implemented here 2006.210.08:15:07.55$4f8m12a/"tpicd=stop 2006.210.08:15:07.55$4f8m12a/vc4f8 2006.210.08:15:07.55$vc4f8/valo=1,532.99 2006.210.08:15:07.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.08:15:07.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.08:15:07.55#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:07.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:07.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:07.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:07.55#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:15:07.55#ibcon#first serial, iclass 12, count 0 2006.210.08:15:07.55#ibcon#enter sib2, iclass 12, count 0 2006.210.08:15:07.55#ibcon#flushed, iclass 12, count 0 2006.210.08:15:07.55#ibcon#about to write, iclass 12, count 0 2006.210.08:15:07.55#ibcon#wrote, iclass 12, count 0 2006.210.08:15:07.56#ibcon#about to read 3, iclass 12, count 0 2006.210.08:15:07.57#ibcon#read 3, iclass 12, count 0 2006.210.08:15:07.57#ibcon#about to read 4, iclass 12, count 0 2006.210.08:15:07.57#ibcon#read 4, iclass 12, count 0 2006.210.08:15:07.57#ibcon#about to read 5, iclass 12, count 0 2006.210.08:15:07.57#ibcon#read 5, iclass 12, count 0 2006.210.08:15:07.57#ibcon#about to read 6, iclass 12, count 0 2006.210.08:15:07.57#ibcon#read 6, iclass 12, count 0 2006.210.08:15:07.57#ibcon#end of sib2, iclass 12, count 0 2006.210.08:15:07.57#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:15:07.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:15:07.57#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:15:07.57#ibcon#*before write, iclass 12, count 0 2006.210.08:15:07.57#ibcon#enter sib2, iclass 12, count 0 2006.210.08:15:07.57#ibcon#flushed, iclass 12, count 0 2006.210.08:15:07.57#ibcon#about to write, iclass 12, count 0 2006.210.08:15:07.57#ibcon#wrote, iclass 12, count 0 2006.210.08:15:07.57#ibcon#about to read 3, iclass 12, count 0 2006.210.08:15:07.62#ibcon#read 3, iclass 12, count 0 2006.210.08:15:07.62#ibcon#about to read 4, iclass 12, count 0 2006.210.08:15:07.62#ibcon#read 4, iclass 12, count 0 2006.210.08:15:07.62#ibcon#about to read 5, iclass 12, count 0 2006.210.08:15:07.62#ibcon#read 5, iclass 12, count 0 2006.210.08:15:07.62#ibcon#about to read 6, iclass 12, count 0 2006.210.08:15:07.62#ibcon#read 6, iclass 12, count 0 2006.210.08:15:07.62#ibcon#end of sib2, iclass 12, count 0 2006.210.08:15:07.62#ibcon#*after write, iclass 12, count 0 2006.210.08:15:07.62#ibcon#*before return 0, iclass 12, count 0 2006.210.08:15:07.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:07.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:07.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:15:07.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:15:07.62$vc4f8/va=1,8 2006.210.08:15:07.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.08:15:07.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.08:15:07.62#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:07.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:07.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:07.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:07.62#ibcon#enter wrdev, iclass 14, count 2 2006.210.08:15:07.62#ibcon#first serial, iclass 14, count 2 2006.210.08:15:07.62#ibcon#enter sib2, iclass 14, count 2 2006.210.08:15:07.62#ibcon#flushed, iclass 14, count 2 2006.210.08:15:07.62#ibcon#about to write, iclass 14, count 2 2006.210.08:15:07.62#ibcon#wrote, iclass 14, count 2 2006.210.08:15:07.62#ibcon#about to read 3, iclass 14, count 2 2006.210.08:15:07.64#ibcon#read 3, iclass 14, count 2 2006.210.08:15:07.64#ibcon#about to read 4, iclass 14, count 2 2006.210.08:15:07.64#ibcon#read 4, iclass 14, count 2 2006.210.08:15:07.64#ibcon#about to read 5, iclass 14, count 2 2006.210.08:15:07.64#ibcon#read 5, iclass 14, count 2 2006.210.08:15:07.64#ibcon#about to read 6, iclass 14, count 2 2006.210.08:15:07.64#ibcon#read 6, iclass 14, count 2 2006.210.08:15:07.64#ibcon#end of sib2, iclass 14, count 2 2006.210.08:15:07.64#ibcon#*mode == 0, iclass 14, count 2 2006.210.08:15:07.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.08:15:07.64#ibcon#[25=AT01-08\r\n] 2006.210.08:15:07.64#ibcon#*before write, iclass 14, count 2 2006.210.08:15:07.64#ibcon#enter sib2, iclass 14, count 2 2006.210.08:15:07.64#ibcon#flushed, iclass 14, count 2 2006.210.08:15:07.64#ibcon#about to write, iclass 14, count 2 2006.210.08:15:07.64#ibcon#wrote, iclass 14, count 2 2006.210.08:15:07.64#ibcon#about to read 3, iclass 14, count 2 2006.210.08:15:07.67#ibcon#read 3, iclass 14, count 2 2006.210.08:15:07.67#ibcon#about to read 4, iclass 14, count 2 2006.210.08:15:07.67#ibcon#read 4, iclass 14, count 2 2006.210.08:15:07.67#ibcon#about to read 5, iclass 14, count 2 2006.210.08:15:07.67#ibcon#read 5, iclass 14, count 2 2006.210.08:15:07.67#ibcon#about to read 6, iclass 14, count 2 2006.210.08:15:07.67#ibcon#read 6, iclass 14, count 2 2006.210.08:15:07.67#ibcon#end of sib2, iclass 14, count 2 2006.210.08:15:07.67#ibcon#*after write, iclass 14, count 2 2006.210.08:15:07.67#ibcon#*before return 0, iclass 14, count 2 2006.210.08:15:07.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:07.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:07.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.08:15:07.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:07.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:07.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:07.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:07.79#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:15:07.79#ibcon#first serial, iclass 14, count 0 2006.210.08:15:07.79#ibcon#enter sib2, iclass 14, count 0 2006.210.08:15:07.79#ibcon#flushed, iclass 14, count 0 2006.210.08:15:07.79#ibcon#about to write, iclass 14, count 0 2006.210.08:15:07.79#ibcon#wrote, iclass 14, count 0 2006.210.08:15:07.79#ibcon#about to read 3, iclass 14, count 0 2006.210.08:15:07.81#ibcon#read 3, iclass 14, count 0 2006.210.08:15:07.81#ibcon#about to read 4, iclass 14, count 0 2006.210.08:15:07.81#ibcon#read 4, iclass 14, count 0 2006.210.08:15:07.81#ibcon#about to read 5, iclass 14, count 0 2006.210.08:15:07.81#ibcon#read 5, iclass 14, count 0 2006.210.08:15:07.81#ibcon#about to read 6, iclass 14, count 0 2006.210.08:15:07.81#ibcon#read 6, iclass 14, count 0 2006.210.08:15:07.81#ibcon#end of sib2, iclass 14, count 0 2006.210.08:15:07.81#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:15:07.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:15:07.81#ibcon#[25=USB\r\n] 2006.210.08:15:07.81#ibcon#*before write, iclass 14, count 0 2006.210.08:15:07.81#ibcon#enter sib2, iclass 14, count 0 2006.210.08:15:07.81#ibcon#flushed, iclass 14, count 0 2006.210.08:15:07.81#ibcon#about to write, iclass 14, count 0 2006.210.08:15:07.81#ibcon#wrote, iclass 14, count 0 2006.210.08:15:07.81#ibcon#about to read 3, iclass 14, count 0 2006.210.08:15:07.84#ibcon#read 3, iclass 14, count 0 2006.210.08:15:07.84#ibcon#about to read 4, iclass 14, count 0 2006.210.08:15:07.84#ibcon#read 4, iclass 14, count 0 2006.210.08:15:07.84#ibcon#about to read 5, iclass 14, count 0 2006.210.08:15:07.84#ibcon#read 5, iclass 14, count 0 2006.210.08:15:07.84#ibcon#about to read 6, iclass 14, count 0 2006.210.08:15:07.84#ibcon#read 6, iclass 14, count 0 2006.210.08:15:07.84#ibcon#end of sib2, iclass 14, count 0 2006.210.08:15:07.84#ibcon#*after write, iclass 14, count 0 2006.210.08:15:07.84#ibcon#*before return 0, iclass 14, count 0 2006.210.08:15:07.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:07.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:07.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:15:07.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:15:07.84$vc4f8/valo=2,572.99 2006.210.08:15:07.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.08:15:07.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.08:15:07.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:07.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:07.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:07.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:07.84#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:15:07.84#ibcon#first serial, iclass 16, count 0 2006.210.08:15:07.84#ibcon#enter sib2, iclass 16, count 0 2006.210.08:15:07.84#ibcon#flushed, iclass 16, count 0 2006.210.08:15:07.84#ibcon#about to write, iclass 16, count 0 2006.210.08:15:07.84#ibcon#wrote, iclass 16, count 0 2006.210.08:15:07.84#ibcon#about to read 3, iclass 16, count 0 2006.210.08:15:07.86#ibcon#read 3, iclass 16, count 0 2006.210.08:15:07.86#ibcon#about to read 4, iclass 16, count 0 2006.210.08:15:07.86#ibcon#read 4, iclass 16, count 0 2006.210.08:15:07.86#ibcon#about to read 5, iclass 16, count 0 2006.210.08:15:07.86#ibcon#read 5, iclass 16, count 0 2006.210.08:15:07.86#ibcon#about to read 6, iclass 16, count 0 2006.210.08:15:07.86#ibcon#read 6, iclass 16, count 0 2006.210.08:15:07.86#ibcon#end of sib2, iclass 16, count 0 2006.210.08:15:07.86#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:15:07.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:15:07.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:15:07.86#ibcon#*before write, iclass 16, count 0 2006.210.08:15:07.86#ibcon#enter sib2, iclass 16, count 0 2006.210.08:15:07.86#ibcon#flushed, iclass 16, count 0 2006.210.08:15:07.86#ibcon#about to write, iclass 16, count 0 2006.210.08:15:07.86#ibcon#wrote, iclass 16, count 0 2006.210.08:15:07.86#ibcon#about to read 3, iclass 16, count 0 2006.210.08:15:07.90#ibcon#read 3, iclass 16, count 0 2006.210.08:15:07.90#ibcon#about to read 4, iclass 16, count 0 2006.210.08:15:07.90#ibcon#read 4, iclass 16, count 0 2006.210.08:15:07.90#ibcon#about to read 5, iclass 16, count 0 2006.210.08:15:07.90#ibcon#read 5, iclass 16, count 0 2006.210.08:15:07.90#ibcon#about to read 6, iclass 16, count 0 2006.210.08:15:07.90#ibcon#read 6, iclass 16, count 0 2006.210.08:15:07.90#ibcon#end of sib2, iclass 16, count 0 2006.210.08:15:07.90#ibcon#*after write, iclass 16, count 0 2006.210.08:15:07.90#ibcon#*before return 0, iclass 16, count 0 2006.210.08:15:07.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:07.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:07.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:15:07.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:15:07.90$vc4f8/va=2,7 2006.210.08:15:07.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.08:15:07.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.08:15:07.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:07.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:07.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:07.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:07.96#ibcon#enter wrdev, iclass 18, count 2 2006.210.08:15:07.96#ibcon#first serial, iclass 18, count 2 2006.210.08:15:07.96#ibcon#enter sib2, iclass 18, count 2 2006.210.08:15:07.96#ibcon#flushed, iclass 18, count 2 2006.210.08:15:07.96#ibcon#about to write, iclass 18, count 2 2006.210.08:15:07.96#ibcon#wrote, iclass 18, count 2 2006.210.08:15:07.96#ibcon#about to read 3, iclass 18, count 2 2006.210.08:15:07.98#ibcon#read 3, iclass 18, count 2 2006.210.08:15:07.98#ibcon#about to read 4, iclass 18, count 2 2006.210.08:15:07.98#ibcon#read 4, iclass 18, count 2 2006.210.08:15:07.98#ibcon#about to read 5, iclass 18, count 2 2006.210.08:15:07.98#ibcon#read 5, iclass 18, count 2 2006.210.08:15:07.98#ibcon#about to read 6, iclass 18, count 2 2006.210.08:15:07.98#ibcon#read 6, iclass 18, count 2 2006.210.08:15:07.98#ibcon#end of sib2, iclass 18, count 2 2006.210.08:15:07.98#ibcon#*mode == 0, iclass 18, count 2 2006.210.08:15:07.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.08:15:07.98#ibcon#[25=AT02-07\r\n] 2006.210.08:15:07.98#ibcon#*before write, iclass 18, count 2 2006.210.08:15:07.98#ibcon#enter sib2, iclass 18, count 2 2006.210.08:15:07.98#ibcon#flushed, iclass 18, count 2 2006.210.08:15:07.98#ibcon#about to write, iclass 18, count 2 2006.210.08:15:07.98#ibcon#wrote, iclass 18, count 2 2006.210.08:15:07.98#ibcon#about to read 3, iclass 18, count 2 2006.210.08:15:08.01#ibcon#read 3, iclass 18, count 2 2006.210.08:15:08.01#ibcon#about to read 4, iclass 18, count 2 2006.210.08:15:08.01#ibcon#read 4, iclass 18, count 2 2006.210.08:15:08.01#ibcon#about to read 5, iclass 18, count 2 2006.210.08:15:08.01#ibcon#read 5, iclass 18, count 2 2006.210.08:15:08.01#ibcon#about to read 6, iclass 18, count 2 2006.210.08:15:08.01#ibcon#read 6, iclass 18, count 2 2006.210.08:15:08.01#ibcon#end of sib2, iclass 18, count 2 2006.210.08:15:08.01#ibcon#*after write, iclass 18, count 2 2006.210.08:15:08.01#ibcon#*before return 0, iclass 18, count 2 2006.210.08:15:08.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:08.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:08.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.08:15:08.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:08.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:08.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:08.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:08.13#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:15:08.13#ibcon#first serial, iclass 18, count 0 2006.210.08:15:08.13#ibcon#enter sib2, iclass 18, count 0 2006.210.08:15:08.13#ibcon#flushed, iclass 18, count 0 2006.210.08:15:08.13#ibcon#about to write, iclass 18, count 0 2006.210.08:15:08.13#ibcon#wrote, iclass 18, count 0 2006.210.08:15:08.13#ibcon#about to read 3, iclass 18, count 0 2006.210.08:15:08.15#ibcon#read 3, iclass 18, count 0 2006.210.08:15:08.15#ibcon#about to read 4, iclass 18, count 0 2006.210.08:15:08.15#ibcon#read 4, iclass 18, count 0 2006.210.08:15:08.15#ibcon#about to read 5, iclass 18, count 0 2006.210.08:15:08.15#ibcon#read 5, iclass 18, count 0 2006.210.08:15:08.15#ibcon#about to read 6, iclass 18, count 0 2006.210.08:15:08.15#ibcon#read 6, iclass 18, count 0 2006.210.08:15:08.15#ibcon#end of sib2, iclass 18, count 0 2006.210.08:15:08.15#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:15:08.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:15:08.15#ibcon#[25=USB\r\n] 2006.210.08:15:08.15#ibcon#*before write, iclass 18, count 0 2006.210.08:15:08.15#ibcon#enter sib2, iclass 18, count 0 2006.210.08:15:08.15#ibcon#flushed, iclass 18, count 0 2006.210.08:15:08.15#ibcon#about to write, iclass 18, count 0 2006.210.08:15:08.15#ibcon#wrote, iclass 18, count 0 2006.210.08:15:08.15#ibcon#about to read 3, iclass 18, count 0 2006.210.08:15:08.18#ibcon#read 3, iclass 18, count 0 2006.210.08:15:08.18#ibcon#about to read 4, iclass 18, count 0 2006.210.08:15:08.18#ibcon#read 4, iclass 18, count 0 2006.210.08:15:08.18#ibcon#about to read 5, iclass 18, count 0 2006.210.08:15:08.18#ibcon#read 5, iclass 18, count 0 2006.210.08:15:08.18#ibcon#about to read 6, iclass 18, count 0 2006.210.08:15:08.18#ibcon#read 6, iclass 18, count 0 2006.210.08:15:08.18#ibcon#end of sib2, iclass 18, count 0 2006.210.08:15:08.18#ibcon#*after write, iclass 18, count 0 2006.210.08:15:08.18#ibcon#*before return 0, iclass 18, count 0 2006.210.08:15:08.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:08.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:08.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:15:08.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:15:08.18$vc4f8/valo=3,672.99 2006.210.08:15:08.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.08:15:08.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.08:15:08.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:08.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:08.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:08.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:08.18#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:15:08.18#ibcon#first serial, iclass 20, count 0 2006.210.08:15:08.18#ibcon#enter sib2, iclass 20, count 0 2006.210.08:15:08.18#ibcon#flushed, iclass 20, count 0 2006.210.08:15:08.18#ibcon#about to write, iclass 20, count 0 2006.210.08:15:08.18#ibcon#wrote, iclass 20, count 0 2006.210.08:15:08.18#ibcon#about to read 3, iclass 20, count 0 2006.210.08:15:08.20#ibcon#read 3, iclass 20, count 0 2006.210.08:15:08.20#ibcon#about to read 4, iclass 20, count 0 2006.210.08:15:08.20#ibcon#read 4, iclass 20, count 0 2006.210.08:15:08.20#ibcon#about to read 5, iclass 20, count 0 2006.210.08:15:08.20#ibcon#read 5, iclass 20, count 0 2006.210.08:15:08.20#ibcon#about to read 6, iclass 20, count 0 2006.210.08:15:08.20#ibcon#read 6, iclass 20, count 0 2006.210.08:15:08.20#ibcon#end of sib2, iclass 20, count 0 2006.210.08:15:08.20#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:15:08.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:15:08.20#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:15:08.20#ibcon#*before write, iclass 20, count 0 2006.210.08:15:08.20#ibcon#enter sib2, iclass 20, count 0 2006.210.08:15:08.20#ibcon#flushed, iclass 20, count 0 2006.210.08:15:08.20#ibcon#about to write, iclass 20, count 0 2006.210.08:15:08.20#ibcon#wrote, iclass 20, count 0 2006.210.08:15:08.20#ibcon#about to read 3, iclass 20, count 0 2006.210.08:15:08.24#ibcon#read 3, iclass 20, count 0 2006.210.08:15:08.24#ibcon#about to read 4, iclass 20, count 0 2006.210.08:15:08.24#ibcon#read 4, iclass 20, count 0 2006.210.08:15:08.24#ibcon#about to read 5, iclass 20, count 0 2006.210.08:15:08.24#ibcon#read 5, iclass 20, count 0 2006.210.08:15:08.24#ibcon#about to read 6, iclass 20, count 0 2006.210.08:15:08.24#ibcon#read 6, iclass 20, count 0 2006.210.08:15:08.24#ibcon#end of sib2, iclass 20, count 0 2006.210.08:15:08.24#ibcon#*after write, iclass 20, count 0 2006.210.08:15:08.24#ibcon#*before return 0, iclass 20, count 0 2006.210.08:15:08.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:08.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:08.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:15:08.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:15:08.24$vc4f8/va=3,6 2006.210.08:15:08.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.08:15:08.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.08:15:08.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:08.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:08.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:08.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:08.30#ibcon#enter wrdev, iclass 22, count 2 2006.210.08:15:08.30#ibcon#first serial, iclass 22, count 2 2006.210.08:15:08.30#ibcon#enter sib2, iclass 22, count 2 2006.210.08:15:08.30#ibcon#flushed, iclass 22, count 2 2006.210.08:15:08.30#ibcon#about to write, iclass 22, count 2 2006.210.08:15:08.30#ibcon#wrote, iclass 22, count 2 2006.210.08:15:08.30#ibcon#about to read 3, iclass 22, count 2 2006.210.08:15:08.32#ibcon#read 3, iclass 22, count 2 2006.210.08:15:08.32#ibcon#about to read 4, iclass 22, count 2 2006.210.08:15:08.32#ibcon#read 4, iclass 22, count 2 2006.210.08:15:08.32#ibcon#about to read 5, iclass 22, count 2 2006.210.08:15:08.32#ibcon#read 5, iclass 22, count 2 2006.210.08:15:08.32#ibcon#about to read 6, iclass 22, count 2 2006.210.08:15:08.32#ibcon#read 6, iclass 22, count 2 2006.210.08:15:08.32#ibcon#end of sib2, iclass 22, count 2 2006.210.08:15:08.32#ibcon#*mode == 0, iclass 22, count 2 2006.210.08:15:08.32#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.08:15:08.32#ibcon#[25=AT03-06\r\n] 2006.210.08:15:08.32#ibcon#*before write, iclass 22, count 2 2006.210.08:15:08.32#ibcon#enter sib2, iclass 22, count 2 2006.210.08:15:08.32#ibcon#flushed, iclass 22, count 2 2006.210.08:15:08.32#ibcon#about to write, iclass 22, count 2 2006.210.08:15:08.32#ibcon#wrote, iclass 22, count 2 2006.210.08:15:08.32#ibcon#about to read 3, iclass 22, count 2 2006.210.08:15:08.35#ibcon#read 3, iclass 22, count 2 2006.210.08:15:08.35#ibcon#about to read 4, iclass 22, count 2 2006.210.08:15:08.35#ibcon#read 4, iclass 22, count 2 2006.210.08:15:08.35#ibcon#about to read 5, iclass 22, count 2 2006.210.08:15:08.35#ibcon#read 5, iclass 22, count 2 2006.210.08:15:08.35#ibcon#about to read 6, iclass 22, count 2 2006.210.08:15:08.35#ibcon#read 6, iclass 22, count 2 2006.210.08:15:08.35#ibcon#end of sib2, iclass 22, count 2 2006.210.08:15:08.35#ibcon#*after write, iclass 22, count 2 2006.210.08:15:08.35#ibcon#*before return 0, iclass 22, count 2 2006.210.08:15:08.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:08.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:08.35#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.08:15:08.35#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:08.35#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:08.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:08.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:08.47#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:15:08.47#ibcon#first serial, iclass 22, count 0 2006.210.08:15:08.47#ibcon#enter sib2, iclass 22, count 0 2006.210.08:15:08.47#ibcon#flushed, iclass 22, count 0 2006.210.08:15:08.47#ibcon#about to write, iclass 22, count 0 2006.210.08:15:08.47#ibcon#wrote, iclass 22, count 0 2006.210.08:15:08.47#ibcon#about to read 3, iclass 22, count 0 2006.210.08:15:08.49#ibcon#read 3, iclass 22, count 0 2006.210.08:15:08.49#ibcon#about to read 4, iclass 22, count 0 2006.210.08:15:08.49#ibcon#read 4, iclass 22, count 0 2006.210.08:15:08.49#ibcon#about to read 5, iclass 22, count 0 2006.210.08:15:08.49#ibcon#read 5, iclass 22, count 0 2006.210.08:15:08.49#ibcon#about to read 6, iclass 22, count 0 2006.210.08:15:08.49#ibcon#read 6, iclass 22, count 0 2006.210.08:15:08.49#ibcon#end of sib2, iclass 22, count 0 2006.210.08:15:08.49#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:15:08.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:15:08.49#ibcon#[25=USB\r\n] 2006.210.08:15:08.49#ibcon#*before write, iclass 22, count 0 2006.210.08:15:08.49#ibcon#enter sib2, iclass 22, count 0 2006.210.08:15:08.49#ibcon#flushed, iclass 22, count 0 2006.210.08:15:08.49#ibcon#about to write, iclass 22, count 0 2006.210.08:15:08.49#ibcon#wrote, iclass 22, count 0 2006.210.08:15:08.49#ibcon#about to read 3, iclass 22, count 0 2006.210.08:15:08.52#ibcon#read 3, iclass 22, count 0 2006.210.08:15:08.52#ibcon#about to read 4, iclass 22, count 0 2006.210.08:15:08.52#ibcon#read 4, iclass 22, count 0 2006.210.08:15:08.52#ibcon#about to read 5, iclass 22, count 0 2006.210.08:15:08.52#ibcon#read 5, iclass 22, count 0 2006.210.08:15:08.52#ibcon#about to read 6, iclass 22, count 0 2006.210.08:15:08.52#ibcon#read 6, iclass 22, count 0 2006.210.08:15:08.52#ibcon#end of sib2, iclass 22, count 0 2006.210.08:15:08.52#ibcon#*after write, iclass 22, count 0 2006.210.08:15:08.52#ibcon#*before return 0, iclass 22, count 0 2006.210.08:15:08.52#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:08.52#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:08.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:15:08.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:15:08.52$vc4f8/valo=4,832.99 2006.210.08:15:08.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.08:15:08.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.08:15:08.52#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:08.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:08.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:08.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:08.52#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:15:08.52#ibcon#first serial, iclass 24, count 0 2006.210.08:15:08.52#ibcon#enter sib2, iclass 24, count 0 2006.210.08:15:08.52#ibcon#flushed, iclass 24, count 0 2006.210.08:15:08.52#ibcon#about to write, iclass 24, count 0 2006.210.08:15:08.52#ibcon#wrote, iclass 24, count 0 2006.210.08:15:08.52#ibcon#about to read 3, iclass 24, count 0 2006.210.08:15:08.54#ibcon#read 3, iclass 24, count 0 2006.210.08:15:08.54#ibcon#about to read 4, iclass 24, count 0 2006.210.08:15:08.54#ibcon#read 4, iclass 24, count 0 2006.210.08:15:08.54#ibcon#about to read 5, iclass 24, count 0 2006.210.08:15:08.54#ibcon#read 5, iclass 24, count 0 2006.210.08:15:08.54#ibcon#about to read 6, iclass 24, count 0 2006.210.08:15:08.54#ibcon#read 6, iclass 24, count 0 2006.210.08:15:08.54#ibcon#end of sib2, iclass 24, count 0 2006.210.08:15:08.54#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:15:08.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:15:08.54#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:15:08.54#ibcon#*before write, iclass 24, count 0 2006.210.08:15:08.54#ibcon#enter sib2, iclass 24, count 0 2006.210.08:15:08.54#ibcon#flushed, iclass 24, count 0 2006.210.08:15:08.54#ibcon#about to write, iclass 24, count 0 2006.210.08:15:08.54#ibcon#wrote, iclass 24, count 0 2006.210.08:15:08.54#ibcon#about to read 3, iclass 24, count 0 2006.210.08:15:08.58#ibcon#read 3, iclass 24, count 0 2006.210.08:15:08.58#ibcon#about to read 4, iclass 24, count 0 2006.210.08:15:08.58#ibcon#read 4, iclass 24, count 0 2006.210.08:15:08.58#ibcon#about to read 5, iclass 24, count 0 2006.210.08:15:08.58#ibcon#read 5, iclass 24, count 0 2006.210.08:15:08.58#ibcon#about to read 6, iclass 24, count 0 2006.210.08:15:08.58#ibcon#read 6, iclass 24, count 0 2006.210.08:15:08.58#ibcon#end of sib2, iclass 24, count 0 2006.210.08:15:08.58#ibcon#*after write, iclass 24, count 0 2006.210.08:15:08.58#ibcon#*before return 0, iclass 24, count 0 2006.210.08:15:08.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:08.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:08.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:15:08.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:15:08.58$vc4f8/va=4,7 2006.210.08:15:08.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.08:15:08.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.08:15:08.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:08.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:08.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:08.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:08.64#ibcon#enter wrdev, iclass 26, count 2 2006.210.08:15:08.64#ibcon#first serial, iclass 26, count 2 2006.210.08:15:08.64#ibcon#enter sib2, iclass 26, count 2 2006.210.08:15:08.64#ibcon#flushed, iclass 26, count 2 2006.210.08:15:08.64#ibcon#about to write, iclass 26, count 2 2006.210.08:15:08.64#ibcon#wrote, iclass 26, count 2 2006.210.08:15:08.64#ibcon#about to read 3, iclass 26, count 2 2006.210.08:15:08.66#ibcon#read 3, iclass 26, count 2 2006.210.08:15:08.66#ibcon#about to read 4, iclass 26, count 2 2006.210.08:15:08.66#ibcon#read 4, iclass 26, count 2 2006.210.08:15:08.66#ibcon#about to read 5, iclass 26, count 2 2006.210.08:15:08.66#ibcon#read 5, iclass 26, count 2 2006.210.08:15:08.66#ibcon#about to read 6, iclass 26, count 2 2006.210.08:15:08.66#ibcon#read 6, iclass 26, count 2 2006.210.08:15:08.66#ibcon#end of sib2, iclass 26, count 2 2006.210.08:15:08.66#ibcon#*mode == 0, iclass 26, count 2 2006.210.08:15:08.66#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.08:15:08.66#ibcon#[25=AT04-07\r\n] 2006.210.08:15:08.66#ibcon#*before write, iclass 26, count 2 2006.210.08:15:08.66#ibcon#enter sib2, iclass 26, count 2 2006.210.08:15:08.66#ibcon#flushed, iclass 26, count 2 2006.210.08:15:08.66#ibcon#about to write, iclass 26, count 2 2006.210.08:15:08.66#ibcon#wrote, iclass 26, count 2 2006.210.08:15:08.66#ibcon#about to read 3, iclass 26, count 2 2006.210.08:15:08.69#ibcon#read 3, iclass 26, count 2 2006.210.08:15:08.69#ibcon#about to read 4, iclass 26, count 2 2006.210.08:15:08.69#ibcon#read 4, iclass 26, count 2 2006.210.08:15:08.69#ibcon#about to read 5, iclass 26, count 2 2006.210.08:15:08.69#ibcon#read 5, iclass 26, count 2 2006.210.08:15:08.69#ibcon#about to read 6, iclass 26, count 2 2006.210.08:15:08.69#ibcon#read 6, iclass 26, count 2 2006.210.08:15:08.69#ibcon#end of sib2, iclass 26, count 2 2006.210.08:15:08.69#ibcon#*after write, iclass 26, count 2 2006.210.08:15:08.69#ibcon#*before return 0, iclass 26, count 2 2006.210.08:15:08.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:08.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:08.69#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.08:15:08.69#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:08.69#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:08.81#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:08.81#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:08.81#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:15:08.81#ibcon#first serial, iclass 26, count 0 2006.210.08:15:08.81#ibcon#enter sib2, iclass 26, count 0 2006.210.08:15:08.81#ibcon#flushed, iclass 26, count 0 2006.210.08:15:08.81#ibcon#about to write, iclass 26, count 0 2006.210.08:15:08.81#ibcon#wrote, iclass 26, count 0 2006.210.08:15:08.81#ibcon#about to read 3, iclass 26, count 0 2006.210.08:15:08.83#ibcon#read 3, iclass 26, count 0 2006.210.08:15:08.83#ibcon#about to read 4, iclass 26, count 0 2006.210.08:15:08.83#ibcon#read 4, iclass 26, count 0 2006.210.08:15:08.83#ibcon#about to read 5, iclass 26, count 0 2006.210.08:15:08.83#ibcon#read 5, iclass 26, count 0 2006.210.08:15:08.83#ibcon#about to read 6, iclass 26, count 0 2006.210.08:15:08.83#ibcon#read 6, iclass 26, count 0 2006.210.08:15:08.83#ibcon#end of sib2, iclass 26, count 0 2006.210.08:15:08.83#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:15:08.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:15:08.83#ibcon#[25=USB\r\n] 2006.210.08:15:08.83#ibcon#*before write, iclass 26, count 0 2006.210.08:15:08.83#ibcon#enter sib2, iclass 26, count 0 2006.210.08:15:08.83#ibcon#flushed, iclass 26, count 0 2006.210.08:15:08.83#ibcon#about to write, iclass 26, count 0 2006.210.08:15:08.83#ibcon#wrote, iclass 26, count 0 2006.210.08:15:08.83#ibcon#about to read 3, iclass 26, count 0 2006.210.08:15:08.86#ibcon#read 3, iclass 26, count 0 2006.210.08:15:08.86#ibcon#about to read 4, iclass 26, count 0 2006.210.08:15:08.86#ibcon#read 4, iclass 26, count 0 2006.210.08:15:08.86#ibcon#about to read 5, iclass 26, count 0 2006.210.08:15:08.86#ibcon#read 5, iclass 26, count 0 2006.210.08:15:08.86#ibcon#about to read 6, iclass 26, count 0 2006.210.08:15:08.86#ibcon#read 6, iclass 26, count 0 2006.210.08:15:08.86#ibcon#end of sib2, iclass 26, count 0 2006.210.08:15:08.86#ibcon#*after write, iclass 26, count 0 2006.210.08:15:08.86#ibcon#*before return 0, iclass 26, count 0 2006.210.08:15:08.86#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:08.86#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:08.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:15:08.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:15:08.86$vc4f8/valo=5,652.99 2006.210.08:15:08.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.08:15:08.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.08:15:08.86#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:08.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:08.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:08.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:08.86#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:15:08.86#ibcon#first serial, iclass 28, count 0 2006.210.08:15:08.86#ibcon#enter sib2, iclass 28, count 0 2006.210.08:15:08.86#ibcon#flushed, iclass 28, count 0 2006.210.08:15:08.86#ibcon#about to write, iclass 28, count 0 2006.210.08:15:08.86#ibcon#wrote, iclass 28, count 0 2006.210.08:15:08.86#ibcon#about to read 3, iclass 28, count 0 2006.210.08:15:08.88#ibcon#read 3, iclass 28, count 0 2006.210.08:15:08.88#ibcon#about to read 4, iclass 28, count 0 2006.210.08:15:08.88#ibcon#read 4, iclass 28, count 0 2006.210.08:15:08.88#ibcon#about to read 5, iclass 28, count 0 2006.210.08:15:08.88#ibcon#read 5, iclass 28, count 0 2006.210.08:15:08.88#ibcon#about to read 6, iclass 28, count 0 2006.210.08:15:08.88#ibcon#read 6, iclass 28, count 0 2006.210.08:15:08.88#ibcon#end of sib2, iclass 28, count 0 2006.210.08:15:08.88#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:15:08.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:15:08.88#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:15:08.88#ibcon#*before write, iclass 28, count 0 2006.210.08:15:08.88#ibcon#enter sib2, iclass 28, count 0 2006.210.08:15:08.88#ibcon#flushed, iclass 28, count 0 2006.210.08:15:08.88#ibcon#about to write, iclass 28, count 0 2006.210.08:15:08.88#ibcon#wrote, iclass 28, count 0 2006.210.08:15:08.88#ibcon#about to read 3, iclass 28, count 0 2006.210.08:15:08.92#ibcon#read 3, iclass 28, count 0 2006.210.08:15:08.92#ibcon#about to read 4, iclass 28, count 0 2006.210.08:15:08.92#ibcon#read 4, iclass 28, count 0 2006.210.08:15:08.92#ibcon#about to read 5, iclass 28, count 0 2006.210.08:15:08.92#ibcon#read 5, iclass 28, count 0 2006.210.08:15:08.92#ibcon#about to read 6, iclass 28, count 0 2006.210.08:15:08.92#ibcon#read 6, iclass 28, count 0 2006.210.08:15:08.92#ibcon#end of sib2, iclass 28, count 0 2006.210.08:15:08.92#ibcon#*after write, iclass 28, count 0 2006.210.08:15:08.92#ibcon#*before return 0, iclass 28, count 0 2006.210.08:15:08.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:08.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:08.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:15:08.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:15:08.92$vc4f8/va=5,7 2006.210.08:15:08.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.08:15:08.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.08:15:08.92#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:08.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:08.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:08.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:08.98#ibcon#enter wrdev, iclass 30, count 2 2006.210.08:15:08.98#ibcon#first serial, iclass 30, count 2 2006.210.08:15:08.98#ibcon#enter sib2, iclass 30, count 2 2006.210.08:15:08.98#ibcon#flushed, iclass 30, count 2 2006.210.08:15:08.98#ibcon#about to write, iclass 30, count 2 2006.210.08:15:08.98#ibcon#wrote, iclass 30, count 2 2006.210.08:15:08.98#ibcon#about to read 3, iclass 30, count 2 2006.210.08:15:09.00#ibcon#read 3, iclass 30, count 2 2006.210.08:15:09.00#ibcon#about to read 4, iclass 30, count 2 2006.210.08:15:09.00#ibcon#read 4, iclass 30, count 2 2006.210.08:15:09.00#ibcon#about to read 5, iclass 30, count 2 2006.210.08:15:09.00#ibcon#read 5, iclass 30, count 2 2006.210.08:15:09.00#ibcon#about to read 6, iclass 30, count 2 2006.210.08:15:09.00#ibcon#read 6, iclass 30, count 2 2006.210.08:15:09.00#ibcon#end of sib2, iclass 30, count 2 2006.210.08:15:09.00#ibcon#*mode == 0, iclass 30, count 2 2006.210.08:15:09.00#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.08:15:09.00#ibcon#[25=AT05-07\r\n] 2006.210.08:15:09.00#ibcon#*before write, iclass 30, count 2 2006.210.08:15:09.00#ibcon#enter sib2, iclass 30, count 2 2006.210.08:15:09.00#ibcon#flushed, iclass 30, count 2 2006.210.08:15:09.00#ibcon#about to write, iclass 30, count 2 2006.210.08:15:09.00#ibcon#wrote, iclass 30, count 2 2006.210.08:15:09.00#ibcon#about to read 3, iclass 30, count 2 2006.210.08:15:09.03#ibcon#read 3, iclass 30, count 2 2006.210.08:15:09.03#ibcon#about to read 4, iclass 30, count 2 2006.210.08:15:09.03#ibcon#read 4, iclass 30, count 2 2006.210.08:15:09.03#ibcon#about to read 5, iclass 30, count 2 2006.210.08:15:09.03#ibcon#read 5, iclass 30, count 2 2006.210.08:15:09.03#ibcon#about to read 6, iclass 30, count 2 2006.210.08:15:09.03#ibcon#read 6, iclass 30, count 2 2006.210.08:15:09.03#ibcon#end of sib2, iclass 30, count 2 2006.210.08:15:09.03#ibcon#*after write, iclass 30, count 2 2006.210.08:15:09.03#ibcon#*before return 0, iclass 30, count 2 2006.210.08:15:09.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:09.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:09.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.08:15:09.03#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:09.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:09.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:09.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:09.15#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:15:09.15#ibcon#first serial, iclass 30, count 0 2006.210.08:15:09.15#ibcon#enter sib2, iclass 30, count 0 2006.210.08:15:09.15#ibcon#flushed, iclass 30, count 0 2006.210.08:15:09.15#ibcon#about to write, iclass 30, count 0 2006.210.08:15:09.15#ibcon#wrote, iclass 30, count 0 2006.210.08:15:09.15#ibcon#about to read 3, iclass 30, count 0 2006.210.08:15:09.17#ibcon#read 3, iclass 30, count 0 2006.210.08:15:09.17#ibcon#about to read 4, iclass 30, count 0 2006.210.08:15:09.17#ibcon#read 4, iclass 30, count 0 2006.210.08:15:09.17#ibcon#about to read 5, iclass 30, count 0 2006.210.08:15:09.17#ibcon#read 5, iclass 30, count 0 2006.210.08:15:09.17#ibcon#about to read 6, iclass 30, count 0 2006.210.08:15:09.17#ibcon#read 6, iclass 30, count 0 2006.210.08:15:09.17#ibcon#end of sib2, iclass 30, count 0 2006.210.08:15:09.17#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:15:09.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:15:09.17#ibcon#[25=USB\r\n] 2006.210.08:15:09.17#ibcon#*before write, iclass 30, count 0 2006.210.08:15:09.17#ibcon#enter sib2, iclass 30, count 0 2006.210.08:15:09.17#ibcon#flushed, iclass 30, count 0 2006.210.08:15:09.17#ibcon#about to write, iclass 30, count 0 2006.210.08:15:09.17#ibcon#wrote, iclass 30, count 0 2006.210.08:15:09.17#ibcon#about to read 3, iclass 30, count 0 2006.210.08:15:09.20#ibcon#read 3, iclass 30, count 0 2006.210.08:15:09.20#ibcon#about to read 4, iclass 30, count 0 2006.210.08:15:09.20#ibcon#read 4, iclass 30, count 0 2006.210.08:15:09.20#ibcon#about to read 5, iclass 30, count 0 2006.210.08:15:09.20#ibcon#read 5, iclass 30, count 0 2006.210.08:15:09.20#ibcon#about to read 6, iclass 30, count 0 2006.210.08:15:09.20#ibcon#read 6, iclass 30, count 0 2006.210.08:15:09.20#ibcon#end of sib2, iclass 30, count 0 2006.210.08:15:09.20#ibcon#*after write, iclass 30, count 0 2006.210.08:15:09.20#ibcon#*before return 0, iclass 30, count 0 2006.210.08:15:09.20#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:09.20#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:09.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:15:09.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:15:09.20$vc4f8/valo=6,772.99 2006.210.08:15:09.20#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.08:15:09.20#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.08:15:09.20#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:09.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:09.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:09.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:09.20#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:15:09.20#ibcon#first serial, iclass 32, count 0 2006.210.08:15:09.20#ibcon#enter sib2, iclass 32, count 0 2006.210.08:15:09.20#ibcon#flushed, iclass 32, count 0 2006.210.08:15:09.20#ibcon#about to write, iclass 32, count 0 2006.210.08:15:09.20#ibcon#wrote, iclass 32, count 0 2006.210.08:15:09.20#ibcon#about to read 3, iclass 32, count 0 2006.210.08:15:09.22#ibcon#read 3, iclass 32, count 0 2006.210.08:15:09.22#ibcon#about to read 4, iclass 32, count 0 2006.210.08:15:09.22#ibcon#read 4, iclass 32, count 0 2006.210.08:15:09.22#ibcon#about to read 5, iclass 32, count 0 2006.210.08:15:09.22#ibcon#read 5, iclass 32, count 0 2006.210.08:15:09.22#ibcon#about to read 6, iclass 32, count 0 2006.210.08:15:09.22#ibcon#read 6, iclass 32, count 0 2006.210.08:15:09.22#ibcon#end of sib2, iclass 32, count 0 2006.210.08:15:09.22#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:15:09.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:15:09.22#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:15:09.22#ibcon#*before write, iclass 32, count 0 2006.210.08:15:09.22#ibcon#enter sib2, iclass 32, count 0 2006.210.08:15:09.22#ibcon#flushed, iclass 32, count 0 2006.210.08:15:09.22#ibcon#about to write, iclass 32, count 0 2006.210.08:15:09.22#ibcon#wrote, iclass 32, count 0 2006.210.08:15:09.22#ibcon#about to read 3, iclass 32, count 0 2006.210.08:15:09.26#ibcon#read 3, iclass 32, count 0 2006.210.08:15:09.26#ibcon#about to read 4, iclass 32, count 0 2006.210.08:15:09.26#ibcon#read 4, iclass 32, count 0 2006.210.08:15:09.26#ibcon#about to read 5, iclass 32, count 0 2006.210.08:15:09.26#ibcon#read 5, iclass 32, count 0 2006.210.08:15:09.26#ibcon#about to read 6, iclass 32, count 0 2006.210.08:15:09.26#ibcon#read 6, iclass 32, count 0 2006.210.08:15:09.26#ibcon#end of sib2, iclass 32, count 0 2006.210.08:15:09.26#ibcon#*after write, iclass 32, count 0 2006.210.08:15:09.26#ibcon#*before return 0, iclass 32, count 0 2006.210.08:15:09.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:09.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:09.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:15:09.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:15:09.26$vc4f8/va=6,6 2006.210.08:15:09.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.210.08:15:09.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.210.08:15:09.26#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:09.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:15:09.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:15:09.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:15:09.32#ibcon#enter wrdev, iclass 34, count 2 2006.210.08:15:09.32#ibcon#first serial, iclass 34, count 2 2006.210.08:15:09.32#ibcon#enter sib2, iclass 34, count 2 2006.210.08:15:09.32#ibcon#flushed, iclass 34, count 2 2006.210.08:15:09.32#ibcon#about to write, iclass 34, count 2 2006.210.08:15:09.32#ibcon#wrote, iclass 34, count 2 2006.210.08:15:09.32#ibcon#about to read 3, iclass 34, count 2 2006.210.08:15:09.34#ibcon#read 3, iclass 34, count 2 2006.210.08:15:09.34#ibcon#about to read 4, iclass 34, count 2 2006.210.08:15:09.34#ibcon#read 4, iclass 34, count 2 2006.210.08:15:09.34#ibcon#about to read 5, iclass 34, count 2 2006.210.08:15:09.34#ibcon#read 5, iclass 34, count 2 2006.210.08:15:09.34#ibcon#about to read 6, iclass 34, count 2 2006.210.08:15:09.34#ibcon#read 6, iclass 34, count 2 2006.210.08:15:09.34#ibcon#end of sib2, iclass 34, count 2 2006.210.08:15:09.34#ibcon#*mode == 0, iclass 34, count 2 2006.210.08:15:09.34#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.210.08:15:09.34#ibcon#[25=AT06-06\r\n] 2006.210.08:15:09.34#ibcon#*before write, iclass 34, count 2 2006.210.08:15:09.34#ibcon#enter sib2, iclass 34, count 2 2006.210.08:15:09.34#ibcon#flushed, iclass 34, count 2 2006.210.08:15:09.34#ibcon#about to write, iclass 34, count 2 2006.210.08:15:09.34#ibcon#wrote, iclass 34, count 2 2006.210.08:15:09.34#ibcon#about to read 3, iclass 34, count 2 2006.210.08:15:09.37#ibcon#read 3, iclass 34, count 2 2006.210.08:15:09.37#ibcon#about to read 4, iclass 34, count 2 2006.210.08:15:09.37#ibcon#read 4, iclass 34, count 2 2006.210.08:15:09.37#ibcon#about to read 5, iclass 34, count 2 2006.210.08:15:09.37#ibcon#read 5, iclass 34, count 2 2006.210.08:15:09.37#ibcon#about to read 6, iclass 34, count 2 2006.210.08:15:09.37#ibcon#read 6, iclass 34, count 2 2006.210.08:15:09.37#ibcon#end of sib2, iclass 34, count 2 2006.210.08:15:09.37#ibcon#*after write, iclass 34, count 2 2006.210.08:15:09.37#ibcon#*before return 0, iclass 34, count 2 2006.210.08:15:09.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:15:09.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.210.08:15:09.37#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.210.08:15:09.37#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:09.37#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:15:09.49#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:15:09.49#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:15:09.49#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:15:09.49#ibcon#first serial, iclass 34, count 0 2006.210.08:15:09.49#ibcon#enter sib2, iclass 34, count 0 2006.210.08:15:09.49#ibcon#flushed, iclass 34, count 0 2006.210.08:15:09.49#ibcon#about to write, iclass 34, count 0 2006.210.08:15:09.49#ibcon#wrote, iclass 34, count 0 2006.210.08:15:09.49#ibcon#about to read 3, iclass 34, count 0 2006.210.08:15:09.51#ibcon#read 3, iclass 34, count 0 2006.210.08:15:09.51#ibcon#about to read 4, iclass 34, count 0 2006.210.08:15:09.51#ibcon#read 4, iclass 34, count 0 2006.210.08:15:09.51#ibcon#about to read 5, iclass 34, count 0 2006.210.08:15:09.51#ibcon#read 5, iclass 34, count 0 2006.210.08:15:09.51#ibcon#about to read 6, iclass 34, count 0 2006.210.08:15:09.51#ibcon#read 6, iclass 34, count 0 2006.210.08:15:09.51#ibcon#end of sib2, iclass 34, count 0 2006.210.08:15:09.51#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:15:09.51#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:15:09.51#ibcon#[25=USB\r\n] 2006.210.08:15:09.51#ibcon#*before write, iclass 34, count 0 2006.210.08:15:09.51#ibcon#enter sib2, iclass 34, count 0 2006.210.08:15:09.51#ibcon#flushed, iclass 34, count 0 2006.210.08:15:09.51#ibcon#about to write, iclass 34, count 0 2006.210.08:15:09.51#ibcon#wrote, iclass 34, count 0 2006.210.08:15:09.51#ibcon#about to read 3, iclass 34, count 0 2006.210.08:15:09.54#ibcon#read 3, iclass 34, count 0 2006.210.08:15:09.54#ibcon#about to read 4, iclass 34, count 0 2006.210.08:15:09.54#ibcon#read 4, iclass 34, count 0 2006.210.08:15:09.54#ibcon#about to read 5, iclass 34, count 0 2006.210.08:15:09.54#ibcon#read 5, iclass 34, count 0 2006.210.08:15:09.54#ibcon#about to read 6, iclass 34, count 0 2006.210.08:15:09.54#ibcon#read 6, iclass 34, count 0 2006.210.08:15:09.54#ibcon#end of sib2, iclass 34, count 0 2006.210.08:15:09.54#ibcon#*after write, iclass 34, count 0 2006.210.08:15:09.54#ibcon#*before return 0, iclass 34, count 0 2006.210.08:15:09.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:15:09.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.210.08:15:09.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:15:09.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:15:09.54$vc4f8/valo=7,832.99 2006.210.08:15:09.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.210.08:15:09.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.210.08:15:09.54#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:09.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:15:09.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:15:09.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:15:09.54#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:15:09.54#ibcon#first serial, iclass 36, count 0 2006.210.08:15:09.54#ibcon#enter sib2, iclass 36, count 0 2006.210.08:15:09.54#ibcon#flushed, iclass 36, count 0 2006.210.08:15:09.54#ibcon#about to write, iclass 36, count 0 2006.210.08:15:09.54#ibcon#wrote, iclass 36, count 0 2006.210.08:15:09.54#ibcon#about to read 3, iclass 36, count 0 2006.210.08:15:09.56#ibcon#read 3, iclass 36, count 0 2006.210.08:15:09.56#ibcon#about to read 4, iclass 36, count 0 2006.210.08:15:09.56#ibcon#read 4, iclass 36, count 0 2006.210.08:15:09.56#ibcon#about to read 5, iclass 36, count 0 2006.210.08:15:09.56#ibcon#read 5, iclass 36, count 0 2006.210.08:15:09.56#ibcon#about to read 6, iclass 36, count 0 2006.210.08:15:09.56#ibcon#read 6, iclass 36, count 0 2006.210.08:15:09.56#ibcon#end of sib2, iclass 36, count 0 2006.210.08:15:09.56#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:15:09.56#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:15:09.56#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:15:09.56#ibcon#*before write, iclass 36, count 0 2006.210.08:15:09.56#ibcon#enter sib2, iclass 36, count 0 2006.210.08:15:09.56#ibcon#flushed, iclass 36, count 0 2006.210.08:15:09.56#ibcon#about to write, iclass 36, count 0 2006.210.08:15:09.56#ibcon#wrote, iclass 36, count 0 2006.210.08:15:09.56#ibcon#about to read 3, iclass 36, count 0 2006.210.08:15:09.60#ibcon#read 3, iclass 36, count 0 2006.210.08:15:09.60#ibcon#about to read 4, iclass 36, count 0 2006.210.08:15:09.60#ibcon#read 4, iclass 36, count 0 2006.210.08:15:09.60#ibcon#about to read 5, iclass 36, count 0 2006.210.08:15:09.60#ibcon#read 5, iclass 36, count 0 2006.210.08:15:09.60#ibcon#about to read 6, iclass 36, count 0 2006.210.08:15:09.60#ibcon#read 6, iclass 36, count 0 2006.210.08:15:09.60#ibcon#end of sib2, iclass 36, count 0 2006.210.08:15:09.60#ibcon#*after write, iclass 36, count 0 2006.210.08:15:09.60#ibcon#*before return 0, iclass 36, count 0 2006.210.08:15:09.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:15:09.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.210.08:15:09.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:15:09.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:15:09.60$vc4f8/va=7,6 2006.210.08:15:09.60#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.210.08:15:09.60#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.210.08:15:09.60#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:09.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:15:09.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:15:09.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:15:09.66#ibcon#enter wrdev, iclass 38, count 2 2006.210.08:15:09.66#ibcon#first serial, iclass 38, count 2 2006.210.08:15:09.66#ibcon#enter sib2, iclass 38, count 2 2006.210.08:15:09.66#ibcon#flushed, iclass 38, count 2 2006.210.08:15:09.66#ibcon#about to write, iclass 38, count 2 2006.210.08:15:09.66#ibcon#wrote, iclass 38, count 2 2006.210.08:15:09.66#ibcon#about to read 3, iclass 38, count 2 2006.210.08:15:09.68#ibcon#read 3, iclass 38, count 2 2006.210.08:15:09.68#ibcon#about to read 4, iclass 38, count 2 2006.210.08:15:09.68#ibcon#read 4, iclass 38, count 2 2006.210.08:15:09.68#ibcon#about to read 5, iclass 38, count 2 2006.210.08:15:09.68#ibcon#read 5, iclass 38, count 2 2006.210.08:15:09.68#ibcon#about to read 6, iclass 38, count 2 2006.210.08:15:09.68#ibcon#read 6, iclass 38, count 2 2006.210.08:15:09.68#ibcon#end of sib2, iclass 38, count 2 2006.210.08:15:09.68#ibcon#*mode == 0, iclass 38, count 2 2006.210.08:15:09.68#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.210.08:15:09.68#ibcon#[25=AT07-06\r\n] 2006.210.08:15:09.68#ibcon#*before write, iclass 38, count 2 2006.210.08:15:09.68#ibcon#enter sib2, iclass 38, count 2 2006.210.08:15:09.68#ibcon#flushed, iclass 38, count 2 2006.210.08:15:09.68#ibcon#about to write, iclass 38, count 2 2006.210.08:15:09.68#ibcon#wrote, iclass 38, count 2 2006.210.08:15:09.68#ibcon#about to read 3, iclass 38, count 2 2006.210.08:15:09.71#ibcon#read 3, iclass 38, count 2 2006.210.08:15:09.71#ibcon#about to read 4, iclass 38, count 2 2006.210.08:15:09.71#ibcon#read 4, iclass 38, count 2 2006.210.08:15:09.71#ibcon#about to read 5, iclass 38, count 2 2006.210.08:15:09.71#ibcon#read 5, iclass 38, count 2 2006.210.08:15:09.71#ibcon#about to read 6, iclass 38, count 2 2006.210.08:15:09.71#ibcon#read 6, iclass 38, count 2 2006.210.08:15:09.71#ibcon#end of sib2, iclass 38, count 2 2006.210.08:15:09.71#ibcon#*after write, iclass 38, count 2 2006.210.08:15:09.71#ibcon#*before return 0, iclass 38, count 2 2006.210.08:15:09.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:15:09.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.210.08:15:09.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.210.08:15:09.71#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:09.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:15:09.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:15:09.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:15:09.83#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:15:09.83#ibcon#first serial, iclass 38, count 0 2006.210.08:15:09.83#ibcon#enter sib2, iclass 38, count 0 2006.210.08:15:09.83#ibcon#flushed, iclass 38, count 0 2006.210.08:15:09.83#ibcon#about to write, iclass 38, count 0 2006.210.08:15:09.83#ibcon#wrote, iclass 38, count 0 2006.210.08:15:09.83#ibcon#about to read 3, iclass 38, count 0 2006.210.08:15:09.85#ibcon#read 3, iclass 38, count 0 2006.210.08:15:09.85#ibcon#about to read 4, iclass 38, count 0 2006.210.08:15:09.85#ibcon#read 4, iclass 38, count 0 2006.210.08:15:09.85#ibcon#about to read 5, iclass 38, count 0 2006.210.08:15:09.85#ibcon#read 5, iclass 38, count 0 2006.210.08:15:09.85#ibcon#about to read 6, iclass 38, count 0 2006.210.08:15:09.85#ibcon#read 6, iclass 38, count 0 2006.210.08:15:09.85#ibcon#end of sib2, iclass 38, count 0 2006.210.08:15:09.85#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:15:09.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:15:09.85#ibcon#[25=USB\r\n] 2006.210.08:15:09.85#ibcon#*before write, iclass 38, count 0 2006.210.08:15:09.85#ibcon#enter sib2, iclass 38, count 0 2006.210.08:15:09.85#ibcon#flushed, iclass 38, count 0 2006.210.08:15:09.85#ibcon#about to write, iclass 38, count 0 2006.210.08:15:09.85#ibcon#wrote, iclass 38, count 0 2006.210.08:15:09.85#ibcon#about to read 3, iclass 38, count 0 2006.210.08:15:09.88#ibcon#read 3, iclass 38, count 0 2006.210.08:15:09.88#ibcon#about to read 4, iclass 38, count 0 2006.210.08:15:09.88#ibcon#read 4, iclass 38, count 0 2006.210.08:15:09.88#ibcon#about to read 5, iclass 38, count 0 2006.210.08:15:09.88#ibcon#read 5, iclass 38, count 0 2006.210.08:15:09.88#ibcon#about to read 6, iclass 38, count 0 2006.210.08:15:09.88#ibcon#read 6, iclass 38, count 0 2006.210.08:15:09.88#ibcon#end of sib2, iclass 38, count 0 2006.210.08:15:09.88#ibcon#*after write, iclass 38, count 0 2006.210.08:15:09.88#ibcon#*before return 0, iclass 38, count 0 2006.210.08:15:09.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:15:09.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.210.08:15:09.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:15:09.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:15:09.88$vc4f8/valo=8,852.99 2006.210.08:15:09.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.210.08:15:09.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.210.08:15:09.88#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:09.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:15:09.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:15:09.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:15:09.88#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:15:09.88#ibcon#first serial, iclass 40, count 0 2006.210.08:15:09.88#ibcon#enter sib2, iclass 40, count 0 2006.210.08:15:09.88#ibcon#flushed, iclass 40, count 0 2006.210.08:15:09.88#ibcon#about to write, iclass 40, count 0 2006.210.08:15:09.88#ibcon#wrote, iclass 40, count 0 2006.210.08:15:09.88#ibcon#about to read 3, iclass 40, count 0 2006.210.08:15:09.90#ibcon#read 3, iclass 40, count 0 2006.210.08:15:09.90#ibcon#about to read 4, iclass 40, count 0 2006.210.08:15:09.90#ibcon#read 4, iclass 40, count 0 2006.210.08:15:09.90#ibcon#about to read 5, iclass 40, count 0 2006.210.08:15:09.90#ibcon#read 5, iclass 40, count 0 2006.210.08:15:09.90#ibcon#about to read 6, iclass 40, count 0 2006.210.08:15:09.90#ibcon#read 6, iclass 40, count 0 2006.210.08:15:09.90#ibcon#end of sib2, iclass 40, count 0 2006.210.08:15:09.90#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:15:09.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:15:09.90#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:15:09.90#ibcon#*before write, iclass 40, count 0 2006.210.08:15:09.90#ibcon#enter sib2, iclass 40, count 0 2006.210.08:15:09.90#ibcon#flushed, iclass 40, count 0 2006.210.08:15:09.90#ibcon#about to write, iclass 40, count 0 2006.210.08:15:09.90#ibcon#wrote, iclass 40, count 0 2006.210.08:15:09.90#ibcon#about to read 3, iclass 40, count 0 2006.210.08:15:09.94#ibcon#read 3, iclass 40, count 0 2006.210.08:15:09.94#ibcon#about to read 4, iclass 40, count 0 2006.210.08:15:09.94#ibcon#read 4, iclass 40, count 0 2006.210.08:15:09.94#ibcon#about to read 5, iclass 40, count 0 2006.210.08:15:09.94#ibcon#read 5, iclass 40, count 0 2006.210.08:15:09.94#ibcon#about to read 6, iclass 40, count 0 2006.210.08:15:09.94#ibcon#read 6, iclass 40, count 0 2006.210.08:15:09.94#ibcon#end of sib2, iclass 40, count 0 2006.210.08:15:09.94#ibcon#*after write, iclass 40, count 0 2006.210.08:15:09.94#ibcon#*before return 0, iclass 40, count 0 2006.210.08:15:09.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:15:09.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.210.08:15:09.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:15:09.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:15:09.94$vc4f8/va=8,7 2006.210.08:15:09.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.210.08:15:09.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.210.08:15:09.94#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:09.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:15:10.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:15:10.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:15:10.00#ibcon#enter wrdev, iclass 4, count 2 2006.210.08:15:10.00#ibcon#first serial, iclass 4, count 2 2006.210.08:15:10.00#ibcon#enter sib2, iclass 4, count 2 2006.210.08:15:10.00#ibcon#flushed, iclass 4, count 2 2006.210.08:15:10.00#ibcon#about to write, iclass 4, count 2 2006.210.08:15:10.00#ibcon#wrote, iclass 4, count 2 2006.210.08:15:10.00#ibcon#about to read 3, iclass 4, count 2 2006.210.08:15:10.02#ibcon#read 3, iclass 4, count 2 2006.210.08:15:10.02#ibcon#about to read 4, iclass 4, count 2 2006.210.08:15:10.02#ibcon#read 4, iclass 4, count 2 2006.210.08:15:10.02#ibcon#about to read 5, iclass 4, count 2 2006.210.08:15:10.02#ibcon#read 5, iclass 4, count 2 2006.210.08:15:10.02#ibcon#about to read 6, iclass 4, count 2 2006.210.08:15:10.02#ibcon#read 6, iclass 4, count 2 2006.210.08:15:10.02#ibcon#end of sib2, iclass 4, count 2 2006.210.08:15:10.02#ibcon#*mode == 0, iclass 4, count 2 2006.210.08:15:10.02#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.210.08:15:10.02#ibcon#[25=AT08-07\r\n] 2006.210.08:15:10.02#ibcon#*before write, iclass 4, count 2 2006.210.08:15:10.02#ibcon#enter sib2, iclass 4, count 2 2006.210.08:15:10.02#ibcon#flushed, iclass 4, count 2 2006.210.08:15:10.02#ibcon#about to write, iclass 4, count 2 2006.210.08:15:10.02#ibcon#wrote, iclass 4, count 2 2006.210.08:15:10.02#ibcon#about to read 3, iclass 4, count 2 2006.210.08:15:10.05#ibcon#read 3, iclass 4, count 2 2006.210.08:15:10.05#ibcon#about to read 4, iclass 4, count 2 2006.210.08:15:10.05#ibcon#read 4, iclass 4, count 2 2006.210.08:15:10.05#ibcon#about to read 5, iclass 4, count 2 2006.210.08:15:10.05#ibcon#read 5, iclass 4, count 2 2006.210.08:15:10.05#ibcon#about to read 6, iclass 4, count 2 2006.210.08:15:10.05#ibcon#read 6, iclass 4, count 2 2006.210.08:15:10.05#ibcon#end of sib2, iclass 4, count 2 2006.210.08:15:10.05#ibcon#*after write, iclass 4, count 2 2006.210.08:15:10.05#ibcon#*before return 0, iclass 4, count 2 2006.210.08:15:10.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:15:10.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.210.08:15:10.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.210.08:15:10.05#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:10.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:15:10.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:15:10.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:15:10.17#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:15:10.17#ibcon#first serial, iclass 4, count 0 2006.210.08:15:10.17#ibcon#enter sib2, iclass 4, count 0 2006.210.08:15:10.17#ibcon#flushed, iclass 4, count 0 2006.210.08:15:10.17#ibcon#about to write, iclass 4, count 0 2006.210.08:15:10.17#ibcon#wrote, iclass 4, count 0 2006.210.08:15:10.17#ibcon#about to read 3, iclass 4, count 0 2006.210.08:15:10.19#ibcon#read 3, iclass 4, count 0 2006.210.08:15:10.19#ibcon#about to read 4, iclass 4, count 0 2006.210.08:15:10.19#ibcon#read 4, iclass 4, count 0 2006.210.08:15:10.19#ibcon#about to read 5, iclass 4, count 0 2006.210.08:15:10.19#ibcon#read 5, iclass 4, count 0 2006.210.08:15:10.19#ibcon#about to read 6, iclass 4, count 0 2006.210.08:15:10.19#ibcon#read 6, iclass 4, count 0 2006.210.08:15:10.19#ibcon#end of sib2, iclass 4, count 0 2006.210.08:15:10.19#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:15:10.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:15:10.19#ibcon#[25=USB\r\n] 2006.210.08:15:10.19#ibcon#*before write, iclass 4, count 0 2006.210.08:15:10.19#ibcon#enter sib2, iclass 4, count 0 2006.210.08:15:10.19#ibcon#flushed, iclass 4, count 0 2006.210.08:15:10.19#ibcon#about to write, iclass 4, count 0 2006.210.08:15:10.19#ibcon#wrote, iclass 4, count 0 2006.210.08:15:10.19#ibcon#about to read 3, iclass 4, count 0 2006.210.08:15:10.22#ibcon#read 3, iclass 4, count 0 2006.210.08:15:10.22#ibcon#about to read 4, iclass 4, count 0 2006.210.08:15:10.22#ibcon#read 4, iclass 4, count 0 2006.210.08:15:10.22#ibcon#about to read 5, iclass 4, count 0 2006.210.08:15:10.22#ibcon#read 5, iclass 4, count 0 2006.210.08:15:10.22#ibcon#about to read 6, iclass 4, count 0 2006.210.08:15:10.22#ibcon#read 6, iclass 4, count 0 2006.210.08:15:10.22#ibcon#end of sib2, iclass 4, count 0 2006.210.08:15:10.22#ibcon#*after write, iclass 4, count 0 2006.210.08:15:10.22#ibcon#*before return 0, iclass 4, count 0 2006.210.08:15:10.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:15:10.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.210.08:15:10.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:15:10.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:15:10.22$vc4f8/vblo=1,632.99 2006.210.08:15:10.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.210.08:15:10.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.210.08:15:10.22#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:10.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:15:10.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:15:10.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:15:10.22#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:15:10.22#ibcon#first serial, iclass 6, count 0 2006.210.08:15:10.22#ibcon#enter sib2, iclass 6, count 0 2006.210.08:15:10.22#ibcon#flushed, iclass 6, count 0 2006.210.08:15:10.22#ibcon#about to write, iclass 6, count 0 2006.210.08:15:10.22#ibcon#wrote, iclass 6, count 0 2006.210.08:15:10.22#ibcon#about to read 3, iclass 6, count 0 2006.210.08:15:10.24#ibcon#read 3, iclass 6, count 0 2006.210.08:15:10.24#ibcon#about to read 4, iclass 6, count 0 2006.210.08:15:10.24#ibcon#read 4, iclass 6, count 0 2006.210.08:15:10.24#ibcon#about to read 5, iclass 6, count 0 2006.210.08:15:10.24#ibcon#read 5, iclass 6, count 0 2006.210.08:15:10.24#ibcon#about to read 6, iclass 6, count 0 2006.210.08:15:10.24#ibcon#read 6, iclass 6, count 0 2006.210.08:15:10.24#ibcon#end of sib2, iclass 6, count 0 2006.210.08:15:10.24#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:15:10.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:15:10.24#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:15:10.24#ibcon#*before write, iclass 6, count 0 2006.210.08:15:10.24#ibcon#enter sib2, iclass 6, count 0 2006.210.08:15:10.24#ibcon#flushed, iclass 6, count 0 2006.210.08:15:10.24#ibcon#about to write, iclass 6, count 0 2006.210.08:15:10.24#ibcon#wrote, iclass 6, count 0 2006.210.08:15:10.24#ibcon#about to read 3, iclass 6, count 0 2006.210.08:15:10.28#ibcon#read 3, iclass 6, count 0 2006.210.08:15:10.28#ibcon#about to read 4, iclass 6, count 0 2006.210.08:15:10.28#ibcon#read 4, iclass 6, count 0 2006.210.08:15:10.28#ibcon#about to read 5, iclass 6, count 0 2006.210.08:15:10.28#ibcon#read 5, iclass 6, count 0 2006.210.08:15:10.28#ibcon#about to read 6, iclass 6, count 0 2006.210.08:15:10.28#ibcon#read 6, iclass 6, count 0 2006.210.08:15:10.28#ibcon#end of sib2, iclass 6, count 0 2006.210.08:15:10.28#ibcon#*after write, iclass 6, count 0 2006.210.08:15:10.28#ibcon#*before return 0, iclass 6, count 0 2006.210.08:15:10.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:15:10.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.210.08:15:10.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:15:10.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:15:10.28$vc4f8/vb=1,4 2006.210.08:15:10.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.210.08:15:10.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.210.08:15:10.28#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:10.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:15:10.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:15:10.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:15:10.28#ibcon#enter wrdev, iclass 10, count 2 2006.210.08:15:10.28#ibcon#first serial, iclass 10, count 2 2006.210.08:15:10.28#ibcon#enter sib2, iclass 10, count 2 2006.210.08:15:10.28#ibcon#flushed, iclass 10, count 2 2006.210.08:15:10.28#ibcon#about to write, iclass 10, count 2 2006.210.08:15:10.28#ibcon#wrote, iclass 10, count 2 2006.210.08:15:10.28#ibcon#about to read 3, iclass 10, count 2 2006.210.08:15:10.30#ibcon#read 3, iclass 10, count 2 2006.210.08:15:10.30#ibcon#about to read 4, iclass 10, count 2 2006.210.08:15:10.30#ibcon#read 4, iclass 10, count 2 2006.210.08:15:10.30#ibcon#about to read 5, iclass 10, count 2 2006.210.08:15:10.30#ibcon#read 5, iclass 10, count 2 2006.210.08:15:10.30#ibcon#about to read 6, iclass 10, count 2 2006.210.08:15:10.30#ibcon#read 6, iclass 10, count 2 2006.210.08:15:10.30#ibcon#end of sib2, iclass 10, count 2 2006.210.08:15:10.30#ibcon#*mode == 0, iclass 10, count 2 2006.210.08:15:10.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.210.08:15:10.30#ibcon#[27=AT01-04\r\n] 2006.210.08:15:10.30#ibcon#*before write, iclass 10, count 2 2006.210.08:15:10.30#ibcon#enter sib2, iclass 10, count 2 2006.210.08:15:10.30#ibcon#flushed, iclass 10, count 2 2006.210.08:15:10.30#ibcon#about to write, iclass 10, count 2 2006.210.08:15:10.30#ibcon#wrote, iclass 10, count 2 2006.210.08:15:10.30#ibcon#about to read 3, iclass 10, count 2 2006.210.08:15:10.33#ibcon#read 3, iclass 10, count 2 2006.210.08:15:10.33#ibcon#about to read 4, iclass 10, count 2 2006.210.08:15:10.33#ibcon#read 4, iclass 10, count 2 2006.210.08:15:10.33#ibcon#about to read 5, iclass 10, count 2 2006.210.08:15:10.33#ibcon#read 5, iclass 10, count 2 2006.210.08:15:10.33#ibcon#about to read 6, iclass 10, count 2 2006.210.08:15:10.33#ibcon#read 6, iclass 10, count 2 2006.210.08:15:10.33#ibcon#end of sib2, iclass 10, count 2 2006.210.08:15:10.33#ibcon#*after write, iclass 10, count 2 2006.210.08:15:10.33#ibcon#*before return 0, iclass 10, count 2 2006.210.08:15:10.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:15:10.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.210.08:15:10.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.210.08:15:10.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:10.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:15:10.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:15:10.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:15:10.45#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:15:10.45#ibcon#first serial, iclass 10, count 0 2006.210.08:15:10.45#ibcon#enter sib2, iclass 10, count 0 2006.210.08:15:10.45#ibcon#flushed, iclass 10, count 0 2006.210.08:15:10.45#ibcon#about to write, iclass 10, count 0 2006.210.08:15:10.45#ibcon#wrote, iclass 10, count 0 2006.210.08:15:10.45#ibcon#about to read 3, iclass 10, count 0 2006.210.08:15:10.47#ibcon#read 3, iclass 10, count 0 2006.210.08:15:10.47#ibcon#about to read 4, iclass 10, count 0 2006.210.08:15:10.47#ibcon#read 4, iclass 10, count 0 2006.210.08:15:10.47#ibcon#about to read 5, iclass 10, count 0 2006.210.08:15:10.47#ibcon#read 5, iclass 10, count 0 2006.210.08:15:10.47#ibcon#about to read 6, iclass 10, count 0 2006.210.08:15:10.47#ibcon#read 6, iclass 10, count 0 2006.210.08:15:10.47#ibcon#end of sib2, iclass 10, count 0 2006.210.08:15:10.47#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:15:10.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:15:10.47#ibcon#[27=USB\r\n] 2006.210.08:15:10.47#ibcon#*before write, iclass 10, count 0 2006.210.08:15:10.47#ibcon#enter sib2, iclass 10, count 0 2006.210.08:15:10.47#ibcon#flushed, iclass 10, count 0 2006.210.08:15:10.47#ibcon#about to write, iclass 10, count 0 2006.210.08:15:10.47#ibcon#wrote, iclass 10, count 0 2006.210.08:15:10.47#ibcon#about to read 3, iclass 10, count 0 2006.210.08:15:10.50#ibcon#read 3, iclass 10, count 0 2006.210.08:15:10.50#ibcon#about to read 4, iclass 10, count 0 2006.210.08:15:10.50#ibcon#read 4, iclass 10, count 0 2006.210.08:15:10.50#ibcon#about to read 5, iclass 10, count 0 2006.210.08:15:10.50#ibcon#read 5, iclass 10, count 0 2006.210.08:15:10.50#ibcon#about to read 6, iclass 10, count 0 2006.210.08:15:10.50#ibcon#read 6, iclass 10, count 0 2006.210.08:15:10.50#ibcon#end of sib2, iclass 10, count 0 2006.210.08:15:10.50#ibcon#*after write, iclass 10, count 0 2006.210.08:15:10.50#ibcon#*before return 0, iclass 10, count 0 2006.210.08:15:10.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:15:10.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.210.08:15:10.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:15:10.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:15:10.50$vc4f8/vblo=2,640.99 2006.210.08:15:10.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.210.08:15:10.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.210.08:15:10.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:10.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:10.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:10.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:10.50#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:15:10.50#ibcon#first serial, iclass 12, count 0 2006.210.08:15:10.50#ibcon#enter sib2, iclass 12, count 0 2006.210.08:15:10.50#ibcon#flushed, iclass 12, count 0 2006.210.08:15:10.50#ibcon#about to write, iclass 12, count 0 2006.210.08:15:10.50#ibcon#wrote, iclass 12, count 0 2006.210.08:15:10.50#ibcon#about to read 3, iclass 12, count 0 2006.210.08:15:10.52#ibcon#read 3, iclass 12, count 0 2006.210.08:15:10.52#ibcon#about to read 4, iclass 12, count 0 2006.210.08:15:10.52#ibcon#read 4, iclass 12, count 0 2006.210.08:15:10.52#ibcon#about to read 5, iclass 12, count 0 2006.210.08:15:10.52#ibcon#read 5, iclass 12, count 0 2006.210.08:15:10.52#ibcon#about to read 6, iclass 12, count 0 2006.210.08:15:10.52#ibcon#read 6, iclass 12, count 0 2006.210.08:15:10.52#ibcon#end of sib2, iclass 12, count 0 2006.210.08:15:10.52#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:15:10.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:15:10.52#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:15:10.52#ibcon#*before write, iclass 12, count 0 2006.210.08:15:10.52#ibcon#enter sib2, iclass 12, count 0 2006.210.08:15:10.52#ibcon#flushed, iclass 12, count 0 2006.210.08:15:10.52#ibcon#about to write, iclass 12, count 0 2006.210.08:15:10.52#ibcon#wrote, iclass 12, count 0 2006.210.08:15:10.52#ibcon#about to read 3, iclass 12, count 0 2006.210.08:15:10.56#ibcon#read 3, iclass 12, count 0 2006.210.08:15:10.56#ibcon#about to read 4, iclass 12, count 0 2006.210.08:15:10.56#ibcon#read 4, iclass 12, count 0 2006.210.08:15:10.56#ibcon#about to read 5, iclass 12, count 0 2006.210.08:15:10.56#ibcon#read 5, iclass 12, count 0 2006.210.08:15:10.56#ibcon#about to read 6, iclass 12, count 0 2006.210.08:15:10.56#ibcon#read 6, iclass 12, count 0 2006.210.08:15:10.56#ibcon#end of sib2, iclass 12, count 0 2006.210.08:15:10.56#ibcon#*after write, iclass 12, count 0 2006.210.08:15:10.56#ibcon#*before return 0, iclass 12, count 0 2006.210.08:15:10.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:10.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.210.08:15:10.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:15:10.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:15:10.56$vc4f8/vb=2,4 2006.210.08:15:10.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.210.08:15:10.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.210.08:15:10.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:10.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:10.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:10.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:10.62#ibcon#enter wrdev, iclass 14, count 2 2006.210.08:15:10.62#ibcon#first serial, iclass 14, count 2 2006.210.08:15:10.62#ibcon#enter sib2, iclass 14, count 2 2006.210.08:15:10.62#ibcon#flushed, iclass 14, count 2 2006.210.08:15:10.62#ibcon#about to write, iclass 14, count 2 2006.210.08:15:10.62#ibcon#wrote, iclass 14, count 2 2006.210.08:15:10.62#ibcon#about to read 3, iclass 14, count 2 2006.210.08:15:10.64#ibcon#read 3, iclass 14, count 2 2006.210.08:15:10.64#ibcon#about to read 4, iclass 14, count 2 2006.210.08:15:10.64#ibcon#read 4, iclass 14, count 2 2006.210.08:15:10.64#ibcon#about to read 5, iclass 14, count 2 2006.210.08:15:10.64#ibcon#read 5, iclass 14, count 2 2006.210.08:15:10.64#ibcon#about to read 6, iclass 14, count 2 2006.210.08:15:10.64#ibcon#read 6, iclass 14, count 2 2006.210.08:15:10.64#ibcon#end of sib2, iclass 14, count 2 2006.210.08:15:10.64#ibcon#*mode == 0, iclass 14, count 2 2006.210.08:15:10.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.210.08:15:10.64#ibcon#[27=AT02-04\r\n] 2006.210.08:15:10.64#ibcon#*before write, iclass 14, count 2 2006.210.08:15:10.64#ibcon#enter sib2, iclass 14, count 2 2006.210.08:15:10.64#ibcon#flushed, iclass 14, count 2 2006.210.08:15:10.64#ibcon#about to write, iclass 14, count 2 2006.210.08:15:10.64#ibcon#wrote, iclass 14, count 2 2006.210.08:15:10.64#ibcon#about to read 3, iclass 14, count 2 2006.210.08:15:10.67#ibcon#read 3, iclass 14, count 2 2006.210.08:15:10.67#ibcon#about to read 4, iclass 14, count 2 2006.210.08:15:10.67#ibcon#read 4, iclass 14, count 2 2006.210.08:15:10.67#ibcon#about to read 5, iclass 14, count 2 2006.210.08:15:10.67#ibcon#read 5, iclass 14, count 2 2006.210.08:15:10.67#ibcon#about to read 6, iclass 14, count 2 2006.210.08:15:10.67#ibcon#read 6, iclass 14, count 2 2006.210.08:15:10.67#ibcon#end of sib2, iclass 14, count 2 2006.210.08:15:10.67#ibcon#*after write, iclass 14, count 2 2006.210.08:15:10.67#ibcon#*before return 0, iclass 14, count 2 2006.210.08:15:10.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:10.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.210.08:15:10.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.210.08:15:10.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:10.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:10.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:10.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:10.79#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:15:10.79#ibcon#first serial, iclass 14, count 0 2006.210.08:15:10.79#ibcon#enter sib2, iclass 14, count 0 2006.210.08:15:10.79#ibcon#flushed, iclass 14, count 0 2006.210.08:15:10.79#ibcon#about to write, iclass 14, count 0 2006.210.08:15:10.79#ibcon#wrote, iclass 14, count 0 2006.210.08:15:10.79#ibcon#about to read 3, iclass 14, count 0 2006.210.08:15:10.81#ibcon#read 3, iclass 14, count 0 2006.210.08:15:10.81#ibcon#about to read 4, iclass 14, count 0 2006.210.08:15:10.81#ibcon#read 4, iclass 14, count 0 2006.210.08:15:10.81#ibcon#about to read 5, iclass 14, count 0 2006.210.08:15:10.81#ibcon#read 5, iclass 14, count 0 2006.210.08:15:10.81#ibcon#about to read 6, iclass 14, count 0 2006.210.08:15:10.81#ibcon#read 6, iclass 14, count 0 2006.210.08:15:10.81#ibcon#end of sib2, iclass 14, count 0 2006.210.08:15:10.81#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:15:10.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:15:10.81#ibcon#[27=USB\r\n] 2006.210.08:15:10.81#ibcon#*before write, iclass 14, count 0 2006.210.08:15:10.81#ibcon#enter sib2, iclass 14, count 0 2006.210.08:15:10.81#ibcon#flushed, iclass 14, count 0 2006.210.08:15:10.81#ibcon#about to write, iclass 14, count 0 2006.210.08:15:10.81#ibcon#wrote, iclass 14, count 0 2006.210.08:15:10.81#ibcon#about to read 3, iclass 14, count 0 2006.210.08:15:10.84#ibcon#read 3, iclass 14, count 0 2006.210.08:15:10.84#ibcon#about to read 4, iclass 14, count 0 2006.210.08:15:10.84#ibcon#read 4, iclass 14, count 0 2006.210.08:15:10.84#ibcon#about to read 5, iclass 14, count 0 2006.210.08:15:10.84#ibcon#read 5, iclass 14, count 0 2006.210.08:15:10.84#ibcon#about to read 6, iclass 14, count 0 2006.210.08:15:10.84#ibcon#read 6, iclass 14, count 0 2006.210.08:15:10.84#ibcon#end of sib2, iclass 14, count 0 2006.210.08:15:10.84#ibcon#*after write, iclass 14, count 0 2006.210.08:15:10.84#ibcon#*before return 0, iclass 14, count 0 2006.210.08:15:10.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:10.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.210.08:15:10.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:15:10.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:15:10.84$vc4f8/vblo=3,656.99 2006.210.08:15:10.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.08:15:10.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.08:15:10.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:10.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:10.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:10.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:10.84#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:15:10.84#ibcon#first serial, iclass 16, count 0 2006.210.08:15:10.84#ibcon#enter sib2, iclass 16, count 0 2006.210.08:15:10.84#ibcon#flushed, iclass 16, count 0 2006.210.08:15:10.84#ibcon#about to write, iclass 16, count 0 2006.210.08:15:10.84#ibcon#wrote, iclass 16, count 0 2006.210.08:15:10.84#ibcon#about to read 3, iclass 16, count 0 2006.210.08:15:10.86#ibcon#read 3, iclass 16, count 0 2006.210.08:15:10.86#ibcon#about to read 4, iclass 16, count 0 2006.210.08:15:10.86#ibcon#read 4, iclass 16, count 0 2006.210.08:15:10.86#ibcon#about to read 5, iclass 16, count 0 2006.210.08:15:10.86#ibcon#read 5, iclass 16, count 0 2006.210.08:15:10.86#ibcon#about to read 6, iclass 16, count 0 2006.210.08:15:10.86#ibcon#read 6, iclass 16, count 0 2006.210.08:15:10.86#ibcon#end of sib2, iclass 16, count 0 2006.210.08:15:10.86#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:15:10.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:15:10.86#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:15:10.86#ibcon#*before write, iclass 16, count 0 2006.210.08:15:10.86#ibcon#enter sib2, iclass 16, count 0 2006.210.08:15:10.86#ibcon#flushed, iclass 16, count 0 2006.210.08:15:10.86#ibcon#about to write, iclass 16, count 0 2006.210.08:15:10.86#ibcon#wrote, iclass 16, count 0 2006.210.08:15:10.86#ibcon#about to read 3, iclass 16, count 0 2006.210.08:15:10.90#ibcon#read 3, iclass 16, count 0 2006.210.08:15:10.90#ibcon#about to read 4, iclass 16, count 0 2006.210.08:15:10.90#ibcon#read 4, iclass 16, count 0 2006.210.08:15:10.90#ibcon#about to read 5, iclass 16, count 0 2006.210.08:15:10.90#ibcon#read 5, iclass 16, count 0 2006.210.08:15:10.90#ibcon#about to read 6, iclass 16, count 0 2006.210.08:15:10.90#ibcon#read 6, iclass 16, count 0 2006.210.08:15:10.90#ibcon#end of sib2, iclass 16, count 0 2006.210.08:15:10.90#ibcon#*after write, iclass 16, count 0 2006.210.08:15:10.90#ibcon#*before return 0, iclass 16, count 0 2006.210.08:15:10.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:10.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:15:10.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:15:10.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:15:10.90$vc4f8/vb=3,3 2006.210.08:15:10.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.210.08:15:10.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.210.08:15:10.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:10.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:10.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:10.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:10.96#ibcon#enter wrdev, iclass 18, count 2 2006.210.08:15:10.96#ibcon#first serial, iclass 18, count 2 2006.210.08:15:10.96#ibcon#enter sib2, iclass 18, count 2 2006.210.08:15:10.96#ibcon#flushed, iclass 18, count 2 2006.210.08:15:10.96#ibcon#about to write, iclass 18, count 2 2006.210.08:15:10.96#ibcon#wrote, iclass 18, count 2 2006.210.08:15:10.96#ibcon#about to read 3, iclass 18, count 2 2006.210.08:15:10.98#ibcon#read 3, iclass 18, count 2 2006.210.08:15:10.98#ibcon#about to read 4, iclass 18, count 2 2006.210.08:15:10.98#ibcon#read 4, iclass 18, count 2 2006.210.08:15:10.98#ibcon#about to read 5, iclass 18, count 2 2006.210.08:15:10.98#ibcon#read 5, iclass 18, count 2 2006.210.08:15:10.98#ibcon#about to read 6, iclass 18, count 2 2006.210.08:15:10.98#ibcon#read 6, iclass 18, count 2 2006.210.08:15:10.98#ibcon#end of sib2, iclass 18, count 2 2006.210.08:15:10.98#ibcon#*mode == 0, iclass 18, count 2 2006.210.08:15:10.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.210.08:15:10.98#ibcon#[27=AT03-03\r\n] 2006.210.08:15:10.98#ibcon#*before write, iclass 18, count 2 2006.210.08:15:10.98#ibcon#enter sib2, iclass 18, count 2 2006.210.08:15:10.98#ibcon#flushed, iclass 18, count 2 2006.210.08:15:10.98#ibcon#about to write, iclass 18, count 2 2006.210.08:15:10.98#ibcon#wrote, iclass 18, count 2 2006.210.08:15:10.98#ibcon#about to read 3, iclass 18, count 2 2006.210.08:15:11.01#ibcon#read 3, iclass 18, count 2 2006.210.08:15:11.01#ibcon#about to read 4, iclass 18, count 2 2006.210.08:15:11.01#ibcon#read 4, iclass 18, count 2 2006.210.08:15:11.01#ibcon#about to read 5, iclass 18, count 2 2006.210.08:15:11.01#ibcon#read 5, iclass 18, count 2 2006.210.08:15:11.01#ibcon#about to read 6, iclass 18, count 2 2006.210.08:15:11.01#ibcon#read 6, iclass 18, count 2 2006.210.08:15:11.01#ibcon#end of sib2, iclass 18, count 2 2006.210.08:15:11.01#ibcon#*after write, iclass 18, count 2 2006.210.08:15:11.01#ibcon#*before return 0, iclass 18, count 2 2006.210.08:15:11.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:11.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.210.08:15:11.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.210.08:15:11.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:11.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:11.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:11.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:11.13#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:15:11.13#ibcon#first serial, iclass 18, count 0 2006.210.08:15:11.13#ibcon#enter sib2, iclass 18, count 0 2006.210.08:15:11.13#ibcon#flushed, iclass 18, count 0 2006.210.08:15:11.13#ibcon#about to write, iclass 18, count 0 2006.210.08:15:11.13#ibcon#wrote, iclass 18, count 0 2006.210.08:15:11.13#ibcon#about to read 3, iclass 18, count 0 2006.210.08:15:11.15#ibcon#read 3, iclass 18, count 0 2006.210.08:15:11.15#ibcon#about to read 4, iclass 18, count 0 2006.210.08:15:11.15#ibcon#read 4, iclass 18, count 0 2006.210.08:15:11.15#ibcon#about to read 5, iclass 18, count 0 2006.210.08:15:11.15#ibcon#read 5, iclass 18, count 0 2006.210.08:15:11.15#ibcon#about to read 6, iclass 18, count 0 2006.210.08:15:11.15#ibcon#read 6, iclass 18, count 0 2006.210.08:15:11.15#ibcon#end of sib2, iclass 18, count 0 2006.210.08:15:11.15#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:15:11.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:15:11.15#ibcon#[27=USB\r\n] 2006.210.08:15:11.15#ibcon#*before write, iclass 18, count 0 2006.210.08:15:11.15#ibcon#enter sib2, iclass 18, count 0 2006.210.08:15:11.15#ibcon#flushed, iclass 18, count 0 2006.210.08:15:11.15#ibcon#about to write, iclass 18, count 0 2006.210.08:15:11.15#ibcon#wrote, iclass 18, count 0 2006.210.08:15:11.15#ibcon#about to read 3, iclass 18, count 0 2006.210.08:15:11.18#ibcon#read 3, iclass 18, count 0 2006.210.08:15:11.18#ibcon#about to read 4, iclass 18, count 0 2006.210.08:15:11.18#ibcon#read 4, iclass 18, count 0 2006.210.08:15:11.18#ibcon#about to read 5, iclass 18, count 0 2006.210.08:15:11.18#ibcon#read 5, iclass 18, count 0 2006.210.08:15:11.18#ibcon#about to read 6, iclass 18, count 0 2006.210.08:15:11.18#ibcon#read 6, iclass 18, count 0 2006.210.08:15:11.18#ibcon#end of sib2, iclass 18, count 0 2006.210.08:15:11.18#ibcon#*after write, iclass 18, count 0 2006.210.08:15:11.18#ibcon#*before return 0, iclass 18, count 0 2006.210.08:15:11.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:11.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.210.08:15:11.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:15:11.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:15:11.18$vc4f8/vblo=4,712.99 2006.210.08:15:11.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.210.08:15:11.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.210.08:15:11.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:11.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:11.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:11.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:11.18#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:15:11.18#ibcon#first serial, iclass 20, count 0 2006.210.08:15:11.18#ibcon#enter sib2, iclass 20, count 0 2006.210.08:15:11.18#ibcon#flushed, iclass 20, count 0 2006.210.08:15:11.18#ibcon#about to write, iclass 20, count 0 2006.210.08:15:11.18#ibcon#wrote, iclass 20, count 0 2006.210.08:15:11.18#ibcon#about to read 3, iclass 20, count 0 2006.210.08:15:11.20#ibcon#read 3, iclass 20, count 0 2006.210.08:15:11.20#ibcon#about to read 4, iclass 20, count 0 2006.210.08:15:11.20#ibcon#read 4, iclass 20, count 0 2006.210.08:15:11.20#ibcon#about to read 5, iclass 20, count 0 2006.210.08:15:11.20#ibcon#read 5, iclass 20, count 0 2006.210.08:15:11.20#ibcon#about to read 6, iclass 20, count 0 2006.210.08:15:11.20#ibcon#read 6, iclass 20, count 0 2006.210.08:15:11.20#ibcon#end of sib2, iclass 20, count 0 2006.210.08:15:11.20#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:15:11.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:15:11.20#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:15:11.20#ibcon#*before write, iclass 20, count 0 2006.210.08:15:11.20#ibcon#enter sib2, iclass 20, count 0 2006.210.08:15:11.20#ibcon#flushed, iclass 20, count 0 2006.210.08:15:11.20#ibcon#about to write, iclass 20, count 0 2006.210.08:15:11.20#ibcon#wrote, iclass 20, count 0 2006.210.08:15:11.20#ibcon#about to read 3, iclass 20, count 0 2006.210.08:15:11.24#ibcon#read 3, iclass 20, count 0 2006.210.08:15:11.24#ibcon#about to read 4, iclass 20, count 0 2006.210.08:15:11.24#ibcon#read 4, iclass 20, count 0 2006.210.08:15:11.24#ibcon#about to read 5, iclass 20, count 0 2006.210.08:15:11.24#ibcon#read 5, iclass 20, count 0 2006.210.08:15:11.24#ibcon#about to read 6, iclass 20, count 0 2006.210.08:15:11.24#ibcon#read 6, iclass 20, count 0 2006.210.08:15:11.24#ibcon#end of sib2, iclass 20, count 0 2006.210.08:15:11.24#ibcon#*after write, iclass 20, count 0 2006.210.08:15:11.24#ibcon#*before return 0, iclass 20, count 0 2006.210.08:15:11.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:11.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.210.08:15:11.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:15:11.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:15:11.24$vc4f8/vb=4,3 2006.210.08:15:11.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.210.08:15:11.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.210.08:15:11.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:11.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:11.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:11.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:11.30#ibcon#enter wrdev, iclass 22, count 2 2006.210.08:15:11.30#ibcon#first serial, iclass 22, count 2 2006.210.08:15:11.30#ibcon#enter sib2, iclass 22, count 2 2006.210.08:15:11.30#ibcon#flushed, iclass 22, count 2 2006.210.08:15:11.30#ibcon#about to write, iclass 22, count 2 2006.210.08:15:11.30#ibcon#wrote, iclass 22, count 2 2006.210.08:15:11.30#ibcon#about to read 3, iclass 22, count 2 2006.210.08:15:11.32#ibcon#read 3, iclass 22, count 2 2006.210.08:15:11.32#ibcon#about to read 4, iclass 22, count 2 2006.210.08:15:11.32#ibcon#read 4, iclass 22, count 2 2006.210.08:15:11.32#ibcon#about to read 5, iclass 22, count 2 2006.210.08:15:11.32#ibcon#read 5, iclass 22, count 2 2006.210.08:15:11.32#ibcon#about to read 6, iclass 22, count 2 2006.210.08:15:11.32#ibcon#read 6, iclass 22, count 2 2006.210.08:15:11.32#ibcon#end of sib2, iclass 22, count 2 2006.210.08:15:11.32#ibcon#*mode == 0, iclass 22, count 2 2006.210.08:15:11.32#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.210.08:15:11.32#ibcon#[27=AT04-03\r\n] 2006.210.08:15:11.32#ibcon#*before write, iclass 22, count 2 2006.210.08:15:11.32#ibcon#enter sib2, iclass 22, count 2 2006.210.08:15:11.32#ibcon#flushed, iclass 22, count 2 2006.210.08:15:11.32#ibcon#about to write, iclass 22, count 2 2006.210.08:15:11.32#ibcon#wrote, iclass 22, count 2 2006.210.08:15:11.32#ibcon#about to read 3, iclass 22, count 2 2006.210.08:15:11.35#ibcon#read 3, iclass 22, count 2 2006.210.08:15:11.35#ibcon#about to read 4, iclass 22, count 2 2006.210.08:15:11.35#ibcon#read 4, iclass 22, count 2 2006.210.08:15:11.35#ibcon#about to read 5, iclass 22, count 2 2006.210.08:15:11.35#ibcon#read 5, iclass 22, count 2 2006.210.08:15:11.35#ibcon#about to read 6, iclass 22, count 2 2006.210.08:15:11.35#ibcon#read 6, iclass 22, count 2 2006.210.08:15:11.35#ibcon#end of sib2, iclass 22, count 2 2006.210.08:15:11.35#ibcon#*after write, iclass 22, count 2 2006.210.08:15:11.35#ibcon#*before return 0, iclass 22, count 2 2006.210.08:15:11.35#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:11.35#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.210.08:15:11.35#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.210.08:15:11.35#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:11.35#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:11.47#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:11.47#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:11.47#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:15:11.47#ibcon#first serial, iclass 22, count 0 2006.210.08:15:11.47#ibcon#enter sib2, iclass 22, count 0 2006.210.08:15:11.47#ibcon#flushed, iclass 22, count 0 2006.210.08:15:11.47#ibcon#about to write, iclass 22, count 0 2006.210.08:15:11.47#ibcon#wrote, iclass 22, count 0 2006.210.08:15:11.47#ibcon#about to read 3, iclass 22, count 0 2006.210.08:15:11.49#ibcon#read 3, iclass 22, count 0 2006.210.08:15:11.49#ibcon#about to read 4, iclass 22, count 0 2006.210.08:15:11.49#ibcon#read 4, iclass 22, count 0 2006.210.08:15:11.49#ibcon#about to read 5, iclass 22, count 0 2006.210.08:15:11.49#ibcon#read 5, iclass 22, count 0 2006.210.08:15:11.49#ibcon#about to read 6, iclass 22, count 0 2006.210.08:15:11.49#ibcon#read 6, iclass 22, count 0 2006.210.08:15:11.49#ibcon#end of sib2, iclass 22, count 0 2006.210.08:15:11.49#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:15:11.49#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:15:11.49#ibcon#[27=USB\r\n] 2006.210.08:15:11.49#ibcon#*before write, iclass 22, count 0 2006.210.08:15:11.49#ibcon#enter sib2, iclass 22, count 0 2006.210.08:15:11.49#ibcon#flushed, iclass 22, count 0 2006.210.08:15:11.49#ibcon#about to write, iclass 22, count 0 2006.210.08:15:11.49#ibcon#wrote, iclass 22, count 0 2006.210.08:15:11.49#ibcon#about to read 3, iclass 22, count 0 2006.210.08:15:11.52#ibcon#read 3, iclass 22, count 0 2006.210.08:15:11.52#ibcon#about to read 4, iclass 22, count 0 2006.210.08:15:11.52#ibcon#read 4, iclass 22, count 0 2006.210.08:15:11.52#ibcon#about to read 5, iclass 22, count 0 2006.210.08:15:11.52#ibcon#read 5, iclass 22, count 0 2006.210.08:15:11.52#ibcon#about to read 6, iclass 22, count 0 2006.210.08:15:11.52#ibcon#read 6, iclass 22, count 0 2006.210.08:15:11.52#ibcon#end of sib2, iclass 22, count 0 2006.210.08:15:11.52#ibcon#*after write, iclass 22, count 0 2006.210.08:15:11.52#ibcon#*before return 0, iclass 22, count 0 2006.210.08:15:11.52#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:11.52#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.210.08:15:11.52#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:15:11.52#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:15:11.52$vc4f8/vblo=5,744.99 2006.210.08:15:11.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.210.08:15:11.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.210.08:15:11.52#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:11.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:11.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:11.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:11.52#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:15:11.52#ibcon#first serial, iclass 24, count 0 2006.210.08:15:11.52#ibcon#enter sib2, iclass 24, count 0 2006.210.08:15:11.52#ibcon#flushed, iclass 24, count 0 2006.210.08:15:11.52#ibcon#about to write, iclass 24, count 0 2006.210.08:15:11.52#ibcon#wrote, iclass 24, count 0 2006.210.08:15:11.52#ibcon#about to read 3, iclass 24, count 0 2006.210.08:15:11.54#ibcon#read 3, iclass 24, count 0 2006.210.08:15:11.54#ibcon#about to read 4, iclass 24, count 0 2006.210.08:15:11.54#ibcon#read 4, iclass 24, count 0 2006.210.08:15:11.54#ibcon#about to read 5, iclass 24, count 0 2006.210.08:15:11.54#ibcon#read 5, iclass 24, count 0 2006.210.08:15:11.54#ibcon#about to read 6, iclass 24, count 0 2006.210.08:15:11.54#ibcon#read 6, iclass 24, count 0 2006.210.08:15:11.54#ibcon#end of sib2, iclass 24, count 0 2006.210.08:15:11.54#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:15:11.54#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:15:11.54#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:15:11.54#ibcon#*before write, iclass 24, count 0 2006.210.08:15:11.54#ibcon#enter sib2, iclass 24, count 0 2006.210.08:15:11.54#ibcon#flushed, iclass 24, count 0 2006.210.08:15:11.54#ibcon#about to write, iclass 24, count 0 2006.210.08:15:11.54#ibcon#wrote, iclass 24, count 0 2006.210.08:15:11.54#ibcon#about to read 3, iclass 24, count 0 2006.210.08:15:11.58#ibcon#read 3, iclass 24, count 0 2006.210.08:15:11.58#ibcon#about to read 4, iclass 24, count 0 2006.210.08:15:11.58#ibcon#read 4, iclass 24, count 0 2006.210.08:15:11.58#ibcon#about to read 5, iclass 24, count 0 2006.210.08:15:11.58#ibcon#read 5, iclass 24, count 0 2006.210.08:15:11.58#ibcon#about to read 6, iclass 24, count 0 2006.210.08:15:11.58#ibcon#read 6, iclass 24, count 0 2006.210.08:15:11.58#ibcon#end of sib2, iclass 24, count 0 2006.210.08:15:11.58#ibcon#*after write, iclass 24, count 0 2006.210.08:15:11.58#ibcon#*before return 0, iclass 24, count 0 2006.210.08:15:11.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:11.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.210.08:15:11.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:15:11.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:15:11.58$vc4f8/vb=5,3 2006.210.08:15:11.58#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.210.08:15:11.58#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.210.08:15:11.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:11.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:11.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:11.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:11.64#ibcon#enter wrdev, iclass 26, count 2 2006.210.08:15:11.64#ibcon#first serial, iclass 26, count 2 2006.210.08:15:11.64#ibcon#enter sib2, iclass 26, count 2 2006.210.08:15:11.64#ibcon#flushed, iclass 26, count 2 2006.210.08:15:11.64#ibcon#about to write, iclass 26, count 2 2006.210.08:15:11.64#ibcon#wrote, iclass 26, count 2 2006.210.08:15:11.64#ibcon#about to read 3, iclass 26, count 2 2006.210.08:15:11.66#ibcon#read 3, iclass 26, count 2 2006.210.08:15:11.66#ibcon#about to read 4, iclass 26, count 2 2006.210.08:15:11.66#ibcon#read 4, iclass 26, count 2 2006.210.08:15:11.66#ibcon#about to read 5, iclass 26, count 2 2006.210.08:15:11.66#ibcon#read 5, iclass 26, count 2 2006.210.08:15:11.66#ibcon#about to read 6, iclass 26, count 2 2006.210.08:15:11.66#ibcon#read 6, iclass 26, count 2 2006.210.08:15:11.66#ibcon#end of sib2, iclass 26, count 2 2006.210.08:15:11.66#ibcon#*mode == 0, iclass 26, count 2 2006.210.08:15:11.66#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.210.08:15:11.66#ibcon#[27=AT05-03\r\n] 2006.210.08:15:11.66#ibcon#*before write, iclass 26, count 2 2006.210.08:15:11.66#ibcon#enter sib2, iclass 26, count 2 2006.210.08:15:11.66#ibcon#flushed, iclass 26, count 2 2006.210.08:15:11.66#ibcon#about to write, iclass 26, count 2 2006.210.08:15:11.66#ibcon#wrote, iclass 26, count 2 2006.210.08:15:11.66#ibcon#about to read 3, iclass 26, count 2 2006.210.08:15:11.69#ibcon#read 3, iclass 26, count 2 2006.210.08:15:11.69#ibcon#about to read 4, iclass 26, count 2 2006.210.08:15:11.69#ibcon#read 4, iclass 26, count 2 2006.210.08:15:11.69#ibcon#about to read 5, iclass 26, count 2 2006.210.08:15:11.69#ibcon#read 5, iclass 26, count 2 2006.210.08:15:11.69#ibcon#about to read 6, iclass 26, count 2 2006.210.08:15:11.69#ibcon#read 6, iclass 26, count 2 2006.210.08:15:11.69#ibcon#end of sib2, iclass 26, count 2 2006.210.08:15:11.69#ibcon#*after write, iclass 26, count 2 2006.210.08:15:11.69#ibcon#*before return 0, iclass 26, count 2 2006.210.08:15:11.69#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:11.69#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.210.08:15:11.69#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.210.08:15:11.69#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:11.69#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:11.81#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:11.81#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:11.81#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:15:11.81#ibcon#first serial, iclass 26, count 0 2006.210.08:15:11.81#ibcon#enter sib2, iclass 26, count 0 2006.210.08:15:11.81#ibcon#flushed, iclass 26, count 0 2006.210.08:15:11.81#ibcon#about to write, iclass 26, count 0 2006.210.08:15:11.81#ibcon#wrote, iclass 26, count 0 2006.210.08:15:11.81#ibcon#about to read 3, iclass 26, count 0 2006.210.08:15:11.83#ibcon#read 3, iclass 26, count 0 2006.210.08:15:11.83#ibcon#about to read 4, iclass 26, count 0 2006.210.08:15:11.83#ibcon#read 4, iclass 26, count 0 2006.210.08:15:11.83#ibcon#about to read 5, iclass 26, count 0 2006.210.08:15:11.83#ibcon#read 5, iclass 26, count 0 2006.210.08:15:11.83#ibcon#about to read 6, iclass 26, count 0 2006.210.08:15:11.83#ibcon#read 6, iclass 26, count 0 2006.210.08:15:11.83#ibcon#end of sib2, iclass 26, count 0 2006.210.08:15:11.83#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:15:11.83#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:15:11.83#ibcon#[27=USB\r\n] 2006.210.08:15:11.83#ibcon#*before write, iclass 26, count 0 2006.210.08:15:11.83#ibcon#enter sib2, iclass 26, count 0 2006.210.08:15:11.83#ibcon#flushed, iclass 26, count 0 2006.210.08:15:11.83#ibcon#about to write, iclass 26, count 0 2006.210.08:15:11.83#ibcon#wrote, iclass 26, count 0 2006.210.08:15:11.83#ibcon#about to read 3, iclass 26, count 0 2006.210.08:15:11.86#ibcon#read 3, iclass 26, count 0 2006.210.08:15:11.86#ibcon#about to read 4, iclass 26, count 0 2006.210.08:15:11.86#ibcon#read 4, iclass 26, count 0 2006.210.08:15:11.86#ibcon#about to read 5, iclass 26, count 0 2006.210.08:15:11.86#ibcon#read 5, iclass 26, count 0 2006.210.08:15:11.86#ibcon#about to read 6, iclass 26, count 0 2006.210.08:15:11.86#ibcon#read 6, iclass 26, count 0 2006.210.08:15:11.86#ibcon#end of sib2, iclass 26, count 0 2006.210.08:15:11.86#ibcon#*after write, iclass 26, count 0 2006.210.08:15:11.86#ibcon#*before return 0, iclass 26, count 0 2006.210.08:15:11.86#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:11.86#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.210.08:15:11.86#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:15:11.86#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:15:11.86$vc4f8/vblo=6,752.99 2006.210.08:15:11.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.210.08:15:11.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.210.08:15:11.86#ibcon#ireg 17 cls_cnt 0 2006.210.08:15:11.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:11.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:11.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:11.86#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:15:11.86#ibcon#first serial, iclass 28, count 0 2006.210.08:15:11.86#ibcon#enter sib2, iclass 28, count 0 2006.210.08:15:11.86#ibcon#flushed, iclass 28, count 0 2006.210.08:15:11.86#ibcon#about to write, iclass 28, count 0 2006.210.08:15:11.86#ibcon#wrote, iclass 28, count 0 2006.210.08:15:11.86#ibcon#about to read 3, iclass 28, count 0 2006.210.08:15:11.88#ibcon#read 3, iclass 28, count 0 2006.210.08:15:11.88#ibcon#about to read 4, iclass 28, count 0 2006.210.08:15:11.88#ibcon#read 4, iclass 28, count 0 2006.210.08:15:11.88#ibcon#about to read 5, iclass 28, count 0 2006.210.08:15:11.88#ibcon#read 5, iclass 28, count 0 2006.210.08:15:11.88#ibcon#about to read 6, iclass 28, count 0 2006.210.08:15:11.88#ibcon#read 6, iclass 28, count 0 2006.210.08:15:11.88#ibcon#end of sib2, iclass 28, count 0 2006.210.08:15:11.88#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:15:11.88#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:15:11.88#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:15:11.88#ibcon#*before write, iclass 28, count 0 2006.210.08:15:11.88#ibcon#enter sib2, iclass 28, count 0 2006.210.08:15:11.88#ibcon#flushed, iclass 28, count 0 2006.210.08:15:11.88#ibcon#about to write, iclass 28, count 0 2006.210.08:15:11.88#ibcon#wrote, iclass 28, count 0 2006.210.08:15:11.88#ibcon#about to read 3, iclass 28, count 0 2006.210.08:15:11.92#ibcon#read 3, iclass 28, count 0 2006.210.08:15:11.92#ibcon#about to read 4, iclass 28, count 0 2006.210.08:15:11.92#ibcon#read 4, iclass 28, count 0 2006.210.08:15:11.92#ibcon#about to read 5, iclass 28, count 0 2006.210.08:15:11.92#ibcon#read 5, iclass 28, count 0 2006.210.08:15:11.92#ibcon#about to read 6, iclass 28, count 0 2006.210.08:15:11.92#ibcon#read 6, iclass 28, count 0 2006.210.08:15:11.92#ibcon#end of sib2, iclass 28, count 0 2006.210.08:15:11.92#ibcon#*after write, iclass 28, count 0 2006.210.08:15:11.92#ibcon#*before return 0, iclass 28, count 0 2006.210.08:15:11.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:11.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.210.08:15:11.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:15:11.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:15:11.92$vc4f8/vb=6,3 2006.210.08:15:11.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.210.08:15:11.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.210.08:15:11.92#ibcon#ireg 11 cls_cnt 2 2006.210.08:15:11.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:11.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:11.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:11.98#ibcon#enter wrdev, iclass 30, count 2 2006.210.08:15:11.98#ibcon#first serial, iclass 30, count 2 2006.210.08:15:11.98#ibcon#enter sib2, iclass 30, count 2 2006.210.08:15:11.98#ibcon#flushed, iclass 30, count 2 2006.210.08:15:11.98#ibcon#about to write, iclass 30, count 2 2006.210.08:15:11.98#ibcon#wrote, iclass 30, count 2 2006.210.08:15:11.98#ibcon#about to read 3, iclass 30, count 2 2006.210.08:15:12.00#ibcon#read 3, iclass 30, count 2 2006.210.08:15:12.00#ibcon#about to read 4, iclass 30, count 2 2006.210.08:15:12.00#ibcon#read 4, iclass 30, count 2 2006.210.08:15:12.00#ibcon#about to read 5, iclass 30, count 2 2006.210.08:15:12.00#ibcon#read 5, iclass 30, count 2 2006.210.08:15:12.00#ibcon#about to read 6, iclass 30, count 2 2006.210.08:15:12.00#ibcon#read 6, iclass 30, count 2 2006.210.08:15:12.00#ibcon#end of sib2, iclass 30, count 2 2006.210.08:15:12.00#ibcon#*mode == 0, iclass 30, count 2 2006.210.08:15:12.00#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.210.08:15:12.00#ibcon#[27=AT06-03\r\n] 2006.210.08:15:12.00#ibcon#*before write, iclass 30, count 2 2006.210.08:15:12.00#ibcon#enter sib2, iclass 30, count 2 2006.210.08:15:12.00#ibcon#flushed, iclass 30, count 2 2006.210.08:15:12.00#ibcon#about to write, iclass 30, count 2 2006.210.08:15:12.00#ibcon#wrote, iclass 30, count 2 2006.210.08:15:12.00#ibcon#about to read 3, iclass 30, count 2 2006.210.08:15:12.03#ibcon#read 3, iclass 30, count 2 2006.210.08:15:12.03#ibcon#about to read 4, iclass 30, count 2 2006.210.08:15:12.03#ibcon#read 4, iclass 30, count 2 2006.210.08:15:12.03#ibcon#about to read 5, iclass 30, count 2 2006.210.08:15:12.03#ibcon#read 5, iclass 30, count 2 2006.210.08:15:12.03#ibcon#about to read 6, iclass 30, count 2 2006.210.08:15:12.03#ibcon#read 6, iclass 30, count 2 2006.210.08:15:12.03#ibcon#end of sib2, iclass 30, count 2 2006.210.08:15:12.03#ibcon#*after write, iclass 30, count 2 2006.210.08:15:12.03#ibcon#*before return 0, iclass 30, count 2 2006.210.08:15:12.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:12.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.210.08:15:12.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.210.08:15:12.03#ibcon#ireg 7 cls_cnt 0 2006.210.08:15:12.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:12.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:12.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:12.15#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:15:12.15#ibcon#first serial, iclass 30, count 0 2006.210.08:15:12.15#ibcon#enter sib2, iclass 30, count 0 2006.210.08:15:12.15#ibcon#flushed, iclass 30, count 0 2006.210.08:15:12.15#ibcon#about to write, iclass 30, count 0 2006.210.08:15:12.15#ibcon#wrote, iclass 30, count 0 2006.210.08:15:12.15#ibcon#about to read 3, iclass 30, count 0 2006.210.08:15:12.17#ibcon#read 3, iclass 30, count 0 2006.210.08:15:12.17#ibcon#about to read 4, iclass 30, count 0 2006.210.08:15:12.17#ibcon#read 4, iclass 30, count 0 2006.210.08:15:12.17#ibcon#about to read 5, iclass 30, count 0 2006.210.08:15:12.17#ibcon#read 5, iclass 30, count 0 2006.210.08:15:12.17#ibcon#about to read 6, iclass 30, count 0 2006.210.08:15:12.17#ibcon#read 6, iclass 30, count 0 2006.210.08:15:12.17#ibcon#end of sib2, iclass 30, count 0 2006.210.08:15:12.17#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:15:12.17#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:15:12.17#ibcon#[27=USB\r\n] 2006.210.08:15:12.17#ibcon#*before write, iclass 30, count 0 2006.210.08:15:12.17#ibcon#enter sib2, iclass 30, count 0 2006.210.08:15:12.17#ibcon#flushed, iclass 30, count 0 2006.210.08:15:12.17#ibcon#about to write, iclass 30, count 0 2006.210.08:15:12.17#ibcon#wrote, iclass 30, count 0 2006.210.08:15:12.17#ibcon#about to read 3, iclass 30, count 0 2006.210.08:15:12.20#ibcon#read 3, iclass 30, count 0 2006.210.08:15:12.20#ibcon#about to read 4, iclass 30, count 0 2006.210.08:15:12.20#ibcon#read 4, iclass 30, count 0 2006.210.08:15:12.20#ibcon#about to read 5, iclass 30, count 0 2006.210.08:15:12.20#ibcon#read 5, iclass 30, count 0 2006.210.08:15:12.20#ibcon#about to read 6, iclass 30, count 0 2006.210.08:15:12.20#ibcon#read 6, iclass 30, count 0 2006.210.08:15:12.20#ibcon#end of sib2, iclass 30, count 0 2006.210.08:15:12.20#ibcon#*after write, iclass 30, count 0 2006.210.08:15:12.20#ibcon#*before return 0, iclass 30, count 0 2006.210.08:15:12.20#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:12.20#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.210.08:15:12.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:15:12.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:15:12.20$vc4f8/vabw=wide 2006.210.08:15:12.20#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.210.08:15:12.20#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.210.08:15:12.20#ibcon#ireg 8 cls_cnt 0 2006.210.08:15:12.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:12.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:12.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:12.20#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:15:12.20#ibcon#first serial, iclass 32, count 0 2006.210.08:15:12.20#ibcon#enter sib2, iclass 32, count 0 2006.210.08:15:12.20#ibcon#flushed, iclass 32, count 0 2006.210.08:15:12.20#ibcon#about to write, iclass 32, count 0 2006.210.08:15:12.20#ibcon#wrote, iclass 32, count 0 2006.210.08:15:12.20#ibcon#about to read 3, iclass 32, count 0 2006.210.08:15:12.22#ibcon#read 3, iclass 32, count 0 2006.210.08:15:12.22#ibcon#about to read 4, iclass 32, count 0 2006.210.08:15:12.22#ibcon#read 4, iclass 32, count 0 2006.210.08:15:12.22#ibcon#about to read 5, iclass 32, count 0 2006.210.08:15:12.22#ibcon#read 5, iclass 32, count 0 2006.210.08:15:12.22#ibcon#about to read 6, iclass 32, count 0 2006.210.08:15:12.22#ibcon#read 6, iclass 32, count 0 2006.210.08:15:12.22#ibcon#end of sib2, iclass 32, count 0 2006.210.08:15:12.22#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:15:12.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:15:12.22#ibcon#[25=BW32\r\n] 2006.210.08:15:12.22#ibcon#*before write, iclass 32, count 0 2006.210.08:15:12.22#ibcon#enter sib2, iclass 32, count 0 2006.210.08:15:12.22#ibcon#flushed, iclass 32, count 0 2006.210.08:15:12.22#ibcon#about to write, iclass 32, count 0 2006.210.08:15:12.22#ibcon#wrote, iclass 32, count 0 2006.210.08:15:12.22#ibcon#about to read 3, iclass 32, count 0 2006.210.08:15:12.25#ibcon#read 3, iclass 32, count 0 2006.210.08:15:12.25#ibcon#about to read 4, iclass 32, count 0 2006.210.08:15:12.25#ibcon#read 4, iclass 32, count 0 2006.210.08:15:12.25#ibcon#about to read 5, iclass 32, count 0 2006.210.08:15:12.25#ibcon#read 5, iclass 32, count 0 2006.210.08:15:12.25#ibcon#about to read 6, iclass 32, count 0 2006.210.08:15:12.25#ibcon#read 6, iclass 32, count 0 2006.210.08:15:12.25#ibcon#end of sib2, iclass 32, count 0 2006.210.08:15:12.25#ibcon#*after write, iclass 32, count 0 2006.210.08:15:12.25#ibcon#*before return 0, iclass 32, count 0 2006.210.08:15:12.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:12.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.210.08:15:12.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:15:12.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:15:12.25$vc4f8/vbbw=wide 2006.210.08:15:12.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:15:12.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:15:12.25#ibcon#ireg 8 cls_cnt 0 2006.210.08:15:12.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:15:12.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:15:12.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:15:12.32#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:15:12.32#ibcon#first serial, iclass 34, count 0 2006.210.08:15:12.32#ibcon#enter sib2, iclass 34, count 0 2006.210.08:15:12.32#ibcon#flushed, iclass 34, count 0 2006.210.08:15:12.32#ibcon#about to write, iclass 34, count 0 2006.210.08:15:12.32#ibcon#wrote, iclass 34, count 0 2006.210.08:15:12.32#ibcon#about to read 3, iclass 34, count 0 2006.210.08:15:12.34#ibcon#read 3, iclass 34, count 0 2006.210.08:15:12.34#ibcon#about to read 4, iclass 34, count 0 2006.210.08:15:12.34#ibcon#read 4, iclass 34, count 0 2006.210.08:15:12.34#ibcon#about to read 5, iclass 34, count 0 2006.210.08:15:12.34#ibcon#read 5, iclass 34, count 0 2006.210.08:15:12.34#ibcon#about to read 6, iclass 34, count 0 2006.210.08:15:12.34#ibcon#read 6, iclass 34, count 0 2006.210.08:15:12.34#ibcon#end of sib2, iclass 34, count 0 2006.210.08:15:12.34#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:15:12.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:15:12.34#ibcon#[27=BW32\r\n] 2006.210.08:15:12.34#ibcon#*before write, iclass 34, count 0 2006.210.08:15:12.34#ibcon#enter sib2, iclass 34, count 0 2006.210.08:15:12.34#ibcon#flushed, iclass 34, count 0 2006.210.08:15:12.34#ibcon#about to write, iclass 34, count 0 2006.210.08:15:12.34#ibcon#wrote, iclass 34, count 0 2006.210.08:15:12.34#ibcon#about to read 3, iclass 34, count 0 2006.210.08:15:12.37#ibcon#read 3, iclass 34, count 0 2006.210.08:15:12.37#ibcon#about to read 4, iclass 34, count 0 2006.210.08:15:12.37#ibcon#read 4, iclass 34, count 0 2006.210.08:15:12.37#ibcon#about to read 5, iclass 34, count 0 2006.210.08:15:12.37#ibcon#read 5, iclass 34, count 0 2006.210.08:15:12.37#ibcon#about to read 6, iclass 34, count 0 2006.210.08:15:12.37#ibcon#read 6, iclass 34, count 0 2006.210.08:15:12.37#ibcon#end of sib2, iclass 34, count 0 2006.210.08:15:12.37#ibcon#*after write, iclass 34, count 0 2006.210.08:15:12.37#ibcon#*before return 0, iclass 34, count 0 2006.210.08:15:12.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:15:12.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:15:12.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:15:12.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:15:12.37$4f8m12a/ifd4f 2006.210.08:15:12.37$ifd4f/lo= 2006.210.08:15:12.37$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:15:12.37$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:15:12.37$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:15:12.37$ifd4f/patch= 2006.210.08:15:12.37$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:15:12.37$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:15:12.37$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:15:12.37$4f8m12a/"form=m,16.000,1:2 2006.210.08:15:12.37$4f8m12a/"tpicd 2006.210.08:15:12.38$4f8m12a/echo=off 2006.210.08:15:12.38$4f8m12a/xlog=off 2006.210.08:15:12.38:!2006.210.08:15:40 2006.210.08:15:21.13#trakl#Source acquired 2006.210.08:15:21.13#flagr#flagr/antenna,acquired 2006.210.08:15:40.01:preob 2006.210.08:15:41.13/onsource/TRACKING 2006.210.08:15:41.13:!2006.210.08:15:50 2006.210.08:15:50.00:data_valid=on 2006.210.08:15:50.00:midob 2006.210.08:15:50.13/onsource/TRACKING 2006.210.08:15:50.13/wx/29.96,1006.4,84 2006.210.08:15:50.34/cable/+6.3955E-03 2006.210.08:15:51.43/va/01,08,usb,yes,28,30 2006.210.08:15:51.43/va/02,07,usb,yes,28,30 2006.210.08:15:51.43/va/03,06,usb,yes,30,30 2006.210.08:15:51.43/va/04,07,usb,yes,29,31 2006.210.08:15:51.43/va/05,07,usb,yes,30,32 2006.210.08:15:51.43/va/06,06,usb,yes,29,29 2006.210.08:15:51.43/va/07,06,usb,yes,30,30 2006.210.08:15:51.43/va/08,07,usb,yes,28,28 2006.210.08:15:51.66/valo/01,532.99,yes,locked 2006.210.08:15:51.66/valo/02,572.99,yes,locked 2006.210.08:15:51.66/valo/03,672.99,yes,locked 2006.210.08:15:51.66/valo/04,832.99,yes,locked 2006.210.08:15:51.66/valo/05,652.99,yes,locked 2006.210.08:15:51.66/valo/06,772.99,yes,locked 2006.210.08:15:51.66/valo/07,832.99,yes,locked 2006.210.08:15:51.66/valo/08,852.99,yes,locked 2006.210.08:15:52.75/vb/01,04,usb,yes,28,27 2006.210.08:15:52.75/vb/02,04,usb,yes,30,31 2006.210.08:15:52.75/vb/03,03,usb,yes,33,37 2006.210.08:15:52.75/vb/04,03,usb,yes,34,34 2006.210.08:15:52.75/vb/05,03,usb,yes,32,36 2006.210.08:15:52.75/vb/06,03,usb,yes,33,36 2006.210.08:15:52.75/vb/07,04,usb,yes,28,28 2006.210.08:15:52.75/vb/08,03,usb,yes,33,36 2006.210.08:15:52.98/vblo/01,632.99,yes,locked 2006.210.08:15:52.98/vblo/02,640.99,yes,locked 2006.210.08:15:52.98/vblo/03,656.99,yes,locked 2006.210.08:15:52.98/vblo/04,712.99,yes,locked 2006.210.08:15:52.98/vblo/05,744.99,yes,locked 2006.210.08:15:52.98/vblo/06,752.99,yes,locked 2006.210.08:15:52.98/vblo/07,734.99,yes,locked 2006.210.08:15:52.98/vblo/08,744.99,yes,locked 2006.210.08:15:53.13/vabw/8 2006.210.08:15:53.28/vbbw/8 2006.210.08:15:53.37/xfe/off,on,13.0 2006.210.08:15:53.74/ifatt/23,28,28,28 2006.210.08:15:54.07/fmout-gps/S +4.58E-07 2006.210.08:15:54.11:!2006.210.08:16:50 2006.210.08:16:50.01:data_valid=off 2006.210.08:16:50.01:postob 2006.210.08:16:50.18/cable/+6.3936E-03 2006.210.08:16:50.18/wx/29.92,1006.4,83 2006.210.08:16:51.07/fmout-gps/S +4.57E-07 2006.210.08:16:51.07:scan_name=210-0818,k06210,70 2006.210.08:16:51.07:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.210.08:16:52.14#flagr#flagr/antenna,new-source 2006.210.08:16:52.14:checkk5 2006.210.08:16:52.49/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:16:52.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:16:53.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:16:53.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:16:53.84/chk_obsdata//k5ts1/T2100815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:16:54.17/chk_obsdata//k5ts2/T2100815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:16:54.50/chk_obsdata//k5ts3/T2100815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:16:54.83/chk_obsdata//k5ts4/T2100815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:16:55.51/k5log//k5ts1_log_newline 2006.210.08:16:56.17/k5log//k5ts2_log_newline 2006.210.08:16:56.84/k5log//k5ts3_log_newline 2006.210.08:16:57.50/k5log//k5ts4_log_newline 2006.210.08:16:57.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:16:57.53:4f8m12a=2 2006.210.08:16:57.53$4f8m12a/echo=on 2006.210.08:16:57.53$4f8m12a/pcalon 2006.210.08:16:57.53$pcalon/"no phase cal control is implemented here 2006.210.08:16:57.53$4f8m12a/"tpicd=stop 2006.210.08:16:57.53$4f8m12a/vc4f8 2006.210.08:16:57.53$vc4f8/valo=1,532.99 2006.210.08:16:57.53#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:16:57.53#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:16:57.53#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:57.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:16:57.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:16:57.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:16:57.53#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:16:57.53#ibcon#first serial, iclass 7, count 0 2006.210.08:16:57.53#ibcon#enter sib2, iclass 7, count 0 2006.210.08:16:57.53#ibcon#flushed, iclass 7, count 0 2006.210.08:16:57.53#ibcon#about to write, iclass 7, count 0 2006.210.08:16:57.53#ibcon#wrote, iclass 7, count 0 2006.210.08:16:57.53#ibcon#about to read 3, iclass 7, count 0 2006.210.08:16:57.55#ibcon#read 3, iclass 7, count 0 2006.210.08:16:57.55#ibcon#about to read 4, iclass 7, count 0 2006.210.08:16:57.55#ibcon#read 4, iclass 7, count 0 2006.210.08:16:57.55#ibcon#about to read 5, iclass 7, count 0 2006.210.08:16:57.55#ibcon#read 5, iclass 7, count 0 2006.210.08:16:57.55#ibcon#about to read 6, iclass 7, count 0 2006.210.08:16:57.55#ibcon#read 6, iclass 7, count 0 2006.210.08:16:57.55#ibcon#end of sib2, iclass 7, count 0 2006.210.08:16:57.55#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:16:57.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:16:57.55#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:16:57.55#ibcon#*before write, iclass 7, count 0 2006.210.08:16:57.55#ibcon#enter sib2, iclass 7, count 0 2006.210.08:16:57.55#ibcon#flushed, iclass 7, count 0 2006.210.08:16:57.55#ibcon#about to write, iclass 7, count 0 2006.210.08:16:57.55#ibcon#wrote, iclass 7, count 0 2006.210.08:16:57.55#ibcon#about to read 3, iclass 7, count 0 2006.210.08:16:57.60#ibcon#read 3, iclass 7, count 0 2006.210.08:16:57.60#ibcon#about to read 4, iclass 7, count 0 2006.210.08:16:57.60#ibcon#read 4, iclass 7, count 0 2006.210.08:16:57.60#ibcon#about to read 5, iclass 7, count 0 2006.210.08:16:57.60#ibcon#read 5, iclass 7, count 0 2006.210.08:16:57.60#ibcon#about to read 6, iclass 7, count 0 2006.210.08:16:57.60#ibcon#read 6, iclass 7, count 0 2006.210.08:16:57.60#ibcon#end of sib2, iclass 7, count 0 2006.210.08:16:57.60#ibcon#*after write, iclass 7, count 0 2006.210.08:16:57.60#ibcon#*before return 0, iclass 7, count 0 2006.210.08:16:57.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:16:57.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:16:57.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:16:57.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:16:57.60$vc4f8/va=1,8 2006.210.08:16:57.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:16:57.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:16:57.60#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:57.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:16:57.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:16:57.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:16:57.60#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:16:57.60#ibcon#first serial, iclass 11, count 2 2006.210.08:16:57.60#ibcon#enter sib2, iclass 11, count 2 2006.210.08:16:57.60#ibcon#flushed, iclass 11, count 2 2006.210.08:16:57.60#ibcon#about to write, iclass 11, count 2 2006.210.08:16:57.60#ibcon#wrote, iclass 11, count 2 2006.210.08:16:57.60#ibcon#about to read 3, iclass 11, count 2 2006.210.08:16:57.62#ibcon#read 3, iclass 11, count 2 2006.210.08:16:57.62#ibcon#about to read 4, iclass 11, count 2 2006.210.08:16:57.62#ibcon#read 4, iclass 11, count 2 2006.210.08:16:57.62#ibcon#about to read 5, iclass 11, count 2 2006.210.08:16:57.62#ibcon#read 5, iclass 11, count 2 2006.210.08:16:57.62#ibcon#about to read 6, iclass 11, count 2 2006.210.08:16:57.62#ibcon#read 6, iclass 11, count 2 2006.210.08:16:57.62#ibcon#end of sib2, iclass 11, count 2 2006.210.08:16:57.62#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:16:57.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:16:57.62#ibcon#[25=AT01-08\r\n] 2006.210.08:16:57.62#ibcon#*before write, iclass 11, count 2 2006.210.08:16:57.62#ibcon#enter sib2, iclass 11, count 2 2006.210.08:16:57.62#ibcon#flushed, iclass 11, count 2 2006.210.08:16:57.62#ibcon#about to write, iclass 11, count 2 2006.210.08:16:57.62#ibcon#wrote, iclass 11, count 2 2006.210.08:16:57.62#ibcon#about to read 3, iclass 11, count 2 2006.210.08:16:57.65#ibcon#read 3, iclass 11, count 2 2006.210.08:16:57.65#ibcon#about to read 4, iclass 11, count 2 2006.210.08:16:57.65#ibcon#read 4, iclass 11, count 2 2006.210.08:16:57.65#ibcon#about to read 5, iclass 11, count 2 2006.210.08:16:57.65#ibcon#read 5, iclass 11, count 2 2006.210.08:16:57.65#ibcon#about to read 6, iclass 11, count 2 2006.210.08:16:57.65#ibcon#read 6, iclass 11, count 2 2006.210.08:16:57.65#ibcon#end of sib2, iclass 11, count 2 2006.210.08:16:57.65#ibcon#*after write, iclass 11, count 2 2006.210.08:16:57.65#ibcon#*before return 0, iclass 11, count 2 2006.210.08:16:57.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:16:57.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:16:57.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:16:57.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:57.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:16:57.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:16:57.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:16:57.77#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:16:57.77#ibcon#first serial, iclass 11, count 0 2006.210.08:16:57.77#ibcon#enter sib2, iclass 11, count 0 2006.210.08:16:57.77#ibcon#flushed, iclass 11, count 0 2006.210.08:16:57.77#ibcon#about to write, iclass 11, count 0 2006.210.08:16:57.77#ibcon#wrote, iclass 11, count 0 2006.210.08:16:57.77#ibcon#about to read 3, iclass 11, count 0 2006.210.08:16:57.79#ibcon#read 3, iclass 11, count 0 2006.210.08:16:57.79#ibcon#about to read 4, iclass 11, count 0 2006.210.08:16:57.79#ibcon#read 4, iclass 11, count 0 2006.210.08:16:57.79#ibcon#about to read 5, iclass 11, count 0 2006.210.08:16:57.79#ibcon#read 5, iclass 11, count 0 2006.210.08:16:57.79#ibcon#about to read 6, iclass 11, count 0 2006.210.08:16:57.79#ibcon#read 6, iclass 11, count 0 2006.210.08:16:57.79#ibcon#end of sib2, iclass 11, count 0 2006.210.08:16:57.79#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:16:57.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:16:57.79#ibcon#[25=USB\r\n] 2006.210.08:16:57.79#ibcon#*before write, iclass 11, count 0 2006.210.08:16:57.79#ibcon#enter sib2, iclass 11, count 0 2006.210.08:16:57.79#ibcon#flushed, iclass 11, count 0 2006.210.08:16:57.79#ibcon#about to write, iclass 11, count 0 2006.210.08:16:57.79#ibcon#wrote, iclass 11, count 0 2006.210.08:16:57.79#ibcon#about to read 3, iclass 11, count 0 2006.210.08:16:57.82#ibcon#read 3, iclass 11, count 0 2006.210.08:16:57.82#ibcon#about to read 4, iclass 11, count 0 2006.210.08:16:57.82#ibcon#read 4, iclass 11, count 0 2006.210.08:16:57.82#ibcon#about to read 5, iclass 11, count 0 2006.210.08:16:57.82#ibcon#read 5, iclass 11, count 0 2006.210.08:16:57.82#ibcon#about to read 6, iclass 11, count 0 2006.210.08:16:57.82#ibcon#read 6, iclass 11, count 0 2006.210.08:16:57.82#ibcon#end of sib2, iclass 11, count 0 2006.210.08:16:57.82#ibcon#*after write, iclass 11, count 0 2006.210.08:16:57.82#ibcon#*before return 0, iclass 11, count 0 2006.210.08:16:57.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:16:57.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:16:57.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:16:57.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:16:57.82$vc4f8/valo=2,572.99 2006.210.08:16:57.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:16:57.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:16:57.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:57.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:16:57.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:16:57.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:16:57.82#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:16:57.82#ibcon#first serial, iclass 13, count 0 2006.210.08:16:57.82#ibcon#enter sib2, iclass 13, count 0 2006.210.08:16:57.82#ibcon#flushed, iclass 13, count 0 2006.210.08:16:57.82#ibcon#about to write, iclass 13, count 0 2006.210.08:16:57.82#ibcon#wrote, iclass 13, count 0 2006.210.08:16:57.82#ibcon#about to read 3, iclass 13, count 0 2006.210.08:16:57.84#ibcon#read 3, iclass 13, count 0 2006.210.08:16:57.84#ibcon#about to read 4, iclass 13, count 0 2006.210.08:16:57.84#ibcon#read 4, iclass 13, count 0 2006.210.08:16:57.84#ibcon#about to read 5, iclass 13, count 0 2006.210.08:16:57.84#ibcon#read 5, iclass 13, count 0 2006.210.08:16:57.84#ibcon#about to read 6, iclass 13, count 0 2006.210.08:16:57.84#ibcon#read 6, iclass 13, count 0 2006.210.08:16:57.84#ibcon#end of sib2, iclass 13, count 0 2006.210.08:16:57.84#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:16:57.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:16:57.84#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:16:57.84#ibcon#*before write, iclass 13, count 0 2006.210.08:16:57.84#ibcon#enter sib2, iclass 13, count 0 2006.210.08:16:57.84#ibcon#flushed, iclass 13, count 0 2006.210.08:16:57.84#ibcon#about to write, iclass 13, count 0 2006.210.08:16:57.84#ibcon#wrote, iclass 13, count 0 2006.210.08:16:57.84#ibcon#about to read 3, iclass 13, count 0 2006.210.08:16:57.88#ibcon#read 3, iclass 13, count 0 2006.210.08:16:57.88#ibcon#about to read 4, iclass 13, count 0 2006.210.08:16:57.88#ibcon#read 4, iclass 13, count 0 2006.210.08:16:57.88#ibcon#about to read 5, iclass 13, count 0 2006.210.08:16:57.88#ibcon#read 5, iclass 13, count 0 2006.210.08:16:57.88#ibcon#about to read 6, iclass 13, count 0 2006.210.08:16:57.88#ibcon#read 6, iclass 13, count 0 2006.210.08:16:57.88#ibcon#end of sib2, iclass 13, count 0 2006.210.08:16:57.88#ibcon#*after write, iclass 13, count 0 2006.210.08:16:57.88#ibcon#*before return 0, iclass 13, count 0 2006.210.08:16:57.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:16:57.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:16:57.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:16:57.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:16:57.88$vc4f8/va=2,7 2006.210.08:16:57.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:16:57.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:16:57.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:57.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:16:57.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:16:57.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:16:57.94#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:16:57.94#ibcon#first serial, iclass 15, count 2 2006.210.08:16:57.94#ibcon#enter sib2, iclass 15, count 2 2006.210.08:16:57.94#ibcon#flushed, iclass 15, count 2 2006.210.08:16:57.94#ibcon#about to write, iclass 15, count 2 2006.210.08:16:57.94#ibcon#wrote, iclass 15, count 2 2006.210.08:16:57.94#ibcon#about to read 3, iclass 15, count 2 2006.210.08:16:57.96#ibcon#read 3, iclass 15, count 2 2006.210.08:16:57.96#ibcon#about to read 4, iclass 15, count 2 2006.210.08:16:57.96#ibcon#read 4, iclass 15, count 2 2006.210.08:16:57.96#ibcon#about to read 5, iclass 15, count 2 2006.210.08:16:57.96#ibcon#read 5, iclass 15, count 2 2006.210.08:16:57.96#ibcon#about to read 6, iclass 15, count 2 2006.210.08:16:57.96#ibcon#read 6, iclass 15, count 2 2006.210.08:16:57.96#ibcon#end of sib2, iclass 15, count 2 2006.210.08:16:57.96#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:16:57.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:16:57.96#ibcon#[25=AT02-07\r\n] 2006.210.08:16:57.96#ibcon#*before write, iclass 15, count 2 2006.210.08:16:57.96#ibcon#enter sib2, iclass 15, count 2 2006.210.08:16:57.96#ibcon#flushed, iclass 15, count 2 2006.210.08:16:57.96#ibcon#about to write, iclass 15, count 2 2006.210.08:16:57.96#ibcon#wrote, iclass 15, count 2 2006.210.08:16:57.96#ibcon#about to read 3, iclass 15, count 2 2006.210.08:16:57.99#ibcon#read 3, iclass 15, count 2 2006.210.08:16:57.99#ibcon#about to read 4, iclass 15, count 2 2006.210.08:16:57.99#ibcon#read 4, iclass 15, count 2 2006.210.08:16:57.99#ibcon#about to read 5, iclass 15, count 2 2006.210.08:16:57.99#ibcon#read 5, iclass 15, count 2 2006.210.08:16:57.99#ibcon#about to read 6, iclass 15, count 2 2006.210.08:16:57.99#ibcon#read 6, iclass 15, count 2 2006.210.08:16:57.99#ibcon#end of sib2, iclass 15, count 2 2006.210.08:16:57.99#ibcon#*after write, iclass 15, count 2 2006.210.08:16:57.99#ibcon#*before return 0, iclass 15, count 2 2006.210.08:16:57.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:16:57.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:16:57.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:16:57.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:57.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:16:58.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:16:58.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:16:58.11#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:16:58.11#ibcon#first serial, iclass 15, count 0 2006.210.08:16:58.11#ibcon#enter sib2, iclass 15, count 0 2006.210.08:16:58.11#ibcon#flushed, iclass 15, count 0 2006.210.08:16:58.11#ibcon#about to write, iclass 15, count 0 2006.210.08:16:58.11#ibcon#wrote, iclass 15, count 0 2006.210.08:16:58.11#ibcon#about to read 3, iclass 15, count 0 2006.210.08:16:58.13#ibcon#read 3, iclass 15, count 0 2006.210.08:16:58.13#ibcon#about to read 4, iclass 15, count 0 2006.210.08:16:58.13#ibcon#read 4, iclass 15, count 0 2006.210.08:16:58.13#ibcon#about to read 5, iclass 15, count 0 2006.210.08:16:58.13#ibcon#read 5, iclass 15, count 0 2006.210.08:16:58.13#ibcon#about to read 6, iclass 15, count 0 2006.210.08:16:58.13#ibcon#read 6, iclass 15, count 0 2006.210.08:16:58.13#ibcon#end of sib2, iclass 15, count 0 2006.210.08:16:58.13#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:16:58.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:16:58.13#ibcon#[25=USB\r\n] 2006.210.08:16:58.13#ibcon#*before write, iclass 15, count 0 2006.210.08:16:58.13#ibcon#enter sib2, iclass 15, count 0 2006.210.08:16:58.13#ibcon#flushed, iclass 15, count 0 2006.210.08:16:58.13#ibcon#about to write, iclass 15, count 0 2006.210.08:16:58.13#ibcon#wrote, iclass 15, count 0 2006.210.08:16:58.13#ibcon#about to read 3, iclass 15, count 0 2006.210.08:16:58.16#ibcon#read 3, iclass 15, count 0 2006.210.08:16:58.16#ibcon#about to read 4, iclass 15, count 0 2006.210.08:16:58.16#ibcon#read 4, iclass 15, count 0 2006.210.08:16:58.16#ibcon#about to read 5, iclass 15, count 0 2006.210.08:16:58.16#ibcon#read 5, iclass 15, count 0 2006.210.08:16:58.16#ibcon#about to read 6, iclass 15, count 0 2006.210.08:16:58.16#ibcon#read 6, iclass 15, count 0 2006.210.08:16:58.16#ibcon#end of sib2, iclass 15, count 0 2006.210.08:16:58.16#ibcon#*after write, iclass 15, count 0 2006.210.08:16:58.16#ibcon#*before return 0, iclass 15, count 0 2006.210.08:16:58.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:16:58.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:16:58.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:16:58.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:16:58.16$vc4f8/valo=3,672.99 2006.210.08:16:58.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:16:58.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:16:58.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:58.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:16:58.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:16:58.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:16:58.16#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:16:58.16#ibcon#first serial, iclass 17, count 0 2006.210.08:16:58.16#ibcon#enter sib2, iclass 17, count 0 2006.210.08:16:58.16#ibcon#flushed, iclass 17, count 0 2006.210.08:16:58.16#ibcon#about to write, iclass 17, count 0 2006.210.08:16:58.16#ibcon#wrote, iclass 17, count 0 2006.210.08:16:58.16#ibcon#about to read 3, iclass 17, count 0 2006.210.08:16:58.18#ibcon#read 3, iclass 17, count 0 2006.210.08:16:58.18#ibcon#about to read 4, iclass 17, count 0 2006.210.08:16:58.18#ibcon#read 4, iclass 17, count 0 2006.210.08:16:58.18#ibcon#about to read 5, iclass 17, count 0 2006.210.08:16:58.18#ibcon#read 5, iclass 17, count 0 2006.210.08:16:58.18#ibcon#about to read 6, iclass 17, count 0 2006.210.08:16:58.18#ibcon#read 6, iclass 17, count 0 2006.210.08:16:58.18#ibcon#end of sib2, iclass 17, count 0 2006.210.08:16:58.18#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:16:58.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:16:58.18#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:16:58.18#ibcon#*before write, iclass 17, count 0 2006.210.08:16:58.18#ibcon#enter sib2, iclass 17, count 0 2006.210.08:16:58.18#ibcon#flushed, iclass 17, count 0 2006.210.08:16:58.18#ibcon#about to write, iclass 17, count 0 2006.210.08:16:58.18#ibcon#wrote, iclass 17, count 0 2006.210.08:16:58.18#ibcon#about to read 3, iclass 17, count 0 2006.210.08:16:58.22#ibcon#read 3, iclass 17, count 0 2006.210.08:16:58.22#ibcon#about to read 4, iclass 17, count 0 2006.210.08:16:58.22#ibcon#read 4, iclass 17, count 0 2006.210.08:16:58.22#ibcon#about to read 5, iclass 17, count 0 2006.210.08:16:58.22#ibcon#read 5, iclass 17, count 0 2006.210.08:16:58.22#ibcon#about to read 6, iclass 17, count 0 2006.210.08:16:58.22#ibcon#read 6, iclass 17, count 0 2006.210.08:16:58.22#ibcon#end of sib2, iclass 17, count 0 2006.210.08:16:58.22#ibcon#*after write, iclass 17, count 0 2006.210.08:16:58.22#ibcon#*before return 0, iclass 17, count 0 2006.210.08:16:58.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:16:58.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:16:58.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:16:58.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:16:58.22$vc4f8/va=3,6 2006.210.08:16:58.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:16:58.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:16:58.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:58.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:16:58.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:16:58.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:16:58.28#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:16:58.28#ibcon#first serial, iclass 19, count 2 2006.210.08:16:58.28#ibcon#enter sib2, iclass 19, count 2 2006.210.08:16:58.28#ibcon#flushed, iclass 19, count 2 2006.210.08:16:58.28#ibcon#about to write, iclass 19, count 2 2006.210.08:16:58.28#ibcon#wrote, iclass 19, count 2 2006.210.08:16:58.28#ibcon#about to read 3, iclass 19, count 2 2006.210.08:16:58.30#ibcon#read 3, iclass 19, count 2 2006.210.08:16:58.30#ibcon#about to read 4, iclass 19, count 2 2006.210.08:16:58.30#ibcon#read 4, iclass 19, count 2 2006.210.08:16:58.30#ibcon#about to read 5, iclass 19, count 2 2006.210.08:16:58.30#ibcon#read 5, iclass 19, count 2 2006.210.08:16:58.30#ibcon#about to read 6, iclass 19, count 2 2006.210.08:16:58.30#ibcon#read 6, iclass 19, count 2 2006.210.08:16:58.30#ibcon#end of sib2, iclass 19, count 2 2006.210.08:16:58.30#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:16:58.30#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:16:58.30#ibcon#[25=AT03-06\r\n] 2006.210.08:16:58.30#ibcon#*before write, iclass 19, count 2 2006.210.08:16:58.30#ibcon#enter sib2, iclass 19, count 2 2006.210.08:16:58.30#ibcon#flushed, iclass 19, count 2 2006.210.08:16:58.30#ibcon#about to write, iclass 19, count 2 2006.210.08:16:58.30#ibcon#wrote, iclass 19, count 2 2006.210.08:16:58.30#ibcon#about to read 3, iclass 19, count 2 2006.210.08:16:58.33#ibcon#read 3, iclass 19, count 2 2006.210.08:16:58.33#ibcon#about to read 4, iclass 19, count 2 2006.210.08:16:58.33#ibcon#read 4, iclass 19, count 2 2006.210.08:16:58.33#ibcon#about to read 5, iclass 19, count 2 2006.210.08:16:58.33#ibcon#read 5, iclass 19, count 2 2006.210.08:16:58.33#ibcon#about to read 6, iclass 19, count 2 2006.210.08:16:58.33#ibcon#read 6, iclass 19, count 2 2006.210.08:16:58.33#ibcon#end of sib2, iclass 19, count 2 2006.210.08:16:58.33#ibcon#*after write, iclass 19, count 2 2006.210.08:16:58.33#ibcon#*before return 0, iclass 19, count 2 2006.210.08:16:58.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:16:58.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:16:58.33#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:16:58.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:58.33#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:16:58.45#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:16:58.45#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:16:58.45#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:16:58.45#ibcon#first serial, iclass 19, count 0 2006.210.08:16:58.45#ibcon#enter sib2, iclass 19, count 0 2006.210.08:16:58.45#ibcon#flushed, iclass 19, count 0 2006.210.08:16:58.45#ibcon#about to write, iclass 19, count 0 2006.210.08:16:58.45#ibcon#wrote, iclass 19, count 0 2006.210.08:16:58.45#ibcon#about to read 3, iclass 19, count 0 2006.210.08:16:58.47#ibcon#read 3, iclass 19, count 0 2006.210.08:16:58.47#ibcon#about to read 4, iclass 19, count 0 2006.210.08:16:58.47#ibcon#read 4, iclass 19, count 0 2006.210.08:16:58.47#ibcon#about to read 5, iclass 19, count 0 2006.210.08:16:58.47#ibcon#read 5, iclass 19, count 0 2006.210.08:16:58.47#ibcon#about to read 6, iclass 19, count 0 2006.210.08:16:58.47#ibcon#read 6, iclass 19, count 0 2006.210.08:16:58.47#ibcon#end of sib2, iclass 19, count 0 2006.210.08:16:58.47#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:16:58.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:16:58.47#ibcon#[25=USB\r\n] 2006.210.08:16:58.47#ibcon#*before write, iclass 19, count 0 2006.210.08:16:58.47#ibcon#enter sib2, iclass 19, count 0 2006.210.08:16:58.47#ibcon#flushed, iclass 19, count 0 2006.210.08:16:58.47#ibcon#about to write, iclass 19, count 0 2006.210.08:16:58.47#ibcon#wrote, iclass 19, count 0 2006.210.08:16:58.47#ibcon#about to read 3, iclass 19, count 0 2006.210.08:16:58.50#ibcon#read 3, iclass 19, count 0 2006.210.08:16:58.50#ibcon#about to read 4, iclass 19, count 0 2006.210.08:16:58.50#ibcon#read 4, iclass 19, count 0 2006.210.08:16:58.50#ibcon#about to read 5, iclass 19, count 0 2006.210.08:16:58.50#ibcon#read 5, iclass 19, count 0 2006.210.08:16:58.50#ibcon#about to read 6, iclass 19, count 0 2006.210.08:16:58.50#ibcon#read 6, iclass 19, count 0 2006.210.08:16:58.50#ibcon#end of sib2, iclass 19, count 0 2006.210.08:16:58.50#ibcon#*after write, iclass 19, count 0 2006.210.08:16:58.50#ibcon#*before return 0, iclass 19, count 0 2006.210.08:16:58.50#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:16:58.50#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:16:58.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:16:58.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:16:58.50$vc4f8/valo=4,832.99 2006.210.08:16:58.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:16:58.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:16:58.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:58.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:16:58.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:16:58.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:16:58.50#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:16:58.50#ibcon#first serial, iclass 21, count 0 2006.210.08:16:58.50#ibcon#enter sib2, iclass 21, count 0 2006.210.08:16:58.50#ibcon#flushed, iclass 21, count 0 2006.210.08:16:58.50#ibcon#about to write, iclass 21, count 0 2006.210.08:16:58.50#ibcon#wrote, iclass 21, count 0 2006.210.08:16:58.50#ibcon#about to read 3, iclass 21, count 0 2006.210.08:16:58.52#ibcon#read 3, iclass 21, count 0 2006.210.08:16:58.52#ibcon#about to read 4, iclass 21, count 0 2006.210.08:16:58.52#ibcon#read 4, iclass 21, count 0 2006.210.08:16:58.52#ibcon#about to read 5, iclass 21, count 0 2006.210.08:16:58.52#ibcon#read 5, iclass 21, count 0 2006.210.08:16:58.52#ibcon#about to read 6, iclass 21, count 0 2006.210.08:16:58.52#ibcon#read 6, iclass 21, count 0 2006.210.08:16:58.52#ibcon#end of sib2, iclass 21, count 0 2006.210.08:16:58.52#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:16:58.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:16:58.52#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:16:58.52#ibcon#*before write, iclass 21, count 0 2006.210.08:16:58.52#ibcon#enter sib2, iclass 21, count 0 2006.210.08:16:58.52#ibcon#flushed, iclass 21, count 0 2006.210.08:16:58.52#ibcon#about to write, iclass 21, count 0 2006.210.08:16:58.52#ibcon#wrote, iclass 21, count 0 2006.210.08:16:58.52#ibcon#about to read 3, iclass 21, count 0 2006.210.08:16:58.56#ibcon#read 3, iclass 21, count 0 2006.210.08:16:58.56#ibcon#about to read 4, iclass 21, count 0 2006.210.08:16:58.56#ibcon#read 4, iclass 21, count 0 2006.210.08:16:58.56#ibcon#about to read 5, iclass 21, count 0 2006.210.08:16:58.56#ibcon#read 5, iclass 21, count 0 2006.210.08:16:58.56#ibcon#about to read 6, iclass 21, count 0 2006.210.08:16:58.56#ibcon#read 6, iclass 21, count 0 2006.210.08:16:58.56#ibcon#end of sib2, iclass 21, count 0 2006.210.08:16:58.56#ibcon#*after write, iclass 21, count 0 2006.210.08:16:58.56#ibcon#*before return 0, iclass 21, count 0 2006.210.08:16:58.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:16:58.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:16:58.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:16:58.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:16:58.56$vc4f8/va=4,7 2006.210.08:16:58.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:16:58.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:16:58.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:58.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:16:58.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:16:58.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:16:58.62#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:16:58.62#ibcon#first serial, iclass 23, count 2 2006.210.08:16:58.62#ibcon#enter sib2, iclass 23, count 2 2006.210.08:16:58.62#ibcon#flushed, iclass 23, count 2 2006.210.08:16:58.62#ibcon#about to write, iclass 23, count 2 2006.210.08:16:58.62#ibcon#wrote, iclass 23, count 2 2006.210.08:16:58.62#ibcon#about to read 3, iclass 23, count 2 2006.210.08:16:58.64#ibcon#read 3, iclass 23, count 2 2006.210.08:16:58.64#ibcon#about to read 4, iclass 23, count 2 2006.210.08:16:58.64#ibcon#read 4, iclass 23, count 2 2006.210.08:16:58.64#ibcon#about to read 5, iclass 23, count 2 2006.210.08:16:58.64#ibcon#read 5, iclass 23, count 2 2006.210.08:16:58.64#ibcon#about to read 6, iclass 23, count 2 2006.210.08:16:58.64#ibcon#read 6, iclass 23, count 2 2006.210.08:16:58.64#ibcon#end of sib2, iclass 23, count 2 2006.210.08:16:58.64#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:16:58.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:16:58.64#ibcon#[25=AT04-07\r\n] 2006.210.08:16:58.64#ibcon#*before write, iclass 23, count 2 2006.210.08:16:58.64#ibcon#enter sib2, iclass 23, count 2 2006.210.08:16:58.64#ibcon#flushed, iclass 23, count 2 2006.210.08:16:58.64#ibcon#about to write, iclass 23, count 2 2006.210.08:16:58.64#ibcon#wrote, iclass 23, count 2 2006.210.08:16:58.64#ibcon#about to read 3, iclass 23, count 2 2006.210.08:16:58.67#ibcon#read 3, iclass 23, count 2 2006.210.08:16:58.67#ibcon#about to read 4, iclass 23, count 2 2006.210.08:16:58.67#ibcon#read 4, iclass 23, count 2 2006.210.08:16:58.67#ibcon#about to read 5, iclass 23, count 2 2006.210.08:16:58.67#ibcon#read 5, iclass 23, count 2 2006.210.08:16:58.67#ibcon#about to read 6, iclass 23, count 2 2006.210.08:16:58.67#ibcon#read 6, iclass 23, count 2 2006.210.08:16:58.67#ibcon#end of sib2, iclass 23, count 2 2006.210.08:16:58.67#ibcon#*after write, iclass 23, count 2 2006.210.08:16:58.67#ibcon#*before return 0, iclass 23, count 2 2006.210.08:16:58.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:16:58.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:16:58.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:16:58.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:58.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:16:58.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:16:58.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:16:58.79#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:16:58.79#ibcon#first serial, iclass 23, count 0 2006.210.08:16:58.79#ibcon#enter sib2, iclass 23, count 0 2006.210.08:16:58.79#ibcon#flushed, iclass 23, count 0 2006.210.08:16:58.79#ibcon#about to write, iclass 23, count 0 2006.210.08:16:58.79#ibcon#wrote, iclass 23, count 0 2006.210.08:16:58.79#ibcon#about to read 3, iclass 23, count 0 2006.210.08:16:58.81#ibcon#read 3, iclass 23, count 0 2006.210.08:16:58.81#ibcon#about to read 4, iclass 23, count 0 2006.210.08:16:58.81#ibcon#read 4, iclass 23, count 0 2006.210.08:16:58.81#ibcon#about to read 5, iclass 23, count 0 2006.210.08:16:58.81#ibcon#read 5, iclass 23, count 0 2006.210.08:16:58.81#ibcon#about to read 6, iclass 23, count 0 2006.210.08:16:58.81#ibcon#read 6, iclass 23, count 0 2006.210.08:16:58.81#ibcon#end of sib2, iclass 23, count 0 2006.210.08:16:58.81#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:16:58.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:16:58.81#ibcon#[25=USB\r\n] 2006.210.08:16:58.81#ibcon#*before write, iclass 23, count 0 2006.210.08:16:58.81#ibcon#enter sib2, iclass 23, count 0 2006.210.08:16:58.81#ibcon#flushed, iclass 23, count 0 2006.210.08:16:58.81#ibcon#about to write, iclass 23, count 0 2006.210.08:16:58.81#ibcon#wrote, iclass 23, count 0 2006.210.08:16:58.81#ibcon#about to read 3, iclass 23, count 0 2006.210.08:16:58.84#ibcon#read 3, iclass 23, count 0 2006.210.08:16:58.84#ibcon#about to read 4, iclass 23, count 0 2006.210.08:16:58.84#ibcon#read 4, iclass 23, count 0 2006.210.08:16:58.84#ibcon#about to read 5, iclass 23, count 0 2006.210.08:16:58.84#ibcon#read 5, iclass 23, count 0 2006.210.08:16:58.84#ibcon#about to read 6, iclass 23, count 0 2006.210.08:16:58.84#ibcon#read 6, iclass 23, count 0 2006.210.08:16:58.84#ibcon#end of sib2, iclass 23, count 0 2006.210.08:16:58.84#ibcon#*after write, iclass 23, count 0 2006.210.08:16:58.84#ibcon#*before return 0, iclass 23, count 0 2006.210.08:16:58.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:16:58.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:16:58.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:16:58.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:16:58.84$vc4f8/valo=5,652.99 2006.210.08:16:58.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:16:58.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:16:58.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:58.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:16:58.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:16:58.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:16:58.84#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:16:58.84#ibcon#first serial, iclass 25, count 0 2006.210.08:16:58.84#ibcon#enter sib2, iclass 25, count 0 2006.210.08:16:58.84#ibcon#flushed, iclass 25, count 0 2006.210.08:16:58.84#ibcon#about to write, iclass 25, count 0 2006.210.08:16:58.84#ibcon#wrote, iclass 25, count 0 2006.210.08:16:58.84#ibcon#about to read 3, iclass 25, count 0 2006.210.08:16:58.86#ibcon#read 3, iclass 25, count 0 2006.210.08:16:58.86#ibcon#about to read 4, iclass 25, count 0 2006.210.08:16:58.86#ibcon#read 4, iclass 25, count 0 2006.210.08:16:58.86#ibcon#about to read 5, iclass 25, count 0 2006.210.08:16:58.86#ibcon#read 5, iclass 25, count 0 2006.210.08:16:58.86#ibcon#about to read 6, iclass 25, count 0 2006.210.08:16:58.86#ibcon#read 6, iclass 25, count 0 2006.210.08:16:58.86#ibcon#end of sib2, iclass 25, count 0 2006.210.08:16:58.86#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:16:58.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:16:58.86#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:16:58.86#ibcon#*before write, iclass 25, count 0 2006.210.08:16:58.86#ibcon#enter sib2, iclass 25, count 0 2006.210.08:16:58.86#ibcon#flushed, iclass 25, count 0 2006.210.08:16:58.86#ibcon#about to write, iclass 25, count 0 2006.210.08:16:58.86#ibcon#wrote, iclass 25, count 0 2006.210.08:16:58.86#ibcon#about to read 3, iclass 25, count 0 2006.210.08:16:58.90#ibcon#read 3, iclass 25, count 0 2006.210.08:16:58.90#ibcon#about to read 4, iclass 25, count 0 2006.210.08:16:58.90#ibcon#read 4, iclass 25, count 0 2006.210.08:16:58.90#ibcon#about to read 5, iclass 25, count 0 2006.210.08:16:58.90#ibcon#read 5, iclass 25, count 0 2006.210.08:16:58.90#ibcon#about to read 6, iclass 25, count 0 2006.210.08:16:58.90#ibcon#read 6, iclass 25, count 0 2006.210.08:16:58.90#ibcon#end of sib2, iclass 25, count 0 2006.210.08:16:58.90#ibcon#*after write, iclass 25, count 0 2006.210.08:16:58.90#ibcon#*before return 0, iclass 25, count 0 2006.210.08:16:58.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:16:58.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:16:58.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:16:58.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:16:58.90$vc4f8/va=5,7 2006.210.08:16:58.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:16:58.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:16:58.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:58.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:16:58.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:16:58.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:16:58.96#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:16:58.96#ibcon#first serial, iclass 27, count 2 2006.210.08:16:58.96#ibcon#enter sib2, iclass 27, count 2 2006.210.08:16:58.96#ibcon#flushed, iclass 27, count 2 2006.210.08:16:58.96#ibcon#about to write, iclass 27, count 2 2006.210.08:16:58.96#ibcon#wrote, iclass 27, count 2 2006.210.08:16:58.96#ibcon#about to read 3, iclass 27, count 2 2006.210.08:16:58.98#ibcon#read 3, iclass 27, count 2 2006.210.08:16:58.98#ibcon#about to read 4, iclass 27, count 2 2006.210.08:16:58.98#ibcon#read 4, iclass 27, count 2 2006.210.08:16:58.98#ibcon#about to read 5, iclass 27, count 2 2006.210.08:16:58.98#ibcon#read 5, iclass 27, count 2 2006.210.08:16:58.98#ibcon#about to read 6, iclass 27, count 2 2006.210.08:16:58.98#ibcon#read 6, iclass 27, count 2 2006.210.08:16:58.98#ibcon#end of sib2, iclass 27, count 2 2006.210.08:16:58.98#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:16:58.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:16:58.98#ibcon#[25=AT05-07\r\n] 2006.210.08:16:58.98#ibcon#*before write, iclass 27, count 2 2006.210.08:16:58.98#ibcon#enter sib2, iclass 27, count 2 2006.210.08:16:58.98#ibcon#flushed, iclass 27, count 2 2006.210.08:16:58.98#ibcon#about to write, iclass 27, count 2 2006.210.08:16:58.98#ibcon#wrote, iclass 27, count 2 2006.210.08:16:58.98#ibcon#about to read 3, iclass 27, count 2 2006.210.08:16:59.01#ibcon#read 3, iclass 27, count 2 2006.210.08:16:59.01#ibcon#about to read 4, iclass 27, count 2 2006.210.08:16:59.01#ibcon#read 4, iclass 27, count 2 2006.210.08:16:59.01#ibcon#about to read 5, iclass 27, count 2 2006.210.08:16:59.01#ibcon#read 5, iclass 27, count 2 2006.210.08:16:59.01#ibcon#about to read 6, iclass 27, count 2 2006.210.08:16:59.01#ibcon#read 6, iclass 27, count 2 2006.210.08:16:59.01#ibcon#end of sib2, iclass 27, count 2 2006.210.08:16:59.01#ibcon#*after write, iclass 27, count 2 2006.210.08:16:59.01#ibcon#*before return 0, iclass 27, count 2 2006.210.08:16:59.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:16:59.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:16:59.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:16:59.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:59.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:16:59.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:16:59.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:16:59.13#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:16:59.13#ibcon#first serial, iclass 27, count 0 2006.210.08:16:59.13#ibcon#enter sib2, iclass 27, count 0 2006.210.08:16:59.13#ibcon#flushed, iclass 27, count 0 2006.210.08:16:59.13#ibcon#about to write, iclass 27, count 0 2006.210.08:16:59.13#ibcon#wrote, iclass 27, count 0 2006.210.08:16:59.13#ibcon#about to read 3, iclass 27, count 0 2006.210.08:16:59.15#ibcon#read 3, iclass 27, count 0 2006.210.08:16:59.15#ibcon#about to read 4, iclass 27, count 0 2006.210.08:16:59.15#ibcon#read 4, iclass 27, count 0 2006.210.08:16:59.15#ibcon#about to read 5, iclass 27, count 0 2006.210.08:16:59.15#ibcon#read 5, iclass 27, count 0 2006.210.08:16:59.15#ibcon#about to read 6, iclass 27, count 0 2006.210.08:16:59.15#ibcon#read 6, iclass 27, count 0 2006.210.08:16:59.15#ibcon#end of sib2, iclass 27, count 0 2006.210.08:16:59.15#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:16:59.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:16:59.15#ibcon#[25=USB\r\n] 2006.210.08:16:59.15#ibcon#*before write, iclass 27, count 0 2006.210.08:16:59.15#ibcon#enter sib2, iclass 27, count 0 2006.210.08:16:59.15#ibcon#flushed, iclass 27, count 0 2006.210.08:16:59.15#ibcon#about to write, iclass 27, count 0 2006.210.08:16:59.15#ibcon#wrote, iclass 27, count 0 2006.210.08:16:59.15#ibcon#about to read 3, iclass 27, count 0 2006.210.08:16:59.18#ibcon#read 3, iclass 27, count 0 2006.210.08:16:59.18#ibcon#about to read 4, iclass 27, count 0 2006.210.08:16:59.18#ibcon#read 4, iclass 27, count 0 2006.210.08:16:59.18#ibcon#about to read 5, iclass 27, count 0 2006.210.08:16:59.18#ibcon#read 5, iclass 27, count 0 2006.210.08:16:59.18#ibcon#about to read 6, iclass 27, count 0 2006.210.08:16:59.18#ibcon#read 6, iclass 27, count 0 2006.210.08:16:59.18#ibcon#end of sib2, iclass 27, count 0 2006.210.08:16:59.18#ibcon#*after write, iclass 27, count 0 2006.210.08:16:59.18#ibcon#*before return 0, iclass 27, count 0 2006.210.08:16:59.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:16:59.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:16:59.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:16:59.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:16:59.18$vc4f8/valo=6,772.99 2006.210.08:16:59.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:16:59.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:16:59.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:59.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:16:59.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:16:59.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:16:59.18#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:16:59.18#ibcon#first serial, iclass 29, count 0 2006.210.08:16:59.18#ibcon#enter sib2, iclass 29, count 0 2006.210.08:16:59.18#ibcon#flushed, iclass 29, count 0 2006.210.08:16:59.18#ibcon#about to write, iclass 29, count 0 2006.210.08:16:59.18#ibcon#wrote, iclass 29, count 0 2006.210.08:16:59.18#ibcon#about to read 3, iclass 29, count 0 2006.210.08:16:59.20#ibcon#read 3, iclass 29, count 0 2006.210.08:16:59.20#ibcon#about to read 4, iclass 29, count 0 2006.210.08:16:59.20#ibcon#read 4, iclass 29, count 0 2006.210.08:16:59.20#ibcon#about to read 5, iclass 29, count 0 2006.210.08:16:59.20#ibcon#read 5, iclass 29, count 0 2006.210.08:16:59.20#ibcon#about to read 6, iclass 29, count 0 2006.210.08:16:59.20#ibcon#read 6, iclass 29, count 0 2006.210.08:16:59.20#ibcon#end of sib2, iclass 29, count 0 2006.210.08:16:59.20#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:16:59.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:16:59.20#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:16:59.20#ibcon#*before write, iclass 29, count 0 2006.210.08:16:59.20#ibcon#enter sib2, iclass 29, count 0 2006.210.08:16:59.20#ibcon#flushed, iclass 29, count 0 2006.210.08:16:59.20#ibcon#about to write, iclass 29, count 0 2006.210.08:16:59.20#ibcon#wrote, iclass 29, count 0 2006.210.08:16:59.20#ibcon#about to read 3, iclass 29, count 0 2006.210.08:16:59.24#ibcon#read 3, iclass 29, count 0 2006.210.08:16:59.24#ibcon#about to read 4, iclass 29, count 0 2006.210.08:16:59.24#ibcon#read 4, iclass 29, count 0 2006.210.08:16:59.24#ibcon#about to read 5, iclass 29, count 0 2006.210.08:16:59.24#ibcon#read 5, iclass 29, count 0 2006.210.08:16:59.24#ibcon#about to read 6, iclass 29, count 0 2006.210.08:16:59.24#ibcon#read 6, iclass 29, count 0 2006.210.08:16:59.24#ibcon#end of sib2, iclass 29, count 0 2006.210.08:16:59.24#ibcon#*after write, iclass 29, count 0 2006.210.08:16:59.24#ibcon#*before return 0, iclass 29, count 0 2006.210.08:16:59.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:16:59.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:16:59.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:16:59.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:16:59.24$vc4f8/va=6,6 2006.210.08:16:59.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.08:16:59.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.08:16:59.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:59.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:16:59.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:16:59.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:16:59.30#ibcon#enter wrdev, iclass 31, count 2 2006.210.08:16:59.30#ibcon#first serial, iclass 31, count 2 2006.210.08:16:59.30#ibcon#enter sib2, iclass 31, count 2 2006.210.08:16:59.30#ibcon#flushed, iclass 31, count 2 2006.210.08:16:59.30#ibcon#about to write, iclass 31, count 2 2006.210.08:16:59.30#ibcon#wrote, iclass 31, count 2 2006.210.08:16:59.30#ibcon#about to read 3, iclass 31, count 2 2006.210.08:16:59.32#ibcon#read 3, iclass 31, count 2 2006.210.08:16:59.32#ibcon#about to read 4, iclass 31, count 2 2006.210.08:16:59.32#ibcon#read 4, iclass 31, count 2 2006.210.08:16:59.32#ibcon#about to read 5, iclass 31, count 2 2006.210.08:16:59.32#ibcon#read 5, iclass 31, count 2 2006.210.08:16:59.32#ibcon#about to read 6, iclass 31, count 2 2006.210.08:16:59.32#ibcon#read 6, iclass 31, count 2 2006.210.08:16:59.32#ibcon#end of sib2, iclass 31, count 2 2006.210.08:16:59.32#ibcon#*mode == 0, iclass 31, count 2 2006.210.08:16:59.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.08:16:59.32#ibcon#[25=AT06-06\r\n] 2006.210.08:16:59.32#ibcon#*before write, iclass 31, count 2 2006.210.08:16:59.32#ibcon#enter sib2, iclass 31, count 2 2006.210.08:16:59.32#ibcon#flushed, iclass 31, count 2 2006.210.08:16:59.32#ibcon#about to write, iclass 31, count 2 2006.210.08:16:59.32#ibcon#wrote, iclass 31, count 2 2006.210.08:16:59.32#ibcon#about to read 3, iclass 31, count 2 2006.210.08:16:59.35#ibcon#read 3, iclass 31, count 2 2006.210.08:16:59.35#ibcon#about to read 4, iclass 31, count 2 2006.210.08:16:59.35#ibcon#read 4, iclass 31, count 2 2006.210.08:16:59.35#ibcon#about to read 5, iclass 31, count 2 2006.210.08:16:59.35#ibcon#read 5, iclass 31, count 2 2006.210.08:16:59.35#ibcon#about to read 6, iclass 31, count 2 2006.210.08:16:59.35#ibcon#read 6, iclass 31, count 2 2006.210.08:16:59.35#ibcon#end of sib2, iclass 31, count 2 2006.210.08:16:59.35#ibcon#*after write, iclass 31, count 2 2006.210.08:16:59.35#ibcon#*before return 0, iclass 31, count 2 2006.210.08:16:59.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:16:59.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:16:59.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.08:16:59.35#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:59.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:16:59.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:16:59.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:16:59.47#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:16:59.47#ibcon#first serial, iclass 31, count 0 2006.210.08:16:59.47#ibcon#enter sib2, iclass 31, count 0 2006.210.08:16:59.47#ibcon#flushed, iclass 31, count 0 2006.210.08:16:59.47#ibcon#about to write, iclass 31, count 0 2006.210.08:16:59.47#ibcon#wrote, iclass 31, count 0 2006.210.08:16:59.47#ibcon#about to read 3, iclass 31, count 0 2006.210.08:16:59.49#ibcon#read 3, iclass 31, count 0 2006.210.08:16:59.49#ibcon#about to read 4, iclass 31, count 0 2006.210.08:16:59.49#ibcon#read 4, iclass 31, count 0 2006.210.08:16:59.49#ibcon#about to read 5, iclass 31, count 0 2006.210.08:16:59.49#ibcon#read 5, iclass 31, count 0 2006.210.08:16:59.49#ibcon#about to read 6, iclass 31, count 0 2006.210.08:16:59.49#ibcon#read 6, iclass 31, count 0 2006.210.08:16:59.49#ibcon#end of sib2, iclass 31, count 0 2006.210.08:16:59.49#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:16:59.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:16:59.49#ibcon#[25=USB\r\n] 2006.210.08:16:59.49#ibcon#*before write, iclass 31, count 0 2006.210.08:16:59.49#ibcon#enter sib2, iclass 31, count 0 2006.210.08:16:59.49#ibcon#flushed, iclass 31, count 0 2006.210.08:16:59.49#ibcon#about to write, iclass 31, count 0 2006.210.08:16:59.49#ibcon#wrote, iclass 31, count 0 2006.210.08:16:59.49#ibcon#about to read 3, iclass 31, count 0 2006.210.08:16:59.52#ibcon#read 3, iclass 31, count 0 2006.210.08:16:59.52#ibcon#about to read 4, iclass 31, count 0 2006.210.08:16:59.52#ibcon#read 4, iclass 31, count 0 2006.210.08:16:59.52#ibcon#about to read 5, iclass 31, count 0 2006.210.08:16:59.52#ibcon#read 5, iclass 31, count 0 2006.210.08:16:59.52#ibcon#about to read 6, iclass 31, count 0 2006.210.08:16:59.52#ibcon#read 6, iclass 31, count 0 2006.210.08:16:59.52#ibcon#end of sib2, iclass 31, count 0 2006.210.08:16:59.52#ibcon#*after write, iclass 31, count 0 2006.210.08:16:59.52#ibcon#*before return 0, iclass 31, count 0 2006.210.08:16:59.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:16:59.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:16:59.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:16:59.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:16:59.52$vc4f8/valo=7,832.99 2006.210.08:16:59.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:16:59.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:16:59.52#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:59.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:16:59.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:16:59.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:16:59.52#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:16:59.52#ibcon#first serial, iclass 33, count 0 2006.210.08:16:59.52#ibcon#enter sib2, iclass 33, count 0 2006.210.08:16:59.52#ibcon#flushed, iclass 33, count 0 2006.210.08:16:59.52#ibcon#about to write, iclass 33, count 0 2006.210.08:16:59.52#ibcon#wrote, iclass 33, count 0 2006.210.08:16:59.52#ibcon#about to read 3, iclass 33, count 0 2006.210.08:16:59.54#ibcon#read 3, iclass 33, count 0 2006.210.08:16:59.54#ibcon#about to read 4, iclass 33, count 0 2006.210.08:16:59.54#ibcon#read 4, iclass 33, count 0 2006.210.08:16:59.54#ibcon#about to read 5, iclass 33, count 0 2006.210.08:16:59.54#ibcon#read 5, iclass 33, count 0 2006.210.08:16:59.54#ibcon#about to read 6, iclass 33, count 0 2006.210.08:16:59.54#ibcon#read 6, iclass 33, count 0 2006.210.08:16:59.54#ibcon#end of sib2, iclass 33, count 0 2006.210.08:16:59.54#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:16:59.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:16:59.54#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:16:59.54#ibcon#*before write, iclass 33, count 0 2006.210.08:16:59.54#ibcon#enter sib2, iclass 33, count 0 2006.210.08:16:59.54#ibcon#flushed, iclass 33, count 0 2006.210.08:16:59.54#ibcon#about to write, iclass 33, count 0 2006.210.08:16:59.54#ibcon#wrote, iclass 33, count 0 2006.210.08:16:59.54#ibcon#about to read 3, iclass 33, count 0 2006.210.08:16:59.58#ibcon#read 3, iclass 33, count 0 2006.210.08:16:59.58#ibcon#about to read 4, iclass 33, count 0 2006.210.08:16:59.58#ibcon#read 4, iclass 33, count 0 2006.210.08:16:59.58#ibcon#about to read 5, iclass 33, count 0 2006.210.08:16:59.58#ibcon#read 5, iclass 33, count 0 2006.210.08:16:59.58#ibcon#about to read 6, iclass 33, count 0 2006.210.08:16:59.58#ibcon#read 6, iclass 33, count 0 2006.210.08:16:59.58#ibcon#end of sib2, iclass 33, count 0 2006.210.08:16:59.58#ibcon#*after write, iclass 33, count 0 2006.210.08:16:59.58#ibcon#*before return 0, iclass 33, count 0 2006.210.08:16:59.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:16:59.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:16:59.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:16:59.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:16:59.58$vc4f8/va=7,6 2006.210.08:16:59.58#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:16:59.58#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:16:59.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:59.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:16:59.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:16:59.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:16:59.64#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:16:59.64#ibcon#first serial, iclass 35, count 2 2006.210.08:16:59.64#ibcon#enter sib2, iclass 35, count 2 2006.210.08:16:59.64#ibcon#flushed, iclass 35, count 2 2006.210.08:16:59.64#ibcon#about to write, iclass 35, count 2 2006.210.08:16:59.64#ibcon#wrote, iclass 35, count 2 2006.210.08:16:59.64#ibcon#about to read 3, iclass 35, count 2 2006.210.08:16:59.66#ibcon#read 3, iclass 35, count 2 2006.210.08:16:59.66#ibcon#about to read 4, iclass 35, count 2 2006.210.08:16:59.66#ibcon#read 4, iclass 35, count 2 2006.210.08:16:59.66#ibcon#about to read 5, iclass 35, count 2 2006.210.08:16:59.66#ibcon#read 5, iclass 35, count 2 2006.210.08:16:59.66#ibcon#about to read 6, iclass 35, count 2 2006.210.08:16:59.66#ibcon#read 6, iclass 35, count 2 2006.210.08:16:59.66#ibcon#end of sib2, iclass 35, count 2 2006.210.08:16:59.66#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:16:59.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:16:59.66#ibcon#[25=AT07-06\r\n] 2006.210.08:16:59.66#ibcon#*before write, iclass 35, count 2 2006.210.08:16:59.66#ibcon#enter sib2, iclass 35, count 2 2006.210.08:16:59.66#ibcon#flushed, iclass 35, count 2 2006.210.08:16:59.66#ibcon#about to write, iclass 35, count 2 2006.210.08:16:59.66#ibcon#wrote, iclass 35, count 2 2006.210.08:16:59.66#ibcon#about to read 3, iclass 35, count 2 2006.210.08:16:59.69#ibcon#read 3, iclass 35, count 2 2006.210.08:16:59.69#ibcon#about to read 4, iclass 35, count 2 2006.210.08:16:59.69#ibcon#read 4, iclass 35, count 2 2006.210.08:16:59.69#ibcon#about to read 5, iclass 35, count 2 2006.210.08:16:59.69#ibcon#read 5, iclass 35, count 2 2006.210.08:16:59.69#ibcon#about to read 6, iclass 35, count 2 2006.210.08:16:59.69#ibcon#read 6, iclass 35, count 2 2006.210.08:16:59.69#ibcon#end of sib2, iclass 35, count 2 2006.210.08:16:59.69#ibcon#*after write, iclass 35, count 2 2006.210.08:16:59.69#ibcon#*before return 0, iclass 35, count 2 2006.210.08:16:59.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:16:59.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:16:59.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:16:59.69#ibcon#ireg 7 cls_cnt 0 2006.210.08:16:59.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:16:59.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:16:59.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:16:59.81#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:16:59.81#ibcon#first serial, iclass 35, count 0 2006.210.08:16:59.81#ibcon#enter sib2, iclass 35, count 0 2006.210.08:16:59.81#ibcon#flushed, iclass 35, count 0 2006.210.08:16:59.81#ibcon#about to write, iclass 35, count 0 2006.210.08:16:59.81#ibcon#wrote, iclass 35, count 0 2006.210.08:16:59.81#ibcon#about to read 3, iclass 35, count 0 2006.210.08:16:59.83#ibcon#read 3, iclass 35, count 0 2006.210.08:16:59.83#ibcon#about to read 4, iclass 35, count 0 2006.210.08:16:59.83#ibcon#read 4, iclass 35, count 0 2006.210.08:16:59.83#ibcon#about to read 5, iclass 35, count 0 2006.210.08:16:59.83#ibcon#read 5, iclass 35, count 0 2006.210.08:16:59.83#ibcon#about to read 6, iclass 35, count 0 2006.210.08:16:59.83#ibcon#read 6, iclass 35, count 0 2006.210.08:16:59.83#ibcon#end of sib2, iclass 35, count 0 2006.210.08:16:59.83#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:16:59.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:16:59.83#ibcon#[25=USB\r\n] 2006.210.08:16:59.83#ibcon#*before write, iclass 35, count 0 2006.210.08:16:59.83#ibcon#enter sib2, iclass 35, count 0 2006.210.08:16:59.83#ibcon#flushed, iclass 35, count 0 2006.210.08:16:59.83#ibcon#about to write, iclass 35, count 0 2006.210.08:16:59.83#ibcon#wrote, iclass 35, count 0 2006.210.08:16:59.83#ibcon#about to read 3, iclass 35, count 0 2006.210.08:16:59.86#ibcon#read 3, iclass 35, count 0 2006.210.08:16:59.86#ibcon#about to read 4, iclass 35, count 0 2006.210.08:16:59.86#ibcon#read 4, iclass 35, count 0 2006.210.08:16:59.86#ibcon#about to read 5, iclass 35, count 0 2006.210.08:16:59.86#ibcon#read 5, iclass 35, count 0 2006.210.08:16:59.86#ibcon#about to read 6, iclass 35, count 0 2006.210.08:16:59.86#ibcon#read 6, iclass 35, count 0 2006.210.08:16:59.86#ibcon#end of sib2, iclass 35, count 0 2006.210.08:16:59.86#ibcon#*after write, iclass 35, count 0 2006.210.08:16:59.86#ibcon#*before return 0, iclass 35, count 0 2006.210.08:16:59.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:16:59.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:16:59.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:16:59.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:16:59.86$vc4f8/valo=8,852.99 2006.210.08:16:59.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:16:59.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:16:59.86#ibcon#ireg 17 cls_cnt 0 2006.210.08:16:59.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:16:59.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:16:59.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:16:59.86#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:16:59.86#ibcon#first serial, iclass 37, count 0 2006.210.08:16:59.86#ibcon#enter sib2, iclass 37, count 0 2006.210.08:16:59.86#ibcon#flushed, iclass 37, count 0 2006.210.08:16:59.86#ibcon#about to write, iclass 37, count 0 2006.210.08:16:59.86#ibcon#wrote, iclass 37, count 0 2006.210.08:16:59.86#ibcon#about to read 3, iclass 37, count 0 2006.210.08:16:59.88#ibcon#read 3, iclass 37, count 0 2006.210.08:16:59.88#ibcon#about to read 4, iclass 37, count 0 2006.210.08:16:59.88#ibcon#read 4, iclass 37, count 0 2006.210.08:16:59.88#ibcon#about to read 5, iclass 37, count 0 2006.210.08:16:59.88#ibcon#read 5, iclass 37, count 0 2006.210.08:16:59.88#ibcon#about to read 6, iclass 37, count 0 2006.210.08:16:59.88#ibcon#read 6, iclass 37, count 0 2006.210.08:16:59.88#ibcon#end of sib2, iclass 37, count 0 2006.210.08:16:59.88#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:16:59.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:16:59.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:16:59.88#ibcon#*before write, iclass 37, count 0 2006.210.08:16:59.88#ibcon#enter sib2, iclass 37, count 0 2006.210.08:16:59.88#ibcon#flushed, iclass 37, count 0 2006.210.08:16:59.88#ibcon#about to write, iclass 37, count 0 2006.210.08:16:59.88#ibcon#wrote, iclass 37, count 0 2006.210.08:16:59.88#ibcon#about to read 3, iclass 37, count 0 2006.210.08:16:59.92#ibcon#read 3, iclass 37, count 0 2006.210.08:16:59.92#ibcon#about to read 4, iclass 37, count 0 2006.210.08:16:59.92#ibcon#read 4, iclass 37, count 0 2006.210.08:16:59.92#ibcon#about to read 5, iclass 37, count 0 2006.210.08:16:59.92#ibcon#read 5, iclass 37, count 0 2006.210.08:16:59.92#ibcon#about to read 6, iclass 37, count 0 2006.210.08:16:59.92#ibcon#read 6, iclass 37, count 0 2006.210.08:16:59.92#ibcon#end of sib2, iclass 37, count 0 2006.210.08:16:59.92#ibcon#*after write, iclass 37, count 0 2006.210.08:16:59.92#ibcon#*before return 0, iclass 37, count 0 2006.210.08:16:59.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:16:59.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:16:59.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:16:59.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:16:59.92$vc4f8/va=8,7 2006.210.08:16:59.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:16:59.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:16:59.92#ibcon#ireg 11 cls_cnt 2 2006.210.08:16:59.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:16:59.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:16:59.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:16:59.98#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:16:59.98#ibcon#first serial, iclass 39, count 2 2006.210.08:16:59.98#ibcon#enter sib2, iclass 39, count 2 2006.210.08:16:59.98#ibcon#flushed, iclass 39, count 2 2006.210.08:16:59.98#ibcon#about to write, iclass 39, count 2 2006.210.08:16:59.98#ibcon#wrote, iclass 39, count 2 2006.210.08:16:59.98#ibcon#about to read 3, iclass 39, count 2 2006.210.08:17:00.00#ibcon#read 3, iclass 39, count 2 2006.210.08:17:00.00#ibcon#about to read 4, iclass 39, count 2 2006.210.08:17:00.00#ibcon#read 4, iclass 39, count 2 2006.210.08:17:00.00#ibcon#about to read 5, iclass 39, count 2 2006.210.08:17:00.00#ibcon#read 5, iclass 39, count 2 2006.210.08:17:00.00#ibcon#about to read 6, iclass 39, count 2 2006.210.08:17:00.00#ibcon#read 6, iclass 39, count 2 2006.210.08:17:00.00#ibcon#end of sib2, iclass 39, count 2 2006.210.08:17:00.00#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:17:00.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:17:00.00#ibcon#[25=AT08-07\r\n] 2006.210.08:17:00.00#ibcon#*before write, iclass 39, count 2 2006.210.08:17:00.00#ibcon#enter sib2, iclass 39, count 2 2006.210.08:17:00.00#ibcon#flushed, iclass 39, count 2 2006.210.08:17:00.00#ibcon#about to write, iclass 39, count 2 2006.210.08:17:00.00#ibcon#wrote, iclass 39, count 2 2006.210.08:17:00.00#ibcon#about to read 3, iclass 39, count 2 2006.210.08:17:00.03#ibcon#read 3, iclass 39, count 2 2006.210.08:17:00.03#ibcon#about to read 4, iclass 39, count 2 2006.210.08:17:00.03#ibcon#read 4, iclass 39, count 2 2006.210.08:17:00.03#ibcon#about to read 5, iclass 39, count 2 2006.210.08:17:00.03#ibcon#read 5, iclass 39, count 2 2006.210.08:17:00.03#ibcon#about to read 6, iclass 39, count 2 2006.210.08:17:00.03#ibcon#read 6, iclass 39, count 2 2006.210.08:17:00.03#ibcon#end of sib2, iclass 39, count 2 2006.210.08:17:00.03#ibcon#*after write, iclass 39, count 2 2006.210.08:17:00.03#ibcon#*before return 0, iclass 39, count 2 2006.210.08:17:00.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:17:00.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:17:00.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:17:00.03#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:00.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:17:00.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:17:00.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:17:00.15#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:17:00.15#ibcon#first serial, iclass 39, count 0 2006.210.08:17:00.15#ibcon#enter sib2, iclass 39, count 0 2006.210.08:17:00.15#ibcon#flushed, iclass 39, count 0 2006.210.08:17:00.15#ibcon#about to write, iclass 39, count 0 2006.210.08:17:00.15#ibcon#wrote, iclass 39, count 0 2006.210.08:17:00.15#ibcon#about to read 3, iclass 39, count 0 2006.210.08:17:00.17#ibcon#read 3, iclass 39, count 0 2006.210.08:17:00.17#ibcon#about to read 4, iclass 39, count 0 2006.210.08:17:00.17#ibcon#read 4, iclass 39, count 0 2006.210.08:17:00.17#ibcon#about to read 5, iclass 39, count 0 2006.210.08:17:00.17#ibcon#read 5, iclass 39, count 0 2006.210.08:17:00.17#ibcon#about to read 6, iclass 39, count 0 2006.210.08:17:00.17#ibcon#read 6, iclass 39, count 0 2006.210.08:17:00.17#ibcon#end of sib2, iclass 39, count 0 2006.210.08:17:00.17#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:17:00.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:17:00.17#ibcon#[25=USB\r\n] 2006.210.08:17:00.17#ibcon#*before write, iclass 39, count 0 2006.210.08:17:00.17#ibcon#enter sib2, iclass 39, count 0 2006.210.08:17:00.17#ibcon#flushed, iclass 39, count 0 2006.210.08:17:00.17#ibcon#about to write, iclass 39, count 0 2006.210.08:17:00.17#ibcon#wrote, iclass 39, count 0 2006.210.08:17:00.17#ibcon#about to read 3, iclass 39, count 0 2006.210.08:17:00.20#ibcon#read 3, iclass 39, count 0 2006.210.08:17:00.20#ibcon#about to read 4, iclass 39, count 0 2006.210.08:17:00.20#ibcon#read 4, iclass 39, count 0 2006.210.08:17:00.20#ibcon#about to read 5, iclass 39, count 0 2006.210.08:17:00.20#ibcon#read 5, iclass 39, count 0 2006.210.08:17:00.20#ibcon#about to read 6, iclass 39, count 0 2006.210.08:17:00.20#ibcon#read 6, iclass 39, count 0 2006.210.08:17:00.20#ibcon#end of sib2, iclass 39, count 0 2006.210.08:17:00.20#ibcon#*after write, iclass 39, count 0 2006.210.08:17:00.20#ibcon#*before return 0, iclass 39, count 0 2006.210.08:17:00.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:17:00.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:17:00.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:17:00.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:17:00.20$vc4f8/vblo=1,632.99 2006.210.08:17:00.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:17:00.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:17:00.20#ibcon#ireg 17 cls_cnt 0 2006.210.08:17:00.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:17:00.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:17:00.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:17:00.20#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:17:00.20#ibcon#first serial, iclass 3, count 0 2006.210.08:17:00.20#ibcon#enter sib2, iclass 3, count 0 2006.210.08:17:00.20#ibcon#flushed, iclass 3, count 0 2006.210.08:17:00.20#ibcon#about to write, iclass 3, count 0 2006.210.08:17:00.20#ibcon#wrote, iclass 3, count 0 2006.210.08:17:00.20#ibcon#about to read 3, iclass 3, count 0 2006.210.08:17:00.22#ibcon#read 3, iclass 3, count 0 2006.210.08:17:00.22#ibcon#about to read 4, iclass 3, count 0 2006.210.08:17:00.22#ibcon#read 4, iclass 3, count 0 2006.210.08:17:00.22#ibcon#about to read 5, iclass 3, count 0 2006.210.08:17:00.22#ibcon#read 5, iclass 3, count 0 2006.210.08:17:00.22#ibcon#about to read 6, iclass 3, count 0 2006.210.08:17:00.22#ibcon#read 6, iclass 3, count 0 2006.210.08:17:00.22#ibcon#end of sib2, iclass 3, count 0 2006.210.08:17:00.22#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:17:00.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:17:00.22#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:17:00.22#ibcon#*before write, iclass 3, count 0 2006.210.08:17:00.22#ibcon#enter sib2, iclass 3, count 0 2006.210.08:17:00.22#ibcon#flushed, iclass 3, count 0 2006.210.08:17:00.22#ibcon#about to write, iclass 3, count 0 2006.210.08:17:00.22#ibcon#wrote, iclass 3, count 0 2006.210.08:17:00.22#ibcon#about to read 3, iclass 3, count 0 2006.210.08:17:00.26#ibcon#read 3, iclass 3, count 0 2006.210.08:17:00.26#ibcon#about to read 4, iclass 3, count 0 2006.210.08:17:00.26#ibcon#read 4, iclass 3, count 0 2006.210.08:17:00.26#ibcon#about to read 5, iclass 3, count 0 2006.210.08:17:00.26#ibcon#read 5, iclass 3, count 0 2006.210.08:17:00.26#ibcon#about to read 6, iclass 3, count 0 2006.210.08:17:00.26#ibcon#read 6, iclass 3, count 0 2006.210.08:17:00.26#ibcon#end of sib2, iclass 3, count 0 2006.210.08:17:00.26#ibcon#*after write, iclass 3, count 0 2006.210.08:17:00.26#ibcon#*before return 0, iclass 3, count 0 2006.210.08:17:00.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:17:00.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:17:00.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:17:00.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:17:00.26$vc4f8/vb=1,4 2006.210.08:17:00.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:17:00.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:17:00.26#ibcon#ireg 11 cls_cnt 2 2006.210.08:17:00.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:17:00.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:17:00.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:17:00.26#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:17:00.26#ibcon#first serial, iclass 5, count 2 2006.210.08:17:00.26#ibcon#enter sib2, iclass 5, count 2 2006.210.08:17:00.26#ibcon#flushed, iclass 5, count 2 2006.210.08:17:00.26#ibcon#about to write, iclass 5, count 2 2006.210.08:17:00.26#ibcon#wrote, iclass 5, count 2 2006.210.08:17:00.26#ibcon#about to read 3, iclass 5, count 2 2006.210.08:17:00.28#ibcon#read 3, iclass 5, count 2 2006.210.08:17:00.28#ibcon#about to read 4, iclass 5, count 2 2006.210.08:17:00.28#ibcon#read 4, iclass 5, count 2 2006.210.08:17:00.28#ibcon#about to read 5, iclass 5, count 2 2006.210.08:17:00.28#ibcon#read 5, iclass 5, count 2 2006.210.08:17:00.28#ibcon#about to read 6, iclass 5, count 2 2006.210.08:17:00.28#ibcon#read 6, iclass 5, count 2 2006.210.08:17:00.28#ibcon#end of sib2, iclass 5, count 2 2006.210.08:17:00.28#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:17:00.28#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:17:00.28#ibcon#[27=AT01-04\r\n] 2006.210.08:17:00.28#ibcon#*before write, iclass 5, count 2 2006.210.08:17:00.28#ibcon#enter sib2, iclass 5, count 2 2006.210.08:17:00.28#ibcon#flushed, iclass 5, count 2 2006.210.08:17:00.28#ibcon#about to write, iclass 5, count 2 2006.210.08:17:00.28#ibcon#wrote, iclass 5, count 2 2006.210.08:17:00.28#ibcon#about to read 3, iclass 5, count 2 2006.210.08:17:00.31#ibcon#read 3, iclass 5, count 2 2006.210.08:17:00.31#ibcon#about to read 4, iclass 5, count 2 2006.210.08:17:00.31#ibcon#read 4, iclass 5, count 2 2006.210.08:17:00.31#ibcon#about to read 5, iclass 5, count 2 2006.210.08:17:00.31#ibcon#read 5, iclass 5, count 2 2006.210.08:17:00.31#ibcon#about to read 6, iclass 5, count 2 2006.210.08:17:00.31#ibcon#read 6, iclass 5, count 2 2006.210.08:17:00.31#ibcon#end of sib2, iclass 5, count 2 2006.210.08:17:00.31#ibcon#*after write, iclass 5, count 2 2006.210.08:17:00.31#ibcon#*before return 0, iclass 5, count 2 2006.210.08:17:00.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:17:00.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:17:00.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:17:00.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:00.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:17:00.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:17:00.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:17:00.43#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:17:00.43#ibcon#first serial, iclass 5, count 0 2006.210.08:17:00.43#ibcon#enter sib2, iclass 5, count 0 2006.210.08:17:00.43#ibcon#flushed, iclass 5, count 0 2006.210.08:17:00.43#ibcon#about to write, iclass 5, count 0 2006.210.08:17:00.43#ibcon#wrote, iclass 5, count 0 2006.210.08:17:00.43#ibcon#about to read 3, iclass 5, count 0 2006.210.08:17:00.45#ibcon#read 3, iclass 5, count 0 2006.210.08:17:00.45#ibcon#about to read 4, iclass 5, count 0 2006.210.08:17:00.45#ibcon#read 4, iclass 5, count 0 2006.210.08:17:00.45#ibcon#about to read 5, iclass 5, count 0 2006.210.08:17:00.45#ibcon#read 5, iclass 5, count 0 2006.210.08:17:00.45#ibcon#about to read 6, iclass 5, count 0 2006.210.08:17:00.45#ibcon#read 6, iclass 5, count 0 2006.210.08:17:00.45#ibcon#end of sib2, iclass 5, count 0 2006.210.08:17:00.45#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:17:00.45#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:17:00.45#ibcon#[27=USB\r\n] 2006.210.08:17:00.45#ibcon#*before write, iclass 5, count 0 2006.210.08:17:00.45#ibcon#enter sib2, iclass 5, count 0 2006.210.08:17:00.45#ibcon#flushed, iclass 5, count 0 2006.210.08:17:00.45#ibcon#about to write, iclass 5, count 0 2006.210.08:17:00.45#ibcon#wrote, iclass 5, count 0 2006.210.08:17:00.45#ibcon#about to read 3, iclass 5, count 0 2006.210.08:17:00.48#ibcon#read 3, iclass 5, count 0 2006.210.08:17:00.48#ibcon#about to read 4, iclass 5, count 0 2006.210.08:17:00.48#ibcon#read 4, iclass 5, count 0 2006.210.08:17:00.48#ibcon#about to read 5, iclass 5, count 0 2006.210.08:17:00.48#ibcon#read 5, iclass 5, count 0 2006.210.08:17:00.48#ibcon#about to read 6, iclass 5, count 0 2006.210.08:17:00.48#ibcon#read 6, iclass 5, count 0 2006.210.08:17:00.48#ibcon#end of sib2, iclass 5, count 0 2006.210.08:17:00.48#ibcon#*after write, iclass 5, count 0 2006.210.08:17:00.48#ibcon#*before return 0, iclass 5, count 0 2006.210.08:17:00.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:17:00.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:17:00.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:17:00.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:17:00.48$vc4f8/vblo=2,640.99 2006.210.08:17:00.48#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:17:00.48#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:17:00.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:17:00.48#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:17:00.48#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:17:00.48#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:17:00.48#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:17:00.48#ibcon#first serial, iclass 7, count 0 2006.210.08:17:00.48#ibcon#enter sib2, iclass 7, count 0 2006.210.08:17:00.48#ibcon#flushed, iclass 7, count 0 2006.210.08:17:00.48#ibcon#about to write, iclass 7, count 0 2006.210.08:17:00.48#ibcon#wrote, iclass 7, count 0 2006.210.08:17:00.48#ibcon#about to read 3, iclass 7, count 0 2006.210.08:17:00.50#ibcon#read 3, iclass 7, count 0 2006.210.08:17:00.50#ibcon#about to read 4, iclass 7, count 0 2006.210.08:17:00.50#ibcon#read 4, iclass 7, count 0 2006.210.08:17:00.50#ibcon#about to read 5, iclass 7, count 0 2006.210.08:17:00.50#ibcon#read 5, iclass 7, count 0 2006.210.08:17:00.50#ibcon#about to read 6, iclass 7, count 0 2006.210.08:17:00.50#ibcon#read 6, iclass 7, count 0 2006.210.08:17:00.50#ibcon#end of sib2, iclass 7, count 0 2006.210.08:17:00.50#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:17:00.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:17:00.50#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:17:00.50#ibcon#*before write, iclass 7, count 0 2006.210.08:17:00.50#ibcon#enter sib2, iclass 7, count 0 2006.210.08:17:00.50#ibcon#flushed, iclass 7, count 0 2006.210.08:17:00.50#ibcon#about to write, iclass 7, count 0 2006.210.08:17:00.50#ibcon#wrote, iclass 7, count 0 2006.210.08:17:00.50#ibcon#about to read 3, iclass 7, count 0 2006.210.08:17:00.54#ibcon#read 3, iclass 7, count 0 2006.210.08:17:00.54#ibcon#about to read 4, iclass 7, count 0 2006.210.08:17:00.54#ibcon#read 4, iclass 7, count 0 2006.210.08:17:00.54#ibcon#about to read 5, iclass 7, count 0 2006.210.08:17:00.54#ibcon#read 5, iclass 7, count 0 2006.210.08:17:00.54#ibcon#about to read 6, iclass 7, count 0 2006.210.08:17:00.54#ibcon#read 6, iclass 7, count 0 2006.210.08:17:00.54#ibcon#end of sib2, iclass 7, count 0 2006.210.08:17:00.54#ibcon#*after write, iclass 7, count 0 2006.210.08:17:00.54#ibcon#*before return 0, iclass 7, count 0 2006.210.08:17:00.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:17:00.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:17:00.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:17:00.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:17:00.54$vc4f8/vb=2,4 2006.210.08:17:00.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:17:00.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:17:00.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:17:00.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:17:00.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:17:00.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:17:00.60#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:17:00.60#ibcon#first serial, iclass 11, count 2 2006.210.08:17:00.60#ibcon#enter sib2, iclass 11, count 2 2006.210.08:17:00.60#ibcon#flushed, iclass 11, count 2 2006.210.08:17:00.60#ibcon#about to write, iclass 11, count 2 2006.210.08:17:00.60#ibcon#wrote, iclass 11, count 2 2006.210.08:17:00.60#ibcon#about to read 3, iclass 11, count 2 2006.210.08:17:00.62#ibcon#read 3, iclass 11, count 2 2006.210.08:17:00.62#ibcon#about to read 4, iclass 11, count 2 2006.210.08:17:00.62#ibcon#read 4, iclass 11, count 2 2006.210.08:17:00.62#ibcon#about to read 5, iclass 11, count 2 2006.210.08:17:00.62#ibcon#read 5, iclass 11, count 2 2006.210.08:17:00.62#ibcon#about to read 6, iclass 11, count 2 2006.210.08:17:00.62#ibcon#read 6, iclass 11, count 2 2006.210.08:17:00.62#ibcon#end of sib2, iclass 11, count 2 2006.210.08:17:00.62#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:17:00.62#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:17:00.62#ibcon#[27=AT02-04\r\n] 2006.210.08:17:00.62#ibcon#*before write, iclass 11, count 2 2006.210.08:17:00.62#ibcon#enter sib2, iclass 11, count 2 2006.210.08:17:00.62#ibcon#flushed, iclass 11, count 2 2006.210.08:17:00.62#ibcon#about to write, iclass 11, count 2 2006.210.08:17:00.62#ibcon#wrote, iclass 11, count 2 2006.210.08:17:00.62#ibcon#about to read 3, iclass 11, count 2 2006.210.08:17:00.65#ibcon#read 3, iclass 11, count 2 2006.210.08:17:00.65#ibcon#about to read 4, iclass 11, count 2 2006.210.08:17:00.65#ibcon#read 4, iclass 11, count 2 2006.210.08:17:00.65#ibcon#about to read 5, iclass 11, count 2 2006.210.08:17:00.65#ibcon#read 5, iclass 11, count 2 2006.210.08:17:00.65#ibcon#about to read 6, iclass 11, count 2 2006.210.08:17:00.65#ibcon#read 6, iclass 11, count 2 2006.210.08:17:00.65#ibcon#end of sib2, iclass 11, count 2 2006.210.08:17:00.65#ibcon#*after write, iclass 11, count 2 2006.210.08:17:00.65#ibcon#*before return 0, iclass 11, count 2 2006.210.08:17:00.65#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:17:00.65#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:17:00.65#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:17:00.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:00.65#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:17:00.77#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:17:00.77#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:17:00.77#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:17:00.77#ibcon#first serial, iclass 11, count 0 2006.210.08:17:00.77#ibcon#enter sib2, iclass 11, count 0 2006.210.08:17:00.77#ibcon#flushed, iclass 11, count 0 2006.210.08:17:00.77#ibcon#about to write, iclass 11, count 0 2006.210.08:17:00.77#ibcon#wrote, iclass 11, count 0 2006.210.08:17:00.77#ibcon#about to read 3, iclass 11, count 0 2006.210.08:17:00.79#ibcon#read 3, iclass 11, count 0 2006.210.08:17:00.79#ibcon#about to read 4, iclass 11, count 0 2006.210.08:17:00.79#ibcon#read 4, iclass 11, count 0 2006.210.08:17:00.79#ibcon#about to read 5, iclass 11, count 0 2006.210.08:17:00.79#ibcon#read 5, iclass 11, count 0 2006.210.08:17:00.79#ibcon#about to read 6, iclass 11, count 0 2006.210.08:17:00.79#ibcon#read 6, iclass 11, count 0 2006.210.08:17:00.79#ibcon#end of sib2, iclass 11, count 0 2006.210.08:17:00.79#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:17:00.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:17:00.79#ibcon#[27=USB\r\n] 2006.210.08:17:00.79#ibcon#*before write, iclass 11, count 0 2006.210.08:17:00.79#ibcon#enter sib2, iclass 11, count 0 2006.210.08:17:00.79#ibcon#flushed, iclass 11, count 0 2006.210.08:17:00.79#ibcon#about to write, iclass 11, count 0 2006.210.08:17:00.79#ibcon#wrote, iclass 11, count 0 2006.210.08:17:00.79#ibcon#about to read 3, iclass 11, count 0 2006.210.08:17:00.82#ibcon#read 3, iclass 11, count 0 2006.210.08:17:00.82#ibcon#about to read 4, iclass 11, count 0 2006.210.08:17:00.82#ibcon#read 4, iclass 11, count 0 2006.210.08:17:00.82#ibcon#about to read 5, iclass 11, count 0 2006.210.08:17:00.82#ibcon#read 5, iclass 11, count 0 2006.210.08:17:00.82#ibcon#about to read 6, iclass 11, count 0 2006.210.08:17:00.82#ibcon#read 6, iclass 11, count 0 2006.210.08:17:00.82#ibcon#end of sib2, iclass 11, count 0 2006.210.08:17:00.82#ibcon#*after write, iclass 11, count 0 2006.210.08:17:00.82#ibcon#*before return 0, iclass 11, count 0 2006.210.08:17:00.82#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:17:00.82#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:17:00.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:17:00.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:17:00.82$vc4f8/vblo=3,656.99 2006.210.08:17:00.82#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:17:00.82#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:17:00.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:17:00.82#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:17:00.82#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:17:00.82#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:17:00.82#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:17:00.82#ibcon#first serial, iclass 13, count 0 2006.210.08:17:00.82#ibcon#enter sib2, iclass 13, count 0 2006.210.08:17:00.82#ibcon#flushed, iclass 13, count 0 2006.210.08:17:00.82#ibcon#about to write, iclass 13, count 0 2006.210.08:17:00.82#ibcon#wrote, iclass 13, count 0 2006.210.08:17:00.82#ibcon#about to read 3, iclass 13, count 0 2006.210.08:17:00.84#ibcon#read 3, iclass 13, count 0 2006.210.08:17:00.84#ibcon#about to read 4, iclass 13, count 0 2006.210.08:17:00.84#ibcon#read 4, iclass 13, count 0 2006.210.08:17:00.84#ibcon#about to read 5, iclass 13, count 0 2006.210.08:17:00.84#ibcon#read 5, iclass 13, count 0 2006.210.08:17:00.84#ibcon#about to read 6, iclass 13, count 0 2006.210.08:17:00.84#ibcon#read 6, iclass 13, count 0 2006.210.08:17:00.84#ibcon#end of sib2, iclass 13, count 0 2006.210.08:17:00.84#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:17:00.84#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:17:00.84#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:17:00.84#ibcon#*before write, iclass 13, count 0 2006.210.08:17:00.84#ibcon#enter sib2, iclass 13, count 0 2006.210.08:17:00.84#ibcon#flushed, iclass 13, count 0 2006.210.08:17:00.84#ibcon#about to write, iclass 13, count 0 2006.210.08:17:00.84#ibcon#wrote, iclass 13, count 0 2006.210.08:17:00.84#ibcon#about to read 3, iclass 13, count 0 2006.210.08:17:00.88#ibcon#read 3, iclass 13, count 0 2006.210.08:17:00.88#ibcon#about to read 4, iclass 13, count 0 2006.210.08:17:00.88#ibcon#read 4, iclass 13, count 0 2006.210.08:17:00.88#ibcon#about to read 5, iclass 13, count 0 2006.210.08:17:00.88#ibcon#read 5, iclass 13, count 0 2006.210.08:17:00.88#ibcon#about to read 6, iclass 13, count 0 2006.210.08:17:00.88#ibcon#read 6, iclass 13, count 0 2006.210.08:17:00.88#ibcon#end of sib2, iclass 13, count 0 2006.210.08:17:00.88#ibcon#*after write, iclass 13, count 0 2006.210.08:17:00.88#ibcon#*before return 0, iclass 13, count 0 2006.210.08:17:00.88#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:17:00.88#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:17:00.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:17:00.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:17:00.88$vc4f8/vb=3,3 2006.210.08:17:00.88#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:17:00.88#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:17:00.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:17:00.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:17:00.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:17:00.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:17:00.94#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:17:00.94#ibcon#first serial, iclass 15, count 2 2006.210.08:17:00.94#ibcon#enter sib2, iclass 15, count 2 2006.210.08:17:00.94#ibcon#flushed, iclass 15, count 2 2006.210.08:17:00.94#ibcon#about to write, iclass 15, count 2 2006.210.08:17:00.94#ibcon#wrote, iclass 15, count 2 2006.210.08:17:00.94#ibcon#about to read 3, iclass 15, count 2 2006.210.08:17:00.96#ibcon#read 3, iclass 15, count 2 2006.210.08:17:00.96#ibcon#about to read 4, iclass 15, count 2 2006.210.08:17:00.96#ibcon#read 4, iclass 15, count 2 2006.210.08:17:00.96#ibcon#about to read 5, iclass 15, count 2 2006.210.08:17:00.96#ibcon#read 5, iclass 15, count 2 2006.210.08:17:00.96#ibcon#about to read 6, iclass 15, count 2 2006.210.08:17:00.96#ibcon#read 6, iclass 15, count 2 2006.210.08:17:00.96#ibcon#end of sib2, iclass 15, count 2 2006.210.08:17:00.96#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:17:00.96#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:17:00.96#ibcon#[27=AT03-03\r\n] 2006.210.08:17:00.96#ibcon#*before write, iclass 15, count 2 2006.210.08:17:00.96#ibcon#enter sib2, iclass 15, count 2 2006.210.08:17:00.96#ibcon#flushed, iclass 15, count 2 2006.210.08:17:00.96#ibcon#about to write, iclass 15, count 2 2006.210.08:17:00.96#ibcon#wrote, iclass 15, count 2 2006.210.08:17:00.96#ibcon#about to read 3, iclass 15, count 2 2006.210.08:17:00.99#ibcon#read 3, iclass 15, count 2 2006.210.08:17:00.99#ibcon#about to read 4, iclass 15, count 2 2006.210.08:17:00.99#ibcon#read 4, iclass 15, count 2 2006.210.08:17:00.99#ibcon#about to read 5, iclass 15, count 2 2006.210.08:17:00.99#ibcon#read 5, iclass 15, count 2 2006.210.08:17:00.99#ibcon#about to read 6, iclass 15, count 2 2006.210.08:17:00.99#ibcon#read 6, iclass 15, count 2 2006.210.08:17:00.99#ibcon#end of sib2, iclass 15, count 2 2006.210.08:17:00.99#ibcon#*after write, iclass 15, count 2 2006.210.08:17:00.99#ibcon#*before return 0, iclass 15, count 2 2006.210.08:17:00.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:17:00.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:17:00.99#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:17:00.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:00.99#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:17:01.11#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:17:01.11#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:17:01.11#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:17:01.11#ibcon#first serial, iclass 15, count 0 2006.210.08:17:01.11#ibcon#enter sib2, iclass 15, count 0 2006.210.08:17:01.11#ibcon#flushed, iclass 15, count 0 2006.210.08:17:01.11#ibcon#about to write, iclass 15, count 0 2006.210.08:17:01.11#ibcon#wrote, iclass 15, count 0 2006.210.08:17:01.11#ibcon#about to read 3, iclass 15, count 0 2006.210.08:17:01.13#ibcon#read 3, iclass 15, count 0 2006.210.08:17:01.13#ibcon#about to read 4, iclass 15, count 0 2006.210.08:17:01.13#ibcon#read 4, iclass 15, count 0 2006.210.08:17:01.13#ibcon#about to read 5, iclass 15, count 0 2006.210.08:17:01.13#ibcon#read 5, iclass 15, count 0 2006.210.08:17:01.13#ibcon#about to read 6, iclass 15, count 0 2006.210.08:17:01.13#ibcon#read 6, iclass 15, count 0 2006.210.08:17:01.13#ibcon#end of sib2, iclass 15, count 0 2006.210.08:17:01.13#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:17:01.13#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:17:01.13#ibcon#[27=USB\r\n] 2006.210.08:17:01.13#ibcon#*before write, iclass 15, count 0 2006.210.08:17:01.13#ibcon#enter sib2, iclass 15, count 0 2006.210.08:17:01.13#ibcon#flushed, iclass 15, count 0 2006.210.08:17:01.13#ibcon#about to write, iclass 15, count 0 2006.210.08:17:01.13#ibcon#wrote, iclass 15, count 0 2006.210.08:17:01.13#ibcon#about to read 3, iclass 15, count 0 2006.210.08:17:01.16#ibcon#read 3, iclass 15, count 0 2006.210.08:17:01.16#ibcon#about to read 4, iclass 15, count 0 2006.210.08:17:01.16#ibcon#read 4, iclass 15, count 0 2006.210.08:17:01.16#ibcon#about to read 5, iclass 15, count 0 2006.210.08:17:01.16#ibcon#read 5, iclass 15, count 0 2006.210.08:17:01.16#ibcon#about to read 6, iclass 15, count 0 2006.210.08:17:01.16#ibcon#read 6, iclass 15, count 0 2006.210.08:17:01.16#ibcon#end of sib2, iclass 15, count 0 2006.210.08:17:01.16#ibcon#*after write, iclass 15, count 0 2006.210.08:17:01.16#ibcon#*before return 0, iclass 15, count 0 2006.210.08:17:01.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:17:01.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:17:01.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:17:01.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:17:01.16$vc4f8/vblo=4,712.99 2006.210.08:17:01.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:17:01.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:17:01.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:17:01.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:17:01.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:17:01.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:17:01.16#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:17:01.16#ibcon#first serial, iclass 17, count 0 2006.210.08:17:01.16#ibcon#enter sib2, iclass 17, count 0 2006.210.08:17:01.16#ibcon#flushed, iclass 17, count 0 2006.210.08:17:01.16#ibcon#about to write, iclass 17, count 0 2006.210.08:17:01.16#ibcon#wrote, iclass 17, count 0 2006.210.08:17:01.16#ibcon#about to read 3, iclass 17, count 0 2006.210.08:17:01.18#ibcon#read 3, iclass 17, count 0 2006.210.08:17:01.18#ibcon#about to read 4, iclass 17, count 0 2006.210.08:17:01.18#ibcon#read 4, iclass 17, count 0 2006.210.08:17:01.18#ibcon#about to read 5, iclass 17, count 0 2006.210.08:17:01.18#ibcon#read 5, iclass 17, count 0 2006.210.08:17:01.18#ibcon#about to read 6, iclass 17, count 0 2006.210.08:17:01.18#ibcon#read 6, iclass 17, count 0 2006.210.08:17:01.18#ibcon#end of sib2, iclass 17, count 0 2006.210.08:17:01.18#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:17:01.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:17:01.18#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:17:01.18#ibcon#*before write, iclass 17, count 0 2006.210.08:17:01.18#ibcon#enter sib2, iclass 17, count 0 2006.210.08:17:01.18#ibcon#flushed, iclass 17, count 0 2006.210.08:17:01.18#ibcon#about to write, iclass 17, count 0 2006.210.08:17:01.18#ibcon#wrote, iclass 17, count 0 2006.210.08:17:01.18#ibcon#about to read 3, iclass 17, count 0 2006.210.08:17:01.22#ibcon#read 3, iclass 17, count 0 2006.210.08:17:01.22#ibcon#about to read 4, iclass 17, count 0 2006.210.08:17:01.22#ibcon#read 4, iclass 17, count 0 2006.210.08:17:01.22#ibcon#about to read 5, iclass 17, count 0 2006.210.08:17:01.22#ibcon#read 5, iclass 17, count 0 2006.210.08:17:01.22#ibcon#about to read 6, iclass 17, count 0 2006.210.08:17:01.22#ibcon#read 6, iclass 17, count 0 2006.210.08:17:01.22#ibcon#end of sib2, iclass 17, count 0 2006.210.08:17:01.22#ibcon#*after write, iclass 17, count 0 2006.210.08:17:01.22#ibcon#*before return 0, iclass 17, count 0 2006.210.08:17:01.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:17:01.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:17:01.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:17:01.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:17:01.22$vc4f8/vb=4,3 2006.210.08:17:01.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:17:01.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:17:01.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:17:01.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:17:01.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:17:01.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:17:01.28#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:17:01.28#ibcon#first serial, iclass 19, count 2 2006.210.08:17:01.28#ibcon#enter sib2, iclass 19, count 2 2006.210.08:17:01.28#ibcon#flushed, iclass 19, count 2 2006.210.08:17:01.28#ibcon#about to write, iclass 19, count 2 2006.210.08:17:01.28#ibcon#wrote, iclass 19, count 2 2006.210.08:17:01.28#ibcon#about to read 3, iclass 19, count 2 2006.210.08:17:01.30#ibcon#read 3, iclass 19, count 2 2006.210.08:17:01.30#ibcon#about to read 4, iclass 19, count 2 2006.210.08:17:01.30#ibcon#read 4, iclass 19, count 2 2006.210.08:17:01.30#ibcon#about to read 5, iclass 19, count 2 2006.210.08:17:01.30#ibcon#read 5, iclass 19, count 2 2006.210.08:17:01.30#ibcon#about to read 6, iclass 19, count 2 2006.210.08:17:01.30#ibcon#read 6, iclass 19, count 2 2006.210.08:17:01.30#ibcon#end of sib2, iclass 19, count 2 2006.210.08:17:01.30#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:17:01.30#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:17:01.30#ibcon#[27=AT04-03\r\n] 2006.210.08:17:01.30#ibcon#*before write, iclass 19, count 2 2006.210.08:17:01.30#ibcon#enter sib2, iclass 19, count 2 2006.210.08:17:01.30#ibcon#flushed, iclass 19, count 2 2006.210.08:17:01.30#ibcon#about to write, iclass 19, count 2 2006.210.08:17:01.30#ibcon#wrote, iclass 19, count 2 2006.210.08:17:01.30#ibcon#about to read 3, iclass 19, count 2 2006.210.08:17:01.33#ibcon#read 3, iclass 19, count 2 2006.210.08:17:01.33#ibcon#about to read 4, iclass 19, count 2 2006.210.08:17:01.33#ibcon#read 4, iclass 19, count 2 2006.210.08:17:01.33#ibcon#about to read 5, iclass 19, count 2 2006.210.08:17:01.33#ibcon#read 5, iclass 19, count 2 2006.210.08:17:01.33#ibcon#about to read 6, iclass 19, count 2 2006.210.08:17:01.33#ibcon#read 6, iclass 19, count 2 2006.210.08:17:01.33#ibcon#end of sib2, iclass 19, count 2 2006.210.08:17:01.33#ibcon#*after write, iclass 19, count 2 2006.210.08:17:01.33#ibcon#*before return 0, iclass 19, count 2 2006.210.08:17:01.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:17:01.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:17:01.33#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:17:01.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:01.33#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:17:01.45#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:17:01.45#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:17:01.45#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:17:01.45#ibcon#first serial, iclass 19, count 0 2006.210.08:17:01.45#ibcon#enter sib2, iclass 19, count 0 2006.210.08:17:01.45#ibcon#flushed, iclass 19, count 0 2006.210.08:17:01.45#ibcon#about to write, iclass 19, count 0 2006.210.08:17:01.45#ibcon#wrote, iclass 19, count 0 2006.210.08:17:01.45#ibcon#about to read 3, iclass 19, count 0 2006.210.08:17:01.47#ibcon#read 3, iclass 19, count 0 2006.210.08:17:01.47#ibcon#about to read 4, iclass 19, count 0 2006.210.08:17:01.47#ibcon#read 4, iclass 19, count 0 2006.210.08:17:01.47#ibcon#about to read 5, iclass 19, count 0 2006.210.08:17:01.47#ibcon#read 5, iclass 19, count 0 2006.210.08:17:01.47#ibcon#about to read 6, iclass 19, count 0 2006.210.08:17:01.47#ibcon#read 6, iclass 19, count 0 2006.210.08:17:01.47#ibcon#end of sib2, iclass 19, count 0 2006.210.08:17:01.47#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:17:01.47#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:17:01.47#ibcon#[27=USB\r\n] 2006.210.08:17:01.47#ibcon#*before write, iclass 19, count 0 2006.210.08:17:01.47#ibcon#enter sib2, iclass 19, count 0 2006.210.08:17:01.47#ibcon#flushed, iclass 19, count 0 2006.210.08:17:01.47#ibcon#about to write, iclass 19, count 0 2006.210.08:17:01.47#ibcon#wrote, iclass 19, count 0 2006.210.08:17:01.47#ibcon#about to read 3, iclass 19, count 0 2006.210.08:17:01.50#ibcon#read 3, iclass 19, count 0 2006.210.08:17:01.50#ibcon#about to read 4, iclass 19, count 0 2006.210.08:17:01.50#ibcon#read 4, iclass 19, count 0 2006.210.08:17:01.50#ibcon#about to read 5, iclass 19, count 0 2006.210.08:17:01.50#ibcon#read 5, iclass 19, count 0 2006.210.08:17:01.50#ibcon#about to read 6, iclass 19, count 0 2006.210.08:17:01.50#ibcon#read 6, iclass 19, count 0 2006.210.08:17:01.50#ibcon#end of sib2, iclass 19, count 0 2006.210.08:17:01.50#ibcon#*after write, iclass 19, count 0 2006.210.08:17:01.50#ibcon#*before return 0, iclass 19, count 0 2006.210.08:17:01.50#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:17:01.50#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:17:01.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:17:01.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:17:01.50$vc4f8/vblo=5,744.99 2006.210.08:17:01.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:17:01.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:17:01.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:17:01.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:17:01.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:17:01.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:17:01.50#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:17:01.50#ibcon#first serial, iclass 21, count 0 2006.210.08:17:01.50#ibcon#enter sib2, iclass 21, count 0 2006.210.08:17:01.50#ibcon#flushed, iclass 21, count 0 2006.210.08:17:01.50#ibcon#about to write, iclass 21, count 0 2006.210.08:17:01.50#ibcon#wrote, iclass 21, count 0 2006.210.08:17:01.50#ibcon#about to read 3, iclass 21, count 0 2006.210.08:17:01.52#ibcon#read 3, iclass 21, count 0 2006.210.08:17:01.52#ibcon#about to read 4, iclass 21, count 0 2006.210.08:17:01.52#ibcon#read 4, iclass 21, count 0 2006.210.08:17:01.52#ibcon#about to read 5, iclass 21, count 0 2006.210.08:17:01.52#ibcon#read 5, iclass 21, count 0 2006.210.08:17:01.52#ibcon#about to read 6, iclass 21, count 0 2006.210.08:17:01.52#ibcon#read 6, iclass 21, count 0 2006.210.08:17:01.52#ibcon#end of sib2, iclass 21, count 0 2006.210.08:17:01.52#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:17:01.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:17:01.52#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:17:01.52#ibcon#*before write, iclass 21, count 0 2006.210.08:17:01.52#ibcon#enter sib2, iclass 21, count 0 2006.210.08:17:01.52#ibcon#flushed, iclass 21, count 0 2006.210.08:17:01.52#ibcon#about to write, iclass 21, count 0 2006.210.08:17:01.52#ibcon#wrote, iclass 21, count 0 2006.210.08:17:01.52#ibcon#about to read 3, iclass 21, count 0 2006.210.08:17:01.56#ibcon#read 3, iclass 21, count 0 2006.210.08:17:01.56#ibcon#about to read 4, iclass 21, count 0 2006.210.08:17:01.56#ibcon#read 4, iclass 21, count 0 2006.210.08:17:01.56#ibcon#about to read 5, iclass 21, count 0 2006.210.08:17:01.56#ibcon#read 5, iclass 21, count 0 2006.210.08:17:01.56#ibcon#about to read 6, iclass 21, count 0 2006.210.08:17:01.56#ibcon#read 6, iclass 21, count 0 2006.210.08:17:01.56#ibcon#end of sib2, iclass 21, count 0 2006.210.08:17:01.56#ibcon#*after write, iclass 21, count 0 2006.210.08:17:01.56#ibcon#*before return 0, iclass 21, count 0 2006.210.08:17:01.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:17:01.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:17:01.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:17:01.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:17:01.56$vc4f8/vb=5,3 2006.210.08:17:01.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:17:01.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:17:01.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:17:01.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:17:01.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:17:01.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:17:01.62#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:17:01.62#ibcon#first serial, iclass 23, count 2 2006.210.08:17:01.62#ibcon#enter sib2, iclass 23, count 2 2006.210.08:17:01.62#ibcon#flushed, iclass 23, count 2 2006.210.08:17:01.62#ibcon#about to write, iclass 23, count 2 2006.210.08:17:01.62#ibcon#wrote, iclass 23, count 2 2006.210.08:17:01.62#ibcon#about to read 3, iclass 23, count 2 2006.210.08:17:01.64#ibcon#read 3, iclass 23, count 2 2006.210.08:17:01.64#ibcon#about to read 4, iclass 23, count 2 2006.210.08:17:01.64#ibcon#read 4, iclass 23, count 2 2006.210.08:17:01.64#ibcon#about to read 5, iclass 23, count 2 2006.210.08:17:01.64#ibcon#read 5, iclass 23, count 2 2006.210.08:17:01.64#ibcon#about to read 6, iclass 23, count 2 2006.210.08:17:01.64#ibcon#read 6, iclass 23, count 2 2006.210.08:17:01.64#ibcon#end of sib2, iclass 23, count 2 2006.210.08:17:01.64#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:17:01.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:17:01.64#ibcon#[27=AT05-03\r\n] 2006.210.08:17:01.64#ibcon#*before write, iclass 23, count 2 2006.210.08:17:01.64#ibcon#enter sib2, iclass 23, count 2 2006.210.08:17:01.64#ibcon#flushed, iclass 23, count 2 2006.210.08:17:01.64#ibcon#about to write, iclass 23, count 2 2006.210.08:17:01.64#ibcon#wrote, iclass 23, count 2 2006.210.08:17:01.64#ibcon#about to read 3, iclass 23, count 2 2006.210.08:17:01.67#ibcon#read 3, iclass 23, count 2 2006.210.08:17:01.67#ibcon#about to read 4, iclass 23, count 2 2006.210.08:17:01.67#ibcon#read 4, iclass 23, count 2 2006.210.08:17:01.67#ibcon#about to read 5, iclass 23, count 2 2006.210.08:17:01.67#ibcon#read 5, iclass 23, count 2 2006.210.08:17:01.67#ibcon#about to read 6, iclass 23, count 2 2006.210.08:17:01.67#ibcon#read 6, iclass 23, count 2 2006.210.08:17:01.67#ibcon#end of sib2, iclass 23, count 2 2006.210.08:17:01.67#ibcon#*after write, iclass 23, count 2 2006.210.08:17:01.67#ibcon#*before return 0, iclass 23, count 2 2006.210.08:17:01.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:17:01.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:17:01.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:17:01.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:01.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:17:01.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:17:01.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:17:01.79#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:17:01.79#ibcon#first serial, iclass 23, count 0 2006.210.08:17:01.79#ibcon#enter sib2, iclass 23, count 0 2006.210.08:17:01.79#ibcon#flushed, iclass 23, count 0 2006.210.08:17:01.79#ibcon#about to write, iclass 23, count 0 2006.210.08:17:01.79#ibcon#wrote, iclass 23, count 0 2006.210.08:17:01.79#ibcon#about to read 3, iclass 23, count 0 2006.210.08:17:01.81#ibcon#read 3, iclass 23, count 0 2006.210.08:17:01.81#ibcon#about to read 4, iclass 23, count 0 2006.210.08:17:01.81#ibcon#read 4, iclass 23, count 0 2006.210.08:17:01.81#ibcon#about to read 5, iclass 23, count 0 2006.210.08:17:01.81#ibcon#read 5, iclass 23, count 0 2006.210.08:17:01.81#ibcon#about to read 6, iclass 23, count 0 2006.210.08:17:01.81#ibcon#read 6, iclass 23, count 0 2006.210.08:17:01.81#ibcon#end of sib2, iclass 23, count 0 2006.210.08:17:01.81#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:17:01.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:17:01.81#ibcon#[27=USB\r\n] 2006.210.08:17:01.81#ibcon#*before write, iclass 23, count 0 2006.210.08:17:01.81#ibcon#enter sib2, iclass 23, count 0 2006.210.08:17:01.81#ibcon#flushed, iclass 23, count 0 2006.210.08:17:01.81#ibcon#about to write, iclass 23, count 0 2006.210.08:17:01.81#ibcon#wrote, iclass 23, count 0 2006.210.08:17:01.81#ibcon#about to read 3, iclass 23, count 0 2006.210.08:17:01.84#ibcon#read 3, iclass 23, count 0 2006.210.08:17:01.84#ibcon#about to read 4, iclass 23, count 0 2006.210.08:17:01.84#ibcon#read 4, iclass 23, count 0 2006.210.08:17:01.84#ibcon#about to read 5, iclass 23, count 0 2006.210.08:17:01.84#ibcon#read 5, iclass 23, count 0 2006.210.08:17:01.84#ibcon#about to read 6, iclass 23, count 0 2006.210.08:17:01.84#ibcon#read 6, iclass 23, count 0 2006.210.08:17:01.84#ibcon#end of sib2, iclass 23, count 0 2006.210.08:17:01.84#ibcon#*after write, iclass 23, count 0 2006.210.08:17:01.84#ibcon#*before return 0, iclass 23, count 0 2006.210.08:17:01.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:17:01.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:17:01.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:17:01.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:17:01.84$vc4f8/vblo=6,752.99 2006.210.08:17:01.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:17:01.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:17:01.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:17:01.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:17:01.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:17:01.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:17:01.84#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:17:01.84#ibcon#first serial, iclass 25, count 0 2006.210.08:17:01.84#ibcon#enter sib2, iclass 25, count 0 2006.210.08:17:01.84#ibcon#flushed, iclass 25, count 0 2006.210.08:17:01.84#ibcon#about to write, iclass 25, count 0 2006.210.08:17:01.84#ibcon#wrote, iclass 25, count 0 2006.210.08:17:01.84#ibcon#about to read 3, iclass 25, count 0 2006.210.08:17:01.86#ibcon#read 3, iclass 25, count 0 2006.210.08:17:01.86#ibcon#about to read 4, iclass 25, count 0 2006.210.08:17:01.86#ibcon#read 4, iclass 25, count 0 2006.210.08:17:01.86#ibcon#about to read 5, iclass 25, count 0 2006.210.08:17:01.86#ibcon#read 5, iclass 25, count 0 2006.210.08:17:01.86#ibcon#about to read 6, iclass 25, count 0 2006.210.08:17:01.86#ibcon#read 6, iclass 25, count 0 2006.210.08:17:01.86#ibcon#end of sib2, iclass 25, count 0 2006.210.08:17:01.86#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:17:01.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:17:01.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:17:01.86#ibcon#*before write, iclass 25, count 0 2006.210.08:17:01.86#ibcon#enter sib2, iclass 25, count 0 2006.210.08:17:01.86#ibcon#flushed, iclass 25, count 0 2006.210.08:17:01.86#ibcon#about to write, iclass 25, count 0 2006.210.08:17:01.86#ibcon#wrote, iclass 25, count 0 2006.210.08:17:01.86#ibcon#about to read 3, iclass 25, count 0 2006.210.08:17:01.90#ibcon#read 3, iclass 25, count 0 2006.210.08:17:01.90#ibcon#about to read 4, iclass 25, count 0 2006.210.08:17:01.90#ibcon#read 4, iclass 25, count 0 2006.210.08:17:01.90#ibcon#about to read 5, iclass 25, count 0 2006.210.08:17:01.90#ibcon#read 5, iclass 25, count 0 2006.210.08:17:01.90#ibcon#about to read 6, iclass 25, count 0 2006.210.08:17:01.90#ibcon#read 6, iclass 25, count 0 2006.210.08:17:01.90#ibcon#end of sib2, iclass 25, count 0 2006.210.08:17:01.90#ibcon#*after write, iclass 25, count 0 2006.210.08:17:01.90#ibcon#*before return 0, iclass 25, count 0 2006.210.08:17:01.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:17:01.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:17:01.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:17:01.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:17:01.90$vc4f8/vb=6,3 2006.210.08:17:01.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:17:01.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:17:01.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:17:01.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:17:01.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:17:01.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:17:01.96#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:17:01.96#ibcon#first serial, iclass 27, count 2 2006.210.08:17:01.96#ibcon#enter sib2, iclass 27, count 2 2006.210.08:17:01.96#ibcon#flushed, iclass 27, count 2 2006.210.08:17:01.96#ibcon#about to write, iclass 27, count 2 2006.210.08:17:01.96#ibcon#wrote, iclass 27, count 2 2006.210.08:17:01.96#ibcon#about to read 3, iclass 27, count 2 2006.210.08:17:01.98#ibcon#read 3, iclass 27, count 2 2006.210.08:17:01.98#ibcon#about to read 4, iclass 27, count 2 2006.210.08:17:01.98#ibcon#read 4, iclass 27, count 2 2006.210.08:17:01.98#ibcon#about to read 5, iclass 27, count 2 2006.210.08:17:01.98#ibcon#read 5, iclass 27, count 2 2006.210.08:17:01.98#ibcon#about to read 6, iclass 27, count 2 2006.210.08:17:01.98#ibcon#read 6, iclass 27, count 2 2006.210.08:17:01.98#ibcon#end of sib2, iclass 27, count 2 2006.210.08:17:01.98#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:17:01.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:17:01.98#ibcon#[27=AT06-03\r\n] 2006.210.08:17:01.98#ibcon#*before write, iclass 27, count 2 2006.210.08:17:01.98#ibcon#enter sib2, iclass 27, count 2 2006.210.08:17:01.98#ibcon#flushed, iclass 27, count 2 2006.210.08:17:01.98#ibcon#about to write, iclass 27, count 2 2006.210.08:17:01.98#ibcon#wrote, iclass 27, count 2 2006.210.08:17:01.98#ibcon#about to read 3, iclass 27, count 2 2006.210.08:17:02.01#ibcon#read 3, iclass 27, count 2 2006.210.08:17:02.01#ibcon#about to read 4, iclass 27, count 2 2006.210.08:17:02.01#ibcon#read 4, iclass 27, count 2 2006.210.08:17:02.01#ibcon#about to read 5, iclass 27, count 2 2006.210.08:17:02.01#ibcon#read 5, iclass 27, count 2 2006.210.08:17:02.01#ibcon#about to read 6, iclass 27, count 2 2006.210.08:17:02.01#ibcon#read 6, iclass 27, count 2 2006.210.08:17:02.01#ibcon#end of sib2, iclass 27, count 2 2006.210.08:17:02.01#ibcon#*after write, iclass 27, count 2 2006.210.08:17:02.01#ibcon#*before return 0, iclass 27, count 2 2006.210.08:17:02.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:17:02.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:17:02.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:17:02.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:17:02.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:17:02.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:17:02.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:17:02.13#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:17:02.13#ibcon#first serial, iclass 27, count 0 2006.210.08:17:02.13#ibcon#enter sib2, iclass 27, count 0 2006.210.08:17:02.13#ibcon#flushed, iclass 27, count 0 2006.210.08:17:02.13#ibcon#about to write, iclass 27, count 0 2006.210.08:17:02.13#ibcon#wrote, iclass 27, count 0 2006.210.08:17:02.13#ibcon#about to read 3, iclass 27, count 0 2006.210.08:17:02.15#ibcon#read 3, iclass 27, count 0 2006.210.08:17:02.15#ibcon#about to read 4, iclass 27, count 0 2006.210.08:17:02.15#ibcon#read 4, iclass 27, count 0 2006.210.08:17:02.15#ibcon#about to read 5, iclass 27, count 0 2006.210.08:17:02.15#ibcon#read 5, iclass 27, count 0 2006.210.08:17:02.15#ibcon#about to read 6, iclass 27, count 0 2006.210.08:17:02.15#ibcon#read 6, iclass 27, count 0 2006.210.08:17:02.15#ibcon#end of sib2, iclass 27, count 0 2006.210.08:17:02.15#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:17:02.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:17:02.15#ibcon#[27=USB\r\n] 2006.210.08:17:02.15#ibcon#*before write, iclass 27, count 0 2006.210.08:17:02.15#ibcon#enter sib2, iclass 27, count 0 2006.210.08:17:02.15#ibcon#flushed, iclass 27, count 0 2006.210.08:17:02.15#ibcon#about to write, iclass 27, count 0 2006.210.08:17:02.15#ibcon#wrote, iclass 27, count 0 2006.210.08:17:02.15#ibcon#about to read 3, iclass 27, count 0 2006.210.08:17:02.18#ibcon#read 3, iclass 27, count 0 2006.210.08:17:02.18#ibcon#about to read 4, iclass 27, count 0 2006.210.08:17:02.18#ibcon#read 4, iclass 27, count 0 2006.210.08:17:02.18#ibcon#about to read 5, iclass 27, count 0 2006.210.08:17:02.18#ibcon#read 5, iclass 27, count 0 2006.210.08:17:02.18#ibcon#about to read 6, iclass 27, count 0 2006.210.08:17:02.18#ibcon#read 6, iclass 27, count 0 2006.210.08:17:02.18#ibcon#end of sib2, iclass 27, count 0 2006.210.08:17:02.18#ibcon#*after write, iclass 27, count 0 2006.210.08:17:02.18#ibcon#*before return 0, iclass 27, count 0 2006.210.08:17:02.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:17:02.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:17:02.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:17:02.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:17:02.18$vc4f8/vabw=wide 2006.210.08:17:02.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:17:02.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:17:02.18#ibcon#ireg 8 cls_cnt 0 2006.210.08:17:02.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:17:02.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:17:02.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:17:02.18#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:17:02.18#ibcon#first serial, iclass 29, count 0 2006.210.08:17:02.18#ibcon#enter sib2, iclass 29, count 0 2006.210.08:17:02.18#ibcon#flushed, iclass 29, count 0 2006.210.08:17:02.18#ibcon#about to write, iclass 29, count 0 2006.210.08:17:02.18#ibcon#wrote, iclass 29, count 0 2006.210.08:17:02.18#ibcon#about to read 3, iclass 29, count 0 2006.210.08:17:02.20#ibcon#read 3, iclass 29, count 0 2006.210.08:17:02.20#ibcon#about to read 4, iclass 29, count 0 2006.210.08:17:02.20#ibcon#read 4, iclass 29, count 0 2006.210.08:17:02.20#ibcon#about to read 5, iclass 29, count 0 2006.210.08:17:02.20#ibcon#read 5, iclass 29, count 0 2006.210.08:17:02.20#ibcon#about to read 6, iclass 29, count 0 2006.210.08:17:02.20#ibcon#read 6, iclass 29, count 0 2006.210.08:17:02.20#ibcon#end of sib2, iclass 29, count 0 2006.210.08:17:02.20#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:17:02.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:17:02.20#ibcon#[25=BW32\r\n] 2006.210.08:17:02.20#ibcon#*before write, iclass 29, count 0 2006.210.08:17:02.20#ibcon#enter sib2, iclass 29, count 0 2006.210.08:17:02.20#ibcon#flushed, iclass 29, count 0 2006.210.08:17:02.20#ibcon#about to write, iclass 29, count 0 2006.210.08:17:02.20#ibcon#wrote, iclass 29, count 0 2006.210.08:17:02.20#ibcon#about to read 3, iclass 29, count 0 2006.210.08:17:02.23#ibcon#read 3, iclass 29, count 0 2006.210.08:17:02.23#ibcon#about to read 4, iclass 29, count 0 2006.210.08:17:02.23#ibcon#read 4, iclass 29, count 0 2006.210.08:17:02.23#ibcon#about to read 5, iclass 29, count 0 2006.210.08:17:02.23#ibcon#read 5, iclass 29, count 0 2006.210.08:17:02.23#ibcon#about to read 6, iclass 29, count 0 2006.210.08:17:02.23#ibcon#read 6, iclass 29, count 0 2006.210.08:17:02.23#ibcon#end of sib2, iclass 29, count 0 2006.210.08:17:02.23#ibcon#*after write, iclass 29, count 0 2006.210.08:17:02.23#ibcon#*before return 0, iclass 29, count 0 2006.210.08:17:02.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:17:02.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:17:02.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:17:02.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:17:02.23$vc4f8/vbbw=wide 2006.210.08:17:02.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.08:17:02.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.08:17:02.23#ibcon#ireg 8 cls_cnt 0 2006.210.08:17:02.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:17:02.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:17:02.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:17:02.30#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:17:02.30#ibcon#first serial, iclass 31, count 0 2006.210.08:17:02.30#ibcon#enter sib2, iclass 31, count 0 2006.210.08:17:02.30#ibcon#flushed, iclass 31, count 0 2006.210.08:17:02.30#ibcon#about to write, iclass 31, count 0 2006.210.08:17:02.30#ibcon#wrote, iclass 31, count 0 2006.210.08:17:02.30#ibcon#about to read 3, iclass 31, count 0 2006.210.08:17:02.32#ibcon#read 3, iclass 31, count 0 2006.210.08:17:02.32#ibcon#about to read 4, iclass 31, count 0 2006.210.08:17:02.32#ibcon#read 4, iclass 31, count 0 2006.210.08:17:02.32#ibcon#about to read 5, iclass 31, count 0 2006.210.08:17:02.32#ibcon#read 5, iclass 31, count 0 2006.210.08:17:02.32#ibcon#about to read 6, iclass 31, count 0 2006.210.08:17:02.32#ibcon#read 6, iclass 31, count 0 2006.210.08:17:02.32#ibcon#end of sib2, iclass 31, count 0 2006.210.08:17:02.32#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:17:02.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:17:02.32#ibcon#[27=BW32\r\n] 2006.210.08:17:02.32#ibcon#*before write, iclass 31, count 0 2006.210.08:17:02.32#ibcon#enter sib2, iclass 31, count 0 2006.210.08:17:02.32#ibcon#flushed, iclass 31, count 0 2006.210.08:17:02.32#ibcon#about to write, iclass 31, count 0 2006.210.08:17:02.32#ibcon#wrote, iclass 31, count 0 2006.210.08:17:02.32#ibcon#about to read 3, iclass 31, count 0 2006.210.08:17:02.35#ibcon#read 3, iclass 31, count 0 2006.210.08:17:02.35#ibcon#about to read 4, iclass 31, count 0 2006.210.08:17:02.35#ibcon#read 4, iclass 31, count 0 2006.210.08:17:02.35#ibcon#about to read 5, iclass 31, count 0 2006.210.08:17:02.35#ibcon#read 5, iclass 31, count 0 2006.210.08:17:02.35#ibcon#about to read 6, iclass 31, count 0 2006.210.08:17:02.35#ibcon#read 6, iclass 31, count 0 2006.210.08:17:02.35#ibcon#end of sib2, iclass 31, count 0 2006.210.08:17:02.35#ibcon#*after write, iclass 31, count 0 2006.210.08:17:02.35#ibcon#*before return 0, iclass 31, count 0 2006.210.08:17:02.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:17:02.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:17:02.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:17:02.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:17:02.35$4f8m12a/ifd4f 2006.210.08:17:02.35$ifd4f/lo= 2006.210.08:17:02.35$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:17:02.35$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:17:02.35$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:17:02.35$ifd4f/patch= 2006.210.08:17:02.35$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:17:02.35$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:17:02.35$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:17:02.35$4f8m12a/"form=m,16.000,1:2 2006.210.08:17:02.35$4f8m12a/"tpicd 2006.210.08:17:02.35$4f8m12a/echo=off 2006.210.08:17:02.35$4f8m12a/xlog=off 2006.210.08:17:02.35:!2006.210.08:17:50 2006.210.08:17:30.14#trakl#Source acquired 2006.210.08:17:32.14#flagr#flagr/antenna,acquired 2006.210.08:17:50.00:preob 2006.210.08:17:51.14/onsource/TRACKING 2006.210.08:17:51.14:!2006.210.08:18:00 2006.210.08:18:00.00:data_valid=on 2006.210.08:18:00.00:midob 2006.210.08:18:00.14/onsource/TRACKING 2006.210.08:18:00.14/wx/29.88,1006.4,83 2006.210.08:18:00.26/cable/+6.3954E-03 2006.210.08:18:01.35/va/01,08,usb,yes,29,30 2006.210.08:18:01.35/va/02,07,usb,yes,29,30 2006.210.08:18:01.35/va/03,06,usb,yes,30,31 2006.210.08:18:01.35/va/04,07,usb,yes,30,32 2006.210.08:18:01.35/va/05,07,usb,yes,31,33 2006.210.08:18:01.35/va/06,06,usb,yes,30,30 2006.210.08:18:01.35/va/07,06,usb,yes,30,30 2006.210.08:18:01.35/va/08,07,usb,yes,29,28 2006.210.08:18:01.58/valo/01,532.99,yes,locked 2006.210.08:18:01.58/valo/02,572.99,yes,locked 2006.210.08:18:01.58/valo/03,672.99,yes,locked 2006.210.08:18:01.58/valo/04,832.99,yes,locked 2006.210.08:18:01.58/valo/05,652.99,yes,locked 2006.210.08:18:01.58/valo/06,772.99,yes,locked 2006.210.08:18:01.58/valo/07,832.99,yes,locked 2006.210.08:18:01.58/valo/08,852.99,yes,locked 2006.210.08:18:02.67/vb/01,04,usb,yes,28,27 2006.210.08:18:02.67/vb/02,04,usb,yes,30,31 2006.210.08:18:02.67/vb/03,03,usb,yes,33,37 2006.210.08:18:02.67/vb/04,03,usb,yes,34,34 2006.210.08:18:02.67/vb/05,03,usb,yes,32,37 2006.210.08:18:02.67/vb/06,03,usb,yes,33,36 2006.210.08:18:02.67/vb/07,04,usb,yes,29,29 2006.210.08:18:02.67/vb/08,03,usb,yes,33,37 2006.210.08:18:02.91/vblo/01,632.99,yes,locked 2006.210.08:18:02.91/vblo/02,640.99,yes,locked 2006.210.08:18:02.91/vblo/03,656.99,yes,locked 2006.210.08:18:02.91/vblo/04,712.99,yes,locked 2006.210.08:18:02.91/vblo/05,744.99,yes,locked 2006.210.08:18:02.91/vblo/06,752.99,yes,locked 2006.210.08:18:02.91/vblo/07,734.99,yes,locked 2006.210.08:18:02.91/vblo/08,744.99,yes,locked 2006.210.08:18:03.06/vabw/8 2006.210.08:18:03.21/vbbw/8 2006.210.08:18:03.30/xfe/off,on,15.7 2006.210.08:18:03.66/ifatt/23,28,28,28 2006.210.08:18:04.07/fmout-gps/S +4.59E-07 2006.210.08:18:04.11:!2006.210.08:19:10 2006.210.08:19:10.00:data_valid=off 2006.210.08:19:10.00:postob 2006.210.08:19:10.17/cable/+6.3962E-03 2006.210.08:19:10.17/wx/29.85,1006.4,82 2006.210.08:19:11.07/fmout-gps/S +4.57E-07 2006.210.08:19:11.07:scan_name=210-0821,k06210,60 2006.210.08:19:11.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.210.08:19:12.14#flagr#flagr/antenna,new-source 2006.210.08:19:12.14:checkk5 2006.210.08:19:12.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:19:12.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:19:13.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:19:13.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:19:13.85/chk_obsdata//k5ts1/T2100818??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.210.08:19:14.18/chk_obsdata//k5ts2/T2100818??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.210.08:19:14.52/chk_obsdata//k5ts3/T2100818??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.210.08:19:14.85/chk_obsdata//k5ts4/T2100818??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.210.08:19:15.51/k5log//k5ts1_log_newline 2006.210.08:19:16.17/k5log//k5ts2_log_newline 2006.210.08:19:16.83/k5log//k5ts3_log_newline 2006.210.08:19:17.48/k5log//k5ts4_log_newline 2006.210.08:19:17.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:19:17.51:4f8m12a=3 2006.210.08:19:17.51$4f8m12a/echo=on 2006.210.08:19:17.51$4f8m12a/pcalon 2006.210.08:19:17.51$pcalon/"no phase cal control is implemented here 2006.210.08:19:17.51$4f8m12a/"tpicd=stop 2006.210.08:19:17.51$4f8m12a/vc4f8 2006.210.08:19:17.51$vc4f8/valo=1,532.99 2006.210.08:19:17.51#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:19:17.51#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:19:17.51#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:17.51#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:17.51#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:17.51#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:17.51#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:19:17.51#ibcon#first serial, iclass 7, count 0 2006.210.08:19:17.51#ibcon#enter sib2, iclass 7, count 0 2006.210.08:19:17.51#ibcon#flushed, iclass 7, count 0 2006.210.08:19:17.51#ibcon#about to write, iclass 7, count 0 2006.210.08:19:17.51#ibcon#wrote, iclass 7, count 0 2006.210.08:19:17.51#ibcon#about to read 3, iclass 7, count 0 2006.210.08:19:17.53#ibcon#read 3, iclass 7, count 0 2006.210.08:19:17.53#ibcon#about to read 4, iclass 7, count 0 2006.210.08:19:17.53#ibcon#read 4, iclass 7, count 0 2006.210.08:19:17.53#ibcon#about to read 5, iclass 7, count 0 2006.210.08:19:17.53#ibcon#read 5, iclass 7, count 0 2006.210.08:19:17.53#ibcon#about to read 6, iclass 7, count 0 2006.210.08:19:17.53#ibcon#read 6, iclass 7, count 0 2006.210.08:19:17.53#ibcon#end of sib2, iclass 7, count 0 2006.210.08:19:17.53#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:19:17.53#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:19:17.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:19:17.53#ibcon#*before write, iclass 7, count 0 2006.210.08:19:17.53#ibcon#enter sib2, iclass 7, count 0 2006.210.08:19:17.53#ibcon#flushed, iclass 7, count 0 2006.210.08:19:17.53#ibcon#about to write, iclass 7, count 0 2006.210.08:19:17.53#ibcon#wrote, iclass 7, count 0 2006.210.08:19:17.53#ibcon#about to read 3, iclass 7, count 0 2006.210.08:19:17.58#ibcon#read 3, iclass 7, count 0 2006.210.08:19:17.58#ibcon#about to read 4, iclass 7, count 0 2006.210.08:19:17.58#ibcon#read 4, iclass 7, count 0 2006.210.08:19:17.58#ibcon#about to read 5, iclass 7, count 0 2006.210.08:19:17.58#ibcon#read 5, iclass 7, count 0 2006.210.08:19:17.58#ibcon#about to read 6, iclass 7, count 0 2006.210.08:19:17.58#ibcon#read 6, iclass 7, count 0 2006.210.08:19:17.58#ibcon#end of sib2, iclass 7, count 0 2006.210.08:19:17.58#ibcon#*after write, iclass 7, count 0 2006.210.08:19:17.58#ibcon#*before return 0, iclass 7, count 0 2006.210.08:19:17.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:17.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:17.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:19:17.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:19:17.58$vc4f8/va=1,8 2006.210.08:19:17.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:19:17.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:19:17.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:17.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:17.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:17.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:17.58#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:19:17.58#ibcon#first serial, iclass 11, count 2 2006.210.08:19:17.58#ibcon#enter sib2, iclass 11, count 2 2006.210.08:19:17.58#ibcon#flushed, iclass 11, count 2 2006.210.08:19:17.58#ibcon#about to write, iclass 11, count 2 2006.210.08:19:17.58#ibcon#wrote, iclass 11, count 2 2006.210.08:19:17.58#ibcon#about to read 3, iclass 11, count 2 2006.210.08:19:17.60#ibcon#read 3, iclass 11, count 2 2006.210.08:19:17.60#ibcon#about to read 4, iclass 11, count 2 2006.210.08:19:17.60#ibcon#read 4, iclass 11, count 2 2006.210.08:19:17.60#ibcon#about to read 5, iclass 11, count 2 2006.210.08:19:17.60#ibcon#read 5, iclass 11, count 2 2006.210.08:19:17.60#ibcon#about to read 6, iclass 11, count 2 2006.210.08:19:17.60#ibcon#read 6, iclass 11, count 2 2006.210.08:19:17.60#ibcon#end of sib2, iclass 11, count 2 2006.210.08:19:17.60#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:19:17.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:19:17.60#ibcon#[25=AT01-08\r\n] 2006.210.08:19:17.60#ibcon#*before write, iclass 11, count 2 2006.210.08:19:17.60#ibcon#enter sib2, iclass 11, count 2 2006.210.08:19:17.60#ibcon#flushed, iclass 11, count 2 2006.210.08:19:17.60#ibcon#about to write, iclass 11, count 2 2006.210.08:19:17.60#ibcon#wrote, iclass 11, count 2 2006.210.08:19:17.60#ibcon#about to read 3, iclass 11, count 2 2006.210.08:19:17.63#ibcon#read 3, iclass 11, count 2 2006.210.08:19:17.63#ibcon#about to read 4, iclass 11, count 2 2006.210.08:19:17.63#ibcon#read 4, iclass 11, count 2 2006.210.08:19:17.63#ibcon#about to read 5, iclass 11, count 2 2006.210.08:19:17.63#ibcon#read 5, iclass 11, count 2 2006.210.08:19:17.63#ibcon#about to read 6, iclass 11, count 2 2006.210.08:19:17.63#ibcon#read 6, iclass 11, count 2 2006.210.08:19:17.63#ibcon#end of sib2, iclass 11, count 2 2006.210.08:19:17.63#ibcon#*after write, iclass 11, count 2 2006.210.08:19:17.63#ibcon#*before return 0, iclass 11, count 2 2006.210.08:19:17.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:17.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:17.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:19:17.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:17.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:17.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:17.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:17.75#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:19:17.75#ibcon#first serial, iclass 11, count 0 2006.210.08:19:17.75#ibcon#enter sib2, iclass 11, count 0 2006.210.08:19:17.75#ibcon#flushed, iclass 11, count 0 2006.210.08:19:17.75#ibcon#about to write, iclass 11, count 0 2006.210.08:19:17.75#ibcon#wrote, iclass 11, count 0 2006.210.08:19:17.75#ibcon#about to read 3, iclass 11, count 0 2006.210.08:19:17.77#ibcon#read 3, iclass 11, count 0 2006.210.08:19:17.77#ibcon#about to read 4, iclass 11, count 0 2006.210.08:19:17.77#ibcon#read 4, iclass 11, count 0 2006.210.08:19:17.77#ibcon#about to read 5, iclass 11, count 0 2006.210.08:19:17.77#ibcon#read 5, iclass 11, count 0 2006.210.08:19:17.77#ibcon#about to read 6, iclass 11, count 0 2006.210.08:19:17.77#ibcon#read 6, iclass 11, count 0 2006.210.08:19:17.77#ibcon#end of sib2, iclass 11, count 0 2006.210.08:19:17.77#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:19:17.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:19:17.77#ibcon#[25=USB\r\n] 2006.210.08:19:17.77#ibcon#*before write, iclass 11, count 0 2006.210.08:19:17.77#ibcon#enter sib2, iclass 11, count 0 2006.210.08:19:17.77#ibcon#flushed, iclass 11, count 0 2006.210.08:19:17.77#ibcon#about to write, iclass 11, count 0 2006.210.08:19:17.77#ibcon#wrote, iclass 11, count 0 2006.210.08:19:17.77#ibcon#about to read 3, iclass 11, count 0 2006.210.08:19:17.80#ibcon#read 3, iclass 11, count 0 2006.210.08:19:17.80#ibcon#about to read 4, iclass 11, count 0 2006.210.08:19:17.80#ibcon#read 4, iclass 11, count 0 2006.210.08:19:17.80#ibcon#about to read 5, iclass 11, count 0 2006.210.08:19:17.80#ibcon#read 5, iclass 11, count 0 2006.210.08:19:17.80#ibcon#about to read 6, iclass 11, count 0 2006.210.08:19:17.80#ibcon#read 6, iclass 11, count 0 2006.210.08:19:17.80#ibcon#end of sib2, iclass 11, count 0 2006.210.08:19:17.80#ibcon#*after write, iclass 11, count 0 2006.210.08:19:17.80#ibcon#*before return 0, iclass 11, count 0 2006.210.08:19:17.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:17.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:17.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:19:17.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:19:17.80$vc4f8/valo=2,572.99 2006.210.08:19:17.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:19:17.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:19:17.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:17.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:17.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:17.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:17.80#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:19:17.80#ibcon#first serial, iclass 13, count 0 2006.210.08:19:17.80#ibcon#enter sib2, iclass 13, count 0 2006.210.08:19:17.80#ibcon#flushed, iclass 13, count 0 2006.210.08:19:17.80#ibcon#about to write, iclass 13, count 0 2006.210.08:19:17.80#ibcon#wrote, iclass 13, count 0 2006.210.08:19:17.80#ibcon#about to read 3, iclass 13, count 0 2006.210.08:19:17.82#ibcon#read 3, iclass 13, count 0 2006.210.08:19:17.82#ibcon#about to read 4, iclass 13, count 0 2006.210.08:19:17.82#ibcon#read 4, iclass 13, count 0 2006.210.08:19:17.82#ibcon#about to read 5, iclass 13, count 0 2006.210.08:19:17.82#ibcon#read 5, iclass 13, count 0 2006.210.08:19:17.82#ibcon#about to read 6, iclass 13, count 0 2006.210.08:19:17.82#ibcon#read 6, iclass 13, count 0 2006.210.08:19:17.82#ibcon#end of sib2, iclass 13, count 0 2006.210.08:19:17.82#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:19:17.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:19:17.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:19:17.82#ibcon#*before write, iclass 13, count 0 2006.210.08:19:17.82#ibcon#enter sib2, iclass 13, count 0 2006.210.08:19:17.82#ibcon#flushed, iclass 13, count 0 2006.210.08:19:17.82#ibcon#about to write, iclass 13, count 0 2006.210.08:19:17.82#ibcon#wrote, iclass 13, count 0 2006.210.08:19:17.82#ibcon#about to read 3, iclass 13, count 0 2006.210.08:19:17.86#ibcon#read 3, iclass 13, count 0 2006.210.08:19:17.86#ibcon#about to read 4, iclass 13, count 0 2006.210.08:19:17.86#ibcon#read 4, iclass 13, count 0 2006.210.08:19:17.86#ibcon#about to read 5, iclass 13, count 0 2006.210.08:19:17.86#ibcon#read 5, iclass 13, count 0 2006.210.08:19:17.86#ibcon#about to read 6, iclass 13, count 0 2006.210.08:19:17.86#ibcon#read 6, iclass 13, count 0 2006.210.08:19:17.86#ibcon#end of sib2, iclass 13, count 0 2006.210.08:19:17.86#ibcon#*after write, iclass 13, count 0 2006.210.08:19:17.86#ibcon#*before return 0, iclass 13, count 0 2006.210.08:19:17.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:17.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:17.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:19:17.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:19:17.86$vc4f8/va=2,7 2006.210.08:19:17.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:19:17.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:19:17.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:17.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:17.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:17.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:17.92#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:19:17.92#ibcon#first serial, iclass 15, count 2 2006.210.08:19:17.92#ibcon#enter sib2, iclass 15, count 2 2006.210.08:19:17.92#ibcon#flushed, iclass 15, count 2 2006.210.08:19:17.92#ibcon#about to write, iclass 15, count 2 2006.210.08:19:17.92#ibcon#wrote, iclass 15, count 2 2006.210.08:19:17.92#ibcon#about to read 3, iclass 15, count 2 2006.210.08:19:17.94#ibcon#read 3, iclass 15, count 2 2006.210.08:19:17.94#ibcon#about to read 4, iclass 15, count 2 2006.210.08:19:17.94#ibcon#read 4, iclass 15, count 2 2006.210.08:19:17.94#ibcon#about to read 5, iclass 15, count 2 2006.210.08:19:17.94#ibcon#read 5, iclass 15, count 2 2006.210.08:19:17.94#ibcon#about to read 6, iclass 15, count 2 2006.210.08:19:17.94#ibcon#read 6, iclass 15, count 2 2006.210.08:19:17.94#ibcon#end of sib2, iclass 15, count 2 2006.210.08:19:17.94#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:19:17.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:19:17.94#ibcon#[25=AT02-07\r\n] 2006.210.08:19:17.94#ibcon#*before write, iclass 15, count 2 2006.210.08:19:17.94#ibcon#enter sib2, iclass 15, count 2 2006.210.08:19:17.94#ibcon#flushed, iclass 15, count 2 2006.210.08:19:17.94#ibcon#about to write, iclass 15, count 2 2006.210.08:19:17.94#ibcon#wrote, iclass 15, count 2 2006.210.08:19:17.94#ibcon#about to read 3, iclass 15, count 2 2006.210.08:19:17.97#ibcon#read 3, iclass 15, count 2 2006.210.08:19:17.97#ibcon#about to read 4, iclass 15, count 2 2006.210.08:19:17.97#ibcon#read 4, iclass 15, count 2 2006.210.08:19:17.97#ibcon#about to read 5, iclass 15, count 2 2006.210.08:19:17.97#ibcon#read 5, iclass 15, count 2 2006.210.08:19:17.97#ibcon#about to read 6, iclass 15, count 2 2006.210.08:19:17.97#ibcon#read 6, iclass 15, count 2 2006.210.08:19:17.97#ibcon#end of sib2, iclass 15, count 2 2006.210.08:19:17.97#ibcon#*after write, iclass 15, count 2 2006.210.08:19:17.97#ibcon#*before return 0, iclass 15, count 2 2006.210.08:19:17.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:17.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:17.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:19:17.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:17.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:18.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:18.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:18.09#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:19:18.09#ibcon#first serial, iclass 15, count 0 2006.210.08:19:18.09#ibcon#enter sib2, iclass 15, count 0 2006.210.08:19:18.09#ibcon#flushed, iclass 15, count 0 2006.210.08:19:18.09#ibcon#about to write, iclass 15, count 0 2006.210.08:19:18.09#ibcon#wrote, iclass 15, count 0 2006.210.08:19:18.09#ibcon#about to read 3, iclass 15, count 0 2006.210.08:19:18.11#ibcon#read 3, iclass 15, count 0 2006.210.08:19:18.11#ibcon#about to read 4, iclass 15, count 0 2006.210.08:19:18.11#ibcon#read 4, iclass 15, count 0 2006.210.08:19:18.11#ibcon#about to read 5, iclass 15, count 0 2006.210.08:19:18.11#ibcon#read 5, iclass 15, count 0 2006.210.08:19:18.11#ibcon#about to read 6, iclass 15, count 0 2006.210.08:19:18.11#ibcon#read 6, iclass 15, count 0 2006.210.08:19:18.11#ibcon#end of sib2, iclass 15, count 0 2006.210.08:19:18.11#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:19:18.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:19:18.11#ibcon#[25=USB\r\n] 2006.210.08:19:18.11#ibcon#*before write, iclass 15, count 0 2006.210.08:19:18.11#ibcon#enter sib2, iclass 15, count 0 2006.210.08:19:18.11#ibcon#flushed, iclass 15, count 0 2006.210.08:19:18.11#ibcon#about to write, iclass 15, count 0 2006.210.08:19:18.11#ibcon#wrote, iclass 15, count 0 2006.210.08:19:18.11#ibcon#about to read 3, iclass 15, count 0 2006.210.08:19:18.14#ibcon#read 3, iclass 15, count 0 2006.210.08:19:18.14#ibcon#about to read 4, iclass 15, count 0 2006.210.08:19:18.14#ibcon#read 4, iclass 15, count 0 2006.210.08:19:18.14#ibcon#about to read 5, iclass 15, count 0 2006.210.08:19:18.14#ibcon#read 5, iclass 15, count 0 2006.210.08:19:18.14#ibcon#about to read 6, iclass 15, count 0 2006.210.08:19:18.14#ibcon#read 6, iclass 15, count 0 2006.210.08:19:18.14#ibcon#end of sib2, iclass 15, count 0 2006.210.08:19:18.14#ibcon#*after write, iclass 15, count 0 2006.210.08:19:18.14#ibcon#*before return 0, iclass 15, count 0 2006.210.08:19:18.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:18.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:18.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:19:18.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:19:18.14$vc4f8/valo=3,672.99 2006.210.08:19:18.14#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:19:18.14#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:19:18.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:18.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:19:18.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:19:18.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:19:18.14#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:19:18.14#ibcon#first serial, iclass 17, count 0 2006.210.08:19:18.14#ibcon#enter sib2, iclass 17, count 0 2006.210.08:19:18.14#ibcon#flushed, iclass 17, count 0 2006.210.08:19:18.14#ibcon#about to write, iclass 17, count 0 2006.210.08:19:18.14#ibcon#wrote, iclass 17, count 0 2006.210.08:19:18.14#ibcon#about to read 3, iclass 17, count 0 2006.210.08:19:18.16#ibcon#read 3, iclass 17, count 0 2006.210.08:19:18.16#ibcon#about to read 4, iclass 17, count 0 2006.210.08:19:18.16#ibcon#read 4, iclass 17, count 0 2006.210.08:19:18.16#ibcon#about to read 5, iclass 17, count 0 2006.210.08:19:18.16#ibcon#read 5, iclass 17, count 0 2006.210.08:19:18.16#ibcon#about to read 6, iclass 17, count 0 2006.210.08:19:18.16#ibcon#read 6, iclass 17, count 0 2006.210.08:19:18.16#ibcon#end of sib2, iclass 17, count 0 2006.210.08:19:18.16#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:19:18.16#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:19:18.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:19:18.16#ibcon#*before write, iclass 17, count 0 2006.210.08:19:18.16#ibcon#enter sib2, iclass 17, count 0 2006.210.08:19:18.16#ibcon#flushed, iclass 17, count 0 2006.210.08:19:18.16#ibcon#about to write, iclass 17, count 0 2006.210.08:19:18.16#ibcon#wrote, iclass 17, count 0 2006.210.08:19:18.16#ibcon#about to read 3, iclass 17, count 0 2006.210.08:19:18.20#ibcon#read 3, iclass 17, count 0 2006.210.08:19:18.20#ibcon#about to read 4, iclass 17, count 0 2006.210.08:19:18.20#ibcon#read 4, iclass 17, count 0 2006.210.08:19:18.20#ibcon#about to read 5, iclass 17, count 0 2006.210.08:19:18.20#ibcon#read 5, iclass 17, count 0 2006.210.08:19:18.20#ibcon#about to read 6, iclass 17, count 0 2006.210.08:19:18.20#ibcon#read 6, iclass 17, count 0 2006.210.08:19:18.20#ibcon#end of sib2, iclass 17, count 0 2006.210.08:19:18.20#ibcon#*after write, iclass 17, count 0 2006.210.08:19:18.20#ibcon#*before return 0, iclass 17, count 0 2006.210.08:19:18.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:19:18.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:19:18.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:19:18.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:19:18.20$vc4f8/va=3,6 2006.210.08:19:18.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.210.08:19:18.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.210.08:19:18.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:18.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:19:18.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:19:18.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:19:18.26#ibcon#enter wrdev, iclass 19, count 2 2006.210.08:19:18.26#ibcon#first serial, iclass 19, count 2 2006.210.08:19:18.26#ibcon#enter sib2, iclass 19, count 2 2006.210.08:19:18.26#ibcon#flushed, iclass 19, count 2 2006.210.08:19:18.26#ibcon#about to write, iclass 19, count 2 2006.210.08:19:18.26#ibcon#wrote, iclass 19, count 2 2006.210.08:19:18.26#ibcon#about to read 3, iclass 19, count 2 2006.210.08:19:18.28#ibcon#read 3, iclass 19, count 2 2006.210.08:19:18.28#ibcon#about to read 4, iclass 19, count 2 2006.210.08:19:18.28#ibcon#read 4, iclass 19, count 2 2006.210.08:19:18.28#ibcon#about to read 5, iclass 19, count 2 2006.210.08:19:18.28#ibcon#read 5, iclass 19, count 2 2006.210.08:19:18.28#ibcon#about to read 6, iclass 19, count 2 2006.210.08:19:18.28#ibcon#read 6, iclass 19, count 2 2006.210.08:19:18.28#ibcon#end of sib2, iclass 19, count 2 2006.210.08:19:18.28#ibcon#*mode == 0, iclass 19, count 2 2006.210.08:19:18.28#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.210.08:19:18.28#ibcon#[25=AT03-06\r\n] 2006.210.08:19:18.28#ibcon#*before write, iclass 19, count 2 2006.210.08:19:18.28#ibcon#enter sib2, iclass 19, count 2 2006.210.08:19:18.28#ibcon#flushed, iclass 19, count 2 2006.210.08:19:18.28#ibcon#about to write, iclass 19, count 2 2006.210.08:19:18.28#ibcon#wrote, iclass 19, count 2 2006.210.08:19:18.28#ibcon#about to read 3, iclass 19, count 2 2006.210.08:19:18.31#ibcon#read 3, iclass 19, count 2 2006.210.08:19:18.31#ibcon#about to read 4, iclass 19, count 2 2006.210.08:19:18.31#ibcon#read 4, iclass 19, count 2 2006.210.08:19:18.31#ibcon#about to read 5, iclass 19, count 2 2006.210.08:19:18.31#ibcon#read 5, iclass 19, count 2 2006.210.08:19:18.31#ibcon#about to read 6, iclass 19, count 2 2006.210.08:19:18.31#ibcon#read 6, iclass 19, count 2 2006.210.08:19:18.31#ibcon#end of sib2, iclass 19, count 2 2006.210.08:19:18.31#ibcon#*after write, iclass 19, count 2 2006.210.08:19:18.31#ibcon#*before return 0, iclass 19, count 2 2006.210.08:19:18.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:19:18.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.210.08:19:18.31#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.210.08:19:18.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:18.31#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:19:18.43#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:19:18.43#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:19:18.43#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:19:18.43#ibcon#first serial, iclass 19, count 0 2006.210.08:19:18.43#ibcon#enter sib2, iclass 19, count 0 2006.210.08:19:18.43#ibcon#flushed, iclass 19, count 0 2006.210.08:19:18.43#ibcon#about to write, iclass 19, count 0 2006.210.08:19:18.43#ibcon#wrote, iclass 19, count 0 2006.210.08:19:18.43#ibcon#about to read 3, iclass 19, count 0 2006.210.08:19:18.45#ibcon#read 3, iclass 19, count 0 2006.210.08:19:18.45#ibcon#about to read 4, iclass 19, count 0 2006.210.08:19:18.45#ibcon#read 4, iclass 19, count 0 2006.210.08:19:18.45#ibcon#about to read 5, iclass 19, count 0 2006.210.08:19:18.45#ibcon#read 5, iclass 19, count 0 2006.210.08:19:18.45#ibcon#about to read 6, iclass 19, count 0 2006.210.08:19:18.45#ibcon#read 6, iclass 19, count 0 2006.210.08:19:18.45#ibcon#end of sib2, iclass 19, count 0 2006.210.08:19:18.45#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:19:18.45#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:19:18.45#ibcon#[25=USB\r\n] 2006.210.08:19:18.45#ibcon#*before write, iclass 19, count 0 2006.210.08:19:18.45#ibcon#enter sib2, iclass 19, count 0 2006.210.08:19:18.45#ibcon#flushed, iclass 19, count 0 2006.210.08:19:18.45#ibcon#about to write, iclass 19, count 0 2006.210.08:19:18.45#ibcon#wrote, iclass 19, count 0 2006.210.08:19:18.45#ibcon#about to read 3, iclass 19, count 0 2006.210.08:19:18.48#ibcon#read 3, iclass 19, count 0 2006.210.08:19:18.48#ibcon#about to read 4, iclass 19, count 0 2006.210.08:19:18.48#ibcon#read 4, iclass 19, count 0 2006.210.08:19:18.48#ibcon#about to read 5, iclass 19, count 0 2006.210.08:19:18.48#ibcon#read 5, iclass 19, count 0 2006.210.08:19:18.48#ibcon#about to read 6, iclass 19, count 0 2006.210.08:19:18.48#ibcon#read 6, iclass 19, count 0 2006.210.08:19:18.48#ibcon#end of sib2, iclass 19, count 0 2006.210.08:19:18.48#ibcon#*after write, iclass 19, count 0 2006.210.08:19:18.48#ibcon#*before return 0, iclass 19, count 0 2006.210.08:19:18.48#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:19:18.48#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.210.08:19:18.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:19:18.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:19:18.48$vc4f8/valo=4,832.99 2006.210.08:19:18.48#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:19:18.48#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:19:18.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:18.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:18.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:18.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:18.48#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:19:18.48#ibcon#first serial, iclass 21, count 0 2006.210.08:19:18.48#ibcon#enter sib2, iclass 21, count 0 2006.210.08:19:18.48#ibcon#flushed, iclass 21, count 0 2006.210.08:19:18.48#ibcon#about to write, iclass 21, count 0 2006.210.08:19:18.48#ibcon#wrote, iclass 21, count 0 2006.210.08:19:18.48#ibcon#about to read 3, iclass 21, count 0 2006.210.08:19:18.50#ibcon#read 3, iclass 21, count 0 2006.210.08:19:18.50#ibcon#about to read 4, iclass 21, count 0 2006.210.08:19:18.50#ibcon#read 4, iclass 21, count 0 2006.210.08:19:18.50#ibcon#about to read 5, iclass 21, count 0 2006.210.08:19:18.50#ibcon#read 5, iclass 21, count 0 2006.210.08:19:18.50#ibcon#about to read 6, iclass 21, count 0 2006.210.08:19:18.50#ibcon#read 6, iclass 21, count 0 2006.210.08:19:18.50#ibcon#end of sib2, iclass 21, count 0 2006.210.08:19:18.50#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:19:18.50#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:19:18.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:19:18.50#ibcon#*before write, iclass 21, count 0 2006.210.08:19:18.50#ibcon#enter sib2, iclass 21, count 0 2006.210.08:19:18.50#ibcon#flushed, iclass 21, count 0 2006.210.08:19:18.50#ibcon#about to write, iclass 21, count 0 2006.210.08:19:18.50#ibcon#wrote, iclass 21, count 0 2006.210.08:19:18.50#ibcon#about to read 3, iclass 21, count 0 2006.210.08:19:18.54#ibcon#read 3, iclass 21, count 0 2006.210.08:19:18.54#ibcon#about to read 4, iclass 21, count 0 2006.210.08:19:18.54#ibcon#read 4, iclass 21, count 0 2006.210.08:19:18.54#ibcon#about to read 5, iclass 21, count 0 2006.210.08:19:18.54#ibcon#read 5, iclass 21, count 0 2006.210.08:19:18.54#ibcon#about to read 6, iclass 21, count 0 2006.210.08:19:18.54#ibcon#read 6, iclass 21, count 0 2006.210.08:19:18.54#ibcon#end of sib2, iclass 21, count 0 2006.210.08:19:18.54#ibcon#*after write, iclass 21, count 0 2006.210.08:19:18.54#ibcon#*before return 0, iclass 21, count 0 2006.210.08:19:18.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:18.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:18.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:19:18.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:19:18.54$vc4f8/va=4,7 2006.210.08:19:18.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:19:18.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:19:18.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:18.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:18.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:18.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:18.60#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:19:18.60#ibcon#first serial, iclass 23, count 2 2006.210.08:19:18.60#ibcon#enter sib2, iclass 23, count 2 2006.210.08:19:18.60#ibcon#flushed, iclass 23, count 2 2006.210.08:19:18.60#ibcon#about to write, iclass 23, count 2 2006.210.08:19:18.60#ibcon#wrote, iclass 23, count 2 2006.210.08:19:18.60#ibcon#about to read 3, iclass 23, count 2 2006.210.08:19:18.62#ibcon#read 3, iclass 23, count 2 2006.210.08:19:18.62#ibcon#about to read 4, iclass 23, count 2 2006.210.08:19:18.62#ibcon#read 4, iclass 23, count 2 2006.210.08:19:18.62#ibcon#about to read 5, iclass 23, count 2 2006.210.08:19:18.62#ibcon#read 5, iclass 23, count 2 2006.210.08:19:18.62#ibcon#about to read 6, iclass 23, count 2 2006.210.08:19:18.62#ibcon#read 6, iclass 23, count 2 2006.210.08:19:18.62#ibcon#end of sib2, iclass 23, count 2 2006.210.08:19:18.62#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:19:18.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:19:18.62#ibcon#[25=AT04-07\r\n] 2006.210.08:19:18.62#ibcon#*before write, iclass 23, count 2 2006.210.08:19:18.62#ibcon#enter sib2, iclass 23, count 2 2006.210.08:19:18.62#ibcon#flushed, iclass 23, count 2 2006.210.08:19:18.62#ibcon#about to write, iclass 23, count 2 2006.210.08:19:18.62#ibcon#wrote, iclass 23, count 2 2006.210.08:19:18.62#ibcon#about to read 3, iclass 23, count 2 2006.210.08:19:18.65#ibcon#read 3, iclass 23, count 2 2006.210.08:19:18.65#ibcon#about to read 4, iclass 23, count 2 2006.210.08:19:18.65#ibcon#read 4, iclass 23, count 2 2006.210.08:19:18.65#ibcon#about to read 5, iclass 23, count 2 2006.210.08:19:18.65#ibcon#read 5, iclass 23, count 2 2006.210.08:19:18.65#ibcon#about to read 6, iclass 23, count 2 2006.210.08:19:18.65#ibcon#read 6, iclass 23, count 2 2006.210.08:19:18.65#ibcon#end of sib2, iclass 23, count 2 2006.210.08:19:18.65#ibcon#*after write, iclass 23, count 2 2006.210.08:19:18.65#ibcon#*before return 0, iclass 23, count 2 2006.210.08:19:18.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:18.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:18.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:19:18.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:18.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:18.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:18.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:18.77#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:19:18.77#ibcon#first serial, iclass 23, count 0 2006.210.08:19:18.77#ibcon#enter sib2, iclass 23, count 0 2006.210.08:19:18.77#ibcon#flushed, iclass 23, count 0 2006.210.08:19:18.77#ibcon#about to write, iclass 23, count 0 2006.210.08:19:18.77#ibcon#wrote, iclass 23, count 0 2006.210.08:19:18.77#ibcon#about to read 3, iclass 23, count 0 2006.210.08:19:18.79#ibcon#read 3, iclass 23, count 0 2006.210.08:19:18.79#ibcon#about to read 4, iclass 23, count 0 2006.210.08:19:18.79#ibcon#read 4, iclass 23, count 0 2006.210.08:19:18.79#ibcon#about to read 5, iclass 23, count 0 2006.210.08:19:18.79#ibcon#read 5, iclass 23, count 0 2006.210.08:19:18.79#ibcon#about to read 6, iclass 23, count 0 2006.210.08:19:18.79#ibcon#read 6, iclass 23, count 0 2006.210.08:19:18.79#ibcon#end of sib2, iclass 23, count 0 2006.210.08:19:18.79#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:19:18.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:19:18.79#ibcon#[25=USB\r\n] 2006.210.08:19:18.79#ibcon#*before write, iclass 23, count 0 2006.210.08:19:18.79#ibcon#enter sib2, iclass 23, count 0 2006.210.08:19:18.79#ibcon#flushed, iclass 23, count 0 2006.210.08:19:18.79#ibcon#about to write, iclass 23, count 0 2006.210.08:19:18.79#ibcon#wrote, iclass 23, count 0 2006.210.08:19:18.79#ibcon#about to read 3, iclass 23, count 0 2006.210.08:19:18.82#ibcon#read 3, iclass 23, count 0 2006.210.08:19:18.82#ibcon#about to read 4, iclass 23, count 0 2006.210.08:19:18.82#ibcon#read 4, iclass 23, count 0 2006.210.08:19:18.82#ibcon#about to read 5, iclass 23, count 0 2006.210.08:19:18.82#ibcon#read 5, iclass 23, count 0 2006.210.08:19:18.82#ibcon#about to read 6, iclass 23, count 0 2006.210.08:19:18.82#ibcon#read 6, iclass 23, count 0 2006.210.08:19:18.82#ibcon#end of sib2, iclass 23, count 0 2006.210.08:19:18.82#ibcon#*after write, iclass 23, count 0 2006.210.08:19:18.82#ibcon#*before return 0, iclass 23, count 0 2006.210.08:19:18.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:18.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:18.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:19:18.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:19:18.82$vc4f8/valo=5,652.99 2006.210.08:19:18.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:19:18.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:19:18.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:18.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:18.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:18.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:18.82#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:19:18.82#ibcon#first serial, iclass 25, count 0 2006.210.08:19:18.82#ibcon#enter sib2, iclass 25, count 0 2006.210.08:19:18.82#ibcon#flushed, iclass 25, count 0 2006.210.08:19:18.82#ibcon#about to write, iclass 25, count 0 2006.210.08:19:18.82#ibcon#wrote, iclass 25, count 0 2006.210.08:19:18.82#ibcon#about to read 3, iclass 25, count 0 2006.210.08:19:18.84#ibcon#read 3, iclass 25, count 0 2006.210.08:19:18.84#ibcon#about to read 4, iclass 25, count 0 2006.210.08:19:18.84#ibcon#read 4, iclass 25, count 0 2006.210.08:19:18.84#ibcon#about to read 5, iclass 25, count 0 2006.210.08:19:18.84#ibcon#read 5, iclass 25, count 0 2006.210.08:19:18.84#ibcon#about to read 6, iclass 25, count 0 2006.210.08:19:18.84#ibcon#read 6, iclass 25, count 0 2006.210.08:19:18.84#ibcon#end of sib2, iclass 25, count 0 2006.210.08:19:18.84#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:19:18.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:19:18.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:19:18.84#ibcon#*before write, iclass 25, count 0 2006.210.08:19:18.84#ibcon#enter sib2, iclass 25, count 0 2006.210.08:19:18.84#ibcon#flushed, iclass 25, count 0 2006.210.08:19:18.84#ibcon#about to write, iclass 25, count 0 2006.210.08:19:18.84#ibcon#wrote, iclass 25, count 0 2006.210.08:19:18.84#ibcon#about to read 3, iclass 25, count 0 2006.210.08:19:18.88#ibcon#read 3, iclass 25, count 0 2006.210.08:19:18.88#ibcon#about to read 4, iclass 25, count 0 2006.210.08:19:18.88#ibcon#read 4, iclass 25, count 0 2006.210.08:19:18.88#ibcon#about to read 5, iclass 25, count 0 2006.210.08:19:18.88#ibcon#read 5, iclass 25, count 0 2006.210.08:19:18.88#ibcon#about to read 6, iclass 25, count 0 2006.210.08:19:18.88#ibcon#read 6, iclass 25, count 0 2006.210.08:19:18.88#ibcon#end of sib2, iclass 25, count 0 2006.210.08:19:18.88#ibcon#*after write, iclass 25, count 0 2006.210.08:19:18.88#ibcon#*before return 0, iclass 25, count 0 2006.210.08:19:18.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:18.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:18.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:19:18.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:19:18.88$vc4f8/va=5,7 2006.210.08:19:18.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:19:18.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:19:18.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:18.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:18.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:18.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:18.94#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:19:18.94#ibcon#first serial, iclass 27, count 2 2006.210.08:19:18.94#ibcon#enter sib2, iclass 27, count 2 2006.210.08:19:18.94#ibcon#flushed, iclass 27, count 2 2006.210.08:19:18.94#ibcon#about to write, iclass 27, count 2 2006.210.08:19:18.94#ibcon#wrote, iclass 27, count 2 2006.210.08:19:18.94#ibcon#about to read 3, iclass 27, count 2 2006.210.08:19:18.96#ibcon#read 3, iclass 27, count 2 2006.210.08:19:18.96#ibcon#about to read 4, iclass 27, count 2 2006.210.08:19:18.96#ibcon#read 4, iclass 27, count 2 2006.210.08:19:18.96#ibcon#about to read 5, iclass 27, count 2 2006.210.08:19:18.96#ibcon#read 5, iclass 27, count 2 2006.210.08:19:18.96#ibcon#about to read 6, iclass 27, count 2 2006.210.08:19:18.96#ibcon#read 6, iclass 27, count 2 2006.210.08:19:18.96#ibcon#end of sib2, iclass 27, count 2 2006.210.08:19:18.96#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:19:18.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:19:18.96#ibcon#[25=AT05-07\r\n] 2006.210.08:19:18.96#ibcon#*before write, iclass 27, count 2 2006.210.08:19:18.96#ibcon#enter sib2, iclass 27, count 2 2006.210.08:19:18.96#ibcon#flushed, iclass 27, count 2 2006.210.08:19:18.96#ibcon#about to write, iclass 27, count 2 2006.210.08:19:18.96#ibcon#wrote, iclass 27, count 2 2006.210.08:19:18.96#ibcon#about to read 3, iclass 27, count 2 2006.210.08:19:18.99#ibcon#read 3, iclass 27, count 2 2006.210.08:19:18.99#ibcon#about to read 4, iclass 27, count 2 2006.210.08:19:18.99#ibcon#read 4, iclass 27, count 2 2006.210.08:19:18.99#ibcon#about to read 5, iclass 27, count 2 2006.210.08:19:18.99#ibcon#read 5, iclass 27, count 2 2006.210.08:19:18.99#ibcon#about to read 6, iclass 27, count 2 2006.210.08:19:18.99#ibcon#read 6, iclass 27, count 2 2006.210.08:19:18.99#ibcon#end of sib2, iclass 27, count 2 2006.210.08:19:18.99#ibcon#*after write, iclass 27, count 2 2006.210.08:19:18.99#ibcon#*before return 0, iclass 27, count 2 2006.210.08:19:18.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:18.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:18.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:19:18.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:18.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:19.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:19.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:19.11#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:19:19.11#ibcon#first serial, iclass 27, count 0 2006.210.08:19:19.11#ibcon#enter sib2, iclass 27, count 0 2006.210.08:19:19.11#ibcon#flushed, iclass 27, count 0 2006.210.08:19:19.11#ibcon#about to write, iclass 27, count 0 2006.210.08:19:19.11#ibcon#wrote, iclass 27, count 0 2006.210.08:19:19.11#ibcon#about to read 3, iclass 27, count 0 2006.210.08:19:19.13#ibcon#read 3, iclass 27, count 0 2006.210.08:19:19.13#ibcon#about to read 4, iclass 27, count 0 2006.210.08:19:19.13#ibcon#read 4, iclass 27, count 0 2006.210.08:19:19.13#ibcon#about to read 5, iclass 27, count 0 2006.210.08:19:19.13#ibcon#read 5, iclass 27, count 0 2006.210.08:19:19.13#ibcon#about to read 6, iclass 27, count 0 2006.210.08:19:19.13#ibcon#read 6, iclass 27, count 0 2006.210.08:19:19.13#ibcon#end of sib2, iclass 27, count 0 2006.210.08:19:19.13#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:19:19.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:19:19.13#ibcon#[25=USB\r\n] 2006.210.08:19:19.13#ibcon#*before write, iclass 27, count 0 2006.210.08:19:19.13#ibcon#enter sib2, iclass 27, count 0 2006.210.08:19:19.13#ibcon#flushed, iclass 27, count 0 2006.210.08:19:19.13#ibcon#about to write, iclass 27, count 0 2006.210.08:19:19.13#ibcon#wrote, iclass 27, count 0 2006.210.08:19:19.13#ibcon#about to read 3, iclass 27, count 0 2006.210.08:19:19.16#ibcon#read 3, iclass 27, count 0 2006.210.08:19:19.16#ibcon#about to read 4, iclass 27, count 0 2006.210.08:19:19.16#ibcon#read 4, iclass 27, count 0 2006.210.08:19:19.16#ibcon#about to read 5, iclass 27, count 0 2006.210.08:19:19.16#ibcon#read 5, iclass 27, count 0 2006.210.08:19:19.16#ibcon#about to read 6, iclass 27, count 0 2006.210.08:19:19.16#ibcon#read 6, iclass 27, count 0 2006.210.08:19:19.16#ibcon#end of sib2, iclass 27, count 0 2006.210.08:19:19.16#ibcon#*after write, iclass 27, count 0 2006.210.08:19:19.16#ibcon#*before return 0, iclass 27, count 0 2006.210.08:19:19.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:19.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:19.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:19:19.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:19:19.16$vc4f8/valo=6,772.99 2006.210.08:19:19.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:19:19.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:19:19.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:19.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:19.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:19.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:19.16#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:19:19.16#ibcon#first serial, iclass 29, count 0 2006.210.08:19:19.16#ibcon#enter sib2, iclass 29, count 0 2006.210.08:19:19.16#ibcon#flushed, iclass 29, count 0 2006.210.08:19:19.16#ibcon#about to write, iclass 29, count 0 2006.210.08:19:19.16#ibcon#wrote, iclass 29, count 0 2006.210.08:19:19.16#ibcon#about to read 3, iclass 29, count 0 2006.210.08:19:19.18#ibcon#read 3, iclass 29, count 0 2006.210.08:19:19.18#ibcon#about to read 4, iclass 29, count 0 2006.210.08:19:19.18#ibcon#read 4, iclass 29, count 0 2006.210.08:19:19.18#ibcon#about to read 5, iclass 29, count 0 2006.210.08:19:19.18#ibcon#read 5, iclass 29, count 0 2006.210.08:19:19.18#ibcon#about to read 6, iclass 29, count 0 2006.210.08:19:19.18#ibcon#read 6, iclass 29, count 0 2006.210.08:19:19.18#ibcon#end of sib2, iclass 29, count 0 2006.210.08:19:19.18#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:19:19.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:19:19.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:19:19.18#ibcon#*before write, iclass 29, count 0 2006.210.08:19:19.18#ibcon#enter sib2, iclass 29, count 0 2006.210.08:19:19.18#ibcon#flushed, iclass 29, count 0 2006.210.08:19:19.18#ibcon#about to write, iclass 29, count 0 2006.210.08:19:19.18#ibcon#wrote, iclass 29, count 0 2006.210.08:19:19.18#ibcon#about to read 3, iclass 29, count 0 2006.210.08:19:19.22#ibcon#read 3, iclass 29, count 0 2006.210.08:19:19.22#ibcon#about to read 4, iclass 29, count 0 2006.210.08:19:19.22#ibcon#read 4, iclass 29, count 0 2006.210.08:19:19.22#ibcon#about to read 5, iclass 29, count 0 2006.210.08:19:19.22#ibcon#read 5, iclass 29, count 0 2006.210.08:19:19.22#ibcon#about to read 6, iclass 29, count 0 2006.210.08:19:19.22#ibcon#read 6, iclass 29, count 0 2006.210.08:19:19.22#ibcon#end of sib2, iclass 29, count 0 2006.210.08:19:19.22#ibcon#*after write, iclass 29, count 0 2006.210.08:19:19.22#ibcon#*before return 0, iclass 29, count 0 2006.210.08:19:19.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:19.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:19.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:19:19.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:19:19.22$vc4f8/va=6,6 2006.210.08:19:19.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.08:19:19.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.08:19:19.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:19.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:19.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:19.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:19.28#ibcon#enter wrdev, iclass 31, count 2 2006.210.08:19:19.28#ibcon#first serial, iclass 31, count 2 2006.210.08:19:19.28#ibcon#enter sib2, iclass 31, count 2 2006.210.08:19:19.28#ibcon#flushed, iclass 31, count 2 2006.210.08:19:19.28#ibcon#about to write, iclass 31, count 2 2006.210.08:19:19.28#ibcon#wrote, iclass 31, count 2 2006.210.08:19:19.28#ibcon#about to read 3, iclass 31, count 2 2006.210.08:19:19.30#ibcon#read 3, iclass 31, count 2 2006.210.08:19:19.30#ibcon#about to read 4, iclass 31, count 2 2006.210.08:19:19.30#ibcon#read 4, iclass 31, count 2 2006.210.08:19:19.30#ibcon#about to read 5, iclass 31, count 2 2006.210.08:19:19.30#ibcon#read 5, iclass 31, count 2 2006.210.08:19:19.30#ibcon#about to read 6, iclass 31, count 2 2006.210.08:19:19.30#ibcon#read 6, iclass 31, count 2 2006.210.08:19:19.30#ibcon#end of sib2, iclass 31, count 2 2006.210.08:19:19.30#ibcon#*mode == 0, iclass 31, count 2 2006.210.08:19:19.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.08:19:19.30#ibcon#[25=AT06-06\r\n] 2006.210.08:19:19.30#ibcon#*before write, iclass 31, count 2 2006.210.08:19:19.30#ibcon#enter sib2, iclass 31, count 2 2006.210.08:19:19.30#ibcon#flushed, iclass 31, count 2 2006.210.08:19:19.30#ibcon#about to write, iclass 31, count 2 2006.210.08:19:19.30#ibcon#wrote, iclass 31, count 2 2006.210.08:19:19.30#ibcon#about to read 3, iclass 31, count 2 2006.210.08:19:19.33#ibcon#read 3, iclass 31, count 2 2006.210.08:19:19.33#ibcon#about to read 4, iclass 31, count 2 2006.210.08:19:19.33#ibcon#read 4, iclass 31, count 2 2006.210.08:19:19.33#ibcon#about to read 5, iclass 31, count 2 2006.210.08:19:19.33#ibcon#read 5, iclass 31, count 2 2006.210.08:19:19.33#ibcon#about to read 6, iclass 31, count 2 2006.210.08:19:19.33#ibcon#read 6, iclass 31, count 2 2006.210.08:19:19.33#ibcon#end of sib2, iclass 31, count 2 2006.210.08:19:19.33#ibcon#*after write, iclass 31, count 2 2006.210.08:19:19.33#ibcon#*before return 0, iclass 31, count 2 2006.210.08:19:19.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:19.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:19.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.08:19:19.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:19.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:19.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:19.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:19.45#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:19:19.45#ibcon#first serial, iclass 31, count 0 2006.210.08:19:19.45#ibcon#enter sib2, iclass 31, count 0 2006.210.08:19:19.45#ibcon#flushed, iclass 31, count 0 2006.210.08:19:19.45#ibcon#about to write, iclass 31, count 0 2006.210.08:19:19.45#ibcon#wrote, iclass 31, count 0 2006.210.08:19:19.45#ibcon#about to read 3, iclass 31, count 0 2006.210.08:19:19.47#ibcon#read 3, iclass 31, count 0 2006.210.08:19:19.47#ibcon#about to read 4, iclass 31, count 0 2006.210.08:19:19.47#ibcon#read 4, iclass 31, count 0 2006.210.08:19:19.47#ibcon#about to read 5, iclass 31, count 0 2006.210.08:19:19.47#ibcon#read 5, iclass 31, count 0 2006.210.08:19:19.47#ibcon#about to read 6, iclass 31, count 0 2006.210.08:19:19.47#ibcon#read 6, iclass 31, count 0 2006.210.08:19:19.47#ibcon#end of sib2, iclass 31, count 0 2006.210.08:19:19.47#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:19:19.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:19:19.47#ibcon#[25=USB\r\n] 2006.210.08:19:19.47#ibcon#*before write, iclass 31, count 0 2006.210.08:19:19.47#ibcon#enter sib2, iclass 31, count 0 2006.210.08:19:19.47#ibcon#flushed, iclass 31, count 0 2006.210.08:19:19.47#ibcon#about to write, iclass 31, count 0 2006.210.08:19:19.47#ibcon#wrote, iclass 31, count 0 2006.210.08:19:19.47#ibcon#about to read 3, iclass 31, count 0 2006.210.08:19:19.50#ibcon#read 3, iclass 31, count 0 2006.210.08:19:19.50#ibcon#about to read 4, iclass 31, count 0 2006.210.08:19:19.50#ibcon#read 4, iclass 31, count 0 2006.210.08:19:19.50#ibcon#about to read 5, iclass 31, count 0 2006.210.08:19:19.50#ibcon#read 5, iclass 31, count 0 2006.210.08:19:19.50#ibcon#about to read 6, iclass 31, count 0 2006.210.08:19:19.50#ibcon#read 6, iclass 31, count 0 2006.210.08:19:19.50#ibcon#end of sib2, iclass 31, count 0 2006.210.08:19:19.50#ibcon#*after write, iclass 31, count 0 2006.210.08:19:19.50#ibcon#*before return 0, iclass 31, count 0 2006.210.08:19:19.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:19.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:19.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:19:19.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:19:19.50$vc4f8/valo=7,832.99 2006.210.08:19:19.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:19:19.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:19:19.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:19.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:19.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:19.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:19.50#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:19:19.50#ibcon#first serial, iclass 33, count 0 2006.210.08:19:19.50#ibcon#enter sib2, iclass 33, count 0 2006.210.08:19:19.50#ibcon#flushed, iclass 33, count 0 2006.210.08:19:19.50#ibcon#about to write, iclass 33, count 0 2006.210.08:19:19.50#ibcon#wrote, iclass 33, count 0 2006.210.08:19:19.50#ibcon#about to read 3, iclass 33, count 0 2006.210.08:19:19.52#ibcon#read 3, iclass 33, count 0 2006.210.08:19:19.52#ibcon#about to read 4, iclass 33, count 0 2006.210.08:19:19.52#ibcon#read 4, iclass 33, count 0 2006.210.08:19:19.52#ibcon#about to read 5, iclass 33, count 0 2006.210.08:19:19.52#ibcon#read 5, iclass 33, count 0 2006.210.08:19:19.52#ibcon#about to read 6, iclass 33, count 0 2006.210.08:19:19.52#ibcon#read 6, iclass 33, count 0 2006.210.08:19:19.52#ibcon#end of sib2, iclass 33, count 0 2006.210.08:19:19.52#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:19:19.52#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:19:19.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:19:19.52#ibcon#*before write, iclass 33, count 0 2006.210.08:19:19.52#ibcon#enter sib2, iclass 33, count 0 2006.210.08:19:19.52#ibcon#flushed, iclass 33, count 0 2006.210.08:19:19.52#ibcon#about to write, iclass 33, count 0 2006.210.08:19:19.52#ibcon#wrote, iclass 33, count 0 2006.210.08:19:19.52#ibcon#about to read 3, iclass 33, count 0 2006.210.08:19:19.56#ibcon#read 3, iclass 33, count 0 2006.210.08:19:19.56#ibcon#about to read 4, iclass 33, count 0 2006.210.08:19:19.56#ibcon#read 4, iclass 33, count 0 2006.210.08:19:19.56#ibcon#about to read 5, iclass 33, count 0 2006.210.08:19:19.56#ibcon#read 5, iclass 33, count 0 2006.210.08:19:19.56#ibcon#about to read 6, iclass 33, count 0 2006.210.08:19:19.56#ibcon#read 6, iclass 33, count 0 2006.210.08:19:19.56#ibcon#end of sib2, iclass 33, count 0 2006.210.08:19:19.56#ibcon#*after write, iclass 33, count 0 2006.210.08:19:19.56#ibcon#*before return 0, iclass 33, count 0 2006.210.08:19:19.56#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:19.56#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:19.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:19:19.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:19:19.56$vc4f8/va=7,6 2006.210.08:19:19.56#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.210.08:19:19.56#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.210.08:19:19.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:19.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:19:19.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:19:19.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:19:19.62#ibcon#enter wrdev, iclass 35, count 2 2006.210.08:19:19.62#ibcon#first serial, iclass 35, count 2 2006.210.08:19:19.62#ibcon#enter sib2, iclass 35, count 2 2006.210.08:19:19.62#ibcon#flushed, iclass 35, count 2 2006.210.08:19:19.62#ibcon#about to write, iclass 35, count 2 2006.210.08:19:19.62#ibcon#wrote, iclass 35, count 2 2006.210.08:19:19.62#ibcon#about to read 3, iclass 35, count 2 2006.210.08:19:19.64#ibcon#read 3, iclass 35, count 2 2006.210.08:19:19.64#ibcon#about to read 4, iclass 35, count 2 2006.210.08:19:19.64#ibcon#read 4, iclass 35, count 2 2006.210.08:19:19.64#ibcon#about to read 5, iclass 35, count 2 2006.210.08:19:19.64#ibcon#read 5, iclass 35, count 2 2006.210.08:19:19.64#ibcon#about to read 6, iclass 35, count 2 2006.210.08:19:19.64#ibcon#read 6, iclass 35, count 2 2006.210.08:19:19.64#ibcon#end of sib2, iclass 35, count 2 2006.210.08:19:19.64#ibcon#*mode == 0, iclass 35, count 2 2006.210.08:19:19.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.210.08:19:19.64#ibcon#[25=AT07-06\r\n] 2006.210.08:19:19.64#ibcon#*before write, iclass 35, count 2 2006.210.08:19:19.64#ibcon#enter sib2, iclass 35, count 2 2006.210.08:19:19.64#ibcon#flushed, iclass 35, count 2 2006.210.08:19:19.64#ibcon#about to write, iclass 35, count 2 2006.210.08:19:19.64#ibcon#wrote, iclass 35, count 2 2006.210.08:19:19.64#ibcon#about to read 3, iclass 35, count 2 2006.210.08:19:19.67#ibcon#read 3, iclass 35, count 2 2006.210.08:19:19.67#ibcon#about to read 4, iclass 35, count 2 2006.210.08:19:19.67#ibcon#read 4, iclass 35, count 2 2006.210.08:19:19.67#ibcon#about to read 5, iclass 35, count 2 2006.210.08:19:19.67#ibcon#read 5, iclass 35, count 2 2006.210.08:19:19.67#ibcon#about to read 6, iclass 35, count 2 2006.210.08:19:19.67#ibcon#read 6, iclass 35, count 2 2006.210.08:19:19.67#ibcon#end of sib2, iclass 35, count 2 2006.210.08:19:19.67#ibcon#*after write, iclass 35, count 2 2006.210.08:19:19.67#ibcon#*before return 0, iclass 35, count 2 2006.210.08:19:19.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:19:19.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.210.08:19:19.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.210.08:19:19.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:19.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:19:19.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:19:19.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:19:19.79#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:19:19.79#ibcon#first serial, iclass 35, count 0 2006.210.08:19:19.79#ibcon#enter sib2, iclass 35, count 0 2006.210.08:19:19.79#ibcon#flushed, iclass 35, count 0 2006.210.08:19:19.79#ibcon#about to write, iclass 35, count 0 2006.210.08:19:19.79#ibcon#wrote, iclass 35, count 0 2006.210.08:19:19.79#ibcon#about to read 3, iclass 35, count 0 2006.210.08:19:19.81#ibcon#read 3, iclass 35, count 0 2006.210.08:19:19.81#ibcon#about to read 4, iclass 35, count 0 2006.210.08:19:19.81#ibcon#read 4, iclass 35, count 0 2006.210.08:19:19.81#ibcon#about to read 5, iclass 35, count 0 2006.210.08:19:19.81#ibcon#read 5, iclass 35, count 0 2006.210.08:19:19.81#ibcon#about to read 6, iclass 35, count 0 2006.210.08:19:19.81#ibcon#read 6, iclass 35, count 0 2006.210.08:19:19.81#ibcon#end of sib2, iclass 35, count 0 2006.210.08:19:19.81#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:19:19.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:19:19.81#ibcon#[25=USB\r\n] 2006.210.08:19:19.81#ibcon#*before write, iclass 35, count 0 2006.210.08:19:19.81#ibcon#enter sib2, iclass 35, count 0 2006.210.08:19:19.81#ibcon#flushed, iclass 35, count 0 2006.210.08:19:19.81#ibcon#about to write, iclass 35, count 0 2006.210.08:19:19.81#ibcon#wrote, iclass 35, count 0 2006.210.08:19:19.81#ibcon#about to read 3, iclass 35, count 0 2006.210.08:19:19.84#ibcon#read 3, iclass 35, count 0 2006.210.08:19:19.84#ibcon#about to read 4, iclass 35, count 0 2006.210.08:19:19.84#ibcon#read 4, iclass 35, count 0 2006.210.08:19:19.84#ibcon#about to read 5, iclass 35, count 0 2006.210.08:19:19.84#ibcon#read 5, iclass 35, count 0 2006.210.08:19:19.84#ibcon#about to read 6, iclass 35, count 0 2006.210.08:19:19.84#ibcon#read 6, iclass 35, count 0 2006.210.08:19:19.84#ibcon#end of sib2, iclass 35, count 0 2006.210.08:19:19.84#ibcon#*after write, iclass 35, count 0 2006.210.08:19:19.84#ibcon#*before return 0, iclass 35, count 0 2006.210.08:19:19.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:19:19.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.210.08:19:19.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:19:19.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:19:19.84$vc4f8/valo=8,852.99 2006.210.08:19:19.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.210.08:19:19.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.210.08:19:19.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:19.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:19:19.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:19:19.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:19:19.84#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:19:19.84#ibcon#first serial, iclass 37, count 0 2006.210.08:19:19.84#ibcon#enter sib2, iclass 37, count 0 2006.210.08:19:19.84#ibcon#flushed, iclass 37, count 0 2006.210.08:19:19.84#ibcon#about to write, iclass 37, count 0 2006.210.08:19:19.84#ibcon#wrote, iclass 37, count 0 2006.210.08:19:19.84#ibcon#about to read 3, iclass 37, count 0 2006.210.08:19:19.86#ibcon#read 3, iclass 37, count 0 2006.210.08:19:19.86#ibcon#about to read 4, iclass 37, count 0 2006.210.08:19:19.86#ibcon#read 4, iclass 37, count 0 2006.210.08:19:19.86#ibcon#about to read 5, iclass 37, count 0 2006.210.08:19:19.86#ibcon#read 5, iclass 37, count 0 2006.210.08:19:19.86#ibcon#about to read 6, iclass 37, count 0 2006.210.08:19:19.86#ibcon#read 6, iclass 37, count 0 2006.210.08:19:19.86#ibcon#end of sib2, iclass 37, count 0 2006.210.08:19:19.86#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:19:19.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:19:19.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:19:19.86#ibcon#*before write, iclass 37, count 0 2006.210.08:19:19.86#ibcon#enter sib2, iclass 37, count 0 2006.210.08:19:19.86#ibcon#flushed, iclass 37, count 0 2006.210.08:19:19.86#ibcon#about to write, iclass 37, count 0 2006.210.08:19:19.86#ibcon#wrote, iclass 37, count 0 2006.210.08:19:19.86#ibcon#about to read 3, iclass 37, count 0 2006.210.08:19:19.90#ibcon#read 3, iclass 37, count 0 2006.210.08:19:19.90#ibcon#about to read 4, iclass 37, count 0 2006.210.08:19:19.90#ibcon#read 4, iclass 37, count 0 2006.210.08:19:19.90#ibcon#about to read 5, iclass 37, count 0 2006.210.08:19:19.90#ibcon#read 5, iclass 37, count 0 2006.210.08:19:19.90#ibcon#about to read 6, iclass 37, count 0 2006.210.08:19:19.90#ibcon#read 6, iclass 37, count 0 2006.210.08:19:19.90#ibcon#end of sib2, iclass 37, count 0 2006.210.08:19:19.90#ibcon#*after write, iclass 37, count 0 2006.210.08:19:19.90#ibcon#*before return 0, iclass 37, count 0 2006.210.08:19:19.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:19:19.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.210.08:19:19.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:19:19.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:19:19.90$vc4f8/va=8,7 2006.210.08:19:19.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.210.08:19:19.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.210.08:19:19.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:19.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:19:19.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:19:19.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:19:19.96#ibcon#enter wrdev, iclass 39, count 2 2006.210.08:19:19.96#ibcon#first serial, iclass 39, count 2 2006.210.08:19:19.96#ibcon#enter sib2, iclass 39, count 2 2006.210.08:19:19.96#ibcon#flushed, iclass 39, count 2 2006.210.08:19:19.96#ibcon#about to write, iclass 39, count 2 2006.210.08:19:19.96#ibcon#wrote, iclass 39, count 2 2006.210.08:19:19.96#ibcon#about to read 3, iclass 39, count 2 2006.210.08:19:19.98#ibcon#read 3, iclass 39, count 2 2006.210.08:19:19.98#ibcon#about to read 4, iclass 39, count 2 2006.210.08:19:19.98#ibcon#read 4, iclass 39, count 2 2006.210.08:19:19.98#ibcon#about to read 5, iclass 39, count 2 2006.210.08:19:19.98#ibcon#read 5, iclass 39, count 2 2006.210.08:19:19.98#ibcon#about to read 6, iclass 39, count 2 2006.210.08:19:19.98#ibcon#read 6, iclass 39, count 2 2006.210.08:19:19.98#ibcon#end of sib2, iclass 39, count 2 2006.210.08:19:19.98#ibcon#*mode == 0, iclass 39, count 2 2006.210.08:19:19.98#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.210.08:19:19.98#ibcon#[25=AT08-07\r\n] 2006.210.08:19:19.98#ibcon#*before write, iclass 39, count 2 2006.210.08:19:19.98#ibcon#enter sib2, iclass 39, count 2 2006.210.08:19:19.98#ibcon#flushed, iclass 39, count 2 2006.210.08:19:19.98#ibcon#about to write, iclass 39, count 2 2006.210.08:19:19.98#ibcon#wrote, iclass 39, count 2 2006.210.08:19:19.98#ibcon#about to read 3, iclass 39, count 2 2006.210.08:19:20.01#ibcon#read 3, iclass 39, count 2 2006.210.08:19:20.01#ibcon#about to read 4, iclass 39, count 2 2006.210.08:19:20.01#ibcon#read 4, iclass 39, count 2 2006.210.08:19:20.01#ibcon#about to read 5, iclass 39, count 2 2006.210.08:19:20.01#ibcon#read 5, iclass 39, count 2 2006.210.08:19:20.01#ibcon#about to read 6, iclass 39, count 2 2006.210.08:19:20.01#ibcon#read 6, iclass 39, count 2 2006.210.08:19:20.01#ibcon#end of sib2, iclass 39, count 2 2006.210.08:19:20.01#ibcon#*after write, iclass 39, count 2 2006.210.08:19:20.01#ibcon#*before return 0, iclass 39, count 2 2006.210.08:19:20.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:19:20.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.210.08:19:20.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.210.08:19:20.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:20.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:19:20.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:19:20.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:19:20.13#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:19:20.13#ibcon#first serial, iclass 39, count 0 2006.210.08:19:20.13#ibcon#enter sib2, iclass 39, count 0 2006.210.08:19:20.13#ibcon#flushed, iclass 39, count 0 2006.210.08:19:20.13#ibcon#about to write, iclass 39, count 0 2006.210.08:19:20.13#ibcon#wrote, iclass 39, count 0 2006.210.08:19:20.13#ibcon#about to read 3, iclass 39, count 0 2006.210.08:19:20.15#ibcon#read 3, iclass 39, count 0 2006.210.08:19:20.15#ibcon#about to read 4, iclass 39, count 0 2006.210.08:19:20.15#ibcon#read 4, iclass 39, count 0 2006.210.08:19:20.15#ibcon#about to read 5, iclass 39, count 0 2006.210.08:19:20.15#ibcon#read 5, iclass 39, count 0 2006.210.08:19:20.15#ibcon#about to read 6, iclass 39, count 0 2006.210.08:19:20.15#ibcon#read 6, iclass 39, count 0 2006.210.08:19:20.15#ibcon#end of sib2, iclass 39, count 0 2006.210.08:19:20.15#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:19:20.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:19:20.15#ibcon#[25=USB\r\n] 2006.210.08:19:20.15#ibcon#*before write, iclass 39, count 0 2006.210.08:19:20.15#ibcon#enter sib2, iclass 39, count 0 2006.210.08:19:20.15#ibcon#flushed, iclass 39, count 0 2006.210.08:19:20.15#ibcon#about to write, iclass 39, count 0 2006.210.08:19:20.15#ibcon#wrote, iclass 39, count 0 2006.210.08:19:20.15#ibcon#about to read 3, iclass 39, count 0 2006.210.08:19:20.18#ibcon#read 3, iclass 39, count 0 2006.210.08:19:20.18#ibcon#about to read 4, iclass 39, count 0 2006.210.08:19:20.18#ibcon#read 4, iclass 39, count 0 2006.210.08:19:20.18#ibcon#about to read 5, iclass 39, count 0 2006.210.08:19:20.18#ibcon#read 5, iclass 39, count 0 2006.210.08:19:20.18#ibcon#about to read 6, iclass 39, count 0 2006.210.08:19:20.18#ibcon#read 6, iclass 39, count 0 2006.210.08:19:20.18#ibcon#end of sib2, iclass 39, count 0 2006.210.08:19:20.18#ibcon#*after write, iclass 39, count 0 2006.210.08:19:20.18#ibcon#*before return 0, iclass 39, count 0 2006.210.08:19:20.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:19:20.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.210.08:19:20.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:19:20.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:19:20.18$vc4f8/vblo=1,632.99 2006.210.08:19:20.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.210.08:19:20.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.210.08:19:20.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:20.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:19:20.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:19:20.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:19:20.18#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:19:20.18#ibcon#first serial, iclass 3, count 0 2006.210.08:19:20.18#ibcon#enter sib2, iclass 3, count 0 2006.210.08:19:20.18#ibcon#flushed, iclass 3, count 0 2006.210.08:19:20.18#ibcon#about to write, iclass 3, count 0 2006.210.08:19:20.18#ibcon#wrote, iclass 3, count 0 2006.210.08:19:20.18#ibcon#about to read 3, iclass 3, count 0 2006.210.08:19:20.20#ibcon#read 3, iclass 3, count 0 2006.210.08:19:20.20#ibcon#about to read 4, iclass 3, count 0 2006.210.08:19:20.20#ibcon#read 4, iclass 3, count 0 2006.210.08:19:20.20#ibcon#about to read 5, iclass 3, count 0 2006.210.08:19:20.20#ibcon#read 5, iclass 3, count 0 2006.210.08:19:20.20#ibcon#about to read 6, iclass 3, count 0 2006.210.08:19:20.20#ibcon#read 6, iclass 3, count 0 2006.210.08:19:20.20#ibcon#end of sib2, iclass 3, count 0 2006.210.08:19:20.20#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:19:20.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:19:20.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:19:20.20#ibcon#*before write, iclass 3, count 0 2006.210.08:19:20.20#ibcon#enter sib2, iclass 3, count 0 2006.210.08:19:20.20#ibcon#flushed, iclass 3, count 0 2006.210.08:19:20.20#ibcon#about to write, iclass 3, count 0 2006.210.08:19:20.20#ibcon#wrote, iclass 3, count 0 2006.210.08:19:20.20#ibcon#about to read 3, iclass 3, count 0 2006.210.08:19:20.24#ibcon#read 3, iclass 3, count 0 2006.210.08:19:20.24#ibcon#about to read 4, iclass 3, count 0 2006.210.08:19:20.24#ibcon#read 4, iclass 3, count 0 2006.210.08:19:20.24#ibcon#about to read 5, iclass 3, count 0 2006.210.08:19:20.24#ibcon#read 5, iclass 3, count 0 2006.210.08:19:20.24#ibcon#about to read 6, iclass 3, count 0 2006.210.08:19:20.24#ibcon#read 6, iclass 3, count 0 2006.210.08:19:20.24#ibcon#end of sib2, iclass 3, count 0 2006.210.08:19:20.24#ibcon#*after write, iclass 3, count 0 2006.210.08:19:20.24#ibcon#*before return 0, iclass 3, count 0 2006.210.08:19:20.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:19:20.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.210.08:19:20.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:19:20.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:19:20.24$vc4f8/vb=1,4 2006.210.08:19:20.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.210.08:19:20.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.210.08:19:20.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:20.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:19:20.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:19:20.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:19:20.24#ibcon#enter wrdev, iclass 5, count 2 2006.210.08:19:20.24#ibcon#first serial, iclass 5, count 2 2006.210.08:19:20.24#ibcon#enter sib2, iclass 5, count 2 2006.210.08:19:20.24#ibcon#flushed, iclass 5, count 2 2006.210.08:19:20.24#ibcon#about to write, iclass 5, count 2 2006.210.08:19:20.24#ibcon#wrote, iclass 5, count 2 2006.210.08:19:20.24#ibcon#about to read 3, iclass 5, count 2 2006.210.08:19:20.26#ibcon#read 3, iclass 5, count 2 2006.210.08:19:20.26#ibcon#about to read 4, iclass 5, count 2 2006.210.08:19:20.26#ibcon#read 4, iclass 5, count 2 2006.210.08:19:20.26#ibcon#about to read 5, iclass 5, count 2 2006.210.08:19:20.26#ibcon#read 5, iclass 5, count 2 2006.210.08:19:20.26#ibcon#about to read 6, iclass 5, count 2 2006.210.08:19:20.26#ibcon#read 6, iclass 5, count 2 2006.210.08:19:20.26#ibcon#end of sib2, iclass 5, count 2 2006.210.08:19:20.26#ibcon#*mode == 0, iclass 5, count 2 2006.210.08:19:20.26#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.210.08:19:20.26#ibcon#[27=AT01-04\r\n] 2006.210.08:19:20.26#ibcon#*before write, iclass 5, count 2 2006.210.08:19:20.26#ibcon#enter sib2, iclass 5, count 2 2006.210.08:19:20.26#ibcon#flushed, iclass 5, count 2 2006.210.08:19:20.26#ibcon#about to write, iclass 5, count 2 2006.210.08:19:20.26#ibcon#wrote, iclass 5, count 2 2006.210.08:19:20.26#ibcon#about to read 3, iclass 5, count 2 2006.210.08:19:20.29#ibcon#read 3, iclass 5, count 2 2006.210.08:19:20.29#ibcon#about to read 4, iclass 5, count 2 2006.210.08:19:20.29#ibcon#read 4, iclass 5, count 2 2006.210.08:19:20.29#ibcon#about to read 5, iclass 5, count 2 2006.210.08:19:20.29#ibcon#read 5, iclass 5, count 2 2006.210.08:19:20.29#ibcon#about to read 6, iclass 5, count 2 2006.210.08:19:20.29#ibcon#read 6, iclass 5, count 2 2006.210.08:19:20.29#ibcon#end of sib2, iclass 5, count 2 2006.210.08:19:20.29#ibcon#*after write, iclass 5, count 2 2006.210.08:19:20.29#ibcon#*before return 0, iclass 5, count 2 2006.210.08:19:20.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:19:20.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.210.08:19:20.29#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.210.08:19:20.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:20.29#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:19:20.41#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:19:20.41#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:19:20.41#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:19:20.41#ibcon#first serial, iclass 5, count 0 2006.210.08:19:20.41#ibcon#enter sib2, iclass 5, count 0 2006.210.08:19:20.41#ibcon#flushed, iclass 5, count 0 2006.210.08:19:20.41#ibcon#about to write, iclass 5, count 0 2006.210.08:19:20.41#ibcon#wrote, iclass 5, count 0 2006.210.08:19:20.41#ibcon#about to read 3, iclass 5, count 0 2006.210.08:19:20.43#ibcon#read 3, iclass 5, count 0 2006.210.08:19:20.43#ibcon#about to read 4, iclass 5, count 0 2006.210.08:19:20.43#ibcon#read 4, iclass 5, count 0 2006.210.08:19:20.43#ibcon#about to read 5, iclass 5, count 0 2006.210.08:19:20.43#ibcon#read 5, iclass 5, count 0 2006.210.08:19:20.43#ibcon#about to read 6, iclass 5, count 0 2006.210.08:19:20.43#ibcon#read 6, iclass 5, count 0 2006.210.08:19:20.43#ibcon#end of sib2, iclass 5, count 0 2006.210.08:19:20.43#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:19:20.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:19:20.43#ibcon#[27=USB\r\n] 2006.210.08:19:20.43#ibcon#*before write, iclass 5, count 0 2006.210.08:19:20.43#ibcon#enter sib2, iclass 5, count 0 2006.210.08:19:20.43#ibcon#flushed, iclass 5, count 0 2006.210.08:19:20.43#ibcon#about to write, iclass 5, count 0 2006.210.08:19:20.43#ibcon#wrote, iclass 5, count 0 2006.210.08:19:20.43#ibcon#about to read 3, iclass 5, count 0 2006.210.08:19:20.46#ibcon#read 3, iclass 5, count 0 2006.210.08:19:20.46#ibcon#about to read 4, iclass 5, count 0 2006.210.08:19:20.46#ibcon#read 4, iclass 5, count 0 2006.210.08:19:20.46#ibcon#about to read 5, iclass 5, count 0 2006.210.08:19:20.46#ibcon#read 5, iclass 5, count 0 2006.210.08:19:20.46#ibcon#about to read 6, iclass 5, count 0 2006.210.08:19:20.46#ibcon#read 6, iclass 5, count 0 2006.210.08:19:20.46#ibcon#end of sib2, iclass 5, count 0 2006.210.08:19:20.46#ibcon#*after write, iclass 5, count 0 2006.210.08:19:20.46#ibcon#*before return 0, iclass 5, count 0 2006.210.08:19:20.46#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:19:20.46#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.210.08:19:20.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:19:20.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:19:20.46$vc4f8/vblo=2,640.99 2006.210.08:19:20.46#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.210.08:19:20.46#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.210.08:19:20.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:20.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:20.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:20.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:20.46#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:19:20.46#ibcon#first serial, iclass 7, count 0 2006.210.08:19:20.46#ibcon#enter sib2, iclass 7, count 0 2006.210.08:19:20.46#ibcon#flushed, iclass 7, count 0 2006.210.08:19:20.46#ibcon#about to write, iclass 7, count 0 2006.210.08:19:20.46#ibcon#wrote, iclass 7, count 0 2006.210.08:19:20.46#ibcon#about to read 3, iclass 7, count 0 2006.210.08:19:20.48#ibcon#read 3, iclass 7, count 0 2006.210.08:19:20.48#ibcon#about to read 4, iclass 7, count 0 2006.210.08:19:20.48#ibcon#read 4, iclass 7, count 0 2006.210.08:19:20.48#ibcon#about to read 5, iclass 7, count 0 2006.210.08:19:20.48#ibcon#read 5, iclass 7, count 0 2006.210.08:19:20.48#ibcon#about to read 6, iclass 7, count 0 2006.210.08:19:20.48#ibcon#read 6, iclass 7, count 0 2006.210.08:19:20.48#ibcon#end of sib2, iclass 7, count 0 2006.210.08:19:20.48#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:19:20.48#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:19:20.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:19:20.48#ibcon#*before write, iclass 7, count 0 2006.210.08:19:20.48#ibcon#enter sib2, iclass 7, count 0 2006.210.08:19:20.48#ibcon#flushed, iclass 7, count 0 2006.210.08:19:20.48#ibcon#about to write, iclass 7, count 0 2006.210.08:19:20.48#ibcon#wrote, iclass 7, count 0 2006.210.08:19:20.48#ibcon#about to read 3, iclass 7, count 0 2006.210.08:19:20.52#ibcon#read 3, iclass 7, count 0 2006.210.08:19:20.52#ibcon#about to read 4, iclass 7, count 0 2006.210.08:19:20.52#ibcon#read 4, iclass 7, count 0 2006.210.08:19:20.52#ibcon#about to read 5, iclass 7, count 0 2006.210.08:19:20.52#ibcon#read 5, iclass 7, count 0 2006.210.08:19:20.52#ibcon#about to read 6, iclass 7, count 0 2006.210.08:19:20.52#ibcon#read 6, iclass 7, count 0 2006.210.08:19:20.52#ibcon#end of sib2, iclass 7, count 0 2006.210.08:19:20.52#ibcon#*after write, iclass 7, count 0 2006.210.08:19:20.52#ibcon#*before return 0, iclass 7, count 0 2006.210.08:19:20.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:20.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.210.08:19:20.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:19:20.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:19:20.52$vc4f8/vb=2,4 2006.210.08:19:20.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.210.08:19:20.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.210.08:19:20.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:20.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:20.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:20.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:20.58#ibcon#enter wrdev, iclass 11, count 2 2006.210.08:19:20.58#ibcon#first serial, iclass 11, count 2 2006.210.08:19:20.58#ibcon#enter sib2, iclass 11, count 2 2006.210.08:19:20.58#ibcon#flushed, iclass 11, count 2 2006.210.08:19:20.58#ibcon#about to write, iclass 11, count 2 2006.210.08:19:20.58#ibcon#wrote, iclass 11, count 2 2006.210.08:19:20.58#ibcon#about to read 3, iclass 11, count 2 2006.210.08:19:20.60#ibcon#read 3, iclass 11, count 2 2006.210.08:19:20.60#ibcon#about to read 4, iclass 11, count 2 2006.210.08:19:20.60#ibcon#read 4, iclass 11, count 2 2006.210.08:19:20.60#ibcon#about to read 5, iclass 11, count 2 2006.210.08:19:20.60#ibcon#read 5, iclass 11, count 2 2006.210.08:19:20.60#ibcon#about to read 6, iclass 11, count 2 2006.210.08:19:20.60#ibcon#read 6, iclass 11, count 2 2006.210.08:19:20.60#ibcon#end of sib2, iclass 11, count 2 2006.210.08:19:20.60#ibcon#*mode == 0, iclass 11, count 2 2006.210.08:19:20.60#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.210.08:19:20.60#ibcon#[27=AT02-04\r\n] 2006.210.08:19:20.60#ibcon#*before write, iclass 11, count 2 2006.210.08:19:20.60#ibcon#enter sib2, iclass 11, count 2 2006.210.08:19:20.60#ibcon#flushed, iclass 11, count 2 2006.210.08:19:20.60#ibcon#about to write, iclass 11, count 2 2006.210.08:19:20.60#ibcon#wrote, iclass 11, count 2 2006.210.08:19:20.60#ibcon#about to read 3, iclass 11, count 2 2006.210.08:19:20.63#ibcon#read 3, iclass 11, count 2 2006.210.08:19:20.63#ibcon#about to read 4, iclass 11, count 2 2006.210.08:19:20.63#ibcon#read 4, iclass 11, count 2 2006.210.08:19:20.63#ibcon#about to read 5, iclass 11, count 2 2006.210.08:19:20.63#ibcon#read 5, iclass 11, count 2 2006.210.08:19:20.63#ibcon#about to read 6, iclass 11, count 2 2006.210.08:19:20.63#ibcon#read 6, iclass 11, count 2 2006.210.08:19:20.63#ibcon#end of sib2, iclass 11, count 2 2006.210.08:19:20.63#ibcon#*after write, iclass 11, count 2 2006.210.08:19:20.63#ibcon#*before return 0, iclass 11, count 2 2006.210.08:19:20.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:20.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.210.08:19:20.63#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.210.08:19:20.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:20.63#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:20.75#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:20.75#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:20.75#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:19:20.75#ibcon#first serial, iclass 11, count 0 2006.210.08:19:20.75#ibcon#enter sib2, iclass 11, count 0 2006.210.08:19:20.75#ibcon#flushed, iclass 11, count 0 2006.210.08:19:20.75#ibcon#about to write, iclass 11, count 0 2006.210.08:19:20.75#ibcon#wrote, iclass 11, count 0 2006.210.08:19:20.75#ibcon#about to read 3, iclass 11, count 0 2006.210.08:19:20.77#ibcon#read 3, iclass 11, count 0 2006.210.08:19:20.77#ibcon#about to read 4, iclass 11, count 0 2006.210.08:19:20.77#ibcon#read 4, iclass 11, count 0 2006.210.08:19:20.77#ibcon#about to read 5, iclass 11, count 0 2006.210.08:19:20.77#ibcon#read 5, iclass 11, count 0 2006.210.08:19:20.77#ibcon#about to read 6, iclass 11, count 0 2006.210.08:19:20.77#ibcon#read 6, iclass 11, count 0 2006.210.08:19:20.77#ibcon#end of sib2, iclass 11, count 0 2006.210.08:19:20.77#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:19:20.77#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:19:20.77#ibcon#[27=USB\r\n] 2006.210.08:19:20.77#ibcon#*before write, iclass 11, count 0 2006.210.08:19:20.77#ibcon#enter sib2, iclass 11, count 0 2006.210.08:19:20.77#ibcon#flushed, iclass 11, count 0 2006.210.08:19:20.77#ibcon#about to write, iclass 11, count 0 2006.210.08:19:20.77#ibcon#wrote, iclass 11, count 0 2006.210.08:19:20.77#ibcon#about to read 3, iclass 11, count 0 2006.210.08:19:20.80#ibcon#read 3, iclass 11, count 0 2006.210.08:19:20.80#ibcon#about to read 4, iclass 11, count 0 2006.210.08:19:20.80#ibcon#read 4, iclass 11, count 0 2006.210.08:19:20.80#ibcon#about to read 5, iclass 11, count 0 2006.210.08:19:20.80#ibcon#read 5, iclass 11, count 0 2006.210.08:19:20.80#ibcon#about to read 6, iclass 11, count 0 2006.210.08:19:20.80#ibcon#read 6, iclass 11, count 0 2006.210.08:19:20.80#ibcon#end of sib2, iclass 11, count 0 2006.210.08:19:20.80#ibcon#*after write, iclass 11, count 0 2006.210.08:19:20.80#ibcon#*before return 0, iclass 11, count 0 2006.210.08:19:20.80#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:20.80#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.210.08:19:20.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:19:20.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:19:20.80$vc4f8/vblo=3,656.99 2006.210.08:19:20.80#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.210.08:19:20.80#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.210.08:19:20.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:20.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:20.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:20.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:20.80#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:19:20.80#ibcon#first serial, iclass 13, count 0 2006.210.08:19:20.80#ibcon#enter sib2, iclass 13, count 0 2006.210.08:19:20.80#ibcon#flushed, iclass 13, count 0 2006.210.08:19:20.80#ibcon#about to write, iclass 13, count 0 2006.210.08:19:20.80#ibcon#wrote, iclass 13, count 0 2006.210.08:19:20.80#ibcon#about to read 3, iclass 13, count 0 2006.210.08:19:20.82#ibcon#read 3, iclass 13, count 0 2006.210.08:19:20.82#ibcon#about to read 4, iclass 13, count 0 2006.210.08:19:20.82#ibcon#read 4, iclass 13, count 0 2006.210.08:19:20.82#ibcon#about to read 5, iclass 13, count 0 2006.210.08:19:20.82#ibcon#read 5, iclass 13, count 0 2006.210.08:19:20.82#ibcon#about to read 6, iclass 13, count 0 2006.210.08:19:20.82#ibcon#read 6, iclass 13, count 0 2006.210.08:19:20.82#ibcon#end of sib2, iclass 13, count 0 2006.210.08:19:20.82#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:19:20.82#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:19:20.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:19:20.82#ibcon#*before write, iclass 13, count 0 2006.210.08:19:20.82#ibcon#enter sib2, iclass 13, count 0 2006.210.08:19:20.82#ibcon#flushed, iclass 13, count 0 2006.210.08:19:20.82#ibcon#about to write, iclass 13, count 0 2006.210.08:19:20.82#ibcon#wrote, iclass 13, count 0 2006.210.08:19:20.82#ibcon#about to read 3, iclass 13, count 0 2006.210.08:19:20.86#ibcon#read 3, iclass 13, count 0 2006.210.08:19:20.86#ibcon#about to read 4, iclass 13, count 0 2006.210.08:19:20.86#ibcon#read 4, iclass 13, count 0 2006.210.08:19:20.86#ibcon#about to read 5, iclass 13, count 0 2006.210.08:19:20.86#ibcon#read 5, iclass 13, count 0 2006.210.08:19:20.86#ibcon#about to read 6, iclass 13, count 0 2006.210.08:19:20.86#ibcon#read 6, iclass 13, count 0 2006.210.08:19:20.86#ibcon#end of sib2, iclass 13, count 0 2006.210.08:19:20.86#ibcon#*after write, iclass 13, count 0 2006.210.08:19:20.86#ibcon#*before return 0, iclass 13, count 0 2006.210.08:19:20.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:20.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.210.08:19:20.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:19:20.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:19:20.86$vc4f8/vb=3,3 2006.210.08:19:20.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.210.08:19:20.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.210.08:19:20.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:20.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:20.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:20.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:20.92#ibcon#enter wrdev, iclass 15, count 2 2006.210.08:19:20.92#ibcon#first serial, iclass 15, count 2 2006.210.08:19:20.92#ibcon#enter sib2, iclass 15, count 2 2006.210.08:19:20.92#ibcon#flushed, iclass 15, count 2 2006.210.08:19:20.92#ibcon#about to write, iclass 15, count 2 2006.210.08:19:20.92#ibcon#wrote, iclass 15, count 2 2006.210.08:19:20.92#ibcon#about to read 3, iclass 15, count 2 2006.210.08:19:20.93#abcon#<5=/05 3.2 6.4 29.84 821006.4\r\n> 2006.210.08:19:20.94#ibcon#read 3, iclass 15, count 2 2006.210.08:19:20.94#ibcon#about to read 4, iclass 15, count 2 2006.210.08:19:20.94#ibcon#read 4, iclass 15, count 2 2006.210.08:19:20.94#ibcon#about to read 5, iclass 15, count 2 2006.210.08:19:20.94#ibcon#read 5, iclass 15, count 2 2006.210.08:19:20.94#ibcon#about to read 6, iclass 15, count 2 2006.210.08:19:20.94#ibcon#read 6, iclass 15, count 2 2006.210.08:19:20.94#ibcon#end of sib2, iclass 15, count 2 2006.210.08:19:20.94#ibcon#*mode == 0, iclass 15, count 2 2006.210.08:19:20.94#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.210.08:19:20.94#ibcon#[27=AT03-03\r\n] 2006.210.08:19:20.94#ibcon#*before write, iclass 15, count 2 2006.210.08:19:20.94#ibcon#enter sib2, iclass 15, count 2 2006.210.08:19:20.94#ibcon#flushed, iclass 15, count 2 2006.210.08:19:20.94#ibcon#about to write, iclass 15, count 2 2006.210.08:19:20.94#ibcon#wrote, iclass 15, count 2 2006.210.08:19:20.94#ibcon#about to read 3, iclass 15, count 2 2006.210.08:19:20.95#abcon#{5=INTERFACE CLEAR} 2006.210.08:19:20.97#ibcon#read 3, iclass 15, count 2 2006.210.08:19:20.97#ibcon#about to read 4, iclass 15, count 2 2006.210.08:19:20.97#ibcon#read 4, iclass 15, count 2 2006.210.08:19:20.97#ibcon#about to read 5, iclass 15, count 2 2006.210.08:19:20.97#ibcon#read 5, iclass 15, count 2 2006.210.08:19:20.97#ibcon#about to read 6, iclass 15, count 2 2006.210.08:19:20.97#ibcon#read 6, iclass 15, count 2 2006.210.08:19:20.97#ibcon#end of sib2, iclass 15, count 2 2006.210.08:19:20.97#ibcon#*after write, iclass 15, count 2 2006.210.08:19:20.97#ibcon#*before return 0, iclass 15, count 2 2006.210.08:19:20.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:20.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.210.08:19:20.97#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.210.08:19:20.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:20.97#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:21.01#abcon#[5=S1D000X0/0*\r\n] 2006.210.08:19:21.09#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:21.09#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:21.09#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:19:21.09#ibcon#first serial, iclass 15, count 0 2006.210.08:19:21.09#ibcon#enter sib2, iclass 15, count 0 2006.210.08:19:21.09#ibcon#flushed, iclass 15, count 0 2006.210.08:19:21.09#ibcon#about to write, iclass 15, count 0 2006.210.08:19:21.09#ibcon#wrote, iclass 15, count 0 2006.210.08:19:21.09#ibcon#about to read 3, iclass 15, count 0 2006.210.08:19:21.11#ibcon#read 3, iclass 15, count 0 2006.210.08:19:21.11#ibcon#about to read 4, iclass 15, count 0 2006.210.08:19:21.11#ibcon#read 4, iclass 15, count 0 2006.210.08:19:21.11#ibcon#about to read 5, iclass 15, count 0 2006.210.08:19:21.11#ibcon#read 5, iclass 15, count 0 2006.210.08:19:21.11#ibcon#about to read 6, iclass 15, count 0 2006.210.08:19:21.11#ibcon#read 6, iclass 15, count 0 2006.210.08:19:21.11#ibcon#end of sib2, iclass 15, count 0 2006.210.08:19:21.11#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:19:21.11#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:19:21.11#ibcon#[27=USB\r\n] 2006.210.08:19:21.11#ibcon#*before write, iclass 15, count 0 2006.210.08:19:21.11#ibcon#enter sib2, iclass 15, count 0 2006.210.08:19:21.11#ibcon#flushed, iclass 15, count 0 2006.210.08:19:21.11#ibcon#about to write, iclass 15, count 0 2006.210.08:19:21.11#ibcon#wrote, iclass 15, count 0 2006.210.08:19:21.11#ibcon#about to read 3, iclass 15, count 0 2006.210.08:19:21.14#ibcon#read 3, iclass 15, count 0 2006.210.08:19:21.14#ibcon#about to read 4, iclass 15, count 0 2006.210.08:19:21.14#ibcon#read 4, iclass 15, count 0 2006.210.08:19:21.14#ibcon#about to read 5, iclass 15, count 0 2006.210.08:19:21.14#ibcon#read 5, iclass 15, count 0 2006.210.08:19:21.14#ibcon#about to read 6, iclass 15, count 0 2006.210.08:19:21.14#ibcon#read 6, iclass 15, count 0 2006.210.08:19:21.14#ibcon#end of sib2, iclass 15, count 0 2006.210.08:19:21.14#ibcon#*after write, iclass 15, count 0 2006.210.08:19:21.14#ibcon#*before return 0, iclass 15, count 0 2006.210.08:19:21.14#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:21.14#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.210.08:19:21.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:19:21.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:19:21.14$vc4f8/vblo=4,712.99 2006.210.08:19:21.14#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.210.08:19:21.14#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.210.08:19:21.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:21.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:21.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:21.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:21.14#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:19:21.14#ibcon#first serial, iclass 21, count 0 2006.210.08:19:21.14#ibcon#enter sib2, iclass 21, count 0 2006.210.08:19:21.14#ibcon#flushed, iclass 21, count 0 2006.210.08:19:21.14#ibcon#about to write, iclass 21, count 0 2006.210.08:19:21.14#ibcon#wrote, iclass 21, count 0 2006.210.08:19:21.14#ibcon#about to read 3, iclass 21, count 0 2006.210.08:19:21.16#ibcon#read 3, iclass 21, count 0 2006.210.08:19:21.16#ibcon#about to read 4, iclass 21, count 0 2006.210.08:19:21.16#ibcon#read 4, iclass 21, count 0 2006.210.08:19:21.16#ibcon#about to read 5, iclass 21, count 0 2006.210.08:19:21.16#ibcon#read 5, iclass 21, count 0 2006.210.08:19:21.16#ibcon#about to read 6, iclass 21, count 0 2006.210.08:19:21.16#ibcon#read 6, iclass 21, count 0 2006.210.08:19:21.16#ibcon#end of sib2, iclass 21, count 0 2006.210.08:19:21.16#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:19:21.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:19:21.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:19:21.16#ibcon#*before write, iclass 21, count 0 2006.210.08:19:21.16#ibcon#enter sib2, iclass 21, count 0 2006.210.08:19:21.16#ibcon#flushed, iclass 21, count 0 2006.210.08:19:21.16#ibcon#about to write, iclass 21, count 0 2006.210.08:19:21.16#ibcon#wrote, iclass 21, count 0 2006.210.08:19:21.16#ibcon#about to read 3, iclass 21, count 0 2006.210.08:19:21.20#ibcon#read 3, iclass 21, count 0 2006.210.08:19:21.20#ibcon#about to read 4, iclass 21, count 0 2006.210.08:19:21.20#ibcon#read 4, iclass 21, count 0 2006.210.08:19:21.20#ibcon#about to read 5, iclass 21, count 0 2006.210.08:19:21.20#ibcon#read 5, iclass 21, count 0 2006.210.08:19:21.20#ibcon#about to read 6, iclass 21, count 0 2006.210.08:19:21.20#ibcon#read 6, iclass 21, count 0 2006.210.08:19:21.20#ibcon#end of sib2, iclass 21, count 0 2006.210.08:19:21.20#ibcon#*after write, iclass 21, count 0 2006.210.08:19:21.20#ibcon#*before return 0, iclass 21, count 0 2006.210.08:19:21.20#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:21.20#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.210.08:19:21.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:19:21.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:19:21.20$vc4f8/vb=4,3 2006.210.08:19:21.20#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.210.08:19:21.20#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.210.08:19:21.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:21.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:21.26#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:21.26#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:21.26#ibcon#enter wrdev, iclass 23, count 2 2006.210.08:19:21.26#ibcon#first serial, iclass 23, count 2 2006.210.08:19:21.26#ibcon#enter sib2, iclass 23, count 2 2006.210.08:19:21.26#ibcon#flushed, iclass 23, count 2 2006.210.08:19:21.26#ibcon#about to write, iclass 23, count 2 2006.210.08:19:21.26#ibcon#wrote, iclass 23, count 2 2006.210.08:19:21.26#ibcon#about to read 3, iclass 23, count 2 2006.210.08:19:21.28#ibcon#read 3, iclass 23, count 2 2006.210.08:19:21.28#ibcon#about to read 4, iclass 23, count 2 2006.210.08:19:21.28#ibcon#read 4, iclass 23, count 2 2006.210.08:19:21.28#ibcon#about to read 5, iclass 23, count 2 2006.210.08:19:21.28#ibcon#read 5, iclass 23, count 2 2006.210.08:19:21.28#ibcon#about to read 6, iclass 23, count 2 2006.210.08:19:21.28#ibcon#read 6, iclass 23, count 2 2006.210.08:19:21.28#ibcon#end of sib2, iclass 23, count 2 2006.210.08:19:21.28#ibcon#*mode == 0, iclass 23, count 2 2006.210.08:19:21.28#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.210.08:19:21.28#ibcon#[27=AT04-03\r\n] 2006.210.08:19:21.28#ibcon#*before write, iclass 23, count 2 2006.210.08:19:21.28#ibcon#enter sib2, iclass 23, count 2 2006.210.08:19:21.28#ibcon#flushed, iclass 23, count 2 2006.210.08:19:21.28#ibcon#about to write, iclass 23, count 2 2006.210.08:19:21.28#ibcon#wrote, iclass 23, count 2 2006.210.08:19:21.28#ibcon#about to read 3, iclass 23, count 2 2006.210.08:19:21.31#ibcon#read 3, iclass 23, count 2 2006.210.08:19:21.31#ibcon#about to read 4, iclass 23, count 2 2006.210.08:19:21.31#ibcon#read 4, iclass 23, count 2 2006.210.08:19:21.31#ibcon#about to read 5, iclass 23, count 2 2006.210.08:19:21.31#ibcon#read 5, iclass 23, count 2 2006.210.08:19:21.31#ibcon#about to read 6, iclass 23, count 2 2006.210.08:19:21.31#ibcon#read 6, iclass 23, count 2 2006.210.08:19:21.31#ibcon#end of sib2, iclass 23, count 2 2006.210.08:19:21.31#ibcon#*after write, iclass 23, count 2 2006.210.08:19:21.31#ibcon#*before return 0, iclass 23, count 2 2006.210.08:19:21.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:21.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.210.08:19:21.31#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.210.08:19:21.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:21.31#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:21.43#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:21.43#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:21.43#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:19:21.43#ibcon#first serial, iclass 23, count 0 2006.210.08:19:21.43#ibcon#enter sib2, iclass 23, count 0 2006.210.08:19:21.43#ibcon#flushed, iclass 23, count 0 2006.210.08:19:21.43#ibcon#about to write, iclass 23, count 0 2006.210.08:19:21.43#ibcon#wrote, iclass 23, count 0 2006.210.08:19:21.43#ibcon#about to read 3, iclass 23, count 0 2006.210.08:19:21.45#ibcon#read 3, iclass 23, count 0 2006.210.08:19:21.45#ibcon#about to read 4, iclass 23, count 0 2006.210.08:19:21.45#ibcon#read 4, iclass 23, count 0 2006.210.08:19:21.45#ibcon#about to read 5, iclass 23, count 0 2006.210.08:19:21.45#ibcon#read 5, iclass 23, count 0 2006.210.08:19:21.45#ibcon#about to read 6, iclass 23, count 0 2006.210.08:19:21.45#ibcon#read 6, iclass 23, count 0 2006.210.08:19:21.45#ibcon#end of sib2, iclass 23, count 0 2006.210.08:19:21.45#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:19:21.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:19:21.45#ibcon#[27=USB\r\n] 2006.210.08:19:21.45#ibcon#*before write, iclass 23, count 0 2006.210.08:19:21.45#ibcon#enter sib2, iclass 23, count 0 2006.210.08:19:21.45#ibcon#flushed, iclass 23, count 0 2006.210.08:19:21.45#ibcon#about to write, iclass 23, count 0 2006.210.08:19:21.45#ibcon#wrote, iclass 23, count 0 2006.210.08:19:21.45#ibcon#about to read 3, iclass 23, count 0 2006.210.08:19:21.48#ibcon#read 3, iclass 23, count 0 2006.210.08:19:21.48#ibcon#about to read 4, iclass 23, count 0 2006.210.08:19:21.48#ibcon#read 4, iclass 23, count 0 2006.210.08:19:21.48#ibcon#about to read 5, iclass 23, count 0 2006.210.08:19:21.48#ibcon#read 5, iclass 23, count 0 2006.210.08:19:21.48#ibcon#about to read 6, iclass 23, count 0 2006.210.08:19:21.48#ibcon#read 6, iclass 23, count 0 2006.210.08:19:21.48#ibcon#end of sib2, iclass 23, count 0 2006.210.08:19:21.48#ibcon#*after write, iclass 23, count 0 2006.210.08:19:21.48#ibcon#*before return 0, iclass 23, count 0 2006.210.08:19:21.48#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:21.48#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.210.08:19:21.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:19:21.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:19:21.48$vc4f8/vblo=5,744.99 2006.210.08:19:21.48#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.210.08:19:21.48#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.210.08:19:21.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:21.48#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:21.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:21.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:21.48#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:19:21.48#ibcon#first serial, iclass 25, count 0 2006.210.08:19:21.48#ibcon#enter sib2, iclass 25, count 0 2006.210.08:19:21.48#ibcon#flushed, iclass 25, count 0 2006.210.08:19:21.48#ibcon#about to write, iclass 25, count 0 2006.210.08:19:21.48#ibcon#wrote, iclass 25, count 0 2006.210.08:19:21.48#ibcon#about to read 3, iclass 25, count 0 2006.210.08:19:21.50#ibcon#read 3, iclass 25, count 0 2006.210.08:19:21.50#ibcon#about to read 4, iclass 25, count 0 2006.210.08:19:21.50#ibcon#read 4, iclass 25, count 0 2006.210.08:19:21.50#ibcon#about to read 5, iclass 25, count 0 2006.210.08:19:21.50#ibcon#read 5, iclass 25, count 0 2006.210.08:19:21.50#ibcon#about to read 6, iclass 25, count 0 2006.210.08:19:21.50#ibcon#read 6, iclass 25, count 0 2006.210.08:19:21.50#ibcon#end of sib2, iclass 25, count 0 2006.210.08:19:21.50#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:19:21.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:19:21.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:19:21.50#ibcon#*before write, iclass 25, count 0 2006.210.08:19:21.50#ibcon#enter sib2, iclass 25, count 0 2006.210.08:19:21.50#ibcon#flushed, iclass 25, count 0 2006.210.08:19:21.50#ibcon#about to write, iclass 25, count 0 2006.210.08:19:21.50#ibcon#wrote, iclass 25, count 0 2006.210.08:19:21.50#ibcon#about to read 3, iclass 25, count 0 2006.210.08:19:21.54#ibcon#read 3, iclass 25, count 0 2006.210.08:19:21.54#ibcon#about to read 4, iclass 25, count 0 2006.210.08:19:21.54#ibcon#read 4, iclass 25, count 0 2006.210.08:19:21.54#ibcon#about to read 5, iclass 25, count 0 2006.210.08:19:21.54#ibcon#read 5, iclass 25, count 0 2006.210.08:19:21.54#ibcon#about to read 6, iclass 25, count 0 2006.210.08:19:21.54#ibcon#read 6, iclass 25, count 0 2006.210.08:19:21.54#ibcon#end of sib2, iclass 25, count 0 2006.210.08:19:21.54#ibcon#*after write, iclass 25, count 0 2006.210.08:19:21.54#ibcon#*before return 0, iclass 25, count 0 2006.210.08:19:21.54#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:21.54#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.210.08:19:21.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:19:21.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:19:21.54$vc4f8/vb=5,3 2006.210.08:19:21.54#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.210.08:19:21.54#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.210.08:19:21.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:21.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:21.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:21.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:21.60#ibcon#enter wrdev, iclass 27, count 2 2006.210.08:19:21.60#ibcon#first serial, iclass 27, count 2 2006.210.08:19:21.60#ibcon#enter sib2, iclass 27, count 2 2006.210.08:19:21.60#ibcon#flushed, iclass 27, count 2 2006.210.08:19:21.60#ibcon#about to write, iclass 27, count 2 2006.210.08:19:21.60#ibcon#wrote, iclass 27, count 2 2006.210.08:19:21.60#ibcon#about to read 3, iclass 27, count 2 2006.210.08:19:21.62#ibcon#read 3, iclass 27, count 2 2006.210.08:19:21.62#ibcon#about to read 4, iclass 27, count 2 2006.210.08:19:21.62#ibcon#read 4, iclass 27, count 2 2006.210.08:19:21.62#ibcon#about to read 5, iclass 27, count 2 2006.210.08:19:21.62#ibcon#read 5, iclass 27, count 2 2006.210.08:19:21.62#ibcon#about to read 6, iclass 27, count 2 2006.210.08:19:21.62#ibcon#read 6, iclass 27, count 2 2006.210.08:19:21.62#ibcon#end of sib2, iclass 27, count 2 2006.210.08:19:21.62#ibcon#*mode == 0, iclass 27, count 2 2006.210.08:19:21.62#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.210.08:19:21.62#ibcon#[27=AT05-03\r\n] 2006.210.08:19:21.62#ibcon#*before write, iclass 27, count 2 2006.210.08:19:21.62#ibcon#enter sib2, iclass 27, count 2 2006.210.08:19:21.62#ibcon#flushed, iclass 27, count 2 2006.210.08:19:21.62#ibcon#about to write, iclass 27, count 2 2006.210.08:19:21.62#ibcon#wrote, iclass 27, count 2 2006.210.08:19:21.62#ibcon#about to read 3, iclass 27, count 2 2006.210.08:19:21.65#ibcon#read 3, iclass 27, count 2 2006.210.08:19:21.65#ibcon#about to read 4, iclass 27, count 2 2006.210.08:19:21.65#ibcon#read 4, iclass 27, count 2 2006.210.08:19:21.65#ibcon#about to read 5, iclass 27, count 2 2006.210.08:19:21.65#ibcon#read 5, iclass 27, count 2 2006.210.08:19:21.65#ibcon#about to read 6, iclass 27, count 2 2006.210.08:19:21.65#ibcon#read 6, iclass 27, count 2 2006.210.08:19:21.65#ibcon#end of sib2, iclass 27, count 2 2006.210.08:19:21.65#ibcon#*after write, iclass 27, count 2 2006.210.08:19:21.65#ibcon#*before return 0, iclass 27, count 2 2006.210.08:19:21.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:21.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.210.08:19:21.65#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.210.08:19:21.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:21.65#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:21.77#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:21.77#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:21.77#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:19:21.77#ibcon#first serial, iclass 27, count 0 2006.210.08:19:21.77#ibcon#enter sib2, iclass 27, count 0 2006.210.08:19:21.77#ibcon#flushed, iclass 27, count 0 2006.210.08:19:21.77#ibcon#about to write, iclass 27, count 0 2006.210.08:19:21.77#ibcon#wrote, iclass 27, count 0 2006.210.08:19:21.77#ibcon#about to read 3, iclass 27, count 0 2006.210.08:19:21.79#ibcon#read 3, iclass 27, count 0 2006.210.08:19:21.79#ibcon#about to read 4, iclass 27, count 0 2006.210.08:19:21.79#ibcon#read 4, iclass 27, count 0 2006.210.08:19:21.79#ibcon#about to read 5, iclass 27, count 0 2006.210.08:19:21.79#ibcon#read 5, iclass 27, count 0 2006.210.08:19:21.79#ibcon#about to read 6, iclass 27, count 0 2006.210.08:19:21.79#ibcon#read 6, iclass 27, count 0 2006.210.08:19:21.79#ibcon#end of sib2, iclass 27, count 0 2006.210.08:19:21.79#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:19:21.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:19:21.79#ibcon#[27=USB\r\n] 2006.210.08:19:21.79#ibcon#*before write, iclass 27, count 0 2006.210.08:19:21.79#ibcon#enter sib2, iclass 27, count 0 2006.210.08:19:21.79#ibcon#flushed, iclass 27, count 0 2006.210.08:19:21.79#ibcon#about to write, iclass 27, count 0 2006.210.08:19:21.79#ibcon#wrote, iclass 27, count 0 2006.210.08:19:21.79#ibcon#about to read 3, iclass 27, count 0 2006.210.08:19:21.82#ibcon#read 3, iclass 27, count 0 2006.210.08:19:21.82#ibcon#about to read 4, iclass 27, count 0 2006.210.08:19:21.82#ibcon#read 4, iclass 27, count 0 2006.210.08:19:21.82#ibcon#about to read 5, iclass 27, count 0 2006.210.08:19:21.82#ibcon#read 5, iclass 27, count 0 2006.210.08:19:21.82#ibcon#about to read 6, iclass 27, count 0 2006.210.08:19:21.82#ibcon#read 6, iclass 27, count 0 2006.210.08:19:21.82#ibcon#end of sib2, iclass 27, count 0 2006.210.08:19:21.82#ibcon#*after write, iclass 27, count 0 2006.210.08:19:21.82#ibcon#*before return 0, iclass 27, count 0 2006.210.08:19:21.82#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:21.82#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.210.08:19:21.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:19:21.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:19:21.82$vc4f8/vblo=6,752.99 2006.210.08:19:21.82#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.210.08:19:21.82#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.210.08:19:21.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:19:21.82#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:21.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:21.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:21.82#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:19:21.82#ibcon#first serial, iclass 29, count 0 2006.210.08:19:21.82#ibcon#enter sib2, iclass 29, count 0 2006.210.08:19:21.82#ibcon#flushed, iclass 29, count 0 2006.210.08:19:21.82#ibcon#about to write, iclass 29, count 0 2006.210.08:19:21.82#ibcon#wrote, iclass 29, count 0 2006.210.08:19:21.82#ibcon#about to read 3, iclass 29, count 0 2006.210.08:19:21.84#ibcon#read 3, iclass 29, count 0 2006.210.08:19:21.84#ibcon#about to read 4, iclass 29, count 0 2006.210.08:19:21.84#ibcon#read 4, iclass 29, count 0 2006.210.08:19:21.84#ibcon#about to read 5, iclass 29, count 0 2006.210.08:19:21.84#ibcon#read 5, iclass 29, count 0 2006.210.08:19:21.84#ibcon#about to read 6, iclass 29, count 0 2006.210.08:19:21.84#ibcon#read 6, iclass 29, count 0 2006.210.08:19:21.84#ibcon#end of sib2, iclass 29, count 0 2006.210.08:19:21.84#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:19:21.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:19:21.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:19:21.84#ibcon#*before write, iclass 29, count 0 2006.210.08:19:21.84#ibcon#enter sib2, iclass 29, count 0 2006.210.08:19:21.84#ibcon#flushed, iclass 29, count 0 2006.210.08:19:21.84#ibcon#about to write, iclass 29, count 0 2006.210.08:19:21.84#ibcon#wrote, iclass 29, count 0 2006.210.08:19:21.84#ibcon#about to read 3, iclass 29, count 0 2006.210.08:19:21.88#ibcon#read 3, iclass 29, count 0 2006.210.08:19:21.88#ibcon#about to read 4, iclass 29, count 0 2006.210.08:19:21.88#ibcon#read 4, iclass 29, count 0 2006.210.08:19:21.88#ibcon#about to read 5, iclass 29, count 0 2006.210.08:19:21.88#ibcon#read 5, iclass 29, count 0 2006.210.08:19:21.88#ibcon#about to read 6, iclass 29, count 0 2006.210.08:19:21.88#ibcon#read 6, iclass 29, count 0 2006.210.08:19:21.88#ibcon#end of sib2, iclass 29, count 0 2006.210.08:19:21.88#ibcon#*after write, iclass 29, count 0 2006.210.08:19:21.88#ibcon#*before return 0, iclass 29, count 0 2006.210.08:19:21.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:21.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.210.08:19:21.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:19:21.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:19:21.88$vc4f8/vb=6,3 2006.210.08:19:21.88#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.210.08:19:21.88#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.210.08:19:21.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:19:21.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:21.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:21.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:21.94#ibcon#enter wrdev, iclass 31, count 2 2006.210.08:19:21.94#ibcon#first serial, iclass 31, count 2 2006.210.08:19:21.94#ibcon#enter sib2, iclass 31, count 2 2006.210.08:19:21.94#ibcon#flushed, iclass 31, count 2 2006.210.08:19:21.94#ibcon#about to write, iclass 31, count 2 2006.210.08:19:21.94#ibcon#wrote, iclass 31, count 2 2006.210.08:19:21.94#ibcon#about to read 3, iclass 31, count 2 2006.210.08:19:21.96#ibcon#read 3, iclass 31, count 2 2006.210.08:19:21.96#ibcon#about to read 4, iclass 31, count 2 2006.210.08:19:21.96#ibcon#read 4, iclass 31, count 2 2006.210.08:19:21.96#ibcon#about to read 5, iclass 31, count 2 2006.210.08:19:21.96#ibcon#read 5, iclass 31, count 2 2006.210.08:19:21.96#ibcon#about to read 6, iclass 31, count 2 2006.210.08:19:21.96#ibcon#read 6, iclass 31, count 2 2006.210.08:19:21.96#ibcon#end of sib2, iclass 31, count 2 2006.210.08:19:21.96#ibcon#*mode == 0, iclass 31, count 2 2006.210.08:19:21.96#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.210.08:19:21.96#ibcon#[27=AT06-03\r\n] 2006.210.08:19:21.96#ibcon#*before write, iclass 31, count 2 2006.210.08:19:21.96#ibcon#enter sib2, iclass 31, count 2 2006.210.08:19:21.96#ibcon#flushed, iclass 31, count 2 2006.210.08:19:21.96#ibcon#about to write, iclass 31, count 2 2006.210.08:19:21.96#ibcon#wrote, iclass 31, count 2 2006.210.08:19:21.96#ibcon#about to read 3, iclass 31, count 2 2006.210.08:19:21.99#ibcon#read 3, iclass 31, count 2 2006.210.08:19:21.99#ibcon#about to read 4, iclass 31, count 2 2006.210.08:19:21.99#ibcon#read 4, iclass 31, count 2 2006.210.08:19:21.99#ibcon#about to read 5, iclass 31, count 2 2006.210.08:19:21.99#ibcon#read 5, iclass 31, count 2 2006.210.08:19:21.99#ibcon#about to read 6, iclass 31, count 2 2006.210.08:19:21.99#ibcon#read 6, iclass 31, count 2 2006.210.08:19:21.99#ibcon#end of sib2, iclass 31, count 2 2006.210.08:19:21.99#ibcon#*after write, iclass 31, count 2 2006.210.08:19:21.99#ibcon#*before return 0, iclass 31, count 2 2006.210.08:19:21.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:21.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.210.08:19:21.99#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.210.08:19:21.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:19:21.99#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:22.11#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:22.11#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:22.11#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:19:22.11#ibcon#first serial, iclass 31, count 0 2006.210.08:19:22.11#ibcon#enter sib2, iclass 31, count 0 2006.210.08:19:22.11#ibcon#flushed, iclass 31, count 0 2006.210.08:19:22.11#ibcon#about to write, iclass 31, count 0 2006.210.08:19:22.11#ibcon#wrote, iclass 31, count 0 2006.210.08:19:22.11#ibcon#about to read 3, iclass 31, count 0 2006.210.08:19:22.13#ibcon#read 3, iclass 31, count 0 2006.210.08:19:22.13#ibcon#about to read 4, iclass 31, count 0 2006.210.08:19:22.13#ibcon#read 4, iclass 31, count 0 2006.210.08:19:22.13#ibcon#about to read 5, iclass 31, count 0 2006.210.08:19:22.13#ibcon#read 5, iclass 31, count 0 2006.210.08:19:22.13#ibcon#about to read 6, iclass 31, count 0 2006.210.08:19:22.13#ibcon#read 6, iclass 31, count 0 2006.210.08:19:22.13#ibcon#end of sib2, iclass 31, count 0 2006.210.08:19:22.13#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:19:22.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:19:22.13#ibcon#[27=USB\r\n] 2006.210.08:19:22.13#ibcon#*before write, iclass 31, count 0 2006.210.08:19:22.13#ibcon#enter sib2, iclass 31, count 0 2006.210.08:19:22.13#ibcon#flushed, iclass 31, count 0 2006.210.08:19:22.13#ibcon#about to write, iclass 31, count 0 2006.210.08:19:22.13#ibcon#wrote, iclass 31, count 0 2006.210.08:19:22.13#ibcon#about to read 3, iclass 31, count 0 2006.210.08:19:22.16#ibcon#read 3, iclass 31, count 0 2006.210.08:19:22.16#ibcon#about to read 4, iclass 31, count 0 2006.210.08:19:22.16#ibcon#read 4, iclass 31, count 0 2006.210.08:19:22.16#ibcon#about to read 5, iclass 31, count 0 2006.210.08:19:22.16#ibcon#read 5, iclass 31, count 0 2006.210.08:19:22.16#ibcon#about to read 6, iclass 31, count 0 2006.210.08:19:22.16#ibcon#read 6, iclass 31, count 0 2006.210.08:19:22.16#ibcon#end of sib2, iclass 31, count 0 2006.210.08:19:22.16#ibcon#*after write, iclass 31, count 0 2006.210.08:19:22.16#ibcon#*before return 0, iclass 31, count 0 2006.210.08:19:22.16#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:22.16#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.210.08:19:22.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:19:22.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:19:22.16$vc4f8/vabw=wide 2006.210.08:19:22.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.210.08:19:22.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.210.08:19:22.16#ibcon#ireg 8 cls_cnt 0 2006.210.08:19:22.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:22.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:22.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:22.16#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:19:22.16#ibcon#first serial, iclass 33, count 0 2006.210.08:19:22.16#ibcon#enter sib2, iclass 33, count 0 2006.210.08:19:22.16#ibcon#flushed, iclass 33, count 0 2006.210.08:19:22.16#ibcon#about to write, iclass 33, count 0 2006.210.08:19:22.16#ibcon#wrote, iclass 33, count 0 2006.210.08:19:22.16#ibcon#about to read 3, iclass 33, count 0 2006.210.08:19:22.18#ibcon#read 3, iclass 33, count 0 2006.210.08:19:22.18#ibcon#about to read 4, iclass 33, count 0 2006.210.08:19:22.18#ibcon#read 4, iclass 33, count 0 2006.210.08:19:22.18#ibcon#about to read 5, iclass 33, count 0 2006.210.08:19:22.18#ibcon#read 5, iclass 33, count 0 2006.210.08:19:22.18#ibcon#about to read 6, iclass 33, count 0 2006.210.08:19:22.18#ibcon#read 6, iclass 33, count 0 2006.210.08:19:22.18#ibcon#end of sib2, iclass 33, count 0 2006.210.08:19:22.18#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:19:22.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:19:22.18#ibcon#[25=BW32\r\n] 2006.210.08:19:22.18#ibcon#*before write, iclass 33, count 0 2006.210.08:19:22.18#ibcon#enter sib2, iclass 33, count 0 2006.210.08:19:22.18#ibcon#flushed, iclass 33, count 0 2006.210.08:19:22.18#ibcon#about to write, iclass 33, count 0 2006.210.08:19:22.18#ibcon#wrote, iclass 33, count 0 2006.210.08:19:22.18#ibcon#about to read 3, iclass 33, count 0 2006.210.08:19:22.21#ibcon#read 3, iclass 33, count 0 2006.210.08:19:22.21#ibcon#about to read 4, iclass 33, count 0 2006.210.08:19:22.21#ibcon#read 4, iclass 33, count 0 2006.210.08:19:22.21#ibcon#about to read 5, iclass 33, count 0 2006.210.08:19:22.21#ibcon#read 5, iclass 33, count 0 2006.210.08:19:22.21#ibcon#about to read 6, iclass 33, count 0 2006.210.08:19:22.21#ibcon#read 6, iclass 33, count 0 2006.210.08:19:22.21#ibcon#end of sib2, iclass 33, count 0 2006.210.08:19:22.21#ibcon#*after write, iclass 33, count 0 2006.210.08:19:22.21#ibcon#*before return 0, iclass 33, count 0 2006.210.08:19:22.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:22.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.210.08:19:22.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:19:22.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:19:22.21$vc4f8/vbbw=wide 2006.210.08:19:22.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:19:22.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:19:22.21#ibcon#ireg 8 cls_cnt 0 2006.210.08:19:22.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:19:22.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:19:22.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:19:22.28#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:19:22.28#ibcon#first serial, iclass 35, count 0 2006.210.08:19:22.28#ibcon#enter sib2, iclass 35, count 0 2006.210.08:19:22.28#ibcon#flushed, iclass 35, count 0 2006.210.08:19:22.28#ibcon#about to write, iclass 35, count 0 2006.210.08:19:22.28#ibcon#wrote, iclass 35, count 0 2006.210.08:19:22.28#ibcon#about to read 3, iclass 35, count 0 2006.210.08:19:22.30#ibcon#read 3, iclass 35, count 0 2006.210.08:19:22.30#ibcon#about to read 4, iclass 35, count 0 2006.210.08:19:22.30#ibcon#read 4, iclass 35, count 0 2006.210.08:19:22.30#ibcon#about to read 5, iclass 35, count 0 2006.210.08:19:22.30#ibcon#read 5, iclass 35, count 0 2006.210.08:19:22.30#ibcon#about to read 6, iclass 35, count 0 2006.210.08:19:22.30#ibcon#read 6, iclass 35, count 0 2006.210.08:19:22.30#ibcon#end of sib2, iclass 35, count 0 2006.210.08:19:22.30#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:19:22.30#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:19:22.30#ibcon#[27=BW32\r\n] 2006.210.08:19:22.30#ibcon#*before write, iclass 35, count 0 2006.210.08:19:22.30#ibcon#enter sib2, iclass 35, count 0 2006.210.08:19:22.30#ibcon#flushed, iclass 35, count 0 2006.210.08:19:22.30#ibcon#about to write, iclass 35, count 0 2006.210.08:19:22.30#ibcon#wrote, iclass 35, count 0 2006.210.08:19:22.30#ibcon#about to read 3, iclass 35, count 0 2006.210.08:19:22.33#ibcon#read 3, iclass 35, count 0 2006.210.08:19:22.33#ibcon#about to read 4, iclass 35, count 0 2006.210.08:19:22.33#ibcon#read 4, iclass 35, count 0 2006.210.08:19:22.33#ibcon#about to read 5, iclass 35, count 0 2006.210.08:19:22.33#ibcon#read 5, iclass 35, count 0 2006.210.08:19:22.33#ibcon#about to read 6, iclass 35, count 0 2006.210.08:19:22.33#ibcon#read 6, iclass 35, count 0 2006.210.08:19:22.33#ibcon#end of sib2, iclass 35, count 0 2006.210.08:19:22.33#ibcon#*after write, iclass 35, count 0 2006.210.08:19:22.33#ibcon#*before return 0, iclass 35, count 0 2006.210.08:19:22.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:19:22.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:19:22.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:19:22.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:19:22.33$4f8m12a/ifd4f 2006.210.08:19:22.33$ifd4f/lo= 2006.210.08:19:22.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:19:22.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:19:22.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:19:22.33$ifd4f/patch= 2006.210.08:19:22.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:19:22.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:19:22.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:19:22.33$4f8m12a/"form=m,16.000,1:2 2006.210.08:19:22.33$4f8m12a/"tpicd 2006.210.08:19:22.33$4f8m12a/echo=off 2006.210.08:19:22.33$4f8m12a/xlog=off 2006.210.08:19:22.33:!2006.210.08:20:50 2006.210.08:19:34.14#trakl#Source acquired 2006.210.08:19:34.14#flagr#flagr/antenna,acquired 2006.210.08:20:50.00:preob 2006.210.08:20:50.14/onsource/TRACKING 2006.210.08:20:50.14:!2006.210.08:21:00 2006.210.08:21:00.00:data_valid=on 2006.210.08:21:00.00:midob 2006.210.08:21:01.14/onsource/TRACKING 2006.210.08:21:01.14/wx/29.78,1006.5,82 2006.210.08:21:01.27/cable/+6.3950E-03 2006.210.08:21:02.36/va/01,08,usb,yes,28,30 2006.210.08:21:02.36/va/02,07,usb,yes,28,30 2006.210.08:21:02.36/va/03,06,usb,yes,30,30 2006.210.08:21:02.36/va/04,07,usb,yes,29,31 2006.210.08:21:02.36/va/05,07,usb,yes,30,32 2006.210.08:21:02.36/va/06,06,usb,yes,30,29 2006.210.08:21:02.36/va/07,06,usb,yes,30,30 2006.210.08:21:02.36/va/08,07,usb,yes,29,28 2006.210.08:21:02.59/valo/01,532.99,yes,locked 2006.210.08:21:02.59/valo/02,572.99,yes,locked 2006.210.08:21:02.59/valo/03,672.99,yes,locked 2006.210.08:21:02.59/valo/04,832.99,yes,locked 2006.210.08:21:02.59/valo/05,652.99,yes,locked 2006.210.08:21:02.59/valo/06,772.99,yes,locked 2006.210.08:21:02.59/valo/07,832.99,yes,locked 2006.210.08:21:02.59/valo/08,852.99,yes,locked 2006.210.08:21:03.68/vb/01,04,usb,yes,28,27 2006.210.08:21:03.68/vb/02,04,usb,yes,30,31 2006.210.08:21:03.68/vb/03,03,usb,yes,33,37 2006.210.08:21:03.68/vb/04,03,usb,yes,34,34 2006.210.08:21:03.68/vb/05,03,usb,yes,32,36 2006.210.08:21:03.68/vb/06,03,usb,yes,33,36 2006.210.08:21:03.68/vb/07,04,usb,yes,29,28 2006.210.08:21:03.68/vb/08,03,usb,yes,33,36 2006.210.08:21:03.91/vblo/01,632.99,yes,locked 2006.210.08:21:03.91/vblo/02,640.99,yes,locked 2006.210.08:21:03.91/vblo/03,656.99,yes,locked 2006.210.08:21:03.91/vblo/04,712.99,yes,locked 2006.210.08:21:03.91/vblo/05,744.99,yes,locked 2006.210.08:21:03.91/vblo/06,752.99,yes,locked 2006.210.08:21:03.91/vblo/07,734.99,yes,locked 2006.210.08:21:03.91/vblo/08,744.99,yes,locked 2006.210.08:21:04.06/vabw/8 2006.210.08:21:04.21/vbbw/8 2006.210.08:21:04.30/xfe/off,on,12.7 2006.210.08:21:04.68/ifatt/23,28,28,28 2006.210.08:21:05.07/fmout-gps/S +4.57E-07 2006.210.08:21:05.11:!2006.210.08:22:00 2006.210.08:22:00.00:data_valid=off 2006.210.08:22:00.00:postob 2006.210.08:22:00.18/cable/+6.3954E-03 2006.210.08:22:00.18/wx/29.73,1006.5,83 2006.210.08:22:01.07/fmout-gps/S +4.54E-07 2006.210.08:22:01.07:scan_name=210-0824,k06210,60 2006.210.08:22:01.07:source=1803+784,180045.68,782804.0,2000.0,cw 2006.210.08:22:01.14#flagr#flagr/antenna,new-source 2006.210.08:22:02.14:checkk5 2006.210.08:22:02.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:22:02.83/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:22:03.17/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:22:03.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:22:03.86/chk_obsdata//k5ts1/T2100821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:22:04.19/chk_obsdata//k5ts2/T2100821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:22:04.52/chk_obsdata//k5ts3/T2100821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:22:04.86/chk_obsdata//k5ts4/T2100821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:22:05.53/k5log//k5ts1_log_newline 2006.210.08:22:06.18/k5log//k5ts2_log_newline 2006.210.08:22:06.83/k5log//k5ts3_log_newline 2006.210.08:22:07.48/k5log//k5ts4_log_newline 2006.210.08:22:07.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:22:07.51:4f8m12a=3 2006.210.08:22:07.51$4f8m12a/echo=on 2006.210.08:22:07.51$4f8m12a/pcalon 2006.210.08:22:07.51$pcalon/"no phase cal control is implemented here 2006.210.08:22:07.51$4f8m12a/"tpicd=stop 2006.210.08:22:07.51$4f8m12a/vc4f8 2006.210.08:22:07.51$vc4f8/valo=1,532.99 2006.210.08:22:07.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.08:22:07.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.08:22:07.51#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:07.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:07.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:07.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:07.51#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:22:07.51#ibcon#first serial, iclass 30, count 0 2006.210.08:22:07.51#ibcon#enter sib2, iclass 30, count 0 2006.210.08:22:07.51#ibcon#flushed, iclass 30, count 0 2006.210.08:22:07.51#ibcon#about to write, iclass 30, count 0 2006.210.08:22:07.51#ibcon#wrote, iclass 30, count 0 2006.210.08:22:07.51#ibcon#about to read 3, iclass 30, count 0 2006.210.08:22:07.53#ibcon#read 3, iclass 30, count 0 2006.210.08:22:07.53#ibcon#about to read 4, iclass 30, count 0 2006.210.08:22:07.53#ibcon#read 4, iclass 30, count 0 2006.210.08:22:07.53#ibcon#about to read 5, iclass 30, count 0 2006.210.08:22:07.53#ibcon#read 5, iclass 30, count 0 2006.210.08:22:07.53#ibcon#about to read 6, iclass 30, count 0 2006.210.08:22:07.53#ibcon#read 6, iclass 30, count 0 2006.210.08:22:07.53#ibcon#end of sib2, iclass 30, count 0 2006.210.08:22:07.53#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:22:07.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:22:07.53#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:22:07.53#ibcon#*before write, iclass 30, count 0 2006.210.08:22:07.53#ibcon#enter sib2, iclass 30, count 0 2006.210.08:22:07.53#ibcon#flushed, iclass 30, count 0 2006.210.08:22:07.53#ibcon#about to write, iclass 30, count 0 2006.210.08:22:07.53#ibcon#wrote, iclass 30, count 0 2006.210.08:22:07.53#ibcon#about to read 3, iclass 30, count 0 2006.210.08:22:07.58#ibcon#read 3, iclass 30, count 0 2006.210.08:22:07.58#ibcon#about to read 4, iclass 30, count 0 2006.210.08:22:07.58#ibcon#read 4, iclass 30, count 0 2006.210.08:22:07.58#ibcon#about to read 5, iclass 30, count 0 2006.210.08:22:07.58#ibcon#read 5, iclass 30, count 0 2006.210.08:22:07.58#ibcon#about to read 6, iclass 30, count 0 2006.210.08:22:07.58#ibcon#read 6, iclass 30, count 0 2006.210.08:22:07.58#ibcon#end of sib2, iclass 30, count 0 2006.210.08:22:07.58#ibcon#*after write, iclass 30, count 0 2006.210.08:22:07.58#ibcon#*before return 0, iclass 30, count 0 2006.210.08:22:07.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:07.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:07.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:22:07.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:22:07.58$vc4f8/va=1,8 2006.210.08:22:07.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.08:22:07.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.08:22:07.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:07.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:07.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:07.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:07.58#ibcon#enter wrdev, iclass 32, count 2 2006.210.08:22:07.58#ibcon#first serial, iclass 32, count 2 2006.210.08:22:07.58#ibcon#enter sib2, iclass 32, count 2 2006.210.08:22:07.58#ibcon#flushed, iclass 32, count 2 2006.210.08:22:07.58#ibcon#about to write, iclass 32, count 2 2006.210.08:22:07.58#ibcon#wrote, iclass 32, count 2 2006.210.08:22:07.58#ibcon#about to read 3, iclass 32, count 2 2006.210.08:22:07.60#ibcon#read 3, iclass 32, count 2 2006.210.08:22:07.60#ibcon#about to read 4, iclass 32, count 2 2006.210.08:22:07.60#ibcon#read 4, iclass 32, count 2 2006.210.08:22:07.60#ibcon#about to read 5, iclass 32, count 2 2006.210.08:22:07.60#ibcon#read 5, iclass 32, count 2 2006.210.08:22:07.60#ibcon#about to read 6, iclass 32, count 2 2006.210.08:22:07.60#ibcon#read 6, iclass 32, count 2 2006.210.08:22:07.60#ibcon#end of sib2, iclass 32, count 2 2006.210.08:22:07.60#ibcon#*mode == 0, iclass 32, count 2 2006.210.08:22:07.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.08:22:07.60#ibcon#[25=AT01-08\r\n] 2006.210.08:22:07.60#ibcon#*before write, iclass 32, count 2 2006.210.08:22:07.60#ibcon#enter sib2, iclass 32, count 2 2006.210.08:22:07.60#ibcon#flushed, iclass 32, count 2 2006.210.08:22:07.60#ibcon#about to write, iclass 32, count 2 2006.210.08:22:07.60#ibcon#wrote, iclass 32, count 2 2006.210.08:22:07.60#ibcon#about to read 3, iclass 32, count 2 2006.210.08:22:07.63#ibcon#read 3, iclass 32, count 2 2006.210.08:22:07.63#ibcon#about to read 4, iclass 32, count 2 2006.210.08:22:07.63#ibcon#read 4, iclass 32, count 2 2006.210.08:22:07.63#ibcon#about to read 5, iclass 32, count 2 2006.210.08:22:07.63#ibcon#read 5, iclass 32, count 2 2006.210.08:22:07.63#ibcon#about to read 6, iclass 32, count 2 2006.210.08:22:07.63#ibcon#read 6, iclass 32, count 2 2006.210.08:22:07.63#ibcon#end of sib2, iclass 32, count 2 2006.210.08:22:07.63#ibcon#*after write, iclass 32, count 2 2006.210.08:22:07.63#ibcon#*before return 0, iclass 32, count 2 2006.210.08:22:07.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:07.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:07.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.08:22:07.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:07.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:07.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:07.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:07.75#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:22:07.75#ibcon#first serial, iclass 32, count 0 2006.210.08:22:07.75#ibcon#enter sib2, iclass 32, count 0 2006.210.08:22:07.75#ibcon#flushed, iclass 32, count 0 2006.210.08:22:07.75#ibcon#about to write, iclass 32, count 0 2006.210.08:22:07.75#ibcon#wrote, iclass 32, count 0 2006.210.08:22:07.75#ibcon#about to read 3, iclass 32, count 0 2006.210.08:22:07.77#ibcon#read 3, iclass 32, count 0 2006.210.08:22:07.77#ibcon#about to read 4, iclass 32, count 0 2006.210.08:22:07.77#ibcon#read 4, iclass 32, count 0 2006.210.08:22:07.77#ibcon#about to read 5, iclass 32, count 0 2006.210.08:22:07.77#ibcon#read 5, iclass 32, count 0 2006.210.08:22:07.77#ibcon#about to read 6, iclass 32, count 0 2006.210.08:22:07.77#ibcon#read 6, iclass 32, count 0 2006.210.08:22:07.77#ibcon#end of sib2, iclass 32, count 0 2006.210.08:22:07.77#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:22:07.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:22:07.77#ibcon#[25=USB\r\n] 2006.210.08:22:07.77#ibcon#*before write, iclass 32, count 0 2006.210.08:22:07.77#ibcon#enter sib2, iclass 32, count 0 2006.210.08:22:07.77#ibcon#flushed, iclass 32, count 0 2006.210.08:22:07.77#ibcon#about to write, iclass 32, count 0 2006.210.08:22:07.77#ibcon#wrote, iclass 32, count 0 2006.210.08:22:07.77#ibcon#about to read 3, iclass 32, count 0 2006.210.08:22:07.80#ibcon#read 3, iclass 32, count 0 2006.210.08:22:07.80#ibcon#about to read 4, iclass 32, count 0 2006.210.08:22:07.80#ibcon#read 4, iclass 32, count 0 2006.210.08:22:07.80#ibcon#about to read 5, iclass 32, count 0 2006.210.08:22:07.80#ibcon#read 5, iclass 32, count 0 2006.210.08:22:07.80#ibcon#about to read 6, iclass 32, count 0 2006.210.08:22:07.80#ibcon#read 6, iclass 32, count 0 2006.210.08:22:07.80#ibcon#end of sib2, iclass 32, count 0 2006.210.08:22:07.80#ibcon#*after write, iclass 32, count 0 2006.210.08:22:07.80#ibcon#*before return 0, iclass 32, count 0 2006.210.08:22:07.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:07.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:07.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:22:07.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:22:07.80$vc4f8/valo=2,572.99 2006.210.08:22:07.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:22:07.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:22:07.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:07.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:07.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:07.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:07.80#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:22:07.80#ibcon#first serial, iclass 34, count 0 2006.210.08:22:07.80#ibcon#enter sib2, iclass 34, count 0 2006.210.08:22:07.80#ibcon#flushed, iclass 34, count 0 2006.210.08:22:07.80#ibcon#about to write, iclass 34, count 0 2006.210.08:22:07.80#ibcon#wrote, iclass 34, count 0 2006.210.08:22:07.80#ibcon#about to read 3, iclass 34, count 0 2006.210.08:22:07.82#ibcon#read 3, iclass 34, count 0 2006.210.08:22:07.82#ibcon#about to read 4, iclass 34, count 0 2006.210.08:22:07.82#ibcon#read 4, iclass 34, count 0 2006.210.08:22:07.82#ibcon#about to read 5, iclass 34, count 0 2006.210.08:22:07.82#ibcon#read 5, iclass 34, count 0 2006.210.08:22:07.82#ibcon#about to read 6, iclass 34, count 0 2006.210.08:22:07.82#ibcon#read 6, iclass 34, count 0 2006.210.08:22:07.82#ibcon#end of sib2, iclass 34, count 0 2006.210.08:22:07.82#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:22:07.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:22:07.82#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:22:07.82#ibcon#*before write, iclass 34, count 0 2006.210.08:22:07.82#ibcon#enter sib2, iclass 34, count 0 2006.210.08:22:07.82#ibcon#flushed, iclass 34, count 0 2006.210.08:22:07.82#ibcon#about to write, iclass 34, count 0 2006.210.08:22:07.82#ibcon#wrote, iclass 34, count 0 2006.210.08:22:07.82#ibcon#about to read 3, iclass 34, count 0 2006.210.08:22:07.86#ibcon#read 3, iclass 34, count 0 2006.210.08:22:07.86#ibcon#about to read 4, iclass 34, count 0 2006.210.08:22:07.86#ibcon#read 4, iclass 34, count 0 2006.210.08:22:07.86#ibcon#about to read 5, iclass 34, count 0 2006.210.08:22:07.86#ibcon#read 5, iclass 34, count 0 2006.210.08:22:07.86#ibcon#about to read 6, iclass 34, count 0 2006.210.08:22:07.86#ibcon#read 6, iclass 34, count 0 2006.210.08:22:07.86#ibcon#end of sib2, iclass 34, count 0 2006.210.08:22:07.86#ibcon#*after write, iclass 34, count 0 2006.210.08:22:07.86#ibcon#*before return 0, iclass 34, count 0 2006.210.08:22:07.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:07.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:07.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:22:07.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:22:07.86$vc4f8/va=2,7 2006.210.08:22:07.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.08:22:07.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.08:22:07.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:07.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:07.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:07.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:07.92#ibcon#enter wrdev, iclass 36, count 2 2006.210.08:22:07.92#ibcon#first serial, iclass 36, count 2 2006.210.08:22:07.92#ibcon#enter sib2, iclass 36, count 2 2006.210.08:22:07.92#ibcon#flushed, iclass 36, count 2 2006.210.08:22:07.92#ibcon#about to write, iclass 36, count 2 2006.210.08:22:07.92#ibcon#wrote, iclass 36, count 2 2006.210.08:22:07.92#ibcon#about to read 3, iclass 36, count 2 2006.210.08:22:07.94#ibcon#read 3, iclass 36, count 2 2006.210.08:22:07.94#ibcon#about to read 4, iclass 36, count 2 2006.210.08:22:07.94#ibcon#read 4, iclass 36, count 2 2006.210.08:22:07.94#ibcon#about to read 5, iclass 36, count 2 2006.210.08:22:07.94#ibcon#read 5, iclass 36, count 2 2006.210.08:22:07.94#ibcon#about to read 6, iclass 36, count 2 2006.210.08:22:07.94#ibcon#read 6, iclass 36, count 2 2006.210.08:22:07.94#ibcon#end of sib2, iclass 36, count 2 2006.210.08:22:07.94#ibcon#*mode == 0, iclass 36, count 2 2006.210.08:22:07.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.08:22:07.94#ibcon#[25=AT02-07\r\n] 2006.210.08:22:07.94#ibcon#*before write, iclass 36, count 2 2006.210.08:22:07.94#ibcon#enter sib2, iclass 36, count 2 2006.210.08:22:07.94#ibcon#flushed, iclass 36, count 2 2006.210.08:22:07.94#ibcon#about to write, iclass 36, count 2 2006.210.08:22:07.94#ibcon#wrote, iclass 36, count 2 2006.210.08:22:07.94#ibcon#about to read 3, iclass 36, count 2 2006.210.08:22:07.97#ibcon#read 3, iclass 36, count 2 2006.210.08:22:07.97#ibcon#about to read 4, iclass 36, count 2 2006.210.08:22:07.97#ibcon#read 4, iclass 36, count 2 2006.210.08:22:07.97#ibcon#about to read 5, iclass 36, count 2 2006.210.08:22:07.97#ibcon#read 5, iclass 36, count 2 2006.210.08:22:07.97#ibcon#about to read 6, iclass 36, count 2 2006.210.08:22:07.97#ibcon#read 6, iclass 36, count 2 2006.210.08:22:07.97#ibcon#end of sib2, iclass 36, count 2 2006.210.08:22:07.97#ibcon#*after write, iclass 36, count 2 2006.210.08:22:07.97#ibcon#*before return 0, iclass 36, count 2 2006.210.08:22:07.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:07.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:07.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.08:22:07.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:07.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:08.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:08.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:08.09#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:22:08.09#ibcon#first serial, iclass 36, count 0 2006.210.08:22:08.09#ibcon#enter sib2, iclass 36, count 0 2006.210.08:22:08.09#ibcon#flushed, iclass 36, count 0 2006.210.08:22:08.09#ibcon#about to write, iclass 36, count 0 2006.210.08:22:08.09#ibcon#wrote, iclass 36, count 0 2006.210.08:22:08.09#ibcon#about to read 3, iclass 36, count 0 2006.210.08:22:08.11#ibcon#read 3, iclass 36, count 0 2006.210.08:22:08.11#ibcon#about to read 4, iclass 36, count 0 2006.210.08:22:08.11#ibcon#read 4, iclass 36, count 0 2006.210.08:22:08.11#ibcon#about to read 5, iclass 36, count 0 2006.210.08:22:08.11#ibcon#read 5, iclass 36, count 0 2006.210.08:22:08.11#ibcon#about to read 6, iclass 36, count 0 2006.210.08:22:08.11#ibcon#read 6, iclass 36, count 0 2006.210.08:22:08.11#ibcon#end of sib2, iclass 36, count 0 2006.210.08:22:08.11#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:22:08.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:22:08.11#ibcon#[25=USB\r\n] 2006.210.08:22:08.11#ibcon#*before write, iclass 36, count 0 2006.210.08:22:08.11#ibcon#enter sib2, iclass 36, count 0 2006.210.08:22:08.11#ibcon#flushed, iclass 36, count 0 2006.210.08:22:08.11#ibcon#about to write, iclass 36, count 0 2006.210.08:22:08.11#ibcon#wrote, iclass 36, count 0 2006.210.08:22:08.11#ibcon#about to read 3, iclass 36, count 0 2006.210.08:22:08.14#ibcon#read 3, iclass 36, count 0 2006.210.08:22:08.14#ibcon#about to read 4, iclass 36, count 0 2006.210.08:22:08.14#ibcon#read 4, iclass 36, count 0 2006.210.08:22:08.14#ibcon#about to read 5, iclass 36, count 0 2006.210.08:22:08.14#ibcon#read 5, iclass 36, count 0 2006.210.08:22:08.14#ibcon#about to read 6, iclass 36, count 0 2006.210.08:22:08.14#ibcon#read 6, iclass 36, count 0 2006.210.08:22:08.14#ibcon#end of sib2, iclass 36, count 0 2006.210.08:22:08.14#ibcon#*after write, iclass 36, count 0 2006.210.08:22:08.14#ibcon#*before return 0, iclass 36, count 0 2006.210.08:22:08.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:08.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:08.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:22:08.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:22:08.14$vc4f8/valo=3,672.99 2006.210.08:22:08.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.08:22:08.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.08:22:08.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:08.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:08.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:08.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:08.14#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:22:08.14#ibcon#first serial, iclass 38, count 0 2006.210.08:22:08.14#ibcon#enter sib2, iclass 38, count 0 2006.210.08:22:08.14#ibcon#flushed, iclass 38, count 0 2006.210.08:22:08.14#ibcon#about to write, iclass 38, count 0 2006.210.08:22:08.14#ibcon#wrote, iclass 38, count 0 2006.210.08:22:08.14#ibcon#about to read 3, iclass 38, count 0 2006.210.08:22:08.16#ibcon#read 3, iclass 38, count 0 2006.210.08:22:08.16#ibcon#about to read 4, iclass 38, count 0 2006.210.08:22:08.16#ibcon#read 4, iclass 38, count 0 2006.210.08:22:08.16#ibcon#about to read 5, iclass 38, count 0 2006.210.08:22:08.16#ibcon#read 5, iclass 38, count 0 2006.210.08:22:08.16#ibcon#about to read 6, iclass 38, count 0 2006.210.08:22:08.16#ibcon#read 6, iclass 38, count 0 2006.210.08:22:08.16#ibcon#end of sib2, iclass 38, count 0 2006.210.08:22:08.16#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:22:08.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:22:08.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:22:08.16#ibcon#*before write, iclass 38, count 0 2006.210.08:22:08.16#ibcon#enter sib2, iclass 38, count 0 2006.210.08:22:08.16#ibcon#flushed, iclass 38, count 0 2006.210.08:22:08.16#ibcon#about to write, iclass 38, count 0 2006.210.08:22:08.16#ibcon#wrote, iclass 38, count 0 2006.210.08:22:08.16#ibcon#about to read 3, iclass 38, count 0 2006.210.08:22:08.20#ibcon#read 3, iclass 38, count 0 2006.210.08:22:08.20#ibcon#about to read 4, iclass 38, count 0 2006.210.08:22:08.20#ibcon#read 4, iclass 38, count 0 2006.210.08:22:08.20#ibcon#about to read 5, iclass 38, count 0 2006.210.08:22:08.20#ibcon#read 5, iclass 38, count 0 2006.210.08:22:08.20#ibcon#about to read 6, iclass 38, count 0 2006.210.08:22:08.20#ibcon#read 6, iclass 38, count 0 2006.210.08:22:08.20#ibcon#end of sib2, iclass 38, count 0 2006.210.08:22:08.20#ibcon#*after write, iclass 38, count 0 2006.210.08:22:08.20#ibcon#*before return 0, iclass 38, count 0 2006.210.08:22:08.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:08.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:08.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:22:08.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:22:08.20$vc4f8/va=3,6 2006.210.08:22:08.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.08:22:08.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.08:22:08.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:08.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:08.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:08.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:08.26#ibcon#enter wrdev, iclass 40, count 2 2006.210.08:22:08.26#ibcon#first serial, iclass 40, count 2 2006.210.08:22:08.26#ibcon#enter sib2, iclass 40, count 2 2006.210.08:22:08.26#ibcon#flushed, iclass 40, count 2 2006.210.08:22:08.26#ibcon#about to write, iclass 40, count 2 2006.210.08:22:08.26#ibcon#wrote, iclass 40, count 2 2006.210.08:22:08.26#ibcon#about to read 3, iclass 40, count 2 2006.210.08:22:08.28#ibcon#read 3, iclass 40, count 2 2006.210.08:22:08.28#ibcon#about to read 4, iclass 40, count 2 2006.210.08:22:08.28#ibcon#read 4, iclass 40, count 2 2006.210.08:22:08.28#ibcon#about to read 5, iclass 40, count 2 2006.210.08:22:08.28#ibcon#read 5, iclass 40, count 2 2006.210.08:22:08.28#ibcon#about to read 6, iclass 40, count 2 2006.210.08:22:08.28#ibcon#read 6, iclass 40, count 2 2006.210.08:22:08.28#ibcon#end of sib2, iclass 40, count 2 2006.210.08:22:08.28#ibcon#*mode == 0, iclass 40, count 2 2006.210.08:22:08.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.08:22:08.28#ibcon#[25=AT03-06\r\n] 2006.210.08:22:08.28#ibcon#*before write, iclass 40, count 2 2006.210.08:22:08.28#ibcon#enter sib2, iclass 40, count 2 2006.210.08:22:08.28#ibcon#flushed, iclass 40, count 2 2006.210.08:22:08.28#ibcon#about to write, iclass 40, count 2 2006.210.08:22:08.28#ibcon#wrote, iclass 40, count 2 2006.210.08:22:08.28#ibcon#about to read 3, iclass 40, count 2 2006.210.08:22:08.31#ibcon#read 3, iclass 40, count 2 2006.210.08:22:08.31#ibcon#about to read 4, iclass 40, count 2 2006.210.08:22:08.31#ibcon#read 4, iclass 40, count 2 2006.210.08:22:08.31#ibcon#about to read 5, iclass 40, count 2 2006.210.08:22:08.31#ibcon#read 5, iclass 40, count 2 2006.210.08:22:08.31#ibcon#about to read 6, iclass 40, count 2 2006.210.08:22:08.31#ibcon#read 6, iclass 40, count 2 2006.210.08:22:08.31#ibcon#end of sib2, iclass 40, count 2 2006.210.08:22:08.31#ibcon#*after write, iclass 40, count 2 2006.210.08:22:08.31#ibcon#*before return 0, iclass 40, count 2 2006.210.08:22:08.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:08.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:08.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.08:22:08.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:08.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:08.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:08.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:08.43#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:22:08.43#ibcon#first serial, iclass 40, count 0 2006.210.08:22:08.43#ibcon#enter sib2, iclass 40, count 0 2006.210.08:22:08.43#ibcon#flushed, iclass 40, count 0 2006.210.08:22:08.43#ibcon#about to write, iclass 40, count 0 2006.210.08:22:08.43#ibcon#wrote, iclass 40, count 0 2006.210.08:22:08.43#ibcon#about to read 3, iclass 40, count 0 2006.210.08:22:08.45#ibcon#read 3, iclass 40, count 0 2006.210.08:22:08.45#ibcon#about to read 4, iclass 40, count 0 2006.210.08:22:08.45#ibcon#read 4, iclass 40, count 0 2006.210.08:22:08.45#ibcon#about to read 5, iclass 40, count 0 2006.210.08:22:08.45#ibcon#read 5, iclass 40, count 0 2006.210.08:22:08.45#ibcon#about to read 6, iclass 40, count 0 2006.210.08:22:08.45#ibcon#read 6, iclass 40, count 0 2006.210.08:22:08.45#ibcon#end of sib2, iclass 40, count 0 2006.210.08:22:08.45#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:22:08.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:22:08.45#ibcon#[25=USB\r\n] 2006.210.08:22:08.45#ibcon#*before write, iclass 40, count 0 2006.210.08:22:08.45#ibcon#enter sib2, iclass 40, count 0 2006.210.08:22:08.45#ibcon#flushed, iclass 40, count 0 2006.210.08:22:08.45#ibcon#about to write, iclass 40, count 0 2006.210.08:22:08.45#ibcon#wrote, iclass 40, count 0 2006.210.08:22:08.45#ibcon#about to read 3, iclass 40, count 0 2006.210.08:22:08.48#ibcon#read 3, iclass 40, count 0 2006.210.08:22:08.48#ibcon#about to read 4, iclass 40, count 0 2006.210.08:22:08.48#ibcon#read 4, iclass 40, count 0 2006.210.08:22:08.48#ibcon#about to read 5, iclass 40, count 0 2006.210.08:22:08.48#ibcon#read 5, iclass 40, count 0 2006.210.08:22:08.48#ibcon#about to read 6, iclass 40, count 0 2006.210.08:22:08.48#ibcon#read 6, iclass 40, count 0 2006.210.08:22:08.48#ibcon#end of sib2, iclass 40, count 0 2006.210.08:22:08.48#ibcon#*after write, iclass 40, count 0 2006.210.08:22:08.48#ibcon#*before return 0, iclass 40, count 0 2006.210.08:22:08.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:08.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:08.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:22:08.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:22:08.48$vc4f8/valo=4,832.99 2006.210.08:22:08.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.08:22:08.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.08:22:08.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:08.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:08.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:08.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:08.48#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:22:08.48#ibcon#first serial, iclass 4, count 0 2006.210.08:22:08.48#ibcon#enter sib2, iclass 4, count 0 2006.210.08:22:08.48#ibcon#flushed, iclass 4, count 0 2006.210.08:22:08.48#ibcon#about to write, iclass 4, count 0 2006.210.08:22:08.48#ibcon#wrote, iclass 4, count 0 2006.210.08:22:08.48#ibcon#about to read 3, iclass 4, count 0 2006.210.08:22:08.50#ibcon#read 3, iclass 4, count 0 2006.210.08:22:08.50#ibcon#about to read 4, iclass 4, count 0 2006.210.08:22:08.50#ibcon#read 4, iclass 4, count 0 2006.210.08:22:08.50#ibcon#about to read 5, iclass 4, count 0 2006.210.08:22:08.50#ibcon#read 5, iclass 4, count 0 2006.210.08:22:08.50#ibcon#about to read 6, iclass 4, count 0 2006.210.08:22:08.50#ibcon#read 6, iclass 4, count 0 2006.210.08:22:08.50#ibcon#end of sib2, iclass 4, count 0 2006.210.08:22:08.50#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:22:08.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:22:08.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:22:08.50#ibcon#*before write, iclass 4, count 0 2006.210.08:22:08.50#ibcon#enter sib2, iclass 4, count 0 2006.210.08:22:08.50#ibcon#flushed, iclass 4, count 0 2006.210.08:22:08.50#ibcon#about to write, iclass 4, count 0 2006.210.08:22:08.50#ibcon#wrote, iclass 4, count 0 2006.210.08:22:08.50#ibcon#about to read 3, iclass 4, count 0 2006.210.08:22:08.54#ibcon#read 3, iclass 4, count 0 2006.210.08:22:08.54#ibcon#about to read 4, iclass 4, count 0 2006.210.08:22:08.54#ibcon#read 4, iclass 4, count 0 2006.210.08:22:08.54#ibcon#about to read 5, iclass 4, count 0 2006.210.08:22:08.54#ibcon#read 5, iclass 4, count 0 2006.210.08:22:08.54#ibcon#about to read 6, iclass 4, count 0 2006.210.08:22:08.54#ibcon#read 6, iclass 4, count 0 2006.210.08:22:08.54#ibcon#end of sib2, iclass 4, count 0 2006.210.08:22:08.54#ibcon#*after write, iclass 4, count 0 2006.210.08:22:08.54#ibcon#*before return 0, iclass 4, count 0 2006.210.08:22:08.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:08.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:08.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:22:08.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:22:08.54$vc4f8/va=4,7 2006.210.08:22:08.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.08:22:08.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.08:22:08.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:08.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:08.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:08.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:08.60#ibcon#enter wrdev, iclass 6, count 2 2006.210.08:22:08.60#ibcon#first serial, iclass 6, count 2 2006.210.08:22:08.60#ibcon#enter sib2, iclass 6, count 2 2006.210.08:22:08.60#ibcon#flushed, iclass 6, count 2 2006.210.08:22:08.60#ibcon#about to write, iclass 6, count 2 2006.210.08:22:08.60#ibcon#wrote, iclass 6, count 2 2006.210.08:22:08.60#ibcon#about to read 3, iclass 6, count 2 2006.210.08:22:08.62#ibcon#read 3, iclass 6, count 2 2006.210.08:22:08.62#ibcon#about to read 4, iclass 6, count 2 2006.210.08:22:08.62#ibcon#read 4, iclass 6, count 2 2006.210.08:22:08.62#ibcon#about to read 5, iclass 6, count 2 2006.210.08:22:08.62#ibcon#read 5, iclass 6, count 2 2006.210.08:22:08.62#ibcon#about to read 6, iclass 6, count 2 2006.210.08:22:08.62#ibcon#read 6, iclass 6, count 2 2006.210.08:22:08.62#ibcon#end of sib2, iclass 6, count 2 2006.210.08:22:08.62#ibcon#*mode == 0, iclass 6, count 2 2006.210.08:22:08.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.08:22:08.62#ibcon#[25=AT04-07\r\n] 2006.210.08:22:08.62#ibcon#*before write, iclass 6, count 2 2006.210.08:22:08.62#ibcon#enter sib2, iclass 6, count 2 2006.210.08:22:08.62#ibcon#flushed, iclass 6, count 2 2006.210.08:22:08.62#ibcon#about to write, iclass 6, count 2 2006.210.08:22:08.62#ibcon#wrote, iclass 6, count 2 2006.210.08:22:08.62#ibcon#about to read 3, iclass 6, count 2 2006.210.08:22:08.65#ibcon#read 3, iclass 6, count 2 2006.210.08:22:08.65#ibcon#about to read 4, iclass 6, count 2 2006.210.08:22:08.65#ibcon#read 4, iclass 6, count 2 2006.210.08:22:08.65#ibcon#about to read 5, iclass 6, count 2 2006.210.08:22:08.65#ibcon#read 5, iclass 6, count 2 2006.210.08:22:08.65#ibcon#about to read 6, iclass 6, count 2 2006.210.08:22:08.65#ibcon#read 6, iclass 6, count 2 2006.210.08:22:08.65#ibcon#end of sib2, iclass 6, count 2 2006.210.08:22:08.65#ibcon#*after write, iclass 6, count 2 2006.210.08:22:08.65#ibcon#*before return 0, iclass 6, count 2 2006.210.08:22:08.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:08.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:08.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.08:22:08.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:08.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:08.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:08.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:08.77#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:22:08.77#ibcon#first serial, iclass 6, count 0 2006.210.08:22:08.77#ibcon#enter sib2, iclass 6, count 0 2006.210.08:22:08.77#ibcon#flushed, iclass 6, count 0 2006.210.08:22:08.77#ibcon#about to write, iclass 6, count 0 2006.210.08:22:08.77#ibcon#wrote, iclass 6, count 0 2006.210.08:22:08.77#ibcon#about to read 3, iclass 6, count 0 2006.210.08:22:08.79#ibcon#read 3, iclass 6, count 0 2006.210.08:22:08.79#ibcon#about to read 4, iclass 6, count 0 2006.210.08:22:08.79#ibcon#read 4, iclass 6, count 0 2006.210.08:22:08.79#ibcon#about to read 5, iclass 6, count 0 2006.210.08:22:08.79#ibcon#read 5, iclass 6, count 0 2006.210.08:22:08.79#ibcon#about to read 6, iclass 6, count 0 2006.210.08:22:08.79#ibcon#read 6, iclass 6, count 0 2006.210.08:22:08.79#ibcon#end of sib2, iclass 6, count 0 2006.210.08:22:08.79#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:22:08.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:22:08.79#ibcon#[25=USB\r\n] 2006.210.08:22:08.79#ibcon#*before write, iclass 6, count 0 2006.210.08:22:08.79#ibcon#enter sib2, iclass 6, count 0 2006.210.08:22:08.79#ibcon#flushed, iclass 6, count 0 2006.210.08:22:08.79#ibcon#about to write, iclass 6, count 0 2006.210.08:22:08.79#ibcon#wrote, iclass 6, count 0 2006.210.08:22:08.79#ibcon#about to read 3, iclass 6, count 0 2006.210.08:22:08.82#ibcon#read 3, iclass 6, count 0 2006.210.08:22:08.82#ibcon#about to read 4, iclass 6, count 0 2006.210.08:22:08.82#ibcon#read 4, iclass 6, count 0 2006.210.08:22:08.82#ibcon#about to read 5, iclass 6, count 0 2006.210.08:22:08.82#ibcon#read 5, iclass 6, count 0 2006.210.08:22:08.82#ibcon#about to read 6, iclass 6, count 0 2006.210.08:22:08.82#ibcon#read 6, iclass 6, count 0 2006.210.08:22:08.82#ibcon#end of sib2, iclass 6, count 0 2006.210.08:22:08.82#ibcon#*after write, iclass 6, count 0 2006.210.08:22:08.82#ibcon#*before return 0, iclass 6, count 0 2006.210.08:22:08.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:08.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:08.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:22:08.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:22:08.82$vc4f8/valo=5,652.99 2006.210.08:22:08.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.08:22:08.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.08:22:08.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:08.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:08.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:08.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:08.82#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:22:08.82#ibcon#first serial, iclass 10, count 0 2006.210.08:22:08.82#ibcon#enter sib2, iclass 10, count 0 2006.210.08:22:08.82#ibcon#flushed, iclass 10, count 0 2006.210.08:22:08.82#ibcon#about to write, iclass 10, count 0 2006.210.08:22:08.82#ibcon#wrote, iclass 10, count 0 2006.210.08:22:08.82#ibcon#about to read 3, iclass 10, count 0 2006.210.08:22:08.84#ibcon#read 3, iclass 10, count 0 2006.210.08:22:08.84#ibcon#about to read 4, iclass 10, count 0 2006.210.08:22:08.84#ibcon#read 4, iclass 10, count 0 2006.210.08:22:08.84#ibcon#about to read 5, iclass 10, count 0 2006.210.08:22:08.84#ibcon#read 5, iclass 10, count 0 2006.210.08:22:08.84#ibcon#about to read 6, iclass 10, count 0 2006.210.08:22:08.84#ibcon#read 6, iclass 10, count 0 2006.210.08:22:08.84#ibcon#end of sib2, iclass 10, count 0 2006.210.08:22:08.84#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:22:08.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:22:08.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:22:08.84#ibcon#*before write, iclass 10, count 0 2006.210.08:22:08.84#ibcon#enter sib2, iclass 10, count 0 2006.210.08:22:08.84#ibcon#flushed, iclass 10, count 0 2006.210.08:22:08.84#ibcon#about to write, iclass 10, count 0 2006.210.08:22:08.84#ibcon#wrote, iclass 10, count 0 2006.210.08:22:08.84#ibcon#about to read 3, iclass 10, count 0 2006.210.08:22:08.88#ibcon#read 3, iclass 10, count 0 2006.210.08:22:08.88#ibcon#about to read 4, iclass 10, count 0 2006.210.08:22:08.88#ibcon#read 4, iclass 10, count 0 2006.210.08:22:08.88#ibcon#about to read 5, iclass 10, count 0 2006.210.08:22:08.88#ibcon#read 5, iclass 10, count 0 2006.210.08:22:08.88#ibcon#about to read 6, iclass 10, count 0 2006.210.08:22:08.88#ibcon#read 6, iclass 10, count 0 2006.210.08:22:08.88#ibcon#end of sib2, iclass 10, count 0 2006.210.08:22:08.88#ibcon#*after write, iclass 10, count 0 2006.210.08:22:08.88#ibcon#*before return 0, iclass 10, count 0 2006.210.08:22:08.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:08.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:08.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:22:08.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:22:08.88$vc4f8/va=5,7 2006.210.08:22:08.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.08:22:08.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.08:22:08.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:08.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:08.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:08.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:08.94#ibcon#enter wrdev, iclass 12, count 2 2006.210.08:22:08.94#ibcon#first serial, iclass 12, count 2 2006.210.08:22:08.94#ibcon#enter sib2, iclass 12, count 2 2006.210.08:22:08.94#ibcon#flushed, iclass 12, count 2 2006.210.08:22:08.94#ibcon#about to write, iclass 12, count 2 2006.210.08:22:08.94#ibcon#wrote, iclass 12, count 2 2006.210.08:22:08.94#ibcon#about to read 3, iclass 12, count 2 2006.210.08:22:08.96#ibcon#read 3, iclass 12, count 2 2006.210.08:22:08.96#ibcon#about to read 4, iclass 12, count 2 2006.210.08:22:08.96#ibcon#read 4, iclass 12, count 2 2006.210.08:22:08.96#ibcon#about to read 5, iclass 12, count 2 2006.210.08:22:08.96#ibcon#read 5, iclass 12, count 2 2006.210.08:22:08.96#ibcon#about to read 6, iclass 12, count 2 2006.210.08:22:08.96#ibcon#read 6, iclass 12, count 2 2006.210.08:22:08.96#ibcon#end of sib2, iclass 12, count 2 2006.210.08:22:08.96#ibcon#*mode == 0, iclass 12, count 2 2006.210.08:22:08.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.08:22:08.96#ibcon#[25=AT05-07\r\n] 2006.210.08:22:08.96#ibcon#*before write, iclass 12, count 2 2006.210.08:22:08.96#ibcon#enter sib2, iclass 12, count 2 2006.210.08:22:08.96#ibcon#flushed, iclass 12, count 2 2006.210.08:22:08.96#ibcon#about to write, iclass 12, count 2 2006.210.08:22:08.96#ibcon#wrote, iclass 12, count 2 2006.210.08:22:08.96#ibcon#about to read 3, iclass 12, count 2 2006.210.08:22:08.99#ibcon#read 3, iclass 12, count 2 2006.210.08:22:08.99#ibcon#about to read 4, iclass 12, count 2 2006.210.08:22:08.99#ibcon#read 4, iclass 12, count 2 2006.210.08:22:08.99#ibcon#about to read 5, iclass 12, count 2 2006.210.08:22:08.99#ibcon#read 5, iclass 12, count 2 2006.210.08:22:08.99#ibcon#about to read 6, iclass 12, count 2 2006.210.08:22:08.99#ibcon#read 6, iclass 12, count 2 2006.210.08:22:08.99#ibcon#end of sib2, iclass 12, count 2 2006.210.08:22:08.99#ibcon#*after write, iclass 12, count 2 2006.210.08:22:08.99#ibcon#*before return 0, iclass 12, count 2 2006.210.08:22:08.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:08.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:08.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.08:22:08.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:08.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:09.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:09.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:09.11#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:22:09.11#ibcon#first serial, iclass 12, count 0 2006.210.08:22:09.11#ibcon#enter sib2, iclass 12, count 0 2006.210.08:22:09.11#ibcon#flushed, iclass 12, count 0 2006.210.08:22:09.11#ibcon#about to write, iclass 12, count 0 2006.210.08:22:09.11#ibcon#wrote, iclass 12, count 0 2006.210.08:22:09.11#ibcon#about to read 3, iclass 12, count 0 2006.210.08:22:09.13#ibcon#read 3, iclass 12, count 0 2006.210.08:22:09.13#ibcon#about to read 4, iclass 12, count 0 2006.210.08:22:09.13#ibcon#read 4, iclass 12, count 0 2006.210.08:22:09.13#ibcon#about to read 5, iclass 12, count 0 2006.210.08:22:09.13#ibcon#read 5, iclass 12, count 0 2006.210.08:22:09.13#ibcon#about to read 6, iclass 12, count 0 2006.210.08:22:09.13#ibcon#read 6, iclass 12, count 0 2006.210.08:22:09.13#ibcon#end of sib2, iclass 12, count 0 2006.210.08:22:09.13#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:22:09.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:22:09.13#ibcon#[25=USB\r\n] 2006.210.08:22:09.13#ibcon#*before write, iclass 12, count 0 2006.210.08:22:09.13#ibcon#enter sib2, iclass 12, count 0 2006.210.08:22:09.13#ibcon#flushed, iclass 12, count 0 2006.210.08:22:09.13#ibcon#about to write, iclass 12, count 0 2006.210.08:22:09.13#ibcon#wrote, iclass 12, count 0 2006.210.08:22:09.13#ibcon#about to read 3, iclass 12, count 0 2006.210.08:22:09.16#ibcon#read 3, iclass 12, count 0 2006.210.08:22:09.16#ibcon#about to read 4, iclass 12, count 0 2006.210.08:22:09.16#ibcon#read 4, iclass 12, count 0 2006.210.08:22:09.16#ibcon#about to read 5, iclass 12, count 0 2006.210.08:22:09.16#ibcon#read 5, iclass 12, count 0 2006.210.08:22:09.16#ibcon#about to read 6, iclass 12, count 0 2006.210.08:22:09.16#ibcon#read 6, iclass 12, count 0 2006.210.08:22:09.16#ibcon#end of sib2, iclass 12, count 0 2006.210.08:22:09.16#ibcon#*after write, iclass 12, count 0 2006.210.08:22:09.16#ibcon#*before return 0, iclass 12, count 0 2006.210.08:22:09.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:09.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:09.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:22:09.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:22:09.16$vc4f8/valo=6,772.99 2006.210.08:22:09.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.08:22:09.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.08:22:09.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:09.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:09.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:09.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:09.16#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:22:09.16#ibcon#first serial, iclass 14, count 0 2006.210.08:22:09.16#ibcon#enter sib2, iclass 14, count 0 2006.210.08:22:09.16#ibcon#flushed, iclass 14, count 0 2006.210.08:22:09.16#ibcon#about to write, iclass 14, count 0 2006.210.08:22:09.16#ibcon#wrote, iclass 14, count 0 2006.210.08:22:09.16#ibcon#about to read 3, iclass 14, count 0 2006.210.08:22:09.18#ibcon#read 3, iclass 14, count 0 2006.210.08:22:09.18#ibcon#about to read 4, iclass 14, count 0 2006.210.08:22:09.18#ibcon#read 4, iclass 14, count 0 2006.210.08:22:09.18#ibcon#about to read 5, iclass 14, count 0 2006.210.08:22:09.18#ibcon#read 5, iclass 14, count 0 2006.210.08:22:09.18#ibcon#about to read 6, iclass 14, count 0 2006.210.08:22:09.18#ibcon#read 6, iclass 14, count 0 2006.210.08:22:09.18#ibcon#end of sib2, iclass 14, count 0 2006.210.08:22:09.18#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:22:09.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:22:09.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:22:09.18#ibcon#*before write, iclass 14, count 0 2006.210.08:22:09.18#ibcon#enter sib2, iclass 14, count 0 2006.210.08:22:09.18#ibcon#flushed, iclass 14, count 0 2006.210.08:22:09.18#ibcon#about to write, iclass 14, count 0 2006.210.08:22:09.18#ibcon#wrote, iclass 14, count 0 2006.210.08:22:09.18#ibcon#about to read 3, iclass 14, count 0 2006.210.08:22:09.22#ibcon#read 3, iclass 14, count 0 2006.210.08:22:09.22#ibcon#about to read 4, iclass 14, count 0 2006.210.08:22:09.22#ibcon#read 4, iclass 14, count 0 2006.210.08:22:09.22#ibcon#about to read 5, iclass 14, count 0 2006.210.08:22:09.22#ibcon#read 5, iclass 14, count 0 2006.210.08:22:09.22#ibcon#about to read 6, iclass 14, count 0 2006.210.08:22:09.22#ibcon#read 6, iclass 14, count 0 2006.210.08:22:09.22#ibcon#end of sib2, iclass 14, count 0 2006.210.08:22:09.22#ibcon#*after write, iclass 14, count 0 2006.210.08:22:09.22#ibcon#*before return 0, iclass 14, count 0 2006.210.08:22:09.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:09.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:09.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:22:09.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:22:09.22$vc4f8/va=6,6 2006.210.08:22:09.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.210.08:22:09.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.210.08:22:09.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:09.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:22:09.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:22:09.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:22:09.28#ibcon#enter wrdev, iclass 16, count 2 2006.210.08:22:09.28#ibcon#first serial, iclass 16, count 2 2006.210.08:22:09.28#ibcon#enter sib2, iclass 16, count 2 2006.210.08:22:09.28#ibcon#flushed, iclass 16, count 2 2006.210.08:22:09.28#ibcon#about to write, iclass 16, count 2 2006.210.08:22:09.28#ibcon#wrote, iclass 16, count 2 2006.210.08:22:09.28#ibcon#about to read 3, iclass 16, count 2 2006.210.08:22:09.30#ibcon#read 3, iclass 16, count 2 2006.210.08:22:09.30#ibcon#about to read 4, iclass 16, count 2 2006.210.08:22:09.30#ibcon#read 4, iclass 16, count 2 2006.210.08:22:09.30#ibcon#about to read 5, iclass 16, count 2 2006.210.08:22:09.30#ibcon#read 5, iclass 16, count 2 2006.210.08:22:09.30#ibcon#about to read 6, iclass 16, count 2 2006.210.08:22:09.30#ibcon#read 6, iclass 16, count 2 2006.210.08:22:09.30#ibcon#end of sib2, iclass 16, count 2 2006.210.08:22:09.30#ibcon#*mode == 0, iclass 16, count 2 2006.210.08:22:09.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.210.08:22:09.30#ibcon#[25=AT06-06\r\n] 2006.210.08:22:09.30#ibcon#*before write, iclass 16, count 2 2006.210.08:22:09.30#ibcon#enter sib2, iclass 16, count 2 2006.210.08:22:09.30#ibcon#flushed, iclass 16, count 2 2006.210.08:22:09.30#ibcon#about to write, iclass 16, count 2 2006.210.08:22:09.30#ibcon#wrote, iclass 16, count 2 2006.210.08:22:09.30#ibcon#about to read 3, iclass 16, count 2 2006.210.08:22:09.33#ibcon#read 3, iclass 16, count 2 2006.210.08:22:09.33#ibcon#about to read 4, iclass 16, count 2 2006.210.08:22:09.33#ibcon#read 4, iclass 16, count 2 2006.210.08:22:09.33#ibcon#about to read 5, iclass 16, count 2 2006.210.08:22:09.33#ibcon#read 5, iclass 16, count 2 2006.210.08:22:09.33#ibcon#about to read 6, iclass 16, count 2 2006.210.08:22:09.33#ibcon#read 6, iclass 16, count 2 2006.210.08:22:09.33#ibcon#end of sib2, iclass 16, count 2 2006.210.08:22:09.33#ibcon#*after write, iclass 16, count 2 2006.210.08:22:09.33#ibcon#*before return 0, iclass 16, count 2 2006.210.08:22:09.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:22:09.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.210.08:22:09.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.210.08:22:09.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:09.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:22:09.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:22:09.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:22:09.45#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:22:09.45#ibcon#first serial, iclass 16, count 0 2006.210.08:22:09.45#ibcon#enter sib2, iclass 16, count 0 2006.210.08:22:09.45#ibcon#flushed, iclass 16, count 0 2006.210.08:22:09.45#ibcon#about to write, iclass 16, count 0 2006.210.08:22:09.45#ibcon#wrote, iclass 16, count 0 2006.210.08:22:09.45#ibcon#about to read 3, iclass 16, count 0 2006.210.08:22:09.47#ibcon#read 3, iclass 16, count 0 2006.210.08:22:09.47#ibcon#about to read 4, iclass 16, count 0 2006.210.08:22:09.47#ibcon#read 4, iclass 16, count 0 2006.210.08:22:09.47#ibcon#about to read 5, iclass 16, count 0 2006.210.08:22:09.47#ibcon#read 5, iclass 16, count 0 2006.210.08:22:09.47#ibcon#about to read 6, iclass 16, count 0 2006.210.08:22:09.47#ibcon#read 6, iclass 16, count 0 2006.210.08:22:09.47#ibcon#end of sib2, iclass 16, count 0 2006.210.08:22:09.47#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:22:09.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:22:09.47#ibcon#[25=USB\r\n] 2006.210.08:22:09.47#ibcon#*before write, iclass 16, count 0 2006.210.08:22:09.47#ibcon#enter sib2, iclass 16, count 0 2006.210.08:22:09.47#ibcon#flushed, iclass 16, count 0 2006.210.08:22:09.47#ibcon#about to write, iclass 16, count 0 2006.210.08:22:09.47#ibcon#wrote, iclass 16, count 0 2006.210.08:22:09.47#ibcon#about to read 3, iclass 16, count 0 2006.210.08:22:09.50#ibcon#read 3, iclass 16, count 0 2006.210.08:22:09.50#ibcon#about to read 4, iclass 16, count 0 2006.210.08:22:09.50#ibcon#read 4, iclass 16, count 0 2006.210.08:22:09.50#ibcon#about to read 5, iclass 16, count 0 2006.210.08:22:09.50#ibcon#read 5, iclass 16, count 0 2006.210.08:22:09.50#ibcon#about to read 6, iclass 16, count 0 2006.210.08:22:09.50#ibcon#read 6, iclass 16, count 0 2006.210.08:22:09.50#ibcon#end of sib2, iclass 16, count 0 2006.210.08:22:09.50#ibcon#*after write, iclass 16, count 0 2006.210.08:22:09.50#ibcon#*before return 0, iclass 16, count 0 2006.210.08:22:09.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:22:09.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.210.08:22:09.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:22:09.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:22:09.50$vc4f8/valo=7,832.99 2006.210.08:22:09.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.210.08:22:09.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.210.08:22:09.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:09.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:22:09.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:22:09.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:22:09.50#ibcon#enter wrdev, iclass 18, count 0 2006.210.08:22:09.50#ibcon#first serial, iclass 18, count 0 2006.210.08:22:09.50#ibcon#enter sib2, iclass 18, count 0 2006.210.08:22:09.50#ibcon#flushed, iclass 18, count 0 2006.210.08:22:09.50#ibcon#about to write, iclass 18, count 0 2006.210.08:22:09.50#ibcon#wrote, iclass 18, count 0 2006.210.08:22:09.50#ibcon#about to read 3, iclass 18, count 0 2006.210.08:22:09.52#ibcon#read 3, iclass 18, count 0 2006.210.08:22:09.52#ibcon#about to read 4, iclass 18, count 0 2006.210.08:22:09.52#ibcon#read 4, iclass 18, count 0 2006.210.08:22:09.52#ibcon#about to read 5, iclass 18, count 0 2006.210.08:22:09.52#ibcon#read 5, iclass 18, count 0 2006.210.08:22:09.52#ibcon#about to read 6, iclass 18, count 0 2006.210.08:22:09.52#ibcon#read 6, iclass 18, count 0 2006.210.08:22:09.52#ibcon#end of sib2, iclass 18, count 0 2006.210.08:22:09.52#ibcon#*mode == 0, iclass 18, count 0 2006.210.08:22:09.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.210.08:22:09.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:22:09.52#ibcon#*before write, iclass 18, count 0 2006.210.08:22:09.52#ibcon#enter sib2, iclass 18, count 0 2006.210.08:22:09.52#ibcon#flushed, iclass 18, count 0 2006.210.08:22:09.52#ibcon#about to write, iclass 18, count 0 2006.210.08:22:09.52#ibcon#wrote, iclass 18, count 0 2006.210.08:22:09.52#ibcon#about to read 3, iclass 18, count 0 2006.210.08:22:09.56#ibcon#read 3, iclass 18, count 0 2006.210.08:22:09.56#ibcon#about to read 4, iclass 18, count 0 2006.210.08:22:09.56#ibcon#read 4, iclass 18, count 0 2006.210.08:22:09.56#ibcon#about to read 5, iclass 18, count 0 2006.210.08:22:09.56#ibcon#read 5, iclass 18, count 0 2006.210.08:22:09.56#ibcon#about to read 6, iclass 18, count 0 2006.210.08:22:09.56#ibcon#read 6, iclass 18, count 0 2006.210.08:22:09.56#ibcon#end of sib2, iclass 18, count 0 2006.210.08:22:09.56#ibcon#*after write, iclass 18, count 0 2006.210.08:22:09.56#ibcon#*before return 0, iclass 18, count 0 2006.210.08:22:09.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:22:09.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.210.08:22:09.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.210.08:22:09.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.210.08:22:09.56$vc4f8/va=7,6 2006.210.08:22:09.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.210.08:22:09.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.210.08:22:09.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:09.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:22:09.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:22:09.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:22:09.62#ibcon#enter wrdev, iclass 20, count 2 2006.210.08:22:09.62#ibcon#first serial, iclass 20, count 2 2006.210.08:22:09.62#ibcon#enter sib2, iclass 20, count 2 2006.210.08:22:09.62#ibcon#flushed, iclass 20, count 2 2006.210.08:22:09.62#ibcon#about to write, iclass 20, count 2 2006.210.08:22:09.62#ibcon#wrote, iclass 20, count 2 2006.210.08:22:09.62#ibcon#about to read 3, iclass 20, count 2 2006.210.08:22:09.64#ibcon#read 3, iclass 20, count 2 2006.210.08:22:09.64#ibcon#about to read 4, iclass 20, count 2 2006.210.08:22:09.64#ibcon#read 4, iclass 20, count 2 2006.210.08:22:09.64#ibcon#about to read 5, iclass 20, count 2 2006.210.08:22:09.64#ibcon#read 5, iclass 20, count 2 2006.210.08:22:09.64#ibcon#about to read 6, iclass 20, count 2 2006.210.08:22:09.64#ibcon#read 6, iclass 20, count 2 2006.210.08:22:09.64#ibcon#end of sib2, iclass 20, count 2 2006.210.08:22:09.64#ibcon#*mode == 0, iclass 20, count 2 2006.210.08:22:09.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.210.08:22:09.64#ibcon#[25=AT07-06\r\n] 2006.210.08:22:09.64#ibcon#*before write, iclass 20, count 2 2006.210.08:22:09.64#ibcon#enter sib2, iclass 20, count 2 2006.210.08:22:09.64#ibcon#flushed, iclass 20, count 2 2006.210.08:22:09.64#ibcon#about to write, iclass 20, count 2 2006.210.08:22:09.64#ibcon#wrote, iclass 20, count 2 2006.210.08:22:09.64#ibcon#about to read 3, iclass 20, count 2 2006.210.08:22:09.67#ibcon#read 3, iclass 20, count 2 2006.210.08:22:09.67#ibcon#about to read 4, iclass 20, count 2 2006.210.08:22:09.67#ibcon#read 4, iclass 20, count 2 2006.210.08:22:09.67#ibcon#about to read 5, iclass 20, count 2 2006.210.08:22:09.67#ibcon#read 5, iclass 20, count 2 2006.210.08:22:09.67#ibcon#about to read 6, iclass 20, count 2 2006.210.08:22:09.67#ibcon#read 6, iclass 20, count 2 2006.210.08:22:09.67#ibcon#end of sib2, iclass 20, count 2 2006.210.08:22:09.67#ibcon#*after write, iclass 20, count 2 2006.210.08:22:09.67#ibcon#*before return 0, iclass 20, count 2 2006.210.08:22:09.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:22:09.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.210.08:22:09.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.210.08:22:09.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:09.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:22:09.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:22:09.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:22:09.79#ibcon#enter wrdev, iclass 20, count 0 2006.210.08:22:09.79#ibcon#first serial, iclass 20, count 0 2006.210.08:22:09.79#ibcon#enter sib2, iclass 20, count 0 2006.210.08:22:09.79#ibcon#flushed, iclass 20, count 0 2006.210.08:22:09.79#ibcon#about to write, iclass 20, count 0 2006.210.08:22:09.79#ibcon#wrote, iclass 20, count 0 2006.210.08:22:09.79#ibcon#about to read 3, iclass 20, count 0 2006.210.08:22:09.81#ibcon#read 3, iclass 20, count 0 2006.210.08:22:09.81#ibcon#about to read 4, iclass 20, count 0 2006.210.08:22:09.81#ibcon#read 4, iclass 20, count 0 2006.210.08:22:09.81#ibcon#about to read 5, iclass 20, count 0 2006.210.08:22:09.81#ibcon#read 5, iclass 20, count 0 2006.210.08:22:09.81#ibcon#about to read 6, iclass 20, count 0 2006.210.08:22:09.81#ibcon#read 6, iclass 20, count 0 2006.210.08:22:09.81#ibcon#end of sib2, iclass 20, count 0 2006.210.08:22:09.81#ibcon#*mode == 0, iclass 20, count 0 2006.210.08:22:09.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.210.08:22:09.81#ibcon#[25=USB\r\n] 2006.210.08:22:09.81#ibcon#*before write, iclass 20, count 0 2006.210.08:22:09.81#ibcon#enter sib2, iclass 20, count 0 2006.210.08:22:09.81#ibcon#flushed, iclass 20, count 0 2006.210.08:22:09.81#ibcon#about to write, iclass 20, count 0 2006.210.08:22:09.81#ibcon#wrote, iclass 20, count 0 2006.210.08:22:09.81#ibcon#about to read 3, iclass 20, count 0 2006.210.08:22:09.84#ibcon#read 3, iclass 20, count 0 2006.210.08:22:09.84#ibcon#about to read 4, iclass 20, count 0 2006.210.08:22:09.84#ibcon#read 4, iclass 20, count 0 2006.210.08:22:09.84#ibcon#about to read 5, iclass 20, count 0 2006.210.08:22:09.84#ibcon#read 5, iclass 20, count 0 2006.210.08:22:09.84#ibcon#about to read 6, iclass 20, count 0 2006.210.08:22:09.84#ibcon#read 6, iclass 20, count 0 2006.210.08:22:09.84#ibcon#end of sib2, iclass 20, count 0 2006.210.08:22:09.84#ibcon#*after write, iclass 20, count 0 2006.210.08:22:09.84#ibcon#*before return 0, iclass 20, count 0 2006.210.08:22:09.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:22:09.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.210.08:22:09.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.210.08:22:09.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.210.08:22:09.84$vc4f8/valo=8,852.99 2006.210.08:22:09.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.210.08:22:09.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.210.08:22:09.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:09.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:22:09.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:22:09.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:22:09.84#ibcon#enter wrdev, iclass 22, count 0 2006.210.08:22:09.84#ibcon#first serial, iclass 22, count 0 2006.210.08:22:09.84#ibcon#enter sib2, iclass 22, count 0 2006.210.08:22:09.84#ibcon#flushed, iclass 22, count 0 2006.210.08:22:09.84#ibcon#about to write, iclass 22, count 0 2006.210.08:22:09.84#ibcon#wrote, iclass 22, count 0 2006.210.08:22:09.84#ibcon#about to read 3, iclass 22, count 0 2006.210.08:22:09.86#ibcon#read 3, iclass 22, count 0 2006.210.08:22:09.86#ibcon#about to read 4, iclass 22, count 0 2006.210.08:22:09.86#ibcon#read 4, iclass 22, count 0 2006.210.08:22:09.86#ibcon#about to read 5, iclass 22, count 0 2006.210.08:22:09.86#ibcon#read 5, iclass 22, count 0 2006.210.08:22:09.86#ibcon#about to read 6, iclass 22, count 0 2006.210.08:22:09.86#ibcon#read 6, iclass 22, count 0 2006.210.08:22:09.86#ibcon#end of sib2, iclass 22, count 0 2006.210.08:22:09.86#ibcon#*mode == 0, iclass 22, count 0 2006.210.08:22:09.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.210.08:22:09.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:22:09.86#ibcon#*before write, iclass 22, count 0 2006.210.08:22:09.86#ibcon#enter sib2, iclass 22, count 0 2006.210.08:22:09.86#ibcon#flushed, iclass 22, count 0 2006.210.08:22:09.86#ibcon#about to write, iclass 22, count 0 2006.210.08:22:09.86#ibcon#wrote, iclass 22, count 0 2006.210.08:22:09.86#ibcon#about to read 3, iclass 22, count 0 2006.210.08:22:09.90#ibcon#read 3, iclass 22, count 0 2006.210.08:22:09.90#ibcon#about to read 4, iclass 22, count 0 2006.210.08:22:09.90#ibcon#read 4, iclass 22, count 0 2006.210.08:22:09.90#ibcon#about to read 5, iclass 22, count 0 2006.210.08:22:09.90#ibcon#read 5, iclass 22, count 0 2006.210.08:22:09.90#ibcon#about to read 6, iclass 22, count 0 2006.210.08:22:09.90#ibcon#read 6, iclass 22, count 0 2006.210.08:22:09.90#ibcon#end of sib2, iclass 22, count 0 2006.210.08:22:09.90#ibcon#*after write, iclass 22, count 0 2006.210.08:22:09.90#ibcon#*before return 0, iclass 22, count 0 2006.210.08:22:09.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:22:09.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.210.08:22:09.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.210.08:22:09.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.210.08:22:09.90$vc4f8/va=8,7 2006.210.08:22:09.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.210.08:22:09.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.210.08:22:09.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:09.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:22:09.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:22:09.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:22:09.96#ibcon#enter wrdev, iclass 24, count 2 2006.210.08:22:09.96#ibcon#first serial, iclass 24, count 2 2006.210.08:22:09.96#ibcon#enter sib2, iclass 24, count 2 2006.210.08:22:09.96#ibcon#flushed, iclass 24, count 2 2006.210.08:22:09.96#ibcon#about to write, iclass 24, count 2 2006.210.08:22:09.96#ibcon#wrote, iclass 24, count 2 2006.210.08:22:09.96#ibcon#about to read 3, iclass 24, count 2 2006.210.08:22:09.98#ibcon#read 3, iclass 24, count 2 2006.210.08:22:09.98#ibcon#about to read 4, iclass 24, count 2 2006.210.08:22:09.98#ibcon#read 4, iclass 24, count 2 2006.210.08:22:09.98#ibcon#about to read 5, iclass 24, count 2 2006.210.08:22:09.98#ibcon#read 5, iclass 24, count 2 2006.210.08:22:09.98#ibcon#about to read 6, iclass 24, count 2 2006.210.08:22:09.98#ibcon#read 6, iclass 24, count 2 2006.210.08:22:09.98#ibcon#end of sib2, iclass 24, count 2 2006.210.08:22:09.98#ibcon#*mode == 0, iclass 24, count 2 2006.210.08:22:09.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.210.08:22:09.98#ibcon#[25=AT08-07\r\n] 2006.210.08:22:09.98#ibcon#*before write, iclass 24, count 2 2006.210.08:22:09.98#ibcon#enter sib2, iclass 24, count 2 2006.210.08:22:09.98#ibcon#flushed, iclass 24, count 2 2006.210.08:22:09.98#ibcon#about to write, iclass 24, count 2 2006.210.08:22:09.98#ibcon#wrote, iclass 24, count 2 2006.210.08:22:09.98#ibcon#about to read 3, iclass 24, count 2 2006.210.08:22:10.01#ibcon#read 3, iclass 24, count 2 2006.210.08:22:10.01#ibcon#about to read 4, iclass 24, count 2 2006.210.08:22:10.01#ibcon#read 4, iclass 24, count 2 2006.210.08:22:10.01#ibcon#about to read 5, iclass 24, count 2 2006.210.08:22:10.01#ibcon#read 5, iclass 24, count 2 2006.210.08:22:10.01#ibcon#about to read 6, iclass 24, count 2 2006.210.08:22:10.01#ibcon#read 6, iclass 24, count 2 2006.210.08:22:10.01#ibcon#end of sib2, iclass 24, count 2 2006.210.08:22:10.01#ibcon#*after write, iclass 24, count 2 2006.210.08:22:10.01#ibcon#*before return 0, iclass 24, count 2 2006.210.08:22:10.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:22:10.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.210.08:22:10.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.210.08:22:10.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:10.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:22:10.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:22:10.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:22:10.13#ibcon#enter wrdev, iclass 24, count 0 2006.210.08:22:10.13#ibcon#first serial, iclass 24, count 0 2006.210.08:22:10.13#ibcon#enter sib2, iclass 24, count 0 2006.210.08:22:10.13#ibcon#flushed, iclass 24, count 0 2006.210.08:22:10.13#ibcon#about to write, iclass 24, count 0 2006.210.08:22:10.13#ibcon#wrote, iclass 24, count 0 2006.210.08:22:10.13#ibcon#about to read 3, iclass 24, count 0 2006.210.08:22:10.15#ibcon#read 3, iclass 24, count 0 2006.210.08:22:10.15#ibcon#about to read 4, iclass 24, count 0 2006.210.08:22:10.15#ibcon#read 4, iclass 24, count 0 2006.210.08:22:10.15#ibcon#about to read 5, iclass 24, count 0 2006.210.08:22:10.15#ibcon#read 5, iclass 24, count 0 2006.210.08:22:10.15#ibcon#about to read 6, iclass 24, count 0 2006.210.08:22:10.15#ibcon#read 6, iclass 24, count 0 2006.210.08:22:10.15#ibcon#end of sib2, iclass 24, count 0 2006.210.08:22:10.15#ibcon#*mode == 0, iclass 24, count 0 2006.210.08:22:10.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.210.08:22:10.15#ibcon#[25=USB\r\n] 2006.210.08:22:10.15#ibcon#*before write, iclass 24, count 0 2006.210.08:22:10.15#ibcon#enter sib2, iclass 24, count 0 2006.210.08:22:10.15#ibcon#flushed, iclass 24, count 0 2006.210.08:22:10.15#ibcon#about to write, iclass 24, count 0 2006.210.08:22:10.15#ibcon#wrote, iclass 24, count 0 2006.210.08:22:10.15#ibcon#about to read 3, iclass 24, count 0 2006.210.08:22:10.18#ibcon#read 3, iclass 24, count 0 2006.210.08:22:10.18#ibcon#about to read 4, iclass 24, count 0 2006.210.08:22:10.18#ibcon#read 4, iclass 24, count 0 2006.210.08:22:10.18#ibcon#about to read 5, iclass 24, count 0 2006.210.08:22:10.18#ibcon#read 5, iclass 24, count 0 2006.210.08:22:10.18#ibcon#about to read 6, iclass 24, count 0 2006.210.08:22:10.18#ibcon#read 6, iclass 24, count 0 2006.210.08:22:10.18#ibcon#end of sib2, iclass 24, count 0 2006.210.08:22:10.18#ibcon#*after write, iclass 24, count 0 2006.210.08:22:10.18#ibcon#*before return 0, iclass 24, count 0 2006.210.08:22:10.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:22:10.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.210.08:22:10.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.210.08:22:10.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.210.08:22:10.18$vc4f8/vblo=1,632.99 2006.210.08:22:10.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.210.08:22:10.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.210.08:22:10.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:10.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:22:10.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:22:10.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:22:10.18#ibcon#enter wrdev, iclass 26, count 0 2006.210.08:22:10.18#ibcon#first serial, iclass 26, count 0 2006.210.08:22:10.18#ibcon#enter sib2, iclass 26, count 0 2006.210.08:22:10.18#ibcon#flushed, iclass 26, count 0 2006.210.08:22:10.18#ibcon#about to write, iclass 26, count 0 2006.210.08:22:10.18#ibcon#wrote, iclass 26, count 0 2006.210.08:22:10.18#ibcon#about to read 3, iclass 26, count 0 2006.210.08:22:10.20#ibcon#read 3, iclass 26, count 0 2006.210.08:22:10.20#ibcon#about to read 4, iclass 26, count 0 2006.210.08:22:10.20#ibcon#read 4, iclass 26, count 0 2006.210.08:22:10.20#ibcon#about to read 5, iclass 26, count 0 2006.210.08:22:10.20#ibcon#read 5, iclass 26, count 0 2006.210.08:22:10.20#ibcon#about to read 6, iclass 26, count 0 2006.210.08:22:10.20#ibcon#read 6, iclass 26, count 0 2006.210.08:22:10.20#ibcon#end of sib2, iclass 26, count 0 2006.210.08:22:10.20#ibcon#*mode == 0, iclass 26, count 0 2006.210.08:22:10.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.210.08:22:10.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:22:10.20#ibcon#*before write, iclass 26, count 0 2006.210.08:22:10.20#ibcon#enter sib2, iclass 26, count 0 2006.210.08:22:10.20#ibcon#flushed, iclass 26, count 0 2006.210.08:22:10.20#ibcon#about to write, iclass 26, count 0 2006.210.08:22:10.20#ibcon#wrote, iclass 26, count 0 2006.210.08:22:10.20#ibcon#about to read 3, iclass 26, count 0 2006.210.08:22:10.24#ibcon#read 3, iclass 26, count 0 2006.210.08:22:10.24#ibcon#about to read 4, iclass 26, count 0 2006.210.08:22:10.24#ibcon#read 4, iclass 26, count 0 2006.210.08:22:10.24#ibcon#about to read 5, iclass 26, count 0 2006.210.08:22:10.24#ibcon#read 5, iclass 26, count 0 2006.210.08:22:10.24#ibcon#about to read 6, iclass 26, count 0 2006.210.08:22:10.24#ibcon#read 6, iclass 26, count 0 2006.210.08:22:10.24#ibcon#end of sib2, iclass 26, count 0 2006.210.08:22:10.24#ibcon#*after write, iclass 26, count 0 2006.210.08:22:10.24#ibcon#*before return 0, iclass 26, count 0 2006.210.08:22:10.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:22:10.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.210.08:22:10.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.210.08:22:10.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.210.08:22:10.24$vc4f8/vb=1,4 2006.210.08:22:10.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.210.08:22:10.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.210.08:22:10.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:10.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:22:10.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:22:10.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:22:10.24#ibcon#enter wrdev, iclass 28, count 2 2006.210.08:22:10.24#ibcon#first serial, iclass 28, count 2 2006.210.08:22:10.24#ibcon#enter sib2, iclass 28, count 2 2006.210.08:22:10.24#ibcon#flushed, iclass 28, count 2 2006.210.08:22:10.24#ibcon#about to write, iclass 28, count 2 2006.210.08:22:10.24#ibcon#wrote, iclass 28, count 2 2006.210.08:22:10.24#ibcon#about to read 3, iclass 28, count 2 2006.210.08:22:10.26#ibcon#read 3, iclass 28, count 2 2006.210.08:22:10.26#ibcon#about to read 4, iclass 28, count 2 2006.210.08:22:10.26#ibcon#read 4, iclass 28, count 2 2006.210.08:22:10.26#ibcon#about to read 5, iclass 28, count 2 2006.210.08:22:10.26#ibcon#read 5, iclass 28, count 2 2006.210.08:22:10.26#ibcon#about to read 6, iclass 28, count 2 2006.210.08:22:10.26#ibcon#read 6, iclass 28, count 2 2006.210.08:22:10.26#ibcon#end of sib2, iclass 28, count 2 2006.210.08:22:10.26#ibcon#*mode == 0, iclass 28, count 2 2006.210.08:22:10.26#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.210.08:22:10.26#ibcon#[27=AT01-04\r\n] 2006.210.08:22:10.26#ibcon#*before write, iclass 28, count 2 2006.210.08:22:10.26#ibcon#enter sib2, iclass 28, count 2 2006.210.08:22:10.26#ibcon#flushed, iclass 28, count 2 2006.210.08:22:10.26#ibcon#about to write, iclass 28, count 2 2006.210.08:22:10.26#ibcon#wrote, iclass 28, count 2 2006.210.08:22:10.26#ibcon#about to read 3, iclass 28, count 2 2006.210.08:22:10.29#ibcon#read 3, iclass 28, count 2 2006.210.08:22:10.29#ibcon#about to read 4, iclass 28, count 2 2006.210.08:22:10.29#ibcon#read 4, iclass 28, count 2 2006.210.08:22:10.29#ibcon#about to read 5, iclass 28, count 2 2006.210.08:22:10.29#ibcon#read 5, iclass 28, count 2 2006.210.08:22:10.29#ibcon#about to read 6, iclass 28, count 2 2006.210.08:22:10.29#ibcon#read 6, iclass 28, count 2 2006.210.08:22:10.29#ibcon#end of sib2, iclass 28, count 2 2006.210.08:22:10.29#ibcon#*after write, iclass 28, count 2 2006.210.08:22:10.29#ibcon#*before return 0, iclass 28, count 2 2006.210.08:22:10.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:22:10.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.210.08:22:10.29#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.210.08:22:10.29#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:10.29#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:22:10.41#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:22:10.41#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:22:10.41#ibcon#enter wrdev, iclass 28, count 0 2006.210.08:22:10.41#ibcon#first serial, iclass 28, count 0 2006.210.08:22:10.41#ibcon#enter sib2, iclass 28, count 0 2006.210.08:22:10.41#ibcon#flushed, iclass 28, count 0 2006.210.08:22:10.41#ibcon#about to write, iclass 28, count 0 2006.210.08:22:10.41#ibcon#wrote, iclass 28, count 0 2006.210.08:22:10.41#ibcon#about to read 3, iclass 28, count 0 2006.210.08:22:10.43#ibcon#read 3, iclass 28, count 0 2006.210.08:22:10.43#ibcon#about to read 4, iclass 28, count 0 2006.210.08:22:10.43#ibcon#read 4, iclass 28, count 0 2006.210.08:22:10.43#ibcon#about to read 5, iclass 28, count 0 2006.210.08:22:10.43#ibcon#read 5, iclass 28, count 0 2006.210.08:22:10.43#ibcon#about to read 6, iclass 28, count 0 2006.210.08:22:10.43#ibcon#read 6, iclass 28, count 0 2006.210.08:22:10.43#ibcon#end of sib2, iclass 28, count 0 2006.210.08:22:10.43#ibcon#*mode == 0, iclass 28, count 0 2006.210.08:22:10.43#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.210.08:22:10.43#ibcon#[27=USB\r\n] 2006.210.08:22:10.43#ibcon#*before write, iclass 28, count 0 2006.210.08:22:10.43#ibcon#enter sib2, iclass 28, count 0 2006.210.08:22:10.43#ibcon#flushed, iclass 28, count 0 2006.210.08:22:10.43#ibcon#about to write, iclass 28, count 0 2006.210.08:22:10.43#ibcon#wrote, iclass 28, count 0 2006.210.08:22:10.43#ibcon#about to read 3, iclass 28, count 0 2006.210.08:22:10.46#ibcon#read 3, iclass 28, count 0 2006.210.08:22:10.46#ibcon#about to read 4, iclass 28, count 0 2006.210.08:22:10.46#ibcon#read 4, iclass 28, count 0 2006.210.08:22:10.46#ibcon#about to read 5, iclass 28, count 0 2006.210.08:22:10.46#ibcon#read 5, iclass 28, count 0 2006.210.08:22:10.46#ibcon#about to read 6, iclass 28, count 0 2006.210.08:22:10.46#ibcon#read 6, iclass 28, count 0 2006.210.08:22:10.46#ibcon#end of sib2, iclass 28, count 0 2006.210.08:22:10.46#ibcon#*after write, iclass 28, count 0 2006.210.08:22:10.46#ibcon#*before return 0, iclass 28, count 0 2006.210.08:22:10.46#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:22:10.46#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.210.08:22:10.46#ibcon#about to clear, iclass 28 cls_cnt 0 2006.210.08:22:10.46#ibcon#cleared, iclass 28 cls_cnt 0 2006.210.08:22:10.46$vc4f8/vblo=2,640.99 2006.210.08:22:10.46#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.210.08:22:10.46#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.210.08:22:10.46#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:10.46#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:10.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:10.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:10.46#ibcon#enter wrdev, iclass 30, count 0 2006.210.08:22:10.46#ibcon#first serial, iclass 30, count 0 2006.210.08:22:10.46#ibcon#enter sib2, iclass 30, count 0 2006.210.08:22:10.46#ibcon#flushed, iclass 30, count 0 2006.210.08:22:10.46#ibcon#about to write, iclass 30, count 0 2006.210.08:22:10.46#ibcon#wrote, iclass 30, count 0 2006.210.08:22:10.46#ibcon#about to read 3, iclass 30, count 0 2006.210.08:22:10.48#ibcon#read 3, iclass 30, count 0 2006.210.08:22:10.48#ibcon#about to read 4, iclass 30, count 0 2006.210.08:22:10.48#ibcon#read 4, iclass 30, count 0 2006.210.08:22:10.48#ibcon#about to read 5, iclass 30, count 0 2006.210.08:22:10.48#ibcon#read 5, iclass 30, count 0 2006.210.08:22:10.48#ibcon#about to read 6, iclass 30, count 0 2006.210.08:22:10.48#ibcon#read 6, iclass 30, count 0 2006.210.08:22:10.48#ibcon#end of sib2, iclass 30, count 0 2006.210.08:22:10.48#ibcon#*mode == 0, iclass 30, count 0 2006.210.08:22:10.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.210.08:22:10.48#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:22:10.48#ibcon#*before write, iclass 30, count 0 2006.210.08:22:10.48#ibcon#enter sib2, iclass 30, count 0 2006.210.08:22:10.48#ibcon#flushed, iclass 30, count 0 2006.210.08:22:10.48#ibcon#about to write, iclass 30, count 0 2006.210.08:22:10.48#ibcon#wrote, iclass 30, count 0 2006.210.08:22:10.48#ibcon#about to read 3, iclass 30, count 0 2006.210.08:22:10.52#ibcon#read 3, iclass 30, count 0 2006.210.08:22:10.52#ibcon#about to read 4, iclass 30, count 0 2006.210.08:22:10.52#ibcon#read 4, iclass 30, count 0 2006.210.08:22:10.52#ibcon#about to read 5, iclass 30, count 0 2006.210.08:22:10.52#ibcon#read 5, iclass 30, count 0 2006.210.08:22:10.52#ibcon#about to read 6, iclass 30, count 0 2006.210.08:22:10.52#ibcon#read 6, iclass 30, count 0 2006.210.08:22:10.52#ibcon#end of sib2, iclass 30, count 0 2006.210.08:22:10.52#ibcon#*after write, iclass 30, count 0 2006.210.08:22:10.52#ibcon#*before return 0, iclass 30, count 0 2006.210.08:22:10.52#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:10.52#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.210.08:22:10.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.210.08:22:10.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.210.08:22:10.52$vc4f8/vb=2,4 2006.210.08:22:10.52#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.210.08:22:10.52#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.210.08:22:10.52#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:10.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:10.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:10.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:10.58#ibcon#enter wrdev, iclass 32, count 2 2006.210.08:22:10.58#ibcon#first serial, iclass 32, count 2 2006.210.08:22:10.58#ibcon#enter sib2, iclass 32, count 2 2006.210.08:22:10.58#ibcon#flushed, iclass 32, count 2 2006.210.08:22:10.58#ibcon#about to write, iclass 32, count 2 2006.210.08:22:10.58#ibcon#wrote, iclass 32, count 2 2006.210.08:22:10.58#ibcon#about to read 3, iclass 32, count 2 2006.210.08:22:10.60#ibcon#read 3, iclass 32, count 2 2006.210.08:22:10.60#ibcon#about to read 4, iclass 32, count 2 2006.210.08:22:10.60#ibcon#read 4, iclass 32, count 2 2006.210.08:22:10.60#ibcon#about to read 5, iclass 32, count 2 2006.210.08:22:10.60#ibcon#read 5, iclass 32, count 2 2006.210.08:22:10.60#ibcon#about to read 6, iclass 32, count 2 2006.210.08:22:10.60#ibcon#read 6, iclass 32, count 2 2006.210.08:22:10.60#ibcon#end of sib2, iclass 32, count 2 2006.210.08:22:10.60#ibcon#*mode == 0, iclass 32, count 2 2006.210.08:22:10.60#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.210.08:22:10.60#ibcon#[27=AT02-04\r\n] 2006.210.08:22:10.60#ibcon#*before write, iclass 32, count 2 2006.210.08:22:10.60#ibcon#enter sib2, iclass 32, count 2 2006.210.08:22:10.60#ibcon#flushed, iclass 32, count 2 2006.210.08:22:10.60#ibcon#about to write, iclass 32, count 2 2006.210.08:22:10.60#ibcon#wrote, iclass 32, count 2 2006.210.08:22:10.60#ibcon#about to read 3, iclass 32, count 2 2006.210.08:22:10.63#ibcon#read 3, iclass 32, count 2 2006.210.08:22:10.63#ibcon#about to read 4, iclass 32, count 2 2006.210.08:22:10.63#ibcon#read 4, iclass 32, count 2 2006.210.08:22:10.63#ibcon#about to read 5, iclass 32, count 2 2006.210.08:22:10.63#ibcon#read 5, iclass 32, count 2 2006.210.08:22:10.63#ibcon#about to read 6, iclass 32, count 2 2006.210.08:22:10.63#ibcon#read 6, iclass 32, count 2 2006.210.08:22:10.63#ibcon#end of sib2, iclass 32, count 2 2006.210.08:22:10.63#ibcon#*after write, iclass 32, count 2 2006.210.08:22:10.63#ibcon#*before return 0, iclass 32, count 2 2006.210.08:22:10.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:10.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.210.08:22:10.63#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.210.08:22:10.63#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:10.63#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:10.75#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:10.75#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:10.75#ibcon#enter wrdev, iclass 32, count 0 2006.210.08:22:10.75#ibcon#first serial, iclass 32, count 0 2006.210.08:22:10.75#ibcon#enter sib2, iclass 32, count 0 2006.210.08:22:10.75#ibcon#flushed, iclass 32, count 0 2006.210.08:22:10.75#ibcon#about to write, iclass 32, count 0 2006.210.08:22:10.75#ibcon#wrote, iclass 32, count 0 2006.210.08:22:10.75#ibcon#about to read 3, iclass 32, count 0 2006.210.08:22:10.77#ibcon#read 3, iclass 32, count 0 2006.210.08:22:10.77#ibcon#about to read 4, iclass 32, count 0 2006.210.08:22:10.77#ibcon#read 4, iclass 32, count 0 2006.210.08:22:10.77#ibcon#about to read 5, iclass 32, count 0 2006.210.08:22:10.77#ibcon#read 5, iclass 32, count 0 2006.210.08:22:10.77#ibcon#about to read 6, iclass 32, count 0 2006.210.08:22:10.77#ibcon#read 6, iclass 32, count 0 2006.210.08:22:10.77#ibcon#end of sib2, iclass 32, count 0 2006.210.08:22:10.77#ibcon#*mode == 0, iclass 32, count 0 2006.210.08:22:10.77#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.210.08:22:10.77#ibcon#[27=USB\r\n] 2006.210.08:22:10.77#ibcon#*before write, iclass 32, count 0 2006.210.08:22:10.77#ibcon#enter sib2, iclass 32, count 0 2006.210.08:22:10.77#ibcon#flushed, iclass 32, count 0 2006.210.08:22:10.77#ibcon#about to write, iclass 32, count 0 2006.210.08:22:10.77#ibcon#wrote, iclass 32, count 0 2006.210.08:22:10.77#ibcon#about to read 3, iclass 32, count 0 2006.210.08:22:10.80#ibcon#read 3, iclass 32, count 0 2006.210.08:22:10.80#ibcon#about to read 4, iclass 32, count 0 2006.210.08:22:10.80#ibcon#read 4, iclass 32, count 0 2006.210.08:22:10.80#ibcon#about to read 5, iclass 32, count 0 2006.210.08:22:10.80#ibcon#read 5, iclass 32, count 0 2006.210.08:22:10.80#ibcon#about to read 6, iclass 32, count 0 2006.210.08:22:10.80#ibcon#read 6, iclass 32, count 0 2006.210.08:22:10.80#ibcon#end of sib2, iclass 32, count 0 2006.210.08:22:10.80#ibcon#*after write, iclass 32, count 0 2006.210.08:22:10.80#ibcon#*before return 0, iclass 32, count 0 2006.210.08:22:10.80#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:10.80#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.210.08:22:10.80#ibcon#about to clear, iclass 32 cls_cnt 0 2006.210.08:22:10.80#ibcon#cleared, iclass 32 cls_cnt 0 2006.210.08:22:10.80$vc4f8/vblo=3,656.99 2006.210.08:22:10.80#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.210.08:22:10.80#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.210.08:22:10.80#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:10.80#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:10.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:10.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:10.80#ibcon#enter wrdev, iclass 34, count 0 2006.210.08:22:10.80#ibcon#first serial, iclass 34, count 0 2006.210.08:22:10.80#ibcon#enter sib2, iclass 34, count 0 2006.210.08:22:10.80#ibcon#flushed, iclass 34, count 0 2006.210.08:22:10.80#ibcon#about to write, iclass 34, count 0 2006.210.08:22:10.80#ibcon#wrote, iclass 34, count 0 2006.210.08:22:10.80#ibcon#about to read 3, iclass 34, count 0 2006.210.08:22:10.82#ibcon#read 3, iclass 34, count 0 2006.210.08:22:10.82#ibcon#about to read 4, iclass 34, count 0 2006.210.08:22:10.82#ibcon#read 4, iclass 34, count 0 2006.210.08:22:10.82#ibcon#about to read 5, iclass 34, count 0 2006.210.08:22:10.82#ibcon#read 5, iclass 34, count 0 2006.210.08:22:10.82#ibcon#about to read 6, iclass 34, count 0 2006.210.08:22:10.82#ibcon#read 6, iclass 34, count 0 2006.210.08:22:10.82#ibcon#end of sib2, iclass 34, count 0 2006.210.08:22:10.82#ibcon#*mode == 0, iclass 34, count 0 2006.210.08:22:10.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.210.08:22:10.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:22:10.82#ibcon#*before write, iclass 34, count 0 2006.210.08:22:10.82#ibcon#enter sib2, iclass 34, count 0 2006.210.08:22:10.82#ibcon#flushed, iclass 34, count 0 2006.210.08:22:10.82#ibcon#about to write, iclass 34, count 0 2006.210.08:22:10.82#ibcon#wrote, iclass 34, count 0 2006.210.08:22:10.82#ibcon#about to read 3, iclass 34, count 0 2006.210.08:22:10.86#ibcon#read 3, iclass 34, count 0 2006.210.08:22:10.86#ibcon#about to read 4, iclass 34, count 0 2006.210.08:22:10.86#ibcon#read 4, iclass 34, count 0 2006.210.08:22:10.86#ibcon#about to read 5, iclass 34, count 0 2006.210.08:22:10.86#ibcon#read 5, iclass 34, count 0 2006.210.08:22:10.86#ibcon#about to read 6, iclass 34, count 0 2006.210.08:22:10.86#ibcon#read 6, iclass 34, count 0 2006.210.08:22:10.86#ibcon#end of sib2, iclass 34, count 0 2006.210.08:22:10.86#ibcon#*after write, iclass 34, count 0 2006.210.08:22:10.86#ibcon#*before return 0, iclass 34, count 0 2006.210.08:22:10.86#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:10.86#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.210.08:22:10.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.210.08:22:10.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.210.08:22:10.86$vc4f8/vb=3,3 2006.210.08:22:10.86#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.210.08:22:10.86#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.210.08:22:10.86#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:10.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:10.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:10.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:10.92#ibcon#enter wrdev, iclass 36, count 2 2006.210.08:22:10.92#ibcon#first serial, iclass 36, count 2 2006.210.08:22:10.92#ibcon#enter sib2, iclass 36, count 2 2006.210.08:22:10.92#ibcon#flushed, iclass 36, count 2 2006.210.08:22:10.92#ibcon#about to write, iclass 36, count 2 2006.210.08:22:10.92#ibcon#wrote, iclass 36, count 2 2006.210.08:22:10.92#ibcon#about to read 3, iclass 36, count 2 2006.210.08:22:10.94#ibcon#read 3, iclass 36, count 2 2006.210.08:22:10.94#ibcon#about to read 4, iclass 36, count 2 2006.210.08:22:10.94#ibcon#read 4, iclass 36, count 2 2006.210.08:22:10.94#ibcon#about to read 5, iclass 36, count 2 2006.210.08:22:10.94#ibcon#read 5, iclass 36, count 2 2006.210.08:22:10.94#ibcon#about to read 6, iclass 36, count 2 2006.210.08:22:10.94#ibcon#read 6, iclass 36, count 2 2006.210.08:22:10.94#ibcon#end of sib2, iclass 36, count 2 2006.210.08:22:10.94#ibcon#*mode == 0, iclass 36, count 2 2006.210.08:22:10.94#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.210.08:22:10.94#ibcon#[27=AT03-03\r\n] 2006.210.08:22:10.94#ibcon#*before write, iclass 36, count 2 2006.210.08:22:10.94#ibcon#enter sib2, iclass 36, count 2 2006.210.08:22:10.94#ibcon#flushed, iclass 36, count 2 2006.210.08:22:10.94#ibcon#about to write, iclass 36, count 2 2006.210.08:22:10.94#ibcon#wrote, iclass 36, count 2 2006.210.08:22:10.94#ibcon#about to read 3, iclass 36, count 2 2006.210.08:22:10.97#ibcon#read 3, iclass 36, count 2 2006.210.08:22:10.97#ibcon#about to read 4, iclass 36, count 2 2006.210.08:22:10.97#ibcon#read 4, iclass 36, count 2 2006.210.08:22:10.97#ibcon#about to read 5, iclass 36, count 2 2006.210.08:22:10.97#ibcon#read 5, iclass 36, count 2 2006.210.08:22:10.97#ibcon#about to read 6, iclass 36, count 2 2006.210.08:22:10.97#ibcon#read 6, iclass 36, count 2 2006.210.08:22:10.97#ibcon#end of sib2, iclass 36, count 2 2006.210.08:22:10.97#ibcon#*after write, iclass 36, count 2 2006.210.08:22:10.97#ibcon#*before return 0, iclass 36, count 2 2006.210.08:22:10.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:10.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.210.08:22:10.97#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.210.08:22:10.97#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:10.97#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:11.09#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:11.09#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:11.09#ibcon#enter wrdev, iclass 36, count 0 2006.210.08:22:11.09#ibcon#first serial, iclass 36, count 0 2006.210.08:22:11.09#ibcon#enter sib2, iclass 36, count 0 2006.210.08:22:11.09#ibcon#flushed, iclass 36, count 0 2006.210.08:22:11.09#ibcon#about to write, iclass 36, count 0 2006.210.08:22:11.09#ibcon#wrote, iclass 36, count 0 2006.210.08:22:11.09#ibcon#about to read 3, iclass 36, count 0 2006.210.08:22:11.11#ibcon#read 3, iclass 36, count 0 2006.210.08:22:11.11#ibcon#about to read 4, iclass 36, count 0 2006.210.08:22:11.11#ibcon#read 4, iclass 36, count 0 2006.210.08:22:11.11#ibcon#about to read 5, iclass 36, count 0 2006.210.08:22:11.11#ibcon#read 5, iclass 36, count 0 2006.210.08:22:11.11#ibcon#about to read 6, iclass 36, count 0 2006.210.08:22:11.11#ibcon#read 6, iclass 36, count 0 2006.210.08:22:11.11#ibcon#end of sib2, iclass 36, count 0 2006.210.08:22:11.11#ibcon#*mode == 0, iclass 36, count 0 2006.210.08:22:11.11#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.210.08:22:11.11#ibcon#[27=USB\r\n] 2006.210.08:22:11.11#ibcon#*before write, iclass 36, count 0 2006.210.08:22:11.11#ibcon#enter sib2, iclass 36, count 0 2006.210.08:22:11.11#ibcon#flushed, iclass 36, count 0 2006.210.08:22:11.11#ibcon#about to write, iclass 36, count 0 2006.210.08:22:11.11#ibcon#wrote, iclass 36, count 0 2006.210.08:22:11.11#ibcon#about to read 3, iclass 36, count 0 2006.210.08:22:11.14#ibcon#read 3, iclass 36, count 0 2006.210.08:22:11.14#ibcon#about to read 4, iclass 36, count 0 2006.210.08:22:11.14#ibcon#read 4, iclass 36, count 0 2006.210.08:22:11.14#ibcon#about to read 5, iclass 36, count 0 2006.210.08:22:11.14#ibcon#read 5, iclass 36, count 0 2006.210.08:22:11.14#ibcon#about to read 6, iclass 36, count 0 2006.210.08:22:11.14#ibcon#read 6, iclass 36, count 0 2006.210.08:22:11.14#ibcon#end of sib2, iclass 36, count 0 2006.210.08:22:11.14#ibcon#*after write, iclass 36, count 0 2006.210.08:22:11.14#ibcon#*before return 0, iclass 36, count 0 2006.210.08:22:11.14#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:11.14#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.210.08:22:11.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.210.08:22:11.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.210.08:22:11.14$vc4f8/vblo=4,712.99 2006.210.08:22:11.14#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.210.08:22:11.14#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.210.08:22:11.14#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:11.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:11.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:11.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:11.14#ibcon#enter wrdev, iclass 38, count 0 2006.210.08:22:11.14#ibcon#first serial, iclass 38, count 0 2006.210.08:22:11.14#ibcon#enter sib2, iclass 38, count 0 2006.210.08:22:11.14#ibcon#flushed, iclass 38, count 0 2006.210.08:22:11.14#ibcon#about to write, iclass 38, count 0 2006.210.08:22:11.14#ibcon#wrote, iclass 38, count 0 2006.210.08:22:11.14#ibcon#about to read 3, iclass 38, count 0 2006.210.08:22:11.16#ibcon#read 3, iclass 38, count 0 2006.210.08:22:11.16#ibcon#about to read 4, iclass 38, count 0 2006.210.08:22:11.16#ibcon#read 4, iclass 38, count 0 2006.210.08:22:11.16#ibcon#about to read 5, iclass 38, count 0 2006.210.08:22:11.16#ibcon#read 5, iclass 38, count 0 2006.210.08:22:11.16#ibcon#about to read 6, iclass 38, count 0 2006.210.08:22:11.16#ibcon#read 6, iclass 38, count 0 2006.210.08:22:11.16#ibcon#end of sib2, iclass 38, count 0 2006.210.08:22:11.16#ibcon#*mode == 0, iclass 38, count 0 2006.210.08:22:11.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.210.08:22:11.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:22:11.16#ibcon#*before write, iclass 38, count 0 2006.210.08:22:11.16#ibcon#enter sib2, iclass 38, count 0 2006.210.08:22:11.16#ibcon#flushed, iclass 38, count 0 2006.210.08:22:11.16#ibcon#about to write, iclass 38, count 0 2006.210.08:22:11.16#ibcon#wrote, iclass 38, count 0 2006.210.08:22:11.16#ibcon#about to read 3, iclass 38, count 0 2006.210.08:22:11.20#ibcon#read 3, iclass 38, count 0 2006.210.08:22:11.20#ibcon#about to read 4, iclass 38, count 0 2006.210.08:22:11.20#ibcon#read 4, iclass 38, count 0 2006.210.08:22:11.20#ibcon#about to read 5, iclass 38, count 0 2006.210.08:22:11.20#ibcon#read 5, iclass 38, count 0 2006.210.08:22:11.20#ibcon#about to read 6, iclass 38, count 0 2006.210.08:22:11.20#ibcon#read 6, iclass 38, count 0 2006.210.08:22:11.20#ibcon#end of sib2, iclass 38, count 0 2006.210.08:22:11.20#ibcon#*after write, iclass 38, count 0 2006.210.08:22:11.20#ibcon#*before return 0, iclass 38, count 0 2006.210.08:22:11.20#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:11.20#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.210.08:22:11.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.210.08:22:11.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.210.08:22:11.20$vc4f8/vb=4,3 2006.210.08:22:11.20#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.210.08:22:11.20#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.210.08:22:11.20#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:11.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:11.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:11.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:11.26#ibcon#enter wrdev, iclass 40, count 2 2006.210.08:22:11.26#ibcon#first serial, iclass 40, count 2 2006.210.08:22:11.26#ibcon#enter sib2, iclass 40, count 2 2006.210.08:22:11.26#ibcon#flushed, iclass 40, count 2 2006.210.08:22:11.26#ibcon#about to write, iclass 40, count 2 2006.210.08:22:11.26#ibcon#wrote, iclass 40, count 2 2006.210.08:22:11.26#ibcon#about to read 3, iclass 40, count 2 2006.210.08:22:11.28#ibcon#read 3, iclass 40, count 2 2006.210.08:22:11.28#ibcon#about to read 4, iclass 40, count 2 2006.210.08:22:11.28#ibcon#read 4, iclass 40, count 2 2006.210.08:22:11.28#ibcon#about to read 5, iclass 40, count 2 2006.210.08:22:11.28#ibcon#read 5, iclass 40, count 2 2006.210.08:22:11.28#ibcon#about to read 6, iclass 40, count 2 2006.210.08:22:11.28#ibcon#read 6, iclass 40, count 2 2006.210.08:22:11.28#ibcon#end of sib2, iclass 40, count 2 2006.210.08:22:11.28#ibcon#*mode == 0, iclass 40, count 2 2006.210.08:22:11.28#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.210.08:22:11.28#ibcon#[27=AT04-03\r\n] 2006.210.08:22:11.28#ibcon#*before write, iclass 40, count 2 2006.210.08:22:11.28#ibcon#enter sib2, iclass 40, count 2 2006.210.08:22:11.28#ibcon#flushed, iclass 40, count 2 2006.210.08:22:11.28#ibcon#about to write, iclass 40, count 2 2006.210.08:22:11.28#ibcon#wrote, iclass 40, count 2 2006.210.08:22:11.28#ibcon#about to read 3, iclass 40, count 2 2006.210.08:22:11.31#ibcon#read 3, iclass 40, count 2 2006.210.08:22:11.31#ibcon#about to read 4, iclass 40, count 2 2006.210.08:22:11.31#ibcon#read 4, iclass 40, count 2 2006.210.08:22:11.31#ibcon#about to read 5, iclass 40, count 2 2006.210.08:22:11.31#ibcon#read 5, iclass 40, count 2 2006.210.08:22:11.31#ibcon#about to read 6, iclass 40, count 2 2006.210.08:22:11.31#ibcon#read 6, iclass 40, count 2 2006.210.08:22:11.31#ibcon#end of sib2, iclass 40, count 2 2006.210.08:22:11.31#ibcon#*after write, iclass 40, count 2 2006.210.08:22:11.31#ibcon#*before return 0, iclass 40, count 2 2006.210.08:22:11.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:11.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.210.08:22:11.31#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.210.08:22:11.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:11.31#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:11.43#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:11.43#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:11.43#ibcon#enter wrdev, iclass 40, count 0 2006.210.08:22:11.43#ibcon#first serial, iclass 40, count 0 2006.210.08:22:11.43#ibcon#enter sib2, iclass 40, count 0 2006.210.08:22:11.43#ibcon#flushed, iclass 40, count 0 2006.210.08:22:11.43#ibcon#about to write, iclass 40, count 0 2006.210.08:22:11.43#ibcon#wrote, iclass 40, count 0 2006.210.08:22:11.43#ibcon#about to read 3, iclass 40, count 0 2006.210.08:22:11.45#ibcon#read 3, iclass 40, count 0 2006.210.08:22:11.45#ibcon#about to read 4, iclass 40, count 0 2006.210.08:22:11.45#ibcon#read 4, iclass 40, count 0 2006.210.08:22:11.45#ibcon#about to read 5, iclass 40, count 0 2006.210.08:22:11.45#ibcon#read 5, iclass 40, count 0 2006.210.08:22:11.45#ibcon#about to read 6, iclass 40, count 0 2006.210.08:22:11.45#ibcon#read 6, iclass 40, count 0 2006.210.08:22:11.45#ibcon#end of sib2, iclass 40, count 0 2006.210.08:22:11.45#ibcon#*mode == 0, iclass 40, count 0 2006.210.08:22:11.45#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.210.08:22:11.45#ibcon#[27=USB\r\n] 2006.210.08:22:11.45#ibcon#*before write, iclass 40, count 0 2006.210.08:22:11.45#ibcon#enter sib2, iclass 40, count 0 2006.210.08:22:11.45#ibcon#flushed, iclass 40, count 0 2006.210.08:22:11.45#ibcon#about to write, iclass 40, count 0 2006.210.08:22:11.45#ibcon#wrote, iclass 40, count 0 2006.210.08:22:11.45#ibcon#about to read 3, iclass 40, count 0 2006.210.08:22:11.48#ibcon#read 3, iclass 40, count 0 2006.210.08:22:11.48#ibcon#about to read 4, iclass 40, count 0 2006.210.08:22:11.48#ibcon#read 4, iclass 40, count 0 2006.210.08:22:11.48#ibcon#about to read 5, iclass 40, count 0 2006.210.08:22:11.48#ibcon#read 5, iclass 40, count 0 2006.210.08:22:11.48#ibcon#about to read 6, iclass 40, count 0 2006.210.08:22:11.48#ibcon#read 6, iclass 40, count 0 2006.210.08:22:11.48#ibcon#end of sib2, iclass 40, count 0 2006.210.08:22:11.48#ibcon#*after write, iclass 40, count 0 2006.210.08:22:11.48#ibcon#*before return 0, iclass 40, count 0 2006.210.08:22:11.48#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:11.48#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.210.08:22:11.48#ibcon#about to clear, iclass 40 cls_cnt 0 2006.210.08:22:11.48#ibcon#cleared, iclass 40 cls_cnt 0 2006.210.08:22:11.48$vc4f8/vblo=5,744.99 2006.210.08:22:11.48#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.210.08:22:11.48#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.210.08:22:11.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:11.48#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:11.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:11.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:11.48#ibcon#enter wrdev, iclass 4, count 0 2006.210.08:22:11.48#ibcon#first serial, iclass 4, count 0 2006.210.08:22:11.48#ibcon#enter sib2, iclass 4, count 0 2006.210.08:22:11.48#ibcon#flushed, iclass 4, count 0 2006.210.08:22:11.48#ibcon#about to write, iclass 4, count 0 2006.210.08:22:11.48#ibcon#wrote, iclass 4, count 0 2006.210.08:22:11.48#ibcon#about to read 3, iclass 4, count 0 2006.210.08:22:11.50#ibcon#read 3, iclass 4, count 0 2006.210.08:22:11.50#ibcon#about to read 4, iclass 4, count 0 2006.210.08:22:11.50#ibcon#read 4, iclass 4, count 0 2006.210.08:22:11.50#ibcon#about to read 5, iclass 4, count 0 2006.210.08:22:11.50#ibcon#read 5, iclass 4, count 0 2006.210.08:22:11.50#ibcon#about to read 6, iclass 4, count 0 2006.210.08:22:11.50#ibcon#read 6, iclass 4, count 0 2006.210.08:22:11.50#ibcon#end of sib2, iclass 4, count 0 2006.210.08:22:11.50#ibcon#*mode == 0, iclass 4, count 0 2006.210.08:22:11.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.210.08:22:11.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:22:11.50#ibcon#*before write, iclass 4, count 0 2006.210.08:22:11.50#ibcon#enter sib2, iclass 4, count 0 2006.210.08:22:11.50#ibcon#flushed, iclass 4, count 0 2006.210.08:22:11.50#ibcon#about to write, iclass 4, count 0 2006.210.08:22:11.50#ibcon#wrote, iclass 4, count 0 2006.210.08:22:11.50#ibcon#about to read 3, iclass 4, count 0 2006.210.08:22:11.54#ibcon#read 3, iclass 4, count 0 2006.210.08:22:11.54#ibcon#about to read 4, iclass 4, count 0 2006.210.08:22:11.54#ibcon#read 4, iclass 4, count 0 2006.210.08:22:11.54#ibcon#about to read 5, iclass 4, count 0 2006.210.08:22:11.54#ibcon#read 5, iclass 4, count 0 2006.210.08:22:11.54#ibcon#about to read 6, iclass 4, count 0 2006.210.08:22:11.54#ibcon#read 6, iclass 4, count 0 2006.210.08:22:11.54#ibcon#end of sib2, iclass 4, count 0 2006.210.08:22:11.54#ibcon#*after write, iclass 4, count 0 2006.210.08:22:11.54#ibcon#*before return 0, iclass 4, count 0 2006.210.08:22:11.54#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:11.54#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.210.08:22:11.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.210.08:22:11.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.210.08:22:11.54$vc4f8/vb=5,3 2006.210.08:22:11.54#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.210.08:22:11.54#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.210.08:22:11.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:11.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:11.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:11.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:11.60#ibcon#enter wrdev, iclass 6, count 2 2006.210.08:22:11.60#ibcon#first serial, iclass 6, count 2 2006.210.08:22:11.60#ibcon#enter sib2, iclass 6, count 2 2006.210.08:22:11.60#ibcon#flushed, iclass 6, count 2 2006.210.08:22:11.60#ibcon#about to write, iclass 6, count 2 2006.210.08:22:11.60#ibcon#wrote, iclass 6, count 2 2006.210.08:22:11.60#ibcon#about to read 3, iclass 6, count 2 2006.210.08:22:11.62#ibcon#read 3, iclass 6, count 2 2006.210.08:22:11.62#ibcon#about to read 4, iclass 6, count 2 2006.210.08:22:11.62#ibcon#read 4, iclass 6, count 2 2006.210.08:22:11.62#ibcon#about to read 5, iclass 6, count 2 2006.210.08:22:11.62#ibcon#read 5, iclass 6, count 2 2006.210.08:22:11.62#ibcon#about to read 6, iclass 6, count 2 2006.210.08:22:11.62#ibcon#read 6, iclass 6, count 2 2006.210.08:22:11.62#ibcon#end of sib2, iclass 6, count 2 2006.210.08:22:11.62#ibcon#*mode == 0, iclass 6, count 2 2006.210.08:22:11.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.210.08:22:11.62#ibcon#[27=AT05-03\r\n] 2006.210.08:22:11.62#ibcon#*before write, iclass 6, count 2 2006.210.08:22:11.62#ibcon#enter sib2, iclass 6, count 2 2006.210.08:22:11.62#ibcon#flushed, iclass 6, count 2 2006.210.08:22:11.62#ibcon#about to write, iclass 6, count 2 2006.210.08:22:11.62#ibcon#wrote, iclass 6, count 2 2006.210.08:22:11.62#ibcon#about to read 3, iclass 6, count 2 2006.210.08:22:11.65#ibcon#read 3, iclass 6, count 2 2006.210.08:22:11.65#ibcon#about to read 4, iclass 6, count 2 2006.210.08:22:11.65#ibcon#read 4, iclass 6, count 2 2006.210.08:22:11.65#ibcon#about to read 5, iclass 6, count 2 2006.210.08:22:11.65#ibcon#read 5, iclass 6, count 2 2006.210.08:22:11.65#ibcon#about to read 6, iclass 6, count 2 2006.210.08:22:11.65#ibcon#read 6, iclass 6, count 2 2006.210.08:22:11.65#ibcon#end of sib2, iclass 6, count 2 2006.210.08:22:11.65#ibcon#*after write, iclass 6, count 2 2006.210.08:22:11.65#ibcon#*before return 0, iclass 6, count 2 2006.210.08:22:11.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:11.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.210.08:22:11.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.210.08:22:11.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:11.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:11.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:11.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:11.77#ibcon#enter wrdev, iclass 6, count 0 2006.210.08:22:11.77#ibcon#first serial, iclass 6, count 0 2006.210.08:22:11.77#ibcon#enter sib2, iclass 6, count 0 2006.210.08:22:11.77#ibcon#flushed, iclass 6, count 0 2006.210.08:22:11.77#ibcon#about to write, iclass 6, count 0 2006.210.08:22:11.77#ibcon#wrote, iclass 6, count 0 2006.210.08:22:11.77#ibcon#about to read 3, iclass 6, count 0 2006.210.08:22:11.79#ibcon#read 3, iclass 6, count 0 2006.210.08:22:11.79#ibcon#about to read 4, iclass 6, count 0 2006.210.08:22:11.79#ibcon#read 4, iclass 6, count 0 2006.210.08:22:11.79#ibcon#about to read 5, iclass 6, count 0 2006.210.08:22:11.79#ibcon#read 5, iclass 6, count 0 2006.210.08:22:11.79#ibcon#about to read 6, iclass 6, count 0 2006.210.08:22:11.79#ibcon#read 6, iclass 6, count 0 2006.210.08:22:11.79#ibcon#end of sib2, iclass 6, count 0 2006.210.08:22:11.79#ibcon#*mode == 0, iclass 6, count 0 2006.210.08:22:11.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.210.08:22:11.79#ibcon#[27=USB\r\n] 2006.210.08:22:11.79#ibcon#*before write, iclass 6, count 0 2006.210.08:22:11.79#ibcon#enter sib2, iclass 6, count 0 2006.210.08:22:11.79#ibcon#flushed, iclass 6, count 0 2006.210.08:22:11.79#ibcon#about to write, iclass 6, count 0 2006.210.08:22:11.79#ibcon#wrote, iclass 6, count 0 2006.210.08:22:11.79#ibcon#about to read 3, iclass 6, count 0 2006.210.08:22:11.82#ibcon#read 3, iclass 6, count 0 2006.210.08:22:11.82#ibcon#about to read 4, iclass 6, count 0 2006.210.08:22:11.82#ibcon#read 4, iclass 6, count 0 2006.210.08:22:11.82#ibcon#about to read 5, iclass 6, count 0 2006.210.08:22:11.82#ibcon#read 5, iclass 6, count 0 2006.210.08:22:11.82#ibcon#about to read 6, iclass 6, count 0 2006.210.08:22:11.82#ibcon#read 6, iclass 6, count 0 2006.210.08:22:11.82#ibcon#end of sib2, iclass 6, count 0 2006.210.08:22:11.82#ibcon#*after write, iclass 6, count 0 2006.210.08:22:11.82#ibcon#*before return 0, iclass 6, count 0 2006.210.08:22:11.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:11.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.210.08:22:11.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.210.08:22:11.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.210.08:22:11.82$vc4f8/vblo=6,752.99 2006.210.08:22:11.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.210.08:22:11.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.210.08:22:11.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:22:11.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:11.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:11.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:11.82#ibcon#enter wrdev, iclass 10, count 0 2006.210.08:22:11.82#ibcon#first serial, iclass 10, count 0 2006.210.08:22:11.82#ibcon#enter sib2, iclass 10, count 0 2006.210.08:22:11.82#ibcon#flushed, iclass 10, count 0 2006.210.08:22:11.82#ibcon#about to write, iclass 10, count 0 2006.210.08:22:11.82#ibcon#wrote, iclass 10, count 0 2006.210.08:22:11.82#ibcon#about to read 3, iclass 10, count 0 2006.210.08:22:11.84#ibcon#read 3, iclass 10, count 0 2006.210.08:22:11.84#ibcon#about to read 4, iclass 10, count 0 2006.210.08:22:11.84#ibcon#read 4, iclass 10, count 0 2006.210.08:22:11.84#ibcon#about to read 5, iclass 10, count 0 2006.210.08:22:11.84#ibcon#read 5, iclass 10, count 0 2006.210.08:22:11.84#ibcon#about to read 6, iclass 10, count 0 2006.210.08:22:11.84#ibcon#read 6, iclass 10, count 0 2006.210.08:22:11.84#ibcon#end of sib2, iclass 10, count 0 2006.210.08:22:11.84#ibcon#*mode == 0, iclass 10, count 0 2006.210.08:22:11.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.210.08:22:11.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:22:11.84#ibcon#*before write, iclass 10, count 0 2006.210.08:22:11.84#ibcon#enter sib2, iclass 10, count 0 2006.210.08:22:11.84#ibcon#flushed, iclass 10, count 0 2006.210.08:22:11.84#ibcon#about to write, iclass 10, count 0 2006.210.08:22:11.84#ibcon#wrote, iclass 10, count 0 2006.210.08:22:11.84#ibcon#about to read 3, iclass 10, count 0 2006.210.08:22:11.88#ibcon#read 3, iclass 10, count 0 2006.210.08:22:11.88#ibcon#about to read 4, iclass 10, count 0 2006.210.08:22:11.88#ibcon#read 4, iclass 10, count 0 2006.210.08:22:11.88#ibcon#about to read 5, iclass 10, count 0 2006.210.08:22:11.88#ibcon#read 5, iclass 10, count 0 2006.210.08:22:11.88#ibcon#about to read 6, iclass 10, count 0 2006.210.08:22:11.88#ibcon#read 6, iclass 10, count 0 2006.210.08:22:11.88#ibcon#end of sib2, iclass 10, count 0 2006.210.08:22:11.88#ibcon#*after write, iclass 10, count 0 2006.210.08:22:11.88#ibcon#*before return 0, iclass 10, count 0 2006.210.08:22:11.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:11.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.210.08:22:11.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.210.08:22:11.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.210.08:22:11.88$vc4f8/vb=6,3 2006.210.08:22:11.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.210.08:22:11.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.210.08:22:11.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:22:11.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:11.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:11.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:11.94#ibcon#enter wrdev, iclass 12, count 2 2006.210.08:22:11.94#ibcon#first serial, iclass 12, count 2 2006.210.08:22:11.94#ibcon#enter sib2, iclass 12, count 2 2006.210.08:22:11.94#ibcon#flushed, iclass 12, count 2 2006.210.08:22:11.94#ibcon#about to write, iclass 12, count 2 2006.210.08:22:11.94#ibcon#wrote, iclass 12, count 2 2006.210.08:22:11.94#ibcon#about to read 3, iclass 12, count 2 2006.210.08:22:11.96#ibcon#read 3, iclass 12, count 2 2006.210.08:22:11.96#ibcon#about to read 4, iclass 12, count 2 2006.210.08:22:11.96#ibcon#read 4, iclass 12, count 2 2006.210.08:22:11.96#ibcon#about to read 5, iclass 12, count 2 2006.210.08:22:11.96#ibcon#read 5, iclass 12, count 2 2006.210.08:22:11.96#ibcon#about to read 6, iclass 12, count 2 2006.210.08:22:11.96#ibcon#read 6, iclass 12, count 2 2006.210.08:22:11.96#ibcon#end of sib2, iclass 12, count 2 2006.210.08:22:11.96#ibcon#*mode == 0, iclass 12, count 2 2006.210.08:22:11.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.210.08:22:11.96#ibcon#[27=AT06-03\r\n] 2006.210.08:22:11.96#ibcon#*before write, iclass 12, count 2 2006.210.08:22:11.96#ibcon#enter sib2, iclass 12, count 2 2006.210.08:22:11.96#ibcon#flushed, iclass 12, count 2 2006.210.08:22:11.96#ibcon#about to write, iclass 12, count 2 2006.210.08:22:11.96#ibcon#wrote, iclass 12, count 2 2006.210.08:22:11.96#ibcon#about to read 3, iclass 12, count 2 2006.210.08:22:11.99#ibcon#read 3, iclass 12, count 2 2006.210.08:22:11.99#ibcon#about to read 4, iclass 12, count 2 2006.210.08:22:11.99#ibcon#read 4, iclass 12, count 2 2006.210.08:22:11.99#ibcon#about to read 5, iclass 12, count 2 2006.210.08:22:11.99#ibcon#read 5, iclass 12, count 2 2006.210.08:22:11.99#ibcon#about to read 6, iclass 12, count 2 2006.210.08:22:11.99#ibcon#read 6, iclass 12, count 2 2006.210.08:22:11.99#ibcon#end of sib2, iclass 12, count 2 2006.210.08:22:11.99#ibcon#*after write, iclass 12, count 2 2006.210.08:22:11.99#ibcon#*before return 0, iclass 12, count 2 2006.210.08:22:11.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:11.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.210.08:22:11.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.210.08:22:11.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:22:11.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:12.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:12.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:12.11#ibcon#enter wrdev, iclass 12, count 0 2006.210.08:22:12.11#ibcon#first serial, iclass 12, count 0 2006.210.08:22:12.11#ibcon#enter sib2, iclass 12, count 0 2006.210.08:22:12.11#ibcon#flushed, iclass 12, count 0 2006.210.08:22:12.11#ibcon#about to write, iclass 12, count 0 2006.210.08:22:12.11#ibcon#wrote, iclass 12, count 0 2006.210.08:22:12.11#ibcon#about to read 3, iclass 12, count 0 2006.210.08:22:12.13#ibcon#read 3, iclass 12, count 0 2006.210.08:22:12.13#ibcon#about to read 4, iclass 12, count 0 2006.210.08:22:12.13#ibcon#read 4, iclass 12, count 0 2006.210.08:22:12.13#ibcon#about to read 5, iclass 12, count 0 2006.210.08:22:12.13#ibcon#read 5, iclass 12, count 0 2006.210.08:22:12.13#ibcon#about to read 6, iclass 12, count 0 2006.210.08:22:12.13#ibcon#read 6, iclass 12, count 0 2006.210.08:22:12.13#ibcon#end of sib2, iclass 12, count 0 2006.210.08:22:12.13#ibcon#*mode == 0, iclass 12, count 0 2006.210.08:22:12.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.210.08:22:12.13#ibcon#[27=USB\r\n] 2006.210.08:22:12.13#ibcon#*before write, iclass 12, count 0 2006.210.08:22:12.13#ibcon#enter sib2, iclass 12, count 0 2006.210.08:22:12.13#ibcon#flushed, iclass 12, count 0 2006.210.08:22:12.13#ibcon#about to write, iclass 12, count 0 2006.210.08:22:12.13#ibcon#wrote, iclass 12, count 0 2006.210.08:22:12.13#ibcon#about to read 3, iclass 12, count 0 2006.210.08:22:12.16#ibcon#read 3, iclass 12, count 0 2006.210.08:22:12.16#ibcon#about to read 4, iclass 12, count 0 2006.210.08:22:12.16#ibcon#read 4, iclass 12, count 0 2006.210.08:22:12.16#ibcon#about to read 5, iclass 12, count 0 2006.210.08:22:12.16#ibcon#read 5, iclass 12, count 0 2006.210.08:22:12.16#ibcon#about to read 6, iclass 12, count 0 2006.210.08:22:12.16#ibcon#read 6, iclass 12, count 0 2006.210.08:22:12.16#ibcon#end of sib2, iclass 12, count 0 2006.210.08:22:12.16#ibcon#*after write, iclass 12, count 0 2006.210.08:22:12.16#ibcon#*before return 0, iclass 12, count 0 2006.210.08:22:12.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:12.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.210.08:22:12.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.210.08:22:12.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.210.08:22:12.16$vc4f8/vabw=wide 2006.210.08:22:12.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.210.08:22:12.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.210.08:22:12.16#ibcon#ireg 8 cls_cnt 0 2006.210.08:22:12.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:12.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:12.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:12.16#ibcon#enter wrdev, iclass 14, count 0 2006.210.08:22:12.16#ibcon#first serial, iclass 14, count 0 2006.210.08:22:12.16#ibcon#enter sib2, iclass 14, count 0 2006.210.08:22:12.16#ibcon#flushed, iclass 14, count 0 2006.210.08:22:12.16#ibcon#about to write, iclass 14, count 0 2006.210.08:22:12.16#ibcon#wrote, iclass 14, count 0 2006.210.08:22:12.16#ibcon#about to read 3, iclass 14, count 0 2006.210.08:22:12.18#ibcon#read 3, iclass 14, count 0 2006.210.08:22:12.18#ibcon#about to read 4, iclass 14, count 0 2006.210.08:22:12.18#ibcon#read 4, iclass 14, count 0 2006.210.08:22:12.18#ibcon#about to read 5, iclass 14, count 0 2006.210.08:22:12.18#ibcon#read 5, iclass 14, count 0 2006.210.08:22:12.18#ibcon#about to read 6, iclass 14, count 0 2006.210.08:22:12.18#ibcon#read 6, iclass 14, count 0 2006.210.08:22:12.18#ibcon#end of sib2, iclass 14, count 0 2006.210.08:22:12.18#ibcon#*mode == 0, iclass 14, count 0 2006.210.08:22:12.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.210.08:22:12.18#ibcon#[25=BW32\r\n] 2006.210.08:22:12.18#ibcon#*before write, iclass 14, count 0 2006.210.08:22:12.18#ibcon#enter sib2, iclass 14, count 0 2006.210.08:22:12.18#ibcon#flushed, iclass 14, count 0 2006.210.08:22:12.18#ibcon#about to write, iclass 14, count 0 2006.210.08:22:12.18#ibcon#wrote, iclass 14, count 0 2006.210.08:22:12.18#ibcon#about to read 3, iclass 14, count 0 2006.210.08:22:12.21#ibcon#read 3, iclass 14, count 0 2006.210.08:22:12.21#ibcon#about to read 4, iclass 14, count 0 2006.210.08:22:12.21#ibcon#read 4, iclass 14, count 0 2006.210.08:22:12.21#ibcon#about to read 5, iclass 14, count 0 2006.210.08:22:12.21#ibcon#read 5, iclass 14, count 0 2006.210.08:22:12.21#ibcon#about to read 6, iclass 14, count 0 2006.210.08:22:12.21#ibcon#read 6, iclass 14, count 0 2006.210.08:22:12.21#ibcon#end of sib2, iclass 14, count 0 2006.210.08:22:12.21#ibcon#*after write, iclass 14, count 0 2006.210.08:22:12.21#ibcon#*before return 0, iclass 14, count 0 2006.210.08:22:12.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:12.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.210.08:22:12.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.210.08:22:12.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.210.08:22:12.21$vc4f8/vbbw=wide 2006.210.08:22:12.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.210.08:22:12.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.210.08:22:12.21#ibcon#ireg 8 cls_cnt 0 2006.210.08:22:12.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:22:12.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:22:12.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:22:12.28#ibcon#enter wrdev, iclass 16, count 0 2006.210.08:22:12.28#ibcon#first serial, iclass 16, count 0 2006.210.08:22:12.28#ibcon#enter sib2, iclass 16, count 0 2006.210.08:22:12.28#ibcon#flushed, iclass 16, count 0 2006.210.08:22:12.28#ibcon#about to write, iclass 16, count 0 2006.210.08:22:12.28#ibcon#wrote, iclass 16, count 0 2006.210.08:22:12.28#ibcon#about to read 3, iclass 16, count 0 2006.210.08:22:12.30#ibcon#read 3, iclass 16, count 0 2006.210.08:22:12.30#ibcon#about to read 4, iclass 16, count 0 2006.210.08:22:12.30#ibcon#read 4, iclass 16, count 0 2006.210.08:22:12.30#ibcon#about to read 5, iclass 16, count 0 2006.210.08:22:12.30#ibcon#read 5, iclass 16, count 0 2006.210.08:22:12.30#ibcon#about to read 6, iclass 16, count 0 2006.210.08:22:12.30#ibcon#read 6, iclass 16, count 0 2006.210.08:22:12.30#ibcon#end of sib2, iclass 16, count 0 2006.210.08:22:12.30#ibcon#*mode == 0, iclass 16, count 0 2006.210.08:22:12.30#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.210.08:22:12.30#ibcon#[27=BW32\r\n] 2006.210.08:22:12.30#ibcon#*before write, iclass 16, count 0 2006.210.08:22:12.30#ibcon#enter sib2, iclass 16, count 0 2006.210.08:22:12.30#ibcon#flushed, iclass 16, count 0 2006.210.08:22:12.30#ibcon#about to write, iclass 16, count 0 2006.210.08:22:12.30#ibcon#wrote, iclass 16, count 0 2006.210.08:22:12.30#ibcon#about to read 3, iclass 16, count 0 2006.210.08:22:12.33#ibcon#read 3, iclass 16, count 0 2006.210.08:22:12.33#ibcon#about to read 4, iclass 16, count 0 2006.210.08:22:12.33#ibcon#read 4, iclass 16, count 0 2006.210.08:22:12.33#ibcon#about to read 5, iclass 16, count 0 2006.210.08:22:12.33#ibcon#read 5, iclass 16, count 0 2006.210.08:22:12.33#ibcon#about to read 6, iclass 16, count 0 2006.210.08:22:12.33#ibcon#read 6, iclass 16, count 0 2006.210.08:22:12.33#ibcon#end of sib2, iclass 16, count 0 2006.210.08:22:12.33#ibcon#*after write, iclass 16, count 0 2006.210.08:22:12.33#ibcon#*before return 0, iclass 16, count 0 2006.210.08:22:12.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:22:12.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.210.08:22:12.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.210.08:22:12.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.210.08:22:12.33$4f8m12a/ifd4f 2006.210.08:22:12.33$ifd4f/lo= 2006.210.08:22:12.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:22:12.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:22:12.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:22:12.33$ifd4f/patch= 2006.210.08:22:12.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:22:12.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:22:12.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:22:12.33$4f8m12a/"form=m,16.000,1:2 2006.210.08:22:12.33$4f8m12a/"tpicd 2006.210.08:22:12.33$4f8m12a/echo=off 2006.210.08:22:12.33$4f8m12a/xlog=off 2006.210.08:22:12.33:!2006.210.08:24:20 2006.210.08:22:40.13#trakl#Source acquired 2006.210.08:22:40.13#flagr#flagr/antenna,acquired 2006.210.08:24:20.00:preob 2006.210.08:24:20.13/onsource/TRACKING 2006.210.08:24:20.13:!2006.210.08:24:30 2006.210.08:24:30.00:data_valid=on 2006.210.08:24:30.00:midob 2006.210.08:24:31.14/onsource/TRACKING 2006.210.08:24:31.14/wx/29.59,1006.6,83 2006.210.08:24:31.33/cable/+6.3940E-03 2006.210.08:24:32.42/va/01,08,usb,yes,29,31 2006.210.08:24:32.42/va/02,07,usb,yes,29,30 2006.210.08:24:32.42/va/03,06,usb,yes,31,31 2006.210.08:24:32.42/va/04,07,usb,yes,30,32 2006.210.08:24:32.42/va/05,07,usb,yes,31,33 2006.210.08:24:32.42/va/06,06,usb,yes,30,30 2006.210.08:24:32.42/va/07,06,usb,yes,31,31 2006.210.08:24:32.42/va/08,07,usb,yes,29,29 2006.210.08:24:32.65/valo/01,532.99,yes,locked 2006.210.08:24:32.65/valo/02,572.99,yes,locked 2006.210.08:24:32.65/valo/03,672.99,yes,locked 2006.210.08:24:32.65/valo/04,832.99,yes,locked 2006.210.08:24:32.65/valo/05,652.99,yes,locked 2006.210.08:24:32.65/valo/06,772.99,yes,locked 2006.210.08:24:32.65/valo/07,832.99,yes,locked 2006.210.08:24:32.65/valo/08,852.99,yes,locked 2006.210.08:24:33.74/vb/01,04,usb,yes,28,27 2006.210.08:24:33.74/vb/02,04,usb,yes,30,31 2006.210.08:24:33.74/vb/03,03,usb,yes,33,37 2006.210.08:24:33.74/vb/04,03,usb,yes,34,34 2006.210.08:24:33.74/vb/05,03,usb,yes,32,37 2006.210.08:24:33.74/vb/06,03,usb,yes,33,36 2006.210.08:24:33.74/vb/07,04,usb,yes,29,29 2006.210.08:24:33.74/vb/08,03,usb,yes,33,37 2006.210.08:24:33.97/vblo/01,632.99,yes,locked 2006.210.08:24:33.97/vblo/02,640.99,yes,locked 2006.210.08:24:33.97/vblo/03,656.99,yes,locked 2006.210.08:24:33.97/vblo/04,712.99,yes,locked 2006.210.08:24:33.97/vblo/05,744.99,yes,locked 2006.210.08:24:33.97/vblo/06,752.99,yes,locked 2006.210.08:24:33.97/vblo/07,734.99,yes,locked 2006.210.08:24:33.97/vblo/08,744.99,yes,locked 2006.210.08:24:34.12/vabw/8 2006.210.08:24:34.27/vbbw/8 2006.210.08:24:34.36/xfe/off,on,14.5 2006.210.08:24:34.74/ifatt/23,28,28,28 2006.210.08:24:35.07/fmout-gps/S +4.57E-07 2006.210.08:24:35.11:!2006.210.08:25:30 2006.210.08:25:30.01:data_valid=off 2006.210.08:25:30.01:postob 2006.210.08:25:30.21/cable/+6.3930E-03 2006.210.08:25:30.21/wx/29.53,1006.6,84 2006.210.08:25:31.07/fmout-gps/S +4.57E-07 2006.210.08:25:31.07:scan_name=210-0826,k06210,60 2006.210.08:25:31.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.210.08:25:31.14#flagr#flagr/antenna,new-source 2006.210.08:25:32.14:checkk5 2006.210.08:25:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.210.08:25:32.82/chk_autoobs//k5ts2/ autoobs is running! 2006.210.08:25:33.16/chk_autoobs//k5ts3/ autoobs is running! 2006.210.08:25:33.51/chk_autoobs//k5ts4/ autoobs is running! 2006.210.08:25:33.84/chk_obsdata//k5ts1/T2100824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:25:34.17/chk_obsdata//k5ts2/T2100824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:25:34.51/chk_obsdata//k5ts3/T2100824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:25:34.85/chk_obsdata//k5ts4/T2100824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.210.08:25:35.52/k5log//k5ts1_log_newline 2006.210.08:25:36.17/k5log//k5ts2_log_newline 2006.210.08:25:36.84/k5log//k5ts3_log_newline 2006.210.08:25:37.50/k5log//k5ts4_log_newline 2006.210.08:25:37.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:25:37.52:4f8m12a=3 2006.210.08:25:37.52$4f8m12a/echo=on 2006.210.08:25:37.52$4f8m12a/pcalon 2006.210.08:25:37.52$pcalon/"no phase cal control is implemented here 2006.210.08:25:37.52$4f8m12a/"tpicd=stop 2006.210.08:25:37.52$4f8m12a/vc4f8 2006.210.08:25:37.52$vc4f8/valo=1,532.99 2006.210.08:25:37.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.08:25:37.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.08:25:37.53#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:37.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:37.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:37.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:37.53#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:25:37.53#ibcon#first serial, iclass 31, count 0 2006.210.08:25:37.53#ibcon#enter sib2, iclass 31, count 0 2006.210.08:25:37.53#ibcon#flushed, iclass 31, count 0 2006.210.08:25:37.53#ibcon#about to write, iclass 31, count 0 2006.210.08:25:37.53#ibcon#wrote, iclass 31, count 0 2006.210.08:25:37.53#ibcon#about to read 3, iclass 31, count 0 2006.210.08:25:37.55#ibcon#read 3, iclass 31, count 0 2006.210.08:25:37.55#ibcon#about to read 4, iclass 31, count 0 2006.210.08:25:37.55#ibcon#read 4, iclass 31, count 0 2006.210.08:25:37.55#ibcon#about to read 5, iclass 31, count 0 2006.210.08:25:37.55#ibcon#read 5, iclass 31, count 0 2006.210.08:25:37.55#ibcon#about to read 6, iclass 31, count 0 2006.210.08:25:37.55#ibcon#read 6, iclass 31, count 0 2006.210.08:25:37.55#ibcon#end of sib2, iclass 31, count 0 2006.210.08:25:37.55#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:25:37.55#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:25:37.55#ibcon#[26=FRQ=01,532.99\r\n] 2006.210.08:25:37.55#ibcon#*before write, iclass 31, count 0 2006.210.08:25:37.55#ibcon#enter sib2, iclass 31, count 0 2006.210.08:25:37.55#ibcon#flushed, iclass 31, count 0 2006.210.08:25:37.55#ibcon#about to write, iclass 31, count 0 2006.210.08:25:37.55#ibcon#wrote, iclass 31, count 0 2006.210.08:25:37.55#ibcon#about to read 3, iclass 31, count 0 2006.210.08:25:37.60#ibcon#read 3, iclass 31, count 0 2006.210.08:25:37.60#ibcon#about to read 4, iclass 31, count 0 2006.210.08:25:37.60#ibcon#read 4, iclass 31, count 0 2006.210.08:25:37.60#ibcon#about to read 5, iclass 31, count 0 2006.210.08:25:37.60#ibcon#read 5, iclass 31, count 0 2006.210.08:25:37.60#ibcon#about to read 6, iclass 31, count 0 2006.210.08:25:37.60#ibcon#read 6, iclass 31, count 0 2006.210.08:25:37.60#ibcon#end of sib2, iclass 31, count 0 2006.210.08:25:37.60#ibcon#*after write, iclass 31, count 0 2006.210.08:25:37.60#ibcon#*before return 0, iclass 31, count 0 2006.210.08:25:37.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:37.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:37.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:25:37.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:25:37.60$vc4f8/va=1,8 2006.210.08:25:37.60#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.08:25:37.60#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.08:25:37.60#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:37.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:37.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:37.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:37.60#ibcon#enter wrdev, iclass 33, count 2 2006.210.08:25:37.60#ibcon#first serial, iclass 33, count 2 2006.210.08:25:37.60#ibcon#enter sib2, iclass 33, count 2 2006.210.08:25:37.60#ibcon#flushed, iclass 33, count 2 2006.210.08:25:37.60#ibcon#about to write, iclass 33, count 2 2006.210.08:25:37.60#ibcon#wrote, iclass 33, count 2 2006.210.08:25:37.60#ibcon#about to read 3, iclass 33, count 2 2006.210.08:25:37.62#ibcon#read 3, iclass 33, count 2 2006.210.08:25:37.62#ibcon#about to read 4, iclass 33, count 2 2006.210.08:25:37.62#ibcon#read 4, iclass 33, count 2 2006.210.08:25:37.62#ibcon#about to read 5, iclass 33, count 2 2006.210.08:25:37.62#ibcon#read 5, iclass 33, count 2 2006.210.08:25:37.62#ibcon#about to read 6, iclass 33, count 2 2006.210.08:25:37.62#ibcon#read 6, iclass 33, count 2 2006.210.08:25:37.62#ibcon#end of sib2, iclass 33, count 2 2006.210.08:25:37.62#ibcon#*mode == 0, iclass 33, count 2 2006.210.08:25:37.62#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.08:25:37.62#ibcon#[25=AT01-08\r\n] 2006.210.08:25:37.62#ibcon#*before write, iclass 33, count 2 2006.210.08:25:37.62#ibcon#enter sib2, iclass 33, count 2 2006.210.08:25:37.62#ibcon#flushed, iclass 33, count 2 2006.210.08:25:37.62#ibcon#about to write, iclass 33, count 2 2006.210.08:25:37.62#ibcon#wrote, iclass 33, count 2 2006.210.08:25:37.62#ibcon#about to read 3, iclass 33, count 2 2006.210.08:25:37.65#ibcon#read 3, iclass 33, count 2 2006.210.08:25:37.65#ibcon#about to read 4, iclass 33, count 2 2006.210.08:25:37.65#ibcon#read 4, iclass 33, count 2 2006.210.08:25:37.65#ibcon#about to read 5, iclass 33, count 2 2006.210.08:25:37.65#ibcon#read 5, iclass 33, count 2 2006.210.08:25:37.65#ibcon#about to read 6, iclass 33, count 2 2006.210.08:25:37.65#ibcon#read 6, iclass 33, count 2 2006.210.08:25:37.65#ibcon#end of sib2, iclass 33, count 2 2006.210.08:25:37.65#ibcon#*after write, iclass 33, count 2 2006.210.08:25:37.65#ibcon#*before return 0, iclass 33, count 2 2006.210.08:25:37.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:37.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:37.65#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.08:25:37.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:37.65#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:37.77#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:37.77#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:37.77#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:25:37.77#ibcon#first serial, iclass 33, count 0 2006.210.08:25:37.77#ibcon#enter sib2, iclass 33, count 0 2006.210.08:25:37.77#ibcon#flushed, iclass 33, count 0 2006.210.08:25:37.77#ibcon#about to write, iclass 33, count 0 2006.210.08:25:37.77#ibcon#wrote, iclass 33, count 0 2006.210.08:25:37.77#ibcon#about to read 3, iclass 33, count 0 2006.210.08:25:37.79#ibcon#read 3, iclass 33, count 0 2006.210.08:25:37.79#ibcon#about to read 4, iclass 33, count 0 2006.210.08:25:37.79#ibcon#read 4, iclass 33, count 0 2006.210.08:25:37.79#ibcon#about to read 5, iclass 33, count 0 2006.210.08:25:37.79#ibcon#read 5, iclass 33, count 0 2006.210.08:25:37.79#ibcon#about to read 6, iclass 33, count 0 2006.210.08:25:37.79#ibcon#read 6, iclass 33, count 0 2006.210.08:25:37.79#ibcon#end of sib2, iclass 33, count 0 2006.210.08:25:37.79#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:25:37.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:25:37.79#ibcon#[25=USB\r\n] 2006.210.08:25:37.79#ibcon#*before write, iclass 33, count 0 2006.210.08:25:37.79#ibcon#enter sib2, iclass 33, count 0 2006.210.08:25:37.79#ibcon#flushed, iclass 33, count 0 2006.210.08:25:37.79#ibcon#about to write, iclass 33, count 0 2006.210.08:25:37.79#ibcon#wrote, iclass 33, count 0 2006.210.08:25:37.79#ibcon#about to read 3, iclass 33, count 0 2006.210.08:25:37.82#ibcon#read 3, iclass 33, count 0 2006.210.08:25:37.82#ibcon#about to read 4, iclass 33, count 0 2006.210.08:25:37.82#ibcon#read 4, iclass 33, count 0 2006.210.08:25:37.82#ibcon#about to read 5, iclass 33, count 0 2006.210.08:25:37.82#ibcon#read 5, iclass 33, count 0 2006.210.08:25:37.82#ibcon#about to read 6, iclass 33, count 0 2006.210.08:25:37.82#ibcon#read 6, iclass 33, count 0 2006.210.08:25:37.82#ibcon#end of sib2, iclass 33, count 0 2006.210.08:25:37.82#ibcon#*after write, iclass 33, count 0 2006.210.08:25:37.82#ibcon#*before return 0, iclass 33, count 0 2006.210.08:25:37.82#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:37.82#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:37.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:25:37.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:25:37.82$vc4f8/valo=2,572.99 2006.210.08:25:37.82#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:25:37.82#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:25:37.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:37.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:37.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:37.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:37.82#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:25:37.82#ibcon#first serial, iclass 35, count 0 2006.210.08:25:37.82#ibcon#enter sib2, iclass 35, count 0 2006.210.08:25:37.82#ibcon#flushed, iclass 35, count 0 2006.210.08:25:37.82#ibcon#about to write, iclass 35, count 0 2006.210.08:25:37.82#ibcon#wrote, iclass 35, count 0 2006.210.08:25:37.82#ibcon#about to read 3, iclass 35, count 0 2006.210.08:25:37.84#ibcon#read 3, iclass 35, count 0 2006.210.08:25:37.84#ibcon#about to read 4, iclass 35, count 0 2006.210.08:25:37.84#ibcon#read 4, iclass 35, count 0 2006.210.08:25:37.84#ibcon#about to read 5, iclass 35, count 0 2006.210.08:25:37.84#ibcon#read 5, iclass 35, count 0 2006.210.08:25:37.84#ibcon#about to read 6, iclass 35, count 0 2006.210.08:25:37.84#ibcon#read 6, iclass 35, count 0 2006.210.08:25:37.84#ibcon#end of sib2, iclass 35, count 0 2006.210.08:25:37.84#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:25:37.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:25:37.84#ibcon#[26=FRQ=02,572.99\r\n] 2006.210.08:25:37.84#ibcon#*before write, iclass 35, count 0 2006.210.08:25:37.84#ibcon#enter sib2, iclass 35, count 0 2006.210.08:25:37.84#ibcon#flushed, iclass 35, count 0 2006.210.08:25:37.84#ibcon#about to write, iclass 35, count 0 2006.210.08:25:37.84#ibcon#wrote, iclass 35, count 0 2006.210.08:25:37.84#ibcon#about to read 3, iclass 35, count 0 2006.210.08:25:37.88#ibcon#read 3, iclass 35, count 0 2006.210.08:25:37.88#ibcon#about to read 4, iclass 35, count 0 2006.210.08:25:37.88#ibcon#read 4, iclass 35, count 0 2006.210.08:25:37.88#ibcon#about to read 5, iclass 35, count 0 2006.210.08:25:37.88#ibcon#read 5, iclass 35, count 0 2006.210.08:25:37.88#ibcon#about to read 6, iclass 35, count 0 2006.210.08:25:37.88#ibcon#read 6, iclass 35, count 0 2006.210.08:25:37.88#ibcon#end of sib2, iclass 35, count 0 2006.210.08:25:37.88#ibcon#*after write, iclass 35, count 0 2006.210.08:25:37.88#ibcon#*before return 0, iclass 35, count 0 2006.210.08:25:37.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:37.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:37.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:25:37.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:25:37.88$vc4f8/va=2,7 2006.210.08:25:37.88#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.08:25:37.88#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.08:25:37.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:37.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:37.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:37.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:37.94#ibcon#enter wrdev, iclass 37, count 2 2006.210.08:25:37.94#ibcon#first serial, iclass 37, count 2 2006.210.08:25:37.94#ibcon#enter sib2, iclass 37, count 2 2006.210.08:25:37.94#ibcon#flushed, iclass 37, count 2 2006.210.08:25:37.94#ibcon#about to write, iclass 37, count 2 2006.210.08:25:37.94#ibcon#wrote, iclass 37, count 2 2006.210.08:25:37.94#ibcon#about to read 3, iclass 37, count 2 2006.210.08:25:37.96#ibcon#read 3, iclass 37, count 2 2006.210.08:25:37.96#ibcon#about to read 4, iclass 37, count 2 2006.210.08:25:37.96#ibcon#read 4, iclass 37, count 2 2006.210.08:25:37.96#ibcon#about to read 5, iclass 37, count 2 2006.210.08:25:37.96#ibcon#read 5, iclass 37, count 2 2006.210.08:25:37.96#ibcon#about to read 6, iclass 37, count 2 2006.210.08:25:37.96#ibcon#read 6, iclass 37, count 2 2006.210.08:25:37.96#ibcon#end of sib2, iclass 37, count 2 2006.210.08:25:37.96#ibcon#*mode == 0, iclass 37, count 2 2006.210.08:25:37.96#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.08:25:37.96#ibcon#[25=AT02-07\r\n] 2006.210.08:25:37.96#ibcon#*before write, iclass 37, count 2 2006.210.08:25:37.96#ibcon#enter sib2, iclass 37, count 2 2006.210.08:25:37.96#ibcon#flushed, iclass 37, count 2 2006.210.08:25:37.96#ibcon#about to write, iclass 37, count 2 2006.210.08:25:37.96#ibcon#wrote, iclass 37, count 2 2006.210.08:25:37.96#ibcon#about to read 3, iclass 37, count 2 2006.210.08:25:37.99#ibcon#read 3, iclass 37, count 2 2006.210.08:25:37.99#ibcon#about to read 4, iclass 37, count 2 2006.210.08:25:37.99#ibcon#read 4, iclass 37, count 2 2006.210.08:25:37.99#ibcon#about to read 5, iclass 37, count 2 2006.210.08:25:37.99#ibcon#read 5, iclass 37, count 2 2006.210.08:25:37.99#ibcon#about to read 6, iclass 37, count 2 2006.210.08:25:37.99#ibcon#read 6, iclass 37, count 2 2006.210.08:25:37.99#ibcon#end of sib2, iclass 37, count 2 2006.210.08:25:37.99#ibcon#*after write, iclass 37, count 2 2006.210.08:25:37.99#ibcon#*before return 0, iclass 37, count 2 2006.210.08:25:37.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:37.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:37.99#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.08:25:37.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:37.99#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:38.11#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:38.11#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:38.11#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:25:38.11#ibcon#first serial, iclass 37, count 0 2006.210.08:25:38.11#ibcon#enter sib2, iclass 37, count 0 2006.210.08:25:38.11#ibcon#flushed, iclass 37, count 0 2006.210.08:25:38.11#ibcon#about to write, iclass 37, count 0 2006.210.08:25:38.11#ibcon#wrote, iclass 37, count 0 2006.210.08:25:38.11#ibcon#about to read 3, iclass 37, count 0 2006.210.08:25:38.13#ibcon#read 3, iclass 37, count 0 2006.210.08:25:38.13#ibcon#about to read 4, iclass 37, count 0 2006.210.08:25:38.13#ibcon#read 4, iclass 37, count 0 2006.210.08:25:38.13#ibcon#about to read 5, iclass 37, count 0 2006.210.08:25:38.13#ibcon#read 5, iclass 37, count 0 2006.210.08:25:38.13#ibcon#about to read 6, iclass 37, count 0 2006.210.08:25:38.13#ibcon#read 6, iclass 37, count 0 2006.210.08:25:38.13#ibcon#end of sib2, iclass 37, count 0 2006.210.08:25:38.13#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:25:38.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:25:38.13#ibcon#[25=USB\r\n] 2006.210.08:25:38.13#ibcon#*before write, iclass 37, count 0 2006.210.08:25:38.13#ibcon#enter sib2, iclass 37, count 0 2006.210.08:25:38.13#ibcon#flushed, iclass 37, count 0 2006.210.08:25:38.13#ibcon#about to write, iclass 37, count 0 2006.210.08:25:38.13#ibcon#wrote, iclass 37, count 0 2006.210.08:25:38.13#ibcon#about to read 3, iclass 37, count 0 2006.210.08:25:38.16#ibcon#read 3, iclass 37, count 0 2006.210.08:25:38.16#ibcon#about to read 4, iclass 37, count 0 2006.210.08:25:38.16#ibcon#read 4, iclass 37, count 0 2006.210.08:25:38.16#ibcon#about to read 5, iclass 37, count 0 2006.210.08:25:38.16#ibcon#read 5, iclass 37, count 0 2006.210.08:25:38.16#ibcon#about to read 6, iclass 37, count 0 2006.210.08:25:38.16#ibcon#read 6, iclass 37, count 0 2006.210.08:25:38.16#ibcon#end of sib2, iclass 37, count 0 2006.210.08:25:38.16#ibcon#*after write, iclass 37, count 0 2006.210.08:25:38.16#ibcon#*before return 0, iclass 37, count 0 2006.210.08:25:38.16#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:38.16#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:38.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:25:38.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:25:38.16$vc4f8/valo=3,672.99 2006.210.08:25:38.16#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.08:25:38.16#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.08:25:38.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:38.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:38.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:38.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:38.16#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:25:38.16#ibcon#first serial, iclass 39, count 0 2006.210.08:25:38.16#ibcon#enter sib2, iclass 39, count 0 2006.210.08:25:38.16#ibcon#flushed, iclass 39, count 0 2006.210.08:25:38.16#ibcon#about to write, iclass 39, count 0 2006.210.08:25:38.16#ibcon#wrote, iclass 39, count 0 2006.210.08:25:38.16#ibcon#about to read 3, iclass 39, count 0 2006.210.08:25:38.18#ibcon#read 3, iclass 39, count 0 2006.210.08:25:38.18#ibcon#about to read 4, iclass 39, count 0 2006.210.08:25:38.18#ibcon#read 4, iclass 39, count 0 2006.210.08:25:38.18#ibcon#about to read 5, iclass 39, count 0 2006.210.08:25:38.18#ibcon#read 5, iclass 39, count 0 2006.210.08:25:38.18#ibcon#about to read 6, iclass 39, count 0 2006.210.08:25:38.18#ibcon#read 6, iclass 39, count 0 2006.210.08:25:38.18#ibcon#end of sib2, iclass 39, count 0 2006.210.08:25:38.18#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:25:38.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:25:38.18#ibcon#[26=FRQ=03,672.99\r\n] 2006.210.08:25:38.18#ibcon#*before write, iclass 39, count 0 2006.210.08:25:38.18#ibcon#enter sib2, iclass 39, count 0 2006.210.08:25:38.18#ibcon#flushed, iclass 39, count 0 2006.210.08:25:38.18#ibcon#about to write, iclass 39, count 0 2006.210.08:25:38.18#ibcon#wrote, iclass 39, count 0 2006.210.08:25:38.18#ibcon#about to read 3, iclass 39, count 0 2006.210.08:25:38.22#ibcon#read 3, iclass 39, count 0 2006.210.08:25:38.22#ibcon#about to read 4, iclass 39, count 0 2006.210.08:25:38.22#ibcon#read 4, iclass 39, count 0 2006.210.08:25:38.22#ibcon#about to read 5, iclass 39, count 0 2006.210.08:25:38.22#ibcon#read 5, iclass 39, count 0 2006.210.08:25:38.22#ibcon#about to read 6, iclass 39, count 0 2006.210.08:25:38.22#ibcon#read 6, iclass 39, count 0 2006.210.08:25:38.22#ibcon#end of sib2, iclass 39, count 0 2006.210.08:25:38.22#ibcon#*after write, iclass 39, count 0 2006.210.08:25:38.22#ibcon#*before return 0, iclass 39, count 0 2006.210.08:25:38.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:38.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:38.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:25:38.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:25:38.22$vc4f8/va=3,6 2006.210.08:25:38.22#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.08:25:38.22#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.08:25:38.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:38.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:38.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:38.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:38.28#ibcon#enter wrdev, iclass 3, count 2 2006.210.08:25:38.28#ibcon#first serial, iclass 3, count 2 2006.210.08:25:38.28#ibcon#enter sib2, iclass 3, count 2 2006.210.08:25:38.28#ibcon#flushed, iclass 3, count 2 2006.210.08:25:38.28#ibcon#about to write, iclass 3, count 2 2006.210.08:25:38.28#ibcon#wrote, iclass 3, count 2 2006.210.08:25:38.28#ibcon#about to read 3, iclass 3, count 2 2006.210.08:25:38.30#ibcon#read 3, iclass 3, count 2 2006.210.08:25:38.30#ibcon#about to read 4, iclass 3, count 2 2006.210.08:25:38.30#ibcon#read 4, iclass 3, count 2 2006.210.08:25:38.30#ibcon#about to read 5, iclass 3, count 2 2006.210.08:25:38.30#ibcon#read 5, iclass 3, count 2 2006.210.08:25:38.30#ibcon#about to read 6, iclass 3, count 2 2006.210.08:25:38.30#ibcon#read 6, iclass 3, count 2 2006.210.08:25:38.30#ibcon#end of sib2, iclass 3, count 2 2006.210.08:25:38.30#ibcon#*mode == 0, iclass 3, count 2 2006.210.08:25:38.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.08:25:38.30#ibcon#[25=AT03-06\r\n] 2006.210.08:25:38.30#ibcon#*before write, iclass 3, count 2 2006.210.08:25:38.30#ibcon#enter sib2, iclass 3, count 2 2006.210.08:25:38.30#ibcon#flushed, iclass 3, count 2 2006.210.08:25:38.30#ibcon#about to write, iclass 3, count 2 2006.210.08:25:38.30#ibcon#wrote, iclass 3, count 2 2006.210.08:25:38.30#ibcon#about to read 3, iclass 3, count 2 2006.210.08:25:38.33#ibcon#read 3, iclass 3, count 2 2006.210.08:25:38.33#ibcon#about to read 4, iclass 3, count 2 2006.210.08:25:38.33#ibcon#read 4, iclass 3, count 2 2006.210.08:25:38.33#ibcon#about to read 5, iclass 3, count 2 2006.210.08:25:38.33#ibcon#read 5, iclass 3, count 2 2006.210.08:25:38.33#ibcon#about to read 6, iclass 3, count 2 2006.210.08:25:38.33#ibcon#read 6, iclass 3, count 2 2006.210.08:25:38.33#ibcon#end of sib2, iclass 3, count 2 2006.210.08:25:38.33#ibcon#*after write, iclass 3, count 2 2006.210.08:25:38.33#ibcon#*before return 0, iclass 3, count 2 2006.210.08:25:38.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:38.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:38.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.08:25:38.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:38.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:38.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:38.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:38.45#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:25:38.45#ibcon#first serial, iclass 3, count 0 2006.210.08:25:38.45#ibcon#enter sib2, iclass 3, count 0 2006.210.08:25:38.45#ibcon#flushed, iclass 3, count 0 2006.210.08:25:38.45#ibcon#about to write, iclass 3, count 0 2006.210.08:25:38.45#ibcon#wrote, iclass 3, count 0 2006.210.08:25:38.45#ibcon#about to read 3, iclass 3, count 0 2006.210.08:25:38.47#ibcon#read 3, iclass 3, count 0 2006.210.08:25:38.47#ibcon#about to read 4, iclass 3, count 0 2006.210.08:25:38.47#ibcon#read 4, iclass 3, count 0 2006.210.08:25:38.47#ibcon#about to read 5, iclass 3, count 0 2006.210.08:25:38.47#ibcon#read 5, iclass 3, count 0 2006.210.08:25:38.47#ibcon#about to read 6, iclass 3, count 0 2006.210.08:25:38.47#ibcon#read 6, iclass 3, count 0 2006.210.08:25:38.47#ibcon#end of sib2, iclass 3, count 0 2006.210.08:25:38.47#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:25:38.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:25:38.47#ibcon#[25=USB\r\n] 2006.210.08:25:38.47#ibcon#*before write, iclass 3, count 0 2006.210.08:25:38.47#ibcon#enter sib2, iclass 3, count 0 2006.210.08:25:38.47#ibcon#flushed, iclass 3, count 0 2006.210.08:25:38.47#ibcon#about to write, iclass 3, count 0 2006.210.08:25:38.47#ibcon#wrote, iclass 3, count 0 2006.210.08:25:38.47#ibcon#about to read 3, iclass 3, count 0 2006.210.08:25:38.50#ibcon#read 3, iclass 3, count 0 2006.210.08:25:38.50#ibcon#about to read 4, iclass 3, count 0 2006.210.08:25:38.50#ibcon#read 4, iclass 3, count 0 2006.210.08:25:38.50#ibcon#about to read 5, iclass 3, count 0 2006.210.08:25:38.50#ibcon#read 5, iclass 3, count 0 2006.210.08:25:38.50#ibcon#about to read 6, iclass 3, count 0 2006.210.08:25:38.50#ibcon#read 6, iclass 3, count 0 2006.210.08:25:38.50#ibcon#end of sib2, iclass 3, count 0 2006.210.08:25:38.50#ibcon#*after write, iclass 3, count 0 2006.210.08:25:38.50#ibcon#*before return 0, iclass 3, count 0 2006.210.08:25:38.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:38.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:38.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:25:38.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:25:38.50$vc4f8/valo=4,832.99 2006.210.08:25:38.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.08:25:38.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.08:25:38.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:38.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:38.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:38.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:38.50#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:25:38.50#ibcon#first serial, iclass 5, count 0 2006.210.08:25:38.50#ibcon#enter sib2, iclass 5, count 0 2006.210.08:25:38.50#ibcon#flushed, iclass 5, count 0 2006.210.08:25:38.50#ibcon#about to write, iclass 5, count 0 2006.210.08:25:38.50#ibcon#wrote, iclass 5, count 0 2006.210.08:25:38.50#ibcon#about to read 3, iclass 5, count 0 2006.210.08:25:38.52#ibcon#read 3, iclass 5, count 0 2006.210.08:25:38.52#ibcon#about to read 4, iclass 5, count 0 2006.210.08:25:38.52#ibcon#read 4, iclass 5, count 0 2006.210.08:25:38.52#ibcon#about to read 5, iclass 5, count 0 2006.210.08:25:38.52#ibcon#read 5, iclass 5, count 0 2006.210.08:25:38.52#ibcon#about to read 6, iclass 5, count 0 2006.210.08:25:38.52#ibcon#read 6, iclass 5, count 0 2006.210.08:25:38.52#ibcon#end of sib2, iclass 5, count 0 2006.210.08:25:38.52#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:25:38.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:25:38.52#ibcon#[26=FRQ=04,832.99\r\n] 2006.210.08:25:38.52#ibcon#*before write, iclass 5, count 0 2006.210.08:25:38.52#ibcon#enter sib2, iclass 5, count 0 2006.210.08:25:38.52#ibcon#flushed, iclass 5, count 0 2006.210.08:25:38.52#ibcon#about to write, iclass 5, count 0 2006.210.08:25:38.52#ibcon#wrote, iclass 5, count 0 2006.210.08:25:38.52#ibcon#about to read 3, iclass 5, count 0 2006.210.08:25:38.56#ibcon#read 3, iclass 5, count 0 2006.210.08:25:38.56#ibcon#about to read 4, iclass 5, count 0 2006.210.08:25:38.56#ibcon#read 4, iclass 5, count 0 2006.210.08:25:38.56#ibcon#about to read 5, iclass 5, count 0 2006.210.08:25:38.56#ibcon#read 5, iclass 5, count 0 2006.210.08:25:38.56#ibcon#about to read 6, iclass 5, count 0 2006.210.08:25:38.56#ibcon#read 6, iclass 5, count 0 2006.210.08:25:38.56#ibcon#end of sib2, iclass 5, count 0 2006.210.08:25:38.56#ibcon#*after write, iclass 5, count 0 2006.210.08:25:38.56#ibcon#*before return 0, iclass 5, count 0 2006.210.08:25:38.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:38.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:38.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:25:38.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:25:38.56$vc4f8/va=4,7 2006.210.08:25:38.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.08:25:38.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.08:25:38.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:38.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:38.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:38.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:38.62#ibcon#enter wrdev, iclass 7, count 2 2006.210.08:25:38.62#ibcon#first serial, iclass 7, count 2 2006.210.08:25:38.62#ibcon#enter sib2, iclass 7, count 2 2006.210.08:25:38.62#ibcon#flushed, iclass 7, count 2 2006.210.08:25:38.62#ibcon#about to write, iclass 7, count 2 2006.210.08:25:38.62#ibcon#wrote, iclass 7, count 2 2006.210.08:25:38.62#ibcon#about to read 3, iclass 7, count 2 2006.210.08:25:38.64#ibcon#read 3, iclass 7, count 2 2006.210.08:25:38.64#ibcon#about to read 4, iclass 7, count 2 2006.210.08:25:38.64#ibcon#read 4, iclass 7, count 2 2006.210.08:25:38.64#ibcon#about to read 5, iclass 7, count 2 2006.210.08:25:38.64#ibcon#read 5, iclass 7, count 2 2006.210.08:25:38.64#ibcon#about to read 6, iclass 7, count 2 2006.210.08:25:38.64#ibcon#read 6, iclass 7, count 2 2006.210.08:25:38.64#ibcon#end of sib2, iclass 7, count 2 2006.210.08:25:38.64#ibcon#*mode == 0, iclass 7, count 2 2006.210.08:25:38.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.08:25:38.64#ibcon#[25=AT04-07\r\n] 2006.210.08:25:38.64#ibcon#*before write, iclass 7, count 2 2006.210.08:25:38.64#ibcon#enter sib2, iclass 7, count 2 2006.210.08:25:38.64#ibcon#flushed, iclass 7, count 2 2006.210.08:25:38.64#ibcon#about to write, iclass 7, count 2 2006.210.08:25:38.64#ibcon#wrote, iclass 7, count 2 2006.210.08:25:38.64#ibcon#about to read 3, iclass 7, count 2 2006.210.08:25:38.67#ibcon#read 3, iclass 7, count 2 2006.210.08:25:38.67#ibcon#about to read 4, iclass 7, count 2 2006.210.08:25:38.67#ibcon#read 4, iclass 7, count 2 2006.210.08:25:38.67#ibcon#about to read 5, iclass 7, count 2 2006.210.08:25:38.67#ibcon#read 5, iclass 7, count 2 2006.210.08:25:38.67#ibcon#about to read 6, iclass 7, count 2 2006.210.08:25:38.67#ibcon#read 6, iclass 7, count 2 2006.210.08:25:38.67#ibcon#end of sib2, iclass 7, count 2 2006.210.08:25:38.67#ibcon#*after write, iclass 7, count 2 2006.210.08:25:38.67#ibcon#*before return 0, iclass 7, count 2 2006.210.08:25:38.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:38.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:38.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.08:25:38.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:38.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:38.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:38.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:38.79#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:25:38.79#ibcon#first serial, iclass 7, count 0 2006.210.08:25:38.79#ibcon#enter sib2, iclass 7, count 0 2006.210.08:25:38.79#ibcon#flushed, iclass 7, count 0 2006.210.08:25:38.79#ibcon#about to write, iclass 7, count 0 2006.210.08:25:38.79#ibcon#wrote, iclass 7, count 0 2006.210.08:25:38.79#ibcon#about to read 3, iclass 7, count 0 2006.210.08:25:38.81#ibcon#read 3, iclass 7, count 0 2006.210.08:25:38.81#ibcon#about to read 4, iclass 7, count 0 2006.210.08:25:38.81#ibcon#read 4, iclass 7, count 0 2006.210.08:25:38.81#ibcon#about to read 5, iclass 7, count 0 2006.210.08:25:38.81#ibcon#read 5, iclass 7, count 0 2006.210.08:25:38.81#ibcon#about to read 6, iclass 7, count 0 2006.210.08:25:38.81#ibcon#read 6, iclass 7, count 0 2006.210.08:25:38.81#ibcon#end of sib2, iclass 7, count 0 2006.210.08:25:38.81#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:25:38.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:25:38.81#ibcon#[25=USB\r\n] 2006.210.08:25:38.81#ibcon#*before write, iclass 7, count 0 2006.210.08:25:38.81#ibcon#enter sib2, iclass 7, count 0 2006.210.08:25:38.81#ibcon#flushed, iclass 7, count 0 2006.210.08:25:38.81#ibcon#about to write, iclass 7, count 0 2006.210.08:25:38.81#ibcon#wrote, iclass 7, count 0 2006.210.08:25:38.81#ibcon#about to read 3, iclass 7, count 0 2006.210.08:25:38.84#ibcon#read 3, iclass 7, count 0 2006.210.08:25:38.84#ibcon#about to read 4, iclass 7, count 0 2006.210.08:25:38.84#ibcon#read 4, iclass 7, count 0 2006.210.08:25:38.84#ibcon#about to read 5, iclass 7, count 0 2006.210.08:25:38.84#ibcon#read 5, iclass 7, count 0 2006.210.08:25:38.84#ibcon#about to read 6, iclass 7, count 0 2006.210.08:25:38.84#ibcon#read 6, iclass 7, count 0 2006.210.08:25:38.84#ibcon#end of sib2, iclass 7, count 0 2006.210.08:25:38.84#ibcon#*after write, iclass 7, count 0 2006.210.08:25:38.84#ibcon#*before return 0, iclass 7, count 0 2006.210.08:25:38.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:38.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:38.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:25:38.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:25:38.84$vc4f8/valo=5,652.99 2006.210.08:25:38.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.08:25:38.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.08:25:38.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:38.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:38.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:38.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:38.84#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:25:38.84#ibcon#first serial, iclass 11, count 0 2006.210.08:25:38.84#ibcon#enter sib2, iclass 11, count 0 2006.210.08:25:38.84#ibcon#flushed, iclass 11, count 0 2006.210.08:25:38.84#ibcon#about to write, iclass 11, count 0 2006.210.08:25:38.84#ibcon#wrote, iclass 11, count 0 2006.210.08:25:38.84#ibcon#about to read 3, iclass 11, count 0 2006.210.08:25:38.86#ibcon#read 3, iclass 11, count 0 2006.210.08:25:38.86#ibcon#about to read 4, iclass 11, count 0 2006.210.08:25:38.86#ibcon#read 4, iclass 11, count 0 2006.210.08:25:38.86#ibcon#about to read 5, iclass 11, count 0 2006.210.08:25:38.86#ibcon#read 5, iclass 11, count 0 2006.210.08:25:38.86#ibcon#about to read 6, iclass 11, count 0 2006.210.08:25:38.86#ibcon#read 6, iclass 11, count 0 2006.210.08:25:38.86#ibcon#end of sib2, iclass 11, count 0 2006.210.08:25:38.86#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:25:38.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:25:38.86#ibcon#[26=FRQ=05,652.99\r\n] 2006.210.08:25:38.86#ibcon#*before write, iclass 11, count 0 2006.210.08:25:38.86#ibcon#enter sib2, iclass 11, count 0 2006.210.08:25:38.86#ibcon#flushed, iclass 11, count 0 2006.210.08:25:38.86#ibcon#about to write, iclass 11, count 0 2006.210.08:25:38.86#ibcon#wrote, iclass 11, count 0 2006.210.08:25:38.86#ibcon#about to read 3, iclass 11, count 0 2006.210.08:25:38.90#ibcon#read 3, iclass 11, count 0 2006.210.08:25:38.90#ibcon#about to read 4, iclass 11, count 0 2006.210.08:25:38.90#ibcon#read 4, iclass 11, count 0 2006.210.08:25:38.90#ibcon#about to read 5, iclass 11, count 0 2006.210.08:25:38.90#ibcon#read 5, iclass 11, count 0 2006.210.08:25:38.90#ibcon#about to read 6, iclass 11, count 0 2006.210.08:25:38.90#ibcon#read 6, iclass 11, count 0 2006.210.08:25:38.90#ibcon#end of sib2, iclass 11, count 0 2006.210.08:25:38.90#ibcon#*after write, iclass 11, count 0 2006.210.08:25:38.90#ibcon#*before return 0, iclass 11, count 0 2006.210.08:25:38.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:38.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:38.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:25:38.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:25:38.90$vc4f8/va=5,7 2006.210.08:25:38.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.08:25:38.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.08:25:38.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:38.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:38.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:38.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:38.96#ibcon#enter wrdev, iclass 13, count 2 2006.210.08:25:38.96#ibcon#first serial, iclass 13, count 2 2006.210.08:25:38.96#ibcon#enter sib2, iclass 13, count 2 2006.210.08:25:38.96#ibcon#flushed, iclass 13, count 2 2006.210.08:25:38.96#ibcon#about to write, iclass 13, count 2 2006.210.08:25:38.96#ibcon#wrote, iclass 13, count 2 2006.210.08:25:38.96#ibcon#about to read 3, iclass 13, count 2 2006.210.08:25:38.98#ibcon#read 3, iclass 13, count 2 2006.210.08:25:38.98#ibcon#about to read 4, iclass 13, count 2 2006.210.08:25:38.98#ibcon#read 4, iclass 13, count 2 2006.210.08:25:38.98#ibcon#about to read 5, iclass 13, count 2 2006.210.08:25:38.98#ibcon#read 5, iclass 13, count 2 2006.210.08:25:38.98#ibcon#about to read 6, iclass 13, count 2 2006.210.08:25:38.98#ibcon#read 6, iclass 13, count 2 2006.210.08:25:38.98#ibcon#end of sib2, iclass 13, count 2 2006.210.08:25:38.98#ibcon#*mode == 0, iclass 13, count 2 2006.210.08:25:38.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.08:25:38.98#ibcon#[25=AT05-07\r\n] 2006.210.08:25:38.98#ibcon#*before write, iclass 13, count 2 2006.210.08:25:38.98#ibcon#enter sib2, iclass 13, count 2 2006.210.08:25:38.98#ibcon#flushed, iclass 13, count 2 2006.210.08:25:38.98#ibcon#about to write, iclass 13, count 2 2006.210.08:25:38.98#ibcon#wrote, iclass 13, count 2 2006.210.08:25:38.98#ibcon#about to read 3, iclass 13, count 2 2006.210.08:25:39.01#ibcon#read 3, iclass 13, count 2 2006.210.08:25:39.01#ibcon#about to read 4, iclass 13, count 2 2006.210.08:25:39.01#ibcon#read 4, iclass 13, count 2 2006.210.08:25:39.01#ibcon#about to read 5, iclass 13, count 2 2006.210.08:25:39.01#ibcon#read 5, iclass 13, count 2 2006.210.08:25:39.01#ibcon#about to read 6, iclass 13, count 2 2006.210.08:25:39.01#ibcon#read 6, iclass 13, count 2 2006.210.08:25:39.01#ibcon#end of sib2, iclass 13, count 2 2006.210.08:25:39.01#ibcon#*after write, iclass 13, count 2 2006.210.08:25:39.01#ibcon#*before return 0, iclass 13, count 2 2006.210.08:25:39.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:39.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:39.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.08:25:39.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:39.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:39.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:39.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:39.13#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:25:39.13#ibcon#first serial, iclass 13, count 0 2006.210.08:25:39.13#ibcon#enter sib2, iclass 13, count 0 2006.210.08:25:39.13#ibcon#flushed, iclass 13, count 0 2006.210.08:25:39.13#ibcon#about to write, iclass 13, count 0 2006.210.08:25:39.13#ibcon#wrote, iclass 13, count 0 2006.210.08:25:39.13#ibcon#about to read 3, iclass 13, count 0 2006.210.08:25:39.15#ibcon#read 3, iclass 13, count 0 2006.210.08:25:39.15#ibcon#about to read 4, iclass 13, count 0 2006.210.08:25:39.15#ibcon#read 4, iclass 13, count 0 2006.210.08:25:39.15#ibcon#about to read 5, iclass 13, count 0 2006.210.08:25:39.15#ibcon#read 5, iclass 13, count 0 2006.210.08:25:39.15#ibcon#about to read 6, iclass 13, count 0 2006.210.08:25:39.15#ibcon#read 6, iclass 13, count 0 2006.210.08:25:39.15#ibcon#end of sib2, iclass 13, count 0 2006.210.08:25:39.15#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:25:39.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:25:39.15#ibcon#[25=USB\r\n] 2006.210.08:25:39.15#ibcon#*before write, iclass 13, count 0 2006.210.08:25:39.15#ibcon#enter sib2, iclass 13, count 0 2006.210.08:25:39.15#ibcon#flushed, iclass 13, count 0 2006.210.08:25:39.15#ibcon#about to write, iclass 13, count 0 2006.210.08:25:39.15#ibcon#wrote, iclass 13, count 0 2006.210.08:25:39.15#ibcon#about to read 3, iclass 13, count 0 2006.210.08:25:39.18#ibcon#read 3, iclass 13, count 0 2006.210.08:25:39.18#ibcon#about to read 4, iclass 13, count 0 2006.210.08:25:39.18#ibcon#read 4, iclass 13, count 0 2006.210.08:25:39.18#ibcon#about to read 5, iclass 13, count 0 2006.210.08:25:39.18#ibcon#read 5, iclass 13, count 0 2006.210.08:25:39.18#ibcon#about to read 6, iclass 13, count 0 2006.210.08:25:39.18#ibcon#read 6, iclass 13, count 0 2006.210.08:25:39.18#ibcon#end of sib2, iclass 13, count 0 2006.210.08:25:39.18#ibcon#*after write, iclass 13, count 0 2006.210.08:25:39.18#ibcon#*before return 0, iclass 13, count 0 2006.210.08:25:39.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:39.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:39.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:25:39.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:25:39.18$vc4f8/valo=6,772.99 2006.210.08:25:39.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.08:25:39.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.08:25:39.18#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:39.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:39.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:39.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:39.18#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:25:39.18#ibcon#first serial, iclass 15, count 0 2006.210.08:25:39.18#ibcon#enter sib2, iclass 15, count 0 2006.210.08:25:39.18#ibcon#flushed, iclass 15, count 0 2006.210.08:25:39.18#ibcon#about to write, iclass 15, count 0 2006.210.08:25:39.18#ibcon#wrote, iclass 15, count 0 2006.210.08:25:39.18#ibcon#about to read 3, iclass 15, count 0 2006.210.08:25:39.20#ibcon#read 3, iclass 15, count 0 2006.210.08:25:39.20#ibcon#about to read 4, iclass 15, count 0 2006.210.08:25:39.20#ibcon#read 4, iclass 15, count 0 2006.210.08:25:39.20#ibcon#about to read 5, iclass 15, count 0 2006.210.08:25:39.20#ibcon#read 5, iclass 15, count 0 2006.210.08:25:39.20#ibcon#about to read 6, iclass 15, count 0 2006.210.08:25:39.20#ibcon#read 6, iclass 15, count 0 2006.210.08:25:39.20#ibcon#end of sib2, iclass 15, count 0 2006.210.08:25:39.20#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:25:39.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:25:39.20#ibcon#[26=FRQ=06,772.99\r\n] 2006.210.08:25:39.20#ibcon#*before write, iclass 15, count 0 2006.210.08:25:39.20#ibcon#enter sib2, iclass 15, count 0 2006.210.08:25:39.20#ibcon#flushed, iclass 15, count 0 2006.210.08:25:39.20#ibcon#about to write, iclass 15, count 0 2006.210.08:25:39.20#ibcon#wrote, iclass 15, count 0 2006.210.08:25:39.20#ibcon#about to read 3, iclass 15, count 0 2006.210.08:25:39.24#ibcon#read 3, iclass 15, count 0 2006.210.08:25:39.24#ibcon#about to read 4, iclass 15, count 0 2006.210.08:25:39.24#ibcon#read 4, iclass 15, count 0 2006.210.08:25:39.24#ibcon#about to read 5, iclass 15, count 0 2006.210.08:25:39.24#ibcon#read 5, iclass 15, count 0 2006.210.08:25:39.24#ibcon#about to read 6, iclass 15, count 0 2006.210.08:25:39.24#ibcon#read 6, iclass 15, count 0 2006.210.08:25:39.24#ibcon#end of sib2, iclass 15, count 0 2006.210.08:25:39.24#ibcon#*after write, iclass 15, count 0 2006.210.08:25:39.24#ibcon#*before return 0, iclass 15, count 0 2006.210.08:25:39.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:39.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:39.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:25:39.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:25:39.24$vc4f8/va=6,6 2006.210.08:25:39.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.210.08:25:39.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.210.08:25:39.24#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:39.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:25:39.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:25:39.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:25:39.30#ibcon#enter wrdev, iclass 17, count 2 2006.210.08:25:39.30#ibcon#first serial, iclass 17, count 2 2006.210.08:25:39.30#ibcon#enter sib2, iclass 17, count 2 2006.210.08:25:39.30#ibcon#flushed, iclass 17, count 2 2006.210.08:25:39.30#ibcon#about to write, iclass 17, count 2 2006.210.08:25:39.30#ibcon#wrote, iclass 17, count 2 2006.210.08:25:39.30#ibcon#about to read 3, iclass 17, count 2 2006.210.08:25:39.32#ibcon#read 3, iclass 17, count 2 2006.210.08:25:39.32#ibcon#about to read 4, iclass 17, count 2 2006.210.08:25:39.32#ibcon#read 4, iclass 17, count 2 2006.210.08:25:39.32#ibcon#about to read 5, iclass 17, count 2 2006.210.08:25:39.32#ibcon#read 5, iclass 17, count 2 2006.210.08:25:39.32#ibcon#about to read 6, iclass 17, count 2 2006.210.08:25:39.32#ibcon#read 6, iclass 17, count 2 2006.210.08:25:39.32#ibcon#end of sib2, iclass 17, count 2 2006.210.08:25:39.32#ibcon#*mode == 0, iclass 17, count 2 2006.210.08:25:39.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.210.08:25:39.32#ibcon#[25=AT06-06\r\n] 2006.210.08:25:39.32#ibcon#*before write, iclass 17, count 2 2006.210.08:25:39.32#ibcon#enter sib2, iclass 17, count 2 2006.210.08:25:39.32#ibcon#flushed, iclass 17, count 2 2006.210.08:25:39.32#ibcon#about to write, iclass 17, count 2 2006.210.08:25:39.32#ibcon#wrote, iclass 17, count 2 2006.210.08:25:39.32#ibcon#about to read 3, iclass 17, count 2 2006.210.08:25:39.35#ibcon#read 3, iclass 17, count 2 2006.210.08:25:39.35#ibcon#about to read 4, iclass 17, count 2 2006.210.08:25:39.35#ibcon#read 4, iclass 17, count 2 2006.210.08:25:39.35#ibcon#about to read 5, iclass 17, count 2 2006.210.08:25:39.35#ibcon#read 5, iclass 17, count 2 2006.210.08:25:39.35#ibcon#about to read 6, iclass 17, count 2 2006.210.08:25:39.35#ibcon#read 6, iclass 17, count 2 2006.210.08:25:39.35#ibcon#end of sib2, iclass 17, count 2 2006.210.08:25:39.35#ibcon#*after write, iclass 17, count 2 2006.210.08:25:39.35#ibcon#*before return 0, iclass 17, count 2 2006.210.08:25:39.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:25:39.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.210.08:25:39.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.210.08:25:39.35#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:39.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:25:39.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:25:39.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:25:39.47#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:25:39.47#ibcon#first serial, iclass 17, count 0 2006.210.08:25:39.47#ibcon#enter sib2, iclass 17, count 0 2006.210.08:25:39.47#ibcon#flushed, iclass 17, count 0 2006.210.08:25:39.47#ibcon#about to write, iclass 17, count 0 2006.210.08:25:39.47#ibcon#wrote, iclass 17, count 0 2006.210.08:25:39.47#ibcon#about to read 3, iclass 17, count 0 2006.210.08:25:39.49#ibcon#read 3, iclass 17, count 0 2006.210.08:25:39.49#ibcon#about to read 4, iclass 17, count 0 2006.210.08:25:39.49#ibcon#read 4, iclass 17, count 0 2006.210.08:25:39.49#ibcon#about to read 5, iclass 17, count 0 2006.210.08:25:39.49#ibcon#read 5, iclass 17, count 0 2006.210.08:25:39.49#ibcon#about to read 6, iclass 17, count 0 2006.210.08:25:39.49#ibcon#read 6, iclass 17, count 0 2006.210.08:25:39.49#ibcon#end of sib2, iclass 17, count 0 2006.210.08:25:39.49#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:25:39.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:25:39.49#ibcon#[25=USB\r\n] 2006.210.08:25:39.49#ibcon#*before write, iclass 17, count 0 2006.210.08:25:39.49#ibcon#enter sib2, iclass 17, count 0 2006.210.08:25:39.49#ibcon#flushed, iclass 17, count 0 2006.210.08:25:39.49#ibcon#about to write, iclass 17, count 0 2006.210.08:25:39.49#ibcon#wrote, iclass 17, count 0 2006.210.08:25:39.49#ibcon#about to read 3, iclass 17, count 0 2006.210.08:25:39.52#ibcon#read 3, iclass 17, count 0 2006.210.08:25:39.52#ibcon#about to read 4, iclass 17, count 0 2006.210.08:25:39.52#ibcon#read 4, iclass 17, count 0 2006.210.08:25:39.52#ibcon#about to read 5, iclass 17, count 0 2006.210.08:25:39.52#ibcon#read 5, iclass 17, count 0 2006.210.08:25:39.52#ibcon#about to read 6, iclass 17, count 0 2006.210.08:25:39.52#ibcon#read 6, iclass 17, count 0 2006.210.08:25:39.52#ibcon#end of sib2, iclass 17, count 0 2006.210.08:25:39.52#ibcon#*after write, iclass 17, count 0 2006.210.08:25:39.52#ibcon#*before return 0, iclass 17, count 0 2006.210.08:25:39.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:25:39.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.210.08:25:39.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:25:39.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:25:39.52$vc4f8/valo=7,832.99 2006.210.08:25:39.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.210.08:25:39.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.210.08:25:39.52#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:39.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:25:39.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:25:39.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:25:39.52#ibcon#enter wrdev, iclass 19, count 0 2006.210.08:25:39.52#ibcon#first serial, iclass 19, count 0 2006.210.08:25:39.52#ibcon#enter sib2, iclass 19, count 0 2006.210.08:25:39.52#ibcon#flushed, iclass 19, count 0 2006.210.08:25:39.52#ibcon#about to write, iclass 19, count 0 2006.210.08:25:39.52#ibcon#wrote, iclass 19, count 0 2006.210.08:25:39.52#ibcon#about to read 3, iclass 19, count 0 2006.210.08:25:39.54#ibcon#read 3, iclass 19, count 0 2006.210.08:25:39.54#ibcon#about to read 4, iclass 19, count 0 2006.210.08:25:39.54#ibcon#read 4, iclass 19, count 0 2006.210.08:25:39.54#ibcon#about to read 5, iclass 19, count 0 2006.210.08:25:39.54#ibcon#read 5, iclass 19, count 0 2006.210.08:25:39.54#ibcon#about to read 6, iclass 19, count 0 2006.210.08:25:39.54#ibcon#read 6, iclass 19, count 0 2006.210.08:25:39.54#ibcon#end of sib2, iclass 19, count 0 2006.210.08:25:39.54#ibcon#*mode == 0, iclass 19, count 0 2006.210.08:25:39.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.210.08:25:39.54#ibcon#[26=FRQ=07,832.99\r\n] 2006.210.08:25:39.54#ibcon#*before write, iclass 19, count 0 2006.210.08:25:39.54#ibcon#enter sib2, iclass 19, count 0 2006.210.08:25:39.54#ibcon#flushed, iclass 19, count 0 2006.210.08:25:39.54#ibcon#about to write, iclass 19, count 0 2006.210.08:25:39.54#ibcon#wrote, iclass 19, count 0 2006.210.08:25:39.54#ibcon#about to read 3, iclass 19, count 0 2006.210.08:25:39.58#ibcon#read 3, iclass 19, count 0 2006.210.08:25:39.58#ibcon#about to read 4, iclass 19, count 0 2006.210.08:25:39.58#ibcon#read 4, iclass 19, count 0 2006.210.08:25:39.58#ibcon#about to read 5, iclass 19, count 0 2006.210.08:25:39.58#ibcon#read 5, iclass 19, count 0 2006.210.08:25:39.58#ibcon#about to read 6, iclass 19, count 0 2006.210.08:25:39.58#ibcon#read 6, iclass 19, count 0 2006.210.08:25:39.58#ibcon#end of sib2, iclass 19, count 0 2006.210.08:25:39.58#ibcon#*after write, iclass 19, count 0 2006.210.08:25:39.58#ibcon#*before return 0, iclass 19, count 0 2006.210.08:25:39.58#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:25:39.58#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.210.08:25:39.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.210.08:25:39.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.210.08:25:39.58$vc4f8/va=7,6 2006.210.08:25:39.58#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.210.08:25:39.58#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.210.08:25:39.58#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:39.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:25:39.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:25:39.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:25:39.64#ibcon#enter wrdev, iclass 21, count 2 2006.210.08:25:39.64#ibcon#first serial, iclass 21, count 2 2006.210.08:25:39.64#ibcon#enter sib2, iclass 21, count 2 2006.210.08:25:39.64#ibcon#flushed, iclass 21, count 2 2006.210.08:25:39.64#ibcon#about to write, iclass 21, count 2 2006.210.08:25:39.64#ibcon#wrote, iclass 21, count 2 2006.210.08:25:39.64#ibcon#about to read 3, iclass 21, count 2 2006.210.08:25:39.66#ibcon#read 3, iclass 21, count 2 2006.210.08:25:39.66#ibcon#about to read 4, iclass 21, count 2 2006.210.08:25:39.66#ibcon#read 4, iclass 21, count 2 2006.210.08:25:39.66#ibcon#about to read 5, iclass 21, count 2 2006.210.08:25:39.66#ibcon#read 5, iclass 21, count 2 2006.210.08:25:39.66#ibcon#about to read 6, iclass 21, count 2 2006.210.08:25:39.66#ibcon#read 6, iclass 21, count 2 2006.210.08:25:39.66#ibcon#end of sib2, iclass 21, count 2 2006.210.08:25:39.66#ibcon#*mode == 0, iclass 21, count 2 2006.210.08:25:39.66#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.210.08:25:39.66#ibcon#[25=AT07-06\r\n] 2006.210.08:25:39.66#ibcon#*before write, iclass 21, count 2 2006.210.08:25:39.66#ibcon#enter sib2, iclass 21, count 2 2006.210.08:25:39.66#ibcon#flushed, iclass 21, count 2 2006.210.08:25:39.66#ibcon#about to write, iclass 21, count 2 2006.210.08:25:39.66#ibcon#wrote, iclass 21, count 2 2006.210.08:25:39.66#ibcon#about to read 3, iclass 21, count 2 2006.210.08:25:39.69#ibcon#read 3, iclass 21, count 2 2006.210.08:25:39.69#ibcon#about to read 4, iclass 21, count 2 2006.210.08:25:39.69#ibcon#read 4, iclass 21, count 2 2006.210.08:25:39.69#ibcon#about to read 5, iclass 21, count 2 2006.210.08:25:39.69#ibcon#read 5, iclass 21, count 2 2006.210.08:25:39.69#ibcon#about to read 6, iclass 21, count 2 2006.210.08:25:39.69#ibcon#read 6, iclass 21, count 2 2006.210.08:25:39.69#ibcon#end of sib2, iclass 21, count 2 2006.210.08:25:39.69#ibcon#*after write, iclass 21, count 2 2006.210.08:25:39.69#ibcon#*before return 0, iclass 21, count 2 2006.210.08:25:39.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:25:39.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.210.08:25:39.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.210.08:25:39.69#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:39.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:25:39.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:25:39.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:25:39.81#ibcon#enter wrdev, iclass 21, count 0 2006.210.08:25:39.81#ibcon#first serial, iclass 21, count 0 2006.210.08:25:39.81#ibcon#enter sib2, iclass 21, count 0 2006.210.08:25:39.81#ibcon#flushed, iclass 21, count 0 2006.210.08:25:39.81#ibcon#about to write, iclass 21, count 0 2006.210.08:25:39.81#ibcon#wrote, iclass 21, count 0 2006.210.08:25:39.81#ibcon#about to read 3, iclass 21, count 0 2006.210.08:25:39.83#ibcon#read 3, iclass 21, count 0 2006.210.08:25:39.83#ibcon#about to read 4, iclass 21, count 0 2006.210.08:25:39.83#ibcon#read 4, iclass 21, count 0 2006.210.08:25:39.83#ibcon#about to read 5, iclass 21, count 0 2006.210.08:25:39.83#ibcon#read 5, iclass 21, count 0 2006.210.08:25:39.83#ibcon#about to read 6, iclass 21, count 0 2006.210.08:25:39.83#ibcon#read 6, iclass 21, count 0 2006.210.08:25:39.83#ibcon#end of sib2, iclass 21, count 0 2006.210.08:25:39.83#ibcon#*mode == 0, iclass 21, count 0 2006.210.08:25:39.83#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.210.08:25:39.83#ibcon#[25=USB\r\n] 2006.210.08:25:39.83#ibcon#*before write, iclass 21, count 0 2006.210.08:25:39.83#ibcon#enter sib2, iclass 21, count 0 2006.210.08:25:39.83#ibcon#flushed, iclass 21, count 0 2006.210.08:25:39.83#ibcon#about to write, iclass 21, count 0 2006.210.08:25:39.83#ibcon#wrote, iclass 21, count 0 2006.210.08:25:39.83#ibcon#about to read 3, iclass 21, count 0 2006.210.08:25:39.86#ibcon#read 3, iclass 21, count 0 2006.210.08:25:39.86#ibcon#about to read 4, iclass 21, count 0 2006.210.08:25:39.86#ibcon#read 4, iclass 21, count 0 2006.210.08:25:39.86#ibcon#about to read 5, iclass 21, count 0 2006.210.08:25:39.86#ibcon#read 5, iclass 21, count 0 2006.210.08:25:39.86#ibcon#about to read 6, iclass 21, count 0 2006.210.08:25:39.86#ibcon#read 6, iclass 21, count 0 2006.210.08:25:39.86#ibcon#end of sib2, iclass 21, count 0 2006.210.08:25:39.86#ibcon#*after write, iclass 21, count 0 2006.210.08:25:39.86#ibcon#*before return 0, iclass 21, count 0 2006.210.08:25:39.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:25:39.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.210.08:25:39.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.210.08:25:39.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.210.08:25:39.86$vc4f8/valo=8,852.99 2006.210.08:25:39.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.210.08:25:39.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.210.08:25:39.86#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:39.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:25:39.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:25:39.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:25:39.86#ibcon#enter wrdev, iclass 23, count 0 2006.210.08:25:39.86#ibcon#first serial, iclass 23, count 0 2006.210.08:25:39.86#ibcon#enter sib2, iclass 23, count 0 2006.210.08:25:39.86#ibcon#flushed, iclass 23, count 0 2006.210.08:25:39.86#ibcon#about to write, iclass 23, count 0 2006.210.08:25:39.86#ibcon#wrote, iclass 23, count 0 2006.210.08:25:39.86#ibcon#about to read 3, iclass 23, count 0 2006.210.08:25:39.88#ibcon#read 3, iclass 23, count 0 2006.210.08:25:39.88#ibcon#about to read 4, iclass 23, count 0 2006.210.08:25:39.88#ibcon#read 4, iclass 23, count 0 2006.210.08:25:39.88#ibcon#about to read 5, iclass 23, count 0 2006.210.08:25:39.88#ibcon#read 5, iclass 23, count 0 2006.210.08:25:39.88#ibcon#about to read 6, iclass 23, count 0 2006.210.08:25:39.88#ibcon#read 6, iclass 23, count 0 2006.210.08:25:39.88#ibcon#end of sib2, iclass 23, count 0 2006.210.08:25:39.88#ibcon#*mode == 0, iclass 23, count 0 2006.210.08:25:39.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.210.08:25:39.88#ibcon#[26=FRQ=08,852.99\r\n] 2006.210.08:25:39.88#ibcon#*before write, iclass 23, count 0 2006.210.08:25:39.88#ibcon#enter sib2, iclass 23, count 0 2006.210.08:25:39.88#ibcon#flushed, iclass 23, count 0 2006.210.08:25:39.88#ibcon#about to write, iclass 23, count 0 2006.210.08:25:39.88#ibcon#wrote, iclass 23, count 0 2006.210.08:25:39.88#ibcon#about to read 3, iclass 23, count 0 2006.210.08:25:39.92#ibcon#read 3, iclass 23, count 0 2006.210.08:25:39.92#ibcon#about to read 4, iclass 23, count 0 2006.210.08:25:39.92#ibcon#read 4, iclass 23, count 0 2006.210.08:25:39.92#ibcon#about to read 5, iclass 23, count 0 2006.210.08:25:39.92#ibcon#read 5, iclass 23, count 0 2006.210.08:25:39.92#ibcon#about to read 6, iclass 23, count 0 2006.210.08:25:39.92#ibcon#read 6, iclass 23, count 0 2006.210.08:25:39.92#ibcon#end of sib2, iclass 23, count 0 2006.210.08:25:39.92#ibcon#*after write, iclass 23, count 0 2006.210.08:25:39.92#ibcon#*before return 0, iclass 23, count 0 2006.210.08:25:39.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:25:39.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.210.08:25:39.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.210.08:25:39.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.210.08:25:39.92$vc4f8/va=8,7 2006.210.08:25:39.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.210.08:25:39.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.210.08:25:39.92#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:39.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:25:39.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:25:39.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:25:39.98#ibcon#enter wrdev, iclass 25, count 2 2006.210.08:25:39.98#ibcon#first serial, iclass 25, count 2 2006.210.08:25:39.98#ibcon#enter sib2, iclass 25, count 2 2006.210.08:25:39.98#ibcon#flushed, iclass 25, count 2 2006.210.08:25:39.98#ibcon#about to write, iclass 25, count 2 2006.210.08:25:39.98#ibcon#wrote, iclass 25, count 2 2006.210.08:25:39.98#ibcon#about to read 3, iclass 25, count 2 2006.210.08:25:40.00#ibcon#read 3, iclass 25, count 2 2006.210.08:25:40.00#ibcon#about to read 4, iclass 25, count 2 2006.210.08:25:40.00#ibcon#read 4, iclass 25, count 2 2006.210.08:25:40.00#ibcon#about to read 5, iclass 25, count 2 2006.210.08:25:40.00#ibcon#read 5, iclass 25, count 2 2006.210.08:25:40.00#ibcon#about to read 6, iclass 25, count 2 2006.210.08:25:40.00#ibcon#read 6, iclass 25, count 2 2006.210.08:25:40.00#ibcon#end of sib2, iclass 25, count 2 2006.210.08:25:40.00#ibcon#*mode == 0, iclass 25, count 2 2006.210.08:25:40.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.210.08:25:40.00#ibcon#[25=AT08-07\r\n] 2006.210.08:25:40.00#ibcon#*before write, iclass 25, count 2 2006.210.08:25:40.00#ibcon#enter sib2, iclass 25, count 2 2006.210.08:25:40.00#ibcon#flushed, iclass 25, count 2 2006.210.08:25:40.00#ibcon#about to write, iclass 25, count 2 2006.210.08:25:40.00#ibcon#wrote, iclass 25, count 2 2006.210.08:25:40.00#ibcon#about to read 3, iclass 25, count 2 2006.210.08:25:40.03#ibcon#read 3, iclass 25, count 2 2006.210.08:25:40.03#ibcon#about to read 4, iclass 25, count 2 2006.210.08:25:40.03#ibcon#read 4, iclass 25, count 2 2006.210.08:25:40.03#ibcon#about to read 5, iclass 25, count 2 2006.210.08:25:40.03#ibcon#read 5, iclass 25, count 2 2006.210.08:25:40.03#ibcon#about to read 6, iclass 25, count 2 2006.210.08:25:40.03#ibcon#read 6, iclass 25, count 2 2006.210.08:25:40.03#ibcon#end of sib2, iclass 25, count 2 2006.210.08:25:40.03#ibcon#*after write, iclass 25, count 2 2006.210.08:25:40.03#ibcon#*before return 0, iclass 25, count 2 2006.210.08:25:40.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:25:40.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.210.08:25:40.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.210.08:25:40.03#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:40.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:25:40.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:25:40.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:25:40.15#ibcon#enter wrdev, iclass 25, count 0 2006.210.08:25:40.15#ibcon#first serial, iclass 25, count 0 2006.210.08:25:40.15#ibcon#enter sib2, iclass 25, count 0 2006.210.08:25:40.15#ibcon#flushed, iclass 25, count 0 2006.210.08:25:40.15#ibcon#about to write, iclass 25, count 0 2006.210.08:25:40.15#ibcon#wrote, iclass 25, count 0 2006.210.08:25:40.15#ibcon#about to read 3, iclass 25, count 0 2006.210.08:25:40.17#ibcon#read 3, iclass 25, count 0 2006.210.08:25:40.17#ibcon#about to read 4, iclass 25, count 0 2006.210.08:25:40.17#ibcon#read 4, iclass 25, count 0 2006.210.08:25:40.17#ibcon#about to read 5, iclass 25, count 0 2006.210.08:25:40.17#ibcon#read 5, iclass 25, count 0 2006.210.08:25:40.17#ibcon#about to read 6, iclass 25, count 0 2006.210.08:25:40.17#ibcon#read 6, iclass 25, count 0 2006.210.08:25:40.17#ibcon#end of sib2, iclass 25, count 0 2006.210.08:25:40.17#ibcon#*mode == 0, iclass 25, count 0 2006.210.08:25:40.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.210.08:25:40.17#ibcon#[25=USB\r\n] 2006.210.08:25:40.17#ibcon#*before write, iclass 25, count 0 2006.210.08:25:40.17#ibcon#enter sib2, iclass 25, count 0 2006.210.08:25:40.17#ibcon#flushed, iclass 25, count 0 2006.210.08:25:40.17#ibcon#about to write, iclass 25, count 0 2006.210.08:25:40.17#ibcon#wrote, iclass 25, count 0 2006.210.08:25:40.17#ibcon#about to read 3, iclass 25, count 0 2006.210.08:25:40.20#ibcon#read 3, iclass 25, count 0 2006.210.08:25:40.20#ibcon#about to read 4, iclass 25, count 0 2006.210.08:25:40.20#ibcon#read 4, iclass 25, count 0 2006.210.08:25:40.20#ibcon#about to read 5, iclass 25, count 0 2006.210.08:25:40.20#ibcon#read 5, iclass 25, count 0 2006.210.08:25:40.20#ibcon#about to read 6, iclass 25, count 0 2006.210.08:25:40.20#ibcon#read 6, iclass 25, count 0 2006.210.08:25:40.20#ibcon#end of sib2, iclass 25, count 0 2006.210.08:25:40.20#ibcon#*after write, iclass 25, count 0 2006.210.08:25:40.20#ibcon#*before return 0, iclass 25, count 0 2006.210.08:25:40.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:25:40.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.210.08:25:40.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.210.08:25:40.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.210.08:25:40.20$vc4f8/vblo=1,632.99 2006.210.08:25:40.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.210.08:25:40.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.210.08:25:40.20#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:40.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:25:40.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:25:40.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:25:40.20#ibcon#enter wrdev, iclass 27, count 0 2006.210.08:25:40.20#ibcon#first serial, iclass 27, count 0 2006.210.08:25:40.20#ibcon#enter sib2, iclass 27, count 0 2006.210.08:25:40.20#ibcon#flushed, iclass 27, count 0 2006.210.08:25:40.20#ibcon#about to write, iclass 27, count 0 2006.210.08:25:40.20#ibcon#wrote, iclass 27, count 0 2006.210.08:25:40.20#ibcon#about to read 3, iclass 27, count 0 2006.210.08:25:40.22#ibcon#read 3, iclass 27, count 0 2006.210.08:25:40.22#ibcon#about to read 4, iclass 27, count 0 2006.210.08:25:40.22#ibcon#read 4, iclass 27, count 0 2006.210.08:25:40.22#ibcon#about to read 5, iclass 27, count 0 2006.210.08:25:40.22#ibcon#read 5, iclass 27, count 0 2006.210.08:25:40.22#ibcon#about to read 6, iclass 27, count 0 2006.210.08:25:40.22#ibcon#read 6, iclass 27, count 0 2006.210.08:25:40.22#ibcon#end of sib2, iclass 27, count 0 2006.210.08:25:40.22#ibcon#*mode == 0, iclass 27, count 0 2006.210.08:25:40.22#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.210.08:25:40.22#ibcon#[28=FRQ=01,632.99\r\n] 2006.210.08:25:40.22#ibcon#*before write, iclass 27, count 0 2006.210.08:25:40.22#ibcon#enter sib2, iclass 27, count 0 2006.210.08:25:40.22#ibcon#flushed, iclass 27, count 0 2006.210.08:25:40.22#ibcon#about to write, iclass 27, count 0 2006.210.08:25:40.22#ibcon#wrote, iclass 27, count 0 2006.210.08:25:40.22#ibcon#about to read 3, iclass 27, count 0 2006.210.08:25:40.26#ibcon#read 3, iclass 27, count 0 2006.210.08:25:40.26#ibcon#about to read 4, iclass 27, count 0 2006.210.08:25:40.26#ibcon#read 4, iclass 27, count 0 2006.210.08:25:40.26#ibcon#about to read 5, iclass 27, count 0 2006.210.08:25:40.26#ibcon#read 5, iclass 27, count 0 2006.210.08:25:40.26#ibcon#about to read 6, iclass 27, count 0 2006.210.08:25:40.26#ibcon#read 6, iclass 27, count 0 2006.210.08:25:40.26#ibcon#end of sib2, iclass 27, count 0 2006.210.08:25:40.26#ibcon#*after write, iclass 27, count 0 2006.210.08:25:40.26#ibcon#*before return 0, iclass 27, count 0 2006.210.08:25:40.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:25:40.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.210.08:25:40.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.210.08:25:40.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.210.08:25:40.26$vc4f8/vb=1,4 2006.210.08:25:40.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.210.08:25:40.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.210.08:25:40.26#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:40.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:25:40.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:25:40.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:25:40.26#ibcon#enter wrdev, iclass 29, count 2 2006.210.08:25:40.26#ibcon#first serial, iclass 29, count 2 2006.210.08:25:40.26#ibcon#enter sib2, iclass 29, count 2 2006.210.08:25:40.26#ibcon#flushed, iclass 29, count 2 2006.210.08:25:40.26#ibcon#about to write, iclass 29, count 2 2006.210.08:25:40.26#ibcon#wrote, iclass 29, count 2 2006.210.08:25:40.26#ibcon#about to read 3, iclass 29, count 2 2006.210.08:25:40.28#ibcon#read 3, iclass 29, count 2 2006.210.08:25:40.28#ibcon#about to read 4, iclass 29, count 2 2006.210.08:25:40.28#ibcon#read 4, iclass 29, count 2 2006.210.08:25:40.28#ibcon#about to read 5, iclass 29, count 2 2006.210.08:25:40.28#ibcon#read 5, iclass 29, count 2 2006.210.08:25:40.28#ibcon#about to read 6, iclass 29, count 2 2006.210.08:25:40.28#ibcon#read 6, iclass 29, count 2 2006.210.08:25:40.28#ibcon#end of sib2, iclass 29, count 2 2006.210.08:25:40.28#ibcon#*mode == 0, iclass 29, count 2 2006.210.08:25:40.28#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.210.08:25:40.28#ibcon#[27=AT01-04\r\n] 2006.210.08:25:40.28#ibcon#*before write, iclass 29, count 2 2006.210.08:25:40.28#ibcon#enter sib2, iclass 29, count 2 2006.210.08:25:40.28#ibcon#flushed, iclass 29, count 2 2006.210.08:25:40.28#ibcon#about to write, iclass 29, count 2 2006.210.08:25:40.28#ibcon#wrote, iclass 29, count 2 2006.210.08:25:40.28#ibcon#about to read 3, iclass 29, count 2 2006.210.08:25:40.31#ibcon#read 3, iclass 29, count 2 2006.210.08:25:40.31#ibcon#about to read 4, iclass 29, count 2 2006.210.08:25:40.31#ibcon#read 4, iclass 29, count 2 2006.210.08:25:40.31#ibcon#about to read 5, iclass 29, count 2 2006.210.08:25:40.31#ibcon#read 5, iclass 29, count 2 2006.210.08:25:40.31#ibcon#about to read 6, iclass 29, count 2 2006.210.08:25:40.31#ibcon#read 6, iclass 29, count 2 2006.210.08:25:40.31#ibcon#end of sib2, iclass 29, count 2 2006.210.08:25:40.31#ibcon#*after write, iclass 29, count 2 2006.210.08:25:40.31#ibcon#*before return 0, iclass 29, count 2 2006.210.08:25:40.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:25:40.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.210.08:25:40.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.210.08:25:40.31#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:40.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:25:40.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:25:40.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:25:40.43#ibcon#enter wrdev, iclass 29, count 0 2006.210.08:25:40.43#ibcon#first serial, iclass 29, count 0 2006.210.08:25:40.43#ibcon#enter sib2, iclass 29, count 0 2006.210.08:25:40.43#ibcon#flushed, iclass 29, count 0 2006.210.08:25:40.43#ibcon#about to write, iclass 29, count 0 2006.210.08:25:40.43#ibcon#wrote, iclass 29, count 0 2006.210.08:25:40.43#ibcon#about to read 3, iclass 29, count 0 2006.210.08:25:40.45#ibcon#read 3, iclass 29, count 0 2006.210.08:25:40.45#ibcon#about to read 4, iclass 29, count 0 2006.210.08:25:40.45#ibcon#read 4, iclass 29, count 0 2006.210.08:25:40.45#ibcon#about to read 5, iclass 29, count 0 2006.210.08:25:40.45#ibcon#read 5, iclass 29, count 0 2006.210.08:25:40.45#ibcon#about to read 6, iclass 29, count 0 2006.210.08:25:40.45#ibcon#read 6, iclass 29, count 0 2006.210.08:25:40.45#ibcon#end of sib2, iclass 29, count 0 2006.210.08:25:40.45#ibcon#*mode == 0, iclass 29, count 0 2006.210.08:25:40.45#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.210.08:25:40.45#ibcon#[27=USB\r\n] 2006.210.08:25:40.45#ibcon#*before write, iclass 29, count 0 2006.210.08:25:40.45#ibcon#enter sib2, iclass 29, count 0 2006.210.08:25:40.45#ibcon#flushed, iclass 29, count 0 2006.210.08:25:40.45#ibcon#about to write, iclass 29, count 0 2006.210.08:25:40.45#ibcon#wrote, iclass 29, count 0 2006.210.08:25:40.45#ibcon#about to read 3, iclass 29, count 0 2006.210.08:25:40.48#ibcon#read 3, iclass 29, count 0 2006.210.08:25:40.48#ibcon#about to read 4, iclass 29, count 0 2006.210.08:25:40.48#ibcon#read 4, iclass 29, count 0 2006.210.08:25:40.48#ibcon#about to read 5, iclass 29, count 0 2006.210.08:25:40.48#ibcon#read 5, iclass 29, count 0 2006.210.08:25:40.48#ibcon#about to read 6, iclass 29, count 0 2006.210.08:25:40.48#ibcon#read 6, iclass 29, count 0 2006.210.08:25:40.48#ibcon#end of sib2, iclass 29, count 0 2006.210.08:25:40.48#ibcon#*after write, iclass 29, count 0 2006.210.08:25:40.48#ibcon#*before return 0, iclass 29, count 0 2006.210.08:25:40.48#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:25:40.48#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.210.08:25:40.48#ibcon#about to clear, iclass 29 cls_cnt 0 2006.210.08:25:40.48#ibcon#cleared, iclass 29 cls_cnt 0 2006.210.08:25:40.48$vc4f8/vblo=2,640.99 2006.210.08:25:40.48#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.210.08:25:40.48#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.210.08:25:40.48#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:40.48#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:40.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:40.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:40.48#ibcon#enter wrdev, iclass 31, count 0 2006.210.08:25:40.48#ibcon#first serial, iclass 31, count 0 2006.210.08:25:40.48#ibcon#enter sib2, iclass 31, count 0 2006.210.08:25:40.48#ibcon#flushed, iclass 31, count 0 2006.210.08:25:40.48#ibcon#about to write, iclass 31, count 0 2006.210.08:25:40.48#ibcon#wrote, iclass 31, count 0 2006.210.08:25:40.48#ibcon#about to read 3, iclass 31, count 0 2006.210.08:25:40.50#ibcon#read 3, iclass 31, count 0 2006.210.08:25:40.50#ibcon#about to read 4, iclass 31, count 0 2006.210.08:25:40.50#ibcon#read 4, iclass 31, count 0 2006.210.08:25:40.50#ibcon#about to read 5, iclass 31, count 0 2006.210.08:25:40.50#ibcon#read 5, iclass 31, count 0 2006.210.08:25:40.50#ibcon#about to read 6, iclass 31, count 0 2006.210.08:25:40.50#ibcon#read 6, iclass 31, count 0 2006.210.08:25:40.50#ibcon#end of sib2, iclass 31, count 0 2006.210.08:25:40.50#ibcon#*mode == 0, iclass 31, count 0 2006.210.08:25:40.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.210.08:25:40.50#ibcon#[28=FRQ=02,640.99\r\n] 2006.210.08:25:40.50#ibcon#*before write, iclass 31, count 0 2006.210.08:25:40.50#ibcon#enter sib2, iclass 31, count 0 2006.210.08:25:40.50#ibcon#flushed, iclass 31, count 0 2006.210.08:25:40.50#ibcon#about to write, iclass 31, count 0 2006.210.08:25:40.50#ibcon#wrote, iclass 31, count 0 2006.210.08:25:40.50#ibcon#about to read 3, iclass 31, count 0 2006.210.08:25:40.54#ibcon#read 3, iclass 31, count 0 2006.210.08:25:40.54#ibcon#about to read 4, iclass 31, count 0 2006.210.08:25:40.54#ibcon#read 4, iclass 31, count 0 2006.210.08:25:40.54#ibcon#about to read 5, iclass 31, count 0 2006.210.08:25:40.54#ibcon#read 5, iclass 31, count 0 2006.210.08:25:40.54#ibcon#about to read 6, iclass 31, count 0 2006.210.08:25:40.54#ibcon#read 6, iclass 31, count 0 2006.210.08:25:40.54#ibcon#end of sib2, iclass 31, count 0 2006.210.08:25:40.54#ibcon#*after write, iclass 31, count 0 2006.210.08:25:40.54#ibcon#*before return 0, iclass 31, count 0 2006.210.08:25:40.54#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:40.54#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.210.08:25:40.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.210.08:25:40.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.210.08:25:40.54$vc4f8/vb=2,4 2006.210.08:25:40.54#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.210.08:25:40.54#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.210.08:25:40.54#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:40.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:40.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:40.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:40.60#ibcon#enter wrdev, iclass 33, count 2 2006.210.08:25:40.60#ibcon#first serial, iclass 33, count 2 2006.210.08:25:40.60#ibcon#enter sib2, iclass 33, count 2 2006.210.08:25:40.60#ibcon#flushed, iclass 33, count 2 2006.210.08:25:40.60#ibcon#about to write, iclass 33, count 2 2006.210.08:25:40.60#ibcon#wrote, iclass 33, count 2 2006.210.08:25:40.60#ibcon#about to read 3, iclass 33, count 2 2006.210.08:25:40.62#ibcon#read 3, iclass 33, count 2 2006.210.08:25:40.62#ibcon#about to read 4, iclass 33, count 2 2006.210.08:25:40.62#ibcon#read 4, iclass 33, count 2 2006.210.08:25:40.62#ibcon#about to read 5, iclass 33, count 2 2006.210.08:25:40.62#ibcon#read 5, iclass 33, count 2 2006.210.08:25:40.62#ibcon#about to read 6, iclass 33, count 2 2006.210.08:25:40.62#ibcon#read 6, iclass 33, count 2 2006.210.08:25:40.62#ibcon#end of sib2, iclass 33, count 2 2006.210.08:25:40.62#ibcon#*mode == 0, iclass 33, count 2 2006.210.08:25:40.62#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.210.08:25:40.62#ibcon#[27=AT02-04\r\n] 2006.210.08:25:40.62#ibcon#*before write, iclass 33, count 2 2006.210.08:25:40.62#ibcon#enter sib2, iclass 33, count 2 2006.210.08:25:40.62#ibcon#flushed, iclass 33, count 2 2006.210.08:25:40.62#ibcon#about to write, iclass 33, count 2 2006.210.08:25:40.62#ibcon#wrote, iclass 33, count 2 2006.210.08:25:40.62#ibcon#about to read 3, iclass 33, count 2 2006.210.08:25:40.65#ibcon#read 3, iclass 33, count 2 2006.210.08:25:40.65#ibcon#about to read 4, iclass 33, count 2 2006.210.08:25:40.65#ibcon#read 4, iclass 33, count 2 2006.210.08:25:40.65#ibcon#about to read 5, iclass 33, count 2 2006.210.08:25:40.65#ibcon#read 5, iclass 33, count 2 2006.210.08:25:40.65#ibcon#about to read 6, iclass 33, count 2 2006.210.08:25:40.65#ibcon#read 6, iclass 33, count 2 2006.210.08:25:40.65#ibcon#end of sib2, iclass 33, count 2 2006.210.08:25:40.65#ibcon#*after write, iclass 33, count 2 2006.210.08:25:40.65#ibcon#*before return 0, iclass 33, count 2 2006.210.08:25:40.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:40.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.210.08:25:40.65#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.210.08:25:40.65#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:40.65#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:40.77#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:40.77#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:40.77#ibcon#enter wrdev, iclass 33, count 0 2006.210.08:25:40.77#ibcon#first serial, iclass 33, count 0 2006.210.08:25:40.77#ibcon#enter sib2, iclass 33, count 0 2006.210.08:25:40.77#ibcon#flushed, iclass 33, count 0 2006.210.08:25:40.77#ibcon#about to write, iclass 33, count 0 2006.210.08:25:40.77#ibcon#wrote, iclass 33, count 0 2006.210.08:25:40.77#ibcon#about to read 3, iclass 33, count 0 2006.210.08:25:40.79#ibcon#read 3, iclass 33, count 0 2006.210.08:25:40.79#ibcon#about to read 4, iclass 33, count 0 2006.210.08:25:40.79#ibcon#read 4, iclass 33, count 0 2006.210.08:25:40.79#ibcon#about to read 5, iclass 33, count 0 2006.210.08:25:40.79#ibcon#read 5, iclass 33, count 0 2006.210.08:25:40.79#ibcon#about to read 6, iclass 33, count 0 2006.210.08:25:40.79#ibcon#read 6, iclass 33, count 0 2006.210.08:25:40.79#ibcon#end of sib2, iclass 33, count 0 2006.210.08:25:40.79#ibcon#*mode == 0, iclass 33, count 0 2006.210.08:25:40.79#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.210.08:25:40.79#ibcon#[27=USB\r\n] 2006.210.08:25:40.79#ibcon#*before write, iclass 33, count 0 2006.210.08:25:40.79#ibcon#enter sib2, iclass 33, count 0 2006.210.08:25:40.79#ibcon#flushed, iclass 33, count 0 2006.210.08:25:40.79#ibcon#about to write, iclass 33, count 0 2006.210.08:25:40.79#ibcon#wrote, iclass 33, count 0 2006.210.08:25:40.79#ibcon#about to read 3, iclass 33, count 0 2006.210.08:25:40.82#ibcon#read 3, iclass 33, count 0 2006.210.08:25:40.82#ibcon#about to read 4, iclass 33, count 0 2006.210.08:25:40.82#ibcon#read 4, iclass 33, count 0 2006.210.08:25:40.82#ibcon#about to read 5, iclass 33, count 0 2006.210.08:25:40.82#ibcon#read 5, iclass 33, count 0 2006.210.08:25:40.82#ibcon#about to read 6, iclass 33, count 0 2006.210.08:25:40.82#ibcon#read 6, iclass 33, count 0 2006.210.08:25:40.82#ibcon#end of sib2, iclass 33, count 0 2006.210.08:25:40.82#ibcon#*after write, iclass 33, count 0 2006.210.08:25:40.82#ibcon#*before return 0, iclass 33, count 0 2006.210.08:25:40.82#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:40.82#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.210.08:25:40.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.210.08:25:40.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.210.08:25:40.82$vc4f8/vblo=3,656.99 2006.210.08:25:40.82#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.210.08:25:40.82#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.210.08:25:40.82#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:40.82#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:40.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:40.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:40.82#ibcon#enter wrdev, iclass 35, count 0 2006.210.08:25:40.82#ibcon#first serial, iclass 35, count 0 2006.210.08:25:40.82#ibcon#enter sib2, iclass 35, count 0 2006.210.08:25:40.82#ibcon#flushed, iclass 35, count 0 2006.210.08:25:40.82#ibcon#about to write, iclass 35, count 0 2006.210.08:25:40.82#ibcon#wrote, iclass 35, count 0 2006.210.08:25:40.82#ibcon#about to read 3, iclass 35, count 0 2006.210.08:25:40.84#ibcon#read 3, iclass 35, count 0 2006.210.08:25:40.84#ibcon#about to read 4, iclass 35, count 0 2006.210.08:25:40.84#ibcon#read 4, iclass 35, count 0 2006.210.08:25:40.84#ibcon#about to read 5, iclass 35, count 0 2006.210.08:25:40.84#ibcon#read 5, iclass 35, count 0 2006.210.08:25:40.84#ibcon#about to read 6, iclass 35, count 0 2006.210.08:25:40.84#ibcon#read 6, iclass 35, count 0 2006.210.08:25:40.84#ibcon#end of sib2, iclass 35, count 0 2006.210.08:25:40.84#ibcon#*mode == 0, iclass 35, count 0 2006.210.08:25:40.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.210.08:25:40.84#ibcon#[28=FRQ=03,656.99\r\n] 2006.210.08:25:40.84#ibcon#*before write, iclass 35, count 0 2006.210.08:25:40.84#ibcon#enter sib2, iclass 35, count 0 2006.210.08:25:40.84#ibcon#flushed, iclass 35, count 0 2006.210.08:25:40.84#ibcon#about to write, iclass 35, count 0 2006.210.08:25:40.84#ibcon#wrote, iclass 35, count 0 2006.210.08:25:40.84#ibcon#about to read 3, iclass 35, count 0 2006.210.08:25:40.88#ibcon#read 3, iclass 35, count 0 2006.210.08:25:40.88#ibcon#about to read 4, iclass 35, count 0 2006.210.08:25:40.88#ibcon#read 4, iclass 35, count 0 2006.210.08:25:40.88#ibcon#about to read 5, iclass 35, count 0 2006.210.08:25:40.88#ibcon#read 5, iclass 35, count 0 2006.210.08:25:40.88#ibcon#about to read 6, iclass 35, count 0 2006.210.08:25:40.88#ibcon#read 6, iclass 35, count 0 2006.210.08:25:40.88#ibcon#end of sib2, iclass 35, count 0 2006.210.08:25:40.88#ibcon#*after write, iclass 35, count 0 2006.210.08:25:40.88#ibcon#*before return 0, iclass 35, count 0 2006.210.08:25:40.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:40.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.210.08:25:40.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.210.08:25:40.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.210.08:25:40.88$vc4f8/vb=3,3 2006.210.08:25:40.88#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.210.08:25:40.88#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.210.08:25:40.88#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:40.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:40.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:40.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:40.94#ibcon#enter wrdev, iclass 37, count 2 2006.210.08:25:40.94#ibcon#first serial, iclass 37, count 2 2006.210.08:25:40.94#ibcon#enter sib2, iclass 37, count 2 2006.210.08:25:40.94#ibcon#flushed, iclass 37, count 2 2006.210.08:25:40.94#ibcon#about to write, iclass 37, count 2 2006.210.08:25:40.94#ibcon#wrote, iclass 37, count 2 2006.210.08:25:40.94#ibcon#about to read 3, iclass 37, count 2 2006.210.08:25:40.96#ibcon#read 3, iclass 37, count 2 2006.210.08:25:40.96#ibcon#about to read 4, iclass 37, count 2 2006.210.08:25:40.96#ibcon#read 4, iclass 37, count 2 2006.210.08:25:40.96#ibcon#about to read 5, iclass 37, count 2 2006.210.08:25:40.96#ibcon#read 5, iclass 37, count 2 2006.210.08:25:40.96#ibcon#about to read 6, iclass 37, count 2 2006.210.08:25:40.96#ibcon#read 6, iclass 37, count 2 2006.210.08:25:40.96#ibcon#end of sib2, iclass 37, count 2 2006.210.08:25:40.96#ibcon#*mode == 0, iclass 37, count 2 2006.210.08:25:40.96#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.210.08:25:40.96#ibcon#[27=AT03-03\r\n] 2006.210.08:25:40.96#ibcon#*before write, iclass 37, count 2 2006.210.08:25:40.96#ibcon#enter sib2, iclass 37, count 2 2006.210.08:25:40.96#ibcon#flushed, iclass 37, count 2 2006.210.08:25:40.96#ibcon#about to write, iclass 37, count 2 2006.210.08:25:40.96#ibcon#wrote, iclass 37, count 2 2006.210.08:25:40.96#ibcon#about to read 3, iclass 37, count 2 2006.210.08:25:40.99#ibcon#read 3, iclass 37, count 2 2006.210.08:25:40.99#ibcon#about to read 4, iclass 37, count 2 2006.210.08:25:40.99#ibcon#read 4, iclass 37, count 2 2006.210.08:25:40.99#ibcon#about to read 5, iclass 37, count 2 2006.210.08:25:40.99#ibcon#read 5, iclass 37, count 2 2006.210.08:25:40.99#ibcon#about to read 6, iclass 37, count 2 2006.210.08:25:40.99#ibcon#read 6, iclass 37, count 2 2006.210.08:25:40.99#ibcon#end of sib2, iclass 37, count 2 2006.210.08:25:40.99#ibcon#*after write, iclass 37, count 2 2006.210.08:25:40.99#ibcon#*before return 0, iclass 37, count 2 2006.210.08:25:40.99#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:40.99#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.210.08:25:40.99#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.210.08:25:40.99#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:40.99#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:41.11#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:41.11#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:41.11#ibcon#enter wrdev, iclass 37, count 0 2006.210.08:25:41.11#ibcon#first serial, iclass 37, count 0 2006.210.08:25:41.11#ibcon#enter sib2, iclass 37, count 0 2006.210.08:25:41.11#ibcon#flushed, iclass 37, count 0 2006.210.08:25:41.11#ibcon#about to write, iclass 37, count 0 2006.210.08:25:41.11#ibcon#wrote, iclass 37, count 0 2006.210.08:25:41.11#ibcon#about to read 3, iclass 37, count 0 2006.210.08:25:41.13#ibcon#read 3, iclass 37, count 0 2006.210.08:25:41.13#ibcon#about to read 4, iclass 37, count 0 2006.210.08:25:41.13#ibcon#read 4, iclass 37, count 0 2006.210.08:25:41.13#ibcon#about to read 5, iclass 37, count 0 2006.210.08:25:41.13#ibcon#read 5, iclass 37, count 0 2006.210.08:25:41.13#ibcon#about to read 6, iclass 37, count 0 2006.210.08:25:41.13#ibcon#read 6, iclass 37, count 0 2006.210.08:25:41.13#ibcon#end of sib2, iclass 37, count 0 2006.210.08:25:41.13#ibcon#*mode == 0, iclass 37, count 0 2006.210.08:25:41.13#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.210.08:25:41.13#ibcon#[27=USB\r\n] 2006.210.08:25:41.13#ibcon#*before write, iclass 37, count 0 2006.210.08:25:41.13#ibcon#enter sib2, iclass 37, count 0 2006.210.08:25:41.13#ibcon#flushed, iclass 37, count 0 2006.210.08:25:41.13#ibcon#about to write, iclass 37, count 0 2006.210.08:25:41.13#ibcon#wrote, iclass 37, count 0 2006.210.08:25:41.13#ibcon#about to read 3, iclass 37, count 0 2006.210.08:25:41.16#ibcon#read 3, iclass 37, count 0 2006.210.08:25:41.16#ibcon#about to read 4, iclass 37, count 0 2006.210.08:25:41.16#ibcon#read 4, iclass 37, count 0 2006.210.08:25:41.16#ibcon#about to read 5, iclass 37, count 0 2006.210.08:25:41.16#ibcon#read 5, iclass 37, count 0 2006.210.08:25:41.16#ibcon#about to read 6, iclass 37, count 0 2006.210.08:25:41.16#ibcon#read 6, iclass 37, count 0 2006.210.08:25:41.16#ibcon#end of sib2, iclass 37, count 0 2006.210.08:25:41.16#ibcon#*after write, iclass 37, count 0 2006.210.08:25:41.16#ibcon#*before return 0, iclass 37, count 0 2006.210.08:25:41.16#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:41.16#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.210.08:25:41.16#ibcon#about to clear, iclass 37 cls_cnt 0 2006.210.08:25:41.16#ibcon#cleared, iclass 37 cls_cnt 0 2006.210.08:25:41.16$vc4f8/vblo=4,712.99 2006.210.08:25:41.16#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.210.08:25:41.16#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.210.08:25:41.16#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:41.16#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:41.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:41.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:41.16#ibcon#enter wrdev, iclass 39, count 0 2006.210.08:25:41.16#ibcon#first serial, iclass 39, count 0 2006.210.08:25:41.16#ibcon#enter sib2, iclass 39, count 0 2006.210.08:25:41.16#ibcon#flushed, iclass 39, count 0 2006.210.08:25:41.16#ibcon#about to write, iclass 39, count 0 2006.210.08:25:41.16#ibcon#wrote, iclass 39, count 0 2006.210.08:25:41.16#ibcon#about to read 3, iclass 39, count 0 2006.210.08:25:41.18#ibcon#read 3, iclass 39, count 0 2006.210.08:25:41.18#ibcon#about to read 4, iclass 39, count 0 2006.210.08:25:41.18#ibcon#read 4, iclass 39, count 0 2006.210.08:25:41.18#ibcon#about to read 5, iclass 39, count 0 2006.210.08:25:41.18#ibcon#read 5, iclass 39, count 0 2006.210.08:25:41.18#ibcon#about to read 6, iclass 39, count 0 2006.210.08:25:41.18#ibcon#read 6, iclass 39, count 0 2006.210.08:25:41.18#ibcon#end of sib2, iclass 39, count 0 2006.210.08:25:41.18#ibcon#*mode == 0, iclass 39, count 0 2006.210.08:25:41.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.210.08:25:41.18#ibcon#[28=FRQ=04,712.99\r\n] 2006.210.08:25:41.18#ibcon#*before write, iclass 39, count 0 2006.210.08:25:41.18#ibcon#enter sib2, iclass 39, count 0 2006.210.08:25:41.18#ibcon#flushed, iclass 39, count 0 2006.210.08:25:41.18#ibcon#about to write, iclass 39, count 0 2006.210.08:25:41.18#ibcon#wrote, iclass 39, count 0 2006.210.08:25:41.18#ibcon#about to read 3, iclass 39, count 0 2006.210.08:25:41.22#ibcon#read 3, iclass 39, count 0 2006.210.08:25:41.22#ibcon#about to read 4, iclass 39, count 0 2006.210.08:25:41.22#ibcon#read 4, iclass 39, count 0 2006.210.08:25:41.22#ibcon#about to read 5, iclass 39, count 0 2006.210.08:25:41.22#ibcon#read 5, iclass 39, count 0 2006.210.08:25:41.22#ibcon#about to read 6, iclass 39, count 0 2006.210.08:25:41.22#ibcon#read 6, iclass 39, count 0 2006.210.08:25:41.22#ibcon#end of sib2, iclass 39, count 0 2006.210.08:25:41.22#ibcon#*after write, iclass 39, count 0 2006.210.08:25:41.22#ibcon#*before return 0, iclass 39, count 0 2006.210.08:25:41.22#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:41.22#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.210.08:25:41.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.210.08:25:41.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.210.08:25:41.22$vc4f8/vb=4,3 2006.210.08:25:41.22#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.210.08:25:41.22#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.210.08:25:41.22#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:41.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:41.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:41.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:41.28#ibcon#enter wrdev, iclass 3, count 2 2006.210.08:25:41.28#ibcon#first serial, iclass 3, count 2 2006.210.08:25:41.28#ibcon#enter sib2, iclass 3, count 2 2006.210.08:25:41.28#ibcon#flushed, iclass 3, count 2 2006.210.08:25:41.28#ibcon#about to write, iclass 3, count 2 2006.210.08:25:41.28#ibcon#wrote, iclass 3, count 2 2006.210.08:25:41.28#ibcon#about to read 3, iclass 3, count 2 2006.210.08:25:41.30#ibcon#read 3, iclass 3, count 2 2006.210.08:25:41.30#ibcon#about to read 4, iclass 3, count 2 2006.210.08:25:41.30#ibcon#read 4, iclass 3, count 2 2006.210.08:25:41.30#ibcon#about to read 5, iclass 3, count 2 2006.210.08:25:41.30#ibcon#read 5, iclass 3, count 2 2006.210.08:25:41.30#ibcon#about to read 6, iclass 3, count 2 2006.210.08:25:41.30#ibcon#read 6, iclass 3, count 2 2006.210.08:25:41.30#ibcon#end of sib2, iclass 3, count 2 2006.210.08:25:41.30#ibcon#*mode == 0, iclass 3, count 2 2006.210.08:25:41.30#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.210.08:25:41.30#ibcon#[27=AT04-03\r\n] 2006.210.08:25:41.30#ibcon#*before write, iclass 3, count 2 2006.210.08:25:41.30#ibcon#enter sib2, iclass 3, count 2 2006.210.08:25:41.30#ibcon#flushed, iclass 3, count 2 2006.210.08:25:41.30#ibcon#about to write, iclass 3, count 2 2006.210.08:25:41.30#ibcon#wrote, iclass 3, count 2 2006.210.08:25:41.30#ibcon#about to read 3, iclass 3, count 2 2006.210.08:25:41.33#ibcon#read 3, iclass 3, count 2 2006.210.08:25:41.33#ibcon#about to read 4, iclass 3, count 2 2006.210.08:25:41.33#ibcon#read 4, iclass 3, count 2 2006.210.08:25:41.33#ibcon#about to read 5, iclass 3, count 2 2006.210.08:25:41.33#ibcon#read 5, iclass 3, count 2 2006.210.08:25:41.33#ibcon#about to read 6, iclass 3, count 2 2006.210.08:25:41.33#ibcon#read 6, iclass 3, count 2 2006.210.08:25:41.33#ibcon#end of sib2, iclass 3, count 2 2006.210.08:25:41.33#ibcon#*after write, iclass 3, count 2 2006.210.08:25:41.33#ibcon#*before return 0, iclass 3, count 2 2006.210.08:25:41.33#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:41.33#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.210.08:25:41.33#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.210.08:25:41.33#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:41.33#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:41.45#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:41.45#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:41.45#ibcon#enter wrdev, iclass 3, count 0 2006.210.08:25:41.45#ibcon#first serial, iclass 3, count 0 2006.210.08:25:41.45#ibcon#enter sib2, iclass 3, count 0 2006.210.08:25:41.45#ibcon#flushed, iclass 3, count 0 2006.210.08:25:41.45#ibcon#about to write, iclass 3, count 0 2006.210.08:25:41.45#ibcon#wrote, iclass 3, count 0 2006.210.08:25:41.45#ibcon#about to read 3, iclass 3, count 0 2006.210.08:25:41.47#ibcon#read 3, iclass 3, count 0 2006.210.08:25:41.47#ibcon#about to read 4, iclass 3, count 0 2006.210.08:25:41.47#ibcon#read 4, iclass 3, count 0 2006.210.08:25:41.47#ibcon#about to read 5, iclass 3, count 0 2006.210.08:25:41.47#ibcon#read 5, iclass 3, count 0 2006.210.08:25:41.47#ibcon#about to read 6, iclass 3, count 0 2006.210.08:25:41.47#ibcon#read 6, iclass 3, count 0 2006.210.08:25:41.47#ibcon#end of sib2, iclass 3, count 0 2006.210.08:25:41.47#ibcon#*mode == 0, iclass 3, count 0 2006.210.08:25:41.47#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.210.08:25:41.47#ibcon#[27=USB\r\n] 2006.210.08:25:41.47#ibcon#*before write, iclass 3, count 0 2006.210.08:25:41.47#ibcon#enter sib2, iclass 3, count 0 2006.210.08:25:41.47#ibcon#flushed, iclass 3, count 0 2006.210.08:25:41.47#ibcon#about to write, iclass 3, count 0 2006.210.08:25:41.47#ibcon#wrote, iclass 3, count 0 2006.210.08:25:41.47#ibcon#about to read 3, iclass 3, count 0 2006.210.08:25:41.50#ibcon#read 3, iclass 3, count 0 2006.210.08:25:41.50#ibcon#about to read 4, iclass 3, count 0 2006.210.08:25:41.50#ibcon#read 4, iclass 3, count 0 2006.210.08:25:41.50#ibcon#about to read 5, iclass 3, count 0 2006.210.08:25:41.50#ibcon#read 5, iclass 3, count 0 2006.210.08:25:41.50#ibcon#about to read 6, iclass 3, count 0 2006.210.08:25:41.50#ibcon#read 6, iclass 3, count 0 2006.210.08:25:41.50#ibcon#end of sib2, iclass 3, count 0 2006.210.08:25:41.50#ibcon#*after write, iclass 3, count 0 2006.210.08:25:41.50#ibcon#*before return 0, iclass 3, count 0 2006.210.08:25:41.50#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:41.50#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.210.08:25:41.50#ibcon#about to clear, iclass 3 cls_cnt 0 2006.210.08:25:41.50#ibcon#cleared, iclass 3 cls_cnt 0 2006.210.08:25:41.50$vc4f8/vblo=5,744.99 2006.210.08:25:41.50#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.210.08:25:41.50#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.210.08:25:41.50#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:41.50#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:41.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:41.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:41.50#ibcon#enter wrdev, iclass 5, count 0 2006.210.08:25:41.50#ibcon#first serial, iclass 5, count 0 2006.210.08:25:41.50#ibcon#enter sib2, iclass 5, count 0 2006.210.08:25:41.50#ibcon#flushed, iclass 5, count 0 2006.210.08:25:41.50#ibcon#about to write, iclass 5, count 0 2006.210.08:25:41.50#ibcon#wrote, iclass 5, count 0 2006.210.08:25:41.50#ibcon#about to read 3, iclass 5, count 0 2006.210.08:25:41.52#ibcon#read 3, iclass 5, count 0 2006.210.08:25:41.52#ibcon#about to read 4, iclass 5, count 0 2006.210.08:25:41.52#ibcon#read 4, iclass 5, count 0 2006.210.08:25:41.52#ibcon#about to read 5, iclass 5, count 0 2006.210.08:25:41.52#ibcon#read 5, iclass 5, count 0 2006.210.08:25:41.52#ibcon#about to read 6, iclass 5, count 0 2006.210.08:25:41.52#ibcon#read 6, iclass 5, count 0 2006.210.08:25:41.52#ibcon#end of sib2, iclass 5, count 0 2006.210.08:25:41.52#ibcon#*mode == 0, iclass 5, count 0 2006.210.08:25:41.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.210.08:25:41.52#ibcon#[28=FRQ=05,744.99\r\n] 2006.210.08:25:41.52#ibcon#*before write, iclass 5, count 0 2006.210.08:25:41.52#ibcon#enter sib2, iclass 5, count 0 2006.210.08:25:41.52#ibcon#flushed, iclass 5, count 0 2006.210.08:25:41.52#ibcon#about to write, iclass 5, count 0 2006.210.08:25:41.52#ibcon#wrote, iclass 5, count 0 2006.210.08:25:41.52#ibcon#about to read 3, iclass 5, count 0 2006.210.08:25:41.56#ibcon#read 3, iclass 5, count 0 2006.210.08:25:41.56#ibcon#about to read 4, iclass 5, count 0 2006.210.08:25:41.56#ibcon#read 4, iclass 5, count 0 2006.210.08:25:41.56#ibcon#about to read 5, iclass 5, count 0 2006.210.08:25:41.56#ibcon#read 5, iclass 5, count 0 2006.210.08:25:41.56#ibcon#about to read 6, iclass 5, count 0 2006.210.08:25:41.56#ibcon#read 6, iclass 5, count 0 2006.210.08:25:41.56#ibcon#end of sib2, iclass 5, count 0 2006.210.08:25:41.56#ibcon#*after write, iclass 5, count 0 2006.210.08:25:41.56#ibcon#*before return 0, iclass 5, count 0 2006.210.08:25:41.56#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:41.56#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.210.08:25:41.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.210.08:25:41.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.210.08:25:41.56$vc4f8/vb=5,3 2006.210.08:25:41.56#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.210.08:25:41.56#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.210.08:25:41.56#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:41.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:41.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:41.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:41.62#ibcon#enter wrdev, iclass 7, count 2 2006.210.08:25:41.62#ibcon#first serial, iclass 7, count 2 2006.210.08:25:41.62#ibcon#enter sib2, iclass 7, count 2 2006.210.08:25:41.62#ibcon#flushed, iclass 7, count 2 2006.210.08:25:41.62#ibcon#about to write, iclass 7, count 2 2006.210.08:25:41.62#ibcon#wrote, iclass 7, count 2 2006.210.08:25:41.62#ibcon#about to read 3, iclass 7, count 2 2006.210.08:25:41.64#ibcon#read 3, iclass 7, count 2 2006.210.08:25:41.64#ibcon#about to read 4, iclass 7, count 2 2006.210.08:25:41.64#ibcon#read 4, iclass 7, count 2 2006.210.08:25:41.64#ibcon#about to read 5, iclass 7, count 2 2006.210.08:25:41.64#ibcon#read 5, iclass 7, count 2 2006.210.08:25:41.64#ibcon#about to read 6, iclass 7, count 2 2006.210.08:25:41.64#ibcon#read 6, iclass 7, count 2 2006.210.08:25:41.64#ibcon#end of sib2, iclass 7, count 2 2006.210.08:25:41.64#ibcon#*mode == 0, iclass 7, count 2 2006.210.08:25:41.64#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.210.08:25:41.64#ibcon#[27=AT05-03\r\n] 2006.210.08:25:41.64#ibcon#*before write, iclass 7, count 2 2006.210.08:25:41.64#ibcon#enter sib2, iclass 7, count 2 2006.210.08:25:41.64#ibcon#flushed, iclass 7, count 2 2006.210.08:25:41.64#ibcon#about to write, iclass 7, count 2 2006.210.08:25:41.64#ibcon#wrote, iclass 7, count 2 2006.210.08:25:41.64#ibcon#about to read 3, iclass 7, count 2 2006.210.08:25:41.67#ibcon#read 3, iclass 7, count 2 2006.210.08:25:41.67#ibcon#about to read 4, iclass 7, count 2 2006.210.08:25:41.67#ibcon#read 4, iclass 7, count 2 2006.210.08:25:41.67#ibcon#about to read 5, iclass 7, count 2 2006.210.08:25:41.67#ibcon#read 5, iclass 7, count 2 2006.210.08:25:41.67#ibcon#about to read 6, iclass 7, count 2 2006.210.08:25:41.67#ibcon#read 6, iclass 7, count 2 2006.210.08:25:41.67#ibcon#end of sib2, iclass 7, count 2 2006.210.08:25:41.67#ibcon#*after write, iclass 7, count 2 2006.210.08:25:41.67#ibcon#*before return 0, iclass 7, count 2 2006.210.08:25:41.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:41.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.210.08:25:41.67#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.210.08:25:41.67#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:41.67#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:41.79#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:41.79#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:41.79#ibcon#enter wrdev, iclass 7, count 0 2006.210.08:25:41.79#ibcon#first serial, iclass 7, count 0 2006.210.08:25:41.79#ibcon#enter sib2, iclass 7, count 0 2006.210.08:25:41.79#ibcon#flushed, iclass 7, count 0 2006.210.08:25:41.79#ibcon#about to write, iclass 7, count 0 2006.210.08:25:41.79#ibcon#wrote, iclass 7, count 0 2006.210.08:25:41.79#ibcon#about to read 3, iclass 7, count 0 2006.210.08:25:41.81#ibcon#read 3, iclass 7, count 0 2006.210.08:25:41.81#ibcon#about to read 4, iclass 7, count 0 2006.210.08:25:41.81#ibcon#read 4, iclass 7, count 0 2006.210.08:25:41.81#ibcon#about to read 5, iclass 7, count 0 2006.210.08:25:41.81#ibcon#read 5, iclass 7, count 0 2006.210.08:25:41.81#ibcon#about to read 6, iclass 7, count 0 2006.210.08:25:41.81#ibcon#read 6, iclass 7, count 0 2006.210.08:25:41.81#ibcon#end of sib2, iclass 7, count 0 2006.210.08:25:41.81#ibcon#*mode == 0, iclass 7, count 0 2006.210.08:25:41.81#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.210.08:25:41.81#ibcon#[27=USB\r\n] 2006.210.08:25:41.81#ibcon#*before write, iclass 7, count 0 2006.210.08:25:41.81#ibcon#enter sib2, iclass 7, count 0 2006.210.08:25:41.81#ibcon#flushed, iclass 7, count 0 2006.210.08:25:41.81#ibcon#about to write, iclass 7, count 0 2006.210.08:25:41.81#ibcon#wrote, iclass 7, count 0 2006.210.08:25:41.81#ibcon#about to read 3, iclass 7, count 0 2006.210.08:25:41.84#ibcon#read 3, iclass 7, count 0 2006.210.08:25:41.84#ibcon#about to read 4, iclass 7, count 0 2006.210.08:25:41.84#ibcon#read 4, iclass 7, count 0 2006.210.08:25:41.84#ibcon#about to read 5, iclass 7, count 0 2006.210.08:25:41.84#ibcon#read 5, iclass 7, count 0 2006.210.08:25:41.84#ibcon#about to read 6, iclass 7, count 0 2006.210.08:25:41.84#ibcon#read 6, iclass 7, count 0 2006.210.08:25:41.84#ibcon#end of sib2, iclass 7, count 0 2006.210.08:25:41.84#ibcon#*after write, iclass 7, count 0 2006.210.08:25:41.84#ibcon#*before return 0, iclass 7, count 0 2006.210.08:25:41.84#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:41.84#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.210.08:25:41.84#ibcon#about to clear, iclass 7 cls_cnt 0 2006.210.08:25:41.84#ibcon#cleared, iclass 7 cls_cnt 0 2006.210.08:25:41.84$vc4f8/vblo=6,752.99 2006.210.08:25:41.84#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.210.08:25:41.84#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.210.08:25:41.84#ibcon#ireg 17 cls_cnt 0 2006.210.08:25:41.84#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:41.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:41.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:41.84#ibcon#enter wrdev, iclass 11, count 0 2006.210.08:25:41.84#ibcon#first serial, iclass 11, count 0 2006.210.08:25:41.84#ibcon#enter sib2, iclass 11, count 0 2006.210.08:25:41.84#ibcon#flushed, iclass 11, count 0 2006.210.08:25:41.84#ibcon#about to write, iclass 11, count 0 2006.210.08:25:41.84#ibcon#wrote, iclass 11, count 0 2006.210.08:25:41.84#ibcon#about to read 3, iclass 11, count 0 2006.210.08:25:41.86#ibcon#read 3, iclass 11, count 0 2006.210.08:25:41.86#ibcon#about to read 4, iclass 11, count 0 2006.210.08:25:41.86#ibcon#read 4, iclass 11, count 0 2006.210.08:25:41.86#ibcon#about to read 5, iclass 11, count 0 2006.210.08:25:41.86#ibcon#read 5, iclass 11, count 0 2006.210.08:25:41.86#ibcon#about to read 6, iclass 11, count 0 2006.210.08:25:41.86#ibcon#read 6, iclass 11, count 0 2006.210.08:25:41.86#ibcon#end of sib2, iclass 11, count 0 2006.210.08:25:41.86#ibcon#*mode == 0, iclass 11, count 0 2006.210.08:25:41.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.210.08:25:41.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.210.08:25:41.86#ibcon#*before write, iclass 11, count 0 2006.210.08:25:41.86#ibcon#enter sib2, iclass 11, count 0 2006.210.08:25:41.86#ibcon#flushed, iclass 11, count 0 2006.210.08:25:41.86#ibcon#about to write, iclass 11, count 0 2006.210.08:25:41.86#ibcon#wrote, iclass 11, count 0 2006.210.08:25:41.86#ibcon#about to read 3, iclass 11, count 0 2006.210.08:25:41.90#ibcon#read 3, iclass 11, count 0 2006.210.08:25:41.90#ibcon#about to read 4, iclass 11, count 0 2006.210.08:25:41.90#ibcon#read 4, iclass 11, count 0 2006.210.08:25:41.90#ibcon#about to read 5, iclass 11, count 0 2006.210.08:25:41.90#ibcon#read 5, iclass 11, count 0 2006.210.08:25:41.90#ibcon#about to read 6, iclass 11, count 0 2006.210.08:25:41.90#ibcon#read 6, iclass 11, count 0 2006.210.08:25:41.90#ibcon#end of sib2, iclass 11, count 0 2006.210.08:25:41.90#ibcon#*after write, iclass 11, count 0 2006.210.08:25:41.90#ibcon#*before return 0, iclass 11, count 0 2006.210.08:25:41.90#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:41.90#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.210.08:25:41.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.210.08:25:41.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.210.08:25:41.90$vc4f8/vb=6,3 2006.210.08:25:41.90#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.210.08:25:41.90#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.210.08:25:41.90#ibcon#ireg 11 cls_cnt 2 2006.210.08:25:41.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:41.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:41.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:41.96#ibcon#enter wrdev, iclass 13, count 2 2006.210.08:25:41.96#ibcon#first serial, iclass 13, count 2 2006.210.08:25:41.96#ibcon#enter sib2, iclass 13, count 2 2006.210.08:25:41.96#ibcon#flushed, iclass 13, count 2 2006.210.08:25:41.96#ibcon#about to write, iclass 13, count 2 2006.210.08:25:41.96#ibcon#wrote, iclass 13, count 2 2006.210.08:25:41.96#ibcon#about to read 3, iclass 13, count 2 2006.210.08:25:41.98#ibcon#read 3, iclass 13, count 2 2006.210.08:25:41.98#ibcon#about to read 4, iclass 13, count 2 2006.210.08:25:41.98#ibcon#read 4, iclass 13, count 2 2006.210.08:25:41.98#ibcon#about to read 5, iclass 13, count 2 2006.210.08:25:41.98#ibcon#read 5, iclass 13, count 2 2006.210.08:25:41.98#ibcon#about to read 6, iclass 13, count 2 2006.210.08:25:41.98#ibcon#read 6, iclass 13, count 2 2006.210.08:25:41.98#ibcon#end of sib2, iclass 13, count 2 2006.210.08:25:41.98#ibcon#*mode == 0, iclass 13, count 2 2006.210.08:25:41.98#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.210.08:25:41.98#ibcon#[27=AT06-03\r\n] 2006.210.08:25:41.98#ibcon#*before write, iclass 13, count 2 2006.210.08:25:41.98#ibcon#enter sib2, iclass 13, count 2 2006.210.08:25:41.98#ibcon#flushed, iclass 13, count 2 2006.210.08:25:41.98#ibcon#about to write, iclass 13, count 2 2006.210.08:25:41.98#ibcon#wrote, iclass 13, count 2 2006.210.08:25:41.98#ibcon#about to read 3, iclass 13, count 2 2006.210.08:25:42.01#ibcon#read 3, iclass 13, count 2 2006.210.08:25:42.01#ibcon#about to read 4, iclass 13, count 2 2006.210.08:25:42.01#ibcon#read 4, iclass 13, count 2 2006.210.08:25:42.01#ibcon#about to read 5, iclass 13, count 2 2006.210.08:25:42.01#ibcon#read 5, iclass 13, count 2 2006.210.08:25:42.01#ibcon#about to read 6, iclass 13, count 2 2006.210.08:25:42.01#ibcon#read 6, iclass 13, count 2 2006.210.08:25:42.01#ibcon#end of sib2, iclass 13, count 2 2006.210.08:25:42.01#ibcon#*after write, iclass 13, count 2 2006.210.08:25:42.01#ibcon#*before return 0, iclass 13, count 2 2006.210.08:25:42.01#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:42.01#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.210.08:25:42.01#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.210.08:25:42.01#ibcon#ireg 7 cls_cnt 0 2006.210.08:25:42.01#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:42.13#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:42.13#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:42.13#ibcon#enter wrdev, iclass 13, count 0 2006.210.08:25:42.13#ibcon#first serial, iclass 13, count 0 2006.210.08:25:42.13#ibcon#enter sib2, iclass 13, count 0 2006.210.08:25:42.13#ibcon#flushed, iclass 13, count 0 2006.210.08:25:42.13#ibcon#about to write, iclass 13, count 0 2006.210.08:25:42.13#ibcon#wrote, iclass 13, count 0 2006.210.08:25:42.13#ibcon#about to read 3, iclass 13, count 0 2006.210.08:25:42.15#ibcon#read 3, iclass 13, count 0 2006.210.08:25:42.15#ibcon#about to read 4, iclass 13, count 0 2006.210.08:25:42.15#ibcon#read 4, iclass 13, count 0 2006.210.08:25:42.15#ibcon#about to read 5, iclass 13, count 0 2006.210.08:25:42.15#ibcon#read 5, iclass 13, count 0 2006.210.08:25:42.15#ibcon#about to read 6, iclass 13, count 0 2006.210.08:25:42.15#ibcon#read 6, iclass 13, count 0 2006.210.08:25:42.15#ibcon#end of sib2, iclass 13, count 0 2006.210.08:25:42.15#ibcon#*mode == 0, iclass 13, count 0 2006.210.08:25:42.15#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.210.08:25:42.15#ibcon#[27=USB\r\n] 2006.210.08:25:42.15#ibcon#*before write, iclass 13, count 0 2006.210.08:25:42.15#ibcon#enter sib2, iclass 13, count 0 2006.210.08:25:42.15#ibcon#flushed, iclass 13, count 0 2006.210.08:25:42.15#ibcon#about to write, iclass 13, count 0 2006.210.08:25:42.15#ibcon#wrote, iclass 13, count 0 2006.210.08:25:42.15#ibcon#about to read 3, iclass 13, count 0 2006.210.08:25:42.18#ibcon#read 3, iclass 13, count 0 2006.210.08:25:42.18#ibcon#about to read 4, iclass 13, count 0 2006.210.08:25:42.18#ibcon#read 4, iclass 13, count 0 2006.210.08:25:42.18#ibcon#about to read 5, iclass 13, count 0 2006.210.08:25:42.18#ibcon#read 5, iclass 13, count 0 2006.210.08:25:42.18#ibcon#about to read 6, iclass 13, count 0 2006.210.08:25:42.18#ibcon#read 6, iclass 13, count 0 2006.210.08:25:42.18#ibcon#end of sib2, iclass 13, count 0 2006.210.08:25:42.18#ibcon#*after write, iclass 13, count 0 2006.210.08:25:42.18#ibcon#*before return 0, iclass 13, count 0 2006.210.08:25:42.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:42.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.210.08:25:42.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.210.08:25:42.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.210.08:25:42.18$vc4f8/vabw=wide 2006.210.08:25:42.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.210.08:25:42.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.210.08:25:42.18#ibcon#ireg 8 cls_cnt 0 2006.210.08:25:42.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:42.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:42.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:42.18#ibcon#enter wrdev, iclass 15, count 0 2006.210.08:25:42.18#ibcon#first serial, iclass 15, count 0 2006.210.08:25:42.18#ibcon#enter sib2, iclass 15, count 0 2006.210.08:25:42.18#ibcon#flushed, iclass 15, count 0 2006.210.08:25:42.18#ibcon#about to write, iclass 15, count 0 2006.210.08:25:42.18#ibcon#wrote, iclass 15, count 0 2006.210.08:25:42.18#ibcon#about to read 3, iclass 15, count 0 2006.210.08:25:42.20#ibcon#read 3, iclass 15, count 0 2006.210.08:25:42.20#ibcon#about to read 4, iclass 15, count 0 2006.210.08:25:42.20#ibcon#read 4, iclass 15, count 0 2006.210.08:25:42.20#ibcon#about to read 5, iclass 15, count 0 2006.210.08:25:42.20#ibcon#read 5, iclass 15, count 0 2006.210.08:25:42.20#ibcon#about to read 6, iclass 15, count 0 2006.210.08:25:42.20#ibcon#read 6, iclass 15, count 0 2006.210.08:25:42.20#ibcon#end of sib2, iclass 15, count 0 2006.210.08:25:42.20#ibcon#*mode == 0, iclass 15, count 0 2006.210.08:25:42.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.210.08:25:42.20#ibcon#[25=BW32\r\n] 2006.210.08:25:42.20#ibcon#*before write, iclass 15, count 0 2006.210.08:25:42.20#ibcon#enter sib2, iclass 15, count 0 2006.210.08:25:42.20#ibcon#flushed, iclass 15, count 0 2006.210.08:25:42.20#ibcon#about to write, iclass 15, count 0 2006.210.08:25:42.20#ibcon#wrote, iclass 15, count 0 2006.210.08:25:42.20#ibcon#about to read 3, iclass 15, count 0 2006.210.08:25:42.23#ibcon#read 3, iclass 15, count 0 2006.210.08:25:42.23#ibcon#about to read 4, iclass 15, count 0 2006.210.08:25:42.23#ibcon#read 4, iclass 15, count 0 2006.210.08:25:42.23#ibcon#about to read 5, iclass 15, count 0 2006.210.08:25:42.23#ibcon#read 5, iclass 15, count 0 2006.210.08:25:42.23#ibcon#about to read 6, iclass 15, count 0 2006.210.08:25:42.23#ibcon#read 6, iclass 15, count 0 2006.210.08:25:42.23#ibcon#end of sib2, iclass 15, count 0 2006.210.08:25:42.23#ibcon#*after write, iclass 15, count 0 2006.210.08:25:42.23#ibcon#*before return 0, iclass 15, count 0 2006.210.08:25:42.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:42.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.210.08:25:42.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.210.08:25:42.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.210.08:25:42.23$vc4f8/vbbw=wide 2006.210.08:25:42.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.210.08:25:42.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.210.08:25:42.23#ibcon#ireg 8 cls_cnt 0 2006.210.08:25:42.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:25:42.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:25:42.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:25:42.30#ibcon#enter wrdev, iclass 17, count 0 2006.210.08:25:42.30#ibcon#first serial, iclass 17, count 0 2006.210.08:25:42.30#ibcon#enter sib2, iclass 17, count 0 2006.210.08:25:42.30#ibcon#flushed, iclass 17, count 0 2006.210.08:25:42.30#ibcon#about to write, iclass 17, count 0 2006.210.08:25:42.30#ibcon#wrote, iclass 17, count 0 2006.210.08:25:42.30#ibcon#about to read 3, iclass 17, count 0 2006.210.08:25:42.32#ibcon#read 3, iclass 17, count 0 2006.210.08:25:42.32#ibcon#about to read 4, iclass 17, count 0 2006.210.08:25:42.32#ibcon#read 4, iclass 17, count 0 2006.210.08:25:42.32#ibcon#about to read 5, iclass 17, count 0 2006.210.08:25:42.32#ibcon#read 5, iclass 17, count 0 2006.210.08:25:42.32#ibcon#about to read 6, iclass 17, count 0 2006.210.08:25:42.32#ibcon#read 6, iclass 17, count 0 2006.210.08:25:42.32#ibcon#end of sib2, iclass 17, count 0 2006.210.08:25:42.32#ibcon#*mode == 0, iclass 17, count 0 2006.210.08:25:42.32#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.210.08:25:42.32#ibcon#[27=BW32\r\n] 2006.210.08:25:42.32#ibcon#*before write, iclass 17, count 0 2006.210.08:25:42.32#ibcon#enter sib2, iclass 17, count 0 2006.210.08:25:42.32#ibcon#flushed, iclass 17, count 0 2006.210.08:25:42.32#ibcon#about to write, iclass 17, count 0 2006.210.08:25:42.32#ibcon#wrote, iclass 17, count 0 2006.210.08:25:42.32#ibcon#about to read 3, iclass 17, count 0 2006.210.08:25:42.35#ibcon#read 3, iclass 17, count 0 2006.210.08:25:42.35#ibcon#about to read 4, iclass 17, count 0 2006.210.08:25:42.35#ibcon#read 4, iclass 17, count 0 2006.210.08:25:42.35#ibcon#about to read 5, iclass 17, count 0 2006.210.08:25:42.35#ibcon#read 5, iclass 17, count 0 2006.210.08:25:42.35#ibcon#about to read 6, iclass 17, count 0 2006.210.08:25:42.35#ibcon#read 6, iclass 17, count 0 2006.210.08:25:42.35#ibcon#end of sib2, iclass 17, count 0 2006.210.08:25:42.35#ibcon#*after write, iclass 17, count 0 2006.210.08:25:42.35#ibcon#*before return 0, iclass 17, count 0 2006.210.08:25:42.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:25:42.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.210.08:25:42.35#ibcon#about to clear, iclass 17 cls_cnt 0 2006.210.08:25:42.35#ibcon#cleared, iclass 17 cls_cnt 0 2006.210.08:25:42.35$4f8m12a/ifd4f 2006.210.08:25:42.35$ifd4f/lo= 2006.210.08:25:42.35$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.210.08:25:42.35$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.210.08:25:42.35$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.210.08:25:42.35$ifd4f/patch= 2006.210.08:25:42.35$ifd4f/patch=lo1,a1,a2,a3,a4 2006.210.08:25:42.35$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.210.08:25:42.35$ifd4f/patch=lo3,a5,a6,a7,a8 2006.210.08:25:42.35$4f8m12a/"form=m,16.000,1:2 2006.210.08:25:42.35$4f8m12a/"tpicd 2006.210.08:25:42.35$4f8m12a/echo=off 2006.210.08:25:42.35$4f8m12a/xlog=off 2006.210.08:25:42.35:!2006.210.08:26:10 2006.210.08:25:54.14#trakl#Source acquired 2006.210.08:25:55.14#flagr#flagr/antenna,acquired 2006.210.08:26:10.00:preob 2006.210.08:26:11.14/onsource/TRACKING 2006.210.08:26:11.14:!2006.210.08:26:20 2006.210.08:26:20.00:data_valid=on 2006.210.08:26:20.00:midob 2006.210.08:26:20.14/onsource/TRACKING 2006.210.08:26:20.14/wx/29.49,1006.6,84 2006.210.08:26:20.31/cable/+6.3946E-03 2006.210.08:26:21.40/va/01,08,usb,yes,28,30 2006.210.08:26:21.40/va/02,07,usb,yes,29,30 2006.210.08:26:21.40/va/03,06,usb,yes,30,30 2006.210.08:26:21.40/va/04,07,usb,yes,29,32 2006.210.08:26:21.40/va/05,07,usb,yes,31,33 2006.210.08:26:21.40/va/06,06,usb,yes,30,30 2006.210.08:26:21.40/va/07,06,usb,yes,31,31 2006.210.08:26:21.40/va/08,07,usb,yes,29,29 2006.210.08:26:21.63/valo/01,532.99,yes,locked 2006.210.08:26:21.63/valo/02,572.99,yes,locked 2006.210.08:26:21.63/valo/03,672.99,yes,locked 2006.210.08:26:21.63/valo/04,832.99,yes,locked 2006.210.08:26:21.63/valo/05,652.99,yes,locked 2006.210.08:26:21.63/valo/06,772.99,yes,locked 2006.210.08:26:21.63/valo/07,832.99,yes,locked 2006.210.08:26:21.63/valo/08,852.99,yes,locked 2006.210.08:26:22.72/vb/01,04,usb,yes,29,27 2006.210.08:26:22.72/vb/02,04,usb,yes,34,32 2006.210.08:26:22.72/vb/03,03,usb,yes,34,42 2006.210.08:26:22.72/vb/04,03,usb,yes,34,34 2006.210.08:26:22.72/vb/05,03,usb,yes,32,37 2006.210.08:26:22.72/vb/06,03,usb,yes,33,36 2006.210.08:26:22.72/vb/07,04,usb,yes,29,29 2006.210.08:26:22.72/vb/08,03,usb,yes,33,37 2006.210.08:26:22.96/vblo/01,632.99,yes,locked 2006.210.08:26:22.96/vblo/02,640.99,yes,locked 2006.210.08:26:22.96/vblo/03,656.99,yes,locked 2006.210.08:26:22.96/vblo/04,712.99,yes,locked 2006.210.08:26:22.96/vblo/05,744.99,yes,locked 2006.210.08:26:22.96/vblo/06,752.99,yes,locked 2006.210.08:26:22.96/vblo/07,734.99,yes,locked 2006.210.08:26:22.96/vblo/08,744.99,yes,locked 2006.210.08:26:23.11/vabw/8 2006.210.08:26:23.26/vbbw/8 2006.210.08:26:23.35/xfe/off,on,13.2 2006.210.08:26:23.72/ifatt/23,28,28,28 2006.210.08:26:24.07/fmout-gps/S +4.56E-07 2006.210.08:26:24.11:!2006.210.08:27:20 2006.210.08:27:20.00:data_valid=off 2006.210.08:27:20.00:postob 2006.210.08:27:20.21/cable/+6.3945E-03 2006.210.08:27:20.21/wx/29.44,1006.6,84 2006.210.08:27:21.08/fmout-gps/S +4.55E-07 2006.210.08:27:21.08:checkk5last 2006.210.08:27:21.08&checkk5last/chk_obsdata=1 2006.210.08:27:21.08&checkk5last/chk_obsdata=2 2006.210.08:27:21.08&checkk5last/chk_obsdata=3 2006.210.08:27:21.08&checkk5last/chk_obsdata=4 2006.210.08:27:21.08&checkk5last/k5log=1 2006.210.08:27:21.08&checkk5last/k5log=2 2006.210.08:27:21.08&checkk5last/k5log=3 2006.210.08:27:21.08&checkk5last/k5log=4 2006.210.08:27:21.08&checkk5last/obsinfo 2006.210.08:27:21.43/chk_obsdata//k5ts1/T2100826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:27:21.76/chk_obsdata//k5ts2/T2100826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:27:22.10/chk_obsdata//k5ts3/T2100826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:27:22.44/chk_obsdata//k5ts4/T2100826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.210.08:27:23.09/k5log//k5ts1_log_newline 2006.210.08:27:23.75/k5log//k5ts2_log_newline 2006.210.08:27:24.41/k5log//k5ts3_log_newline 2006.210.08:27:25.06/k5log//k5ts4_log_newline 2006.210.08:27:25.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.210.08:27:25.09:"sched_end 2006.210.08:27:25.09:source=idle 2006.210.08:27:26.14:stow 2006.210.08:27:26.14&stow/source=idle 2006.210.08:27:26.14&stow/"this is stow command. 2006.210.08:27:26.14&stow/antenna=m3 2006.210.08:27:26.14#flagr#flagr/antenna,new-source 2006.210.08:27:29.01:!+10m 2006.210.08:37:29.02:standby 2006.210.08:37:29.02&standby/"this is standby command. 2006.210.08:37:29.02&standby/antenna=m0 2006.210.08:37:30.01:checkk5hdd 2006.210.08:37:30.01&checkk5hdd/chk_hdd=1 2006.210.08:37:30.01&checkk5hdd/chk_hdd=2 2006.210.08:37:30.01&checkk5hdd/chk_hdd=3 2006.210.08:37:30.01&checkk5hdd/chk_hdd=4 2006.210.08:37:32.78/chk_hdd//k5ts1/GSI00275:T210073000a.dat~T210082620a.dat[13169393664Byte] 2006.210.08:37:35.56/chk_hdd//k5ts2/GSI00163:T210073000b.dat~T210082620b.dat[13169393664Byte] 2006.210.08:37:38.34/chk_hdd//k5ts3/GSI00278:T210073000c.dat~T210082620c.dat[13169393664Byte] 2006.210.08:37:41.10/chk_hdd//k5ts4/GSI00220:T210073000d.dat~T210082620d.dat[13169393664Byte] 2006.210.08:37:41.10:sy=cp /usr2/log/k06210ts.log /usr2/log_backup/ 2006.210.08:37:41.15:log=u06211ts